target/linux/ipq806x/patches-4.0/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch

   1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
   2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
   3 @@ -24,6 +24,11 @@
   4                         next-level-cache = <&L2>;
   5                         qcom,acc = <&acc0>;
   6                         qcom,saw = <&saw0>;
   7 +                       clocks = <&kraitcc 0>;
   8 +                       clock-names = "cpu";
   9 +                       clock-latency = <100000>;
  10 +                       core-supply = <&smb208_s2a>;
  11 +                       voltage-tolerance = <5>;
  12                 };
  13
  14                 cpu@1 {
  15 @@ -34,11 +39,24 @@
  16                         next-level-cache = <&L2>;
  17                         qcom,acc = <&acc1>;
  18                         qcom,saw = <&saw1>;
  19 +                       clocks = <&kraitcc 1>;
  20 +                       clock-names = "cpu";
  21 +                       clock-latency = <100000>;
  22 +                       core-supply = <&smb208_s2b>;
  23                 };
  24
  25                 L2: l2-cache {
  26                         compatible = "cache";
  27                         cache-level = <2>;
  28 +                       clocks = <&kraitcc 4>;
  29 +                       clock-names = "cache";
  30 +                       cache-points-kHz = <
  31 +                               /* kHz    uV    CPU kHz */
  32 +                               1200000 1150000 1200000
  33 +                               1000000 1100000  600000
  34 +                                384000 1100000  384000
  35 +                       >;
  36 +                       vdd_dig-supply = <&smb208_s1a>;
  37                 };
  38         };
  39
  40 @@ -71,6 +89,46 @@
  41                 };
  42         };
  43
  44 +       kraitcc: clock-controller {
  45 +               compatible = "qcom,krait-cc-v1";
  46 +               #clock-cells = <1>;
  47 +       };
  48 +
  49 +       qcom,pvs {
  50 +               qcom,pvs-format-a;
  51 +               qcom,speed0-pvs0-bin-v0 =
  52 +                       < 1400000000 1250000 >,
  53 +                       < 1200000000 1200000 >,
  54 +                       < 1000000000 1150000 >,
  55 +                        < 800000000 1100000 >,
  56 +                        < 600000000 1050000 >,
  57 +                        < 384000000 1000000 >;
  58 +
  59 +               qcom,speed0-pvs1-bin-v0 =
  60 +                       < 1400000000 1175000 >,
  61 +                       < 1200000000 1125000 >,
  62 +                       < 1000000000 1075000 >,
  63 +                        < 800000000 1025000 >,
  64 +                        < 600000000  975000 >,
  65 +                        < 384000000  925000 >;
  66 +
  67 +               qcom,speed0-pvs2-bin-v0 =
  68 +                       < 1400000000 1125000 >,
  69 +                       < 1200000000 1075000 >,
  70 +                       < 1000000000 1025000 >,
  71 +                        < 800000000  995000 >,
  72 +                        < 600000000  925000 >,
  73 +                        < 384000000  875000 >;
  74 +
  75 +               qcom,speed0-pvs3-bin-v0 =
  76 +                       < 1400000000 1050000 >,
  77 +                       < 1200000000 1000000 >,
  78 +                       < 1000000000  950000 >,
  79 +                        < 800000000  900000 >,
  80 +                        < 600000000  850000 >,
  81 +                        < 384000000  800000 >;
  82 +       };
  83 +
  84         soc: soc {
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87 @@ -171,11 +229,13 @@
  88                 acc0: clock-controller@2088000 {
  89                         compatible = "qcom,kpss-acc-v1";
  90                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
  91 +                       clock-output-names = "acpu0_aux";
  92                 };
  93
  94                 acc1: clock-controller@2098000 {
  95                         compatible = "qcom,kpss-acc-v1";
  96                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
  97 +                       clock-output-names = "acpu1_aux";
  98                 };
  99
 100                 l2cc: clock-controller@2011000 {