imx6: Add 4.3 support
[openwrt.git] / target / linux / imx6 / patches-4.3 / 203-net-igb-add-phy-read-write-functions-that-accept-phy.patch
1 From 16df7dc5901c1cb2a40f6adbd0d9423768ed8210 Mon Sep 17 00:00:00 2001
2 From: Tim Harvey <tharvey@gateworks.com>
3 Date: Thu, 15 May 2014 00:29:18 -0700
4 Subject: [PATCH] net: igb: add phy read/write functions that accept phy addr
5
6 Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address.
7 The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers
8 to this function.
9
10 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
11 ---
12  drivers/net/ethernet/intel/igb/e1000_82575.c |  4 +-
13  drivers/net/ethernet/intel/igb/e1000_phy.c   | 74 +++++++++++++++++++---------
14  drivers/net/ethernet/intel/igb/e1000_phy.h   |  6 ++-
15  3 files changed, 58 insertions(+), 26 deletions(-)
16
17 Index: linux-4.3/drivers/net/ethernet/intel/igb/e1000_82575.c
18 ===================================================================
19 --- linux-4.3.orig/drivers/net/ethernet/intel/igb/e1000_82575.c 2015-11-01 16:05:25.000000000 -0800
20 +++ linux-4.3/drivers/net/ethernet/intel/igb/e1000_82575.c      2015-12-18 10:43:28.000000000 -0800
21 @@ -2153,7 +2153,7 @@
22         if (ret_val)
23                 goto out;
24  
25 -       ret_val = igb_read_phy_reg_mdic(hw, offset, data);
26 +       ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data);
27  
28         hw->phy.ops.release(hw);
29  
30 @@ -2178,7 +2178,7 @@
31         if (ret_val)
32                 goto out;
33  
34 -       ret_val = igb_write_phy_reg_mdic(hw, offset, data);
35 +       ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data);
36  
37         hw->phy.ops.release(hw);
38  
39 Index: linux-4.3/drivers/net/ethernet/intel/igb/e1000_phy.c
40 ===================================================================
41 --- linux-4.3.orig/drivers/net/ethernet/intel/igb/e1000_phy.c   2015-12-18 10:39:44.931158318 -0800
42 +++ linux-4.3/drivers/net/ethernet/intel/igb/e1000_phy.c        2015-12-18 10:39:44.939158318 -0800
43 @@ -126,9 +126,8 @@
44   *  Reads the MDI control regsiter in the PHY at offset and stores the
45   *  information read to data.
46   **/
47 -s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
48 +s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
49  {
50 -       struct e1000_phy_info *phy = &hw->phy;
51         u32 i, mdicnfg, mdic = 0;
52         s32 ret_val = 0;
53  
54 @@ -147,14 +146,14 @@
55         case e1000_i211:
56                 mdicnfg = rd32(E1000_MDICNFG);
57                 mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
58 -               mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
59 +               mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
60                 wr32(E1000_MDICNFG, mdicnfg);
61                 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
62                         (E1000_MDIC_OP_READ));
63                 break;
64         default:
65                 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
66 -                       (phy->addr << E1000_MDIC_PHY_SHIFT) |
67 +                       (addr << E1000_MDIC_PHY_SHIFT) |
68                         (E1000_MDIC_OP_READ));
69                 break;
70         }
71 @@ -208,9 +207,8 @@
72   *
73   *  Writes data to MDI control register in the PHY at offset.
74   **/
75 -s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
76 +s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
77  {
78 -       struct e1000_phy_info *phy = &hw->phy;
79         u32 i, mdicnfg, mdic = 0;
80         s32 ret_val = 0;
81  
82 @@ -229,7 +227,7 @@
83                 case e1000_i211:
84                         mdicnfg = rd32(E1000_MDICNFG);
85                         mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
86 -                       mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
87 +                       mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
88                         wr32(E1000_MDICNFG, mdicnfg);
89                         mdic = (((u32)data) |
90                                 (offset << E1000_MDIC_REG_SHIFT) |
91 @@ -238,7 +236,7 @@
92                 default:
93                         mdic = (((u32)data) |
94                                 (offset << E1000_MDIC_REG_SHIFT) |
95 -                               (phy->addr << E1000_MDIC_PHY_SHIFT) |
96 +                               (addr << E1000_MDIC_PHY_SHIFT) |
97                                 (E1000_MDIC_OP_WRITE));
98                         break;
99         }
100 @@ -458,7 +456,7 @@
101                 goto out;
102  
103         if (offset > MAX_PHY_MULTI_PAGE_REG) {
104 -               ret_val = igb_write_phy_reg_mdic(hw,
105 +               ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
106                                                  IGP01E1000_PHY_PAGE_SELECT,
107                                                  (u16)offset);
108                 if (ret_val) {
109 @@ -467,8 +465,8 @@
110                 }
111         }
112  
113 -       ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
114 -                                       data);
115 +       ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr,
116 +                                       MAX_PHY_REG_ADDRESS & offset, data);
117  
118         hw->phy.ops.release(hw);
119  
120 @@ -497,7 +495,7 @@
121                 goto out;
122  
123         if (offset > MAX_PHY_MULTI_PAGE_REG) {
124 -               ret_val = igb_write_phy_reg_mdic(hw,
125 +               ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
126                                                  IGP01E1000_PHY_PAGE_SELECT,
127                                                  (u16)offset);
128                 if (ret_val) {
129 @@ -506,8 +504,8 @@
130                 }
131         }
132  
133 -       ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
134 -                                        data);
135 +       ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
136 +                                        MAX_PHY_REG_ADDRESS & offset, data);
137  
138         hw->phy.ops.release(hw);
139  
140 @@ -2547,8 +2545,9 @@
141  }
142  
143  /**
144 - *  igb_write_phy_reg_gs40g - Write GS40G PHY register
145 + *  igb_write_reg_gs40g - Write GS40G PHY register
146   *  @hw: pointer to the HW structure
147 + *  @addr: phy address to write to
148   *  @offset: lower half is register offset to write to
149   *     upper half is page to use.
150   *  @data: data to write at register offset
151 @@ -2556,7 +2555,7 @@
152   *  Acquires semaphore, if necessary, then writes the data to PHY register
153   *  at the offset.  Release any acquired semaphores before exiting.
154   **/
155 -s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
156 +s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
157  {
158         s32 ret_val;
159         u16 page = offset >> GS40G_PAGE_SHIFT;
160 @@ -2566,10 +2565,10 @@
161         if (ret_val)
162                 return ret_val;
163  
164 -       ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
165 +       ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
166         if (ret_val)
167                 goto release;
168 -       ret_val = igb_write_phy_reg_mdic(hw, offset, data);
169 +       ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data);
170  
171  release:
172         hw->phy.ops.release(hw);
173 @@ -2577,8 +2576,24 @@
174  }
175  
176  /**
177 - *  igb_read_phy_reg_gs40g - Read GS40G  PHY register
178 + *  igb_write_phy_reg_gs40g - Write GS40G PHY register
179 + *  @hw: pointer to the HW structure
180 + *  @offset: lower half is register offset to write to
181 + *     upper half is page to use.
182 + *  @data: data to write at register offset
183 + *
184 + *  Acquires semaphore, if necessary, then writes the data to PHY register
185 + *  at the offset.  Release any acquired semaphores before exiting.
186 + **/
187 +s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
188 +{
189 +       return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data);
190 +}
191 +
192 +/**
193 + *  igb_read_reg_gs40g - Read GS40G  PHY register
194   *  @hw: pointer to the HW structure
195 + *  @addr: phy address to read from
196   *  @offset: lower half is register offset to read to
197   *     upper half is page to use.
198   *  @data: data to read at register offset
199 @@ -2586,7 +2601,7 @@
200   *  Acquires semaphore, if necessary, then reads the data in the PHY register
201   *  at the offset.  Release any acquired semaphores before exiting.
202   **/
203 -s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
204 +s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
205  {
206         s32 ret_val;
207         u16 page = offset >> GS40G_PAGE_SHIFT;
208 @@ -2596,10 +2611,10 @@
209         if (ret_val)
210                 return ret_val;
211  
212 -       ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
213 +       ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
214         if (ret_val)
215                 goto release;
216 -       ret_val = igb_read_phy_reg_mdic(hw, offset, data);
217 +       ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data);
218  
219  release:
220         hw->phy.ops.release(hw);
221 @@ -2607,6 +2622,21 @@
222  }
223  
224  /**
225 + *  igb_read_phy_reg_gs40g - Read GS40G  PHY register
226 + *  @hw: pointer to the HW structure
227 + *  @offset: lower half is register offset to read to
228 + *     upper half is page to use.
229 + *  @data: data to read at register offset
230 + *
231 + *  Acquires semaphore, if necessary, then reads the data in the PHY register
232 + *  at the offset.  Release any acquired semaphores before exiting.
233 + **/
234 +s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
235 +{
236 +       return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data);
237 +}
238 +
239 +/**
240   *  igb_set_master_slave_mode - Setup PHY for Master/slave mode
241   *  @hw: pointer to the HW structure
242   *
243 Index: linux-4.3/drivers/net/ethernet/intel/igb/e1000_phy.h
244 ===================================================================
245 --- linux-4.3.orig/drivers/net/ethernet/intel/igb/e1000_phy.h   2015-11-01 16:05:25.000000000 -0800
246 +++ linux-4.3/drivers/net/ethernet/intel/igb/e1000_phy.h        2015-12-18 10:39:44.939158318 -0800
247 @@ -62,8 +62,8 @@
248  void igb_power_down_phy_copper(struct e1000_hw *hw);
249  s32  igb_phy_init_script_igp3(struct e1000_hw *hw);
250  s32  igb_initialize_M88E1512_phy(struct e1000_hw *hw);
251 -s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
252 -s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
253 +s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
254 +s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
255  s32  igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
256  s32  igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
257  s32  igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
258 @@ -73,6 +73,8 @@
259  s32  igb_get_cable_length_82580(struct e1000_hw *hw);
260  s32  igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
261  s32  igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
262 +s32  igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
263 +s32  igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
264  s32  igb_check_polarity_m88(struct e1000_hw *hw);
265  
266  /* IGP01E1000 Specific Registers */