target/linux/imx6/patches-4.3/202-net-igb-add-i210-i211-support-for-phy-read-write.patch

   1 Author: Tim Harvey <tharvey@gateworks.com>
   2 Date:   Thu May 15 00:12:26 2014 -0700
   3
   4     net: igb: add i210/i211 support for phy read/write
   5
   6     The i210/i211 uses the MDICNFG register for the phy address instead of the
   7     MDIC register.
   8
   9     Signed-off-by: Tim Harvey <tharvey@gateworks.com>
  10
  11 Index: linux-4.3/drivers/net/ethernet/intel/igb/e1000_phy.c
  12 ===================================================================
  13 --- linux-4.3.orig/drivers/net/ethernet/intel/igb/e1000_phy.c   2015-11-01 16:05:25.000000000 -0800
  14 +++ linux-4.3/drivers/net/ethernet/intel/igb/e1000_phy.c        2015-12-18 10:43:28.000000000 -0800
  15 @@ -129,7 +129,7 @@
  16  s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
  17  {
  18         struct e1000_phy_info *phy = &hw->phy;
  19 -       u32 i, mdic = 0;
  20 +       u32 i, mdicnfg, mdic = 0;
  21         s32 ret_val = 0;
  22
  23         if (offset > MAX_PHY_REG_ADDRESS) {
  24 @@ -142,11 +142,25 @@
  25          * Control register.  The MAC will take care of interfacing with the
  26          * PHY to retrieve the desired data.
  27          */
  28 -       mdic = ((offset << E1000_MDIC_REG_SHIFT) |
  29 -               (phy->addr << E1000_MDIC_PHY_SHIFT) |
  30 -               (E1000_MDIC_OP_READ));
  31 +       switch (hw->mac.type) {
  32 +       case e1000_i210:
  33 +       case e1000_i211:
  34 +               mdicnfg = rd32(E1000_MDICNFG);
  35 +               mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
  36 +               mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
  37 +               wr32(E1000_MDICNFG, mdicnfg);
  38 +               mdic = ((offset << E1000_MDIC_REG_SHIFT) |
  39 +                       (E1000_MDIC_OP_READ));
  40 +               break;
  41 +       default:
  42 +               mdic = ((offset << E1000_MDIC_REG_SHIFT) |
  43 +                       (phy->addr << E1000_MDIC_PHY_SHIFT) |
  44 +                       (E1000_MDIC_OP_READ));
  45 +               break;
  46 +       }
  47
  48         wr32(E1000_MDIC, mdic);
  49 +       wrfl();
  50
  51         /* Poll the ready bit to see if the MDI read completed
  52          * Increasing the time out as testing showed failures with
  53 @@ -171,6 +185,18 @@
  54         *data = (u16) mdic;
  55
  56  out:
  57 +       switch (hw->mac.type) {
  58 +               /* restore MDICNFG to have phy's addr */
  59 +               case e1000_i210:
  60 +               case e1000_i211:
  61 +                       mdicnfg = rd32(E1000_MDICNFG);
  62 +                       mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
  63 +                       mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
  64 +                       wr32(E1000_MDICNFG, mdicnfg);
  65 +                       break;
  66 +               default:
  67 +                       break;
  68 +       }
  69         return ret_val;
  70  }
  71
  72 @@ -185,7 +211,7 @@
  73  s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
  74  {
  75         struct e1000_phy_info *phy = &hw->phy;
  76 -       u32 i, mdic = 0;
  77 +       u32 i, mdicnfg, mdic = 0;
  78         s32 ret_val = 0;
  79
  80         if (offset > MAX_PHY_REG_ADDRESS) {
  81 @@ -198,12 +224,27 @@
  82          * Control register.  The MAC will take care of interfacing with the
  83          * PHY to retrieve the desired data.
  84          */
  85 -       mdic = (((u32)data) |
  86 -               (offset << E1000_MDIC_REG_SHIFT) |
  87 -               (phy->addr << E1000_MDIC_PHY_SHIFT) |
  88 -               (E1000_MDIC_OP_WRITE));
  89 +       switch (hw->mac.type) {
  90 +               case e1000_i210:
  91 +               case e1000_i211:
  92 +                       mdicnfg = rd32(E1000_MDICNFG);
  93 +                       mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
  94 +                       mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
  95 +                       wr32(E1000_MDICNFG, mdicnfg);
  96 +                       mdic = (((u32)data) |
  97 +                               (offset << E1000_MDIC_REG_SHIFT) |
  98 +                               (E1000_MDIC_OP_WRITE));
  99 +                       break;
 100 +               default:
 101 +                       mdic = (((u32)data) |
 102 +                               (offset << E1000_MDIC_REG_SHIFT) |
 103 +                               (phy->addr << E1000_MDIC_PHY_SHIFT) |
 104 +                               (E1000_MDIC_OP_WRITE));
 105 +                       break;
 106 +       }
 107
 108         wr32(E1000_MDIC, mdic);
 109 +       wrfl();
 110
 111         /* Poll the ready bit to see if the MDI read completed
 112          * Increasing the time out as testing showed failures with
 113 @@ -227,6 +268,18 @@
 114         }
 115
 116  out:
 117 +       switch (hw->mac.type) {
 118 +               /* restore MDICNFG to have phy's addr */
 119 +               case e1000_i210:
 120 +               case e1000_i211:
 121 +                       mdicnfg = rd32(E1000_MDICNFG);
 122 +                       mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
 123 +                       mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
 124 +                       wr32(E1000_MDICNFG, mdicnfg);
 125 +                       break;
 126 +               default:
 127 +                       break;
 128 +       }
 129         return ret_val;
 130  }
 131