7869b1cf531726627810a022cbd6129f8905cde7
[openwrt.git] / target / linux / imx6 / patches-3.18 / 203-net-igb-add-phy-read-write-functions-that-accept-phy.patch
1 From 16df7dc5901c1cb2a40f6adbd0d9423768ed8210 Mon Sep 17 00:00:00 2001
2 From: Tim Harvey <tharvey@gateworks.com>
3 Date: Thu, 15 May 2014 00:29:18 -0700
4 Subject: [PATCH] net: igb: add phy read/write functions that accept phy addr
5
6 Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address.
7 The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers
8 to this function.
9
10 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
11 ---
12  drivers/net/ethernet/intel/igb/e1000_82575.c |  4 +-
13  drivers/net/ethernet/intel/igb/e1000_phy.c   | 74 +++++++++++++++++++---------
14  drivers/net/ethernet/intel/igb/e1000_phy.h   |  6 ++-
15  3 files changed, 58 insertions(+), 26 deletions(-)
16
17 --- a/drivers/net/ethernet/intel/igb/e1000_82575.c
18 +++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
19 @@ -2129,7 +2129,7 @@ static s32 igb_read_phy_reg_82580(struct
20         if (ret_val)
21                 goto out;
22  
23 -       ret_val = igb_read_phy_reg_mdic(hw, offset, data);
24 +       ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data);
25  
26         hw->phy.ops.release(hw);
27  
28 @@ -2154,7 +2154,7 @@ static s32 igb_write_phy_reg_82580(struc
29         if (ret_val)
30                 goto out;
31  
32 -       ret_val = igb_write_phy_reg_mdic(hw, offset, data);
33 +       ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data);
34  
35         hw->phy.ops.release(hw);
36  
37 --- a/drivers/net/ethernet/intel/igb/e1000_phy.c
38 +++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
39 @@ -132,9 +132,8 @@ out:
40   *  Reads the MDI control regsiter in the PHY at offset and stores the
41   *  information read to data.
42   **/
43 -s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
44 +s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
45  {
46 -       struct e1000_phy_info *phy = &hw->phy;
47         u32 i, mdicnfg, mdic = 0;
48         s32 ret_val = 0;
49  
50 @@ -153,14 +152,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
51         case e1000_i211:
52                 mdicnfg = rd32(E1000_MDICNFG);
53                 mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
54 -               mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
55 +               mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
56                 wr32(E1000_MDICNFG, mdicnfg);
57                 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
58                         (E1000_MDIC_OP_READ));
59                 break;
60         default:
61                 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
62 -                       (phy->addr << E1000_MDIC_PHY_SHIFT) |
63 +                       (addr << E1000_MDIC_PHY_SHIFT) |
64                         (E1000_MDIC_OP_READ));
65                 break;
66         }
67 @@ -214,9 +213,8 @@ out:
68   *
69   *  Writes data to MDI control register in the PHY at offset.
70   **/
71 -s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
72 +s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
73  {
74 -       struct e1000_phy_info *phy = &hw->phy;
75         u32 i, mdicnfg, mdic = 0;
76         s32 ret_val = 0;
77  
78 @@ -235,7 +233,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
79                 case e1000_i211:
80                         mdicnfg = rd32(E1000_MDICNFG);
81                         mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
82 -                       mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
83 +                       mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
84                         wr32(E1000_MDICNFG, mdicnfg);
85                         mdic = (((u32)data) |
86                                 (offset << E1000_MDIC_REG_SHIFT) |
87 @@ -244,7 +242,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
88                 default:
89                         mdic = (((u32)data) |
90                                 (offset << E1000_MDIC_REG_SHIFT) |
91 -                               (phy->addr << E1000_MDIC_PHY_SHIFT) |
92 +                               (addr << E1000_MDIC_PHY_SHIFT) |
93                                 (E1000_MDIC_OP_WRITE));
94                         break;
95         }
96 @@ -464,7 +462,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
97                 goto out;
98  
99         if (offset > MAX_PHY_MULTI_PAGE_REG) {
100 -               ret_val = igb_write_phy_reg_mdic(hw,
101 +               ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
102                                                  IGP01E1000_PHY_PAGE_SELECT,
103                                                  (u16)offset);
104                 if (ret_val) {
105 @@ -473,8 +471,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
106                 }
107         }
108  
109 -       ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
110 -                                       data);
111 +       ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr,
112 +                                       MAX_PHY_REG_ADDRESS & offset, data);
113  
114         hw->phy.ops.release(hw);
115  
116 @@ -503,7 +501,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h
117                 goto out;
118  
119         if (offset > MAX_PHY_MULTI_PAGE_REG) {
120 -               ret_val = igb_write_phy_reg_mdic(hw,
121 +               ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
122                                                  IGP01E1000_PHY_PAGE_SELECT,
123                                                  (u16)offset);
124                 if (ret_val) {
125 @@ -512,8 +510,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h
126                 }
127         }
128  
129 -       ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
130 -                                        data);
131 +       ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
132 +                                        MAX_PHY_REG_ADDRESS & offset, data);
133  
134         hw->phy.ops.release(hw);
135  
136 @@ -2464,8 +2462,9 @@ out:
137  }
138  
139  /**
140 - *  igb_write_phy_reg_gs40g - Write GS40G PHY register
141 + *  igb_write_reg_gs40g - Write GS40G PHY register
142   *  @hw: pointer to the HW structure
143 + *  @addr: phy address to write to
144   *  @offset: lower half is register offset to write to
145   *     upper half is page to use.
146   *  @data: data to write at register offset
147 @@ -2473,7 +2472,7 @@ out:
148   *  Acquires semaphore, if necessary, then writes the data to PHY register
149   *  at the offset.  Release any acquired semaphores before exiting.
150   **/
151 -s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
152 +s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
153  {
154         s32 ret_val;
155         u16 page = offset >> GS40G_PAGE_SHIFT;
156 @@ -2483,10 +2482,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000
157         if (ret_val)
158                 return ret_val;
159  
160 -       ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
161 +       ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
162         if (ret_val)
163                 goto release;
164 -       ret_val = igb_write_phy_reg_mdic(hw, offset, data);
165 +       ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data);
166  
167  release:
168         hw->phy.ops.release(hw);
169 @@ -2494,8 +2493,24 @@ release:
170  }
171  
172  /**
173 - *  igb_read_phy_reg_gs40g - Read GS40G  PHY register
174 + *  igb_write_phy_reg_gs40g - Write GS40G PHY register
175 + *  @hw: pointer to the HW structure
176 + *  @offset: lower half is register offset to write to
177 + *     upper half is page to use.
178 + *  @data: data to write at register offset
179 + *
180 + *  Acquires semaphore, if necessary, then writes the data to PHY register
181 + *  at the offset.  Release any acquired semaphores before exiting.
182 + **/
183 +s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
184 +{
185 +       return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data);
186 +}
187 +
188 +/**
189 + *  igb_read_reg_gs40g - Read GS40G  PHY register
190   *  @hw: pointer to the HW structure
191 + *  @addr: phy address to read from
192   *  @offset: lower half is register offset to read to
193   *     upper half is page to use.
194   *  @data: data to read at register offset
195 @@ -2503,7 +2518,7 @@ release:
196   *  Acquires semaphore, if necessary, then reads the data in the PHY register
197   *  at the offset.  Release any acquired semaphores before exiting.
198   **/
199 -s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
200 +s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
201  {
202         s32 ret_val;
203         u16 page = offset >> GS40G_PAGE_SHIFT;
204 @@ -2513,10 +2528,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_
205         if (ret_val)
206                 return ret_val;
207  
208 -       ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
209 +       ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
210         if (ret_val)
211                 goto release;
212 -       ret_val = igb_read_phy_reg_mdic(hw, offset, data);
213 +       ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data);
214  
215  release:
216         hw->phy.ops.release(hw);
217 @@ -2524,6 +2539,21 @@ release:
218  }
219  
220  /**
221 + *  igb_read_phy_reg_gs40g - Read GS40G  PHY register
222 + *  @hw: pointer to the HW structure
223 + *  @offset: lower half is register offset to read to
224 + *     upper half is page to use.
225 + *  @data: data to read at register offset
226 + *
227 + *  Acquires semaphore, if necessary, then reads the data in the PHY register
228 + *  at the offset.  Release any acquired semaphores before exiting.
229 + **/
230 +s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
231 +{
232 +       return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data);
233 +}
234 +
235 +/**
236   *  igb_set_master_slave_mode - Setup PHY for Master/slave mode
237   *  @hw: pointer to the HW structure
238   *
239 --- a/drivers/net/ethernet/intel/igb/e1000_phy.h
240 +++ b/drivers/net/ethernet/intel/igb/e1000_phy.h
241 @@ -61,8 +61,8 @@ s32  igb_phy_has_link(struct e1000_hw *h
242  void igb_power_up_phy_copper(struct e1000_hw *hw);
243  void igb_power_down_phy_copper(struct e1000_hw *hw);
244  s32  igb_phy_init_script_igp3(struct e1000_hw *hw);
245 -s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
246 -s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
247 +s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
248 +s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
249  s32  igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
250  s32  igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
251  s32  igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
252 @@ -72,6 +72,8 @@ s32  igb_phy_force_speed_duplex_82580(st
253  s32  igb_get_cable_length_82580(struct e1000_hw *hw);
254  s32  igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
255  s32  igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
256 +s32  igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
257 +s32  igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
258  s32  igb_check_polarity_m88(struct e1000_hw *hw);
259  
260  /* IGP01E1000 Specific Registers */