target/linux/generic/files/drivers/net/phy/rtl8366rb.c

   1 /*
   2  * Platform driver for the Realtek RTL8366RB ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published
  10  * by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/device.h>
  17 #include <linux/of.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/delay.h>
  20 #include <linux/skbuff.h>
  21 #include <linux/rtl8366.h>
  22
  23 #include "rtl8366_smi.h"
  24
  25 #define RTL8366RB_DRIVER_DESC   "Realtek RTL8366RB ethernet switch driver"
  26 #define RTL8366RB_DRIVER_VER    "0.2.3"
  27
  28 #define RTL8366RB_PHY_NO_MAX    4
  29 #define RTL8366RB_PHY_PAGE_MAX  7
  30 #define RTL8366RB_PHY_ADDR_MAX  31
  31
  32 /* Switch Global Configuration register */
  33 #define RTL8366RB_SGCR                          0x0000
  34 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL         BIT(0)
  35 #define RTL8366RB_SGCR_MAX_LENGTH(_x)           (_x << 4)
  36 #define RTL8366RB_SGCR_MAX_LENGTH_MASK          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  37 #define RTL8366RB_SGCR_MAX_LENGTH_1522          RTL8366RB_SGCR_MAX_LENGTH(0x0)
  38 #define RTL8366RB_SGCR_MAX_LENGTH_1536          RTL8366RB_SGCR_MAX_LENGTH(0x1)
  39 #define RTL8366RB_SGCR_MAX_LENGTH_1552          RTL8366RB_SGCR_MAX_LENGTH(0x2)
  40 #define RTL8366RB_SGCR_MAX_LENGTH_9216          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  41 #define RTL8366RB_SGCR_EN_VLAN                  BIT(13)
  42 #define RTL8366RB_SGCR_EN_VLAN_4KTB             BIT(14)
  43
  44 /* Port Enable Control register */
  45 #define RTL8366RB_PECR                          0x0001
  46
  47 /* Switch Security Control registers */
  48 #define RTL8366RB_SSCR0                         0x0002
  49 #define RTL8366RB_SSCR1                         0x0003
  50 #define RTL8366RB_SSCR2                         0x0004
  51 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA         BIT(0)
  52
  53 #define RTL8366RB_RESET_CTRL_REG                0x0100
  54 #define RTL8366RB_CHIP_CTRL_RESET_HW            1
  55 #define RTL8366RB_CHIP_CTRL_RESET_SW            (1 << 1)
  56
  57 #define RTL8366RB_CHIP_VERSION_CTRL_REG         0x050A
  58 #define RTL8366RB_CHIP_VERSION_MASK             0xf
  59 #define RTL8366RB_CHIP_ID_REG                   0x0509
  60 #define RTL8366RB_CHIP_ID_8366                  0x5937
  61
  62 /* PHY registers control */
  63 #define RTL8366RB_PHY_ACCESS_CTRL_REG           0x8000
  64 #define RTL8366RB_PHY_ACCESS_DATA_REG           0x8002
  65
  66 #define RTL8366RB_PHY_CTRL_READ                 1
  67 #define RTL8366RB_PHY_CTRL_WRITE                0
  68
  69 #define RTL8366RB_PHY_REG_MASK                  0x1f
  70 #define RTL8366RB_PHY_PAGE_OFFSET               5
  71 #define RTL8366RB_PHY_PAGE_MASK                 (0xf << 5)
  72 #define RTL8366RB_PHY_NO_OFFSET                 9
  73 #define RTL8366RB_PHY_NO_MASK                   (0x1f << 9)
  74
  75 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG        0x037f
  76
  77 /* LED control registers */
  78 #define RTL8366RB_LED_BLINKRATE_REG             0x0430
  79 #define RTL8366RB_LED_BLINKRATE_BIT             0
  80 #define RTL8366RB_LED_BLINKRATE_MASK            0x0007
  81
  82 #define RTL8366RB_LED_CTRL_REG                  0x0431
  83 #define RTL8366RB_LED_0_1_CTRL_REG              0x0432
  84 #define RTL8366RB_LED_2_3_CTRL_REG              0x0433
  85
  86 #define RTL8366RB_MIB_COUNT                     33
  87 #define RTL8366RB_GLOBAL_MIB_COUNT              1
  88 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET       0x0050
  89 #define RTL8366RB_MIB_COUNTER_BASE              0x1000
  90 #define RTL8366RB_MIB_CTRL_REG                  0x13F0
  91 #define RTL8366RB_MIB_CTRL_USER_MASK            0x0FFC
  92 #define RTL8366RB_MIB_CTRL_BUSY_MASK            BIT(0)
  93 #define RTL8366RB_MIB_CTRL_RESET_MASK           BIT(1)
  94 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)       BIT(2 + (_p))
  95 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET         BIT(11)
  96
  97 #define RTL8366RB_PORT_VLAN_CTRL_BASE           0x0063
  98 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
  99                 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
 100 #define RTL8366RB_PORT_VLAN_CTRL_MASK           0xf
 101 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)      (4 * ((_p) % 4))
 102
 103
 104 #define RTL8366RB_VLAN_TABLE_READ_BASE          0x018C
 105 #define RTL8366RB_VLAN_TABLE_WRITE_BASE         0x0185
 106
 107
 108 #define RTL8366RB_TABLE_ACCESS_CTRL_REG         0x0180
 109 #define RTL8366RB_TABLE_VLAN_READ_CTRL          0x0E01
 110 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL         0x0F01
 111
 112 #define RTL8366RB_VLAN_MC_BASE(_x)              (0x0020 + (_x) * 3)
 113
 114
 115 #define RTL8366RB_PORT_LINK_STATUS_BASE         0x0014
 116 #define RTL8366RB_PORT_STATUS_SPEED_MASK        0x0003
 117 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK       0x0004
 118 #define RTL8366RB_PORT_STATUS_LINK_MASK         0x0010
 119 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK      0x0020
 120 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK      0x0040
 121 #define RTL8366RB_PORT_STATUS_AN_MASK           0x0080
 122
 123
 124 #define RTL8366RB_PORT_NUM_CPU          5
 125 #define RTL8366RB_NUM_PORTS             6
 126 #define RTL8366RB_NUM_VLANS             16
 127 #define RTL8366RB_NUM_LEDGROUPS         4
 128 #define RTL8366RB_NUM_VIDS              4096
 129 #define RTL8366RB_PRIORITYMAX           7
 130 #define RTL8366RB_FIDMAX                7
 131
 132
 133 #define RTL8366RB_PORT_1                (1 << 0) /* In userspace port 0 */
 134 #define RTL8366RB_PORT_2                (1 << 1) /* In userspace port 1 */
 135 #define RTL8366RB_PORT_3                (1 << 2) /* In userspace port 2 */
 136 #define RTL8366RB_PORT_4                (1 << 3) /* In userspace port 3 */
 137 #define RTL8366RB_PORT_5                (1 << 4) /* In userspace port 4 */
 138
 139 #define RTL8366RB_PORT_CPU              (1 << 5) /* CPU port */
 140
 141 #define RTL8366RB_PORT_ALL              (RTL8366RB_PORT_1 |     \
 142                                          RTL8366RB_PORT_2 |     \
 143                                          RTL8366RB_PORT_3 |     \
 144                                          RTL8366RB_PORT_4 |     \
 145                                          RTL8366RB_PORT_5 |     \
 146                                          RTL8366RB_PORT_CPU)
 147
 148 #define RTL8366RB_PORT_ALL_BUT_CPU      (RTL8366RB_PORT_1 |     \
 149                                          RTL8366RB_PORT_2 |     \
 150                                          RTL8366RB_PORT_3 |     \
 151                                          RTL8366RB_PORT_4 |     \
 152                                          RTL8366RB_PORT_5)
 153
 154 #define RTL8366RB_PORT_ALL_EXTERNAL     (RTL8366RB_PORT_1 |     \
 155                                          RTL8366RB_PORT_2 |     \
 156                                          RTL8366RB_PORT_3 |     \
 157                                          RTL8366RB_PORT_4)
 158
 159 #define RTL8366RB_PORT_ALL_INTERNAL      RTL8366RB_PORT_CPU
 160
 161 #define RTL8366RB_VLAN_VID_MASK         0xfff
 162 #define RTL8366RB_VLAN_PRIORITY_SHIFT   12
 163 #define RTL8366RB_VLAN_PRIORITY_MASK    0x7
 164 #define RTL8366RB_VLAN_UNTAG_SHIFT      8
 165 #define RTL8366RB_VLAN_UNTAG_MASK       0xff
 166 #define RTL8366RB_VLAN_MEMBER_MASK      0xff
 167 #define RTL8366RB_VLAN_FID_MASK         0x7
 168
 169
 170 /* Port ingress bandwidth control */
 171 #define RTL8366RB_IB_BASE               0x0200
 172 #define RTL8366RB_IB_REG(pnum)          (RTL8366RB_IB_BASE + pnum)
 173 #define RTL8366RB_IB_BDTH_MASK          0x3fff
 174 #define RTL8366RB_IB_PREIFG_OFFSET      14
 175 #define RTL8366RB_IB_PREIFG_MASK        (1 << RTL8366RB_IB_PREIFG_OFFSET)
 176
 177 /* Port egress bandwidth control */
 178 #define RTL8366RB_EB_BASE               0x02d1
 179 #define RTL8366RB_EB_REG(pnum)          (RTL8366RB_EB_BASE + pnum)
 180 #define RTL8366RB_EB_BDTH_MASK          0x3fff
 181 #define RTL8366RB_EB_PREIFG_REG 0x02f8
 182 #define RTL8366RB_EB_PREIFG_OFFSET      9
 183 #define RTL8366RB_EB_PREIFG_MASK        (1 << RTL8366RB_EB_PREIFG_OFFSET)
 184
 185 #define RTL8366RB_BDTH_SW_MAX           1048512
 186 #define RTL8366RB_BDTH_UNIT             64
 187 #define RTL8366RB_BDTH_REG_DEFAULT      16383
 188
 189 /* QOS */
 190 #define RTL8366RB_QOS_BIT               15
 191 #define RTL8366RB_QOS_MASK              (1 << RTL8366RB_QOS_BIT)
 192 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
 193 #define RTL8366RB_QOS_DEFAULT_PREIFG    1
 194
 195
 196 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
 197         { 0,  0, 4, "IfInOctets"                                },
 198         { 0,  4, 4, "EtherStatsOctets"                          },
 199         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 200         { 0, 10, 2, "EtherFragments"                            },
 201         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 202         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 203         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 204         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 205         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 206         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 207         { 0, 24, 2, "EtherOversizeStats"                        },
 208         { 0, 26, 2, "EtherStatsJabbers"                         },
 209         { 0, 28, 2, "IfInUcastPkts"                             },
 210         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 211         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 212         { 0, 34, 2, "EtherStatsDropEvents"                      },
 213         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 214         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 215         { 0, 40, 2, "Dot3InPauseFrames"                         },
 216         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 217         { 0, 44, 4, "IfOutOctets"                               },
 218         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 219         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 220         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 221         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 222         { 0, 56, 2, "EtherStatsCollisions"                      },
 223         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 224         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 225         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 226         { 0, 64, 2, "Dot1dTpPortInDiscards"                     },
 227         { 0, 66, 2, "IfOutUcastPkts"                            },
 228         { 0, 68, 2, "IfOutMulticastPkts"                        },
 229         { 0, 70, 2, "IfOutBroadcastPkts"                        },
 230 };
 231
 232 #define REG_WR(_smi, _reg, _val)                                        \
 233         do {                                                            \
 234                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 235                 if (err)                                                \
 236                         return err;                                     \
 237         } while (0)
 238
 239 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 240         do {                                                            \
 241                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 242                 if (err)                                                \
 243                         return err;                                     \
 244         } while (0)
 245
 246 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
 247 {
 248         int timeout = 10;
 249         u32 data;
 250
 251         rtl8366_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG,
 252                                     RTL8366RB_CHIP_CTRL_RESET_HW);
 253         do {
 254                 msleep(1);
 255                 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
 256                         return -EIO;
 257
 258                 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
 259                         break;
 260         } while (--timeout);
 261
 262         if (!timeout) {
 263                 printk("Timeout waiting for the switch to reset\n");
 264                 return -EIO;
 265         }
 266
 267         return 0;
 268 }
 269
 270 static int rtl8366rb_setup(struct rtl8366_smi *smi)
 271 {
 272         int err;
 273
 274         /* set maximum packet length to 1536 bytes */
 275         REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
 276                 RTL8366RB_SGCR_MAX_LENGTH_1536);
 277
 278         /* enable learning for all ports */
 279         REG_WR(smi, RTL8366RB_SSCR0, 0);
 280
 281         /* enable auto ageing for all ports */
 282         REG_WR(smi, RTL8366RB_SSCR1, 0);
 283
 284         /*
 285          * discard VLAN tagged packets if the port is not a member of
 286          * the VLAN with which the packets is associated.
 287          */
 288         REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
 289
 290         /* don't drop packets whose DA has not been learned */
 291         REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
 292
 293         return 0;
 294 }
 295
 296 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
 297                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 298 {
 299         u32 reg;
 300         int ret;
 301
 302         if (phy_no > RTL8366RB_PHY_NO_MAX)
 303                 return -EINVAL;
 304
 305         if (page > RTL8366RB_PHY_PAGE_MAX)
 306                 return -EINVAL;
 307
 308         if (addr > RTL8366RB_PHY_ADDR_MAX)
 309                 return -EINVAL;
 310
 311         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 312                                     RTL8366RB_PHY_CTRL_READ);
 313         if (ret)
 314                 return ret;
 315
 316         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 317               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 318               (addr & RTL8366RB_PHY_REG_MASK);
 319
 320         ret = rtl8366_smi_write_reg(smi, reg, 0);
 321         if (ret)
 322                 return ret;
 323
 324         ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
 325         if (ret)
 326                 return ret;
 327
 328         return 0;
 329 }
 330
 331 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
 332                                   u32 phy_no, u32 page, u32 addr, u32 data)
 333 {
 334         u32 reg;
 335         int ret;
 336
 337         if (phy_no > RTL8366RB_PHY_NO_MAX)
 338                 return -EINVAL;
 339
 340         if (page > RTL8366RB_PHY_PAGE_MAX)
 341                 return -EINVAL;
 342
 343         if (addr > RTL8366RB_PHY_ADDR_MAX)
 344                 return -EINVAL;
 345
 346         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 347                                     RTL8366RB_PHY_CTRL_WRITE);
 348         if (ret)
 349                 return ret;
 350
 351         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 352               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 353               (addr & RTL8366RB_PHY_REG_MASK);
 354
 355         ret = rtl8366_smi_write_reg(smi, reg, data);
 356         if (ret)
 357                 return ret;
 358
 359         return 0;
 360 }
 361
 362 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
 363                                      int port, unsigned long long *val)
 364 {
 365         int i;
 366         int err;
 367         u32 addr, data;
 368         u64 mibvalue;
 369
 370         if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
 371                 return -EINVAL;
 372
 373         addr = RTL8366RB_MIB_COUNTER_BASE +
 374                RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
 375                rtl8366rb_mib_counters[counter].offset;
 376
 377         /*
 378          * Writing access counter address first
 379          * then ASIC will prepare 64bits counter wait for being retrived
 380          */
 381         data = 0; /* writing data will be discard by ASIC */
 382         err = rtl8366_smi_write_reg(smi, addr, data);
 383         if (err)
 384                 return err;
 385
 386         /* read MIB control register */
 387         err =  rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
 388         if (err)
 389                 return err;
 390
 391         if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
 392                 return -EBUSY;
 393
 394         if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
 395                 return -EIO;
 396
 397         mibvalue = 0;
 398         for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
 399                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 400                 if (err)
 401                         return err;
 402
 403                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 404         }
 405
 406         *val = mibvalue;
 407         return 0;
 408 }
 409
 410 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 411                                  struct rtl8366_vlan_4k *vlan4k)
 412 {
 413         u32 data[3];
 414         int err;
 415         int i;
 416
 417         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 418
 419         if (vid >= RTL8366RB_NUM_VIDS)
 420                 return -EINVAL;
 421
 422         /* write VID */
 423         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
 424                                     vid & RTL8366RB_VLAN_VID_MASK);
 425         if (err)
 426                 return err;
 427
 428         /* write table access control word */
 429         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 430                                     RTL8366RB_TABLE_VLAN_READ_CTRL);
 431         if (err)
 432                 return err;
 433
 434         for (i = 0; i < 3; i++) {
 435                 err = rtl8366_smi_read_reg(smi,
 436                                            RTL8366RB_VLAN_TABLE_READ_BASE + i,
 437                                            &data[i]);
 438                 if (err)
 439                         return err;
 440         }
 441
 442         vlan4k->vid = vid;
 443         vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
 444                         RTL8366RB_VLAN_UNTAG_MASK;
 445         vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
 446         vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
 447
 448         return 0;
 449 }
 450
 451 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
 452                                  const struct rtl8366_vlan_4k *vlan4k)
 453 {
 454         u32 data[3];
 455         int err;
 456         int i;
 457
 458         if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
 459             vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
 460             vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
 461             vlan4k->fid > RTL8366RB_FIDMAX)
 462                 return -EINVAL;
 463
 464         data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
 465         data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
 466                   ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
 467                         RTL8366RB_VLAN_UNTAG_SHIFT);
 468         data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
 469
 470         for (i = 0; i < 3; i++) {
 471                 err = rtl8366_smi_write_reg(smi,
 472                                             RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
 473                                             data[i]);
 474                 if (err)
 475                         return err;
 476         }
 477
 478         /* write table access control word */
 479         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 480                                     RTL8366RB_TABLE_VLAN_WRITE_CTRL);
 481
 482         return err;
 483 }
 484
 485 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 486                                  struct rtl8366_vlan_mc *vlanmc)
 487 {
 488         u32 data[3];
 489         int err;
 490         int i;
 491
 492         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 493
 494         if (index >= RTL8366RB_NUM_VLANS)
 495                 return -EINVAL;
 496
 497         for (i = 0; i < 3; i++) {
 498                 err = rtl8366_smi_read_reg(smi,
 499                                            RTL8366RB_VLAN_MC_BASE(index) + i,
 500                                            &data[i]);
 501                 if (err)
 502                         return err;
 503         }
 504
 505         vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
 506         vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
 507                            RTL8366RB_VLAN_PRIORITY_MASK;
 508         vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
 509                         RTL8366RB_VLAN_UNTAG_MASK;
 510         vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
 511         vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
 512
 513         return 0;
 514 }
 515
 516 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 517                                  const struct rtl8366_vlan_mc *vlanmc)
 518 {
 519         u32 data[3];
 520         int err;
 521         int i;
 522
 523         if (index >= RTL8366RB_NUM_VLANS ||
 524             vlanmc->vid >= RTL8366RB_NUM_VIDS ||
 525             vlanmc->priority > RTL8366RB_PRIORITYMAX ||
 526             vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
 527             vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
 528             vlanmc->fid > RTL8366RB_FIDMAX)
 529                 return -EINVAL;
 530
 531         data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
 532                   ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
 533                         RTL8366RB_VLAN_PRIORITY_SHIFT);
 534         data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
 535                   ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
 536                         RTL8366RB_VLAN_UNTAG_SHIFT);
 537         data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
 538
 539         for (i = 0; i < 3; i++) {
 540                 err = rtl8366_smi_write_reg(smi,
 541                                             RTL8366RB_VLAN_MC_BASE(index) + i,
 542                                             data[i]);
 543                 if (err)
 544                         return err;
 545         }
 546
 547         return 0;
 548 }
 549
 550 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 551 {
 552         u32 data;
 553         int err;
 554
 555         if (port >= RTL8366RB_NUM_PORTS)
 556                 return -EINVAL;
 557
 558         err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 559                                    &data);
 560         if (err)
 561                 return err;
 562
 563         *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
 564                RTL8366RB_PORT_VLAN_CTRL_MASK;
 565
 566         return 0;
 567
 568 }
 569
 570 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 571 {
 572         if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
 573                 return -EINVAL;
 574
 575         return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 576                                 RTL8366RB_PORT_VLAN_CTRL_MASK <<
 577                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
 578                                 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
 579                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
 580 }
 581
 582 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
 583 {
 584         unsigned max = RTL8366RB_NUM_VLANS;
 585
 586         if (smi->vlan4k_enabled)
 587                 max = RTL8366RB_NUM_VIDS - 1;
 588
 589         if (vlan == 0 || vlan >= max)
 590                 return 0;
 591
 592         return 1;
 593 }
 594
 595 static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
 596 {
 597         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
 598                                 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
 599 }
 600
 601 static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
 602 {
 603         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
 604                                 RTL8366RB_SGCR_EN_VLAN_4KTB,
 605                                 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
 606 }
 607
 608 static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable)
 609 {
 610         return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port),
 611                                 (enable) ? 0 : (1 << port));
 612 }
 613
 614 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
 615                                   const struct switch_attr *attr,
 616                                   struct switch_val *val)
 617 {
 618         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 619
 620         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 621                                 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
 622 }
 623
 624 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
 625                                      const struct switch_attr *attr,
 626                                      struct switch_val *val)
 627 {
 628         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 629         u32 data;
 630
 631         rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
 632
 633         val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
 634
 635         return 0;
 636 }
 637
 638 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
 639                                     const struct switch_attr *attr,
 640                                     struct switch_val *val)
 641 {
 642         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 643
 644         if (val->value.i >= 6)
 645                 return -EINVAL;
 646
 647         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
 648                                 RTL8366RB_LED_BLINKRATE_MASK,
 649                                 val->value.i);
 650 }
 651
 652 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
 653                                        const struct switch_attr *attr,
 654                                        struct switch_val *val)
 655 {
 656         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 657         u32 data;
 658
 659         rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
 660         val->value.i = !data;
 661
 662         return 0;
 663 }
 664
 665
 666 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
 667                                        const struct switch_attr *attr,
 668                                        struct switch_val *val)
 669 {
 670         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 671         u32 portmask = 0;
 672         int err = 0;
 673
 674         if (!val->value.i)
 675                 portmask = RTL8366RB_PORT_ALL;
 676
 677         /* set learning for all ports */
 678         REG_WR(smi, RTL8366RB_SSCR0, portmask);
 679
 680         /* set auto ageing for all ports */
 681         REG_WR(smi, RTL8366RB_SSCR1, portmask);
 682
 683         return 0;
 684 }
 685
 686 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
 687                                      int port,
 688                                      struct switch_port_link *link)
 689 {
 690         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 691         u32 data = 0;
 692         u32 speed;
 693
 694         if (port >= RTL8366RB_NUM_PORTS)
 695                 return -EINVAL;
 696
 697         rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + (port / 2),
 698                              &data);
 699
 700         if (port % 2)
 701                 data = data >> 8;
 702
 703         link->link = !!(data & RTL8366RB_PORT_STATUS_LINK_MASK);
 704         if (!link->link)
 705                 return 0;
 706
 707         link->duplex = !!(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK);
 708         link->rx_flow = !!(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK);
 709         link->tx_flow = !!(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK);
 710         link->aneg = !!(data & RTL8366RB_PORT_STATUS_AN_MASK);
 711
 712         speed = (data & RTL8366RB_PORT_STATUS_SPEED_MASK);
 713         switch (speed) {
 714         case 0:
 715                 link->speed = SWITCH_PORT_SPEED_10;
 716                 break;
 717         case 1:
 718                 link->speed = SWITCH_PORT_SPEED_100;
 719                 break;
 720         case 2:
 721                 link->speed = SWITCH_PORT_SPEED_1000;
 722                 break;
 723         default:
 724                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 725                 break;
 726         }
 727
 728         return 0;
 729 }
 730
 731 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
 732                                     const struct switch_attr *attr,
 733                                     struct switch_val *val)
 734 {
 735         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 736         u32 data;
 737         u32 mask;
 738         u32 reg;
 739
 740         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 741                 return -EINVAL;
 742
 743         if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
 744                 reg = RTL8366RB_LED_BLINKRATE_REG;
 745                 mask = 0xF << 4;
 746                 data = val->value.i << 4;
 747         } else {
 748                 reg = RTL8366RB_LED_CTRL_REG;
 749                 mask = 0xF << (val->port_vlan * 4),
 750                 data = val->value.i << (val->port_vlan * 4);
 751         }
 752
 753         return rtl8366_smi_rmwr(smi, reg, mask, data);
 754 }
 755
 756 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
 757                                     const struct switch_attr *attr,
 758                                     struct switch_val *val)
 759 {
 760         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 761         u32 data = 0;
 762
 763         if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
 764                 return -EINVAL;
 765
 766         rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
 767         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 768
 769         return 0;
 770 }
 771
 772 static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
 773                                     const struct switch_attr *attr,
 774                                     struct switch_val *val)
 775 {
 776         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 777         u32 mask, data;
 778
 779         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 780                 return -EINVAL;
 781
 782         mask = 1 << val->port_vlan ;
 783         if (val->value.i)
 784                 data = mask;
 785         else
 786                 data = 0;
 787
 788         return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
 789 }
 790
 791 static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
 792                                     const struct switch_attr *attr,
 793                                     struct switch_val *val)
 794 {
 795         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 796         u32 data;
 797
 798         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 799                 return -EINVAL;
 800
 801         rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
 802         if (data & (1 << val->port_vlan))
 803                 val->value.i = 1;
 804         else
 805                 val->value.i = 0;
 806
 807         return 0;
 808 }
 809
 810 static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
 811                                     const struct switch_attr *attr,
 812                                     struct switch_val *val)
 813 {
 814         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 815
 816         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 817                 return -EINVAL;
 818
 819         if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
 820                 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
 821         else
 822                 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
 823
 824         return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
 825                 RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
 826                 val->value.i |
 827                 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
 828
 829 }
 830
 831 static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
 832                                     const struct switch_attr *attr,
 833                                     struct switch_val *val)
 834 {
 835         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 836         u32 data;
 837
 838         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 839                 return -EINVAL;
 840
 841         rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
 842         data &= RTL8366RB_IB_BDTH_MASK;
 843         if (data < RTL8366RB_IB_BDTH_MASK)
 844                 data += 1;
 845
 846         val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
 847
 848         return 0;
 849 }
 850
 851 static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
 852                                     const struct switch_attr *attr,
 853                                     struct switch_val *val)
 854 {
 855         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 856
 857         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 858                 return -EINVAL;
 859
 860         rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
 861                 RTL8366RB_EB_PREIFG_MASK,
 862                 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
 863
 864         if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
 865                 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
 866         else
 867                 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
 868
 869         return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
 870                         RTL8366RB_EB_BDTH_MASK, val->value.i );
 871
 872 }
 873
 874 static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
 875                                     const struct switch_attr *attr,
 876                                     struct switch_val *val)
 877 {
 878         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 879         u32 data;
 880
 881         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 882                 return -EINVAL;
 883
 884         rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
 885         data &= RTL8366RB_EB_BDTH_MASK;
 886         if (data < RTL8366RB_EB_BDTH_MASK)
 887                 data += 1;
 888
 889         val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
 890
 891         return 0;
 892 }
 893
 894 static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
 895                                     const struct switch_attr *attr,
 896                                     struct switch_val *val)
 897 {
 898         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 899         u32 data;
 900
 901         if (val->value.i)
 902                 data = RTL8366RB_QOS_MASK;
 903         else
 904                 data = 0;
 905
 906         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
 907 }
 908
 909 static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
 910                                     const struct switch_attr *attr,
 911                                     struct switch_val *val)
 912 {
 913         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 914         u32 data;
 915
 916         rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
 917         if (data & RTL8366RB_QOS_MASK)
 918                 val->value.i = 1;
 919         else
 920                 val->value.i = 0;
 921
 922         return 0;
 923 }
 924
 925 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
 926                                        const struct switch_attr *attr,
 927                                        struct switch_val *val)
 928 {
 929         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 930
 931         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 932                 return -EINVAL;
 933
 934         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 935                                 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
 936 }
 937
 938 static struct switch_attr rtl8366rb_globals[] = {
 939         {
 940                 .type = SWITCH_TYPE_INT,
 941                 .name = "enable_learning",
 942                 .description = "Enable learning, enable aging",
 943                 .set = rtl8366rb_sw_set_learning_enable,
 944                 .get = rtl8366rb_sw_get_learning_enable,
 945                 .max = 1
 946         }, {
 947                 .type = SWITCH_TYPE_INT,
 948                 .name = "enable_vlan",
 949                 .description = "Enable VLAN mode",
 950                 .set = rtl8366_sw_set_vlan_enable,
 951                 .get = rtl8366_sw_get_vlan_enable,
 952                 .max = 1,
 953                 .ofs = 1
 954         }, {
 955                 .type = SWITCH_TYPE_INT,
 956                 .name = "enable_vlan4k",
 957                 .description = "Enable VLAN 4K mode",
 958                 .set = rtl8366_sw_set_vlan_enable,
 959                 .get = rtl8366_sw_get_vlan_enable,
 960                 .max = 1,
 961                 .ofs = 2
 962         }, {
 963                 .type = SWITCH_TYPE_NOVAL,
 964                 .name = "reset_mibs",
 965                 .description = "Reset all MIB counters",
 966                 .set = rtl8366rb_sw_reset_mibs,
 967         }, {
 968                 .type = SWITCH_TYPE_INT,
 969                 .name = "blinkrate",
 970                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
 971                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
 972                 .set = rtl8366rb_sw_set_blinkrate,
 973                 .get = rtl8366rb_sw_get_blinkrate,
 974                 .max = 5
 975         }, {
 976                 .type = SWITCH_TYPE_INT,
 977                 .name = "enable_qos",
 978                 .description = "Enable QOS",
 979                 .set = rtl8366rb_sw_set_qos_enable,
 980                 .get = rtl8366rb_sw_get_qos_enable,
 981                 .max = 1
 982         },
 983 };
 984
 985 static struct switch_attr rtl8366rb_port[] = {
 986         {
 987                 .type = SWITCH_TYPE_NOVAL,
 988                 .name = "reset_mib",
 989                 .description = "Reset single port MIB counters",
 990                 .set = rtl8366rb_sw_reset_port_mibs,
 991         }, {
 992                 .type = SWITCH_TYPE_STRING,
 993                 .name = "mib",
 994                 .description = "Get MIB counters for port",
 995                 .max = 33,
 996                 .set = NULL,
 997                 .get = rtl8366_sw_get_port_mib,
 998         }, {
 999                 .type = SWITCH_TYPE_INT,
1000                 .name = "led",
1001                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1002                 .max = 15,
1003                 .set = rtl8366rb_sw_set_port_led,
1004                 .get = rtl8366rb_sw_get_port_led,
1005         }, {
1006                 .type = SWITCH_TYPE_INT,
1007                 .name = "disable",
1008                 .description = "Get/Set port state (enabled or disabled)",
1009                 .max = 1,
1010                 .set = rtl8366rb_sw_set_port_disable,
1011                 .get = rtl8366rb_sw_get_port_disable,
1012         }, {
1013                 .type = SWITCH_TYPE_INT,
1014                 .name = "rate_in",
1015                 .description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
1016                 .max = RTL8366RB_BDTH_SW_MAX,
1017                 .set = rtl8366rb_sw_set_port_rate_in,
1018                 .get = rtl8366rb_sw_get_port_rate_in,
1019         }, {
1020                 .type = SWITCH_TYPE_INT,
1021                 .name = "rate_out",
1022                 .description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
1023                 .max = RTL8366RB_BDTH_SW_MAX,
1024                 .set = rtl8366rb_sw_set_port_rate_out,
1025                 .get = rtl8366rb_sw_get_port_rate_out,
1026         },
1027 };
1028
1029 static struct switch_attr rtl8366rb_vlan[] = {
1030         {
1031                 .type = SWITCH_TYPE_STRING,
1032                 .name = "info",
1033                 .description = "Get vlan information",
1034                 .max = 1,
1035                 .set = NULL,
1036                 .get = rtl8366_sw_get_vlan_info,
1037         }, {
1038                 .type = SWITCH_TYPE_INT,
1039                 .name = "fid",
1040                 .description = "Get/Set vlan FID",
1041                 .max = RTL8366RB_FIDMAX,
1042                 .set = rtl8366_sw_set_vlan_fid,
1043                 .get = rtl8366_sw_get_vlan_fid,
1044         },
1045 };
1046
1047 static const struct switch_dev_ops rtl8366_ops = {
1048         .attr_global = {
1049                 .attr = rtl8366rb_globals,
1050                 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1051         },
1052         .attr_port = {
1053                 .attr = rtl8366rb_port,
1054                 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1055         },
1056         .attr_vlan = {
1057                 .attr = rtl8366rb_vlan,
1058                 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1059         },
1060
1061         .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1062         .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1063         .get_port_pvid = rtl8366_sw_get_port_pvid,
1064         .set_port_pvid = rtl8366_sw_set_port_pvid,
1065         .reset_switch = rtl8366_sw_reset_switch,
1066         .get_port_link = rtl8366rb_sw_get_port_link,
1067 };
1068
1069 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
1070 {
1071         struct switch_dev *dev = &smi->sw_dev;
1072         int err;
1073
1074         dev->name = "RTL8366RB";
1075         dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
1076         dev->ports = RTL8366RB_NUM_PORTS;
1077         dev->vlans = RTL8366RB_NUM_VIDS;
1078         dev->ops = &rtl8366_ops;
1079         dev->alias = dev_name(smi->parent);
1080
1081         err = register_switch(dev, NULL);
1082         if (err)
1083                 dev_err(smi->parent, "switch registration failed\n");
1084
1085         return err;
1086 }
1087
1088 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
1089 {
1090         unregister_switch(&smi->sw_dev);
1091 }
1092
1093 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1094 {
1095         struct rtl8366_smi *smi = bus->priv;
1096         u32 val = 0;
1097         int err;
1098
1099         err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1100         if (err)
1101                 return 0xffff;
1102
1103         return val;
1104 }
1105
1106 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1107 {
1108         struct rtl8366_smi *smi = bus->priv;
1109         u32 t;
1110         int err;
1111
1112         err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1113         /* flush write */
1114         (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1115
1116         return err;
1117 }
1118
1119 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1120 {
1121         u32 chip_id = 0;
1122         u32 chip_ver = 0;
1123         int ret;
1124
1125         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1126         if (ret) {
1127                 dev_err(smi->parent, "unable to read chip id\n");
1128                 return ret;
1129         }
1130
1131         switch (chip_id) {
1132         case RTL8366RB_CHIP_ID_8366:
1133                 break;
1134         default:
1135                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1136                 return -ENODEV;
1137         }
1138
1139         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1140                                    &chip_ver);
1141         if (ret) {
1142                 dev_err(smi->parent, "unable to read chip version\n");
1143                 return ret;
1144         }
1145
1146         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1147                  chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1148
1149         return 0;
1150 }
1151
1152 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1153         .detect         = rtl8366rb_detect,
1154         .reset_chip     = rtl8366rb_reset_chip,
1155         .setup          = rtl8366rb_setup,
1156
1157         .mii_read       = rtl8366rb_mii_read,
1158         .mii_write      = rtl8366rb_mii_write,
1159
1160         .get_vlan_mc    = rtl8366rb_get_vlan_mc,
1161         .set_vlan_mc    = rtl8366rb_set_vlan_mc,
1162         .get_vlan_4k    = rtl8366rb_get_vlan_4k,
1163         .set_vlan_4k    = rtl8366rb_set_vlan_4k,
1164         .get_mc_index   = rtl8366rb_get_mc_index,
1165         .set_mc_index   = rtl8366rb_set_mc_index,
1166         .get_mib_counter = rtl8366rb_get_mib_counter,
1167         .is_vlan_valid  = rtl8366rb_is_vlan_valid,
1168         .enable_vlan    = rtl8366rb_enable_vlan,
1169         .enable_vlan4k  = rtl8366rb_enable_vlan4k,
1170         .enable_port    = rtl8366rb_enable_port,
1171 };
1172
1173 static int __devinit rtl8366rb_probe(struct platform_device *pdev)
1174 {
1175         static int rtl8366_smi_version_printed;
1176         struct rtl8366_smi *smi;
1177         int err;
1178
1179         if (!rtl8366_smi_version_printed++)
1180                 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1181                        " version " RTL8366RB_DRIVER_VER"\n");
1182
1183         smi = rtl8366_smi_probe(pdev);
1184         if (!smi)
1185                 return -ENODEV;
1186
1187         smi->clk_delay = 10;
1188         smi->cmd_read = 0xa9;
1189         smi->cmd_write = 0xa8;
1190         smi->ops = &rtl8366rb_smi_ops;
1191         smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1192         smi->num_ports = RTL8366RB_NUM_PORTS;
1193         smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1194         smi->mib_counters = rtl8366rb_mib_counters;
1195         smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1196
1197         err = rtl8366_smi_init(smi);
1198         if (err)
1199                 goto err_free_smi;
1200
1201         platform_set_drvdata(pdev, smi);
1202
1203         err = rtl8366rb_switch_init(smi);
1204         if (err)
1205                 goto err_clear_drvdata;
1206
1207         return 0;
1208
1209  err_clear_drvdata:
1210         platform_set_drvdata(pdev, NULL);
1211         rtl8366_smi_cleanup(smi);
1212  err_free_smi:
1213         kfree(smi);
1214         return err;
1215 }
1216
1217 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1218 {
1219         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1220
1221         if (smi) {
1222                 rtl8366rb_switch_cleanup(smi);
1223                 platform_set_drvdata(pdev, NULL);
1224                 rtl8366_smi_cleanup(smi);
1225                 kfree(smi);
1226         }
1227
1228         return 0;
1229 }
1230
1231 #ifdef CONFIG_OF
1232 static const struct of_device_id rtl8366rb_match[] = {
1233         { .compatible = "rtl8366rb" },
1234         {},
1235 };
1236 MODULE_DEVICE_TABLE(of, rtl8366rb_match);
1237 #endif
1238
1239 static struct platform_driver rtl8366rb_driver = {
1240         .driver = {
1241                 .name           = RTL8366RB_DRIVER_NAME,
1242                 .owner          = THIS_MODULE,
1243                 .of_match_table = of_match_ptr(rtl8366rb_match),
1244         },
1245         .probe          = rtl8366rb_probe,
1246         .remove         = __devexit_p(rtl8366rb_remove),
1247 };
1248
1249 static int __init rtl8366rb_module_init(void)
1250 {
1251         return platform_driver_register(&rtl8366rb_driver);
1252 }
1253 module_init(rtl8366rb_module_init);
1254
1255 static void __exit rtl8366rb_module_exit(void)
1256 {
1257         platform_driver_unregister(&rtl8366rb_driver);
1258 }
1259 module_exit(rtl8366rb_module_exit);
1260
1261 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1262 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1263 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1264 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1265 MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1266 MODULE_LICENSE("GPL v2");
1267 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);