target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include "ar8216.h"
  37
  38 /* size of the vlan table */
  39 #define AR8X16_MAX_VLANS        128
  40 #define AR8X16_PROBE_RETRIES    10
  41 #define AR8X16_MAX_PORTS        8
  42
  43 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  44
  45 struct ar8216_priv;
  46
  47 #define AR8XXX_CAP_GIGE                 BIT(0)
  48 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  49
  50 enum {
  51         AR8XXX_VER_AR8216 = 0x01,
  52         AR8XXX_VER_AR8236 = 0x03,
  53         AR8XXX_VER_AR8316 = 0x10,
  54         AR8XXX_VER_AR8327 = 0x12,
  55 };
  56
  57 struct ar8xxx_mib_desc {
  58         unsigned int size;
  59         unsigned int offset;
  60         const char *name;
  61 };
  62
  63 struct ar8xxx_chip {
  64         unsigned long caps;
  65
  66         int (*hw_init)(struct ar8216_priv *priv);
  67         void (*init_globals)(struct ar8216_priv *priv);
  68         void (*init_port)(struct ar8216_priv *priv, int port);
  69         void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
  70                            u32 ingress, u32 members, u32 pvid);
  71         u32 (*read_port_status)(struct ar8216_priv *priv, int port);
  72         int (*atu_flush)(struct ar8216_priv *priv);
  73         void (*vtu_flush)(struct ar8216_priv *priv);
  74         void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
  75
  76         const struct ar8xxx_mib_desc *mib_decs;
  77         unsigned num_mibs;
  78 };
  79
  80 struct ar8216_priv {
  81         struct switch_dev dev;
  82         struct mii_bus *mii_bus;
  83         struct phy_device *phy;
  84         u32 (*read)(struct ar8216_priv *priv, int reg);
  85         void (*write)(struct ar8216_priv *priv, int reg, u32 val);
  86         const struct net_device_ops *ndo_old;
  87         struct net_device_ops ndo;
  88         struct mutex reg_mutex;
  89         u8 chip_ver;
  90         u8 chip_rev;
  91         const struct ar8xxx_chip *chip;
  92         bool initialized;
  93         bool port4_phy;
  94         char buf[2048];
  95
  96         bool init;
  97         bool mii_lo_first;
  98
  99         struct mutex mib_lock;
 100         struct delayed_work mib_work;
 101         int mib_next_port;
 102         u64 *mib_stats;
 103
 104         /* all fields below are cleared on reset */
 105         bool vlan;
 106         u16 vlan_id[AR8X16_MAX_VLANS];
 107         u8 vlan_table[AR8X16_MAX_VLANS];
 108         u8 vlan_tagged;
 109         u16 pvid[AR8X16_MAX_PORTS];
 110 };
 111
 112 #define MIB_DESC(_s , _o, _n)   \
 113         {                       \
 114                 .size = (_s),   \
 115                 .offset = (_o), \
 116                 .name = (_n),   \
 117         }
 118
 119 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
 120         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 121         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 122         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 123         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 124         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 125         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 126         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 127         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 128         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 129         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 130         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 131         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 132         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 133         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 134         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 135         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 136         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 137         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 138         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 139         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 140         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 141         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 142         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 143         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 144         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 145         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 146         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 147         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 148         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 149         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 150         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 151         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 152         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 153         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 154         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 155         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 156         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 157 };
 158
 159 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 160         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 161         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 162         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 163         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 164         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 165         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 166         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 167         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 168         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 169         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 170         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 171         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 172         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 173         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 174         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 175         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 176         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 177         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 178         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 179         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 180         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 181         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 182         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 183         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 184         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 185         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 186         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 187         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 188         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 189         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 190         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 191         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 192         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 193         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 194         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 195         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 196         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 197         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 198         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 199 };
 200
 201 static inline struct ar8216_priv *
 202 swdev_to_ar8216(struct switch_dev *swdev)
 203 {
 204         return container_of(swdev, struct ar8216_priv, dev);
 205 }
 206
 207 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
 208 {
 209         return priv->chip->caps & AR8XXX_CAP_GIGE;
 210 }
 211
 212 static inline bool ar8xxx_has_mib_counters(struct ar8216_priv *priv)
 213 {
 214         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 215 }
 216
 217 static inline bool chip_is_ar8216(struct ar8216_priv *priv)
 218 {
 219         return priv->chip_ver == AR8XXX_VER_AR8216;
 220 }
 221
 222 static inline bool chip_is_ar8236(struct ar8216_priv *priv)
 223 {
 224         return priv->chip_ver == AR8XXX_VER_AR8236;
 225 }
 226
 227 static inline bool chip_is_ar8316(struct ar8216_priv *priv)
 228 {
 229         return priv->chip_ver == AR8XXX_VER_AR8316;
 230 }
 231
 232 static inline bool chip_is_ar8327(struct ar8216_priv *priv)
 233 {
 234         return priv->chip_ver == AR8XXX_VER_AR8327;
 235 }
 236
 237 static inline void
 238 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 239 {
 240         regaddr >>= 1;
 241         *r1 = regaddr & 0x1e;
 242
 243         regaddr >>= 5;
 244         *r2 = regaddr & 0x7;
 245
 246         regaddr >>= 3;
 247         *page = regaddr & 0x1ff;
 248 }
 249
 250 static u32
 251 ar8216_mii_read(struct ar8216_priv *priv, int reg)
 252 {
 253         struct mii_bus *bus = priv->mii_bus;
 254         u16 r1, r2, page;
 255         u16 lo, hi;
 256
 257         split_addr((u32) reg, &r1, &r2, &page);
 258
 259         mutex_lock(&bus->mdio_lock);
 260
 261         bus->write(bus, 0x18, 0, page);
 262         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 263         lo = bus->read(bus, 0x10 | r2, r1);
 264         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 265
 266         mutex_unlock(&bus->mdio_lock);
 267
 268         return (hi << 16) | lo;
 269 }
 270
 271 static void
 272 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
 273 {
 274         struct mii_bus *bus = priv->mii_bus;
 275         u16 r1, r2, r3;
 276         u16 lo, hi;
 277
 278         split_addr((u32) reg, &r1, &r2, &r3);
 279         lo = val & 0xffff;
 280         hi = (u16) (val >> 16);
 281
 282         mutex_lock(&bus->mdio_lock);
 283
 284         bus->write(bus, 0x18, 0, r3);
 285         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 286         if (priv->mii_lo_first) {
 287                 bus->write(bus, 0x10 | r2, r1, lo);
 288                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 289         } else {
 290                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 291                 bus->write(bus, 0x10 | r2, r1, lo);
 292         }
 293
 294         mutex_unlock(&bus->mdio_lock);
 295 }
 296
 297 static void
 298 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
 299                      u16 dbg_addr, u16 dbg_data)
 300 {
 301         struct mii_bus *bus = priv->mii_bus;
 302
 303         mutex_lock(&bus->mdio_lock);
 304         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 305         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 306         mutex_unlock(&bus->mdio_lock);
 307 }
 308
 309 static void
 310 ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
 311 {
 312         struct mii_bus *bus = priv->mii_bus;
 313
 314         mutex_lock(&bus->mdio_lock);
 315         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 316         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 317         mutex_unlock(&bus->mdio_lock);
 318 }
 319
 320 static u32
 321 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
 322 {
 323         u32 v;
 324
 325         lockdep_assert_held(&priv->reg_mutex);
 326
 327         v = priv->read(priv, reg);
 328         v &= ~mask;
 329         v |= val;
 330         priv->write(priv, reg, v);
 331
 332         return v;
 333 }
 334
 335 static inline void
 336 ar8216_reg_set(struct ar8216_priv *priv, int reg, u32 val)
 337 {
 338         u32 v;
 339
 340         lockdep_assert_held(&priv->reg_mutex);
 341
 342         v = priv->read(priv, reg);
 343         v |= val;
 344         priv->write(priv, reg, v);
 345 }
 346
 347 static int
 348 ar8216_reg_wait(struct ar8216_priv *priv, u32 reg, u32 mask, u32 val,
 349                 unsigned timeout)
 350 {
 351         int i;
 352
 353         for (i = 0; i < timeout; i++) {
 354                 u32 t;
 355
 356                 t = priv->read(priv, reg);
 357                 if ((t & mask) == val)
 358                         return 0;
 359
 360                 usleep_range(1000, 2000);
 361         }
 362
 363         return -ETIMEDOUT;
 364 }
 365
 366 static int
 367 ar8216_mib_op(struct ar8216_priv *priv, u32 op)
 368 {
 369         unsigned mib_func;
 370         int ret;
 371
 372         lockdep_assert_held(&priv->mib_lock);
 373
 374         if (chip_is_ar8327(priv))
 375                 mib_func = AR8327_REG_MIB_FUNC;
 376         else
 377                 mib_func = AR8216_REG_MIB_FUNC;
 378
 379         mutex_lock(&priv->reg_mutex);
 380         /* Capture the hardware statistics for all ports */
 381         ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 382         mutex_unlock(&priv->reg_mutex);
 383
 384         /* Wait for the capturing to complete. */
 385         ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 386         if (ret)
 387                 goto out;
 388
 389         ret = 0;
 390
 391 out:
 392         return ret;
 393 }
 394
 395 static int
 396 ar8216_mib_capture(struct ar8216_priv *priv)
 397 {
 398         return ar8216_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 399 }
 400
 401 static int
 402 ar8216_mib_flush(struct ar8216_priv *priv)
 403 {
 404         return ar8216_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 405 }
 406
 407 static void
 408 ar8216_mib_fetch_port_stat(struct ar8216_priv *priv, int port, bool flush)
 409 {
 410         unsigned int base;
 411         u64 *mib_stats;
 412         int i;
 413
 414         WARN_ON(port >= priv->dev.ports);
 415
 416         lockdep_assert_held(&priv->mib_lock);
 417
 418         if (chip_is_ar8327(priv))
 419                 base = AR8327_REG_PORT_STATS_BASE(port);
 420         else if (chip_is_ar8236(priv) ||
 421                  chip_is_ar8316(priv))
 422                 base = AR8236_REG_PORT_STATS_BASE(port);
 423         else
 424                 base = AR8216_REG_PORT_STATS_BASE(port);
 425
 426         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 427         for (i = 0; i < priv->chip->num_mibs; i++) {
 428                 const struct ar8xxx_mib_desc *mib;
 429                 u64 t;
 430
 431                 mib = &priv->chip->mib_decs[i];
 432                 t = priv->read(priv, base + mib->offset);
 433                 if (mib->size == 2) {
 434                         u64 hi;
 435
 436                         hi = priv->read(priv, base + mib->offset + 4);
 437                         t |= hi << 32;
 438                 }
 439
 440                 if (flush)
 441                         mib_stats[i] = 0;
 442                 else
 443                         mib_stats[i] += t;
 444         }
 445 }
 446
 447 static void
 448 ar8216_read_port_link(struct ar8216_priv *priv, int port,
 449                       struct switch_port_link *link)
 450 {
 451         u32 status;
 452         u32 speed;
 453
 454         memset(link, '\0', sizeof(*link));
 455
 456         status = priv->chip->read_port_status(priv, port);
 457
 458         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 459         if (link->aneg) {
 460                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 461                 if (!link->link)
 462                         return;
 463         } else {
 464                 link->link = true;
 465         }
 466
 467         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 468         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 469         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 470
 471         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 472                  AR8216_PORT_STATUS_SPEED_S;
 473
 474         switch (speed) {
 475         case AR8216_PORT_SPEED_10M:
 476                 link->speed = SWITCH_PORT_SPEED_10;
 477                 break;
 478         case AR8216_PORT_SPEED_100M:
 479                 link->speed = SWITCH_PORT_SPEED_100;
 480                 break;
 481         case AR8216_PORT_SPEED_1000M:
 482                 link->speed = SWITCH_PORT_SPEED_1000;
 483                 break;
 484         default:
 485                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 486                 break;
 487         }
 488 }
 489
 490 static struct sk_buff *
 491 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 492 {
 493         struct ar8216_priv *priv = dev->phy_ptr;
 494         unsigned char *buf;
 495
 496         if (unlikely(!priv))
 497                 goto error;
 498
 499         if (!priv->vlan)
 500                 goto send;
 501
 502         if (unlikely(skb_headroom(skb) < 2)) {
 503                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 504                         goto error;
 505         }
 506
 507         buf = skb_push(skb, 2);
 508         buf[0] = 0x10;
 509         buf[1] = 0x80;
 510
 511 send:
 512         return skb;
 513
 514 error:
 515         dev_kfree_skb_any(skb);
 516         return NULL;
 517 }
 518
 519 static void
 520 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 521 {
 522         struct ar8216_priv *priv;
 523         unsigned char *buf;
 524         int port, vlan;
 525
 526         priv = dev->phy_ptr;
 527         if (!priv)
 528                 return;
 529
 530         /* don't strip the header if vlan mode is disabled */
 531         if (!priv->vlan)
 532                 return;
 533
 534         /* strip header, get vlan id */
 535         buf = skb->data;
 536         skb_pull(skb, 2);
 537
 538         /* check for vlan header presence */
 539         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 540                 return;
 541
 542         port = buf[0] & 0xf;
 543
 544         /* no need to fix up packets coming from a tagged source */
 545         if (priv->vlan_tagged & (1 << port))
 546                 return;
 547
 548         /* lookup port vid from local table, the switch passes an invalid vlan id */
 549         vlan = priv->vlan_id[priv->pvid[port]];
 550
 551         buf[14 + 2] &= 0xf0;
 552         buf[14 + 2] |= vlan >> 8;
 553         buf[15 + 2] = vlan & 0xff;
 554 }
 555
 556 static int
 557 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
 558 {
 559         int timeout = 20;
 560         u32 t = 0;
 561
 562         while (1) {
 563                 t = priv->read(priv, reg);
 564                 if ((t & mask) == val)
 565                         return 0;
 566
 567                 if (timeout-- <= 0)
 568                         break;
 569
 570                 udelay(10);
 571         }
 572
 573         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 574                (unsigned int) reg, t, mask, val);
 575         return -ETIMEDOUT;
 576 }
 577
 578 static void
 579 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
 580 {
 581         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 582                 return;
 583         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 584                 val &= AR8216_VTUDATA_MEMBER;
 585                 val |= AR8216_VTUDATA_VALID;
 586                 priv->write(priv, AR8216_REG_VTU_DATA, val);
 587         }
 588         op |= AR8216_VTU_ACTIVE;
 589         priv->write(priv, AR8216_REG_VTU, op);
 590 }
 591
 592 static void
 593 ar8216_vtu_flush(struct ar8216_priv *priv)
 594 {
 595         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 596 }
 597
 598 static void
 599 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
 600 {
 601         u32 op;
 602
 603         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 604         ar8216_vtu_op(priv, op, port_mask);
 605 }
 606
 607 static int
 608 ar8216_atu_flush(struct ar8216_priv *priv)
 609 {
 610         int ret;
 611
 612         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 613         if (!ret)
 614                 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 615
 616         return ret;
 617 }
 618
 619 static u32
 620 ar8216_read_port_status(struct ar8216_priv *priv, int port)
 621 {
 622         return priv->read(priv, AR8216_REG_PORT_STATUS(port));
 623 }
 624
 625 static void
 626 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
 627                   u32 members, u32 pvid)
 628 {
 629         u32 header;
 630
 631         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 632                 header = AR8216_PORT_CTRL_HEADER;
 633         else
 634                 header = 0;
 635
 636         ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
 637                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 638                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 639                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 640                    AR8216_PORT_CTRL_LEARN | header |
 641                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 642                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 643
 644         ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
 645                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 646                    AR8216_PORT_VLAN_DEFAULT_ID,
 647                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 648                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 649                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 650 }
 651
 652 static int
 653 ar8216_hw_init(struct ar8216_priv *priv)
 654 {
 655         return 0;
 656 }
 657
 658 static void
 659 ar8216_init_globals(struct ar8216_priv *priv)
 660 {
 661         /* standard atheros magic */
 662         priv->write(priv, 0x38, 0xc000050e);
 663
 664         ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 665                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 666 }
 667
 668 static void
 669 ar8216_init_port(struct ar8216_priv *priv, int port)
 670 {
 671         /* Enable port learning and tx */
 672         priv->write(priv, AR8216_REG_PORT_CTRL(port),
 673                 AR8216_PORT_CTRL_LEARN |
 674                 (4 << AR8216_PORT_CTRL_STATE_S));
 675
 676         priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
 677
 678         if (port == AR8216_PORT_CPU) {
 679                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 680                         AR8216_PORT_STATUS_LINK_UP |
 681                         (ar8xxx_has_gige(priv) ?
 682                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 683                         AR8216_PORT_STATUS_TXMAC |
 684                         AR8216_PORT_STATUS_RXMAC |
 685                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 686                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 687                         AR8216_PORT_STATUS_DUPLEX);
 688         } else {
 689                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 690                         AR8216_PORT_STATUS_LINK_AUTO);
 691         }
 692 }
 693
 694 static const struct ar8xxx_chip ar8216_chip = {
 695         .caps = AR8XXX_CAP_MIB_COUNTERS,
 696
 697         .hw_init = ar8216_hw_init,
 698         .init_globals = ar8216_init_globals,
 699         .init_port = ar8216_init_port,
 700         .setup_port = ar8216_setup_port,
 701         .read_port_status = ar8216_read_port_status,
 702         .atu_flush = ar8216_atu_flush,
 703         .vtu_flush = ar8216_vtu_flush,
 704         .vtu_load_vlan = ar8216_vtu_load_vlan,
 705
 706         .num_mibs = ARRAY_SIZE(ar8216_mibs),
 707         .mib_decs = ar8216_mibs,
 708 };
 709
 710 static void
 711 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
 712                   u32 members, u32 pvid)
 713 {
 714         ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
 715                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 716                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 717                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 718                    AR8216_PORT_CTRL_LEARN |
 719                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 720                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 721
 722         ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
 723                    AR8236_PORT_VLAN_DEFAULT_ID,
 724                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 725
 726         ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 727                    AR8236_PORT_VLAN2_VLAN_MODE |
 728                    AR8236_PORT_VLAN2_MEMBER,
 729                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 730                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 731 }
 732
 733 static int
 734 ar8236_hw_init(struct ar8216_priv *priv)
 735 {
 736         int i;
 737         struct mii_bus *bus;
 738
 739         if (priv->initialized)
 740                 return 0;
 741
 742         /* Initialize the PHYs */
 743         bus = priv->mii_bus;
 744         for (i = 0; i < 5; i++) {
 745                 mdiobus_write(bus, i, MII_ADVERTISE,
 746                               ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
 747                               ADVERTISE_PAUSE_ASYM);
 748                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 749         }
 750         msleep(1000);
 751
 752         priv->initialized = true;
 753         return 0;
 754 }
 755
 756 static void
 757 ar8236_init_globals(struct ar8216_priv *priv)
 758 {
 759         /* enable jumbo frames */
 760         ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 761                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 762
 763         /* Enable MIB counters */
 764         ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 765                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 766                    AR8236_MIB_EN);
 767 }
 768
 769 static const struct ar8xxx_chip ar8236_chip = {
 770         .caps = AR8XXX_CAP_MIB_COUNTERS,
 771         .hw_init = ar8236_hw_init,
 772         .init_globals = ar8236_init_globals,
 773         .init_port = ar8216_init_port,
 774         .setup_port = ar8236_setup_port,
 775         .read_port_status = ar8216_read_port_status,
 776         .atu_flush = ar8216_atu_flush,
 777         .vtu_flush = ar8216_vtu_flush,
 778         .vtu_load_vlan = ar8216_vtu_load_vlan,
 779
 780         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 781         .mib_decs = ar8236_mibs,
 782 };
 783
 784 static int
 785 ar8316_hw_init(struct ar8216_priv *priv)
 786 {
 787         int i;
 788         u32 val, newval;
 789         struct mii_bus *bus;
 790
 791         val = priv->read(priv, 0x8);
 792
 793         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 794                 if (priv->port4_phy) {
 795                         /* value taken from Ubiquiti RouterStation Pro */
 796                         newval = 0x81461bea;
 797                         printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
 798                 } else {
 799                         newval = 0x01261be2;
 800                         printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
 801                 }
 802         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 803                 /* value taken from AVM Fritz!Box 7390 sources */
 804                 newval = 0x010e5b71;
 805         } else {
 806                 /* no known value for phy interface */
 807                 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
 808                         priv->phy->interface);
 809                 return -EINVAL;
 810         }
 811
 812         if (val == newval)
 813                 goto out;
 814
 815         priv->write(priv, 0x8, newval);
 816
 817         /* Initialize the ports */
 818         bus = priv->mii_bus;
 819         for (i = 0; i < 5; i++) {
 820                 if ((i == 4) && priv->port4_phy &&
 821                     priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 822                         /* work around for phy4 rgmii mode */
 823                         ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
 824                         /* rx delay */
 825                         ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
 826                         /* tx delay */
 827                         ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
 828                         msleep(1000);
 829                 }
 830
 831                 /* initialize the port itself */
 832                 mdiobus_write(bus, i, MII_ADVERTISE,
 833                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 834                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 835                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 836                 msleep(1000);
 837         }
 838
 839 out:
 840         priv->initialized = true;
 841         return 0;
 842 }
 843
 844 static void
 845 ar8316_init_globals(struct ar8216_priv *priv)
 846 {
 847         /* standard atheros magic */
 848         priv->write(priv, 0x38, 0xc000050e);
 849
 850         /* enable cpu port to receive multicast and broadcast frames */
 851         priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 852
 853         /* enable jumbo frames */
 854         ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 855                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 856
 857         /* Enable MIB counters */
 858         ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 859                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 860                    AR8236_MIB_EN);
 861 }
 862
 863 static const struct ar8xxx_chip ar8316_chip = {
 864         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
 865         .hw_init = ar8316_hw_init,
 866         .init_globals = ar8316_init_globals,
 867         .init_port = ar8216_init_port,
 868         .setup_port = ar8216_setup_port,
 869         .read_port_status = ar8216_read_port_status,
 870         .atu_flush = ar8216_atu_flush,
 871         .vtu_flush = ar8216_vtu_flush,
 872         .vtu_load_vlan = ar8216_vtu_load_vlan,
 873
 874         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 875         .mib_decs = ar8236_mibs,
 876 };
 877
 878 static u32
 879 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
 880 {
 881         u32 t;
 882
 883         if (!cfg)
 884                 return 0;
 885
 886         t = 0;
 887         switch (cfg->mode) {
 888         case AR8327_PAD_NC:
 889                 break;
 890
 891         case AR8327_PAD_MAC2MAC_MII:
 892                 t = AR8327_PAD_MAC_MII_EN;
 893                 if (cfg->rxclk_sel)
 894                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
 895                 if (cfg->txclk_sel)
 896                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
 897                 break;
 898
 899         case AR8327_PAD_MAC2MAC_GMII:
 900                 t = AR8327_PAD_MAC_GMII_EN;
 901                 if (cfg->rxclk_sel)
 902                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
 903                 if (cfg->txclk_sel)
 904                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
 905                 break;
 906
 907         case AR8327_PAD_MAC_SGMII:
 908                 t = AR8327_PAD_SGMII_EN;
 909
 910                 /*
 911                  * WAR for the QUalcomm Atheros AP136 board.
 912                  * It seems that RGMII TX/RX delay settings needs to be
 913                  * applied for SGMII mode as well, The ethernet is not
 914                  * reliable without this.
 915                  */
 916                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
 917                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
 918                 if (cfg->rxclk_delay_en)
 919                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
 920                 if (cfg->txclk_delay_en)
 921                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
 922
 923                 if (cfg->sgmii_delay_en)
 924                         t |= AR8327_PAD_SGMII_DELAY_EN;
 925
 926                 break;
 927
 928         case AR8327_PAD_MAC2PHY_MII:
 929                 t = AR8327_PAD_PHY_MII_EN;
 930                 if (cfg->rxclk_sel)
 931                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
 932                 if (cfg->txclk_sel)
 933                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
 934                 break;
 935
 936         case AR8327_PAD_MAC2PHY_GMII:
 937                 t = AR8327_PAD_PHY_GMII_EN;
 938                 if (cfg->pipe_rxclk_sel)
 939                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
 940                 if (cfg->rxclk_sel)
 941                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
 942                 if (cfg->txclk_sel)
 943                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
 944                 break;
 945
 946         case AR8327_PAD_MAC_RGMII:
 947                 t = AR8327_PAD_RGMII_EN;
 948                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
 949                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
 950                 if (cfg->rxclk_delay_en)
 951                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
 952                 if (cfg->txclk_delay_en)
 953                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
 954                 break;
 955
 956         case AR8327_PAD_PHY_GMII:
 957                 t = AR8327_PAD_PHYX_GMII_EN;
 958                 break;
 959
 960         case AR8327_PAD_PHY_RGMII:
 961                 t = AR8327_PAD_PHYX_RGMII_EN;
 962                 break;
 963
 964         case AR8327_PAD_PHY_MII:
 965                 t = AR8327_PAD_PHYX_MII_EN;
 966                 break;
 967         }
 968
 969         return t;
 970 }
 971
 972 static void
 973 ar8327_phy_fixup(struct ar8216_priv *priv, int phy)
 974 {
 975         switch (priv->chip_rev) {
 976         case 1:
 977                 /* For 100M waveform */
 978                 ar8216_phy_dbg_write(priv, phy, 0, 0x02ea);
 979                 /* Turn on Gigabit clock */
 980                 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
 981                 break;
 982
 983         case 2:
 984                 ar8216_phy_mmd_write(priv, phy, 0x7, 0x3c);
 985                 ar8216_phy_mmd_write(priv, phy, 0x4007, 0x0);
 986                 /* fallthrough */
 987         case 4:
 988                 ar8216_phy_mmd_write(priv, phy, 0x3, 0x800d);
 989                 ar8216_phy_mmd_write(priv, phy, 0x4003, 0x803f);
 990
 991                 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x6860);
 992                 ar8216_phy_dbg_write(priv, phy, 0x5, 0x2c46);
 993                 ar8216_phy_dbg_write(priv, phy, 0x3c, 0x6000);
 994                 break;
 995         }
 996 }
 997
 998 static int
 999 ar8327_hw_init(struct ar8216_priv *priv)
1000 {
1001         struct ar8327_platform_data *pdata;
1002         struct ar8327_led_cfg *led_cfg;
1003         struct mii_bus *bus;
1004         u32 pos, new_pos;
1005         u32 t;
1006         int i;
1007
1008         pdata = priv->phy->dev.platform_data;
1009         if (!pdata)
1010                 return -EINVAL;
1011
1012         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1013         priv->write(priv, AR8327_REG_PAD0_MODE, t);
1014         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1015         priv->write(priv, AR8327_REG_PAD5_MODE, t);
1016         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1017         priv->write(priv, AR8327_REG_PAD6_MODE, t);
1018
1019         pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1020         new_pos = pos;
1021
1022         led_cfg = pdata->led_cfg;
1023         if (led_cfg) {
1024                 if (led_cfg->open_drain)
1025                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1026                 else
1027                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1028
1029                 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1030                 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1031                 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1032                 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1033         }
1034
1035         if (new_pos != pos) {
1036                 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1037                 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1038         }
1039
1040         bus = priv->mii_bus;
1041         for (i = 0; i < AR8327_NUM_PHYS; i++) {
1042                 ar8327_phy_fixup(priv, i);
1043
1044                 /* start aneg on the PHY */
1045                 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1046                                                      ADVERTISE_PAUSE_CAP |
1047                                                      ADVERTISE_PAUSE_ASYM);
1048                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1049                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1050         }
1051
1052         msleep(1000);
1053
1054         return 0;
1055 }
1056
1057 static void
1058 ar8327_init_globals(struct ar8216_priv *priv)
1059 {
1060         u32 t;
1061
1062         /* enable CPU port and disable mirror port */
1063         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1064             AR8327_FWD_CTRL0_MIRROR_PORT;
1065         priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1066
1067         /* forward multicast and broadcast frames to CPU */
1068         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1069             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1070             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1071         priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1072
1073         /* setup MTU */
1074         ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1075                    AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1076
1077         /* Enable MIB counters */
1078         ar8216_reg_set(priv, AR8327_REG_MODULE_EN,
1079                        AR8327_MODULE_EN_MIB);
1080 }
1081
1082 static void
1083 ar8327_config_port(struct ar8216_priv *priv, unsigned int port,
1084                     struct ar8327_port_cfg *cfg)
1085 {
1086         u32 t;
1087
1088         if (!cfg || !cfg->force_link) {
1089                 priv->write(priv, AR8327_REG_PORT_STATUS(port),
1090                             AR8216_PORT_STATUS_LINK_AUTO);
1091                 return;
1092         }
1093
1094         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1095         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1096         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1097         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1098
1099         switch (cfg->speed) {
1100         case AR8327_PORT_SPEED_10:
1101                 t |= AR8216_PORT_SPEED_10M;
1102                 break;
1103         case AR8327_PORT_SPEED_100:
1104                 t |= AR8216_PORT_SPEED_100M;
1105                 break;
1106         case AR8327_PORT_SPEED_1000:
1107                 t |= AR8216_PORT_SPEED_1000M;
1108                 break;
1109         }
1110
1111         priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1112 }
1113
1114 static void
1115 ar8327_init_port(struct ar8216_priv *priv, int port)
1116 {
1117         struct ar8327_platform_data *pdata;
1118         struct ar8327_port_cfg *cfg;
1119         u32 t;
1120
1121         pdata = priv->phy->dev.platform_data;
1122
1123         if (pdata && port == AR8216_PORT_CPU)
1124                 cfg = &pdata->port0_cfg;
1125         else if (pdata && port == 6)
1126                 cfg = &pdata->port6_cfg;
1127         else
1128                 cfg = NULL;
1129
1130         ar8327_config_port(priv, port, cfg);
1131
1132         priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1133
1134         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1135         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1136         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1137
1138         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1139         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1140
1141         t = AR8327_PORT_LOOKUP_LEARN;
1142         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1143         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1144 }
1145
1146 static u32
1147 ar8327_read_port_status(struct ar8216_priv *priv, int port)
1148 {
1149         return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1150 }
1151
1152 static int
1153 ar8327_atu_flush(struct ar8216_priv *priv)
1154 {
1155         int ret;
1156
1157         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1158                               AR8327_ATU_FUNC_BUSY, 0);
1159         if (!ret)
1160                 priv->write(priv, AR8327_REG_ATU_FUNC,
1161                             AR8327_ATU_FUNC_OP_FLUSH);
1162
1163         return ret;
1164 }
1165
1166 static void
1167 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
1168 {
1169         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1170                             AR8327_VTU_FUNC1_BUSY, 0))
1171                 return;
1172
1173         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1174                 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1175
1176         op |= AR8327_VTU_FUNC1_BUSY;
1177         priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1178 }
1179
1180 static void
1181 ar8327_vtu_flush(struct ar8216_priv *priv)
1182 {
1183         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1184 }
1185
1186 static void
1187 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
1188 {
1189         u32 op;
1190         u32 val;
1191         int i;
1192
1193         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1194         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1195         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1196                 u32 mode;
1197
1198                 if ((port_mask & BIT(i)) == 0)
1199                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1200                 else if (priv->vlan == 0)
1201                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1202                 else if (priv->vlan_tagged & BIT(i))
1203                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1204                 else
1205                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1206
1207                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1208         }
1209         ar8327_vtu_op(priv, op, val);
1210 }
1211
1212 static void
1213 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
1214                   u32 members, u32 pvid)
1215 {
1216         u32 t;
1217         u32 mode;
1218
1219         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1220         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1221         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1222
1223         mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1224         switch (egress) {
1225         case AR8216_OUT_KEEP:
1226                 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1227                 break;
1228         case AR8216_OUT_STRIP_VLAN:
1229                 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1230                 break;
1231         case AR8216_OUT_ADD_VLAN:
1232                 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1233                 break;
1234         }
1235
1236         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1237         t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1238         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1239
1240         t = members;
1241         t |= AR8327_PORT_LOOKUP_LEARN;
1242         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1243         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1244         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1245 }
1246
1247 static const struct ar8xxx_chip ar8327_chip = {
1248         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1249         .hw_init = ar8327_hw_init,
1250         .init_globals = ar8327_init_globals,
1251         .init_port = ar8327_init_port,
1252         .setup_port = ar8327_setup_port,
1253         .read_port_status = ar8327_read_port_status,
1254         .atu_flush = ar8327_atu_flush,
1255         .vtu_flush = ar8327_vtu_flush,
1256         .vtu_load_vlan = ar8327_vtu_load_vlan,
1257
1258         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1259         .mib_decs = ar8236_mibs,
1260 };
1261
1262 static int
1263 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1264                    struct switch_val *val)
1265 {
1266         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1267         priv->vlan = !!val->value.i;
1268         return 0;
1269 }
1270
1271 static int
1272 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1273                    struct switch_val *val)
1274 {
1275         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1276         val->value.i = priv->vlan;
1277         return 0;
1278 }
1279
1280
1281 static int
1282 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1283 {
1284         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1285
1286         /* make sure no invalid PVIDs get set */
1287
1288         if (vlan >= dev->vlans)
1289                 return -EINVAL;
1290
1291         priv->pvid[port] = vlan;
1292         return 0;
1293 }
1294
1295 static int
1296 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1297 {
1298         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1299         *vlan = priv->pvid[port];
1300         return 0;
1301 }
1302
1303 static int
1304 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1305                   struct switch_val *val)
1306 {
1307         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1308         priv->vlan_id[val->port_vlan] = val->value.i;
1309         return 0;
1310 }
1311
1312 static int
1313 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1314                   struct switch_val *val)
1315 {
1316         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1317         val->value.i = priv->vlan_id[val->port_vlan];
1318         return 0;
1319 }
1320
1321 static int
1322 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
1323                         struct switch_port_link *link)
1324 {
1325         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1326
1327         ar8216_read_port_link(priv, port, link);
1328         return 0;
1329 }
1330
1331 static int
1332 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1333 {
1334         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1335         u8 ports = priv->vlan_table[val->port_vlan];
1336         int i;
1337
1338         val->len = 0;
1339         for (i = 0; i < dev->ports; i++) {
1340                 struct switch_port *p;
1341
1342                 if (!(ports & (1 << i)))
1343                         continue;
1344
1345                 p = &val->value.ports[val->len++];
1346                 p->id = i;
1347                 if (priv->vlan_tagged & (1 << i))
1348                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1349                 else
1350                         p->flags = 0;
1351         }
1352         return 0;
1353 }
1354
1355 static int
1356 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1357 {
1358         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1359         u8 *vt = &priv->vlan_table[val->port_vlan];
1360         int i, j;
1361
1362         *vt = 0;
1363         for (i = 0; i < val->len; i++) {
1364                 struct switch_port *p = &val->value.ports[i];
1365
1366                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1367                         priv->vlan_tagged |= (1 << p->id);
1368                 } else {
1369                         priv->vlan_tagged &= ~(1 << p->id);
1370                         priv->pvid[p->id] = val->port_vlan;
1371
1372                         /* make sure that an untagged port does not
1373                          * appear in other vlans */
1374                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1375                                 if (j == val->port_vlan)
1376                                         continue;
1377                                 priv->vlan_table[j] &= ~(1 << p->id);
1378                         }
1379                 }
1380
1381                 *vt |= 1 << p->id;
1382         }
1383         return 0;
1384 }
1385
1386 static int
1387 ar8216_sw_hw_apply(struct switch_dev *dev)
1388 {
1389         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1390         u8 portmask[AR8X16_MAX_PORTS];
1391         int i, j;
1392
1393         mutex_lock(&priv->reg_mutex);
1394         /* flush all vlan translation unit entries */
1395         priv->chip->vtu_flush(priv);
1396
1397         memset(portmask, 0, sizeof(portmask));
1398         if (!priv->init) {
1399                 /* calculate the port destination masks and load vlans
1400                  * into the vlan translation unit */
1401                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1402                         u8 vp = priv->vlan_table[j];
1403
1404                         if (!vp)
1405                                 continue;
1406
1407                         for (i = 0; i < dev->ports; i++) {
1408                                 u8 mask = (1 << i);
1409                                 if (vp & mask)
1410                                         portmask[i] |= vp & ~mask;
1411                         }
1412
1413                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1414                                                  priv->vlan_table[j]);
1415                 }
1416         } else {
1417                 /* vlan disabled:
1418                  * isolate all ports, but connect them to the cpu port */
1419                 for (i = 0; i < dev->ports; i++) {
1420                         if (i == AR8216_PORT_CPU)
1421                                 continue;
1422
1423                         portmask[i] = 1 << AR8216_PORT_CPU;
1424                         portmask[AR8216_PORT_CPU] |= (1 << i);
1425                 }
1426         }
1427
1428         /* update the port destination mask registers and tag settings */
1429         for (i = 0; i < dev->ports; i++) {
1430                 int egress, ingress;
1431                 int pvid;
1432
1433                 if (priv->vlan) {
1434                         pvid = priv->vlan_id[priv->pvid[i]];
1435                         if (priv->vlan_tagged & (1 << i))
1436                                 egress = AR8216_OUT_ADD_VLAN;
1437                         else
1438                                 egress = AR8216_OUT_STRIP_VLAN;
1439                         ingress = AR8216_IN_SECURE;
1440                 } else {
1441                         pvid = i;
1442                         egress = AR8216_OUT_KEEP;
1443                         ingress = AR8216_IN_PORT_ONLY;
1444                 }
1445
1446                 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1447                                        pvid);
1448         }
1449         mutex_unlock(&priv->reg_mutex);
1450         return 0;
1451 }
1452
1453 static int
1454 ar8216_sw_reset_switch(struct switch_dev *dev)
1455 {
1456         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1457         int i;
1458
1459         mutex_lock(&priv->reg_mutex);
1460         memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1461                 offsetof(struct ar8216_priv, vlan));
1462
1463         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1464                 priv->vlan_id[i] = i;
1465
1466         /* Configure all ports */
1467         for (i = 0; i < dev->ports; i++)
1468                 priv->chip->init_port(priv, i);
1469
1470         priv->chip->init_globals(priv);
1471         mutex_unlock(&priv->reg_mutex);
1472
1473         return ar8216_sw_hw_apply(dev);
1474 }
1475
1476 static int
1477 ar8216_sw_set_reset_mibs(struct switch_dev *dev,
1478                          const struct switch_attr *attr,
1479                          struct switch_val *val)
1480 {
1481         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1482         unsigned int len;
1483         int ret;
1484
1485         if (!ar8xxx_has_mib_counters(priv))
1486                 return -EOPNOTSUPP;
1487
1488         mutex_lock(&priv->mib_lock);
1489
1490         len = priv->dev.ports * priv->chip->num_mibs *
1491               sizeof(*priv->mib_stats);
1492         memset(priv->mib_stats, '\0', len);
1493         ret = ar8216_mib_flush(priv);
1494         if (ret)
1495                 goto unlock;
1496
1497         ret = 0;
1498
1499 unlock:
1500         mutex_unlock(&priv->mib_lock);
1501         return ret;
1502 }
1503
1504 static int
1505 ar8216_sw_set_port_reset_mib(struct switch_dev *dev,
1506                              const struct switch_attr *attr,
1507                              struct switch_val *val)
1508 {
1509         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1510         int port;
1511         int ret;
1512
1513         if (!ar8xxx_has_mib_counters(priv))
1514                 return -EOPNOTSUPP;
1515
1516         port = val->port_vlan;
1517         if (port >= dev->ports)
1518                 return -EINVAL;
1519
1520         mutex_lock(&priv->mib_lock);
1521         ret = ar8216_mib_capture(priv);
1522         if (ret)
1523                 goto unlock;
1524
1525         ar8216_mib_fetch_port_stat(priv, port, true);
1526
1527         ret = 0;
1528
1529 unlock:
1530         mutex_unlock(&priv->mib_lock);
1531         return ret;
1532 }
1533
1534 static int
1535 ar8216_sw_get_port_mib(struct switch_dev *dev,
1536                        const struct switch_attr *attr,
1537                        struct switch_val *val)
1538 {
1539         struct ar8216_priv *priv = swdev_to_ar8216(dev);
1540         const struct ar8xxx_chip *chip = priv->chip;
1541         u64 *mib_stats;
1542         int port;
1543         int ret;
1544         char *buf = priv->buf;
1545         int i, len = 0;
1546
1547         if (!ar8xxx_has_mib_counters(priv))
1548                 return -EOPNOTSUPP;
1549
1550         port = val->port_vlan;
1551         if (port >= dev->ports)
1552                 return -EINVAL;
1553
1554         mutex_lock(&priv->mib_lock);
1555         ret = ar8216_mib_capture(priv);
1556         if (ret)
1557                 goto unlock;
1558
1559         ar8216_mib_fetch_port_stat(priv, port, false);
1560
1561         len += snprintf(buf + len, sizeof(priv->buf) - len,
1562                         "Port %d MIB counters\n",
1563                         port);
1564
1565         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1566         for (i = 0; i < chip->num_mibs; i++)
1567                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1568                                 "%-12s: %llu\n",
1569                                 chip->mib_decs[i].name,
1570                                 mib_stats[i]);
1571
1572         val->value.s = buf;
1573         val->len = len;
1574
1575         ret = 0;
1576
1577 unlock:
1578         mutex_unlock(&priv->mib_lock);
1579         return ret;
1580 }
1581
1582 static struct switch_attr ar8216_globals[] = {
1583         {
1584                 .type = SWITCH_TYPE_INT,
1585                 .name = "enable_vlan",
1586                 .description = "Enable VLAN mode",
1587                 .set = ar8216_sw_set_vlan,
1588                 .get = ar8216_sw_get_vlan,
1589                 .max = 1
1590         },
1591         {
1592                 .type = SWITCH_TYPE_NOVAL,
1593                 .name = "reset_mibs",
1594                 .description = "Reset all MIB counters",
1595                 .set = ar8216_sw_set_reset_mibs,
1596         },
1597
1598 };
1599
1600 static struct switch_attr ar8216_port[] = {
1601         {
1602                 .type = SWITCH_TYPE_NOVAL,
1603                 .name = "reset_mib",
1604                 .description = "Reset single port MIB counters",
1605                 .set = ar8216_sw_set_port_reset_mib,
1606         },
1607         {
1608                 .type = SWITCH_TYPE_STRING,
1609                 .name = "mib",
1610                 .description = "Get port's MIB counters",
1611                 .set = NULL,
1612                 .get = ar8216_sw_get_port_mib,
1613         },
1614 };
1615
1616 static struct switch_attr ar8216_vlan[] = {
1617         {
1618                 .type = SWITCH_TYPE_INT,
1619                 .name = "vid",
1620                 .description = "VLAN ID (0-4094)",
1621                 .set = ar8216_sw_set_vid,
1622                 .get = ar8216_sw_get_vid,
1623                 .max = 4094,
1624         },
1625 };
1626
1627 static const struct switch_dev_ops ar8216_sw_ops = {
1628         .attr_global = {
1629                 .attr = ar8216_globals,
1630                 .n_attr = ARRAY_SIZE(ar8216_globals),
1631         },
1632         .attr_port = {
1633                 .attr = ar8216_port,
1634                 .n_attr = ARRAY_SIZE(ar8216_port),
1635         },
1636         .attr_vlan = {
1637                 .attr = ar8216_vlan,
1638                 .n_attr = ARRAY_SIZE(ar8216_vlan),
1639         },
1640         .get_port_pvid = ar8216_sw_get_pvid,
1641         .set_port_pvid = ar8216_sw_set_pvid,
1642         .get_vlan_ports = ar8216_sw_get_ports,
1643         .set_vlan_ports = ar8216_sw_set_ports,
1644         .apply_config = ar8216_sw_hw_apply,
1645         .reset_switch = ar8216_sw_reset_switch,
1646         .get_port_link = ar8216_sw_get_port_link,
1647 };
1648
1649 static int
1650 ar8216_id_chip(struct ar8216_priv *priv)
1651 {
1652         u32 val;
1653         u16 id;
1654         int i;
1655
1656         val = priv->read(priv, AR8216_REG_CTRL);
1657         if (val == ~0)
1658                 return -ENODEV;
1659
1660         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1661         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1662                 u16 t;
1663
1664                 val = priv->read(priv, AR8216_REG_CTRL);
1665                 if (val == ~0)
1666                         return -ENODEV;
1667
1668                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1669                 if (t != id)
1670                         return -ENODEV;
1671         }
1672
1673         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1674         priv->chip_rev = (id & AR8216_CTRL_REVISION);
1675
1676         switch (priv->chip_ver) {
1677         case AR8XXX_VER_AR8216:
1678                 priv->chip = &ar8216_chip;
1679                 break;
1680         case AR8XXX_VER_AR8236:
1681                 priv->chip = &ar8236_chip;
1682                 break;
1683         case AR8XXX_VER_AR8316:
1684                 priv->chip = &ar8316_chip;
1685                 break;
1686         case AR8XXX_VER_AR8327:
1687                 priv->mii_lo_first = true;
1688                 priv->chip = &ar8327_chip;
1689                 break;
1690         default:
1691                 printk(KERN_DEBUG
1692                         "ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1693                         priv->chip_ver, priv->chip_rev);
1694
1695                 return -ENODEV;
1696         }
1697
1698         return 0;
1699 }
1700
1701 static void
1702 ar8xxx_mib_work_func(struct work_struct *work)
1703 {
1704         struct ar8216_priv *priv;
1705         int err;
1706
1707         priv = container_of(work, struct ar8216_priv, mib_work.work);
1708
1709         mutex_lock(&priv->mib_lock);
1710
1711         err = ar8216_mib_capture(priv);
1712         if (err)
1713                 goto next_port;
1714
1715         ar8216_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1716
1717 next_port:
1718         priv->mib_next_port++;
1719         if (priv->mib_next_port >= priv->dev.ports)
1720                 priv->mib_next_port = 0;
1721
1722         mutex_unlock(&priv->mib_lock);
1723         schedule_delayed_work(&priv->mib_work,
1724                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1725 }
1726
1727 static int
1728 ar8xxx_mib_init(struct ar8216_priv *priv)
1729 {
1730         unsigned int len;
1731
1732         if (!ar8xxx_has_mib_counters(priv))
1733                 return 0;
1734
1735         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1736
1737         len = priv->dev.ports * priv->chip->num_mibs *
1738               sizeof(*priv->mib_stats);
1739         priv->mib_stats = kzalloc(len, GFP_KERNEL);
1740
1741         if (!priv->mib_stats)
1742                 return -ENOMEM;
1743
1744         mutex_init(&priv->mib_lock);
1745         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1746
1747         return 0;
1748 }
1749
1750 static void
1751 ar8xxx_mib_start(struct ar8216_priv *priv)
1752 {
1753         if (!ar8xxx_has_mib_counters(priv))
1754                 return;
1755
1756         schedule_delayed_work(&priv->mib_work,
1757                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1758 }
1759
1760 static void
1761 ar8xxx_mib_cleanup(struct ar8216_priv *priv)
1762 {
1763         if (!ar8xxx_has_mib_counters(priv))
1764                 return;
1765
1766         cancel_delayed_work(&priv->mib_work);
1767         kfree(priv->mib_stats);
1768 }
1769
1770 static int
1771 ar8216_config_init(struct phy_device *pdev)
1772 {
1773         struct ar8216_priv *priv = pdev->priv;
1774         struct net_device *dev = pdev->attached_dev;
1775         struct switch_dev *swdev;
1776         int ret;
1777
1778         if (!priv) {
1779                 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1780                 if (priv == NULL)
1781                         return -ENOMEM;
1782         }
1783
1784         priv->mii_bus = pdev->bus;
1785         priv->read = ar8216_mii_read;
1786         priv->write = ar8216_mii_write;
1787
1788         priv->phy = pdev;
1789
1790         ret = ar8216_id_chip(priv);
1791         if (ret)
1792                 goto err_free_priv;
1793
1794         if (pdev->addr != 0) {
1795                 if (ar8xxx_has_gige(priv)) {
1796                         pdev->supported |= SUPPORTED_1000baseT_Full;
1797                         pdev->advertising |= ADVERTISED_1000baseT_Full;
1798                 }
1799
1800                 if (chip_is_ar8316(priv)) {
1801                         /* check if we're attaching to the switch twice */
1802                         pdev = pdev->bus->phy_map[0];
1803                         if (!pdev) {
1804                                 kfree(priv);
1805                                 return 0;
1806                         }
1807
1808                         /* switch device has not been initialized, reuse priv */
1809                         if (!pdev->priv) {
1810                                 priv->port4_phy = true;
1811                                 pdev->priv = priv;
1812                                 return 0;
1813                         }
1814
1815                         kfree(priv);
1816
1817                         /* switch device has been initialized, reinit */
1818                         priv = pdev->priv;
1819                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
1820                         priv->initialized = false;
1821                         priv->port4_phy = true;
1822                         ar8316_hw_init(priv);
1823                         return 0;
1824                 }
1825
1826                 kfree(priv);
1827                 return 0;
1828         }
1829
1830         if (ar8xxx_has_gige(priv))
1831                 pdev->supported = SUPPORTED_1000baseT_Full;
1832         else
1833                 pdev->supported = SUPPORTED_100baseT_Full;
1834         pdev->advertising = pdev->supported;
1835
1836         mutex_init(&priv->reg_mutex);
1837
1838         pdev->priv = priv;
1839
1840         swdev = &priv->dev;
1841         swdev->cpu_port = AR8216_PORT_CPU;
1842         swdev->ops = &ar8216_sw_ops;
1843         swdev->ports = AR8216_NUM_PORTS;
1844
1845         if (chip_is_ar8316(priv)) {
1846                 swdev->name = "Atheros AR8316";
1847                 swdev->vlans = AR8X16_MAX_VLANS;
1848
1849                 if (priv->port4_phy) {
1850                         /* port 5 connected to the other mac, therefore unusable */
1851                         swdev->ports = (AR8216_NUM_PORTS - 1);
1852                 }
1853         } else if (chip_is_ar8236(priv)) {
1854                 swdev->name = "Atheros AR8236";
1855                 swdev->vlans = AR8216_NUM_VLANS;
1856                 swdev->ports = AR8216_NUM_PORTS;
1857         } else if (chip_is_ar8327(priv)) {
1858                 swdev->name = "Atheros AR8327";
1859                 swdev->vlans = AR8X16_MAX_VLANS;
1860                 swdev->ports = AR8327_NUM_PORTS;
1861         } else {
1862                 swdev->name = "Atheros AR8216";
1863                 swdev->vlans = AR8216_NUM_VLANS;
1864         }
1865
1866         ret = ar8xxx_mib_init(priv);
1867         if (ret)
1868                 goto err_free_priv;
1869
1870         ret = register_switch(swdev, pdev->attached_dev);
1871         if (ret)
1872                 goto err_cleanup_mib;
1873
1874         printk(KERN_INFO "%s: %s switch driver attached.\n",
1875                 pdev->attached_dev->name, swdev->name);
1876
1877         priv->init = true;
1878
1879         ret = priv->chip->hw_init(priv);
1880         if (ret)
1881                 goto err_unregister_switch;
1882
1883         ret = ar8216_sw_reset_switch(&priv->dev);
1884         if (ret)
1885                 goto err_unregister_switch;
1886
1887         dev->phy_ptr = priv;
1888
1889         /* VID fixup only needed on ar8216 */
1890         if (chip_is_ar8216(priv) && pdev->addr == 0) {
1891                 dev->priv_flags |= IFF_NO_IP_ALIGN;
1892                 dev->eth_mangle_rx = ar8216_mangle_rx;
1893                 dev->eth_mangle_tx = ar8216_mangle_tx;
1894         }
1895
1896         priv->init = false;
1897
1898         ar8xxx_mib_start(priv);
1899
1900         return 0;
1901
1902 err_unregister_switch:
1903         unregister_switch(&priv->dev);
1904 err_cleanup_mib:
1905         ar8xxx_mib_cleanup(priv);
1906 err_free_priv:
1907         kfree(priv);
1908         pdev->priv = NULL;
1909         return ret;
1910 }
1911
1912 static int
1913 ar8216_read_status(struct phy_device *phydev)
1914 {
1915         struct ar8216_priv *priv = phydev->priv;
1916         struct switch_port_link link;
1917         int ret;
1918
1919         if (phydev->addr != 0)
1920                 return genphy_read_status(phydev);
1921
1922         ar8216_read_port_link(priv, phydev->addr, &link);
1923         phydev->link = !!link.link;
1924         if (!phydev->link)
1925                 return 0;
1926
1927         switch (link.speed) {
1928         case SWITCH_PORT_SPEED_10:
1929                 phydev->speed = SPEED_10;
1930                 break;
1931         case SWITCH_PORT_SPEED_100:
1932                 phydev->speed = SPEED_100;
1933                 break;
1934         case SWITCH_PORT_SPEED_1000:
1935                 phydev->speed = SPEED_1000;
1936                 break;
1937         default:
1938                 phydev->speed = 0;
1939         }
1940         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1941
1942         /* flush the address translation unit */
1943         mutex_lock(&priv->reg_mutex);
1944         ret = priv->chip->atu_flush(priv);
1945         mutex_unlock(&priv->reg_mutex);
1946
1947         phydev->state = PHY_RUNNING;
1948         netif_carrier_on(phydev->attached_dev);
1949         phydev->adjust_link(phydev->attached_dev);
1950
1951         return ret;
1952 }
1953
1954 static int
1955 ar8216_config_aneg(struct phy_device *phydev)
1956 {
1957         if (phydev->addr == 0)
1958                 return 0;
1959
1960         return genphy_config_aneg(phydev);
1961 }
1962
1963 static int
1964 ar8216_probe(struct phy_device *pdev)
1965 {
1966         struct ar8216_priv *priv;
1967         int ret;
1968
1969         priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1970         if (priv == NULL)
1971                 return -ENOMEM;
1972
1973         priv->mii_bus = pdev->bus;
1974         priv->read = ar8216_mii_read;
1975         priv->write = ar8216_mii_write;
1976         priv->phy = pdev;
1977
1978         ret = ar8216_id_chip(priv);
1979         kfree(priv);
1980
1981         return ret;
1982 }
1983
1984 static void
1985 ar8216_detach(struct phy_device *pdev)
1986 {
1987         struct net_device *dev = pdev->attached_dev;
1988
1989         if (!dev)
1990                 return;
1991
1992         dev->phy_ptr = NULL;
1993         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1994         dev->eth_mangle_rx = NULL;
1995         dev->eth_mangle_tx = NULL;
1996 }
1997
1998 static void
1999 ar8216_remove(struct phy_device *pdev)
2000 {
2001         struct ar8216_priv *priv = pdev->priv;
2002
2003         if (!priv)
2004                 return;
2005
2006         pdev->priv = NULL;
2007
2008         if (pdev->addr == 0)
2009                 unregister_switch(&priv->dev);
2010
2011         ar8xxx_mib_cleanup(priv);
2012         kfree(priv);
2013 }
2014
2015 static struct phy_driver ar8216_driver = {
2016         .phy_id         = 0x004d0000,
2017         .name           = "Atheros AR8216/AR8236/AR8316",
2018         .phy_id_mask    = 0xffff0000,
2019         .features       = PHY_BASIC_FEATURES,
2020         .probe          = ar8216_probe,
2021         .remove         = ar8216_remove,
2022         .detach         = ar8216_detach,
2023         .config_init    = &ar8216_config_init,
2024         .config_aneg    = &ar8216_config_aneg,
2025         .read_status    = &ar8216_read_status,
2026         .driver         = { .owner = THIS_MODULE },
2027 };
2028
2029 int __init
2030 ar8216_init(void)
2031 {
2032         return phy_driver_register(&ar8216_driver);
2033 }
2034
2035 void __exit
2036 ar8216_exit(void)
2037 {
2038         phy_driver_unregister(&ar8216_driver);
2039 }
2040
2041 module_init(ar8216_init);
2042 module_exit(ar8216_exit);
2043 MODULE_LICENSE("GPL");
2044