target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include "ar8216.h"
  37
  38 /* size of the vlan table */
  39 #define AR8X16_MAX_VLANS        128
  40 #define AR8X16_PROBE_RETRIES    10
  41 #define AR8X16_MAX_PORTS        8
  42
  43 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  44
  45 struct ar8216_priv;
  46
  47 #define AR8XXX_CAP_GIGE                 BIT(0)
  48 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  49
  50 enum {
  51         AR8XXX_VER_AR8216 = 0x01,
  52         AR8XXX_VER_AR8236 = 0x03,
  53         AR8XXX_VER_AR8316 = 0x10,
  54         AR8XXX_VER_AR8327 = 0x12,
  55 };
  56
  57 struct ar8xxx_mib_desc {
  58         unsigned int size;
  59         unsigned int offset;
  60         const char *name;
  61 };
  62
  63 struct ar8xxx_chip {
  64         unsigned long caps;
  65
  66         int (*hw_init)(struct ar8216_priv *priv);
  67         void (*init_globals)(struct ar8216_priv *priv);
  68         void (*init_port)(struct ar8216_priv *priv, int port);
  69         void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
  70                            u32 ingress, u32 members, u32 pvid);
  71         u32 (*read_port_status)(struct ar8216_priv *priv, int port);
  72         int (*atu_flush)(struct ar8216_priv *priv);
  73         void (*vtu_flush)(struct ar8216_priv *priv);
  74         void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
  75
  76         const struct ar8xxx_mib_desc *mib_decs;
  77         unsigned num_mibs;
  78 };
  79
  80 struct ar8216_priv {
  81         struct switch_dev dev;
  82         struct phy_device *phy;
  83         u32 (*read)(struct ar8216_priv *priv, int reg);
  84         void (*write)(struct ar8216_priv *priv, int reg, u32 val);
  85         const struct net_device_ops *ndo_old;
  86         struct net_device_ops ndo;
  87         struct mutex reg_mutex;
  88         u8 chip_ver;
  89         u8 chip_rev;
  90         const struct ar8xxx_chip *chip;
  91         bool initialized;
  92         bool port4_phy;
  93         char buf[2048];
  94
  95         bool init;
  96         bool mii_lo_first;
  97
  98         struct mutex mib_lock;
  99         struct delayed_work mib_work;
 100         int mib_next_port;
 101         u64 *mib_stats;
 102
 103         /* all fields below are cleared on reset */
 104         bool vlan;
 105         u16 vlan_id[AR8X16_MAX_VLANS];
 106         u8 vlan_table[AR8X16_MAX_VLANS];
 107         u8 vlan_tagged;
 108         u16 pvid[AR8X16_MAX_PORTS];
 109 };
 110
 111 #define MIB_DESC(_s , _o, _n)   \
 112         {                       \
 113                 .size = (_s),   \
 114                 .offset = (_o), \
 115                 .name = (_n),   \
 116         }
 117
 118 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 119         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 120         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 121         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 122         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 123         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 124         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 125         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 126         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 127         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 128         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 129         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 130         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 131         MIB_DESC(1, AR8216_STATS_RX1518BYTE, "Rx1518Byte"),
 132         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 133         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 134         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 135         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 136         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 137         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 138         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 139         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 140         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 141         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 142         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 143         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 144         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 145         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 146         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 147         MIB_DESC(1, AR8216_STATS_TX1518BYTE, "Tx1518Byte"),
 148         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 149         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 150         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 151         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 152         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 153         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 154         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 155         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 156         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 157         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 158 };
 159
 160 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
 161
 162 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
 163 {
 164         return priv->chip->caps & AR8XXX_CAP_GIGE;
 165 }
 166
 167 static inline bool ar8xxx_has_mib_counters(struct ar8216_priv *priv)
 168 {
 169         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 170 }
 171
 172 static inline bool chip_is_ar8216(struct ar8216_priv *priv)
 173 {
 174         return priv->chip_ver == AR8XXX_VER_AR8216;
 175 }
 176
 177 static inline bool chip_is_ar8236(struct ar8216_priv *priv)
 178 {
 179         return priv->chip_ver == AR8XXX_VER_AR8236;
 180 }
 181
 182 static inline bool chip_is_ar8316(struct ar8216_priv *priv)
 183 {
 184         return priv->chip_ver == AR8XXX_VER_AR8316;
 185 }
 186
 187 static inline bool chip_is_ar8327(struct ar8216_priv *priv)
 188 {
 189         return priv->chip_ver == AR8XXX_VER_AR8327;
 190 }
 191
 192 static inline void
 193 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 194 {
 195         regaddr >>= 1;
 196         *r1 = regaddr & 0x1e;
 197
 198         regaddr >>= 5;
 199         *r2 = regaddr & 0x7;
 200
 201         regaddr >>= 3;
 202         *page = regaddr & 0x1ff;
 203 }
 204
 205 static u32
 206 ar8216_mii_read(struct ar8216_priv *priv, int reg)
 207 {
 208         struct phy_device *phy = priv->phy;
 209         struct mii_bus *bus = phy->bus;
 210         u16 r1, r2, page;
 211         u16 lo, hi;
 212
 213         split_addr((u32) reg, &r1, &r2, &page);
 214
 215         mutex_lock(&bus->mdio_lock);
 216
 217         bus->write(bus, 0x18, 0, page);
 218         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 219         lo = bus->read(bus, 0x10 | r2, r1);
 220         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 221
 222         mutex_unlock(&bus->mdio_lock);
 223
 224         return (hi << 16) | lo;
 225 }
 226
 227 static void
 228 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
 229 {
 230         struct phy_device *phy = priv->phy;
 231         struct mii_bus *bus = phy->bus;
 232         u16 r1, r2, r3;
 233         u16 lo, hi;
 234
 235         split_addr((u32) reg, &r1, &r2, &r3);
 236         lo = val & 0xffff;
 237         hi = (u16) (val >> 16);
 238
 239         mutex_lock(&bus->mdio_lock);
 240
 241         bus->write(bus, 0x18, 0, r3);
 242         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 243         if (priv->mii_lo_first) {
 244                 bus->write(bus, 0x10 | r2, r1, lo);
 245                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 246         } else {
 247                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 248                 bus->write(bus, 0x10 | r2, r1, lo);
 249         }
 250
 251         mutex_unlock(&bus->mdio_lock);
 252 }
 253
 254 static void
 255 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
 256                      u16 dbg_addr, u16 dbg_data)
 257 {
 258         struct mii_bus *bus = priv->phy->bus;
 259
 260         mutex_lock(&bus->mdio_lock);
 261         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 262         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 263         mutex_unlock(&bus->mdio_lock);
 264 }
 265
 266 static void
 267 ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
 268 {
 269         struct mii_bus *bus = priv->phy->bus;
 270
 271         mutex_lock(&bus->mdio_lock);
 272         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 273         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 274         mutex_unlock(&bus->mdio_lock);
 275 }
 276
 277 static u32
 278 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
 279 {
 280         u32 v;
 281
 282         lockdep_assert_held(&priv->reg_mutex);
 283
 284         v = priv->read(priv, reg);
 285         v &= ~mask;
 286         v |= val;
 287         priv->write(priv, reg, v);
 288
 289         return v;
 290 }
 291
 292 static inline void
 293 ar8216_reg_set(struct ar8216_priv *priv, int reg, u32 val)
 294 {
 295         u32 v;
 296
 297         lockdep_assert_held(&priv->reg_mutex);
 298
 299         v = priv->read(priv, reg);
 300         v |= val;
 301         priv->write(priv, reg, v);
 302 }
 303
 304 static int
 305 ar8216_reg_wait(struct ar8216_priv *priv, u32 reg, u32 mask, u32 val,
 306                 unsigned timeout)
 307 {
 308         int i;
 309
 310         for (i = 0; i < timeout; i++) {
 311                 u32 t;
 312
 313                 t = priv->read(priv, reg);
 314                 if ((t & mask) == val)
 315                         return 0;
 316
 317                 usleep_range(1000, 2000);
 318         }
 319
 320         return -ETIMEDOUT;
 321 }
 322
 323 static int
 324 ar8216_mib_capture(struct ar8216_priv *priv)
 325 {
 326         unsigned mib_func;
 327         int ret;
 328
 329         lockdep_assert_held(&priv->mib_lock);
 330
 331         if (chip_is_ar8327(priv))
 332                 mib_func = AR8327_REG_MIB_FUNC;
 333         else
 334                 mib_func = AR8216_REG_MIB_FUNC;
 335
 336         /* Capture the hardware statistics for all ports */
 337         ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC,
 338                    (AR8216_MIB_FUNC_CAPTURE << AR8216_MIB_FUNC_S));
 339
 340         /* Wait for the capturing to complete. */
 341         ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 342         if (ret)
 343                 goto out;
 344
 345         ret = 0;
 346
 347 out:
 348         return ret;
 349 }
 350
 351 static int
 352 ar8216_mib_flush(struct ar8216_priv *priv)
 353 {
 354         unsigned mib_func;
 355         int ret;
 356
 357         lockdep_assert_held(&priv->mib_lock);
 358
 359         if (chip_is_ar8327(priv))
 360                 mib_func = AR8327_REG_MIB_FUNC;
 361         else
 362                 mib_func = AR8216_REG_MIB_FUNC;
 363
 364         /* Flush hardware statistics for all ports */
 365         ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC,
 366                    (AR8216_MIB_FUNC_FLUSH << AR8216_MIB_FUNC_S));
 367
 368         /* Wait for the capturing to complete. */
 369         ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 370         if (ret)
 371                 goto out;
 372
 373         ret = 0;
 374
 375 out:
 376         return ret;
 377 }
 378
 379 static void
 380 ar8216_mib_fetch_port_stat(struct ar8216_priv *priv, int port, bool flush)
 381 {
 382         unsigned int base;
 383         u64 *mib_stats;
 384         int i;
 385
 386         lockdep_assert_held(&priv->mib_lock);
 387
 388         if (chip_is_ar8327(priv))
 389                 base = AR8327_REG_PORT_STATS_BASE(port);
 390         else
 391                 base = AR8216_REG_PORT_STATS_BASE(port);
 392
 393         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 394         for (i = 0; i < priv->chip->num_mibs; i++) {
 395                 const struct ar8xxx_mib_desc *mib;
 396                 u64 t;
 397
 398                 mib = &priv->chip->mib_decs[i];
 399                 t = priv->read(priv, base + mib->offset);
 400                 if (mib->size == 2) {
 401                         u64 hi;
 402
 403                         hi = priv->read(priv, base + mib->offset + 4);
 404                         t |= hi << 32;
 405                 }
 406
 407                 if (flush)
 408                         mib_stats[i] = 0;
 409                 else
 410                         mib_stats[i] += t;
 411         }
 412 }
 413
 414 static void
 415 ar8216_read_port_link(struct ar8216_priv *priv, int port,
 416                       struct switch_port_link *link)
 417 {
 418         u32 status;
 419         u32 speed;
 420
 421         memset(link, '\0', sizeof(*link));
 422
 423         status = priv->chip->read_port_status(priv, port);
 424
 425         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 426         if (link->aneg) {
 427                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 428                 if (!link->link)
 429                         return;
 430         } else {
 431                 link->link = true;
 432         }
 433
 434         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 435         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 436         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 437
 438         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 439                  AR8216_PORT_STATUS_SPEED_S;
 440
 441         switch (speed) {
 442         case AR8216_PORT_SPEED_10M:
 443                 link->speed = SWITCH_PORT_SPEED_10;
 444                 break;
 445         case AR8216_PORT_SPEED_100M:
 446                 link->speed = SWITCH_PORT_SPEED_100;
 447                 break;
 448         case AR8216_PORT_SPEED_1000M:
 449                 link->speed = SWITCH_PORT_SPEED_1000;
 450                 break;
 451         default:
 452                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 453                 break;
 454         }
 455 }
 456
 457 static struct sk_buff *
 458 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 459 {
 460         struct ar8216_priv *priv = dev->phy_ptr;
 461         unsigned char *buf;
 462
 463         if (unlikely(!priv))
 464                 goto error;
 465
 466         if (!priv->vlan)
 467                 goto send;
 468
 469         if (unlikely(skb_headroom(skb) < 2)) {
 470                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 471                         goto error;
 472         }
 473
 474         buf = skb_push(skb, 2);
 475         buf[0] = 0x10;
 476         buf[1] = 0x80;
 477
 478 send:
 479         return skb;
 480
 481 error:
 482         dev_kfree_skb_any(skb);
 483         return NULL;
 484 }
 485
 486 static void
 487 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 488 {
 489         struct ar8216_priv *priv;
 490         unsigned char *buf;
 491         int port, vlan;
 492
 493         priv = dev->phy_ptr;
 494         if (!priv)
 495                 return;
 496
 497         /* don't strip the header if vlan mode is disabled */
 498         if (!priv->vlan)
 499                 return;
 500
 501         /* strip header, get vlan id */
 502         buf = skb->data;
 503         skb_pull(skb, 2);
 504
 505         /* check for vlan header presence */
 506         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 507                 return;
 508
 509         port = buf[0] & 0xf;
 510
 511         /* no need to fix up packets coming from a tagged source */
 512         if (priv->vlan_tagged & (1 << port))
 513                 return;
 514
 515         /* lookup port vid from local table, the switch passes an invalid vlan id */
 516         vlan = priv->vlan_id[priv->pvid[port]];
 517
 518         buf[14 + 2] &= 0xf0;
 519         buf[14 + 2] |= vlan >> 8;
 520         buf[15 + 2] = vlan & 0xff;
 521 }
 522
 523 static int
 524 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
 525 {
 526         int timeout = 20;
 527         u32 t = 0;
 528
 529         while (1) {
 530                 t = priv->read(priv, reg);
 531                 if ((t & mask) == val)
 532                         return 0;
 533
 534                 if (timeout-- <= 0)
 535                         break;
 536
 537                 udelay(10);
 538         }
 539
 540         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 541                (unsigned int) reg, t, mask, val);
 542         return -ETIMEDOUT;
 543 }
 544
 545 static void
 546 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
 547 {
 548         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 549                 return;
 550         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 551                 val &= AR8216_VTUDATA_MEMBER;
 552                 val |= AR8216_VTUDATA_VALID;
 553                 priv->write(priv, AR8216_REG_VTU_DATA, val);
 554         }
 555         op |= AR8216_VTU_ACTIVE;
 556         priv->write(priv, AR8216_REG_VTU, op);
 557 }
 558
 559 static void
 560 ar8216_vtu_flush(struct ar8216_priv *priv)
 561 {
 562         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 563 }
 564
 565 static void
 566 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
 567 {
 568         u32 op;
 569
 570         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 571         ar8216_vtu_op(priv, op, port_mask);
 572 }
 573
 574 static int
 575 ar8216_atu_flush(struct ar8216_priv *priv)
 576 {
 577         int ret;
 578
 579         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 580         if (!ret)
 581                 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 582
 583         return ret;
 584 }
 585
 586 static u32
 587 ar8216_read_port_status(struct ar8216_priv *priv, int port)
 588 {
 589         return priv->read(priv, AR8216_REG_PORT_STATUS(port));
 590 }
 591
 592 static void
 593 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
 594                   u32 members, u32 pvid)
 595 {
 596         u32 header;
 597
 598         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 599                 header = AR8216_PORT_CTRL_HEADER;
 600         else
 601                 header = 0;
 602
 603         ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
 604                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 605                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 606                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 607                    AR8216_PORT_CTRL_LEARN | header |
 608                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 609                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 610
 611         ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
 612                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 613                    AR8216_PORT_VLAN_DEFAULT_ID,
 614                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 615                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 616                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 617 }
 618
 619 static int
 620 ar8216_hw_init(struct ar8216_priv *priv)
 621 {
 622         return 0;
 623 }
 624
 625 static void
 626 ar8216_init_globals(struct ar8216_priv *priv)
 627 {
 628         /* standard atheros magic */
 629         priv->write(priv, 0x38, 0xc000050e);
 630
 631         ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 632                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 633 }
 634
 635 static void
 636 ar8216_init_port(struct ar8216_priv *priv, int port)
 637 {
 638         /* Enable port learning and tx */
 639         priv->write(priv, AR8216_REG_PORT_CTRL(port),
 640                 AR8216_PORT_CTRL_LEARN |
 641                 (4 << AR8216_PORT_CTRL_STATE_S));
 642
 643         priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
 644
 645         if (port == AR8216_PORT_CPU) {
 646                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 647                         AR8216_PORT_STATUS_LINK_UP |
 648                         (ar8xxx_has_gige(priv) ?
 649                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 650                         AR8216_PORT_STATUS_TXMAC |
 651                         AR8216_PORT_STATUS_RXMAC |
 652                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 653                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 654                         AR8216_PORT_STATUS_DUPLEX);
 655         } else {
 656                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 657                         AR8216_PORT_STATUS_LINK_AUTO);
 658         }
 659 }
 660
 661 static const struct ar8xxx_chip ar8216_chip = {
 662         .hw_init = ar8216_hw_init,
 663         .init_globals = ar8216_init_globals,
 664         .init_port = ar8216_init_port,
 665         .setup_port = ar8216_setup_port,
 666         .read_port_status = ar8216_read_port_status,
 667         .atu_flush = ar8216_atu_flush,
 668         .vtu_flush = ar8216_vtu_flush,
 669         .vtu_load_vlan = ar8216_vtu_load_vlan,
 670 };
 671
 672 static void
 673 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
 674                   u32 members, u32 pvid)
 675 {
 676         ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
 677                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 678                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 679                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 680                    AR8216_PORT_CTRL_LEARN |
 681                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 682                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 683
 684         ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
 685                    AR8236_PORT_VLAN_DEFAULT_ID,
 686                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 687
 688         ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 689                    AR8236_PORT_VLAN2_VLAN_MODE |
 690                    AR8236_PORT_VLAN2_MEMBER,
 691                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 692                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 693 }
 694
 695 static int
 696 ar8236_hw_init(struct ar8216_priv *priv)
 697 {
 698         int i;
 699         struct mii_bus *bus;
 700
 701         if (priv->initialized)
 702                 return 0;
 703
 704         /* Initialize the PHYs */
 705         bus = priv->phy->bus;
 706         for (i = 0; i < 5; i++) {
 707                 mdiobus_write(bus, i, MII_ADVERTISE,
 708                               ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
 709                               ADVERTISE_PAUSE_ASYM);
 710                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 711         }
 712         msleep(1000);
 713
 714         priv->initialized = true;
 715         return 0;
 716 }
 717
 718 static void
 719 ar8236_init_globals(struct ar8216_priv *priv)
 720 {
 721         /* enable jumbo frames */
 722         ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 723                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 724
 725         /* Enable MIB counters */
 726         ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 727                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 728                    AR8236_MIB_EN);
 729 }
 730
 731 static const struct ar8xxx_chip ar8236_chip = {
 732         .caps = AR8XXX_CAP_MIB_COUNTERS,
 733         .hw_init = ar8236_hw_init,
 734         .init_globals = ar8236_init_globals,
 735         .init_port = ar8216_init_port,
 736         .setup_port = ar8236_setup_port,
 737         .read_port_status = ar8216_read_port_status,
 738         .atu_flush = ar8216_atu_flush,
 739         .vtu_flush = ar8216_vtu_flush,
 740         .vtu_load_vlan = ar8216_vtu_load_vlan,
 741
 742         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 743         .mib_decs = ar8236_mibs,
 744 };
 745
 746 static int
 747 ar8316_hw_init(struct ar8216_priv *priv)
 748 {
 749         int i;
 750         u32 val, newval;
 751         struct mii_bus *bus;
 752
 753         val = priv->read(priv, 0x8);
 754
 755         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 756                 if (priv->port4_phy) {
 757                         /* value taken from Ubiquiti RouterStation Pro */
 758                         newval = 0x81461bea;
 759                         printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
 760                 } else {
 761                         newval = 0x01261be2;
 762                         printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
 763                 }
 764         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 765                 /* value taken from AVM Fritz!Box 7390 sources */
 766                 newval = 0x010e5b71;
 767         } else {
 768                 /* no known value for phy interface */
 769                 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
 770                         priv->phy->interface);
 771                 return -EINVAL;
 772         }
 773
 774         if (val == newval)
 775                 goto out;
 776
 777         priv->write(priv, 0x8, newval);
 778
 779         /* Initialize the ports */
 780         bus = priv->phy->bus;
 781         for (i = 0; i < 5; i++) {
 782                 if ((i == 4) && priv->port4_phy &&
 783                     priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 784                         /* work around for phy4 rgmii mode */
 785                         ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
 786                         /* rx delay */
 787                         ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
 788                         /* tx delay */
 789                         ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
 790                         msleep(1000);
 791                 }
 792
 793                 /* initialize the port itself */
 794                 mdiobus_write(bus, i, MII_ADVERTISE,
 795                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 796                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 797                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 798                 msleep(1000);
 799         }
 800
 801 out:
 802         priv->initialized = true;
 803         return 0;
 804 }
 805
 806 static void
 807 ar8316_init_globals(struct ar8216_priv *priv)
 808 {
 809         /* standard atheros magic */
 810         priv->write(priv, 0x38, 0xc000050e);
 811
 812         /* enable cpu port to receive multicast and broadcast frames */
 813         priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 814
 815         /* enable jumbo frames */
 816         ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 817                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 818
 819         /* Enable MIB counters */
 820         ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 821                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 822                    AR8236_MIB_EN);
 823 }
 824
 825 static const struct ar8xxx_chip ar8316_chip = {
 826         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
 827         .hw_init = ar8316_hw_init,
 828         .init_globals = ar8316_init_globals,
 829         .init_port = ar8216_init_port,
 830         .setup_port = ar8216_setup_port,
 831         .read_port_status = ar8216_read_port_status,
 832         .atu_flush = ar8216_atu_flush,
 833         .vtu_flush = ar8216_vtu_flush,
 834         .vtu_load_vlan = ar8216_vtu_load_vlan,
 835
 836         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 837         .mib_decs = ar8236_mibs,
 838 };
 839
 840 static u32
 841 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
 842 {
 843         u32 t;
 844
 845         if (!cfg)
 846                 return 0;
 847
 848         t = 0;
 849         switch (cfg->mode) {
 850         case AR8327_PAD_NC:
 851                 break;
 852
 853         case AR8327_PAD_MAC2MAC_MII:
 854                 t = AR8327_PAD_MAC_MII_EN;
 855                 if (cfg->rxclk_sel)
 856                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
 857                 if (cfg->txclk_sel)
 858                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
 859                 break;
 860
 861         case AR8327_PAD_MAC2MAC_GMII:
 862                 t = AR8327_PAD_MAC_GMII_EN;
 863                 if (cfg->rxclk_sel)
 864                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
 865                 if (cfg->txclk_sel)
 866                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
 867                 break;
 868
 869         case AR8327_PAD_MAC_SGMII:
 870                 t = AR8327_PAD_SGMII_EN;
 871                 break;
 872
 873         case AR8327_PAD_MAC2PHY_MII:
 874                 t = AR8327_PAD_PHY_MII_EN;
 875                 if (cfg->rxclk_sel)
 876                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
 877                 if (cfg->txclk_sel)
 878                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
 879                 break;
 880
 881         case AR8327_PAD_MAC2PHY_GMII:
 882                 t = AR8327_PAD_PHY_GMII_EN;
 883                 if (cfg->pipe_rxclk_sel)
 884                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
 885                 if (cfg->rxclk_sel)
 886                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
 887                 if (cfg->txclk_sel)
 888                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
 889                 break;
 890
 891         case AR8327_PAD_MAC_RGMII:
 892                 t = AR8327_PAD_RGMII_EN;
 893                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
 894                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
 895                 if (cfg->rxclk_delay_en)
 896                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
 897                 if (cfg->txclk_delay_en)
 898                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
 899                 break;
 900
 901         case AR8327_PAD_PHY_GMII:
 902                 t = AR8327_PAD_PHYX_GMII_EN;
 903                 break;
 904
 905         case AR8327_PAD_PHY_RGMII:
 906                 t = AR8327_PAD_PHYX_RGMII_EN;
 907                 break;
 908
 909         case AR8327_PAD_PHY_MII:
 910                 t = AR8327_PAD_PHYX_MII_EN;
 911                 break;
 912         }
 913
 914         return t;
 915 }
 916
 917 static void
 918 ar8327_phy_fixup(struct ar8216_priv *priv, int phy)
 919 {
 920         switch (priv->chip_rev) {
 921         case 1:
 922                 /* For 100M waveform */
 923                 ar8216_phy_dbg_write(priv, phy, 0, 0x02ea);
 924                 /* Turn on Gigabit clock */
 925                 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
 926                 break;
 927
 928         case 2:
 929                 ar8216_phy_mmd_write(priv, phy, 0x7, 0x3c);
 930                 ar8216_phy_mmd_write(priv, phy, 0x4007, 0x0);
 931                 /* fallthrough */
 932         case 4:
 933                 ar8216_phy_mmd_write(priv, phy, 0x3, 0x800d);
 934                 ar8216_phy_mmd_write(priv, phy, 0x4003, 0x803f);
 935
 936                 ar8216_phy_dbg_write(priv, phy, 0x3d, 0x6860);
 937                 ar8216_phy_dbg_write(priv, phy, 0x5, 0x2c46);
 938                 ar8216_phy_dbg_write(priv, phy, 0x3c, 0x6000);
 939                 break;
 940         }
 941 }
 942
 943 static int
 944 ar8327_hw_init(struct ar8216_priv *priv)
 945 {
 946         struct ar8327_platform_data *pdata;
 947         struct ar8327_led_cfg *led_cfg;
 948         struct mii_bus *bus;
 949         u32 pos, new_pos;
 950         u32 t;
 951         int i;
 952
 953         pdata = priv->phy->dev.platform_data;
 954         if (!pdata)
 955                 return -EINVAL;
 956
 957         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
 958         priv->write(priv, AR8327_REG_PAD0_MODE, t);
 959         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
 960         priv->write(priv, AR8327_REG_PAD5_MODE, t);
 961         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
 962         priv->write(priv, AR8327_REG_PAD6_MODE, t);
 963
 964         pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
 965         new_pos = pos;
 966
 967         led_cfg = pdata->led_cfg;
 968         if (led_cfg) {
 969                 if (led_cfg->open_drain)
 970                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
 971                 else
 972                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
 973
 974                 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
 975                 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
 976                 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
 977                 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
 978         }
 979
 980         if (new_pos != pos) {
 981                 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
 982                 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
 983         }
 984
 985         bus = priv->phy->bus;
 986         for (i = 0; i < AR8327_NUM_PHYS; i++) {
 987                 ar8327_phy_fixup(priv, i);
 988
 989                 /* start aneg on the PHY */
 990                 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
 991                                                      ADVERTISE_PAUSE_CAP |
 992                                                      ADVERTISE_PAUSE_ASYM);
 993                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 994                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 995         }
 996
 997         msleep(1000);
 998
 999         return 0;
1000 }
1001
1002 static void
1003 ar8327_init_globals(struct ar8216_priv *priv)
1004 {
1005         u32 t;
1006
1007         /* enable CPU port and disable mirror port */
1008         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1009             AR8327_FWD_CTRL0_MIRROR_PORT;
1010         priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1011
1012         /* forward multicast and broadcast frames to CPU */
1013         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1014             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1015             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1016         priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1017
1018         /* setup MTU */
1019         ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1020                    AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1021
1022         /* Enable MIB counters */
1023         ar8216_reg_set(priv, AR8327_REG_MODULE_EN,
1024                        AR8327_MODULE_EN_MIB);
1025 }
1026
1027 static void
1028 ar8327_init_cpuport(struct ar8216_priv *priv)
1029 {
1030         struct ar8327_platform_data *pdata;
1031         struct ar8327_port_cfg *cfg;
1032         u32 t;
1033
1034         pdata = priv->phy->dev.platform_data;
1035         if (!pdata)
1036                 return;
1037
1038         cfg = &pdata->cpuport_cfg;
1039         if (!cfg->force_link) {
1040                 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
1041                             AR8216_PORT_STATUS_LINK_AUTO);
1042                 return;
1043         }
1044
1045         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1046         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1047         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1048         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1049         switch (cfg->speed) {
1050         case AR8327_PORT_SPEED_10:
1051                 t |= AR8216_PORT_SPEED_10M;
1052                 break;
1053         case AR8327_PORT_SPEED_100:
1054                 t |= AR8216_PORT_SPEED_100M;
1055                 break;
1056         case AR8327_PORT_SPEED_1000:
1057                 t |= AR8216_PORT_SPEED_1000M;
1058                 break;
1059         }
1060
1061         priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
1062 }
1063
1064 static void
1065 ar8327_init_port(struct ar8216_priv *priv, int port)
1066 {
1067         u32 t;
1068
1069         if (port == AR8216_PORT_CPU) {
1070                 ar8327_init_cpuport(priv);
1071         } else {
1072                 t = AR8216_PORT_STATUS_LINK_AUTO;
1073                 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1074         }
1075
1076         priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1077
1078         priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
1079
1080         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1081         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1082
1083         t = AR8327_PORT_LOOKUP_LEARN;
1084         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1085         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1086 }
1087
1088 static u32
1089 ar8327_read_port_status(struct ar8216_priv *priv, int port)
1090 {
1091         return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1092 }
1093
1094 static int
1095 ar8327_atu_flush(struct ar8216_priv *priv)
1096 {
1097         int ret;
1098
1099         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1100                               AR8327_ATU_FUNC_BUSY, 0);
1101         if (!ret)
1102                 priv->write(priv, AR8327_REG_ATU_FUNC,
1103                             AR8327_ATU_FUNC_OP_FLUSH);
1104
1105         return ret;
1106 }
1107
1108 static void
1109 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
1110 {
1111         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1112                             AR8327_VTU_FUNC1_BUSY, 0))
1113                 return;
1114
1115         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1116                 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1117
1118         op |= AR8327_VTU_FUNC1_BUSY;
1119         priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1120 }
1121
1122 static void
1123 ar8327_vtu_flush(struct ar8216_priv *priv)
1124 {
1125         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1126 }
1127
1128 static void
1129 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
1130 {
1131         u32 op;
1132         u32 val;
1133         int i;
1134
1135         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1136         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1137         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1138                 u32 mode;
1139
1140                 if ((port_mask & BIT(i)) == 0)
1141                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1142                 else if (priv->vlan == 0)
1143                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1144                 else if (priv->vlan_tagged & BIT(i))
1145                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1146                 else
1147                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1148
1149                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1150         }
1151         ar8327_vtu_op(priv, op, val);
1152 }
1153
1154 static void
1155 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
1156                   u32 members, u32 pvid)
1157 {
1158         u32 t;
1159         u32 mode;
1160
1161         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1162         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1163         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1164
1165         mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1166         switch (egress) {
1167         case AR8216_OUT_KEEP:
1168                 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1169                 break;
1170         case AR8216_OUT_STRIP_VLAN:
1171                 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1172                 break;
1173         case AR8216_OUT_ADD_VLAN:
1174                 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1175                 break;
1176         }
1177
1178         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1179         t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1180         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1181
1182         t = members;
1183         t |= AR8327_PORT_LOOKUP_LEARN;
1184         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1185         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1186         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1187 }
1188
1189 static const struct ar8xxx_chip ar8327_chip = {
1190         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1191         .hw_init = ar8327_hw_init,
1192         .init_globals = ar8327_init_globals,
1193         .init_port = ar8327_init_port,
1194         .setup_port = ar8327_setup_port,
1195         .read_port_status = ar8327_read_port_status,
1196         .atu_flush = ar8327_atu_flush,
1197         .vtu_flush = ar8327_vtu_flush,
1198         .vtu_load_vlan = ar8327_vtu_load_vlan,
1199
1200         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1201         .mib_decs = ar8236_mibs,
1202 };
1203
1204 static int
1205 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1206                    struct switch_val *val)
1207 {
1208         struct ar8216_priv *priv = to_ar8216(dev);
1209         priv->vlan = !!val->value.i;
1210         return 0;
1211 }
1212
1213 static int
1214 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1215                    struct switch_val *val)
1216 {
1217         struct ar8216_priv *priv = to_ar8216(dev);
1218         val->value.i = priv->vlan;
1219         return 0;
1220 }
1221
1222
1223 static int
1224 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1225 {
1226         struct ar8216_priv *priv = to_ar8216(dev);
1227
1228         /* make sure no invalid PVIDs get set */
1229
1230         if (vlan >= dev->vlans)
1231                 return -EINVAL;
1232
1233         priv->pvid[port] = vlan;
1234         return 0;
1235 }
1236
1237 static int
1238 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1239 {
1240         struct ar8216_priv *priv = to_ar8216(dev);
1241         *vlan = priv->pvid[port];
1242         return 0;
1243 }
1244
1245 static int
1246 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1247                   struct switch_val *val)
1248 {
1249         struct ar8216_priv *priv = to_ar8216(dev);
1250         priv->vlan_id[val->port_vlan] = val->value.i;
1251         return 0;
1252 }
1253
1254 static int
1255 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1256                   struct switch_val *val)
1257 {
1258         struct ar8216_priv *priv = to_ar8216(dev);
1259         val->value.i = priv->vlan_id[val->port_vlan];
1260         return 0;
1261 }
1262
1263 static int
1264 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
1265                         struct switch_port_link *link)
1266 {
1267         struct ar8216_priv *priv = to_ar8216(dev);
1268
1269         ar8216_read_port_link(priv, port, link);
1270         return 0;
1271 }
1272
1273 static int
1274 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1275 {
1276         struct ar8216_priv *priv = to_ar8216(dev);
1277         u8 ports = priv->vlan_table[val->port_vlan];
1278         int i;
1279
1280         val->len = 0;
1281         for (i = 0; i < dev->ports; i++) {
1282                 struct switch_port *p;
1283
1284                 if (!(ports & (1 << i)))
1285                         continue;
1286
1287                 p = &val->value.ports[val->len++];
1288                 p->id = i;
1289                 if (priv->vlan_tagged & (1 << i))
1290                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1291                 else
1292                         p->flags = 0;
1293         }
1294         return 0;
1295 }
1296
1297 static int
1298 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1299 {
1300         struct ar8216_priv *priv = to_ar8216(dev);
1301         u8 *vt = &priv->vlan_table[val->port_vlan];
1302         int i, j;
1303
1304         *vt = 0;
1305         for (i = 0; i < val->len; i++) {
1306                 struct switch_port *p = &val->value.ports[i];
1307
1308                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1309                         priv->vlan_tagged |= (1 << p->id);
1310                 } else {
1311                         priv->vlan_tagged &= ~(1 << p->id);
1312                         priv->pvid[p->id] = val->port_vlan;
1313
1314                         /* make sure that an untagged port does not
1315                          * appear in other vlans */
1316                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1317                                 if (j == val->port_vlan)
1318                                         continue;
1319                                 priv->vlan_table[j] &= ~(1 << p->id);
1320                         }
1321                 }
1322
1323                 *vt |= 1 << p->id;
1324         }
1325         return 0;
1326 }
1327
1328 static int
1329 ar8216_sw_hw_apply(struct switch_dev *dev)
1330 {
1331         struct ar8216_priv *priv = to_ar8216(dev);
1332         u8 portmask[AR8X16_MAX_PORTS];
1333         int i, j;
1334
1335         mutex_lock(&priv->reg_mutex);
1336         /* flush all vlan translation unit entries */
1337         priv->chip->vtu_flush(priv);
1338
1339         memset(portmask, 0, sizeof(portmask));
1340         if (!priv->init) {
1341                 /* calculate the port destination masks and load vlans
1342                  * into the vlan translation unit */
1343                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1344                         u8 vp = priv->vlan_table[j];
1345
1346                         if (!vp)
1347                                 continue;
1348
1349                         for (i = 0; i < dev->ports; i++) {
1350                                 u8 mask = (1 << i);
1351                                 if (vp & mask)
1352                                         portmask[i] |= vp & ~mask;
1353                         }
1354
1355                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1356                                                  priv->vlan_table[j]);
1357                 }
1358         } else {
1359                 /* vlan disabled:
1360                  * isolate all ports, but connect them to the cpu port */
1361                 for (i = 0; i < dev->ports; i++) {
1362                         if (i == AR8216_PORT_CPU)
1363                                 continue;
1364
1365                         portmask[i] = 1 << AR8216_PORT_CPU;
1366                         portmask[AR8216_PORT_CPU] |= (1 << i);
1367                 }
1368         }
1369
1370         /* update the port destination mask registers and tag settings */
1371         for (i = 0; i < dev->ports; i++) {
1372                 int egress, ingress;
1373                 int pvid;
1374
1375                 if (priv->vlan) {
1376                         pvid = priv->vlan_id[priv->pvid[i]];
1377                         if (priv->vlan_tagged & (1 << i))
1378                                 egress = AR8216_OUT_ADD_VLAN;
1379                         else
1380                                 egress = AR8216_OUT_STRIP_VLAN;
1381                         ingress = AR8216_IN_SECURE;
1382                 } else {
1383                         pvid = i;
1384                         egress = AR8216_OUT_KEEP;
1385                         ingress = AR8216_IN_PORT_ONLY;
1386                 }
1387
1388                 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1389                                        pvid);
1390         }
1391         mutex_unlock(&priv->reg_mutex);
1392         return 0;
1393 }
1394
1395 static int
1396 ar8216_sw_reset_switch(struct switch_dev *dev)
1397 {
1398         struct ar8216_priv *priv = to_ar8216(dev);
1399         int i;
1400
1401         mutex_lock(&priv->reg_mutex);
1402         memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1403                 offsetof(struct ar8216_priv, vlan));
1404
1405         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1406                 priv->vlan_id[i] = i;
1407
1408         /* Configure all ports */
1409         for (i = 0; i < dev->ports; i++)
1410                 priv->chip->init_port(priv, i);
1411
1412         priv->chip->init_globals(priv);
1413         mutex_unlock(&priv->reg_mutex);
1414
1415         return ar8216_sw_hw_apply(dev);
1416 }
1417
1418 static int
1419 ar8216_sw_set_reset_mibs(struct switch_dev *dev,
1420                          const struct switch_attr *attr,
1421                          struct switch_val *val)
1422 {
1423         struct ar8216_priv *priv = to_ar8216(dev);
1424         unsigned int len;
1425         int ret;
1426
1427         if (!ar8xxx_has_mib_counters(priv))
1428                 return -EOPNOTSUPP;
1429
1430         mutex_lock(&priv->mib_lock);
1431
1432         len = priv->dev.ports * priv->chip->num_mibs *
1433               sizeof(*priv->mib_stats);
1434         memset(priv->mib_stats, '\0', len);
1435         ret = ar8216_mib_flush(priv);
1436         if (ret)
1437                 goto unlock;
1438
1439         ret = 0;
1440
1441 unlock:
1442         mutex_unlock(&priv->mib_lock);
1443         return ret;
1444 }
1445
1446 static int
1447 ar8216_sw_set_port_reset_mib(struct switch_dev *dev,
1448                              const struct switch_attr *attr,
1449                              struct switch_val *val)
1450 {
1451         struct ar8216_priv *priv = to_ar8216(dev);
1452         int port;
1453         int ret;
1454
1455         if (!ar8xxx_has_mib_counters(priv))
1456                 return -EOPNOTSUPP;
1457
1458         port = val->port_vlan;
1459         if (port >= dev->ports)
1460                 return -EINVAL;
1461
1462         mutex_lock(&priv->mib_lock);
1463         ret = ar8216_mib_capture(priv);
1464         if (ret)
1465                 goto unlock;
1466
1467         ar8216_mib_fetch_port_stat(priv, port, true);
1468
1469         ret = 0;
1470
1471 unlock:
1472         mutex_unlock(&priv->mib_lock);
1473         return ret;
1474 }
1475
1476 static int
1477 ar8216_sw_get_port_mib(struct switch_dev *dev,
1478                        const struct switch_attr *attr,
1479                        struct switch_val *val)
1480 {
1481         struct ar8216_priv *priv = to_ar8216(dev);
1482         const struct ar8xxx_chip *chip = priv->chip;
1483         u64 *mib_stats;
1484         int port;
1485         int ret;
1486         char *buf = priv->buf;
1487         int i, len = 0;
1488
1489         if (!ar8xxx_has_mib_counters(priv))
1490                 return -EOPNOTSUPP;
1491
1492         port = val->port_vlan;
1493         if (port >= dev->ports)
1494                 return -EINVAL;
1495
1496         mutex_lock(&priv->mib_lock);
1497         ret = ar8216_mib_capture(priv);
1498         if (ret)
1499                 goto unlock;
1500
1501         ar8216_mib_fetch_port_stat(priv, port, false);
1502         mutex_unlock(&priv->mib_lock);
1503
1504         len += snprintf(buf + len, sizeof(priv->buf) - len,
1505                         "Port %d MIB counters\n",
1506                         port);
1507
1508         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1509         for (i = 0; i < chip->num_mibs; i++)
1510                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1511                                 "%-12s: %llu\n",
1512                                 chip->mib_decs[i].name,
1513                                 mib_stats[i]);
1514
1515         val->value.s = buf;
1516         val->len = len;
1517
1518         ret = 0;
1519
1520 unlock:
1521         mutex_unlock(&priv->mib_lock);
1522         return ret;
1523 }
1524
1525 static struct switch_attr ar8216_globals[] = {
1526         {
1527                 .type = SWITCH_TYPE_INT,
1528                 .name = "enable_vlan",
1529                 .description = "Enable VLAN mode",
1530                 .set = ar8216_sw_set_vlan,
1531                 .get = ar8216_sw_get_vlan,
1532                 .max = 1
1533         },
1534         {
1535                 .type = SWITCH_TYPE_NOVAL,
1536                 .name = "reset_mibs",
1537                 .description = "Reset all MIB counters",
1538                 .set = ar8216_sw_set_reset_mibs,
1539         },
1540
1541 };
1542
1543 static struct switch_attr ar8216_port[] = {
1544         {
1545                 .type = SWITCH_TYPE_NOVAL,
1546                 .name = "reset_mib",
1547                 .description = "Reset single port MIB counters",
1548                 .set = ar8216_sw_set_port_reset_mib,
1549         },
1550         {
1551                 .type = SWITCH_TYPE_STRING,
1552                 .name = "mib",
1553                 .description = "Get port's MIB counters",
1554                 .set = NULL,
1555                 .get = ar8216_sw_get_port_mib,
1556         },
1557 };
1558
1559 static struct switch_attr ar8216_vlan[] = {
1560         {
1561                 .type = SWITCH_TYPE_INT,
1562                 .name = "vid",
1563                 .description = "VLAN ID (0-4094)",
1564                 .set = ar8216_sw_set_vid,
1565                 .get = ar8216_sw_get_vid,
1566                 .max = 4094,
1567         },
1568 };
1569
1570 static const struct switch_dev_ops ar8216_sw_ops = {
1571         .attr_global = {
1572                 .attr = ar8216_globals,
1573                 .n_attr = ARRAY_SIZE(ar8216_globals),
1574         },
1575         .attr_port = {
1576                 .attr = ar8216_port,
1577                 .n_attr = ARRAY_SIZE(ar8216_port),
1578         },
1579         .attr_vlan = {
1580                 .attr = ar8216_vlan,
1581                 .n_attr = ARRAY_SIZE(ar8216_vlan),
1582         },
1583         .get_port_pvid = ar8216_sw_get_pvid,
1584         .set_port_pvid = ar8216_sw_set_pvid,
1585         .get_vlan_ports = ar8216_sw_get_ports,
1586         .set_vlan_ports = ar8216_sw_set_ports,
1587         .apply_config = ar8216_sw_hw_apply,
1588         .reset_switch = ar8216_sw_reset_switch,
1589         .get_port_link = ar8216_sw_get_port_link,
1590 };
1591
1592 static int
1593 ar8216_id_chip(struct ar8216_priv *priv)
1594 {
1595         u32 val;
1596         u16 id;
1597         int i;
1598
1599         val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1600         if (val == ~0)
1601                 return -ENODEV;
1602
1603         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1604         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1605                 u16 t;
1606
1607                 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1608                 if (val == ~0)
1609                         return -ENODEV;
1610
1611                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1612                 if (t != id)
1613                         return -ENODEV;
1614         }
1615
1616         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1617         priv->chip_rev = (id & AR8216_CTRL_REVISION);
1618
1619         switch (priv->chip_ver) {
1620         case AR8XXX_VER_AR8216:
1621                 priv->chip = &ar8216_chip;
1622                 break;
1623         case AR8XXX_VER_AR8236:
1624                 priv->chip = &ar8236_chip;
1625                 break;
1626         case AR8XXX_VER_AR8316:
1627                 priv->chip = &ar8316_chip;
1628                 break;
1629         case AR8XXX_VER_AR8327:
1630                 priv->mii_lo_first = true;
1631                 priv->chip = &ar8327_chip;
1632                 break;
1633         default:
1634                 printk(KERN_DEBUG
1635                         "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1636                         priv->chip_ver, priv->chip_rev,
1637                         mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
1638                         mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
1639
1640                 return -ENODEV;
1641         }
1642
1643         return 0;
1644 }
1645
1646 static void
1647 ar8xxx_mib_work_func(struct work_struct *work)
1648 {
1649         struct ar8216_priv *priv;
1650         int err;
1651
1652         priv = container_of(work, struct ar8216_priv, mib_work.work);
1653
1654         mutex_lock(&priv->mib_lock);
1655
1656         err = ar8216_mib_capture(priv);
1657         if (err)
1658                 goto next_port;
1659
1660         ar8216_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1661
1662 next_port:
1663         priv->mib_next_port++;
1664         if (priv->mib_next_port > priv->dev.ports)
1665                 priv->mib_next_port = 0;
1666
1667         mutex_unlock(&priv->mib_lock);
1668         schedule_delayed_work(&priv->mib_work,
1669                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1670 }
1671
1672 static int
1673 ar8xxx_mib_init(struct ar8216_priv *priv)
1674 {
1675         unsigned int len;
1676
1677         if (!ar8xxx_has_mib_counters(priv))
1678                 return 0;
1679
1680         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1681
1682         len = priv->dev.ports * priv->chip->num_mibs *
1683               sizeof(*priv->mib_stats);
1684         priv->mib_stats = kzalloc(len, GFP_KERNEL);
1685
1686         if (!priv->mib_stats)
1687                 return -ENOMEM;
1688
1689         mutex_init(&priv->mib_lock);
1690         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1691
1692         return 0;
1693 }
1694
1695 static void
1696 ar8xxx_mib_start(struct ar8216_priv *priv)
1697 {
1698         if (!ar8xxx_has_mib_counters(priv))
1699                 return;
1700
1701         schedule_delayed_work(&priv->mib_work,
1702                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1703 }
1704
1705 static void
1706 ar8xxx_mib_cleanup(struct ar8216_priv *priv)
1707 {
1708         if (!ar8xxx_has_mib_counters(priv))
1709                 return;
1710
1711         cancel_delayed_work(&priv->mib_work);
1712         kfree(priv->mib_stats);
1713 }
1714
1715 static int
1716 ar8216_config_init(struct phy_device *pdev)
1717 {
1718         struct ar8216_priv *priv = pdev->priv;
1719         struct net_device *dev = pdev->attached_dev;
1720         struct switch_dev *swdev;
1721         int ret;
1722
1723         if (!priv) {
1724                 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1725                 if (priv == NULL)
1726                         return -ENOMEM;
1727         }
1728
1729         priv->phy = pdev;
1730
1731         ret = ar8216_id_chip(priv);
1732         if (ret)
1733                 goto err_free_priv;
1734
1735         if (pdev->addr != 0) {
1736                 if (ar8xxx_has_gige(priv)) {
1737                         pdev->supported |= SUPPORTED_1000baseT_Full;
1738                         pdev->advertising |= ADVERTISED_1000baseT_Full;
1739                 }
1740
1741                 if (chip_is_ar8316(priv)) {
1742                         /* check if we're attaching to the switch twice */
1743                         pdev = pdev->bus->phy_map[0];
1744                         if (!pdev) {
1745                                 kfree(priv);
1746                                 return 0;
1747                         }
1748
1749                         /* switch device has not been initialized, reuse priv */
1750                         if (!pdev->priv) {
1751                                 priv->port4_phy = true;
1752                                 pdev->priv = priv;
1753                                 return 0;
1754                         }
1755
1756                         kfree(priv);
1757
1758                         /* switch device has been initialized, reinit */
1759                         priv = pdev->priv;
1760                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
1761                         priv->initialized = false;
1762                         priv->port4_phy = true;
1763                         ar8316_hw_init(priv);
1764                         return 0;
1765                 }
1766
1767                 kfree(priv);
1768                 return 0;
1769         }
1770
1771         if (ar8xxx_has_gige(priv))
1772                 pdev->supported = SUPPORTED_1000baseT_Full;
1773         else
1774                 pdev->supported = SUPPORTED_100baseT_Full;
1775         pdev->advertising = pdev->supported;
1776
1777         mutex_init(&priv->reg_mutex);
1778         priv->read = ar8216_mii_read;
1779         priv->write = ar8216_mii_write;
1780
1781         pdev->priv = priv;
1782
1783         swdev = &priv->dev;
1784         swdev->cpu_port = AR8216_PORT_CPU;
1785         swdev->ops = &ar8216_sw_ops;
1786         swdev->ports = AR8216_NUM_PORTS;
1787
1788         if (chip_is_ar8316(priv)) {
1789                 swdev->name = "Atheros AR8316";
1790                 swdev->vlans = AR8X16_MAX_VLANS;
1791
1792                 if (priv->port4_phy) {
1793                         /* port 5 connected to the other mac, therefore unusable */
1794                         swdev->ports = (AR8216_NUM_PORTS - 1);
1795                 }
1796         } else if (chip_is_ar8236(priv)) {
1797                 swdev->name = "Atheros AR8236";
1798                 swdev->vlans = AR8216_NUM_VLANS;
1799                 swdev->ports = AR8216_NUM_PORTS;
1800         } else if (chip_is_ar8327(priv)) {
1801                 swdev->name = "Atheros AR8327";
1802                 swdev->vlans = AR8X16_MAX_VLANS;
1803                 swdev->ports = AR8327_NUM_PORTS;
1804         } else {
1805                 swdev->name = "Atheros AR8216";
1806                 swdev->vlans = AR8216_NUM_VLANS;
1807         }
1808
1809         ret = ar8xxx_mib_init(priv);
1810         if (ret)
1811                 goto err_free_priv;
1812
1813         ret = register_switch(&priv->dev, pdev->attached_dev);
1814         if (ret)
1815                 goto err_cleanup_mib;
1816
1817         printk(KERN_INFO "%s: %s switch driver attached.\n",
1818                 pdev->attached_dev->name, swdev->name);
1819
1820         priv->init = true;
1821
1822         ret = priv->chip->hw_init(priv);
1823         if (ret)
1824                 goto err_cleanup_mib;
1825
1826         ret = ar8216_sw_reset_switch(&priv->dev);
1827         if (ret)
1828                 goto err_cleanup_mib;
1829
1830         dev->phy_ptr = priv;
1831
1832         /* VID fixup only needed on ar8216 */
1833         if (chip_is_ar8216(priv) && pdev->addr == 0) {
1834                 dev->priv_flags |= IFF_NO_IP_ALIGN;
1835                 dev->eth_mangle_rx = ar8216_mangle_rx;
1836                 dev->eth_mangle_tx = ar8216_mangle_tx;
1837         }
1838
1839         priv->init = false;
1840
1841         ar8xxx_mib_start(priv);
1842
1843         return 0;
1844
1845 err_cleanup_mib:
1846         ar8xxx_mib_cleanup(priv);
1847 err_free_priv:
1848         kfree(priv);
1849         return ret;
1850 }
1851
1852 static int
1853 ar8216_read_status(struct phy_device *phydev)
1854 {
1855         struct ar8216_priv *priv = phydev->priv;
1856         struct switch_port_link link;
1857         int ret;
1858
1859         if (phydev->addr != 0)
1860                 return genphy_read_status(phydev);
1861
1862         ar8216_read_port_link(priv, phydev->addr, &link);
1863         phydev->link = !!link.link;
1864         if (!phydev->link)
1865                 return 0;
1866
1867         switch (link.speed) {
1868         case SWITCH_PORT_SPEED_10:
1869                 phydev->speed = SPEED_10;
1870                 break;
1871         case SWITCH_PORT_SPEED_100:
1872                 phydev->speed = SPEED_100;
1873                 break;
1874         case SWITCH_PORT_SPEED_1000:
1875                 phydev->speed = SPEED_1000;
1876                 break;
1877         default:
1878                 phydev->speed = 0;
1879         }
1880         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1881
1882         /* flush the address translation unit */
1883         mutex_lock(&priv->reg_mutex);
1884         ret = priv->chip->atu_flush(priv);
1885         mutex_unlock(&priv->reg_mutex);
1886
1887         phydev->state = PHY_RUNNING;
1888         netif_carrier_on(phydev->attached_dev);
1889         phydev->adjust_link(phydev->attached_dev);
1890
1891         return ret;
1892 }
1893
1894 static int
1895 ar8216_config_aneg(struct phy_device *phydev)
1896 {
1897         if (phydev->addr == 0)
1898                 return 0;
1899
1900         return genphy_config_aneg(phydev);
1901 }
1902
1903 static int
1904 ar8216_probe(struct phy_device *pdev)
1905 {
1906         struct ar8216_priv *priv;
1907         int ret;
1908
1909         priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1910         if (priv == NULL)
1911                 return -ENOMEM;
1912
1913         priv->phy = pdev;
1914
1915         ret = ar8216_id_chip(priv);
1916         kfree(priv);
1917
1918         return ret;
1919 }
1920
1921 static void
1922 ar8216_remove(struct phy_device *pdev)
1923 {
1924         struct ar8216_priv *priv = pdev->priv;
1925         struct net_device *dev = pdev->attached_dev;
1926
1927         if (!priv)
1928                 return;
1929
1930         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1931         dev->eth_mangle_rx = NULL;
1932         dev->eth_mangle_tx = NULL;
1933
1934         if (pdev->addr == 0)
1935                 unregister_switch(&priv->dev);
1936
1937         ar8xxx_mib_cleanup(priv);
1938         kfree(priv);
1939 }
1940
1941 static struct phy_driver ar8216_driver = {
1942         .phy_id         = 0x004d0000,
1943         .name           = "Atheros AR8216/AR8236/AR8316",
1944         .phy_id_mask    = 0xffff0000,
1945         .features       = PHY_BASIC_FEATURES,
1946         .probe          = ar8216_probe,
1947         .remove         = ar8216_remove,
1948         .config_init    = &ar8216_config_init,
1949         .config_aneg    = &ar8216_config_aneg,
1950         .read_status    = &ar8216_read_status,
1951         .driver         = { .owner = THIS_MODULE },
1952 };
1953
1954 int __init
1955 ar8216_init(void)
1956 {
1957         return phy_driver_register(&ar8216_driver);
1958 }
1959
1960 void __exit
1961 ar8216_exit(void)
1962 {
1963         phy_driver_unregister(&ar8216_driver);
1964 }
1965
1966 module_init(ar8216_init);
1967 module_exit(ar8216_exit);
1968 MODULE_LICENSE("GPL");
1969