target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/version.h>
  37
  38 #include "ar8216.h"
  39
  40 extern const struct ar8xxx_chip ar8327_chip;
  41 extern const struct ar8xxx_chip ar8337_chip;
  42
  43 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  44
  45 #define MIB_DESC(_s , _o, _n)   \
  46         {                       \
  47                 .size = (_s),   \
  48                 .offset = (_o), \
  49                 .name = (_n),   \
  50         }
  51
  52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  53         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  54         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  55         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  56         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  57         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  58         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  59         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  60         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  61         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  62         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  63         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  64         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  65         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  66         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  67         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  68         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  69         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  70         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  71         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  72         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  73         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  74         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  75         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  76         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  77         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  78         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  79         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  80         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  81         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  82         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  83         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  84         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  85         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  86         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  87         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  88         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  89         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  90 };
  91
  92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
  93         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
  94         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
  95         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
  96         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
  97         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
  98         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
  99         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 100         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 101         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 102         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 103         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 104         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 105         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 106         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 107         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 108         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 109         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 110         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 111         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 112         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 113         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 114         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 115         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 116         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 117         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 118         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 119         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 120         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 121         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 122         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 123         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 124         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 125         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 126         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 127         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 128         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 129         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 130         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 131         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 132 };
 133
 134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 135 static LIST_HEAD(ar8xxx_dev_list);
 136
 137 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 138 static int
 139 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 140 {
 141         unsigned int sleep_msecs = 20;
 142         int ret, elapsed, i;
 143
 144         for (elapsed = sleep_msecs; elapsed <= 600;
 145              elapsed += sleep_msecs) {
 146                 msleep(sleep_msecs);
 147                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 148                         ret = mdiobus_read(bus, i, MII_BMCR);
 149                         if (ret < 0)
 150                                 return ret;
 151                         if (ret & BMCR_RESET)
 152                                 break;
 153                         if (i == AR8XXX_NUM_PHYS - 1) {
 154                                 usleep_range(1000, 2000);
 155                                 return 0;
 156                         }
 157                 }
 158         }
 159         return -ETIMEDOUT;
 160 }
 161
 162 static int
 163 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 164 {
 165         int ret;
 166
 167         if (phydev->autoneg != AUTONEG_ENABLE)
 168                 return 0;
 169         /*
 170          * BMCR_ANENABLE might have been cleared
 171          * by phy_init_hw in certain kernel versions
 172          * therefore check for it
 173          */
 174         ret = phy_read(phydev, MII_BMCR);
 175         if (ret < 0)
 176                 return ret;
 177         if (ret & BMCR_ANENABLE)
 178                 return 0;
 179
 180         dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
 181         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 182         return phy_write(phydev, MII_BMCR, ret);
 183 }
 184
 185 void
 186 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 187 {
 188         int i;
 189         struct mii_bus *bus;
 190
 191         bus = priv->mii_bus;
 192         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 193                 if (priv->chip->phy_fixup)
 194                         priv->chip->phy_fixup(priv, i);
 195
 196                 /* initialize the port itself */
 197                 mdiobus_write(bus, i, MII_ADVERTISE,
 198                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 199                 if (ar8xxx_has_gige(priv))
 200                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 201                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 202         }
 203
 204         ar8xxx_phy_poll_reset(bus);
 205 }
 206
 207 u32
 208 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
 209 {
 210         struct mii_bus *bus = priv->mii_bus;
 211         u16 lo, hi;
 212
 213         lo = bus->read(bus, phy_id, regnum);
 214         hi = bus->read(bus, phy_id, regnum + 1);
 215
 216         return (hi << 16) | lo;
 217 }
 218
 219 void
 220 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
 221 {
 222         struct mii_bus *bus = priv->mii_bus;
 223         u16 lo, hi;
 224
 225         lo = val & 0xffff;
 226         hi = (u16) (val >> 16);
 227
 228         if (priv->chip->mii_lo_first)
 229         {
 230                 bus->write(bus, phy_id, regnum, lo);
 231                 bus->write(bus, phy_id, regnum + 1, hi);
 232         } else {
 233                 bus->write(bus, phy_id, regnum + 1, hi);
 234                 bus->write(bus, phy_id, regnum, lo);
 235         }
 236 }
 237
 238 u32
 239 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
 240 {
 241         struct mii_bus *bus = priv->mii_bus;
 242         u16 r1, r2, page;
 243         u32 val;
 244
 245         split_addr((u32) reg, &r1, &r2, &page);
 246
 247         mutex_lock(&bus->mdio_lock);
 248
 249         bus->write(bus, 0x18, 0, page);
 250         wait_for_page_switch();
 251         val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
 252
 253         mutex_unlock(&bus->mdio_lock);
 254
 255         return val;
 256 }
 257
 258 void
 259 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
 260 {
 261         struct mii_bus *bus = priv->mii_bus;
 262         u16 r1, r2, page;
 263
 264         split_addr((u32) reg, &r1, &r2, &page);
 265
 266         mutex_lock(&bus->mdio_lock);
 267
 268         bus->write(bus, 0x18, 0, page);
 269         wait_for_page_switch();
 270         ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
 271
 272         mutex_unlock(&bus->mdio_lock);
 273 }
 274
 275 u32
 276 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 277 {
 278         struct mii_bus *bus = priv->mii_bus;
 279         u16 r1, r2, page;
 280         u32 ret;
 281
 282         split_addr((u32) reg, &r1, &r2, &page);
 283
 284         mutex_lock(&bus->mdio_lock);
 285
 286         bus->write(bus, 0x18, 0, page);
 287         wait_for_page_switch();
 288
 289         ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
 290         ret &= ~mask;
 291         ret |= val;
 292         ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
 293
 294         mutex_unlock(&bus->mdio_lock);
 295
 296         return ret;
 297 }
 298
 299 void
 300 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 301                      u16 dbg_addr, u16 dbg_data)
 302 {
 303         struct mii_bus *bus = priv->mii_bus;
 304
 305         mutex_lock(&bus->mdio_lock);
 306         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 307         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 308         mutex_unlock(&bus->mdio_lock);
 309 }
 310
 311 void
 312 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 313 {
 314         struct mii_bus *bus = priv->mii_bus;
 315
 316         mutex_lock(&bus->mdio_lock);
 317         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 318         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 319         mutex_unlock(&bus->mdio_lock);
 320 }
 321
 322 u16
 323 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr)
 324 {
 325         struct mii_bus *bus = priv->mii_bus;
 326         u16 data;
 327
 328         mutex_lock(&bus->mdio_lock);
 329         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 330         data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
 331         mutex_unlock(&bus->mdio_lock);
 332
 333         return data;
 334 }
 335
 336 static int
 337 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 338                 unsigned timeout)
 339 {
 340         int i;
 341
 342         for (i = 0; i < timeout; i++) {
 343                 u32 t;
 344
 345                 t = ar8xxx_read(priv, reg);
 346                 if ((t & mask) == val)
 347                         return 0;
 348
 349                 usleep_range(1000, 2000);
 350         }
 351
 352         return -ETIMEDOUT;
 353 }
 354
 355 static int
 356 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 357 {
 358         unsigned mib_func = priv->chip->mib_func;
 359         int ret;
 360
 361         lockdep_assert_held(&priv->mib_lock);
 362
 363         /* Capture the hardware statistics for all ports */
 364         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 365
 366         /* Wait for the capturing to complete. */
 367         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 368         if (ret)
 369                 goto out;
 370
 371         ret = 0;
 372
 373 out:
 374         return ret;
 375 }
 376
 377 static int
 378 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 379 {
 380         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 381 }
 382
 383 static int
 384 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 385 {
 386         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 387 }
 388
 389 static void
 390 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 391 {
 392         unsigned int base;
 393         u64 *mib_stats;
 394         int i;
 395
 396         WARN_ON(port >= priv->dev.ports);
 397
 398         lockdep_assert_held(&priv->mib_lock);
 399
 400         base = priv->chip->reg_port_stats_start +
 401                priv->chip->reg_port_stats_length * port;
 402
 403         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 404         for (i = 0; i < priv->chip->num_mibs; i++) {
 405                 const struct ar8xxx_mib_desc *mib;
 406                 u64 t;
 407
 408                 mib = &priv->chip->mib_decs[i];
 409                 t = ar8xxx_read(priv, base + mib->offset);
 410                 if (mib->size == 2) {
 411                         u64 hi;
 412
 413                         hi = ar8xxx_read(priv, base + mib->offset + 4);
 414                         t |= hi << 32;
 415                 }
 416
 417                 if (flush)
 418                         mib_stats[i] = 0;
 419                 else
 420                         mib_stats[i] += t;
 421         }
 422 }
 423
 424 static void
 425 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 426                       struct switch_port_link *link)
 427 {
 428         u32 status;
 429         u32 speed;
 430
 431         memset(link, '\0', sizeof(*link));
 432
 433         status = priv->chip->read_port_status(priv, port);
 434
 435         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 436         if (link->aneg) {
 437                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 438         } else {
 439                 link->link = true;
 440
 441                 if (priv->get_port_link) {
 442                         int err;
 443
 444                         err = priv->get_port_link(port);
 445                         if (err >= 0)
 446                                 link->link = !!err;
 447                 }
 448         }
 449
 450         if (!link->link)
 451                 return;
 452
 453         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 454         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 455         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 456
 457         if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
 458                 link->eee = priv->chip->read_port_eee_status(priv, port);
 459
 460         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 461                  AR8216_PORT_STATUS_SPEED_S;
 462
 463         switch (speed) {
 464         case AR8216_PORT_SPEED_10M:
 465                 link->speed = SWITCH_PORT_SPEED_10;
 466                 break;
 467         case AR8216_PORT_SPEED_100M:
 468                 link->speed = SWITCH_PORT_SPEED_100;
 469                 break;
 470         case AR8216_PORT_SPEED_1000M:
 471                 link->speed = SWITCH_PORT_SPEED_1000;
 472                 break;
 473         default:
 474                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 475                 break;
 476         }
 477 }
 478
 479 static struct sk_buff *
 480 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 481 {
 482         struct ar8xxx_priv *priv = dev->phy_ptr;
 483         unsigned char *buf;
 484
 485         if (unlikely(!priv))
 486                 goto error;
 487
 488         if (!priv->vlan)
 489                 goto send;
 490
 491         if (unlikely(skb_headroom(skb) < 2)) {
 492                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 493                         goto error;
 494         }
 495
 496         buf = skb_push(skb, 2);
 497         buf[0] = 0x10;
 498         buf[1] = 0x80;
 499
 500 send:
 501         return skb;
 502
 503 error:
 504         dev_kfree_skb_any(skb);
 505         return NULL;
 506 }
 507
 508 static void
 509 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 510 {
 511         struct ar8xxx_priv *priv;
 512         unsigned char *buf;
 513         int port, vlan;
 514
 515         priv = dev->phy_ptr;
 516         if (!priv)
 517                 return;
 518
 519         /* don't strip the header if vlan mode is disabled */
 520         if (!priv->vlan)
 521                 return;
 522
 523         /* strip header, get vlan id */
 524         buf = skb->data;
 525         skb_pull(skb, 2);
 526
 527         /* check for vlan header presence */
 528         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 529                 return;
 530
 531         port = buf[0] & 0xf;
 532
 533         /* no need to fix up packets coming from a tagged source */
 534         if (priv->vlan_tagged & (1 << port))
 535                 return;
 536
 537         /* lookup port vid from local table, the switch passes an invalid vlan id */
 538         vlan = priv->vlan_id[priv->pvid[port]];
 539
 540         buf[14 + 2] &= 0xf0;
 541         buf[14 + 2] |= vlan >> 8;
 542         buf[15 + 2] = vlan & 0xff;
 543 }
 544
 545 int
 546 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 547 {
 548         int timeout = 20;
 549         u32 t = 0;
 550
 551         while (1) {
 552                 t = ar8xxx_read(priv, reg);
 553                 if ((t & mask) == val)
 554                         return 0;
 555
 556                 if (timeout-- <= 0)
 557                         break;
 558
 559                 udelay(10);
 560         }
 561
 562         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 563                (unsigned int) reg, t, mask, val);
 564         return -ETIMEDOUT;
 565 }
 566
 567 static void
 568 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 569 {
 570         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 571                 return;
 572         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 573                 val &= AR8216_VTUDATA_MEMBER;
 574                 val |= AR8216_VTUDATA_VALID;
 575                 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
 576         }
 577         op |= AR8216_VTU_ACTIVE;
 578         ar8xxx_write(priv, AR8216_REG_VTU, op);
 579 }
 580
 581 static void
 582 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 583 {
 584         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 585 }
 586
 587 static void
 588 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 589 {
 590         u32 op;
 591
 592         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 593         ar8216_vtu_op(priv, op, port_mask);
 594 }
 595
 596 static int
 597 ar8216_atu_flush(struct ar8xxx_priv *priv)
 598 {
 599         int ret;
 600
 601         ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
 602         if (!ret)
 603                 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
 604                                                          AR8216_ATU_ACTIVE);
 605
 606         return ret;
 607 }
 608
 609 static int
 610 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
 611 {
 612         u32 t;
 613         int ret;
 614
 615         ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
 616         if (!ret) {
 617                 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
 618                 t |= AR8216_ATU_ACTIVE;
 619                 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
 620         }
 621
 622         return ret;
 623 }
 624
 625 static u32
 626 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 627 {
 628         return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
 629 }
 630
 631 static void
 632 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 633 {
 634         u32 header;
 635         u32 egress, ingress;
 636         u32 pvid;
 637
 638         if (priv->vlan) {
 639                 pvid = priv->vlan_id[priv->pvid[port]];
 640                 if (priv->vlan_tagged & (1 << port))
 641                         egress = AR8216_OUT_ADD_VLAN;
 642                 else
 643                         egress = AR8216_OUT_STRIP_VLAN;
 644                 ingress = AR8216_IN_SECURE;
 645         } else {
 646                 pvid = port;
 647                 egress = AR8216_OUT_KEEP;
 648                 ingress = AR8216_IN_PORT_ONLY;
 649         }
 650
 651         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 652                 header = AR8216_PORT_CTRL_HEADER;
 653         else
 654                 header = 0;
 655
 656         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 657                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 658                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 659                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 660                    AR8216_PORT_CTRL_LEARN | header |
 661                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 662                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 663
 664         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 665                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 666                    AR8216_PORT_VLAN_DEFAULT_ID,
 667                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 668                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 669                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 670 }
 671
 672 static int
 673 ar8216_hw_init(struct ar8xxx_priv *priv)
 674 {
 675         if (priv->initialized)
 676                 return 0;
 677
 678         ar8xxx_phy_init(priv);
 679
 680         priv->initialized = true;
 681         return 0;
 682 }
 683
 684 static void
 685 ar8216_init_globals(struct ar8xxx_priv *priv)
 686 {
 687         /* standard atheros magic */
 688         ar8xxx_write(priv, 0x38, 0xc000050e);
 689
 690         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 691                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 692 }
 693
 694 static void
 695 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 696 {
 697         /* Enable port learning and tx */
 698         ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
 699                 AR8216_PORT_CTRL_LEARN |
 700                 (4 << AR8216_PORT_CTRL_STATE_S));
 701
 702         ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
 703
 704         if (port == AR8216_PORT_CPU) {
 705                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 706                         AR8216_PORT_STATUS_LINK_UP |
 707                         (ar8xxx_has_gige(priv) ?
 708                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 709                         AR8216_PORT_STATUS_TXMAC |
 710                         AR8216_PORT_STATUS_RXMAC |
 711                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 712                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 713                         AR8216_PORT_STATUS_DUPLEX);
 714         } else {
 715                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 716                         AR8216_PORT_STATUS_LINK_AUTO);
 717         }
 718 }
 719
 720 static void
 721 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
 722 {
 723         int timeout = 20;
 724
 725         while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout)
 726                 udelay(10);
 727
 728         if (!timeout)
 729                 pr_err("ar8216: timeout waiting for atu to become ready\n");
 730 }
 731
 732 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
 733                                  struct arl_entry *a, u32 *status, enum arl_op op)
 734 {
 735         struct mii_bus *bus = priv->mii_bus;
 736         u16 r2, page;
 737         u16 r1_func0, r1_func1, r1_func2;
 738         u32 t, val0, val1, val2;
 739         int i;
 740
 741         split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
 742         r2 |= 0x10;
 743
 744         r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
 745         r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
 746
 747         switch (op) {
 748         case AR8XXX_ARL_INITIALIZE:
 749                 /* all ATU registers are on the same page
 750                 * therefore set page only once
 751                 */
 752                 bus->write(bus, 0x18, 0, page);
 753                 wait_for_page_switch();
 754
 755                 ar8216_wait_atu_ready(priv, r2, r1_func0);
 756
 757                 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
 758                 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
 759                 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
 760                 break;
 761         case AR8XXX_ARL_GET_NEXT:
 762                 t = ar8xxx_mii_read32(priv, r2, r1_func0);
 763                 t |= AR8216_ATU_ACTIVE;
 764                 ar8xxx_mii_write32(priv, r2, r1_func0, t);
 765                 ar8216_wait_atu_ready(priv, r2, r1_func0);
 766
 767                 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
 768                 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
 769                 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
 770
 771                 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
 772                 if (!*status)
 773                         break;
 774
 775                 i = 0;
 776                 t = AR8216_ATU_PORT0;
 777                 while (!(val2 & t) && ++i < priv->dev.ports)
 778                         t <<= 1;
 779
 780                 a->port = i;
 781                 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
 782                 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
 783                 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
 784                 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
 785                 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
 786                 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
 787                 break;
 788         }
 789 }
 790
 791 static void
 792 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 793 {
 794         u32 egress, ingress;
 795         u32 pvid;
 796
 797         if (priv->vlan) {
 798                 pvid = priv->vlan_id[priv->pvid[port]];
 799                 if (priv->vlan_tagged & (1 << port))
 800                         egress = AR8216_OUT_ADD_VLAN;
 801                 else
 802                         egress = AR8216_OUT_STRIP_VLAN;
 803                 ingress = AR8216_IN_SECURE;
 804         } else {
 805                 pvid = port;
 806                 egress = AR8216_OUT_KEEP;
 807                 ingress = AR8216_IN_PORT_ONLY;
 808         }
 809
 810         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 811                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 812                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 813                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 814                    AR8216_PORT_CTRL_LEARN |
 815                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 816                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 817
 818         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 819                    AR8236_PORT_VLAN_DEFAULT_ID,
 820                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 821
 822         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 823                    AR8236_PORT_VLAN2_VLAN_MODE |
 824                    AR8236_PORT_VLAN2_MEMBER,
 825                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 826                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 827 }
 828
 829 static void
 830 ar8236_init_globals(struct ar8xxx_priv *priv)
 831 {
 832         /* enable jumbo frames */
 833         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 834                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 835
 836         /* enable cpu port to receive arp frames */
 837         ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
 838                    AR8236_ATU_CTRL_RES);
 839
 840         /* enable cpu port to receive multicast and broadcast frames */
 841         ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
 842                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
 843
 844         /* Enable MIB counters */
 845         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 846                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 847                    AR8236_MIB_EN);
 848 }
 849
 850 static int
 851 ar8316_hw_init(struct ar8xxx_priv *priv)
 852 {
 853         u32 val, newval;
 854
 855         val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
 856
 857         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 858                 if (priv->port4_phy) {
 859                         /* value taken from Ubiquiti RouterStation Pro */
 860                         newval = 0x81461bea;
 861                         pr_info("ar8316: Using port 4 as PHY\n");
 862                 } else {
 863                         newval = 0x01261be2;
 864                         pr_info("ar8316: Using port 4 as switch port\n");
 865                 }
 866         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 867                 /* value taken from AVM Fritz!Box 7390 sources */
 868                 newval = 0x010e5b71;
 869         } else {
 870                 /* no known value for phy interface */
 871                 pr_err("ar8316: unsupported mii mode: %d.\n",
 872                        priv->phy->interface);
 873                 return -EINVAL;
 874         }
 875
 876         if (val == newval)
 877                 goto out;
 878
 879         ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
 880
 881         if (priv->port4_phy &&
 882             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 883                 /* work around for phy4 rgmii mode */
 884                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 885                 /* rx delay */
 886                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 887                 /* tx delay */
 888                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 889                 msleep(1000);
 890         }
 891
 892         ar8xxx_phy_init(priv);
 893
 894 out:
 895         priv->initialized = true;
 896         return 0;
 897 }
 898
 899 static void
 900 ar8316_init_globals(struct ar8xxx_priv *priv)
 901 {
 902         /* standard atheros magic */
 903         ar8xxx_write(priv, 0x38, 0xc000050e);
 904
 905         /* enable cpu port to receive multicast and broadcast frames */
 906         ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 907
 908         /* enable jumbo frames */
 909         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 910                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 911
 912         /* Enable MIB counters */
 913         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 914                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 915                    AR8236_MIB_EN);
 916 }
 917
 918 int
 919 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 920                    struct switch_val *val)
 921 {
 922         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 923         priv->vlan = !!val->value.i;
 924         return 0;
 925 }
 926
 927 int
 928 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 929                    struct switch_val *val)
 930 {
 931         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 932         val->value.i = priv->vlan;
 933         return 0;
 934 }
 935
 936
 937 int
 938 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
 939 {
 940         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 941
 942         /* make sure no invalid PVIDs get set */
 943
 944         if (vlan >= dev->vlans)
 945                 return -EINVAL;
 946
 947         priv->pvid[port] = vlan;
 948         return 0;
 949 }
 950
 951 int
 952 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
 953 {
 954         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 955         *vlan = priv->pvid[port];
 956         return 0;
 957 }
 958
 959 static int
 960 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
 961                   struct switch_val *val)
 962 {
 963         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 964         priv->vlan_id[val->port_vlan] = val->value.i;
 965         return 0;
 966 }
 967
 968 static int
 969 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
 970                   struct switch_val *val)
 971 {
 972         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 973         val->value.i = priv->vlan_id[val->port_vlan];
 974         return 0;
 975 }
 976
 977 int
 978 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
 979                         struct switch_port_link *link)
 980 {
 981         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 982
 983         ar8216_read_port_link(priv, port, link);
 984         return 0;
 985 }
 986
 987 static int
 988 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
 989 {
 990         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 991         u8 ports = priv->vlan_table[val->port_vlan];
 992         int i;
 993
 994         val->len = 0;
 995         for (i = 0; i < dev->ports; i++) {
 996                 struct switch_port *p;
 997
 998                 if (!(ports & (1 << i)))
 999                         continue;
1000
1001                 p = &val->value.ports[val->len++];
1002                 p->id = i;
1003                 if (priv->vlan_tagged & (1 << i))
1004                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1005                 else
1006                         p->flags = 0;
1007         }
1008         return 0;
1009 }
1010
1011 static int
1012 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1013 {
1014         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1015         u8 *vt = &priv->vlan_table[val->port_vlan];
1016         int i, j;
1017
1018         *vt = 0;
1019         for (i = 0; i < val->len; i++) {
1020                 struct switch_port *p = &val->value.ports[i];
1021
1022                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1023                         priv->vlan_tagged |= (1 << p->id);
1024                 } else {
1025                         priv->vlan_tagged &= ~(1 << p->id);
1026                         priv->pvid[p->id] = val->port_vlan;
1027
1028                         /* make sure that an untagged port does not
1029                          * appear in other vlans */
1030                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1031                                 if (j == val->port_vlan)
1032                                         continue;
1033                                 priv->vlan_table[j] &= ~(1 << p->id);
1034                         }
1035                 }
1036
1037                 *vt |= 1 << p->id;
1038         }
1039         return 0;
1040 }
1041
1042 static void
1043 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1044 {
1045         int port;
1046
1047         /* reset all mirror registers */
1048         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1049                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1050                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1051         for (port = 0; port < AR8216_NUM_PORTS; port++) {
1052                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1053                            AR8216_PORT_CTRL_MIRROR_RX);
1054
1055                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1056                            AR8216_PORT_CTRL_MIRROR_TX);
1057         }
1058
1059         /* now enable mirroring if necessary */
1060         if (priv->source_port >= AR8216_NUM_PORTS ||
1061             priv->monitor_port >= AR8216_NUM_PORTS ||
1062             priv->source_port == priv->monitor_port) {
1063                 return;
1064         }
1065
1066         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1067                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1068                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1069
1070         if (priv->mirror_rx)
1071                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1072                            AR8216_PORT_CTRL_MIRROR_RX);
1073
1074         if (priv->mirror_tx)
1075                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1076                            AR8216_PORT_CTRL_MIRROR_TX);
1077 }
1078
1079 static inline u32
1080 ar8xxx_age_time_val(int age_time)
1081 {
1082         return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1083                AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1084 }
1085
1086 static inline void
1087 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1088 {
1089         u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1090         ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1091 }
1092
1093 int
1094 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1095 {
1096         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1097         const struct ar8xxx_chip *chip = priv->chip;
1098         u8 portmask[AR8X16_MAX_PORTS];
1099         int i, j;
1100
1101         mutex_lock(&priv->reg_mutex);
1102         /* flush all vlan translation unit entries */
1103         priv->chip->vtu_flush(priv);
1104
1105         memset(portmask, 0, sizeof(portmask));
1106         if (!priv->init) {
1107                 /* calculate the port destination masks and load vlans
1108                  * into the vlan translation unit */
1109                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1110                         u8 vp = priv->vlan_table[j];
1111
1112                         if (!vp)
1113                                 continue;
1114
1115                         for (i = 0; i < dev->ports; i++) {
1116                                 u8 mask = (1 << i);
1117                                 if (vp & mask)
1118                                         portmask[i] |= vp & ~mask;
1119                         }
1120
1121                         chip->vtu_load_vlan(priv, priv->vlan_id[j],
1122                                             priv->vlan_table[j]);
1123                 }
1124         } else {
1125                 /* vlan disabled:
1126                  * isolate all ports, but connect them to the cpu port */
1127                 for (i = 0; i < dev->ports; i++) {
1128                         if (i == AR8216_PORT_CPU)
1129                                 continue;
1130
1131                         portmask[i] = 1 << AR8216_PORT_CPU;
1132                         portmask[AR8216_PORT_CPU] |= (1 << i);
1133                 }
1134         }
1135
1136         /* update the port destination mask registers and tag settings */
1137         for (i = 0; i < dev->ports; i++) {
1138                 chip->setup_port(priv, i, portmask[i]);
1139         }
1140
1141         chip->set_mirror_regs(priv);
1142
1143         /* set age time */
1144         if (chip->reg_arl_ctrl)
1145                 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1146
1147         mutex_unlock(&priv->reg_mutex);
1148         return 0;
1149 }
1150
1151 int
1152 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1153 {
1154         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1155         const struct ar8xxx_chip *chip = priv->chip;
1156         int i;
1157
1158         mutex_lock(&priv->reg_mutex);
1159         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1160                 offsetof(struct ar8xxx_priv, vlan));
1161
1162         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1163                 priv->vlan_id[i] = i;
1164
1165         /* Configure all ports */
1166         for (i = 0; i < dev->ports; i++)
1167                 chip->init_port(priv, i);
1168
1169         priv->mirror_rx = false;
1170         priv->mirror_tx = false;
1171         priv->source_port = 0;
1172         priv->monitor_port = 0;
1173         priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1174
1175         chip->init_globals(priv);
1176
1177         mutex_unlock(&priv->reg_mutex);
1178
1179         return chip->sw_hw_apply(dev);
1180 }
1181
1182 int
1183 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1184                          const struct switch_attr *attr,
1185                          struct switch_val *val)
1186 {
1187         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1188         unsigned int len;
1189         int ret;
1190
1191         if (!ar8xxx_has_mib_counters(priv))
1192                 return -EOPNOTSUPP;
1193
1194         mutex_lock(&priv->mib_lock);
1195
1196         len = priv->dev.ports * priv->chip->num_mibs *
1197               sizeof(*priv->mib_stats);
1198         memset(priv->mib_stats, '\0', len);
1199         ret = ar8xxx_mib_flush(priv);
1200         if (ret)
1201                 goto unlock;
1202
1203         ret = 0;
1204
1205 unlock:
1206         mutex_unlock(&priv->mib_lock);
1207         return ret;
1208 }
1209
1210 int
1211 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1212                                const struct switch_attr *attr,
1213                                struct switch_val *val)
1214 {
1215         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1216
1217         mutex_lock(&priv->reg_mutex);
1218         priv->mirror_rx = !!val->value.i;
1219         priv->chip->set_mirror_regs(priv);
1220         mutex_unlock(&priv->reg_mutex);
1221
1222         return 0;
1223 }
1224
1225 int
1226 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1227                                const struct switch_attr *attr,
1228                                struct switch_val *val)
1229 {
1230         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1231         val->value.i = priv->mirror_rx;
1232         return 0;
1233 }
1234
1235 int
1236 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1237                                const struct switch_attr *attr,
1238                                struct switch_val *val)
1239 {
1240         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1241
1242         mutex_lock(&priv->reg_mutex);
1243         priv->mirror_tx = !!val->value.i;
1244         priv->chip->set_mirror_regs(priv);
1245         mutex_unlock(&priv->reg_mutex);
1246
1247         return 0;
1248 }
1249
1250 int
1251 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1252                                const struct switch_attr *attr,
1253                                struct switch_val *val)
1254 {
1255         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1256         val->value.i = priv->mirror_tx;
1257         return 0;
1258 }
1259
1260 int
1261 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1262                                   const struct switch_attr *attr,
1263                                   struct switch_val *val)
1264 {
1265         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1266
1267         mutex_lock(&priv->reg_mutex);
1268         priv->monitor_port = val->value.i;
1269         priv->chip->set_mirror_regs(priv);
1270         mutex_unlock(&priv->reg_mutex);
1271
1272         return 0;
1273 }
1274
1275 int
1276 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1277                                   const struct switch_attr *attr,
1278                                   struct switch_val *val)
1279 {
1280         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1281         val->value.i = priv->monitor_port;
1282         return 0;
1283 }
1284
1285 int
1286 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1287                                  const struct switch_attr *attr,
1288                                  struct switch_val *val)
1289 {
1290         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1291
1292         mutex_lock(&priv->reg_mutex);
1293         priv->source_port = val->value.i;
1294         priv->chip->set_mirror_regs(priv);
1295         mutex_unlock(&priv->reg_mutex);
1296
1297         return 0;
1298 }
1299
1300 int
1301 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1302                                  const struct switch_attr *attr,
1303                                  struct switch_val *val)
1304 {
1305         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1306         val->value.i = priv->source_port;
1307         return 0;
1308 }
1309
1310 int
1311 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1312                              const struct switch_attr *attr,
1313                              struct switch_val *val)
1314 {
1315         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1316         int port;
1317         int ret;
1318
1319         if (!ar8xxx_has_mib_counters(priv))
1320                 return -EOPNOTSUPP;
1321
1322         port = val->port_vlan;
1323         if (port >= dev->ports)
1324                 return -EINVAL;
1325
1326         mutex_lock(&priv->mib_lock);
1327         ret = ar8xxx_mib_capture(priv);
1328         if (ret)
1329                 goto unlock;
1330
1331         ar8xxx_mib_fetch_port_stat(priv, port, true);
1332
1333         ret = 0;
1334
1335 unlock:
1336         mutex_unlock(&priv->mib_lock);
1337         return ret;
1338 }
1339
1340 static void
1341 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1342 {
1343         unsigned long b;
1344         const char *unit;
1345
1346         if (byte >= 0x40000000) { /* 1 GiB */
1347                 b = byte * 10 / 0x40000000;
1348                 unit = "GiB";
1349         } else if (byte >= 0x100000) { /* 1 MiB */
1350                 b = byte * 10 / 0x100000;
1351                 unit = "MiB";
1352         } else if (byte >= 0x400) { /* 1 KiB */
1353                 b = byte * 10 / 0x400;
1354                 unit = "KiB";
1355         } else {
1356                 b = byte;
1357                 unit = "Byte";
1358         }
1359         if (strcmp(unit, "Byte"))
1360                 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1361         else
1362                 snprintf(buf, len, "%lu %s", b, unit);
1363 }
1364
1365 int
1366 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1367                        const struct switch_attr *attr,
1368                        struct switch_val *val)
1369 {
1370         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1371         const struct ar8xxx_chip *chip = priv->chip;
1372         u64 *mib_stats, mib_data;
1373         int port;
1374         int ret;
1375         char *buf = priv->buf;
1376         char buf1[64];
1377         const char *mib_name;
1378         int i, len = 0;
1379         bool mib_stats_empty = true;
1380
1381         if (!ar8xxx_has_mib_counters(priv))
1382                 return -EOPNOTSUPP;
1383
1384         port = val->port_vlan;
1385         if (port >= dev->ports)
1386                 return -EINVAL;
1387
1388         mutex_lock(&priv->mib_lock);
1389         ret = ar8xxx_mib_capture(priv);
1390         if (ret)
1391                 goto unlock;
1392
1393         ar8xxx_mib_fetch_port_stat(priv, port, false);
1394
1395         len += snprintf(buf + len, sizeof(priv->buf) - len,
1396                         "MIB counters\n");
1397
1398         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1399         for (i = 0; i < chip->num_mibs; i++) {
1400                 mib_name = chip->mib_decs[i].name;
1401                 mib_data = mib_stats[i];
1402                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1403                                 "%-12s: %llu\n", mib_name, mib_data);
1404                 if ((!strcmp(mib_name, "TxByte") ||
1405                     !strcmp(mib_name, "RxGoodByte")) &&
1406                     mib_data >= 1024) {
1407                         ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1408                         --len; /* discard newline at the end of buf */
1409                         len += snprintf(buf + len, sizeof(priv->buf) - len,
1410                                         " (%s)\n", buf1);
1411                 }
1412                 if (mib_stats_empty && mib_data)
1413                         mib_stats_empty = false;
1414         }
1415
1416         if (mib_stats_empty)
1417                 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1418
1419         val->value.s = buf;
1420         val->len = len;
1421
1422         ret = 0;
1423
1424 unlock:
1425         mutex_unlock(&priv->mib_lock);
1426         return ret;
1427 }
1428
1429 int
1430 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1431                            struct switch_val *val)
1432 {
1433         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1434         int age_time = val->value.i;
1435         u32 age_time_val;
1436
1437         if (age_time < 0)
1438                 return -EINVAL;
1439
1440         age_time_val = ar8xxx_age_time_val(age_time);
1441         if (age_time_val == 0 || age_time_val > 0xffff)
1442                 return -EINVAL;
1443
1444         priv->arl_age_time = age_time;
1445         return 0;
1446 }
1447
1448 int
1449 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1450                    struct switch_val *val)
1451 {
1452         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1453         val->value.i = priv->arl_age_time;
1454         return 0;
1455 }
1456
1457 int
1458 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1459                         const struct switch_attr *attr,
1460                         struct switch_val *val)
1461 {
1462         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1463         struct mii_bus *bus = priv->mii_bus;
1464         const struct ar8xxx_chip *chip = priv->chip;
1465         char *buf = priv->arl_buf;
1466         int i, j, k, len = 0;
1467         struct arl_entry *a, *a1;
1468         u32 status;
1469
1470         if (!chip->get_arl_entry)
1471                 return -EOPNOTSUPP;
1472
1473         mutex_lock(&priv->reg_mutex);
1474         mutex_lock(&bus->mdio_lock);
1475
1476         chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1477
1478         for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1479                 a = &priv->arl_table[i];
1480                 duplicate:
1481                 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1482
1483                 if (!status)
1484                         break;
1485
1486                 /* avoid duplicates
1487                  * ARL table can include multiple valid entries
1488                  * per MAC, just with differing status codes
1489                  */
1490                 for (j = 0; j < i; ++j) {
1491                         a1 = &priv->arl_table[j];
1492                         if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
1493                                 goto duplicate;
1494                 }
1495         }
1496
1497         mutex_unlock(&bus->mdio_lock);
1498
1499         len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1500                         "address resolution table\n");
1501
1502         if (i == AR8XXX_NUM_ARL_RECORDS)
1503                 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1504                                 "Too many entries found, displaying the first %d only!\n",
1505                                 AR8XXX_NUM_ARL_RECORDS);
1506
1507         for (j = 0; j < priv->dev.ports; ++j) {
1508                 for (k = 0; k < i; ++k) {
1509                         a = &priv->arl_table[k];
1510                         if (a->port != j)
1511                                 continue;
1512                         len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1513                                         "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1514                                         j,
1515                                         a->mac[5], a->mac[4], a->mac[3],
1516                                         a->mac[2], a->mac[1], a->mac[0]);
1517                 }
1518         }
1519
1520         val->value.s = buf;
1521         val->len = len;
1522
1523         mutex_unlock(&priv->reg_mutex);
1524
1525         return 0;
1526 }
1527
1528 int
1529 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1530                               const struct switch_attr *attr,
1531                               struct switch_val *val)
1532 {
1533         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1534         int ret;
1535
1536         mutex_lock(&priv->reg_mutex);
1537         ret = priv->chip->atu_flush(priv);
1538         mutex_unlock(&priv->reg_mutex);
1539
1540         return ret;
1541 }
1542
1543 int
1544 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1545                                    const struct switch_attr *attr,
1546                                    struct switch_val *val)
1547 {
1548         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1549         int port, ret;
1550
1551         port = val->port_vlan;
1552         if (port >= dev->ports)
1553                 return -EINVAL;
1554
1555         mutex_lock(&priv->reg_mutex);
1556         ret = priv->chip->atu_flush_port(priv, port);
1557         mutex_unlock(&priv->reg_mutex);
1558
1559         return ret;
1560 }
1561
1562 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1563         {
1564                 .type = SWITCH_TYPE_INT,
1565                 .name = "enable_vlan",
1566                 .description = "Enable VLAN mode",
1567                 .set = ar8xxx_sw_set_vlan,
1568                 .get = ar8xxx_sw_get_vlan,
1569                 .max = 1
1570         },
1571         {
1572                 .type = SWITCH_TYPE_NOVAL,
1573                 .name = "reset_mibs",
1574                 .description = "Reset all MIB counters",
1575                 .set = ar8xxx_sw_set_reset_mibs,
1576         },
1577         {
1578                 .type = SWITCH_TYPE_INT,
1579                 .name = "enable_mirror_rx",
1580                 .description = "Enable mirroring of RX packets",
1581                 .set = ar8xxx_sw_set_mirror_rx_enable,
1582                 .get = ar8xxx_sw_get_mirror_rx_enable,
1583                 .max = 1
1584         },
1585         {
1586                 .type = SWITCH_TYPE_INT,
1587                 .name = "enable_mirror_tx",
1588                 .description = "Enable mirroring of TX packets",
1589                 .set = ar8xxx_sw_set_mirror_tx_enable,
1590                 .get = ar8xxx_sw_get_mirror_tx_enable,
1591                 .max = 1
1592         },
1593         {
1594                 .type = SWITCH_TYPE_INT,
1595                 .name = "mirror_monitor_port",
1596                 .description = "Mirror monitor port",
1597                 .set = ar8xxx_sw_set_mirror_monitor_port,
1598                 .get = ar8xxx_sw_get_mirror_monitor_port,
1599                 .max = AR8216_NUM_PORTS - 1
1600         },
1601         {
1602                 .type = SWITCH_TYPE_INT,
1603                 .name = "mirror_source_port",
1604                 .description = "Mirror source port",
1605                 .set = ar8xxx_sw_set_mirror_source_port,
1606                 .get = ar8xxx_sw_get_mirror_source_port,
1607                 .max = AR8216_NUM_PORTS - 1
1608         },
1609         {
1610                 .type = SWITCH_TYPE_STRING,
1611                 .name = "arl_table",
1612                 .description = "Get ARL table",
1613                 .set = NULL,
1614                 .get = ar8xxx_sw_get_arl_table,
1615         },
1616         {
1617                 .type = SWITCH_TYPE_NOVAL,
1618                 .name = "flush_arl_table",
1619                 .description = "Flush ARL table",
1620                 .set = ar8xxx_sw_set_flush_arl_table,
1621         },
1622 };
1623
1624 const struct switch_attr ar8xxx_sw_attr_port[] = {
1625         {
1626                 .type = SWITCH_TYPE_NOVAL,
1627                 .name = "reset_mib",
1628                 .description = "Reset single port MIB counters",
1629                 .set = ar8xxx_sw_set_port_reset_mib,
1630         },
1631         {
1632                 .type = SWITCH_TYPE_STRING,
1633                 .name = "mib",
1634                 .description = "Get port's MIB counters",
1635                 .set = NULL,
1636                 .get = ar8xxx_sw_get_port_mib,
1637         },
1638         {
1639                 .type = SWITCH_TYPE_NOVAL,
1640                 .name = "flush_arl_table",
1641                 .description = "Flush port's ARL table entries",
1642                 .set = ar8xxx_sw_set_flush_port_arl_table,
1643         },
1644 };
1645
1646 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1647         {
1648                 .type = SWITCH_TYPE_INT,
1649                 .name = "vid",
1650                 .description = "VLAN ID (0-4094)",
1651                 .set = ar8xxx_sw_set_vid,
1652                 .get = ar8xxx_sw_get_vid,
1653                 .max = 4094,
1654         },
1655 };
1656
1657 static const struct switch_dev_ops ar8xxx_sw_ops = {
1658         .attr_global = {
1659                 .attr = ar8xxx_sw_attr_globals,
1660                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1661         },
1662         .attr_port = {
1663                 .attr = ar8xxx_sw_attr_port,
1664                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1665         },
1666         .attr_vlan = {
1667                 .attr = ar8xxx_sw_attr_vlan,
1668                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1669         },
1670         .get_port_pvid = ar8xxx_sw_get_pvid,
1671         .set_port_pvid = ar8xxx_sw_set_pvid,
1672         .get_vlan_ports = ar8xxx_sw_get_ports,
1673         .set_vlan_ports = ar8xxx_sw_set_ports,
1674         .apply_config = ar8xxx_sw_hw_apply,
1675         .reset_switch = ar8xxx_sw_reset_switch,
1676         .get_port_link = ar8xxx_sw_get_port_link,
1677 };
1678
1679 static const struct ar8xxx_chip ar8216_chip = {
1680         .caps = AR8XXX_CAP_MIB_COUNTERS,
1681
1682         .reg_port_stats_start = 0x19000,
1683         .reg_port_stats_length = 0xa0,
1684         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1685
1686         .name = "Atheros AR8216",
1687         .ports = AR8216_NUM_PORTS,
1688         .vlans = AR8216_NUM_VLANS,
1689         .swops = &ar8xxx_sw_ops,
1690
1691         .hw_init = ar8216_hw_init,
1692         .init_globals = ar8216_init_globals,
1693         .init_port = ar8216_init_port,
1694         .setup_port = ar8216_setup_port,
1695         .read_port_status = ar8216_read_port_status,
1696         .atu_flush = ar8216_atu_flush,
1697         .atu_flush_port = ar8216_atu_flush_port,
1698         .vtu_flush = ar8216_vtu_flush,
1699         .vtu_load_vlan = ar8216_vtu_load_vlan,
1700         .set_mirror_regs = ar8216_set_mirror_regs,
1701         .get_arl_entry = ar8216_get_arl_entry,
1702         .sw_hw_apply = ar8xxx_sw_hw_apply,
1703
1704         .num_mibs = ARRAY_SIZE(ar8216_mibs),
1705         .mib_decs = ar8216_mibs,
1706         .mib_func = AR8216_REG_MIB_FUNC
1707 };
1708
1709 static const struct ar8xxx_chip ar8236_chip = {
1710         .caps = AR8XXX_CAP_MIB_COUNTERS,
1711
1712         .reg_port_stats_start = 0x20000,
1713         .reg_port_stats_length = 0x100,
1714         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1715
1716         .name = "Atheros AR8236",
1717         .ports = AR8216_NUM_PORTS,
1718         .vlans = AR8216_NUM_VLANS,
1719         .swops = &ar8xxx_sw_ops,
1720
1721         .hw_init = ar8216_hw_init,
1722         .init_globals = ar8236_init_globals,
1723         .init_port = ar8216_init_port,
1724         .setup_port = ar8236_setup_port,
1725         .read_port_status = ar8216_read_port_status,
1726         .atu_flush = ar8216_atu_flush,
1727         .atu_flush_port = ar8216_atu_flush_port,
1728         .vtu_flush = ar8216_vtu_flush,
1729         .vtu_load_vlan = ar8216_vtu_load_vlan,
1730         .set_mirror_regs = ar8216_set_mirror_regs,
1731         .get_arl_entry = ar8216_get_arl_entry,
1732         .sw_hw_apply = ar8xxx_sw_hw_apply,
1733
1734         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1735         .mib_decs = ar8236_mibs,
1736         .mib_func = AR8216_REG_MIB_FUNC
1737 };
1738
1739 static const struct ar8xxx_chip ar8316_chip = {
1740         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1741
1742         .reg_port_stats_start = 0x20000,
1743         .reg_port_stats_length = 0x100,
1744         .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1745
1746         .name = "Atheros AR8316",
1747         .ports = AR8216_NUM_PORTS,
1748         .vlans = AR8X16_MAX_VLANS,
1749         .swops = &ar8xxx_sw_ops,
1750
1751         .hw_init = ar8316_hw_init,
1752         .init_globals = ar8316_init_globals,
1753         .init_port = ar8216_init_port,
1754         .setup_port = ar8216_setup_port,
1755         .read_port_status = ar8216_read_port_status,
1756         .atu_flush = ar8216_atu_flush,
1757         .atu_flush_port = ar8216_atu_flush_port,
1758         .vtu_flush = ar8216_vtu_flush,
1759         .vtu_load_vlan = ar8216_vtu_load_vlan,
1760         .set_mirror_regs = ar8216_set_mirror_regs,
1761         .get_arl_entry = ar8216_get_arl_entry,
1762         .sw_hw_apply = ar8xxx_sw_hw_apply,
1763
1764         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1765         .mib_decs = ar8236_mibs,
1766         .mib_func = AR8216_REG_MIB_FUNC
1767 };
1768
1769 static int
1770 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1771 {
1772         u32 val;
1773         u16 id;
1774         int i;
1775
1776         val = ar8xxx_read(priv, AR8216_REG_CTRL);
1777         if (val == ~0)
1778                 return -ENODEV;
1779
1780         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1781         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1782                 u16 t;
1783
1784                 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1785                 if (val == ~0)
1786                         return -ENODEV;
1787
1788                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1789                 if (t != id)
1790                         return -ENODEV;
1791         }
1792
1793         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1794         priv->chip_rev = (id & AR8216_CTRL_REVISION);
1795
1796         switch (priv->chip_ver) {
1797         case AR8XXX_VER_AR8216:
1798                 priv->chip = &ar8216_chip;
1799                 break;
1800         case AR8XXX_VER_AR8236:
1801                 priv->chip = &ar8236_chip;
1802                 break;
1803         case AR8XXX_VER_AR8316:
1804                 priv->chip = &ar8316_chip;
1805                 break;
1806         case AR8XXX_VER_AR8327:
1807                 priv->chip = &ar8327_chip;
1808                 break;
1809         case AR8XXX_VER_AR8337:
1810                 priv->chip = &ar8337_chip;
1811                 break;
1812         default:
1813                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1814                        priv->chip_ver, priv->chip_rev);
1815
1816                 return -ENODEV;
1817         }
1818
1819         return 0;
1820 }
1821
1822 static void
1823 ar8xxx_mib_work_func(struct work_struct *work)
1824 {
1825         struct ar8xxx_priv *priv;
1826         int err;
1827
1828         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1829
1830         mutex_lock(&priv->mib_lock);
1831
1832         err = ar8xxx_mib_capture(priv);
1833         if (err)
1834                 goto next_port;
1835
1836         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1837
1838 next_port:
1839         priv->mib_next_port++;
1840         if (priv->mib_next_port >= priv->dev.ports)
1841                 priv->mib_next_port = 0;
1842
1843         mutex_unlock(&priv->mib_lock);
1844         schedule_delayed_work(&priv->mib_work,
1845                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1846 }
1847
1848 static int
1849 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1850 {
1851         unsigned int len;
1852
1853         if (!ar8xxx_has_mib_counters(priv))
1854                 return 0;
1855
1856         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1857
1858         len = priv->dev.ports * priv->chip->num_mibs *
1859               sizeof(*priv->mib_stats);
1860         priv->mib_stats = kzalloc(len, GFP_KERNEL);
1861
1862         if (!priv->mib_stats)
1863                 return -ENOMEM;
1864
1865         return 0;
1866 }
1867
1868 static void
1869 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1870 {
1871         if (!ar8xxx_has_mib_counters(priv))
1872                 return;
1873
1874         schedule_delayed_work(&priv->mib_work,
1875                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1876 }
1877
1878 static void
1879 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1880 {
1881         if (!ar8xxx_has_mib_counters(priv))
1882                 return;
1883
1884         cancel_delayed_work(&priv->mib_work);
1885 }
1886
1887 static struct ar8xxx_priv *
1888 ar8xxx_create(void)
1889 {
1890         struct ar8xxx_priv *priv;
1891
1892         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1893         if (priv == NULL)
1894                 return NULL;
1895
1896         mutex_init(&priv->reg_mutex);
1897         mutex_init(&priv->mib_lock);
1898         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1899
1900         return priv;
1901 }
1902
1903 static void
1904 ar8xxx_free(struct ar8xxx_priv *priv)
1905 {
1906         if (priv->chip && priv->chip->cleanup)
1907                 priv->chip->cleanup(priv);
1908
1909         kfree(priv->chip_data);
1910         kfree(priv->mib_stats);
1911         kfree(priv);
1912 }
1913
1914 static int
1915 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1916 {
1917         const struct ar8xxx_chip *chip;
1918         struct switch_dev *swdev;
1919         int ret;
1920
1921         ret = ar8xxx_id_chip(priv);
1922         if (ret)
1923                 return ret;
1924
1925         chip = priv->chip;
1926
1927         swdev = &priv->dev;
1928         swdev->cpu_port = AR8216_PORT_CPU;
1929         swdev->name = chip->name;
1930         swdev->vlans = chip->vlans;
1931         swdev->ports = chip->ports;
1932         swdev->ops = chip->swops;
1933
1934         ret = ar8xxx_mib_init(priv);
1935         if (ret)
1936                 return ret;
1937
1938         return 0;
1939 }
1940
1941 static int
1942 ar8xxx_start(struct ar8xxx_priv *priv)
1943 {
1944         int ret;
1945
1946         priv->init = true;
1947
1948         ret = priv->chip->hw_init(priv);
1949         if (ret)
1950                 return ret;
1951
1952         ret = ar8xxx_sw_reset_switch(&priv->dev);
1953         if (ret)
1954                 return ret;
1955
1956         priv->init = false;
1957
1958         ar8xxx_mib_start(priv);
1959
1960         return 0;
1961 }
1962
1963 static int
1964 ar8xxx_phy_config_init(struct phy_device *phydev)
1965 {
1966         struct ar8xxx_priv *priv = phydev->priv;
1967         struct net_device *dev = phydev->attached_dev;
1968         int ret;
1969
1970         if (WARN_ON(!priv))
1971                 return -ENODEV;
1972
1973         if (priv->chip->config_at_probe)
1974                 return ar8xxx_phy_check_aneg(phydev);
1975
1976         priv->phy = phydev;
1977
1978         if (phydev->addr != 0) {
1979                 if (chip_is_ar8316(priv)) {
1980                         /* switch device has been initialized, reinit */
1981                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
1982                         priv->initialized = false;
1983                         priv->port4_phy = true;
1984                         ar8316_hw_init(priv);
1985                         return 0;
1986                 }
1987
1988                 return 0;
1989         }
1990
1991         ret = ar8xxx_start(priv);
1992         if (ret)
1993                 return ret;
1994
1995         /* VID fixup only needed on ar8216 */
1996         if (chip_is_ar8216(priv)) {
1997                 dev->phy_ptr = priv;
1998                 dev->priv_flags |= IFF_NO_IP_ALIGN;
1999                 dev->eth_mangle_rx = ar8216_mangle_rx;
2000                 dev->eth_mangle_tx = ar8216_mangle_tx;
2001         }
2002
2003         return 0;
2004 }
2005
2006 static bool
2007 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2008 {
2009         bool link_new, changed = false;
2010         u32 status;
2011         int i;
2012
2013         mutex_lock(&priv->reg_mutex);
2014
2015         for (i = 0; i < priv->dev.ports; i++) {
2016                 status = priv->chip->read_port_status(priv, i);
2017                 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2018                 if (link_new == priv->link_up[i])
2019                         continue;
2020
2021                 priv->link_up[i] = link_new;
2022                 changed = true;
2023                 /* flush ARL entries for this port if it went down*/
2024                 if (!link_new)
2025                         priv->chip->atu_flush_port(priv, i);
2026                 dev_info(&priv->phy->dev, "Port %d is %s\n",
2027                          i, link_new ? "up" : "down");
2028         }
2029
2030         mutex_unlock(&priv->reg_mutex);
2031
2032         return changed;
2033 }
2034
2035 static int
2036 ar8xxx_phy_read_status(struct phy_device *phydev)
2037 {
2038         struct ar8xxx_priv *priv = phydev->priv;
2039         struct switch_port_link link;
2040
2041         /* check for switch port link changes */
2042         if (phydev->state == PHY_CHANGELINK)
2043                 ar8xxx_check_link_states(priv);
2044
2045         if (phydev->addr != 0)
2046                 return genphy_read_status(phydev);
2047
2048         ar8216_read_port_link(priv, phydev->addr, &link);
2049         phydev->link = !!link.link;
2050         if (!phydev->link)
2051                 return 0;
2052
2053         switch (link.speed) {
2054         case SWITCH_PORT_SPEED_10:
2055                 phydev->speed = SPEED_10;
2056                 break;
2057         case SWITCH_PORT_SPEED_100:
2058                 phydev->speed = SPEED_100;
2059                 break;
2060         case SWITCH_PORT_SPEED_1000:
2061                 phydev->speed = SPEED_1000;
2062                 break;
2063         default:
2064                 phydev->speed = 0;
2065         }
2066         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2067
2068         phydev->state = PHY_RUNNING;
2069         netif_carrier_on(phydev->attached_dev);
2070         phydev->adjust_link(phydev->attached_dev);
2071
2072         return 0;
2073 }
2074
2075 static int
2076 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2077 {
2078         if (phydev->addr == 0)
2079                 return 0;
2080
2081         return genphy_config_aneg(phydev);
2082 }
2083
2084 static const u32 ar8xxx_phy_ids[] = {
2085         0x004dd033,
2086         0x004dd034, /* AR8327 */
2087         0x004dd036, /* AR8337 */
2088         0x004dd041,
2089         0x004dd042,
2090         0x004dd043, /* AR8236 */
2091 };
2092
2093 static bool
2094 ar8xxx_phy_match(u32 phy_id)
2095 {
2096         int i;
2097
2098         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2099                 if (phy_id == ar8xxx_phy_ids[i])
2100                         return true;
2101
2102         return false;
2103 }
2104
2105 static bool
2106 ar8xxx_is_possible(struct mii_bus *bus)
2107 {
2108         unsigned i;
2109
2110         for (i = 0; i < 4; i++) {
2111                 u32 phy_id;
2112
2113                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2114                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2115                 if (!ar8xxx_phy_match(phy_id)) {
2116                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2117                                  dev_name(&bus->dev), i, phy_id);
2118                         return false;
2119                 }
2120         }
2121
2122         return true;
2123 }
2124
2125 static int
2126 ar8xxx_phy_probe(struct phy_device *phydev)
2127 {
2128         struct ar8xxx_priv *priv;
2129         struct switch_dev *swdev;
2130         int ret;
2131
2132         /* skip PHYs at unused adresses */
2133         if (phydev->addr != 0 && phydev->addr != 4)
2134                 return -ENODEV;
2135
2136         if (!ar8xxx_is_possible(phydev->bus))
2137                 return -ENODEV;
2138
2139         mutex_lock(&ar8xxx_dev_list_lock);
2140         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2141                 if (priv->mii_bus == phydev->bus)
2142                         goto found;
2143
2144         priv = ar8xxx_create();
2145         if (priv == NULL) {
2146                 ret = -ENOMEM;
2147                 goto unlock;
2148         }
2149
2150         priv->mii_bus = phydev->bus;
2151
2152         ret = ar8xxx_probe_switch(priv);
2153         if (ret)
2154                 goto free_priv;
2155
2156         swdev = &priv->dev;
2157         swdev->alias = dev_name(&priv->mii_bus->dev);
2158         ret = register_switch(swdev, NULL);
2159         if (ret)
2160                 goto free_priv;
2161
2162         pr_info("%s: %s rev. %u switch registered on %s\n",
2163                 swdev->devname, swdev->name, priv->chip_rev,
2164                 dev_name(&priv->mii_bus->dev));
2165
2166 found:
2167         priv->use_count++;
2168
2169         if (phydev->addr == 0) {
2170                 if (ar8xxx_has_gige(priv)) {
2171                         phydev->supported = SUPPORTED_1000baseT_Full;
2172                         phydev->advertising = ADVERTISED_1000baseT_Full;
2173                 } else {
2174                         phydev->supported = SUPPORTED_100baseT_Full;
2175                         phydev->advertising = ADVERTISED_100baseT_Full;
2176                 }
2177
2178                 if (priv->chip->config_at_probe) {
2179                         priv->phy = phydev;
2180
2181                         ret = ar8xxx_start(priv);
2182                         if (ret)
2183                                 goto err_unregister_switch;
2184                 }
2185         } else {
2186                 if (ar8xxx_has_gige(priv)) {
2187                         phydev->supported |= SUPPORTED_1000baseT_Full;
2188                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2189                 }
2190         }
2191
2192         phydev->priv = priv;
2193
2194         list_add(&priv->list, &ar8xxx_dev_list);
2195
2196         mutex_unlock(&ar8xxx_dev_list_lock);
2197
2198         return 0;
2199
2200 err_unregister_switch:
2201         if (--priv->use_count)
2202                 goto unlock;
2203
2204         unregister_switch(&priv->dev);
2205
2206 free_priv:
2207         ar8xxx_free(priv);
2208 unlock:
2209         mutex_unlock(&ar8xxx_dev_list_lock);
2210         return ret;
2211 }
2212
2213 static void
2214 ar8xxx_phy_detach(struct phy_device *phydev)
2215 {
2216         struct net_device *dev = phydev->attached_dev;
2217
2218         if (!dev)
2219                 return;
2220
2221         dev->phy_ptr = NULL;
2222         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2223         dev->eth_mangle_rx = NULL;
2224         dev->eth_mangle_tx = NULL;
2225 }
2226
2227 static void
2228 ar8xxx_phy_remove(struct phy_device *phydev)
2229 {
2230         struct ar8xxx_priv *priv = phydev->priv;
2231
2232         if (WARN_ON(!priv))
2233                 return;
2234
2235         phydev->priv = NULL;
2236         if (--priv->use_count > 0)
2237                 return;
2238
2239         mutex_lock(&ar8xxx_dev_list_lock);
2240         list_del(&priv->list);
2241         mutex_unlock(&ar8xxx_dev_list_lock);
2242
2243         unregister_switch(&priv->dev);
2244         ar8xxx_mib_stop(priv);
2245         ar8xxx_free(priv);
2246 }
2247
2248 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2249 static int
2250 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2251 {
2252         /* we don't need an extra reset */
2253         return 0;
2254 }
2255 #endif
2256
2257 static struct phy_driver ar8xxx_phy_driver = {
2258         .phy_id         = 0x004d0000,
2259         .name           = "Atheros AR8216/AR8236/AR8316",
2260         .phy_id_mask    = 0xffff0000,
2261         .features       = PHY_BASIC_FEATURES,
2262         .probe          = ar8xxx_phy_probe,
2263         .remove         = ar8xxx_phy_remove,
2264         .detach         = ar8xxx_phy_detach,
2265         .config_init    = ar8xxx_phy_config_init,
2266         .config_aneg    = ar8xxx_phy_config_aneg,
2267         .read_status    = ar8xxx_phy_read_status,
2268 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2269         .soft_reset     = ar8xxx_phy_soft_reset,
2270 #endif
2271         .driver         = { .owner = THIS_MODULE },
2272 };
2273
2274 int __init
2275 ar8xxx_init(void)
2276 {
2277         return phy_driver_register(&ar8xxx_phy_driver);
2278 }
2279
2280 void __exit
2281 ar8xxx_exit(void)
2282 {
2283         phy_driver_unregister(&ar8xxx_phy_driver);
2284 }
2285
2286 module_init(ar8xxx_init);
2287 module_exit(ar8xxx_exit);
2288 MODULE_LICENSE("GPL");
2289