target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of_device.h>
  37
  38 #include "ar8216.h"
  39
  40 /* size of the vlan table */
  41 #define AR8X16_MAX_VLANS        128
  42 #define AR8X16_PROBE_RETRIES    10
  43 #define AR8X16_MAX_PORTS        8
  44
  45 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  46
  47 struct ar8xxx_priv;
  48
  49 #define AR8XXX_CAP_GIGE                 BIT(0)
  50 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  51
  52 enum {
  53         AR8XXX_VER_AR8216 = 0x01,
  54         AR8XXX_VER_AR8236 = 0x03,
  55         AR8XXX_VER_AR8316 = 0x10,
  56         AR8XXX_VER_AR8327 = 0x12,
  57         AR8XXX_VER_AR8337 = 0x13,
  58 };
  59
  60 struct ar8xxx_mib_desc {
  61         unsigned int size;
  62         unsigned int offset;
  63         const char *name;
  64 };
  65
  66 struct ar8xxx_chip {
  67         unsigned long caps;
  68
  69         int (*hw_init)(struct ar8xxx_priv *priv);
  70         void (*init_globals)(struct ar8xxx_priv *priv);
  71         void (*init_port)(struct ar8xxx_priv *priv, int port);
  72         void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 egress,
  73                            u32 ingress, u32 members, u32 pvid);
  74         u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  75         int (*atu_flush)(struct ar8xxx_priv *priv);
  76         void (*vtu_flush)(struct ar8xxx_priv *priv);
  77         void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
  78
  79         const struct ar8xxx_mib_desc *mib_decs;
  80         unsigned num_mibs;
  81 };
  82
  83 struct ar8327_data {
  84         u32 port0_status;
  85         u32 port6_status;
  86 };
  87
  88 struct ar8xxx_priv {
  89         struct switch_dev dev;
  90         struct mii_bus *mii_bus;
  91         struct phy_device *phy;
  92
  93         u32 (*read)(struct ar8xxx_priv *priv, int reg);
  94         void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
  95
  96         int (*get_port_link)(unsigned port);
  97
  98         const struct net_device_ops *ndo_old;
  99         struct net_device_ops ndo;
 100         struct mutex reg_mutex;
 101         u8 chip_ver;
 102         u8 chip_rev;
 103         const struct ar8xxx_chip *chip;
 104         union {
 105                 struct ar8327_data ar8327;
 106         } chip_data;
 107         bool initialized;
 108         bool port4_phy;
 109         char buf[2048];
 110
 111         bool init;
 112         bool mii_lo_first;
 113
 114         struct mutex mib_lock;
 115         struct delayed_work mib_work;
 116         int mib_next_port;
 117         u64 *mib_stats;
 118
 119         struct list_head list;
 120         unsigned int use_count;
 121
 122         /* all fields below are cleared on reset */
 123         bool vlan;
 124         u16 vlan_id[AR8X16_MAX_VLANS];
 125         u8 vlan_table[AR8X16_MAX_VLANS];
 126         u8 vlan_tagged;
 127         u16 pvid[AR8X16_MAX_PORTS];
 128
 129         /* mirroring */
 130         bool mirror_rx;
 131         bool mirror_tx;
 132         int source_port;
 133         int monitor_port;
 134 };
 135
 136 #define MIB_DESC(_s , _o, _n)   \
 137         {                       \
 138                 .size = (_s),   \
 139                 .offset = (_o), \
 140                 .name = (_n),   \
 141         }
 142
 143 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
 144         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 145         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 146         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 147         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 148         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 149         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 150         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 151         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 152         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 153         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 154         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 155         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 156         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 157         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 158         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 159         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 160         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 161         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 162         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 163         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 164         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 165         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 166         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 167         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 168         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 169         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 170         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 171         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 172         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 173         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 174         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 175         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 176         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 177         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 178         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 179         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 180         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 181 };
 182
 183 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 184         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 185         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 186         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 187         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 188         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 189         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 190         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 191         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 192         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 193         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 194         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 195         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 196         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 197         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 198         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 199         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 200         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 201         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 202         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 203         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 204         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 205         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 206         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 207         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 208         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 209         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 210         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 211         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 212         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 213         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 214         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 215         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 216         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 217         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 218         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 219         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 220         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 221         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 222         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 223 };
 224
 225 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 226 static LIST_HEAD(ar8xxx_dev_list);
 227
 228 static inline struct ar8xxx_priv *
 229 swdev_to_ar8xxx(struct switch_dev *swdev)
 230 {
 231         return container_of(swdev, struct ar8xxx_priv, dev);
 232 }
 233
 234 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
 235 {
 236         return priv->chip->caps & AR8XXX_CAP_GIGE;
 237 }
 238
 239 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
 240 {
 241         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 242 }
 243
 244 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
 245 {
 246         return priv->chip_ver == AR8XXX_VER_AR8216;
 247 }
 248
 249 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
 250 {
 251         return priv->chip_ver == AR8XXX_VER_AR8236;
 252 }
 253
 254 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
 255 {
 256         return priv->chip_ver == AR8XXX_VER_AR8316;
 257 }
 258
 259 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
 260 {
 261         return priv->chip_ver == AR8XXX_VER_AR8327;
 262 }
 263
 264 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
 265 {
 266         return priv->chip_ver == AR8XXX_VER_AR8337;
 267 }
 268
 269 static inline void
 270 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 271 {
 272         regaddr >>= 1;
 273         *r1 = regaddr & 0x1e;
 274
 275         regaddr >>= 5;
 276         *r2 = regaddr & 0x7;
 277
 278         regaddr >>= 3;
 279         *page = regaddr & 0x1ff;
 280 }
 281
 282 static u32
 283 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
 284 {
 285         struct mii_bus *bus = priv->mii_bus;
 286         u16 r1, r2, page;
 287         u16 lo, hi;
 288
 289         split_addr((u32) reg, &r1, &r2, &page);
 290
 291         mutex_lock(&bus->mdio_lock);
 292
 293         bus->write(bus, 0x18, 0, page);
 294         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 295         lo = bus->read(bus, 0x10 | r2, r1);
 296         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 297
 298         mutex_unlock(&bus->mdio_lock);
 299
 300         return (hi << 16) | lo;
 301 }
 302
 303 static void
 304 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
 305 {
 306         struct mii_bus *bus = priv->mii_bus;
 307         u16 r1, r2, r3;
 308         u16 lo, hi;
 309
 310         split_addr((u32) reg, &r1, &r2, &r3);
 311         lo = val & 0xffff;
 312         hi = (u16) (val >> 16);
 313
 314         mutex_lock(&bus->mdio_lock);
 315
 316         bus->write(bus, 0x18, 0, r3);
 317         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 318         if (priv->mii_lo_first) {
 319                 bus->write(bus, 0x10 | r2, r1, lo);
 320                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 321         } else {
 322                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 323                 bus->write(bus, 0x10 | r2, r1, lo);
 324         }
 325
 326         mutex_unlock(&bus->mdio_lock);
 327 }
 328
 329 static void
 330 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 331                      u16 dbg_addr, u16 dbg_data)
 332 {
 333         struct mii_bus *bus = priv->mii_bus;
 334
 335         mutex_lock(&bus->mdio_lock);
 336         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 337         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 338         mutex_unlock(&bus->mdio_lock);
 339 }
 340
 341 static void
 342 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 343 {
 344         struct mii_bus *bus = priv->mii_bus;
 345
 346         mutex_lock(&bus->mdio_lock);
 347         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 348         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 349         mutex_unlock(&bus->mdio_lock);
 350 }
 351
 352 static u32
 353 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 354 {
 355         u32 v;
 356
 357         lockdep_assert_held(&priv->reg_mutex);
 358
 359         v = priv->read(priv, reg);
 360         v &= ~mask;
 361         v |= val;
 362         priv->write(priv, reg, v);
 363
 364         return v;
 365 }
 366
 367 static inline void
 368 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
 369 {
 370         u32 v;
 371
 372         lockdep_assert_held(&priv->reg_mutex);
 373
 374         v = priv->read(priv, reg);
 375         v |= val;
 376         priv->write(priv, reg, v);
 377 }
 378
 379 static int
 380 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 381                 unsigned timeout)
 382 {
 383         int i;
 384
 385         for (i = 0; i < timeout; i++) {
 386                 u32 t;
 387
 388                 t = priv->read(priv, reg);
 389                 if ((t & mask) == val)
 390                         return 0;
 391
 392                 usleep_range(1000, 2000);
 393         }
 394
 395         return -ETIMEDOUT;
 396 }
 397
 398 static int
 399 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 400 {
 401         unsigned mib_func;
 402         int ret;
 403
 404         lockdep_assert_held(&priv->mib_lock);
 405
 406         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
 407                 mib_func = AR8327_REG_MIB_FUNC;
 408         else
 409                 mib_func = AR8216_REG_MIB_FUNC;
 410
 411         mutex_lock(&priv->reg_mutex);
 412         /* Capture the hardware statistics for all ports */
 413         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 414         mutex_unlock(&priv->reg_mutex);
 415
 416         /* Wait for the capturing to complete. */
 417         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 418         if (ret)
 419                 goto out;
 420
 421         ret = 0;
 422
 423 out:
 424         return ret;
 425 }
 426
 427 static int
 428 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 429 {
 430         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 431 }
 432
 433 static int
 434 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 435 {
 436         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 437 }
 438
 439 static void
 440 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 441 {
 442         unsigned int base;
 443         u64 *mib_stats;
 444         int i;
 445
 446         WARN_ON(port >= priv->dev.ports);
 447
 448         lockdep_assert_held(&priv->mib_lock);
 449
 450         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
 451                 base = AR8327_REG_PORT_STATS_BASE(port);
 452         else if (chip_is_ar8236(priv) ||
 453                  chip_is_ar8316(priv))
 454                 base = AR8236_REG_PORT_STATS_BASE(port);
 455         else
 456                 base = AR8216_REG_PORT_STATS_BASE(port);
 457
 458         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 459         for (i = 0; i < priv->chip->num_mibs; i++) {
 460                 const struct ar8xxx_mib_desc *mib;
 461                 u64 t;
 462
 463                 mib = &priv->chip->mib_decs[i];
 464                 t = priv->read(priv, base + mib->offset);
 465                 if (mib->size == 2) {
 466                         u64 hi;
 467
 468                         hi = priv->read(priv, base + mib->offset + 4);
 469                         t |= hi << 32;
 470                 }
 471
 472                 if (flush)
 473                         mib_stats[i] = 0;
 474                 else
 475                         mib_stats[i] += t;
 476         }
 477 }
 478
 479 static void
 480 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 481                       struct switch_port_link *link)
 482 {
 483         u32 status;
 484         u32 speed;
 485
 486         memset(link, '\0', sizeof(*link));
 487
 488         status = priv->chip->read_port_status(priv, port);
 489
 490         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 491         if (link->aneg) {
 492                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 493         } else {
 494                 link->link = true;
 495
 496                 if (priv->get_port_link) {
 497                         int err;
 498
 499                         err = priv->get_port_link(port);
 500                         if (err >= 0)
 501                                 link->link = !!err;
 502                 }
 503         }
 504
 505         if (!link->link)
 506                 return;
 507
 508         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 509         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 510         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 511
 512         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 513                  AR8216_PORT_STATUS_SPEED_S;
 514
 515         switch (speed) {
 516         case AR8216_PORT_SPEED_10M:
 517                 link->speed = SWITCH_PORT_SPEED_10;
 518                 break;
 519         case AR8216_PORT_SPEED_100M:
 520                 link->speed = SWITCH_PORT_SPEED_100;
 521                 break;
 522         case AR8216_PORT_SPEED_1000M:
 523                 link->speed = SWITCH_PORT_SPEED_1000;
 524                 break;
 525         default:
 526                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 527                 break;
 528         }
 529 }
 530
 531 static struct sk_buff *
 532 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 533 {
 534         struct ar8xxx_priv *priv = dev->phy_ptr;
 535         unsigned char *buf;
 536
 537         if (unlikely(!priv))
 538                 goto error;
 539
 540         if (!priv->vlan)
 541                 goto send;
 542
 543         if (unlikely(skb_headroom(skb) < 2)) {
 544                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 545                         goto error;
 546         }
 547
 548         buf = skb_push(skb, 2);
 549         buf[0] = 0x10;
 550         buf[1] = 0x80;
 551
 552 send:
 553         return skb;
 554
 555 error:
 556         dev_kfree_skb_any(skb);
 557         return NULL;
 558 }
 559
 560 static void
 561 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 562 {
 563         struct ar8xxx_priv *priv;
 564         unsigned char *buf;
 565         int port, vlan;
 566
 567         priv = dev->phy_ptr;
 568         if (!priv)
 569                 return;
 570
 571         /* don't strip the header if vlan mode is disabled */
 572         if (!priv->vlan)
 573                 return;
 574
 575         /* strip header, get vlan id */
 576         buf = skb->data;
 577         skb_pull(skb, 2);
 578
 579         /* check for vlan header presence */
 580         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 581                 return;
 582
 583         port = buf[0] & 0xf;
 584
 585         /* no need to fix up packets coming from a tagged source */
 586         if (priv->vlan_tagged & (1 << port))
 587                 return;
 588
 589         /* lookup port vid from local table, the switch passes an invalid vlan id */
 590         vlan = priv->vlan_id[priv->pvid[port]];
 591
 592         buf[14 + 2] &= 0xf0;
 593         buf[14 + 2] |= vlan >> 8;
 594         buf[15 + 2] = vlan & 0xff;
 595 }
 596
 597 static int
 598 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 599 {
 600         int timeout = 20;
 601         u32 t = 0;
 602
 603         while (1) {
 604                 t = priv->read(priv, reg);
 605                 if ((t & mask) == val)
 606                         return 0;
 607
 608                 if (timeout-- <= 0)
 609                         break;
 610
 611                 udelay(10);
 612         }
 613
 614         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 615                (unsigned int) reg, t, mask, val);
 616         return -ETIMEDOUT;
 617 }
 618
 619 static void
 620 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 621 {
 622         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 623                 return;
 624         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 625                 val &= AR8216_VTUDATA_MEMBER;
 626                 val |= AR8216_VTUDATA_VALID;
 627                 priv->write(priv, AR8216_REG_VTU_DATA, val);
 628         }
 629         op |= AR8216_VTU_ACTIVE;
 630         priv->write(priv, AR8216_REG_VTU, op);
 631 }
 632
 633 static void
 634 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 635 {
 636         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 637 }
 638
 639 static void
 640 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 641 {
 642         u32 op;
 643
 644         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 645         ar8216_vtu_op(priv, op, port_mask);
 646 }
 647
 648 static int
 649 ar8216_atu_flush(struct ar8xxx_priv *priv)
 650 {
 651         int ret;
 652
 653         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 654         if (!ret)
 655                 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 656
 657         return ret;
 658 }
 659
 660 static u32
 661 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 662 {
 663         return priv->read(priv, AR8216_REG_PORT_STATUS(port));
 664 }
 665
 666 static void
 667 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
 668                   u32 members, u32 pvid)
 669 {
 670         u32 header;
 671
 672         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 673                 header = AR8216_PORT_CTRL_HEADER;
 674         else
 675                 header = 0;
 676
 677         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 678                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 679                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 680                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 681                    AR8216_PORT_CTRL_LEARN | header |
 682                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 683                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 684
 685         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 686                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 687                    AR8216_PORT_VLAN_DEFAULT_ID,
 688                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 689                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 690                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 691 }
 692
 693 static int
 694 ar8216_hw_init(struct ar8xxx_priv *priv)
 695 {
 696         return 0;
 697 }
 698
 699 static void
 700 ar8216_init_globals(struct ar8xxx_priv *priv)
 701 {
 702         /* standard atheros magic */
 703         priv->write(priv, 0x38, 0xc000050e);
 704
 705         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 706                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 707 }
 708
 709 static void
 710 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 711 {
 712         /* Enable port learning and tx */
 713         priv->write(priv, AR8216_REG_PORT_CTRL(port),
 714                 AR8216_PORT_CTRL_LEARN |
 715                 (4 << AR8216_PORT_CTRL_STATE_S));
 716
 717         priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
 718
 719         if (port == AR8216_PORT_CPU) {
 720                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 721                         AR8216_PORT_STATUS_LINK_UP |
 722                         (ar8xxx_has_gige(priv) ?
 723                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 724                         AR8216_PORT_STATUS_TXMAC |
 725                         AR8216_PORT_STATUS_RXMAC |
 726                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 727                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 728                         AR8216_PORT_STATUS_DUPLEX);
 729         } else {
 730                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 731                         AR8216_PORT_STATUS_LINK_AUTO);
 732         }
 733 }
 734
 735 static const struct ar8xxx_chip ar8216_chip = {
 736         .caps = AR8XXX_CAP_MIB_COUNTERS,
 737
 738         .hw_init = ar8216_hw_init,
 739         .init_globals = ar8216_init_globals,
 740         .init_port = ar8216_init_port,
 741         .setup_port = ar8216_setup_port,
 742         .read_port_status = ar8216_read_port_status,
 743         .atu_flush = ar8216_atu_flush,
 744         .vtu_flush = ar8216_vtu_flush,
 745         .vtu_load_vlan = ar8216_vtu_load_vlan,
 746
 747         .num_mibs = ARRAY_SIZE(ar8216_mibs),
 748         .mib_decs = ar8216_mibs,
 749 };
 750
 751 static void
 752 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
 753                   u32 members, u32 pvid)
 754 {
 755         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 756                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 757                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 758                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 759                    AR8216_PORT_CTRL_LEARN |
 760                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 761                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 762
 763         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 764                    AR8236_PORT_VLAN_DEFAULT_ID,
 765                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 766
 767         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 768                    AR8236_PORT_VLAN2_VLAN_MODE |
 769                    AR8236_PORT_VLAN2_MEMBER,
 770                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 771                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 772 }
 773
 774 static int
 775 ar8236_hw_init(struct ar8xxx_priv *priv)
 776 {
 777         int i;
 778         struct mii_bus *bus;
 779
 780         if (priv->initialized)
 781                 return 0;
 782
 783         /* Initialize the PHYs */
 784         bus = priv->mii_bus;
 785         for (i = 0; i < 5; i++) {
 786                 mdiobus_write(bus, i, MII_ADVERTISE,
 787                               ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
 788                               ADVERTISE_PAUSE_ASYM);
 789                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 790         }
 791         msleep(1000);
 792
 793         priv->initialized = true;
 794         return 0;
 795 }
 796
 797 static void
 798 ar8236_init_globals(struct ar8xxx_priv *priv)
 799 {
 800         /* enable jumbo frames */
 801         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 802                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 803
 804         /* Enable MIB counters */
 805         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 806                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 807                    AR8236_MIB_EN);
 808 }
 809
 810 static const struct ar8xxx_chip ar8236_chip = {
 811         .caps = AR8XXX_CAP_MIB_COUNTERS,
 812         .hw_init = ar8236_hw_init,
 813         .init_globals = ar8236_init_globals,
 814         .init_port = ar8216_init_port,
 815         .setup_port = ar8236_setup_port,
 816         .read_port_status = ar8216_read_port_status,
 817         .atu_flush = ar8216_atu_flush,
 818         .vtu_flush = ar8216_vtu_flush,
 819         .vtu_load_vlan = ar8216_vtu_load_vlan,
 820
 821         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 822         .mib_decs = ar8236_mibs,
 823 };
 824
 825 static int
 826 ar8316_hw_init(struct ar8xxx_priv *priv)
 827 {
 828         int i;
 829         u32 val, newval;
 830         struct mii_bus *bus;
 831
 832         val = priv->read(priv, AR8316_REG_POSTRIP);
 833
 834         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 835                 if (priv->port4_phy) {
 836                         /* value taken from Ubiquiti RouterStation Pro */
 837                         newval = 0x81461bea;
 838                         pr_info("ar8316: Using port 4 as PHY\n");
 839                 } else {
 840                         newval = 0x01261be2;
 841                         pr_info("ar8316: Using port 4 as switch port\n");
 842                 }
 843         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 844                 /* value taken from AVM Fritz!Box 7390 sources */
 845                 newval = 0x010e5b71;
 846         } else {
 847                 /* no known value for phy interface */
 848                 pr_err("ar8316: unsupported mii mode: %d.\n",
 849                        priv->phy->interface);
 850                 return -EINVAL;
 851         }
 852
 853         if (val == newval)
 854                 goto out;
 855
 856         priv->write(priv, AR8316_REG_POSTRIP, newval);
 857
 858         if (priv->port4_phy &&
 859             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 860                 /* work around for phy4 rgmii mode */
 861                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 862                 /* rx delay */
 863                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 864                 /* tx delay */
 865                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 866                 msleep(1000);
 867         }
 868
 869         /* Initialize the ports */
 870         bus = priv->mii_bus;
 871         for (i = 0; i < 5; i++) {
 872                 /* initialize the port itself */
 873                 mdiobus_write(bus, i, MII_ADVERTISE,
 874                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 875                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 876                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 877         }
 878
 879         msleep(1000);
 880
 881 out:
 882         priv->initialized = true;
 883         return 0;
 884 }
 885
 886 static void
 887 ar8316_init_globals(struct ar8xxx_priv *priv)
 888 {
 889         /* standard atheros magic */
 890         priv->write(priv, 0x38, 0xc000050e);
 891
 892         /* enable cpu port to receive multicast and broadcast frames */
 893         priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 894
 895         /* enable jumbo frames */
 896         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 897                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 898
 899         /* Enable MIB counters */
 900         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 901                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 902                    AR8236_MIB_EN);
 903 }
 904
 905 static const struct ar8xxx_chip ar8316_chip = {
 906         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
 907         .hw_init = ar8316_hw_init,
 908         .init_globals = ar8316_init_globals,
 909         .init_port = ar8216_init_port,
 910         .setup_port = ar8216_setup_port,
 911         .read_port_status = ar8216_read_port_status,
 912         .atu_flush = ar8216_atu_flush,
 913         .vtu_flush = ar8216_vtu_flush,
 914         .vtu_load_vlan = ar8216_vtu_load_vlan,
 915
 916         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 917         .mib_decs = ar8236_mibs,
 918 };
 919
 920 static u32
 921 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
 922 {
 923         u32 t;
 924
 925         if (!cfg)
 926                 return 0;
 927
 928         t = 0;
 929         switch (cfg->mode) {
 930         case AR8327_PAD_NC:
 931                 break;
 932
 933         case AR8327_PAD_MAC2MAC_MII:
 934                 t = AR8327_PAD_MAC_MII_EN;
 935                 if (cfg->rxclk_sel)
 936                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
 937                 if (cfg->txclk_sel)
 938                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
 939                 break;
 940
 941         case AR8327_PAD_MAC2MAC_GMII:
 942                 t = AR8327_PAD_MAC_GMII_EN;
 943                 if (cfg->rxclk_sel)
 944                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
 945                 if (cfg->txclk_sel)
 946                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
 947                 break;
 948
 949         case AR8327_PAD_MAC_SGMII:
 950                 t = AR8327_PAD_SGMII_EN;
 951
 952                 /*
 953                  * WAR for the QUalcomm Atheros AP136 board.
 954                  * It seems that RGMII TX/RX delay settings needs to be
 955                  * applied for SGMII mode as well, The ethernet is not
 956                  * reliable without this.
 957                  */
 958                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
 959                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
 960                 if (cfg->rxclk_delay_en)
 961                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
 962                 if (cfg->txclk_delay_en)
 963                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
 964
 965                 if (cfg->sgmii_delay_en)
 966                         t |= AR8327_PAD_SGMII_DELAY_EN;
 967
 968                 break;
 969
 970         case AR8327_PAD_MAC2PHY_MII:
 971                 t = AR8327_PAD_PHY_MII_EN;
 972                 if (cfg->rxclk_sel)
 973                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
 974                 if (cfg->txclk_sel)
 975                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
 976                 break;
 977
 978         case AR8327_PAD_MAC2PHY_GMII:
 979                 t = AR8327_PAD_PHY_GMII_EN;
 980                 if (cfg->pipe_rxclk_sel)
 981                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
 982                 if (cfg->rxclk_sel)
 983                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
 984                 if (cfg->txclk_sel)
 985                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
 986                 break;
 987
 988         case AR8327_PAD_MAC_RGMII:
 989                 t = AR8327_PAD_RGMII_EN;
 990                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
 991                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
 992                 if (cfg->rxclk_delay_en)
 993                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
 994                 if (cfg->txclk_delay_en)
 995                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
 996                 break;
 997
 998         case AR8327_PAD_PHY_GMII:
 999                 t = AR8327_PAD_PHYX_GMII_EN;
1000                 break;
1001
1002         case AR8327_PAD_PHY_RGMII:
1003                 t = AR8327_PAD_PHYX_RGMII_EN;
1004                 break;
1005
1006         case AR8327_PAD_PHY_MII:
1007                 t = AR8327_PAD_PHYX_MII_EN;
1008                 break;
1009         }
1010
1011         return t;
1012 }
1013
1014 static void
1015 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1016 {
1017         switch (priv->chip_rev) {
1018         case 1:
1019                 /* For 100M waveform */
1020                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1021                 /* Turn on Gigabit clock */
1022                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1023                 break;
1024
1025         case 2:
1026                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1027                 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1028                 /* fallthrough */
1029         case 4:
1030                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1031                 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1032
1033                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1034                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1035                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1036                 break;
1037         }
1038 }
1039
1040 static u32
1041 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1042 {
1043         u32 t;
1044
1045         if (!cfg->force_link)
1046                 return AR8216_PORT_STATUS_LINK_AUTO;
1047
1048         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1049         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1050         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1051         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1052
1053         switch (cfg->speed) {
1054         case AR8327_PORT_SPEED_10:
1055                 t |= AR8216_PORT_SPEED_10M;
1056                 break;
1057         case AR8327_PORT_SPEED_100:
1058                 t |= AR8216_PORT_SPEED_100M;
1059                 break;
1060         case AR8327_PORT_SPEED_1000:
1061                 t |= AR8216_PORT_SPEED_1000M;
1062                 break;
1063         }
1064
1065         return t;
1066 }
1067
1068 static int
1069 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1070                        struct ar8327_platform_data *pdata)
1071 {
1072         struct ar8327_led_cfg *led_cfg;
1073         struct ar8327_data *data;
1074         u32 pos, new_pos;
1075         u32 t;
1076
1077         if (!pdata)
1078                 return -EINVAL;
1079
1080         priv->get_port_link = pdata->get_port_link;
1081
1082         data = &priv->chip_data.ar8327;
1083
1084         data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1085         data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1086
1087         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1088         if (chip_is_ar8337(priv))
1089                 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1090
1091         priv->write(priv, AR8327_REG_PAD0_MODE, t);
1092         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1093         priv->write(priv, AR8327_REG_PAD5_MODE, t);
1094         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1095         priv->write(priv, AR8327_REG_PAD6_MODE, t);
1096
1097         pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1098         new_pos = pos;
1099
1100         led_cfg = pdata->led_cfg;
1101         if (led_cfg) {
1102                 if (led_cfg->open_drain)
1103                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1104                 else
1105                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1106
1107                 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1108                 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1109                 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1110                 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1111
1112                 if (new_pos != pos)
1113                         new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1114         }
1115
1116         if (pdata->sgmii_cfg) {
1117                 t = pdata->sgmii_cfg->sgmii_ctrl;
1118                 if (priv->chip_rev == 1)
1119                         t |= AR8327_SGMII_CTRL_EN_PLL |
1120                              AR8327_SGMII_CTRL_EN_RX |
1121                              AR8327_SGMII_CTRL_EN_TX;
1122                 else
1123                         t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1124                                AR8327_SGMII_CTRL_EN_RX |
1125                                AR8327_SGMII_CTRL_EN_TX);
1126
1127                 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1128
1129                 if (pdata->sgmii_cfg->serdes_aen)
1130                         new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1131                 else
1132                         new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1133         }
1134
1135         priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1136
1137         return 0;
1138 }
1139
1140 #ifdef CONFIG_OF
1141 static int
1142 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1143 {
1144         const __be32 *paddr;
1145         int len;
1146         int i;
1147
1148         paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1149         if (!paddr || len < (2 * sizeof(*paddr)))
1150                 return -EINVAL;
1151
1152         len /= sizeof(*paddr);
1153
1154         for (i = 0; i < len - 1; i += 2) {
1155                 u32 reg;
1156                 u32 val;
1157
1158                 reg = be32_to_cpup(paddr + i);
1159                 val = be32_to_cpup(paddr + i + 1);
1160
1161                 switch (reg) {
1162                 case AR8327_REG_PORT_STATUS(0):
1163                         priv->chip_data.ar8327.port0_status = val;
1164                         break;
1165                 case AR8327_REG_PORT_STATUS(6):
1166                         priv->chip_data.ar8327.port6_status = val;
1167                         break;
1168                 default:
1169                         priv->write(priv, reg, val);
1170                         break;
1171                 }
1172         }
1173
1174         return 0;
1175 }
1176 #else
1177 static inline int
1178 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1179 {
1180         return -EINVAL;
1181 }
1182 #endif
1183
1184 static int
1185 ar8327_hw_init(struct ar8xxx_priv *priv)
1186 {
1187         struct mii_bus *bus;
1188         int ret;
1189         int i;
1190
1191         if (priv->phy->dev.of_node)
1192                 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1193         else
1194                 ret = ar8327_hw_config_pdata(priv,
1195                                              priv->phy->dev.platform_data);
1196
1197         if (ret)
1198                 return ret;
1199
1200         bus = priv->mii_bus;
1201         for (i = 0; i < AR8327_NUM_PHYS; i++) {
1202                 ar8327_phy_fixup(priv, i);
1203
1204                 /* start aneg on the PHY */
1205                 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1206                                                      ADVERTISE_PAUSE_CAP |
1207                                                      ADVERTISE_PAUSE_ASYM);
1208                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1209                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1210         }
1211
1212         msleep(1000);
1213
1214         return 0;
1215 }
1216
1217 static void
1218 ar8327_init_globals(struct ar8xxx_priv *priv)
1219 {
1220         u32 t;
1221
1222         /* enable CPU port and disable mirror port */
1223         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1224             AR8327_FWD_CTRL0_MIRROR_PORT;
1225         priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1226
1227         /* forward multicast and broadcast frames to CPU */
1228         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1229             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1230             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1231         priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1232
1233         /* setup MTU */
1234         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1235                    AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1236
1237         /* Enable MIB counters */
1238         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1239                        AR8327_MODULE_EN_MIB);
1240 }
1241
1242 static void
1243 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1244 {
1245         u32 t;
1246
1247         if (port == AR8216_PORT_CPU)
1248                 t = priv->chip_data.ar8327.port0_status;
1249         else if (port == 6)
1250                 t = priv->chip_data.ar8327.port6_status;
1251         else
1252                 t = AR8216_PORT_STATUS_LINK_AUTO;
1253
1254         priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1255         priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1256
1257         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1258         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1259         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1260
1261         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1262         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1263
1264         t = AR8327_PORT_LOOKUP_LEARN;
1265         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1266         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1267 }
1268
1269 static u32
1270 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1271 {
1272         return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1273 }
1274
1275 static int
1276 ar8327_atu_flush(struct ar8xxx_priv *priv)
1277 {
1278         int ret;
1279
1280         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1281                               AR8327_ATU_FUNC_BUSY, 0);
1282         if (!ret)
1283                 priv->write(priv, AR8327_REG_ATU_FUNC,
1284                             AR8327_ATU_FUNC_OP_FLUSH);
1285
1286         return ret;
1287 }
1288
1289 static void
1290 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1291 {
1292         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1293                             AR8327_VTU_FUNC1_BUSY, 0))
1294                 return;
1295
1296         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1297                 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1298
1299         op |= AR8327_VTU_FUNC1_BUSY;
1300         priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1301 }
1302
1303 static void
1304 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1305 {
1306         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1307 }
1308
1309 static void
1310 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1311 {
1312         u32 op;
1313         u32 val;
1314         int i;
1315
1316         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1317         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1318         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1319                 u32 mode;
1320
1321                 if ((port_mask & BIT(i)) == 0)
1322                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1323                 else if (priv->vlan == 0)
1324                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1325                 else if (priv->vlan_tagged & BIT(i))
1326                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1327                 else
1328                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1329
1330                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1331         }
1332         ar8327_vtu_op(priv, op, val);
1333 }
1334
1335 static void
1336 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
1337                   u32 members, u32 pvid)
1338 {
1339         u32 t;
1340         u32 mode;
1341
1342         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1343         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1344         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1345
1346         mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1347         switch (egress) {
1348         case AR8216_OUT_KEEP:
1349                 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1350                 break;
1351         case AR8216_OUT_STRIP_VLAN:
1352                 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1353                 break;
1354         case AR8216_OUT_ADD_VLAN:
1355                 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1356                 break;
1357         }
1358
1359         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1360         t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1361         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1362
1363         t = members;
1364         t |= AR8327_PORT_LOOKUP_LEARN;
1365         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1366         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1367         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1368 }
1369
1370 static const struct ar8xxx_chip ar8327_chip = {
1371         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1372         .hw_init = ar8327_hw_init,
1373         .init_globals = ar8327_init_globals,
1374         .init_port = ar8327_init_port,
1375         .setup_port = ar8327_setup_port,
1376         .read_port_status = ar8327_read_port_status,
1377         .atu_flush = ar8327_atu_flush,
1378         .vtu_flush = ar8327_vtu_flush,
1379         .vtu_load_vlan = ar8327_vtu_load_vlan,
1380
1381         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1382         .mib_decs = ar8236_mibs,
1383 };
1384
1385 static int
1386 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1387                    struct switch_val *val)
1388 {
1389         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1390         priv->vlan = !!val->value.i;
1391         return 0;
1392 }
1393
1394 static int
1395 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1396                    struct switch_val *val)
1397 {
1398         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1399         val->value.i = priv->vlan;
1400         return 0;
1401 }
1402
1403
1404 static int
1405 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1406 {
1407         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1408
1409         /* make sure no invalid PVIDs get set */
1410
1411         if (vlan >= dev->vlans)
1412                 return -EINVAL;
1413
1414         priv->pvid[port] = vlan;
1415         return 0;
1416 }
1417
1418 static int
1419 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1420 {
1421         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1422         *vlan = priv->pvid[port];
1423         return 0;
1424 }
1425
1426 static int
1427 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1428                   struct switch_val *val)
1429 {
1430         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1431         priv->vlan_id[val->port_vlan] = val->value.i;
1432         return 0;
1433 }
1434
1435 static int
1436 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1437                   struct switch_val *val)
1438 {
1439         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1440         val->value.i = priv->vlan_id[val->port_vlan];
1441         return 0;
1442 }
1443
1444 static int
1445 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1446                         struct switch_port_link *link)
1447 {
1448         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1449
1450         ar8216_read_port_link(priv, port, link);
1451         return 0;
1452 }
1453
1454 static int
1455 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1456 {
1457         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1458         u8 ports = priv->vlan_table[val->port_vlan];
1459         int i;
1460
1461         val->len = 0;
1462         for (i = 0; i < dev->ports; i++) {
1463                 struct switch_port *p;
1464
1465                 if (!(ports & (1 << i)))
1466                         continue;
1467
1468                 p = &val->value.ports[val->len++];
1469                 p->id = i;
1470                 if (priv->vlan_tagged & (1 << i))
1471                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1472                 else
1473                         p->flags = 0;
1474         }
1475         return 0;
1476 }
1477
1478 static int
1479 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1480 {
1481         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1482         u8 *vt = &priv->vlan_table[val->port_vlan];
1483         int i, j;
1484
1485         *vt = 0;
1486         for (i = 0; i < val->len; i++) {
1487                 struct switch_port *p = &val->value.ports[i];
1488
1489                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1490                         priv->vlan_tagged |= (1 << p->id);
1491                 } else {
1492                         priv->vlan_tagged &= ~(1 << p->id);
1493                         priv->pvid[p->id] = val->port_vlan;
1494
1495                         /* make sure that an untagged port does not
1496                          * appear in other vlans */
1497                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1498                                 if (j == val->port_vlan)
1499                                         continue;
1500                                 priv->vlan_table[j] &= ~(1 << p->id);
1501                         }
1502                 }
1503
1504                 *vt |= 1 << p->id;
1505         }
1506         return 0;
1507 }
1508
1509 static void
1510 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1511 {
1512         int port;
1513
1514         /* reset all mirror registers */
1515         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1516                    AR8327_FWD_CTRL0_MIRROR_PORT,
1517                    (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1518         for (port = 0; port < AR8327_NUM_PORTS; port++) {
1519                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1520                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1521                            0);
1522
1523                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1524                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1525                            0);
1526         }
1527
1528         /* now enable mirroring if necessary */
1529         if (priv->source_port >= AR8327_NUM_PORTS ||
1530             priv->monitor_port >= AR8327_NUM_PORTS ||
1531             priv->source_port == priv->monitor_port) {
1532                 return;
1533         }
1534
1535         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1536                    AR8327_FWD_CTRL0_MIRROR_PORT,
1537                    (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1538
1539         if (priv->mirror_rx)
1540                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1541                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1542                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1543
1544         if (priv->mirror_tx)
1545                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1546                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1547                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1548 }
1549
1550 static void
1551 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1552 {
1553         int port;
1554
1555         /* reset all mirror registers */
1556         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1557                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1558                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1559         for (port = 0; port < AR8216_NUM_PORTS; port++) {
1560                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1561                            AR8216_PORT_CTRL_MIRROR_RX,
1562                            0);
1563
1564                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1565                            AR8216_PORT_CTRL_MIRROR_TX,
1566                            0);
1567         }
1568
1569         /* now enable mirroring if necessary */
1570         if (priv->source_port >= AR8216_NUM_PORTS ||
1571             priv->monitor_port >= AR8216_NUM_PORTS ||
1572             priv->source_port == priv->monitor_port) {
1573                 return;
1574         }
1575
1576         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1577                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1578                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1579
1580         if (priv->mirror_rx)
1581                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1582                            AR8216_PORT_CTRL_MIRROR_RX,
1583                            AR8216_PORT_CTRL_MIRROR_RX);
1584
1585         if (priv->mirror_tx)
1586                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1587                            AR8216_PORT_CTRL_MIRROR_TX,
1588                            AR8216_PORT_CTRL_MIRROR_TX);
1589 }
1590
1591 static void
1592 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
1593 {
1594         if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
1595                 ar8327_set_mirror_regs(priv);
1596         } else {
1597                 ar8216_set_mirror_regs(priv);
1598         }
1599 }
1600
1601 static int
1602 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1603 {
1604         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1605         u8 portmask[AR8X16_MAX_PORTS];
1606         int i, j;
1607
1608         mutex_lock(&priv->reg_mutex);
1609         /* flush all vlan translation unit entries */
1610         priv->chip->vtu_flush(priv);
1611
1612         memset(portmask, 0, sizeof(portmask));
1613         if (!priv->init) {
1614                 /* calculate the port destination masks and load vlans
1615                  * into the vlan translation unit */
1616                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1617                         u8 vp = priv->vlan_table[j];
1618
1619                         if (!vp)
1620                                 continue;
1621
1622                         for (i = 0; i < dev->ports; i++) {
1623                                 u8 mask = (1 << i);
1624                                 if (vp & mask)
1625                                         portmask[i] |= vp & ~mask;
1626                         }
1627
1628                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1629                                                  priv->vlan_table[j]);
1630                 }
1631         } else {
1632                 /* vlan disabled:
1633                  * isolate all ports, but connect them to the cpu port */
1634                 for (i = 0; i < dev->ports; i++) {
1635                         if (i == AR8216_PORT_CPU)
1636                                 continue;
1637
1638                         portmask[i] = 1 << AR8216_PORT_CPU;
1639                         portmask[AR8216_PORT_CPU] |= (1 << i);
1640                 }
1641         }
1642
1643         /* update the port destination mask registers and tag settings */
1644         for (i = 0; i < dev->ports; i++) {
1645                 int egress, ingress;
1646                 int pvid;
1647
1648                 if (priv->vlan) {
1649                         pvid = priv->vlan_id[priv->pvid[i]];
1650                         if (priv->vlan_tagged & (1 << i))
1651                                 egress = AR8216_OUT_ADD_VLAN;
1652                         else
1653                                 egress = AR8216_OUT_STRIP_VLAN;
1654                         ingress = AR8216_IN_SECURE;
1655                 } else {
1656                         pvid = i;
1657                         egress = AR8216_OUT_KEEP;
1658                         ingress = AR8216_IN_PORT_ONLY;
1659                 }
1660
1661                 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1662                                        pvid);
1663         }
1664
1665         ar8xxx_set_mirror_regs(priv);
1666
1667         mutex_unlock(&priv->reg_mutex);
1668         return 0;
1669 }
1670
1671 static int
1672 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1673 {
1674         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1675         int i;
1676
1677         mutex_lock(&priv->reg_mutex);
1678         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1679                 offsetof(struct ar8xxx_priv, vlan));
1680
1681         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1682                 priv->vlan_id[i] = i;
1683
1684         /* Configure all ports */
1685         for (i = 0; i < dev->ports; i++)
1686                 priv->chip->init_port(priv, i);
1687
1688         priv->mirror_rx = false;
1689         priv->mirror_tx = false;
1690         priv->source_port = 0;
1691         priv->monitor_port = 0;
1692
1693         priv->chip->init_globals(priv);
1694
1695         mutex_unlock(&priv->reg_mutex);
1696
1697         return ar8xxx_sw_hw_apply(dev);
1698 }
1699
1700 static int
1701 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1702                          const struct switch_attr *attr,
1703                          struct switch_val *val)
1704 {
1705         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1706         unsigned int len;
1707         int ret;
1708
1709         if (!ar8xxx_has_mib_counters(priv))
1710                 return -EOPNOTSUPP;
1711
1712         mutex_lock(&priv->mib_lock);
1713
1714         len = priv->dev.ports * priv->chip->num_mibs *
1715               sizeof(*priv->mib_stats);
1716         memset(priv->mib_stats, '\0', len);
1717         ret = ar8xxx_mib_flush(priv);
1718         if (ret)
1719                 goto unlock;
1720
1721         ret = 0;
1722
1723 unlock:
1724         mutex_unlock(&priv->mib_lock);
1725         return ret;
1726 }
1727
1728 static int
1729 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1730                                const struct switch_attr *attr,
1731                                struct switch_val *val)
1732 {
1733         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1734
1735         mutex_lock(&priv->reg_mutex);
1736         priv->mirror_rx = !!val->value.i;
1737         ar8xxx_set_mirror_regs(priv);
1738         mutex_unlock(&priv->reg_mutex);
1739
1740         return 0;
1741 }
1742
1743 static int
1744 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1745                                const struct switch_attr *attr,
1746                                struct switch_val *val)
1747 {
1748         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1749         val->value.i = priv->mirror_rx;
1750         return 0;
1751 }
1752
1753 static int
1754 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1755                                const struct switch_attr *attr,
1756                                struct switch_val *val)
1757 {
1758         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1759
1760         mutex_lock(&priv->reg_mutex);
1761         priv->mirror_tx = !!val->value.i;
1762         ar8xxx_set_mirror_regs(priv);
1763         mutex_unlock(&priv->reg_mutex);
1764
1765         return 0;
1766 }
1767
1768 static int
1769 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1770                                const struct switch_attr *attr,
1771                                struct switch_val *val)
1772 {
1773         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1774         val->value.i = priv->mirror_tx;
1775         return 0;
1776 }
1777
1778 static int
1779 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1780                                   const struct switch_attr *attr,
1781                                   struct switch_val *val)
1782 {
1783         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1784
1785         mutex_lock(&priv->reg_mutex);
1786         priv->monitor_port = val->value.i;
1787         ar8xxx_set_mirror_regs(priv);
1788         mutex_unlock(&priv->reg_mutex);
1789
1790         return 0;
1791 }
1792
1793 static int
1794 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1795                                   const struct switch_attr *attr,
1796                                   struct switch_val *val)
1797 {
1798         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1799         val->value.i = priv->monitor_port;
1800         return 0;
1801 }
1802
1803 static int
1804 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1805                                  const struct switch_attr *attr,
1806                                  struct switch_val *val)
1807 {
1808         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1809
1810         mutex_lock(&priv->reg_mutex);
1811         priv->source_port = val->value.i;
1812         ar8xxx_set_mirror_regs(priv);
1813         mutex_unlock(&priv->reg_mutex);
1814
1815         return 0;
1816 }
1817
1818 static int
1819 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1820                                  const struct switch_attr *attr,
1821                                  struct switch_val *val)
1822 {
1823         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1824         val->value.i = priv->source_port;
1825         return 0;
1826 }
1827
1828 static int
1829 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1830                              const struct switch_attr *attr,
1831                              struct switch_val *val)
1832 {
1833         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1834         int port;
1835         int ret;
1836
1837         if (!ar8xxx_has_mib_counters(priv))
1838                 return -EOPNOTSUPP;
1839
1840         port = val->port_vlan;
1841         if (port >= dev->ports)
1842                 return -EINVAL;
1843
1844         mutex_lock(&priv->mib_lock);
1845         ret = ar8xxx_mib_capture(priv);
1846         if (ret)
1847                 goto unlock;
1848
1849         ar8xxx_mib_fetch_port_stat(priv, port, true);
1850
1851         ret = 0;
1852
1853 unlock:
1854         mutex_unlock(&priv->mib_lock);
1855         return ret;
1856 }
1857
1858 static int
1859 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1860                        const struct switch_attr *attr,
1861                        struct switch_val *val)
1862 {
1863         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1864         const struct ar8xxx_chip *chip = priv->chip;
1865         u64 *mib_stats;
1866         int port;
1867         int ret;
1868         char *buf = priv->buf;
1869         int i, len = 0;
1870
1871         if (!ar8xxx_has_mib_counters(priv))
1872                 return -EOPNOTSUPP;
1873
1874         port = val->port_vlan;
1875         if (port >= dev->ports)
1876                 return -EINVAL;
1877
1878         mutex_lock(&priv->mib_lock);
1879         ret = ar8xxx_mib_capture(priv);
1880         if (ret)
1881                 goto unlock;
1882
1883         ar8xxx_mib_fetch_port_stat(priv, port, false);
1884
1885         len += snprintf(buf + len, sizeof(priv->buf) - len,
1886                         "Port %d MIB counters\n",
1887                         port);
1888
1889         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1890         for (i = 0; i < chip->num_mibs; i++)
1891                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1892                                 "%-12s: %llu\n",
1893                                 chip->mib_decs[i].name,
1894                                 mib_stats[i]);
1895
1896         val->value.s = buf;
1897         val->len = len;
1898
1899         ret = 0;
1900
1901 unlock:
1902         mutex_unlock(&priv->mib_lock);
1903         return ret;
1904 }
1905
1906 static struct switch_attr ar8xxx_sw_attr_globals[] = {
1907         {
1908                 .type = SWITCH_TYPE_INT,
1909                 .name = "enable_vlan",
1910                 .description = "Enable VLAN mode",
1911                 .set = ar8xxx_sw_set_vlan,
1912                 .get = ar8xxx_sw_get_vlan,
1913                 .max = 1
1914         },
1915         {
1916                 .type = SWITCH_TYPE_NOVAL,
1917                 .name = "reset_mibs",
1918                 .description = "Reset all MIB counters",
1919                 .set = ar8xxx_sw_set_reset_mibs,
1920         },
1921         {
1922                 .type = SWITCH_TYPE_INT,
1923                 .name = "enable_mirror_rx",
1924                 .description = "Enable mirroring of RX packets",
1925                 .set = ar8xxx_sw_set_mirror_rx_enable,
1926                 .get = ar8xxx_sw_get_mirror_rx_enable,
1927                 .max = 1
1928         },
1929         {
1930                 .type = SWITCH_TYPE_INT,
1931                 .name = "enable_mirror_tx",
1932                 .description = "Enable mirroring of TX packets",
1933                 .set = ar8xxx_sw_set_mirror_tx_enable,
1934                 .get = ar8xxx_sw_get_mirror_tx_enable,
1935                 .max = 1
1936         },
1937         {
1938                 .type = SWITCH_TYPE_INT,
1939                 .name = "mirror_monitor_port",
1940                 .description = "Mirror monitor port",
1941                 .set = ar8xxx_sw_set_mirror_monitor_port,
1942                 .get = ar8xxx_sw_get_mirror_monitor_port,
1943                 .max = AR8216_NUM_PORTS - 1
1944         },
1945         {
1946                 .type = SWITCH_TYPE_INT,
1947                 .name = "mirror_source_port",
1948                 .description = "Mirror source port",
1949                 .set = ar8xxx_sw_set_mirror_source_port,
1950                 .get = ar8xxx_sw_get_mirror_source_port,
1951                 .max = AR8216_NUM_PORTS - 1
1952         },
1953 };
1954
1955 static struct switch_attr ar8327_sw_attr_globals[] = {
1956         {
1957                 .type = SWITCH_TYPE_INT,
1958                 .name = "enable_vlan",
1959                 .description = "Enable VLAN mode",
1960                 .set = ar8xxx_sw_set_vlan,
1961                 .get = ar8xxx_sw_get_vlan,
1962                 .max = 1
1963         },
1964         {
1965                 .type = SWITCH_TYPE_NOVAL,
1966                 .name = "reset_mibs",
1967                 .description = "Reset all MIB counters",
1968                 .set = ar8xxx_sw_set_reset_mibs,
1969         },
1970         {
1971                 .type = SWITCH_TYPE_INT,
1972                 .name = "enable_mirror_rx",
1973                 .description = "Enable mirroring of RX packets",
1974                 .set = ar8xxx_sw_set_mirror_rx_enable,
1975                 .get = ar8xxx_sw_get_mirror_rx_enable,
1976                 .max = 1
1977         },
1978         {
1979                 .type = SWITCH_TYPE_INT,
1980                 .name = "enable_mirror_tx",
1981                 .description = "Enable mirroring of TX packets",
1982                 .set = ar8xxx_sw_set_mirror_tx_enable,
1983                 .get = ar8xxx_sw_get_mirror_tx_enable,
1984                 .max = 1
1985         },
1986         {
1987                 .type = SWITCH_TYPE_INT,
1988                 .name = "mirror_monitor_port",
1989                 .description = "Mirror monitor port",
1990                 .set = ar8xxx_sw_set_mirror_monitor_port,
1991                 .get = ar8xxx_sw_get_mirror_monitor_port,
1992                 .max = AR8327_NUM_PORTS - 1
1993         },
1994         {
1995                 .type = SWITCH_TYPE_INT,
1996                 .name = "mirror_source_port",
1997                 .description = "Mirror source port",
1998                 .set = ar8xxx_sw_set_mirror_source_port,
1999                 .get = ar8xxx_sw_get_mirror_source_port,
2000                 .max = AR8327_NUM_PORTS - 1
2001         },
2002 };
2003
2004 static struct switch_attr ar8xxx_sw_attr_port[] = {
2005         {
2006                 .type = SWITCH_TYPE_NOVAL,
2007                 .name = "reset_mib",
2008                 .description = "Reset single port MIB counters",
2009                 .set = ar8xxx_sw_set_port_reset_mib,
2010         },
2011         {
2012                 .type = SWITCH_TYPE_STRING,
2013                 .name = "mib",
2014                 .description = "Get port's MIB counters",
2015                 .set = NULL,
2016                 .get = ar8xxx_sw_get_port_mib,
2017         },
2018 };
2019
2020 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2021         {
2022                 .type = SWITCH_TYPE_INT,
2023                 .name = "vid",
2024                 .description = "VLAN ID (0-4094)",
2025                 .set = ar8xxx_sw_set_vid,
2026                 .get = ar8xxx_sw_get_vid,
2027                 .max = 4094,
2028         },
2029 };
2030
2031 static const struct switch_dev_ops ar8xxx_sw_ops = {
2032         .attr_global = {
2033                 .attr = ar8xxx_sw_attr_globals,
2034                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2035         },
2036         .attr_port = {
2037                 .attr = ar8xxx_sw_attr_port,
2038                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2039         },
2040         .attr_vlan = {
2041                 .attr = ar8xxx_sw_attr_vlan,
2042                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2043         },
2044         .get_port_pvid = ar8xxx_sw_get_pvid,
2045         .set_port_pvid = ar8xxx_sw_set_pvid,
2046         .get_vlan_ports = ar8xxx_sw_get_ports,
2047         .set_vlan_ports = ar8xxx_sw_set_ports,
2048         .apply_config = ar8xxx_sw_hw_apply,
2049         .reset_switch = ar8xxx_sw_reset_switch,
2050         .get_port_link = ar8xxx_sw_get_port_link,
2051 };
2052
2053 static const struct switch_dev_ops ar8327_sw_ops = {
2054         .attr_global = {
2055                 .attr = ar8327_sw_attr_globals,
2056                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2057         },
2058         .attr_port = {
2059                 .attr = ar8xxx_sw_attr_port,
2060                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2061         },
2062         .attr_vlan = {
2063                 .attr = ar8xxx_sw_attr_vlan,
2064                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2065         },
2066         .get_port_pvid = ar8xxx_sw_get_pvid,
2067         .set_port_pvid = ar8xxx_sw_set_pvid,
2068         .get_vlan_ports = ar8xxx_sw_get_ports,
2069         .set_vlan_ports = ar8xxx_sw_set_ports,
2070         .apply_config = ar8xxx_sw_hw_apply,
2071         .reset_switch = ar8xxx_sw_reset_switch,
2072         .get_port_link = ar8xxx_sw_get_port_link,
2073 };
2074
2075 static int
2076 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2077 {
2078         u32 val;
2079         u16 id;
2080         int i;
2081
2082         val = priv->read(priv, AR8216_REG_CTRL);
2083         if (val == ~0)
2084                 return -ENODEV;
2085
2086         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2087         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2088                 u16 t;
2089
2090                 val = priv->read(priv, AR8216_REG_CTRL);
2091                 if (val == ~0)
2092                         return -ENODEV;
2093
2094                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2095                 if (t != id)
2096                         return -ENODEV;
2097         }
2098
2099         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2100         priv->chip_rev = (id & AR8216_CTRL_REVISION);
2101
2102         switch (priv->chip_ver) {
2103         case AR8XXX_VER_AR8216:
2104                 priv->chip = &ar8216_chip;
2105                 break;
2106         case AR8XXX_VER_AR8236:
2107                 priv->chip = &ar8236_chip;
2108                 break;
2109         case AR8XXX_VER_AR8316:
2110                 priv->chip = &ar8316_chip;
2111                 break;
2112         case AR8XXX_VER_AR8327:
2113                 priv->mii_lo_first = true;
2114                 priv->chip = &ar8327_chip;
2115                 break;
2116         case AR8XXX_VER_AR8337:
2117                 priv->mii_lo_first = true;
2118                 priv->chip = &ar8327_chip;
2119                 break;
2120         default:
2121                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2122                        priv->chip_ver, priv->chip_rev);
2123
2124                 return -ENODEV;
2125         }
2126
2127         return 0;
2128 }
2129
2130 static void
2131 ar8xxx_mib_work_func(struct work_struct *work)
2132 {
2133         struct ar8xxx_priv *priv;
2134         int err;
2135
2136         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2137
2138         mutex_lock(&priv->mib_lock);
2139
2140         err = ar8xxx_mib_capture(priv);
2141         if (err)
2142                 goto next_port;
2143
2144         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2145
2146 next_port:
2147         priv->mib_next_port++;
2148         if (priv->mib_next_port >= priv->dev.ports)
2149                 priv->mib_next_port = 0;
2150
2151         mutex_unlock(&priv->mib_lock);
2152         schedule_delayed_work(&priv->mib_work,
2153                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2154 }
2155
2156 static int
2157 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2158 {
2159         unsigned int len;
2160
2161         if (!ar8xxx_has_mib_counters(priv))
2162                 return 0;
2163
2164         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2165
2166         len = priv->dev.ports * priv->chip->num_mibs *
2167               sizeof(*priv->mib_stats);
2168         priv->mib_stats = kzalloc(len, GFP_KERNEL);
2169
2170         if (!priv->mib_stats)
2171                 return -ENOMEM;
2172
2173         return 0;
2174 }
2175
2176 static void
2177 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2178 {
2179         if (!ar8xxx_has_mib_counters(priv))
2180                 return;
2181
2182         schedule_delayed_work(&priv->mib_work,
2183                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2184 }
2185
2186 static void
2187 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2188 {
2189         if (!ar8xxx_has_mib_counters(priv))
2190                 return;
2191
2192         cancel_delayed_work(&priv->mib_work);
2193 }
2194
2195 static struct ar8xxx_priv *
2196 ar8xxx_create(void)
2197 {
2198         struct ar8xxx_priv *priv;
2199
2200         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2201         if (priv == NULL)
2202                 return NULL;
2203
2204         mutex_init(&priv->reg_mutex);
2205         mutex_init(&priv->mib_lock);
2206         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2207
2208         return priv;
2209 }
2210
2211 static void
2212 ar8xxx_free(struct ar8xxx_priv *priv)
2213 {
2214         kfree(priv->mib_stats);
2215         kfree(priv);
2216 }
2217
2218 static struct ar8xxx_priv *
2219 ar8xxx_create_mii(struct mii_bus *bus)
2220 {
2221         struct ar8xxx_priv *priv;
2222
2223         priv = ar8xxx_create();
2224         if (priv) {
2225                 priv->mii_bus = bus;
2226                 priv->read = ar8xxx_mii_read;
2227                 priv->write = ar8xxx_mii_write;
2228         }
2229
2230         return priv;
2231 }
2232
2233 static int
2234 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2235 {
2236         struct switch_dev *swdev;
2237         int ret;
2238
2239         ret = ar8xxx_id_chip(priv);
2240         if (ret)
2241                 return ret;
2242
2243         swdev = &priv->dev;
2244         swdev->cpu_port = AR8216_PORT_CPU;
2245         swdev->ops = &ar8xxx_sw_ops;
2246
2247         if (chip_is_ar8316(priv)) {
2248                 swdev->name = "Atheros AR8316";
2249                 swdev->vlans = AR8X16_MAX_VLANS;
2250                 swdev->ports = AR8216_NUM_PORTS;
2251         } else if (chip_is_ar8236(priv)) {
2252                 swdev->name = "Atheros AR8236";
2253                 swdev->vlans = AR8216_NUM_VLANS;
2254                 swdev->ports = AR8216_NUM_PORTS;
2255         } else if (chip_is_ar8327(priv)) {
2256                 swdev->name = "Atheros AR8327";
2257                 swdev->vlans = AR8X16_MAX_VLANS;
2258                 swdev->ports = AR8327_NUM_PORTS;
2259                 swdev->ops = &ar8327_sw_ops;
2260         } else if (chip_is_ar8337(priv)) {
2261                 swdev->name = "Atheros AR8337";
2262                 swdev->vlans = AR8X16_MAX_VLANS;
2263                 swdev->ports = AR8327_NUM_PORTS;
2264                 swdev->ops = &ar8327_sw_ops;
2265         } else {
2266                 swdev->name = "Atheros AR8216";
2267                 swdev->vlans = AR8216_NUM_VLANS;
2268                 swdev->ports = AR8216_NUM_PORTS;
2269         }
2270
2271         ret = ar8xxx_mib_init(priv);
2272         if (ret)
2273                 return ret;
2274
2275         return 0;
2276 }
2277
2278 static int
2279 ar8xxx_start(struct ar8xxx_priv *priv)
2280 {
2281         int ret;
2282
2283         priv->init = true;
2284
2285         ret = priv->chip->hw_init(priv);
2286         if (ret)
2287                 return ret;
2288
2289         ret = ar8xxx_sw_reset_switch(&priv->dev);
2290         if (ret)
2291                 return ret;
2292
2293         priv->init = false;
2294
2295         ar8xxx_mib_start(priv);
2296
2297         return 0;
2298 }
2299
2300 static int
2301 ar8xxx_phy_config_init(struct phy_device *phydev)
2302 {
2303         struct ar8xxx_priv *priv = phydev->priv;
2304         struct net_device *dev = phydev->attached_dev;
2305         int ret;
2306
2307         if (WARN_ON(!priv))
2308                 return -ENODEV;
2309
2310         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
2311                 return 0;
2312
2313         priv->phy = phydev;
2314
2315         if (phydev->addr != 0) {
2316                 if (chip_is_ar8316(priv)) {
2317                         /* switch device has been initialized, reinit */
2318                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2319                         priv->initialized = false;
2320                         priv->port4_phy = true;
2321                         ar8316_hw_init(priv);
2322                         return 0;
2323                 }
2324
2325                 return 0;
2326         }
2327
2328         ret = ar8xxx_start(priv);
2329         if (ret)
2330                 return ret;
2331
2332         /* VID fixup only needed on ar8216 */
2333         if (chip_is_ar8216(priv)) {
2334                 dev->phy_ptr = priv;
2335                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2336                 dev->eth_mangle_rx = ar8216_mangle_rx;
2337                 dev->eth_mangle_tx = ar8216_mangle_tx;
2338         }
2339
2340         return 0;
2341 }
2342
2343 static int
2344 ar8xxx_phy_read_status(struct phy_device *phydev)
2345 {
2346         struct ar8xxx_priv *priv = phydev->priv;
2347         struct switch_port_link link;
2348         int ret;
2349
2350         if (phydev->addr != 0)
2351                 return genphy_read_status(phydev);
2352
2353         ar8216_read_port_link(priv, phydev->addr, &link);
2354         phydev->link = !!link.link;
2355         if (!phydev->link)
2356                 return 0;
2357
2358         switch (link.speed) {
2359         case SWITCH_PORT_SPEED_10:
2360                 phydev->speed = SPEED_10;
2361                 break;
2362         case SWITCH_PORT_SPEED_100:
2363                 phydev->speed = SPEED_100;
2364                 break;
2365         case SWITCH_PORT_SPEED_1000:
2366                 phydev->speed = SPEED_1000;
2367                 break;
2368         default:
2369                 phydev->speed = 0;
2370         }
2371         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2372
2373         /* flush the address translation unit */
2374         mutex_lock(&priv->reg_mutex);
2375         ret = priv->chip->atu_flush(priv);
2376         mutex_unlock(&priv->reg_mutex);
2377
2378         phydev->state = PHY_RUNNING;
2379         netif_carrier_on(phydev->attached_dev);
2380         phydev->adjust_link(phydev->attached_dev);
2381
2382         return ret;
2383 }
2384
2385 static int
2386 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2387 {
2388         if (phydev->addr == 0)
2389                 return 0;
2390
2391         return genphy_config_aneg(phydev);
2392 }
2393
2394 static const u32 ar8xxx_phy_ids[] = {
2395         0x004dd033,
2396         0x004dd034, /* AR8327 */
2397         0x004dd036, /* AR8337 */
2398         0x004dd041,
2399         0x004dd042,
2400 };
2401
2402 static bool
2403 ar8xxx_phy_match(u32 phy_id)
2404 {
2405         int i;
2406
2407         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2408                 if (phy_id == ar8xxx_phy_ids[i])
2409                         return true;
2410
2411         return false;
2412 }
2413
2414 static bool
2415 ar8xxx_is_possible(struct mii_bus *bus)
2416 {
2417         unsigned i;
2418
2419         for (i = 0; i < 4; i++) {
2420                 u32 phy_id;
2421
2422                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2423                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2424                 if (!ar8xxx_phy_match(phy_id)) {
2425                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2426                                  dev_name(&bus->dev), i, phy_id);
2427                         return false;
2428                 }
2429         }
2430
2431         return true;
2432 }
2433
2434 static int
2435 ar8xxx_phy_probe(struct phy_device *phydev)
2436 {
2437         struct ar8xxx_priv *priv;
2438         struct switch_dev *swdev;
2439         int ret;
2440
2441         /* skip PHYs at unused adresses */
2442         if (phydev->addr != 0 && phydev->addr != 4)
2443                 return -ENODEV;
2444
2445         if (!ar8xxx_is_possible(phydev->bus))
2446                 return -ENODEV;
2447
2448         mutex_lock(&ar8xxx_dev_list_lock);
2449         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2450                 if (priv->mii_bus == phydev->bus)
2451                         goto found;
2452
2453         priv = ar8xxx_create_mii(phydev->bus);
2454         if (priv == NULL) {
2455                 ret = -ENOMEM;
2456                 goto unlock;
2457         }
2458
2459         ret = ar8xxx_probe_switch(priv);
2460         if (ret)
2461                 goto free_priv;
2462
2463         swdev = &priv->dev;
2464         swdev->alias = dev_name(&priv->mii_bus->dev);
2465         ret = register_switch(swdev, NULL);
2466         if (ret)
2467                 goto free_priv;
2468
2469         pr_info("%s: %s rev. %u switch registered on %s\n",
2470                 swdev->devname, swdev->name, priv->chip_rev,
2471                 dev_name(&priv->mii_bus->dev));
2472
2473 found:
2474         priv->use_count++;
2475
2476         if (phydev->addr == 0) {
2477                 if (ar8xxx_has_gige(priv)) {
2478                         phydev->supported = SUPPORTED_1000baseT_Full;
2479                         phydev->advertising = ADVERTISED_1000baseT_Full;
2480                 } else {
2481                         phydev->supported = SUPPORTED_100baseT_Full;
2482                         phydev->advertising = ADVERTISED_100baseT_Full;
2483                 }
2484
2485                 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2486                         priv->phy = phydev;
2487
2488                         ret = ar8xxx_start(priv);
2489                         if (ret)
2490                                 goto err_unregister_switch;
2491                 }
2492         } else {
2493                 if (ar8xxx_has_gige(priv)) {
2494                         phydev->supported |= SUPPORTED_1000baseT_Full;
2495                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2496                 }
2497         }
2498
2499         phydev->priv = priv;
2500
2501         list_add(&priv->list, &ar8xxx_dev_list);
2502
2503         mutex_unlock(&ar8xxx_dev_list_lock);
2504
2505         return 0;
2506
2507 err_unregister_switch:
2508         if (--priv->use_count)
2509                 goto unlock;
2510
2511         unregister_switch(&priv->dev);
2512
2513 free_priv:
2514         ar8xxx_free(priv);
2515 unlock:
2516         mutex_unlock(&ar8xxx_dev_list_lock);
2517         return ret;
2518 }
2519
2520 static void
2521 ar8xxx_phy_detach(struct phy_device *phydev)
2522 {
2523         struct net_device *dev = phydev->attached_dev;
2524
2525         if (!dev)
2526                 return;
2527
2528         dev->phy_ptr = NULL;
2529         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2530         dev->eth_mangle_rx = NULL;
2531         dev->eth_mangle_tx = NULL;
2532 }
2533
2534 static void
2535 ar8xxx_phy_remove(struct phy_device *phydev)
2536 {
2537         struct ar8xxx_priv *priv = phydev->priv;
2538
2539         if (WARN_ON(!priv))
2540                 return;
2541
2542         phydev->priv = NULL;
2543         if (--priv->use_count > 0)
2544                 return;
2545
2546         mutex_lock(&ar8xxx_dev_list_lock);
2547         list_del(&priv->list);
2548         mutex_unlock(&ar8xxx_dev_list_lock);
2549
2550         unregister_switch(&priv->dev);
2551         ar8xxx_mib_stop(priv);
2552         ar8xxx_free(priv);
2553 }
2554
2555 static struct phy_driver ar8xxx_phy_driver = {
2556         .phy_id         = 0x004d0000,
2557         .name           = "Atheros AR8216/AR8236/AR8316",
2558         .phy_id_mask    = 0xffff0000,
2559         .features       = PHY_BASIC_FEATURES,
2560         .probe          = ar8xxx_phy_probe,
2561         .remove         = ar8xxx_phy_remove,
2562         .detach         = ar8xxx_phy_detach,
2563         .config_init    = ar8xxx_phy_config_init,
2564         .config_aneg    = ar8xxx_phy_config_aneg,
2565         .read_status    = ar8xxx_phy_read_status,
2566         .driver         = { .owner = THIS_MODULE },
2567 };
2568
2569 int __init
2570 ar8xxx_init(void)
2571 {
2572         return phy_driver_register(&ar8xxx_phy_driver);
2573 }
2574
2575 void __exit
2576 ar8xxx_exit(void)
2577 {
2578         phy_driver_unregister(&ar8xxx_phy_driver);
2579 }
2580
2581 module_init(ar8xxx_init);
2582 module_exit(ar8xxx_exit);
2583 MODULE_LICENSE("GPL");
2584