target/linux/gemini/patches/120-net-add-gemini-gmac-driver.patch

   1 --- /dev/null
   2 +++ b/arch/arm/mach-gemini/include/mach/gmac.h
   3 @@ -0,0 +1,21 @@
   4 +/*
   5 + * Gemini GMAC specific defines
   6 + *
   7 + * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
   8 + *
   9 + * This program is free software; you can redistribute it and/or modify
  10 + * it under the terms of the GNU General Public License as published by
  11 + * the Free Software Foundation; either version 2 of the License, or
  12 + * (at your option) any later version.
  13 + */
  14 +#ifndef __MACH_GMAC_H__
  15 +#define __MACH_GMAC_H__
  16 +
  17 +#include <linux/phy.h>
  18 +
  19 +struct gemini_gmac_platform_data {
  20 +       char *bus_id[2]; /* NULL means that this port is not used */
  21 +       phy_interface_t interface[2];
  22 +};
  23 +
  24 +#endif /* __MACH_GMAC_H__ */
  25 --- /dev/null
  26 +++ b/drivers/net/gemini_negmac/gm_gmac.c
  27 @@ -0,0 +1,1359 @@
  28 +/*
  29 + *  Ethernet device driver for Gemini SoC.
  30 + *
  31 + *  Copyright (C) 2006, Storlink, Corp.
  32 + *  Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
  33 + *
  34 + * This program is free software; you can redistribute it and/or modify
  35 + * it under the terms of the GNU General Public License as published by
  36 + * the Free Software Foundation; either version 2 of the License, or
  37 + * (at your option) any later version.
  38 + */
  39 +#include <linux/module.h>
  40 +#include <linux/kernel.h>
  41 +#include <linux/platform_device.h>
  42 +#include <linux/slab.h>
  43 +#include <linux/mm.h>
  44 +#include <linux/compiler.h>
  45 +#include <linux/dma-mapping.h>
  46 +#include <linux/init.h>
  47 +#include <linux/ioport.h>
  48 +#include <linux/netdevice.h>
  49 +#include <linux/etherdevice.h>
  50 +#include <linux/rtnetlink.h>
  51 +#include <linux/delay.h>
  52 +#include <linux/ethtool.h>
  53 +#include <linux/mii.h>
  54 +#include <linux/phy.h>
  55 +#include <linux/irq.h>
  56 +#include <linux/interrupt.h>
  57 +#include <linux/completion.h>
  58 +#include <linux/kthread.h>
  59 +#include <linux/io.h>
  60 +#include <mach/hardware.h>
  61 +#include <linux/semaphore.h>
  62 +#include <mach/irqs.h>
  63 +#include <linux/skbuff.h>
  64 +#include <linux/in.h>
  65 +#include <linux/ip.h>
  66 +#include <linux/tcp.h>
  67 +#include <linux/udp.h>
  68 +#include <mach/gmac.h>
  69 +
  70 +#include "gm_gmac.h"
  71 +
  72 +/* #define GMAX_TX_INTR_DISABLED */
  73 +/* #define DO_HW_CHKSUM */
  74 +/* #define ENABLE_TSO */
  75 +#define GMAC_USE_TXQ0
  76 +/* #define GMAC_LEN_1_2_ISSUE */
  77 +
  78 +#define DEFAULT_RXQ_MAX_CNT                    256
  79 +
  80 +/* define chip information */
  81 +#define DRV_VERSION                    "0.2"
  82 +#define SL351x_DRIVER_NAME             "Gemini Ethernet driver " DRV_VERSION
  83 +
  84 +#ifdef GMAC_LEN_1_2_ISSUE
  85 +       #define _DEBUG_PREFETCH_NUM     256
  86 +static int     _debug_prefetch_cnt;
  87 +static char _debug_prefetch_buf[_DEBUG_PREFETCH_NUM][4] __attribute__((aligned(4)));
  88 +#endif
  89 +
  90 +static inline void gmac_write_reg(void __iomem *base, unsigned int offset,
  91 +                                 unsigned int data, unsigned int bit_mask)
  92 +{
  93 +       unsigned int reg_val;
  94 +
  95 +       reg_val = (__raw_readl(base + offset) & (~bit_mask)) | (data & bit_mask);
  96 +       __raw_writel(reg_val, base + offset);
  97 +}
  98 +
  99 +/*----------------------------------------------------------------------
 100 +*      toe_init_free_queue
 101 +*      (1) Initialize the Free Queue Descriptor Base Address & size
 102 +*              Register: TOE_GLOBAL_BASE + 0x0004
 103 +*      (2) Initialize DMA Read/Write pointer for
 104 +*              SW Free Queue and HW Free Queue
 105 +*      (3)     Initialize DMA Descriptors for
 106 +*              SW Free Queue and HW Free Queue,
 107 +*----------------------------------------------------------------------*/
 108 +static void toe_init_free_queue(struct toe_private *toe)
 109 +{
 110 +       int                     i;
 111 +       DMA_RWPTR_T             rwptr_reg;
 112 +       void                    *desc_buf;
 113 +       GMAC_RXDESC_T           *sw_desc_ptr;
 114 +       struct sk_buff          *skb;
 115 +
 116 +       desc_buf = dma_alloc_coherent(toe->dev, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
 117 +                                     &toe->sw_freeq_desc_base_dma, GFP_KERNEL);
 118 +       sw_desc_ptr = (GMAC_RXDESC_T *)desc_buf;
 119 +       if (!desc_buf) {
 120 +               dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
 121 +               return;
 122 +       }
 123 +       memset(desc_buf, 0, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
 124 +
 125 +       /* DMA Queue Base & Size */
 126 +       __raw_writel((toe->sw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_SW_FREEQ_DESC_POWER,
 127 +                       toe->global_base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
 128 +
 129 +       /* init descriptor base */
 130 +       toe->swfq_desc_base = (unsigned int)desc_buf;
 131 +
 132 +       /* SW Free Queue Descriptors */
 133 +       for (i = 0; i < TOE_SW_FREEQ_DESC_NUM; i++) {
 134 +               sw_desc_ptr->word0.bits.buffer_size = SW_RX_BUF_SIZE;
 135 +               skb = dev_alloc_skb(SW_RX_BUF_SIZE);    /* allocate socket buffer */
 136 +               if (!skb) {
 137 +                       dev_err(toe->dev, "%s::skb buffer allocation fail\n", __func__);
 138 +                       return;
 139 +               }
 140 +               REG32(skb->data) = (unsigned int)skb;
 141 +               skb_reserve(skb, SKB_RESERVE_BYTES);
 142 +               sw_desc_ptr->word2.buf_adr = dma_map_single(toe->dev, skb->data,
 143 +                                       SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
 144 +                                       DMA_FROM_DEVICE);
 145 +               sw_desc_ptr++;
 146 +       }
 147 +
 148 +       dma_sync_single_for_device(toe->dev, toe->sw_freeq_desc_base_dma,
 149 +                               TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
 150 +                               DMA_TO_DEVICE);
 151 +
 152 +       /* SW Free Queue Read/Write Pointer */
 153 +       rwptr_reg.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
 154 +       rwptr_reg.bits.rptr = 0;
 155 +       __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
 156 +
 157 +       /* DMA Queue Base & Size */
 158 +       __raw_writel(TOE_HW_FREEQ_DESC_POWER,
 159 +               toe->global_base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
 160 +       rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
 161 +       rwptr_reg.bits.rptr = 0;
 162 +       __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_HWFQ_RWPTR_REG);
 163 +}
 164 +
 165 +/*----------------------------------------------------------------------
 166 +*      toe_init_swtx_queue
 167 +*      (2) Initialize the GMAC 0/1 SW TXQ Queue Descriptor Base Address & sizeup
 168 +*              GMAC_SW_TX_QUEUE_BASE_REG(0x0050)
 169 +*      (2) Initialize DMA Read/Write pointer for
 170 +*              GMAC 0/1 SW TX Q0-5
 171 +*----------------------------------------------------------------------*/
 172 +static void toe_init_swtx_queue(struct net_device *dev)
 173 +{
 174 +       int                     i;
 175 +       struct gmac_private     *gmac = netdev_priv(dev);
 176 +       struct toe_private      *toe = dev->ml_priv;
 177 +       DMA_RWPTR_T             rwptr_reg;
 178 +       void __iomem            *rwptr_addr;
 179 +       void                    *desc_buf;
 180 +       unsigned int            offset;
 181 +
 182 +       desc_buf = dma_alloc_coherent(toe->dev, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
 183 +                                     &gmac->swtxq_desc_base_dma, GFP_KERNEL);
 184 +       gmac->swtxq_desc_base = (unsigned int)desc_buf;
 185 +       if (!desc_buf) {
 186 +               dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
 187 +               return;
 188 +       }
 189 +       memset(desc_buf, 0, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
 190 +       dma_sync_single_for_device(toe->dev, gmac->swtxq_desc_base_dma,
 191 +                               TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
 192 +                               DMA_TO_DEVICE);
 193 +       __raw_writel((gmac->swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC_SWTXQ_DESC_POWER,
 194 +                       gmac->dma_base_addr + GMAC_SW_TX_QUEUE_BASE_REG);
 195 +
 196 +       /* GMAC0 SW TX Q0-Q5 */
 197 +       offset = 0;
 198 +       rwptr_reg.bits.wptr = 0;
 199 +       rwptr_reg.bits.rptr = 0;
 200 +       rwptr_addr = gmac->dma_base_addr + GMAC_SW_TX_QUEUE0_PTR_REG;
 201 +       for (i = 0; i < TOE_SW_TXQ_NUM; i++) {
 202 +               gmac->swtxq[i].rwptr_reg = rwptr_addr;
 203 +               gmac->swtxq[i].desc_base_dma = (unsigned int)gmac->swtxq_desc_base_dma + offset;
 204 +               gmac->swtxq[i].desc_base = (unsigned int)desc_buf + offset;
 205 +               offset += TOE_GMAC_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
 206 +               __raw_writel(rwptr_reg.bits32, rwptr_addr);
 207 +               rwptr_addr += 4;
 208 +       }
 209 +}
 210 +
 211 +/*----------------------------------------------------------------------
 212 +*      toe_init_default_queue
 213 +*      (1) Initialize the default 0/1 Queue Header
 214 +*              Register: TOE_DEFAULT_Q0_HDR_BASE (0x60002000)
 215 +*                        TOE_DEFAULT_Q1_HDR_BASE (0x60002008)
 216 +*      (2)     Initialize Descriptors of Default Queue 0/1
 217 +*----------------------------------------------------------------------*/
 218 +static void toe_init_default_queue(struct net_device *dev)
 219 +{
 220 +       struct gmac_private     *gmac = netdev_priv(dev);
 221 +       struct toe_private      *toe = dev->ml_priv;
 222 +       volatile NONTOE_QHDR_T  *qhdr;
 223 +       GMAC_RXDESC_T           *desc_ptr;
 224 +
 225 +       desc_ptr = dma_alloc_coherent(toe->dev, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
 226 +                                     &gmac->default_desc_base_dma, GFP_KERNEL);
 227 +       if (!desc_ptr) {
 228 +               dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
 229 +               return;
 230 +       }
 231 +       memset(desc_ptr, 0, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T));
 232 +       dma_sync_single_for_device(toe->dev, gmac->default_desc_base_dma,
 233 +                       TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
 234 +                       DMA_TO_DEVICE);
 235 +       gmac->default_desc_base = (unsigned int)desc_ptr;
 236 +       qhdr = (volatile NONTOE_QHDR_T *)(toe->global_base + TOE_DEFAULT_Q_HDR_BASE(gmac->port_id));
 237 +       qhdr->word0.base_size = ((unsigned int)gmac->default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q_DESC_POWER;
 238 +       qhdr->word1.bits32 = 0;
 239 +       gmac->default_qhdr = (NONTOE_QHDR_T *)qhdr;
 240 +}
 241 +
 242 +/*----------------------------------------------------------------------
 243 +*      toe_init_interrupt_config
 244 +*      Interrupt Select Registers are used to map interrupt to int0 or int1
 245 +*      Int0 and int1 are wired to CPU 0/1 GMAC 0/1
 246 +*      Interrupt Device Inteface data are used to pass device info to
 247 +*              upper device driver or store status/statistics
 248 +*      ISR handler
 249 +*              (1) If status bit ON but masked, the prinf error message (bug issue)
 250 +*              (2) If select bits are for me, handle it, else skip to let
 251 +*                      the other ISR handles it.
 252 +*  Notes:
 253 +*              GMACx init routine (for eCOS) or open routine (for Linux)
 254 +*              enable the interrupt bits only which are selected for it.
 255 +*
 256 +*      Default Setting:
 257 +*              GMAC0 intr bits ------> int0 ----> eth0
 258 +*              GMAC1 intr bits ------> int1 ----> eth1
 259 +*              TOE intr -------------> int0 ----> eth0
 260 +*              Classification Intr --> int0 ----> eth0
 261 +*              Default Q0 -----------> int0 ----> eth0
 262 +*              Default Q1 -----------> int1 ----> eth1
 263 +*----------------------------------------------------------------------*/
 264 +static void toe_init_interrupt_config(struct toe_private *toe)
 265 +{
 266 +       /* clear all status bits */
 267 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
 268 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
 269 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
 270 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
 271 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
 272 +
 273 +       /* Init select registers */
 274 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
 275 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
 276 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
 277 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
 278 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
 279 +
 280 +       /* disable all interrupt */
 281 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_0_REG);
 282 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_1_REG);
 283 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_2_REG);
 284 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_3_REG);
 285 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_4_REG);
 286 +}
 287 +
 288 +static void toe_gmac_hw_start(struct gmac_private *gmac)
 289 +{
 290 +       GMAC_DMA_CTRL_T dma_ctrl;
 291 +
 292 +       /* program dma control register */
 293 +       dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
 294 +       dma_ctrl.bits.rd_enable = 1;
 295 +       dma_ctrl.bits.td_enable = 1;
 296 +       dma_ctrl.bits.loopback = 0;
 297 +       dma_ctrl.bits.drop_small_ack = 0;
 298 +       dma_ctrl.bits.rd_prot = 0;
 299 +       dma_ctrl.bits.rd_burst_size = 3;
 300 +       dma_ctrl.bits.rd_insert_bytes = RX_INSERT_BYTES;
 301 +       dma_ctrl.bits.rd_bus = 3;
 302 +       dma_ctrl.bits.td_prot = 0;
 303 +       dma_ctrl.bits.td_burst_size = 3;
 304 +       dma_ctrl.bits.td_bus = 3;
 305 +
 306 +       __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
 307 +}
 308 +
 309 +static void toe_gmac_hw_stop(struct gmac_private *gmac)
 310 +{
 311 +       GMAC_DMA_CTRL_T dma_ctrl;
 312 +
 313 +       /* program dma control register */
 314 +       dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
 315 +       dma_ctrl.bits.rd_enable = 0;
 316 +       dma_ctrl.bits.td_enable = 0;
 317 +       __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
 318 +}
 319 +
 320 +static void toe_gmac_init_chip(struct net_device *dev)
 321 +{
 322 +       struct gmac_private     *gmac = netdev_priv(dev);
 323 +       GMAC_CONFIG2_T  config2_val;
 324 +       GMAC_CONFIG0_T  config0;
 325 +       GMAC_CONFIG1_T  config1;
 326 +       GMAC_STATUS_T   status;
 327 +       GMAC_TX_WCR0_T  hw_weigh;
 328 +       GMAC_TX_WCR1_T  sw_weigh;
 329 +       GMAC_RX_FLTR_T  rx_filter;
 330 +
 331 +       /* set RX_FLTR register to receive all multicast packet */
 332 +       rx_filter.bits32 = __raw_readl(gmac->base_addr + GMAC_RX_FLTR);
 333 +       rx_filter.bits.unicast = 1;
 334 +       rx_filter.bits.multicast = 1;
 335 +       rx_filter.bits.broadcast = 1;
 336 +       __raw_writel(rx_filter.bits32, gmac->base_addr + GMAC_RX_FLTR);
 337 +
 338 +       /* set flow control threshold */
 339 +       config1.bits32 = 0;
 340 +       config1.bits.set_threshold = 32 / 2;
 341 +       config1.bits.rel_threshold = 32 / 4 * 3;
 342 +       __raw_writel(config1.bits32, gmac->base_addr + GMAC_CONFIG1);
 343 +
 344 +       /* set flow control threshold */
 345 +       config2_val.bits32 = 0;
 346 +       config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM / 4;
 347 +       config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM / 2;
 348 +       __raw_writel(config2_val.bits32, gmac->base_addr + GMAC_CONFIG2);
 349 +
 350 +       /* disable TX/RX and disable internal loop back */
 351 +       config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
 352 +
 353 +       config0.bits.max_len = 2;
 354 +
 355 +       gmac->flow_control_enable = 0;
 356 +
 357 +       config0.bits.tx_fc_en = 0;      /* disable tx flow control */
 358 +       config0.bits.rx_fc_en = 0;      /* disable rx flow control */
 359 +       config0.bits.dis_rx = 1;        /* disable rx */
 360 +       config0.bits.dis_tx = 1;        /* disable tx */
 361 +       config0.bits.loop_back = 0;     /* enable/disable GMAC loopback */
 362 +       config0.bits.rx_err_detect = 1;
 363 +       config0.bits.rgmii_en = 0;
 364 +       config0.bits.rgmm_edge = 1;
 365 +       config0.bits.rxc_inv = 0;
 366 +       config0.bits.ipv4_rx_chksum = 1;        /* enable H/W to check ip checksum */
 367 +       config0.bits.ipv6_rx_chksum = 1;        /* enable H/W to check ip checksum */
 368 +       config0.bits.port0_chk_hwq = 1;
 369 +       config0.bits.port1_chk_hwq = 1;
 370 +       config0.bits.port0_chk_toeq = 1;
 371 +       config0.bits.port1_chk_toeq = 1;
 372 +       config0.bits.port0_chk_classq = 1;
 373 +       config0.bits.port1_chk_classq = 1;
 374 +
 375 +       __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
 376 +
 377 +       hw_weigh.bits32 = 0;
 378 +       hw_weigh.bits.hw_tq3 = 1;
 379 +       hw_weigh.bits.hw_tq2 = 1;
 380 +       hw_weigh.bits.hw_tq1 = 1;
 381 +       hw_weigh.bits.hw_tq0 = 1;
 382 +       __raw_writel(hw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_0_REG);
 383 +
 384 +       sw_weigh.bits32 = 0;
 385 +       sw_weigh.bits.sw_tq5 = 1;
 386 +       sw_weigh.bits.sw_tq4 = 1;
 387 +       sw_weigh.bits.sw_tq3 = 1;
 388 +       sw_weigh.bits.sw_tq2 = 1;
 389 +       sw_weigh.bits.sw_tq1 = 1;
 390 +       sw_weigh.bits.sw_tq0 = 1;
 391 +       __raw_writel(sw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_1_REG);
 392 +
 393 +       /* set interface type */
 394 +       status.bits32 = __raw_readl(gmac->base_addr + GMAC_STATUS);
 395 +
 396 +       switch (gmac->phydev->interface) {
 397 +       case PHY_INTERFACE_MODE_MII:
 398 +               status.bits.mii_rmii = GMAC_PHY_MII;
 399 +               break;
 400 +       case PHY_INTERFACE_MODE_GMII:
 401 +               status.bits.mii_rmii = GMAC_PHY_GMII;
 402 +               break;
 403 +       case PHY_INTERFACE_MODE_RGMII:
 404 +               status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
 405 +               break;
 406 +       default:
 407 +               dev_err(&dev->dev, "Unsupported MII interface\n");
 408 +               return;
 409 +       }
 410 +
 411 +       __raw_writel(status.bits32, gmac->base_addr + GMAC_STATUS);
 412 +}
 413 +
 414 +static void toe_init_gmac(struct net_device *dev)
 415 +{
 416 +       struct gmac_private     *gmac = netdev_priv(dev);
 417 +       struct toe_private      *toe = dev->ml_priv;
 418 +       u32                     data;
 419 +
 420 +       /* GMAC initialization */
 421 +       toe_gmac_init_chip(dev);
 422 +
 423 +       /* -----------------------------------------------------------
 424 +       Enable GMAC interrupt & disable loopback
 425 +       Notes:
 426 +               GMACx init routine (for eCOS) or open routine (for Linux)
 427 +               enable the interrupt bits only which are selected for him.
 428 +       --------------------------------------------------------------*/
 429 +
 430 +       /* Enable Interrupt Bits */
 431 +       if (gmac->port_id == 0) {
 432 +               gmac->intr0_selected =  GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT     |
 433 +                                       GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT     |
 434 +                                       GMAC0_SWTQ05_FIN_INT_BIT | GMAC0_SWTQ05_EOF_INT_BIT |
 435 +                                       GMAC0_SWTQ04_FIN_INT_BIT | GMAC0_SWTQ04_EOF_INT_BIT |
 436 +                                       GMAC0_SWTQ03_FIN_INT_BIT | GMAC0_SWTQ03_EOF_INT_BIT |
 437 +                                       GMAC0_SWTQ02_FIN_INT_BIT | GMAC0_SWTQ02_EOF_INT_BIT |
 438 +                                       GMAC0_SWTQ01_FIN_INT_BIT | GMAC0_SWTQ01_EOF_INT_BIT |
 439 +                                       GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
 440 +
 441 +#ifdef GMAX_TX_INTR_DISABLED
 442 +               gmac->intr0_enabled = 0;
 443 +#else
 444 +               gmac->intr0_enabled = GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
 445 +#endif
 446 +
 447 +               gmac->intr1_selected = TOE_IQ_ALL_BITS | TOE_CLASS_RX_INT_BITS |
 448 +                                       GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
 449 +                                       GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT |
 450 +                                       DEFAULT_Q0_INT_BIT;
 451 +               gmac->intr1_enabled =   DEFAULT_Q0_INT_BIT | TOE_IQ_ALL_BITS;
 452 +               gmac->intr2_selected =  0xffffffff;      /* TOE Queue 32-63 FUUL Intr */
 453 +               gmac->intr2_enabled =   0xffffffff;
 454 +               gmac->intr3_selected =  0xffffffff;      /* TOE Queue 0-31 FUUL Intr */
 455 +               gmac->intr3_enabled =   0xffffffff;
 456 +               gmac->intr4_selected =  GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
 457 +                                                       HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
 458 +               gmac->intr4_enabled =   GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
 459 +
 460 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) & ~gmac->intr0_selected;
 461 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
 462 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) & ~gmac->intr1_selected;
 463 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
 464 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) & ~gmac->intr2_selected;
 465 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
 466 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) & ~gmac->intr3_selected;
 467 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
 468 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) & ~gmac->intr4_selected;
 469 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
 470 +       } else {
 471 +               gmac->intr0_selected =  GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT     |
 472 +                                       GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT     |
 473 +                                       GMAC1_SWTQ15_FIN_INT_BIT | GMAC1_SWTQ15_EOF_INT_BIT |
 474 +                                       GMAC1_SWTQ14_FIN_INT_BIT | GMAC1_SWTQ14_EOF_INT_BIT |
 475 +                                       GMAC1_SWTQ13_FIN_INT_BIT | GMAC1_SWTQ13_EOF_INT_BIT |
 476 +                                       GMAC1_SWTQ12_FIN_INT_BIT | GMAC1_SWTQ12_EOF_INT_BIT |
 477 +                                       GMAC1_SWTQ11_FIN_INT_BIT | GMAC1_SWTQ11_EOF_INT_BIT |
 478 +                                       GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
 479 +#ifdef GMAX_TX_INTR_DISABLED
 480 +               gmac->intr0_enabled =           0;
 481 +#else
 482 +               gmac->intr0_enabled =           GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
 483 +#endif
 484 +
 485 +               gmac->intr1_selected =  DEFAULT_Q1_INT_BIT;
 486 +               gmac->intr1_enabled =   DEFAULT_Q1_INT_BIT | TOE_IQ_ALL_BITS;
 487 +               gmac->intr2_selected =  0;       /* TOE Queue 32-63 FUUL Intr */
 488 +               gmac->intr2_enabled =   0;
 489 +               gmac->intr3_selected =  0;       /* TOE Queue 0-31 FUUL Intr */
 490 +               gmac->intr3_enabled =   0;
 491 +               gmac->intr4_selected =  GMAC1_INT_BITS;
 492 +               gmac->intr4_enabled =   GMAC1_INT_BITS;
 493 +
 494 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) | gmac->intr0_selected;
 495 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
 496 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) | gmac->intr1_selected;
 497 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
 498 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) | gmac->intr2_selected;
 499 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
 500 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) | gmac->intr3_selected;
 501 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
 502 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) | gmac->intr4_selected;
 503 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
 504 +       }
 505 +
 506 +       /* enable only selected bits */
 507 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_0_REG,
 508 +                                       gmac->intr0_enabled, gmac->intr0_selected);
 509 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_1_REG,
 510 +                                       gmac->intr1_enabled, gmac->intr1_selected);
 511 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_2_REG,
 512 +                                       gmac->intr2_enabled, gmac->intr2_selected);
 513 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_3_REG,
 514 +                                       gmac->intr3_enabled, gmac->intr3_selected);
 515 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_4_REG,
 516 +                                       gmac->intr4_enabled, gmac->intr4_selected);
 517 +
 518 +       /* start DMA process */
 519 +       toe_gmac_hw_start(gmac);
 520 +}
 521 +
 522 +static void toe_gmac_enable_tx_rx(struct net_device *dev)
 523 +{
 524 +       struct gmac_private *gmac = netdev_priv(dev);
 525 +       GMAC_CONFIG0_T  config0;
 526 +
 527 +       /* enable TX/RX */
 528 +       config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
 529 +       config0.bits.dis_rx = 0;        /* enable rx */
 530 +       config0.bits.dis_tx = 0;        /* enable tx */
 531 +       __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
 532 +}
 533 +
 534 +static void toe_gmac_disable_tx_rx(struct net_device *dev)
 535 +{
 536 +       struct gmac_private *gmac = netdev_priv(dev);
 537 +       GMAC_CONFIG0_T  config0;
 538 +
 539 +       /* enable TX/RX */
 540 +       config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
 541 +       config0.bits.dis_rx = 1;        /* disable rx */
 542 +       config0.bits.dis_tx = 1;        /* disable tx */
 543 +       __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
 544 +}
 545 +
 546 +static void toe_gmac_tx_complete(struct net_device *dev, unsigned int tx_qid)
 547 +{
 548 +       struct gmac_private             *gmac = netdev_priv(dev);
 549 +       struct toe_private              *toe = dev->ml_priv;
 550 +       GMAC_TXDESC_T                   *curr_desc;
 551 +       GMAC_TXDESC_0_T                 word0;
 552 +       GMAC_TXDESC_1_T                 word1;
 553 +       unsigned int                    desc_count;
 554 +       GMAC_SWTXQ_T                    *swtxq;
 555 +       DMA_RWPTR_T                     rwptr;
 556 +
 557 +       /* get tx H/W completed descriptor virtual address */
 558 +       /* check tx status and accumulate tx statistics */
 559 +       swtxq = &gmac->swtxq[tx_qid];
 560 +       for (;;) {
 561 +               rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
 562 +               if (rwptr.bits.rptr == swtxq->finished_idx)
 563 +                       break;
 564 +               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
 565 +               dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
 566 +                                               swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
 567 +                                               sizeof(GMAC_TXDESC_T),
 568 +                                               DMA_FROM_DEVICE);
 569 +               word0.bits32 = curr_desc->word0.bits32;
 570 +               word1.bits32 = curr_desc->word1.bits32;
 571 +
 572 +               if (word0.bits.status_tx_ok) {
 573 +                       dev->stats.tx_bytes += word1.bits.byte_count;
 574 +                       desc_count = word0.bits.desc_count;
 575 +                       if (desc_count == 0) {
 576 +                               dev_err(&dev->dev, "%s::Desc 0x%x = 0x%x, desc_count=%d\n", __func__, (u32)curr_desc, word0.bits32, desc_count);
 577 +                               BUG();
 578 +                       }
 579 +                       while (--desc_count) {
 580 +                               word0.bits.status_tx_ok = 0;
 581 +                               curr_desc->word0.bits32 = word0.bits32;
 582 +                               dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
 583 +                                                               swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
 584 +                                                               sizeof(GMAC_TXDESC_T),
 585 +                                                               DMA_TO_DEVICE);
 586 +                               swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
 587 +                               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
 588 +                               dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
 589 +                                                               swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
 590 +                                                               sizeof(GMAC_TXDESC_T),
 591 +                                                               DMA_FROM_DEVICE);
 592 +                               word0.bits32 = curr_desc->word0.bits32;
 593 +                       }
 594 +
 595 +                       word0.bits.status_tx_ok = 0;
 596 +                       dev_kfree_skb_any(swtxq->tx_skb[swtxq->finished_idx]);
 597 +                       swtxq->tx_skb[swtxq->finished_idx] = NULL;
 598 +
 599 +                       curr_desc->word0.bits32 = word0.bits32;
 600 +                       dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
 601 +                                                       swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
 602 +                                                       sizeof(GMAC_TXDESC_T),
 603 +                                                       DMA_TO_DEVICE);
 604 +                       dev->stats.tx_packets++;
 605 +                       swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
 606 +               } else {
 607 +                       break;
 608 +               }
 609 +       }
 610 +
 611 +       if (netif_queue_stopped(dev))
 612 +               netif_wake_queue(dev);
 613 +}
 614 +
 615 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
 616 +{
 617 +       struct gmac_private     *gmac = netdev_priv(dev);
 618 +       struct toe_private      *toe = dev->ml_priv;
 619 +       DMA_RWPTR_T             rwptr;
 620 +       GMAC_TXDESC_T           *curr_desc;
 621 +       int                     snd_pages = skb_shinfo(skb)->nr_frags + 1;      /* get number of descriptor */
 622 +       int                     frag_id = 0;
 623 +       int                     len, total_len = skb->len;
 624 +       struct net_device_stats *isPtr = &dev->stats;
 625 +       unsigned int            free_desc;
 626 +       GMAC_SWTXQ_T            *swtxq;
 627 +       register unsigned long  word0, word1, word2, word3;
 628 +       unsigned short          wptr, rptr;
 629 +
 630 +#ifdef GMAC_LEN_1_2_ISSUE
 631 +       int                     total_pages;
 632 +       total_pages = snd_pages;
 633 +#endif
 634 +
 635 +       if (skb->len >= 0x10000) {
 636 +               isPtr->tx_dropped++;
 637 +               dev_err(&dev->dev, "%s::skb->len %d >= 64K\n", __func__, skb->len);
 638 +               netif_stop_queue(dev);
 639 +               return 1;
 640 +       }
 641 +
 642 +#ifdef GMAC_USE_TXQ0
 643 +       #define tx_qid  0
 644 +#endif
 645 +
 646 +       swtxq = &gmac->swtxq[tx_qid];
 647 +
 648 +       rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
 649 +       wptr = rwptr.bits.wptr;
 650 +       rptr = rwptr.bits.rptr;
 651 +
 652 +       /*
 653 +        * check finished desc or empty BD
 654 +        * cannot check by read ptr of RW PTR register,
 655 +        * because the HW complete to send but the SW may NOT handle it
 656 +        */
 657 +#ifdef GMAX_TX_INTR_DISABLED
 658 +       toe_gmac_tx_complete(dev, tx_qid);
 659 +#endif
 660 +       if (wptr >= swtxq->finished_idx)
 661 +               free_desc = TOE_GMAC_SWTXQ_DESC_NUM - wptr + swtxq->finished_idx;
 662 +       else
 663 +               free_desc = swtxq->finished_idx - wptr;
 664 +
 665 +       if (free_desc < snd_pages) {
 666 +               isPtr->tx_dropped++;
 667 +               netif_stop_queue(dev);
 668 +               return 1;
 669 +       }
 670 +
 671 +       while (snd_pages) {
 672 +               dma_addr_t pkt_datap;
 673 +
 674 +               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + wptr;
 675 +               if (frag_id == 0) {
 676 +                       len = skb_headlen(skb);
 677 +                       pkt_datap = dma_map_single(toe->dev, skb->data, len, DMA_TO_DEVICE);
 678 +               } else {
 679 +                       skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_id - 1];
 680 +                       len = frag->size;
 681 +                       pkt_datap = dma_map_page(toe->dev, frag->page.p, frag->page_offset, len, DMA_TO_DEVICE);
 682 +               }
 683 +
 684 +               /* set TX descriptor */
 685 +               word0 = len;
 686 +               word3 = (dev->mtu + 14) | EOFIE_BIT;
 687 +
 688 +#ifdef DO_HW_CHKSUM
 689 +               if (total_len <= 1514 && ip_hdr(skb) && (ip_hdr(skb)->frag_off & __constant_htons(0x3fff)))
 690 +                       word1  = total_len |
 691 +                                       TSS_IP_CHKSUM_BIT  |
 692 +                                       TSS_IPV6_ENABLE_BIT |
 693 +                                       TSS_MTU_ENABLE_BIT;
 694 +               else
 695 +                       word1 = total_len |
 696 +                                       TSS_UDP_CHKSUM_BIT |
 697 +                                       TSS_TCP_CHKSUM_BIT |
 698 +                                       TSS_IP_CHKSUM_BIT  |
 699 +                                       TSS_IPV6_ENABLE_BIT |
 700 +                                       TSS_MTU_ENABLE_BIT;
 701 +#else
 702 +               word1 = total_len | TSS_MTU_ENABLE_BIT;
 703 +#endif
 704 +               word2 = (unsigned long)pkt_datap;
 705 +
 706 +               if (frag_id == 0)
 707 +                       word3 |= SOF_BIT;
 708 +
 709 +               if (snd_pages == 1) {
 710 +                       word3 |= EOF_BIT;
 711 +                       swtxq->tx_skb[wptr] = skb;
 712 +               } else
 713 +                       swtxq->tx_skb[wptr] = NULL;
 714 +
 715 +#ifdef GMAC_LEN_1_2_ISSUE
 716 +               if ((total_pages != snd_pages) && (len == 1 || len == 2) && ((u32)pkt_datap & 0x03)) {
 717 +                       memcpy((void *)&_debug_prefetch_buf[_debug_prefetch_cnt][0], pkt_datap, len);
 718 +                       pkt_datap = (char *)&_debug_prefetch_buf[_debug_prefetch_cnt][0];
 719 +                       word2 = (unsigned long)__pa(pkt_datap);
 720 +                       _debug_prefetch_cnt++;
 721 +                       if (_debug_prefetch_cnt >= _DEBUG_PREFETCH_NUM)
 722 +                               _debug_prefetch_cnt = 0;
 723 +               }
 724 +#endif
 725 +               curr_desc->word0.bits32 = word0;
 726 +               curr_desc->word1.bits32 = word1;
 727 +               curr_desc->word2.bits32 = word2;
 728 +               curr_desc->word3.bits32 = word3;
 729 +               free_desc--;
 730 +               dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
 731 +                                               wptr * sizeof(GMAC_TXDESC_T),
 732 +                                               sizeof(GMAC_TXDESC_T),
 733 +                                               DMA_TO_DEVICE);
 734 +               wptr = RWPTR_ADVANCE_ONE(wptr, TOE_GMAC_SWTXQ_DESC_NUM);
 735 +               frag_id++;
 736 +               snd_pages--;
 737 +       }
 738 +
 739 +       SET_WPTR(swtxq->rwptr_reg, wptr);
 740 +       dev->trans_start = jiffies;
 741 +
 742 +       return 0;
 743 +}
 744 +
 745 +static void __gmac_set_mac_address(struct net_device *dev)
 746 +{
 747 +       struct gmac_private *gmac = netdev_priv(dev);
 748 +       unsigned int    reg_val;
 749 +
 750 +       reg_val = dev->dev_addr[0] + (dev->dev_addr[1] << 8) +
 751 +                 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
 752 +       __raw_writel(reg_val, gmac->base_addr + GMAC_STA_ADD0);
 753 +       reg_val = (__raw_readl(gmac->base_addr + GMAC_STA_ADD1) & 0xFFFF0000) +
 754 +                 dev->dev_addr[4] + (dev->dev_addr[5] << 8);
 755 +       __raw_writel(reg_val, gmac->base_addr + GMAC_STA_ADD1);
 756 +}
 757 +
 758 +static int gmac_set_mac_address(struct net_device *dev, void *addr)
 759 +{
 760 +       struct sockaddr *sa = addr;
 761 +
 762 +       memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
 763 +
 764 +       __gmac_set_mac_address(dev);
 765 +
 766 +       return 0;
 767 +}
 768 +
 769 +static void gmac_get_mac_address(struct net_device *dev)
 770 +{
 771 +       struct gmac_private *gmac = netdev_priv(dev);
 772 +       unsigned int reg_val;
 773 +
 774 +       reg_val = __raw_readl(gmac->base_addr + GMAC_STA_ADD0);
 775 +       dev->dev_addr[0] = reg_val & 0xFF;
 776 +       dev->dev_addr[1] = (reg_val >> 8) & 0xFF;
 777 +       dev->dev_addr[2] = (reg_val >> 16) & 0xFF;
 778 +       dev->dev_addr[3] = (reg_val >> 24) & 0xFF;
 779 +       reg_val = __raw_readl(gmac->base_addr + GMAC_STA_ADD1);
 780 +       dev->dev_addr[4] = reg_val & 0xFF;
 781 +       dev->dev_addr[5] = (reg_val >> 8) & 0xFF;
 782 +
 783 +       if (!is_valid_ether_addr(dev->dev_addr)) {
 784 +               random_ether_addr(dev->dev_addr);
 785 +               __gmac_set_mac_address(dev);
 786 +       }
 787 +}
 788 +
 789 +struct net_device_stats *gmac_get_stats(struct net_device *dev)
 790 +{
 791 +       struct gmac_private *gmac = netdev_priv(dev);
 792 +
 793 +       if (netif_running(dev)) {
 794 +               unsigned short multicast;
 795 +
 796 +               multicast = __raw_readw(gmac->base_addr + GMAC_IN_MCAST) +
 797 +                               __raw_readw(gmac->base_addr + GMAC_IN_BCAST);
 798 +
 799 +               dev->stats.rx_dropped += __raw_readw(gmac->base_addr + GMAC_IN_DISCARDS);
 800 +               dev->stats.rx_errors += __raw_readw(gmac->base_addr + GMAC_IN_ERRORS);
 801 +               dev->stats.rx_packets += __raw_readl(gmac->base_addr + GMAC_IN_MAC1) + multicast;
 802 +               dev->stats.multicast += multicast;
 803 +       }
 804 +
 805 +       return &dev->stats;
 806 +}
 807 +
 808 +/* TODO: If possible use crc32 from kernel lib */
 809 +static unsigned const ethernet_polynomial = 0x04c11db7U;
 810 +static unsigned int ether_crc(int length, unsigned char *data)
 811 +{
 812 +       int crc = -1;
 813 +       unsigned int i;
 814 +       unsigned int crc_val = 0;
 815 +
 816 +       while (--length >= 0) {
 817 +               unsigned char current_octet = *data++;
 818 +               int bit;
 819 +               for (bit = 0; bit < 8; bit++, current_octet >>= 1)
 820 +                       crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
 821 +                               ethernet_polynomial : 0);
 822 +       }
 823 +       crc = ~crc;
 824 +       for (i = 0; i < 32; i++)
 825 +               crc_val = crc_val + (((crc << i) & 0x80000000) >> (31 - i));
 826 +
 827 +       return crc_val;
 828 +}
 829 +
 830 +/*----------------------------------------------------------------------
 831 +* toe_gmac_fill_free_q
 832 +* allocate buffers for free queue.
 833 +*----------------------------------------------------------------------*/
 834 +static void toe_gmac_fill_free_q(struct toe_private *toe)
 835 +{
 836 +       struct sk_buff  *skb;
 837 +       DMA_RWPTR_T     fq_rwptr;
 838 +       GMAC_RXDESC_T   *fq_desc;
 839 +       unsigned long   flags;
 840 +
 841 +       spin_lock_irqsave(&toe->freeq_lock, flags);
 842 +       fq_rwptr.bits32 = __raw_readl(toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
 843 +       while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
 844 +               TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
 845 +               skb = dev_alloc_skb(SW_RX_BUF_SIZE);
 846 +               if (skb == NULL) {
 847 +                       dev_err(toe->dev, "%s::skb allocation fail\n", __func__);
 848 +                       break;
 849 +               }
 850 +               REG32(skb->data) = (unsigned int)skb;
 851 +               skb_reserve(skb, SKB_RESERVE_BYTES);
 852 +               fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
 853 +                       TOE_SW_FREEQ_DESC_NUM);
 854 +               fq_desc = (GMAC_RXDESC_T *)toe->swfq_desc_base + fq_rwptr.bits.wptr;
 855 +               fq_desc->word2.buf_adr = dma_map_single(toe->dev, skb->data,
 856 +                                       SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
 857 +                                       DMA_FROM_DEVICE);
 858 +               dma_sync_single_range_for_device(toe->dev,
 859 +                               toe->sw_freeq_desc_base_dma,
 860 +                               fq_rwptr.bits.wptr * sizeof(GMAC_RXDESC_T),
 861 +                               sizeof(GMAC_RXDESC_T),
 862 +                               DMA_TO_DEVICE);
 863 +               SET_WPTR(toe->global_base + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
 864 +       }
 865 +       spin_unlock_irqrestore(&toe->freeq_lock, flags);
 866 +}
 867 +
 868 +static void fill_free_q_worker(struct work_struct *work)
 869 +{
 870 +       struct toe_private *toe = container_of(work, struct toe_private, freq_work);
 871 +
 872 +       toe_gmac_fill_free_q(toe);
 873 +}
 874 +
 875 +/*----------------------------------------------------------------------
 876 +*      toe_gmac_handle_default_rxq
 877 +*      (1) Get rx Buffer for default Rx queue
 878 +*      (2) notify or call upper-routine to handle it
 879 +*      (3) get a new buffer and insert it into SW free queue
 880 +*      (4) Note: The SW free queue Read-Write Pointer should be locked when accessing
 881 +*----------------------------------------------------------------------*/
 882 +static void toe_gmac_handle_default_rxq(struct net_device *dev)
 883 +{
 884 +       struct gmac_private *gmac = netdev_priv(dev);
 885 +       struct toe_private *toe = dev->ml_priv;
 886 +       GMAC_RXDESC_T   *curr_desc;
 887 +       struct sk_buff  *skb;
 888 +       DMA_RWPTR_T     rwptr;
 889 +       unsigned int    pkt_size;
 890 +       int             max_cnt;
 891 +       unsigned int    desc_count;
 892 +       unsigned int    chksum_status, rx_status;
 893 +       struct net_device_stats *isPtr = &dev->stats;
 894 +
 895 +       rwptr.bits32 = __raw_readl(&gmac->default_qhdr->word1);
 896 +       max_cnt = DEFAULT_RXQ_MAX_CNT;
 897 +       while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr) {
 898 +               curr_desc = (GMAC_RXDESC_T *)gmac->default_desc_base + rwptr.bits.rptr;
 899 +               dma_sync_single_range_for_device(toe->dev,
 900 +                               gmac->default_desc_base_dma,
 901 +                               rwptr.bits.rptr * sizeof(GMAC_RXDESC_T),
 902 +                               sizeof(GMAC_RXDESC_T),
 903 +                               DMA_FROM_DEVICE);
 904 +               rx_status = curr_desc->word0.bits.status;
 905 +               chksum_status = curr_desc->word0.bits.chksum_status;
 906 +               pkt_size = curr_desc->word1.bits.byte_count;    /* total byte count in a frame */
 907 +               desc_count = curr_desc->word0.bits.desc_count;  /* get descriptor count per frame */
 908 +               skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
 909 +
 910 +               if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
 911 +                       || (pkt_size < 60) || (chksum_status & 0x4) || rx_status) {
 912 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
 913 +                               dev_err(&dev->dev, "%s::derr\n", __func__);
 914 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
 915 +                               dev_err(&dev->dev, "%s::perr\n", __func__);
 916 +                       if (rx_status && (rx_status == 4 || rx_status == 7))
 917 +                               isPtr->rx_crc_errors++;
 918 +
 919 +                       dev_kfree_skb_irq(skb);
 920 +                       goto bad_frame;
 921 +               }
 922 +
 923 +               if (curr_desc->word0.bits.drop)
 924 +                       dev_warn(&dev->dev, "%s::Drop\n", __func__);
 925 +
 926 +               /* get frame information from the first descriptor of the frame */
 927 +               skb_reserve(skb, RX_INSERT_BYTES);      /* 16 byte align the IP fields. */
 928 +               skb_put(skb, pkt_size);
 929 +               skb->dev = dev;
 930 +               skb->protocol = eth_type_trans(skb, dev);
 931 +               if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK || chksum_status == RX_CHKSUM_IP_OK_ONLY)
 932 +                       skb->ip_summed = CHECKSUM_UNNECESSARY;
 933 +
 934 +               netif_rx(skb);  /* socket rx */
 935 +               dev->last_rx = jiffies;
 936 +
 937 +               isPtr->rx_bytes += pkt_size;
 938 +
 939 +bad_frame:
 940 +               /* advance one for Rx default Q 0/1 */
 941 +               rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, TOE_DEFAULT_Q_DESC_NUM);
 942 +               SET_RPTR(&gmac->default_qhdr->word1, rwptr.bits.rptr);
 943 +       }
 944 +
 945 +       schedule_work(&toe->freq_work);
 946 +}
 947 +
 948 +static irqreturn_t toe_gmac_interrupt(int irq, void *dev_instance)
 949 +{
 950 +       struct net_device       *dev = dev_instance;
 951 +       struct gmac_private     *gmac = netdev_priv(dev);
 952 +       struct toe_private      *toe = dev->ml_priv;
 953 +       unsigned int            status0;
 954 +       unsigned int            status1;
 955 +       unsigned int            status2;
 956 +       unsigned int            status3;
 957 +       unsigned int            status4;
 958 +       int                     handled = 0;
 959 +
 960 +       /* read Interrupt status */
 961 +       status0 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
 962 +       status1 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
 963 +       status2 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
 964 +       status3 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
 965 +       status4 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
 966 +
 967 +       /* clear interrupts */
 968 +       if (status0)
 969 +               __raw_writel(status0, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
 970 +       if (status1)
 971 +               __raw_writel(status1, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
 972 +       if (status2)
 973 +               __raw_writel(status2, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
 974 +       if (status3)
 975 +               __raw_writel(status3, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
 976 +       if (status4)
 977 +               __raw_writel(status4, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
 978 +
 979 +       /* handle freeq interrupt first */
 980 +       if (status4 & gmac->intr4_enabled) {
 981 +               if ((status4 & SWFQ_EMPTY_INT_BIT) && (gmac->intr4_enabled & SWFQ_EMPTY_INT_BIT)) {
 982 +                       toe_gmac_fill_free_q(toe);
 983 +                       handled = 1;
 984 +               }
 985 +       }
 986 +
 987 +       /* Interrupt Status 1 */
 988 +       if (status1 & gmac->intr1_enabled) {
 989 +               /*
 990 +                * Handle GMAC 0/1 HW Tx queue 0-3 EOF events
 991 +                * Only count
 992 +                * TOE, Classification, and default queues interrupts are handled by ISR
 993 +                * because they should pass packets to upper layer
 994 +                */
 995 +               if (gmac->port_id == 0) {
 996 +                       if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q0_INT_BIT)) {
 997 +                               toe_gmac_handle_default_rxq(dev);
 998 +                               handled = 1;
 999 +                       }
1000 +               } else if (gmac->port_id == 1) {
1001 +                       if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q1_INT_BIT)) {
1002 +                               toe_gmac_handle_default_rxq(dev);
1003 +                               handled = 1;
1004 +                       }
1005 +               }
1006 +       }
1007 +
1008 +       /* Interrupt Status 0 */
1009 +       if (status0 & gmac->intr0_enabled) {
1010 +#ifndef        GMAX_TX_INTR_DISABLED
1011 +               if (gmac->port_id == 1 && netif_running(dev) &&
1012 +                       (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
1013 +                       ||
1014 +                       ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT)))) {
1015 +                       toe_gmac_tx_complete(dev, 0);
1016 +                       handled = 1;
1017 +               }
1018 +
1019 +               if (gmac->port_id == 0 && netif_running(dev) &&
1020 +                       (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
1021 +                       ||
1022 +                       ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT)))) {
1023 +                       toe_gmac_tx_complete(dev, 0);
1024 +                       handled = 1;
1025 +               }
1026 +#endif
1027 +       }
1028 +
1029 +       return IRQ_RETVAL(handled);
1030 +}
1031 +
1032 +static int gmac_open(struct net_device *dev)
1033 +{
1034 +       struct gmac_private     *gmac = netdev_priv(dev);
1035 +       int                     retval;
1036 +
1037 +       /* hook ISR */
1038 +       retval = request_irq(dev->irq, toe_gmac_interrupt, 0, dev->name, dev);
1039 +       if (retval)
1040 +               return retval;
1041 +
1042 +       toe_init_gmac(dev);
1043 +
1044 +       netif_carrier_off(dev);
1045 +       phy_start(gmac->phydev);
1046 +
1047 +       netif_start_queue(dev);
1048 +
1049 +       return 0;
1050 +}
1051 +
1052 +static int gmac_close(struct net_device *dev)
1053 +{
1054 +       struct gmac_private     *gmac = netdev_priv(dev);
1055 +
1056 +       netif_stop_queue(dev);
1057 +       mdelay(20);
1058 +
1059 +       if (gmac->phydev)
1060 +               phy_stop(gmac->phydev);
1061 +
1062 +       /* stop tx/rx packet */
1063 +       toe_gmac_disable_tx_rx(dev);
1064 +       mdelay(20);
1065 +
1066 +       /* stop the chip's Tx and Rx DMA processes */
1067 +       toe_gmac_hw_stop(gmac);
1068 +
1069 +       disable_irq(dev->irq);
1070 +       free_irq(dev->irq, dev);
1071 +
1072 +       return 0;
1073 +}
1074 +
1075 +static void gmac_get_phy_status(struct net_device *dev)
1076 +{
1077 +       struct gmac_private *gmac = netdev_priv(dev);
1078 +       GMAC_CONFIG0_T  config0;
1079 +       GMAC_STATUS_T   status, old_status;
1080 +       struct phy_device *phydev = gmac->phydev;
1081 +
1082 +       old_status.bits32 = status.bits32 = __raw_readl(gmac->base_addr + GMAC_STATUS);
1083 +
1084 +       status.bits.link = phydev->link;
1085 +       status.bits.duplex = phydev->duplex;
1086 +
1087 +       switch (phydev->speed) {
1088 +       case 1000:
1089 +               status.bits.speed = GMAC_SPEED_1000;
1090 +               if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1091 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
1092 +               break;
1093 +       case 100:
1094 +               status.bits.speed = GMAC_SPEED_100;
1095 +               if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1096 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
1097 +               break;
1098 +       case 10:
1099 +               status.bits.speed = GMAC_SPEED_10;
1100 +               if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1101 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
1102 +               break;
1103 +       default:
1104 +               dev_warn(&dev->dev, "Not supported PHY speed (%d)\n", phydev->speed);
1105 +       }
1106 +
1107 +       if (phydev->pause) {
1108 +               if (gmac->flow_control_enable == 0) {
1109 +                       config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
1110 +                       config0.bits.tx_fc_en = 1;      /* enable tx flow control */
1111 +                       config0.bits.rx_fc_en = 1;      /* enable rx flow control */
1112 +                       __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
1113 +                       dev_info(&dev->dev, "MII flow control enabled\n");
1114 +               }
1115 +               gmac->flow_control_enable = 1;
1116 +       } else {
1117 +               if (gmac->flow_control_enable == 1) {
1118 +                       config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
1119 +                       config0.bits.tx_fc_en = 0;      /* disable tx flow control */
1120 +                       config0.bits.rx_fc_en = 0;      /* disable rx flow control */
1121 +                       __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
1122 +                       dev_info(&dev->dev, "MII flow control disabled\n");
1123 +               }
1124 +               gmac->flow_control_enable = 0;
1125 +       }
1126 +
1127 +       if (old_status.bits32 != status.bits32) {
1128 +               toe_gmac_disable_tx_rx(dev);
1129 +               phy_print_status(phydev);
1130 +               mdelay(10);     /* let GMAC consume packet */
1131 +               __raw_writel(status.bits32, gmac->base_addr + GMAC_STATUS);
1132 +               if (status.bits.link)
1133 +                       toe_gmac_enable_tx_rx(dev);
1134 +       }
1135 +}
1136 +
1137 +static void gmac_set_rx_mode(struct net_device *dev)
1138 +{
1139 +       struct gmac_private *gmac = netdev_priv(dev);
1140 +       GMAC_RX_FLTR_T  filter;
1141 +       unsigned int    mc_filter[2];   /* Multicast hash filter */
1142 +       int             bit_nr;
1143 +
1144 +       filter.bits32 = 0;
1145 +       filter.bits.error = 0;
1146 +       if (dev->flags & IFF_PROMISC) {
1147 +               filter.bits.error = 1;
1148 +               filter.bits.promiscuous = 1;
1149 +               filter.bits.broadcast = 1;
1150 +               filter.bits.multicast = 1;
1151 +               filter.bits.unicast = 1;
1152 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
1153 +       } else if (dev->flags & IFF_ALLMULTI) {
1154 +               filter.bits.broadcast = 1;
1155 +               filter.bits.multicast = 1;
1156 +               filter.bits.unicast = 1;
1157 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
1158 +       } else {
1159 +               struct netdev_hw_addr *ha;
1160 +
1161 +               filter.bits.broadcast = 1;
1162 +               filter.bits.multicast = 1;
1163 +               filter.bits.unicast = 1;
1164 +               mc_filter[1] = mc_filter[0] = 0;
1165 +               netdev_for_each_mc_addr(ha, dev) {
1166 +                       bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
1167 +                       if (bit_nr <= 32)
1168 +                               mc_filter[0] = mc_filter[0] | (1 << bit_nr);
1169 +                       else
1170 +                               mc_filter[1] = mc_filter[1] | (1 << (bit_nr - 32));
1171 +               }
1172 +       }
1173 +       __raw_writel(filter.bits32, gmac->base_addr + GMAC_RX_FLTR);
1174 +       __raw_writel(mc_filter[0], gmac->base_addr + GMAC_MCAST_FIL0);
1175 +       __raw_writel(mc_filter[1], gmac->base_addr + GMAC_MCAST_FIL1);
1176 +}
1177 +
1178 +static void gmac_tx_timeout(struct net_device *dev)
1179 +{
1180 +       if (!netif_queue_stopped(dev))
1181 +               netif_wake_queue(dev);
1182 +
1183 +       dev_warn(&dev->dev, "TX timeout\n");
1184 +}
1185 +
1186 +const static struct net_device_ops gemini_gmac_ops = {
1187 +       .ndo_open               = gmac_open,
1188 +       .ndo_stop               = gmac_close,
1189 +       .ndo_start_xmit         = gmac_start_xmit,
1190 +       .ndo_get_stats          = gmac_get_stats,
1191 +       .ndo_set_rx_mode        = gmac_set_rx_mode,
1192 +       .ndo_set_mac_address    = gmac_set_mac_address,
1193 +       .ndo_tx_timeout         = gmac_tx_timeout,
1194 +};
1195 +
1196 +static void mac_init_drv(struct toe_private *toe)
1197 +{
1198 +       QUEUE_THRESHOLD_T       threshold;
1199 +       DMA_SKB_SIZE_T          skb_size;
1200 +
1201 +       /* clear non TOE Queue Header Area */
1202 +       memset(toe->global_base + TOE_NONTOE_QUE_HDR_BASE, 0,
1203 +               NONTOE_Q_HDR_AREA_END - TOE_NONTOE_QUE_HDR_BASE);
1204 +
1205 +       /* clear TOE Queue Header Area */
1206 +       memset(toe->global_base + TOE_TOE_QUE_HDR_BASE, 0,
1207 +               TOE_Q_HDR_AREA_END - TOE_TOE_QUE_HDR_BASE);
1208 +
1209 +       /* Write GLOBAL_QUEUE_THRESHOLD_REG */
1210 +       threshold.bits32 = 0;
1211 +       threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
1212 +                                       TOE_SW_FREEQ_DESC_NUM / 2;
1213 +       threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256 / 4 :
1214 +                                       TOE_HW_FREEQ_DESC_NUM / 4;
1215 +       threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256 / 4 :
1216 +                                       TOE_TOE_DESC_NUM / 4;
1217 +       threshold.bits.intrq = (TOE_INTR_DESC_NUM > 256) ? 256 / 4 :
1218 +                                       TOE_INTR_DESC_NUM / 4;
1219 +       __raw_writel(threshold.bits32, toe->global_base + GLOBAL_QUEUE_THRESHOLD_REG);
1220 +
1221 +       /* Init skb size */
1222 +       skb_size.bits.hw_skb_size = HW_RX_BUF_SIZE;
1223 +       skb_size.bits.sw_skb_size = SW_RX_BUF_SIZE;
1224 +       __raw_writel(skb_size.bits32, toe->global_base + GLOBAL_DMA_SKB_SIZE_REG);
1225 +
1226 +       toe_init_free_queue(toe);
1227 +       toe_init_interrupt_config(toe);
1228 +}
1229 +
1230 +static int gmac_init_eth(struct platform_device *pdev,
1231 +                                  unsigned int num)
1232 +{
1233 +       struct gmac_private     *gmac;
1234 +       struct net_device       *dev;
1235 +       struct toe_private      *toe = platform_get_drvdata(pdev);
1236 +       struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
1237 +
1238 +       if (!pdata->bus_id[num])
1239 +               return 0;
1240 +
1241 +       dev = alloc_etherdev(sizeof(*gmac));
1242 +       if (dev == NULL) {
1243 +               dev_err(&pdev->dev, "Can't allocate ethernet device #%d\n", num);
1244 +               return -ENOMEM;
1245 +       }
1246 +
1247 +       gmac = netdev_priv(dev);
1248 +       dev->ml_priv = toe;
1249 +       toe->net_dev[num] = dev;
1250 +
1251 +       gmac->base_addr = toe->global_base + TOE_GMAC_BASE(num);
1252 +       gmac->dma_base_addr = toe->global_base + TOE_GMAC_DMA_BASE(num);
1253 +       gmac->port_id = num;
1254 +
1255 +       dev->base_addr = (unsigned int) gmac->base_addr;
1256 +       dev->irq = platform_get_irq(pdev, num);
1257 +       dev->netdev_ops = &gemini_gmac_ops;
1258 +       dev->watchdog_timeo = GMAC_DEV_TX_TIMEOUT;
1259 +       dev->tx_queue_len = TOE_GMAC_SWTXQ_DESC_NUM;
1260 +
1261 +#ifdef DO_HW_CHKSUM
1262 +       dev->features = NETIF_F_SG | NETIF_F_HW_CSUM;
1263 +#ifdef ENABLE_TSO
1264 +       dev->features |= NETIF_F_TSO;
1265 +#endif
1266 +#endif
1267 +
1268 +       toe_init_swtx_queue(dev);
1269 +       toe_init_default_queue(dev);
1270 +
1271 +       gmac_get_mac_address(dev);
1272 +
1273 +       /* TODO: Do we need this? */
1274 +       __raw_writel(0x55aa55aa, gmac->base_addr + GMAC_STA_ADD2);
1275 +
1276 +       if (register_netdev(dev))
1277 +               return -1;
1278 +
1279 +       gmac->phydev = phy_connect(dev, pdata->bus_id[num], &gmac_get_phy_status,
1280 +                                pdata->interface[num]);
1281 +       if (IS_ERR(gmac->phydev))
1282 +               return PTR_ERR(gmac->phydev);
1283 +
1284 +       gmac->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause;
1285 +       gmac->phydev->advertising = gmac->phydev->supported;
1286 +
1287 +       return 0;
1288 +}
1289 +
1290 +static int gmac_probe(struct platform_device *pdev)
1291 +{
1292 +       struct resource                         *res;
1293 +       struct toe_private                      *toe;
1294 +       int                                     retval;
1295 +
1296 +       if (!pdev->dev.platform_data)
1297 +               return -EINVAL;
1298 +
1299 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1300 +       if (!res) {
1301 +               dev_err(&pdev->dev, "can't get device resources\n");
1302 +               return -ENODEV;
1303 +       }
1304 +
1305 +       toe = kzalloc(sizeof(struct toe_private), GFP_KERNEL);
1306 +       if (!toe)
1307 +               return -ENOMEM;
1308 +
1309 +       toe->dev = &pdev->dev;
1310 +
1311 +       toe->global_base = ioremap(res->start, resource_size(res));
1312 +       if (!toe->global_base) {
1313 +               dev_err(toe->dev, "ioremap failed\n");
1314 +               retval = -EIO;
1315 +               goto err_data;
1316 +       }
1317 +
1318 +       platform_set_drvdata(pdev, toe);
1319 +
1320 +       mac_init_drv(toe);
1321 +
1322 +       INIT_WORK(&toe->freq_work, fill_free_q_worker);
1323 +       spin_lock_init(&toe->freeq_lock);
1324 +
1325 +       retval = gmac_init_eth(pdev, GMAC_PORT0);
1326 +       if (retval)
1327 +               goto err_unmap;
1328 +       retval = gmac_init_eth(pdev, GMAC_PORT1);
1329 +       if (retval)
1330 +               goto err_unmap;
1331 +
1332 +       dev_info(&pdev->dev, SL351x_DRIVER_NAME "\n");
1333 +
1334 +       return 0;
1335 +
1336 +err_unmap:
1337 +       iounmap(toe->global_base);
1338 +err_data:
1339 +       kfree(toe);
1340 +       return retval;
1341 +}
1342 +
1343 +static int gmac_remove(struct platform_device *pdev)
1344 +{
1345 +       struct toe_private *toe = platform_get_drvdata(pdev);
1346 +       int i;
1347 +
1348 +       for (i = 0; i < 2; i++)
1349 +               if (toe->net_dev[i]) {
1350 +                       unregister_netdev(toe->net_dev[i]);
1351 +                       kfree(toe->net_dev[i]);
1352 +               }
1353 +
1354 +       iounmap(toe->global_base);
1355 +
1356 +       kfree(toe);
1357 +
1358 +       return 0;
1359 +}
1360 +
1361 +static struct platform_driver gemini_gmac_driver = {
1362 +       .probe          = gmac_probe,
1363 +       .remove         = gmac_remove,
1364 +       .driver         = {
1365 +               .name   = "gemini-gmac",
1366 +               .owner  = THIS_MODULE,
1367 +       },
1368 +};
1369 +
1370 +static int __init gemini_gmac_init(void)
1371 +{
1372 +       return platform_driver_register(&gemini_gmac_driver);
1373 +}
1374 +
1375 +static void __exit gemini_gmac_exit(void)
1376 +{
1377 +       platform_driver_unregister(&gemini_gmac_driver);
1378 +}
1379 +
1380 +module_init(gemini_gmac_init);
1381 +module_exit(gemini_gmac_exit);
1382 +
1383 +MODULE_AUTHOR("Paulius Zaleckas");
1384 +MODULE_DESCRIPTION("Ethernet device driver for Gemini SoC");
1385 +MODULE_LICENSE("GPL");
1386 +MODULE_ALIAS("platform:gemini-gmac");
1387 --- /dev/null
1388 +++ b/drivers/net/gemini_negmac/gm_gmac.h
1389 @@ -0,0 +1,1489 @@
1390 +/*
1391 + *  Register definitions for Gemini Ethernet device driver.
1392 + *
1393 + *  Copyright (C) 2006, Storlink, Corp.
1394 + *  Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
1395 + *
1396 + * This program is free software; you can redistribute it and/or modify
1397 + * it under the terms of the GNU General Public License as published by
1398 + * the Free Software Foundation; either version 2 of the License, or
1399 + * (at your option) any later version.
1400 + */
1401 +#ifndef _GMAC_SL351x_H
1402 +#define _GMAC_SL351x_H
1403 +#include <linux/skbuff.h>
1404 +
1405 +#define _PACKED_                       __attribute__ ((aligned(1), packed))
1406 +
1407 +#ifndef BIT
1408 +#define BIT(x)                         (1 << (x))
1409 +#endif
1410 +
1411 +#define REG32(addr)                    (*(volatile unsigned long  * const)(addr))
1412 +
1413 +/* Define frame size */
1414 +#define GMAC_MAX_ETH_FRAME_SIZE                1514
1415 +#define GMAC_TX_BUF_SIZE               ((GMAC_MAX_ETH_FRAME_SIZE + 31) & (~31))
1416 +
1417 +#define SW_RX_BUF_SIZE                 1536
1418 +#define HW_RX_BUF_SIZE                 1536
1419 +
1420 +#define GMAC_DEV_TX_TIMEOUT            (10*HZ)
1421 +#define        SKB_RESERVE_BYTES               16
1422 +
1423 +/*
1424 + * Base Registers
1425 + */
1426 +#define TOE_NONTOE_QUE_HDR_BASE                0x2000
1427 +#define TOE_TOE_QUE_HDR_BASE           0x3000
1428 +#define TOE_V_BIT_BASE                 0x4000
1429 +#define TOE_A_BIT_BASE                 0x6000
1430 +#define TOE_GMAC_DMA_BASE(x)           (0x8000 + 0x4000 * (x))
1431 +#define TOE_GMAC_BASE(x)               (0xA000 + 0x4000 * (x))
1432 +
1433 +/*
1434 + * Queue ID
1435 + */
1436 +#define TOE_SW_FREE_QID                        0x00
1437 +#define TOE_HW_FREE_QID                        0x01
1438 +#define TOE_GMAC0_SW_TXQ0_QID          0x02
1439 +#define TOE_GMAC0_SW_TXQ1_QID          0x03
1440 +#define TOE_GMAC0_SW_TXQ2_QID          0x04
1441 +#define TOE_GMAC0_SW_TXQ3_QID          0x05
1442 +#define TOE_GMAC0_SW_TXQ4_QID          0x06
1443 +#define TOE_GMAC0_SW_TXQ5_QID          0x07
1444 +#define TOE_GMAC0_HW_TXQ0_QID          0x08
1445 +#define TOE_GMAC0_HW_TXQ1_QID          0x09
1446 +#define TOE_GMAC0_HW_TXQ2_QID          0x0A
1447 +#define TOE_GMAC0_HW_TXQ3_QID          0x0B
1448 +#define TOE_GMAC1_SW_TXQ0_QID          0x12
1449 +#define TOE_GMAC1_SW_TXQ1_QID          0x13
1450 +#define TOE_GMAC1_SW_TXQ2_QID          0x14
1451 +#define TOE_GMAC1_SW_TXQ3_QID          0x15
1452 +#define TOE_GMAC1_SW_TXQ4_QID          0x16
1453 +#define TOE_GMAC1_SW_TXQ5_QID          0x17
1454 +#define TOE_GMAC1_HW_TXQ0_QID          0x18
1455 +#define TOE_GMAC1_HW_TXQ1_QID          0x19
1456 +#define TOE_GMAC1_HW_TXQ2_QID          0x1A
1457 +#define TOE_GMAC1_HW_TXQ3_QID          0x1B
1458 +#define TOE_GMAC0_DEFAULT_QID          0x20
1459 +#define TOE_GMAC1_DEFAULT_QID          0x21
1460 +#define TOE_CLASSIFICATION_QID(x)      (0x22 + x)      // 0x22 ~ 0x2F
1461 +#define TOE_TOE_QID(x)                 (0x40 + x)      // 0x40 ~ 0x7F
1462 +
1463 +/*
1464 + * TOE DMA Queue Number should be 2^n, n = 6...12
1465 + * TOE DMA Queues are the following queue types:
1466 + *             SW Free Queue, HW Free Queue,
1467 + *             GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
1468 + * They have same descriptor numbers.
1469 + * The base address and descriptor number are configured at
1470 + * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
1471 + */
1472 +#define TOE_SW_FREEQ_DESC_POWER                8
1473 +#define TOE_SW_FREEQ_DESC_NUM          (1<<TOE_SW_FREEQ_DESC_POWER)
1474 +#define TOE_HW_FREEQ_DESC_POWER                8
1475 +#define TOE_HW_FREEQ_DESC_NUM          (1<<TOE_HW_FREEQ_DESC_POWER)
1476 +#define TOE_GMAC_SWTXQ_DESC_POWER      8
1477 +#define TOE_GMAC_SWTXQ_DESC_NUM                (1<<TOE_GMAC_SWTXQ_DESC_POWER)
1478 +#define TOE_GMAC_HWTXQ_DESC_POWER      8
1479 +#define TOE_GMAC_HWTXQ_DESC_NUM                (1<<TOE_GMAC_HWTXQ_DESC_POWER)
1480 +#define TOE_DEFAULT_Q_DESC_POWER       8
1481 +#define TOE_DEFAULT_Q_DESC_NUM         (1<<TOE_DEFAULT_Q_DESC_POWER)
1482 +#define TOE_TOE_DESC_POWER             8
1483 +#define TOE_TOE_DESC_NUM               (1<<TOE_TOE_DESC_POWER)
1484 +#define TOE_CLASS_DESC_POWER           8
1485 +#define TOE_CLASS_DESC_NUM             (1<<TOE_CLASS_DESC_POWER)
1486 +#define TOE_INTR_DESC_POWER            8
1487 +#define TOE_INTR_DESC_NUM              (1<<TOE_INTR_DESC_POWER)
1488 +
1489 +#define TOE_TOE_QUEUE_MAX      64
1490 +#define TOE_TOE_QUEUE_NUM      64
1491 +#define TOE_CLASS_QUEUE_MAX    14
1492 +#define TOE_CLASS_QUEUE_NUM    14
1493 +#define TOE_INTR_QUEUE_MAX     4
1494 +#define TOE_INTR_QUEUE_NUM     4
1495 +#define TOE_SW_TXQ_MAX         6
1496 +#define TOE_SW_TXQ_NUM         1
1497 +#define TOE_HW_TXQ_MAX         4
1498 +#define TOE_HW_TXQ_NUM         4
1499 +
1500 +#define RWPTR_ADVANCE_ONE(x, max)      ((x == (max -1)) ? 0 : x+1)
1501 +#define RWPTR_RECEDE_ONE(x, max)       ((x == 0) ? (max -1) : x-1)
1502 +#define SET_WPTR(addr, data)           (*(volatile u16 * const)((u32)(addr) + 2) = (u16)data)
1503 +#define SET_RPTR(addr, data)           (*(volatile u16 * const)((u32)(addr)) = (u16)data)
1504 +
1505 +/*
1506 + * Global registers
1507 + * #define TOE_GLOBAL_BASE                     (TOE_BASE + 0x0000)
1508 + * Base 0x60000000
1509 + */
1510 +#define GLOBAL_TOE_VERSION_REG         0x0000
1511 +#define GLOBAL_SW_FREEQ_BASE_SIZE_REG  0x0004
1512 +#define GLOBAL_HW_FREEQ_BASE_SIZE_REG  0x0008
1513 +#define GLOBAL_DMA_SKB_SIZE_REG                0x0010
1514 +#define GLOBAL_SWFQ_RWPTR_REG          0x0014
1515 +#define GLOBAL_HWFQ_RWPTR_REG          0x0018
1516 +#define GLOBAL_INTERRUPT_STATUS_0_REG  0x0020
1517 +#define GLOBAL_INTERRUPT_ENABLE_0_REG  0x0024
1518 +#define GLOBAL_INTERRUPT_SELECT_0_REG  0x0028
1519 +#define GLOBAL_INTERRUPT_STATUS_1_REG  0x0030
1520 +#define GLOBAL_INTERRUPT_ENABLE_1_REG  0x0034
1521 +#define GLOBAL_INTERRUPT_SELECT_1_REG  0x0038
1522 +#define GLOBAL_INTERRUPT_STATUS_2_REG  0x0040
1523 +#define GLOBAL_INTERRUPT_ENABLE_2_REG  0x0044
1524 +#define GLOBAL_INTERRUPT_SELECT_2_REG  0x0048
1525 +#define GLOBAL_INTERRUPT_STATUS_3_REG  0x0050
1526 +#define GLOBAL_INTERRUPT_ENABLE_3_REG  0x0054
1527 +#define GLOBAL_INTERRUPT_SELECT_3_REG  0x0058
1528 +#define GLOBAL_INTERRUPT_STATUS_4_REG  0x0060
1529 +#define GLOBAL_INTERRUPT_ENABLE_4_REG  0x0064
1530 +#define GLOBAL_INTERRUPT_SELECT_4_REG  0x0068
1531 +#define GLOBAL_HASH_TABLE_BASE_REG     0x006C
1532 +#define GLOBAL_QUEUE_THRESHOLD_REG     0x0070
1533 +
1534 +/*
1535 + * GMAC 0/1 DMA/TOE register
1536 + * #define TOE_GMAC0_DMA_BASE          (TOE_BASE + 0x8000)
1537 + * #define TOE_GMAC1_DMA_BASE          (TOE_BASE + 0xC000)
1538 + * Base 0x60008000 or 0x6000C000
1539 + */
1540 +#define GMAC_DMA_CTRL_REG              0x0000
1541 +#define GMAC_TX_WEIGHTING_CTRL_0_REG   0x0004
1542 +#define GMAC_TX_WEIGHTING_CTRL_1_REG   0x0008
1543 +#define GMAC_SW_TX_QUEUE0_PTR_REG      0x000C
1544 +#define GMAC_SW_TX_QUEUE1_PTR_REG      0x0010
1545 +#define GMAC_SW_TX_QUEUE2_PTR_REG      0x0014
1546 +#define GMAC_SW_TX_QUEUE3_PTR_REG      0x0018
1547 +#define GMAC_SW_TX_QUEUE4_PTR_REG      0x001C
1548 +#define GMAC_SW_TX_QUEUE5_PTR_REG      0x0020
1549 +#define GMAC_HW_TX_QUEUE0_PTR_REG      0x0024
1550 +#define GMAC_HW_TX_QUEUE1_PTR_REG      0x0028
1551 +#define GMAC_HW_TX_QUEUE2_PTR_REG      0x002C
1552 +#define GMAC_HW_TX_QUEUE3_PTR_REG      0x0030
1553 +#define GMAC_DMA_TX_FIRST_DESC_REG     0x0038
1554 +#define GMAC_DMA_TX_CURR_DESC_REG      0x003C
1555 +#define GMAC_DMA_TX_DESC_WORD0_REG     0x0040
1556 +#define GMAC_DMA_TX_DESC_WORD1_REG     0x0044
1557 +#define GMAC_DMA_TX_DESC_WORD2_REG     0x0048
1558 +#define GMAC_DMA_TX_DESC_WORD3_REG     0x004C
1559 +#define GMAC_SW_TX_QUEUE_BASE_REG      0x0050
1560 +#define GMAC_HW_TX_QUEUE_BASE_REG      0x0054
1561 +#define GMAC_DMA_RX_FIRST_DESC_REG     0x0058
1562 +#define GMAC_DMA_RX_CURR_DESC_REG      0x005C
1563 +#define GMAC_DMA_RX_DESC_WORD0_REG     0x0060
1564 +#define GMAC_DMA_RX_DESC_WORD1_REG     0x0064
1565 +#define GMAC_DMA_RX_DESC_WORD2_REG     0x0068
1566 +#define GMAC_DMA_RX_DESC_WORD3_REG     0x006C
1567 +#define GMAC_HASH_ENGINE_REG0          0x0070
1568 +#define GMAC_HASH_ENGINE_REG1          0x0074
1569 +/* matching rule 0 Control register 0 */
1570 +#define GMAC_MR0CR0                    0x0078
1571 +#define GMAC_MR0CR1                    0x007C
1572 +#define GMAC_MR0CR2                    0x0080
1573 +#define GMAC_MR1CR0                    0x0084
1574 +#define GMAC_MR1CR1                    0x0088
1575 +#define GMAC_MR1CR2                    0x008C
1576 +#define GMAC_MR2CR0                    0x0090
1577 +#define GMAC_MR2CR1                    0x0094
1578 +#define GMAC_MR2CR2                    0x0098
1579 +#define GMAC_MR3CR0                    0x009C
1580 +#define GMAC_MR3CR1                    0x00A0
1581 +#define GMAC_MR3CR2                    0x00A4
1582 +/* Support Protocol Regsister 0 */
1583 +#define GMAC_SPR0                      0x00A8
1584 +#define GMAC_SPR1                      0x00AC
1585 +#define GMAC_SPR2                      0x00B0
1586 +#define GMAC_SPR3                      0x00B4
1587 +#define GMAC_SPR4                      0x00B8
1588 +#define GMAC_SPR5                      0x00BC
1589 +#define GMAC_SPR6                      0x00C0
1590 +#define GMAC_SPR7                      0x00C4
1591 +/* GMAC Hash/Rx/Tx AHB Weighting register */
1592 +#define GMAC_AHB_WEIGHT_REG            0x00C8
1593 +
1594 +/*
1595 + * TOE GMAC 0/1 register
1596 + * #define TOE_GMAC0_BASE                              (TOE_BASE + 0xA000)
1597 + * #define TOE_GMAC1_BASE                              (TOE_BASE + 0xE000)
1598 + * Base 0x6000A000 or 0x6000E000
1599 + */
1600 +enum GMAC_REGISTER {
1601 +       GMAC_STA_ADD0   = 0x0000,
1602 +       GMAC_STA_ADD1   = 0x0004,
1603 +       GMAC_STA_ADD2   = 0x0008,
1604 +       GMAC_RX_FLTR    = 0x000c,
1605 +       GMAC_MCAST_FIL0 = 0x0010,
1606 +       GMAC_MCAST_FIL1 = 0x0014,
1607 +       GMAC_CONFIG0    = 0x0018,
1608 +       GMAC_CONFIG1    = 0x001c,
1609 +       GMAC_CONFIG2    = 0x0020,
1610 +       GMAC_CONFIG3    = 0x0024,
1611 +       GMAC_RESERVED   = 0x0028,
1612 +       GMAC_STATUS     = 0x002c,
1613 +       GMAC_IN_DISCARDS= 0x0030,
1614 +       GMAC_IN_ERRORS  = 0x0034,
1615 +       GMAC_IN_MCAST   = 0x0038,
1616 +       GMAC_IN_BCAST   = 0x003c,
1617 +       GMAC_IN_MAC1    = 0x0040,       /* for STA 1 MAC Address */
1618 +       GMAC_IN_MAC2    = 0x0044        /* for STA 2 MAC Address */
1619 +};
1620 +
1621 +/*
1622 + * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
1623 + */
1624 +typedef union {
1625 +       unsigned int bits32;
1626 +       unsigned int base_size;
1627 +} DMA_Q_BASE_SIZE_T;
1628 +#define DMA_Q_BASE_MASK        (~0x0f)
1629 +
1630 +/*
1631 + * DMA SKB Buffer register (offset 0x0008)
1632 + */
1633 +typedef union {
1634 +       unsigned int bits32;
1635 +       struct bit_0008 {
1636 +               unsigned int sw_skb_size : 16;  /* SW Free poll SKB Size */
1637 +               unsigned int hw_skb_size : 16;  /* HW Free poll SKB Size */
1638 +       } bits;
1639 +} DMA_SKB_SIZE_T;
1640 +
1641 +/*
1642 + * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
1643 + */
1644 +typedef union {
1645 +       unsigned int bits32;
1646 +       struct bit_000c {
1647 +               unsigned int rptr       : 16;   /* Read Ptr, RO */
1648 +               unsigned int wptr       : 16;   /* Write Ptr, RW */
1649 +       } bits;
1650 +} DMA_RWPTR_T;
1651 +
1652 +/*
1653 + * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
1654 + * see DMA_RWPTR_T structure
1655 + */
1656 +
1657 +/*
1658 + * Interrupt Status Register 0         (offset 0x0020)
1659 + * Interrupt Mask Register 0   (offset 0x0024)
1660 + * Interrupt Select Register 0         (offset 0x0028)
1661 + */
1662 +typedef union {
1663 +       unsigned int bits32;
1664 +       struct bit_0020 {
1665 +               /* GMAC0 SW Tx Queue 0 EOF Interrupt */
1666 +               unsigned int swtq00_eof : 1;
1667 +               unsigned int swtq01_eof : 1;
1668 +               unsigned int swtq02_eof : 1;
1669 +               unsigned int swtq03_eof : 1;
1670 +               unsigned int swtq04_eof : 1;
1671 +               unsigned int swtq05_eof : 1;
1672 +               /* GMAC1 SW Tx Queue 0 EOF Interrupt */
1673 +               unsigned int swtq10_eof : 1;
1674 +               unsigned int swtq11_eof : 1;
1675 +               unsigned int swtq12_eof : 1;
1676 +               unsigned int swtq13_eof : 1;
1677 +               unsigned int swtq14_eof : 1;
1678 +               unsigned int swtq15_eof : 1;
1679 +               /* GMAC0 SW Tx Queue 0 Finish Interrupt */
1680 +               unsigned int swtq00_fin : 1;
1681 +               unsigned int swtq01_fin : 1;
1682 +               unsigned int swtq02_fin : 1;
1683 +               unsigned int swtq03_fin : 1;
1684 +               unsigned int swtq04_fin : 1;
1685 +               unsigned int swtq05_fin : 1;
1686 +               /* GMAC1 SW Tx Queue 0 Finish Interrupt */
1687 +               unsigned int swtq10_fin : 1;
1688 +               unsigned int swtq11_fin : 1;
1689 +               unsigned int swtq12_fin : 1;
1690 +               unsigned int swtq13_fin : 1;
1691 +               unsigned int swtq14_fin : 1;
1692 +               unsigned int swtq15_fin : 1;
1693 +               /* GMAC0 Rx Descriptor Protocol Error */
1694 +               unsigned int rxPerr0    : 1;
1695 +               /* GMAC0 AHB Bus Error while Rx */
1696 +               unsigned int rxDerr0    : 1;
1697 +               /* GMAC1 Rx Descriptor Protocol Error */
1698 +               unsigned int rxPerr1    : 1;
1699 +               /* GMAC1 AHB Bus Error while Rx */
1700 +               unsigned int rxDerr1    : 1;
1701 +               /* GMAC0 Tx Descriptor Protocol Error */
1702 +               unsigned int txPerr0    : 1;
1703 +               /* GMAC0 AHB Bus Error while Tx */
1704 +               unsigned int txDerr0    : 1;
1705 +               /* GMAC1 Tx Descriptor Protocol Error */
1706 +               unsigned int txPerr1    : 1;
1707 +               /* GMAC1 AHB Bus Error while Tx */
1708 +               unsigned int txDerr1    : 1;
1709 +       } bits;
1710 +} INTR_REG0_T;
1711 +
1712 +#define GMAC1_TXDERR_INT_BIT           BIT(31)
1713 +#define GMAC1_TXPERR_INT_BIT           BIT(30)
1714 +#define GMAC0_TXDERR_INT_BIT           BIT(29)
1715 +#define GMAC0_TXPERR_INT_BIT           BIT(28)
1716 +#define GMAC1_RXDERR_INT_BIT           BIT(27)
1717 +#define GMAC1_RXPERR_INT_BIT           BIT(26)
1718 +#define GMAC0_RXDERR_INT_BIT           BIT(25)
1719 +#define GMAC0_RXPERR_INT_BIT           BIT(24)
1720 +#define GMAC1_SWTQ15_FIN_INT_BIT       BIT(23)
1721 +#define GMAC1_SWTQ14_FIN_INT_BIT       BIT(22)
1722 +#define GMAC1_SWTQ13_FIN_INT_BIT       BIT(21)
1723 +#define GMAC1_SWTQ12_FIN_INT_BIT       BIT(20)
1724 +#define GMAC1_SWTQ11_FIN_INT_BIT       BIT(19)
1725 +#define GMAC1_SWTQ10_FIN_INT_BIT       BIT(18)
1726 +#define GMAC0_SWTQ05_FIN_INT_BIT       BIT(17)
1727 +#define GMAC0_SWTQ04_FIN_INT_BIT       BIT(16)
1728 +#define GMAC0_SWTQ03_FIN_INT_BIT       BIT(15)
1729 +#define GMAC0_SWTQ02_FIN_INT_BIT       BIT(14)
1730 +#define GMAC0_SWTQ01_FIN_INT_BIT       BIT(13)
1731 +#define GMAC0_SWTQ00_FIN_INT_BIT       BIT(12)
1732 +#define GMAC1_SWTQ15_EOF_INT_BIT       BIT(11)
1733 +#define GMAC1_SWTQ14_EOF_INT_BIT       BIT(10)
1734 +#define GMAC1_SWTQ13_EOF_INT_BIT       BIT(9)
1735 +#define GMAC1_SWTQ12_EOF_INT_BIT       BIT(8)
1736 +#define GMAC1_SWTQ11_EOF_INT_BIT       BIT(7)
1737 +#define GMAC1_SWTQ10_EOF_INT_BIT       BIT(6)
1738 +#define GMAC0_SWTQ05_EOF_INT_BIT       BIT(5)
1739 +#define GMAC0_SWTQ04_EOF_INT_BIT       BIT(4)
1740 +#define GMAC0_SWTQ03_EOF_INT_BIT       BIT(3)
1741 +#define GMAC0_SWTQ02_EOF_INT_BIT       BIT(2)
1742 +#define GMAC0_SWTQ01_EOF_INT_BIT       BIT(1)
1743 +#define GMAC0_SWTQ00_EOF_INT_BIT       BIT(0)
1744 +
1745 +/*
1746 + * Interrupt Status Register 1         (offset 0x0030)
1747 + * Interrupt Mask Register 1   (offset 0x0034)
1748 + * Interrupt Select Register 1         (offset 0x0038)
1749 + */
1750 +typedef union {
1751 +       unsigned int bits32;
1752 +       struct bit_0030 {
1753 +               unsigned int default_q0_eof     : 1;    /* Default Queue 0 EOF Interrupt */
1754 +               unsigned int default_q1_eof     : 1;    /* Default Queue 1 EOF Interrupt */
1755 +               unsigned int class_rx           : 14;   /* Classification Queue Rx Interrupt */
1756 +               unsigned int hwtq00_eof         : 1;    /* GMAC0 HW Tx Queue0 EOF Interrupt */
1757 +               unsigned int hwtq01_eof         : 1;    /* GMAC0 HW Tx Queue1 EOF Interrupt */
1758 +               unsigned int hwtq02_eof         : 1;    /* GMAC0 HW Tx Queue2 EOF Interrupt */
1759 +               unsigned int hwtq03_eof         : 1;    /* GMAC0 HW Tx Queue3 EOF Interrupt */
1760 +               unsigned int hwtq10_eof         : 1;    /* GMAC1 HW Tx Queue0 EOF Interrupt */
1761 +               unsigned int hwtq11_eof         : 1;    /* GMAC1 HW Tx Queue1 EOF Interrupt */
1762 +               unsigned int hwtq12_eof         : 1;    /* GMAC1 HW Tx Queue2 EOF Interrupt */
1763 +               unsigned int hwtq13_eof         : 1;    /* GMAC1 HW Tx Queue3 EOF Interrupt */
1764 +               unsigned int toe_iq0_intr       : 1;    /* TOE Interrupt Queue 0 with Interrupts */
1765 +               unsigned int toe_iq1_intr       : 1;    /* TOE Interrupt Queue 1 with Interrupts */
1766 +               unsigned int toe_iq2_intr       : 1;    /* TOE Interrupt Queue 2 with Interrupts */
1767 +               unsigned int toe_iq3_intr       : 1;    /* TOE Interrupt Queue 3 with Interrupts */
1768 +               unsigned int toe_iq0_full       : 1;    /* TOE Interrupt Queue 0 Full Interrupt */
1769 +               unsigned int toe_iq1_full       : 1;    /* TOE Interrupt Queue 1 Full Interrupt */
1770 +               unsigned int toe_iq2_full       : 1;    /* TOE Interrupt Queue 2 Full Interrupt */
1771 +               unsigned int toe_iq3_full       : 1;    /* TOE Interrupt Queue 3 Full Interrupt */
1772 +       } bits;
1773 +} INTR_REG1_T;
1774 +
1775 +#define TOE_IQ3_FULL_INT_BIT           BIT(31)
1776 +#define TOE_IQ2_FULL_INT_BIT           BIT(30)
1777 +#define TOE_IQ1_FULL_INT_BIT           BIT(29)
1778 +#define TOE_IQ0_FULL_INT_BIT           BIT(28)
1779 +#define TOE_IQ3_INT_BIT                        BIT(27)
1780 +#define TOE_IQ2_INT_BIT                        BIT(26)
1781 +#define TOE_IQ1_INT_BIT                        BIT(25)
1782 +#define TOE_IQ0_INT_BIT                        BIT(24)
1783 +#define GMAC1_HWTQ13_EOF_INT_BIT       BIT(23)
1784 +#define GMAC1_HWTQ12_EOF_INT_BIT       BIT(22)
1785 +#define GMAC1_HWTQ11_EOF_INT_BIT       BIT(21)
1786 +#define GMAC1_HWTQ10_EOF_INT_BIT       BIT(20)
1787 +#define GMAC0_HWTQ03_EOF_INT_BIT       BIT(19)
1788 +#define GMAC0_HWTQ02_EOF_INT_BIT       BIT(18)
1789 +#define GMAC0_HWTQ01_EOF_INT_BIT       BIT(17)
1790 +#define GMAC0_HWTQ00_EOF_INT_BIT       BIT(16)
1791 +#define CLASS_RX_INT_BIT(x)            BIT((x + 2))
1792 +#define DEFAULT_Q1_INT_BIT             BIT(1)
1793 +#define DEFAULT_Q0_INT_BIT             BIT(0)
1794 +
1795 +#define TOE_IQ_INT_BITS                (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
1796 +                                TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
1797 +#define        TOE_IQ_FULL_BITS        (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
1798 +                                TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
1799 +#define        TOE_IQ_ALL_BITS         (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
1800 +#define TOE_CLASS_RX_INT_BITS  0xfffc
1801 +
1802 +/*
1803 + * Interrupt Status Register 2         (offset 0x0040)
1804 + * Interrupt Mask Register 2   (offset 0x0044)
1805 + * Interrupt Select Register 2         (offset 0x0048)
1806 + */
1807 +typedef union {
1808 +       unsigned int bits32;
1809 +       struct bit_0040 {
1810 +               unsigned int toe_q0_full        : 1;    // bit 0        TOE Queue 0 Full Interrupt
1811 +               unsigned int toe_q1_full        : 1;    // bit 1        TOE Queue 1 Full Interrupt
1812 +               unsigned int toe_q2_full        : 1;    // bit 2        TOE Queue 2 Full Interrupt
1813 +               unsigned int toe_q3_full        : 1;    // bit 3        TOE Queue 3 Full Interrupt
1814 +               unsigned int toe_q4_full        : 1;    // bit 4        TOE Queue 4 Full Interrupt
1815 +               unsigned int toe_q5_full        : 1;    // bit 5        TOE Queue 5 Full Interrupt
1816 +               unsigned int toe_q6_full        : 1;    // bit 6        TOE Queue 6 Full Interrupt
1817 +               unsigned int toe_q7_full        : 1;    // bit 7        TOE Queue 7 Full Interrupt
1818 +               unsigned int toe_q8_full        : 1;    // bit 8        TOE Queue 8 Full Interrupt
1819 +               unsigned int toe_q9_full        : 1;    // bit 9        TOE Queue 9 Full Interrupt
1820 +               unsigned int toe_q10_full       : 1;    // bit 10       TOE Queue 10 Full Interrupt
1821 +               unsigned int toe_q11_full       : 1;    // bit 11       TOE Queue 11 Full Interrupt
1822 +               unsigned int toe_q12_full       : 1;    // bit 12       TOE Queue 12 Full Interrupt
1823 +               unsigned int toe_q13_full       : 1;    // bit 13       TOE Queue 13 Full Interrupt
1824 +               unsigned int toe_q14_full       : 1;    // bit 14       TOE Queue 14 Full Interrupt
1825 +               unsigned int toe_q15_full       : 1;    // bit 15       TOE Queue 15 Full Interrupt
1826 +               unsigned int toe_q16_full       : 1;    // bit 16       TOE Queue 16 Full Interrupt
1827 +               unsigned int toe_q17_full       : 1;    // bit 17       TOE Queue 17 Full Interrupt
1828 +               unsigned int toe_q18_full       : 1;    // bit 18       TOE Queue 18 Full Interrupt
1829 +               unsigned int toe_q19_full       : 1;    // bit 19       TOE Queue 19 Full Interrupt
1830 +               unsigned int toe_q20_full       : 1;    // bit 20       TOE Queue 20 Full Interrupt
1831 +               unsigned int toe_q21_full       : 1;    // bit 21       TOE Queue 21 Full Interrupt
1832 +               unsigned int toe_q22_full       : 1;    // bit 22       TOE Queue 22 Full Interrupt
1833 +               unsigned int toe_q23_full       : 1;    // bit 23       TOE Queue 23 Full Interrupt
1834 +               unsigned int toe_q24_full       : 1;    // bit 24       TOE Queue 24 Full Interrupt
1835 +               unsigned int toe_q25_full       : 1;    // bit 25       TOE Queue 25 Full Interrupt
1836 +               unsigned int toe_q26_full       : 1;    // bit 26       TOE Queue 26 Full Interrupt
1837 +               unsigned int toe_q27_full       : 1;    // bit 27       TOE Queue 27 Full Interrupt
1838 +               unsigned int toe_q28_full       : 1;    // bit 28       TOE Queue 28 Full Interrupt
1839 +               unsigned int toe_q29_full       : 1;    // bit 29       TOE Queue 29 Full Interrupt
1840 +               unsigned int toe_q30_full       : 1;    // bit 30       TOE Queue 30 Full Interrupt
1841 +               unsigned int toe_q31_full       : 1;    // bit 31       TOE Queue 31 Full Interrupt
1842 +       } bits;
1843 +} INTR_REG2_T;
1844 +
1845 +#define TOE_QL_FULL_INT_BIT(x)         BIT(x)
1846 +
1847 +/*
1848 + * Interrupt Status Register 3         (offset 0x0050)
1849 + * Interrupt Mask Register 3   (offset 0x0054)
1850 + * Interrupt Select Register 3         (offset 0x0058)
1851 + */
1852 +typedef union {
1853 +       unsigned int bits32;
1854 +       struct bit_0050 {
1855 +               unsigned int toe_q32_full       : 1;    // bit 32       TOE Queue 32 Full Interrupt
1856 +               unsigned int toe_q33_full       : 1;    // bit 33       TOE Queue 33 Full Interrupt
1857 +               unsigned int toe_q34_full       : 1;    // bit 34       TOE Queue 34 Full Interrupt
1858 +               unsigned int toe_q35_full       : 1;    // bit 35       TOE Queue 35 Full Interrupt
1859 +               unsigned int toe_q36_full       : 1;    // bit 36       TOE Queue 36 Full Interrupt
1860 +               unsigned int toe_q37_full       : 1;    // bit 37       TOE Queue 37 Full Interrupt
1861 +               unsigned int toe_q38_full       : 1;    // bit 38       TOE Queue 38 Full Interrupt
1862 +               unsigned int toe_q39_full       : 1;    // bit 39       TOE Queue 39 Full Interrupt
1863 +               unsigned int toe_q40_full       : 1;    // bit 40       TOE Queue 40 Full Interrupt
1864 +               unsigned int toe_q41_full       : 1;    // bit 41       TOE Queue 41 Full Interrupt
1865 +               unsigned int toe_q42_full       : 1;    // bit 42       TOE Queue 42 Full Interrupt
1866 +               unsigned int toe_q43_full       : 1;    // bit 43       TOE Queue 43 Full Interrupt
1867 +               unsigned int toe_q44_full       : 1;    // bit 44       TOE Queue 44 Full Interrupt
1868 +               unsigned int toe_q45_full       : 1;    // bit 45       TOE Queue 45 Full Interrupt
1869 +               unsigned int toe_q46_full       : 1;    // bit 46       TOE Queue 46 Full Interrupt
1870 +               unsigned int toe_q47_full       : 1;    // bit 47       TOE Queue 47 Full Interrupt
1871 +               unsigned int toe_q48_full       : 1;    // bit 48       TOE Queue 48 Full Interrupt
1872 +               unsigned int toe_q49_full       : 1;    // bit 49       TOE Queue 49 Full Interrupt
1873 +               unsigned int toe_q50_full       : 1;    // bit 50       TOE Queue 50 Full Interrupt
1874 +               unsigned int toe_q51_full       : 1;    // bit 51       TOE Queue 51 Full Interrupt
1875 +               unsigned int toe_q52_full       : 1;    // bit 52       TOE Queue 52 Full Interrupt
1876 +               unsigned int toe_q53_full       : 1;    // bit 53       TOE Queue 53 Full Interrupt
1877 +               unsigned int toe_q54_full       : 1;    // bit 54       TOE Queue 54 Full Interrupt
1878 +               unsigned int toe_q55_full       : 1;    // bit 55       TOE Queue 55 Full Interrupt
1879 +               unsigned int toe_q56_full       : 1;    // bit 56       TOE Queue 56 Full Interrupt
1880 +               unsigned int toe_q57_full       : 1;    // bit 57       TOE Queue 57 Full Interrupt
1881 +               unsigned int toe_q58_full       : 1;    // bit 58       TOE Queue 58 Full Interrupt
1882 +               unsigned int toe_q59_full       : 1;    // bit 59       TOE Queue 59 Full Interrupt
1883 +               unsigned int toe_q60_full       : 1;    // bit 60       TOE Queue 60 Full Interrupt
1884 +               unsigned int toe_q61_full       : 1;    // bit 61       TOE Queue 61 Full Interrupt
1885 +               unsigned int toe_q62_full       : 1;    // bit 62       TOE Queue 62 Full Interrupt
1886 +               unsigned int toe_q63_full       : 1;    // bit 63       TOE Queue 63 Full Interrupt
1887 +       } bits;
1888 +} INTR_REG3_T;
1889 +
1890 +#define TOE_QH_FULL_INT_BIT(x)         BIT(x-32)
1891 +
1892 +/*
1893 + * Interrupt Status Register 4         (offset 0x0060)
1894 + * Interrupt Mask Register 4   (offset 0x0064)
1895 + * Interrupt Select Register 4         (offset 0x0068)
1896 + */
1897 +typedef union {
1898 +       unsigned char byte;
1899 +       struct bit_0060 {
1900 +               unsigned char status_changed    : 1;    // Status Changed Intr for RGMII Mode
1901 +               unsigned char rx_overrun        : 1;   // GMAC Rx FIFO overrun interrupt
1902 +               unsigned char tx_pause_off      : 1;    // received pause off frame interrupt
1903 +               unsigned char rx_pause_off      : 1;    // received pause off frame interrupt
1904 +               unsigned char tx_pause_on       : 1;    // transmit pause on frame interrupt
1905 +               unsigned char rx_pause_on       : 1;    // received pause on frame interrupt
1906 +               unsigned char cnt_full          : 1;    // MIB counters half full interrupt
1907 +               unsigned char reserved          : 1;    //
1908 +       } _PACKED_ bits;
1909 +} _PACKED_ GMAC_INTR_T;
1910 +
1911 +typedef union {
1912 +       unsigned int bits32;
1913 +       struct bit_0060_2 {
1914 +               unsigned int    swfq_empty      : 1;    // bit 0        Software Free Queue Empty Intr.
1915 +               unsigned int    hwfq_empty      : 1;    // bit 1        Hardware Free Queue Empty Intr.
1916 +               unsigned int    class_qf_int    : 14;   // bit 15:2 Classification Rx Queue13-0 Full Intr.
1917 +               GMAC_INTR_T     gmac0;
1918 +               GMAC_INTR_T     gmac1;
1919 +       } bits;
1920 +} INTR_REG4_T;
1921 +
1922 +#define GMAC1_RESERVED_INT_BIT         BIT(31)
1923 +#define GMAC1_MIB_INT_BIT              BIT(30)
1924 +#define GMAC1_RX_PAUSE_ON_INT_BIT      BIT(29)
1925 +#define GMAC1_TX_PAUSE_ON_INT_BIT      BIT(28)
1926 +#define GMAC1_RX_PAUSE_OFF_INT_BIT     BIT(27)
1927 +#define GMAC1_TX_PAUSE_OFF_INT_BIT     BIT(26)
1928 +#define GMAC1_RX_OVERRUN_INT_BIT       BIT(25)
1929 +#define GMAC1_STATUS_CHANGE_INT_BIT    BIT(24)
1930 +#define GMAC0_RESERVED_INT_BIT         BIT(23)
1931 +#define GMAC0_MIB_INT_BIT              BIT(22)
1932 +#define GMAC0_RX_PAUSE_ON_INT_BIT      BIT(21)
1933 +#define GMAC0_TX_PAUSE_ON_INT_BIT      BIT(20)
1934 +#define GMAC0_RX_PAUSE_OFF_INT_BIT     BIT(19)
1935 +#define GMAC0_TX_PAUSE_OFF_INT_BIT     BIT(18)
1936 +#define GMAC0_RX_OVERRUN_INT_BIT       BIT(17)
1937 +#define GMAC0_STATUS_CHANGE_INT_BIT    BIT(16)
1938 +#define CLASS_RX_FULL_INT_BIT(x)       BIT((x+2))
1939 +#define HWFQ_EMPTY_INT_BIT             BIT(1)
1940 +#define SWFQ_EMPTY_INT_BIT             BIT(0)
1941 +
1942 +#if 1
1943 +#define GMAC0_INT_BITS         (GMAC0_MIB_INT_BIT)
1944 +#define GMAC1_INT_BITS         (GMAC1_MIB_INT_BIT)
1945 +#else
1946 +#define GMAC0_INT_BITS         (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
1947 +                                GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT |        \
1948 +                                GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT |      \
1949 +                                GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
1950 +#define GMAC1_INT_BITS         (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
1951 +                                GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT |        \
1952 +                                GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT |      \
1953 +                                GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
1954 +#endif
1955 +
1956 +#define CLASS_RX_FULL_INT_BITS         0xfffc
1957 +
1958 +/*
1959 + * GLOBAL_QUEUE_THRESHOLD_REG  (offset 0x0070)
1960 + */
1961 +typedef union {
1962 +       unsigned int bits32;
1963 +       struct bit_0070_2 {
1964 +               unsigned int    swfq_empty      : 8;    //  7:0         Software Free Queue Empty Threshold
1965 +               unsigned int    hwfq_empty      : 8;    // 15:8         Hardware Free Queue Empty Threshold
1966 +               unsigned int    intrq           : 8;    // 23:16
1967 +               unsigned int    toe_class       : 8;    // 31:24
1968 +       } bits;
1969 +} QUEUE_THRESHOLD_T;
1970 +
1971 +
1972 +/*
1973 + * GMAC DMA Control Register
1974 + * GMAC0 offset 0x8000
1975 + * GMAC1 offset 0xC000
1976 + */
1977 +typedef union {
1978 +       unsigned int bits32;
1979 +       struct bit_8000 {
1980 +               unsigned int    td_bus          : 2;    // bit 1:0      Peripheral Bus Width
1981 +               unsigned int    td_burst_size   : 2;    // bit 3:2      TxDMA max burst size for every AHB request
1982 +               unsigned int    td_prot         : 4;    // bit 7:4      TxDMA protection control
1983 +               unsigned int    rd_bus          : 2;    // bit 9:8      Peripheral Bus Width
1984 +               unsigned int    rd_burst_size   : 2;    // bit 11:10    DMA max burst size for every AHB request
1985 +               unsigned int    rd_prot         : 4;    // bit 15:12    DMA Protection Control
1986 +               unsigned int    rd_insert_bytes : 2;    // bit 17:16
1987 +               unsigned int    reserved        : 10;   // bit 27:18
1988 +               unsigned int    drop_small_ack  : 1;    // bit 28       1: Drop, 0: Accept
1989 +               unsigned int    loopback        : 1;    // bit 29       Loopback TxDMA to RxDMA
1990 +               unsigned int    td_enable       : 1;    // bit 30       Tx DMA Enable
1991 +               unsigned int    rd_enable       : 1;    // bit 31       Rx DMA Enable
1992 +       } bits;
1993 +} GMAC_DMA_CTRL_T;
1994 +
1995 +/*
1996 + * GMAC Tx Weighting Control Register 0
1997 + * GMAC0 offset 0x8004
1998 + * GMAC1 offset 0xC004
1999 + */
2000 +typedef union {
2001 +       unsigned int bits32;
2002 +       struct bit_8004 {
2003 +               unsigned int    hw_tq0          : 6;    // bit 5:0      HW TX Queue 3
2004 +               unsigned int    hw_tq1          : 6;    // bit 11:6     HW TX Queue 2
2005 +               unsigned int    hw_tq2          : 6;    // bit 17:12    HW TX Queue 1
2006 +               unsigned int    hw_tq3          : 6;    // bit 23:18    HW TX Queue 0
2007 +               unsigned int    reserved        : 8;    // bit 31:24
2008 +       } bits;
2009 +} GMAC_TX_WCR0_T;      /* Weighting Control Register 0 */
2010 +
2011 +/*
2012 + * GMAC Tx Weighting Control Register 1
2013 + * GMAC0 offset 0x8008
2014 + * GMAC1 offset 0xC008
2015 + */
2016 +typedef union {
2017 +       unsigned int bits32;
2018 +       struct bit_8008 {
2019 +               unsigned int    sw_tq0          : 5;    // bit 4:0      SW TX Queue 0
2020 +               unsigned int    sw_tq1          : 5;    // bit 9:5      SW TX Queue 1
2021 +               unsigned int    sw_tq2          : 5;    // bit 14:10    SW TX Queue 2
2022 +               unsigned int    sw_tq3          : 5;    // bit 19:15    SW TX Queue 3
2023 +               unsigned int    sw_tq4          : 5;    // bit 24:20    SW TX Queue 4
2024 +               unsigned int    sw_tq5          : 5;    // bit 29:25    SW TX Queue 5
2025 +               unsigned int    reserved        : 2;    // bit 31:30
2026 +       } bits;
2027 +} GMAC_TX_WCR1_T;      /* Weighting Control Register 1 */
2028 +
2029 +/*
2030 + * Queue Read/Write Pointer
2031 + * GMAC SW TX Queue 0~5 Read/Write Pointer register
2032 + * GMAC0 offset 0x800C ~ 0x8020
2033 + * GMAC1 offset 0xC00C ~ 0xC020
2034 + * GMAC HW TX Queue 0~3 Read/Write Pointer register
2035 + * GMAC0 offset 0x8024 ~ 0x8030
2036 + * GMAC1 offset 0xC024 ~ 0xC030
2037 + *
2038 + * see DMA_RWPTR_T structure
2039 + */
2040 +
2041 +/*
2042 + * GMAC DMA Tx First Description Address Register
2043 + * GMAC0 offset 0x8038
2044 + * GMAC1 offset 0xC038
2045 + */
2046 +typedef union {
2047 +       unsigned int bits32;
2048 +       struct bit_8038 {
2049 +               unsigned int reserved           :  3;
2050 +               unsigned int td_busy            :  1;   // bit 3        1: TxDMA busy; 0: TxDMA idle
2051 +               unsigned int td_first_des_ptr   : 28;   // bit 31:4     first descriptor address
2052 +       } bits;
2053 +} GMAC_TXDMA_FIRST_DESC_T;
2054 +
2055 +/*
2056 + * GMAC DMA Tx Current Description Address Register
2057 + * GMAC0 offset 0x803C
2058 + * GMAC1 offset 0xC03C
2059 + */
2060 +typedef union {
2061 +       unsigned int bits32;
2062 +       struct bit_803C {
2063 +               unsigned int reserved           :  4;
2064 +               unsigned int td_curr_desc_ptr   : 28;   // bit 31:4     current descriptor address
2065 +       } bits;
2066 +} GMAC_TXDMA_CURR_DESC_T;
2067 +
2068 +/*
2069 + * GMAC DMA Tx Description Word 0 Register
2070 + * GMAC0 offset 0x8040
2071 + * GMAC1 offset 0xC040
2072 + */
2073 +typedef union {
2074 +       unsigned int bits32;
2075 +       struct bit_8040 {
2076 +               unsigned int buffer_size        : 16;   // bit 15:0     Transfer size
2077 +               unsigned int desc_count         : 6;    // bit 21:16    number of descriptors used for the current frame
2078 +               unsigned int status_tx_ok       : 1;    // bit 22       Tx Status, 1: Successful 0: Failed
2079 +               unsigned int status_rvd         : 6;    // bit 28:23    Tx Status, Reserved bits
2080 +               unsigned int perr               : 1;    // bit 29       protocol error during processing this descriptor
2081 +               unsigned int derr               : 1;    // bit 30       data error during processing this descriptor
2082 +               unsigned int reserved           : 1;    // bit 31
2083 +       } bits;
2084 +} GMAC_TXDESC_0_T;
2085 +
2086 +/*
2087 + * GMAC DMA Tx Description Word 1 Register
2088 + * GMAC0 offset 0x8044
2089 + * GMAC1 offset 0xC044
2090 + */
2091 +typedef union {
2092 +       unsigned int bits32;
2093 +       struct txdesc_word1 {
2094 +               unsigned int    byte_count      : 16;   // bit 15: 0    Tx Frame Byte Count
2095 +               unsigned int    mtu_enable      : 1;    // bit 16       TSS segmentation use MTU setting
2096 +               unsigned int    ip_chksum       : 1;    // bit 17       IPV4 Header Checksum Enable
2097 +               unsigned int    ipv6_enable     : 1;    // bit 18       IPV6 Tx Enable
2098 +               unsigned int    tcp_chksum      : 1;    // bit 19       TCP Checksum Enable
2099 +               unsigned int    udp_chksum      : 1;    // bit 20       UDP Checksum Enable
2100 +               unsigned int    bypass_tss      : 1;    // bit 21
2101 +               unsigned int    ip_fixed_len    : 1;    // bit 22
2102 +               unsigned int    reserved        : 9;    // bit 31:23    Tx Flag, Reserved
2103 +       } bits;
2104 +} GMAC_TXDESC_1_T;
2105 +
2106 +#define TSS_IP_FIXED_LEN_BIT   BIT(22)
2107 +#define TSS_UDP_CHKSUM_BIT     BIT(20)
2108 +#define TSS_TCP_CHKSUM_BIT     BIT(19)
2109 +#define TSS_IPV6_ENABLE_BIT    BIT(18)
2110 +#define TSS_IP_CHKSUM_BIT      BIT(17)
2111 +#define TSS_MTU_ENABLE_BIT     BIT(16)
2112 +
2113 +/*
2114 + * GMAC DMA Tx Description Word 2 Register
2115 + * GMAC0 offset 0x8048
2116 + * GMAC1 offset 0xC048
2117 + */
2118 +typedef union {
2119 +       unsigned int    bits32;
2120 +       unsigned int    buf_adr;
2121 +} GMAC_TXDESC_2_T;
2122 +
2123 +/*
2124 + * GMAC DMA Tx Description Word 3 Register
2125 + * GMAC0 offset 0x804C
2126 + * GMAC1 offset 0xC04C
2127 + */
2128 +typedef union {
2129 +       unsigned int bits32;
2130 +       struct txdesc_word3 {
2131 +               unsigned int    mtu_size        : 11;   // bit 10: 0    Tx Frame Byte Count
2132 +               unsigned int    reserved        : 18;   // bit 28:11
2133 +               unsigned int    eofie           : 1;    // bit 29       End of frame interrupt enable
2134 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
2135 +       } bits;
2136 +} GMAC_TXDESC_3_T;
2137 +#define SOF_EOF_BIT_MASK       0x3fffffff
2138 +#define SOF_BIT                        0x80000000
2139 +#define EOF_BIT                        0x40000000
2140 +#define EOFIE_BIT              BIT(29)
2141 +#define MTU_SIZE_BIT_MASK      0x7ff
2142 +
2143 +/*
2144 + * GMAC Tx Descriptor
2145 + */
2146 +typedef struct {
2147 +       GMAC_TXDESC_0_T word0;
2148 +       GMAC_TXDESC_1_T word1;
2149 +       GMAC_TXDESC_2_T word2;
2150 +       GMAC_TXDESC_3_T word3;
2151 +} GMAC_TXDESC_T;
2152 +
2153 +/*
2154 + * GMAC DMA Rx First Description Address Register
2155 + * GMAC0 offset 0x8058
2156 + * GMAC1 offset 0xC058
2157 + */
2158 +typedef union {
2159 +       unsigned int bits32;
2160 +       struct bit_8058 {
2161 +               unsigned int reserved           :  3;   // bit 2:0
2162 +               unsigned int rd_busy            :  1;   // bit 3        1-RxDMA busy; 0-RxDMA idle
2163 +               unsigned int rd_first_des_ptr   : 28;   // bit 31:4 first descriptor address
2164 +       } bits;
2165 +} GMAC_RXDMA_FIRST_DESC_T;
2166 +
2167 +/*
2168 + * GMAC DMA Rx Current Description Address Register
2169 + * GMAC0 offset 0x805C
2170 + * GMAC1 offset 0xC05C
2171 + */
2172 +typedef union {
2173 +       unsigned int bits32;
2174 +       struct bit_805C {
2175 +               unsigned int reserved           :  4;   // bit 3:0
2176 +               unsigned int rd_curr_des_ptr    : 28;   // bit 31:4 current descriptor address
2177 +       } bits;
2178 +} GMAC_RXDMA_CURR_DESC_T;
2179 +
2180 +/*
2181 + * GMAC DMA Rx Description Word 0 Register
2182 + * GMAC0 offset 0x8060
2183 + * GMAC1 offset 0xC060
2184 + */
2185 +typedef union {
2186 +       unsigned int bits32;
2187 +       struct bit_8060 {
2188 +               unsigned int buffer_size        : 16;   // bit 15:0  number of descriptors used for the current frame
2189 +               unsigned int desc_count         : 6;    // bit 21:16 number of descriptors used for the current frame
2190 +               unsigned int status             : 4;    // bit 24:22 Status of rx frame
2191 +               unsigned int chksum_status      : 3;    // bit 28:26 Check Sum Status
2192 +               unsigned int perr               : 1;    // bit 29        protocol error during processing this descriptor
2193 +               unsigned int derr               : 1;    // bit 30        data error during processing this descriptor
2194 +               unsigned int drop               : 1;    // bit 31        TOE/CIS Queue Full dropped packet to default queue
2195 +       } bits;
2196 +} GMAC_RXDESC_0_T;
2197 +
2198 +#define                GMAC_RXDESC_0_T_derr                    BIT(30)
2199 +#define                GMAC_RXDESC_0_T_perr                    BIT(29)
2200 +#define                GMAC_RXDESC_0_T_chksum_status(x)        BIT((x+26))
2201 +#define                GMAC_RXDESC_0_T_status(x)               BIT((x+22))
2202 +#define                GMAC_RXDESC_0_T_desc_count(x)           BIT((x+16))
2203 +
2204 +#define        RX_CHKSUM_IP_UDP_TCP_OK                 0
2205 +#define        RX_CHKSUM_IP_OK_ONLY                    1
2206 +#define        RX_CHKSUM_NONE                          2
2207 +#define        RX_CHKSUM_IP_ERR_UNKNOWN                4
2208 +#define        RX_CHKSUM_IP_ERR                        5
2209 +#define        RX_CHKSUM_TCP_UDP_ERR                   6
2210 +#define RX_CHKSUM_NUM                          8
2211 +
2212 +#define RX_STATUS_GOOD_FRAME                   0
2213 +#define RX_STATUS_TOO_LONG_GOOD_CRC            1
2214 +#define RX_STATUS_RUNT_FRAME                   2
2215 +#define RX_STATUS_SFD_NOT_FOUND                        3
2216 +#define RX_STATUS_CRC_ERROR                    4
2217 +#define RX_STATUS_TOO_LONG_BAD_CRC             5
2218 +#define RX_STATUS_ALIGNMENT_ERROR              6
2219 +#define RX_STATUS_TOO_LONG_BAD_ALIGN           7
2220 +#define RX_STATUS_RX_ERR                       8
2221 +#define RX_STATUS_DA_FILTERED                  9
2222 +#define RX_STATUS_BUFFER_FULL                  10
2223 +#define RX_STATUS_NUM                          16
2224 +
2225 +
2226 +/*
2227 + * GMAC DMA Rx Description Word 1 Register
2228 + * GMAC0 offset 0x8064
2229 + * GMAC1 offset 0xC064
2230 + */
2231 +typedef union {
2232 +       unsigned int bits32;
2233 +       struct rxdesc_word1 {
2234 +               unsigned int    byte_count      : 16;   // bit 15: 0    Rx Frame Byte Count
2235 +               unsigned int    sw_id           : 16;   // bit 31:16    Software ID
2236 +       } bits;
2237 +} GMAC_RXDESC_1_T;
2238 +
2239 +/*
2240 + * GMAC DMA Rx Description Word 2 Register
2241 + * GMAC0 offset 0x8068
2242 + * GMAC1 offset 0xC068
2243 + */
2244 +typedef union {
2245 +       unsigned int    bits32;
2246 +       unsigned int    buf_adr;
2247 +} GMAC_RXDESC_2_T;
2248 +
2249 +#define RX_INSERT_NONE         0
2250 +#define RX_INSERT_1_BYTE       1
2251 +#define RX_INSERT_2_BYTE       2
2252 +#define RX_INSERT_3_BYTE       3
2253 +
2254 +#define RX_INSERT_BYTES                RX_INSERT_2_BYTE
2255 +/*
2256 + * GMAC DMA Rx Description Word 3 Register
2257 + * GMAC0 offset 0x806C
2258 + * GMAC1 offset 0xC06C
2259 + */
2260 +typedef union {
2261 +       unsigned int bits32;
2262 +       struct rxdesc_word3 {
2263 +               unsigned int    l3_offset       : 8;    // bit 7: 0     L3 data offset
2264 +               unsigned int    l4_offset       : 8;    // bit 15: 8    L4 data offset
2265 +               unsigned int    l7_offset       : 8;    // bit 23: 16   L7 data offset
2266 +               unsigned int    dup_ack         : 1;    // bit 24       Duplicated ACK detected
2267 +               unsigned int    abnormal        : 1;    // bit 25       abnormal case found
2268 +               unsigned int    option          : 1;    // bit 26       IPV4 option or IPV6 extension header
2269 +               unsigned int    out_of_seq      : 1;    // bit 27       Out of Sequence packet
2270 +               unsigned int    ctrl_flag       : 1;    // bit 28       Control Flag is present
2271 +               unsigned int    eofie           : 1;    // bit 29       End of frame interrupt enable
2272 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
2273 +       } bits;
2274 +} GMAC_RXDESC_3_T;
2275 +
2276 +/*
2277 + * GMAC Rx Descriptor
2278 + */
2279 +typedef struct {
2280 +       GMAC_RXDESC_0_T word0;
2281 +       GMAC_RXDESC_1_T word1;
2282 +       GMAC_RXDESC_2_T word2;
2283 +       GMAC_RXDESC_3_T word3;
2284 +} GMAC_RXDESC_T;
2285 +
2286 +/*
2287 + * GMAC Hash Engine Enable/Action Register 0 Offset Register
2288 + * GMAC0 offset 0x8070
2289 + * GMAC1 offset 0xC070
2290 + */
2291 +typedef union {
2292 +       unsigned int bits32;
2293 +       struct bit_8070 {
2294 +               unsigned int    mr0hel          : 6;    // bit 5:0      match rule 0 hash entry size
2295 +               unsigned int    mr0_action      : 5;    // bit 10:6     Matching Rule 0 action offset
2296 +               unsigned int    reserved0       : 4;    // bit 14:11
2297 +               unsigned int    mr0en           : 1;    // bit 15       Enable Matching Rule 0
2298 +               unsigned int    mr1hel          : 6;    // bit 21:16    match rule 1 hash entry size
2299 +               unsigned int    mr1_action      : 5;    // bit 26:22    Matching Rule 1 action offset
2300 +               unsigned int    timing          : 3;    // bit 29:27
2301 +               unsigned int    reserved1       : 1;    // bit 30
2302 +               unsigned int    mr1en           : 1;    // bit 31       Enable Matching Rule 1
2303 +       } bits;
2304 +} GMAC_HASH_ENABLE_REG0_T;
2305 +
2306 +/*
2307 + * GMAC Hash Engine Enable/Action Register 1 Offset Register
2308 + * GMAC0 offset 0x8074
2309 + * GMAC1 offset 0xC074
2310 + */
2311 +typedef union {
2312 +       unsigned int bits32;
2313 +       struct bit_8074 {
2314 +               unsigned int    mr2hel          : 6;    // bit 5:0      match rule 2 hash entry size
2315 +               unsigned int    mr2_action      : 5;    // bit 10:6     Matching Rule 2 action offset
2316 +               unsigned int    reserved2       : 4;    // bit 14:11
2317 +               unsigned int    mr2en           : 1;    // bit 15       Enable Matching Rule 2
2318 +               unsigned int    mr3hel          : 6;    // bit 21:16    match rule 3 hash entry size
2319 +               unsigned int    mr3_action      : 5;    // bit 26:22    Matching Rule 3 action offset
2320 +               unsigned int    reserved1       : 4;    // bit 30:27
2321 +               unsigned int    mr3en           : 1;    // bit 31       Enable Matching Rule 3
2322 +       } bits;
2323 +} GMAC_HASH_ENABLE_REG1_T;
2324 +
2325 +/*
2326 + * GMAC Matching Rule Control Register 0
2327 + * GMAC0 offset 0x8078
2328 + * GMAC1 offset 0xC078
2329 + */
2330 +typedef union {
2331 +       unsigned int bits32;
2332 +       struct bit_8078 {
2333 +               unsigned int    sprx            : 8;    // bit 7:0      Support Protocol Register 7:0
2334 +               unsigned int    reserved2       : 4;    // bit 11:8
2335 +               unsigned int    tos_traffic     : 1;    // bit 12       IPV4 TOS or IPV6 Traffice Class
2336 +               unsigned int    flow_lable      : 1;    // bit 13       IPV6 Flow label
2337 +               unsigned int    ip_hdr_len      : 1;    // bit 14       IPV4 Header length
2338 +               unsigned int    ip_version      : 1;    // bit 15       0: IPV4, 1: IPV6
2339 +               unsigned int    reserved1       : 3;    // bit 18:16
2340 +               unsigned int    pppoe           : 1;    // bit 19       PPPoE Session ID enable
2341 +               unsigned int    vlan            : 1;    // bit 20       VLAN ID enable
2342 +               unsigned int    ether_type      : 1;    // bit 21       Ethernet type enable
2343 +               unsigned int    sa              : 1;    // bit 22       MAC SA enable
2344 +               unsigned int    da              : 1;    // bit 23       MAC DA enable
2345 +               unsigned int    priority        : 3;    // bit 26:24    priority if multi-rules matched
2346 +               unsigned int    port            : 1;    // bit 27       PORT ID matching enable
2347 +               unsigned int    l7              : 1;    // bit 28       L7 matching enable
2348 +               unsigned int    l4              : 1;    // bit 29       L4 matching enable
2349 +               unsigned int    l3              : 1;    // bit 30       L3 matching enable
2350 +               unsigned int    l2              : 1;    // bit 31       L2 matching enable
2351 +       } bits;
2352 +} GMAC_MRxCR0_T;
2353 +
2354 +#define MR_L2_BIT              BIT(31)
2355 +#define MR_L3_BIT              BIT(30)
2356 +#define MR_L4_BIT              BIT(29)
2357 +#define MR_L7_BIT              BIT(28)
2358 +#define MR_PORT_BIT            BIT(27)
2359 +#define MR_PRIORITY_BIT                BIT(26)
2360 +#define MR_DA_BIT              BIT(23)
2361 +#define MR_SA_BIT              BIT(22)
2362 +#define MR_ETHER_TYPE_BIT      BIT(21)
2363 +#define MR_VLAN_BIT            BIT(20)
2364 +#define MR_PPPOE_BIT           BIT(19)
2365 +#define MR_IP_VER_BIT          BIT(15)
2366 +#define MR_IP_HDR_LEN_BIT      BIT(14)
2367 +#define MR_FLOW_LABLE_BIT      BIT(13)
2368 +#define MR_TOS_TRAFFIC_BIT     BIT(12)
2369 +#define MR_SPR_BIT(x)          BIT(x)
2370 +#define MR_SPR_BITS            0xff
2371 +
2372 +/*
2373 + * GMAC Matching Rule Control Register 1
2374 + * GMAC0 offset 0x807C
2375 + * GMAC1 offset 0xC07C
2376 + */
2377 +typedef union {
2378 +       unsigned int bits32;
2379 +       struct bit_807C {
2380 +               unsigned int    l4_byte0_15     : 16;   // bit 15: 0
2381 +               unsigned int    dip_netmask     : 7;    // bit 22:16    Dest IP net mask, number of mask bits
2382 +               unsigned int    dip             : 1;    // bit 23               Dest IP
2383 +               unsigned int    sip_netmask     : 7;    // bit 30:24    Srce IP net mask, number of mask bits
2384 +               unsigned int    sip             : 1;    // bit 31               Srce IP
2385 +       } bits;
2386 +} GMAC_MRxCR1_T;
2387 +
2388 +/*
2389 + * GMAC Matching Rule Control Register 2
2390 + * GMAC0 offset 0x8080
2391 + * GMAC1 offset 0xC080
2392 + */
2393 +typedef union {
2394 +       unsigned int bits32;
2395 +       struct bit_8080 {
2396 +               unsigned int    l7_byte0_23     : 24;   // bit 23:0
2397 +               unsigned int    l4_byte16_24    : 8;    // bit 31: 24
2398 +       } bits;
2399 +} GMAC_MRxCR2_T;
2400 +
2401 +/*
2402 + * GMAC Support registers
2403 + * GMAC0 offset 0x80A8
2404 + * GMAC1 offset 0xC0A8
2405 + */
2406 +typedef union {
2407 +       unsigned int bits32;
2408 +       struct bit_80A8 {
2409 +               unsigned int    protocol        : 8;    // bit 7:0              Supported protocol
2410 +               unsigned int    swap            : 3;    // bit 10:8             Swap
2411 +               unsigned int    reserved        : 21;   // bit 31:11
2412 +       } bits;
2413 +} GMAC_SPR_T;
2414 +
2415 +/*
2416 + * GMAC_AHB_WEIGHT registers
2417 + * GMAC0 offset 0x80C8
2418 + * GMAC1 offset 0xC0C8
2419 + */
2420 +typedef union {
2421 +       unsigned int bits32;
2422 +       struct bit_80C8 {
2423 +               unsigned int    hash_weight     : 5;    // 4:0
2424 +               unsigned int    rx_weight       : 5;    // 9:5
2425 +               unsigned int    tx_weight       : 5;    // 14:10
2426 +               unsigned int    pre_req         : 5;    // 19:15 Rx Data Pre Request FIFO Threshold
2427 +               unsigned int    tqDV_threshold  : 5;    // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
2428 +               unsigned int    reserved        : 7;    // 31:25
2429 +       } bits;
2430 +} GMAC_AHB_WEIGHT_T;
2431 +
2432 +/*
2433 + * the register structure of GMAC
2434 + */
2435 +
2436 +/*
2437 + * GMAC RX FLTR
2438 + * GMAC0 Offset 0xA00C
2439 + * GMAC1 Offset 0xE00C
2440 + */
2441 +typedef union {
2442 +       unsigned int bits32;
2443 +       struct bit1_000c {
2444 +               unsigned int unicast            :  1;   /* enable receive of unicast frames that are sent to STA address */
2445 +               unsigned int multicast          :  1;   /* enable receive of multicast frames that pass multicast filter */
2446 +               unsigned int broadcast          :  1;   /* enable receive of broadcast frames */
2447 +               unsigned int promiscuous        :  1;   /* enable receive of all frames */
2448 +               unsigned int error              :  1;   /* enable receive of all error frames */
2449 +               unsigned int                    : 27;
2450 +       } bits;
2451 +} GMAC_RX_FLTR_T;
2452 +
2453 +/*
2454 + * GMAC Configuration 0
2455 + * GMAC0 Offset 0xA018
2456 + * GMAC1 Offset 0xE018
2457 + */
2458 +typedef union {
2459 +       unsigned int bits32;
2460 +       struct bit1_0018 {
2461 +               unsigned int dis_tx             :  1;   /* 0: disable transmit */
2462 +               unsigned int dis_rx             :  1;   /* 1: disable receive */
2463 +               unsigned int loop_back          :  1;   /* 2: transmit data loopback enable */
2464 +               unsigned int flow_ctrl          :  1;   /* 3: flow control also trigged by Rx queues */
2465 +               unsigned int adj_ifg            :  4;   /* 4-7: adjust IFG from 96+/-56 */
2466 +               unsigned int max_len            :  3;   /* 8-10 maximum receive frame length allowed */
2467 +               unsigned int dis_bkoff          :  1;   /* 11: disable back-off function */
2468 +               unsigned int dis_col            :  1;   /* 12: disable 16 collisions abort function */
2469 +               unsigned int sim_test           :  1;   /* 13: speed up timers in simulation */
2470 +               unsigned int rx_fc_en           :  1;   /* 14: RX flow control enable */
2471 +               unsigned int tx_fc_en           :  1;   /* 15: TX flow control enable */
2472 +               unsigned int rgmii_en           :  1;   /* 16: RGMII in-band status enable */
2473 +               unsigned int ipv4_rx_chksum     :  1;   /* 17: IPv4 RX Checksum enable */
2474 +               unsigned int ipv6_rx_chksum     :  1;   /* 18: IPv6 RX Checksum enable */
2475 +               unsigned int rx_tag_remove      :  1;   /* 19: Remove Rx VLAN tag */
2476 +               unsigned int rgmm_edge          :  1;   // 20
2477 +               unsigned int rxc_inv            :  1;   // 21
2478 +               unsigned int ipv6_exthdr_order  :  1;   // 22
2479 +               unsigned int rx_err_detect      :  1;   // 23
2480 +               unsigned int port0_chk_hwq      :  1;   // 24
2481 +               unsigned int port1_chk_hwq      :  1;   // 25
2482 +               unsigned int port0_chk_toeq     :  1;   // 26
2483 +               unsigned int port1_chk_toeq     :  1;   // 27
2484 +               unsigned int port0_chk_classq   :  1;   // 28
2485 +               unsigned int port1_chk_classq   :  1;   // 29
2486 +               unsigned int reserved           :  2;   // 31
2487 +       } bits;
2488 +} GMAC_CONFIG0_T;
2489 +
2490 +/*
2491 + * GMAC Configuration 1
2492 + * GMAC0 Offset 0xA01C
2493 + * GMAC1 Offset 0xE01C
2494 + */
2495 +typedef union {
2496 +       unsigned int bits32;
2497 +       struct bit1_001c {
2498 +               unsigned int set_threshold      : 8;    /* flow control set threshold */
2499 +               unsigned int rel_threshold      : 8;    /* flow control release threshold */
2500 +               unsigned int reserved           : 16;
2501 +       } bits;
2502 +} GMAC_CONFIG1_T;
2503 +
2504 +#define GMAC_FLOWCTRL_SET_MAX          32
2505 +#define GMAC_FLOWCTRL_SET_MIN          0
2506 +#define GMAC_FLOWCTRL_RELEASE_MAX      32
2507 +#define GMAC_FLOWCTRL_RELEASE_MIN      0
2508 +
2509 +/*
2510 + * GMAC Configuration 2
2511 + * GMAC0 Offset 0xA020
2512 + * GMAC1 Offset 0xE020
2513 + */
2514 +typedef union {
2515 +       unsigned int bits32;
2516 +       struct bit1_0020 {
2517 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
2518 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
2519 +       } bits;
2520 +} GMAC_CONFIG2_T;
2521 +
2522 +/*
2523 + * GMAC Configuration 3
2524 + * GMAC0 Offset 0xA024
2525 + * GMAC1 Offset 0xE024
2526 + */
2527 +typedef union {
2528 +       unsigned int bits32;
2529 +       struct bit1_0024 {
2530 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
2531 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
2532 +       } bits;
2533 +} GMAC_CONFIG3_T;
2534 +
2535 +
2536 +/*
2537 + * GMAC STATUS
2538 + * GMAC0 Offset 0xA02C
2539 + * GMAC1 Offset 0xE02C
2540 + */
2541 +typedef union {
2542 +       unsigned int bits32;
2543 +       struct bit1_002c {
2544 +               unsigned int link               :  1;   /* link status */
2545 +               unsigned int speed              :  2;   /* link speed(00->2.5M 01->25M 10->125M) */
2546 +               unsigned int duplex             :  1;   /* duplex mode */
2547 +               unsigned int reserved           :  1;
2548 +               unsigned int mii_rmii           :  2;   /* PHY interface type */
2549 +               unsigned int                    : 25;
2550 +       } bits;
2551 +} GMAC_STATUS_T;
2552 +
2553 +#define GMAC_SPEED_10                  0
2554 +#define GMAC_SPEED_100                 1
2555 +#define GMAC_SPEED_1000                        2
2556 +
2557 +#define GMAC_PHY_MII                   0
2558 +#define GMAC_PHY_GMII                  1
2559 +#define GMAC_PHY_RGMII_100_10          2
2560 +#define GMAC_PHY_RGMII_1000            3
2561 +
2562 +/*
2563 + * Queue Header
2564 + *     (1) TOE Queue Header
2565 + *     (2) Non-TOE Queue Header
2566 + *     (3) Interrupt Queue Header
2567 + *
2568 + * memory Layout
2569 + *     TOE Queue Header
2570 + *      0x60003000 +---------------------------+ 0x0000
2571 + *                             |     TOE Queue 0 Header        |
2572 + *                             |         8 * 4 Bytes       |
2573 + *                             +---------------------------+ 0x0020
2574 + *                             |     TOE Queue 1 Header        |
2575 + *                             |         8 * 4 Bytes           |
2576 + *                             +---------------------------+ 0x0040
2577 + *                             |       ......                          |
2578 + *                             |                                               |
2579 + *                             +---------------------------+
2580 + *
2581 + *     Non TOE Queue Header
2582 + *      0x60002000 +---------------------------+ 0x0000
2583 + *                             |   Default Queue 0 Header  |
2584 + *                             |         2 * 4 Bytes           |
2585 + *                             +---------------------------+ 0x0008
2586 + *                             |   Default Queue 1 Header      |
2587 + *                             |         2 * 4 Bytes           |
2588 + *                             +---------------------------+ 0x0010
2589 + *                             |   Classification Queue 0      |
2590 + *                             |         2 * 4 Bytes           |
2591 + *                             +---------------------------+
2592 + *                             |   Classification Queue 1      |
2593 + *                             |         2 * 4 Bytes           |
2594 + *                             +---------------------------+ (n * 8 + 0x10)
2595 + *                             |               ...                             |
2596 + *                             |         2 * 4 Bytes           |
2597 + *                             +---------------------------+ (13 * 8 + 0x10)
2598 + *                             |   Classification Queue 13     |
2599 + *                             |         2 * 4 Bytes           |
2600 + *                             +---------------------------+ 0x80
2601 + *                             |      Interrupt Queue 0        |
2602 + *                             |         2 * 4 Bytes           |
2603 + *                             +---------------------------+
2604 + *                             |      Interrupt Queue 1        |
2605 + *                             |         2 * 4 Bytes           |
2606 + *                             +---------------------------+
2607 + *                             |      Interrupt Queue 2        |
2608 + *                             |         2 * 4 Bytes           |
2609 + *                             +---------------------------+
2610 + *                             |      Interrupt Queue 3        |
2611 + *                             |         2 * 4 Bytes           |
2612 + *                             +---------------------------+
2613 + *
2614 + */
2615 +#define TOE_QUEUE_HDR_ADDR(n)          (TOE_TOE_QUE_HDR_BASE + n * 32)
2616 +#define TOE_Q_HDR_AREA_END             (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
2617 +#define TOE_DEFAULT_Q_HDR_BASE(x)      (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
2618 +#define TOE_CLASS_Q_HDR_BASE           (TOE_NONTOE_QUE_HDR_BASE + 0x10)
2619 +#define TOE_INTR_Q_HDR_BASE            (TOE_NONTOE_QUE_HDR_BASE + 0x80)
2620 +#define INTERRUPT_QUEUE_HDR_ADDR(n)    (TOE_INTR_Q_HDR_BASE + n * 8)
2621 +#define NONTOE_Q_HDR_AREA_END          (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
2622 +/*
2623 + * TOE Queue Header Word 0
2624 + */
2625 +typedef union {
2626 +       unsigned int bits32;
2627 +       unsigned int base_size;
2628 +} TOE_QHDR0_T;
2629 +
2630 +#define TOE_QHDR0_BASE_MASK    (~0x0f)
2631 +
2632 +/*
2633 + * TOE Queue Header Word 1
2634 + */
2635 +typedef union {
2636 +       unsigned int bits32;
2637 +       struct bit_qhdr1 {
2638 +               unsigned int rptr       : 16;   // bit 15:0
2639 +               unsigned int wptr       : 16;   // bit 31:16
2640 +       } bits;
2641 +} TOE_QHDR1_T;
2642 +
2643 +/*
2644 + * TOE Queue Header Word 2
2645 + */
2646 +typedef union {
2647 +       unsigned int bits32;
2648 +       struct bit_qhdr2 {
2649 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
2650 +               unsigned int reserved           : 7;    // bit 23:17
2651 +               unsigned int dack               : 1;    // bit 24       1: Duplicated ACK
2652 +               unsigned int abn                : 1;    // bit 25       1: Abnormal case Found
2653 +               unsigned int tcp_opt            : 1;    // bit 26       1: Have TCP option
2654 +               unsigned int ip_opt             : 1;    // bit 27       1: have IPV4 option or IPV6 Extension header
2655 +               unsigned int sat                : 1;    // bit 28       1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
2656 +               unsigned int osq                : 1;    // bit 29       1: out of sequence
2657 +               unsigned int ctl                : 1;    // bit 30       1: have control flag bits (except ack)
2658 +               unsigned int usd                : 1;    // bit 31       0: if no data assembled yet
2659 +       } bits;
2660 +} TOE_QHDR2_T;
2661 +
2662 +/*
2663 + * TOE Queue Header Word 3
2664 + */
2665 +typedef union {
2666 +       unsigned int bits32;
2667 +       unsigned int seq_num;
2668 +} TOE_QHDR3_T;
2669 +
2670 +/*
2671 + * TOE Queue Header Word 4
2672 + */
2673 +typedef union {
2674 +       unsigned int bits32;
2675 +       unsigned int ack_num;
2676 +} TOE_QHDR4_T;
2677 +
2678 +/*
2679 + * TOE Queue Header Word 5
2680 + */
2681 +typedef union {
2682 +       unsigned int bits32;
2683 +       struct bit_qhdr5 {
2684 +               unsigned int AckCnt     : 16;   // bit 15:0
2685 +               unsigned int SeqCnt     : 16;   // bit 31:16
2686 +       } bits;
2687 +} TOE_QHDR5_T;
2688 +
2689 +/*
2690 + * TOE Queue Header Word 6
2691 + */
2692 +typedef union {
2693 +       unsigned int bits32;
2694 +       struct bit_qhdr6 {
2695 +               unsigned int WinSize    : 16;   // bit 15:0
2696 +               unsigned int iq_num     : 2;    // bit 17:16
2697 +               unsigned int MaxPktSize : 14;   // bit 31:18
2698 +       } bits;
2699 +} TOE_QHDR6_T;
2700 +
2701 +/*
2702 + * TOE Queue Header Word 7
2703 + */
2704 +typedef union {
2705 +       unsigned int bits32;
2706 +       struct bit_qhdr7 {
2707 +               unsigned int AckThreshold       : 16;   // bit 15:0
2708 +               unsigned int SeqThreshold       : 16;   // bit 31:16
2709 +       } bits;
2710 +} TOE_QHDR7_T;
2711 +
2712 +/*
2713 + * TOE Queue Header
2714 + */
2715 +typedef struct {
2716 +       TOE_QHDR0_T             word0;
2717 +       TOE_QHDR1_T             word1;
2718 +       TOE_QHDR2_T             word2;
2719 +       TOE_QHDR3_T             word3;
2720 +       TOE_QHDR4_T             word4;
2721 +       TOE_QHDR5_T             word5;
2722 +       TOE_QHDR6_T             word6;
2723 +       TOE_QHDR7_T             word7;
2724 +} TOE_QHDR_T;
2725 +
2726 +/*
2727 + * NONTOE Queue Header Word 0
2728 + */
2729 +typedef union {
2730 +       unsigned int bits32;
2731 +       unsigned int base_size;
2732 +} NONTOE_QHDR0_T;
2733 +
2734 +#define NONTOE_QHDR0_BASE_MASK         (~0x0f)
2735 +
2736 +/*
2737 + * NONTOE Queue Header Word 1
2738 + */
2739 +typedef union {
2740 +       unsigned int bits32;
2741 +       struct bit_nonqhdr1 {
2742 +               unsigned int rptr       : 16;   // bit 15:0
2743 +               unsigned int wptr       : 16;   // bit 31:16
2744 +       } bits;
2745 +} NONTOE_QHDR1_T;
2746 +
2747 +/*
2748 + * Non-TOE Queue Header
2749 + */
2750 +typedef struct {
2751 +       NONTOE_QHDR0_T          word0;
2752 +       NONTOE_QHDR1_T          word1;
2753 +} NONTOE_QHDR_T;
2754 +
2755 +/*
2756 + * Interrupt Queue Header Word 0
2757 + */
2758 +typedef union {
2759 +       unsigned int bits32;
2760 +       struct bit_intrqhdr0 {
2761 +               unsigned int win_size   : 16;   // bit 15:0     Descriptor Ring Size
2762 +               unsigned int wptr       : 16;   // bit 31:16    Write Pointer where hw stopped
2763 +       } bits;
2764 +} INTR_QHDR0_T;
2765 +
2766 +/*
2767 + * Interrupt Queue Header Word 1
2768 + */
2769 +typedef union {
2770 +       unsigned int bits32;
2771 +       struct bit_intrqhdr1 {
2772 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
2773 +               unsigned int tcp_qid            : 8;    // bit 24:17    TCP Queue ID
2774 +               unsigned int dack               : 1;    // bit 25       1: Duplicated ACK
2775 +               unsigned int abn                : 1;    // bit 26       1: Abnormal case Found
2776 +               unsigned int tcp_opt            : 1;    // bit 27       1: Have TCP option
2777 +               unsigned int ip_opt             : 1;    // bit 28       1: have IPV4 option or IPV6 Extension header
2778 +               unsigned int sat                : 1;    // bit 29       1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
2779 +               unsigned int osq                : 1;    // bit 30       1: out of sequence
2780 +               unsigned int ctl                : 1;    // bit 31       1: have control flag bits (except ack)
2781 +       } bits;
2782 +} INTR_QHDR1_T;
2783 +
2784 +/*
2785 + * Interrupt Queue Header Word 2
2786 + */
2787 +typedef union {
2788 +       unsigned int bits32;
2789 +       unsigned int seq_num;
2790 +} INTR_QHDR2_T;
2791 +
2792 +/*
2793 + * Interrupt Queue Header Word 3
2794 + */
2795 +typedef union {
2796 +       unsigned int bits32;
2797 +       unsigned int ack_num;
2798 +} INTR_QHDR3_T;
2799 +
2800 +/*
2801 + * Interrupt Queue Header Word 4
2802 + */
2803 +typedef union {
2804 +       unsigned int bits32;
2805 +       struct bit_intrqhdr4 {
2806 +               unsigned int AckCnt             : 16;   // bit 15:0     Ack# change since last ack# intr.
2807 +               unsigned int SeqCnt             : 16;   // bit 31:16    Seq# change since last seq# intr.
2808 +       } bits;
2809 +} INTR_QHDR4_T;
2810 +
2811 +/*
2812 + * Interrupt Queue Header
2813 + */
2814 +typedef struct {
2815 +       INTR_QHDR0_T            word0;
2816 +       INTR_QHDR1_T            word1;
2817 +       INTR_QHDR2_T            word2;
2818 +       INTR_QHDR3_T            word3;
2819 +       INTR_QHDR4_T            word4;
2820 +       unsigned int            word5;
2821 +       unsigned int            word6;
2822 +       unsigned int            word7;
2823 +} INTR_QHDR_T;
2824 +
2825 +/*
2826 + * GMAC private data
2827 + */
2828 +typedef struct {
2829 +       void __iomem            *rwptr_reg;
2830 +       unsigned int            desc_base;
2831 +       unsigned int            desc_base_dma;
2832 +       unsigned short          finished_idx;
2833 +       struct sk_buff          *tx_skb[TOE_GMAC_SWTXQ_DESC_NUM];
2834 +} GMAC_SWTXQ_T;
2835 +
2836 +struct gmac_private {
2837 +       struct phy_device       *phydev;
2838 +       unsigned int            port_id;
2839 +       void __iomem            *base_addr;
2840 +       void __iomem            *dma_base_addr;
2841 +       unsigned int            swtxq_desc_base;
2842 +       GMAC_SWTXQ_T            swtxq[TOE_SW_TXQ_NUM];
2843 +       NONTOE_QHDR_T           *default_qhdr;
2844 +       unsigned int            default_desc_base;
2845 +       dma_addr_t              default_desc_base_dma;
2846 +       dma_addr_t              swtxq_desc_base_dma;
2847 +       unsigned int            flow_control_enable;
2848 +       unsigned int            intr0_enabled;
2849 +       unsigned int            intr1_enabled;
2850 +       unsigned int            intr2_enabled;
2851 +       unsigned int            intr3_enabled;
2852 +       unsigned int            intr4_enabled;
2853 +       unsigned int            intr0_selected;
2854 +       unsigned int            intr1_selected;
2855 +       unsigned int            intr2_selected;
2856 +       unsigned int            intr3_selected;
2857 +       unsigned int            intr4_selected;
2858 +};
2859 +
2860 +struct toe_private {
2861 +       void __iomem            *global_base;
2862 +       struct net_device       *net_dev[2];
2863 +       struct device           *dev;
2864 +       struct work_struct      freq_work;
2865 +       spinlock_t              freeq_lock;
2866 +       unsigned int            swfq_desc_base;
2867 +       unsigned int            hwfq_desc_base;
2868 +       unsigned int            hwfq_buf_base;
2869 +       dma_addr_t              sw_freeq_desc_base_dma;
2870 +       dma_addr_t              hw_freeq_desc_base_dma;
2871 +       dma_addr_t              hwfq_buf_base_dma;
2872 +       dma_addr_t              hwfq_buf_end_dma;
2873 +};
2874 +
2875 +#define GMAC_PORT0     0
2876 +#define GMAC_PORT1     1
2877 +
2878 +#endif /* _GMAC_SL351x_H */
2879 --- /dev/null
2880 +++ b/drivers/net/gemini_negmac/Makefile
2881 @@ -0,0 +1,3 @@
2882 +obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC)+= gemini_negmac.o
2883 +
2884 +gemini_negmac-objs := gm_gmac.o
2885 --- a/drivers/net/Kconfig
2886 +++ b/drivers/net/Kconfig
2887 @@ -100,6 +100,13 @@ config NET_FC
2888           adaptor below. You also should have said Y to "SCSI support" and
2889           "SCSI generic support".
2890
2891 +config GEMINI_NET_ENGINE_GMAC
2892 +       tristate "Gemini Gigabit Ethernet support"
2893 +       depends on ARCH_GEMINI
2894 +       select PHYLIB
2895 +       help
2896 +         This driver supports Gemini TOE and NAT dual Gigabit Ethernet.
2897 +
2898  config MII
2899         tristate "Generic Media Independent Interface device support"
2900         help
2901 --- a/drivers/net/Makefile
2902 +++ b/drivers/net/Makefile
2903 @@ -34,6 +34,7 @@ obj-$(CONFIG_ETRAX_ETHERNET) += cris/
2904  obj-$(CONFIG_NET_DSA) += dsa/
2905  obj-$(CONFIG_ETHERNET) += ethernet/
2906  obj-$(CONFIG_FDDI) += fddi/
2907 +obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC) += gemini_negmac/
2908  obj-$(CONFIG_HIPPI) += hippi/
2909  obj-$(CONFIG_HAMRADIO) += hamradio/
2910  obj-$(CONFIG_IRDA) += irda/