target/linux/gemini/patches-3.18/120-net-add-gemini-gmac-driver.patch

   1 --- /dev/null
   2 +++ b/arch/arm/mach-gemini/include/mach/gmac.h
   3 @@ -0,0 +1,21 @@
   4 +/*
   5 + * Gemini GMAC specific defines
   6 + *
   7 + * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@gmail.com>
   8 + *
   9 + * This program is free software; you can redistribute it and/or modify
  10 + * it under the terms of the GNU General Public License as published by
  11 + * the Free Software Foundation; either version 2 of the License, or
  12 + * (at your option) any later version.
  13 + */
  14 +#ifndef __NET_GEMINI_PLATFORM_H__
  15 +#define __NET_GEMINI_PLATFORM_H__
  16 +
  17 +#include <linux/phy.h>
  18 +
  19 +struct gemini_gmac_platform_data {
  20 +       char *bus_id[2]; /* NULL means that this port is not used */
  21 +       phy_interface_t interface[2];
  22 +};
  23 +
  24 +#endif /* __NET_GEMINI_PLATFORM_H__ */
  25 --- a/arch/arm/mach-gemini/common.h
  26 +++ b/arch/arm/mach-gemini/common.h
  27 @@ -13,6 +13,7 @@
  28  #define __GEMINI_COMMON_H__
  29
  30  struct mtd_partition;
  31 +struct gemini_gmac_platform_data;
  32
  33  extern void gemini_map_io(void);
  34  extern void gemini_init_irq(void);
  35 @@ -26,6 +27,7 @@ extern int platform_register_pflash(unsi
  36                                     struct mtd_partition *parts,
  37                                     unsigned int nr_parts);
  38  extern int platform_register_watchdog(void);
  39 +extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
  40
  41  extern void gemini_restart(enum reboot_mode mode, const char *cmd);
  42
  43 --- a/arch/arm/mach-gemini/devices.c
  44 +++ b/arch/arm/mach-gemini/devices.c
  45 @@ -17,6 +17,7 @@
  46  #include <mach/irqs.h>
  47  #include <mach/hardware.h>
  48  #include <mach/global_reg.h>
  49 +#include <mach/gmac.h>
  50  #include "common.h"
  51
  52  static struct plat_serial8250_port serial_platform_data[] = {
  53 @@ -134,3 +135,56 @@ int __init platform_register_watchdog(vo
  54  {
  55         return platform_device_register(&wdt_device);
  56  }
  57 +
  58 +static struct resource gmac_resources[] = {
  59 +       {
  60 +               .start  = GEMINI_TOE_BASE,
  61 +               .end    = GEMINI_TOE_BASE + 0xffff,
  62 +               .flags  = IORESOURCE_MEM,
  63 +       },
  64 +       {
  65 +               .start  = IRQ_GMAC0,
  66 +               .end    = IRQ_GMAC0,
  67 +               .flags  = IORESOURCE_IRQ,
  68 +       },
  69 +       {
  70 +               .start  = IRQ_GMAC1,
  71 +               .end    = IRQ_GMAC1,
  72 +               .flags  = IORESOURCE_IRQ,
  73 +       },
  74 +};
  75 +
  76 +static u64 gmac_dmamask = 0xffffffffUL;
  77 +
  78 +static struct platform_device ethernet_device = {
  79 +       .name   = "gmac-gemini",
  80 +       .id     = 0,
  81 +       .dev    = {
  82 +               .dma_mask               = &gmac_dmamask,
  83 +               .coherent_dma_mask      = 0xffffffff,
  84 +       },
  85 +       .num_resources  = ARRAY_SIZE(gmac_resources),
  86 +       .resource       = gmac_resources,
  87 +};
  88 +
  89 +int platform_register_ethernet(struct gemini_gmac_platform_data *pdata)
  90 +{
  91 +       unsigned int reg;
  92 +
  93 +       reg = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
  94 +               GLOBAL_MISC_CTRL));
  95 +
  96 +       reg &= ~(GMAC_GMII | GMAC_1_ENABLE);
  97 +
  98 +       if (pdata->bus_id[1])
  99 +               reg |= GMAC_1_ENABLE;
 100 +       else if (pdata->interface[0] == PHY_INTERFACE_MODE_GMII)
 101 +               reg |= GMAC_GMII;
 102 +
 103 +       writel(reg, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
 104 +               GLOBAL_MISC_CTRL));
 105 +
 106 +       ethernet_device.dev.platform_data = pdata;
 107 +
 108 +       return platform_device_register(&ethernet_device);
 109 +}
 110 --- a/drivers/net/ethernet/Kconfig
 111 +++ b/drivers/net/ethernet/Kconfig
 112 @@ -70,6 +70,7 @@ source "drivers/net/ethernet/neterion/Kc
 113  source "drivers/net/ethernet/faraday/Kconfig"
 114  source "drivers/net/ethernet/freescale/Kconfig"
 115  source "drivers/net/ethernet/fujitsu/Kconfig"
 116 +source "drivers/net/ethernet/gemini/Kconfig"
 117  source "drivers/net/ethernet/hisilicon/Kconfig"
 118  source "drivers/net/ethernet/hp/Kconfig"
 119  source "drivers/net/ethernet/ibm/Kconfig"
 120 --- a/drivers/net/ethernet/Makefile
 121 +++ b/drivers/net/ethernet/Makefile
 122 @@ -33,6 +33,7 @@ obj-$(CONFIG_NET_VENDOR_EXAR) += neterio
 123  obj-$(CONFIG_NET_VENDOR_FARADAY) += faraday/
 124  obj-$(CONFIG_NET_VENDOR_FREESCALE) += freescale/
 125  obj-$(CONFIG_NET_VENDOR_FUJITSU) += fujitsu/
 126 +obj-$(CONFIG_NET_VENDOR_GEMINI) += gemini/
 127  obj-$(CONFIG_NET_VENDOR_HISILICON) += hisilicon/
 128  obj-$(CONFIG_NET_VENDOR_HP) += hp/
 129  obj-$(CONFIG_NET_VENDOR_IBM) += ibm/
 130 --- /dev/null
 131 +++ b/drivers/net/ethernet/gemini/Kconfig
 132 @@ -0,0 +1,31 @@
 133 +#
 134 +# Gemini device configuration
 135 +#
 136 +
 137 +config NET_VENDOR_GEMINI
 138 +       bool "Cortina Gemini devices"
 139 +       default y
 140 +       depends on ARCH_GEMINI
 141 +       ---help---
 142 +         If you have a network (Ethernet) card belonging to this class, say Y
 143 +         and read the Ethernet-HOWTO, available from
 144 +         <http://www.tldp.org/docs.html#howto>.
 145 +
 146 +         Note that the answer to this question doesn't directly affect the
 147 +         kernel: saying N will just cause the configurator to skip all
 148 +         the questions about D-Link devices. If you say Y, you will be asked for
 149 +         your specific card in the following questions.
 150 +
 151 +if NET_VENDOR_GEMINI
 152 +
 153 +config GEMINI_SL351X
 154 +       tristate "StorLink SL351x Gigabit Ethernet support"
 155 +       depends on ARCH_GEMINI
 156 +       select PHYLIB
 157 +       select MDIO_BITBANG
 158 +       select MDIO_GPIO
 159 +       select CRC32
 160 +       ---help---
 161 +         This driver supports StorLink SL351x (Gemini) dual Gigabit Ethernet.
 162 +
 163 +endif # NET_VENDOR_GEMINI
 164 --- /dev/null
 165 +++ b/drivers/net/ethernet/gemini/Makefile
 166 @@ -0,0 +1,5 @@
 167 +#
 168 +# Makefile for the Cortina Gemini network device drivers.
 169 +#
 170 +
 171 +obj-$(CONFIG_GEMINI_SL351X) += sl351x.o
 172 --- /dev/null
 173 +++ b/drivers/net/ethernet/gemini/sl351x.c
 174 @@ -0,0 +1,2340 @@
 175 +/*
 176 + *  Ethernet device driver for Gemini SoC (SL351x GMAC).
 177 + *
 178 + *  Copyright (C) 2011, Tobias Waldvogel <tobias.waldvogel@gmail.com>
 179 + *
 180 + *  Based on work by Michał Mirosław <mirq-linux@rere.qmqm.pl> and
 181 + *  Paulius Zaleckas <paulius.zaleckas@gmail.com> and
 182 + *  Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it> and
 183 + *  GPLd spaghetti code from Raidsonic and other Gemini-based NAS vendors.
 184 + *
 185 + * This program is free software; you can redistribute it and/or modify
 186 + * it under the terms of the GNU General Public License as published by
 187 + * the Free Software Foundation; either version 2 of the License, or
 188 + * (at your option) any later version.
 189 + */
 190 +
 191 +#include <linux/module.h>
 192 +#include <linux/kernel.h>
 193 +#include <linux/init.h>
 194 +
 195 +#include <linux/spinlock.h>
 196 +#include <linux/slab.h>
 197 +#include <linux/dma-mapping.h>
 198 +#include <linux/cache.h>
 199 +#include <linux/interrupt.h>
 200 +
 201 +#include <linux/platform_device.h>
 202 +#include <linux/etherdevice.h>
 203 +#include <linux/if_vlan.h>
 204 +#include <linux/skbuff.h>
 205 +#include <linux/phy.h>
 206 +#include <linux/crc32.h>
 207 +#include <linux/ethtool.h>
 208 +#include <linux/tcp.h>
 209 +#include <linux/u64_stats_sync.h>
 210 +
 211 +#include <linux/in.h>
 212 +#include <linux/ip.h>
 213 +#include <linux/ipv6.h>
 214 +
 215 +#include <mach/hardware.h>
 216 +#include <mach/global_reg.h>
 217 +
 218 +#include <mach/gmac.h>
 219 +#include "sl351x_hw.h"
 220 +
 221 +#define DRV_NAME               "gmac-gemini"
 222 +#define DRV_VERSION            "1.0"
 223 +
 224 +#define HSIZE_8                        0b00
 225 +#define HSIZE_16               0b01
 226 +#define HSIZE_32               0b10
 227 +
 228 +#define HBURST_SINGLE          0b00
 229 +#define HBURST_INCR            0b01
 230 +#define HBURST_INCR4           0b10
 231 +#define HBURST_INCR8           0b11
 232 +
 233 +#define HPROT_DATA_CACHE       BIT(0)
 234 +#define HPROT_PRIVILIGED       BIT(1)
 235 +#define HPROT_BUFFERABLE       BIT(2)
 236 +#define HPROT_CACHABLE         BIT(3)
 237 +
 238 +#define DEFAULT_RX_COALESCE_NSECS      0
 239 +#define DEFAULT_GMAC_RXQ_ORDER         9
 240 +#define DEFAULT_GMAC_TXQ_ORDER         8
 241 +#define DEFAULT_RX_BUF_ORDER           11
 242 +#define DEFAULT_NAPI_WEIGHT            64
 243 +#define TX_MAX_FRAGS                   16
 244 +#define TX_QUEUE_NUM                   1       /* max: 6 */
 245 +#define RX_MAX_ALLOC_ORDER             2
 246 +
 247 +#define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT|GMAC0_TXPERR_INT_BIT| \
 248 +       GMAC0_RXDERR_INT_BIT|GMAC0_RXPERR_INT_BIT)
 249 +#define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT| \
 250 +                             GMAC0_SWTQ00_FIN_INT_BIT)
 251 +#define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT|GMAC0_RX_OVERRUN_INT_BIT)
 252 +
 253 +#define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
 254 +               NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
 255 +               NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
 256 +
 257 +MODULE_AUTHOR("Tobias Waldvogel");
 258 +MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
 259 +MODULE_LICENSE("GPL");
 260 +MODULE_ALIAS("platform:" DRV_NAME);
 261 +
 262 +struct toe_private {
 263 +       void __iomem    *iomem;
 264 +       spinlock_t      irq_lock;
 265 +
 266 +       struct net_device *netdev[2];
 267 +       __le32          mac_addr[2][3];
 268 +
 269 +       struct device   *dev;
 270 +       int             irq;
 271 +
 272 +       unsigned int    freeq_order;
 273 +       unsigned int    freeq_frag_order;
 274 +       GMAC_RXDESC_T   *freeq_ring;
 275 +       dma_addr_t      freeq_dma_base;
 276 +       struct page     **freeq_page_tab;
 277 +       spinlock_t      freeq_lock;
 278 +};
 279 +
 280 +struct gmac_txq {
 281 +       GMAC_TXDESC_T   *ring;
 282 +       struct sk_buff  **skb;
 283 +       unsigned int    cptr;
 284 +       unsigned int    noirq_packets;
 285 +};
 286 +
 287 +struct gmac_private {
 288 +       unsigned int            num;
 289 +       struct toe_private      *toe;
 290 +       void __iomem            *ctl_iomem;
 291 +       void __iomem            *dma_iomem;
 292 +
 293 +       void __iomem            *rxq_rwptr;
 294 +       GMAC_RXDESC_T           *rxq_ring;
 295 +       unsigned int            rxq_order;
 296 +
 297 +       struct napi_struct      napi;
 298 +       struct hrtimer          rx_coalesce_timer;
 299 +       unsigned int            rx_coalesce_nsecs;
 300 +       unsigned int            freeq_refill;
 301 +       struct gmac_txq         txq[TX_QUEUE_NUM];
 302 +       unsigned int            txq_order;
 303 +       unsigned int            irq_every_tx_packets;
 304 +
 305 +       dma_addr_t              rxq_dma_base;
 306 +       dma_addr_t              txq_dma_base;
 307 +
 308 +       unsigned int            msg_enable;
 309 +       spinlock_t              config_lock;
 310 +
 311 +       struct u64_stats_sync   tx_stats_syncp;
 312 +       struct u64_stats_sync   rx_stats_syncp;
 313 +       struct u64_stats_sync   ir_stats_syncp;
 314 +
 315 +       struct rtnl_link_stats64 stats;
 316 +       u64                     hw_stats[RX_STATS_NUM];
 317 +       u64                     rx_stats[RX_STATUS_NUM];
 318 +       u64                     rx_csum_stats[RX_CHKSUM_NUM];
 319 +       u64                     rx_napi_exits;
 320 +       u64                     tx_frag_stats[TX_MAX_FRAGS];
 321 +       u64                     tx_frags_linearized;
 322 +       u64                     tx_hw_csummed;
 323 +};
 324 +
 325 +#define GMAC_STATS_NUM ( \
 326 +       RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
 327 +       TX_MAX_FRAGS + 2)
 328 +
 329 +static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
 330 +       "GMAC_IN_DISCARDS",
 331 +       "GMAC_IN_ERRORS",
 332 +       "GMAC_IN_MCAST",
 333 +       "GMAC_IN_BCAST",
 334 +       "GMAC_IN_MAC1",
 335 +       "GMAC_IN_MAC2",
 336 +       "RX_STATUS_GOOD_FRAME",
 337 +       "RX_STATUS_TOO_LONG_GOOD_CRC",
 338 +       "RX_STATUS_RUNT_FRAME",
 339 +       "RX_STATUS_SFD_NOT_FOUND",
 340 +       "RX_STATUS_CRC_ERROR",
 341 +       "RX_STATUS_TOO_LONG_BAD_CRC",
 342 +       "RX_STATUS_ALIGNMENT_ERROR",
 343 +       "RX_STATUS_TOO_LONG_BAD_ALIGN",
 344 +       "RX_STATUS_RX_ERR",
 345 +       "RX_STATUS_DA_FILTERED",
 346 +       "RX_STATUS_BUFFER_FULL",
 347 +       "RX_STATUS_11",
 348 +       "RX_STATUS_12",
 349 +       "RX_STATUS_13",
 350 +       "RX_STATUS_14",
 351 +       "RX_STATUS_15",
 352 +       "RX_CHKSUM_IP_UDP_TCP_OK",
 353 +       "RX_CHKSUM_IP_OK_ONLY",
 354 +       "RX_CHKSUM_NONE",
 355 +       "RX_CHKSUM_3",
 356 +       "RX_CHKSUM_IP_ERR_UNKNOWN",
 357 +       "RX_CHKSUM_IP_ERR",
 358 +       "RX_CHKSUM_TCP_UDP_ERR",
 359 +       "RX_CHKSUM_7",
 360 +       "RX_NAPI_EXITS",
 361 +       "TX_FRAGS[1]",
 362 +       "TX_FRAGS[2]",
 363 +       "TX_FRAGS[3]",
 364 +       "TX_FRAGS[4]",
 365 +       "TX_FRAGS[5]",
 366 +       "TX_FRAGS[6]",
 367 +       "TX_FRAGS[7]",
 368 +       "TX_FRAGS[8]",
 369 +       "TX_FRAGS[9]",
 370 +       "TX_FRAGS[10]",
 371 +       "TX_FRAGS[11]",
 372 +       "TX_FRAGS[12]",
 373 +       "TX_FRAGS[13]",
 374 +       "TX_FRAGS[14]",
 375 +       "TX_FRAGS[15]",
 376 +       "TX_FRAGS[16+]",
 377 +       "TX_FRAGS_LINEARIZED",
 378 +       "TX_HW_CSUMMED",
 379 +};
 380 +
 381 +static void gmac_dump_dma_state(struct net_device *dev);
 382 +
 383 +static void gmac_update_config0_reg(struct net_device *dev, u32 val, u32 vmask)
 384 +{
 385 +       struct gmac_private *gmac = netdev_priv(dev);
 386 +       unsigned long flags;
 387 +       u32 reg;
 388 +
 389 +       spin_lock_irqsave(&gmac->config_lock, flags);
 390 +
 391 +       reg = readl(gmac->ctl_iomem + GMAC_CONFIG0);
 392 +       reg = (reg & ~vmask) | val;
 393 +       writel(reg, gmac->ctl_iomem + GMAC_CONFIG0);
 394 +
 395 +       spin_unlock_irqrestore(&gmac->config_lock, flags);
 396 +}
 397 +
 398 +static void gmac_enable_tx_rx(struct net_device *dev)
 399 +{
 400 +       struct gmac_private *gmac = netdev_priv(dev);
 401 +       void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0;
 402 +       unsigned long flags;
 403 +       u32 reg;
 404 +
 405 +       spin_lock_irqsave(&gmac->config_lock, flags);
 406 +
 407 +       reg = readl(config0);
 408 +       reg &= ~CONFIG0_TX_RX_DISABLE;
 409 +       writel(reg, config0);
 410 +
 411 +       spin_unlock_irqrestore(&gmac->config_lock, flags);
 412 +}
 413 +
 414 +static void gmac_disable_tx_rx(struct net_device *dev)
 415 +{
 416 +       struct gmac_private *gmac = netdev_priv(dev);
 417 +       void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0;
 418 +       unsigned long flags;
 419 +       u32 reg;
 420 +
 421 +       spin_lock_irqsave(&gmac->config_lock, flags);
 422 +
 423 +       reg = readl(config0);
 424 +       reg |= CONFIG0_TX_RX_DISABLE;
 425 +       writel(reg, config0);
 426 +
 427 +       spin_unlock_irqrestore(&gmac->config_lock, flags);
 428 +
 429 +       mdelay(10);     /* let GMAC consume packet */
 430 +}
 431 +
 432 +static void gmac_set_flow_control(struct net_device *dev, bool tx, bool rx)
 433 +{
 434 +       struct gmac_private *gmac = netdev_priv(dev);
 435 +       void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0;
 436 +       unsigned long flags;
 437 +       u32 reg;
 438 +
 439 +       spin_lock_irqsave(&gmac->config_lock, flags);
 440 +
 441 +       reg = readl(config0);
 442 +       reg &= ~CONFIG0_FLOW_CTL;
 443 +       if (tx)
 444 +               reg |= CONFIG0_FLOW_TX;
 445 +       if (rx)
 446 +               reg |= CONFIG0_FLOW_RX;
 447 +       writel(reg, config0);
 448 +
 449 +       spin_unlock_irqrestore(&gmac->config_lock, flags);
 450 +}
 451 +
 452 +static void gmac_update_link_state(struct net_device *dev)
 453 +{
 454 +       struct gmac_private *gmac = netdev_priv(dev);
 455 +       void __iomem *status_reg = gmac->ctl_iomem + GMAC_STATUS;
 456 +       struct phy_device *phydev = dev->phydev;
 457 +       GMAC_STATUS_T status, old_status;
 458 +       int pause_tx=0, pause_rx=0;
 459 +
 460 +       old_status.bits32 = status.bits32 = readl(status_reg);
 461 +
 462 +       status.bits.link = phydev->link;
 463 +       status.bits.duplex = phydev->duplex;
 464 +
 465 +       switch (phydev->speed) {
 466 +       case 1000:
 467 +               status.bits.speed = GMAC_SPEED_1000;
 468 +               if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
 469 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
 470 +               break;
 471 +       case 100:
 472 +               status.bits.speed = GMAC_SPEED_100;
 473 +               if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
 474 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
 475 +               break;
 476 +       case 10:
 477 +               status.bits.speed = GMAC_SPEED_10;
 478 +               if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
 479 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
 480 +               break;
 481 +       default:
 482 +               netdev_warn(dev, "Not supported PHY speed (%d)\n",
 483 +                       phydev->speed);
 484 +       }
 485 +
 486 +       if (phydev->duplex == DUPLEX_FULL) {
 487 +               u16 lcladv = phy_read(phydev, MII_ADVERTISE);
 488 +               u16 rmtadv = phy_read(phydev, MII_LPA);
 489 +               u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
 490 +
 491 +               if (cap & FLOW_CTRL_RX)
 492 +                       pause_rx=1;
 493 +               if (cap & FLOW_CTRL_TX)
 494 +                       pause_tx=1;
 495 +       }
 496 +
 497 +       gmac_set_flow_control(dev, pause_tx, pause_rx);
 498 +
 499 +       if (old_status.bits32 == status.bits32)
 500 +               return;
 501 +
 502 +       if (netif_msg_link(gmac)) {
 503 +               phy_print_status(phydev);
 504 +               netdev_info(dev, "link flow control: %s\n",
 505 +                       phydev->pause
 506 +                               ? (phydev->asym_pause ? "tx" : "both")
 507 +                               : (phydev->asym_pause ? "rx" : "none")
 508 +               );
 509 +       }
 510 +
 511 +       gmac_disable_tx_rx(dev);
 512 +       writel(status.bits32, status_reg);
 513 +       gmac_enable_tx_rx(dev);
 514 +}
 515 +
 516 +static int gmac_setup_phy(struct net_device *dev)
 517 +{
 518 +       struct gmac_private *gmac = netdev_priv(dev);
 519 +       struct toe_private *toe = gmac->toe;
 520 +       struct gemini_gmac_platform_data *pdata = toe->dev->platform_data;
 521 +       GMAC_STATUS_T status = { .bits32 = 0 };
 522 +       int num = dev->dev_id;
 523 +
 524 +       dev->phydev = phy_connect(dev, pdata->bus_id[num],
 525 +               &gmac_update_link_state, pdata->interface[num]);
 526 +
 527 +       if (IS_ERR(dev->phydev)) {
 528 +               int err = PTR_ERR(dev->phydev);
 529 +               dev->phydev = NULL;
 530 +               return err;
 531 +       }
 532 +
 533 +       dev->phydev->supported &= PHY_GBIT_FEATURES;
 534 +       dev->phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause;
 535 +       dev->phydev->advertising = dev->phydev->supported;
 536 +
 537 +       /* set PHY interface type */
 538 +       switch (dev->phydev->interface) {
 539 +       case PHY_INTERFACE_MODE_MII:
 540 +               status.bits.mii_rmii = GMAC_PHY_MII;
 541 +               break;
 542 +       case PHY_INTERFACE_MODE_GMII:
 543 +               status.bits.mii_rmii = GMAC_PHY_GMII;
 544 +               break;
 545 +       case PHY_INTERFACE_MODE_RGMII:
 546 +               status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
 547 +               break;
 548 +       default:
 549 +               netdev_err(dev, "Unsupported MII interface\n");
 550 +               phy_disconnect(dev->phydev);
 551 +               dev->phydev = NULL;
 552 +               return -EINVAL;
 553 +       }
 554 +       writel(status.bits32, gmac->ctl_iomem + GMAC_STATUS);
 555 +
 556 +       return 0;
 557 +}
 558 +
 559 +static int gmac_pick_rx_max_len(int max_l3_len)
 560 +{
 561 +       /* index = CONFIG_MAXLEN_XXX values */
 562 +       static const int max_len[8] = {
 563 +               1536, 1518, 1522, 1542,
 564 +               9212, 10236, 1518, 1518
 565 +       };
 566 +       int i, n = 5;
 567 +
 568 +       max_l3_len += ETH_HLEN + VLAN_HLEN;
 569 +
 570 +       if (max_l3_len > max_len[n])
 571 +               return -1;
 572 +
 573 +       for (i = 0; i < 5; ++i) {
 574 +               if (max_len[i] >= max_l3_len && max_len[i] < max_len[n])
 575 +                       n = i;
 576 +       }
 577 +
 578 +       return n;
 579 +}
 580 +
 581 +static int gmac_init(struct net_device *dev)
 582 +{
 583 +       struct gmac_private *gmac = netdev_priv(dev);
 584 +       u32 val;
 585 +
 586 +       GMAC_CONFIG0_T config0 = { .bits = {
 587 +               .dis_tx = 1,
 588 +               .dis_rx = 1,
 589 +               .ipv4_rx_chksum = 1,
 590 +               .ipv6_rx_chksum = 1,
 591 +               .rx_err_detect = 1,
 592 +               .rgmm_edge = 1,
 593 +               .port0_chk_hwq = 1,
 594 +               .port1_chk_hwq = 1,
 595 +               .port0_chk_toeq = 1,
 596 +               .port1_chk_toeq = 1,
 597 +               .port0_chk_classq = 1,
 598 +               .port1_chk_classq = 1,
 599 +       } };
 600 +       GMAC_AHB_WEIGHT_T ahb_weight = { .bits = {
 601 +               .rx_weight = 1,
 602 +               .tx_weight = 1,
 603 +               .hash_weight = 1,
 604 +               .pre_req = 0x1f,
 605 +               .tqDV_threshold = 0,
 606 +       } };
 607 +       GMAC_TX_WCR0_T hw_weigh = { .bits = {
 608 +               .hw_tq3 = 1,
 609 +               .hw_tq2 = 1,
 610 +               .hw_tq1 = 1,
 611 +               .hw_tq0 = 1,
 612 +       } };
 613 +       GMAC_TX_WCR1_T sw_weigh = { .bits = {
 614 +               .sw_tq5 = 1,
 615 +               .sw_tq4 = 1,
 616 +               .sw_tq3 = 1,
 617 +               .sw_tq2 = 1,
 618 +               .sw_tq1 = 1,
 619 +               .sw_tq0 = 1,
 620 +       } };
 621 +       GMAC_CONFIG1_T config1 = { .bits = {
 622 +               .set_threshold = 16,
 623 +               .rel_threshold = 24,
 624 +       } };
 625 +       GMAC_CONFIG2_T config2 = { .bits = {
 626 +               .set_threshold = 16,
 627 +               .rel_threshold = 32,
 628 +       } };
 629 +       GMAC_CONFIG3_T config3 = { .bits = {
 630 +               .set_threshold = 0,
 631 +               .rel_threshold = 0,
 632 +       } };
 633 +
 634 +       config0.bits.max_len = gmac_pick_rx_max_len(dev->mtu);
 635 +
 636 +       val = readl(gmac->ctl_iomem + GMAC_CONFIG0);
 637 +       config0.bits.reserved = ((GMAC_CONFIG0_T)val).bits.reserved;
 638 +       writel(config0.bits32, gmac->ctl_iomem + GMAC_CONFIG0);
 639 +       writel(config1.bits32, gmac->ctl_iomem + GMAC_CONFIG1);
 640 +       writel(config2.bits32, gmac->ctl_iomem + GMAC_CONFIG2);
 641 +       writel(config3.bits32, gmac->ctl_iomem + GMAC_CONFIG3);
 642 +
 643 +       val = readl(gmac->dma_iomem + GMAC_AHB_WEIGHT_REG);
 644 +       writel(ahb_weight.bits32, gmac->dma_iomem + GMAC_AHB_WEIGHT_REG);
 645 +
 646 +       writel(hw_weigh.bits32,
 647 +               gmac->dma_iomem + GMAC_TX_WEIGHTING_CTRL_0_REG);
 648 +       writel(sw_weigh.bits32,
 649 +               gmac->dma_iomem + GMAC_TX_WEIGHTING_CTRL_1_REG);
 650 +
 651 +       gmac->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
 652 +       gmac->txq_order = DEFAULT_GMAC_TXQ_ORDER;
 653 +       gmac->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;
 654 +
 655 +       /* Mark every quarter of the queue a packet for interrupt
 656 +          in order to be able to wake up the queue if it was stopped */
 657 +       gmac->irq_every_tx_packets = 1 << (gmac->txq_order - 2);
 658 +
 659 +       return 0;
 660 +}
 661 +
 662 +static void gmac_uninit(struct net_device *dev)
 663 +{
 664 +       if (dev->phydev)
 665 +               phy_disconnect(dev->phydev);
 666 +}
 667 +
 668 +static int gmac_setup_txqs(struct net_device *dev)
 669 +{
 670 +       struct gmac_private *gmac = netdev_priv(dev);
 671 +       struct toe_private *toe = gmac->toe;
 672 +       void __iomem *rwptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG;
 673 +       void __iomem *base_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_BASE_REG;
 674 +
 675 +       unsigned int n_txq = dev->num_tx_queues;
 676 +       size_t entries = 1 <<gmac->txq_order;
 677 +       size_t len = n_txq * entries;
 678 +       struct gmac_txq *txq = gmac->txq;
 679 +       GMAC_TXDESC_T *desc_ring;
 680 +       struct sk_buff **skb_tab;
 681 +       unsigned int r;
 682 +       int i;
 683 +
 684 +       skb_tab = kzalloc(len * sizeof(*skb_tab), GFP_KERNEL);
 685 +       if (!skb_tab)
 686 +               return -ENOMEM;
 687 +
 688 +       desc_ring = dma_alloc_coherent(toe->dev, len * sizeof(*desc_ring),
 689 +               &gmac->txq_dma_base, GFP_KERNEL);
 690 +
 691 +       if (!desc_ring) {
 692 +               kfree(skb_tab);
 693 +               return -ENOMEM;
 694 +       }
 695 +
 696 +       BUG_ON(gmac->txq_dma_base & ~DMA_Q_BASE_MASK);
 697 +
 698 +       writel(gmac->txq_dma_base | gmac->txq_order, base_reg);
 699 +
 700 +       for (i = 0; i < n_txq; i++) {
 701 +               txq->ring = desc_ring;
 702 +               txq->skb = skb_tab;
 703 +               txq->noirq_packets = 0;
 704 +
 705 +               r = readw(rwptr_reg);
 706 +               rwptr_reg += 2;
 707 +               writew(r, rwptr_reg);
 708 +               rwptr_reg +=2;
 709 +               txq->cptr = r;
 710 +
 711 +               txq++;
 712 +               desc_ring += entries;
 713 +               skb_tab += entries;
 714 +       }
 715 +
 716 +       return 0;
 717 +}
 718 +
 719 +static void gmac_clean_txq(struct net_device *dev, struct gmac_txq *txq,
 720 +                          unsigned int r)
 721 +{
 722 +       struct gmac_private *gmac = netdev_priv(dev);
 723 +       struct toe_private *toe = gmac->toe;
 724 +       unsigned int errs = 0;
 725 +       unsigned int pkts = 0;
 726 +       unsigned int hwchksum = 0;
 727 +       unsigned long bytes = 0;
 728 +       unsigned int m = (1 << gmac->txq_order) - 1;
 729 +       unsigned int c = txq->cptr;
 730 +       GMAC_TXDESC_0_T word0;
 731 +       GMAC_TXDESC_1_T word1;
 732 +       unsigned int word3;
 733 +       dma_addr_t mapping;
 734 +       GMAC_TXDESC_T *txd;
 735 +       unsigned short nfrags;
 736 +
 737 +       if (unlikely(c == r))
 738 +               return;
 739 +
 740 +       rmb();
 741 +       while (c != r) {
 742 +               txd = txq->ring + c;
 743 +               word0 = txd->word0;
 744 +               word1 = txd->word1;
 745 +               mapping = txd->word2.buf_adr;
 746 +               word3 = txd->word3.bits32;
 747 +
 748 +               dma_unmap_single(toe->dev, mapping, word0.bits.buffer_size, DMA_TO_DEVICE);
 749 +
 750 +               if (word3 & EOF_BIT)
 751 +                       dev_kfree_skb(txq->skb[c]);
 752 +
 753 +               c++;
 754 +               c &= m;
 755 +
 756 +               if (!(word3 & SOF_BIT))
 757 +                       continue;
 758 +
 759 +               if (!word0.bits.status_tx_ok) {
 760 +                       errs++;
 761 +                       continue;
 762 +               }
 763 +
 764 +               pkts++;
 765 +               bytes += txd->word1.bits.byte_count;
 766 +
 767 +               if (word1.bits32 & TSS_CHECKUM_ENABLE)
 768 +                       hwchksum++;
 769 +
 770 +               nfrags = word0.bits.desc_count - 1;
 771 +               if (nfrags) {
 772 +                       if (nfrags >= TX_MAX_FRAGS)
 773 +                               nfrags = TX_MAX_FRAGS - 1;
 774 +
 775 +                       u64_stats_update_begin(&gmac->tx_stats_syncp);
 776 +                       gmac->tx_frag_stats[nfrags]++;
 777 +                       u64_stats_update_end(&gmac->ir_stats_syncp);
 778 +               }
 779 +       }
 780 +
 781 +       u64_stats_update_begin(&gmac->ir_stats_syncp);
 782 +       gmac->stats.tx_errors += errs;
 783 +       gmac->stats.tx_packets += pkts;
 784 +       gmac->stats.tx_bytes += bytes;
 785 +       gmac->tx_hw_csummed += hwchksum;
 786 +       u64_stats_update_end(&gmac->ir_stats_syncp);
 787 +
 788 +       txq->cptr = c;
 789 +}
 790 +
 791 +static void gmac_cleanup_txqs(struct net_device *dev)
 792 +{
 793 +       struct gmac_private *gmac = netdev_priv(dev);
 794 +       struct toe_private *toe = gmac->toe;
 795 +       void __iomem *rwptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG;
 796 +       void __iomem *base_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_BASE_REG;
 797 +
 798 +       unsigned n_txq = dev->num_tx_queues;
 799 +       unsigned int r, i;
 800 +
 801 +       for (i = 0; i < n_txq; i++) {
 802 +               r = readw(rwptr_reg);
 803 +               rwptr_reg += 2;
 804 +               writew(r, rwptr_reg);
 805 +               rwptr_reg += 2;
 806 +
 807 +               gmac_clean_txq(dev, gmac->txq + i, r);
 808 +       }
 809 +       writel(0, base_reg);
 810 +
 811 +       kfree(gmac->txq->skb);
 812 +       dma_free_coherent(toe->dev,
 813 +               n_txq * sizeof(*gmac->txq->ring) << gmac->txq_order,
 814 +               gmac->txq->ring, gmac->txq_dma_base);
 815 +}
 816 +
 817 +static int gmac_setup_rxq(struct net_device *dev)
 818 +{
 819 +       struct gmac_private *gmac = netdev_priv(dev);
 820 +       struct toe_private *toe = gmac->toe;
 821 +       NONTOE_QHDR_T __iomem *qhdr = toe->iomem + TOE_DEFAULT_Q_HDR_BASE(dev->dev_id);
 822 +
 823 +       gmac->rxq_rwptr = &qhdr->word1;
 824 +       gmac->rxq_ring = dma_alloc_coherent(toe->dev,
 825 +               sizeof(*gmac->rxq_ring) << gmac->rxq_order,
 826 +               &gmac->rxq_dma_base, GFP_KERNEL);
 827 +       if (!gmac->rxq_ring)
 828 +               return -ENOMEM;
 829 +
 830 +       BUG_ON(gmac->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK);
 831 +
 832 +       writel(gmac->rxq_dma_base | gmac->rxq_order, &qhdr->word0);
 833 +       writel(0, gmac->rxq_rwptr);
 834 +       return 0;
 835 +}
 836 +
 837 +static void gmac_cleanup_rxq(struct net_device *dev)
 838 +{
 839 +       struct gmac_private *gmac = netdev_priv(dev);
 840 +       struct toe_private *toe = gmac->toe;
 841 +
 842 +       NONTOE_QHDR_T __iomem *qhdr = toe->iomem + TOE_DEFAULT_Q_HDR_BASE(dev->dev_id);
 843 +       void __iomem *dma_reg = &qhdr->word0;
 844 +       void __iomem *ptr_reg = &qhdr->word1;
 845 +       GMAC_RXDESC_T *rxd = gmac->rxq_ring;
 846 +       DMA_RWPTR_T rw;
 847 +       unsigned int r, w;
 848 +       unsigned int m = (1 <<gmac->rxq_order) - 1;
 849 +       struct page *page;
 850 +       dma_addr_t mapping;
 851 +
 852 +       rw.bits32 = readl(ptr_reg);
 853 +       r = rw.bits.rptr;
 854 +       w = rw.bits.wptr;
 855 +       writew(r, ptr_reg + 2);
 856 +
 857 +       writel(0, dma_reg);
 858 +
 859 +       rmb();
 860 +       while (r != w) {
 861 +               mapping = rxd[r].word2.buf_adr;
 862 +               r++;
 863 +               r &= m;
 864 +
 865 +               if (!mapping)
 866 +                       continue;
 867 +
 868 +               page = pfn_to_page(dma_to_pfn(toe->dev, mapping));
 869 +               put_page(page);
 870 +       }
 871 +
 872 +       dma_free_coherent(toe->dev, sizeof(*gmac->rxq_ring) << gmac->rxq_order,
 873 +               gmac->rxq_ring, gmac->rxq_dma_base);
 874 +}
 875 +
 876 +static struct page *toe_freeq_alloc_map_page(struct toe_private *toe, int pn)
 877 +{
 878 +       unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order;
 879 +       unsigned int frag_len = 1 << toe->freeq_frag_order;
 880 +       GMAC_RXDESC_T *freeq_entry;
 881 +       dma_addr_t mapping;
 882 +       struct page *page;
 883 +       int i;
 884 +
 885 +       page = alloc_page(__GFP_COLD | GFP_ATOMIC);
 886 +       if (!page)
 887 +               return NULL;
 888 +
 889 +       mapping = dma_map_single(toe->dev, page_address(page),
 890 +                               PAGE_SIZE, DMA_FROM_DEVICE);
 891 +
 892 +       if (unlikely(dma_mapping_error(toe->dev, mapping) || !mapping)) {
 893 +               put_page(page);
 894 +               return NULL;
 895 +       }
 896 +
 897 +       freeq_entry = toe->freeq_ring + (pn << fpp_order);
 898 +       for (i = 1 << fpp_order; i > 0; --i) {
 899 +               freeq_entry->word2.buf_adr = mapping;
 900 +               freeq_entry++;
 901 +               mapping += frag_len;
 902 +       }
 903 +
 904 +       if (toe->freeq_page_tab[pn]) {
 905 +               mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr;
 906 +               dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE);
 907 +               put_page(toe->freeq_page_tab[pn]);
 908 +       }
 909 +
 910 +       toe->freeq_page_tab[pn] = page;
 911 +       return page;
 912 +}
 913 +
 914 +static unsigned int toe_fill_freeq(struct toe_private *toe, int reset)
 915 +{
 916 +       void __iomem *rwptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG;
 917 +
 918 +       DMA_RWPTR_T rw;
 919 +       unsigned int pn, epn;
 920 +       unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order;
 921 +       unsigned int m_pn = (1 << (toe->freeq_order - fpp_order)) - 1;
 922 +       struct page *page;
 923 +       unsigned int count = 0;
 924 +       unsigned long flags;
 925 +
 926 +       spin_lock_irqsave(&toe->freeq_lock, flags);
 927 +
 928 +       rw.bits32 = readl(rwptr_reg);
 929 +       pn = (reset ? rw.bits.rptr : rw.bits.wptr) >> fpp_order;
 930 +       epn = (rw.bits.rptr >> fpp_order) - 1;
 931 +       epn &= m_pn;
 932 +
 933 +       while (pn != epn) {
 934 +               page = toe->freeq_page_tab[pn];
 935 +
 936 +               if (atomic_read(&page->_count) > 1) {
 937 +                       unsigned int fl = (pn -epn) & m_pn;
 938 +
 939 +                       if (fl > 64 >> fpp_order)
 940 +                               break;
 941 +
 942 +                       page = toe_freeq_alloc_map_page(toe, pn);
 943 +                       if (!page)
 944 +                               break;
 945 +               }
 946 +
 947 +               atomic_add(1 << fpp_order, &page->_count);
 948 +               count += 1 << fpp_order;
 949 +               pn++;
 950 +               pn &= m_pn;
 951 +       }
 952 +
 953 +       wmb();
 954 +       writew(pn << fpp_order, rwptr_reg+2);
 955 +
 956 +       spin_unlock_irqrestore(&toe->freeq_lock, flags);
 957 +       return count;
 958 +}
 959 +
 960 +static int toe_setup_freeq(struct toe_private *toe)
 961 +{
 962 +       void __iomem *dma_reg = toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG;
 963 +       QUEUE_THRESHOLD_T qt;
 964 +       DMA_SKB_SIZE_T skbsz;
 965 +       unsigned int filled;
 966 +       unsigned int frag_len = 1 << toe->freeq_frag_order;
 967 +       unsigned int len = 1 << toe->freeq_order;
 968 +       unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order;
 969 +       unsigned int pages = len >> fpp_order;
 970 +       dma_addr_t mapping;
 971 +       unsigned int pn;
 972 +
 973 +       toe->freeq_ring = dma_alloc_coherent(toe->dev,
 974 +               sizeof(*toe->freeq_ring) << toe->freeq_order,
 975 +               &toe->freeq_dma_base, GFP_KERNEL);
 976 +       if (!toe->freeq_ring)
 977 +               return -ENOMEM;
 978 +
 979 +       BUG_ON(toe->freeq_dma_base & ~DMA_Q_BASE_MASK);
 980 +
 981 +       toe->freeq_page_tab = kzalloc(pages * sizeof(*toe->freeq_page_tab),
 982 +                                                       GFP_KERNEL);
 983 +       if (!toe->freeq_page_tab)
 984 +               goto err_freeq;
 985 +
 986 +       for (pn = 0; pn < pages; pn++)
 987 +               if (!toe_freeq_alloc_map_page(toe, pn))
 988 +                       goto err_freeq_alloc;
 989 +
 990 +       filled = toe_fill_freeq(toe, 1);
 991 +       if (!filled)
 992 +               goto err_freeq_alloc;
 993 +
 994 +       qt.bits32 = readl(toe->iomem + GLOBAL_QUEUE_THRESHOLD_REG);
 995 +       qt.bits.swfq_empty = 32;
 996 +       writel(qt.bits32, toe->iomem + GLOBAL_QUEUE_THRESHOLD_REG);
 997 +
 998 +       skbsz.bits.sw_skb_size = 1 << toe->freeq_frag_order;
 999 +       writel(skbsz.bits32, toe->iomem + GLOBAL_DMA_SKB_SIZE_REG);
1000 +       writel(toe->freeq_dma_base | toe->freeq_order, dma_reg);
1001 +
1002 +       return 0;
1003 +
1004 +err_freeq_alloc:
1005 +       while (pn > 0) {
1006 +               --pn;
1007 +               mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr;
1008 +               dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE);
1009 +               put_page(toe->freeq_page_tab[pn]);
1010 +       }
1011 +
1012 +err_freeq:
1013 +       dma_free_coherent(toe->dev,
1014 +               sizeof(*toe->freeq_ring) << toe->freeq_order,
1015 +               toe->freeq_ring, toe->freeq_dma_base);
1016 +       toe->freeq_ring = NULL;
1017 +       return -ENOMEM;
1018 +}
1019 +
1020 +static void toe_cleanup_freeq(struct toe_private *toe)
1021 +{
1022 +       void __iomem *dma_reg = toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG;
1023 +       void __iomem *ptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG;
1024 +
1025 +       unsigned int frag_len = 1 << toe->freeq_frag_order;
1026 +       unsigned int len = 1 << toe->freeq_order;
1027 +       unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order;
1028 +       unsigned int pages = len >> fpp_order;
1029 +       struct page *page;
1030 +       dma_addr_t mapping;
1031 +       unsigned int pn;
1032 +
1033 +       writew(readw(ptr_reg), ptr_reg + 2);
1034 +       writel(0, dma_reg);
1035 +
1036 +       for (pn = 0; pn < pages; pn++) {
1037 +               mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr;
1038 +               dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE);
1039 +
1040 +               page = toe->freeq_page_tab[pn];
1041 +               while (atomic_read(&page->_count) > 0)
1042 +                       put_page(page);
1043 +       }
1044 +
1045 +       kfree(toe->freeq_page_tab);
1046 +
1047 +       dma_free_coherent(toe->dev,
1048 +               sizeof(*toe->freeq_ring) << toe->freeq_order,
1049 +               toe->freeq_ring, toe->freeq_dma_base);
1050 +}
1051 +
1052 +static int toe_resize_freeq(struct toe_private *toe, int changing_dev_id)
1053 +{
1054 +       void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG;
1055 +       struct gmac_private *gmac;
1056 +       struct net_device *other = toe->netdev[1 - changing_dev_id];
1057 +       unsigned new_size = 0;
1058 +       unsigned new_order;
1059 +       int err;
1060 +       unsigned long flags;
1061 +       unsigned en;
1062 +
1063 +       if (other && netif_running(other))
1064 +               return -EBUSY;
1065 +
1066 +       if (toe->netdev[0]) {
1067 +               gmac = netdev_priv(toe->netdev[0]);
1068 +               new_size  = 1 << (gmac->rxq_order + 1);
1069 +       }
1070 +
1071 +       if (toe->netdev[1]) {
1072 +               gmac = netdev_priv(toe->netdev[1]);
1073 +               new_size  += 1 << (gmac->rxq_order + 1);
1074 +       }
1075 +
1076 +       new_order = min(15, ilog2(new_size - 1) + 1);
1077 +       if (toe->freeq_order == new_order)
1078 +               return 0;
1079 +
1080 +       spin_lock_irqsave(&toe->irq_lock, flags);
1081 +       en = readl(irqen_reg);
1082 +       en &= ~SWFQ_EMPTY_INT_BIT;
1083 +       writel(en, irqen_reg);
1084 +
1085 +       if (toe->freeq_ring)
1086 +               toe_cleanup_freeq(toe);
1087 +
1088 +       toe->freeq_order = new_order;
1089 +       err = toe_setup_freeq(toe);
1090 +
1091 +       en |= SWFQ_EMPTY_INT_BIT;
1092 +       writel(en, irqen_reg);
1093 +       spin_unlock_irqrestore(&toe->irq_lock, flags);
1094 +
1095 +       return err;
1096 +}
1097 +
1098 +static void gmac_tx_irq_enable(struct net_device *dev, unsigned txq, int en)
1099 +{
1100 +       struct gmac_private *gmac = netdev_priv(dev);
1101 +       struct toe_private *toe = gmac->toe;
1102 +       unsigned val, mask;
1103 +
1104 +       mask = GMAC0_IRQ0_TXQ0_INTS << (6 * dev->dev_id + txq);
1105 +
1106 +       if (en)
1107 +               writel(mask, toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG);
1108 +
1109 +       val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
1110 +       val = en ? val | mask : val & ~mask;
1111 +       writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
1112 +}
1113 +
1114 +
1115 +static void gmac_tx_irq(struct net_device *dev, unsigned txq_num)
1116 +{
1117 +       struct netdev_queue *ntxq = netdev_get_tx_queue(dev, txq_num);
1118 +
1119 +       gmac_tx_irq_enable(dev, txq_num, 0);
1120 +       netif_tx_wake_queue(ntxq);
1121 +}
1122 +
1123 +static int gmac_map_tx_bufs(struct net_device *dev, struct sk_buff *skb,
1124 +                           struct gmac_txq *txq, unsigned short *desc)
1125 +{
1126 +       struct gmac_private *gmac = netdev_priv(dev);
1127 +       struct toe_private *toe = gmac->toe;
1128 +       struct skb_shared_info *skb_si =  skb_shinfo(skb);
1129 +       skb_frag_t *skb_frag;
1130 +       short frag, last_frag = skb_si->nr_frags - 1;
1131 +       unsigned short m = (1 << gmac->txq_order) -1;
1132 +       unsigned short w = *desc;
1133 +       unsigned word1, word3, buflen;
1134 +       dma_addr_t mapping;
1135 +       void *buffer;
1136 +       unsigned short mtu;
1137 +       GMAC_TXDESC_T *txd;
1138 +
1139 +       mtu  = ETH_HLEN;
1140 +       mtu += dev->mtu;
1141 +       if (skb->protocol == htons(ETH_P_8021Q))
1142 +               mtu += VLAN_HLEN;
1143 +
1144 +       word1 = skb->len;
1145 +       word3 = SOF_BIT;
1146 +
1147 +       if (word1 > mtu) {
1148 +               word1 |= TSS_MTU_ENABLE_BIT;
1149 +               word3 += mtu;
1150 +       }
1151 +
1152 +       if (skb->ip_summed != CHECKSUM_NONE) {
1153 +               int tcp = 0;
1154 +               if (skb->protocol == htons(ETH_P_IP)) {
1155 +                       word1 |= TSS_IP_CHKSUM_BIT;
1156 +                       tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
1157 +               } else { /* IPv6 */
1158 +                       word1 |= TSS_IPV6_ENABLE_BIT;
1159 +                       tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
1160 +               }
1161 +
1162 +               word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
1163 +       }
1164 +
1165 +       frag = -1;
1166 +       while (frag <= last_frag) {
1167 +               if (frag == -1) {
1168 +                       buffer = skb->data;
1169 +                       buflen = skb_headlen(skb);
1170 +               } else {
1171 +                       skb_frag = skb_si->frags + frag;
1172 +                       buffer = page_address(skb_frag_page(skb_frag)) +
1173 +                                skb_frag->page_offset;
1174 +                       buflen = skb_frag->size;
1175 +               }
1176 +
1177 +               if (frag == last_frag) {
1178 +                       word3 |= EOF_BIT;
1179 +                       txq->skb[w] = skb;
1180 +               }
1181 +
1182 +               mapping = dma_map_single(toe->dev, buffer, buflen,
1183 +                                       DMA_TO_DEVICE);
1184 +               if (dma_mapping_error(toe->dev, mapping) ||
1185 +                       !(mapping & PAGE_MASK))
1186 +                       goto map_error;
1187 +
1188 +               txd = txq->ring + w;
1189 +               txd->word0.bits32 = buflen;
1190 +               txd->word1.bits32 = word1;
1191 +               txd->word2.buf_adr = mapping;
1192 +               txd->word3.bits32 = word3;
1193 +
1194 +               word3 &= MTU_SIZE_BIT_MASK;
1195 +               w++;
1196 +               w &= m;
1197 +               frag++;
1198 +       }
1199 +
1200 +       *desc = w;
1201 +       return 0;
1202 +
1203 +map_error:
1204 +       while (w != *desc) {
1205 +               w--;
1206 +               w &= m;
1207 +
1208 +               dma_unmap_page(toe->dev, txq->ring[w].word2.buf_adr,
1209 +                       txq->ring[w].word0.bits.buffer_size, DMA_TO_DEVICE);
1210 +       }
1211 +       return ENOMEM;
1212 +}
1213 +
1214 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
1215 +{
1216 +       struct gmac_private *gmac = netdev_priv(dev);
1217 +
1218 +       void __iomem *ptr_reg;
1219 +       struct gmac_txq *txq;
1220 +       struct netdev_queue *ntxq;
1221 +       int txq_num, nfrags;
1222 +       DMA_RWPTR_T rw;
1223 +       unsigned short r, w, d;
1224 +       unsigned short m = (1 << gmac->txq_order) - 1;
1225 +
1226 +       SKB_FRAG_ASSERT(skb);
1227 +
1228 +       if (unlikely(skb->len >= 0x10000))
1229 +               goto out_drop_free;
1230 +
1231 +               txq_num = skb_get_queue_mapping(skb);
1232 +       ptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
1233 +       txq = &gmac->txq[txq_num];
1234 +       ntxq = netdev_get_tx_queue(dev, txq_num);
1235 +       nfrags = skb_shinfo(skb)->nr_frags;
1236 +
1237 +       rw.bits32 = readl(ptr_reg);
1238 +       r = rw.bits.rptr;
1239 +       w = rw.bits.wptr;
1240 +
1241 +       d = txq->cptr - w - 1;
1242 +       d &= m;
1243 +
1244 +       if (unlikely(d < nfrags+2))
1245 +       {
1246 +               gmac_clean_txq(dev, txq, r);
1247 +               d = txq->cptr - w - 1;
1248 +               d &= m;
1249 +
1250 +               if (unlikely(d < nfrags+2)) {
1251 +                       netif_tx_stop_queue(ntxq);
1252 +
1253 +                       d = txq->cptr + nfrags + 16;
1254 +                       d &= m;
1255 +                       txq->ring[d].word3.bits.eofie = 1;
1256 +                       gmac_tx_irq_enable(dev, txq_num, 1);
1257 +
1258 +                       u64_stats_update_begin(&gmac->tx_stats_syncp);
1259 +                       dev->stats.tx_fifo_errors++;
1260 +                       u64_stats_update_end(&gmac->tx_stats_syncp);
1261 +                       return NETDEV_TX_BUSY;
1262 +               }
1263 +       }
1264 +
1265 +       if (unlikely(gmac_map_tx_bufs(dev, skb, txq, &w))) {
1266 +               if (skb_linearize(skb))
1267 +                       goto out_drop;
1268 +
1269 +               if (unlikely(gmac_map_tx_bufs(dev, skb, txq, &w)))
1270 +                       goto out_drop_free;
1271 +
1272 +               u64_stats_update_begin(&gmac->tx_stats_syncp);
1273 +               gmac->tx_frags_linearized++;
1274 +               u64_stats_update_end(&gmac->tx_stats_syncp);
1275 +       }
1276 +
1277 +       writew(w, ptr_reg+2);
1278 +
1279 +       gmac_clean_txq(dev, txq, r);
1280 +       return NETDEV_TX_OK;
1281 +
1282 +out_drop_free:
1283 +       dev_kfree_skb(skb);
1284 +out_drop:
1285 +       u64_stats_update_begin(&gmac->tx_stats_syncp);
1286 +       gmac->stats.tx_dropped++;
1287 +       u64_stats_update_end(&gmac->tx_stats_syncp);
1288 +       return NETDEV_TX_OK;
1289 +}
1290 +
1291 +static void gmac_tx_timeout(struct net_device *dev)
1292 +{
1293 +       netdev_err(dev, "Tx timeout\n");
1294 +       gmac_dump_dma_state(dev);
1295 +}
1296 +
1297 +static void gmac_enable_irq(struct net_device *dev, int enable)
1298 +{
1299 +       struct gmac_private *gmac = netdev_priv(dev);
1300 +       struct toe_private *toe = gmac->toe;
1301 +       unsigned long flags;
1302 +       unsigned val, mask;
1303 +
1304 +       spin_lock_irqsave(&toe->irq_lock, flags);
1305 +
1306 +       mask = GMAC0_IRQ0_2 << (dev->dev_id * 2);
1307 +       val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
1308 +       val = enable ? (val | mask) : (val & ~mask);
1309 +       writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
1310 +
1311 +       mask = DEFAULT_Q0_INT_BIT << dev->dev_id;
1312 +       val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
1313 +       val = enable ? (val | mask) : (val & ~mask);
1314 +       writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
1315 +
1316 +       mask = GMAC0_IRQ4_8 << (dev->dev_id * 8);
1317 +       val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG);
1318 +       val = enable ? (val | mask) : (val & ~mask);
1319 +       writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG);
1320 +
1321 +       spin_unlock_irqrestore(&toe->irq_lock, flags);
1322 +}
1323 +
1324 +static void gmac_enable_rx_irq(struct net_device *dev, int enable)
1325 +{
1326 +       struct gmac_private *gmac = netdev_priv(dev);
1327 +       struct toe_private *toe = gmac->toe;
1328 +       unsigned long flags;
1329 +       unsigned val, mask;
1330 +
1331 +       spin_lock_irqsave(&toe->irq_lock, flags);
1332 +       mask = DEFAULT_Q0_INT_BIT << dev->dev_id;
1333 +
1334 +       val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
1335 +       val = enable ? (val | mask) : (val & ~mask);
1336 +       writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
1337 +
1338 +       spin_unlock_irqrestore(&toe->irq_lock, flags);
1339 +}
1340 +
1341 +static struct sk_buff *gmac_skb_if_good_frame(struct gmac_private *gmac,
1342 +       GMAC_RXDESC_0_T word0, unsigned frame_len)
1343 +{
1344 +       struct sk_buff *skb = NULL;
1345 +       unsigned rx_status = word0.bits.status;
1346 +       unsigned rx_csum = word0.bits.chksum_status;
1347 +
1348 +       gmac->rx_stats[rx_status]++;
1349 +       gmac->rx_csum_stats[rx_csum]++;
1350 +
1351 +       if (word0.bits.derr || word0.bits.perr ||
1352 +           rx_status || frame_len < ETH_ZLEN ||
1353 +           rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
1354 +               gmac->stats.rx_errors++;
1355 +
1356 +               if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
1357 +                       gmac->stats.rx_length_errors++;
1358 +               if (RX_ERROR_OVER(rx_status))
1359 +                       gmac->stats.rx_over_errors++;
1360 +               if (RX_ERROR_CRC(rx_status))
1361 +                       gmac->stats.rx_crc_errors++;
1362 +               if (RX_ERROR_FRAME(rx_status))
1363 +                       gmac->stats.rx_frame_errors++;
1364 +
1365 +               return NULL;
1366 +       }
1367 +
1368 +       skb = napi_get_frags(&gmac->napi);
1369 +       if (!skb)
1370 +               return NULL;
1371 +
1372 +       if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
1373 +               skb->ip_summed = CHECKSUM_UNNECESSARY;
1374 +
1375 +       gmac->stats.rx_bytes += frame_len;
1376 +       gmac->stats.rx_packets++;
1377 +       return skb;
1378 +}
1379 +
1380 +static unsigned gmac_rx(struct net_device *dev, unsigned budget)
1381 +{
1382 +       struct gmac_private *gmac = netdev_priv(dev);
1383 +       struct toe_private *toe = gmac->toe;
1384 +       void __iomem *ptr_reg = gmac->rxq_rwptr;
1385 +
1386 +       static struct sk_buff *skb;
1387 +
1388 +       DMA_RWPTR_T rw;
1389 +       unsigned short r, w;
1390 +       unsigned short m = (1 << gmac->rxq_order) -1;
1391 +       GMAC_RXDESC_T *rx = NULL;
1392 +       struct page* page = NULL;
1393 +       unsigned page_offs;
1394 +       unsigned int frame_len, frag_len;
1395 +       int frag_nr = 0;
1396 +
1397 +       GMAC_RXDESC_0_T word0;
1398 +       GMAC_RXDESC_1_T word1;
1399 +       dma_addr_t mapping;
1400 +       GMAC_RXDESC_3_T word3;
1401 +
1402 +       rw.bits32 = readl(ptr_reg);
1403 +       /* Reset interrupt as all packages until here are taken into account */
1404 +       writel(DEFAULT_Q0_INT_BIT << dev->dev_id,
1405 +               toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG);
1406 +       r = rw.bits.rptr;
1407 +       w = rw.bits.wptr;
1408 +
1409 +       while (budget && w != r) {
1410 +               rx = gmac->rxq_ring + r;
1411 +               word0 = rx->word0;
1412 +               word1 = rx->word1;
1413 +               mapping = rx->word2.buf_adr;
1414 +               word3 = rx->word3;
1415 +
1416 +               r++;
1417 +               r &= m;
1418 +
1419 +               frag_len = word0.bits.buffer_size;
1420 +               frame_len =word1.bits.byte_count;
1421 +               page_offs = mapping & ~PAGE_MASK;
1422 +
1423 +               if (unlikely(!mapping)) {
1424 +                       netdev_err(dev, "rxq[%u]: HW BUG: zero DMA desc\n", r);
1425 +                       goto err_drop;
1426 +               }
1427 +
1428 +               page = pfn_to_page(dma_to_pfn(toe->dev, mapping));
1429 +
1430 +               if (word3.bits32 & SOF_BIT) {
1431 +                       if (unlikely(skb)) {
1432 +                               napi_free_frags(&gmac->napi);
1433 +                               gmac->stats.rx_dropped++;
1434 +                       }
1435 +
1436 +                       skb = gmac_skb_if_good_frame(gmac, word0, frame_len);
1437 +                       if (unlikely(!skb))
1438 +                               goto err_drop;
1439 +
1440 +                       page_offs += NET_IP_ALIGN;
1441 +                       frag_len -= NET_IP_ALIGN;
1442 +                       frag_nr = 0;
1443 +
1444 +               } else if (!skb) {
1445 +                       put_page(page);
1446 +                       continue;
1447 +               }
1448 +
1449 +               if (word3.bits32 & EOF_BIT)
1450 +                       frag_len = frame_len - skb->len;
1451 +
1452 +               /* append page frag to skb */
1453 +               if (unlikely(frag_nr == MAX_SKB_FRAGS))
1454 +                       goto err_drop;
1455 +
1456 +               if (frag_len == 0)
1457 +                       netdev_err(dev, "Received fragment with len = 0\n");
1458 +
1459 +               skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
1460 +               skb->len += frag_len;
1461 +               skb->data_len += frag_len;
1462 +               skb->truesize += frag_len;
1463 +               frag_nr++;
1464 +
1465 +               if (word3.bits32 & EOF_BIT) {
1466 +                       napi_gro_frags(&gmac->napi);
1467 +                       skb = NULL;
1468 +                       --budget;
1469 +               }
1470 +               continue;
1471 +
1472 +err_drop:
1473 +               if (skb) {
1474 +                       napi_free_frags(&gmac->napi);
1475 +                       skb = NULL;
1476 +               }
1477 +
1478 +               if (mapping)
1479 +                       put_page(page);
1480 +
1481 +               gmac->stats.rx_dropped++;
1482 +       }
1483 +
1484 +       writew(r, ptr_reg);
1485 +       return budget;
1486 +}
1487 +
1488 +static int gmac_napi_poll(struct napi_struct *napi, int budget)
1489 +{
1490 +       struct gmac_private *gmac = netdev_priv(napi->dev);
1491 +       struct toe_private *toe = gmac->toe;
1492 +       unsigned rx;
1493 +       unsigned freeq_threshold = 1 << (toe->freeq_order - 1);
1494 +
1495 +       u64_stats_update_begin(&gmac->rx_stats_syncp);
1496 +
1497 +       rx = budget - gmac_rx(napi->dev, budget);
1498 +
1499 +       if (rx == 0) {
1500 +               napi_gro_flush(napi, false);
1501 +               __napi_complete(napi);
1502 +               gmac_enable_rx_irq(napi->dev, 1);
1503 +               ++gmac->rx_napi_exits;
1504 +       }
1505 +
1506 +       gmac->freeq_refill += rx;
1507 +       if (gmac->freeq_refill > freeq_threshold) {
1508 +               gmac->freeq_refill -= freeq_threshold;
1509 +               toe_fill_freeq(toe, 0);
1510 +       }
1511 +
1512 +       u64_stats_update_end(&gmac->rx_stats_syncp);
1513 +       return rx;
1514 +}
1515 +
1516 +static void gmac_dump_dma_state(struct net_device *dev)
1517 +{
1518 +       struct gmac_private *gmac = netdev_priv(dev);
1519 +       struct toe_private *toe = gmac->toe;
1520 +       void __iomem *ptr_reg;
1521 +       unsigned reg[5];
1522 +
1523 +       /* Interrupt status */
1524 +       reg[0] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG);
1525 +       reg[1] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG);
1526 +       reg[2] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_2_REG);
1527 +       reg[3] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_3_REG);
1528 +       reg[4] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG);
1529 +       netdev_err(dev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1530 +               reg[0], reg[1], reg[2], reg[3], reg[4]);
1531 +
1532 +       /* Interrupt enable */
1533 +       reg[0] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
1534 +       reg[1] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
1535 +       reg[2] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_2_REG);
1536 +       reg[3] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_3_REG);
1537 +       reg[4] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG);
1538 +       netdev_err(dev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1539 +               reg[0], reg[1], reg[2], reg[3], reg[4]);
1540 +
1541 +       /* RX DMA status */
1542 +       reg[0] = readl(gmac->dma_iomem + GMAC_DMA_RX_FIRST_DESC_REG);
1543 +       reg[1] = readl(gmac->dma_iomem + GMAC_DMA_RX_CURR_DESC_REG);
1544 +       reg[2] = GET_RPTR(gmac->rxq_rwptr);
1545 +       reg[3] = GET_WPTR(gmac->rxq_rwptr);
1546 +       netdev_err(dev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1547 +               reg[0], reg[1], reg[2], reg[3]);
1548 +
1549 +       reg[0] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD0_REG);
1550 +       reg[1] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD1_REG);
1551 +       reg[2] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD2_REG);
1552 +       reg[3] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD3_REG);
1553 +       netdev_err(dev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1554 +               reg[0], reg[1], reg[2], reg[3]);
1555 +
1556 +       /* TX DMA status */
1557 +       ptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG;
1558 +
1559 +       reg[0] = readl(gmac->dma_iomem + GMAC_DMA_TX_FIRST_DESC_REG);
1560 +       reg[1] = readl(gmac->dma_iomem + GMAC_DMA_TX_CURR_DESC_REG);
1561 +       reg[2] = GET_RPTR(ptr_reg);
1562 +       reg[3] = GET_WPTR(ptr_reg);
1563 +       netdev_err(dev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1564 +               reg[0], reg[1], reg[2], reg[3]);
1565 +
1566 +       reg[0] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD0_REG);
1567 +       reg[1] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD1_REG);
1568 +       reg[2] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD2_REG);
1569 +       reg[3] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD3_REG);
1570 +       netdev_err(dev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1571 +               reg[0], reg[1], reg[2], reg[3]);
1572 +
1573 +       /* FREE queues status */
1574 +       ptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG;
1575 +
1576 +       reg[0] = GET_RPTR(ptr_reg);
1577 +       reg[1] = GET_WPTR(ptr_reg);
1578 +
1579 +       ptr_reg = toe->iomem + GLOBAL_HWFQ_RWPTR_REG;
1580 +
1581 +       reg[2] = GET_RPTR(ptr_reg);
1582 +       reg[3] = GET_WPTR(ptr_reg);
1583 +       netdev_err(dev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
1584 +               reg[0], reg[1], reg[2], reg[3]);
1585 +}
1586 +
1587 +static void gmac_update_hw_stats(struct net_device *dev)
1588 +{
1589 +       struct gmac_private *gmac = netdev_priv(dev);
1590 +       struct toe_private *toe = gmac->toe;
1591 +       unsigned long flags;
1592 +       unsigned int rx_discards, rx_mcast, rx_bcast;
1593 +
1594 +       spin_lock_irqsave(&toe->irq_lock, flags);
1595 +       u64_stats_update_begin(&gmac->ir_stats_syncp);
1596 +
1597 +       gmac->hw_stats[0] += rx_discards = readl(gmac->ctl_iomem + GMAC_IN_DISCARDS);
1598 +       gmac->hw_stats[1] += readl(gmac->ctl_iomem + GMAC_IN_ERRORS);
1599 +       gmac->hw_stats[2] += rx_mcast = readl(gmac->ctl_iomem + GMAC_IN_MCAST);
1600 +       gmac->hw_stats[3] += rx_bcast = readl(gmac->ctl_iomem + GMAC_IN_BCAST);
1601 +       gmac->hw_stats[4] += readl(gmac->ctl_iomem + GMAC_IN_MAC1);
1602 +       gmac->hw_stats[5] += readl(gmac->ctl_iomem + GMAC_IN_MAC2);
1603 +
1604 +       gmac->stats.rx_missed_errors += rx_discards;
1605 +       gmac->stats.multicast += rx_mcast;
1606 +       gmac->stats.multicast += rx_bcast;
1607 +
1608 +       writel(GMAC0_MIB_INT_BIT << (dev->dev_id * 8),
1609 +               toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG);
1610 +
1611 +       u64_stats_update_end(&gmac->ir_stats_syncp);
1612 +       spin_unlock_irqrestore(&toe->irq_lock, flags);
1613 +}
1614 +
1615 +static inline unsigned gmac_get_intr_flags(struct net_device *dev, int i)
1616 +{
1617 +       struct gmac_private *gmac = netdev_priv(dev);
1618 +       struct toe_private *toe = gmac->toe;
1619 +       void __iomem *irqif_reg, *irqen_reg;
1620 +       unsigned offs, val;
1621 +
1622 +       offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG - GLOBAL_INTERRUPT_STATUS_0_REG);
1623 +
1624 +       irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
1625 +       irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;
1626 +
1627 +       val = readl(irqif_reg) & readl(irqen_reg);
1628 +       return val;
1629 +}
1630 +
1631 +enum hrtimer_restart gmac_coalesce_delay_expired( struct hrtimer *timer )
1632 +{
1633 +       struct gmac_private *gmac = container_of(timer, struct gmac_private, rx_coalesce_timer);
1634 +
1635 +       napi_schedule(&gmac->napi);
1636 +       return HRTIMER_NORESTART;
1637 +}
1638 +
1639 +static irqreturn_t gmac_irq(int irq, void *data)
1640 +{
1641 +       struct net_device *dev = data;
1642 +       struct gmac_private *gmac = netdev_priv(dev);
1643 +       struct toe_private *toe = gmac->toe;
1644 +       unsigned val, orr = 0;
1645 +
1646 +       orr |= val = gmac_get_intr_flags(dev, 0);
1647 +
1648 +       if (unlikely(val & (GMAC0_IRQ0_2 << (dev->dev_id * 2)))) {
1649 +               /* oh, crap. */
1650 +               netdev_err(dev, "hw failure/sw bug\n");
1651 +               gmac_dump_dma_state(dev);
1652 +
1653 +               /* don't know how to recover, just reduce losses */
1654 +               gmac_enable_irq(dev, 0);
1655 +               return IRQ_HANDLED;
1656 +       }
1657 +
1658 +       if (val & (GMAC0_IRQ0_TXQ0_INTS << (dev->dev_id * 6)))
1659 +               gmac_tx_irq(dev, 0);
1660 +
1661 +       orr |= val = gmac_get_intr_flags(dev, 1);
1662 +
1663 +       if (val & (DEFAULT_Q0_INT_BIT << dev->dev_id)) {
1664 +
1665 +               gmac_enable_rx_irq(dev, 0);
1666 +
1667 +               if (!gmac->rx_coalesce_nsecs)
1668 +                       napi_schedule(&gmac->napi);
1669 +               else {
1670 +                       ktime_t ktime;
1671 +                       ktime = ktime_set(0, gmac->rx_coalesce_nsecs);
1672 +                       hrtimer_start(&gmac->rx_coalesce_timer, ktime, HRTIMER_MODE_REL);
1673 +               }
1674 +       }
1675 +
1676 +       orr |= val = gmac_get_intr_flags(dev, 4);
1677 +
1678 +       if (unlikely(val & (GMAC0_MIB_INT_BIT << (dev->dev_id * 8))))
1679 +               gmac_update_hw_stats(dev);
1680 +
1681 +       if (unlikely(val & (GMAC0_RX_OVERRUN_INT_BIT << (dev->dev_id * 8)))) {
1682 +               writel(GMAC0_RXDERR_INT_BIT << (dev->dev_id * 8),
1683 +                       toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG);
1684 +
1685 +               spin_lock(&toe->irq_lock);
1686 +               u64_stats_update_begin(&gmac->ir_stats_syncp);
1687 +               ++gmac->stats.rx_fifo_errors;
1688 +               u64_stats_update_end(&gmac->ir_stats_syncp);
1689 +               spin_unlock(&toe->irq_lock);
1690 +       }
1691 +
1692 +       return orr ? IRQ_HANDLED : IRQ_NONE;
1693 +}
1694 +
1695 +static void gmac_start_dma(struct gmac_private *gmac)
1696 +{
1697 +       void __iomem *dma_ctrl_reg = gmac->dma_iomem + GMAC_DMA_CTRL_REG;
1698 +       GMAC_DMA_CTRL_T dma_ctrl;
1699 +
1700 +       dma_ctrl.bits32 = readl(dma_ctrl_reg);
1701 +       dma_ctrl.bits.rd_enable = 1;
1702 +       dma_ctrl.bits.td_enable = 1;
1703 +       dma_ctrl.bits.loopback = 0;
1704 +       dma_ctrl.bits.drop_small_ack = 0;
1705 +       dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
1706 +       dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
1707 +       dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
1708 +       dma_ctrl.bits.rd_bus = HSIZE_8;
1709 +       dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
1710 +       dma_ctrl.bits.td_burst_size = HBURST_INCR8;
1711 +       dma_ctrl.bits.td_bus = HSIZE_8;
1712 +
1713 +       writel(dma_ctrl.bits32, dma_ctrl_reg);
1714 +}
1715 +
1716 +static void gmac_stop_dma(struct gmac_private *gmac)
1717 +{
1718 +       void __iomem *dma_ctrl_reg = gmac->dma_iomem + GMAC_DMA_CTRL_REG;
1719 +       GMAC_DMA_CTRL_T dma_ctrl;
1720 +
1721 +       dma_ctrl.bits32 = readl(dma_ctrl_reg);
1722 +       dma_ctrl.bits.rd_enable = 0;
1723 +       dma_ctrl.bits.td_enable = 0;
1724 +       writel(dma_ctrl.bits32, dma_ctrl_reg);
1725 +}
1726 +
1727 +static int gmac_open(struct net_device *dev)
1728 +{
1729 +       struct gmac_private *gmac = netdev_priv(dev);
1730 +       int err;
1731 +
1732 +       if (!dev->phydev) {
1733 +               err = gmac_setup_phy(dev);
1734 +               if (err) {
1735 +                       netif_err(gmac, ifup, dev,
1736 +                               "PHY init failed: %d\n", err);
1737 +                       return err;
1738 +               }
1739 +       }
1740 +
1741 +       err = request_irq(dev->irq, gmac_irq,
1742 +               IRQF_SHARED, dev->name, dev);
1743 +       if (unlikely(err))
1744 +               return err;
1745 +
1746 +       netif_carrier_off(dev);
1747 +       phy_start(dev->phydev);
1748 +
1749 +       err = toe_resize_freeq(gmac->toe, dev->dev_id);
1750 +       if (unlikely(err))
1751 +               goto err_stop_phy;
1752 +
1753 +       err = gmac_setup_rxq(dev);
1754 +       if (unlikely(err))
1755 +               goto err_stop_phy;
1756 +
1757 +       err = gmac_setup_txqs(dev);
1758 +       if (unlikely(err)) {
1759 +               gmac_cleanup_rxq(dev);
1760 +               goto err_stop_phy;
1761 +       }
1762 +
1763 +       napi_enable(&gmac->napi);
1764 +
1765 +       gmac_start_dma(gmac);
1766 +       gmac_enable_irq(dev, 1);
1767 +       gmac_enable_tx_rx(dev);
1768 +       netif_tx_start_all_queues(dev);
1769 +
1770 +       hrtimer_init(&gmac->rx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1771 +       gmac->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;
1772 +       return 0;
1773 +
1774 +err_stop_phy:
1775 +       phy_stop(dev->phydev);
1776 +       free_irq(dev->irq, dev);
1777 +       return err;
1778 +}
1779 +
1780 +static int gmac_stop(struct net_device *dev)
1781 +{
1782 +       struct gmac_private *gmac = netdev_priv(dev);
1783 +
1784 +       hrtimer_cancel(&gmac->rx_coalesce_timer);
1785 +       netif_tx_stop_all_queues(dev);
1786 +       gmac_disable_tx_rx(dev);
1787 +       gmac_stop_dma(gmac);
1788 +       napi_disable(&gmac->napi);
1789 +
1790 +       gmac_enable_irq(dev, 0);
1791 +       gmac_cleanup_rxq(dev);
1792 +       gmac_cleanup_txqs(dev);
1793 +
1794 +       phy_stop(dev->phydev);
1795 +       free_irq(dev->irq, dev);
1796 +
1797 +       gmac_update_hw_stats(dev);
1798 +       return 0;
1799 +}
1800 +
1801 +static void gmac_set_rx_mode(struct net_device *dev)
1802 +{
1803 +       struct gmac_private *gmac = netdev_priv(dev);
1804 +       struct netdev_hw_addr *ha;
1805 +       __u32 mc_filter[2];
1806 +       unsigned bit_nr;
1807 +       GMAC_RX_FLTR_T filter = { .bits = {
1808 +               .broadcast = 1,
1809 +               .multicast = 1,
1810 +               .unicast = 1,
1811 +       } };
1812 +
1813 +       mc_filter[1] = mc_filter[0] = 0;
1814 +
1815 +       if (dev->flags & IFF_PROMISC) {
1816 +               filter.bits.error = 1;
1817 +               filter.bits.promiscuous = 1;
1818 +       } else if (!(dev->flags & IFF_ALLMULTI)) {
1819 +               mc_filter[1] = mc_filter[0] = 0;
1820 +               netdev_for_each_mc_addr(ha, dev) {
1821 +                       bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
1822 +                       mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
1823 +               }
1824 +       }
1825 +
1826 +       writel(mc_filter[0], gmac->ctl_iomem + GMAC_MCAST_FIL0);
1827 +       writel(mc_filter[1], gmac->ctl_iomem + GMAC_MCAST_FIL1);
1828 +       writel(filter.bits32, gmac->ctl_iomem + GMAC_RX_FLTR);
1829 +}
1830 +
1831 +static void __gmac_set_mac_address(struct net_device *dev)
1832 +{
1833 +       struct gmac_private *gmac = netdev_priv(dev);
1834 +       __le32 addr[3];
1835 +
1836 +       memset(addr, 0, sizeof(addr));
1837 +       memcpy(addr, dev->dev_addr, ETH_ALEN);
1838 +
1839 +       writel(le32_to_cpu(addr[0]), gmac->ctl_iomem + GMAC_STA_ADD0);
1840 +       writel(le32_to_cpu(addr[1]), gmac->ctl_iomem + GMAC_STA_ADD1);
1841 +       writel(le32_to_cpu(addr[2]), gmac->ctl_iomem + GMAC_STA_ADD2);
1842 +}
1843 +
1844 +static int gmac_set_mac_address(struct net_device *dev, void *addr)
1845 +{
1846 +       struct sockaddr *sa = addr;
1847 +
1848 +       memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1849 +       __gmac_set_mac_address(dev);
1850 +
1851 +       return 0;
1852 +}
1853 +
1854 +static void gmac_clear_hw_stats(struct net_device *dev)
1855 +{
1856 +       struct gmac_private *gmac = netdev_priv(dev);
1857 +
1858 +       readl(gmac->ctl_iomem + GMAC_IN_DISCARDS);
1859 +       readl(gmac->ctl_iomem + GMAC_IN_ERRORS);
1860 +       readl(gmac->ctl_iomem + GMAC_IN_MCAST);
1861 +       readl(gmac->ctl_iomem + GMAC_IN_BCAST);
1862 +       readl(gmac->ctl_iomem + GMAC_IN_MAC1);
1863 +       readl(gmac->ctl_iomem + GMAC_IN_MAC2);
1864 +}
1865 +
1866 +static struct rtnl_link_stats64 *gmac_get_stats64(struct net_device *dev,
1867 +       struct rtnl_link_stats64 *storage)
1868 +{
1869 +       struct gmac_private *gmac = netdev_priv(dev);
1870 +       unsigned int start;
1871 +
1872 +       gmac_update_hw_stats(dev);
1873 +
1874 +       /* racing with RX NAPI */
1875 +       do {
1876 +               start = u64_stats_fetch_begin(&gmac->rx_stats_syncp);
1877 +
1878 +               storage->rx_packets = gmac->stats.rx_packets;
1879 +               storage->rx_bytes = gmac->stats.rx_bytes;
1880 +               storage->rx_errors = gmac->stats.rx_errors;
1881 +               storage->rx_dropped = gmac->stats.rx_dropped;
1882 +
1883 +               storage->rx_length_errors = gmac->stats.rx_length_errors;
1884 +               storage->rx_over_errors = gmac->stats.rx_over_errors;
1885 +               storage->rx_crc_errors = gmac->stats.rx_crc_errors;
1886 +               storage->rx_frame_errors = gmac->stats.rx_frame_errors;
1887 +
1888 +       } while (u64_stats_fetch_retry(&gmac->rx_stats_syncp, start));
1889 +
1890 +       /* racing with MIB and TX completion interrupts */
1891 +       do {
1892 +               start = u64_stats_fetch_begin(&gmac->ir_stats_syncp);
1893 +
1894 +               storage->tx_errors = gmac->stats.tx_errors;
1895 +               storage->tx_packets = gmac->stats.tx_packets;
1896 +               storage->tx_bytes = gmac->stats.tx_bytes;
1897 +
1898 +               storage->multicast = gmac->stats.multicast;
1899 +               storage->rx_missed_errors = gmac->stats.rx_missed_errors;
1900 +               storage->rx_fifo_errors = gmac->stats.rx_fifo_errors;
1901 +
1902 +       } while (u64_stats_fetch_retry(&gmac->ir_stats_syncp, start));
1903 +
1904 +       /* racing with hard_start_xmit */
1905 +       do {
1906 +               start = u64_stats_fetch_begin(&gmac->tx_stats_syncp);
1907 +
1908 +               storage->tx_dropped = gmac->stats.tx_dropped;
1909 +
1910 +       } while (u64_stats_fetch_retry(&gmac->tx_stats_syncp, start));
1911 +
1912 +       storage->rx_dropped += storage->rx_missed_errors;
1913 +
1914 +       return storage;
1915 +}
1916 +
1917 +static int gmac_change_mtu(struct net_device *dev, int new_mtu)
1918 +{
1919 +       int max_len = gmac_pick_rx_max_len(new_mtu);
1920 +
1921 +       if (max_len < 0)
1922 +               return -EINVAL;
1923 +
1924 +       gmac_disable_tx_rx(dev);
1925 +
1926 +       dev->mtu = new_mtu;
1927 +       gmac_update_config0_reg(dev,
1928 +               max_len << CONFIG0_MAXLEN_SHIFT,
1929 +               CONFIG0_MAXLEN_MASK);
1930 +
1931 +       netdev_update_features(dev);
1932 +
1933 +       gmac_enable_tx_rx(dev);
1934 +
1935 +       return 0;
1936 +}
1937 +
1938 +static netdev_features_t gmac_fix_features(struct net_device *dev, netdev_features_t features)
1939 +{
1940 +       if (dev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK)
1941 +               features &= ~GMAC_OFFLOAD_FEATURES;
1942 +
1943 +       return features;
1944 +}
1945 +
1946 +static int gmac_set_features(struct net_device *dev, netdev_features_t features)
1947 +{
1948 +       struct gmac_private *gmac = netdev_priv(dev);
1949 +       int enable = features & NETIF_F_RXCSUM;
1950 +       unsigned long flags;
1951 +       u32 reg;
1952 +
1953 +       spin_lock_irqsave(&gmac->config_lock, flags);
1954 +
1955 +       reg = readl(gmac->ctl_iomem + GMAC_CONFIG0);
1956 +       reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
1957 +       writel(reg, gmac->ctl_iomem + GMAC_CONFIG0);
1958 +
1959 +       spin_unlock_irqrestore(&gmac->config_lock, flags);
1960 +       return 0;
1961 +}
1962 +
1963 +static int gmac_get_sset_count(struct net_device *dev, int sset)
1964 +{
1965 +       return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
1966 +}
1967 +
1968 +static void gmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1969 +{
1970 +       if (stringset != ETH_SS_STATS)
1971 +               return;
1972 +
1973 +       memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
1974 +}
1975 +
1976 +static void gmac_get_ethtool_stats(struct net_device *dev,
1977 +       struct ethtool_stats *estats, u64 *values)
1978 +{
1979 +       struct gmac_private *gmac = netdev_priv(dev);
1980 +       unsigned int start;
1981 +       u64 *p;
1982 +       int i;
1983 +
1984 +       gmac_update_hw_stats(dev);
1985 +
1986 +       /* racing with MIB interrupt */
1987 +       do {
1988 +               p = values;
1989 +               start = u64_stats_fetch_begin(&gmac->ir_stats_syncp);
1990 +
1991 +               for (i = 0; i < RX_STATS_NUM; ++i)
1992 +                       *p++ = gmac->hw_stats[i];
1993 +
1994 +       } while (u64_stats_fetch_retry(&gmac->ir_stats_syncp, start));
1995 +       values = p;
1996 +
1997 +       /* racing with RX NAPI */
1998 +       do {
1999 +               p = values;
2000 +               start = u64_stats_fetch_begin(&gmac->rx_stats_syncp);
2001 +
2002 +               for (i = 0; i < RX_STATUS_NUM; ++i)
2003 +                       *p++ = gmac->rx_stats[i];
2004 +               for (i = 0; i < RX_CHKSUM_NUM; ++i)
2005 +                       *p++ = gmac->rx_csum_stats[i];
2006 +               *p++ = gmac->rx_napi_exits;
2007 +
2008 +       } while (u64_stats_fetch_retry(&gmac->rx_stats_syncp, start));
2009 +       values = p;
2010 +
2011 +       /* racing with TX start_xmit */
2012 +       do {
2013 +               p = values;
2014 +               start = u64_stats_fetch_begin(&gmac->tx_stats_syncp);
2015 +
2016 +               for (i = 0; i < TX_MAX_FRAGS; ++i) {
2017 +                       *values++ = gmac->tx_frag_stats[i];
2018 +                       gmac->tx_frag_stats[i] = 0;
2019 +               }
2020 +               *values++ = gmac->tx_frags_linearized;
2021 +               *values++ = gmac->tx_hw_csummed;
2022 +
2023 +       } while (u64_stats_fetch_retry(&gmac->tx_stats_syncp, start));
2024 +}
2025 +
2026 +static int gmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2027 +{
2028 +       if (!dev->phydev)
2029 +               return -ENXIO;
2030 +       return phy_ethtool_gset(dev->phydev, cmd);
2031 +}
2032 +
2033 +static int gmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2034 +{
2035 +       if (!dev->phydev)
2036 +               return -ENXIO;
2037 +       return phy_ethtool_sset(dev->phydev, cmd);
2038 +}
2039 +
2040 +static int gmac_nway_reset(struct net_device *dev)
2041 +{
2042 +       if (!dev->phydev)
2043 +               return -ENXIO;
2044 +       return phy_start_aneg(dev->phydev);
2045 +}
2046 +
2047 +static void gmac_get_pauseparam(struct net_device *dev,
2048 +       struct ethtool_pauseparam *pparam)
2049 +{
2050 +       struct gmac_private *gmac = netdev_priv(dev);
2051 +       GMAC_CONFIG0_T config0;
2052 +
2053 +       config0.bits32 = readl(gmac->ctl_iomem + GMAC_CONFIG0);
2054 +
2055 +       pparam->rx_pause = config0.bits.rx_fc_en;
2056 +       pparam->tx_pause = config0.bits.tx_fc_en;
2057 +       pparam->autoneg = true;
2058 +}
2059 +
2060 +static void gmac_get_ringparam(struct net_device *dev,
2061 +       struct ethtool_ringparam *rp)
2062 +{
2063 +       struct gmac_private *gmac = netdev_priv(dev);
2064 +       GMAC_CONFIG0_T config0;
2065 +
2066 +       config0.bits32 = readl(gmac->ctl_iomem + GMAC_CONFIG0);
2067 +
2068 +       rp->rx_max_pending = 1 << 15;
2069 +       rp->rx_mini_max_pending = 0;
2070 +       rp->rx_jumbo_max_pending = 0;
2071 +       rp->tx_max_pending = 1 << 15;
2072 +
2073 +       rp->rx_pending = 1 << gmac->rxq_order;
2074 +       rp->rx_mini_pending = 0;
2075 +       rp->rx_jumbo_pending = 0;
2076 +       rp->tx_pending = 1 << gmac->txq_order;
2077 +}
2078 +
2079 +static int toe_resize_freeq(struct toe_private *toe, int changing_dev_id);
2080 +
2081 +static int gmac_set_ringparam(struct net_device *dev,
2082 +       struct ethtool_ringparam *rp)
2083 +{
2084 +       struct gmac_private *gmac = netdev_priv(dev);
2085 +       struct toe_private *toe = gmac->toe;
2086 +       int err = 0;
2087 +
2088 +       if (netif_running(dev))
2089 +               return -EBUSY;
2090 +
2091 +       if (rp->rx_pending) {
2092 +               gmac->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
2093 +               err = toe_resize_freeq(toe, dev->dev_id);
2094 +       }
2095 +
2096 +       if (rp->tx_pending)
2097 +       {
2098 +               gmac->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
2099 +               gmac->irq_every_tx_packets = 1 << (gmac->txq_order - 2);
2100 +       }
2101 +
2102 +       return err;
2103 +}
2104 +
2105 +static int gmac_get_coalesce(struct net_device *dev,
2106 +       struct ethtool_coalesce *ecmd)
2107 +{
2108 +       struct gmac_private *gmac = netdev_priv(dev);
2109 +
2110 +       ecmd->rx_max_coalesced_frames = 1;
2111 +       ecmd->tx_max_coalesced_frames = gmac->irq_every_tx_packets;
2112 +       ecmd->rx_coalesce_usecs = gmac->rx_coalesce_nsecs/1000;
2113 +
2114 +       return 0;
2115 +}
2116 +
2117 +static int gmac_set_coalesce(struct net_device *dev,
2118 +       struct ethtool_coalesce *ecmd)
2119 +{
2120 +       struct gmac_private *gmac = netdev_priv(dev);
2121 +
2122 +       if (ecmd->tx_max_coalesced_frames < 1)
2123 +               return -EINVAL;
2124 +       if (ecmd->tx_max_coalesced_frames >= 1 << gmac->txq_order)
2125 +               return -EINVAL;
2126 +
2127 +       gmac->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
2128 +       gmac->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;
2129 +
2130 +       return 0;
2131 +}
2132 +
2133 +static u32 gmac_get_msglevel(struct net_device *dev)
2134 +{
2135 +       struct gmac_private *gmac = netdev_priv(dev);
2136 +       return gmac->msg_enable;
2137 +}
2138 +
2139 +static void gmac_set_msglevel(struct net_device *dev, u32 level)
2140 +{
2141 +       struct gmac_private *gmac = netdev_priv(dev);
2142 +       gmac->msg_enable = level;
2143 +}
2144 +
2145 +static void gmac_get_drvinfo(struct net_device *dev,
2146 +       struct ethtool_drvinfo *info)
2147 +{
2148 +       strcpy(info->driver,  DRV_NAME);
2149 +       strcpy(info->version, DRV_VERSION);
2150 +       strcpy(info->bus_info, dev->dev_id ? "1" : "0");
2151 +}
2152 +
2153 +static const struct net_device_ops gmac_351x_ops = {
2154 +       .ndo_init               = gmac_init,
2155 +       .ndo_uninit             = gmac_uninit,
2156 +       .ndo_open               = gmac_open,
2157 +       .ndo_stop               = gmac_stop,
2158 +       .ndo_start_xmit         = gmac_start_xmit,
2159 +       .ndo_tx_timeout         = gmac_tx_timeout,
2160 +       .ndo_set_rx_mode        = gmac_set_rx_mode,
2161 +       .ndo_set_mac_address    = gmac_set_mac_address,
2162 +       .ndo_get_stats64        = gmac_get_stats64,
2163 +       .ndo_change_mtu         = gmac_change_mtu,
2164 +       .ndo_fix_features       = gmac_fix_features,
2165 +       .ndo_set_features       = gmac_set_features,
2166 +};
2167 +
2168 +static const struct ethtool_ops gmac_351x_ethtool_ops = {
2169 +       .get_sset_count = gmac_get_sset_count,
2170 +       .get_strings    = gmac_get_strings,
2171 +       .get_ethtool_stats = gmac_get_ethtool_stats,
2172 +       .get_settings   = gmac_get_settings,
2173 +       .set_settings   = gmac_set_settings,
2174 +       .get_link       = ethtool_op_get_link,
2175 +       .nway_reset     = gmac_nway_reset,
2176 +       .get_pauseparam = gmac_get_pauseparam,
2177 +       .get_ringparam  = gmac_get_ringparam,
2178 +       .set_ringparam  = gmac_set_ringparam,
2179 +       .get_coalesce   = gmac_get_coalesce,
2180 +       .set_coalesce   = gmac_set_coalesce,
2181 +       .get_msglevel   = gmac_get_msglevel,
2182 +       .set_msglevel   = gmac_set_msglevel,
2183 +       .get_drvinfo    = gmac_get_drvinfo,
2184 +};
2185 +
2186 +static int gmac_init_netdev(struct toe_private *toe, int num,
2187 +       struct platform_device *pdev)
2188 +{
2189 +       struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
2190 +       struct gmac_private *gmac;
2191 +       struct net_device *dev;
2192 +       int irq, err;
2193 +
2194 +       if (!pdata->bus_id[num])
2195 +               return 0;
2196 +
2197 +       irq = platform_get_irq(pdev, num);
2198 +       if (irq < 0) {
2199 +               dev_err(toe->dev, "No IRQ for ethernet device #%d\n", num);
2200 +               return irq;
2201 +       }
2202 +
2203 +       dev = alloc_etherdev_mq(sizeof(*gmac), TX_QUEUE_NUM);
2204 +       if (!dev) {
2205 +               dev_err(toe->dev, "Can't allocate ethernet device #%d\n", num);
2206 +               return -ENOMEM;
2207 +       }
2208 +
2209 +       gmac = netdev_priv(dev);
2210 +       gmac->num = num;
2211 +       gmac->toe = toe;
2212 +       SET_NETDEV_DEV(dev, toe->dev);
2213 +
2214 +       toe->netdev[num] = dev;
2215 +       dev->dev_id = num;
2216 +
2217 +       gmac->ctl_iomem = toe->iomem + TOE_GMAC_BASE(num);
2218 +       gmac->dma_iomem = toe->iomem + TOE_GMAC_DMA_BASE(num);
2219 +       dev->irq = irq;
2220 +
2221 +       dev->netdev_ops = &gmac_351x_ops;
2222 +       dev->ethtool_ops = &gmac_351x_ethtool_ops;
2223 +
2224 +       spin_lock_init(&gmac->config_lock);
2225 +       gmac_clear_hw_stats(dev);
2226 +
2227 +       dev->hw_features = GMAC_OFFLOAD_FEATURES;
2228 +       dev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;
2229 +
2230 +       gmac->freeq_refill = 0;
2231 +       netif_napi_add(dev, &gmac->napi, gmac_napi_poll, DEFAULT_NAPI_WEIGHT);
2232 +
2233 +       if (is_valid_ether_addr((void *)toe->mac_addr[num]))
2234 +               memcpy(dev->dev_addr, toe->mac_addr[num], ETH_ALEN);
2235 +       else
2236 +               random_ether_addr(dev->dev_addr);
2237 +       __gmac_set_mac_address(dev);
2238 +
2239 +       err = gmac_setup_phy(dev);
2240 +       if (err)
2241 +               netif_warn(gmac, probe, dev,
2242 +                       "PHY init failed: %d, deferring to ifup time\n", err);
2243 +
2244 +       err = register_netdev(dev);
2245 +       if (!err)
2246 +       {
2247 +               pr_info(DRV_NAME " %s: irq %d, dma base 0x%p, io base 0x%p\n",
2248 +                       dev->name, irq, gmac->dma_iomem, gmac->ctl_iomem);
2249 +               return 0;
2250 +       }
2251 +
2252 +       toe->netdev[num] = NULL;
2253 +       free_netdev(dev);
2254 +       return err;
2255 +}
2256 +
2257 +static irqreturn_t toe_irq_thread(int irq, void *data)
2258 +{
2259 +       struct toe_private *toe = data;
2260 +       void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG;
2261 +       void __iomem *irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG;
2262 +       unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
2263 +       unsigned long flags;
2264 +
2265 +       toe_fill_freeq(toe, 0);
2266 +
2267 +       /* Ack and enable interrupt */
2268 +       spin_lock_irqsave(&toe->irq_lock, flags);
2269 +       writel(irqmask, irqif_reg);
2270 +       irqmask |= readl(irqen_reg);
2271 +       writel(irqmask, irqen_reg);
2272 +       spin_unlock_irqrestore(&toe->irq_lock, flags);
2273 +
2274 +       return IRQ_HANDLED;
2275 +}
2276 +
2277 +static irqreturn_t toe_irq(int irq, void *data)
2278 +{
2279 +       struct toe_private *toe = data;
2280 +       void __iomem *irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG;
2281 +       void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG;
2282 +       unsigned long val, en;
2283 +       irqreturn_t ret = IRQ_NONE;
2284 +
2285 +       spin_lock(&toe->irq_lock);
2286 +
2287 +       val = readl(irqif_reg);
2288 +       en = readl(irqen_reg);
2289 +
2290 +       if (val & en & SWFQ_EMPTY_INT_BIT) {
2291 +               en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
2292 +                                          | GMAC1_RX_OVERRUN_INT_BIT);
2293 +               writel(en, irqen_reg);
2294 +               ret = IRQ_WAKE_THREAD;
2295 +       }
2296 +
2297 +       spin_unlock(&toe->irq_lock);
2298 +       return ret;
2299 +}
2300 +
2301 +static int toe_init(struct toe_private *toe,
2302 +       struct platform_device *pdev)
2303 +{
2304 +       int err;
2305 +
2306 +       writel(0, toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
2307 +       writel(0, toe->iomem + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
2308 +       writel(0, toe->iomem + GLOBAL_SWFQ_RWPTR_REG);
2309 +       writel(0, toe->iomem + GLOBAL_HWFQ_RWPTR_REG);
2310 +
2311 +       toe->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
2312 +       toe->freeq_order = ~0;
2313 +
2314 +       err = request_threaded_irq(toe->irq, toe_irq,
2315 +               toe_irq_thread, IRQF_SHARED, DRV_NAME " toe", toe);
2316 +       if (err)
2317 +               goto err_freeq;
2318 +
2319 +       return 0;
2320 +
2321 +err_freeq:
2322 +       toe_cleanup_freeq(toe);
2323 +       return err;
2324 +}
2325 +
2326 +static void toe_deinit(struct toe_private *toe)
2327 +{
2328 +       free_irq(toe->irq, toe);
2329 +       toe_cleanup_freeq(toe);
2330 +}
2331 +
2332 +static int toe_reset(struct toe_private *toe)
2333 +{
2334 +       unsigned int reg = 0, retry = 5;
2335 +
2336 +       reg = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
2337 +               GLOBAL_RESET));
2338 +       reg |= RESET_GMAC1 | RESET_GMAC0;
2339 +       writel(reg, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
2340 +               GLOBAL_RESET));
2341 +
2342 +       do {
2343 +               udelay(2);
2344 +               reg = readl((void __iomem*)(toe->iomem +
2345 +                       GLOBAL_TOE_VERSION_REG));
2346 +               barrier();
2347 +       } while (!reg && --retry);
2348 +
2349 +       return reg ? 0 : -EIO;
2350 +}
2351 +
2352 +/*
2353 + * Interrupt config:
2354 + *
2355 + *     GMAC0 intr bits ------> int0 ----> eth0
2356 + *     GMAC1 intr bits ------> int1 ----> eth1
2357 + *     TOE intr -------------> int1 ----> eth1
2358 + *     Classification Intr --> int0 ----> eth0
2359 + *     Default Q0 -----------> int0 ----> eth0
2360 + *     Default Q1 -----------> int1 ----> eth1
2361 + *     FreeQ intr -----------> int1 ----> eth1
2362 + */
2363 +static void toe_init_irq(struct toe_private *toe)
2364 +{
2365 +       writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
2366 +       writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
2367 +       writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_2_REG);
2368 +       writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_3_REG);
2369 +       writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG);
2370 +
2371 +       writel(0xCCFC0FC0, toe->iomem + GLOBAL_INTERRUPT_SELECT_0_REG);
2372 +       writel(0x00F00002, toe->iomem + GLOBAL_INTERRUPT_SELECT_1_REG);
2373 +       writel(0xFFFFFFFF, toe->iomem + GLOBAL_INTERRUPT_SELECT_2_REG);
2374 +       writel(0xFFFFFFFF, toe->iomem + GLOBAL_INTERRUPT_SELECT_3_REG);
2375 +       writel(0xFF000003, toe->iomem + GLOBAL_INTERRUPT_SELECT_4_REG);
2376 +
2377 +       /* edge-triggered interrupts packed to level-triggered one... */
2378 +       writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG);
2379 +       writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG);
2380 +       writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_2_REG);
2381 +       writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_3_REG);
2382 +       writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG);
2383 +}
2384 +
2385 +static void toe_save_mac_addr(struct toe_private *toe,
2386 +                       struct platform_device *pdev)
2387 +{
2388 +       struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
2389 +       void __iomem *ctl;
2390 +       int i;
2391 +
2392 +       for (i = 0; i < 2; i++) {
2393 +               if (pdata->bus_id[i]) {
2394 +                       ctl = toe->iomem + TOE_GMAC_BASE(i);
2395 +                       toe->mac_addr[i][0] = cpu_to_le32(readl(ctl + GMAC_STA_ADD0));
2396 +                       toe->mac_addr[i][1] = cpu_to_le32(readl(ctl + GMAC_STA_ADD1));
2397 +                       toe->mac_addr[i][2] = cpu_to_le32(readl(ctl + GMAC_STA_ADD2));
2398 +               }
2399 +       }
2400 +}
2401 +
2402 +static int gemini_gmac_probe(struct platform_device *pdev)
2403 +{
2404 +       struct resource *res;
2405 +       struct toe_private *toe;
2406 +       int irq, retval;
2407 +
2408 +       if (!pdev->dev.platform_data)
2409 +               return -EINVAL;
2410 +
2411 +       irq = platform_get_irq(pdev, 1);
2412 +       if (irq < 0)
2413 +               return irq;
2414 +
2415 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2416 +       if (!res) {
2417 +               dev_err(&pdev->dev, "can't get device resources\n");
2418 +               return -ENODEV;
2419 +       }
2420 +
2421 +       toe = kzalloc(sizeof(*toe), GFP_KERNEL);
2422 +       if (!toe)
2423 +               return -ENOMEM;
2424 +
2425 +       platform_set_drvdata(pdev, toe);
2426 +       toe->dev = &pdev->dev;
2427 +       toe->irq = irq;
2428 +
2429 +       toe->iomem = ioremap(res->start, resource_size(res));
2430 +       if (!toe->iomem) {
2431 +               dev_err(toe->dev, "ioremap failed\n");
2432 +               retval = -EIO;
2433 +               goto err_data;
2434 +       }
2435 +
2436 +       toe_save_mac_addr(toe, pdev);
2437 +
2438 +       retval = toe_reset(toe);
2439 +       if (retval < 0)
2440 +               goto err_unmap;
2441 +
2442 +       pr_info(DRV_NAME " toe: irq %d, io base 0x%08x, version %d\n",
2443 +               irq, res->start, retval);
2444 +
2445 +       spin_lock_init(&toe->irq_lock);
2446 +       spin_lock_init(&toe->freeq_lock);
2447 +
2448 +       toe_init_irq(toe);
2449 +
2450 +       retval = toe_init(toe, pdev);
2451 +       if (retval)
2452 +               goto err_unmap;
2453 +
2454 +       retval = gmac_init_netdev(toe, 0, pdev);
2455 +       if (retval)
2456 +               goto err_uninit;
2457 +
2458 +       retval = gmac_init_netdev(toe, 1, pdev);
2459 +       if (retval)
2460 +               goto err_uninit;
2461 +
2462 +       return 0;
2463 +
2464 +err_uninit:
2465 +       if (toe->netdev[0])
2466 +               unregister_netdev(toe->netdev[0]);
2467 +       toe_deinit(toe);
2468 +err_unmap:
2469 +       iounmap(toe->iomem);
2470 +err_data:
2471 +       kfree(toe);
2472 +       return retval;
2473 +}
2474 +
2475 +static int gemini_gmac_remove(struct platform_device *pdev)
2476 +{
2477 +       struct toe_private *toe = platform_get_drvdata(pdev);
2478 +       int i;
2479 +
2480 +       for (i = 0; i < 2; i++)
2481 +               if (toe->netdev[i])
2482 +                       unregister_netdev(toe->netdev[i]);
2483 +
2484 +       toe_init_irq(toe);
2485 +       toe_deinit(toe);
2486 +
2487 +       iounmap(toe->iomem);
2488 +       kfree(toe);
2489 +
2490 +       return 0;
2491 +}
2492 +
2493 +static struct platform_driver gemini_gmac_driver = {
2494 +       .probe          = gemini_gmac_probe,
2495 +       .remove         = gemini_gmac_remove,
2496 +       .driver.name    = DRV_NAME,
2497 +       .driver.owner   = THIS_MODULE,
2498 +};
2499 +
2500 +static int __init gemini_gmac_init(void)
2501 +{
2502 +#ifdef CONFIG_MDIO_GPIO_MODULE
2503 +       request_module("mdio-gpio");
2504 +#endif
2505 +       return platform_driver_register(&gemini_gmac_driver);
2506 +}
2507 +
2508 +static void __exit gemini_gmac_exit(void)
2509 +{
2510 +       platform_driver_unregister(&gemini_gmac_driver);
2511 +}
2512 +
2513 +module_init(gemini_gmac_init);
2514 +module_exit(gemini_gmac_exit);
2515 --- /dev/null
2516 +++ b/drivers/net/ethernet/gemini/sl351x_hw.h
2517 @@ -0,0 +1,1436 @@
2518 +/*
2519 + *  Register definitions for Gemini LEPUS GMAC Ethernet device driver.
2520 + *
2521 + *  Copyright (C) 2006, Storlink, Corp.
2522 + *  Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
2523 + *  Copyright (C) 2010, Michał Mirosław <mirq-linux@rere.qmqm.pl>
2524 + *
2525 + * This program is free software; you can redistribute it and/or modify
2526 + * it under the terms of the GNU General Public License as published by
2527 + * the Free Software Foundation; either version 2 of the License, or
2528 + * (at your option) any later version.
2529 + */
2530 +#ifndef _GMAC_HW_H
2531 +#define _GMAC_HW_H
2532 +
2533 +#include <linux/bitops.h>
2534 +
2535 +/*
2536 + * Base Registers
2537 + */
2538 +#define TOE_NONTOE_QUE_HDR_BASE                0x2000
2539 +#define TOE_TOE_QUE_HDR_BASE           0x3000
2540 +#define TOE_V_BIT_BASE                 0x4000
2541 +#define TOE_A_BIT_BASE                 0x6000
2542 +#define TOE_GMAC_DMA_BASE(x)           (0x8000 + 0x4000 * (x))
2543 +#define TOE_GMAC_BASE(x)               (0xA000 + 0x4000 * (x))
2544 +
2545 +/*
2546 + * Queue ID
2547 + */
2548 +#define TOE_SW_FREE_QID                        0x00
2549 +#define TOE_HW_FREE_QID                        0x01
2550 +#define TOE_GMAC0_SW_TXQ0_QID          0x02
2551 +#define TOE_GMAC0_SW_TXQ1_QID          0x03
2552 +#define TOE_GMAC0_SW_TXQ2_QID          0x04
2553 +#define TOE_GMAC0_SW_TXQ3_QID          0x05
2554 +#define TOE_GMAC0_SW_TXQ4_QID          0x06
2555 +#define TOE_GMAC0_SW_TXQ5_QID          0x07
2556 +#define TOE_GMAC0_HW_TXQ0_QID          0x08
2557 +#define TOE_GMAC0_HW_TXQ1_QID          0x09
2558 +#define TOE_GMAC0_HW_TXQ2_QID          0x0A
2559 +#define TOE_GMAC0_HW_TXQ3_QID          0x0B
2560 +#define TOE_GMAC1_SW_TXQ0_QID          0x12
2561 +#define TOE_GMAC1_SW_TXQ1_QID          0x13
2562 +#define TOE_GMAC1_SW_TXQ2_QID          0x14
2563 +#define TOE_GMAC1_SW_TXQ3_QID          0x15
2564 +#define TOE_GMAC1_SW_TXQ4_QID          0x16
2565 +#define TOE_GMAC1_SW_TXQ5_QID          0x17
2566 +#define TOE_GMAC1_HW_TXQ0_QID          0x18
2567 +#define TOE_GMAC1_HW_TXQ1_QID          0x19
2568 +#define TOE_GMAC1_HW_TXQ2_QID          0x1A
2569 +#define TOE_GMAC1_HW_TXQ3_QID          0x1B
2570 +#define TOE_GMAC0_DEFAULT_QID          0x20
2571 +#define TOE_GMAC1_DEFAULT_QID          0x21
2572 +#define TOE_CLASSIFICATION_QID(x)      (0x22 + x)      /* 0x22 ~ 0x2F */
2573 +#define TOE_TOE_QID(x)                 (0x40 + x)      /* 0x40 ~ 0x7F */
2574 +
2575 +/*
2576 + * old info:
2577 + * TOE DMA Queue Size should be 2^n, n = 6...12
2578 + * TOE DMA Queues are the following queue types:
2579 + *             SW Free Queue, HW Free Queue,
2580 + *             GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
2581 + * The base address and descriptor number are configured at
2582 + * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
2583 + */
2584 +
2585 +#define GET_WPTR(addr)                 __raw_readw((addr) + 2)
2586 +#define GET_RPTR(addr)                 __raw_readw((addr))
2587 +#define SET_WPTR(addr, data)           __raw_writew((data), (addr) + 2)
2588 +#define SET_RPTR(addr, data)           __raw_writew((data), (addr))
2589 +#define __RWPTR_NEXT(x, mask)          (((unsigned int)(x) + 1) & (mask))
2590 +#define __RWPTR_PREV(x, mask)          (((unsigned int)(x) - 1) & (mask))
2591 +#define __RWPTR_DISTANCE(r, w, mask)   (((unsigned int)(w) - (r)) & (mask))
2592 +#define __RWPTR_MASK(order)            ((1 << (order)) - 1)
2593 +#define RWPTR_NEXT(x, order)           __RWPTR_NEXT((x), __RWPTR_MASK((order)))
2594 +#define RWPTR_PREV(x, order)           __RWPTR_PREV((x), __RWPTR_MASK((order)))
2595 +#define RWPTR_DISTANCE(r, w, order)    __RWPTR_DISTANCE((r), (w), \
2596 +                                               __RWPTR_MASK((order)))
2597 +
2598 +/*
2599 + * Global registers
2600 + * #define TOE_GLOBAL_BASE                     (TOE_BASE + 0x0000)
2601 + * Base 0x60000000
2602 + */
2603 +#define GLOBAL_TOE_VERSION_REG         0x0000
2604 +#define GLOBAL_SW_FREEQ_BASE_SIZE_REG  0x0004
2605 +#define GLOBAL_HW_FREEQ_BASE_SIZE_REG  0x0008
2606 +#define GLOBAL_DMA_SKB_SIZE_REG                0x0010
2607 +#define GLOBAL_SWFQ_RWPTR_REG          0x0014
2608 +#define GLOBAL_HWFQ_RWPTR_REG          0x0018
2609 +#define GLOBAL_INTERRUPT_STATUS_0_REG  0x0020
2610 +#define GLOBAL_INTERRUPT_ENABLE_0_REG  0x0024
2611 +#define GLOBAL_INTERRUPT_SELECT_0_REG  0x0028
2612 +#define GLOBAL_INTERRUPT_STATUS_1_REG  0x0030
2613 +#define GLOBAL_INTERRUPT_ENABLE_1_REG  0x0034
2614 +#define GLOBAL_INTERRUPT_SELECT_1_REG  0x0038
2615 +#define GLOBAL_INTERRUPT_STATUS_2_REG  0x0040
2616 +#define GLOBAL_INTERRUPT_ENABLE_2_REG  0x0044
2617 +#define GLOBAL_INTERRUPT_SELECT_2_REG  0x0048
2618 +#define GLOBAL_INTERRUPT_STATUS_3_REG  0x0050
2619 +#define GLOBAL_INTERRUPT_ENABLE_3_REG  0x0054
2620 +#define GLOBAL_INTERRUPT_SELECT_3_REG  0x0058
2621 +#define GLOBAL_INTERRUPT_STATUS_4_REG  0x0060
2622 +#define GLOBAL_INTERRUPT_ENABLE_4_REG  0x0064
2623 +#define GLOBAL_INTERRUPT_SELECT_4_REG  0x0068
2624 +#define GLOBAL_HASH_TABLE_BASE_REG     0x006C
2625 +#define GLOBAL_QUEUE_THRESHOLD_REG     0x0070
2626 +
2627 +/*
2628 + * GMAC 0/1 DMA/TOE register
2629 + * #define TOE_GMAC0_DMA_BASE          (TOE_BASE + 0x8000)
2630 + * #define TOE_GMAC1_DMA_BASE          (TOE_BASE + 0xC000)
2631 + * Base 0x60008000 or 0x6000C000
2632 + */
2633 +#define GMAC_DMA_CTRL_REG              0x0000
2634 +#define GMAC_TX_WEIGHTING_CTRL_0_REG   0x0004
2635 +#define GMAC_TX_WEIGHTING_CTRL_1_REG   0x0008
2636 +#define GMAC_SW_TX_QUEUE0_PTR_REG      0x000C
2637 +#define GMAC_SW_TX_QUEUE1_PTR_REG      0x0010
2638 +#define GMAC_SW_TX_QUEUE2_PTR_REG      0x0014
2639 +#define GMAC_SW_TX_QUEUE3_PTR_REG      0x0018
2640 +#define GMAC_SW_TX_QUEUE4_PTR_REG      0x001C
2641 +#define GMAC_SW_TX_QUEUE5_PTR_REG      0x0020
2642 +#define GMAC_SW_TX_QUEUE_PTR_REG(i)    (GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i))
2643 +#define GMAC_HW_TX_QUEUE0_PTR_REG      0x0024
2644 +#define GMAC_HW_TX_QUEUE1_PTR_REG      0x0028
2645 +#define GMAC_HW_TX_QUEUE2_PTR_REG      0x002C
2646 +#define GMAC_HW_TX_QUEUE3_PTR_REG      0x0030
2647 +#define GMAC_HW_TX_QUEUE_PTR_REG(i)    (GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i))
2648 +#define GMAC_DMA_TX_FIRST_DESC_REG     0x0038
2649 +#define GMAC_DMA_TX_CURR_DESC_REG      0x003C
2650 +#define GMAC_DMA_TX_DESC_WORD0_REG     0x0040
2651 +#define GMAC_DMA_TX_DESC_WORD1_REG     0x0044
2652 +#define GMAC_DMA_TX_DESC_WORD2_REG     0x0048
2653 +#define GMAC_DMA_TX_DESC_WORD3_REG     0x004C
2654 +#define GMAC_SW_TX_QUEUE_BASE_REG      0x0050
2655 +#define GMAC_HW_TX_QUEUE_BASE_REG      0x0054
2656 +#define GMAC_DMA_RX_FIRST_DESC_REG     0x0058
2657 +#define GMAC_DMA_RX_CURR_DESC_REG      0x005C
2658 +#define GMAC_DMA_RX_DESC_WORD0_REG     0x0060
2659 +#define GMAC_DMA_RX_DESC_WORD1_REG     0x0064
2660 +#define GMAC_DMA_RX_DESC_WORD2_REG     0x0068
2661 +#define GMAC_DMA_RX_DESC_WORD3_REG     0x006C
2662 +#define GMAC_HASH_ENGINE_REG0          0x0070
2663 +#define GMAC_HASH_ENGINE_REG1          0x0074
2664 +/* matching rule 0 Control register 0 */
2665 +#define GMAC_MR0CR0                    0x0078
2666 +#define GMAC_MR0CR1                    0x007C
2667 +#define GMAC_MR0CR2                    0x0080
2668 +#define GMAC_MR1CR0                    0x0084
2669 +#define GMAC_MR1CR1                    0x0088
2670 +#define GMAC_MR1CR2                    0x008C
2671 +#define GMAC_MR2CR0                    0x0090
2672 +#define GMAC_MR2CR1                    0x0094
2673 +#define GMAC_MR2CR2                    0x0098
2674 +#define GMAC_MR3CR0                    0x009C
2675 +#define GMAC_MR3CR1                    0x00A0
2676 +#define GMAC_MR3CR2                    0x00A4
2677 +/* Support Protocol Regsister 0 */
2678 +#define GMAC_SPR0                      0x00A8
2679 +#define GMAC_SPR1                      0x00AC
2680 +#define GMAC_SPR2                      0x00B0
2681 +#define GMAC_SPR3                      0x00B4
2682 +#define GMAC_SPR4                      0x00B8
2683 +#define GMAC_SPR5                      0x00BC
2684 +#define GMAC_SPR6                      0x00C0
2685 +#define GMAC_SPR7                      0x00C4
2686 +/* GMAC Hash/Rx/Tx AHB Weighting register */
2687 +#define GMAC_AHB_WEIGHT_REG            0x00C8
2688 +
2689 +/*
2690 + * TOE GMAC 0/1 register
2691 + * #define TOE_GMAC0_BASE                              (TOE_BASE + 0xA000)
2692 + * #define TOE_GMAC1_BASE                              (TOE_BASE + 0xE000)
2693 + * Base 0x6000A000 or 0x6000E000
2694 + */
2695 +enum GMAC_REGISTER {
2696 +       GMAC_STA_ADD0   = 0x0000,
2697 +       GMAC_STA_ADD1   = 0x0004,
2698 +       GMAC_STA_ADD2   = 0x0008,
2699 +       GMAC_RX_FLTR    = 0x000c,
2700 +       GMAC_MCAST_FIL0 = 0x0010,
2701 +       GMAC_MCAST_FIL1 = 0x0014,
2702 +       GMAC_CONFIG0    = 0x0018,
2703 +       GMAC_CONFIG1    = 0x001c,
2704 +       GMAC_CONFIG2    = 0x0020,
2705 +       GMAC_CONFIG3    = 0x0024,
2706 +       GMAC_RESERVED   = 0x0028,
2707 +       GMAC_STATUS     = 0x002c,
2708 +       GMAC_IN_DISCARDS= 0x0030,
2709 +       GMAC_IN_ERRORS  = 0x0034,
2710 +       GMAC_IN_MCAST   = 0x0038,
2711 +       GMAC_IN_BCAST   = 0x003c,
2712 +       GMAC_IN_MAC1    = 0x0040,       /* for STA 1 MAC Address */
2713 +       GMAC_IN_MAC2    = 0x0044        /* for STA 2 MAC Address */
2714 +};
2715 +
2716 +#define RX_STATS_NUM   6
2717 +
2718 +/*
2719 + * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
2720 + */
2721 +typedef union {
2722 +       unsigned int bits32;
2723 +       unsigned int base_size;
2724 +} DMA_Q_BASE_SIZE_T;
2725 +#define DMA_Q_BASE_MASK                (~0x0f)
2726 +
2727 +/*
2728 + * DMA SKB Buffer register (offset 0x0008)
2729 + */
2730 +typedef union {
2731 +       unsigned int bits32;
2732 +       struct bit_0008 {
2733 +               unsigned int sw_skb_size : 16;  /* SW Free poll SKB Size */
2734 +               unsigned int hw_skb_size : 16;  /* HW Free poll SKB Size */
2735 +       } bits;
2736 +} DMA_SKB_SIZE_T;
2737 +
2738 +/*
2739 + * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
2740 + */
2741 +typedef union {
2742 +       unsigned int bits32;
2743 +       struct bit_000c {
2744 +               unsigned int rptr       : 16;   /* Read Ptr, RO */
2745 +               unsigned int wptr       : 16;   /* Write Ptr, RW */
2746 +       } bits;
2747 +} DMA_RWPTR_T;
2748 +
2749 +/*
2750 + * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
2751 + * see DMA_RWPTR_T structure
2752 + */
2753 +
2754 +/*
2755 + * Interrupt Status Register 0 (offset 0x0020)
2756 + * Interrupt Mask Register 0   (offset 0x0024)
2757 + * Interrupt Select Register 0 (offset 0x0028)
2758 + */
2759 +typedef union {
2760 +       unsigned int bits32;
2761 +       struct bit_0020 {
2762 +               /* GMAC0 SW Tx Queue 0 EOF Interrupt */
2763 +               unsigned int swtq00_eof : 1;
2764 +               unsigned int swtq01_eof : 1;
2765 +               unsigned int swtq02_eof : 1;
2766 +               unsigned int swtq03_eof : 1;
2767 +               unsigned int swtq04_eof : 1;
2768 +               unsigned int swtq05_eof : 1;
2769 +               /* GMAC1 SW Tx Queue 0 EOF Interrupt */
2770 +               unsigned int swtq10_eof : 1;
2771 +               unsigned int swtq11_eof : 1;
2772 +               unsigned int swtq12_eof : 1;
2773 +               unsigned int swtq13_eof : 1;
2774 +               unsigned int swtq14_eof : 1;
2775 +               unsigned int swtq15_eof : 1;
2776 +               /* GMAC0 SW Tx Queue 0 Finish Interrupt */
2777 +               unsigned int swtq00_fin : 1;
2778 +               unsigned int swtq01_fin : 1;
2779 +               unsigned int swtq02_fin : 1;
2780 +               unsigned int swtq03_fin : 1;
2781 +               unsigned int swtq04_fin : 1;
2782 +               unsigned int swtq05_fin : 1;
2783 +               /* GMAC1 SW Tx Queue 0 Finish Interrupt */
2784 +               unsigned int swtq10_fin : 1;
2785 +               unsigned int swtq11_fin : 1;
2786 +               unsigned int swtq12_fin : 1;
2787 +               unsigned int swtq13_fin : 1;
2788 +               unsigned int swtq14_fin : 1;
2789 +               unsigned int swtq15_fin : 1;
2790 +               /* GMAC0 Rx Descriptor Protocol Error */
2791 +               unsigned int rxPerr0    : 1;
2792 +               /* GMAC0 AHB Bus Error while Rx */
2793 +               unsigned int rxDerr0    : 1;
2794 +               /* GMAC1 Rx Descriptor Protocol Error */
2795 +               unsigned int rxPerr1    : 1;
2796 +               /* GMAC1 AHB Bus Error while Rx */
2797 +               unsigned int rxDerr1    : 1;
2798 +               /* GMAC0 Tx Descriptor Protocol Error */
2799 +               unsigned int txPerr0    : 1;
2800 +               /* GMAC0 AHB Bus Error while Tx */
2801 +               unsigned int txDerr0    : 1;
2802 +               /* GMAC1 Tx Descriptor Protocol Error */
2803 +               unsigned int txPerr1    : 1;
2804 +               /* GMAC1 AHB Bus Error while Tx */
2805 +               unsigned int txDerr1    : 1;
2806 +       } bits;
2807 +} INTR_REG0_T;
2808 +
2809 +#define GMAC1_TXDERR_INT_BIT           BIT(31)
2810 +#define GMAC1_TXPERR_INT_BIT           BIT(30)
2811 +#define GMAC0_TXDERR_INT_BIT           BIT(29)
2812 +#define GMAC0_TXPERR_INT_BIT           BIT(28)
2813 +#define GMAC1_RXDERR_INT_BIT           BIT(27)
2814 +#define GMAC1_RXPERR_INT_BIT           BIT(26)
2815 +#define GMAC0_RXDERR_INT_BIT           BIT(25)
2816 +#define GMAC0_RXPERR_INT_BIT           BIT(24)
2817 +#define GMAC1_SWTQ15_FIN_INT_BIT       BIT(23)
2818 +#define GMAC1_SWTQ14_FIN_INT_BIT       BIT(22)
2819 +#define GMAC1_SWTQ13_FIN_INT_BIT       BIT(21)
2820 +#define GMAC1_SWTQ12_FIN_INT_BIT       BIT(20)
2821 +#define GMAC1_SWTQ11_FIN_INT_BIT       BIT(19)
2822 +#define GMAC1_SWTQ10_FIN_INT_BIT       BIT(18)
2823 +#define GMAC0_SWTQ05_FIN_INT_BIT       BIT(17)
2824 +#define GMAC0_SWTQ04_FIN_INT_BIT       BIT(16)
2825 +#define GMAC0_SWTQ03_FIN_INT_BIT       BIT(15)
2826 +#define GMAC0_SWTQ02_FIN_INT_BIT       BIT(14)
2827 +#define GMAC0_SWTQ01_FIN_INT_BIT       BIT(13)
2828 +#define GMAC0_SWTQ00_FIN_INT_BIT       BIT(12)
2829 +#define GMAC1_SWTQ15_EOF_INT_BIT       BIT(11)
2830 +#define GMAC1_SWTQ14_EOF_INT_BIT       BIT(10)
2831 +#define GMAC1_SWTQ13_EOF_INT_BIT       BIT(9)
2832 +#define GMAC1_SWTQ12_EOF_INT_BIT       BIT(8)
2833 +#define GMAC1_SWTQ11_EOF_INT_BIT       BIT(7)
2834 +#define GMAC1_SWTQ10_EOF_INT_BIT       BIT(6)
2835 +#define GMAC0_SWTQ05_EOF_INT_BIT       BIT(5)
2836 +#define GMAC0_SWTQ04_EOF_INT_BIT       BIT(4)
2837 +#define GMAC0_SWTQ03_EOF_INT_BIT       BIT(3)
2838 +#define GMAC0_SWTQ02_EOF_INT_BIT       BIT(2)
2839 +#define GMAC0_SWTQ01_EOF_INT_BIT       BIT(1)
2840 +#define GMAC0_SWTQ00_EOF_INT_BIT       BIT(0)
2841 +
2842 +/*
2843 + * Interrupt Status Register 1 (offset 0x0030)
2844 + * Interrupt Mask Register 1   (offset 0x0034)
2845 + * Interrupt Select Register 1 (offset 0x0038)
2846 + */
2847 +typedef union {
2848 +       unsigned int bits32;
2849 +       struct bit_0030 {
2850 +               unsigned int default_q0_eof     : 1;    /* Default Queue 0 EOF Interrupt */
2851 +               unsigned int default_q1_eof     : 1;    /* Default Queue 1 EOF Interrupt */
2852 +               unsigned int class_rx           : 14;   /* Classification Queue Rx Interrupt */
2853 +               unsigned int hwtq00_eof         : 1;    /* GMAC0 HW Tx Queue0 EOF Interrupt */
2854 +               unsigned int hwtq01_eof         : 1;    /* GMAC0 HW Tx Queue1 EOF Interrupt */
2855 +               unsigned int hwtq02_eof         : 1;    /* GMAC0 HW Tx Queue2 EOF Interrupt */
2856 +               unsigned int hwtq03_eof         : 1;    /* GMAC0 HW Tx Queue3 EOF Interrupt */
2857 +               unsigned int hwtq10_eof         : 1;    /* GMAC1 HW Tx Queue0 EOF Interrupt */
2858 +               unsigned int hwtq11_eof         : 1;    /* GMAC1 HW Tx Queue1 EOF Interrupt */
2859 +               unsigned int hwtq12_eof         : 1;    /* GMAC1 HW Tx Queue2 EOF Interrupt */
2860 +               unsigned int hwtq13_eof         : 1;    /* GMAC1 HW Tx Queue3 EOF Interrupt */
2861 +               unsigned int toe_iq0_intr       : 1;    /* TOE Interrupt Queue 0 with Interrupts */
2862 +               unsigned int toe_iq1_intr       : 1;    /* TOE Interrupt Queue 1 with Interrupts */
2863 +               unsigned int toe_iq2_intr       : 1;    /* TOE Interrupt Queue 2 with Interrupts */
2864 +               unsigned int toe_iq3_intr       : 1;    /* TOE Interrupt Queue 3 with Interrupts */
2865 +               unsigned int toe_iq0_full       : 1;    /* TOE Interrupt Queue 0 Full Interrupt */
2866 +               unsigned int toe_iq1_full       : 1;    /* TOE Interrupt Queue 1 Full Interrupt */
2867 +               unsigned int toe_iq2_full       : 1;    /* TOE Interrupt Queue 2 Full Interrupt */
2868 +               unsigned int toe_iq3_full       : 1;    /* TOE Interrupt Queue 3 Full Interrupt */
2869 +       } bits;
2870 +} INTR_REG1_T;
2871 +
2872 +#define TOE_IQ3_FULL_INT_BIT           BIT(31)
2873 +#define TOE_IQ2_FULL_INT_BIT           BIT(30)
2874 +#define TOE_IQ1_FULL_INT_BIT           BIT(29)
2875 +#define TOE_IQ0_FULL_INT_BIT           BIT(28)
2876 +#define TOE_IQ3_INT_BIT                        BIT(27)
2877 +#define TOE_IQ2_INT_BIT                        BIT(26)
2878 +#define TOE_IQ1_INT_BIT                        BIT(25)
2879 +#define TOE_IQ0_INT_BIT                        BIT(24)
2880 +#define GMAC1_HWTQ13_EOF_INT_BIT       BIT(23)
2881 +#define GMAC1_HWTQ12_EOF_INT_BIT       BIT(22)
2882 +#define GMAC1_HWTQ11_EOF_INT_BIT       BIT(21)
2883 +#define GMAC1_HWTQ10_EOF_INT_BIT       BIT(20)
2884 +#define GMAC0_HWTQ03_EOF_INT_BIT       BIT(19)
2885 +#define GMAC0_HWTQ02_EOF_INT_BIT       BIT(18)
2886 +#define GMAC0_HWTQ01_EOF_INT_BIT       BIT(17)
2887 +#define GMAC0_HWTQ00_EOF_INT_BIT       BIT(16)
2888 +#define CLASS_RX_INT_BIT(x)            BIT((x + 2))
2889 +#define DEFAULT_Q1_INT_BIT             BIT(1)
2890 +#define DEFAULT_Q0_INT_BIT             BIT(0)
2891 +
2892 +#define TOE_IQ_INT_BITS                (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
2893 +                                TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
2894 +#define        TOE_IQ_FULL_BITS        (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
2895 +                                TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
2896 +#define        TOE_IQ_ALL_BITS         (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
2897 +#define TOE_CLASS_RX_INT_BITS  0xfffc
2898 +
2899 +/*
2900 + * Interrupt Status Register 2 (offset 0x0040)
2901 + * Interrupt Mask Register 2   (offset 0x0044)
2902 + * Interrupt Select Register 2 (offset 0x0048)
2903 + */
2904 +typedef union {
2905 +       unsigned int bits32;
2906 +       struct bit_0040 {
2907 +               unsigned int toe_q0_full        : 1;    /* bit 0        TOE Queue 0 Full Interrupt */
2908 +               unsigned int toe_q1_full        : 1;    /* bit 1        TOE Queue 1 Full Interrupt */
2909 +               unsigned int toe_q2_full        : 1;    /* bit 2        TOE Queue 2 Full Interrupt */
2910 +               unsigned int toe_q3_full        : 1;    /* bit 3        TOE Queue 3 Full Interrupt */
2911 +               unsigned int toe_q4_full        : 1;    /* bit 4        TOE Queue 4 Full Interrupt */
2912 +               unsigned int toe_q5_full        : 1;    /* bit 5        TOE Queue 5 Full Interrupt */
2913 +               unsigned int toe_q6_full        : 1;    /* bit 6        TOE Queue 6 Full Interrupt */
2914 +               unsigned int toe_q7_full        : 1;    /* bit 7        TOE Queue 7 Full Interrupt */
2915 +               unsigned int toe_q8_full        : 1;    /* bit 8        TOE Queue 8 Full Interrupt */
2916 +               unsigned int toe_q9_full        : 1;    /* bit 9        TOE Queue 9 Full Interrupt */
2917 +               unsigned int toe_q10_full       : 1;    /* bit 10       TOE Queue 10 Full Interrupt */
2918 +               unsigned int toe_q11_full       : 1;    /* bit 11       TOE Queue 11 Full Interrupt */
2919 +               unsigned int toe_q12_full       : 1;    /* bit 12       TOE Queue 12 Full Interrupt */
2920 +               unsigned int toe_q13_full       : 1;    /* bit 13       TOE Queue 13 Full Interrupt */
2921 +               unsigned int toe_q14_full       : 1;    /* bit 14       TOE Queue 14 Full Interrupt */
2922 +               unsigned int toe_q15_full       : 1;    /* bit 15       TOE Queue 15 Full Interrupt */
2923 +               unsigned int toe_q16_full       : 1;    /* bit 16       TOE Queue 16 Full Interrupt */
2924 +               unsigned int toe_q17_full       : 1;    /* bit 17       TOE Queue 17 Full Interrupt */
2925 +               unsigned int toe_q18_full       : 1;    /* bit 18       TOE Queue 18 Full Interrupt */
2926 +               unsigned int toe_q19_full       : 1;    /* bit 19       TOE Queue 19 Full Interrupt */
2927 +               unsigned int toe_q20_full       : 1;    /* bit 20       TOE Queue 20 Full Interrupt */
2928 +               unsigned int toe_q21_full       : 1;    /* bit 21       TOE Queue 21 Full Interrupt */
2929 +               unsigned int toe_q22_full       : 1;    /* bit 22       TOE Queue 22 Full Interrupt */
2930 +               unsigned int toe_q23_full       : 1;    /* bit 23       TOE Queue 23 Full Interrupt */
2931 +               unsigned int toe_q24_full       : 1;    /* bit 24       TOE Queue 24 Full Interrupt */
2932 +               unsigned int toe_q25_full       : 1;    /* bit 25       TOE Queue 25 Full Interrupt */
2933 +               unsigned int toe_q26_full       : 1;    /* bit 26       TOE Queue 26 Full Interrupt */
2934 +               unsigned int toe_q27_full       : 1;    /* bit 27       TOE Queue 27 Full Interrupt */
2935 +               unsigned int toe_q28_full       : 1;    /* bit 28       TOE Queue 28 Full Interrupt */
2936 +               unsigned int toe_q29_full       : 1;    /* bit 29       TOE Queue 29 Full Interrupt */
2937 +               unsigned int toe_q30_full       : 1;    /* bit 30       TOE Queue 30 Full Interrupt */
2938 +               unsigned int toe_q31_full       : 1;    /* bit 31       TOE Queue 31 Full Interrupt */
2939 +       } bits;
2940 +} INTR_REG2_T;
2941 +
2942 +#define TOE_QL_FULL_INT_BIT(x)         BIT(x)
2943 +
2944 +/*
2945 + * Interrupt Status Register 3 (offset 0x0050)
2946 + * Interrupt Mask Register 3   (offset 0x0054)
2947 + * Interrupt Select Register 3 (offset 0x0058)
2948 + */
2949 +typedef union {
2950 +       unsigned int bits32;
2951 +       struct bit_0050 {
2952 +               unsigned int toe_q32_full       : 1;    /* bit 32       TOE Queue 32 Full Interrupt */
2953 +               unsigned int toe_q33_full       : 1;    /* bit 33       TOE Queue 33 Full Interrupt */
2954 +               unsigned int toe_q34_full       : 1;    /* bit 34       TOE Queue 34 Full Interrupt */
2955 +               unsigned int toe_q35_full       : 1;    /* bit 35       TOE Queue 35 Full Interrupt */
2956 +               unsigned int toe_q36_full       : 1;    /* bit 36       TOE Queue 36 Full Interrupt */
2957 +               unsigned int toe_q37_full       : 1;    /* bit 37       TOE Queue 37 Full Interrupt */
2958 +               unsigned int toe_q38_full       : 1;    /* bit 38       TOE Queue 38 Full Interrupt */
2959 +               unsigned int toe_q39_full       : 1;    /* bit 39       TOE Queue 39 Full Interrupt */
2960 +               unsigned int toe_q40_full       : 1;    /* bit 40       TOE Queue 40 Full Interrupt */
2961 +               unsigned int toe_q41_full       : 1;    /* bit 41       TOE Queue 41 Full Interrupt */
2962 +               unsigned int toe_q42_full       : 1;    /* bit 42       TOE Queue 42 Full Interrupt */
2963 +               unsigned int toe_q43_full       : 1;    /* bit 43       TOE Queue 43 Full Interrupt */
2964 +               unsigned int toe_q44_full       : 1;    /* bit 44       TOE Queue 44 Full Interrupt */
2965 +               unsigned int toe_q45_full       : 1;    /* bit 45       TOE Queue 45 Full Interrupt */
2966 +               unsigned int toe_q46_full       : 1;    /* bit 46       TOE Queue 46 Full Interrupt */
2967 +               unsigned int toe_q47_full       : 1;    /* bit 47       TOE Queue 47 Full Interrupt */
2968 +               unsigned int toe_q48_full       : 1;    /* bit 48       TOE Queue 48 Full Interrupt */
2969 +               unsigned int toe_q49_full       : 1;    /* bit 49       TOE Queue 49 Full Interrupt */
2970 +               unsigned int toe_q50_full       : 1;    /* bit 50       TOE Queue 50 Full Interrupt */
2971 +               unsigned int toe_q51_full       : 1;    /* bit 51       TOE Queue 51 Full Interrupt */
2972 +               unsigned int toe_q52_full       : 1;    /* bit 52       TOE Queue 52 Full Interrupt */
2973 +               unsigned int toe_q53_full       : 1;    /* bit 53       TOE Queue 53 Full Interrupt */
2974 +               unsigned int toe_q54_full       : 1;    /* bit 54       TOE Queue 54 Full Interrupt */
2975 +               unsigned int toe_q55_full       : 1;    /* bit 55       TOE Queue 55 Full Interrupt */
2976 +               unsigned int toe_q56_full       : 1;    /* bit 56       TOE Queue 56 Full Interrupt */
2977 +               unsigned int toe_q57_full       : 1;    /* bit 57       TOE Queue 57 Full Interrupt */
2978 +               unsigned int toe_q58_full       : 1;    /* bit 58       TOE Queue 58 Full Interrupt */
2979 +               unsigned int toe_q59_full       : 1;    /* bit 59       TOE Queue 59 Full Interrupt */
2980 +               unsigned int toe_q60_full       : 1;    /* bit 60       TOE Queue 60 Full Interrupt */
2981 +               unsigned int toe_q61_full       : 1;    /* bit 61       TOE Queue 61 Full Interrupt */
2982 +               unsigned int toe_q62_full       : 1;    /* bit 62       TOE Queue 62 Full Interrupt */
2983 +               unsigned int toe_q63_full       : 1;    /* bit 63       TOE Queue 63 Full Interrupt */
2984 +       } bits;
2985 +} INTR_REG3_T;
2986 +
2987 +#define TOE_QH_FULL_INT_BIT(x)         BIT(x-32)
2988 +
2989 +/*
2990 + * Interrupt Status Register 4 (offset 0x0060)
2991 + * Interrupt Mask Register 4   (offset 0x0064)
2992 + * Interrupt Select Register 4 (offset 0x0068)
2993 + */
2994 +typedef union {
2995 +       unsigned char byte;
2996 +       struct bit_0060 {
2997 +               unsigned char status_changed    : 1;    /* Status Changed Intr for RGMII Mode */
2998 +               unsigned char rx_overrun        : 1;   /* GMAC Rx FIFO overrun interrupt */
2999 +               unsigned char tx_pause_off      : 1;    /* received pause off frame interrupt */
3000 +               unsigned char rx_pause_off      : 1;    /* received pause off frame interrupt */
3001 +               unsigned char tx_pause_on       : 1;    /* transmit pause on frame interrupt */
3002 +               unsigned char rx_pause_on       : 1;    /* received pause on frame interrupt */
3003 +               unsigned char cnt_full          : 1;    /* MIB counters half full interrupt */
3004 +               unsigned char reserved          : 1;    /* */
3005 +       } __packed bits;
3006 +} __packed GMAC_INTR_T;
3007 +
3008 +typedef union {
3009 +       unsigned int bits32;
3010 +       struct bit_0060_2 {
3011 +               unsigned int    swfq_empty      : 1;    /* bit 0        Software Free Queue Empty Intr. */
3012 +               unsigned int    hwfq_empty      : 1;    /* bit 1        Hardware Free Queue Empty Intr. */
3013 +               unsigned int    class_qf_int    : 14;   /* bit 15:2 Classification Rx Queue13-0 Full Intr. */
3014 +               GMAC_INTR_T     gmac0;
3015 +               GMAC_INTR_T     gmac1;
3016 +       } bits;
3017 +} INTR_REG4_T;
3018 +
3019 +#define GMAC1_RESERVED_INT_BIT         BIT(31)
3020 +#define GMAC1_MIB_INT_BIT              BIT(30)
3021 +#define GMAC1_RX_PAUSE_ON_INT_BIT      BIT(29)
3022 +#define GMAC1_TX_PAUSE_ON_INT_BIT      BIT(28)
3023 +#define GMAC1_RX_PAUSE_OFF_INT_BIT     BIT(27)
3024 +#define GMAC1_TX_PAUSE_OFF_INT_BIT     BIT(26)
3025 +#define GMAC1_RX_OVERRUN_INT_BIT       BIT(25)
3026 +#define GMAC1_STATUS_CHANGE_INT_BIT    BIT(24)
3027 +#define GMAC0_RESERVED_INT_BIT         BIT(23)
3028 +#define GMAC0_MIB_INT_BIT              BIT(22)
3029 +#define GMAC0_RX_PAUSE_ON_INT_BIT      BIT(21)
3030 +#define GMAC0_TX_PAUSE_ON_INT_BIT      BIT(20)
3031 +#define GMAC0_RX_PAUSE_OFF_INT_BIT     BIT(19)
3032 +#define GMAC0_TX_PAUSE_OFF_INT_BIT     BIT(18)
3033 +#define GMAC0_RX_OVERRUN_INT_BIT       BIT(17)
3034 +#define GMAC0_STATUS_CHANGE_INT_BIT    BIT(16)
3035 +#define CLASS_RX_FULL_INT_BIT(x)       BIT((x+2))
3036 +#define HWFQ_EMPTY_INT_BIT             BIT(1)
3037 +#define SWFQ_EMPTY_INT_BIT             BIT(0)
3038 +
3039 +#define GMAC0_INT_BITS         (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
3040 +                                GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT |        \
3041 +                                GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT |      \
3042 +                                GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
3043 +#define GMAC1_INT_BITS         (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
3044 +                                GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT |        \
3045 +                                GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT |      \
3046 +                                GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
3047 +
3048 +#define CLASS_RX_FULL_INT_BITS         0xfffc
3049 +
3050 +/*
3051 + * GLOBAL_QUEUE_THRESHOLD_REG  (offset 0x0070)
3052 + */
3053 +typedef union {
3054 +       unsigned int bits32;
3055 +       struct bit_0070_2 {
3056 +               unsigned int    swfq_empty      : 8;    /*  7:0         Software Free Queue Empty Threshold */
3057 +               unsigned int    hwfq_empty      : 8;    /* 15:8         Hardware Free Queue Empty Threshold */
3058 +               unsigned int    intrq           : 8;    /* 23:16 */
3059 +               unsigned int    toe_class       : 8;    /* 31:24 */
3060 +       } bits;
3061 +} QUEUE_THRESHOLD_T;
3062 +
3063 +
3064 +/*
3065 + * GMAC DMA Control Register
3066 + * GMAC0 offset 0x8000
3067 + * GMAC1 offset 0xC000
3068 + */
3069 +typedef union {
3070 +       unsigned int bits32;
3071 +       struct bit_8000 {
3072 +               unsigned int    td_bus          : 2;    /* bit 1:0      Peripheral Bus Width */
3073 +               unsigned int    td_burst_size   : 2;    /* bit 3:2      TxDMA max burst size for every AHB request */
3074 +               unsigned int    td_prot         : 4;    /* bit 7:4      TxDMA protection control */
3075 +               unsigned int    rd_bus          : 2;    /* bit 9:8      Peripheral Bus Width */
3076 +               unsigned int    rd_burst_size   : 2;    /* bit 11:10    DMA max burst size for every AHB request */
3077 +               unsigned int    rd_prot         : 4;    /* bit 15:12    DMA Protection Control */
3078 +               unsigned int    rd_insert_bytes : 2;    /* bit 17:16 */
3079 +               unsigned int    reserved        : 10;   /* bit 27:18 */
3080 +               unsigned int    drop_small_ack  : 1;    /* bit 28       1: Drop, 0: Accept */
3081 +               unsigned int    loopback        : 1;    /* bit 29       Loopback TxDMA to RxDMA */
3082 +               unsigned int    td_enable       : 1;    /* bit 30       Tx DMA Enable */
3083 +               unsigned int    rd_enable       : 1;    /* bit 31       Rx DMA Enable */
3084 +       } bits;
3085 +} GMAC_DMA_CTRL_T;
3086 +
3087 +/*
3088 + * GMAC Tx Weighting Control Register 0
3089 + * GMAC0 offset 0x8004
3090 + * GMAC1 offset 0xC004
3091 + */
3092 +typedef union {
3093 +       unsigned int bits32;
3094 +       struct bit_8004 {
3095 +               unsigned int    hw_tq0          : 6;    /* bit 5:0      HW TX Queue 3 */
3096 +               unsigned int    hw_tq1          : 6;    /* bit 11:6     HW TX Queue 2 */
3097 +               unsigned int    hw_tq2          : 6;    /* bit 17:12    HW TX Queue 1 */
3098 +               unsigned int    hw_tq3          : 6;    /* bit 23:18    HW TX Queue 0 */
3099 +               unsigned int    reserved        : 8;    /* bit 31:24 */
3100 +       } bits;
3101 +} GMAC_TX_WCR0_T;      /* Weighting Control Register 0 */
3102 +
3103 +/*
3104 + * GMAC Tx Weighting Control Register 1
3105 + * GMAC0 offset 0x8008
3106 + * GMAC1 offset 0xC008
3107 + */
3108 +typedef union {
3109 +       unsigned int bits32;
3110 +       struct bit_8008 {
3111 +               unsigned int    sw_tq0          : 5;    /* bit 4:0      SW TX Queue 0 */
3112 +               unsigned int    sw_tq1          : 5;    /* bit 9:5      SW TX Queue 1 */
3113 +               unsigned int    sw_tq2          : 5;    /* bit 14:10    SW TX Queue 2 */
3114 +               unsigned int    sw_tq3          : 5;    /* bit 19:15    SW TX Queue 3 */
3115 +               unsigned int    sw_tq4          : 5;    /* bit 24:20    SW TX Queue 4 */
3116 +               unsigned int    sw_tq5          : 5;    /* bit 29:25    SW TX Queue 5 */
3117 +               unsigned int    reserved        : 2;    /* bit 31:30 */
3118 +       } bits;
3119 +} GMAC_TX_WCR1_T;      /* Weighting Control Register 1 */
3120 +
3121 +/*
3122 + * Queue Read/Write Pointer
3123 + * GMAC SW TX Queue 0~5 Read/Write Pointer register
3124 + * GMAC0 offset 0x800C ~ 0x8020
3125 + * GMAC1 offset 0xC00C ~ 0xC020
3126 + * GMAC HW TX Queue 0~3 Read/Write Pointer register
3127 + * GMAC0 offset 0x8024 ~ 0x8030
3128 + * GMAC1 offset 0xC024 ~ 0xC030
3129 + *
3130 + * see DMA_RWPTR_T structure
3131 + */
3132 +
3133 +/*
3134 + * GMAC DMA Tx First Description Address Register
3135 + * GMAC0 offset 0x8038
3136 + * GMAC1 offset 0xC038
3137 + */
3138 +typedef union {
3139 +       unsigned int bits32;
3140 +       struct bit_8038 {
3141 +               unsigned int reserved           :  3;
3142 +               unsigned int td_busy            :  1;   /* bit 3        1: TxDMA busy; 0: TxDMA idle */
3143 +               unsigned int td_first_des_ptr   : 28;   /* bit 31:4     first descriptor address */
3144 +       } bits;
3145 +} GMAC_TXDMA_FIRST_DESC_T;
3146 +
3147 +/*
3148 + * GMAC DMA Tx Current Description Address Register
3149 + * GMAC0 offset 0x803C
3150 + * GMAC1 offset 0xC03C
3151 + */
3152 +typedef union {
3153 +       unsigned int bits32;
3154 +       struct bit_803C {
3155 +               unsigned int reserved           :  4;
3156 +               unsigned int td_curr_desc_ptr   : 28;   /* bit 31:4     current descriptor address */
3157 +       } bits;
3158 +} GMAC_TXDMA_CURR_DESC_T;
3159 +
3160 +/*
3161 + * GMAC DMA Tx Description Word 0 Register
3162 + * GMAC0 offset 0x8040
3163 + * GMAC1 offset 0xC040
3164 + */
3165 +typedef union {
3166 +       unsigned int bits32;
3167 +       struct bit_8040 {
3168 +               unsigned int buffer_size        : 16;   /* bit 15:0     Transfer size */
3169 +               unsigned int desc_count         : 6;    /* bit 21:16    number of descriptors used for the current frame */
3170 +               unsigned int status_tx_ok       : 1;    /* bit 22       Tx Status, 1: Successful 0: Failed */
3171 +               unsigned int status_rvd         : 6;    /* bit 28:23    Tx Status, Reserved bits */
3172 +               unsigned int perr               : 1;    /* bit 29       protocol error during processing this descriptor */
3173 +               unsigned int derr               : 1;    /* bit 30       data error during processing this descriptor */
3174 +               unsigned int reserved           : 1;    /* bit 31 */
3175 +       } bits;
3176 +} GMAC_TXDESC_0_T;
3177 +
3178 +/*
3179 + * GMAC DMA Tx Description Word 1 Register
3180 + * GMAC0 offset 0x8044
3181 + * GMAC1 offset 0xC044
3182 + */
3183 +typedef union {
3184 +       unsigned int bits32;
3185 +       struct txdesc_word1 {
3186 +               unsigned int    byte_count      : 16;   /* bit 15: 0    Tx Frame Byte Count */
3187 +               unsigned int    mtu_enable      : 1;    /* bit 16       TSS segmentation use MTU setting */
3188 +               unsigned int    ip_chksum       : 1;    /* bit 17       IPV4 Header Checksum Enable */
3189 +               unsigned int    ipv6_enable     : 1;    /* bit 18       IPV6 Tx Enable */
3190 +               unsigned int    tcp_chksum      : 1;    /* bit 19       TCP Checksum Enable */
3191 +               unsigned int    udp_chksum      : 1;    /* bit 20       UDP Checksum Enable */
3192 +               unsigned int    bypass_tss      : 1;    /* bit 21       Bypass HW offload engine */
3193 +               unsigned int    ip_fixed_len    : 1;    /* bit 22       Don't update IP length field */
3194 +               unsigned int    reserved        : 9;    /* bit 31:23    Tx Flag, Reserved */
3195 +       } bits;
3196 +} GMAC_TXDESC_1_T;
3197 +
3198 +#define TSS_IP_FIXED_LEN_BIT   BIT(22)
3199 +#define TSS_BYPASS_BIT         BIT(21)
3200 +#define TSS_UDP_CHKSUM_BIT     BIT(20)
3201 +#define TSS_TCP_CHKSUM_BIT     BIT(19)
3202 +#define TSS_IPV6_ENABLE_BIT    BIT(18)
3203 +#define TSS_IP_CHKSUM_BIT      BIT(17)
3204 +#define TSS_MTU_ENABLE_BIT     BIT(16)
3205 +
3206 +#define TSS_CHECKUM_ENABLE     \
3207 +       (TSS_IP_CHKSUM_BIT|TSS_IPV6_ENABLE_BIT| \
3208 +        TSS_TCP_CHKSUM_BIT|TSS_UDP_CHKSUM_BIT)
3209 +
3210 +/*
3211 + * GMAC DMA Tx Description Word 2 Register
3212 + * GMAC0 offset 0x8048
3213 + * GMAC1 offset 0xC048
3214 + */
3215 +typedef union {
3216 +       unsigned int    bits32;
3217 +       unsigned int    buf_adr;
3218 +} GMAC_TXDESC_2_T;
3219 +
3220 +/*
3221 + * GMAC DMA Tx Description Word 3 Register
3222 + * GMAC0 offset 0x804C
3223 + * GMAC1 offset 0xC04C
3224 + */
3225 +typedef union {
3226 +       unsigned int bits32;
3227 +       struct txdesc_word3 {
3228 +               unsigned int    mtu_size        : 13;   /* bit 12: 0    Tx Frame Byte Count */
3229 +               unsigned int    reserved        : 16;   /* bit 28:13 */
3230 +               unsigned int    eofie           : 1;    /* bit 29       End of frame interrupt enable */
3231 +               unsigned int    sof_eof         : 2;    /* bit 31:30    11: only one, 10: first, 01: last, 00: linking */
3232 +       } bits;
3233 +} GMAC_TXDESC_3_T;
3234 +#define SOF_EOF_BIT_MASK       0x3fffffff
3235 +#define SOF_BIT                        0x80000000
3236 +#define EOF_BIT                        0x40000000
3237 +#define EOFIE_BIT              BIT(29)
3238 +#define MTU_SIZE_BIT_MASK      0x1fff
3239 +
3240 +/*
3241 + * GMAC Tx Descriptor
3242 + */
3243 +typedef struct {
3244 +       GMAC_TXDESC_0_T word0;
3245 +       GMAC_TXDESC_1_T word1;
3246 +       GMAC_TXDESC_2_T word2;
3247 +       GMAC_TXDESC_3_T word3;
3248 +} GMAC_TXDESC_T;
3249 +
3250 +/*
3251 + * GMAC DMA Rx First Description Address Register
3252 + * GMAC0 offset 0x8058
3253 + * GMAC1 offset 0xC058
3254 + */
3255 +typedef union {
3256 +       unsigned int bits32;
3257 +       struct bit_8058 {
3258 +               unsigned int reserved           :  3;   /* bit 2:0 */
3259 +               unsigned int rd_busy            :  1;   /* bit 3        1-RxDMA busy; 0-RxDMA idle */
3260 +               unsigned int rd_first_des_ptr   : 28;   /* bit 31:4 first descriptor address */
3261 +       } bits;
3262 +} GMAC_RXDMA_FIRST_DESC_T;
3263 +
3264 +/*
3265 + * GMAC DMA Rx Current Description Address Register
3266 + * GMAC0 offset 0x805C
3267 + * GMAC1 offset 0xC05C
3268 + */
3269 +typedef union {
3270 +       unsigned int bits32;
3271 +       struct bit_805C {
3272 +               unsigned int reserved           :  4;   /* bit 3:0 */
3273 +               unsigned int rd_curr_des_ptr    : 28;   /* bit 31:4 current descriptor address */
3274 +       } bits;
3275 +} GMAC_RXDMA_CURR_DESC_T;
3276 +
3277 +/*
3278 + * GMAC DMA Rx Description Word 0 Register
3279 + * GMAC0 offset 0x8060
3280 + * GMAC1 offset 0xC060
3281 + */
3282 +typedef union {
3283 +       unsigned int bits32;
3284 +       struct bit_8060 {
3285 +               unsigned int buffer_size        : 16;   /* bit 15:0  number of descriptors used for the current frame */
3286 +               unsigned int desc_count         : 6;    /* bit 21:16 number of descriptors used for the current frame */
3287 +               unsigned int status             : 4;    /* bit 24:22 Status of rx frame */
3288 +               unsigned int chksum_status      : 3;    /* bit 28:26 Check Sum Status */
3289 +               unsigned int perr               : 1;    /* bit 29        protocol error during processing this descriptor */
3290 +               unsigned int derr               : 1;    /* bit 30        data error during processing this descriptor */
3291 +               unsigned int drop               : 1;    /* bit 31        TOE/CIS Queue Full dropped packet to default queue */
3292 +       } bits;
3293 +} GMAC_RXDESC_0_T;
3294 +
3295 +#define                GMAC_RXDESC_0_T_derr                    BIT(30)
3296 +#define                GMAC_RXDESC_0_T_perr                    BIT(29)
3297 +#define                GMAC_RXDESC_0_T_chksum_status(x)        BIT((x+26))
3298 +#define                GMAC_RXDESC_0_T_status(x)               BIT((x+22))
3299 +#define                GMAC_RXDESC_0_T_desc_count(x)           BIT((x+16))
3300 +
3301 +#define        RX_CHKSUM_IP_UDP_TCP_OK                 0
3302 +#define        RX_CHKSUM_IP_OK_ONLY                    1
3303 +#define        RX_CHKSUM_NONE                          2
3304 +#define        RX_CHKSUM_IP_ERR_UNKNOWN                4
3305 +#define        RX_CHKSUM_IP_ERR                        5
3306 +#define        RX_CHKSUM_TCP_UDP_ERR                   6
3307 +#define RX_CHKSUM_NUM                          8
3308 +
3309 +#define RX_STATUS_GOOD_FRAME                   0
3310 +#define RX_STATUS_TOO_LONG_GOOD_CRC            1
3311 +#define RX_STATUS_RUNT_FRAME                   2
3312 +#define RX_STATUS_SFD_NOT_FOUND                        3
3313 +#define RX_STATUS_CRC_ERROR                    4
3314 +#define RX_STATUS_TOO_LONG_BAD_CRC             5
3315 +#define RX_STATUS_ALIGNMENT_ERROR              6
3316 +#define RX_STATUS_TOO_LONG_BAD_ALIGN           7
3317 +#define RX_STATUS_RX_ERR                       8
3318 +#define RX_STATUS_DA_FILTERED                  9
3319 +#define RX_STATUS_BUFFER_FULL                  10
3320 +#define RX_STATUS_NUM                          16
3321 +
3322 +#define RX_ERROR_LENGTH(s) \
3323 +       ((s) == RX_STATUS_TOO_LONG_GOOD_CRC || \
3324 +        (s) == RX_STATUS_TOO_LONG_BAD_CRC || \
3325 +        (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
3326 +#define RX_ERROR_OVER(s) \
3327 +       ((s) == RX_STATUS_BUFFER_FULL)
3328 +#define RX_ERROR_CRC(s) \
3329 +       ((s) == RX_STATUS_CRC_ERROR || \
3330 +        (s) == RX_STATUS_TOO_LONG_BAD_CRC)
3331 +#define RX_ERROR_FRAME(s) \
3332 +       ((s) == RX_STATUS_ALIGNMENT_ERROR || \
3333 +        (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
3334 +#define RX_ERROR_FIFO(s) \
3335 +       (0)
3336 +
3337 +/*
3338 + * GMAC DMA Rx Description Word 1 Register
3339 + * GMAC0 offset 0x8064
3340 + * GMAC1 offset 0xC064
3341 + */
3342 +typedef union {
3343 +       unsigned int bits32;
3344 +       struct rxdesc_word1 {
3345 +               unsigned int    byte_count      : 16;   /* bit 15: 0    Rx Frame Byte Count */
3346 +               unsigned int    sw_id           : 16;   /* bit 31:16    Software ID */
3347 +       } bits;
3348 +} GMAC_RXDESC_1_T;
3349 +
3350 +/*
3351 + * GMAC DMA Rx Description Word 2 Register
3352 + * GMAC0 offset 0x8068
3353 + * GMAC1 offset 0xC068
3354 + */
3355 +typedef union {
3356 +       unsigned int    bits32;
3357 +       unsigned int    buf_adr;
3358 +} GMAC_RXDESC_2_T;
3359 +
3360 +#define RX_INSERT_NONE         0
3361 +#define RX_INSERT_1_BYTE       1
3362 +#define RX_INSERT_2_BYTE       2
3363 +#define RX_INSERT_3_BYTE       3
3364 +
3365 +/*
3366 + * GMAC DMA Rx Description Word 3 Register
3367 + * GMAC0 offset 0x806C
3368 + * GMAC1 offset 0xC06C
3369 + */
3370 +typedef union {
3371 +       unsigned int bits32;
3372 +       struct rxdesc_word3 {
3373 +               unsigned int    l3_offset       : 8;    /* bit 7: 0     L3 data offset */
3374 +               unsigned int    l4_offset       : 8;    /* bit 15: 8    L4 data offset */
3375 +               unsigned int    l7_offset       : 8;    /* bit 23: 16   L7 data offset */
3376 +               unsigned int    dup_ack         : 1;    /* bit 24       Duplicated ACK detected */
3377 +               unsigned int    abnormal        : 1;    /* bit 25       abnormal case found */
3378 +               unsigned int    option          : 1;    /* bit 26       IPV4 option or IPV6 extension header */
3379 +               unsigned int    out_of_seq      : 1;    /* bit 27       Out of Sequence packet */
3380 +               unsigned int    ctrl_flag       : 1;    /* bit 28       Control Flag is present */
3381 +               unsigned int    eofie           : 1;    /* bit 29       End of frame interrupt enable */
3382 +               unsigned int    sof_eof         : 2;    /* bit 31:30    11: only one, 10: first, 01: last, 00: linking */
3383 +       } bits;
3384 +} GMAC_RXDESC_3_T;
3385 +
3386 +/*
3387 + * GMAC Rx Descriptor
3388 + */
3389 +typedef struct {
3390 +       GMAC_RXDESC_0_T word0;
3391 +       GMAC_RXDESC_1_T word1;
3392 +       GMAC_RXDESC_2_T word2;
3393 +       GMAC_RXDESC_3_T word3;
3394 +} GMAC_RXDESC_T;
3395 +
3396 +/*
3397 + * GMAC Hash Engine Enable/Action Register 0 Offset Register
3398 + * GMAC0 offset 0x8070
3399 + * GMAC1 offset 0xC070
3400 + */
3401 +typedef union {
3402 +       unsigned int bits32;
3403 +       struct bit_8070 {
3404 +               unsigned int    mr0hel          : 6;    /* bit 5:0      match rule 0 hash entry size */
3405 +               unsigned int    mr0_action      : 5;    /* bit 10:6     Matching Rule 0 action offset */
3406 +               unsigned int    reserved0       : 4;    /* bit 14:11 */
3407 +               unsigned int    mr0en           : 1;    /* bit 15       Enable Matching Rule 0 */
3408 +               unsigned int    mr1hel          : 6;    /* bit 21:16    match rule 1 hash entry size */
3409 +               unsigned int    mr1_action      : 5;    /* bit 26:22    Matching Rule 1 action offset */
3410 +               unsigned int    timing          : 3;    /* bit 29:27 */
3411 +               unsigned int    reserved1       : 1;    /* bit 30 */
3412 +               unsigned int    mr1en           : 1;    /* bit 31       Enable Matching Rule 1 */
3413 +       } bits;
3414 +} GMAC_HASH_ENABLE_REG0_T;
3415 +
3416 +/*
3417 + * GMAC Hash Engine Enable/Action Register 1 Offset Register
3418 + * GMAC0 offset 0x8074
3419 + * GMAC1 offset 0xC074
3420 + */
3421 +typedef union {
3422 +       unsigned int bits32;
3423 +       struct bit_8074 {
3424 +               unsigned int    mr2hel          : 6;    /* bit 5:0      match rule 2 hash entry size */
3425 +               unsigned int    mr2_action      : 5;    /* bit 10:6     Matching Rule 2 action offset */
3426 +               unsigned int    reserved2       : 4;    /* bit 14:11 */
3427 +               unsigned int    mr2en           : 1;    /* bit 15       Enable Matching Rule 2 */
3428 +               unsigned int    mr3hel          : 6;    /* bit 21:16    match rule 3 hash entry size */
3429 +               unsigned int    mr3_action      : 5;    /* bit 26:22    Matching Rule 3 action offset */
3430 +               unsigned int    reserved1       : 4;    /* bit 30:27 */
3431 +               unsigned int    mr3en           : 1;    /* bit 31       Enable Matching Rule 3 */
3432 +       } bits;
3433 +} GMAC_HASH_ENABLE_REG1_T;
3434 +
3435 +/*
3436 + * GMAC Matching Rule Control Register 0
3437 + * GMAC0 offset 0x8078
3438 + * GMAC1 offset 0xC078
3439 + */
3440 +typedef union {
3441 +       unsigned int bits32;
3442 +       struct bit_8078 {
3443 +               unsigned int    sprx            : 8;    /* bit 7:0      Support Protocol Register 7:0 */
3444 +               unsigned int    reserved2       : 4;    /* bit 11:8 */
3445 +               unsigned int    tos_traffic     : 1;    /* bit 12       IPV4 TOS or IPV6 Traffice Class */
3446 +               unsigned int    flow_lable      : 1;    /* bit 13       IPV6 Flow label */
3447 +               unsigned int    ip_hdr_len      : 1;    /* bit 14       IPV4 Header length */
3448 +               unsigned int    ip_version      : 1;    /* bit 15       0: IPV4, 1: IPV6 */
3449 +               unsigned int    reserved1       : 3;    /* bit 18:16 */
3450 +               unsigned int    pppoe           : 1;    /* bit 19       PPPoE Session ID enable */
3451 +               unsigned int    vlan            : 1;    /* bit 20       VLAN ID enable */
3452 +               unsigned int    ether_type      : 1;    /* bit 21       Ethernet type enable */
3453 +               unsigned int    sa              : 1;    /* bit 22       MAC SA enable */
3454 +               unsigned int    da              : 1;    /* bit 23       MAC DA enable */
3455 +               unsigned int    priority        : 3;    /* bit 26:24    priority if multi-rules matched */
3456 +               unsigned int    port            : 1;    /* bit 27       PORT ID matching enable */
3457 +               unsigned int    l7              : 1;    /* bit 28       L7 matching enable */
3458 +               unsigned int    l4              : 1;    /* bit 29       L4 matching enable */
3459 +               unsigned int    l3              : 1;    /* bit 30       L3 matching enable */
3460 +               unsigned int    l2              : 1;    /* bit 31       L2 matching enable */
3461 +       } bits;
3462 +} GMAC_MRxCR0_T;
3463 +
3464 +#define MR_L2_BIT              BIT(31)
3465 +#define MR_L3_BIT              BIT(30)
3466 +#define MR_L4_BIT              BIT(29)
3467 +#define MR_L7_BIT              BIT(28)
3468 +#define MR_PORT_BIT            BIT(27)
3469 +#define MR_PRIORITY_BIT                BIT(26)
3470 +#define MR_DA_BIT              BIT(23)
3471 +#define MR_SA_BIT              BIT(22)
3472 +#define MR_ETHER_TYPE_BIT      BIT(21)
3473 +#define MR_VLAN_BIT            BIT(20)
3474 +#define MR_PPPOE_BIT           BIT(19)
3475 +#define MR_IP_VER_BIT          BIT(15)
3476 +#define MR_IP_HDR_LEN_BIT      BIT(14)
3477 +#define MR_FLOW_LABLE_BIT      BIT(13)
3478 +#define MR_TOS_TRAFFIC_BIT     BIT(12)
3479 +#define MR_SPR_BIT(x)          BIT(x)
3480 +#define MR_SPR_BITS            0xff
3481 +
3482 +/*
3483 + * GMAC Matching Rule Control Register 1
3484 + * GMAC0 offset 0x807C
3485 + * GMAC1 offset 0xC07C
3486 + */
3487 +typedef union {
3488 +       unsigned int bits32;
3489 +       struct bit_807C {
3490 +               unsigned int    l4_byte0_15     : 16;   /* bit 15: 0 */
3491 +               unsigned int    dip_netmask     : 7;    /* bit 22:16    Dest IP net mask, number of mask bits */
3492 +               unsigned int    dip             : 1;    /* bit 23               Dest IP */
3493 +               unsigned int    sip_netmask     : 7;    /* bit 30:24    Srce IP net mask, number of mask bits */
3494 +               unsigned int    sip             : 1;    /* bit 31               Srce IP */
3495 +       } bits;
3496 +} GMAC_MRxCR1_T;
3497 +
3498 +/*
3499 + * GMAC Matching Rule Control Register 2
3500 + * GMAC0 offset 0x8080
3501 + * GMAC1 offset 0xC080
3502 + */
3503 +typedef union {
3504 +       unsigned int bits32;
3505 +       struct bit_8080 {
3506 +               unsigned int    l7_byte0_23     : 24;   /* bit 23:0 */
3507 +               unsigned int    l4_byte16_24    : 8;    /* bit 31: 24 */
3508 +       } bits;
3509 +} GMAC_MRxCR2_T;
3510 +
3511 +/*
3512 + * GMAC Support registers
3513 + * GMAC0 offset 0x80A8
3514 + * GMAC1 offset 0xC0A8
3515 + */
3516 +typedef union {
3517 +       unsigned int bits32;
3518 +       struct bit_80A8 {
3519 +               unsigned int    protocol        : 8;    /* bit 7:0              Supported protocol */
3520 +               unsigned int    swap            : 3;    /* bit 10:8             Swap */
3521 +               unsigned int    reserved        : 21;   /* bit 31:11 */
3522 +       } bits;
3523 +} GMAC_SPR_T;
3524 +
3525 +/*
3526 + * GMAC_AHB_WEIGHT registers
3527 + * GMAC0 offset 0x80C8
3528 + * GMAC1 offset 0xC0C8
3529 + */
3530 +typedef union {
3531 +       unsigned int bits32;
3532 +       struct bit_80C8 {
3533 +               unsigned int    hash_weight     : 5;    /* 4:0 */
3534 +               unsigned int    rx_weight       : 5;    /* 9:5 */
3535 +               unsigned int    tx_weight       : 5;    /* 14:10 */
3536 +               unsigned int    pre_req         : 5;    /* 19:15 Rx Data Pre Request FIFO Threshold */
3537 +               unsigned int    tqDV_threshold  : 5;    /* 24:20 DMA TqCtrl to Start tqDV FIFO Threshold */
3538 +               unsigned int    reserved        : 7;    /* 31:25 */
3539 +       } bits;
3540 +} GMAC_AHB_WEIGHT_T;
3541 +
3542 +/*
3543 + * the register structure of GMAC
3544 + */
3545 +
3546 +/*
3547 + * GMAC RX FLTR
3548 + * GMAC0 Offset 0xA00C
3549 + * GMAC1 Offset 0xE00C
3550 + */
3551 +typedef union {
3552 +       unsigned int bits32;
3553 +       struct bit1_000c {
3554 +               unsigned int unicast            :  1;   /* enable receive of unicast frames that are sent to STA address */
3555 +               unsigned int multicast          :  1;   /* enable receive of multicast frames that pass multicast filter */
3556 +               unsigned int broadcast          :  1;   /* enable receive of broadcast frames */
3557 +               unsigned int promiscuous        :  1;   /* enable receive of all frames */
3558 +               unsigned int error              :  1;   /* enable receive of all error frames */
3559 +               unsigned int                    : 27;
3560 +       } bits;
3561 +} GMAC_RX_FLTR_T;
3562 +
3563 +/*
3564 + * GMAC Configuration 0
3565 + * GMAC0 Offset 0xA018
3566 + * GMAC1 Offset 0xE018
3567 + */
3568 +typedef union {
3569 +       unsigned int bits32;
3570 +       struct bit1_0018 {
3571 +               unsigned int dis_tx             :  1;   /* 0: disable transmit */
3572 +               unsigned int dis_rx             :  1;   /* 1: disable receive */
3573 +               unsigned int loop_back          :  1;   /* 2: transmit data loopback enable */
3574 +               unsigned int flow_ctrl          :  1;   /* 3: flow control also trigged by Rx queues */
3575 +               unsigned int adj_ifg            :  4;   /* 4-7: adjust IFG from 96+/-56 */
3576 +               unsigned int max_len            :  3;   /* 8-10 maximum receive frame length allowed */
3577 +               unsigned int dis_bkoff          :  1;   /* 11: disable back-off function */
3578 +               unsigned int dis_col            :  1;   /* 12: disable 16 collisions abort function */
3579 +               unsigned int sim_test           :  1;   /* 13: speed up timers in simulation */
3580 +               unsigned int rx_fc_en           :  1;   /* 14: RX flow control enable */
3581 +               unsigned int tx_fc_en           :  1;   /* 15: TX flow control enable */
3582 +               unsigned int rgmii_en           :  1;   /* 16: RGMII in-band status enable */
3583 +               unsigned int ipv4_rx_chksum     :  1;   /* 17: IPv4 RX Checksum enable */
3584 +               unsigned int ipv6_rx_chksum     :  1;   /* 18: IPv6 RX Checksum enable */
3585 +               unsigned int rx_tag_remove      :  1;   /* 19: Remove Rx VLAN tag */
3586 +               unsigned int rgmm_edge          :  1;   /* 20 */
3587 +               unsigned int rxc_inv            :  1;   /* 21 */
3588 +               unsigned int ipv6_exthdr_order  :  1;   /* 22 */
3589 +               unsigned int rx_err_detect      :  1;   /* 23 */
3590 +               unsigned int port0_chk_hwq      :  1;   /* 24 */
3591 +               unsigned int port1_chk_hwq      :  1;   /* 25 */
3592 +               unsigned int port0_chk_toeq     :  1;   /* 26 */
3593 +               unsigned int port1_chk_toeq     :  1;   /* 27 */
3594 +               unsigned int port0_chk_classq   :  1;   /* 28 */
3595 +               unsigned int port1_chk_classq   :  1;   /* 29 */
3596 +               unsigned int reserved           :  2;   /* 31 */
3597 +       } bits;
3598 +} GMAC_CONFIG0_T;
3599 +
3600 +#define CONFIG0_TX_RX_DISABLE  (BIT(1)|BIT(0))
3601 +#define CONFIG0_RX_CHKSUM      (BIT(18)|BIT(17))
3602 +#define CONFIG0_FLOW_RX                (BIT(14))
3603 +#define CONFIG0_FLOW_TX                (BIT(15))
3604 +#define CONFIG0_FLOW_TX_RX     (BIT(14)|BIT(15))
3605 +#define CONFIG0_FLOW_CTL       (BIT(14)|BIT(15))
3606 +
3607 +#define CONFIG0_MAXLEN_SHIFT   8
3608 +#define CONFIG0_MAXLEN_MASK    (7 << CONFIG0_MAXLEN_SHIFT)
3609 +#define  CONFIG0_MAXLEN_1536   0
3610 +#define  CONFIG0_MAXLEN_1518   1
3611 +#define  CONFIG0_MAXLEN_1522   2
3612 +#define  CONFIG0_MAXLEN_1542   3
3613 +#define  CONFIG0_MAXLEN_9k     4       /* 9212 */
3614 +#define  CONFIG0_MAXLEN_10k    5       /* 10236 */
3615 +#define  CONFIG0_MAXLEN_1518__6        6
3616 +#define  CONFIG0_MAXLEN_1518__7        7
3617 +
3618 +/*
3619 + * GMAC Configuration 1
3620 + * GMAC0 Offset 0xA01C
3621 + * GMAC1 Offset 0xE01C
3622 + */
3623 +typedef union {
3624 +       unsigned int bits32;
3625 +       struct bit1_001c {
3626 +               unsigned int set_threshold      : 8;    /* flow control set threshold */
3627 +               unsigned int rel_threshold      : 8;    /* flow control release threshold */
3628 +               unsigned int reserved           : 16;
3629 +       } bits;
3630 +} GMAC_CONFIG1_T;
3631 +
3632 +#define GMAC_FLOWCTRL_SET_MAX          32
3633 +#define GMAC_FLOWCTRL_SET_MIN          0
3634 +#define GMAC_FLOWCTRL_RELEASE_MAX      32
3635 +#define GMAC_FLOWCTRL_RELEASE_MIN      0
3636 +
3637 +/*
3638 + * GMAC Configuration 2
3639 + * GMAC0 Offset 0xA020
3640 + * GMAC1 Offset 0xE020
3641 + */
3642 +typedef union {
3643 +       unsigned int bits32;
3644 +       struct bit1_0020 {
3645 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
3646 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
3647 +       } bits;
3648 +} GMAC_CONFIG2_T;
3649 +
3650 +/*
3651 + * GMAC Configuration 3
3652 + * GMAC0 Offset 0xA024
3653 + * GMAC1 Offset 0xE024
3654 + */
3655 +typedef union {
3656 +       unsigned int bits32;
3657 +       struct bit1_0024 {
3658 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
3659 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
3660 +       } bits;
3661 +} GMAC_CONFIG3_T;
3662 +
3663 +
3664 +/*
3665 + * GMAC STATUS
3666 + * GMAC0 Offset 0xA02C
3667 + * GMAC1 Offset 0xE02C
3668 + */
3669 +typedef union {
3670 +       unsigned int bits32;
3671 +       struct bit1_002c {
3672 +               unsigned int link               :  1;   /* link status */
3673 +               unsigned int speed              :  2;   /* link speed(00->2.5M 01->25M 10->125M) */
3674 +               unsigned int duplex             :  1;   /* duplex mode */
3675 +               unsigned int reserved           :  1;
3676 +               unsigned int mii_rmii           :  2;   /* PHY interface type */
3677 +               unsigned int                    : 25;
3678 +       } bits;
3679 +} GMAC_STATUS_T;
3680 +
3681 +#define GMAC_SPEED_10                  0
3682 +#define GMAC_SPEED_100                 1
3683 +#define GMAC_SPEED_1000                        2
3684 +
3685 +#define GMAC_PHY_MII                   0
3686 +#define GMAC_PHY_GMII                  1
3687 +#define GMAC_PHY_RGMII_100_10          2
3688 +#define GMAC_PHY_RGMII_1000            3
3689 +
3690 +/*
3691 + * Queue Header
3692 + *     (1) TOE Queue Header
3693 + *     (2) Non-TOE Queue Header
3694 + *     (3) Interrupt Queue Header
3695 + *
3696 + * memory Layout
3697 + *     TOE Queue Header
3698 + *                  0x60003000 +---------------------------+ 0x0000
3699 + *                             |     TOE Queue 0 Header    |
3700 + *                             |         8 * 4 Bytes       |
3701 + *                             +---------------------------+ 0x0020
3702 + *                             |     TOE Queue 1 Header    |
3703 + *                             |         8 * 4 Bytes       |
3704 + *                             +---------------------------+ 0x0040
3705 + *                             |          ......           |
3706 + *                             |                           |
3707 + *                             +---------------------------+
3708 + *
3709 + *     Non TOE Queue Header
3710 + *                  0x60002000 +---------------------------+ 0x0000
3711 + *                             |   Default Queue 0 Header  |
3712 + *                             |         2 * 4 Bytes       |
3713 + *                             +---------------------------+ 0x0008
3714 + *                             |   Default Queue 1 Header  |
3715 + *                             |         2 * 4 Bytes       |
3716 + *                             +---------------------------+ 0x0010
3717 + *                             |   Classification Queue 0  |
3718 + *                             |         2 * 4 Bytes       |
3719 + *                             +---------------------------+
3720 + *                             |   Classification Queue 1  |
3721 + *                             |         2 * 4 Bytes       |
3722 + *                             +---------------------------+ (n * 8 + 0x10)
3723 + *                             |               ...         |
3724 + *                             |         2 * 4 Bytes       |
3725 + *                             +---------------------------+ (13 * 8 + 0x10)
3726 + *                             |   Classification Queue 13 |
3727 + *                             |         2 * 4 Bytes       |
3728 + *                             +---------------------------+ 0x80
3729 + *                             |      Interrupt Queue 0    |
3730 + *                             |         2 * 4 Bytes       |
3731 + *                             +---------------------------+
3732 + *                             |      Interrupt Queue 1    |
3733 + *                             |         2 * 4 Bytes       |
3734 + *                             +---------------------------+
3735 + *                             |      Interrupt Queue 2    |
3736 + *                             |         2 * 4 Bytes       |
3737 + *                             +---------------------------+
3738 + *                             |      Interrupt Queue 3    |
3739 + *                             |         2 * 4 Bytes       |
3740 + *                             +---------------------------+
3741 + *
3742 + */
3743 +#define TOE_QUEUE_HDR_ADDR(n)          (TOE_TOE_QUE_HDR_BASE + n * 32)
3744 +#define TOE_Q_HDR_AREA_END             (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
3745 +#define TOE_DEFAULT_Q_HDR_BASE(x)      (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
3746 +#define TOE_CLASS_Q_HDR_BASE           (TOE_NONTOE_QUE_HDR_BASE + 0x10)
3747 +#define TOE_INTR_Q_HDR_BASE            (TOE_NONTOE_QUE_HDR_BASE + 0x80)
3748 +#define INTERRUPT_QUEUE_HDR_ADDR(n)    (TOE_INTR_Q_HDR_BASE + n * 8)
3749 +#define NONTOE_Q_HDR_AREA_END          (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
3750 +/*
3751 + * TOE Queue Header Word 0
3752 + */
3753 +typedef union {
3754 +       unsigned int bits32;
3755 +       unsigned int base_size;
3756 +} TOE_QHDR0_T;
3757 +
3758 +#define TOE_QHDR0_BASE_MASK    (~0x0f)
3759 +
3760 +/*
3761 + * TOE Queue Header Word 1
3762 + */
3763 +typedef union {
3764 +       unsigned int bits32;
3765 +       struct bit_qhdr1 {
3766 +               unsigned int rptr       : 16;   /* bit 15:0 */
3767 +               unsigned int wptr       : 16;   /* bit 31:16 */
3768 +       } bits;
3769 +} TOE_QHDR1_T;
3770 +
3771 +/*
3772 + * TOE Queue Header Word 2
3773 + */
3774 +typedef union {
3775 +       unsigned int bits32;
3776 +       struct bit_qhdr2 {
3777 +               unsigned int TotalPktSize       : 17;   /* bit 16: 0    Total packet size */
3778 +               unsigned int reserved           : 7;    /* bit 23:17 */
3779 +               unsigned int dack               : 1;    /* bit 24       1: Duplicated ACK */
3780 +               unsigned int abn                : 1;    /* bit 25       1: Abnormal case Found */
3781 +               unsigned int tcp_opt            : 1;    /* bit 26       1: Have TCP option */
3782 +               unsigned int ip_opt             : 1;    /* bit 27       1: have IPV4 option or IPV6 Extension header */
3783 +               unsigned int sat                : 1;    /* bit 28       1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold */
3784 +               unsigned int osq                : 1;    /* bit 29       1: out of sequence */
3785 +               unsigned int ctl                : 1;    /* bit 30       1: have control flag bits (except ack) */
3786 +               unsigned int usd                : 1;    /* bit 31       0: if no data assembled yet */
3787 +       } bits;
3788 +} TOE_QHDR2_T;
3789 +
3790 +/*
3791 + * TOE Queue Header Word 3
3792 + */
3793 +typedef union {
3794 +       unsigned int bits32;
3795 +       unsigned int seq_num;
3796 +} TOE_QHDR3_T;
3797 +
3798 +/*
3799 + * TOE Queue Header Word 4
3800 + */
3801 +typedef union {
3802 +       unsigned int bits32;
3803 +       unsigned int ack_num;
3804 +} TOE_QHDR4_T;
3805 +
3806 +/*
3807 + * TOE Queue Header Word 5
3808 + */
3809 +typedef union {
3810 +       unsigned int bits32;
3811 +       struct bit_qhdr5 {
3812 +               unsigned int AckCnt     : 16;   /* bit 15:0 */
3813 +               unsigned int SeqCnt     : 16;   /* bit 31:16 */
3814 +       } bits;
3815 +} TOE_QHDR5_T;
3816 +
3817 +/*
3818 + * TOE Queue Header Word 6
3819 + */
3820 +typedef union {
3821 +       unsigned int bits32;
3822 +       struct bit_qhdr6 {
3823 +               unsigned int WinSize    : 16;   /* bit 15:0 */
3824 +               unsigned int iq_num     : 2;    /* bit 17:16 */
3825 +               unsigned int MaxPktSize : 14;   /* bit 31:18 */
3826 +       } bits;
3827 +} TOE_QHDR6_T;
3828 +
3829 +/*
3830 + * TOE Queue Header Word 7
3831 + */
3832 +typedef union {
3833 +       unsigned int bits32;
3834 +       struct bit_qhdr7 {
3835 +               unsigned int AckThreshold       : 16;   /* bit 15:0 */
3836 +               unsigned int SeqThreshold       : 16;   /* bit 31:16 */
3837 +       } bits;
3838 +} TOE_QHDR7_T;
3839 +
3840 +/*
3841 + * TOE Queue Header
3842 + */
3843 +typedef struct {
3844 +       TOE_QHDR0_T             word0;
3845 +       TOE_QHDR1_T             word1;
3846 +       TOE_QHDR2_T             word2;
3847 +       TOE_QHDR3_T             word3;
3848 +       TOE_QHDR4_T             word4;
3849 +       TOE_QHDR5_T             word5;
3850 +       TOE_QHDR6_T             word6;
3851 +       TOE_QHDR7_T             word7;
3852 +} TOE_QHDR_T;
3853 +
3854 +/*
3855 + * NONTOE Queue Header Word 0
3856 + */
3857 +typedef union {
3858 +       unsigned int bits32;
3859 +       unsigned int base_size;
3860 +} NONTOE_QHDR0_T;
3861 +
3862 +#define NONTOE_QHDR0_BASE_MASK (~0x0f)
3863 +
3864 +/*
3865 + * NONTOE Queue Header Word 1
3866 + */
3867 +typedef union {
3868 +       unsigned int bits32;
3869 +       struct bit_nonqhdr1 {
3870 +               unsigned int rptr       : 16;   /* bit 15:0 */
3871 +               unsigned int wptr       : 16;   /* bit 31:16 */
3872 +       } bits;
3873 +} NONTOE_QHDR1_T;
3874 +
3875 +/*
3876 + * Non-TOE Queue Header
3877 + */
3878 +typedef struct {
3879 +       NONTOE_QHDR0_T          word0;
3880 +       NONTOE_QHDR1_T          word1;
3881 +} NONTOE_QHDR_T;
3882 +
3883 +/*
3884 + * Interrupt Queue Header Word 0
3885 + */
3886 +typedef union {
3887 +       unsigned int bits32;
3888 +       struct bit_intrqhdr0 {
3889 +               unsigned int win_size   : 16;   /* bit 15:0     Descriptor Ring Size */
3890 +               unsigned int wptr       : 16;   /* bit 31:16    Write Pointer where hw stopped */
3891 +       } bits;
3892 +} INTR_QHDR0_T;
3893 +
3894 +/*
3895 + * Interrupt Queue Header Word 1
3896 + */
3897 +typedef union {
3898 +       unsigned int bits32;
3899 +       struct bit_intrqhdr1 {
3900 +               unsigned int TotalPktSize       : 17;   /* bit 16: 0    Total packet size */
3901 +               unsigned int tcp_qid            : 8;    /* bit 24:17    TCP Queue ID */
3902 +               unsigned int dack               : 1;    /* bit 25       1: Duplicated ACK */
3903 +               unsigned int abn                : 1;    /* bit 26       1: Abnormal case Found */
3904 +               unsigned int tcp_opt            : 1;    /* bit 27       1: Have TCP option */
3905 +               unsigned int ip_opt             : 1;    /* bit 28       1: have IPV4 option or IPV6 Extension header */
3906 +               unsigned int sat                : 1;    /* bit 29       1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold */
3907 +               unsigned int osq                : 1;    /* bit 30       1: out of sequence */
3908 +               unsigned int ctl                : 1;    /* bit 31       1: have control flag bits (except ack) */
3909 +       } bits;
3910 +} INTR_QHDR1_T;
3911 +
3912 +/*
3913 + * Interrupt Queue Header Word 2
3914 + */
3915 +typedef union {
3916 +       unsigned int bits32;
3917 +       unsigned int seq_num;
3918 +} INTR_QHDR2_T;
3919 +
3920 +/*
3921 + * Interrupt Queue Header Word 3
3922 + */
3923 +typedef union {
3924 +       unsigned int bits32;
3925 +       unsigned int ack_num;
3926 +} INTR_QHDR3_T;
3927 +
3928 +/*
3929 + * Interrupt Queue Header Word 4
3930 + */
3931 +typedef union {
3932 +       unsigned int bits32;
3933 +       struct bit_intrqhdr4 {
3934 +               unsigned int AckCnt             : 16;   /* bit 15:0     Ack# change since last ack# intr. */
3935 +               unsigned int SeqCnt             : 16;   /* bit 31:16    Seq# change since last seq# intr. */
3936 +       } bits;
3937 +} INTR_QHDR4_T;
3938 +
3939 +/*
3940 + * Interrupt Queue Header
3941 + */
3942 +typedef struct {
3943 +       INTR_QHDR0_T            word0;
3944 +       INTR_QHDR1_T            word1;
3945 +       INTR_QHDR2_T            word2;
3946 +       INTR_QHDR3_T            word3;
3947 +       INTR_QHDR4_T            word4;
3948 +       unsigned int            word5;
3949 +       unsigned int            word6;
3950 +       unsigned int            word7;
3951 +} INTR_QHDR_T;
3952 +
3953 +#endif /* _GMAC_SL351x_H */