1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
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19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
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29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
38 * This file contains the functions to manage Queue Heads and Queue
39 * Transfer Descriptors.
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/device.h>
46 #include <linux/errno.h>
47 #include <linux/list.h>
48 #include <linux/interrupt.h>
49 #include <linux/string.h>
50 #include <linux/version.h>
52 #include <mach/irqs.h>
54 #include "otg_driver.h"
59 * This function allocates and initializes a QH.
61 * @param hcd The HCD state structure for the DWC OTG controller.
62 * @param[in] urb Holds the information about the device/endpoint that we need
63 * to initialize the QH.
65 * @return Returns pointer to the newly allocated QH, or NULL on error. */
66 dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, struct urb *urb)
71 /** @todo add memflags argument */
72 qh = dwc_otg_hcd_qh_alloc ();
77 dwc_otg_hcd_qh_init (hcd, qh, urb);
81 /** Free each QTD in the QH's QTD-list then free the QH. QH should already be
82 * removed from a list. QTD list should already be empty if called from URB
85 * @param[in] hcd HCD instance.
86 * @param[in] qh The QH to free.
88 void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
91 struct list_head *pos;
92 //unsigned long flags;
94 /* Free each QTD in the QTD list */
97 //the spinlock is locked before this function get called,
98 //but in case the lock is needed, the check function is preserved
100 //but in non-SMP mode, all spinlock is lockable.
101 //don't do the test in non-SMP mode
103 if(spin_trylock(&hcd->lock)) {
104 printk("%s: It is not supposed to be lockable!!\n",__func__);
108 // SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
109 for (pos = qh->qtd_list.next;
110 pos != &qh->qtd_list;
111 pos = qh->qtd_list.next)
114 qtd = dwc_list_to_qtd (pos);
115 dwc_otg_hcd_qtd_free (qtd);
117 // SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
123 /** Initializes a QH structure.
125 * @param[in] hcd The HCD state structure for the DWC OTG controller.
126 * @param[in] qh The QH to init.
127 * @param[in] urb Holds the information about the device/endpoint that we need
128 * to initialize the QH. */
129 #define SCHEDULE_SLOP 10
130 void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb)
133 memset (qh, 0, sizeof (dwc_otg_qh_t));
136 switch (usb_pipetype(urb->pipe)) {
138 qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
141 qh->ep_type = USB_ENDPOINT_XFER_BULK;
143 case PIPE_ISOCHRONOUS:
144 qh->ep_type = USB_ENDPOINT_XFER_ISOC;
147 qh->ep_type = USB_ENDPOINT_XFER_INT;
151 qh->ep_is_in = usb_pipein(urb->pipe) ? 1 : 0;
153 qh->data_toggle = DWC_OTG_HC_PID_DATA0;
154 qh->maxp = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe)));
155 INIT_LIST_HEAD(&qh->qtd_list);
156 INIT_LIST_HEAD(&qh->qh_list_entry);
158 qh->speed = urb->dev->speed;
160 /* FS/LS Enpoint on HS Hub
161 * NOT virtual root hub */
163 if (((urb->dev->speed == USB_SPEED_LOW) ||
164 (urb->dev->speed == USB_SPEED_FULL)) &&
165 (urb->dev->tt) && (urb->dev->tt->hub) && (urb->dev->tt->hub->devnum != 1))
167 DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
168 usb_pipeendpoint(urb->pipe), urb->dev->tt->hub->devnum,
173 if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
174 qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
175 /* Compute scheduling parameters once and save them. */
178 /** @todo Account for split transfers in the bus time. */
179 int bytecount = dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
180 qh->usecs = NS_TO_US(usb_calc_bus_time(urb->dev->speed,
181 usb_pipein(urb->pipe),
182 (qh->ep_type == USB_ENDPOINT_XFER_ISOC),
185 /* Start in a slightly future (micro)frame. */
186 qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
188 qh->interval = urb->interval;
190 /* Increase interrupt polling rate for debugging. */
191 if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
195 hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
196 if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
197 ((urb->dev->speed == USB_SPEED_LOW) ||
198 (urb->dev->speed == USB_SPEED_FULL))) {
200 qh->sched_frame |= 0x7;
201 qh->start_split_frame = qh->sched_frame;
206 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
207 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
208 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
210 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
211 usb_pipeendpoint(urb->pipe),
212 usb_pipein(urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
214 qh->nak_frame = 0xffff;
216 switch(urb->dev->speed) {
230 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
232 switch (qh->ep_type) {
233 case USB_ENDPOINT_XFER_ISOC:
234 type = "isochronous";
236 case USB_ENDPOINT_XFER_INT:
239 case USB_ENDPOINT_XFER_CONTROL:
242 case USB_ENDPOINT_XFER_BULK:
249 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",type);
252 if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
253 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
255 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
264 * Microframe scheduler
265 * track the total use in hcd->frame_usecs
266 * keep each qh use in qh->frame_usecs
267 * when surrendering the qh then donate the time back
269 static const u16 max_uframe_usecs[] = { 100, 100, 100, 100, 100, 100, 30, 0 };
272 * called from dwc_otg_hcd.c:dwc_otg_hcd_init
274 int init_hcd_usecs(dwc_otg_hcd_t *hcd)
278 for (i = 0; i < 8; i++)
279 hcd->frame_usecs[i] = max_uframe_usecs[i];
284 static int find_single_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
298 /* At the start hcd->frame_usecs[i] = max_uframe_usecs[i]; */
299 if (utime <= hcd->frame_usecs[i]) {
300 hcd->frame_usecs[i] -= utime;
301 qh->frame_usecs[i] += utime;
318 * use this for FS apps that can span multiple uframes
320 static int find_multi_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
337 if (hcd->frame_usecs[i] <= 0) {
347 * We need n consequtive slots so use j as a start slot.
348 * j plus j+1 must be enough time (for now)
350 xtime = hcd->frame_usecs[i];
351 for (j = i + 1; j < 8; j++) {
353 * if we add this frame remaining time to xtime we may
354 * be OK, if not we need to test j for a complete frame.
356 if ((xtime + hcd->frame_usecs[j]) < utime) {
357 if (hcd->frame_usecs[j] < max_uframe_usecs[j]) {
363 if (xtime >= utime) {
365 j = 8; /* stop loop with a good value ret */
368 /* add the frame time to x time */
369 xtime += hcd->frame_usecs[j];
370 /* we must have a fully available next frame or break */
371 if ((xtime < utime) &&
372 (hcd->frame_usecs[j] == max_uframe_usecs[j])) {
374 j = 8; /* stop loop with a bad value ret */
380 for (j = i; (t_left > 0) && (j < 8); j++) {
381 t_left -= hcd->frame_usecs[j];
383 qh->frame_usecs[j] +=
384 hcd->frame_usecs[j] + t_left;
385 hcd->frame_usecs[j] = -t_left;
389 qh->frame_usecs[j] +=
391 hcd->frame_usecs[j] = 0;
405 static int find_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
409 if (qh->speed == USB_SPEED_HIGH)
410 /* if this is a hs transaction we need a full frame */
411 ret = find_single_uframe(hcd, qh);
413 /* FS transaction may need a sequence of frames */
414 ret = find_multi_uframe(hcd, qh);
420 * Checks that the max transfer size allowed in a host channel is large enough
421 * to handle the maximum data transfer in a single (micro)frame for a periodic
424 * @param hcd The HCD state structure for the DWC OTG controller.
425 * @param qh QH for a periodic endpoint.
427 * @return 0 if successful, negative error code otherwise.
429 static int check_max_xfer_size(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
432 uint32_t max_xfer_size;
433 uint32_t max_channel_xfer_size;
437 max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
438 max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
440 if (max_xfer_size > max_channel_xfer_size) {
441 DWC_NOTICE("%s: Periodic xfer length %d > "
442 "max xfer length for channel %d\n",
443 __func__, max_xfer_size, max_channel_xfer_size);
451 * Schedules an interrupt or isochronous transfer in the periodic schedule.
453 static int schedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
456 struct usb_bus *bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
460 num_channels = hcd->core_if->core_params->host_channels;
462 if ((hcd->periodic_channels < num_channels - 1)) {
463 if (hcd->periodic_channels + hcd->nakking_channels >= num_channels) {
464 /* All non-periodic channels are nakking? Halt
465 * one to make room (as long as there is at
466 * least one channel for non-periodic transfers,
467 * all the blocking non-periodics can time-share
468 * that one channel. */
469 dwc_hc_t *hc = dwc_otg_halt_nakking_channel(hcd);
471 DWC_DEBUGPL(DBG_HCD, "Out of Host Channels for periodic transfer - Halting channel %d (dev %d ep%d%s)\n", hc->hc_num, hc->dev_addr, hc->ep_num, (hc->ep_is_in ? "in" : "out"));
473 /* It could be that all channels are currently occupied,
474 * but in that case one will be freed up soon (either
475 * because it completed or because it was forced to halt
478 status = find_uframe(hcd, qh);
486 /* Set the new frame up */
488 qh->sched_frame &= ~0x7;
489 qh->sched_frame |= (frame & 7);
494 pr_notice("%s: Insufficient periodic bandwidth for "
495 "periodic transfer.\n", __func__);
498 status = check_max_xfer_size(hcd, qh);
500 pr_notice("%s: Channel max transfer size too small "
501 "for periodic transfer.\n", __func__);
504 /* Always start in the inactive schedule. */
505 list_add_tail(&qh->qh_list_entry, &hcd->periodic_sched_inactive);
507 hcd->periodic_channels++;
509 /* Update claimed usecs per (micro)frame. */
510 hcd->periodic_usecs += qh->usecs;
513 * Update average periodic bandwidth claimed and # periodic reqs for
516 bus->bandwidth_allocated += qh->usecs / qh->interval;
518 if (qh->ep_type == USB_ENDPOINT_XFER_INT)
519 bus->bandwidth_int_reqs++;
521 bus->bandwidth_isoc_reqs++;
527 * This function adds a QH to either the non periodic or periodic schedule if
528 * it is not already in the schedule. If the QH is already in the schedule, no
531 * @return 0 if successful, negative error code otherwise.
533 int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
535 //unsigned long flags;
539 //the spinlock is locked before this function get called,
540 //but in case the lock is needed, the check function is preserved
541 //but in non-SMP mode, all spinlock is lockable.
542 //don't do the test in non-SMP mode
544 if(spin_trylock(&hcd->lock)) {
545 printk("%s: It is not supposed to be lockable!!\n",__func__);
549 // SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
551 if (!list_empty(&qh->qh_list_entry)) {
552 /* QH already in a schedule. */
556 /* Add the new QH to the appropriate schedule */
557 if (dwc_qh_is_non_per(qh)) {
558 /* Always start in the inactive schedule. */
559 list_add_tail(&qh->qh_list_entry, &hcd->non_periodic_sched_inactive);
561 status = schedule_periodic(hcd, qh);
565 // SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
571 * Removes an interrupt or isochronous transfer from the periodic schedule.
573 static void deschedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
575 struct usb_bus *bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
578 list_del_init(&qh->qh_list_entry);
580 hcd->periodic_channels--;
582 /* Update claimed usecs per (micro)frame. */
583 hcd->periodic_usecs -= qh->usecs;
584 for (i = 0; i < 8; i++) {
585 hcd->frame_usecs[i] += qh->frame_usecs[i];
586 qh->frame_usecs[i] = 0;
589 * Update average periodic bandwidth claimed and # periodic reqs for
592 bus->bandwidth_allocated -= qh->usecs / qh->interval;
594 if (qh->ep_type == USB_ENDPOINT_XFER_INT)
595 bus->bandwidth_int_reqs--;
597 bus->bandwidth_isoc_reqs--;
601 * Removes a QH from either the non-periodic or periodic schedule. Memory is
604 * @param[in] hcd The HCD state structure.
605 * @param[in] qh QH to remove from schedule. */
606 void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
608 //unsigned long flags;
611 //the spinlock is locked before this function get called,
612 //but in case the lock is needed, the check function is preserved
613 //but in non-SMP mode, all spinlock is lockable.
614 //don't do the test in non-SMP mode
616 if(spin_trylock(&hcd->lock)) {
617 printk("%s: It is not supposed to be lockable!!\n",__func__);
621 // SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
623 if (list_empty(&qh->qh_list_entry)) {
624 /* QH is not in a schedule. */
628 if (dwc_qh_is_non_per(qh)) {
629 if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
630 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
632 list_del_init(&qh->qh_list_entry);
634 deschedule_periodic(hcd, qh);
638 // SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
643 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
644 * non-periodic schedule. The QH is added to the inactive non-periodic
645 * schedule if any QTDs are still attached to the QH.
647 * For periodic QHs, the QH is removed from the periodic queued schedule. If
648 * there are any QTDs still attached to the QH, the QH is added to either the
649 * periodic inactive schedule or the periodic ready schedule and its next
650 * scheduled frame is calculated. The QH is placed in the ready schedule if
651 * the scheduled frame has been reached already. Otherwise it's placed in the
652 * inactive schedule. If there are no QTDs attached to the QH, the QH is
653 * completely removed from the periodic schedule.
655 void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split)
657 if (dwc_qh_is_non_per(qh)) {
658 dwc_otg_hcd_qh_remove(hcd, qh);
659 if (!list_empty(&qh->qtd_list)) {
660 /* Add back to inactive non-periodic schedule. */
661 dwc_otg_hcd_qh_add(hcd, qh);
664 uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
667 /* Schedule the next continuing periodic split transfer */
668 if (sched_next_periodic_split) {
670 qh->sched_frame = frame_number;
671 if (dwc_frame_num_le(frame_number,
672 dwc_frame_num_inc(qh->start_split_frame, 1))) {
674 * Allow one frame to elapse after start
675 * split microframe before scheduling
676 * complete split, but DONT if we are
677 * doing the next start split in the
678 * same frame for an ISOC out.
680 if ((qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (qh->ep_is_in != 0)) {
681 qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, 1);
685 qh->sched_frame = dwc_frame_num_inc(qh->start_split_frame,
687 if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
688 qh->sched_frame = frame_number;
690 qh->sched_frame |= 0x7;
691 qh->start_split_frame = qh->sched_frame;
694 qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval);
695 if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
696 qh->sched_frame = frame_number;
700 if (list_empty(&qh->qtd_list)) {
701 dwc_otg_hcd_qh_remove(hcd, qh);
704 * Remove from periodic_sched_queued and move to
707 if (qh->sched_frame == frame_number) {
708 list_move(&qh->qh_list_entry,
709 &hcd->periodic_sched_ready);
711 list_move(&qh->qh_list_entry,
712 &hcd->periodic_sched_inactive);
719 * This function allocates and initializes a QTD.
721 * @param[in] urb The URB to create a QTD from. Each URB-QTD pair will end up
722 * pointing to each other so each pair should have a unique correlation.
724 * @return Returns pointer to the newly allocated QTD, or NULL on error. */
725 dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb)
729 qtd = dwc_otg_hcd_qtd_alloc ();
734 dwc_otg_hcd_qtd_init (qtd, urb);
739 * Initializes a QTD structure.
741 * @param[in] qtd The QTD to initialize.
742 * @param[in] urb The URB to use for initialization. */
743 void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb)
745 memset (qtd, 0, sizeof (dwc_otg_qtd_t));
747 if (usb_pipecontrol(urb->pipe)) {
749 * The only time the QTD data toggle is used is on the data
750 * phase of control transfers. This phase always starts with
753 qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
754 qtd->control_phase = DWC_OTG_CONTROL_SETUP;
758 qtd->complete_split = 0;
759 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
760 qtd->isoc_split_offset = 0;
762 /* Store the qtd ptr in the urb to reference what QTD. */
768 * This function adds a QTD to the QTD-list of a QH. It will find the correct
769 * QH to place the QTD into. If it does not find a QH, then it will create a
770 * new QH. If the QH to which the QTD is added is not currently scheduled, it
771 * is placed into the proper schedule based on its EP type.
773 * @param[in] qtd The QTD to add
774 * @param[in] dwc_otg_hcd The DWC HCD structure
776 * @return 0 if successful, negative error code otherwise.
778 int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd,
779 dwc_otg_hcd_t *dwc_otg_hcd)
781 struct usb_host_endpoint *ep;
785 struct urb *urb = qtd->urb;
788 * Get the QH which holds the QTD-list to insert to. Create QH if it
791 usb_hcd_link_urb_to_ep(dwc_otg_hcd_to_hcd(dwc_otg_hcd), urb);
792 ep = dwc_urb_to_endpoint(urb);
793 qh = (dwc_otg_qh_t *)ep->hcpriv;
795 qh = dwc_otg_hcd_qh_create (dwc_otg_hcd, urb);
797 usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(dwc_otg_hcd), urb);
804 retval = dwc_otg_hcd_qh_add(dwc_otg_hcd, qh);
806 list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
808 usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(dwc_otg_hcd), urb);
815 #endif /* DWC_DEVICE_ONLY */