target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c

   1 /*
   2  * Cavium CNS3xxx Gigabit driver for Linux
   3  *
   4  * Copyright 2011 Gateworks Corporation
   5  *                Chris Lang <clang@gateworks.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of version 2 of the GNU General Public License
   9  * as published by the Free Software Foundation.
  10  *
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/module.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/dmapool.h>
  17 #include <linux/etherdevice.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/phy.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/platform_data/cns3xxx.h>
  24 #include <linux/skbuff.h>
  25
  26 #define DRV_NAME "cns3xxx_eth"
  27
  28 #define RX_DESCS 256
  29 #define TX_DESCS 128
  30 #define TX_DESC_RESERVE 20
  31
  32 #define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS)
  33 #define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS)
  34 #define REGS_SIZE 336
  35
  36 #define RX_BUFFER_ALIGN 64
  37 #define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1))
  38
  39 #define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN)
  40 #define RX_SEGMENT_ALLOC_SIZE 2048
  41 #define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE))
  42 #define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN)
  43 #define MAX_MTU 9500
  44
  45 #define NAPI_WEIGHT 64
  46
  47 /* MDIO Defines */
  48 #define MDIO_CMD_COMPLETE 0x00008000
  49 #define MDIO_WRITE_COMMAND 0x00002000
  50 #define MDIO_READ_COMMAND 0x00004000
  51 #define MDIO_REG_OFFSET 8
  52 #define MDIO_VALUE_OFFSET 16
  53
  54 /* Descritor Defines */
  55 #define END_OF_RING 0x40000000
  56 #define FIRST_SEGMENT 0x20000000
  57 #define LAST_SEGMENT 0x10000000
  58 #define FORCE_ROUTE 0x04000000
  59 #define UDP_CHECKSUM 0x00020000
  60 #define TCP_CHECKSUM 0x00010000
  61
  62 /* Port Config Defines */
  63 #define PORT_BP_ENABLE 0x00020000
  64 #define PORT_DISABLE 0x00040000
  65 #define PORT_LEARN_DIS 0x00080000
  66 #define PORT_BLOCK_STATE 0x00100000
  67 #define PORT_BLOCK_MODE 0x00200000
  68
  69 #define PROMISC_OFFSET 29
  70
  71 /* Global Config Defines */
  72 #define UNKNOWN_VLAN_TO_CPU 0x02000000
  73 #define ACCEPT_CRC_PACKET 0x00200000
  74 #define CRC_STRIPPING 0x00100000
  75
  76 /* VLAN Config Defines */
  77 #define NIC_MODE 0x00008000
  78 #define VLAN_UNAWARE 0x00000001
  79
  80 /* DMA AUTO Poll Defines */
  81 #define TS_POLL_EN 0x00000020
  82 #define TS_SUSPEND 0x00000010
  83 #define FS_POLL_EN 0x00000002
  84 #define FS_SUSPEND 0x00000001
  85
  86 /* DMA Ring Control Defines */
  87 #define QUEUE_THRESHOLD 0x000000f0
  88 #define CLR_FS_STATE 0x80000000
  89
  90 /* Interrupt Status Defines */
  91 #define MAC0_STATUS_CHANGE 0x00004000
  92 #define MAC1_STATUS_CHANGE 0x00008000
  93 #define MAC2_STATUS_CHANGE 0x00010000
  94 #define MAC0_RX_ERROR 0x00100000
  95 #define MAC1_RX_ERROR 0x00200000
  96 #define MAC2_RX_ERROR 0x00400000
  97
  98 struct tx_desc
  99 {
 100         u32 sdp; /* segment data pointer */
 101
 102         union {
 103                 struct {
 104                         u32 sdl:16; /* segment data length */
 105                         u32 tco:1;
 106                         u32 uco:1;
 107                         u32 ico:1;
 108                         u32 rsv_1:3; /* reserve */
 109                         u32 pri:3;
 110                         u32 fp:1; /* force priority */
 111                         u32 fr:1;
 112                         u32 interrupt:1;
 113                         u32 lsd:1;
 114                         u32 fsd:1;
 115                         u32 eor:1;
 116                         u32 cown:1;
 117                 };
 118                 u32 config0;
 119         };
 120
 121         union {
 122                 struct {
 123                         u32 ctv:1;
 124                         u32 stv:1;
 125                         u32 sid:4;
 126                         u32 inss:1;
 127                         u32 dels:1;
 128                         u32 rsv_2:9;
 129                         u32 pmap:5;
 130                         u32 mark:3;
 131                         u32 ewan:1;
 132                         u32 fewan:1;
 133                         u32 rsv_3:5;
 134                 };
 135                 u32 config1;
 136         };
 137
 138         union {
 139                 struct {
 140                         u32 c_vid:12;
 141                         u32 c_cfs:1;
 142                         u32 c_pri:3;
 143                         u32 s_vid:12;
 144                         u32 s_dei:1;
 145                         u32 s_pri:3;
 146                 };
 147                 u32 config2;
 148         };
 149
 150         u8 alignment[16]; /* for 32 byte */
 151 };
 152
 153 struct rx_desc
 154 {
 155         u32 sdp; /* segment data pointer */
 156
 157         union {
 158                 struct {
 159                         u32 sdl:16; /* segment data length */
 160                         u32 l4f:1;
 161                         u32 ipf:1;
 162                         u32 prot:4;
 163                         u32 hr:6;
 164                         u32 lsd:1;
 165                         u32 fsd:1;
 166                         u32 eor:1;
 167                         u32 cown:1;
 168                 };
 169                 u32 config0;
 170         };
 171
 172         union {
 173                 struct {
 174                         u32 ctv:1;
 175                         u32 stv:1;
 176                         u32 unv:1;
 177                         u32 iwan:1;
 178                         u32 exdv:1;
 179                         u32 e_wan:1;
 180                         u32 rsv_1:2;
 181                         u32 sp:3;
 182                         u32 crc_err:1;
 183                         u32 un_eth:1;
 184                         u32 tc:2;
 185                         u32 rsv_2:1;
 186                         u32 ip_offset:5;
 187                         u32 rsv_3:11;
 188                 };
 189                 u32 config1;
 190         };
 191
 192         union {
 193                 struct {
 194                         u32 c_vid:12;
 195                         u32 c_cfs:1;
 196                         u32 c_pri:3;
 197                         u32 s_vid:12;
 198                         u32 s_dei:1;
 199                         u32 s_pri:3;
 200                 };
 201                 u32 config2;
 202         };
 203
 204         u8 alignment[16]; /* for 32 byte alignment */
 205 };
 206
 207
 208 struct switch_regs {
 209         u32 phy_control;
 210         u32 phy_auto_addr;
 211         u32 mac_glob_cfg;
 212         u32 mac_cfg[4];
 213         u32 mac_pri_ctrl[5], __res;
 214         u32 etype[2];
 215         u32 udp_range[4];
 216         u32 prio_etype_udp;
 217         u32 prio_ipdscp[8];
 218         u32 tc_ctrl;
 219         u32 rate_ctrl;
 220         u32 fc_glob_thrs;
 221         u32 fc_port_thrs;
 222         u32 mc_fc_glob_thrs;
 223         u32 dc_glob_thrs;
 224         u32 arl_vlan_cmd;
 225         u32 arl_ctrl[3];
 226         u32 vlan_cfg;
 227         u32 pvid[2];
 228         u32 vlan_ctrl[3];
 229         u32 session_id[8];
 230         u32 intr_stat;
 231         u32 intr_mask;
 232         u32 sram_test;
 233         u32 mem_queue;
 234         u32 farl_ctrl;
 235         u32 fc_input_thrs, __res1[2];
 236         u32 clk_skew_ctrl;
 237         u32 mac_glob_cfg_ext, __res2[2];
 238         u32 dma_ring_ctrl;
 239         u32 dma_auto_poll_cfg;
 240         u32 delay_intr_cfg, __res3;
 241         u32 ts_dma_ctrl0;
 242         u32 ts_desc_ptr0;
 243         u32 ts_desc_base_addr0, __res4;
 244         u32 fs_dma_ctrl0;
 245         u32 fs_desc_ptr0;
 246         u32 fs_desc_base_addr0, __res5;
 247         u32 ts_dma_ctrl1;
 248         u32 ts_desc_ptr1;
 249         u32 ts_desc_base_addr1, __res6;
 250         u32 fs_dma_ctrl1;
 251         u32 fs_desc_ptr1;
 252         u32 fs_desc_base_addr1;
 253         u32 __res7[109];
 254         u32 mac_counter0[13];
 255 };
 256
 257 struct _tx_ring {
 258         struct tx_desc *desc;
 259         dma_addr_t phys_addr;
 260         struct tx_desc *cur_addr;
 261         struct sk_buff *buff_tab[TX_DESCS];
 262         unsigned int phys_tab[TX_DESCS];
 263         u32 free_index;
 264         u32 count_index;
 265         u32 cur_index;
 266         int num_used;
 267         int num_count;
 268         bool stopped;
 269 };
 270
 271 struct _rx_ring {
 272         struct rx_desc *desc;
 273         dma_addr_t phys_addr;
 274         struct rx_desc *cur_addr;
 275         void *buff_tab[RX_DESCS];
 276         unsigned int phys_tab[RX_DESCS];
 277         u32 cur_index;
 278         u32 alloc_index;
 279         int alloc_count;
 280 };
 281
 282 struct sw {
 283         struct switch_regs __iomem *regs;
 284         struct napi_struct napi;
 285         struct cns3xxx_plat_info *plat;
 286         struct _tx_ring tx_ring;
 287         struct _rx_ring rx_ring;
 288         struct sk_buff *frag_first;
 289         struct sk_buff *frag_last;
 290         struct device *dev;
 291         int rx_irq;
 292         int stat_irq;
 293 };
 294
 295 struct port {
 296         struct net_device *netdev;
 297         struct phy_device *phydev;
 298         struct sw *sw;
 299         int id;                 /* logical port ID */
 300         int speed, duplex;
 301 };
 302
 303 static spinlock_t mdio_lock;
 304 static DEFINE_SPINLOCK(tx_lock);
 305 static struct switch_regs __iomem *mdio_regs; /* mdio command and status only */
 306 struct mii_bus *mdio_bus;
 307 static int ports_open;
 308 static struct port *switch_port_tab[4];
 309 struct net_device *napi_dev;
 310
 311 static int cns3xxx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
 312                            int write, u16 cmd)
 313 {
 314         int cycles = 0;
 315         u32 temp = 0;
 316
 317         temp = __raw_readl(&mdio_regs->phy_control);
 318         temp |= MDIO_CMD_COMPLETE;
 319         __raw_writel(temp, &mdio_regs->phy_control);
 320         udelay(10);
 321
 322         if (write) {
 323                 temp = (cmd << MDIO_VALUE_OFFSET);
 324                 temp |= MDIO_WRITE_COMMAND;
 325         } else {
 326                 temp = MDIO_READ_COMMAND;
 327         }
 328         temp |= ((location & 0x1f) << MDIO_REG_OFFSET);
 329         temp |= (phy_id & 0x1f);
 330
 331         __raw_writel(temp, &mdio_regs->phy_control);
 332
 333         while (((__raw_readl(&mdio_regs->phy_control) & MDIO_CMD_COMPLETE) == 0)
 334                         && cycles < 5000) {
 335                 udelay(1);
 336                 cycles++;
 337         }
 338
 339         if (cycles == 5000) {
 340                 printk(KERN_ERR "%s #%i: MII transaction failed\n", bus->name,
 341                        phy_id);
 342                 return -1;
 343         }
 344
 345         temp = __raw_readl(&mdio_regs->phy_control);
 346         temp |= MDIO_CMD_COMPLETE;
 347         __raw_writel(temp, &mdio_regs->phy_control);
 348
 349         if (write)
 350                 return 0;
 351
 352         return ((temp >> MDIO_VALUE_OFFSET) & 0xFFFF);
 353 }
 354
 355 static int cns3xxx_mdio_read(struct mii_bus *bus, int phy_id, int location)
 356 {
 357         unsigned long flags;
 358         int ret;
 359
 360         spin_lock_irqsave(&mdio_lock, flags);
 361         ret = cns3xxx_mdio_cmd(bus, phy_id, location, 0, 0);
 362         spin_unlock_irqrestore(&mdio_lock, flags);
 363         return ret;
 364 }
 365
 366 static int cns3xxx_mdio_write(struct mii_bus *bus, int phy_id, int location,
 367                              u16 val)
 368 {
 369         unsigned long flags;
 370         int ret;
 371
 372         spin_lock_irqsave(&mdio_lock, flags);
 373         ret = cns3xxx_mdio_cmd(bus, phy_id, location, 1, val);
 374         spin_unlock_irqrestore(&mdio_lock, flags);
 375         return ret;
 376 }
 377
 378 static int cns3xxx_mdio_register(void __iomem *base)
 379 {
 380         int err;
 381
 382         if (!(mdio_bus = mdiobus_alloc()))
 383                 return -ENOMEM;
 384
 385         mdio_regs = base;
 386
 387         spin_lock_init(&mdio_lock);
 388         mdio_bus->name = "CNS3xxx MII Bus";
 389         mdio_bus->read = &cns3xxx_mdio_read;
 390         mdio_bus->write = &cns3xxx_mdio_write;
 391         strcpy(mdio_bus->id, "0");
 392
 393         if ((err = mdiobus_register(mdio_bus)))
 394                 mdiobus_free(mdio_bus);
 395         return err;
 396 }
 397
 398 static void cns3xxx_mdio_remove(void)
 399 {
 400         mdiobus_unregister(mdio_bus);
 401         mdiobus_free(mdio_bus);
 402 }
 403
 404 static void enable_tx_dma(struct sw *sw)
 405 {
 406         __raw_writel(0x1, &sw->regs->ts_dma_ctrl0);
 407 }
 408
 409 static void enable_rx_dma(struct sw *sw)
 410 {
 411         __raw_writel(0x1, &sw->regs->fs_dma_ctrl0);
 412 }
 413
 414 static void cns3xxx_adjust_link(struct net_device *dev)
 415 {
 416         struct port *port = netdev_priv(dev);
 417         struct phy_device *phydev = port->phydev;
 418
 419         if (!phydev->link) {
 420                 if (port->speed) {
 421                         port->speed = 0;
 422                         printk(KERN_INFO "%s: link down\n", dev->name);
 423                 }
 424                 return;
 425         }
 426
 427         if (port->speed == phydev->speed && port->duplex == phydev->duplex)
 428                 return;
 429
 430         port->speed = phydev->speed;
 431         port->duplex = phydev->duplex;
 432
 433         printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
 434                dev->name, port->speed, port->duplex ? "full" : "half");
 435 }
 436
 437 static void eth_schedule_poll(struct sw *sw)
 438 {
 439         if (unlikely(!napi_schedule_prep(&sw->napi)))
 440                 return;
 441
 442         disable_irq_nosync(sw->rx_irq);
 443         __napi_schedule(&sw->napi);
 444 }
 445
 446 irqreturn_t eth_rx_irq(int irq, void *pdev)
 447 {
 448         struct net_device *dev = pdev;
 449         struct sw *sw = netdev_priv(dev);
 450         eth_schedule_poll(sw);
 451         return (IRQ_HANDLED);
 452 }
 453
 454 irqreturn_t eth_stat_irq(int irq, void *pdev)
 455 {
 456         struct net_device *dev = pdev;
 457         struct sw *sw = netdev_priv(dev);
 458         u32 cfg;
 459         u32 stat = __raw_readl(&sw->regs->intr_stat);
 460         __raw_writel(0xffffffff, &sw->regs->intr_stat);
 461
 462         if (stat & MAC2_RX_ERROR)
 463                 switch_port_tab[3]->netdev->stats.rx_dropped++;
 464         if (stat & MAC1_RX_ERROR)
 465                 switch_port_tab[1]->netdev->stats.rx_dropped++;
 466         if (stat & MAC0_RX_ERROR)
 467                 switch_port_tab[0]->netdev->stats.rx_dropped++;
 468
 469         if (stat & MAC0_STATUS_CHANGE) {
 470                 cfg = __raw_readl(&sw->regs->mac_cfg[0]);
 471                 switch_port_tab[0]->phydev->link = (cfg & 0x1);
 472                 switch_port_tab[0]->phydev->duplex = ((cfg >> 4) & 0x1);
 473                 if (((cfg >> 2) & 0x3) == 2)
 474                         switch_port_tab[0]->phydev->speed = 1000;
 475                 else if (((cfg >> 2) & 0x3) == 1)
 476                         switch_port_tab[0]->phydev->speed = 100;
 477                 else
 478                         switch_port_tab[0]->phydev->speed = 10;
 479                 cns3xxx_adjust_link(switch_port_tab[0]->netdev);
 480         }
 481
 482         if (stat & MAC1_STATUS_CHANGE) {
 483                 cfg = __raw_readl(&sw->regs->mac_cfg[1]);
 484                 switch_port_tab[1]->phydev->link = (cfg & 0x1);
 485                 switch_port_tab[1]->phydev->duplex = ((cfg >> 4) & 0x1);
 486                 if (((cfg >> 2) & 0x3) == 2)
 487                         switch_port_tab[1]->phydev->speed = 1000;
 488                 else if (((cfg >> 2) & 0x3) == 1)
 489                         switch_port_tab[1]->phydev->speed = 100;
 490                 else
 491                         switch_port_tab[1]->phydev->speed = 10;
 492                 cns3xxx_adjust_link(switch_port_tab[1]->netdev);
 493         }
 494
 495         if (stat & MAC2_STATUS_CHANGE) {
 496                 cfg = __raw_readl(&sw->regs->mac_cfg[3]);
 497                 switch_port_tab[3]->phydev->link = (cfg & 0x1);
 498                 switch_port_tab[3]->phydev->duplex = ((cfg >> 4) & 0x1);
 499                 if (((cfg >> 2) & 0x3) == 2)
 500                         switch_port_tab[3]->phydev->speed = 1000;
 501                 else if (((cfg >> 2) & 0x3) == 1)
 502                         switch_port_tab[3]->phydev->speed = 100;
 503                 else
 504                         switch_port_tab[3]->phydev->speed = 10;
 505                 cns3xxx_adjust_link(switch_port_tab[3]->netdev);
 506         }
 507
 508         return (IRQ_HANDLED);
 509 }
 510
 511
 512 static void cns3xxx_alloc_rx_buf(struct sw *sw, int received)
 513 {
 514         struct _rx_ring *rx_ring = &sw->rx_ring;
 515         unsigned int i = rx_ring->alloc_index;
 516         struct rx_desc *desc = &(rx_ring)->desc[i];
 517         void *buf;
 518         unsigned int phys;
 519
 520         for (received += rx_ring->alloc_count; received > 0; received--) {
 521                 buf = napi_alloc_frag(RX_SEGMENT_ALLOC_SIZE);
 522                 if (!buf)
 523                         break;
 524
 525                 phys = dma_map_single(sw->dev, buf + SKB_HEAD_ALIGN,
 526                                       RX_SEGMENT_MRU, DMA_FROM_DEVICE);
 527                 if (dma_mapping_error(sw->dev, phys)) {
 528                         skb_free_frag(buf);
 529                         break;
 530                 }
 531
 532                 desc->sdl = RX_SEGMENT_MRU;
 533                 desc->sdp = phys;
 534
 535                 wmb();
 536
 537                 /* put the new buffer on RX-free queue */
 538                 rx_ring->buff_tab[i] = buf;
 539                 rx_ring->phys_tab[i] = phys;
 540                 if (i == RX_DESCS - 1) {
 541                         i = 0;
 542                         desc->config0 = END_OF_RING | FIRST_SEGMENT |
 543                                         LAST_SEGMENT | RX_SEGMENT_MRU;
 544                         desc = &(rx_ring)->desc[i];
 545                 } else {
 546                         desc->config0 = FIRST_SEGMENT | LAST_SEGMENT |
 547                                         RX_SEGMENT_MRU;
 548                         i++;
 549                         desc++;
 550                 }
 551         }
 552
 553         rx_ring->alloc_count = received;
 554         rx_ring->alloc_index = i;
 555 }
 556
 557 static void eth_check_num_used(struct _tx_ring *tx_ring)
 558 {
 559         bool stop = false;
 560         int i;
 561
 562         if (tx_ring->num_used >= TX_DESCS - TX_DESC_RESERVE)
 563                 stop = true;
 564
 565         if (tx_ring->stopped == stop)
 566                 return;
 567
 568         tx_ring->stopped = stop;
 569         for (i = 0; i < 4; i++) {
 570                 struct port *port = switch_port_tab[i];
 571                 struct net_device *dev;
 572
 573                 if (!port)
 574                         continue;
 575
 576                 dev = port->netdev;
 577                 if (stop)
 578                         netif_stop_queue(dev);
 579                 else
 580                         netif_wake_queue(dev);
 581         }
 582 }
 583
 584 static void eth_complete_tx(struct sw *sw)
 585 {
 586         struct _tx_ring *tx_ring = &sw->tx_ring;
 587         struct tx_desc *desc;
 588         int i;
 589         int index;
 590         int num_used = tx_ring->num_used;
 591         struct sk_buff *skb;
 592
 593         index = tx_ring->free_index;
 594         desc = &(tx_ring)->desc[index];
 595         for (i = 0; i < num_used; i++) {
 596                 if (desc->cown) {
 597                         skb = tx_ring->buff_tab[index];
 598                         tx_ring->buff_tab[index] = 0;
 599                         if (skb)
 600                                 dev_kfree_skb_any(skb);
 601                         dma_unmap_single(sw->dev, tx_ring->phys_tab[index],
 602                                 desc->sdl, DMA_TO_DEVICE);
 603                         if (++index == TX_DESCS) {
 604                                 index = 0;
 605                                 desc = &(tx_ring)->desc[index];
 606                         } else {
 607                                 desc++;
 608                         }
 609                 } else {
 610                         break;
 611                 }
 612         }
 613         tx_ring->free_index = index;
 614         tx_ring->num_used -= i;
 615         eth_check_num_used(tx_ring);
 616 }
 617
 618 static int eth_poll(struct napi_struct *napi, int budget)
 619 {
 620         struct sw *sw = container_of(napi, struct sw, napi);
 621         struct _rx_ring *rx_ring = &sw->rx_ring;
 622         int received = 0;
 623         unsigned int length;
 624         unsigned int i = rx_ring->cur_index;
 625         struct rx_desc *desc = &(rx_ring)->desc[i];
 626         unsigned int alloc_count = rx_ring->alloc_count;
 627
 628         while (desc->cown && alloc_count + received < RX_DESCS - 1) {
 629                 struct sk_buff *skb;
 630                 int reserve = SKB_HEAD_ALIGN;
 631
 632                 if (received >= budget)
 633                         break;
 634
 635                 /* process received frame */
 636                 dma_unmap_single(sw->dev, rx_ring->phys_tab[i],
 637                                  RX_SEGMENT_MRU, DMA_FROM_DEVICE);
 638
 639                 skb = build_skb(rx_ring->buff_tab[i], RX_SEGMENT_ALLOC_SIZE);
 640                 if (!skb)
 641                         break;
 642
 643                 skb->dev = switch_port_tab[desc->sp]->netdev;
 644
 645                 length = desc->sdl;
 646                 if (desc->fsd && !desc->lsd)
 647                         length = RX_SEGMENT_MRU;
 648
 649                 if (!desc->fsd) {
 650                         reserve -= NET_IP_ALIGN;
 651                         if (!desc->lsd)
 652                                 length += NET_IP_ALIGN;
 653                 }
 654
 655                 skb_reserve(skb, reserve);
 656                 skb_put(skb, length);
 657
 658                 if (!sw->frag_first)
 659                         sw->frag_first = skb;
 660                 else {
 661                         if (sw->frag_first == sw->frag_last)
 662                                 skb_shinfo(sw->frag_first)->frag_list = skb;
 663                         else
 664                                 sw->frag_last->next = skb;
 665                         sw->frag_first->len += skb->len;
 666                         sw->frag_first->data_len += skb->len;
 667                         sw->frag_first->truesize += skb->truesize;
 668                 }
 669                 sw->frag_last = skb;
 670
 671                 if (desc->lsd) {
 672                         struct net_device *dev;
 673
 674                         skb = sw->frag_first;
 675                         dev = skb->dev;
 676                         skb->protocol = eth_type_trans(skb, dev);
 677
 678                         dev->stats.rx_packets++;
 679                         dev->stats.rx_bytes += skb->len;
 680
 681                         /* RX Hardware checksum offload */
 682                         skb->ip_summed = CHECKSUM_NONE;
 683                         switch (desc->prot) {
 684                                 case 1:
 685                                 case 2:
 686                                 case 5:
 687                                 case 6:
 688                                 case 13:
 689                                 case 14:
 690                                         if (!desc->l4f) {
 691                                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 692                                                 napi_gro_receive(napi, skb);
 693                                                 break;
 694                                         }
 695                                         /* fall through */
 696                                 default:
 697                                         netif_receive_skb(skb);
 698                                         break;
 699                         }
 700
 701                         sw->frag_first = NULL;
 702                         sw->frag_last = NULL;
 703                 }
 704
 705                 received++;
 706                 if (++i == RX_DESCS) {
 707                         i = 0;
 708                         desc = &(rx_ring)->desc[i];
 709                 } else {
 710                         desc++;
 711                 }
 712         }
 713
 714         rx_ring->cur_index = i;
 715         if (!received) {
 716                 napi_complete(napi);
 717                 enable_irq(sw->rx_irq);
 718                 budget = 0;
 719
 720                 /* if rx descriptors are full schedule another poll */
 721                 if (rx_ring->desc[(i-1) & (RX_DESCS-1)].cown)
 722                         eth_schedule_poll(sw);
 723         }
 724
 725         spin_lock_bh(&tx_lock);
 726         eth_complete_tx(sw);
 727         spin_unlock_bh(&tx_lock);
 728
 729         cns3xxx_alloc_rx_buf(sw, received);
 730
 731         wmb();
 732         enable_rx_dma(sw);
 733
 734         return budget;
 735 }
 736
 737 static void eth_set_desc(struct sw *sw, struct _tx_ring *tx_ring, int index,
 738                          int index_last, void *data, int len, u32 config0,
 739                          u32 pmap)
 740 {
 741         struct tx_desc *tx_desc = &(tx_ring)->desc[index];
 742         unsigned int phys;
 743
 744         phys = dma_map_single(sw->dev, data, len, DMA_TO_DEVICE);
 745         tx_desc->sdp = phys;
 746         tx_desc->pmap = pmap;
 747         tx_ring->phys_tab[index] = phys;
 748
 749         config0 |= len;
 750         if (index == TX_DESCS - 1)
 751                 config0 |= END_OF_RING;
 752         if (index == index_last)
 753                 config0 |= LAST_SEGMENT;
 754
 755         wmb();
 756         tx_desc->config0 = config0;
 757 }
 758
 759 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
 760 {
 761         struct port *port = netdev_priv(dev);
 762         struct sw *sw = port->sw;
 763         struct _tx_ring *tx_ring = &sw->tx_ring;
 764         struct sk_buff *skb1;
 765         char pmap = (1 << port->id);
 766         int nr_frags = skb_shinfo(skb)->nr_frags;
 767         int nr_desc = nr_frags;
 768         int index0, index, index_last;
 769         int len0;
 770         unsigned int i;
 771         u32 config0;
 772
 773         if (pmap == 8)
 774                 pmap = (1 << 4);
 775
 776         skb_walk_frags(skb, skb1)
 777                 nr_desc++;
 778
 779         eth_schedule_poll(sw);
 780         spin_lock_bh(&tx_lock);
 781         if ((tx_ring->num_used + nr_desc + 1) >= TX_DESCS) {
 782                 spin_unlock_bh(&tx_lock);
 783                 return NETDEV_TX_BUSY;
 784         }
 785
 786         index = index0 = tx_ring->cur_index;
 787         index_last = (index0 + nr_desc) % TX_DESCS;
 788         tx_ring->cur_index = (index_last + 1) % TX_DESCS;
 789
 790         spin_unlock_bh(&tx_lock);
 791
 792         config0 = FORCE_ROUTE;
 793         if (skb->ip_summed == CHECKSUM_PARTIAL)
 794                 config0 |= UDP_CHECKSUM | TCP_CHECKSUM;
 795
 796         len0 = skb->len;
 797
 798         /* fragments */
 799         for (i = 0; i < nr_frags; i++) {
 800                 struct skb_frag_struct *frag;
 801                 void *addr;
 802
 803                 index = (index + 1) % TX_DESCS;
 804
 805                 frag = &skb_shinfo(skb)->frags[i];
 806                 addr = page_address(skb_frag_page(frag)) + frag->page_offset;
 807
 808                 eth_set_desc(sw, tx_ring, index, index_last, addr, frag->size,
 809                              config0, pmap);
 810         }
 811
 812         if (nr_frags)
 813                 len0 = skb->len - skb->data_len;
 814
 815         skb_walk_frags(skb, skb1) {
 816                 index = (index + 1) % TX_DESCS;
 817                 len0 -= skb1->len;
 818
 819                 eth_set_desc(sw, tx_ring, index, index_last, skb1->data,
 820                              skb1->len, config0, pmap);
 821         }
 822
 823         tx_ring->buff_tab[index0] = skb;
 824         eth_set_desc(sw, tx_ring, index0, index_last, skb->data, len0,
 825                      config0 | FIRST_SEGMENT, pmap);
 826
 827         wmb();
 828
 829         spin_lock(&tx_lock);
 830         tx_ring->num_used += nr_desc + 1;
 831         spin_unlock(&tx_lock);
 832
 833         dev->stats.tx_packets++;
 834         dev->stats.tx_bytes += skb->len;
 835
 836         enable_tx_dma(sw);
 837
 838         return NETDEV_TX_OK;
 839 }
 840
 841 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
 842 {
 843         struct port *port = netdev_priv(dev);
 844
 845         if (!netif_running(dev))
 846                 return -EINVAL;
 847         return phy_mii_ioctl(port->phydev, req, cmd);
 848 }
 849
 850 /* ethtool support */
 851
 852 static void cns3xxx_get_drvinfo(struct net_device *dev,
 853                                struct ethtool_drvinfo *info)
 854 {
 855         strcpy(info->driver, DRV_NAME);
 856         strcpy(info->bus_info, "internal");
 857 }
 858
 859 static int cns3xxx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 860 {
 861         struct port *port = netdev_priv(dev);
 862         return phy_ethtool_gset(port->phydev, cmd);
 863 }
 864
 865 static int cns3xxx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 866 {
 867         struct port *port = netdev_priv(dev);
 868         return phy_ethtool_sset(port->phydev, cmd);
 869 }
 870
 871 static int cns3xxx_nway_reset(struct net_device *dev)
 872 {
 873         struct port *port = netdev_priv(dev);
 874         return phy_start_aneg(port->phydev);
 875 }
 876
 877 static struct ethtool_ops cns3xxx_ethtool_ops = {
 878         .get_drvinfo = cns3xxx_get_drvinfo,
 879         .get_settings = cns3xxx_get_settings,
 880         .set_settings = cns3xxx_set_settings,
 881         .nway_reset = cns3xxx_nway_reset,
 882         .get_link = ethtool_op_get_link,
 883 };
 884
 885
 886 static int init_rings(struct sw *sw)
 887 {
 888         int i;
 889         struct _rx_ring *rx_ring = &sw->rx_ring;
 890         struct _tx_ring *tx_ring = &sw->tx_ring;
 891
 892         __raw_writel(0, &sw->regs->fs_dma_ctrl0);
 893         __raw_writel(TS_SUSPEND | FS_SUSPEND, &sw->regs->dma_auto_poll_cfg);
 894         __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
 895         __raw_writel(CLR_FS_STATE | QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
 896
 897         __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
 898
 899         rx_ring->desc = dmam_alloc_coherent(sw->dev, RX_POOL_ALLOC_SIZE,
 900                                             &rx_ring->phys_addr, GFP_KERNEL);
 901         if (!rx_ring->desc)
 902                 return -ENOMEM;
 903
 904         /* Setup RX buffers */
 905         memset(rx_ring->desc, 0, RX_POOL_ALLOC_SIZE);
 906         for (i = 0; i < RX_DESCS; i++) {
 907                 struct rx_desc *desc = &(rx_ring)->desc[i];
 908                 void *buf;
 909
 910                 buf = netdev_alloc_frag(RX_SEGMENT_ALLOC_SIZE);
 911                 if (!buf)
 912                         return -ENOMEM;
 913
 914                 desc->sdl = RX_SEGMENT_MRU;
 915                 if (i == (RX_DESCS - 1))
 916                         desc->eor = 1;
 917                 desc->fsd = 1;
 918                 desc->lsd = 1;
 919
 920                 desc->sdp = dma_map_single(sw->dev, buf + SKB_HEAD_ALIGN,
 921                                            RX_SEGMENT_MRU, DMA_FROM_DEVICE);
 922                 if (dma_mapping_error(sw->dev, desc->sdp))
 923                         return -EIO;
 924
 925                 rx_ring->buff_tab[i] = buf;
 926                 rx_ring->phys_tab[i] = desc->sdp;
 927                 desc->cown = 0;
 928         }
 929         __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_ptr0);
 930         __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_base_addr0);
 931
 932         tx_ring->desc = dmam_alloc_coherent(sw->dev, TX_POOL_ALLOC_SIZE,
 933                                             &tx_ring->phys_addr, GFP_KERNEL);
 934         if (!tx_ring->desc)
 935                 return -ENOMEM;
 936
 937         /* Setup TX buffers */
 938         memset(tx_ring->desc, 0, TX_POOL_ALLOC_SIZE);
 939         for (i = 0; i < TX_DESCS; i++) {
 940                 struct tx_desc *desc = &(tx_ring)->desc[i];
 941                 tx_ring->buff_tab[i] = 0;
 942
 943                 if (i == (TX_DESCS - 1))
 944                         desc->eor = 1;
 945                 desc->cown = 1;
 946         }
 947         __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_ptr0);
 948         __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_base_addr0);
 949
 950         return 0;
 951 }
 952
 953 static void destroy_rings(struct sw *sw)
 954 {
 955         int i;
 956
 957         for (i = 0; i < RX_DESCS; i++) {
 958                 struct _rx_ring *rx_ring = &sw->rx_ring;
 959                 struct rx_desc *desc = &(rx_ring)->desc[i];
 960                 void *buf = sw->rx_ring.buff_tab[i];
 961
 962                 if (!buf)
 963                         continue;
 964
 965                 dma_unmap_single(sw->dev, desc->sdp, RX_SEGMENT_MRU,
 966                                  DMA_FROM_DEVICE);
 967                 skb_free_frag(buf);
 968         }
 969
 970         for (i = 0; i < TX_DESCS; i++) {
 971                 struct _tx_ring *tx_ring = &sw->tx_ring;
 972                 struct tx_desc *desc = &(tx_ring)->desc[i];
 973                 struct sk_buff *skb = sw->tx_ring.buff_tab[i];
 974
 975                 if (!skb)
 976                         continue;
 977
 978                 dma_unmap_single(sw->dev, desc->sdp, skb->len, DMA_TO_DEVICE);
 979                 dev_kfree_skb(skb);
 980         }
 981 }
 982
 983 static int eth_open(struct net_device *dev)
 984 {
 985         struct port *port = netdev_priv(dev);
 986         struct sw *sw = port->sw;
 987         u32 temp;
 988
 989         port->speed = 0;        /* force "link up" message */
 990         phy_start(port->phydev);
 991
 992         netif_start_queue(dev);
 993
 994         if (!ports_open) {
 995                 request_irq(sw->rx_irq, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev);
 996                 request_irq(sw->stat_irq, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev);
 997                 napi_enable(&sw->napi);
 998                 netif_start_queue(napi_dev);
 999
1000                 __raw_writel(~(MAC0_STATUS_CHANGE | MAC1_STATUS_CHANGE | MAC2_STATUS_CHANGE |
1001                                MAC0_RX_ERROR | MAC1_RX_ERROR | MAC2_RX_ERROR), &sw->regs->intr_mask);
1002
1003                 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1004                 temp &= ~(PORT_DISABLE);
1005                 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1006
1007                 temp = __raw_readl(&sw->regs->dma_auto_poll_cfg);
1008                 temp &= ~(TS_SUSPEND | FS_SUSPEND);
1009                 __raw_writel(temp, &sw->regs->dma_auto_poll_cfg);
1010
1011                 enable_rx_dma(sw);
1012         }
1013         temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1014         temp &= ~(PORT_DISABLE);
1015         __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1016
1017         ports_open++;
1018         netif_carrier_on(dev);
1019
1020         return 0;
1021 }
1022
1023 static int eth_close(struct net_device *dev)
1024 {
1025         struct port *port = netdev_priv(dev);
1026         struct sw *sw = port->sw;
1027         u32 temp;
1028
1029         ports_open--;
1030
1031         temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1032         temp |= (PORT_DISABLE);
1033         __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1034
1035         netif_stop_queue(dev);
1036
1037         phy_stop(port->phydev);
1038
1039         if (!ports_open) {
1040                 disable_irq(sw->rx_irq);
1041                 free_irq(sw->rx_irq, napi_dev);
1042                 disable_irq(sw->stat_irq);
1043                 free_irq(sw->stat_irq, napi_dev);
1044                 napi_disable(&sw->napi);
1045                 netif_stop_queue(napi_dev);
1046                 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1047                 temp |= (PORT_DISABLE);
1048                 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1049
1050                 __raw_writel(TS_SUSPEND | FS_SUSPEND,
1051                              &sw->regs->dma_auto_poll_cfg);
1052         }
1053
1054         netif_carrier_off(dev);
1055         return 0;
1056 }
1057
1058 static void eth_rx_mode(struct net_device *dev)
1059 {
1060         struct port *port = netdev_priv(dev);
1061         struct sw *sw = port->sw;
1062         u32 temp;
1063
1064         temp = __raw_readl(&sw->regs->mac_glob_cfg);
1065
1066         if (dev->flags & IFF_PROMISC) {
1067                 if (port->id == 3)
1068                         temp |= ((1 << 2) << PROMISC_OFFSET);
1069                 else
1070                         temp |= ((1 << port->id) << PROMISC_OFFSET);
1071         } else {
1072                 if (port->id == 3)
1073                         temp &= ~((1 << 2) << PROMISC_OFFSET);
1074                 else
1075                         temp &= ~((1 << port->id) << PROMISC_OFFSET);
1076         }
1077         __raw_writel(temp, &sw->regs->mac_glob_cfg);
1078 }
1079
1080 static int eth_set_mac(struct net_device *netdev, void *p)
1081 {
1082         struct port *port = netdev_priv(netdev);
1083         struct sw *sw = port->sw;
1084         struct sockaddr *addr = p;
1085         u32 cycles = 0;
1086
1087         if (!is_valid_ether_addr(addr->sa_data))
1088                 return -EADDRNOTAVAIL;
1089
1090         /* Invalidate old ARL Entry */
1091         if (port->id == 3)
1092                 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1093         else
1094                 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1095         __raw_writel( ((netdev->dev_addr[0] << 24) | (netdev->dev_addr[1] << 16) |
1096                         (netdev->dev_addr[2] << 8) | (netdev->dev_addr[3])),
1097                         &sw->regs->arl_ctrl[1]);
1098
1099         __raw_writel( ((netdev->dev_addr[4] << 24) | (netdev->dev_addr[5] << 16) |
1100                         (1 << 1)),
1101                         &sw->regs->arl_ctrl[2]);
1102         __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1103
1104         while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1105                         && cycles < 5000) {
1106                 udelay(1);
1107                 cycles++;
1108         }
1109
1110         cycles = 0;
1111         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1112
1113         if (port->id == 3)
1114                 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1115         else
1116                 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1117         __raw_writel( ((addr->sa_data[0] << 24) | (addr->sa_data[1] << 16) |
1118                         (addr->sa_data[2] << 8) | (addr->sa_data[3])),
1119                         &sw->regs->arl_ctrl[1]);
1120
1121         __raw_writel( ((addr->sa_data[4] << 24) | (addr->sa_data[5] << 16) |
1122                         (7 << 4) | (1 << 1)), &sw->regs->arl_ctrl[2]);
1123         __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1124
1125         while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1126                 && cycles < 5000) {
1127                 udelay(1);
1128                 cycles++;
1129         }
1130         return 0;
1131 }
1132
1133 static int cns3xxx_change_mtu(struct net_device *dev, int new_mtu)
1134 {
1135         if (new_mtu > MAX_MTU)
1136                 return -EINVAL;
1137
1138         dev->mtu = new_mtu;
1139         return 0;
1140 }
1141
1142 static const struct net_device_ops cns3xxx_netdev_ops = {
1143         .ndo_open = eth_open,
1144         .ndo_stop = eth_close,
1145         .ndo_start_xmit = eth_xmit,
1146         .ndo_set_rx_mode = eth_rx_mode,
1147         .ndo_do_ioctl = eth_ioctl,
1148         .ndo_change_mtu = cns3xxx_change_mtu,
1149         .ndo_set_mac_address = eth_set_mac,
1150         .ndo_validate_addr = eth_validate_addr,
1151 };
1152
1153 static int eth_init_one(struct platform_device *pdev)
1154 {
1155         int i;
1156         struct port *port;
1157         struct sw *sw;
1158         struct net_device *dev;
1159         struct cns3xxx_plat_info *plat = pdev->dev.platform_data;
1160         char phy_id[MII_BUS_ID_SIZE + 3];
1161         int err;
1162         u32 temp;
1163         struct resource *res;
1164         void __iomem *regs;
1165
1166         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1167         regs = devm_ioremap_resource(&pdev->dev, res);
1168         if (IS_ERR(regs))
1169                 return PTR_ERR(regs);
1170
1171         err = cns3xxx_mdio_register(regs);
1172         if (err)
1173                 return err;
1174
1175         if (!(napi_dev = alloc_etherdev(sizeof(struct sw)))) {
1176                 err = -ENOMEM;
1177                 goto err_remove_mdio;
1178         }
1179
1180         strcpy(napi_dev->name, "switch%d");
1181         napi_dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1182
1183         SET_NETDEV_DEV(napi_dev, &pdev->dev);
1184         sw = netdev_priv(napi_dev);
1185         memset(sw, 0, sizeof(struct sw));
1186         sw->regs = regs;
1187         sw->dev = &pdev->dev;
1188
1189         sw->rx_irq = platform_get_irq_byname(pdev, "eth_rx");
1190         sw->stat_irq = platform_get_irq_byname(pdev, "eth_stat");
1191
1192         temp = __raw_readl(&sw->regs->phy_auto_addr);
1193         temp |= (3 << 30); /* maximum frame length: 9600 bytes */
1194         __raw_writel(temp, &sw->regs->phy_auto_addr);
1195
1196         for (i = 0; i < 4; i++) {
1197                 temp = __raw_readl(&sw->regs->mac_cfg[i]);
1198                 temp |= (PORT_DISABLE);
1199                 __raw_writel(temp, &sw->regs->mac_cfg[i]);
1200         }
1201
1202         temp = PORT_DISABLE;
1203         __raw_writel(temp, &sw->regs->mac_cfg[2]);
1204
1205         temp = __raw_readl(&sw->regs->vlan_cfg);
1206         temp |= NIC_MODE | VLAN_UNAWARE;
1207         __raw_writel(temp, &sw->regs->vlan_cfg);
1208
1209         __raw_writel(UNKNOWN_VLAN_TO_CPU |
1210                      CRC_STRIPPING, &sw->regs->mac_glob_cfg);
1211
1212         if ((err = init_rings(sw)) != 0) {
1213                 err = -ENOMEM;
1214                 goto err_free;
1215         }
1216         platform_set_drvdata(pdev, napi_dev);
1217
1218         netif_napi_add(napi_dev, &sw->napi, eth_poll, NAPI_WEIGHT);
1219
1220         for (i = 0; i < 3; i++) {
1221                 if (!(plat->ports & (1 << i))) {
1222                         continue;
1223                 }
1224
1225                 if (!(dev = alloc_etherdev(sizeof(struct port)))) {
1226                         goto free_ports;
1227                 }
1228
1229                 port = netdev_priv(dev);
1230                 port->netdev = dev;
1231                 if (i == 2)
1232                         port->id = 3;
1233                 else
1234                         port->id = i;
1235                 port->sw = sw;
1236
1237                 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1238                 temp |= (PORT_DISABLE | PORT_BLOCK_STATE | PORT_LEARN_DIS);
1239                 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1240
1241                 SET_NETDEV_DEV(dev, &pdev->dev);
1242                 dev->netdev_ops = &cns3xxx_netdev_ops;
1243                 dev->ethtool_ops = &cns3xxx_ethtool_ops;
1244                 dev->tx_queue_len = 1000;
1245                 dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1246
1247                 switch_port_tab[port->id] = port;
1248                 memcpy(dev->dev_addr, &plat->hwaddr[i], ETH_ALEN);
1249
1250                 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy[i]);
1251                 port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link,
1252                         PHY_INTERFACE_MODE_RGMII);
1253                 if ((err = IS_ERR(port->phydev))) {
1254                         switch_port_tab[port->id] = 0;
1255                         free_netdev(dev);
1256                         goto free_ports;
1257                 }
1258
1259                 port->phydev->irq = PHY_IGNORE_INTERRUPT;
1260
1261                 if ((err = register_netdev(dev))) {
1262                         phy_disconnect(port->phydev);
1263                         switch_port_tab[port->id] = 0;
1264                         free_netdev(dev);
1265                         goto free_ports;
1266                 }
1267
1268                 printk(KERN_INFO "%s: RGMII PHY %i on cns3xxx Switch\n", dev->name, plat->phy[i]);
1269                 netif_carrier_off(dev);
1270                 dev = 0;
1271         }
1272
1273         return 0;
1274
1275 free_ports:
1276         err = -ENOMEM;
1277         for (--i; i >= 0; i--) {
1278                 if (switch_port_tab[i]) {
1279                         port = switch_port_tab[i];
1280                         dev = port->netdev;
1281                         unregister_netdev(dev);
1282                         phy_disconnect(port->phydev);
1283                         switch_port_tab[i] = 0;
1284                         free_netdev(dev);
1285                 }
1286         }
1287 err_free:
1288         free_netdev(napi_dev);
1289 err_remove_mdio:
1290         cns3xxx_mdio_remove();
1291         return err;
1292 }
1293
1294 static int eth_remove_one(struct platform_device *pdev)
1295 {
1296         struct net_device *dev = platform_get_drvdata(pdev);
1297         struct sw *sw = netdev_priv(dev);
1298         int i;
1299
1300         destroy_rings(sw);
1301         for (i = 3; i >= 0; i--) {
1302                 if (switch_port_tab[i]) {
1303                         struct port *port = switch_port_tab[i];
1304                         struct net_device *dev = port->netdev;
1305                         unregister_netdev(dev);
1306                         phy_disconnect(port->phydev);
1307                         switch_port_tab[i] = 0;
1308                         free_netdev(dev);
1309                 }
1310         }
1311
1312         free_netdev(napi_dev);
1313         cns3xxx_mdio_remove();
1314
1315         return 0;
1316 }
1317
1318 static struct platform_driver cns3xxx_eth_driver = {
1319         .driver.name    = DRV_NAME,
1320         .probe          = eth_init_one,
1321         .remove         = eth_remove_one,
1322 };
1323
1324 static int __init eth_init_module(void)
1325 {
1326         return platform_driver_register(&cns3xxx_eth_driver);
1327 }
1328
1329 static void __exit eth_cleanup_module(void)
1330 {
1331         platform_driver_unregister(&cns3xxx_eth_driver);
1332 }
1333
1334 module_init(eth_init_module);
1335 module_exit(eth_cleanup_module);
1336
1337 MODULE_AUTHOR("Chris Lang");
1338 MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver");
1339 MODULE_LICENSE("GPL v2");
1340 MODULE_ALIAS("platform:cns3xxx_eth");