cns3xxx: ethernet - clean up tx descs only when needed
[openwrt.git] / target / linux / cns3xxx / files / drivers / net / ethernet / cavium / cns3xxx_eth.c
1 /*
2  * Cavium CNS3xxx Gigabit driver for Linux
3  *
4  * Copyright 2011 Gateworks Corporation
5  *                Chris Lang <clang@gateworks.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of version 2 of the GNU General Public License
9  * as published by the Free Software Foundation.
10  *
11  */
12
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmapool.h>
17 #include <linux/etherdevice.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/skbuff.h>
24 #include <mach/irqs.h>
25 #include <mach/platform.h>
26
27 #define DRV_NAME "cns3xxx_eth"
28
29 #define RX_DESCS 256
30 #define TX_DESCS 128
31 #define TX_DESC_RESERVE 20
32
33 #define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS)
34 #define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS)
35 #define REGS_SIZE 336
36
37 #define RX_BUFFER_ALIGN 64
38 #define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1))
39
40 #define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN)
41 #define RX_SEGMENT_ALLOC_SIZE 2048
42 #define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE))
43 #define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN)
44 #define MAX_MTU 9500
45
46 #define NAPI_WEIGHT 64
47
48 /* MDIO Defines */
49 #define MDIO_CMD_COMPLETE 0x00008000
50 #define MDIO_WRITE_COMMAND 0x00002000
51 #define MDIO_READ_COMMAND 0x00004000
52 #define MDIO_REG_OFFSET 8
53 #define MDIO_VALUE_OFFSET 16
54
55 /* Descritor Defines */
56 #define END_OF_RING 0x40000000
57 #define FIRST_SEGMENT 0x20000000
58 #define LAST_SEGMENT 0x10000000
59 #define FORCE_ROUTE 0x04000000
60 #define IP_CHECKSUM 0x00040000
61 #define UDP_CHECKSUM 0x00020000
62 #define TCP_CHECKSUM 0x00010000
63
64 /* Port Config Defines */
65 #define PORT_BP_ENABLE 0x00020000
66 #define PORT_DISABLE 0x00040000
67 #define PORT_LEARN_DIS 0x00080000
68 #define PORT_BLOCK_STATE 0x00100000
69 #define PORT_BLOCK_MODE 0x00200000
70
71 #define PROMISC_OFFSET 29
72
73 /* Global Config Defines */
74 #define UNKNOWN_VLAN_TO_CPU 0x02000000
75 #define ACCEPT_CRC_PACKET 0x00200000
76 #define CRC_STRIPPING 0x00100000
77
78 /* VLAN Config Defines */
79 #define NIC_MODE 0x00008000
80 #define VLAN_UNAWARE 0x00000001
81
82 /* DMA AUTO Poll Defines */
83 #define TS_POLL_EN 0x00000020
84 #define TS_SUSPEND 0x00000010
85 #define FS_POLL_EN 0x00000002
86 #define FS_SUSPEND 0x00000001
87
88 /* DMA Ring Control Defines */
89 #define QUEUE_THRESHOLD 0x000000f0
90 #define CLR_FS_STATE 0x80000000
91
92 /* Interrupt Status Defines */
93 #define MAC0_STATUS_CHANGE 0x00004000
94 #define MAC1_STATUS_CHANGE 0x00008000
95 #define MAC2_STATUS_CHANGE 0x00010000
96 #define MAC0_RX_ERROR 0x00100000
97 #define MAC1_RX_ERROR 0x00200000
98 #define MAC2_RX_ERROR 0x00400000
99
100 struct tx_desc
101 {
102         u32 sdp; /* segment data pointer */
103
104         union {
105                 struct {
106                         u32 sdl:16; /* segment data length */
107                         u32 tco:1;
108                         u32 uco:1;
109                         u32 ico:1;
110                         u32 rsv_1:3; /* reserve */
111                         u32 pri:3;
112                         u32 fp:1; /* force priority */
113                         u32 fr:1;
114                         u32 interrupt:1;
115                         u32 lsd:1;
116                         u32 fsd:1;
117                         u32 eor:1;
118                         u32 cown:1;
119                 };
120                 u32 config0;
121         };
122
123         union {
124                 struct {
125                         u32 ctv:1;
126                         u32 stv:1;
127                         u32 sid:4;
128                         u32 inss:1;
129                         u32 dels:1;
130                         u32 rsv_2:9;
131                         u32 pmap:5;
132                         u32 mark:3;
133                         u32 ewan:1;
134                         u32 fewan:1;
135                         u32 rsv_3:5;
136                 };
137                 u32 config1;
138         };
139
140         union {
141                 struct {
142                         u32 c_vid:12;
143                         u32 c_cfs:1;
144                         u32 c_pri:3;
145                         u32 s_vid:12;
146                         u32 s_dei:1;
147                         u32 s_pri:3;
148                 };
149                 u32 config2;
150         };
151
152         u8 alignment[16]; /* for 32 byte */
153 };
154
155 struct rx_desc
156 {
157         u32 sdp; /* segment data pointer */
158
159         union {
160                 struct {
161                         u32 sdl:16; /* segment data length */
162                         u32 l4f:1;
163                         u32 ipf:1;
164                         u32 prot:4;
165                         u32 hr:6;
166                         u32 lsd:1;
167                         u32 fsd:1;
168                         u32 eor:1;
169                         u32 cown:1;
170                 };
171                 u32 config0;
172         };
173
174         union {
175                 struct {
176                         u32 ctv:1;
177                         u32 stv:1;
178                         u32 unv:1;
179                         u32 iwan:1;
180                         u32 exdv:1;
181                         u32 e_wan:1;
182                         u32 rsv_1:2;
183                         u32 sp:3;
184                         u32 crc_err:1;
185                         u32 un_eth:1;
186                         u32 tc:2;
187                         u32 rsv_2:1;
188                         u32 ip_offset:5;
189                         u32 rsv_3:11;
190                 };
191                 u32 config1;
192         };
193
194         union {
195                 struct {
196                         u32 c_vid:12;
197                         u32 c_cfs:1;
198                         u32 c_pri:3;
199                         u32 s_vid:12;
200                         u32 s_dei:1;
201                         u32 s_pri:3;
202                 };
203                 u32 config2;
204         };
205
206         u8 alignment[16]; /* for 32 byte alignment */
207 };
208
209
210 struct switch_regs {
211         u32 phy_control;
212         u32 phy_auto_addr;
213         u32 mac_glob_cfg;
214         u32 mac_cfg[4];
215         u32 mac_pri_ctrl[5], __res;
216         u32 etype[2];
217         u32 udp_range[4];
218         u32 prio_etype_udp;
219         u32 prio_ipdscp[8];
220         u32 tc_ctrl;
221         u32 rate_ctrl;
222         u32 fc_glob_thrs;
223         u32 fc_port_thrs;
224         u32 mc_fc_glob_thrs;
225         u32 dc_glob_thrs;
226         u32 arl_vlan_cmd;
227         u32 arl_ctrl[3];
228         u32 vlan_cfg;
229         u32 pvid[2];
230         u32 vlan_ctrl[3];
231         u32 session_id[8];
232         u32 intr_stat;
233         u32 intr_mask;
234         u32 sram_test;
235         u32 mem_queue;
236         u32 farl_ctrl;
237         u32 fc_input_thrs, __res1[2];
238         u32 clk_skew_ctrl;
239         u32 mac_glob_cfg_ext, __res2[2];
240         u32 dma_ring_ctrl;
241         u32 dma_auto_poll_cfg;
242         u32 delay_intr_cfg, __res3;
243         u32 ts_dma_ctrl0;
244         u32 ts_desc_ptr0;
245         u32 ts_desc_base_addr0, __res4;
246         u32 fs_dma_ctrl0;
247         u32 fs_desc_ptr0;
248         u32 fs_desc_base_addr0, __res5;
249         u32 ts_dma_ctrl1;
250         u32 ts_desc_ptr1;
251         u32 ts_desc_base_addr1, __res6;
252         u32 fs_dma_ctrl1;
253         u32 fs_desc_ptr1;
254         u32 fs_desc_base_addr1;
255         u32 __res7[109];
256         u32 mac_counter0[13];
257 };
258
259 struct _tx_ring {
260         struct tx_desc *desc;
261         dma_addr_t phys_addr;
262         struct tx_desc *cur_addr;
263         struct sk_buff *buff_tab[TX_DESCS];
264         unsigned int phys_tab[TX_DESCS];
265         u32 free_index;
266         u32 count_index;
267         u32 cur_index;
268         int num_used;
269         int num_count;
270         bool stopped;
271 };
272
273 struct _rx_ring {
274         struct rx_desc *desc;
275         dma_addr_t phys_addr;
276         struct rx_desc *cur_addr;
277         void *buff_tab[RX_DESCS];
278         unsigned int phys_tab[RX_DESCS];
279         u32 cur_index;
280         u32 alloc_index;
281         int alloc_count;
282 };
283
284 struct sw {
285         struct resource *mem_res;
286         struct switch_regs __iomem *regs;
287         struct napi_struct napi;
288         struct cns3xxx_plat_info *plat;
289         struct _tx_ring tx_ring;
290         struct _rx_ring rx_ring;
291         struct sk_buff *frag_first;
292         struct sk_buff *frag_last;
293 };
294
295 struct port {
296         struct net_device *netdev;
297         struct phy_device *phydev;
298         struct sw *sw;
299         int id;                 /* logical port ID */
300         int speed, duplex;
301 };
302
303 static spinlock_t mdio_lock;
304 static DEFINE_SPINLOCK(tx_lock);
305 static struct switch_regs __iomem *mdio_regs; /* mdio command and status only */
306 struct mii_bus *mdio_bus;
307 static int ports_open;
308 static struct port *switch_port_tab[4];
309 static struct dma_pool *rx_dma_pool;
310 static struct dma_pool *tx_dma_pool;
311 struct net_device *napi_dev;
312
313 static int cns3xxx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
314                            int write, u16 cmd)
315 {
316         int cycles = 0;
317         u32 temp = 0;
318
319         temp = __raw_readl(&mdio_regs->phy_control);
320         temp |= MDIO_CMD_COMPLETE;
321         __raw_writel(temp, &mdio_regs->phy_control);
322         udelay(10);
323
324         if (write) {
325                 temp = (cmd << MDIO_VALUE_OFFSET);
326                 temp |= MDIO_WRITE_COMMAND;
327         } else {
328                 temp = MDIO_READ_COMMAND;
329         }
330         temp |= ((location & 0x1f) << MDIO_REG_OFFSET);
331         temp |= (phy_id & 0x1f);
332
333         __raw_writel(temp, &mdio_regs->phy_control);
334
335         while (((__raw_readl(&mdio_regs->phy_control) & MDIO_CMD_COMPLETE) == 0)
336                         && cycles < 5000) {
337                 udelay(1);
338                 cycles++;
339         }
340
341         if (cycles == 5000) {
342                 printk(KERN_ERR "%s #%i: MII transaction failed\n", bus->name,
343                        phy_id);
344                 return -1;
345         }
346
347         temp = __raw_readl(&mdio_regs->phy_control);
348         temp |= MDIO_CMD_COMPLETE;
349         __raw_writel(temp, &mdio_regs->phy_control);
350
351         if (write)
352                 return 0;
353
354         return ((temp >> MDIO_VALUE_OFFSET) & 0xFFFF);
355 }
356
357 static int cns3xxx_mdio_read(struct mii_bus *bus, int phy_id, int location)
358 {
359         unsigned long flags;
360         int ret;
361
362         spin_lock_irqsave(&mdio_lock, flags);
363         ret = cns3xxx_mdio_cmd(bus, phy_id, location, 0, 0);
364         spin_unlock_irqrestore(&mdio_lock, flags);
365         return ret;
366 }
367
368 static int cns3xxx_mdio_write(struct mii_bus *bus, int phy_id, int location,
369                              u16 val)
370 {
371         unsigned long flags;
372         int ret;
373
374         spin_lock_irqsave(&mdio_lock, flags);
375         ret = cns3xxx_mdio_cmd(bus, phy_id, location, 1, val);
376         spin_unlock_irqrestore(&mdio_lock, flags);
377         return ret;
378 }
379
380 static int cns3xxx_mdio_register(void)
381 {
382         int err;
383
384         if (!(mdio_bus = mdiobus_alloc()))
385                 return -ENOMEM;
386
387         mdio_regs = (struct switch_regs __iomem *)CNS3XXX_SWITCH_BASE_VIRT;
388
389         spin_lock_init(&mdio_lock);
390         mdio_bus->name = "CNS3xxx MII Bus";
391         mdio_bus->read = &cns3xxx_mdio_read;
392         mdio_bus->write = &cns3xxx_mdio_write;
393         strcpy(mdio_bus->id, "0");
394
395         if ((err = mdiobus_register(mdio_bus)))
396                 mdiobus_free(mdio_bus);
397         return err;
398 }
399
400 static void cns3xxx_mdio_remove(void)
401 {
402         mdiobus_unregister(mdio_bus);
403         mdiobus_free(mdio_bus);
404 }
405
406 static void enable_tx_dma(struct sw *sw)
407 {
408         __raw_writel(0x1, &sw->regs->ts_dma_ctrl0);
409 }
410
411 static void enable_rx_dma(struct sw *sw)
412 {
413         __raw_writel(0x1, &sw->regs->fs_dma_ctrl0);
414 }
415
416 static void cns3xxx_adjust_link(struct net_device *dev)
417 {
418         struct port *port = netdev_priv(dev);
419         struct phy_device *phydev = port->phydev;
420
421         if (!phydev->link) {
422                 if (port->speed) {
423                         port->speed = 0;
424                         printk(KERN_INFO "%s: link down\n", dev->name);
425                 }
426                 return;
427         }
428
429         if (port->speed == phydev->speed && port->duplex == phydev->duplex)
430                 return;
431
432         port->speed = phydev->speed;
433         port->duplex = phydev->duplex;
434
435         printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
436                dev->name, port->speed, port->duplex ? "full" : "half");
437 }
438
439 static void eth_schedule_poll(struct sw *sw)
440 {
441         if (unlikely(!napi_schedule_prep(&sw->napi)))
442                 return;
443
444         disable_irq_nosync(IRQ_CNS3XXX_SW_R0RXC);
445         __napi_schedule(&sw->napi);
446 }
447
448 irqreturn_t eth_rx_irq(int irq, void *pdev)
449 {
450         struct net_device *dev = pdev;
451         struct sw *sw = netdev_priv(dev);
452         eth_schedule_poll(sw);
453         return (IRQ_HANDLED);
454 }
455
456 irqreturn_t eth_stat_irq(int irq, void *pdev)
457 {
458         struct net_device *dev = pdev;
459         struct sw *sw = netdev_priv(dev);
460         u32 cfg;
461         u32 stat = __raw_readl(&sw->regs->intr_stat);
462         __raw_writel(0xffffffff, &sw->regs->intr_stat);
463
464         if (stat & MAC2_RX_ERROR)
465                 switch_port_tab[3]->netdev->stats.rx_dropped++;
466         if (stat & MAC1_RX_ERROR)
467                 switch_port_tab[1]->netdev->stats.rx_dropped++;
468         if (stat & MAC0_RX_ERROR)
469                 switch_port_tab[0]->netdev->stats.rx_dropped++;
470
471         if (stat & MAC0_STATUS_CHANGE) {
472                 cfg = __raw_readl(&sw->regs->mac_cfg[0]);
473                 switch_port_tab[0]->phydev->link = (cfg & 0x1);
474                 switch_port_tab[0]->phydev->duplex = ((cfg >> 4) & 0x1);
475                 if (((cfg >> 2) & 0x3) == 2)
476                         switch_port_tab[0]->phydev->speed = 1000;
477                 else if (((cfg >> 2) & 0x3) == 1)
478                         switch_port_tab[0]->phydev->speed = 100;
479                 else
480                         switch_port_tab[0]->phydev->speed = 10;
481                 cns3xxx_adjust_link(switch_port_tab[0]->netdev);
482         }
483
484         if (stat & MAC1_STATUS_CHANGE) {
485                 cfg = __raw_readl(&sw->regs->mac_cfg[1]);
486                 switch_port_tab[1]->phydev->link = (cfg & 0x1);
487                 switch_port_tab[1]->phydev->duplex = ((cfg >> 4) & 0x1);
488                 if (((cfg >> 2) & 0x3) == 2)
489                         switch_port_tab[1]->phydev->speed = 1000;
490                 else if (((cfg >> 2) & 0x3) == 1)
491                         switch_port_tab[1]->phydev->speed = 100;
492                 else
493                         switch_port_tab[1]->phydev->speed = 10;
494                 cns3xxx_adjust_link(switch_port_tab[1]->netdev);
495         }
496
497         if (stat & MAC2_STATUS_CHANGE) {
498                 cfg = __raw_readl(&sw->regs->mac_cfg[3]);
499                 switch_port_tab[3]->phydev->link = (cfg & 0x1);
500                 switch_port_tab[3]->phydev->duplex = ((cfg >> 4) & 0x1);
501                 if (((cfg >> 2) & 0x3) == 2)
502                         switch_port_tab[3]->phydev->speed = 1000;
503                 else if (((cfg >> 2) & 0x3) == 1)
504                         switch_port_tab[3]->phydev->speed = 100;
505                 else
506                         switch_port_tab[3]->phydev->speed = 10;
507                 cns3xxx_adjust_link(switch_port_tab[3]->netdev);
508         }
509
510         return (IRQ_HANDLED);
511 }
512
513
514 static void cns3xxx_alloc_rx_buf(struct sw *sw, int received)
515 {
516         struct _rx_ring *rx_ring = &sw->rx_ring;
517         unsigned int i = rx_ring->alloc_index;
518         struct rx_desc *desc = &(rx_ring)->desc[i];
519         void *buf;
520         unsigned int phys;
521
522         for (received += rx_ring->alloc_count; received > 0; received--) {
523                 buf = kmalloc(RX_SEGMENT_ALLOC_SIZE, GFP_ATOMIC);
524                 if (!buf)
525                         break;
526
527                 phys = dma_map_single(NULL, buf + SKB_HEAD_ALIGN,
528                                       RX_SEGMENT_MRU, DMA_FROM_DEVICE);
529                 if (dma_mapping_error(NULL, phys)) {
530                         kfree(buf);
531                         break;
532                 }
533
534                 desc->sdl = RX_SEGMENT_MRU;
535                 desc->sdp = phys;
536
537                 wmb();
538
539                 /* put the new buffer on RX-free queue */
540                 rx_ring->buff_tab[i] = buf;
541                 rx_ring->phys_tab[i] = phys;
542                 if (i == RX_DESCS - 1) {
543                         i = 0;
544                         desc->config0 = END_OF_RING | FIRST_SEGMENT |
545                                         LAST_SEGMENT | RX_SEGMENT_MRU;
546                         desc = &(rx_ring)->desc[i];
547                 } else {
548                         desc->config0 = FIRST_SEGMENT | LAST_SEGMENT |
549                                         RX_SEGMENT_MRU;
550                         i++;
551                         desc++;
552                 }
553         }
554
555         rx_ring->alloc_count = received;
556         rx_ring->alloc_index = i;
557 }
558
559 static void eth_check_num_used(struct _tx_ring *tx_ring)
560 {
561         bool stop = false;
562         int i;
563
564         if (tx_ring->num_used >= TX_DESCS - TX_DESC_RESERVE)
565                 stop = true;
566
567         if (tx_ring->stopped == stop)
568                 return;
569
570         tx_ring->stopped = stop;
571         for (i = 0; i < 4; i++) {
572                 struct port *port = switch_port_tab[i];
573                 struct net_device *dev;
574
575                 if (!port)
576                         continue;
577
578                 dev = port->netdev;
579                 if (stop)
580                         netif_stop_queue(dev);
581                 else
582                         netif_wake_queue(dev);
583         }
584 }
585
586 static int eth_complete_tx(struct sw *sw)
587 {
588         struct _tx_ring *tx_ring = &sw->tx_ring;
589         struct tx_desc *desc;
590         int i;
591         int index;
592         int num_used = tx_ring->num_used;
593         struct sk_buff *skb;
594
595         index = tx_ring->free_index;
596         desc = &(tx_ring)->desc[index];
597         for (i = 0; i < num_used; i++) {
598                 if (desc->cown) {
599                         skb = tx_ring->buff_tab[index];
600                         tx_ring->buff_tab[index] = 0;
601                         if (skb)
602                                 dev_kfree_skb_any(skb);
603                         dma_unmap_single(NULL, tx_ring->phys_tab[index],
604                                 desc->sdl, DMA_TO_DEVICE);
605                         if (++index == TX_DESCS) {
606                                 index = 0;
607                                 desc = &(tx_ring)->desc[index];
608                         } else {
609                                 desc++;
610                         }
611                 } else {
612                         break;
613                 }
614         }
615         tx_ring->free_index = index;
616         tx_ring->num_used -= i;
617         eth_check_num_used(tx_ring);
618
619         return TX_DESCS - tx_ring->num_used;
620 }
621
622 static int eth_poll(struct napi_struct *napi, int budget)
623 {
624         struct sw *sw = container_of(napi, struct sw, napi);
625         struct _rx_ring *rx_ring = &sw->rx_ring;
626         int received = 0;
627         unsigned int length;
628         unsigned int i = rx_ring->cur_index;
629         struct rx_desc *desc = &(rx_ring)->desc[i];
630         unsigned int alloc_count = rx_ring->alloc_count;
631
632         while (desc->cown && alloc_count + received < RX_DESCS - 1) {
633                 struct sk_buff *skb;
634                 int reserve = SKB_HEAD_ALIGN;
635
636                 if (received >= budget)
637                         break;
638
639                 /* process received frame */
640                 dma_unmap_single(NULL, rx_ring->phys_tab[i],
641                                  RX_SEGMENT_MRU, DMA_FROM_DEVICE);
642
643                 skb = build_skb(rx_ring->buff_tab[i], 0);
644                 if (!skb)
645                         break;
646
647                 skb->dev = switch_port_tab[desc->sp]->netdev;
648
649                 length = desc->sdl;
650                 if (desc->fsd && !desc->lsd)
651                         length = RX_SEGMENT_MRU;
652
653                 if (!desc->fsd) {
654                         reserve -= NET_IP_ALIGN;
655                         if (!desc->lsd)
656                                 length += NET_IP_ALIGN;
657                 }
658
659                 skb_reserve(skb, reserve);
660                 skb_put(skb, length);
661
662                 if (!sw->frag_first)
663                         sw->frag_first = skb;
664                 else {
665                         if (sw->frag_first == sw->frag_last)
666                                 skb_frag_add_head(sw->frag_first, skb);
667                         else
668                                 sw->frag_last->next = skb;
669                         sw->frag_first->len += skb->len;
670                         sw->frag_first->data_len += skb->len;
671                         sw->frag_first->truesize += skb->truesize;
672                 }
673                 sw->frag_last = skb;
674
675                 if (desc->lsd) {
676                         struct net_device *dev;
677
678                         skb = sw->frag_first;
679                         dev = skb->dev;
680                         skb->protocol = eth_type_trans(skb, dev);
681
682                         dev->stats.rx_packets++;
683                         dev->stats.rx_bytes += skb->len;
684
685                         /* RX Hardware checksum offload */
686                         skb->ip_summed = CHECKSUM_NONE;
687                         switch (desc->prot) {
688                                 case 1:
689                                 case 2:
690                                 case 5:
691                                 case 6:
692                                 case 13:
693                                 case 14:
694                                         if (!desc->l4f) {
695                                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
696                                                 napi_gro_receive(napi, skb);
697                                                 break;
698                                         }
699                                         /* fall through */
700                                 default:
701                                         netif_receive_skb(skb);
702                                         break;
703                         }
704
705                         sw->frag_first = NULL;
706                         sw->frag_last = NULL;
707                 }
708
709                 received++;
710                 if (++i == RX_DESCS) {
711                         i = 0;
712                         desc = &(rx_ring)->desc[i];
713                 } else {
714                         desc++;
715                 }
716         }
717
718         rx_ring->cur_index = i;
719         if (!received) {
720                 napi_complete(napi);
721                 enable_irq(IRQ_CNS3XXX_SW_R0RXC);
722
723                 /* if rx descriptors are full schedule another poll */
724                 if (rx_ring->desc[(i-1) & (RX_DESCS-1)].cown)
725                         eth_schedule_poll(sw);
726         }
727
728         spin_lock_bh(&tx_lock);
729         eth_complete_tx(sw);
730         spin_unlock_bh(&tx_lock);
731
732         cns3xxx_alloc_rx_buf(sw, received);
733
734         wmb();
735         enable_rx_dma(sw);
736
737         return received;
738 }
739
740 static void eth_set_desc(struct _tx_ring *tx_ring, int index, int index_last,
741                          void *data, int len, u32 config0, u32 pmap)
742 {
743         struct tx_desc *tx_desc = &(tx_ring)->desc[index];
744         unsigned int phys;
745
746         phys = dma_map_single(NULL, data, len, DMA_TO_DEVICE);
747         tx_desc->sdp = phys;
748         tx_desc->pmap = pmap;
749         tx_ring->phys_tab[index] = phys;
750
751         config0 |= len;
752         if (index == TX_DESCS - 1)
753                 config0 |= END_OF_RING;
754         if (index == index_last)
755                 config0 |= LAST_SEGMENT;
756
757         wmb();
758         tx_desc->config0 = config0;
759 }
760
761 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
762 {
763         struct port *port = netdev_priv(dev);
764         struct sw *sw = port->sw;
765         struct _tx_ring *tx_ring = &sw->tx_ring;
766         struct sk_buff *skb1;
767         char pmap = (1 << port->id);
768         int nr_frags = skb_shinfo(skb)->nr_frags;
769         int nr_desc = nr_frags;
770         int index0, index, index_last;
771         int len0;
772         unsigned int i;
773         u32 config0;
774
775         if (pmap == 8)
776                 pmap = (1 << 4);
777
778         skb_walk_frags(skb, skb1)
779                 nr_desc++;
780
781         spin_lock_bh(&tx_lock);
782         if ((tx_ring->num_used + nr_desc + 1) >= TX_DESCS) {
783                 /* clean up tx descriptors when needed */
784                 if (eth_complete_tx(sw) < nr_desc) {
785                         spin_unlock_bh(&tx_lock);
786                         return NETDEV_TX_BUSY;
787                 }
788         }
789
790         index = index0 = tx_ring->cur_index;
791         index_last = (index0 + nr_desc) % TX_DESCS;
792         tx_ring->cur_index = (index_last + 1) % TX_DESCS;
793
794         spin_unlock_bh(&tx_lock);
795
796         config0 = FORCE_ROUTE;
797         if (skb->ip_summed == CHECKSUM_PARTIAL)
798                 config0 |= UDP_CHECKSUM | TCP_CHECKSUM;
799
800         len0 = skb->len;
801
802         /* fragments */
803         for (i = 0; i < nr_frags; i++) {
804                 struct skb_frag_struct *frag;
805                 void *addr;
806
807                 index = (index + 1) % TX_DESCS;
808
809                 frag = &skb_shinfo(skb)->frags[i];
810                 addr = page_address(skb_frag_page(frag)) + frag->page_offset;
811
812                 eth_set_desc(tx_ring, index, index_last, addr, frag->size,
813                              config0, pmap);
814         }
815
816         if (nr_frags)
817                 len0 = skb->len - skb->data_len;
818
819         skb_walk_frags(skb, skb1) {
820                 index = (index + 1) % TX_DESCS;
821                 len0 -= skb1->len;
822
823                 eth_set_desc(tx_ring, index, index_last, skb1->data, skb1->len,
824                              config0, pmap);
825         }
826
827         tx_ring->buff_tab[index0] = skb;
828         eth_set_desc(tx_ring, index0, index_last, skb->data, len0,
829                      config0 | FIRST_SEGMENT, pmap);
830
831         wmb();
832
833         spin_lock(&tx_lock);
834         tx_ring->num_used += nr_desc + 1;
835         spin_unlock(&tx_lock);
836
837         dev->stats.tx_packets++;
838         dev->stats.tx_bytes += skb->len;
839
840         enable_tx_dma(sw);
841
842         return NETDEV_TX_OK;
843 }
844
845 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
846 {
847         struct port *port = netdev_priv(dev);
848
849         if (!netif_running(dev))
850                 return -EINVAL;
851         return phy_mii_ioctl(port->phydev, req, cmd);
852 }
853
854 /* ethtool support */
855
856 static void cns3xxx_get_drvinfo(struct net_device *dev,
857                                struct ethtool_drvinfo *info)
858 {
859         strcpy(info->driver, DRV_NAME);
860         strcpy(info->bus_info, "internal");
861 }
862
863 static int cns3xxx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
864 {
865         struct port *port = netdev_priv(dev);
866         return phy_ethtool_gset(port->phydev, cmd);
867 }
868
869 static int cns3xxx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
870 {
871         struct port *port = netdev_priv(dev);
872         return phy_ethtool_sset(port->phydev, cmd);
873 }
874
875 static int cns3xxx_nway_reset(struct net_device *dev)
876 {
877         struct port *port = netdev_priv(dev);
878         return phy_start_aneg(port->phydev);
879 }
880
881 static struct ethtool_ops cns3xxx_ethtool_ops = {
882         .get_drvinfo = cns3xxx_get_drvinfo,
883         .get_settings = cns3xxx_get_settings,
884         .set_settings = cns3xxx_set_settings,
885         .nway_reset = cns3xxx_nway_reset,
886         .get_link = ethtool_op_get_link,
887 };
888
889
890 static int init_rings(struct sw *sw)
891 {
892         int i;
893         struct _rx_ring *rx_ring = &sw->rx_ring;
894         struct _tx_ring *tx_ring = &sw->tx_ring;
895
896         __raw_writel(0, &sw->regs->fs_dma_ctrl0);
897         __raw_writel(TS_SUSPEND | FS_SUSPEND, &sw->regs->dma_auto_poll_cfg);
898         __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
899         __raw_writel(CLR_FS_STATE | QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
900
901         __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl);
902
903         if (!(rx_dma_pool = dma_pool_create(DRV_NAME, NULL,
904                                             RX_POOL_ALLOC_SIZE, 32, 0)))
905                 return -ENOMEM;
906
907         if (!(rx_ring->desc = dma_pool_alloc(rx_dma_pool, GFP_KERNEL,
908                                               &rx_ring->phys_addr)))
909                 return -ENOMEM;
910         memset(rx_ring->desc, 0, RX_POOL_ALLOC_SIZE);
911
912         /* Setup RX buffers */
913         for (i = 0; i < RX_DESCS; i++) {
914                 struct rx_desc *desc = &(rx_ring)->desc[i];
915                 void *buf;
916
917                 buf = kzalloc(RX_SEGMENT_ALLOC_SIZE, GFP_KERNEL);
918                 if (!buf)
919                         return -ENOMEM;
920
921                 desc->sdl = RX_SEGMENT_MRU;
922                 if (i == (RX_DESCS - 1))
923                         desc->eor = 1;
924                 desc->fsd = 1;
925                 desc->lsd = 1;
926
927                 desc->sdp = dma_map_single(NULL, buf + SKB_HEAD_ALIGN,
928                                            RX_SEGMENT_MRU, DMA_FROM_DEVICE);
929                 if (dma_mapping_error(NULL, desc->sdp))
930                         return -EIO;
931
932                 rx_ring->buff_tab[i] = buf;
933                 rx_ring->phys_tab[i] = desc->sdp;
934                 desc->cown = 0;
935         }
936         __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_ptr0);
937         __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_base_addr0);
938
939         if (!(tx_dma_pool = dma_pool_create(DRV_NAME, NULL,
940                                             TX_POOL_ALLOC_SIZE, 32, 0)))
941                 return -ENOMEM;
942
943         if (!(tx_ring->desc = dma_pool_alloc(tx_dma_pool, GFP_KERNEL,
944                                               &tx_ring->phys_addr)))
945                 return -ENOMEM;
946         memset(tx_ring->desc, 0, TX_POOL_ALLOC_SIZE);
947
948         /* Setup TX buffers */
949         for (i = 0; i < TX_DESCS; i++) {
950                 struct tx_desc *desc = &(tx_ring)->desc[i];
951                 tx_ring->buff_tab[i] = 0;
952
953                 if (i == (TX_DESCS - 1))
954                         desc->eor = 1;
955                 desc->cown = 1;
956         }
957         __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_ptr0);
958         __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_base_addr0);
959
960         return 0;
961 }
962
963 static void destroy_rings(struct sw *sw)
964 {
965         int i;
966         if (sw->rx_ring.desc) {
967                 for (i = 0; i < RX_DESCS; i++) {
968                         struct _rx_ring *rx_ring = &sw->rx_ring;
969                         struct rx_desc *desc = &(rx_ring)->desc[i];
970                         struct sk_buff *skb = sw->rx_ring.buff_tab[i];
971
972                         if (!skb)
973                                 continue;
974
975                         dma_unmap_single(NULL, desc->sdp, RX_SEGMENT_MRU,
976                                          DMA_FROM_DEVICE);
977                         dev_kfree_skb(skb);
978                 }
979                 dma_pool_free(rx_dma_pool, sw->rx_ring.desc, sw->rx_ring.phys_addr);
980                 dma_pool_destroy(rx_dma_pool);
981                 rx_dma_pool = 0;
982                 sw->rx_ring.desc = 0;
983         }
984         if (sw->tx_ring.desc) {
985                 for (i = 0; i < TX_DESCS; i++) {
986                         struct _tx_ring *tx_ring = &sw->tx_ring;
987                         struct tx_desc *desc = &(tx_ring)->desc[i];
988                         struct sk_buff *skb = sw->tx_ring.buff_tab[i];
989                         if (skb) {
990                                 dma_unmap_single(NULL, desc->sdp,
991                                         skb->len, DMA_TO_DEVICE);
992                                 dev_kfree_skb(skb);
993                         }
994                 }
995                 dma_pool_free(tx_dma_pool, sw->tx_ring.desc, sw->tx_ring.phys_addr);
996                 dma_pool_destroy(tx_dma_pool);
997                 tx_dma_pool = 0;
998                 sw->tx_ring.desc = 0;
999         }
1000 }
1001
1002 static int eth_open(struct net_device *dev)
1003 {
1004         struct port *port = netdev_priv(dev);
1005         struct sw *sw = port->sw;
1006         u32 temp;
1007
1008         port->speed = 0;        /* force "link up" message */
1009         phy_start(port->phydev);
1010
1011         netif_start_queue(dev);
1012
1013         if (!ports_open) {
1014                 request_irq(IRQ_CNS3XXX_SW_R0RXC, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev);
1015                 request_irq(IRQ_CNS3XXX_SW_STATUS, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev);
1016                 napi_enable(&sw->napi);
1017                 netif_start_queue(napi_dev);
1018
1019                 __raw_writel(~(MAC0_STATUS_CHANGE | MAC1_STATUS_CHANGE | MAC2_STATUS_CHANGE |
1020                                MAC0_RX_ERROR | MAC1_RX_ERROR | MAC2_RX_ERROR), &sw->regs->intr_mask);
1021
1022                 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1023                 temp &= ~(PORT_DISABLE);
1024                 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1025
1026                 temp = __raw_readl(&sw->regs->dma_auto_poll_cfg);
1027                 temp &= ~(TS_SUSPEND | FS_SUSPEND);
1028                 __raw_writel(temp, &sw->regs->dma_auto_poll_cfg);
1029
1030                 enable_rx_dma(sw);
1031         }
1032         temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1033         temp &= ~(PORT_DISABLE);
1034         __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1035
1036         ports_open++;
1037         netif_carrier_on(dev);
1038
1039         return 0;
1040 }
1041
1042 static int eth_close(struct net_device *dev)
1043 {
1044         struct port *port = netdev_priv(dev);
1045         struct sw *sw = port->sw;
1046         u32 temp;
1047
1048         ports_open--;
1049
1050         temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1051         temp |= (PORT_DISABLE);
1052         __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1053
1054         netif_stop_queue(dev);
1055
1056         phy_stop(port->phydev);
1057
1058         if (!ports_open) {
1059                 disable_irq(IRQ_CNS3XXX_SW_R0RXC);
1060                 free_irq(IRQ_CNS3XXX_SW_R0RXC, napi_dev);
1061                 disable_irq(IRQ_CNS3XXX_SW_STATUS);
1062                 free_irq(IRQ_CNS3XXX_SW_STATUS, napi_dev);
1063                 napi_disable(&sw->napi);
1064                 netif_stop_queue(napi_dev);
1065                 temp = __raw_readl(&sw->regs->mac_cfg[2]);
1066                 temp |= (PORT_DISABLE);
1067                 __raw_writel(temp, &sw->regs->mac_cfg[2]);
1068
1069                 __raw_writel(TS_SUSPEND | FS_SUSPEND,
1070                              &sw->regs->dma_auto_poll_cfg);
1071         }
1072
1073         netif_carrier_off(dev);
1074         return 0;
1075 }
1076
1077 static void eth_rx_mode(struct net_device *dev)
1078 {
1079         struct port *port = netdev_priv(dev);
1080         struct sw *sw = port->sw;
1081         u32 temp;
1082
1083         temp = __raw_readl(&sw->regs->mac_glob_cfg);
1084
1085         if (dev->flags & IFF_PROMISC) {
1086                 if (port->id == 3)
1087                         temp |= ((1 << 2) << PROMISC_OFFSET);
1088                 else
1089                         temp |= ((1 << port->id) << PROMISC_OFFSET);
1090         } else {
1091                 if (port->id == 3)
1092                         temp &= ~((1 << 2) << PROMISC_OFFSET);
1093                 else
1094                         temp &= ~((1 << port->id) << PROMISC_OFFSET);
1095         }
1096         __raw_writel(temp, &sw->regs->mac_glob_cfg);
1097 }
1098
1099 static int eth_set_mac(struct net_device *netdev, void *p)
1100 {
1101         struct port *port = netdev_priv(netdev);
1102         struct sw *sw = port->sw;
1103         struct sockaddr *addr = p;
1104         u32 cycles = 0;
1105
1106         if (!is_valid_ether_addr(addr->sa_data))
1107                 return -EADDRNOTAVAIL;
1108
1109         /* Invalidate old ARL Entry */
1110         if (port->id == 3)
1111                 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1112         else
1113                 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1114         __raw_writel( ((netdev->dev_addr[0] << 24) | (netdev->dev_addr[1] << 16) |
1115                         (netdev->dev_addr[2] << 8) | (netdev->dev_addr[3])),
1116                         &sw->regs->arl_ctrl[1]);
1117
1118         __raw_writel( ((netdev->dev_addr[4] << 24) | (netdev->dev_addr[5] << 16) |
1119                         (1 << 1)),
1120                         &sw->regs->arl_ctrl[2]);
1121         __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1122
1123         while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1124                         && cycles < 5000) {
1125                 udelay(1);
1126                 cycles++;
1127         }
1128
1129         cycles = 0;
1130         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1131
1132         if (port->id == 3)
1133                 __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1134         else
1135                 __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]);
1136         __raw_writel( ((addr->sa_data[0] << 24) | (addr->sa_data[1] << 16) |
1137                         (addr->sa_data[2] << 8) | (addr->sa_data[3])),
1138                         &sw->regs->arl_ctrl[1]);
1139
1140         __raw_writel( ((addr->sa_data[4] << 24) | (addr->sa_data[5] << 16) |
1141                         (7 << 4) | (1 << 1)), &sw->regs->arl_ctrl[2]);
1142         __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd);
1143
1144         while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0)
1145                 && cycles < 5000) {
1146                 udelay(1);
1147                 cycles++;
1148         }
1149         return 0;
1150 }
1151
1152 static int cns3xxx_change_mtu(struct net_device *dev, int new_mtu)
1153 {
1154         if (new_mtu > MAX_MTU)
1155                 return -EINVAL;
1156
1157         dev->mtu = new_mtu;
1158         return 0;
1159 }
1160
1161 static const struct net_device_ops cns3xxx_netdev_ops = {
1162         .ndo_open = eth_open,
1163         .ndo_stop = eth_close,
1164         .ndo_start_xmit = eth_xmit,
1165         .ndo_set_rx_mode = eth_rx_mode,
1166         .ndo_do_ioctl = eth_ioctl,
1167         .ndo_change_mtu = cns3xxx_change_mtu,
1168         .ndo_set_mac_address = eth_set_mac,
1169         .ndo_validate_addr = eth_validate_addr,
1170 };
1171
1172 static int eth_init_one(struct platform_device *pdev)
1173 {
1174         int i;
1175         struct port *port;
1176         struct sw *sw;
1177         struct net_device *dev;
1178         struct cns3xxx_plat_info *plat = pdev->dev.platform_data;
1179         u32 regs_phys;
1180         char phy_id[MII_BUS_ID_SIZE + 3];
1181         int err;
1182         u32 temp;
1183
1184         if (!(napi_dev = alloc_etherdev(sizeof(struct sw))))
1185                 return -ENOMEM;
1186         strcpy(napi_dev->name, "switch%d");
1187         napi_dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1188
1189         SET_NETDEV_DEV(napi_dev, &pdev->dev);
1190         sw = netdev_priv(napi_dev);
1191         memset(sw, 0, sizeof(struct sw));
1192         sw->regs = (struct switch_regs __iomem *)CNS3XXX_SWITCH_BASE_VIRT;
1193         regs_phys = CNS3XXX_SWITCH_BASE;
1194         sw->mem_res = request_mem_region(regs_phys, REGS_SIZE, napi_dev->name);
1195         if (!sw->mem_res) {
1196                 err = -EBUSY;
1197                 goto err_free;
1198         }
1199
1200         temp = __raw_readl(&sw->regs->phy_auto_addr);
1201         temp |= (3 << 30); /* maximum frame length: 9600 bytes */
1202         __raw_writel(temp, &sw->regs->phy_auto_addr);
1203
1204         for (i = 0; i < 4; i++) {
1205                 temp = __raw_readl(&sw->regs->mac_cfg[i]);
1206                 temp |= (PORT_DISABLE);
1207                 __raw_writel(temp, &sw->regs->mac_cfg[i]);
1208         }
1209
1210         temp = PORT_DISABLE;
1211         __raw_writel(temp, &sw->regs->mac_cfg[2]);
1212
1213         temp = __raw_readl(&sw->regs->vlan_cfg);
1214         temp |= NIC_MODE | VLAN_UNAWARE;
1215         __raw_writel(temp, &sw->regs->vlan_cfg);
1216
1217         __raw_writel(UNKNOWN_VLAN_TO_CPU |
1218                      CRC_STRIPPING, &sw->regs->mac_glob_cfg);
1219
1220         if ((err = init_rings(sw)) != 0) {
1221                 destroy_rings(sw);
1222                 err = -ENOMEM;
1223                 goto err_free;
1224         }
1225         platform_set_drvdata(pdev, napi_dev);
1226
1227         netif_napi_add(napi_dev, &sw->napi, eth_poll, NAPI_WEIGHT);
1228
1229         for (i = 0; i < 3; i++) {
1230                 if (!(plat->ports & (1 << i))) {
1231                         continue;
1232                 }
1233
1234                 if (!(dev = alloc_etherdev(sizeof(struct port)))) {
1235                         goto free_ports;
1236                 }
1237
1238                 port = netdev_priv(dev);
1239                 port->netdev = dev;
1240                 if (i == 2)
1241                         port->id = 3;
1242                 else
1243                         port->id = i;
1244                 port->sw = sw;
1245
1246                 temp = __raw_readl(&sw->regs->mac_cfg[port->id]);
1247                 temp |= (PORT_DISABLE | PORT_BLOCK_STATE | PORT_LEARN_DIS);
1248                 __raw_writel(temp, &sw->regs->mac_cfg[port->id]);
1249
1250                 dev->netdev_ops = &cns3xxx_netdev_ops;
1251                 dev->ethtool_ops = &cns3xxx_ethtool_ops;
1252                 dev->tx_queue_len = 1000;
1253                 dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
1254
1255                 switch_port_tab[port->id] = port;
1256                 memcpy(dev->dev_addr, &plat->hwaddr[i], ETH_ALEN);
1257
1258                 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy[i]);
1259                 port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link, 0,
1260                         PHY_INTERFACE_MODE_RGMII);
1261                 if ((err = IS_ERR(port->phydev))) {
1262                         switch_port_tab[port->id] = 0;
1263                         free_netdev(dev);
1264                         goto free_ports;
1265                 }
1266
1267                 port->phydev->irq = PHY_IGNORE_INTERRUPT;
1268
1269                 if ((err = register_netdev(dev))) {
1270                         phy_disconnect(port->phydev);
1271                         switch_port_tab[port->id] = 0;
1272                         free_netdev(dev);
1273                         goto free_ports;
1274                 }
1275
1276                 printk(KERN_INFO "%s: RGMII PHY %i on cns3xxx Switch\n", dev->name, plat->phy[i]);
1277                 netif_carrier_off(dev);
1278                 dev = 0;
1279         }
1280
1281         return 0;
1282
1283 free_ports:
1284         err = -ENOMEM;
1285         for (--i; i >= 0; i--) {
1286                 if (switch_port_tab[i]) {
1287                         port = switch_port_tab[i];
1288                         dev = port->netdev;
1289                         unregister_netdev(dev);
1290                         phy_disconnect(port->phydev);
1291                         switch_port_tab[i] = 0;
1292                         free_netdev(dev);
1293                 }
1294         }
1295 err_free:
1296         free_netdev(napi_dev);
1297         return err;
1298 }
1299
1300 static int eth_remove_one(struct platform_device *pdev)
1301 {
1302         struct net_device *dev = platform_get_drvdata(pdev);
1303         struct sw *sw = netdev_priv(dev);
1304         int i;
1305         destroy_rings(sw);
1306
1307         for (i = 3; i >= 0; i--) {
1308                 if (switch_port_tab[i]) {
1309                         struct port *port = switch_port_tab[i];
1310                         struct net_device *dev = port->netdev;
1311                         unregister_netdev(dev);
1312                         phy_disconnect(port->phydev);
1313                         switch_port_tab[i] = 0;
1314                         free_netdev(dev);
1315                 }
1316         }
1317
1318         release_resource(sw->mem_res);
1319         free_netdev(napi_dev);
1320         return 0;
1321 }
1322
1323 static struct platform_driver cns3xxx_eth_driver = {
1324         .driver.name    = DRV_NAME,
1325         .probe          = eth_init_one,
1326         .remove         = eth_remove_one,
1327 };
1328
1329 static int __init eth_init_module(void)
1330 {
1331         int err;
1332         if ((err = cns3xxx_mdio_register()))
1333                 return err;
1334         return platform_driver_register(&cns3xxx_eth_driver);
1335 }
1336
1337 static void __exit eth_cleanup_module(void)
1338 {
1339         platform_driver_unregister(&cns3xxx_eth_driver);
1340         cns3xxx_mdio_remove();
1341 }
1342
1343 module_init(eth_init_module);
1344 module_exit(eth_cleanup_module);
1345
1346 MODULE_AUTHOR("Chris Lang");
1347 MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver");
1348 MODULE_LICENSE("GPL v2");
1349 MODULE_ALIAS("platform:cns3xxx_eth");