target/linux/brcm2708/patches-4.1/0189-Add-SMI-driver.patch

   1 From 8174e93335b0ebd7d7eb4484cd1518547b00d336 Mon Sep 17 00:00:00 2001
   2 From: Luke Wren <wren6991@gmail.com>
   3 Date: Sat, 5 Sep 2015 01:14:45 +0100
   4 Subject: [PATCH 189/222] Add SMI driver
   5
   6 Signed-off-by: Luke Wren <wren6991@gmail.com>
   7 ---
   8  .../bindings/misc/brcm,bcm2835-smi-dev.txt         |  17 +
   9  .../devicetree/bindings/misc/brcm,bcm2835-smi.txt  |  48 +
  10  arch/arm/boot/dts/bcm2708_common.dtsi              |  11 +
  11  arch/arm/boot/dts/overlays/Makefile                |   2 +
  12  arch/arm/boot/dts/overlays/smi-dev-overlay.dts     |  18 +
  13  arch/arm/boot/dts/overlays/smi-overlay.dts         |  37 +
  14  drivers/char/broadcom/Kconfig                      |   8 +
  15  drivers/char/broadcom/Makefile                     |   2 +-
  16  drivers/char/broadcom/bcm2835_smi_dev.c            | 402 +++++++++
  17  drivers/misc/Kconfig                               |   8 +
  18  drivers/misc/Makefile                              |   1 +
  19  drivers/misc/bcm2835_smi.c                         | 985 +++++++++++++++++++++
  20  include/linux/broadcom/bcm2835_smi.h               | 391 ++++++++
  21  13 files changed, 1929 insertions(+), 1 deletion(-)
  22  create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt
  23  create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt
  24  create mode 100644 arch/arm/boot/dts/overlays/smi-dev-overlay.dts
  25  create mode 100644 arch/arm/boot/dts/overlays/smi-overlay.dts
  26  create mode 100644 drivers/char/broadcom/bcm2835_smi_dev.c
  27  create mode 100644 drivers/misc/bcm2835_smi.c
  28  create mode 100644 include/linux/broadcom/bcm2835_smi.h
  29
  30 --- /dev/null
  31 +++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt
  32 @@ -0,0 +1,17 @@
  33 +* Broadcom BCM2835 SMI character device driver.
  34 +
  35 +SMI or secondary memory interface is a peripheral specific to certain Broadcom
  36 +SOCs, and is helpful for talking to things like parallel-interface displays
  37 +and NAND flashes (in fact, most things with a parallel register interface).
  38 +
  39 +This driver adds a character device which provides a user-space interface to
  40 +an instance of the SMI driver.
  41 +
  42 +Required properties:
  43 +- compatible: "brcm,bcm2835-smi-dev"
  44 +- smi_handle: a phandle to the smi node.
  45 +
  46 +Optional properties:
  47 +- None.
  48 +
  49 +
  50 --- /dev/null
  51 +++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt
  52 @@ -0,0 +1,48 @@
  53 +* Broadcom BCM2835 SMI driver.
  54 +
  55 +SMI or secondary memory interface is a peripheral specific to certain Broadcom
  56 +SOCs, and is helpful for talking to things like parallel-interface displays
  57 +and NAND flashes (in fact, most things with a parallel register interface).
  58 +
  59 +Required properties:
  60 +- compatible: "brcm,bcm2835-smi"
  61 +- reg: Should contain location and length of SMI registers and SMI clkman regs
  62 +- interrupts: *the* SMI interrupt.
  63 +- pinctrl-names: should be "default".
  64 +- pinctrl-0: the phandle of the gpio pin node.
  65 +- brcm,smi-clock-source: the clock source for clkman
  66 +- brcm,smi-clock-divisor: the integer clock divisor for clkman
  67 +- dmas: the dma controller phandle and the DREQ number (4 on a 2835)
  68 +- dma-names: the name used by the driver to request its channel.
  69 +  Should be "rx-tx".
  70 +
  71 +Optional properties:
  72 +- None.
  73 +
  74 +Examples:
  75 +
  76 +8 data pin configuration:
  77 +
  78 +smi: smi@7e600000 {
  79 +       compatible = "brcm,bcm2835-smi";
  80 +       reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>;
  81 +       interrupts = <2 16>;
  82 +       pinctrl-names = "default";
  83 +       pinctrl-0 = <&smi_pins>;
  84 +       brcm,smi-clock-source = <6>;
  85 +       brcm,smi-clock-divisor = <4>;
  86 +       dmas = <&dma 4>;
  87 +       dma-names = "rx-tx";
  88 +
  89 +       status = "okay";
  90 +};
  91 +
  92 +smi_pins: smi_pins {
  93 +       brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  94 +       /* Alt 1: SMI */
  95 +       brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5>;
  96 +       /* /CS, /WE and /OE are pulled high, as they are
  97 +          generally active low signals */
  98 +       brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0>;
  99 +};
 100 +
 101 --- a/arch/arm/boot/dts/bcm2708_common.dtsi
 102 +++ b/arch/arm/boot/dts/bcm2708_common.dtsi
 103 @@ -205,6 +205,17 @@
 104                         status = "disabled";
 105                 };
 106
 107 +               smi: smi@7e600000 {
 108 +                       compatible = "brcm,bcm2835-smi";
 109 +                       reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>;
 110 +                       interrupts = <2 16>;
 111 +                       brcm,smi-clock-source = <6>;
 112 +                       brcm,smi-clock-divisor = <4>;
 113 +                       dmas = <&dma 4>;
 114 +                       dma-names = "rx-tx";
 115 +                       status = "disabled";
 116 +               };
 117 +
 118                 usb: usb@7e980000 {
 119                         compatible = "brcm,bcm2708-usb";
 120                         reg = <0x7e980000 0x10000>,
 121 --- a/arch/arm/boot/dts/overlays/Makefile
 122 +++ b/arch/arm/boot/dts/overlays/Makefile
 123 @@ -13,6 +13,8 @@ ifeq ($(CONFIG_ARCH_BCM2835),y)
 124  endif
 125
 126  dtb-$(RPI_DT_OVERLAYS) += ads7846-overlay.dtb
 127 +dtb-$(RPI_DT_OVERLAYS) += smi-overlay.dtb
 128 +dtb-$(RPI_DT_OVERLAYS) += smi-dev-overlay.dtb
 129  dtb-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor-overlay.dtb
 130  dtb-$(RPI_DT_OVERLAYS) += dht11-overlay.dtb
 131  dtb-$(RPI_DT_OVERLAYS) += enc28j60-overlay.dtb
 132 --- /dev/null
 133 +++ b/arch/arm/boot/dts/overlays/smi-dev-overlay.dts
 134 @@ -0,0 +1,18 @@
 135 +// Description: Overlay to enable character device interface for SMI.
 136 +// Author:     Luke Wren <luke@raspberrypi.org>
 137 +
 138 +/dts-v1/;
 139 +/plugin/;
 140 +
 141 +/{
 142 +       fragment@0 {
 143 +               target = <&soc>;
 144 +               __overlay__ {
 145 +                       smi_dev {
 146 +                               compatible = "brcm,bcm2835-smi-dev";
 147 +                               smi_handle = <&smi>;
 148 +                               status = "okay";
 149 +                       };
 150 +               };
 151 +       };
 152 +};
 153 --- /dev/null
 154 +++ b/arch/arm/boot/dts/overlays/smi-overlay.dts
 155 @@ -0,0 +1,37 @@
 156 +// Description:        Overlay to enable the secondary memory interface peripheral
 157 +// Author:     Luke Wren
 158 +
 159 +/dts-v1/;
 160 +/plugin/;
 161 +
 162 +/{
 163 +       compatible = "brcm,bcm2708";
 164 +
 165 +       fragment@0 {
 166 +               target = <&smi>;
 167 +               __overlay__ {
 168 +                       pinctrl-names = "default";
 169 +                       pinctrl-0 = <&smi_pins>;
 170 +                       status = "okay";
 171 +               };
 172 +       };
 173 +
 174 +       fragment@1 {
 175 +               target = <&gpio>;
 176 +               __overlay__ {
 177 +                       smi_pins: smi_pins {
 178 +                               /* Don't configure the top two address bits, as
 179 +                                  these are already used as ID_SD and ID_SC */
 180 +                               brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15
 181 +                                            16 17 18 19 20 21 22 23 24 25>;
 182 +                               /* Alt 0: SMI */
 183 +                               brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
 184 +                                                5 5 5 5 5 5 5 5 5>;
 185 +                               /* /CS, /WE and /OE are pulled high, as they are
 186 +                                  generally active low signals */
 187 +                               brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0
 188 +                                            0 0 0 0 0 0 0>;
 189 +                       };
 190 +               };
 191 +       };
 192 +};
 193 --- a/drivers/char/broadcom/Kconfig
 194 +++ b/drivers/char/broadcom/Kconfig
 195 @@ -47,3 +47,11 @@ config BCM2835_DEVGPIOMEM
 196                 on the 2835. Calling mmap(/dev/gpiomem) will map the GPIO
 197                 register page to the user's pointer.
 198
 199 +config BCM2835_SMI_DEV
 200 +       tristate "Character device driver for BCM2835 Secondary Memory Interface"
 201 +       depends on (MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835) && BCM2835_SMI
 202 +       default m
 203 +       help
 204 +               This driver provides a character device interface (ioctl + read/write) to
 205 +               Broadcom's Secondary Memory interface. The low-level functionality is provided
 206 +               by the SMI driver itself.
 207 --- a/drivers/char/broadcom/Makefile
 208 +++ b/drivers/char/broadcom/Makefile
 209 @@ -4,4 +4,4 @@ obj-$(CONFIG_BCM_VCIO)          += vcio.o
 210  obj-$(CONFIG_BCM_VC_SM)         += vc_sm/
 211
 212  obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o
 213 -
 214 +obj-$(CONFIG_BCM2835_SMI_DEV)  += bcm2835_smi_dev.o
 215 --- /dev/null
 216 +++ b/drivers/char/broadcom/bcm2835_smi_dev.c
 217 @@ -0,0 +1,402 @@
 218 +/**
 219 + * Character device driver for Broadcom Secondary Memory Interface
 220 + *
 221 + * Written by Luke Wren <luke@raspberrypi.org>
 222 + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
 223 + *
 224 + * Redistribution and use in source and binary forms, with or without
 225 + * modification, are permitted provided that the following conditions
 226 + * are met:
 227 + * 1. Redistributions of source code must retain the above copyright
 228 + *    notice, this list of conditions, and the following disclaimer,
 229 + *    without modification.
 230 + * 2. Redistributions in binary form must reproduce the above copyright
 231 + *    notice, this list of conditions and the following disclaimer in the
 232 + *    documentation and/or other materials provided with the distribution.
 233 + * 3. The names of the above-listed copyright holders may not be used
 234 + *    to endorse or promote products derived from this software without
 235 + *    specific prior written permission.
 236 + *
 237 + * ALTERNATIVELY, this software may be distributed under the terms of the
 238 + * GNU General Public License ("GPL") version 2, as published by the Free
 239 + * Software Foundation.
 240 + *
 241 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 242 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 243 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 244 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 245 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 246 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 247 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 248 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 249 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 250 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 251 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 252 + */
 253 +
 254 +#include <linux/kernel.h>
 255 +#include <linux/module.h>
 256 +#include <linux/of.h>
 257 +#include <linux/platform_device.h>
 258 +#include <linux/slab.h>
 259 +#include <linux/mm.h>
 260 +#include <linux/pagemap.h>
 261 +#include <linux/fs.h>
 262 +#include <linux/cdev.h>
 263 +#include <linux/fs.h>
 264 +
 265 +#include <linux/broadcom/bcm2835_smi.h>
 266 +
 267 +#define DEVICE_NAME "bcm2835-smi-dev"
 268 +#define DRIVER_NAME "smi-dev-bcm2835"
 269 +#define DEVICE_MINOR 0
 270 +
 271 +static struct cdev bcm2835_smi_cdev;
 272 +static dev_t bcm2835_smi_devid;
 273 +static struct class *bcm2835_smi_class;
 274 +static struct device *bcm2835_smi_dev;
 275 +
 276 +struct bcm2835_smi_dev_instance {
 277 +       struct device *dev;
 278 +};
 279 +
 280 +static struct bcm2835_smi_instance *smi_inst;
 281 +static struct bcm2835_smi_dev_instance *inst;
 282 +
 283 +static const char *const ioctl_names[] = {
 284 +       "READ_SETTINGS",
 285 +       "WRITE_SETTINGS",
 286 +       "ADDRESS"
 287 +};
 288 +
 289 +/****************************************************************************
 290 +*
 291 +*   SMI chardev file ops
 292 +*
 293 +***************************************************************************/
 294 +static long
 295 +bcm2835_smi_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 296 +{
 297 +       long ret = 0;
 298 +
 299 +       dev_info(inst->dev, "serving ioctl...");
 300 +
 301 +       switch (cmd) {
 302 +       case BCM2835_SMI_IOC_GET_SETTINGS:{
 303 +               struct smi_settings *settings;
 304 +
 305 +               dev_info(inst->dev, "Reading SMI settings to user.");
 306 +               settings = bcm2835_smi_get_settings_from_regs(smi_inst);
 307 +               if (copy_to_user((void *)arg, settings,
 308 +                                sizeof(struct smi_settings)))
 309 +                       dev_err(inst->dev, "settings copy failed.");
 310 +               break;
 311 +       }
 312 +       case BCM2835_SMI_IOC_WRITE_SETTINGS:{
 313 +               struct smi_settings *settings;
 314 +
 315 +               dev_info(inst->dev, "Setting user's SMI settings.");
 316 +               settings = bcm2835_smi_get_settings_from_regs(smi_inst);
 317 +               if (copy_from_user(settings, (void *)arg,
 318 +                                  sizeof(struct smi_settings)))
 319 +                       dev_err(inst->dev, "settings copy failed.");
 320 +               else
 321 +                       bcm2835_smi_set_regs_from_settings(smi_inst);
 322 +               break;
 323 +       }
 324 +       case BCM2835_SMI_IOC_ADDRESS:
 325 +               dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg);
 326 +               bcm2835_smi_set_address(smi_inst, arg);
 327 +               break;
 328 +       default:
 329 +               dev_err(inst->dev, "invalid ioctl cmd: %d", cmd);
 330 +               ret = -ENOTTY;
 331 +               break;
 332 +       }
 333 +
 334 +       return ret;
 335 +}
 336 +
 337 +static int bcm2835_smi_open(struct inode *inode, struct file *file)
 338 +{
 339 +       int dev = iminor(inode);
 340 +
 341 +       dev_dbg(inst->dev, "SMI device opened.");
 342 +
 343 +       if (dev != DEVICE_MINOR) {
 344 +               dev_err(inst->dev,
 345 +                       "bcm2835_smi_release: Unknown minor device: %d",
 346 +                       dev);
 347 +               return -ENXIO;
 348 +       }
 349 +
 350 +       return 0;
 351 +}
 352 +
 353 +static int bcm2835_smi_release(struct inode *inode, struct file *file)
 354 +{
 355 +       int dev = iminor(inode);
 356 +
 357 +       if (dev != DEVICE_MINOR) {
 358 +               dev_err(inst->dev,
 359 +                       "bcm2835_smi_release: Unknown minor device %d", dev);
 360 +               return -ENXIO;
 361 +       }
 362 +
 363 +       return 0;
 364 +}
 365 +
 366 +static ssize_t dma_bounce_user(
 367 +       enum dma_transfer_direction dma_dir,
 368 +       char __user *user_ptr,
 369 +       size_t count,
 370 +       struct bcm2835_smi_bounce_info *bounce)
 371 +{
 372 +       int chunk_size;
 373 +       int chunk_no = 0;
 374 +       int count_left = count;
 375 +
 376 +       while (count_left) {
 377 +               int rv;
 378 +               void *buf;
 379 +
 380 +               /* Wait for current chunk to complete: */
 381 +               if (down_timeout(&bounce->callback_sem,
 382 +                       msecs_to_jiffies(1000))) {
 383 +                       dev_err(inst->dev, "DMA bounce timed out");
 384 +                       count -= (count_left);
 385 +                       break;
 386 +               }
 387 +
 388 +               if (bounce->callback_sem.count >= DMA_BOUNCE_BUFFER_COUNT - 1)
 389 +                       dev_err(inst->dev, "WARNING: Ring buffer overflow");
 390 +               chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
 391 +                       DMA_BOUNCE_BUFFER_SIZE : count_left;
 392 +               buf = bounce->buffer[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
 393 +               if (dma_dir == DMA_DEV_TO_MEM)
 394 +                       rv = copy_to_user(user_ptr, buf, chunk_size);
 395 +               else
 396 +                       rv = copy_from_user(buf, user_ptr, chunk_size);
 397 +               if (rv)
 398 +                       dev_err(inst->dev, "copy_*_user() failed!: %d", rv);
 399 +               user_ptr += chunk_size;
 400 +               count_left -= chunk_size;
 401 +               chunk_no++;
 402 +       }
 403 +       return count;
 404 +}
 405 +
 406 +static ssize_t
 407 +bcm2835_read_file(struct file *f, char __user *user_ptr,
 408 +                 size_t count, loff_t *offs)
 409 +{
 410 +       int odd_bytes;
 411 +
 412 +       dev_dbg(inst->dev, "User reading %d bytes from SMI.", count);
 413 +       /* We don't want to DMA a number of bytes % 4 != 0 (32 bit FIFO) */
 414 +       if (count > DMA_THRESHOLD_BYTES)
 415 +               odd_bytes = count & 0x3;
 416 +       else
 417 +               odd_bytes = count;
 418 +       count -= odd_bytes;
 419 +       if (count) {
 420 +               struct bcm2835_smi_bounce_info *bounce;
 421 +
 422 +               count = bcm2835_smi_user_dma(smi_inst,
 423 +                       DMA_DEV_TO_MEM, user_ptr, count,
 424 +                       &bounce);
 425 +               if (count)
 426 +                       count = dma_bounce_user(DMA_DEV_TO_MEM, user_ptr,
 427 +                               count, bounce);
 428 +       }
 429 +       if (odd_bytes) {
 430 +               /* Read from FIFO directly if not using DMA */
 431 +               uint8_t buf[DMA_THRESHOLD_BYTES];
 432 +
 433 +               bcm2835_smi_read_buf(smi_inst, buf, odd_bytes);
 434 +               if (copy_to_user(user_ptr, buf, odd_bytes))
 435 +                       dev_err(inst->dev, "copy_to_user() failed.");
 436 +               count += odd_bytes;
 437 +
 438 +       }
 439 +       return count;
 440 +}
 441 +
 442 +static ssize_t
 443 +bcm2835_write_file(struct file *f, const char __user *user_ptr,
 444 +                  size_t count, loff_t *offs)
 445 +{
 446 +       int odd_bytes;
 447 +
 448 +       dev_dbg(inst->dev, "User writing %d bytes to SMI.", count);
 449 +       if (count > DMA_THRESHOLD_BYTES)
 450 +               odd_bytes = count & 0x3;
 451 +       else
 452 +               odd_bytes = count;
 453 +       count -= odd_bytes;
 454 +       if (count) {
 455 +               struct bcm2835_smi_bounce_info *bounce;
 456 +
 457 +               count = bcm2835_smi_user_dma(smi_inst,
 458 +                       DMA_MEM_TO_DEV, (char __user *)user_ptr, count,
 459 +                       &bounce);
 460 +               if (count)
 461 +                       count = dma_bounce_user(DMA_MEM_TO_DEV,
 462 +                               (char __user *)user_ptr,
 463 +                               count, bounce);
 464 +       }
 465 +       if (odd_bytes) {
 466 +               uint8_t buf[DMA_THRESHOLD_BYTES];
 467 +
 468 +               if (copy_from_user(buf, user_ptr, odd_bytes))
 469 +                       dev_err(inst->dev, "copy_from_user() failed.");
 470 +               else
 471 +                       bcm2835_smi_write_buf(smi_inst, buf, odd_bytes);
 472 +               count += odd_bytes;
 473 +       }
 474 +       return count;
 475 +}
 476 +
 477 +static const struct file_operations
 478 +bcm2835_smi_fops = {
 479 +       .owner = THIS_MODULE,
 480 +       .unlocked_ioctl = bcm2835_smi_ioctl,
 481 +       .open = bcm2835_smi_open,
 482 +       .release = bcm2835_smi_release,
 483 +       .read = bcm2835_read_file,
 484 +       .write = bcm2835_write_file,
 485 +};
 486 +
 487 +
 488 +/****************************************************************************
 489 +*
 490 +*   bcm2835_smi_probe - called when the driver is loaded.
 491 +*
 492 +***************************************************************************/
 493 +
 494 +static int bcm2835_smi_dev_probe(struct platform_device *pdev)
 495 +{
 496 +       int err;
 497 +       void *ptr_err;
 498 +       struct device *dev = &pdev->dev;
 499 +       struct device_node *node = dev->of_node, *smi_node;
 500 +
 501 +       if (!node) {
 502 +               dev_err(dev, "No device tree node supplied!");
 503 +               return -EINVAL;
 504 +       }
 505 +
 506 +       smi_node = of_parse_phandle(node, "smi_handle", 0);
 507 +
 508 +       if (!smi_node) {
 509 +               dev_err(dev, "No such property: smi_handle");
 510 +               return -ENXIO;
 511 +       }
 512 +
 513 +       smi_inst = bcm2835_smi_get(smi_node);
 514 +
 515 +       if (!smi_inst)
 516 +               return -EPROBE_DEFER;
 517 +
 518 +       /* Allocate buffers and instance data */
 519 +
 520 +       inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
 521 +
 522 +       if (!inst)
 523 +               return -ENOMEM;
 524 +
 525 +       inst->dev = dev;
 526 +
 527 +       /* Create character device entries */
 528 +
 529 +       err = alloc_chrdev_region(&bcm2835_smi_devid,
 530 +                                 DEVICE_MINOR, 1, DEVICE_NAME);
 531 +       if (err != 0) {
 532 +               dev_err(inst->dev, "unable to allocate device number");
 533 +               return -ENOMEM;
 534 +       }
 535 +       cdev_init(&bcm2835_smi_cdev, &bcm2835_smi_fops);
 536 +       bcm2835_smi_cdev.owner = THIS_MODULE;
 537 +       err = cdev_add(&bcm2835_smi_cdev, bcm2835_smi_devid, 1);
 538 +       if (err != 0) {
 539 +               dev_err(inst->dev, "unable to register device");
 540 +               err = -ENOMEM;
 541 +               goto failed_cdev_add;
 542 +       }
 543 +
 544 +       /* Create sysfs entries */
 545 +
 546 +       bcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME);
 547 +       ptr_err = bcm2835_smi_class;
 548 +       if (IS_ERR(ptr_err))
 549 +               goto failed_class_create;
 550 +
 551 +       bcm2835_smi_dev = device_create(bcm2835_smi_class, NULL,
 552 +                                       bcm2835_smi_devid, NULL,
 553 +                                       "smi");
 554 +       ptr_err = bcm2835_smi_dev;
 555 +       if (IS_ERR(ptr_err))
 556 +               goto failed_device_create;
 557 +
 558 +       dev_info(inst->dev, "initialised");
 559 +
 560 +       return 0;
 561 +
 562 +failed_device_create:
 563 +       class_destroy(bcm2835_smi_class);
 564 +failed_class_create:
 565 +       cdev_del(&bcm2835_smi_cdev);
 566 +       err = PTR_ERR(ptr_err);
 567 +failed_cdev_add:
 568 +       unregister_chrdev_region(bcm2835_smi_devid, 1);
 569 +       dev_err(dev, "could not load bcm2835_smi_dev");
 570 +       return err;
 571 +}
 572 +
 573 +/****************************************************************************
 574 +*
 575 +*   bcm2835_smi_remove - called when the driver is unloaded.
 576 +*
 577 +***************************************************************************/
 578 +
 579 +static int bcm2835_smi_dev_remove(struct platform_device *pdev)
 580 +{
 581 +       device_destroy(bcm2835_smi_class, bcm2835_smi_devid);
 582 +       class_destroy(bcm2835_smi_class);
 583 +       cdev_del(&bcm2835_smi_cdev);
 584 +       unregister_chrdev_region(bcm2835_smi_devid, 1);
 585 +
 586 +       dev_info(inst->dev, "SMI character dev removed - OK");
 587 +       return 0;
 588 +}
 589 +
 590 +/****************************************************************************
 591 +*
 592 +*   Register the driver with device tree
 593 +*
 594 +***************************************************************************/
 595 +
 596 +static const struct of_device_id bcm2835_smi_dev_of_match[] = {
 597 +       {.compatible = "brcm,bcm2835-smi-dev",},
 598 +       { /* sentinel */ },
 599 +};
 600 +
 601 +MODULE_DEVICE_TABLE(of, bcm2835_smi_dev_of_match);
 602 +
 603 +static struct platform_driver bcm2835_smi_dev_driver = {
 604 +       .probe = bcm2835_smi_dev_probe,
 605 +       .remove = bcm2835_smi_dev_remove,
 606 +       .driver = {
 607 +                  .name = DRIVER_NAME,
 608 +                  .owner = THIS_MODULE,
 609 +                  .of_match_table = bcm2835_smi_dev_of_match,
 610 +                  },
 611 +};
 612 +
 613 +module_platform_driver(bcm2835_smi_dev_driver);
 614 +
 615 +MODULE_ALIAS("platform:smi-dev-bcm2835");
 616 +MODULE_LICENSE("GPL");
 617 +MODULE_DESCRIPTION(
 618 +       "Character device driver for BCM2835's secondary memory interface");
 619 +MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
 620 --- a/drivers/misc/Kconfig
 621 +++ b/drivers/misc/Kconfig
 622 @@ -10,6 +10,14 @@ config SENSORS_LIS3LV02D
 623         select INPUT_POLLDEV
 624         default n
 625
 626 +config BCM2835_SMI
 627 +       tristate "Broadcom 283x Secondary Memory Interface driver"
 628 +       depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
 629 +       default m
 630 +       help
 631 +               Driver for enabling and using Broadcom's Secondary/Slow Memory Interface.
 632 +               Appears as /dev/bcm2835_smi. For ioctl interface see drivers/misc/bcm2835_smi.h
 633 +
 634  config AD525X_DPOT
 635         tristate "Analog Devices Digital Potentiometers"
 636         depends on (I2C || SPI) && SYSFS
 637 --- a/drivers/misc/Makefile
 638 +++ b/drivers/misc/Makefile
 639 @@ -9,6 +9,7 @@ obj-$(CONFIG_AD525X_DPOT_SPI)   += ad525x_
 640  obj-$(CONFIG_INTEL_MID_PTI)    += pti.o
 641  obj-$(CONFIG_ATMEL_SSC)                += atmel-ssc.o
 642  obj-$(CONFIG_ATMEL_TCLIB)      += atmel_tclib.o
 643 +obj-$(CONFIG_BCM2835_SMI)      += bcm2835_smi.o
 644  obj-$(CONFIG_BMP085)           += bmp085.o
 645  obj-$(CONFIG_BMP085_I2C)       += bmp085-i2c.o
 646  obj-$(CONFIG_BMP085_SPI)       += bmp085-spi.o
 647 --- /dev/null
 648 +++ b/drivers/misc/bcm2835_smi.c
 649 @@ -0,0 +1,985 @@
 650 +/**
 651 + * Broadcom Secondary Memory Interface driver
 652 + *
 653 + * Written by Luke Wren <luke@raspberrypi.org>
 654 + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
 655 + *
 656 + * Redistribution and use in source and binary forms, with or without
 657 + * modification, are permitted provided that the following conditions
 658 + * are met:
 659 + * 1. Redistributions of source code must retain the above copyright
 660 + *    notice, this list of conditions, and the following disclaimer,
 661 + *    without modification.
 662 + * 2. Redistributions in binary form must reproduce the above copyright
 663 + *    notice, this list of conditions and the following disclaimer in the
 664 + *    documentation and/or other materials provided with the distribution.
 665 + * 3. The names of the above-listed copyright holders may not be used
 666 + *    to endorse or promote products derived from this software without
 667 + *    specific prior written permission.
 668 + *
 669 + * ALTERNATIVELY, this software may be distributed under the terms of the
 670 + * GNU General Public License ("GPL") version 2, as published by the Free
 671 + * Software Foundation.
 672 + *
 673 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 674 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 675 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 676 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 677 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 678 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 679 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 680 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 681 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 682 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 683 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 684 + */
 685 +
 686 +#include <linux/kernel.h>
 687 +#include <linux/module.h>
 688 +#include <linux/of.h>
 689 +#include <linux/platform_device.h>
 690 +#include <linux/of_address.h>
 691 +#include <linux/of_platform.h>
 692 +#include <linux/mm.h>
 693 +#include <linux/slab.h>
 694 +#include <linux/pagemap.h>
 695 +#include <linux/dma-mapping.h>
 696 +#include <linux/dmaengine.h>
 697 +#include <linux/semaphore.h>
 698 +#include <linux/spinlock.h>
 699 +#include <linux/io.h>
 700 +
 701 +#define BCM2835_SMI_IMPLEMENTATION
 702 +#include <linux/broadcom/bcm2835_smi.h>
 703 +
 704 +#define DRIVER_NAME "smi-bcm2835"
 705 +
 706 +#define N_PAGES_FROM_BYTES(n) ((n + PAGE_SIZE-1) / PAGE_SIZE)
 707 +
 708 +#define DMA_WRITE_TO_MEM true
 709 +#define DMA_READ_FROM_MEM false
 710 +
 711 +struct bcm2835_smi_instance {
 712 +       struct device *dev;
 713 +       struct smi_settings settings;
 714 +       __iomem void *smi_regs_ptr, *cm_smi_regs_ptr;
 715 +       dma_addr_t smi_regs_busaddr;
 716 +
 717 +       struct dma_chan *dma_chan;
 718 +       struct dma_slave_config dma_config;
 719 +
 720 +       struct bcm2835_smi_bounce_info bounce;
 721 +
 722 +       struct scatterlist buffer_sgl;
 723 +
 724 +       int clock_source;
 725 +       int clock_divisor;
 726 +
 727 +       /* Sometimes we are called into in an atomic context (e.g. by
 728 +          JFFS2 + MTD) so we can't use a mutex */
 729 +       spinlock_t transaction_lock;
 730 +};
 731 +
 732 +/****************************************************************************
 733 +*
 734 +*   SMI clock manager setup
 735 +*
 736 +***************************************************************************/
 737 +
 738 +static inline void write_smi_cm_reg(struct bcm2835_smi_instance *inst,
 739 +       u32 val, unsigned reg)
 740 +{
 741 +       writel(CM_PWD | val, inst->cm_smi_regs_ptr + reg);
 742 +}
 743 +
 744 +static inline u32 read_smi_cm_reg(struct bcm2835_smi_instance *inst,
 745 +       unsigned reg)
 746 +{
 747 +       return readl(inst->cm_smi_regs_ptr + reg);
 748 +}
 749 +
 750 +static void smi_setup_clock(struct bcm2835_smi_instance *inst)
 751 +{
 752 +       dev_dbg(inst->dev, "Setting up clock...");
 753 +       /* Disable SMI clock and wait for it to stop. */
 754 +       write_smi_cm_reg(inst, 0, CM_SMI_CTL);
 755 +       while (read_smi_cm_reg(inst, CM_SMI_CTL) & CM_SMI_CTL_BUSY)
 756 +               ;
 757 +
 758 +       write_smi_cm_reg(inst, (inst->clock_divisor << CM_SMI_DIV_DIVI_OFFS),
 759 +              CM_SMI_DIV);
 760 +       write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS),
 761 +              CM_SMI_CTL);
 762 +
 763 +       /* Enable the clock */
 764 +       write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS) |
 765 +              CM_SMI_CTL_ENAB, CM_SMI_CTL);
 766 +}
 767 +
 768 +/****************************************************************************
 769 +*
 770 +*   SMI peripheral setup
 771 +*
 772 +***************************************************************************/
 773 +
 774 +static inline void write_smi_reg(struct bcm2835_smi_instance *inst,
 775 +       u32 val, unsigned reg)
 776 +{
 777 +       writel(val, inst->smi_regs_ptr + reg);
 778 +}
 779 +
 780 +static inline u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg)
 781 +{
 782 +       return readl(inst->smi_regs_ptr + reg);
 783 +}
 784 +
 785 +/* Token-paste macro for e.g SMIDSR_RSTROBE ->  value of SMIDSR_RSTROBE_MASK */
 786 +#define _CONCAT(x, y) x##y
 787 +#define CONCAT(x, y) _CONCAT(x, y)
 788 +
 789 +#define SET_BIT_FIELD(dest, field, bits) ((dest) = \
 790 +       ((dest) & ~CONCAT(field, _MASK)) | (((bits) << CONCAT(field, _OFFS))& \
 791 +        CONCAT(field, _MASK)))
 792 +#define GET_BIT_FIELD(src, field) (((src) & \
 793 +       CONCAT(field, _MASK)) >> CONCAT(field, _OFFS))
 794 +
 795 +static void smi_dump_context_labelled(struct bcm2835_smi_instance *inst,
 796 +       const char *label)
 797 +{
 798 +       dev_err(inst->dev, "SMI context dump: %s", label);
 799 +       dev_err(inst->dev, "SMICS:  0x%08x", read_smi_reg(inst, SMICS));
 800 +       dev_err(inst->dev, "SMIL:   0x%08x", read_smi_reg(inst, SMIL));
 801 +       dev_err(inst->dev, "SMIDSR: 0x%08x", read_smi_reg(inst, SMIDSR0));
 802 +       dev_err(inst->dev, "SMIDSW: 0x%08x", read_smi_reg(inst, SMIDSW0));
 803 +       dev_err(inst->dev, "SMIDC:  0x%08x", read_smi_reg(inst, SMIDC));
 804 +       dev_err(inst->dev, "SMIFD:  0x%08x", read_smi_reg(inst, SMIFD));
 805 +       dev_err(inst->dev, " ");
 806 +}
 807 +
 808 +static inline void smi_dump_context(struct bcm2835_smi_instance *inst)
 809 +{
 810 +       smi_dump_context_labelled(inst, "");
 811 +}
 812 +
 813 +static void smi_get_default_settings(struct bcm2835_smi_instance *inst)
 814 +{
 815 +       struct smi_settings *settings = &inst->settings;
 816 +
 817 +       settings->data_width = SMI_WIDTH_16BIT;
 818 +       settings->pack_data = true;
 819 +
 820 +       settings->read_setup_time = 1;
 821 +       settings->read_hold_time = 1;
 822 +       settings->read_pace_time = 1;
 823 +       settings->read_strobe_time = 3;
 824 +
 825 +       settings->write_setup_time = settings->read_setup_time;
 826 +       settings->write_hold_time = settings->read_hold_time;
 827 +       settings->write_pace_time = settings->read_pace_time;
 828 +       settings->write_strobe_time = settings->read_strobe_time;
 829 +
 830 +       settings->dma_enable = true;
 831 +       settings->dma_passthrough_enable = false;
 832 +       settings->dma_read_thresh = 0x01;
 833 +       settings->dma_write_thresh = 0x3f;
 834 +       settings->dma_panic_read_thresh = 0x20;
 835 +       settings->dma_panic_write_thresh = 0x20;
 836 +}
 837 +
 838 +void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *inst)
 839 +{
 840 +       struct smi_settings *settings = &inst->settings;
 841 +       int smidsr_temp = 0, smidsw_temp = 0, smics_temp,
 842 +           smidcs_temp, smidc_temp = 0;
 843 +
 844 +       spin_lock(&inst->transaction_lock);
 845 +
 846 +       /* temporarily disable the peripheral: */
 847 +       smics_temp = read_smi_reg(inst, SMICS);
 848 +       write_smi_reg(inst, 0, SMICS);
 849 +       smidcs_temp = read_smi_reg(inst, SMIDCS);
 850 +       write_smi_reg(inst, 0, SMIDCS);
 851 +
 852 +       if (settings->pack_data)
 853 +               smics_temp |= SMICS_PXLDAT;
 854 +       else
 855 +               smics_temp &= ~SMICS_PXLDAT;
 856 +
 857 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RWIDTH, settings->data_width);
 858 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RSETUP, settings->read_setup_time);
 859 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RHOLD, settings->read_hold_time);
 860 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RPACE, settings->read_pace_time);
 861 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RSTROBE, settings->read_strobe_time);
 862 +       write_smi_reg(inst, smidsr_temp, SMIDSR0);
 863 +
 864 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WWIDTH, settings->data_width);
 865 +       if (settings->data_width == SMI_WIDTH_8BIT)
 866 +               smidsw_temp |= SMIDSW_WSWAP;
 867 +       else
 868 +               smidsw_temp &= ~SMIDSW_WSWAP;
 869 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WSETUP, settings->write_setup_time);
 870 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WHOLD, settings->write_hold_time);
 871 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WPACE, settings->write_pace_time);
 872 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WSTROBE,
 873 +                       settings->write_strobe_time);
 874 +       write_smi_reg(inst, smidsw_temp, SMIDSW0);
 875 +
 876 +       SET_BIT_FIELD(smidc_temp, SMIDC_REQR, settings->dma_read_thresh);
 877 +       SET_BIT_FIELD(smidc_temp, SMIDC_REQW, settings->dma_write_thresh);
 878 +       SET_BIT_FIELD(smidc_temp, SMIDC_PANICR,
 879 +                     settings->dma_panic_read_thresh);
 880 +       SET_BIT_FIELD(smidc_temp, SMIDC_PANICW,
 881 +                     settings->dma_panic_write_thresh);
 882 +       if (settings->dma_passthrough_enable) {
 883 +               smidc_temp |= SMIDC_DMAP;
 884 +               smidsr_temp |= SMIDSR_RDREQ;
 885 +               write_smi_reg(inst, smidsr_temp, SMIDSR0);
 886 +               smidsw_temp |= SMIDSW_WDREQ;
 887 +               write_smi_reg(inst, smidsw_temp, SMIDSW0);
 888 +       } else
 889 +               smidc_temp &= ~SMIDC_DMAP;
 890 +       if (settings->dma_enable)
 891 +               smidc_temp |= SMIDC_DMAEN;
 892 +       else
 893 +               smidc_temp &= ~SMIDC_DMAEN;
 894 +
 895 +       write_smi_reg(inst, smidc_temp, SMIDC);
 896 +
 897 +       /* re-enable (if was previously enabled) */
 898 +       write_smi_reg(inst, smics_temp, SMICS);
 899 +       write_smi_reg(inst, smidcs_temp, SMIDCS);
 900 +
 901 +       spin_unlock(&inst->transaction_lock);
 902 +}
 903 +EXPORT_SYMBOL(bcm2835_smi_set_regs_from_settings);
 904 +
 905 +struct smi_settings *bcm2835_smi_get_settings_from_regs
 906 +       (struct bcm2835_smi_instance *inst)
 907 +{
 908 +       struct smi_settings *settings = &inst->settings;
 909 +       int smidsr, smidsw, smidc;
 910 +
 911 +       spin_lock(&inst->transaction_lock);
 912 +
 913 +       smidsr = read_smi_reg(inst, SMIDSR0);
 914 +       smidsw = read_smi_reg(inst, SMIDSW0);
 915 +       smidc = read_smi_reg(inst, SMIDC);
 916 +
 917 +       settings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ?
 918 +           true : false;
 919 +
 920 +       settings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH);
 921 +       settings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP);
 922 +       settings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD);
 923 +       settings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE);
 924 +       settings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE);
 925 +
 926 +       settings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP);
 927 +       settings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD);
 928 +       settings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE);
 929 +       settings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE);
 930 +
 931 +       settings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR);
 932 +       settings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW);
 933 +       settings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR);
 934 +       settings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW);
 935 +       settings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false;
 936 +       settings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false;
 937 +
 938 +       spin_unlock(&inst->transaction_lock);
 939 +
 940 +       return settings;
 941 +}
 942 +EXPORT_SYMBOL(bcm2835_smi_get_settings_from_regs);
 943 +
 944 +static inline void smi_set_address(struct bcm2835_smi_instance *inst,
 945 +       unsigned int address)
 946 +{
 947 +       int smia_temp = 0, smida_temp = 0;
 948 +
 949 +       SET_BIT_FIELD(smia_temp, SMIA_ADDR, address);
 950 +       SET_BIT_FIELD(smida_temp, SMIDA_ADDR, address);
 951 +
 952 +       /* Write to both address registers - user doesn't care whether we're
 953 +          doing programmed or direct transfers. */
 954 +       write_smi_reg(inst, smia_temp, SMIA);
 955 +       write_smi_reg(inst, smida_temp, SMIDA);
 956 +}
 957 +
 958 +static void smi_setup_regs(struct bcm2835_smi_instance *inst)
 959 +{
 960 +
 961 +       dev_dbg(inst->dev, "Initialising SMI registers...");
 962 +       /* Disable the peripheral if already enabled */
 963 +       write_smi_reg(inst, 0, SMICS);
 964 +       write_smi_reg(inst, 0, SMIDCS);
 965 +
 966 +       smi_get_default_settings(inst);
 967 +       bcm2835_smi_set_regs_from_settings(inst);
 968 +       smi_set_address(inst, 0);
 969 +
 970 +       write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ENABLE, SMICS);
 971 +       write_smi_reg(inst, read_smi_reg(inst, SMIDCS) | SMIDCS_ENABLE,
 972 +               SMIDCS);
 973 +}
 974 +
 975 +/****************************************************************************
 976 +*
 977 +*   Low-level SMI access functions
 978 +*   Other modules should use the exported higher-level functions e.g.
 979 +*   bcm2835_smi_write_buf() unless they have a good reason to use these
 980 +*
 981 +***************************************************************************/
 982 +
 983 +static inline uint32_t smi_read_single_word(struct bcm2835_smi_instance *inst)
 984 +{
 985 +       int timeout = 0;
 986 +
 987 +       write_smi_reg(inst, SMIDCS_ENABLE, SMIDCS);
 988 +       write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_START, SMIDCS);
 989 +       /* Make sure things happen in the right order...*/
 990 +       mb();
 991 +       while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&
 992 +               ++timeout < 10000)
 993 +               ;
 994 +       if (timeout < 10000)
 995 +               return read_smi_reg(inst, SMIDD);
 996 +
 997 +       dev_err(inst->dev,
 998 +               "SMI direct read timed out (is the clock set up correctly?)");
 999 +       return 0;
1000 +}
1001 +
1002 +static inline void smi_write_single_word(struct bcm2835_smi_instance *inst,
1003 +       uint32_t data)
1004 +{
1005 +       int timeout = 0;
1006 +
1007 +       write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE, SMIDCS);
1008 +       write_smi_reg(inst, data, SMIDD);
1009 +       write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE | SMIDCS_START,
1010 +               SMIDCS);
1011 +
1012 +       while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&
1013 +               ++timeout < 10000)
1014 +               ;
1015 +       if (timeout >= 10000)
1016 +               dev_err(inst->dev,
1017 +               "SMI direct write timed out (is the clock set up correctly?)");
1018 +}
1019 +
1020 +/* Initiates a programmed read into the read FIFO. It is up to the caller to
1021 + * read data from the FIFO -  either via paced DMA transfer,
1022 + * or polling SMICS_RXD to check whether data is available.
1023 + * SMICS_ACTIVE will go low upon completion. */
1024 +static void smi_init_programmed_read(struct bcm2835_smi_instance *inst,
1025 +       int num_transfers)
1026 +{
1027 +       int smics_temp;
1028 +
1029 +       /* Disable the peripheral: */
1030 +       smics_temp = read_smi_reg(inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE);
1031 +       write_smi_reg(inst, smics_temp, SMICS);
1032 +       while (read_smi_reg(inst, SMICS) & SMICS_ENABLE)
1033 +               ;
1034 +
1035 +       /* Program the transfer count: */
1036 +       write_smi_reg(inst, num_transfers, SMIL);
1037 +
1038 +       /* re-enable and start: */
1039 +       smics_temp |= SMICS_ENABLE;
1040 +       write_smi_reg(inst, smics_temp, SMICS);
1041 +       smics_temp |= SMICS_CLEAR;
1042 +       /* Just to be certain: */
1043 +       mb();
1044 +       while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
1045 +               ;
1046 +       write_smi_reg(inst, smics_temp, SMICS);
1047 +       smics_temp |= SMICS_START;
1048 +       write_smi_reg(inst, smics_temp, SMICS);
1049 +}
1050 +
1051 +/* Initiates a programmed write sequence, using data from the write FIFO.
1052 + * It is up to the caller to initiate a DMA transfer before calling,
1053 + * or use another method to keep the write FIFO topped up.
1054 + * SMICS_ACTIVE will go low upon completion.
1055 + */
1056 +static void smi_init_programmed_write(struct bcm2835_smi_instance *inst,
1057 +       int num_transfers)
1058 +{
1059 +       int smics_temp;
1060 +
1061 +       /* Disable the peripheral: */
1062 +       smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;
1063 +       write_smi_reg(inst, smics_temp, SMICS);
1064 +       while (read_smi_reg(inst, SMICS) & SMICS_ENABLE)
1065 +               ;
1066 +
1067 +       /* Program the transfer count: */
1068 +       write_smi_reg(inst, num_transfers, SMIL);
1069 +
1070 +       /* setup, re-enable and start: */
1071 +       smics_temp |= SMICS_WRITE | SMICS_ENABLE;
1072 +       write_smi_reg(inst, smics_temp, SMICS);
1073 +       smics_temp |= SMICS_START;
1074 +       write_smi_reg(inst, smics_temp, SMICS);
1075 +}
1076 +
1077 +/* Initiate a read and then poll FIFO for data, reading out as it appears. */
1078 +static void smi_read_fifo(struct bcm2835_smi_instance *inst,
1079 +       uint32_t *dest, int n_bytes)
1080 +{
1081 +       if (read_smi_reg(inst, SMICS) & SMICS_RXD) {
1082 +               smi_dump_context_labelled(inst,
1083 +                       "WARNING: read FIFO not empty at start of read call.");
1084 +               while (read_smi_reg(inst, SMICS))
1085 +                       ;
1086 +       }
1087 +
1088 +       /* Dispatch the read: */
1089 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1090 +               smi_init_programmed_read(inst, n_bytes);
1091 +       else if (inst->settings.data_width == SMI_WIDTH_16BIT)
1092 +               smi_init_programmed_read(inst, n_bytes / 2);
1093 +       else {
1094 +               dev_err(inst->dev, "Unsupported data width for read.");
1095 +               return;
1096 +       }
1097 +
1098 +       /* Poll FIFO to keep it empty */
1099 +       while (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
1100 +               if (read_smi_reg(inst, SMICS) & SMICS_RXD)
1101 +                       *dest++ = read_smi_reg(inst, SMID);
1102 +
1103 +       /* Ensure that the FIFO is emptied */
1104 +       if (read_smi_reg(inst, SMICS) & SMICS_RXD) {
1105 +               int fifo_count;
1106 +
1107 +               fifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD),
1108 +                       SMIFD_FCNT);
1109 +               while (fifo_count--)
1110 +                       *dest++ = read_smi_reg(inst, SMID);
1111 +       }
1112 +
1113 +       if (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
1114 +               smi_dump_context_labelled(inst,
1115 +                       "WARNING: transaction finished but done bit not set.");
1116 +
1117 +       if (read_smi_reg(inst, SMICS) & SMICS_RXD)
1118 +               smi_dump_context_labelled(inst,
1119 +                       "WARNING: read FIFO not empty at end of read call.");
1120 +
1121 +}
1122 +
1123 +/* Initiate a write, and then keep the FIFO topped up. */
1124 +static void smi_write_fifo(struct bcm2835_smi_instance *inst,
1125 +       uint32_t *src, int n_bytes)
1126 +{
1127 +       int i, timeout = 0;
1128 +
1129 +       /* Empty FIFOs if not already so */
1130 +       if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) {
1131 +               smi_dump_context_labelled(inst,
1132 +                   "WARNING: write fifo not empty at start of write call.");
1133 +               write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_CLEAR,
1134 +                       SMICS);
1135 +       }
1136 +
1137 +       /* Initiate the transfer */
1138 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1139 +               smi_init_programmed_write(inst, n_bytes);
1140 +       else if (inst->settings.data_width == SMI_WIDTH_16BIT)
1141 +               smi_init_programmed_write(inst, n_bytes / 2);
1142 +       else {
1143 +               dev_err(inst->dev, "Unsupported data width for write.");
1144 +               return;
1145 +       }
1146 +       /* Fill the FIFO: */
1147 +       for (i = 0; i < (n_bytes - 1) / 4 + 1; ++i) {
1148 +               while (!(read_smi_reg(inst, SMICS) & SMICS_TXD))
1149 +                       ;
1150 +               write_smi_reg(inst, *src++, SMID);
1151 +       }
1152 +       /* Busy wait... */
1153 +       while (!(read_smi_reg(inst, SMICS) & SMICS_DONE) && ++timeout <
1154 +               1000000)
1155 +               ;
1156 +       if (timeout >= 1000000)
1157 +               smi_dump_context_labelled(inst,
1158 +                       "Timed out on write operation!");
1159 +       if (!(read_smi_reg(inst, SMICS) & SMICS_TXE))
1160 +               smi_dump_context_labelled(inst,
1161 +                       "WARNING: FIFO not empty at end of write operation.");
1162 +}
1163 +
1164 +/****************************************************************************
1165 +*
1166 +*   SMI DMA operations
1167 +*
1168 +***************************************************************************/
1169 +
1170 +/* Disable SMI and put it into the correct direction before doing DMA setup.
1171 +   Stops spurious DREQs during setup. Peripheral is re-enabled by init_*() */
1172 +static void smi_disable(struct bcm2835_smi_instance *inst,
1173 +       enum dma_transfer_direction direction)
1174 +{
1175 +       int smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;
1176 +
1177 +       if (direction == DMA_DEV_TO_MEM)
1178 +               smics_temp &= ~SMICS_WRITE;
1179 +       else
1180 +               smics_temp |= SMICS_WRITE;
1181 +       write_smi_reg(inst, smics_temp, SMICS);
1182 +       while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
1183 +               ;
1184 +}
1185 +
1186 +static struct scatterlist *smi_scatterlist_from_buffer(
1187 +       struct bcm2835_smi_instance *inst,
1188 +       dma_addr_t buf,
1189 +       size_t len,
1190 +       struct scatterlist *sg)
1191 +{
1192 +       sg_init_table(sg, 1);
1193 +       sg_dma_address(sg) = buf;
1194 +       sg_dma_len(sg) = len;
1195 +       return sg;
1196 +}
1197 +
1198 +static void smi_dma_callback_user_copy(void *param)
1199 +{
1200 +       /* Notify the bottom half that a chunk is ready for user copy */
1201 +       struct bcm2835_smi_instance *inst =
1202 +               (struct bcm2835_smi_instance *)param;
1203 +
1204 +       up(&inst->bounce.callback_sem);
1205 +}
1206 +
1207 +/* Creates a descriptor, assigns the given callback, and submits the
1208 +   descriptor to dmaengine. Does not block - can queue up multiple
1209 +   descriptors and then wait for them all to complete.
1210 +   sg_len is the number of control blocks, NOT the number of bytes.
1211 +   dir can be DMA_MEM_TO_DEV or DMA_DEV_TO_MEM.
1212 +   callback can be NULL - in this case it is not called. */
1213 +static inline struct dma_async_tx_descriptor *smi_dma_submit_sgl(
1214 +       struct bcm2835_smi_instance *inst,
1215 +       struct scatterlist *sgl,
1216 +       size_t sg_len,
1217 +       enum dma_transfer_direction dir,
1218 +       dma_async_tx_callback callback)
1219 +{
1220 +       struct dma_async_tx_descriptor *desc;
1221 +
1222 +       desc = dmaengine_prep_slave_sg(inst->dma_chan,
1223 +                                      sgl,
1224 +                                      sg_len,
1225 +                                      dir,
1226 +                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK |
1227 +                                      DMA_PREP_FENCE);
1228 +       if (!desc) {
1229 +               dev_err(inst->dev, "read_sgl: dma slave preparation failed!");
1230 +               write_smi_reg(inst, read_smi_reg(inst, SMICS) & ~SMICS_ACTIVE,
1231 +                       SMICS);
1232 +               while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
1233 +                       cpu_relax();
1234 +               write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ACTIVE,
1235 +                       SMICS);
1236 +               return NULL;
1237 +       }
1238 +       desc->callback = callback;
1239 +       desc->callback_param = inst;
1240 +       if (dmaengine_submit(desc) < 0)
1241 +               return NULL;
1242 +       return desc;
1243 +}
1244 +
1245 +/* NB this function blocks until the transfer is complete */
1246 +static void
1247 +smi_dma_read_sgl(struct bcm2835_smi_instance *inst,
1248 +       struct scatterlist *sgl, size_t sg_len, size_t n_bytes)
1249 +{
1250 +       struct dma_async_tx_descriptor *desc;
1251 +
1252 +       /* Disable SMI and set to read before dispatching DMA - if SMI is in
1253 +        * write mode and TX fifo is empty, it will generate a DREQ which may
1254 +        * cause the read DMA to complete before the SMI read command is even
1255 +        * dispatched! We want to dispatch DMA before SMI read so that reading
1256 +        * is gapless, for logic analyser.
1257 +        */
1258 +
1259 +       smi_disable(inst, DMA_DEV_TO_MEM);
1260 +
1261 +       desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_DEV_TO_MEM, NULL);
1262 +       dma_async_issue_pending(inst->dma_chan);
1263 +
1264 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1265 +               smi_init_programmed_read(inst, n_bytes);
1266 +       else
1267 +               smi_init_programmed_read(inst, n_bytes / 2);
1268 +
1269 +       if (dma_wait_for_async_tx(desc) == DMA_ERROR)
1270 +               smi_dump_context_labelled(inst, "DMA timeout!");
1271 +}
1272 +
1273 +static void
1274 +smi_dma_write_sgl(struct bcm2835_smi_instance *inst,
1275 +       struct scatterlist *sgl, size_t sg_len, size_t n_bytes)
1276 +{
1277 +       struct dma_async_tx_descriptor *desc;
1278 +
1279 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1280 +               smi_init_programmed_write(inst, n_bytes);
1281 +       else
1282 +               smi_init_programmed_write(inst, n_bytes / 2);
1283 +
1284 +       desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_MEM_TO_DEV, NULL);
1285 +       dma_async_issue_pending(inst->dma_chan);
1286 +
1287 +       if (dma_wait_for_async_tx(desc) == DMA_ERROR)
1288 +               smi_dump_context_labelled(inst, "DMA timeout!");
1289 +       else
1290 +               /* Wait for SMI to finish our writes */
1291 +               while (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
1292 +                       cpu_relax();
1293 +}
1294 +
1295 +ssize_t bcm2835_smi_user_dma(
1296 +       struct bcm2835_smi_instance *inst,
1297 +       enum dma_transfer_direction dma_dir,
1298 +       char __user *user_ptr, size_t count,
1299 +       struct bcm2835_smi_bounce_info **bounce)
1300 +{
1301 +       int chunk_no = 0, chunk_size, count_left = count;
1302 +       struct scatterlist *sgl;
1303 +       void (*init_trans_func)(struct bcm2835_smi_instance *, int);
1304 +
1305 +       spin_lock(&inst->transaction_lock);
1306 +
1307 +       if (dma_dir == DMA_DEV_TO_MEM)
1308 +               init_trans_func = smi_init_programmed_read;
1309 +       else
1310 +               init_trans_func = smi_init_programmed_write;
1311 +
1312 +       smi_disable(inst, dma_dir);
1313 +
1314 +       sema_init(&inst->bounce.callback_sem, 0);
1315 +       if (bounce)
1316 +               *bounce = &inst->bounce;
1317 +       while (count_left) {
1318 +               chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
1319 +                       DMA_BOUNCE_BUFFER_SIZE : count_left;
1320 +               if (chunk_size == DMA_BOUNCE_BUFFER_SIZE) {
1321 +                       sgl =
1322 +                       &inst->bounce.sgl[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
1323 +               } else {
1324 +                       sgl = smi_scatterlist_from_buffer(
1325 +                               inst,
1326 +                               inst->bounce.phys[
1327 +                                       chunk_no % DMA_BOUNCE_BUFFER_COUNT],
1328 +                               chunk_size,
1329 +                               &inst->buffer_sgl);
1330 +               }
1331 +
1332 +               if (!smi_dma_submit_sgl(inst, sgl, 1, dma_dir,
1333 +                       smi_dma_callback_user_copy
1334 +               )) {
1335 +                       dev_err(inst->dev, "sgl submit failed");
1336 +                       count = 0;
1337 +                       goto out;
1338 +               }
1339 +               count_left -= chunk_size;
1340 +               chunk_no++;
1341 +       }
1342 +       dma_async_issue_pending(inst->dma_chan);
1343 +
1344 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1345 +               init_trans_func(inst, count);
1346 +       else if (inst->settings.data_width == SMI_WIDTH_16BIT)
1347 +               init_trans_func(inst, count / 2);
1348 +out:
1349 +       spin_unlock(&inst->transaction_lock);
1350 +       return count;
1351 +}
1352 +EXPORT_SYMBOL(bcm2835_smi_user_dma);
1353 +
1354 +
1355 +/****************************************************************************
1356 +*
1357 +*   High level buffer transfer functions - for use by other drivers
1358 +*
1359 +***************************************************************************/
1360 +
1361 +/* Buffer must be physically contiguous - i.e. kmalloc, not vmalloc! */
1362 +void bcm2835_smi_write_buf(
1363 +       struct bcm2835_smi_instance *inst,
1364 +       const void *buf, size_t n_bytes)
1365 +{
1366 +       int odd_bytes = n_bytes & 0x3;
1367 +
1368 +       n_bytes -= odd_bytes;
1369 +
1370 +       spin_lock(&inst->transaction_lock);
1371 +
1372 +       if (n_bytes > DMA_THRESHOLD_BYTES) {
1373 +               dma_addr_t phy_addr = dma_map_single(
1374 +                       inst->dev,
1375 +                       (void *)buf,
1376 +                       n_bytes,
1377 +                       DMA_MEM_TO_DEV);
1378 +               struct scatterlist *sgl =
1379 +                       smi_scatterlist_from_buffer(inst, phy_addr, n_bytes,
1380 +                               &inst->buffer_sgl);
1381 +
1382 +               if (!sgl) {
1383 +                       smi_dump_context_labelled(inst,
1384 +                       "Error: could not create scatterlist for write!");
1385 +                       goto out;
1386 +               }
1387 +               smi_dma_write_sgl(inst, sgl, 1, n_bytes);
1388 +
1389 +               dma_unmap_single
1390 +                       (inst->dev, phy_addr, n_bytes, DMA_MEM_TO_DEV);
1391 +       } else if (n_bytes) {
1392 +               smi_write_fifo(inst, (uint32_t *) buf, n_bytes);
1393 +       }
1394 +       buf += n_bytes;
1395 +
1396 +       if (inst->settings.data_width == SMI_WIDTH_8BIT) {
1397 +               while (odd_bytes--)
1398 +                       smi_write_single_word(inst, *(uint8_t *) (buf++));
1399 +       } else {
1400 +               while (odd_bytes >= 2) {
1401 +                       smi_write_single_word(inst, *(uint16_t *)buf);
1402 +                       buf += 2;
1403 +                       odd_bytes -= 2;
1404 +               }
1405 +               if (odd_bytes) {
1406 +                       /* Reading an odd number of bytes on a 16 bit bus is
1407 +                          a user bug. It's kinder to fail early and tell them
1408 +                          than to e.g. transparently give them the bottom byte
1409 +                          of a 16 bit transfer. */
1410 +                       dev_err(inst->dev,
1411 +               "WARNING: odd number of bytes specified for wide transfer.");
1412 +                       dev_err(inst->dev,
1413 +               "At least one byte dropped as a result.");
1414 +                       dump_stack();
1415 +               }
1416 +       }
1417 +out:
1418 +       spin_unlock(&inst->transaction_lock);
1419 +}
1420 +EXPORT_SYMBOL(bcm2835_smi_write_buf);
1421 +
1422 +void bcm2835_smi_read_buf(struct bcm2835_smi_instance *inst,
1423 +       void *buf, size_t n_bytes)
1424 +{
1425 +
1426 +       /* SMI is inherently 32-bit, which causes surprising amounts of mess
1427 +          for bytes % 4 != 0. Easiest to avoid this mess altogether
1428 +          by handling remainder separately. */
1429 +       int odd_bytes = n_bytes & 0x3;
1430 +
1431 +       spin_lock(&inst->transaction_lock);
1432 +       n_bytes -= odd_bytes;
1433 +       if (n_bytes > DMA_THRESHOLD_BYTES) {
1434 +               dma_addr_t phy_addr = dma_map_single(inst->dev,
1435 +                                                    buf, n_bytes,
1436 +                                                    DMA_DEV_TO_MEM);
1437 +               struct scatterlist *sgl = smi_scatterlist_from_buffer(
1438 +                       inst, phy_addr, n_bytes,
1439 +                       &inst->buffer_sgl);
1440 +               if (!sgl) {
1441 +                       smi_dump_context_labelled(inst,
1442 +                       "Error: could not create scatterlist for read!");
1443 +                       goto out;
1444 +               }
1445 +               smi_dma_read_sgl(inst, sgl, 1, n_bytes);
1446 +               dma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_DEV_TO_MEM);
1447 +       } else if (n_bytes) {
1448 +               smi_read_fifo(inst, (uint32_t *)buf, n_bytes);
1449 +       }
1450 +       buf += n_bytes;
1451 +
1452 +       if (inst->settings.data_width == SMI_WIDTH_8BIT) {
1453 +               while (odd_bytes--)
1454 +                       *((uint8_t *) (buf++)) = smi_read_single_word(inst);
1455 +       } else {
1456 +               while (odd_bytes >= 2) {
1457 +                       *(uint16_t *) buf = smi_read_single_word(inst);
1458 +                       buf += 2;
1459 +                       odd_bytes -= 2;
1460 +               }
1461 +               if (odd_bytes) {
1462 +                       dev_err(inst->dev,
1463 +               "WARNING: odd number of bytes specified for wide transfer.");
1464 +                       dev_err(inst->dev,
1465 +               "At least one byte dropped as a result.");
1466 +                       dump_stack();
1467 +               }
1468 +       }
1469 +out:
1470 +       spin_unlock(&inst->transaction_lock);
1471 +}
1472 +EXPORT_SYMBOL(bcm2835_smi_read_buf);
1473 +
1474 +void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
1475 +       unsigned int address)
1476 +{
1477 +       spin_lock(&inst->transaction_lock);
1478 +       smi_set_address(inst, address);
1479 +       spin_unlock(&inst->transaction_lock);
1480 +}
1481 +EXPORT_SYMBOL(bcm2835_smi_set_address);
1482 +
1483 +struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node)
1484 +{
1485 +       struct platform_device *pdev;
1486 +
1487 +       if (!node)
1488 +               return NULL;
1489 +
1490 +       pdev = of_find_device_by_node(node);
1491 +       if (!pdev)
1492 +               return NULL;
1493 +
1494 +       return platform_get_drvdata(pdev);
1495 +}
1496 +EXPORT_SYMBOL(bcm2835_smi_get);
1497 +
1498 +/****************************************************************************
1499 +*
1500 +*   bcm2835_smi_probe - called when the driver is loaded.
1501 +*
1502 +***************************************************************************/
1503 +
1504 +static int bcm2835_smi_dma_setup(struct bcm2835_smi_instance *inst)
1505 +{
1506 +       int i, rv = 0;
1507 +
1508 +       inst->dma_chan = dma_request_slave_channel(inst->dev, "rx-tx");
1509 +
1510 +       inst->dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1511 +       inst->dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1512 +       inst->dma_config.src_addr = inst->smi_regs_busaddr + SMID;
1513 +       inst->dma_config.dst_addr = inst->dma_config.src_addr;
1514 +       /* Direction unimportant - always overridden by prep_slave_sg */
1515 +       inst->dma_config.direction = DMA_DEV_TO_MEM;
1516 +       dmaengine_slave_config(inst->dma_chan, &inst->dma_config);
1517 +       /* Alloc and map bounce buffers */
1518 +       for (i = 0; i < DMA_BOUNCE_BUFFER_COUNT; ++i) {
1519 +               inst->bounce.buffer[i] =
1520 +               dmam_alloc_coherent(inst->dev, DMA_BOUNCE_BUFFER_SIZE,
1521 +                               &inst->bounce.phys[i],
1522 +                               GFP_KERNEL);
1523 +               if (!inst->bounce.buffer[i]) {
1524 +                       dev_err(inst->dev, "Could not allocate buffer!");
1525 +                       rv = -ENOMEM;
1526 +                       break;
1527 +               }
1528 +               smi_scatterlist_from_buffer(
1529 +                       inst,
1530 +                       inst->bounce.phys[i],
1531 +                       DMA_BOUNCE_BUFFER_SIZE,
1532 +                       &inst->bounce.sgl[i]
1533 +               );
1534 +       }
1535 +
1536 +       return rv;
1537 +}
1538 +
1539 +static int bcm2835_smi_probe(struct platform_device *pdev)
1540 +{
1541 +       int err;
1542 +       struct device *dev = &pdev->dev;
1543 +       struct device_node *node = dev->of_node;
1544 +       struct resource *ioresource;
1545 +       struct bcm2835_smi_instance *inst;
1546 +
1547 +       /* Allocate buffers and instance data */
1548 +
1549 +       inst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance),
1550 +               GFP_KERNEL);
1551 +
1552 +       if (!inst)
1553 +               return -ENOMEM;
1554 +
1555 +       inst->dev = dev;
1556 +       spin_lock_init(&inst->transaction_lock);
1557 +
1558 +       /* We require device tree support */
1559 +       if (!node)
1560 +               return -EINVAL;
1561 +
1562 +       ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1563 +       inst->smi_regs_ptr = devm_ioremap_resource(dev, ioresource);
1564 +       ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1565 +       inst->cm_smi_regs_ptr = devm_ioremap_resource(dev, ioresource);
1566 +       inst->smi_regs_busaddr = be32_to_cpu(
1567 +               *of_get_address(node, 0, NULL, NULL));
1568 +       of_property_read_u32(node,
1569 +                            "brcm,smi-clock-source",
1570 +                            &inst->clock_source);
1571 +       of_property_read_u32(node,
1572 +                            "brcm,smi-clock-divisor",
1573 +                            &inst->clock_divisor);
1574 +
1575 +       err = bcm2835_smi_dma_setup(inst);
1576 +       if (err)
1577 +               return err;
1578 +
1579 +       /* Finally, do peripheral setup */
1580 +
1581 +       smi_setup_clock(inst);
1582 +       smi_setup_regs(inst);
1583 +
1584 +       platform_set_drvdata(pdev, inst);
1585 +
1586 +       dev_info(inst->dev, "initialised");
1587 +
1588 +       return 0;
1589 +}
1590 +
1591 +/****************************************************************************
1592 +*
1593 +*   bcm2835_smi_remove - called when the driver is unloaded.
1594 +*
1595 +***************************************************************************/
1596 +
1597 +static int bcm2835_smi_remove(struct platform_device *pdev)
1598 +{
1599 +       struct bcm2835_smi_instance *inst = platform_get_drvdata(pdev);
1600 +       struct device *dev = inst->dev;
1601 +
1602 +       dev_info(dev, "SMI device removed - OK");
1603 +       return 0;
1604 +}
1605 +
1606 +/****************************************************************************
1607 +*
1608 +*   Register the driver with device tree
1609 +*
1610 +***************************************************************************/
1611 +
1612 +static const struct of_device_id bcm2835_smi_of_match[] = {
1613 +       {.compatible = "brcm,bcm2835-smi",},
1614 +       { /* sentinel */ },
1615 +};
1616 +
1617 +MODULE_DEVICE_TABLE(of, bcm2835_smi_of_match);
1618 +
1619 +static struct platform_driver bcm2835_smi_driver = {
1620 +       .probe = bcm2835_smi_probe,
1621 +       .remove = bcm2835_smi_remove,
1622 +       .driver = {
1623 +                  .name = DRIVER_NAME,
1624 +                  .owner = THIS_MODULE,
1625 +                  .of_match_table = bcm2835_smi_of_match,
1626 +                  },
1627 +};
1628 +
1629 +module_platform_driver(bcm2835_smi_driver);
1630 +
1631 +MODULE_ALIAS("platform:smi-bcm2835");
1632 +MODULE_LICENSE("GPL");
1633 +MODULE_DESCRIPTION("Device driver for BCM2835's secondary memory interface");
1634 +MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
1635 --- /dev/null
1636 +++ b/include/linux/broadcom/bcm2835_smi.h
1637 @@ -0,0 +1,391 @@
1638 +/**
1639 + * Declarations and definitions for Broadcom's Secondary Memory Interface
1640 + *
1641 + * Written by Luke Wren <luke@raspberrypi.org>
1642 + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
1643 + * Copyright (c) 2010-2012 Broadcom. All rights reserved.
1644 + *
1645 + * Redistribution and use in source and binary forms, with or without
1646 + * modification, are permitted provided that the following conditions
1647 + * are met:
1648 + * 1. Redistributions of source code must retain the above copyright
1649 + *    notice, this list of conditions, and the following disclaimer,
1650 + *    without modification.
1651 + * 2. Redistributions in binary form must reproduce the above copyright
1652 + *    notice, this list of conditions and the following disclaimer in the
1653 + *    documentation and/or other materials provided with the distribution.
1654 + * 3. The names of the above-listed copyright holders may not be used
1655 + *    to endorse or promote products derived from this software without
1656 + *    specific prior written permission.
1657 + *
1658 + * ALTERNATIVELY, this software may be distributed under the terms of the
1659 + * GNU General Public License ("GPL") version 2, as published by the Free
1660 + * Software Foundation.
1661 + *
1662 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
1663 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
1664 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
1665 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
1666 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
1667 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
1668 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
1669 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
1670 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
1671 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1672 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1673 + */
1674 +
1675 +#ifndef BCM2835_SMI_H
1676 +#define BCM2835_SMI_H
1677 +
1678 +#include <linux/ioctl.h>
1679 +
1680 +#ifndef __KERNEL__
1681 +#include <stdint.h>
1682 +#include <stdbool.h>
1683 +#endif
1684 +
1685 +#define BCM2835_SMI_IOC_MAGIC 0x1
1686 +#define BCM2835_SMI_INVALID_HANDLE (~0)
1687 +
1688 +/* IOCTLs 0x100...0x1ff are not device-specific - we can use them */
1689 +#define BCM2835_SMI_IOC_GET_SETTINGS    _IO(BCM2835_SMI_IOC_MAGIC, 0)
1690 +#define BCM2835_SMI_IOC_WRITE_SETTINGS  _IO(BCM2835_SMI_IOC_MAGIC, 1)
1691 +#define BCM2835_SMI_IOC_ADDRESS         _IO(BCM2835_SMI_IOC_MAGIC, 2)
1692 +#define BCM2835_SMI_IOC_MAX         2
1693 +
1694 +#define SMI_WIDTH_8BIT 0
1695 +#define SMI_WIDTH_16BIT 1
1696 +#define SMI_WIDTH_9BIT 2
1697 +#define SMI_WIDTH_18BIT 3
1698 +
1699 +/* max number of bytes where DMA will not be used */
1700 +#define DMA_THRESHOLD_BYTES 128
1701 +#define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2)
1702 +#define DMA_BOUNCE_BUFFER_COUNT 3
1703 +
1704 +
1705 +struct smi_settings {
1706 +       int data_width;
1707 +       /* Whether or not to pack multiple SMI transfers into a
1708 +          single 32 bit FIFO word */
1709 +       bool pack_data;
1710 +
1711 +       /* Timing for reads (writes the same but for WE)
1712 +        *
1713 +        * OE ----------+          +--------------------
1714 +        *              |          |
1715 +        *              +----------+
1716 +        * SD -<==============================>-----------
1717 +        * SA -<=========================================>-
1718 +        *    <-setup->  <-strobe ->  <-hold ->  <- pace ->
1719 +        */
1720 +
1721 +       int read_setup_time;
1722 +       int read_hold_time;
1723 +       int read_pace_time;
1724 +       int read_strobe_time;
1725 +
1726 +       int write_setup_time;
1727 +       int write_hold_time;
1728 +       int write_pace_time;
1729 +       int write_strobe_time;
1730 +
1731 +       bool dma_enable;                /* DREQs */
1732 +       bool dma_passthrough_enable;    /* External DREQs */
1733 +       int dma_read_thresh;
1734 +       int dma_write_thresh;
1735 +       int dma_panic_read_thresh;
1736 +       int dma_panic_write_thresh;
1737 +};
1738 +
1739 +/****************************************************************************
1740 +*
1741 +*   Declare exported SMI functions
1742 +*
1743 +***************************************************************************/
1744 +
1745 +#ifdef __KERNEL__
1746 +
1747 +#include <linux/dmaengine.h> /* for enum dma_transfer_direction */
1748 +#include <linux/of.h>
1749 +#include <linux/semaphore.h>
1750 +
1751 +struct bcm2835_smi_instance;
1752 +
1753 +struct bcm2835_smi_bounce_info {
1754 +       struct semaphore callback_sem;
1755 +       void *buffer[DMA_BOUNCE_BUFFER_COUNT];
1756 +       dma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT];
1757 +       struct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT];
1758 +};
1759 +
1760 +
1761 +void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *);
1762 +
1763 +struct smi_settings *bcm2835_smi_get_settings_from_regs(
1764 +       struct bcm2835_smi_instance *inst);
1765 +
1766 +void bcm2835_smi_write_buf(
1767 +       struct bcm2835_smi_instance *inst,
1768 +       const void *buf,
1769 +       size_t n_bytes);
1770 +
1771 +void bcm2835_smi_read_buf(
1772 +       struct bcm2835_smi_instance *inst,
1773 +       void *buf,
1774 +       size_t n_bytes);
1775 +
1776 +void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
1777 +       unsigned int address);
1778 +
1779 +ssize_t bcm2835_smi_user_dma(
1780 +       struct bcm2835_smi_instance *inst,
1781 +       enum dma_transfer_direction dma_dir,
1782 +       char __user *user_ptr,
1783 +       size_t count,
1784 +       struct bcm2835_smi_bounce_info **bounce);
1785 +
1786 +struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node);
1787 +
1788 +#endif /* __KERNEL__ */
1789 +
1790 +/****************************************************************
1791 +*
1792 +*      Implementation-only declarations
1793 +*
1794 +****************************************************************/
1795 +
1796 +#ifdef BCM2835_SMI_IMPLEMENTATION
1797 +
1798 +/* Clock manager registers for SMI clock: */
1799 +#define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0)
1800 +/* Clock manager "password" to protect registers from spurious writes */
1801 +#define CM_PWD (0x5a << 24)
1802 +
1803 +#define CM_SMI_CTL     0x00
1804 +#define CM_SMI_DIV     0x04
1805 +
1806 +#define CM_SMI_CTL_FLIP (1 << 8)
1807 +#define CM_SMI_CTL_BUSY (1 << 7)
1808 +#define CM_SMI_CTL_KILL (1 << 5)
1809 +#define CM_SMI_CTL_ENAB (1 << 4)
1810 +#define CM_SMI_CTL_SRC_MASK (0xf)
1811 +#define CM_SMI_CTL_SRC_OFFS (0)
1812 +
1813 +#define CM_SMI_DIV_DIVI_MASK (0xf <<  12)
1814 +#define CM_SMI_DIV_DIVI_OFFS (12)
1815 +#define CM_SMI_DIV_DIVF_MASK (0xff << 4)
1816 +#define CM_SMI_DIV_DIVF_OFFS (4)
1817 +
1818 +/* SMI register mapping:*/
1819 +#define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000)
1820 +
1821 +#define SMICS  0x00    /* control + status register            */
1822 +#define SMIL   0x04    /* length/count (n external txfers)     */
1823 +#define SMIA   0x08    /* address register                     */
1824 +#define SMID   0x0c    /* data register                        */
1825 +#define SMIDSR0        0x10    /* device 0 read settings               */
1826 +#define SMIDSW0        0x14    /* device 0 write settings              */
1827 +#define SMIDSR1        0x18    /* device 1 read settings               */
1828 +#define SMIDSW1        0x1c    /* device 1 write settings              */
1829 +#define SMIDSR2        0x20    /* device 2 read settings               */
1830 +#define SMIDSW2        0x24    /* device 2 write settings              */
1831 +#define SMIDSR3        0x28    /* device 3 read settings               */
1832 +#define SMIDSW3        0x2c    /* device 3 write settings              */
1833 +#define SMIDC  0x30    /* DMA control registers                */
1834 +#define SMIDCS 0x34    /* direct control/status register       */
1835 +#define SMIDA  0x38    /* direct address register              */
1836 +#define SMIDD  0x3c    /* direct data registers                */
1837 +#define SMIFD  0x40    /* FIFO debug register                  */
1838 +
1839 +
1840 +
1841 +/* Control and Status register bits:
1842 + * SMICS_RXF   : RX fifo full: 1 when RX fifo is full
1843 + * SMICS_TXE   : TX fifo empty: 1 when empty.
1844 + * SMICS_RXD   : RX fifo contains data: 1 when there is data.
1845 + * SMICS_TXD   : TX fifo can accept data: 1 when true.
1846 + * SMICS_RXR   : RX fifo needs reading: 1 when fifo more than 3/4 full, or
1847 + *               when "DONE" and fifo not emptied.
1848 + * SMICS_TXW   : TX fifo needs writing: 1 when less than 1/4 full.
1849 + * SMICS_AFERR : AXI FIFO error: 1 when fifo read when empty or written
1850 + *               when full. Write 1 to clear.
1851 + * SMICS_EDREQ : 1 when external DREQ received.
1852 + * SMICS_PXLDAT        :  Pixel data:  write 1 to enable pixel transfer modes.
1853 + * SMICS_SETERR        : 1 if there was an error writing to setup regs (e.g.
1854 + *               tx was in progress). Write 1 to clear.
1855 + * SMICS_PVMODE        : Set to 1 to enable pixel valve mode.
1856 + * SMICS_INTR  : Set to 1 to enable interrupt on RX.
1857 + * SMICS_INTT  : Set to 1 to enable interrupt on TX.
1858 + * SMICS_INTD  : Set to 1 to enable interrupt on DONE condition.
1859 + * SMICS_TEEN  : Tear effect mode enabled: Programmed transfers will wait
1860 + *               for a TE trigger before writing.
1861 + * SMICS_PAD1  : Padding settings for external transfers. For writes: the
1862 + *               number of bytes initially written to  the TX fifo that
1863 + * SMICS_PAD0  : should be ignored. For reads: the number of bytes that will
1864 + *               be read before the data, and should be dropped.
1865 + * SMICS_WRITE : Transfer direction: 1 = write to external device, 0 = read
1866 + * SMICS_CLEAR : Write 1 to clear the FIFOs.
1867 + * SMICS_START : Write 1 to start the programmed transfer.
1868 + * SMICS_ACTIVE        : Reads as 1 when a programmed transfer is underway.
1869 + * SMICS_DONE  : Reads as 1 when transfer finished. For RX, not set until
1870 + *               FIFO emptied.
1871 + * SMICS_ENABLE        : Set to 1 to enable the SMI peripheral, 0 to disable.
1872 + */
1873 +
1874 +#define SMICS_RXF      (1 << 31)
1875 +#define SMICS_TXE      (1 << 30)
1876 +#define SMICS_RXD      (1 << 29)
1877 +#define SMICS_TXD      (1 << 28)
1878 +#define SMICS_RXR      (1 << 27)
1879 +#define SMICS_TXW      (1 << 26)
1880 +#define SMICS_AFERR    (1 << 25)
1881 +#define SMICS_EDREQ    (1 << 15)
1882 +#define SMICS_PXLDAT   (1 << 14)
1883 +#define SMICS_SETERR   (1 << 13)
1884 +#define SMICS_PVMODE   (1 << 12)
1885 +#define SMICS_INTR     (1 << 11)
1886 +#define SMICS_INTT     (1 << 10)
1887 +#define SMICS_INTD     (1 << 9)
1888 +#define SMICS_TEEN     (1 << 8)
1889 +#define SMICS_PAD1     (1 << 7)
1890 +#define SMICS_PAD0     (1 << 6)
1891 +#define SMICS_WRITE    (1 << 5)
1892 +#define SMICS_CLEAR    (1 << 4)
1893 +#define SMICS_START    (1 << 3)
1894 +#define SMICS_ACTIVE   (1 << 2)
1895 +#define SMICS_DONE     (1 << 1)
1896 +#define SMICS_ENABLE   (1 << 0)
1897 +
1898 +/* Address register bits: */
1899 +
1900 +#define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8))
1901 +#define SMIA_DEVICE_OFFS (8)
1902 +#define SMIA_ADDR_MASK (0x3f)  /* bits 5 -> 0 */
1903 +#define SMIA_ADDR_OFFS (0)
1904 +
1905 +/* DMA control register bits:
1906 + * SMIDC_DMAEN : DMA enable: set 1: DMA requests will be issued.
1907 + * SMIDC_DMAP  : DMA passthrough: when set to 0, top two data pins are used by
1908 + *               SMI as usual. When set to 1, the top two pins are used for
1909 + *               external DREQs: pin 16 read request, 17 write.
1910 + * SMIDC_PANIC*        : Threshold at which DMA will panic during read/write.
1911 + * SMIDC_REQ*  : Threshold at which DMA will generate a DREQ.
1912 + */
1913 +
1914 +#define SMIDC_DMAEN            (1 << 28)
1915 +#define SMIDC_DMAP             (1 << 24)
1916 +#define SMIDC_PANICR_MASK      (0x3f << 18)
1917 +#define SMIDC_PANICR_OFFS      (18)
1918 +#define SMIDC_PANICW_MASK      (0x3f << 12)
1919 +#define SMIDC_PANICW_OFFS      (12)
1920 +#define SMIDC_REQR_MASK                (0x3f << 6)
1921 +#define SMIDC_REQR_OFFS                (6)
1922 +#define SMIDC_REQW_MASK                (0x3f)
1923 +#define SMIDC_REQW_OFFS                (0)
1924 +
1925 +/* Device settings register bits: same for all 4 (or 3?) device register sets.
1926 + * Device read settings:
1927 + * SMIDSR_RWIDTH       : Read transfer width. 00 = 8bit, 01 = 16bit,
1928 + *                       10 = 18bit, 11 = 9bit.
1929 + * SMIDSR_RSETUP       : Read setup time: number of core cycles between chip
1930 + *                       select/address and read strobe. Min 1, max 64.
1931 + * SMIDSR_MODE68       : 1 for System 68 mode (i.e. enable + direction pins,
1932 + *                       rather than OE + WE pin)
1933 + * SMIDSR_FSETUP       : If set to 1, setup time only applies to first
1934 + *                       transfer after address change.
1935 + * SMIDSR_RHOLD                : Number of core cycles between read strobe going
1936 + *                       inactive and CS/address going inactive. Min 1, max 64
1937 + * SMIDSR_RPACEALL     : When set to 1, this device's RPACE value will always
1938 + *                       be used for the next transaction, even if it is not
1939 + *                       to this device.
1940 + * SMIDSR_RPACE                : Number of core cycles spent waiting between CS
1941 + *                       deassert and start of next transfer. Min 1, max 128
1942 + * SMIDSR_RDREQ                : 1 = use external DMA request on SD16 to pace reads
1943 + *                       from device. Must also set DMAP in SMICS.
1944 + * SMIDSR_RSTROBE      : Number of cycles to assert the read strobe.
1945 + *                       min 1, max 128.
1946 + */
1947 +#define SMIDSR_RWIDTH_MASK     ((1<<31)|(1<<30))
1948 +#define SMIDSR_RWIDTH_OFFS     (30)
1949 +#define SMIDSR_RSETUP_MASK     (0x3f << 24)
1950 +#define SMIDSR_RSETUP_OFFS     (24)
1951 +#define SMIDSR_MODE68          (1 << 23)
1952 +#define SMIDSR_FSETUP          (1 << 22)
1953 +#define SMIDSR_RHOLD_MASK      (0x3f << 16)
1954 +#define SMIDSR_RHOLD_OFFS      (16)
1955 +#define SMIDSR_RPACEALL                (1 << 15)
1956 +#define SMIDSR_RPACE_MASK      (0x7f << 8)
1957 +#define SMIDSR_RPACE_OFFS      (8)
1958 +#define SMIDSR_RDREQ           (1 << 7)
1959 +#define SMIDSR_RSTROBE_MASK    (0x7f)
1960 +#define SMIDSR_RSTROBE_OFFS    (0)
1961 +
1962 +/* Device write settings:
1963 + * SMIDSW_WWIDTH       : Write transfer width. 00 = 8bit, 01 = 16bit,
1964 + *                       10= 18bit, 11 = 9bit.
1965 + * SMIDSW_WSETUP       : Number of cycles between CS assert and write strobe.
1966 + *                       Min 1, max 64.
1967 + * SMIDSW_WFORMAT      : Pixel format of input. 0 = 16bit RGB 565,
1968 + *                       1 = 32bit RGBA 8888
1969 + * SMIDSW_WSWAP                : 1 = swap pixel data bits. (Use with SMICS_PXLDAT)
1970 + * SMIDSW_WHOLD                : Time between WE deassert and CS deassert. 1 to 64
1971 + * SMIDSW_WPACEALL     : 1: this device's WPACE will be used for the next
1972 + *                       transfer, regardless of that transfer's device.
1973 + * SMIDSW_WPACE                : Cycles between CS deassert and next CS assert.
1974 + *                       Min 1, max 128
1975 + * SMIDSW_WDREQ                : Use external DREQ on pin 17 to pace writes. DMAP must
1976 + *                       be set in SMICS.
1977 + * SMIDSW_WSTROBE      : Number of cycles to assert the write strobe.
1978 + *                       Min 1, max 128
1979 + */
1980 +#define SMIDSW_WWIDTH_MASK      ((1<<31)|(1<<30))
1981 +#define SMIDSW_WWIDTH_OFFS     (30)
1982 +#define SMIDSW_WSETUP_MASK     (0x3f << 24)
1983 +#define SMIDSW_WSETUP_OFFS     (24)
1984 +#define SMIDSW_WFORMAT         (1 << 23)
1985 +#define SMIDSW_WSWAP           (1 << 22)
1986 +#define SMIDSW_WHOLD_MASK      (0x3f << 16)
1987 +#define SMIDSW_WHOLD_OFFS      (16)
1988 +#define SMIDSW_WPACEALL                (1 << 15)
1989 +#define SMIDSW_WPACE_MASK      (0x7f << 8)
1990 +#define SMIDSW_WPACE_OFFS      (8)
1991 +#define SMIDSW_WDREQ           (1 << 7)
1992 +#define SMIDSW_WSTROBE_MASK     (0x7f)
1993 +#define SMIDSW_WSTROBE_OFFS     (0)
1994 +
1995 +/* Direct transfer control + status register
1996 + * SMIDCS_WRITE        : Direction of transfer: 1 -> write, 0 -> read
1997 + * SMIDCS_DONE : 1 when a transfer has finished. Write 1 to clear.
1998 + * SMIDCS_START        : Write 1 to start a transfer, if one is not already underway.
1999 + * SMIDCE_ENABLE: Write 1 to enable SMI in direct mode.
2000 + */
2001 +
2002 +#define SMIDCS_WRITE           (1 << 3)
2003 +#define SMIDCS_DONE            (1 << 2)
2004 +#define SMIDCS_START           (1 << 1)
2005 +#define SMIDCS_ENABLE          (1 << 0)
2006 +
2007 +/* Direct transfer address register
2008 + * SMIDA_DEVICE        : Indicates which of the device settings banks should be used.
2009 + * SMIDA_ADDR  : The value to be asserted on the address pins.
2010 + */
2011 +
2012 +#define SMIDA_DEVICE_MASK      ((1<<9)|(1<<8))
2013 +#define SMIDA_DEVICE_OFFS      (8)
2014 +#define SMIDA_ADDR_MASK                (0x3f)
2015 +#define SMIDA_ADDR_OFFS                (0)
2016 +
2017 +/* FIFO debug register
2018 + * SMIFD_FLVL  : The high-tide mark of FIFO count during the most recent txfer
2019 + * SMIFD_FCNT  : The current FIFO count.
2020 + */
2021 +#define SMIFD_FLVL_MASK                (0x3f << 8)
2022 +#define SMIFD_FLVL_OFFS                (8)
2023 +#define SMIFD_FCNT_MASK                (0x3f)
2024 +#define SMIFD_FCNT_OFFS                (0)
2025 +
2026 +#endif /* BCM2835_SMI_IMPLEMENTATION */
2027 +
2028 +#endif /* BCM2835_SMI_H */