target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
   7  * Copyright (C) 2006 FON Technology, SL.
   8  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
   9  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  10  */
  11
  12 /*
  13  * Platform devices for Atheros SoCs
  14  */
  15
  16 #include <linux/autoconf.h>
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/types.h>
  20 #include <linux/string.h>
  21 #include <linux/mtd/physmap.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/kernel.h>
  24 #include <linux/reboot.h>
  25 #include <asm/bootinfo.h>
  26 #include <asm/reboot.h>
  27 #include <asm/time.h>
  28 #include <asm/irq.h>
  29 #include <asm/io.h>
  30 #include "ar531x.h"
  31
  32
  33 #define AR531X_IRQ_WLAN0_INTRS  MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
  34 #define AR531X_IRQ_ENET0_INTRS  MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
  35 #define AR531X_IRQ_ENET1_INTRS  MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
  36 #define AR531X_IRQ_WLAN1_INTRS  MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
  37 #define AR531X_IRQ_MISC_INTRS   MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
  38
  39
  40 static struct platform_device *ar5312_devs[5];
  41
  42 static struct resource ar5312_eth0_res[] = {
  43         {
  44                 .name = "eth_membase",
  45                 .flags = IORESOURCE_MEM,
  46                 .start = KSEG1ADDR(AR531X_ENET0),
  47                 .end = KSEG1ADDR(AR531X_ENET0 + 0x2000),
  48         },
  49         {
  50                 .name = "eth_irq",
  51                 .flags = IORESOURCE_IRQ,
  52                 .start = AR531X_IRQ_ENET0_INTRS,
  53                 .end = AR531X_IRQ_ENET0_INTRS,
  54         },
  55 };
  56
  57
  58 static struct resource ar5312_eth1_res[] = {
  59         {
  60                 .name = "eth_membase",
  61                 .flags = IORESOURCE_MEM,
  62                 .start = KSEG1ADDR(AR531X_ENET1),
  63                 .end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
  64         },
  65         {
  66                 .name = "eth_irq",
  67                 .flags = IORESOURCE_IRQ,
  68                 .start = AR531X_IRQ_ENET1_INTRS,
  69                 .end = AR531X_IRQ_ENET1_INTRS,
  70         },
  71 };
  72
  73
  74 static struct ar531x_eth ar5312_eth0_data = {
  75         .phy = 0x1f,
  76         .mac = 0,
  77         .reset_base = AR531X_RESET,
  78         .reset_mac = AR531X_RESET_ENET0,
  79         .reset_phy = AR531X_RESET_EPHY0,
  80 };
  81
  82 static struct ar531x_eth ar5312_eth1_data = {
  83         .phy = 0,
  84         .mac = 1,
  85         .reset_base = AR531X_RESET,
  86         .reset_mac = AR531X_RESET_ENET1,
  87         .reset_phy = AR531X_RESET_EPHY1,
  88 };
  89
  90 static struct platform_device ar5312_eth[] = {
  91         {
  92                 .id = 0,
  93                 .name = "ar531x-eth",
  94                 .dev.platform_data = &ar5312_eth0_data,
  95                 .resource = ar5312_eth0_res,
  96                 .num_resources = ARRAY_SIZE(ar5312_eth0_res)
  97         },
  98         {
  99                 .id = 1,
 100                 .name = "ar531x-eth",
 101                 .dev.platform_data = &ar5312_eth1_data,
 102                 .resource = ar5312_eth1_res,
 103                 .num_resources = ARRAY_SIZE(ar5312_eth1_res)
 104         },
 105 };
 106
 107 static struct platform_device ar5312_wmac[] = {
 108         {
 109                 .id = 0,
 110                 .name = "ar531x-wmac",
 111         },
 112         {
 113                 .id = 1,
 114                 .name = "ar531x-wmac",
 115         },
 116 };
 117
 118
 119 static struct physmap_flash_data ar5312_flash_data = {
 120         .width    = 2,
 121 };
 122
 123 static struct resource ar5312_flash_resource = {
 124         .start  = AR531X_FLASH,
 125         .end    = AR531X_FLASH + 0x400000 - 1,
 126         .flags  = IORESOURCE_MEM,
 127 };
 128
 129 static struct platform_device ar5312_physmap_flash = {
 130         .name      = "physmap-flash",
 131         .id      = 0,
 132         .dev            = {
 133                 .platform_data  = &ar5312_flash_data,
 134         },
 135         .num_resources  = 1,
 136         .resource   = &ar5312_flash_resource,
 137 };
 138
 139
 140 /*
 141  * NB: This mapping size is larger than the actual flash size,
 142  * but this shouldn't be a problem here, because the flash
 143  * will simply be mapped multiple times.
 144  */
 145 static char __init *ar5312_flash_limit(void)
 146 {
 147         u32 ctl;
 148         /* Configure flash bank 0 */
 149         ctl = FLASHCTL_E |
 150                 FLASHCTL_AC_8M |
 151                 FLASHCTL_RBLE |
 152                 (0x01 << FLASHCTL_IDCY_S) |
 153                 (0x07 << FLASHCTL_WST1_S) |
 154                 (0x07 << FLASHCTL_WST2_S) |
 155                 (sysRegRead(AR531X_FLASHCTL0) & FLASHCTL_MW);
 156
 157         sysRegWrite(AR531X_FLASHCTL0, ctl);
 158
 159         /* Disable other flash banks */
 160         sysRegWrite(AR531X_FLASHCTL1,
 161                 sysRegRead(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
 162
 163         sysRegWrite(AR531X_FLASHCTL2,
 164                 sysRegRead(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
 165
 166         return (char *) KSEG1ADDR(AR531X_FLASH + 0x400000);
 167 }
 168
 169 static struct ar531x_config __init *init_wmac(int unit)
 170 {
 171         struct ar531x_config *config;
 172
 173         config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
 174         config->board = board_config;
 175         config->radio = radio_config;
 176         config->unit = unit;
 177         config->tag = (u_int16_t) ((sysRegRead(AR531X_REV) >> AR531X_REV_WMAC_MIN_S) & AR531X_REV_CHIP);
 178
 179         return config;
 180 }
 181
 182 int __init ar5312_init_devices(void)
 183 {
 184         char *radio;
 185         int dev = 0;
 186
 187         if (mips_machtype != MACH_ATHEROS_AR5312)
 188                 return 0;
 189
 190         ar531x_find_config(ar5312_flash_limit());
 191         ar5312_eth0_data.board_config = board_config;
 192         ar5312_eth1_data.board_config = board_config;
 193         ar5312_devs[dev++] = &ar5312_physmap_flash;
 194         ar5312_devs[dev++] = &ar5312_eth[0];
 195         ar5312_devs[dev++] = &ar5312_eth[1];
 196
 197         radio = radio_config + AR531X_RADIO_MASK_OFF;
 198         if (*((u32 *) radio) & AR531X_RADIO0_MASK) {
 199                 ar5312_wmac[0].dev.platform_data = init_wmac(0);
 200                 ar5312_devs[dev++] = &ar5312_wmac[0];
 201         }
 202         if (*((u32 *) radio) & AR531X_RADIO1_MASK) {
 203                 ar5312_wmac[1].dev.platform_data = init_wmac(1);
 204                 ar5312_devs[dev++] = &ar5312_wmac[1];
 205         }
 206
 207         return platform_add_devices(ar5312_devs, dev);
 208 }
 209
 210
 211 /*
 212  * Called when an interrupt is received, this function
 213  * determines exactly which interrupt it was, and it
 214  * invokes the appropriate handler.
 215  *
 216  * Implicitly, we also define interrupt priority by
 217  * choosing which to dispatch first.
 218  */
 219 asmlinkage void ar5312_irq_dispatch(void)
 220 {
 221         int pending = read_c0_status() & read_c0_cause();
 222
 223         if (pending & CAUSEF_IP2)
 224                 do_IRQ(AR531X_IRQ_WLAN0_INTRS);
 225         else if (pending & CAUSEF_IP3)
 226                 do_IRQ(AR531X_IRQ_ENET0_INTRS);
 227         else if (pending & CAUSEF_IP4)
 228                 do_IRQ(AR531X_IRQ_ENET1_INTRS);
 229         else if (pending & CAUSEF_IP5)
 230                 do_IRQ(AR531X_IRQ_WLAN1_INTRS);
 231         else if (pending & CAUSEF_IP6) {
 232                 unsigned int ar531x_misc_intrs = sysRegRead(AR531X_ISR) & sysRegRead(AR531X_IMR);
 233
 234                 if (ar531x_misc_intrs & AR531X_ISR_TIMER) {
 235                         do_IRQ(AR531X_MISC_IRQ_TIMER);
 236                         (void)sysRegRead(AR531X_TIMER);
 237                 } else if (ar531x_misc_intrs & AR531X_ISR_AHBPROC)
 238                         do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
 239                 else if ((ar531x_misc_intrs & AR531X_ISR_UART0))
 240                         do_IRQ(AR531X_MISC_IRQ_UART0);
 241                 else if (ar531x_misc_intrs & AR531X_ISR_WD)
 242                         do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
 243                 else
 244                         do_IRQ(AR531X_MISC_IRQ_NONE);
 245         } else if (pending & CAUSEF_IP7) {
 246                 do_IRQ(AR531X_IRQ_CPU_CLOCK);
 247         }
 248         else
 249                 do_IRQ(AR531X_IRQ_NONE);
 250 }
 251
 252 static void ar5312_halt(void)
 253 {
 254          while (1);
 255 }
 256
 257 static void ar5312_power_off(void)
 258 {
 259          ar5312_halt();
 260 }
 261
 262
 263 static void ar5312_restart(char *command)
 264 {
 265         /* reset the system */
 266         for(;;) sysRegWrite(AR531X_RESET, AR531X_RESET_SYSTEM);
 267 }
 268
 269
 270 /*
 271  * This table is indexed by bits 5..4 of the CLOCKCTL1 register
 272  * to determine the predevisor value.
 273  */
 274 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
 275         1,
 276         2,
 277         4,
 278         5
 279 };
 280
 281
 282 static unsigned int __init ar5312_cpu_frequency(void)
 283 {
 284         unsigned int result;
 285         unsigned int predivide_mask, predivide_shift;
 286         unsigned int multiplier_mask, multiplier_shift;
 287         unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
 288         unsigned int doubler_mask;
 289         unsigned int wisoc_revision;
 290
 291         /* Trust the bootrom's idea of cpu frequency. */
 292         if ((result = sysRegRead(AR5312_SCRATCH)))
 293                 return result;
 294
 295         wisoc_revision = (sysRegRead(AR531X_REV) & AR531X_REV_MAJ) >> AR531X_REV_MAJ_S;
 296         if (wisoc_revision == AR531X_REV_MAJ_AR2313) {
 297                 predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
 298                 predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
 299                 multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
 300                 multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
 301                 doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
 302         } else { /* AR5312 and AR2312 */
 303                 predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
 304                 predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
 305                 multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
 306                 multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
 307                 doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
 308         }
 309
 310         /*
 311          * Clocking is derived from a fixed 40MHz input clock.
 312          *
 313          *  cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
 314          *  sysFreq = cpuFreq / 4          (used for APB clock, serial,
 315          *                                                         flash, Timer, Watchdog Timer)
 316          *
 317          *  cntFreq = cpuFreq / 2          (use for CPU count/compare)
 318          *
 319          * So, for example, with a PLL multiplier of 5, we have
 320          *
 321          *  cpuFreq = 200MHz
 322          *  sysFreq = 50MHz
 323          *  cntFreq = 100MHz
 324          *
 325          * We compute the CPU frequency, based on PLL settings.
 326          */
 327
 328         clockCtl1 = sysRegRead(AR5312_CLOCKCTL1);
 329         preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
 330         preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
 331         multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
 332
 333         if (clockCtl1 & doubler_mask) {
 334                 multiplier = multiplier << 1;
 335         }
 336         return (40000000 / preDivisor) * multiplier;
 337 }
 338
 339 static inline int ar5312_sys_frequency(void)
 340 {
 341         return ar5312_cpu_frequency() / 4;
 342 }
 343
 344 static void __init ar5312_time_init(void)
 345 {
 346         mips_hpt_frequency = ar5312_cpu_frequency() / 2;
 347 }
 348
 349
 350 /* Enable the specified AR531X_MISC_IRQ interrupt */
 351 static void
 352 ar5312_misc_intr_enable(unsigned int irq)
 353 {
 354         unsigned int imr;
 355
 356         imr = sysRegRead(AR531X_IMR);
 357         imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
 358         sysRegWrite(AR531X_IMR, imr);
 359         sysRegRead(AR531X_IMR); /* flush write buffer */
 360 }
 361
 362 /* Disable the specified AR531X_MISC_IRQ interrupt */
 363 static void
 364 ar5312_misc_intr_disable(unsigned int irq)
 365 {
 366         unsigned int imr;
 367
 368         imr = sysRegRead(AR531X_IMR);
 369         imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
 370         sysRegWrite(AR531X_IMR, imr);
 371         sysRegRead(AR531X_IMR); /* flush write buffer */
 372 }
 373
 374 /* Turn on the specified AR531X_MISC_IRQ interrupt */
 375 static unsigned int
 376 ar5312_misc_intr_startup(unsigned int irq)
 377 {
 378         ar5312_misc_intr_enable(irq);
 379         return 0;
 380 }
 381
 382 /* Turn off the specified AR531X_MISC_IRQ interrupt */
 383 static void
 384 ar5312_misc_intr_shutdown(unsigned int irq)
 385 {
 386         ar5312_misc_intr_disable(irq);
 387 }
 388
 389 static void
 390 ar5312_misc_intr_ack(unsigned int irq)
 391 {
 392         ar5312_misc_intr_disable(irq);
 393 }
 394
 395 static void
 396 ar5312_misc_intr_end(unsigned int irq)
 397 {
 398         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 399                 ar5312_misc_intr_enable(irq);
 400 }
 401
 402 static struct irq_chip ar5312_misc_intr_controller = {
 403         .typename       = "AR5312 misc",
 404         .startup        = ar5312_misc_intr_startup,
 405         .shutdown       = ar5312_misc_intr_shutdown,
 406         .enable         = ar5312_misc_intr_enable,
 407         .disable        = ar5312_misc_intr_disable,
 408         .ack            = ar5312_misc_intr_ack,
 409         .end            = ar5312_misc_intr_end,
 410 };
 411
 412 static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
 413 {
 414         u32 proc1 = sysRegRead(AR531X_PROC1);
 415         u32 procAddr = sysRegRead(AR531X_PROCADDR); /* clears error state */
 416         u32 dma1 = sysRegRead(AR531X_DMA1);
 417         u32 dmaAddr = sysRegRead(AR531X_DMAADDR);   /* clears error state */
 418
 419         printk("AHB interrupt: PROCADDR=0x%8.8x  PROC1=0x%8.8x  DMAADDR=0x%8.8x  DMA1=0x%8.8x\n",
 420                         procAddr, proc1, dmaAddr, dma1);
 421
 422         machine_restart("AHB error"); /* Catastrophic failure */
 423         return IRQ_HANDLED;
 424 }
 425
 426
 427 static struct irqaction ar5312_ahb_proc_interrupt  = {
 428         .handler        = ar5312_ahb_proc_handler,
 429         .flags          = SA_INTERRUPT,
 430         .name           = "ar5312_ahb_proc_interrupt",
 431 };
 432
 433
 434 static struct irqaction cascade  = {
 435         .handler        = no_action,
 436         .flags          = SA_INTERRUPT,
 437         .name           = "cascade",
 438 };
 439
 440 void __init ar5312_misc_intr_init(int irq_base)
 441 {
 442         int i;
 443
 444         for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
 445                 irq_desc[i].status = IRQ_DISABLED;
 446                 irq_desc[i].action = NULL;
 447                 irq_desc[i].depth = 1;
 448                 irq_desc[i].chip = &ar5312_misc_intr_controller;
 449         }
 450         setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
 451         setup_irq(AR531X_IRQ_MISC_INTRS, &cascade);
 452 }
 453
 454
 455 void __init ar5312_plat_setup(void)
 456 {
 457         /* Clear any lingering AHB errors */
 458         sysRegRead(AR531X_PROCADDR);
 459         sysRegRead(AR531X_DMAADDR);
 460         sysRegWrite(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
 461
 462         board_time_init = ar5312_time_init;
 463
 464         _machine_restart = ar5312_restart;
 465         _machine_halt = ar5312_halt;
 466         pm_power_off = ar5312_power_off;
 467
 468         serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
 469 }
 470
 471 arch_initcall(ar5312_init_devices);