target/linux/aruba-2.6/patches/000-aruba.patch

   1 diff -Nur linux-2.6.17/arch/mips/aruba/Makefile linux-2.6.17-owrt/arch/mips/aruba/Makefile
   2 --- linux-2.6.17/arch/mips/aruba/Makefile       1970-01-01 01:00:00.000000000 +0100
   3 +++ linux-2.6.17-owrt/arch/mips/aruba/Makefile  2006-06-18 12:44:28.000000000 +0200
   4 @@ -0,0 +1,49 @@
   5 +###############################################################################
   6 +#
   7 +#  BRIEF MODULE DESCRIPTION
   8 +#     Makefile for IDT EB434 BSP
   9 +#
  10 +#  Copyright 2004 IDT Inc. (rischelp@idt.com)
  11 +#
  12 +#  This program is free software; you can redistribute  it and/or modify it
  13 +#  under  the terms of  the GNU General  Public License as published by the
  14 +#  Free Software Foundation;  either version 2 of the  License, or (at your
  15 +#  option) any later version.
  16 +#
  17 +#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  18 +#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  19 +#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  20 +#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  21 +#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22 +#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  23 +#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24 +#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  25 +#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26 +#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 +#
  28 +#   You should have received a copy of the  GNU General Public License along
  29 +#   with this program; if not, write  to the Free Software Foundation, Inc.,
  30 +#   675 Mass Ave, Cambridge, MA 02139, USA.
  31 +#
  32 +#
  33 +###############################################################################
  34 +#  May 2004 rkt, neb
  35 +#
  36 +#  Initial Release
  37 +#
  38 +#
  39 +#
  40 +###############################################################################
  41 +
  42 +
  43 +# .S.s:
  44 +#      $(CPP) $(CFLAGS) $< -o $*.s
  45 +# .S.o:
  46 +#      $(CC) $(CFLAGS) -c $< -o $*.o
  47 +
  48 +obj-y   := prom.o setup.o irq.o time.o flash_lock.o
  49 +obj-$(CONFIG_SERIAL_8250)              += serial.o
  50 +
  51 +subdir-y         += nvram
  52 +obj-y            += nvram/built-in.o
  53 +
  54 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/Makefile linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile
  55 --- linux-2.6.17/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
  56 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile    2006-06-18 12:44:28.000000000 +0200
  57 @@ -0,0 +1,46 @@
  58 +###############################################################################
  59 +#
  60 +#  BRIEF MODULE DESCRIPTION
  61 +#     Makefile for IDT EB434 nvram access routines
  62 +#
  63 +#  Copyright 2004 IDT Inc. (rischelp@idt.com)
  64 +#
  65 +#  This program is free software; you can redistribute  it and/or modify it
  66 +#  under  the terms of  the GNU General  Public License as published by the
  67 +#  Free Software Foundation;  either version 2 of the  License, or (at your
  68 +#  option) any later version.
  69 +#
  70 +#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  71 +#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  72 +#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  73 +#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  74 +#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  75 +#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  76 +#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  77 +#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  78 +#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  79 +#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  80 +#
  81 +#   You should have received a copy of the  GNU General Public License along
  82 +#   with this program; if not, write  to the Free Software Foundation, Inc.,
  83 +#   675 Mass Ave, Cambridge, MA 02139, USA.
  84 +#
  85 +#
  86 +###############################################################################
  87 +#  May 2004  rkt, neb
  88 +#
  89 +#  Initial Release
  90 +#
  91 +#
  92 +#
  93 +###############################################################################
  94 +
  95 +obj-y   := nvram434.o
  96 +obj-m   := $(O_TARGET)
  97 +
  98 +
  99 +
 100 +
 101 +
 102 +
 103 +
 104 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.c linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c
 105 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.c       1970-01-01 01:00:00.000000000 +0100
 106 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c  2006-06-18 12:44:28.000000000 +0200
 107 @@ -0,0 +1,392 @@
 108 +/**************************************************************************
 109 + *
 110 + *  BRIEF MODULE DESCRIPTION
 111 + *     nvram interface routines.
 112 + *
 113 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 114 + *
 115 + *  This program is free software; you can redistribute  it and/or modify it
 116 + *  under  the terms of  the GNU General  Public License as published by the
 117 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 118 + *  option) any later version.
 119 + *
 120 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 121 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 122 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 123 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 124 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 125 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 126 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 127 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 128 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 129 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 130 + *
 131 + *  You should have received a copy of the  GNU General Public License along
 132 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 133 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 134 + *
 135 + *
 136 + **************************************************************************
 137 + * May 2004 rkt, neb
 138 + *
 139 + * Initial Release
 140 + *
 141 + *
 142 + *
 143 + **************************************************************************
 144 + */
 145 +
 146 +#include <linux/ctype.h>
 147 +#include <linux/string.h>
 148 +
 149 +//#include <asm/ds1553rtc.h>
 150 +#include "nvram434.h"
 151 +#define  NVRAM_BASE 0xbfff8000
 152 +
 153 +extern void setenv (char *e, char *v, int rewrite);
 154 +extern void unsetenv (char *e);
 155 +extern void mapenv (int (*func)(char *, char *));
 156 +extern char *getenv (char *s);
 157 +extern void purgeenv(void);
 158 +
 159 +static void nvram_initenv(void);
 160 +
 161 +static unsigned char
 162 +nvram_getbyte(int offs)
 163 +{
 164 +  return(*((unsigned char*)(NVRAM_BASE + offs)));
 165 +}
 166 +
 167 +static void
 168 +nvram_setbyte(int offs, unsigned char val)
 169 +{
 170 +  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
 171 +
 172 +  *nvramDataPointer = val;
 173 +}
 174 +
 175 +/*
 176 + * BigEndian!
 177 + */
 178 +static unsigned short
 179 +nvram_getshort(int offs)
 180 +{
 181 +  return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
 182 +}
 183 +
 184 +static void
 185 +nvram_setshort(int offs, unsigned short val)
 186 +{
 187 +  nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
 188 +  nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
 189 +}
 190 +#if 0
 191 +static unsigned int
 192 +nvram_getint(int offs)
 193 +{
 194 +  unsigned int val;
 195 +  val = nvram_getbyte(offs) << 24;
 196 +  val |= nvram_getbyte(offs + 1) << 16;
 197 +  val |= nvram_getbyte(offs + 2) << 8;
 198 +  val |= nvram_getbyte(offs + 3);
 199 +  return(val);
 200 +}
 201 +
 202 +static void
 203 +nvram_setint(int offs, unsigned int val)
 204 +{
 205 +  nvram_setbyte(offs, val >> 24);
 206 +  nvram_setbyte(offs + 1, val >> 16);
 207 +  nvram_setbyte(offs + 2, val >> 8);
 208 +  nvram_setbyte(offs + 3, val);
 209 +}
 210 +#endif
 211 +/*
 212 + * calculate NVRAM checksum
 213 + */
 214 +static unsigned short
 215 +nvram_calcsum(void)
 216 +{
 217 +  unsigned short sum = NV_MAGIC;
 218 +  int     i;
 219 +
 220 +  for (i = ENV_BASE; i < ENV_TOP; i += 2)
 221 +    sum += nvram_getshort(i);
 222 +  return(sum);
 223 +}
 224 +
 225 +/*
 226 + * update the nvram checksum
 227 + */
 228 +static void
 229 +nvram_updatesum (void)
 230 +{
 231 +  nvram_setshort(NVOFF_CSUM, nvram_calcsum());
 232 +}
 233 +
 234 +/*
 235 + * test validity of nvram by checksumming it
 236 + */
 237 +static int
 238 +nvram_isvalid(void)
 239 +{
 240 +  static int  is_valid;
 241 +
 242 +  if (is_valid)
 243 +    return(1);
 244 +
 245 +  if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
 246 +       printk("nvram_isvalid FAILED\n");
 247 +    //nvram_initenv();
 248 +  }
 249 +  is_valid = 1;
 250 +  return(1);
 251 +}
 252 +
 253 +/* return nvram address of environment string */
 254 +static int
 255 +nvram_matchenv(char *s)
 256 +{
 257 +  int envsize, envp, n, i, varsize;
 258 +  char *var;
 259 +
 260 +  envsize = nvram_getshort(NVOFF_ENVSIZE);
 261 +
 262 +  if (envsize > ENV_AVAIL)
 263 +    return(0);     /* sanity */
 264 +
 265 +  envp = ENV_BASE;
 266 +
 267 +  if ((n = strlen (s)) > 255)
 268 +    return(0);
 269 +
 270 +  while (envsize > 0) {
 271 +    varsize = nvram_getbyte(envp);
 272 +    if (varsize == 0 || (envp + varsize) > ENV_TOP)
 273 +      return(0);   /* sanity */
 274 +    for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
 275 +      char c1 = nvram_getbyte(i);
 276 +      char c2 = *var;
 277 +      if (islower(c1))
 278 +        c1 = toupper(c1);
 279 +      if (islower(c2))
 280 +        c2 = toupper(c2);
 281 +      if (c1 != c2)
 282 +        break;
 283 +    }
 284 +    if (i > envp + n) {       /* match so far */
 285 +      if (n == varsize - 1)   /* match on boolean */
 286 +        return(envp);
 287 +      if (nvram_getbyte(i) == '=')  /* exact match on variable */
 288 +        return(envp);
 289 +    }
 290 +    envsize -= varsize;
 291 +    envp += varsize;
 292 +  }
 293 +  return(0);
 294 +}
 295 +
 296 +static void nvram_initenv(void)
 297 +{
 298 +  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
 299 +  nvram_setshort(NVOFF_ENVSIZE, 0);
 300 +
 301 +  nvram_updatesum();
 302 +}
 303 +
 304 +static void
 305 +nvram_delenv(char *s)
 306 +{
 307 +  int nenvp, envp, envsize, nbytes;
 308 +
 309 +  envp = nvram_matchenv(s);
 310 +  if (envp == 0)
 311 +    return;
 312 +
 313 +  nenvp = envp + nvram_getbyte(envp);
 314 +  envsize = nvram_getshort(NVOFF_ENVSIZE);
 315 +  nbytes = envsize - (nenvp - ENV_BASE);
 316 +  nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
 317 +  while (nbytes--) {
 318 +    nvram_setbyte(envp, nvram_getbyte(nenvp));
 319 +    envp++;
 320 +    nenvp++;
 321 +  }
 322 +  nvram_updatesum();
 323 +}
 324 +
 325 +static int
 326 +nvram_setenv(char *s, char *v)
 327 +{
 328 +  int ns, nv, total;
 329 +  int envp;
 330 +
 331 +  if (!nvram_isvalid())
 332 +    return(-1);
 333 +
 334 +  nvram_delenv(s);
 335 +  ns = strlen(s);
 336 +  if (ns == 0)
 337 +    return (-1);
 338 +  if (v && *v) {
 339 +    nv = strlen(v);
 340 +    total = ns + nv + 2;
 341 +  }
 342 +  else {
 343 +    nv = 0;
 344 +    total = ns + 1;
 345 +  }
 346 +  if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
 347 +    return(-1);
 348 +
 349 +  envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
 350 +
 351 +  nvram_setbyte(envp, (unsigned char) total);
 352 +  envp++;
 353 +
 354 +  while (ns--) {
 355 +    nvram_setbyte(envp, *s);
 356 +    envp++;
 357 +    s++;
 358 +  }
 359 +
 360 +  if (nv) {
 361 +    nvram_setbyte(envp, '=');
 362 +    envp++;
 363 +    while (nv--) {
 364 +      nvram_setbyte(envp, *v);
 365 +      envp++;
 366 +      v++;
 367 +    }
 368 +  }
 369 +  nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
 370 +  nvram_updatesum();
 371 +  return 0;
 372 +}
 373 +
 374 +static char *
 375 +nvram_getenv(char *s)
 376 +{
 377 +  static char buf[256];   /* FIXME: this cannot be static */
 378 +  int envp, ns, nbytes, i;
 379 +
 380 +  if (!nvram_isvalid())
 381 +    return "INVALID NVRAM"; //((char *)0);
 382 +
 383 +  envp = nvram_matchenv(s);
 384 +  if (envp == 0)
 385 +    return "NOT FOUND"; //((char *)0);
 386 +  ns = strlen(s);
 387 +  if (nvram_getbyte(envp) == ns + 1)  /* boolean */
 388 +    buf[0] = '\0';
 389 +  else {
 390 +    nbytes = nvram_getbyte(envp) - (ns + 2);
 391 +    envp += ns + 2;
 392 +    for (i = 0; i < nbytes; i++)
 393 +      buf[i] = nvram_getbyte(envp++);
 394 +    buf[i] = '\0';
 395 +  }
 396 +  return(buf);
 397 +}
 398 +
 399 +static void
 400 +nvram_unsetenv(char *s)
 401 +{
 402 +  if (!nvram_isvalid())
 403 +    return;
 404 +
 405 +  nvram_delenv(s);
 406 +}
 407 +
 408 +/*
 409 + * apply func to each string in environment
 410 + */
 411 +static void
 412 +nvram_mapenv(int (*func)(char *, char *))
 413 +{
 414 +  int envsize, envp, n, i, seeneql;
 415 +  char name[256], value[256];
 416 +  char c, *s;
 417 +
 418 +  if (!nvram_isvalid())
 419 +    return;
 420 +
 421 +  envsize = nvram_getshort(NVOFF_ENVSIZE);
 422 +  envp = ENV_BASE;
 423 +
 424 +  while (envsize > 0) {
 425 +    value[0] = '\0';
 426 +    seeneql = 0;
 427 +    s = name;
 428 +    n = nvram_getbyte(envp);
 429 +    for (i = envp + 1; i < envp + n; i++) {
 430 +      c = nvram_getbyte(i);
 431 +      if ((c == '=') && !seeneql) {
 432 +        *s = '\0';
 433 +        s = value;
 434 +        seeneql = 1;
 435 +        continue;
 436 +      }
 437 +      *s++ = c;
 438 +    }
 439 +    *s = '\0';
 440 +    (*func)(name, value);
 441 +    envsize -= n;
 442 +    envp += n;
 443 +  }
 444 +}
 445 +#if 0
 446 +static unsigned int
 447 +digit(char c)
 448 +{
 449 +  if ('0' <= c && c <= '9')
 450 +    return (c - '0');
 451 +  if ('A' <= c && c <= 'Z')
 452 +    return (10 + c - 'A');
 453 +  if ('a' <= c && c <= 'z')
 454 +    return (10 + c - 'a');
 455 +  return (~0);
 456 +}
 457 +#endif
 458 +/*
 459 + * Wrappers to allow 'special' environment variables to get processed
 460 + */
 461 +void
 462 +setenv(char *e, char *v, int rewrite)
 463 +{
 464 +  if (nvram_getenv(e) && !rewrite)
 465 +    return;
 466 +
 467 +  nvram_setenv(e, v);
 468 +}
 469 +
 470 +char *
 471 +getenv(char *e)
 472 +{
 473 +  return(nvram_getenv(e));
 474 +}
 475 +
 476 +void
 477 +unsetenv(char *e)
 478 +{
 479 +  nvram_unsetenv(e);
 480 +}
 481 +
 482 +void
 483 +purgeenv()
 484 +{
 485 +  int i;
 486 +  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
 487 +
 488 +  for (i = ENV_BASE; i < ENV_TOP; i++)
 489 +    *nvramDataPointer++ = 0;
 490 +  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
 491 +  nvram_setshort(NVOFF_ENVSIZE, 0);
 492 +  nvram_setshort(NVOFF_CSUM, NV_MAGIC);
 493 +}
 494 +
 495 +void
 496 +mapenv(int (*func)(char *, char *))
 497 +{
 498 +  nvram_mapenv(func);
 499 +}
 500 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.h linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h
 501 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.h       1970-01-01 01:00:00.000000000 +0100
 502 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h  2006-06-18 12:44:28.000000000 +0200
 503 @@ -0,0 +1,66 @@
 504 +/**************************************************************************
 505 + *
 506 + *  BRIEF MODULE DESCRIPTION
 507 + *     nvram definitions.
 508 + *
 509 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 510 + *
 511 + *  This program is free software; you can redistribute  it and/or modify it
 512 + *  under  the terms of  the GNU General  Public License as published by the
 513 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 514 + *  option) any later version.
 515 + *
 516 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 517 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 518 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 519 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 520 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 521 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 522 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 523 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 524 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 525 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 526 + *
 527 + *  You should have received a copy of the  GNU General Public License along
 528 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 529 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 530 + *
 531 + *
 532 + **************************************************************************
 533 + * May 2004 rkt, neb
 534 + *
 535 + * Initial Release
 536 + *
 537 + *
 538 + *
 539 + **************************************************************************
 540 + */
 541 +
 542 +
 543 +#ifndef _NVRAM_
 544 +#define _NVRAM_
 545 +#define NVOFFSET        0                 /* use all of NVRAM */
 546 +
 547 +/* Offsets to reserved locations */
 548 +              /* size description */
 549 +#define NVOFF_MAGIC     (NVOFFSET + 0)    /* 2 magic value */
 550 +#define NVOFF_CSUM      (NVOFFSET + 2)    /* 2 NVRAM environment checksum */
 551 +#define NVOFF_ENVSIZE   (NVOFFSET + 4)    /* 2 size of 'environment' */
 552 +#define NVOFF_TEST      (NVOFFSET + 5)    /* 1 cold start test byte */
 553 +#define NVOFF_ETHADDR   (NVOFFSET + 6)    /* 6 decoded ethernet address */
 554 +#define NVOFF_UNUSED    (NVOFFSET + 12)   /* 0 current end of table */
 555 +
 556 +#define NV_MAGIC        0xdeaf            /* nvram magic number */
 557 +#define NV_RESERVED     6                 /* number of reserved bytes */
 558 +
 559 +#undef  NVOFF_ETHADDR
 560 +#define NVOFF_ETHADDR   (NVOFFSET + NV_RESERVED - 6)
 561 +
 562 +/* number of bytes available for environment */
 563 +#define ENV_BASE        (NVOFFSET + NV_RESERVED)
 564 +#define ENV_TOP         0x2000
 565 +#define ENV_AVAIL       (ENV_TOP - ENV_BASE)
 566 +
 567 +#endif /* _NVRAM_ */
 568 +
 569 +
 570 diff -Nur linux-2.6.17/arch/mips/aruba/prom.c linux-2.6.17-owrt/arch/mips/aruba/prom.c
 571 --- linux-2.6.17/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
 572 +++ linux-2.6.17-owrt/arch/mips/aruba/prom.c    2006-06-18 12:44:28.000000000 +0200
 573 @@ -0,0 +1,114 @@
 574 +/**************************************************************************
 575 + *
 576 + *  BRIEF MODULE DESCRIPTION
 577 + *     prom interface routines
 578 + *
 579 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 580 + *
 581 + *  This program is free software; you can redistribute  it and/or modify it
 582 + *  under  the terms of  the GNU General  Public License as published by the
 583 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 584 + *  option) any later version.
 585 + *
 586 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 587 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 588 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 589 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 590 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 591 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 592 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 593 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 594 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 595 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 596 + *
 597 + *  You should have received a copy of the  GNU General Public License along
 598 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 599 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 600 + *
 601 + *
 602 + **************************************************************************
 603 + * May 2004 rkt, neb
 604 + *
 605 + * Initial Release
 606 + *
 607 + *
 608 + *
 609 + **************************************************************************
 610 + */
 611 +
 612 +#include <linux/autoconf.h>
 613 +#include <linux/init.h>
 614 +#include <linux/mm.h>
 615 +#include <linux/module.h>
 616 +#include <linux/string.h>
 617 +#include <linux/console.h>
 618 +#include <asm/bootinfo.h>
 619 +#include <linux/bootmem.h>
 620 +#include <linux/ioport.h>
 621 +#include <linux/serial.h>
 622 +#include <linux/serialP.h>
 623 +#include <asm/serial.h>
 624 +#include <linux/ioport.h>
 625 +
 626 +unsigned int idt_cpu_freq;
 627 +EXPORT_SYMBOL(idt_cpu_freq);
 628 +
 629 +unsigned int arch_has_pci=0;
 630 +
 631 +/* Kernel Boot parameters */
 632 +static unsigned char bootparm[] =
 633 +       "mtdparts=physmap-flash.0:3520k@0x080000(zImage),2752k@0x140000(JFFS2),8k@0x3f8000(NVRAM) "
 634 +       "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2 ";
 635 +
 636 +
 637 +extern unsigned long mips_machgroup;
 638 +extern unsigned long mips_machtype;
 639 +
 640 +extern void setup_serial_port(void);
 641 +extern char * getenv(char *e);
 642 +
 643 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
 644 +#define RAM_SIZE        32*1024*1024
 645 +
 646 +char *__init prom_getcmdline(void)
 647 +{
 648 +       return &(arcs_cmdline[0]);
 649 +}
 650 +
 651 +void __init prom_init(void)
 652 +{
 653 +       char *boardname;
 654 +       sprintf(arcs_cmdline, "%s", bootparm);
 655 +
 656 +       /* set our arch type */
 657 +       mips_machgroup = MACH_GROUP_ARUBA;
 658 +       mips_machtype = MACH_ARUBA_UNKNOWN;
 659 +
 660 +       boardname=getenv("boardname");
 661 +
 662 +       if (!strcmp(boardname,"Muscat")) {
 663 +               mips_machtype = MACH_ARUBA_AP70;
 664 +               idt_cpu_freq = 133000000;
 665 +               arch_has_pci=1;
 666 +       } else if (!strcmp(boardname,"Mataro")) {
 667 +               mips_machtype = MACH_ARUBA_AP65;
 668 +               idt_cpu_freq = 110000000;
 669 +       } else if (!strcmp(boardname,"Merlot")) {
 670 +               mips_machtype = MACH_ARUBA_AP60;
 671 +               idt_cpu_freq = 90000000;
 672 +       }
 673 +
 674 +       /* turn on the console */
 675 +       setup_serial_port();
 676 +
 677 +       /*
 678 +        * give all RAM to boot allocator,
 679 +        * except where the kernel was loaded
 680 +        */
 681 +       add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
 682 +}
 683 +
 684 +void prom_free_prom_memory(void)
 685 +{
 686 +       printk("stubbed prom_free_prom_memory()\n");
 687 +}
 688 diff -Nur linux-2.6.17/arch/mips/aruba/serial.c linux-2.6.17-owrt/arch/mips/aruba/serial.c
 689 --- linux-2.6.17/arch/mips/aruba/serial.c       1970-01-01 01:00:00.000000000 +0100
 690 +++ linux-2.6.17-owrt/arch/mips/aruba/serial.c  2006-06-18 12:44:28.000000000 +0200
 691 @@ -0,0 +1,94 @@
 692 +/**************************************************************************
 693 + *
 694 + *  BRIEF MODULE DESCRIPTION
 695 + *     Serial port initialisation.
 696 + *
 697 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 698 + *
 699 + *  This program is free software; you can redistribute  it and/or modify it
 700 + *  under  the terms of  the GNU General  Public License as published by the
 701 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 702 + *  option) any later version.
 703 + *
 704 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 705 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 706 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 707 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 708 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 709 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 710 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 711 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 712 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 713 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 714 + *
 715 + *  You should have received a copy of the  GNU General Public License along
 716 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 717 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 718 + *
 719 + *
 720 + **************************************************************************
 721 + * May 2004 rkt, neb
 722 + *
 723 + * Initial Release
 724 + *
 725 + *
 726 + *
 727 + **************************************************************************
 728 + */
 729 +
 730 +
 731 +#include <linux/autoconf.h>
 732 +#include <linux/init.h>
 733 +#include <linux/sched.h>
 734 +#include <linux/pci.h>
 735 +#include <linux/interrupt.h>
 736 +#include <linux/tty.h>
 737 +#include <linux/serial.h>
 738 +#include <linux/serial_core.h>
 739 +
 740 +#include <asm/time.h>
 741 +#include <asm/cpu.h>
 742 +#include <asm/bootinfo.h>
 743 +#include <asm/irq.h>
 744 +#include <asm/serial.h>
 745 +
 746 +#include <asm/idt-boards/rc32434/rc32434.h>
 747 +
 748 +extern int __init early_serial_setup(struct uart_port *port);
 749 +
 750 +#define BASE_BAUD (1843200 / 16)
 751 +
 752 +extern unsigned int idt_cpu_freq;
 753 +
 754 +extern int __init setup_serial_port(void)
 755 +{
 756 +       static struct uart_port serial_req[2];
 757 +
 758 +       memset(serial_req, 0, sizeof(serial_req));
 759 +       serial_req[0].type       = PORT_16550A;
 760 +       serial_req[0].line       = 0;
 761 +       serial_req[0].flags      = STD_COM_FLAGS;
 762 +       serial_req[0].iotype     = SERIAL_IO_MEM;
 763 +       serial_req[0].regshift   = 2;
 764 +
 765 +       switch (mips_machtype) {
 766 +               case MACH_ARUBA_AP70:
 767 +                       serial_req[0].irq        = 104;
 768 +                       serial_req[0].mapbase    = KSEG1ADDR(0x18058003);
 769 +                       serial_req[0].membase    = (char *) KSEG1ADDR(0x18058003);
 770 +                       serial_req[0].uartclk    = idt_cpu_freq;
 771 +                       break;
 772 +               case MACH_ARUBA_AP65:
 773 +               case MACH_ARUBA_AP60:
 774 +               default:
 775 +                       serial_req[0].irq        = 12;
 776 +                       serial_req[0].mapbase    = KSEG1ADDR(0xbc000003);
 777 +                       serial_req[0].membase    = (char *) KSEG1ADDR(0xbc000003);
 778 +                       serial_req[0].uartclk    = idt_cpu_freq / 2;
 779 +                       break;
 780 +       }
 781 +
 782 +       early_serial_setup(&serial_req[0]);
 783 +
 784 +       return(0);
 785 +}
 786 diff -Nur linux-2.6.17/arch/mips/aruba/setup.c linux-2.6.17-owrt/arch/mips/aruba/setup.c
 787 --- linux-2.6.17/arch/mips/aruba/setup.c        1970-01-01 01:00:00.000000000 +0100
 788 +++ linux-2.6.17-owrt/arch/mips/aruba/setup.c   2006-06-18 12:44:28.000000000 +0200
 789 @@ -0,0 +1,128 @@
 790 +/**************************************************************************
 791 + *
 792 + *  BRIEF MODULE DESCRIPTION
 793 + *     setup routines for IDT EB434 boards
 794 + *
 795 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 796 + *
 797 + *  This program is free software; you can redistribute  it and/or modify it
 798 + *  under  the terms of  the GNU General  Public License as published by the
 799 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 800 + *  option) any later version.
 801 + *
 802 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 803 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 804 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 805 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 806 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 807 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 808 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 809 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 810 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 811 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 812 + *
 813 + *  You should have received a copy of the  GNU General Public License along
 814 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 815 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 816 + *
 817 + *
 818 + **************************************************************************
 819 + * May 2004 rkt, neb
 820 + *
 821 + * Initial Release
 822 + *
 823 + *
 824 + *
 825 + **************************************************************************
 826 + */
 827 +
 828 +#include <linux/init.h>
 829 +#include <linux/module.h>
 830 +#include <linux/mm.h>
 831 +#include <linux/sched.h>
 832 +#include <linux/irq.h>
 833 +#include <asm/bootinfo.h>
 834 +#include <asm/io.h>
 835 +#include <linux/ioport.h>
 836 +#include <asm/mipsregs.h>
 837 +#include <asm/pgtable.h>
 838 +#include <asm/reboot.h>
 839 +#include <asm/addrspace.h>     /* for KSEG1ADDR() */
 840 +#include <asm/idt-boards/rc32434/rc32434.h>
 841 +#include <linux/pm.h>
 842 +
 843 +extern char *__init prom_getcmdline(void);
 844 +
 845 +extern void (*board_time_init) (void);
 846 +extern void aruba_time_init(void);
 847 +extern void aruba_reset(void);
 848 +
 849 +#define epldMask ((volatile unsigned char *)0xB900000d)
 850 +
 851 +static void aruba_machine_restart(char *command)
 852 +{
 853 +       switch (mips_machtype) {
 854 +               case MACH_ARUBA_AP70:
 855 +                       *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
 856 +                       break;
 857 +               case MACH_ARUBA_AP65:
 858 +               case MACH_ARUBA_AP60:
 859 +               default:
 860 +                       /* Reset*/
 861 +                       *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
 862 +                       udelay(100);
 863 +                       *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
 864 +                       udelay(100);
 865 +                       *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
 866 +                       break;
 867 +       }
 868 +}
 869 +
 870 +static void aruba_machine_halt(void)
 871 +{
 872 +       for (;;) continue;
 873 +}
 874 +
 875 +extern char * getenv(char *e);
 876 +extern void unlock_ap60_70_flash(void);
 877 +
 878 +void __init plat_mem_setup(void)
 879 +{
 880 +       board_time_init = aruba_time_init;
 881 +
 882 +       _machine_restart = aruba_machine_restart;
 883 +       _machine_halt = aruba_machine_halt;
 884 +       pm_power_off = aruba_machine_halt;
 885 +
 886 +       set_io_port_base(KSEG1);
 887 +
 888 +       /* Enable PCI interrupts in EPLD Mask register */
 889 +       *epldMask = 0x0;
 890 +       *(epldMask + 1) = 0x0;
 891 +
 892 +       write_c0_wired(0);
 893 +       unlock_ap60_70_flash();
 894 +
 895 +       printk("BOARD - %s\n",getenv("boardname"));
 896 +}
 897 +
 898 +int page_is_ram(unsigned long pagenr)
 899 +{
 900 +       return 1;
 901 +}
 902 +
 903 +const char *get_system_type(void)
 904 +{
 905 +       switch (mips_machtype) {
 906 +               case MACH_ARUBA_AP70:
 907 +                       return "Aruba AP70";
 908 +               case MACH_ARUBA_AP65:
 909 +                       return "Aruba AP65";
 910 +               case MACH_ARUBA_AP60:
 911 +                       return "Aruba AP60/AP61";
 912 +               default:
 913 +                       return "Aruba UNKNOWN";
 914 +       }
 915 +}
 916 +
 917 +EXPORT_SYMBOL(get_system_type);
 918 diff -Nur linux-2.6.17/arch/mips/aruba/time.c linux-2.6.17-owrt/arch/mips/aruba/time.c
 919 --- linux-2.6.17/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
 920 +++ linux-2.6.17-owrt/arch/mips/aruba/time.c    2006-06-18 12:44:28.000000000 +0200
 921 @@ -0,0 +1,110 @@
 922 +/**************************************************************************
 923 + *
 924 + *  BRIEF MODULE DESCRIPTION
 925 + *     timer routines for IDT EB434 boards
 926 + *
 927 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 928 + *
 929 + *  This program is free software; you can redistribute  it and/or modify it
 930 + *  under  the terms of  the GNU General  Public License as published by the
 931 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 932 + *  option) any later version.
 933 + *
 934 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 935 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 936 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 937 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 938 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 939 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 940 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 941 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 942 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 943 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 944 + *
 945 + *  You should have received a copy of the  GNU General Public License along
 946 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 947 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 948 + *
 949 + *
 950 + **************************************************************************
 951 + * May 2004 rkt, neb
 952 + *
 953 + * Initial Release
 954 + *
 955 + *
 956 + *
 957 + **************************************************************************
 958 + */
 959 +
 960 +#include <linux/autoconf.h>
 961 +#include <linux/init.h>
 962 +#include <linux/kernel_stat.h>
 963 +#include <linux/sched.h>
 964 +#include <linux/spinlock.h>
 965 +#include <linux/mc146818rtc.h>
 966 +#include <linux/irq.h>
 967 +#include <linux/timex.h>
 968 +
 969 +#include <linux/param.h>
 970 +#include <asm/mipsregs.h>
 971 +#include <asm/ptrace.h>
 972 +#include <asm/time.h>
 973 +#include <asm/hardirq.h>
 974 +
 975 +#include <asm/mipsregs.h>
 976 +#include <asm/ptrace.h>
 977 +#include <asm/debug.h>
 978 +#include <asm/time.h>
 979 +
 980 +#include <asm/idt-boards/rc32434/rc32434.h>
 981 +
 982 +static unsigned long r4k_offset;       /* Amount to incr compare reg each time */
 983 +static unsigned long r4k_cur;  /* What counter should be at next timer irq */
 984 +
 985 +extern unsigned int idt_cpu_freq;
 986 +
 987 +static unsigned long __init cal_r4koff(void)
 988 +{
 989 +       mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
 990 +       return (mips_hpt_frequency / HZ);
 991 +}
 992 +
 993 +void __init aruba_time_init(void)
 994 +{
 995 +       unsigned int est_freq, flags;
 996 +       local_irq_save(flags);
 997 +
 998 +       printk("calculating r4koff... ");
 999 +       r4k_offset = cal_r4koff();
1000 +       printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
1001 +
1002 +       est_freq = 2 * r4k_offset * HZ;
1003 +       est_freq += 5000;       /* round */
1004 +       est_freq -= est_freq % 10000;
1005 +       printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1006 +              (est_freq % 1000000) * 100 / 1000000);
1007 +       local_irq_restore(flags);
1008 +
1009 +}
1010 +
1011 +void __init plat_timer_setup(struct irqaction *irq)
1012 +{
1013 +       /* we are using the cpu counter for timer interrupts */
1014 +       setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1015 +
1016 +       /* to generate the first timer interrupt */
1017 +       r4k_cur = (read_c0_count() + r4k_offset);
1018 +       write_c0_compare(r4k_cur);
1019 +
1020 +}
1021 +
1022 +asmlinkage void aruba_timer_interrupt(struct pt_regs *regs)
1023 +{
1024 +       int irq = MIPS_CPU_TIMER_IRQ;
1025 +
1026 +       irq_enter();
1027 +       kstat_this_cpu.irqs[irq]++;
1028 +
1029 +       timer_interrupt(irq, NULL);
1030 +       irq_exit();
1031 +}
1032 diff -Nur linux-2.6.17/arch/mips/Kconfig linux-2.6.17-owrt/arch/mips/Kconfig
1033 --- linux-2.6.17/arch/mips/Kconfig      2006-06-18 03:49:35.000000000 +0200
1034 +++ linux-2.6.17-owrt/arch/mips/Kconfig 2006-06-18 12:44:28.000000000 +0200
1035 @@ -227,6 +227,17 @@
1036           either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1037           a kernel for this platform.
1038
1039 +config MACH_ARUBA
1040 +       bool "Support for the ARUBA product line"
1041 +       select DMA_NONCOHERENT
1042 +       select CPU_HAS_PREFETCH
1043 +       select HW_HAS_PCI
1044 +       select SWAP_IO_SPACE
1045 +       select SYS_SUPPORTS_32BIT_KERNEL
1046 +       select SYS_HAS_CPU_MIPS32_R1
1047 +       select SYS_SUPPORTS_BIG_ENDIAN
1048 +
1049 +
1050  config MACH_JAZZ
1051         bool "Jazz family of machines"
1052         select ARC
1053 diff -Nur linux-2.6.17/arch/mips/Makefile linux-2.6.17-owrt/arch/mips/Makefile
1054 --- linux-2.6.17/arch/mips/Makefile     2006-06-18 03:49:35.000000000 +0200
1055 +++ linux-2.6.17-owrt/arch/mips/Makefile        2006-06-18 12:44:28.000000000 +0200
1056 @@ -145,6 +145,14 @@
1057  #
1058
1059  #
1060 +# Aruba
1061 +#
1062 +
1063 +core-$(CONFIG_MACH_ARUBA)      += arch/mips/aruba/
1064 +cflags-$(CONFIG_MACH_ARUBA)    += -Iinclude/asm-mips/aruba
1065 +load-$(CONFIG_MACH_ARUBA)      += 0x80100000
1066 +
1067 +#
1068  # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1069  #
1070  core-$(CONFIG_MACH_JAZZ)       += arch/mips/jazz/
1071 diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
1072 --- linux-2.6.17/arch/mips/mm/tlbex.c   2006-06-18 03:49:35.000000000 +0200
1073 +++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c      2006-06-18 12:48:27.000000000 +0200
1074 @@ -876,7 +876,6 @@
1075         case CPU_R10000:
1076         case CPU_R12000:
1077         case CPU_R14000:
1078 -       case CPU_4KC:
1079         case CPU_SB1:
1080         case CPU_SB1A:
1081         case CPU_4KSC:
1082 @@ -904,6 +903,7 @@
1083                 tlbw(p);
1084                 break;
1085
1086 +       case CPU_4KC:
1087         case CPU_4KEC:
1088         case CPU_24K:
1089         case CPU_34K:
1090 diff -Nur linux-2.6.17/drivers/net/Kconfig linux-2.6.17-owrt/drivers/net/Kconfig
1091 --- linux-2.6.17/drivers/net/Kconfig    2006-06-18 03:49:35.000000000 +0200
1092 +++ linux-2.6.17-owrt/drivers/net/Kconfig       2006-06-18 12:44:28.000000000 +0200
1093 @@ -187,6 +187,13 @@
1094
1095  source "drivers/net/arm/Kconfig"
1096
1097 +config IDT_RC32434_ETH
1098 +        tristate "IDT RC32434 Local Ethernet support"
1099 +        depends on NET_ETHERNET
1100 +        help
1101 +        IDT RC32434 has one local ethernet port. Say Y here to enable it.
1102 +        To compile this driver as a module, choose M here.
1103 +
1104  config MACE
1105         tristate "MACE (Power Mac ethernet) support"
1106         depends on NET_ETHERNET && PPC_PMAC && PPC32
1107 diff -Nur linux-2.6.17/drivers/net/Makefile linux-2.6.17-owrt/drivers/net/Makefile
1108 --- linux-2.6.17/drivers/net/Makefile   2006-06-18 03:49:35.000000000 +0200
1109 +++ linux-2.6.17-owrt/drivers/net/Makefile      2006-06-18 12:44:28.000000000 +0200
1110 @@ -38,6 +38,7 @@
1111
1112  obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1113
1114 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1115  obj-$(CONFIG_DGRS) += dgrs.o
1116  obj-$(CONFIG_VORTEX) += 3c59x.o
1117  obj-$(CONFIG_TYPHOON) += typhoon.o
1118 diff -Nur linux-2.6.17/drivers/net/natsemi.c linux-2.6.17-owrt/drivers/net/natsemi.c
1119 --- linux-2.6.17/drivers/net/natsemi.c  2006-06-18 03:49:35.000000000 +0200
1120 +++ linux-2.6.17-owrt/drivers/net/natsemi.c     2006-06-18 12:44:28.000000000 +0200
1121 @@ -771,6 +771,49 @@
1122  static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1123  static struct ethtool_ops ethtool_ops;
1124
1125 +#ifdef CONFIG_MACH_ARUBA
1126 +
1127 +#include <linux/ctype.h>
1128 +
1129 +#ifndef ERR
1130 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1131 +#endif
1132 +
1133 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1134 +{
1135 +        int i, j;
1136 +        unsigned char result, value;
1137 +
1138 +        for (i=0; i<6; i++) {
1139 +                result = 0;
1140 +                if (i != 5 && *(macstr+2) != ':') {
1141 +                        ERR("invalid mac address format: %d %c\n",
1142 +                            i, *(macstr+2));
1143 +                        return -EINVAL;
1144 +                }
1145 +                for (j=0; j<2; j++) {
1146 +                        if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1147 +                                                  toupper(*macstr)-'A'+10) < 16) {
1148 +                                result = result*16 + value;
1149 +                                macstr++;
1150 +                        }
1151 +                        else {
1152 +                                ERR("invalid mac address "
1153 +                                    "character: %c\n", *macstr);
1154 +                                return -EINVAL;
1155 +                        }
1156 +                }
1157 +
1158 +                macstr++;
1159 +                dev->dev_addr[i] = result;
1160 +        }
1161 +
1162 +       dev->dev_addr[5]++;
1163 +        return 0;
1164 +}
1165 +
1166 +#endif
1167 +
1168  static inline void __iomem *ns_ioaddr(struct net_device *dev)
1169  {
1170         return (void __iomem *) dev->base_addr;
1171 @@ -871,6 +914,7 @@
1172                 goto err_ioremap;
1173         }
1174
1175 +#ifndef CONFIG_MACH_ARUBA
1176         /* Work around the dropped serial bit. */
1177         prev_eedata = eeprom_read(ioaddr, 6);
1178         for (i = 0; i < 3; i++) {
1179 @@ -879,6 +923,19 @@
1180                 dev->dev_addr[i*2+1] = eedata >> 7;
1181                 prev_eedata = eedata;
1182         }
1183 +#else
1184 +       {
1185 +               char mac[32];
1186 +               unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1187 +               extern char *getenv(char *e);
1188 +               memset(mac, 0, 32);
1189 +               memcpy(mac, getenv("ethaddr"), 17);
1190 +               if (parse_mac_addr(dev, mac)){
1191 +                       printk("%s: MAC address not found\n", __func__);
1192 +                       memcpy(dev->dev_addr, def_mac, 6);
1193 +               }
1194 +       }
1195 +#endif
1196
1197         dev->base_addr = (unsigned long __force) ioaddr;
1198         dev->irq = irq;
1199 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.c linux-2.6.17-owrt/drivers/net/rc32434_eth.c
1200 --- linux-2.6.17/drivers/net/rc32434_eth.c      1970-01-01 01:00:00.000000000 +0100
1201 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.c 2006-06-18 12:44:28.000000000 +0200
1202 @@ -0,0 +1,1273 @@
1203 +/**************************************************************************
1204 + *
1205 + *  BRIEF MODULE DESCRIPTION
1206 + *     Driver for the IDT RC32434 on-chip ethernet controller.
1207 + *
1208 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
1209 + *
1210 + *  This program is free software; you can redistribute  it and/or modify it
1211 + *  under  the terms of  the GNU General  Public License as published by the
1212 + *  Free Software Foundation;  either version 2 of the  License, or (at your
1213 + *  option) any later version.
1214 + *
1215 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
1216 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
1217 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
1218 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
1219 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1220 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
1221 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1222 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
1223 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1224 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1225 + *
1226 + *  You should have received a copy of the  GNU General Public License along
1227 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
1228 + *  675 Mass Ave, Cambridge, MA 02139, USA.
1229 + *
1230 + *
1231 + **************************************************************************
1232 + * May 2004 rkt, neb
1233 + *
1234 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1235 + *
1236 + * Aug 2004 Sadik
1237 + *
1238 + * Added NAPI
1239 + *
1240 + **************************************************************************
1241 + */
1242 +
1243 +#include <linux/autoconf.h>
1244 +#include <linux/version.h>
1245 +#include <linux/module.h>
1246 +#include <linux/kernel.h>
1247 +#include <linux/moduleparam.h>
1248 +#include <linux/sched.h>
1249 +#include <linux/ctype.h>
1250 +#include <linux/types.h>
1251 +#include <linux/fcntl.h>
1252 +#include <linux/interrupt.h>
1253 +#include <linux/ptrace.h>
1254 +#include <linux/init.h>
1255 +#include <linux/ioport.h>
1256 +#include <linux/proc_fs.h>
1257 +#include <linux/in.h>
1258 +#include <linux/slab.h>
1259 +#include <linux/string.h>
1260 +#include <linux/delay.h>
1261 +#include <linux/netdevice.h>
1262 +#include <linux/etherdevice.h>
1263 +#include <linux/skbuff.h>
1264 +#include <linux/errno.h>
1265 +#include <asm/bootinfo.h>
1266 +#include <asm/system.h>
1267 +#include <asm/bitops.h>
1268 +#include <asm/pgtable.h>
1269 +#include <asm/segment.h>
1270 +#include <asm/io.h>
1271 +#include <asm/dma.h>
1272 +
1273 +#include "rc32434_eth.h"
1274 +
1275 +#define DRIVER_VERSION "(mar2904)"
1276 +
1277 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1278 +
1279 +
1280 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1281 +                                  ((dev)->dev_addr[1]))
1282 +#define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
1283 +                                  ((dev)->dev_addr[3] << 16) | \
1284 +                                  ((dev)->dev_addr[4] << 8)  | \
1285 +                                  ((dev)->dev_addr[5]))
1286 +
1287 +#define MII_CLOCK 1250000                              /* no more than 2.5MHz */
1288 +static char mac0[18] = "08:00:06:05:40:01";
1289 +
1290 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52)
1291 +module_param_string(mac0, mac0, 18, 0);
1292 +#else
1293 +MODULE_PARM(mac0, "c18");
1294 +#endif
1295 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1296 +
1297 +static struct rc32434_if_t {
1298 +       char *name;
1299 +       struct net_device *dev;
1300 +       char* mac_str;
1301 +       int weight;
1302 +       u32 iobase;
1303 +       u32 rxdmabase;
1304 +       u32 txdmabase;
1305 +       int rx_dma_irq;
1306 +       int tx_dma_irq;
1307 +       int rx_ovr_irq;
1308 +       int tx_und_irq;
1309 +} rc32434_iflist[] =
1310 +{
1311 +       {
1312 +               "rc32434_eth0",      NULL,       mac0,
1313 +               64,
1314 +               ETH0_PhysicalAddress,
1315 +               ETH0_RX_DMA_ADDR,
1316 +               ETH0_TX_DMA_ADDR,
1317 +               ETH0_DMA_RX_IRQ,
1318 +               ETH0_DMA_TX_IRQ,
1319 +               ETH0_RX_OVR_IRQ,
1320 +               ETH0_TX_UND_IRQ
1321 +       }
1322 +};
1323 +
1324 +
1325 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1326 +{
1327 +       int i, j;
1328 +       unsigned char result, value;
1329 +
1330 +       for (i=0; i<6; i++) {
1331 +               result = 0;
1332 +               if (i != 5 && *(macstr+2) != ':') {
1333 +                       ERR("invalid mac address format: %d %c\n",
1334 +                           i, *(macstr+2));
1335 +                       return -EINVAL;
1336 +               }
1337 +               for (j=0; j<2; j++) {
1338 +                       if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1339 +                                                 toupper(*macstr)-'A'+10) < 16) {
1340 +                               result = result*16 + value;
1341 +                               macstr++;
1342 +                       }
1343 +                       else {
1344 +                               ERR("invalid mac address "
1345 +                                   "character: %c\n", *macstr);
1346 +                               return -EINVAL;
1347 +                       }
1348 +               }
1349 +
1350 +               macstr++;
1351 +               dev->dev_addr[i] = result;
1352 +       }
1353 +
1354 +       return 0;
1355 +}
1356 +
1357 +
1358 +
1359 +static inline void rc32434_abort_tx(struct net_device *dev)
1360 +{
1361 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1362 +       rc32434_abort_dma(dev, lp->tx_dma_regs);
1363 +
1364 +}
1365 +
1366 +static inline void rc32434_abort_rx(struct net_device *dev)
1367 +{
1368 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1369 +       rc32434_abort_dma(dev, lp->rx_dma_regs);
1370 +
1371 +}
1372 +
1373 +static inline void rc32434_start_tx(struct rc32434_local *lp,  volatile DMAD_t td)
1374 +{
1375 +       rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1376 +}
1377 +
1378 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1379 +{
1380 +       rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1381 +}
1382 +
1383 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1384 +{
1385 +       rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1386 +}
1387 +
1388 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1389 +{
1390 +       rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1391 +}
1392 +
1393 +#ifdef RC32434_PROC_DEBUG
1394 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1395 +                            int length, int *eof, void *data)
1396 +{
1397 +       struct net_device *dev = (struct net_device *)data;
1398 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1399 +       int len = 0;
1400 +
1401 +       /* print out header */
1402 +       len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1403 +       len += sprintf (buf + len,
1404 +                       "DMA halt count      = %10d, DMA run count = %10d\n",
1405 +                       lp->dma_halt_cnt, lp->dma_run_cnt);
1406 +
1407 +       if (fpos >= len) {
1408 +               *start = buf;
1409 +               *eof = 1;
1410 +               return 0;
1411 +       }
1412 +       *start = buf + fpos;
1413 +
1414 +       if ((len -= fpos) > length)
1415 +               return length;
1416 +       *eof = 1;
1417 +
1418 +       return len;
1419 +
1420 +}
1421 +#endif
1422 +
1423 +
1424 +/*
1425 + * Restart the RC32434 ethernet controller.
1426 + */
1427 +static int rc32434_restart(struct net_device *dev)
1428 +{
1429 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1430 +
1431 +       /*
1432 +        * Disable interrupts
1433 +        */
1434 +       disable_irq(lp->rx_irq);
1435 +       disable_irq(lp->tx_irq);
1436 +#ifdef RC32434_REVISION
1437 +       disable_irq(lp->ovr_irq);
1438 +#endif
1439 +       disable_irq(lp->und_irq);
1440 +
1441 +       /* Mask F E bit in Tx DMA */
1442 +       rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1443 +       /* Mask D H E bit in Rx DMA */
1444 +       rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1445 +
1446 +       rc32434_init(dev);
1447 +       rc32434_multicast_list(dev);
1448 +
1449 +       enable_irq(lp->und_irq);
1450 +#ifdef RC32434_REVISION
1451 +       enable_irq(lp->ovr_irq);
1452 +#endif
1453 +       enable_irq(lp->tx_irq);
1454 +       enable_irq(lp->rx_irq);
1455 +
1456 +       return 0;
1457 +}
1458 +
1459 +int rc32434_init_module(void)
1460 +{
1461 +#ifdef CONFIG_MACH_ARUBA
1462 +       if (mips_machtype != MACH_ARUBA_AP70)
1463 +               return 1;
1464 +#endif
1465 +
1466 +       printk(KERN_INFO DRIVER_NAME " \n");
1467 +       return rc32434_probe(0);
1468 +}
1469 +
1470 +static int rc32434_probe(int port_num)
1471 +{
1472 +       struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1473 +       struct rc32434_local *lp = NULL;
1474 +       struct net_device *dev = NULL;
1475 +       int i, retval,err;
1476 +
1477 +       dev = alloc_etherdev(sizeof(struct rc32434_local));
1478 +       if(!dev) {
1479 +               ERR("rc32434_eth: alloc_etherdev failed\n");
1480 +               return -1;
1481 +       }
1482 +
1483 +       SET_MODULE_OWNER(dev);
1484 +       bif->dev = dev;
1485 +
1486 +#ifdef CONFIG_MACH_ARUBA
1487 +       {
1488 +               extern char * getenv(char *e);
1489 +               memcpy(bif->mac_str, getenv("ethaddr"), 17);
1490 +       }
1491 +#endif
1492 +
1493 +       printk("mac: %s\n", bif->mac_str);
1494 +       if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1495 +               ERR("MAC address parse failed\n");
1496 +               free_netdev(dev);
1497 +               return -1;
1498 +       }
1499 +
1500 +
1501 +       /* Initialize the device structure. */
1502 +       if (dev->priv == NULL) {
1503 +               lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1504 +               memset(lp, 0, sizeof(struct rc32434_local));
1505 +       }
1506 +       else {
1507 +               lp = (struct rc32434_local *)dev->priv;
1508 +       }
1509 +
1510 +       lp->rx_irq = bif->rx_dma_irq;
1511 +       lp->tx_irq = bif->tx_dma_irq;
1512 +       lp->ovr_irq = bif->rx_ovr_irq;
1513 +       lp->und_irq = bif->tx_und_irq;
1514 +
1515 +       lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1516 +
1517 +       if (!lp->eth_regs) {
1518 +               ERR("Can't remap eth registers\n");
1519 +               retval = -ENXIO;
1520 +               goto probe_err_out;
1521 +       }
1522 +
1523 +       lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1524 +
1525 +       if (!lp->rx_dma_regs) {
1526 +               ERR("Can't remap Rx DMA registers\n");
1527 +               retval = -ENXIO;
1528 +               goto probe_err_out;
1529 +       }
1530 +       lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1531 +
1532 +       if (!lp->tx_dma_regs) {
1533 +               ERR("Can't remap Tx DMA registers\n");
1534 +               retval = -ENXIO;
1535 +               goto probe_err_out;
1536 +       }
1537 +
1538 +#ifdef RC32434_PROC_DEBUG
1539 +       lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1540 +                                        rc32434_read_proc, dev);
1541 +#endif
1542 +
1543 +       lp->td_ring =   (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1544 +       if (!lp->td_ring) {
1545 +               ERR("Can't allocate descriptors\n");
1546 +               retval = -ENOMEM;
1547 +               goto probe_err_out;
1548 +       }
1549 +
1550 +       dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1551 +
1552 +       /* now convert TD_RING pointer to KSEG1 */
1553 +       lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1554 +       lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1555 +
1556 +
1557 +       spin_lock_init(&lp->lock);
1558 +
1559 +       dev->base_addr = bif->iobase;
1560 +       /* just use the rx dma irq */
1561 +       dev->irq = bif->rx_dma_irq;
1562 +
1563 +       dev->priv = lp;
1564 +
1565 +       dev->open = rc32434_open;
1566 +       dev->stop = rc32434_close;
1567 +       dev->hard_start_xmit = rc32434_send_packet;
1568 +       dev->get_stats  = rc32434_get_stats;
1569 +       dev->set_multicast_list = &rc32434_multicast_list;
1570 +       dev->tx_timeout = rc32434_tx_timeout;
1571 +       dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1572 +
1573 +#ifdef CONFIG_IDT_USE_NAPI
1574 +       dev->poll = rc32434_poll;
1575 +       dev->weight = bif->weight;
1576 +       printk("Using NAPI with weight %d\n",dev->weight);
1577 +#else
1578 +       lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1579 +       tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1580 +#endif
1581 +       lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1582 +       tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1583 +
1584 +       if ((err = register_netdev(dev))) {
1585 +               printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1586 +               free_netdev(dev);
1587 +               retval = -EINVAL;
1588 +               goto probe_err_out;
1589 +       }
1590 +
1591 +       INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1592 +       for (i = 0; i < 6; i++) {
1593 +               printk("%2.2x", dev->dev_addr[i]);
1594 +               if (i<5)
1595 +                       printk(":");
1596 +       }
1597 +       printk("\n");
1598 +
1599 +       return 0;
1600 +
1601 + probe_err_out:
1602 +       rc32434_cleanup_module();
1603 +       ERR(" failed.  Returns %d\n", retval);
1604 +       return retval;
1605 +
1606 +}
1607 +
1608 +
1609 +static void rc32434_cleanup_module(void)
1610 +{
1611 +       int i;
1612 +
1613 +       for (i = 0; rc32434_iflist[i].iobase; i++) {
1614 +               struct rc32434_if_t * bif = &rc32434_iflist[i];
1615 +               if (bif->dev != NULL) {
1616 +                       struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1617 +                       if (lp != NULL) {
1618 +                               if (lp->eth_regs)
1619 +                                       iounmap((void*)lp->eth_regs);
1620 +                               if (lp->rx_dma_regs)
1621 +                                       iounmap((void*)lp->rx_dma_regs);
1622 +                               if (lp->tx_dma_regs)
1623 +                                       iounmap((void*)lp->tx_dma_regs);
1624 +                               if (lp->td_ring)
1625 +                                       kfree((void*)KSEG0ADDR(lp->td_ring));
1626 +
1627 +#ifdef RC32434_PROC_DEBUG
1628 +                               if (lp->ps) {
1629 +                                       remove_proc_entry(bif->name, proc_net);
1630 +                               }
1631 +#endif
1632 +                               kfree(lp);
1633 +                       }
1634 +
1635 +                       unregister_netdev(bif->dev);
1636 +                       free_netdev(bif->dev);
1637 +                       kfree(bif->dev);
1638 +               }
1639 +       }
1640 +}
1641 +
1642 +
1643 +
1644 +static int rc32434_open(struct net_device *dev)
1645 +{
1646 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1647 +
1648 +       /* Initialize */
1649 +       if (rc32434_init(dev)) {
1650 +               ERR("Error: cannot open the Ethernet device\n");
1651 +               return -EAGAIN;
1652 +       }
1653 +
1654 +       /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1655 +       if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1656 +                 SA_SHIRQ | SA_INTERRUPT,
1657 +                       "rc32434 ethernet Rx", dev)) {
1658 +               ERR(": unable to get Rx DMA IRQ %d\n",
1659 +                   lp->rx_irq);
1660 +               return -EAGAIN;
1661 +       }
1662 +       if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1663 +                 SA_SHIRQ | SA_INTERRUPT,
1664 +                       "rc32434 ethernet Tx", dev)) {
1665 +               ERR(": unable to get Tx DMA IRQ %d\n",
1666 +                   lp->tx_irq);
1667 +               free_irq(lp->rx_irq, dev);
1668 +               return -EAGAIN;
1669 +       }
1670 +
1671 +#ifdef RC32434_REVISION
1672 +       /* Install handler for overrun error. */
1673 +       if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1674 +                       SA_SHIRQ | SA_INTERRUPT,
1675 +                       "Ethernet Overflow", dev)) {
1676 +               ERR(": unable to get OVR IRQ %d\n",
1677 +                   lp->ovr_irq);
1678 +               free_irq(lp->rx_irq, dev);
1679 +               free_irq(lp->tx_irq, dev);
1680 +               return -EAGAIN;
1681 +       }
1682 +#endif
1683 +
1684 +       /* Install handler for underflow error. */
1685 +       if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1686 +                       SA_SHIRQ | SA_INTERRUPT,
1687 +                       "Ethernet Underflow", dev)) {
1688 +               ERR(": unable to get UND IRQ %d\n",
1689 +                   lp->und_irq);
1690 +               free_irq(lp->rx_irq, dev);
1691 +               free_irq(lp->tx_irq, dev);
1692 +#ifdef RC32434_REVISION
1693 +               free_irq(lp->ovr_irq, dev);
1694 +#endif
1695 +               return -EAGAIN;
1696 +       }
1697 +
1698 +
1699 +       return 0;
1700 +}
1701 +
1702 +
1703 +
1704 +
1705 +static int rc32434_close(struct net_device *dev)
1706 +{
1707 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1708 +       u32 tmp;
1709 +
1710 +       /* Disable interrupts */
1711 +       disable_irq(lp->rx_irq);
1712 +       disable_irq(lp->tx_irq);
1713 +#ifdef RC32434_REVISION
1714 +       disable_irq(lp->ovr_irq);
1715 +#endif
1716 +       disable_irq(lp->und_irq);
1717 +
1718 +       tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1719 +       tmp = tmp | DMASM_f_m | DMASM_e_m;
1720 +       rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1721 +
1722 +       tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1723 +       tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1724 +       rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1725 +
1726 +       free_irq(lp->rx_irq, dev);
1727 +       free_irq(lp->tx_irq, dev);
1728 +#ifdef RC32434_REVISION
1729 +       free_irq(lp->ovr_irq, dev);
1730 +#endif
1731 +       free_irq(lp->und_irq, dev);
1732 +       return 0;
1733 +}
1734 +
1735 +
1736 +/* transmit packet */
1737 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1738 +{
1739 +       struct rc32434_local            *lp = (struct rc32434_local *)dev->priv;
1740 +       unsigned long                   flags;
1741 +       u32                                     length;
1742 +       DMAD_t                          td;
1743 +
1744 +
1745 +       spin_lock_irqsave(&lp->lock, flags);
1746 +
1747 +       td = &lp->td_ring[lp->tx_chain_tail];
1748 +
1749 +       /* stop queue when full, drop pkts if queue already full */
1750 +       if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1751 +               lp->tx_full = 1;
1752 +
1753 +               if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1754 +                       netif_stop_queue(dev);
1755 +               }
1756 +               else {
1757 +                       lp->stats.tx_dropped++;
1758 +                       dev_kfree_skb_any(skb);
1759 +                       spin_unlock_irqrestore(&lp->lock, flags);
1760 +                       return 1;
1761 +               }
1762 +       }
1763 +
1764 +       lp->tx_count ++;
1765 +
1766 +       lp->tx_skb[lp->tx_chain_tail] = skb;
1767 +
1768 +       length = skb->len;
1769 +
1770 +       /* Setup the transmit descriptor. */
1771 +       td->ca = CPHYSADDR(skb->data);
1772 +
1773 +       if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1774 +               if( lp->tx_chain_status == empty ) {
1775 +                       td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /*  Update tail      */
1776 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /*   Move tail       */
1777 +                       rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR    */
1778 +                       lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
1779 +               }
1780 +               else {
1781 +                       td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m;                                 /* Update tail */
1782 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
1783 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
1784 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
1785 +                       rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1786 +                       lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
1787 +                       lp->tx_chain_status = empty;
1788 +               }
1789 +       }
1790 +       else {
1791 +               if( lp->tx_chain_status == empty ) {
1792 +                       td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
1793 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
1794 +                       lp->tx_chain_status = filled;
1795 +               }
1796 +               else {
1797 +                       td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
1798 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
1799 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
1800 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
1801 +               }
1802 +       }
1803 +
1804 +       dev->trans_start = jiffies;
1805 +
1806 +       spin_unlock_irqrestore(&lp->lock, flags);
1807 +
1808 +       return 0;
1809 +}
1810 +
1811 +
1812 +/* Ethernet MII-PHY Handler */
1813 +static void rc32434_mii_handler(unsigned long data)
1814 +{
1815 +       struct net_device *dev = (struct net_device *)data;
1816 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1817 +       unsigned long   flags;
1818 +       unsigned long duplex_status;
1819 +       int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1820 +
1821 +       spin_lock_irqsave(&lp->lock, flags);
1822 +
1823 +       /* Two ports are using the same MII, the difference is the PHY address */
1824 +       rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1825 +       rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1826 +       rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1827 +       rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1828 +       while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1829 +
1830 +       ERR("irq:%x             port_addr:%x    RDD:%x\n",
1831 +           lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1832 +       duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1833 +       if(duplex_status != lp->duplex_mode) {
1834 +               ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1835 +               lp->duplex_mode = duplex_status;
1836 +               rc32434_restart(dev);
1837 +       }
1838 +
1839 +       lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1840 +       add_timer(&lp->mii_phy_timer);
1841 +
1842 +       spin_unlock_irqrestore(&lp->lock, flags);
1843 +
1844 +}
1845 +
1846 +#ifdef RC32434_REVISION
1847 +/* Ethernet Rx Overflow interrupt */
1848 +static irqreturn_t
1849 +rc32434_ovr_interrupt(int irq, void *dev_id)
1850 +{
1851 +       struct net_device *dev = (struct net_device *)dev_id;
1852 +       struct rc32434_local *lp;
1853 +       unsigned int ovr;
1854 +       irqreturn_t retval = IRQ_NONE;
1855 +
1856 +       ASSERT(dev != NULL);
1857 +
1858 +       lp = (struct rc32434_local *)dev->priv;
1859 +       spin_lock(&lp->lock);
1860 +       ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1861 +
1862 +       if(ovr & ETHINTFC_ovr_m) {
1863 +               netif_stop_queue(dev);
1864 +
1865 +               /* clear OVR bit */
1866 +               rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1867 +
1868 +               /* Restart interface */
1869 +               rc32434_restart(dev);
1870 +               retval = IRQ_HANDLED;
1871 +       }
1872 +       spin_unlock(&lp->lock);
1873 +
1874 +       return retval;
1875 +}
1876 +
1877 +#endif
1878 +
1879 +
1880 +/* Ethernet Tx Underflow interrupt */
1881 +static irqreturn_t
1882 +rc32434_und_interrupt(int irq, void *dev_id)
1883 +{
1884 +       struct net_device *dev = (struct net_device *)dev_id;
1885 +       struct rc32434_local *lp;
1886 +       unsigned int und;
1887 +       irqreturn_t retval = IRQ_NONE;
1888 +
1889 +       ASSERT(dev != NULL);
1890 +
1891 +       lp = (struct rc32434_local *)dev->priv;
1892 +
1893 +       spin_lock(&lp->lock);
1894 +
1895 +       und = rc32434_readl(&lp->eth_regs->ethintfc);
1896 +
1897 +       if(und & ETHINTFC_und_m) {
1898 +               netif_stop_queue(dev);
1899 +
1900 +               rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1901 +
1902 +               /* Restart interface */
1903 +               rc32434_restart(dev);
1904 +               retval = IRQ_HANDLED;
1905 +       }
1906 +
1907 +       spin_unlock(&lp->lock);
1908 +
1909 +       return retval;
1910 +}
1911 +
1912 +
1913 +/* Ethernet Rx DMA interrupt */
1914 +static irqreturn_t
1915 +rc32434_rx_dma_interrupt(int irq, void *dev_id)
1916 +{
1917 +       struct net_device *dev = (struct net_device *)dev_id;
1918 +       struct rc32434_local* lp;
1919 +       volatile u32 dmas,dmasm;
1920 +       irqreturn_t retval;
1921 +
1922 +       ASSERT(dev != NULL);
1923 +
1924 +       lp = (struct rc32434_local *)dev->priv;
1925 +
1926 +       spin_lock(&lp->lock);
1927 +       dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1928 +       if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1929 +               /* Mask D H E bit in Rx DMA */
1930 +               dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1931 +               rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1932 +#ifdef CONFIG_IDT_USE_NAPI
1933 +               if(netif_rx_schedule_prep(dev))
1934 +                        __netif_rx_schedule(dev);
1935 +#else
1936 +               tasklet_hi_schedule(lp->rx_tasklet);
1937 +#endif
1938 +
1939 +               if (dmas & DMAS_e_m)
1940 +                       ERR(": DMA error\n");
1941 +
1942 +               retval = IRQ_HANDLED;
1943 +       }
1944 +       else
1945 +               retval = IRQ_NONE;
1946 +
1947 +       spin_unlock(&lp->lock);
1948 +       return retval;
1949 +}
1950 +
1951 +#ifdef CONFIG_IDT_USE_NAPI
1952 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1953 +#else
1954 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1955 +#endif
1956 +{
1957 +       struct net_device *dev = (struct net_device *)rx_data_dev;
1958 +       struct rc32434_local* lp = netdev_priv(dev);
1959 +       volatile DMAD_t  rd = &lp->rd_ring[lp->rx_next_done];
1960 +       struct sk_buff *skb, *skb_new;
1961 +       u8* pkt_buf;
1962 +       u32 devcs, count, pkt_len, pktuncrc_len;
1963 +       volatile u32 dmas;
1964 +#ifdef CONFIG_IDT_USE_NAPI
1965 +       u32 received = 0;
1966 +       int rx_work_limit = min(*budget,dev->quota);
1967 +#else
1968 +       unsigned long   flags;
1969 +       spin_lock_irqsave(&lp->lock, flags);
1970 +#endif
1971 +
1972 +       while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1973 +#ifdef CONFIG_IDT_USE_NAPI
1974 +               if(--rx_work_limit <0)
1975 +                {
1976 +                        break;
1977 +                }
1978 +#endif
1979 +               /* init the var. used for the later operations within the while loop */
1980 +               skb_new = NULL;
1981 +               devcs = rd->devcs;
1982 +               pkt_len = RCVPKT_LENGTH(devcs);
1983 +               skb = lp->rx_skb[lp->rx_next_done];
1984 +
1985 +               if (count < 64) {
1986 +                       lp->stats.rx_errors++;
1987 +                       lp->stats.rx_dropped++;
1988 +               }
1989 +               else if ((devcs & ( ETHRX_ld_m)) !=     ETHRX_ld_m) {
1990 +                       /* check that this is a whole packet */
1991 +                       /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1992 +                       lp->stats.rx_errors++;
1993 +                       lp->stats.rx_dropped++;
1994 +               }
1995 +               else if ( (devcs & ETHRX_rok_m)  ) {
1996 +
1997 +                       {
1998 +                               /* must be the (first and) last descriptor then */
1999 +                               pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
2000 +
2001 +                               pktuncrc_len = pkt_len - 4;
2002 +                               /* invalidate the cache */
2003 +                               dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
2004 +
2005 +                               /* Malloc up new buffer. */
2006 +                               skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
2007 +
2008 +                               if (skb_new != NULL){
2009 +                                       /* Make room */
2010 +                                       skb_put(skb, pktuncrc_len);
2011 +
2012 +                                       skb->protocol = eth_type_trans(skb, dev);
2013 +
2014 +                                       /* pass the packet to upper layers */
2015 +#ifdef CONFIG_IDT_USE_NAPI
2016 +                                       netif_receive_skb(skb);
2017 +#else
2018 +                                       netif_rx(skb);
2019 +#endif
2020 +
2021 +                                       dev->last_rx = jiffies;
2022 +                                       lp->stats.rx_packets++;
2023 +                                       lp->stats.rx_bytes += pktuncrc_len;
2024 +
2025 +                                       if (IS_RCV_MP(devcs))
2026 +                                               lp->stats.multicast++;
2027 +
2028 +                                       /* 16 bit align */
2029 +                                       skb_reserve(skb_new, 2);
2030 +
2031 +                                       skb_new->dev = dev;
2032 +                                       lp->rx_skb[lp->rx_next_done] = skb_new;
2033 +                               }
2034 +                               else {
2035 +                                       ERR("no memory, dropping rx packet.\n");
2036 +                                       lp->stats.rx_errors++;
2037 +                                       lp->stats.rx_dropped++;
2038 +                               }
2039 +                       }
2040 +
2041 +               }
2042 +               else {
2043 +                       /* This should only happen if we enable accepting broken packets */
2044 +                       lp->stats.rx_errors++;
2045 +                       lp->stats.rx_dropped++;
2046 +
2047 +                       /* add statistics counters */
2048 +                       if (IS_RCV_CRC_ERR(devcs)) {
2049 +                               DBG(2, "RX CRC error\n");
2050 +                               lp->stats.rx_crc_errors++;
2051 +                       }
2052 +                       else if (IS_RCV_LOR_ERR(devcs)) {
2053 +                               DBG(2, "RX LOR error\n");
2054 +                               lp->stats.rx_length_errors++;
2055 +                       }
2056 +                       else if (IS_RCV_LE_ERR(devcs)) {
2057 +                               DBG(2, "RX LE error\n");
2058 +                               lp->stats.rx_length_errors++;
2059 +                       }
2060 +                       else if (IS_RCV_OVR_ERR(devcs)) {
2061 +                               lp->stats.rx_over_errors++;
2062 +                       }
2063 +                       else if (IS_RCV_CV_ERR(devcs)) {
2064 +                               /* code violation */
2065 +                               DBG(2, "RX CV error\n");
2066 +                               lp->stats.rx_frame_errors++;
2067 +                       }
2068 +                       else if (IS_RCV_CES_ERR(devcs)) {
2069 +                               DBG(2, "RX Preamble error\n");
2070 +                       }
2071 +               }
2072 +
2073 +               rd->devcs = 0;
2074 +
2075 +               /* restore descriptor's curr_addr */
2076 +               if(skb_new)
2077 +                       rd->ca = CPHYSADDR(skb_new->data);
2078 +               else
2079 +                       rd->ca = CPHYSADDR(skb->data);
2080 +
2081 +               rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2082 +               lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &=  ~(DMAD_cod_m);
2083 +
2084 +               lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2085 +               rd = &lp->rd_ring[lp->rx_next_done];
2086 +               rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2087 +       }
2088 +#ifdef CONFIG_IDT_USE_NAPI
2089 +        dev->quota -= received;
2090 +        *budget =- received;
2091 +        if(rx_work_limit < 0)
2092 +                goto not_done;
2093 +#endif
2094 +
2095 +       dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2096 +
2097 +       if(dmas & DMAS_h_m) {
2098 +               rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2099 +#ifdef RC32434_PROC_DEBUG
2100 +               lp->dma_halt_cnt++;
2101 +#endif
2102 +               rd->devcs = 0;
2103 +               skb = lp->rx_skb[lp->rx_next_done];
2104 +               rd->ca = CPHYSADDR(skb->data);
2105 +               rc32434_chain_rx(lp,rd);
2106 +       }
2107 +
2108 +#ifdef CONFIG_IDT_USE_NAPI
2109 +       netif_rx_complete(dev);
2110 +#endif
2111 +       /* Enable D H E bit in Rx DMA */
2112 +       rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2113 +#ifdef CONFIG_IDT_USE_NAPI
2114 +       return 0;
2115 + not_done:
2116 +       return 1;
2117 +#else
2118 +       spin_unlock_irqrestore(&lp->lock, flags);
2119 +       return;
2120 +#endif
2121 +
2122 +
2123 +}
2124 +
2125 +
2126 +
2127 +/* Ethernet Tx DMA interrupt */
2128 +static irqreturn_t
2129 +rc32434_tx_dma_interrupt(int irq, void *dev_id)
2130 +{
2131 +       struct net_device *dev = (struct net_device *)dev_id;
2132 +       struct rc32434_local *lp;
2133 +       volatile u32 dmas,dmasm;
2134 +       irqreturn_t retval;
2135 +
2136 +       ASSERT(dev != NULL);
2137 +
2138 +       lp = (struct rc32434_local *)dev->priv;
2139 +
2140 +       spin_lock(&lp->lock);
2141 +
2142 +       dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2143 +
2144 +       if (dmas & (DMAS_f_m | DMAS_e_m)) {
2145 +               dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2146 +               /* Mask F E bit in Tx DMA */
2147 +               rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2148 +
2149 +               tasklet_hi_schedule(lp->tx_tasklet);
2150 +
2151 +               if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2152 +                       rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2153 +                       lp->tx_chain_status = empty;
2154 +                       lp->tx_chain_head = lp->tx_chain_tail;
2155 +                       dev->trans_start = jiffies;
2156 +               }
2157 +
2158 +               if (dmas & DMAS_e_m)
2159 +                       ERR(": DMA error\n");
2160 +
2161 +               retval = IRQ_HANDLED;
2162 +       }
2163 +       else
2164 +               retval = IRQ_NONE;
2165 +
2166 +       spin_unlock(&lp->lock);
2167 +
2168 +       return retval;
2169 +}
2170 +
2171 +
2172 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2173 +{
2174 +       struct net_device *dev = (struct net_device *)tx_data_dev;
2175 +       struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2176 +       volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2177 +       u32 devcs;
2178 +       unsigned long   flags;
2179 +       volatile u32 dmas;
2180 +
2181 +       spin_lock_irqsave(&lp->lock, flags);
2182 +
2183 +       /* process all desc that are done */
2184 +       while(IS_DMA_FINISHED(td->control)) {
2185 +               if(lp->tx_full == 1) {
2186 +                       netif_wake_queue(dev);
2187 +                       lp->tx_full = 0;
2188 +               }
2189 +
2190 +               devcs = lp->td_ring[lp->tx_next_done].devcs;
2191 +               if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2192 +                       lp->stats.tx_errors++;
2193 +                       lp->stats.tx_dropped++;
2194 +
2195 +                       /* should never happen */
2196 +                       DBG(1, __FUNCTION__ ": split tx ignored\n");
2197 +               }
2198 +               else if (IS_TX_TOK(devcs)) {
2199 +                       lp->stats.tx_packets++;
2200 +               }
2201 +               else {
2202 +                       lp->stats.tx_errors++;
2203 +                       lp->stats.tx_dropped++;
2204 +
2205 +                       /* underflow */
2206 +                       if (IS_TX_UND_ERR(devcs))
2207 +                               lp->stats.tx_fifo_errors++;
2208 +
2209 +                       /* oversized frame */
2210 +                       if (IS_TX_OF_ERR(devcs))
2211 +                               lp->stats.tx_aborted_errors++;
2212 +
2213 +                       /* excessive deferrals */
2214 +                       if (IS_TX_ED_ERR(devcs))
2215 +                               lp->stats.tx_carrier_errors++;
2216 +
2217 +                       /* collisions: medium busy */
2218 +                       if (IS_TX_EC_ERR(devcs))
2219 +                               lp->stats.collisions++;
2220 +
2221 +                       /* late collision */
2222 +                       if (IS_TX_LC_ERR(devcs))
2223 +                               lp->stats.tx_window_errors++;
2224 +
2225 +               }
2226 +
2227 +               /* We must always free the original skb */
2228 +               if (lp->tx_skb[lp->tx_next_done] != NULL) {
2229 +                       dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2230 +                       lp->tx_skb[lp->tx_next_done] = NULL;
2231 +               }
2232 +
2233 +               lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2234 +               lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2235 +               lp->td_ring[lp->tx_next_done].link = 0;
2236 +               lp->td_ring[lp->tx_next_done].ca = 0;
2237 +               lp->tx_count --;
2238 +
2239 +               /* go on to next transmission */
2240 +               lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2241 +               td = &lp->td_ring[lp->tx_next_done];
2242 +
2243 +       }
2244 +
2245 +       dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2246 +       rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2247 +
2248 +       /* Enable F E bit in Tx DMA */
2249 +       rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2250 +       spin_unlock_irqrestore(&lp->lock, flags);
2251 +
2252 +}
2253 +
2254 +
2255 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2256 +{
2257 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2258 +       return &lp->stats;
2259 +}
2260 +
2261 +
2262 +/*
2263 + * Set or clear the multicast filter for this adaptor.
2264 + */
2265 +static void rc32434_multicast_list(struct net_device *dev)
2266 +{
2267 +       /* listen to broadcasts always and to treat     */
2268 +       /*       IFF bits independantly */
2269 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2270 +       unsigned long flags;
2271 +       u32 recognise = ETHARC_ab_m;            /* always accept broadcasts */
2272 +
2273 +       if (dev->flags & IFF_PROMISC)                   /* set promiscuous mode */
2274 +               recognise |= ETHARC_pro_m;
2275 +
2276 +       if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2277 +               recognise |= ETHARC_am_m;               /* all multicast & bcast */
2278 +       else if (dev->mc_count > 0) {
2279 +               DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2280 +               recognise |= ETHARC_am_m;               /* for the time being */
2281 +       }
2282 +
2283 +       spin_lock_irqsave(&lp->lock, flags);
2284 +       rc32434_writel(recognise, &lp->eth_regs->etharc);
2285 +       spin_unlock_irqrestore(&lp->lock, flags);
2286 +}
2287 +
2288 +
2289 +static void rc32434_tx_timeout(struct net_device *dev)
2290 +{
2291 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2292 +       unsigned long flags;
2293 +
2294 +       spin_lock_irqsave(&lp->lock, flags);
2295 +       rc32434_restart(dev);
2296 +       spin_unlock_irqrestore(&lp->lock, flags);
2297 +
2298 +}
2299 +
2300 +
2301 +/*
2302 + * Initialize the RC32434 ethernet controller.
2303 + */
2304 +static int rc32434_init(struct net_device *dev)
2305 +{
2306 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2307 +       int i, j;
2308 +
2309 +       /* Disable DMA */
2310 +       rc32434_abort_tx(dev);
2311 +       rc32434_abort_rx(dev);
2312 +
2313 +       /* reset ethernet logic */
2314 +       rc32434_writel(0, &lp->eth_regs->ethintfc);
2315 +       while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2316 +               dev->trans_start = jiffies;
2317 +
2318 +       /* Enable Ethernet Interface */
2319 +       rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2320 +
2321 +#ifndef CONFIG_IDT_USE_NAPI
2322 +       tasklet_disable(lp->rx_tasklet);
2323 +#endif
2324 +       tasklet_disable(lp->tx_tasklet);
2325 +
2326 +       /* Initialize the transmit Descriptors */
2327 +       for (i = 0; i < RC32434_NUM_TDS; i++) {
2328 +               lp->td_ring[i].control = DMAD_iof_m;
2329 +               lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2330 +               lp->td_ring[i].ca = 0;
2331 +               lp->td_ring[i].link = 0;
2332 +               if (lp->tx_skb[i] != NULL) {
2333 +                       dev_kfree_skb_any(lp->tx_skb[i]);
2334 +                       lp->tx_skb[i] = NULL;
2335 +               }
2336 +       }
2337 +       lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =      lp->tx_full = lp->tx_count = 0;
2338 +       lp->    tx_chain_status = empty;
2339 +
2340 +       /*
2341 +        * Initialize the receive descriptors so that they
2342 +        * become a circular linked list, ie. let the last
2343 +        * descriptor point to the first again.
2344 +        */
2345 +       for (i=0; i<RC32434_NUM_RDS; i++) {
2346 +               struct sk_buff *skb = lp->rx_skb[i];
2347 +
2348 +               if (lp->rx_skb[i] == NULL) {
2349 +                       skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2350 +                       if (skb == NULL) {
2351 +                               ERR("No memory in the system\n");
2352 +                               for (j = 0; j < RC32434_NUM_RDS; j ++)
2353 +                                       if (lp->rx_skb[j] != NULL)
2354 +                                               dev_kfree_skb_any(lp->rx_skb[j]);
2355 +
2356 +                               return 1;
2357 +                       }
2358 +                       else {
2359 +                               skb->dev = dev;
2360 +                               skb_reserve(skb, 2);
2361 +                               lp->rx_skb[i] = skb;
2362 +                               lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2363 +
2364 +                       }
2365 +               }
2366 +               lp->rd_ring[i].control =        DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2367 +               lp->rd_ring[i].devcs = 0;
2368 +               lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2369 +               lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2370 +
2371 +       }
2372 +       /* loop back */
2373 +       lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2374 +       lp->rx_next_done   = 0;
2375 +
2376 +       lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2377 +       lp->rx_chain_head = 0;
2378 +       lp->rx_chain_tail = 0;
2379 +       lp->rx_chain_status = empty;
2380 +
2381 +       rc32434_writel(0, &lp->rx_dma_regs->dmas);
2382 +       /* Start Rx DMA */
2383 +       rc32434_start_rx(lp, &lp->rd_ring[0]);
2384 +
2385 +       /* Enable F E bit in Tx DMA */
2386 +       rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2387 +       /* Enable D H E bit in Rx DMA */
2388 +       rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2389 +
2390 +       /* Accept only packets destined for this Ethernet device address */
2391 +       rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2392 +
2393 +       /* Set all Ether station address registers to their initial values */
2394 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2395 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2396 +
2397 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2398 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2399 +
2400 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2401 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2402 +
2403 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2404 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2405 +
2406 +
2407 +       /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2408 +       rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2409 +       //ETHMAC2_flc_m         ETHMAC2_fd_m    lp->duplex_mode
2410 +
2411 +       /* Back to back inter-packet-gap */
2412 +       rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2413 +       /* Non - Back to back inter-packet-gap */
2414 +       rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2415 +
2416 +       /* Management Clock Prescaler Divisor */
2417 +       /* Clock independent setting */
2418 +       rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2419 +                      &lp->eth_regs->ethmcp);
2420 +
2421 +       /* don't transmit until fifo contains 48b */
2422 +       rc32434_writel(48, &lp->eth_regs->ethfifott);
2423 +
2424 +       rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2425 +
2426 +#ifndef CONFIG_IDT_USE_NAPI
2427 +       tasklet_enable(lp->rx_tasklet);
2428 +#endif
2429 +       tasklet_enable(lp->tx_tasklet);
2430 +
2431 +       netif_start_queue(dev);
2432 +
2433 +
2434 +       return 0;
2435 +
2436 +}
2437 +
2438 +
2439 +#ifndef MODULE
2440 +
2441 +static int __init rc32434_setup(char *options)
2442 +{
2443 +       /* no options yet */
2444 +       return 1;
2445 +}
2446 +
2447 +static int __init rc32434_setup_ethaddr0(char *options)
2448 +{
2449 +       memcpy(mac0, options, 17);
2450 +       mac0[17]= '\0';
2451 +       return 1;
2452 +}
2453 +
2454 +__setup("rc32434eth=", rc32434_setup);
2455 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2456 +
2457 +
2458 +#endif /* MODULE */
2459 +
2460 +module_init(rc32434_init_module);
2461 +module_exit(rc32434_cleanup_module);
2462 +
2463 +
2464 +
2465 +
2466 +
2467 +
2468 +
2469 +
2470 +
2471 +
2472 +
2473 +
2474 +
2475 +
2476 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.h linux-2.6.17-owrt/drivers/net/rc32434_eth.h
2477 --- linux-2.6.17/drivers/net/rc32434_eth.h      1970-01-01 01:00:00.000000000 +0100
2478 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
2479 @@ -0,0 +1,187 @@
2480 +/**************************************************************************
2481 + *
2482 + *  BRIEF MODULE DESCRIPTION
2483 + *     Definitions for IDT RC32434 on-chip ethernet controller.
2484 + *
2485 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2486 + *
2487 + *  This program is free software; you can redistribute  it and/or modify it
2488 + *  under  the terms of  the GNU General  Public License as published by the
2489 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2490 + *  option) any later version.
2491 + *
2492 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2493 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2494 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2495 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2496 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2497 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2498 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2499 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2500 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2501 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2502 + *
2503 + *  You should have received a copy of the  GNU General Public License along
2504 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2505 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2506 + *
2507 + *
2508 + **************************************************************************
2509 + * May 2004 rkt, neb
2510 + *
2511 + * Initial Release
2512 + *
2513 + * Aug 2004
2514 + *
2515 + * Added NAPI
2516 + *
2517 + **************************************************************************
2518 + */
2519 +
2520 +
2521 +#include  <asm/idt-boards/rc32434/rc32434.h>
2522 +#include  <asm/idt-boards/rc32434/rc32434_dma_v.h>
2523 +#include  <asm/idt-boards/rc32434/rc32434_eth_v.h>
2524 +
2525 +#define RC32434_DEBUG  2
2526 +//#define RC32434_PROC_DEBUG
2527 +#undef RC32434_DEBUG
2528 +
2529 +#ifdef RC32434_DEBUG
2530 +
2531 +/* use 0 for production, 1 for verification, >2 for debug */
2532 +static int rc32434_debug = RC32434_DEBUG;
2533 +#define ASSERT(expr) \
2534 +       if(!(expr)) {   \
2535 +               printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2536 +               #expr,__FILE__,__FUNCTION__,__LINE__);          }
2537 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2538 +#else
2539 +#define ASSERT(expr) do {} while (0)
2540 +#define DBG(lvl, format, arg...) do {} while (0)
2541 +#endif
2542 +
2543 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2544 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2545 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2546 +
2547 +#define ETH0_DMA_RX_IRQ        GROUP1_IRQ_BASE + 0
2548 +#define ETH0_DMA_TX_IRQ        GROUP1_IRQ_BASE + 1
2549 +#define ETH0_RX_OVR_IRQ        GROUP3_IRQ_BASE + 9
2550 +#define ETH0_TX_UND_IRQ        GROUP3_IRQ_BASE + 10
2551 +
2552 +#define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2553 +#define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2554 +
2555 +/* the following must be powers of two */
2556 +#ifdef CONFIG_IDT_USE_NAPI
2557 +#define RC32434_NUM_RDS    64                  /* number of receive descriptors */
2558 +#define RC32434_NUM_TDS    64                  /* number of transmit descriptors */
2559 +#else
2560 +#define RC32434_NUM_RDS    128                 /* number of receive descriptors */
2561 +#define RC32434_NUM_TDS    128                 /* number of transmit descriptors */
2562 +#endif
2563 +
2564 +#define RC32434_RBSIZE     1536                /* size of one resource buffer = Ether MTU */
2565 +#define RC32434_RDS_MASK   (RC32434_NUM_RDS-1)
2566 +#define RC32434_TDS_MASK   (RC32434_NUM_TDS-1)
2567 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2568 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2569 +
2570 +#define RC32434_TX_TIMEOUT HZ * 100
2571 +
2572 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2573 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2574 +
2575 +enum status    { filled,       empty};
2576 +#define IS_DMA_FINISHED(X)   (((X) & (DMAD_f_m)) != 0)
2577 +#define IS_DMA_DONE(X)   (((X) & (DMAD_d_m)) != 0)
2578 +
2579 +
2580 +/* Information that need to be kept for each board. */
2581 +struct rc32434_local {
2582 +       ETH_t  eth_regs;
2583 +       DMA_Chan_t  rx_dma_regs;
2584 +       DMA_Chan_t  tx_dma_regs;
2585 +       volatile DMAD_t   td_ring;                      /* transmit descriptor ring */
2586 +       volatile DMAD_t   rd_ring;                      /* receive descriptor ring  */
2587 +
2588 +       struct sk_buff* tx_skb[RC32434_NUM_TDS];        /* skbuffs for pkt to trans */
2589 +       struct sk_buff* rx_skb[RC32434_NUM_RDS];        /* skbuffs for pkt to trans */
2590 +
2591 +#ifndef CONFIG_IDT_USE_NAPI
2592 +       struct tasklet_struct * rx_tasklet;
2593 +#endif
2594 +       struct tasklet_struct * tx_tasklet;
2595 +
2596 +       int     rx_next_done;
2597 +       int     rx_chain_head;
2598 +       int     rx_chain_tail;
2599 +       enum status     rx_chain_status;
2600 +
2601 +       int     tx_next_done;
2602 +       int     tx_chain_head;
2603 +       int     tx_chain_tail;
2604 +       enum status     tx_chain_status;
2605 +       int tx_count;
2606 +       int     tx_full;
2607 +
2608 +       struct timer_list    mii_phy_timer;
2609 +       unsigned long duplex_mode;
2610 +
2611 +       int     rx_irq;
2612 +       int    tx_irq;
2613 +       int    ovr_irq;
2614 +       int    und_irq;
2615 +
2616 +       struct net_device_stats stats;
2617 +       spinlock_t lock;
2618 +
2619 +       /* debug /proc entry */
2620 +       struct proc_dir_entry *ps;
2621 +       int dma_halt_cnt;  int dma_run_cnt;
2622 +};
2623 +
2624 +extern unsigned int idt_cpu_freq;
2625 +
2626 +/* Index to functions, as function prototypes. */
2627 +static int rc32434_open(struct net_device *dev);
2628 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2629 +static void rc32434_mii_handler(unsigned long data);
2630 +static irqreturn_t  rc32434_und_interrupt(int irq, void *dev_id);
2631 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id);
2632 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id);
2633 +#ifdef RC32434_REVISION
2634 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id);
2635 +#endif
2636 +static int  rc32434_close(struct net_device *dev);
2637 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2638 +static void rc32434_multicast_list(struct net_device *dev);
2639 +static int  rc32434_init(struct net_device *dev);
2640 +static void rc32434_tx_timeout(struct net_device *dev);
2641 +
2642 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2643 +#ifdef CONFIG_IDT_USE_NAPI
2644 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2645 +#else
2646 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2647 +#endif
2648 +static void rc32434_cleanup_module(void);
2649 +static int rc32434_probe(int port_num);
2650 +int rc32434_init_module(void);
2651 +
2652 +
2653 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2654 +{
2655 +       if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2656 +               rc32434_writel(0x10, &ch->dmac);
2657 +
2658 +               while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2659 +                       dev->trans_start = jiffies;
2660 +
2661 +               rc32434_writel(0, &ch->dmas);
2662 +       }
2663 +
2664 +       rc32434_writel(0, &ch->dmadptr);
2665 +       rc32434_writel(0, &ch->dmandptr);
2666 +}
2667 diff -Nur linux-2.6.17/include/asm-mips/bootinfo.h linux-2.6.17-owrt/include/asm-mips/bootinfo.h
2668 --- linux-2.6.17/include/asm-mips/bootinfo.h    2006-06-18 03:49:35.000000000 +0200
2669 +++ linux-2.6.17-owrt/include/asm-mips/bootinfo.h       2006-06-18 12:44:28.000000000 +0200
2670 @@ -218,6 +218,17 @@
2671  #define MACH_GROUP_TITAN       22      /* PMC-Sierra Titan             */
2672  #define  MACH_TITAN_YOSEMITE   1       /* PMC-Sierra Yosemite          */
2673
2674 +
2675 +/*
2676 + * Valid machtype for group ARUBA
2677 + */
2678 +#define MACH_GROUP_ARUBA       23
2679 +#define  MACH_ARUBA_UNKNOWN    0
2680 +#define  MACH_ARUBA_AP60       1
2681 +#define  MACH_ARUBA_AP65       2
2682 +#define  MACH_ARUBA_AP70       3
2683 +#define  MACH_ARUBA_AP40       4
2684 +
2685  #define CL_SIZE                        COMMAND_LINE_SIZE
2686
2687  const char *get_system_type(void);
2688 diff -Nur linux-2.6.17/include/asm-mips/cpu.h linux-2.6.17-owrt/include/asm-mips/cpu.h
2689 --- linux-2.6.17/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
2690 +++ linux-2.6.17-owrt/include/asm-mips/cpu.h    2006-06-18 12:45:56.000000000 +0200
2691 @@ -54,6 +54,9 @@
2692  #define PRID_IMP_R14000                0x0f00
2693  #define PRID_IMP_R8000         0x1000
2694  #define PRID_IMP_PR4450                0x1200
2695 +#define PRID_IMP_RC32334       0x1800
2696 +#define PRID_IMP_RC32355       0x1900
2697 +#define PRID_IMP_RC32365       0x1900
2698  #define PRID_IMP_R4600         0x2000
2699  #define PRID_IMP_R4700         0x2100
2700  #define PRID_IMP_TX39          0x2200
2701 @@ -200,7 +203,8 @@
2702  #define CPU_SB1A               62
2703  #define CPU_74K                        63
2704  #define CPU_R14000             64
2705 -#define CPU_LAST               64
2706 +#define CPU_RC32300            65
2707 +#define CPU_LAST               65
2708
2709  /*
2710   * ISA Level encodings
2711 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2712 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h  1970-01-01 01:00:00.000000000 +0100
2713 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h     2006-06-18 12:44:28.000000000 +0200
2714 @@ -0,0 +1,142 @@
2715 +/**************************************************************************
2716 + *
2717 + *  BRIEF MODULE DESCRIPTION
2718 + *   RC32300 helper routines
2719 + *
2720 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2721 + *
2722 + *  This program is free software; you can redistribute  it and/or modify it
2723 + *  under  the terms of  the GNU General  Public License as published by the
2724 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2725 + *  option) any later version.
2726 + *
2727 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2728 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2729 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2730 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2731 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2732 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2733 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2734 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2735 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2736 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2737 + *
2738 + *  You should have received a copy of the  GNU General Public License along
2739 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2740 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2741 + *
2742 + *
2743 + **************************************************************************
2744 + * May 2004 P. Sadik.
2745 + *
2746 + * Initial Release
2747 + *
2748 + *
2749 + *
2750 + **************************************************************************
2751 + */
2752 +
2753 +#ifndef __IDT_RC32300_H__
2754 +#define __IDT_RC32300_H__
2755 +
2756 +#include <linux/delay.h>
2757 +#include <asm/io.h>
2758 +
2759 +
2760 +/* cpu pipeline flush */
2761 +static inline void rc32300_sync(void)
2762 +{
2763 +       __asm__ volatile ("sync");
2764 +}
2765 +
2766 +static inline void rc32300_sync_udelay(int us)
2767 +{
2768 +       __asm__ volatile ("sync");
2769 +       udelay(us);
2770 +}
2771 +
2772 +static inline void rc32300_sync_delay(int ms)
2773 +{
2774 +       __asm__ volatile ("sync");
2775 +       mdelay(ms);
2776 +}
2777 +
2778 +/*
2779 + * Macros to access internal RC32300 registers. No byte
2780 + * swapping should be done when accessing the internal
2781 + * registers.
2782 + */
2783 +
2784 +static inline u8 rc32300_readb(unsigned long pa)
2785 +{
2786 +       return *((volatile u8 *)KSEG1ADDR(pa));
2787 +}
2788 +static inline u16 rc32300_readw(unsigned long pa)
2789 +{
2790 +       return *((volatile u16 *)KSEG1ADDR(pa));
2791 +}
2792 +static inline u32 rc32300_readl(unsigned long pa)
2793 +{
2794 +       return *((volatile u32 *)KSEG1ADDR(pa));
2795 +}
2796 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2797 +{
2798 +       *((volatile u8 *)KSEG1ADDR(pa)) = val;
2799 +}
2800 +static inline void rc32300_writew(u16 val, unsigned long pa)
2801 +{
2802 +       *((volatile u16 *)KSEG1ADDR(pa)) = val;
2803 +}
2804 +static inline void rc32300_writel(u32 val, unsigned long pa)
2805 +{
2806 +       *((volatile u32 *)KSEG1ADDR(pa)) = val;
2807 +}
2808 +
2809 +
2810 +#define local_readb __raw_readb
2811 +#define local_readw __raw_readw
2812 +#define local_readl __raw_readl
2813 +
2814 +#define local_writeb __raw_writeb
2815 +#define local_writew __raw_writew
2816 +#define local_writel __raw_writel
2817 +
2818 +
2819 +/*
2820 + * C access to CLZ and CLO instructions
2821 + * (count leading zeroes/ones).
2822 + */
2823 +static inline int rc32300_clz(unsigned long val)
2824 +{
2825 +       int ret;
2826 +       __asm__ volatile (
2827 +               ".set\tnoreorder\n\t"
2828 +               ".set\tnoat\n\t"
2829 +               ".set\tmips32\n\t"
2830 +               "clz\t%0,%1\n\t"
2831 +               ".set\tmips0\n\t"
2832 +               ".set\tat\n\t"
2833 +               ".set\treorder"
2834 +               : "=r" (ret)
2835 +               : "r" (val));
2836 +
2837 +       return ret;
2838 +}
2839 +static inline int rc32300_clo(unsigned long val)
2840 +{
2841 +       int ret;
2842 +       __asm__ volatile (
2843 +                   ".set\tnoreorder\n\t"
2844 +                   ".set\tnoat\n\t"
2845 +                   ".set\tmips32\n\t"
2846 +                   "clo\t%0,%1\n\t"
2847 +                   ".set\tmips0\n\t"
2848 +                   ".set\tat\n\t"
2849 +                   ".set\treorder"
2850 +                   : "=r" (ret)
2851 +                   : "r" (val));
2852 +
2853 +       return ret;
2854 +}
2855 +
2856 +#endif  // __IDT_RC32300_H__
2857 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2858 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h  1970-01-01 01:00:00.000000000 +0100
2859 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h     2006-06-18 12:44:28.000000000 +0200
2860 @@ -0,0 +1,207 @@
2861 +/**************************************************************************
2862 + *
2863 + *  BRIEF MODULE DESCRIPTION
2864 + *   Definitions for IDT RC32334 CPU.
2865 + *
2866 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2867 + *
2868 + *  This program is free software; you can redistribute  it and/or modify it
2869 + *  under  the terms of  the GNU General  Public License as published by the
2870 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2871 + *  option) any later version.
2872 + *
2873 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2874 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2875 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2876 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2877 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2878 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2879 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2880 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2881 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2882 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2883 + *
2884 + *  You should have received a copy of the  GNU General Public License along
2885 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2886 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2887 + *
2888 + *
2889 + **************************************************************************
2890 + * May 2004 P. Sadik.
2891 + *
2892 + * Initial Release
2893 + *
2894 + *
2895 + *
2896 + **************************************************************************
2897 + */
2898 +
2899 +
2900 +#ifndef __IDT_RC32334_H__
2901 +#define __IDT_RC32334_H__
2902 +
2903 +#include <linux/delay.h>
2904 +#include <asm/io.h>
2905 +
2906 +/* Base address of internal registers */
2907 +#define RC32334_REG_BASE   0x18000000
2908 +
2909 +/* CPU and IP Bus Control */
2910 +#define CPU_PORT_WIDTH     0xffffe200 // virtual!
2911 +#define CPU_BTA            0xffffe204 // virtual!
2912 +#define CPU_BUSERR_ADDR    0xffffe208 // virtual!
2913 +#define CPU_IP_BTA         (RC32334_REG_BASE + 0x0000)
2914 +#define CPU_IP_ADDR_LATCH  (RC32334_REG_BASE + 0x0004)
2915 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2916 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2917 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2918 +#define CPU_IP_SYSID       (RC32334_REG_BASE + 0x0018)
2919 +
2920 +/* Memory Controller */
2921 +#define MEM_BASE_BANK0     (RC32334_REG_BASE + 0x0080)
2922 +#define MEM_MASK_BANK0     (RC32334_REG_BASE + 0x0084)
2923 +#define MEM_CNTL_BANK0     (RC32334_REG_BASE + 0x0200)
2924 +#define MEM_BASE_BANK1     (RC32334_REG_BASE + 0x0088)
2925 +#define MEM_MASK_BANK1     (RC32334_REG_BASE + 0x008c)
2926 +#define MEM_CNTL_BANK1     (RC32334_REG_BASE + 0x0204)
2927 +#define MEM_CNTL_BANK2     (RC32334_REG_BASE + 0x0208)
2928 +#define MEM_CNTL_BANK3     (RC32334_REG_BASE + 0x020c)
2929 +#define MEM_CNTL_BANK4     (RC32334_REG_BASE + 0x0210)
2930 +#define MEM_CNTL_BANK5     (RC32334_REG_BASE + 0x0214)
2931 +
2932 +/* PCI Controller */
2933 +#define PCI_INTR_PEND      (RC32334_REG_BASE + 0x05b0)
2934 +#define PCI_INTR_MASK      (RC32334_REG_BASE + 0x05b4)
2935 +#define PCI_INTR_CLEAR     (RC32334_REG_BASE + 0x05b8)
2936 +#define CPU2PCI_INTR_PEND  (RC32334_REG_BASE + 0x05c0)
2937 +#define CPU2PCI_INTR_MASK  (RC32334_REG_BASE + 0x05c4)
2938 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2939 +#define PCI2CPU_INTR_PEND  (RC32334_REG_BASE + 0x05d0)
2940 +#define PCI2CPU_INTR_MASK  (RC32334_REG_BASE + 0x05d4)
2941 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2942 +#define PCI_MEM1_BASE      (RC32334_REG_BASE + 0x20b0)
2943 +#define PCI_MEM2_BASE      (RC32334_REG_BASE + 0x20b8)
2944 +#define PCI_MEM3_BASE      (RC32334_REG_BASE + 0x20c0)
2945 +#define PCI_IO1_BASE       (RC32334_REG_BASE + 0x20c8)
2946 +#define PCI_ARBITRATION    (RC32334_REG_BASE + 0x20e0)
2947 +#define PCI_CPU_MEM1_BASE  (RC32334_REG_BASE + 0x20e8)
2948 +#define PCI_CPU_IO_BASE    (RC32334_REG_BASE + 0x2100)
2949 +#define PCI_CFG_CNTL      (RC32334_REG_BASE + 0x2cf8)
2950 +#define PCI_CFG_DATA      (RC32334_REG_BASE + 0x2cfc)
2951 +
2952 +/* Timers */
2953 +#define TIMER0_CNTL        (RC32334_REG_BASE + 0x0700)
2954 +#define TIMER0_COUNT       (RC32334_REG_BASE + 0x0704)
2955 +#define TIMER0_COMPARE     (RC32334_REG_BASE + 0x0708)
2956 +#define TIMER_REG_OFFSET   0x10
2957 +
2958 +/* Programmable I/O */
2959 +#define PIO_DATA0          (RC32334_REG_BASE + 0x0600)
2960 +#define PIO_DATA1          (RC32334_REG_BASE + 0x0610)
2961 +
2962 +/*
2963 + * DMA
2964 + *
2965 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2966 + *
2967 + * DMA0: 18001400
2968 + * DMA1: 18001440
2969 + * DMA2: 18001900
2970 + * DMA3: 18001940
2971 + * NB: dma number must be immediate value or variable.
2972 + *      It MUST NOT be a function since it would get called twice!
2973 + */
2974 +#define DMA_IO(n)       (((n)>1?0x500:0)+((n)&1?0x40:0))
2975 +
2976 +#define RC32300_IO_DMA(n)       (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2977 +#define RC32300_DMA_CONFREG(n)  RC32300_IO_DMA(n)
2978 +#define RC32300_DMA_BASEREG(n)  (RC32300_IO_DMA(n)+0x4)
2979 +
2980 +#define RC32300_DMA_CURRREG(n)  (RC32300_IO_DMA(n)+0x8)
2981 +#define RC32300_DMA_STATREG(n)  (RC32300_IO_DMA(n)+0x10)
2982 +#define RC32300_DMA_SRCREG(n)   (RC32300_IO_DMA(n)+0x14)
2983 +#define RC32300_DMA_DSTREG(n)   (RC32300_IO_DMA(n)+0x18)
2984 +#define RC32300_DMA_NEXTREG(n)  (RC32300_IO_DMA(n)+0x1c)
2985 +
2986 +#define RC32300_DMA_IRQ(n)  (GROUP7_IRQ_BASE+5*(n))
2987 +
2988 +/* Expansion Interrupt Controller */
2989 +#define IC_GROUP0_PEND     (RC32334_REG_BASE + 0x0500)
2990 +#define IC_GROUP0_MASK     (RC32334_REG_BASE + 0x0504)
2991 +#define IC_GROUP0_CLEAR    (RC32334_REG_BASE + 0x0508)
2992 +#define IC_GROUP_OFFSET    0x10
2993 +
2994 +#define NUM_INTR_GROUPS    15
2995 +/*
2996 + * The IRQ mapping is as follows:
2997 + *
2998 + *    IRQ         Mapped To
2999 + *    ---     -------------------
3000 + *     0      SW0  (IP0) SW0 intr
3001 + *     1      SW1  (IP1) SW1 intr
3002 + *     2      Int0 (IP2) board-specific
3003 + *     3      Int1 (IP3) board-specific
3004 + *     4      Int2 (IP4) board-specific
3005 + *     -      Int3 (IP5) not used, mapped to IRQ's 8 and up
3006 + *     6      Int4 (IP6) board-specific
3007 + *     7      Int5 (IP7) CP0 Timer
3008 + *
3009 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
3010 + * internally on the RC32334 is routed to the Expansion
3011 + * Interrupt Controller.
3012 + */
3013 +#define MIPS_CPU_TIMER_IRQ 7
3014 +
3015 +#define GROUP1_IRQ_BASE  8                       // bus error
3016 +#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 1)   // PIO active low
3017 +#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 12)  // PIO active high
3018 +#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 8)   // Timer Rollovers
3019 +#define GROUP5_IRQ_BASE  (GROUP4_IRQ_BASE + 8)   // UART0
3020 +#define GROUP6_IRQ_BASE  (GROUP5_IRQ_BASE + 3)   // UART1
3021 +#define GROUP7_IRQ_BASE  (GROUP6_IRQ_BASE + 3)   // DMA Ch0
3022 +#define GROUP8_IRQ_BASE  (GROUP7_IRQ_BASE + 5)   // DMA Ch1
3023 +#define GROUP9_IRQ_BASE  (GROUP8_IRQ_BASE + 5)   // DMA Ch2
3024 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5)   // DMA Ch3
3025 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5)  // PCI Ctlr errors
3026 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4)  // PCI Satellite Mode
3027 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3028 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4)  // SPI
3029 +
3030 +#define RC32334_NR_IRQS  (GROUP14_IRQ_BASE + 1)
3031 +
3032 +/* 16550 UARTs */
3033 +#ifdef __MIPSEB__
3034 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3035 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3036 +#else
3037 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3038 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3039 +#endif
3040 +
3041 +#define RC32300_UART0_IRQ  GROUP5_IRQ_BASE
3042 +#define RC32300_UART1_IRQ  GROUP6_IRQ_BASE
3043 +
3044 +#define IDT_CLOCK_MULT 2
3045 +
3046 +/* NVRAM */
3047 +#define NVRAM_BASE         0x12000000
3048 +#define NVRAM_ENVSIZE_OFF  4
3049 +#define NVRAM_ENVSTART_OFF 0x40
3050 +
3051 +/* LCD 4-digit display */
3052 +#define LCD_CLEAR          0x14000400
3053 +#define LCD_DIGIT0         0x1400000f
3054 +#define LCD_DIGIT1         0x14000008
3055 +#define LCD_DIGIT2         0x14000007
3056 +#define LCD_DIGIT3         0x14000003
3057 +
3058 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3059 +#define RC32334_SCC8530_IRQ  2
3060 +#define RC32334_PCI_INTA_IRQ 3
3061 +#define RC32334_PCI_INTB_IRQ 4
3062 +#define RC32334_PCI_INTC_IRQ 6
3063 +#define RC32334_PCI_INTD_IRQ 7
3064 +
3065 +#define RAM_SIZE       (32*1024*1024)
3066 +
3067 +#endif // __IDT_RC32334_H__
3068 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3069 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h      1970-01-01 01:00:00.000000000 +0100
3070 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-06-18 12:44:28.000000000 +0200
3071 @@ -0,0 +1,206 @@
3072 +/**************************************************************************
3073 + *
3074 + *  BRIEF MODULE DESCRIPTION
3075 + *     DMA controller defines on IDT RC32355
3076 + *
3077 + *  Copyright 2004 IDT Inc.
3078 + *  Author: Integrated Device Technology Inc. rischelp@idt.com
3079 + *
3080 + *
3081 + *  This program is free software; you can redistribute  it and/or modify it
3082 + *  under  the terms of  the GNU General  Public License as published by the
3083 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3084 + *  option) any later version.
3085 + *
3086 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3087 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3088 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3089 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3090 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3091 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3092 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3093 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3094 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3095 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3096 + *
3097 + *  You should have received a copy of the  GNU General Public License along
3098 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3099 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3100 + *
3101 + *
3102 + *  May 2004 rkt
3103 + *  Initial Release
3104 + *
3105 + **************************************************************************
3106 + */
3107 +
3108 +#ifndef BANYAN_DMA_H
3109 +#define BANYAN_DMA_H
3110 +#include  <asm/idt-boards/rc32300/rc32300.h>
3111 +
3112 +/*
3113 + * An image of one RC32355 dma channel registers
3114 + */
3115 +typedef struct {
3116 +       u32 dmac;
3117 +       u32 dmas;
3118 +       u32 dmasm;
3119 +       u32 dmadptr;
3120 +       u32 dmandptr;
3121 +} rc32355_dma_ch_t;
3122 +
3123 +/*
3124 + * An image of all RC32355 dma channel registers
3125 + */
3126 +typedef struct {
3127 +       rc32355_dma_ch_t ch[16];
3128 +} rc32355_dma_regs_t;
3129 +
3130 +
3131 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3132 +
3133 +
3134 +/* DMAC register layout */
3135 +
3136 +#define DMAC_RUN       0x1     /* Halts processing when cleared        */
3137 +#define DMAC_DM                0x2     /* Done Mask, ignore DMA events         */
3138 +#define DMAC_MODE_MASK 0xC     /* DMA operating mode                   */
3139 +
3140 +#define DMAC_MODE_AUTO 0x0     /* DMA Auto Request Mode                */
3141 +#define DMAC_MODE_BURST        0x4     /* DMA Burst Request Mode               */
3142 +#define DMAC_MODE_TFER 0x8     /* DMA Transfer Request Mode            */
3143 +
3144 +/* DMAS and DMASM register layout */
3145 +
3146 +#define DMAS_F         0x01    /* Finished */
3147 +#define DMAS_D         0x02    /* Done */
3148 +#define DMAS_C         0x04    /* Chain */
3149 +#define DMAS_E         0x08    /* Error */
3150 +#define DMAS_H         0x10    /* Halt */
3151 +
3152 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3153 +#define DMA_HALT_TIMEOUT 500
3154 +
3155 +
3156 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3157 +{
3158 +       int timeout=1;
3159 +
3160 +       if (local_readl(&ch->dmac) & DMAC_RUN) {
3161 +               local_writel(0, &ch->dmac);
3162 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3163 +                       if (local_readl(&ch->dmas) & DMAS_H) {
3164 +                               local_writel(0, &ch->dmas);
3165 +                               break;
3166 +                       }
3167 +               }
3168 +       }
3169 +
3170 +       return timeout ? 0 : 1;
3171 +}
3172 +
3173 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3174 +{
3175 +       local_writel(0, &ch->dmandptr);
3176 +       local_writel(dma_addr, &ch->dmadptr);
3177 +}
3178 +
3179 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3180 +{
3181 +       local_writel(dma_addr, &ch->dmandptr);
3182 +}
3183 +
3184 +
3185 +/* The following can be used to describe DMA channels 0 to 15, and the */
3186 +/* sub device's needed to select them in the DMADESC_DS_MASK field     */
3187 +
3188 +#define DMA_CHAN_ATM01         0            /* ATM interface 0,1 chan  */
3189 +
3190 +#define DMA_CHAN_ATM0IN                0            /* ATM interface 0 input   */
3191 +#define DMA_DEV_ATM0IN         0            /* ATM interface 0 input   */
3192 +
3193 +#define DMA_CHAN_ATM1IN                0            /* ATM interface 1 input   */
3194 +#define DMA_DEV_ATM1IN         1            /* ATM interface 1 input   */
3195 +
3196 +#define DMA_CHAN_ATM0OUT       0            /* ATM interface 0 output  */
3197 +#define DMA_DEV_ATM0OUT                2            /* ATM interface 0 output  */
3198 +
3199 +#define DMA_CHAN_ATM1OUT       0            /* ATM interface 1 output  */
3200 +#define DMA_DEV_ATM1OUT                3            /* ATM interface 1 output  */
3201 +
3202 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3203 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1)  /* ATM VC cache entry      */
3204 +#define DMA_DEV_ATMVCC(entry)  0
3205 +
3206 +#define DMA_CHAN_MEMTOMEM      6            /* Memory to memory DMA    */
3207 +#define DMA_DEV_MEMTOMEM       1            /* Memory to memory DMA    */
3208 +
3209 +#define DMA_CHAN_ATMFMB0       7            /* ATM Frame Mode Buffer 0 */
3210 +#define DMA_DEV_ATMFMB0                1            /* ATM Frame Mode Buffer 0 */
3211 +
3212 +#define DMA_CHAN_ATMFMB1       8            /* ATM Frame Mode Buffer 1 */
3213 +#define DMA_DEV_ATMFMB1                1            /* ATM Frame Mode Buffer 1 */
3214 +
3215 +#define DMA_CHAN_ETHERIN       9            /* Ethernet input          */
3216 +#define DMA_DEV_ETHERIN                0            /* Ethernet input          */
3217 +
3218 +#define DMA_CHAN_ETHEROUT      10           /* Ethernet output         */
3219 +#define DMA_DEV_ETHEROUT       0            /* Ethernet output         */
3220 +
3221 +#define DMA_CHAN_TDMIN         11           /* TDM Bus input           */
3222 +#define DMA_DEV_TDMIN          0            /* TDM Bus input           */
3223 +
3224 +#define DMA_CHAN_TDMOUT                12           /* TDM Bus output          */
3225 +#define DMA_DEV_TDMOUT         0            /* TDM Bus output          */
3226 +
3227 +#define DMA_CHAN_USBIN         13           /* USB input               */
3228 +#define DMA_DEV_USBIN          0            /* USB input               */
3229 +
3230 +#define DMA_CHAN_USBOUT                14           /* USB output              */
3231 +#define DMA_DEV_USBOUT         0            /* USB output              */
3232 +
3233 +#define DMA_CHAN_EXTERN                15           /* External DMA            */
3234 +#define DMA_DEV_EXTERN         0            /* External DMA            */
3235 +
3236 +/*
3237 + * An RC32355 dma descriptor in system memory
3238 + */
3239 +typedef struct {
3240 +       u32 cmdstat;    /* control and status */
3241 +       u32 curr_addr;  /* current address of data */
3242 +       u32 devcs;      /* peripheral-specific control and status */
3243 +       u32 link;       /* link to next descriptor */
3244 +} rc32355_dma_desc_t;
3245 +
3246 +/* Values for the descriptor cmdstat word */
3247 +
3248 +#define DMADESC_F              0x80000000u  /* Finished bit            */
3249 +#define DMADESC_D              0x40000000u  /* Done bit                */
3250 +#define DMADESC_T              0x20000000u  /* Terminated bit          */
3251 +#define DMADESC_IOD            0x10000000u  /* Interrupt On Done       */
3252 +#define DMADESC_IOF            0x08000000u  /* Interrupt On Finished   */
3253 +#define DMADESC_COD            0x04000000u  /* Chain On Done           */
3254 +#define DMADESC_COF            0x02000000u  /* Chain On Finished       */
3255 +
3256 +#define DMADESC_DEVCMD_MASK    0x01C00000u  /* Device Command mask     */
3257 +#define DMADESC_DEVCMD_SHIFT   22           /* Device Command shift    */
3258 +
3259 +#define DMADESC_DS_MASK                0x00300000u  /* Device Select mask      */
3260 +#define DMADESC_DS_SHIFT       20           /* Device Select shift     */
3261 +
3262 +#define DMADESC_COUNT_MASK     0x0003FFFFu  /* Byte Count mask         */
3263 +#define DMADESC_COUNT_SHIFT    0            /* Byte Count shift        */
3264 +
3265 +#define IS_DMA_FINISHED(X)   ( ( (X) & DMADESC_F ) >> 31)   /* F Bit    */
3266 +#define IS_DMA_DONE(X)       ( ( (X) & DMADESC_D ) >> 30)   /* D Bit    */
3267 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29)   /* T Bit    */
3268 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3269 +
3270 +#define DMA_DEVCMD(devcmd) \
3271 +  (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3272 +#define DMA_DS(ds)         \
3273 +  (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3274 +#define DMA_COUNT(count)   \
3275 +  ((count) & DMADESC_COUNT_MASK)
3276 +
3277 +#endif /* RC32355_DMA_H */
3278 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3279 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h      1970-01-01 01:00:00.000000000 +0100
3280 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-06-18 12:44:28.000000000 +0200
3281 @@ -0,0 +1,442 @@
3282 +/**************************************************************************
3283 + *
3284 + *  BRIEF MODULE DESCRIPTION
3285 + *     Ethernet registers on IDT RC32355
3286 + *
3287 + *  Copyright 2004 IDT Inc.
3288 + *  Author: Integrated Device Technology Inc. rischelp@idt.com
3289 + *
3290 + *
3291 + *  This program is free software; you can redistribute  it and/or modify it
3292 + *  under  the terms of  the GNU General  Public License as published by the
3293 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3294 + *  option) any later version.
3295 + *
3296 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3297 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3298 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3299 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3300 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3301 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3302 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3303 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3304 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3305 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3306 + *
3307 + *  You should have received a copy of the  GNU General Public License along
3308 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3309 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3310 + *
3311 + *
3312 + *  May 2004 rkt
3313 + *  Initial Release
3314 + *
3315 + **************************************************************************
3316 + */
3317 +
3318 +
3319 +#ifndef RC32355_ETHER_H
3320 +#define RC32355_ETHER_H
3321 +
3322 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3323 +
3324 +/*
3325 + * A partial image of the RC32355 ethernet registers
3326 + */
3327 +typedef struct {
3328 +       u32 ethintfc;
3329 +       u32 ethfifott;
3330 +       u32 etharc;
3331 +       u32 ethhash0;
3332 +       u32 ethhash1;
3333 +       u32 ethfifost;
3334 +       u32 ethfifos;
3335 +       u32 ethodeops;
3336 +       u32 ethis;
3337 +       u32 ethos;
3338 +       u32 ethmcp;
3339 +       u32 _u1;
3340 +       u32 ethid;
3341 +       u32 _u2;
3342 +       u32 _u3;
3343 +       u32 _u4;
3344 +       u32 ethod;
3345 +       u32 _u5;
3346 +       u32 _u6;
3347 +       u32 _u7;
3348 +       u32 ethodeop;
3349 +       u32 _u8[43];
3350 +       u32 ethsal0;
3351 +       u32 ethsah0;
3352 +       u32 ethsal1;
3353 +       u32 ethsah1;
3354 +       u32 ethsal2;
3355 +       u32 ethsah2;
3356 +       u32 ethsal3;
3357 +       u32 ethsah3;
3358 +       u32 ethrbc;
3359 +       u32 ethrpc;
3360 +       u32 ethrupc;
3361 +       u32 ethrfc;
3362 +       u32 ethtbc;
3363 +       u32 ethgpf;
3364 +       u32 _u9[50];
3365 +       u32 ethmac1;
3366 +       u32 ethmac2;
3367 +       u32 ethipgt;
3368 +       u32 ethipgr;
3369 +       u32 ethclrt;
3370 +       u32 ethmaxf;
3371 +       u32 _u10;
3372 +       u32 ethmtest;
3373 +       u32 miimcfg;
3374 +       u32 miimcmd;
3375 +       u32 miimaddr;
3376 +       u32 miimwtd;
3377 +       u32 miimrdd;
3378 +       u32 miimind;
3379 +       u32 _u11;
3380 +       u32 _u12;
3381 +       u32 ethcfsa0;
3382 +       u32 ethcfsa1;
3383 +       u32 ethcfsa2;
3384 +} rc32355_eth_regs_t;
3385 +
3386 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3387 +
3388 +#define ETH_INTFC   (RC32355_ETH_BASE + 0x000) /* INTerFace Control  */
3389 +#define ETH_FIFOTT  (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold  */
3390 +#define ETH_ARC     (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl  */
3391 +#define ETH_HASH0   (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3392 +#define ETH_HASH1   (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3393 +#define ETH_FIFOST  (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3394 +#define ETH_FIFOS   (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3395 +#define ETH_ODEOPS  (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3396 +#define ETH_IS      (RC32355_ETH_BASE + 0x020) /* Input Status */
3397 +#define ETH_OS      (RC32355_ETH_BASE + 0x024) /* Output Status  */
3398 +#define ETH_MCP     (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3399 +#define ETH_ID      (RC32355_ETH_BASE + 0x030) /* Input Data register */
3400 +#define ETH_OD      (RC32355_ETH_BASE + 0x040) /* Output Data register */
3401 +#define ETH_ODEOP   (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3402 +
3403 +/* for n in { 0, 1, 2, 3 } */
3404 +#define ETH_SAL(n)  (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3405 +#define ETH_SAH(n)  (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3406 +
3407 +#define ETH_RBC     (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3408 +#define ETH_RPC     (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3409 +#define ETH_RUPC    (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3410 +#define ETH_RFC     (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3411 +#define ETH_TBC     (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3412 +#define ETH_GPF     (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3413 +#define ETH_MAC1    (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3414 +#define ETH_MAC2    (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3415 +#define ETH_IPGT    (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3416 +#define ETH_IPGR    (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3417 +#define ETH_CLRT    (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3418 +#define ETH_MAXF    (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3419 +#define ETH_MTEST   (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3420 +
3421 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3422 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command  */
3423 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3424 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3425 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3426 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3427 +
3428 +/* for n in { 0, 1, 2 } */
3429 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4))  /* Station Addr */
3430 +
3431 +
3432 +/*
3433 + * Register Interpretations follow
3434 + */
3435 +
3436 +/******************************************************************************
3437 + * ETHINTFC register
3438 + *****************************************************************************/
3439 +
3440 +#define ETHERINTFC_EN            (1<<0)
3441 +#define ETHERINTFC_ITS           (1<<1)
3442 +#define ETHERINTFC_RES           (1<<2)
3443 +#define ETHERINTFC_RIP           (1<<2)
3444 +#define ETHERINTFC_JAM           (1<<3)
3445 +
3446 +/******************************************************************************
3447 + * ETHFIFOTT register
3448 + *****************************************************************************/
3449 +
3450 +#define ETHERFIFOTT_TTH(v)      (((v)&0x3f)<<0)
3451 +
3452 +/******************************************************************************
3453 + * ETHARC register
3454 + *****************************************************************************/
3455 +
3456 +#define ETHERARC_PRO             (1<<0)
3457 +#define ETHERARC_AM              (1<<1)
3458 +#define ETHERARC_AFM             (1<<2)
3459 +#define ETHERARC_AB              (1<<3)
3460 +
3461 +/******************************************************************************
3462 + * ETHHASH registers
3463 + *****************************************************************************/
3464 +
3465 +#define ETHERHASH0(v)            (((v)&0xffff)<<0)
3466 +#define ETHERHASH1(v)            (((v)&0xffff)<<0)
3467 +
3468 +/******************************************************************************
3469 + * ETHSA registers
3470 + *****************************************************************************/
3471 +
3472 +#define ETHERSAL0(v)             (((v)&0xffff)<<0)
3473 +#define ETHERSAL1(v)             (((v)&0xffff)<<0)
3474 +#define ETHERSAL2(v)             (((v)&0xffff)<<0)
3475 +#define ETHERSAL3(v)             (((v)&0xffff)<<0)
3476 +#define ETHERSAH0(v)             (((v)&0xff)<<0)
3477 +#define ETHERSAH1(v)             (((v)&0xff)<<0)
3478 +#define ETHERSAH2(v)             (((v)&0xff)<<0)
3479 +#define ETHERSAH3(v)             (((v)&0xff)<<0)
3480 +
3481 +/******************************************************************************
3482 + * ETHFIFOST register
3483 + *****************************************************************************/
3484 +
3485 +#define ETHERFIFOST_IRTH(v)      (((v)&0x3f)<<0)
3486 +#define ETHERFIFOST_ORTH(v)      (((v)&0x3f)<<16)
3487 +
3488 +/******************************************************************************
3489 + * ETHFIFOS register
3490 + *****************************************************************************/
3491 +
3492 +#define ETHERFIFOS_IR            (1<<0)
3493 +#define ETHERFIFOS_OR            (1<<1)
3494 +#define ETHERFIFOS_OVR           (1<<2)
3495 +#define ETHERFIFOS_UND           (1<<3)
3496 +
3497 +/******************************************************************************
3498 + * DATA registers
3499 + *****************************************************************************/
3500 +
3501 +#define ETHERID(v)               (((v)&0xffff)<<0)
3502 +#define ETHEROD(v)               (((v)&0xffff)<<0)
3503 +
3504 +/******************************************************************************
3505 + * ETHODEOPS register
3506 + *****************************************************************************/
3507 +
3508 +#define ETHERODEOPS_SIZE(v)      (((v)&0x3)<<0)
3509 +
3510 +/******************************************************************************
3511 + * ETHODEOP register
3512 + *****************************************************************************/
3513 +
3514 +#define ETHERODEOP(v)            (((v)&0xffff)<<0)
3515 +
3516 +/******************************************************************************
3517 + * ETHIS register
3518 + *****************************************************************************/
3519 +
3520 +#define ETHERIS_EOP              (1<<0)
3521 +#define ETHERIS_ROK              (1<<2)
3522 +#define ETHERIS_FM               (1<<3)
3523 +#define ETHERIS_MP               (1<<4)
3524 +#define ETHERIS_BP               (1<<5)
3525 +#define ETHERIS_VLT              (1<<6)
3526 +#define ETHERIS_CF               (1<<7)
3527 +#define ETHERIS_OVR              (1<<8)
3528 +#define ETHERIS_CRC              (1<<9)
3529 +#define ETHERIS_CV               (1<<10)
3530 +#define ETHERIS_DB               (1<<11)
3531 +#define ETHERIS_LE               (1<<12)
3532 +#define ETHERIS_LOR              (1<<13)
3533 +#define ETHERIS_SIZE(v)          (((v)&0x3)<<14)
3534 +#define ETHERIS_LENGTH(v)        (((v)&0xff)<<16)
3535 +
3536 +/******************************************************************************
3537 + * ETHOS register
3538 + *****************************************************************************/
3539 +
3540 +#define ETHEROS_T                (1<<0)
3541 +#define ETHEROS_TOK              (1<<6)
3542 +#define ETHEROS_MP               (1<<7)
3543 +#define ETHEROS_BP               (1<<8)
3544 +#define ETHEROS_UND              (1<<9)
3545 +#define ETHEROS_OF               (1<<10)
3546 +#define ETHEROS_ED               (1<<11)
3547 +#define ETHEROS_EC               (1<<12)
3548 +#define ETHEROS_LC               (1<<13)
3549 +#define ETHEROS_TD               (1<<14)
3550 +#define ETHEROS_CRC              (1<<15)
3551 +#define ETHEROS_LE               (1<<16)
3552 +#define ETHEROS_CC(v)            (((v)&0xf)<<17)
3553 +#define ETHEROS_PFD              (1<<21)
3554 +
3555 +/******************************************************************************
3556 + * Statistics registers
3557 + *****************************************************************************/
3558 +
3559 +#define ETHERRBC(v)              (((v)&0xffff)<<0)
3560 +#define ETHERRPC(v)              (((v)&0xffff)<<0)
3561 +#define ETHERRUPC(v)             (((v)&0xffff)<<0)
3562 +#define ETHERRFC(v)              (((v)&0xffff)<<0)
3563 +#define ETHERTBC(v)              (((v)&0xffff)<<0)
3564 +
3565 +/******************************************************************************
3566 + * ETHGPF register
3567 + *****************************************************************************/
3568 +
3569 +#define ETHERGPF_PTV(v)          (((v)&0xff)<<0)
3570 +
3571 +/******************************************************************************
3572 + * MAC registers
3573 + *****************************************************************************/
3574 +//ETHMAC1
3575 +#define ETHERMAC1_RE             (1<<0)
3576 +#define ETHERMAC1_PAF            (1<<1)
3577 +#define ETHERMAC1_RFC            (1<<2)
3578 +#define ETHERMAC1_TFC            (1<<3)
3579 +#define ETHERMAC1_LB             (1<<4)
3580 +#define ETHERMAC1_MR             (1<<15)
3581 +
3582 +//ETHMAC2
3583 +#define ETHERMAC2_FD             (1<<0)
3584 +#define ETHERMAC2_FLC            (1<<1)
3585 +#define ETHERMAC2_HFE            (1<<2)
3586 +#define ETHERMAC2_DC             (1<<3)
3587 +#define ETHERMAC2_CEN            (1<<4)
3588 +#define ETHERMAC2_PE             (1<<5)
3589 +#define ETHERMAC2_VPE            (1<<6)
3590 +#define ETHERMAC2_APE            (1<<7)
3591 +#define ETHERMAC2_PPE            (1<<8)
3592 +#define ETHERMAC2_LPE            (1<<9)
3593 +#define ETHERMAC2_NB             (1<<12)
3594 +#define ETHERMAC2_BP             (1<<13)
3595 +#define ETHERMAC2_ED             (1<<14)
3596 +
3597 +//ETHIPGT
3598 +#define ETHERIPGT(v)             (((v)&0x3f)<<0)
3599 +
3600 +//ETHIPGR
3601 +#define ETHERIPGR_IPGR1(v)       (((v)&0x3f)<<0)
3602 +#define ETHERIPGR_IPGR2(v)       (((v)&0x3f)<<8)
3603 +
3604 +//ETHCLRT
3605 +#define ETHERCLRT_MAXRET(v)      (((v)&0x3f)<<0)
3606 +#define ETHERCLRT_COLWIN(v)      (((v)&0x3f)<<8)
3607 +
3608 +//ETHMAXF
3609 +#define ETHERMAXF(v)             (((v)&0x3f)<<0)
3610 +
3611 +//ETHMTEST
3612 +#define ETHERMTEST_TB            (1<<2)
3613 +
3614 +//ETHMCP
3615 +#define ETHERMCP_DIV(v)          (((v)&0xff)<<0)
3616 +
3617 +//MIIMCFG
3618 +#define ETHERMIIMCFG_CS(v)          (((v)&0x3)<<2)
3619 +#define ETHERMIIMCFG_R              (1<<15)
3620 +
3621 +//MIIMCMD
3622 +#define ETHERMIIMCMD_RD             (1<<0)
3623 +#define ETHERMIIMCMD_SCN            (1<<1)
3624 +
3625 +//MIIMADDR
3626 +#define ETHERMIIMADDR_REGADDR(v)    (((v)&0x1f)<<0)
3627 +#define ETHERMIIMADDR_PHYADDR(v)    (((v)&0x1f)<<8)
3628 +
3629 +//MIIMWTD
3630 +#define ETHERMIIMWTD(v)             (((v)&0xff)<<0)
3631 +
3632 +//MIIMRDD
3633 +#define ETHERMIIMRDD(v)             (((v)&0xff)<<0)
3634 +
3635 +//MIIMIND
3636 +#define ETHERMIIMIND_BSY            (1<<0)
3637 +#define ETHERMIIMIND_SCN            (1<<1)
3638 +#define ETHERMIIMIND_NV             (1<<2)
3639 +
3640 +//DMA DEVCS IN
3641 +#define ETHERDMA_IN_LENGTH(v)  (((v)&0xffff)<<16)
3642 +#define ETHERDMA_IN_CES                (1<<14)
3643 +#define ETHERDMA_IN_LOR                (1<<13)
3644 +#define ETHERDMA_IN_LE         (1<<12)
3645 +#define ETHERDMA_IN_DB         (1<<11)
3646 +#define ETHERDMA_IN_CV         (1<<10)
3647 +#define ETHERDMA_IN_CRC                (1<<9)
3648 +#define ETHERDMA_IN_OVR                (1<<8)
3649 +#define ETHERDMA_IN_CF         (1<<7)
3650 +#define ETHERDMA_IN_VLT                (1<<6)
3651 +#define ETHERDMA_IN_BP         (1<<5)
3652 +#define ETHERDMA_IN_MP         (1<<4)
3653 +#define ETHERDMA_IN_FM         (1<<3)
3654 +#define ETHERDMA_IN_ROK                (1<<2)
3655 +#define ETHERDMA_IN_LD         (1<<1)
3656 +#define ETHERDMA_IN_FD         (1<<0)
3657 +
3658 +//DMA DEVCS OUT
3659 +#define ETHERDMA_OUT_CC(v)     (((v)&0xf)<<17)
3660 +#define ETHERDMA_OUT_CNT         0x001e0000
3661 +#define ETHERDMA_OUT_SHFT       17
3662 +#define ETHERDMA_OUT_LE                (1<<16)
3663 +
3664 +#define ETHERDMA_OUT_CRC       (1<<15)
3665 +#define ETHERDMA_OUT_TD                (1<<14)
3666 +#define ETHERDMA_OUT_LC                (1<<13)
3667 +#define ETHERDMA_OUT_EC                (1<<12)
3668 +#define ETHERDMA_OUT_ED                (1<<11)
3669 +#define ETHERDMA_OUT_OF                (1<<10)
3670 +#define ETHERDMA_OUT_UND       (1<<9)
3671 +#define ETHERDMA_OUT_BP                (1<<8)
3672 +#define ETHERDMA_OUT_MP                (1<<7)
3673 +#define ETHERDMA_OUT_TOK       (1<<6)
3674 +#define ETHERDMA_OUT_HEN       (1<<5)
3675 +#define ETHERDMA_OUT_CEN       (1<<4)
3676 +#define ETHERDMA_OUT_PEN       (1<<3)
3677 +#define ETHERDMA_OUT_OEN       (1<<2)
3678 +#define ETHERDMA_OUT_LD                (1<<1)
3679 +#define ETHERDMA_OUT_FD                (1<<0)
3680 +
3681 +#define RCV_ERRS \
3682 +  (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3683 +#define TX_ERRS  \
3684 +  (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3685 +   ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3686 +
3687 +#define IS_RCV_ROK(X)        (((X) & (1<<2)) >> 2)       /* Receive Okay     */
3688 +#define IS_RCV_FM(X)         (((X) & (1<<3)) >> 3)       /* Is Filter Match  */
3689 +#define IS_RCV_MP(X)         (((X) & (1<<4)) >> 4)       /* Is it MP         */
3690 +#define IS_RCV_BP(X)         (((X) & (1<<5)) >> 5)       /* Is it BP         */
3691 +#define IS_RCV_VLT(X)        (((X) & (1<<6)) >> 6)       /* VLAN Tag Detect  */
3692 +#define IS_RCV_CF(X)         (((X) & (1<<7)) >> 7)       /* Control Frame    */
3693 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<8)) >> 8)       /* Receive Overflow */
3694 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<9)) >> 9)       /* CRC Error        */
3695 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<10))>>10)       /* Code Violation   */
3696 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<11))>>11)       /* Dribble Bits     */
3697 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<12))>>12)       /* Length error     */
3698 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<13))>>13)       /* Length Out of
3699 +                                                            Range            */
3700 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<14))>>14)       /* Preamble error   */
3701 +#define RCVPKT_LENGTH(X)     (((X) & 0xFFFF0000)>>16)    /* Length of the
3702 +                                                            received packet  */
3703 +
3704 +#define IS_TX_TOK(X)         (((X) & (1<<6) ) >> 6 )     /* Transmit Okay    */
3705 +#define IS_TX_MP(X)          (((X) & (1<<7) ) >> 7 )     /* Multicast        */
3706 +
3707 +#define IS_TX_BP(X)          (((X) & (1<<8) ) >> 8 )     /* Broadcast        */
3708 +#define IS_TX_UND_ERR(X)     (((X) & (1<<9) ) >> 9 )     /* Transmit FIFO
3709 +                                                            Underflow        */
3710 +#define IS_TX_OF_ERR(X)      (((X) & (1<<10)) >>10 )     /* Oversized frame  */
3711 +#define IS_TX_ED_ERR(X)      (((X) & (1<<11)) >>11 )     /* Excessive
3712 +                                                           deferral        */
3713 +#define IS_TX_EC_ERR(X)      (((X) & (1<<12)) >>12 )     /* Excessive
3714 +                                                           collisions      */
3715 +#define IS_TX_LC_ERR(X)      (((X) & (1<<13)) >>13 )     /* Late Collision   */
3716 +#define IS_TX_TD_ERR(X)      (((X) & (1<<14)) >>14 )     /* Transmit deferred*/
3717 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<15)) >>15 )     /* CRC Error        */
3718 +#define IS_TX_LE_ERR(X)      (((X) & (1<<16)) >>16 )     /* Length Error     */
3719 +
3720 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17)  /* Collision Count  */
3721 +
3722 +#endif /* RC32355_ETHER_H */
3723 +
3724 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3725 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h  1970-01-01 01:00:00.000000000 +0100
3726 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h     2006-06-18 12:44:28.000000000 +0200
3727 @@ -0,0 +1,177 @@
3728 +/**************************************************************************
3729 + *
3730 + *  BRIEF MODULE DESCRIPTION
3731 + *     Definitions for IDT RC32355 CPU.
3732 + *
3733 + *  Copyright 2004 IDT Inc.
3734 + *  Author: Integrated Device Technology Inc. rischelp@idt.com
3735 + *
3736 + *
3737 + *  This program is free software; you can redistribute  it and/or modify it
3738 + *  under  the terms of  the GNU General  Public License as published by the
3739 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3740 + *  option) any later version.
3741 + *
3742 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3743 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3744 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3745 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3746 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3747 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3748 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3749 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3750 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3751 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3752 + *
3753 + *  You should have received a copy of the  GNU General Public License along
3754 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3755 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3756 + *
3757 + *
3758 + *  May 2004 rkt
3759 + *  Initial Release
3760 + *
3761 + **************************************************************************
3762 + */
3763 +
3764 +
3765 +#ifndef _RC32355_H_
3766 +#define _RC32355_H_
3767 +
3768 +#include <linux/delay.h>
3769 +#include <asm/io.h>
3770 +
3771 +/* Base address of internal registers */
3772 +#define RC32355_REG_BASE   0x18000000
3773 +
3774 +/* System ID Registers */
3775 +#define CPU_SYSID          (RC32355_REG_BASE + 0x00018)
3776 +#define CPU_BTADDR         (RC32355_REG_BASE + 0x0001c)
3777 +#define CPU_REV            (RC32355_REG_BASE + 0x0002c)
3778 +
3779 +/* Reset Controller */
3780 +#define RESET_CNTL         (RC32355_REG_BASE + 0x08000)
3781 +
3782 +/* Device Controller */
3783 +#define DEV0_BASE          (RC32355_REG_BASE + 0x10000)
3784 +#define DEV0_MASK          (RC32355_REG_BASE + 0x10004)
3785 +#define DEV0_CNTL          (RC32355_REG_BASE + 0x10008)
3786 +#define DEV0_TIMING        (RC32355_REG_BASE + 0x1000c)
3787 +#define DEV_REG_OFFSET     0x10
3788 +
3789 +/* SDRAM Controller */
3790 +#define SDRAM0_BASE        (RC32355_REG_BASE + 0x18000)
3791 +#define SDRAM0_MASK        (RC32355_REG_BASE + 0x18004)
3792 +#define SDRAM1_BASE        (RC32355_REG_BASE + 0x18008)
3793 +#define SDRAM1_MASK        (RC32355_REG_BASE + 0x1800c)
3794 +#define SDRAM_CNTL         (RC32355_REG_BASE + 0x18010)
3795 +
3796 +/* Bus Arbiter */
3797 +#define BUS_ARB_CNTL0      (RC32355_REG_BASE + 0x20000)
3798 +#define BUS_ARB_CNTL1      (RC32355_REG_BASE + 0x20004)
3799 +
3800 +/* Counters/Timers */
3801 +#define TIMER0_COUNT       (RC32355_REG_BASE + 0x28000)
3802 +#define TIMER0_COMPARE     (RC32355_REG_BASE + 0x28004)
3803 +#define TIMER0_CNTL        (RC32355_REG_BASE + 0x28008)
3804 +#define TIMER_REG_OFFSET   0x0C
3805 +
3806 +/* System Integrity */
3807 +
3808 +/* Interrupt Controller */
3809 +#define IC_GROUP0_PEND     (RC32355_REG_BASE + 0x30000)
3810 +#define IC_GROUP0_MASK     (RC32355_REG_BASE + 0x30004)
3811 +#define IC_GROUP_OFFSET    0x08
3812 +
3813 +#define NUM_INTR_GROUPS    5
3814 +/*
3815 + * The IRQ mapping is as follows:
3816 + *
3817 + *    IRQ         Mapped To
3818 + *    ---     -------------------
3819 + *     0      SW0  (IP0) SW0 intr
3820 + *     1      SW1  (IP1) SW1 intr
3821 + *     -      Int0 (IP2) mapped to GROUP0_IRQ_BASE
3822 + *     -      Int1 (IP3) mapped to GROUP1_IRQ_BASE
3823 + *     -      Int2 (IP4) mapped to GROUP2_IRQ_BASE
3824 + *     -      Int3 (IP5) mapped to GROUP3_IRQ_BASE
3825 + *     -      Int4 (IP6) mapped to GROUP4_IRQ_BASE
3826 + *     7      Int5 (IP7) CP0 Timer
3827 + *
3828 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
3829 + * internally on the RC32355 is routed to the Expansion
3830 + * Interrupt Controller.
3831 + */
3832 +#define MIPS_CPU_TIMER_IRQ 7
3833 +
3834 +#define GROUP0_IRQ_BASE  8                      // Counter/Timers, UCW
3835 +#define GROUP1_IRQ_BASE  (GROUP0_IRQ_BASE + 32) // DMA
3836 +#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 32) // ATM
3837 +#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
3838 +#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 32) // GPIO
3839 +
3840 +#define RC32355_NR_IRQS  (GROUP4_IRQ_BASE + 32)
3841 +
3842 +/* DMA - see rc32355_dma.h for full list of registers */
3843 +
3844 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
3845 +#define DMA_CHAN_OFFSET  0x14
3846 +
3847 +/* GPIO Controller */
3848 +
3849 +/* TDM Bus */
3850 +
3851 +/* 16550 UARTs */
3852 +#ifdef __MIPSEB__
3853 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
3854 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
3855 +#else
3856 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
3857 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
3858 +#endif
3859 +
3860 +#define RC32300_UART0_IRQ  (GROUP3_IRQ_BASE + 14)
3861 +#define RC32300_UART1_IRQ  (GROUP3_IRQ_BASE + 17)
3862 +
3863 +/* ATM */
3864 +
3865 +/* Ethernet - see rc32355_eth.h for full list of registers */
3866 +
3867 +#define RC32355_ETH_BASE   (RC32355_REG_BASE + 0x60000)
3868 +
3869 +
3870 +#define IDT_CLOCK_MULT 2
3871 +
3872 +/* Memory map of 79EB355 board */
3873 +
3874 +/* DRAM */
3875 +#define RAM_BASE        0x00000000
3876 +#define RAM_SIZE       (32*1024*1024)
3877 +
3878 +/* SRAM (device 1) */
3879 +#define SRAM_BASE       0x02000000
3880 +#define SRAM_SIZE       0x00100000
3881 +
3882 +/* FLASH (device 2) */
3883 +#define FLASH_BASE      0x0C000000
3884 +#define FLASH_SIZE      0x00C00000
3885 +
3886 +/* ATM PHY (device 4) */
3887 +#define ATM_PHY_BASE    0x14000000
3888 +
3889 +/* TDM switch (device 3) */
3890 +#define TDM_BASE        0x1A000000
3891 +
3892 +/* LCD panel (device 3) */
3893 +#define LCD_BASE        0x1A002000
3894 +
3895 +/* RTC (DS1511W) (device 3) */
3896 +#define RTC_BASE        0x1A004000
3897 +
3898 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
3899 +#define NVRAM_ADDR      RTC_BASE + 0x10
3900 +#define NVRAM_DATA      RTC_BASE + 0x13
3901 +#define NVRAM_ENVSIZE_OFF  4
3902 +#define NVRAM_ENVSTART_OFF 32
3903 +
3904 +#endif /* _RC32355_H_ */
3905 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
3906 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h      1970-01-01 01:00:00.000000000 +0100
3907 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-06-18 12:44:28.000000000 +0200
3908 @@ -0,0 +1,226 @@
3909 +/**************************************************************************
3910 + *
3911 + *  BRIEF MODULE DESCRIPTION
3912 + *   RC32365/336 DMA hardware abstraction.
3913 + *
3914 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
3915 + *
3916 + *  This program is free software; you can redistribute  it and/or modify it
3917 + *  under  the terms of  the GNU General  Public License as published by the
3918 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3919 + *  option) any later version.
3920 + *
3921 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3922 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3923 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3924 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3925 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3926 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3927 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3928 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3929 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3930 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3931 + *
3932 + *  You should have received a copy of the  GNU General Public License along
3933 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3934 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3935 + *
3936 + *
3937 + **************************************************************************
3938 + * May 2004 P. Sadik.
3939 + *
3940 + * Initial Release
3941 + *
3942 + *
3943 + *
3944 + **************************************************************************
3945 + */
3946 +
3947 +#ifndef __IDT_RC32365_DMA_H__
3948 +#define __IDT_RC32365_DMA_H__
3949 +
3950 +enum
3951 +{
3952 +       DMA0_PhysicalAddress    = 0x18038000,
3953 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
3954 +
3955 +       DMA0_VirtualAddress     = 0xb8038000,
3956 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
3957 +} ;
3958 +
3959 +/*
3960 + * DMA descriptor (in physical memory).
3961 + */
3962 +
3963 +typedef struct DMAD_s
3964 +{
3965 +       u32                     control ;       // Control. use DMAD_*
3966 +       u32                     ca ;            // Current Address.
3967 +       u32                     devcs ;         // Device control and status.
3968 +       u32                     link ;          // Next descriptor in chain.
3969 +} volatile *DMAD_t ;
3970 +
3971 +enum
3972 +{
3973 +       DMAD_size               = sizeof (struct DMAD_s),
3974 +       DMAD_count_b            = 0,            // in DMAD_t -> control
3975 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
3976 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
3977 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
3978 +       DMAD_ds_extToMem0_v     = 0,
3979 +       DMAD_ds_memToExt0_v     = 1,
3980 +       DMAD_ds_extToMem1_v     = 0,
3981 +       DMAD_ds_memToExt1_v     = 1,
3982 +       DMAD_ds_ethRcv0_v       = 0,
3983 +       DMAD_ds_ethXmt0_v       = 0,
3984 +       DMAD_ds_ethRcv1_v       = 0,
3985 +       DMAD_ds_ethXmt2_v       = 0,
3986 +       DMAD_ds_memToFifo_v     = 0,
3987 +       DMAD_ds_fifoToMem_v     = 0,
3988 +       DMAD_ds_rng_de_v           = 1,//randomNumberGenerator on LC/DE
3989 +       DMAD_ds_pciToMem_v      = 0,
3990 +       DMAD_ds_memToPci_v      = 0,
3991 +       DMAD_ds_securityInput_v = 0,
3992 +       DMAD_ds_securityOutput_v = 0,
3993 +       DMAD_ds_rng_se_v        = 0,//randomNumberGenerator on SE
3994 +
3995 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
3996 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
3997 +       DMAD_devcmd_byte_v      = 0,    //memory-to-memory
3998 +       DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
3999 +       DMAD_devcmd_word_v      = 2,    //memory-to-memory
4000 +       DMAD_devcmd_2words_v    = 3,    //memory-to-memory
4001 +       DMAD_devcmd_4words_v    = 4,    //memory-to-memory
4002 +       DMAD_devcmd_6words_v    = 5,    //memory-to-memory
4003 +       DMAD_devcmd_8words_v    = 6,    //memory-to-memory
4004 +       DMAD_devcmd_16words_v   = 7,    //memory-to-memory
4005 +       DMAD_cof_b              = 25,           // chain on finished
4006 +       DMAD_cof_m              = 0x02000000,   //
4007 +       DMAD_cod_b              = 26,           // chain on done
4008 +       DMAD_cod_m              = 0x04000000,   //
4009 +       DMAD_iof_b              = 27,           // interrupt on finished
4010 +       DMAD_iof_m              = 0x08000000,   //
4011 +       DMAD_iod_b              = 28,           // interrupt on done
4012 +       DMAD_iod_m              = 0x10000000,   //
4013 +       DMAD_t_b                = 29,           // terminated
4014 +       DMAD_t_m                = 0x20000000,   //
4015 +       DMAD_d_b                = 30,           // done
4016 +       DMAD_d_m                = 0x40000000,   //
4017 +       DMAD_f_b                = 31,           // finished
4018 +       DMAD_f_m                = 0x80000000,   //
4019 +} ;
4020 +
4021 +/*
4022 + * DMA register (within Internal Register Map).
4023 + */
4024 +
4025 +struct DMA_Chan_s
4026 +{
4027 +       u32             dmac ;          // Control.
4028 +       u32             dmas ;          // Status.
4029 +       u32             dmasm ;         // Mask.
4030 +       u32             dmadptr ;       // Descriptor pointer.
4031 +       u32             dmandptr ;      // Next descriptor pointer.
4032 +};
4033 +
4034 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
4035 +
4036 +//DMA_Channels   use DMACH_count instead
4037 +
4038 +enum
4039 +{
4040 +       DMAC_run_b      = 0,            //
4041 +       DMAC_run_m      = 0x00000001,   //
4042 +       DMAC_dm_b       = 1,            // done mask
4043 +       DMAC_dm_m       = 0x00000002,   //
4044 +       DMAC_mode_b     = 2,            //
4045 +       DMAC_mode_m     = 0x0000000c,   //
4046 +       DMAC_mode_auto_v        = 0,
4047 +       DMAC_mode_burst_v       = 1,
4048 +       DMAC_mode_transfer_v    = 2, //usually used
4049 +       DMAC_mode_reserved_v    = 3,
4050 +       DMAC_a_b        = 4,            //
4051 +       DMAC_a_m        = 0x00000010,   //
4052 +
4053 +       DMAS_f_b        = 0,            // finished (sticky)
4054 +       DMAS_f_m        = 0x00000001,   //
4055 +       DMAS_d_b        = 1,            // done (sticky)
4056 +       DMAS_d_m        = 0x00000002,   //
4057 +       DMAS_c_b        = 2,            // chain (sticky)
4058 +       DMAS_c_m        = 0x00000004,   //
4059 +       DMAS_e_b        = 3,            // error (sticky)
4060 +       DMAS_e_m        = 0x00000008,   //
4061 +       DMAS_h_b        = 4,            // halt (sticky)
4062 +       DMAS_h_m        = 0x00000010,   //
4063 +
4064 +       DMASM_f_b       = 0,            // finished (1=mask)
4065 +       DMASM_f_m       = 0x00000001,   //
4066 +       DMASM_d_b       = 1,            // done (1=mask)
4067 +       DMASM_d_m       = 0x00000002,   //
4068 +       DMASM_c_b       = 2,            // chain (1=mask)
4069 +       DMASM_c_m       = 0x00000004,   //
4070 +       DMASM_e_b       = 3,            // error (1=mask)
4071 +       DMASM_e_m       = 0x00000008,   //
4072 +       DMASM_h_b       = 4,            // halt (1=mask)
4073 +       DMASM_h_m       = 0x00000010,   //
4074 +} ;
4075 +
4076 +/*
4077 + * DMA channel definitions
4078 + */
4079 +
4080 +enum
4081 +{
4082 +       DMACH_ethRcv0 = 0,
4083 +       DMACH_ethXmt0 = 1,
4084 +       DMACH_ethRcv1 = 2,
4085 +       DMACH_ethXmt2 = 3,
4086 +       DMACH_pciToMem = 4,
4087 +       DMACH_memToPci = 5,
4088 +       DMACH_securityInput = 6,
4089 +       DMACH_securityOutput = 7,
4090 +       DMACH_rng = 8,
4091 +
4092 +       DMACH_count //must be last
4093 +};
4094 +
4095 +
4096 +typedef struct DMAC_s
4097 +{
4098 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
4099 +} volatile *DMA_t ;
4100 +
4101 +
4102 +/*
4103 + * External DMA parameters
4104 +*/
4105 +
4106 +enum
4107 +{
4108 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
4109 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
4110 +       DMADEVCMD_ts_byte_v     = 0,
4111 +       DMADEVCMD_ts_halfword_v = 1,
4112 +       DMADEVCMD_ts_word_v     = 2,
4113 +       DMADEVCMD_ts_2word_v    = 3,
4114 +       DMADEVCMD_ts_4word_v    = 4,
4115 +       DMADEVCMD_ts_6word_v    = 5,
4116 +       DMADEVCMD_ts_8word_v    = 6,
4117 +       DMADEVCMD_ts_16word_v   = 7
4118 +};
4119 +
4120 +
4121 +#if 1  // aws - Compatibility.
4122 +#      define  EXTDMA_ts_b             DMADEVCMD_ts_b
4123 +#      define  EXTDMA_ts_m             DMADEVCMD_ts_m
4124 +#      define  EXTDMA_ts_byte_v        DMADEVCMD_ts_byte_v
4125 +#      define  EXTDMA_ts_halfword_v    DMADEVCMD_ts_halfword_v
4126 +#      define  EXTDMA_ts_word_v        DMADEVCMD_ts_word_v
4127 +#      define  EXTDMA_ts_2word_v       DMADEVCMD_ts_2word_v
4128 +#      define  EXTDMA_ts_4word_v       DMADEVCMD_ts_4word_v
4129 +#      define  EXTDMA_ts_6word_v       DMADEVCMD_ts_6word_v
4130 +#      define  EXTDMA_ts_8word_v       DMADEVCMD_ts_8word_v
4131 +#      define  EXTDMA_ts_16word_v      DMADEVCMD_ts_16word_v
4132 +#endif // aws - Compatibility.
4133 +
4134 +#endif // __IDT_RC32365_DMA_H__
4135 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
4136 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h    1970-01-01 01:00:00.000000000 +0100
4137 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h       2006-06-18 12:44:28.000000000 +0200
4138 @@ -0,0 +1,86 @@
4139 +/**************************************************************************
4140 + *
4141 + *  BRIEF MODULE DESCRIPTION
4142 + *   RC32365/336 DMA interface routines.
4143 + *
4144 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4145 + *
4146 + *  This program is free software; you can redistribute  it and/or modify it
4147 + *  under  the terms of  the GNU General  Public License as published by the
4148 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4149 + *  option) any later version.
4150 + *
4151 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4152 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4153 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4154 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4155 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4156 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4157 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4158 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4159 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4160 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4161 + *
4162 + *  You should have received a copy of the  GNU General Public License along
4163 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4164 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4165 + *
4166 + *
4167 + **************************************************************************
4168 + * May 2004 P. Sadik.
4169 + *
4170 + * Initial Release
4171 + *
4172 + *
4173 + *
4174 + **************************************************************************
4175 + */
4176 +
4177 +#ifndef __IDT_RC32365_DMA_V_H__
4178 +#define __IDT_RC32365_DMA_V_H__
4179 +
4180 +
4181 +#include  <asm/idt-boards/rc32300/rc32300.h>
4182 +#include  <asm/idt-boards/rc32300/rc32365_dma.h>
4183 +#include  <asm/idt-boards/rc32300/rc32365.h>
4184 +
4185 +#define DMA_CHAN_OFFSET  0x14
4186 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
4187 +#define IS_DMA_FINISHED(X)   (((X) & (DMAD_f_m)) != 0)
4188 +#define IS_DMA_DONE(X)   (((X) & (DMAD_d_m)) != 0)
4189 +
4190 +#define DMA_COUNT(count)   \
4191 +  ((count) & DMAD_count_m)
4192 +
4193 +#define DMA_HALT_TIMEOUT 500
4194 +
4195 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
4196 +{
4197 +       int timeout=1;
4198 +       if (local_readl(&ch->dmac) & DMAC_run_m) {
4199 +               local_writel(0, &ch->dmac);
4200 +
4201 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4202 +                       if (local_readl(&ch->dmas) & DMAS_h_m) {
4203 +                               local_writel(0, &ch->dmas);
4204 +                               break;
4205 +                       }
4206 +               }
4207 +
4208 +       }
4209 +
4210 +       return timeout ? 0 : 1;
4211 +}
4212 +
4213 +
4214 +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
4215 +{
4216 +       local_writel(0, &ch->dmandptr);
4217 +       local_writel(dma_addr, &ch->dmadptr);
4218 +}
4219 +
4220 +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
4221 +{
4222 +       local_writel(dma_addr, &ch->dmandptr);
4223 +}
4224 +#endif //__IDT_RC32365_DMA_V_H__
4225 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
4226 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h      1970-01-01 01:00:00.000000000 +0100
4227 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2006-06-18 12:44:28.000000000 +0200
4228 @@ -0,0 +1,344 @@
4229 +/**************************************************************************
4230 + *
4231 + *  BRIEF MODULE DESCRIPTION
4232 + *   RC32365/336 Ethernet hardware abstraction.
4233 + *
4234 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4235 + *
4236 + *  This program is free software; you can redistribute  it and/or modify it
4237 + *  under  the terms of  the GNU General  Public License as published by the
4238 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4239 + *  option) any later version.
4240 + *
4241 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4242 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4243 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4244 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4245 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4246 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4247 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4248 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4249 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4250 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4251 + *
4252 + *  You should have received a copy of the  GNU General Public License along
4253 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4254 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4255 + *
4256 + *
4257 + **************************************************************************
4258 + * May 2004 P. Sadik.
4259 + *
4260 + * Initial Release
4261 + *
4262 + *
4263 + *
4264 + **************************************************************************
4265 + */
4266 +
4267 +#ifndef        __IDT_RC32365_ETH_H__
4268 +#define        __IDT_RC32365_ETH_H__
4269 +
4270 +enum
4271 +{
4272 +       ETH0_PhysicalAddress    = 0x18058000,
4273 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
4274 +       ETH0_VirtualAddress     = 0xb8058000,
4275 +
4276 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
4277 +
4278 +       ETH1_PhysicalAddress    = 0x18060000,
4279 +       ETH1_VirtualAddress     = 0xb8060000,                   // Default
4280 +} ;
4281 +
4282 +typedef struct
4283 +{
4284 +       u32 ethintfc            ;
4285 +       u32 ethfifott           ;
4286 +       u32 etharc              ;
4287 +       u32 ethhash0            ;
4288 +       u32 ethhash1            ;
4289 +       u32 ethu0 [4]           ;       // Reserved.
4290 +       u32 ethpfs              ;
4291 +       u32 ethmcp              ;
4292 +       u32 eth_u1 [10]         ;       // Reserved.
4293 +       u32 ethspare            ;
4294 +       u32 eth_u2 [42]         ;       // Reserved.
4295 +       u32 ethsal0             ;
4296 +       u32 ethsah0             ;
4297 +       u32 ethsal1             ;
4298 +       u32 ethsah1             ;
4299 +       u32 ethsal2             ;
4300 +       u32 ethsah2             ;
4301 +       u32 ethsal3             ;
4302 +       u32 ethsah3             ;
4303 +       u32 ethrbc              ;
4304 +       u32 ethrpc              ;
4305 +       u32 ethrupc             ;
4306 +       u32 ethrfc              ;
4307 +       u32 ethtbc              ;
4308 +       u32 ethgpf              ;
4309 +       u32 eth_u9 [50]         ;       // Reserved.
4310 +       u32 ethmac1             ;
4311 +       u32 ethmac2             ;
4312 +       u32 ethipgt             ;
4313 +       u32 ethipgr             ;
4314 +       u32 ethclrt             ;
4315 +       u32 ethmaxf             ;
4316 +       u32 eth_u10             ;       // Reserved.
4317 +       u32 ethmtest            ;
4318 +       u32 miimcfg             ;
4319 +       u32 miimcmd             ;
4320 +       u32 miimaddr            ;
4321 +       u32 miimwtd             ;
4322 +       u32 miimrdd             ;
4323 +       u32 miimind             ;
4324 +       u32 eth_u11             ;       // Reserved.
4325 +       u32 eth_u12             ;       // Reserved.
4326 +       u32 ethcfsa0            ;
4327 +       u32 ethcfsa1            ;
4328 +       u32 ethcfsa2            ;
4329 +} volatile *ETH_t;
4330 +
4331 +enum
4332 +{
4333 +       ETHINTFC_en_b           = 0,
4334 +       ETHINTFC_en_m           = 0x00000001,
4335 +       ETHINTFC_its_b          = 1,
4336 +       ETHINTFC_its_m          = 0x00000002,
4337 +       ETHINTFC_rip_b          = 2,
4338 +       ETHINTFC_rip_m          = 0x00000004,
4339 +       ETHINTFC_jam_b          = 3,
4340 +       ETHINTFC_jam_m          = 0x00000008,
4341 +       ETHINTFC_ovr_b          = 4,
4342 +       ETHINTFC_ovr_m          = 0x00000010,
4343 +       ETHINTFC_und_b          = 5,
4344 +       ETHINTFC_und_m          = 0x00000020,
4345 +
4346 +       ETHFIFOTT_tth_b         = 0,
4347 +       ETHFIFOTT_tth_m         = 0x0000007f,
4348 +
4349 +       ETHARC_pro_b            = 0,
4350 +       ETHARC_pro_m            = 0x00000001,
4351 +       ETHARC_am_b             = 1,
4352 +       ETHARC_am_m             = 0x00000002,
4353 +       ETHARC_afm_b            = 2,
4354 +       ETHARC_afm_m            = 0x00000004,
4355 +       ETHARC_ab_b             = 3,
4356 +       ETHARC_ab_m             = 0x00000008,
4357 +
4358 +       ETHSAL_byte5_b          = 0,
4359 +       ETHSAL_byte5_m          = 0x000000ff,
4360 +       ETHSAL_byte4_b          = 8,
4361 +       ETHSAL_byte4_m          = 0x0000ff00,
4362 +       ETHSAL_byte3_b          = 16,
4363 +       ETHSAL_byte3_m          = 0x00ff0000,
4364 +       ETHSAL_byte2_b          = 24,
4365 +       ETHSAL_byte2_m          = 0xff000000,
4366 +
4367 +       ETHSAH_byte1_b          = 0,
4368 +       ETHSAH_byte1_m          = 0x000000ff,
4369 +       ETHSAH_byte0_b          = 8,
4370 +       ETHSAH_byte0_m          = 0x0000ff00,
4371 +
4372 +       ETHGPF_ptv_b            = 0,
4373 +       ETHGPF_ptv_m            = 0x0000ffff,
4374 +
4375 +       ETHPFS_pfd_b            = 0,
4376 +       ETHPFS_pfd_m            = 0x00000001,
4377 +
4378 +       ETHCFSA0_cfsa4_b        = 0,
4379 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
4380 +       ETHCFSA0_cfsa5_b        = 8,
4381 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
4382 +
4383 +       ETHCFSA1_cfsa2_b        = 0,
4384 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
4385 +       ETHCFSA1_cfsa3_b        = 8,
4386 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
4387 +
4388 +       ETHCFSA2_cfsa0_b        = 0,
4389 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
4390 +       ETHCFSA2_cfsa1_b        = 8,
4391 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
4392 +
4393 +       ETHMAC1_re_b            = 0,
4394 +       ETHMAC1_re_m            = 0x00000001,
4395 +       ETHMAC1_paf_b           = 1,
4396 +       ETHMAC1_paf_m           = 0x00000002,
4397 +       ETHMAC1_rfc_b           = 2,
4398 +       ETHMAC1_rfc_m           = 0x00000004,
4399 +       ETHMAC1_tfc_b           = 3,
4400 +       ETHMAC1_tfc_m           = 0x00000008,
4401 +       ETHMAC1_lb_b            = 4,
4402 +       ETHMAC1_lb_m            = 0x00000010,
4403 +       ETHMAC1_mr_b            = 31,
4404 +       ETHMAC1_mr_m            = 0x80000000,
4405 +
4406 +       ETHMAC2_fd_b            = 0,
4407 +       ETHMAC2_fd_m            = 0x00000001,
4408 +       ETHMAC2_flc_b           = 1,
4409 +       ETHMAC2_flc_m           = 0x00000002,
4410 +       ETHMAC2_hfe_b           = 2,
4411 +       ETHMAC2_hfe_m           = 0x00000004,
4412 +       ETHMAC2_dc_b            = 3,
4413 +       ETHMAC2_dc_m            = 0x00000008,
4414 +       ETHMAC2_cen_b           = 4,
4415 +       ETHMAC2_cen_m           = 0x00000010,
4416 +       ETHMAC2_pe_b            = 5,
4417 +       ETHMAC2_pe_m            = 0x00000020,
4418 +       ETHMAC2_vpe_b           = 6,
4419 +       ETHMAC2_vpe_m           = 0x00000040,
4420 +       ETHMAC2_ape_b           = 7,
4421 +       ETHMAC2_ape_m           = 0x00000080,
4422 +       ETHMAC2_ppe_b           = 8,
4423 +       ETHMAC2_ppe_m           = 0x00000100,
4424 +       ETHMAC2_lpe_b           = 9,
4425 +       ETHMAC2_lpe_m           = 0x00000200,
4426 +       ETHMAC2_nb_b            = 12,
4427 +       ETHMAC2_nb_m            = 0x00001000,
4428 +       ETHMAC2_bp_b            = 13,
4429 +       ETHMAC2_bp_m            = 0x00002000,
4430 +       ETHMAC2_ed_b            = 14,
4431 +       ETHMAC2_ed_m            = 0x00004000,
4432 +
4433 +       ETHIPGT_ipgt_b          = 0,
4434 +       ETHIPGT_ipgt_m          = 0x0000007f,
4435 +
4436 +       ETHIPGR_ipgr2_b         = 0,
4437 +       ETHIPGR_ipgr2_m         = 0x0000007f,
4438 +       ETHIPGR_ipgr1_b         = 8,
4439 +       ETHIPGR_ipgr1_m         = 0x00007f00,
4440 +
4441 +       ETHCLRT_maxret_b        = 0,
4442 +       ETHCLRT_maxret_m        = 0x0000000f,
4443 +       ETHCLRT_colwin_b        = 8,
4444 +       ETHCLRT_colwin_m        = 0x00003f00,
4445 +
4446 +       ETHMAXF_maxf_b          = 0,
4447 +       ETHMAXF_maxf_m          = 0x0000ffff,
4448 +
4449 +       ETHMTEST_tb_b           = 2,
4450 +       ETHMTEST_tb_m           = 0x00000004,
4451 +
4452 +       ETHMCP_div_b            = 0,
4453 +       ETHMCP_div_m            = 0x000000ff,
4454 +
4455 +       MIIMCFG_rsv_b           = 0,
4456 +       MIIMCFG_rsv_m           = 0x0000000c,
4457 +
4458 +       MIIMCMD_rd_b            = 0,
4459 +       MIIMCMD_rd_m            = 0x00000001,
4460 +       MIIMCMD_scn_b           = 1,
4461 +       MIIMCMD_scn_m           = 0x00000002,
4462 +
4463 +       MIIMADDR_regaddr_b      = 0,
4464 +       MIIMADDR_regaddr_m      = 0x0000001f,
4465 +       MIIMADDR_phyaddr_b      = 8,
4466 +       MIIMADDR_phyaddr_m      = 0x00001f00,
4467 +
4468 +       MIIMWTD_wdata_b         = 0,
4469 +       MIIMWTD_wdata_m         = 0x0000ffff,
4470 +
4471 +       MIIMRDD_rdata_b         = 0,
4472 +       MIIMRDD_rdata_m         = 0x0000ffff,
4473 +
4474 +       MIIMIND_bsy_b           = 0,
4475 +       MIIMIND_bsy_m           = 0x00000001,
4476 +       MIIMIND_scn_b           = 1,
4477 +       MIIMIND_scn_m           = 0x00000002,
4478 +       MIIMIND_nv_b            = 2,
4479 +       MIIMIND_nv_m            = 0x00000004,
4480 +
4481 +} ;
4482 +
4483 +/*
4484 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
4485 + */
4486 +enum
4487 +{
4488 +       ETHRX_fd_b              = 0,
4489 +       ETHRX_fd_m              = 0x00000001,
4490 +       ETHRX_ld_b              = 1,
4491 +       ETHRX_ld_m              = 0x00000002,
4492 +       ETHRX_rok_b             = 2,
4493 +       ETHRX_rok_m             = 0x00000004,
4494 +       ETHRX_fm_b              = 3,
4495 +       ETHRX_fm_m              = 0x00000008,
4496 +       ETHRX_mp_b              = 4,
4497 +       ETHRX_mp_m              = 0x00000010,
4498 +       ETHRX_bp_b              = 5,
4499 +       ETHRX_bp_m              = 0x00000020,
4500 +       ETHRX_vlt_b             = 6,
4501 +       ETHRX_vlt_m             = 0x00000040,
4502 +       ETHRX_cf_b              = 7,
4503 +       ETHRX_cf_m              = 0x00000080,
4504 +       ETHRX_ovr_b             = 8,
4505 +       ETHRX_ovr_m             = 0x00000100,
4506 +       ETHRX_crc_b             = 9,
4507 +       ETHRX_crc_m             = 0x00000200,
4508 +       ETHRX_cv_b              = 10,
4509 +       ETHRX_cv_m              = 0x00000400,
4510 +       ETHRX_db_b              = 11,
4511 +       ETHRX_db_m              = 0x00000800,
4512 +       ETHRX_le_b              = 12,
4513 +       ETHRX_le_m              = 0x00001000,
4514 +       ETHRX_lor_b             = 13,
4515 +       ETHRX_lor_m             = 0x00002000,
4516 +       ETHRX_ces_b             = 14,
4517 +       ETHRX_ces_m             = 0x00004000,
4518 +       ETHRX_length_b          = 16,
4519 +       ETHRX_length_m          = 0xffff0000,
4520 +
4521 +       ETHTX_fd_b              = 0,
4522 +       ETHTX_fd_m              = 0x00000001,
4523 +       ETHTX_ld_b              = 1,
4524 +       ETHTX_ld_m              = 0x00000002,
4525 +       ETHTX_oen_b             = 2,
4526 +       ETHTX_oen_m             = 0x00000004,
4527 +       ETHTX_pen_b             = 3,
4528 +       ETHTX_pen_m             = 0x00000008,
4529 +       ETHTX_cen_b             = 4,
4530 +       ETHTX_cen_m             = 0x00000010,
4531 +       ETHTX_hen_b             = 5,
4532 +       ETHTX_hen_m             = 0x00000020,
4533 +       ETHTX_tok_b             = 6,
4534 +       ETHTX_tok_m             = 0x00000040,
4535 +       ETHTX_mp_b              = 7,
4536 +       ETHTX_mp_m              = 0x00000080,
4537 +       ETHTX_bp_b              = 8,
4538 +       ETHTX_bp_m              = 0x00000100,
4539 +       ETHTX_und_b             = 9,
4540 +       ETHTX_und_m             = 0x00000200,
4541 +       ETHTX_of_b              = 10,
4542 +       ETHTX_of_m              = 0x00000400,
4543 +       ETHTX_ed_b              = 11,
4544 +       ETHTX_ed_m              = 0x00000800,
4545 +       ETHTX_ec_b              = 12,
4546 +       ETHTX_ec_m              = 0x00001000,
4547 +       ETHTX_lc_b              = 13,
4548 +       ETHTX_lc_m              = 0x00002000,
4549 +       ETHTX_td_b              = 14,
4550 +       ETHTX_td_m              = 0x00004000,
4551 +       ETHTX_crc_b             = 15,
4552 +       ETHTX_crc_m             = 0x00008000,
4553 +       ETHTX_le_b              = 16,
4554 +       ETHTX_le_m              = 0x00010000,
4555 +       ETHTX_cc_b              = 17,
4556 +       ETHTX_cc_m              = 0x001E0000,
4557 +} ;
4558 +
4559 +enum
4560 +{
4561 +       ETH0_IPABMC_PhysicalAddress     = 0x18040010,
4562 +       ETH0_IPABMC_VirtualAddress      = 0xb8040000,
4563 +       ETH1_IPABMC_PhysicalAddress     = 0x18040018,
4564 +       ETH1_IPABMC_VirtualAddress      = 0xb8040018,
4565 +} ;
4566 +
4567 +typedef struct
4568 +{
4569 +       u32 ipabmcrx            ;
4570 +       u32 ipabmctx            ;
4571 +}volatile *IPABM_ETH_t;
4572 +#endif //__IDT_RC32365_ETH_H__
4573 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
4574 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h    1970-01-01 01:00:00.000000000 +0100
4575 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h       2006-06-18 12:44:28.000000000 +0200
4576 @@ -0,0 +1,72 @@
4577 +/**************************************************************************
4578 + *
4579 + *  BRIEF MODULE DESCRIPTION
4580 + *   RC32365/336 Ethernet status checking.
4581 + *
4582 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4583 + *
4584 + *  This program is free software; you can redistribute  it and/or modify it
4585 + *  under  the terms of  the GNU General  Public License as published by the
4586 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4587 + *  option) any later version.
4588 + *
4589 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4590 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4591 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4592 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4593 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4594 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4595 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4596 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4597 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4598 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4599 + *
4600 + *  You should have received a copy of the  GNU General Public License along
4601 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4602 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4603 + *
4604 + *
4605 + **************************************************************************
4606 + * May 2004 P. Sadik.
4607 + *
4608 + * Initial Release
4609 + *
4610 + *
4611 + *
4612 + **************************************************************************
4613 + */
4614 +
4615 +#ifndef __IDT_RC32365_ETH_V_H__
4616 +#define __IDT_RC32365_ETH_V_H__
4617 +#include  <asm/idt-boards/rc32300/rc32365_eth.h>
4618 +
4619 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
4620 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
4621 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
4622 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
4623 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
4624 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
4625 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
4626 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
4627 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
4628 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
4629 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
4630 +
4631 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
4632 +
4633 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
4634 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
4635 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
4636 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
4637 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
4638 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
4639 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
4640 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
4641 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
4642 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
4643 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
4644 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
4645 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
4646 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
4647 +
4648 +#endif //__IDT_RC32365_ETH_V_H__
4649 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
4650 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h     1970-01-01 01:00:00.000000000 +0100
4651 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h        2006-06-18 12:44:28.000000000 +0200
4652 @@ -0,0 +1,181 @@
4653 +/**************************************************************************
4654 + *
4655 + *  BRIEF MODULE DESCRIPTION
4656 + *   RC32365/336 GPIO hardware abstraction.
4657 + *
4658 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4659 + *
4660 + *  This program is free software; you can redistribute  it and/or modify it
4661 + *  under  the terms of  the GNU General  Public License as published by the
4662 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4663 + *  option) any later version.
4664 + *
4665 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4666 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4667 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4668 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4669 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4670 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4671 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4672 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4673 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4674 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4675 + *
4676 + *  You should have received a copy of the  GNU General Public License along
4677 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4678 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4679 + *
4680 + *
4681 + **************************************************************************
4682 + * May 2004 P. Sadik.
4683 + *
4684 + * Initial Release
4685 + *
4686 + *
4687 + *
4688 + **************************************************************************
4689 + */
4690 +
4691 +#ifndef        __IDT_RC32365_GPIO_H__
4692 +#define        __IDT_RC32365_GPIO_H__
4693 +
4694 +enum
4695 +{
4696 +       GPIO0_PhysicalAddress   = 0x18048000,
4697 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
4698 +
4699 +       GPIO0_VirtualAddress    = 0xb8048000,
4700 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
4701 +} ;
4702 +
4703 +typedef struct
4704 +{
4705 +       u32   gpiofunc;   /* GPIO Function Register
4706 +                          * gpiofunc[x]==0 bit = gpio
4707 +                          * func[x]==1  bit = altfunc
4708 +                          */
4709 +       u32   gpiocfg;    /* GPIO Configuration Register
4710 +                          * gpiocfg[x]==0 bit = input
4711 +                          * gpiocfg[x]==1 bit = output
4712 +                          */
4713 +       u32   gpiod;        /* GPIO Data Register
4714 +                            * gpiod[x] read/write gpio pinX status
4715 +                            */
4716 +       u32   gpioilevel; /* GPIO Interrupt Status Register
4717 +                          * interrupt level (see gpioistat)
4718 +                          */
4719 +       u32   gpioistat;  /* Gpio Interrupt Status Register
4720 +                          * istat[x] = (gpiod[x] == level[x])
4721 +                          * cleared in ISR (STICKY bits)
4722 +                          */
4723 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
4724 +} volatile * GPIO_t ;
4725 +
4726 +typedef enum
4727 +{
4728 +       GPIO_gpio_v         = 0,                // gpiofunc use pin as GPIO.
4729 +       GPIO_alt_v          = 1,                // gpiofunc use pin as alt.
4730 +       GPIO_input_v        = 0,                // gpiocfg use pin as input.
4731 +       GPIO_output_v       = 1,                // gpiocfg use pin as output.
4732 +       GPIO_pin0_b         = 0,
4733 +       GPIO_pin0_m         = 0x00000001,
4734 +       GPIO_pin1_b         = 1,
4735 +       GPIO_pin1_m         = 0x00000002,
4736 +       GPIO_pin2_b         = 2,
4737 +       GPIO_pin2_m         = 0x00000004,
4738 +       GPIO_pin3_b         = 3,
4739 +       GPIO_pin3_m         = 0x00000008,
4740 +       GPIO_pin4_b         = 4,
4741 +       GPIO_pin4_m         = 0x00000010,
4742 +       GPIO_pin5_b         = 5,
4743 +       GPIO_pin5_m         = 0x00000020,
4744 +       GPIO_pin6_b         = 6,
4745 +       GPIO_pin6_m         = 0x00000040,
4746 +       GPIO_pin7_b         = 7,
4747 +       GPIO_pin7_m         = 0x00000080,
4748 +       GPIO_pin8_b         = 8,
4749 +       GPIO_pin8_m         = 0x00000100,
4750 +       GPIO_pin9_b         = 9,
4751 +       GPIO_pin9_m         = 0x00000200,
4752 +       GPIO_pin10_b        = 10,
4753 +       GPIO_pin10_m        = 0x00000400,
4754 +       GPIO_pin11_b        = 11,
4755 +       GPIO_pin11_m        = 0x00000800,
4756 +       GPIO_pin12_b        = 12,
4757 +       GPIO_pin12_m        = 0x00001000,
4758 +       GPIO_pin13_b        = 13,
4759 +       GPIO_pin13_m        = 0x00002000,
4760 +       GPIO_pin14_b        = 14,
4761 +       GPIO_pin14_m        = 0x00004000,
4762 +       GPIO_pin15_b        = 15,
4763 +       GPIO_pin15_m        = 0x00008000,
4764 +
4765 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
4766 +
4767 +       GPIO_u0sout_b       = GPIO_pin0_b,              // UART 0 serial out.
4768 +       GPIO_u0sout_m       = GPIO_pin0_m,
4769 +       GPIO_u0sout_cfg_v   = GPIO_output_v,
4770 +
4771 +       GPIO_u0sinp_b       = GPIO_pin1_b,                      // UART 0 serial in.
4772 +       GPIO_u0sinp_m       = GPIO_pin1_m,
4773 +       GPIO_u0sinp_cfg_v   = GPIO_input_v,
4774 +
4775 +       GPIO_maddr22_b      = GPIO_pin2_b,      // M&P bus bit 22.
4776 +       GPIO_maddr22_m      = GPIO_pin2_m,
4777 +       GPIO_maddr22_cfg_v  = GPIO_output_v,
4778 +
4779 +       GPIO_maddr23_b      = GPIO_pin3_b,      // M&P bus bit 23.
4780 +       GPIO_maddr23_m      = GPIO_pin3_m,
4781 +       GPIO_maddr23_cfg_v  = GPIO_output_v,
4782 +
4783 +       GPIO_maddr24_b      = GPIO_pin4_b,      // M&P bus bit 24.
4784 +       GPIO_maddr24_m      = GPIO_pin4_m,
4785 +       GPIO_maddr24_cfg_v  = GPIO_output_v,
4786 +
4787 +       GPIO_maddr25_b      = GPIO_pin5_b,      // M&P bus bit 25.
4788 +       GPIO_maddr25_m      = GPIO_pin5_m,
4789 +       GPIO_maddr25_cfg_v  = GPIO_output_v,
4790 +
4791 +       GPIO_rngclk_b       = GPIO_pin6_b,      // reserved.
4792 +       GPIO_rngclk_m       = GPIO_pin6_m,
4793 +       GPIO_rngclk_cfg_v   = GPIO_input_v,
4794 +
4795 +       GPIO_sdckenp_b      = GPIO_pin7_b,      // reserved.
4796 +       GPIO_sdckenp_m      = GPIO_pin7_m,
4797 +       GPIO_sdckenp_cfg_v  = GPIO_output_v,
4798 +
4799 +       GPIO_cen1_b         = GPIO_pin8_b,      // reserved.
4800 +       GPIO_cen1_m         = GPIO_pin8_m,
4801 +       GPIO_cen1_cfg_v     = GPIO_output_v,
4802 +
4803 +       GPIO_cen2_b         = GPIO_pin9_b,      // reserved.
4804 +       GPIO_cen2_m         = GPIO_pin9_m,
4805 +       GPIO_cen2_cfg_v     = GPIO_output_v,
4806 +
4807 +       GPIO_regn_b         = GPIO_pin10_b,     // reserved.
4808 +       GPIO_regn_m         = GPIO_pin10_m,
4809 +       GPIO_regn_cfg_v     = GPIO_output_v,
4810 +
4811 +       GPIO_iordn_b        = GPIO_pin11_b,     // reserved.
4812 +       GPIO_iordn_m        = GPIO_pin11_m,
4813 +       GPIO_iordn_cfg_v    = GPIO_output_v,
4814 +
4815 +       GPIO_iowrn_b        = GPIO_pin12_b,     // reserved.
4816 +       GPIO_iowrn_m        = GPIO_pin12_m,
4817 +       GPIO_iowrn_cfg_v    = GPIO_output_v,
4818 +
4819 +       GPIO_pcireqn2_b     = GPIO_pin13_b,     // PCI messaging int.
4820 +       GPIO_pcireqn2_m     = GPIO_pin13_m,
4821 +       GPIO_pcireqn2_cfg_v = GPIO_input_v,
4822 +
4823 +       GPIO_pcigntn2_b     = GPIO_pin14_b,     // PCI messaging int.
4824 +       GPIO_pcigntn2_m     = GPIO_pin14_m,
4825 +       GPIO_pcigntn2_cfg_v = GPIO_output_v,
4826 +
4827 +       GPIO_pcimuintn_b    = GPIO_pin15_b,     // PCI messaging int.
4828 +       GPIO_pcimuintn_m    = GPIO_pin15_m,
4829 +       GPIO_pcimuintn_cfg_v= GPIO_output_v,
4830 +
4831 +} GPIO_DEFS_t;
4832 +
4833 +#endif //__IDT_RC32365_GPIO_H__
4834 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
4835 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h   1970-01-01 01:00:00.000000000 +0100
4836 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h      2006-06-18 12:44:28.000000000 +0200
4837 @@ -0,0 +1,91 @@
4838 +/**************************************************************************
4839 + *
4840 + *  BRIEF MODULE DESCRIPTION
4841 + *   Routines to set/clear/toggle GPIO on RC32365
4842 + *
4843 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4844 + *
4845 + *  This program is free software; you can redistribute  it and/or modify it
4846 + *  under  the terms of  the GNU General  Public License as published by the
4847 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4848 + *  option) any later version.
4849 + *
4850 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4851 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4852 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4853 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4854 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4855 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4856 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4857 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4858 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4859 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4860 + *
4861 + *  You should have received a copy of the  GNU General Public License along
4862 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4863 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4864 + *
4865 + *
4866 + **************************************************************************
4867 + * May 2004 P. Sadik.
4868 + *
4869 + * Initial Release
4870 + *
4871 + *
4872 + *
4873 + **************************************************************************
4874 + */
4875 +#ifndef        __IDT_RC32365_GPIO_V_H__
4876 +#define        __IDT_RC32365_GPIO_V_H__
4877 +
4878 +
4879 +#ifdef _LANGUAGE_ASSEMBLY
4880 +#define SET_GPIO(pin) \
4881 +       lui t5,0xb804 ; \
4882 +       ori t5,t5,0x8000 ; \
4883 +       lw  t4,8(t5) ; \
4884 +       ori t4,t4,pin ; \
4885 +       sw  t4,8(t5) ;
4886 +
4887 +#define CLEAR_GPIO(pin) \
4888 +       lui t5,0xb804 ; \
4889 +       ori t5,t5,0x8000 ; \
4890 +       lw  t4,8(t5) ; \
4891 +        lui t6,0xFFFF; \
4892 +        ori t6,t6,0xFFFF; \
4893 +       xori t6,t6,pin ; \
4894 +        and  t4,t6 ; \
4895 +       sw  t4,8(t5) ;
4896 +
4897 +#define TOGGLE_GPIO(pin) \
4898 +       lui t5,0xb804 ; \
4899 +       ori t5,t5,0x8000 ; \
4900 +       lw  t4,8(t5) ; \
4901 +       xori t4,t4,pin ; \
4902 +       sw  t4,8(t5) ;
4903 +
4904 +#else // !_LANGUAGE_ASSEMBLY
4905 +#include  <asm/rc32300/types.h>
4906 +#include  <asm/rc32300/rc32365_gpio.h>
4907 +#include  <asm/rc32300/rc32365.h>
4908 +
4909 +static inline void set_gpio(unsigned long pin)
4910 +{
4911 +  idt_gpio->gpiod |= pin;
4912 +}
4913 +
4914 +static inline void clear_gpio(unsigned long pin)
4915 +{
4916 +  idt_gpio->gpiod &= ~pin;
4917 +}
4918 +static inline void toggle_gpio(unsigned long pin)
4919 +{
4920 +  idt_gpio->gpiod ^= pin;
4921 +}
4922 +#define SET_GPIO(pin) set_gpio(pin)
4923 +#define CLEAR_GPIO(pin) clear_gpio(pin)
4924 +#define TOGGLE_GPIO(pin) toggle_gpio(pin)
4925 +#endif // _LANGUAGE_ASSEMBLY
4926 +
4927 +#endif //__IDT_RC32365_GPIO_V_H__
4928 +
4929 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h
4930 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365.h  1970-01-01 01:00:00.000000000 +0100
4931 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h     2006-06-18 12:44:28.000000000 +0200
4932 @@ -0,0 +1,160 @@
4933 +/**************************************************************************
4934 + *
4935 + *  BRIEF MODULE DESCRIPTION
4936 + *   Definitions for IDT RC32365 CPU.
4937 + *
4938 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4939 + *
4940 + *  This program is free software; you can redistribute  it and/or modify it
4941 + *  under  the terms of  the GNU General  Public License as published by the
4942 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4943 + *  option) any later version.
4944 + *
4945 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4946 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4947 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4948 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4949 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4950 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4951 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4952 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4953 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4954 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4955 + *
4956 + *  You should have received a copy of the  GNU General Public License along
4957 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4958 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4959 + *
4960 + *
4961 + **************************************************************************
4962 + * May 2004 P. Sadik.
4963 + *
4964 + * Initial Release
4965 + *
4966 + *
4967 + *
4968 + **************************************************************************
4969 + */
4970 +
4971 +#ifndef __IDT_RC32365_H__
4972 +#define __IDT_RC32365_H__
4973 +
4974 +extern unsigned int cedar_za;
4975 +
4976 +/* Base address of internal registers */
4977 +#define RC32365_REG_BASE   0x18000000
4978 +
4979 +/* System ID Registers */
4980 +#define CPU_SYSID          (RC32365_REG_BASE + 0x00018)
4981 +#define CPU_DEVTYPE        (RC32365_REG_BASE + 0x0001c)
4982 +
4983 +/* Reset Controller */
4984 +#define RESET_CNTL         (RC32365_REG_BASE + 0x08000)
4985 +#define BOOT_VECTOR        (RC32365_REG_BASE + 0x08004)
4986 +
4987 +/* Device Controller */
4988 +#define DEV0_BASE          (RC32365_REG_BASE + 0x10000)
4989 +#define DEV0_MASK          (RC32365_REG_BASE + 0x10004)
4990 +#define DEV0_CNTL          (RC32365_REG_BASE + 0x10008)
4991 +#define DEV0_TIMING        (RC32365_REG_BASE + 0x1000c)
4992 +#define DEV_REG_OFFSET     0x10
4993 +
4994 +/* SDRAM Controller */
4995 +#define SDRAM0_BASE        (RC32365_REG_BASE + 0x18000)
4996 +#define SDRAM0_MASK        (RC32365_REG_BASE + 0x18004)
4997 +#define SDRAM1_BASE        (RC32365_REG_BASE + 0x18008)
4998 +#define SDRAM1_MASK        (RC32365_REG_BASE + 0x1800c)
4999 +#define SDRAM_CNTL         (RC32365_REG_BASE + 0x18010)
5000 +
5001 +/* Counters/Timers */
5002 +#define TIMER0_COUNT       (RC32365_REG_BASE + 0x20000)
5003 +#define TIMER0_COMPARE     (RC32365_REG_BASE + 0x20004)
5004 +#define TIMER0_CNTL        (RC32365_REG_BASE + 0x20008)
5005 +#define TIMER0_SELECT      (RC32365_REG_BASE + 0x2000c)
5006 +#define TIMER_REG_OFFSET   0x10
5007 +
5008 +/* System Integrity */
5009 +
5010 +/* Interrupt Controller */
5011 +#define IC_GROUP0_PEND     (RC32365_REG_BASE + 0x30000)
5012 +#define IC_GROUP0_TEST     (RC32365_REG_BASE + 0x30004)
5013 +#define IC_GROUP0_MASK     (RC32365_REG_BASE + 0x30008)
5014 +#define IC_GROUP_OFFSET    0x0c
5015 +
5016 +#define NUM_INTR_GROUPS    5
5017 +/*
5018 + * The IRQ mapping is as follows:
5019 + *
5020 + *    IRQ         Mapped To
5021 + *    ---     -------------------
5022 + *     0      SW0  (IP0) SW0 intr
5023 + *     1      SW1  (IP1) SW1 intr
5024 + *     -      Int0 (IP2) mapped to GROUP0_IRQ_BASE
5025 + *     -      Int1 (IP3) mapped to GROUP1_IRQ_BASE
5026 + *     -      Int2 (IP4) mapped to GROUP2_IRQ_BASE
5027 + *     -      Int3 (IP5) mapped to GROUP3_IRQ_BASE
5028 + *     -      Int4 (IP6) mapped to GROUP4_IRQ_BASE
5029 + *     7      Int5 (IP7) CP0 Timer
5030 + *
5031 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
5032 + * internally on the RC32365 is routed to the Expansion
5033 + * Interrupt Controller.
5034 + */
5035 +#define MIPS_CPU_TIMER_IRQ 7
5036 +
5037 +#define GROUP0_IRQ_BASE  8                      // Counter/Timers, UCW
5038 +#define GROUP1_IRQ_BASE  (GROUP0_IRQ_BASE + 32) // DMA
5039 +#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 32) // RNG, SEC
5040 +#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
5041 +#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 32) // GPIO
5042 +
5043 +#define RC32365_NR_IRQS  (GROUP4_IRQ_BASE + 32)
5044 +
5045 +/* DMA - see rc32365_dma.h for full list of registers */
5046 +
5047 +#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
5048 +#define DMA_CHAN_OFFSET  0x14
5049 +
5050 +/* GPIO Controller */
5051 +#define idt_gpio              ((volatile GPIO_t) GPIO0_VirtualAddress)
5052 +
5053 +/* 16550 UARTs */
5054 +#ifdef __MIPSEB__
5055 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
5056 +#else
5057 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
5058 +#endif
5059 +#define RC32300_UART0_IRQ  (GROUP3_IRQ_BASE + 0)
5060 +
5061 +/* Ethernet - see rc32365_eth.h for full list of registers */
5062 +
5063 +#define RC32365_ETH_BASE   (RC32365_REG_BASE + 0x58000)
5064 +
5065 +#define IDT_CLOCK_MULT     2
5066 +
5067 +/* FLASH (device 1) */
5068 +#define FLASH_BASE         0x08000000
5069 +#define FLASH_SIZE         0x00800000
5070 +
5071 +/* LCD 4-digit display (device 2) */
5072 +#define LCD_DIGIT0         0x0C000003
5073 +#define LCD_DIGIT1         0x0C000002
5074 +#define LCD_DIGIT2         0x0C000001
5075 +#define LCD_DIGIT3         0x0C000000
5076 +
5077 +/* RTC (DS1553) (device 2) */
5078 +#define RTC_BASE           0x0c800000
5079 +/* NVRAM */
5080 +#define NVRAM_BASE         RTC_BASE
5081 +#define NVRAM_ENVSIZE_OFF  4
5082 +#define NVRAM_ENVSTART_OFF 32
5083 +
5084 +/* Interrupts routed on 79EB365 board */
5085 +#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE +  8)
5086 +#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE +  9)
5087 +#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
5088 +#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
5089 +
5090 +#define RAM_SIZE          (32 * 1024 * 1024)
5091 +
5092 +#endif //__IDT_RC32365_H__
5093 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
5094 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci.h      1970-01-01 01:00:00.000000000 +0100
5095 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 2006-06-18 12:44:28.000000000 +0200
5096 @@ -0,0 +1,515 @@
5097 +/**************************************************************************
5098 + *
5099 + *  BRIEF MODULE DESCRIPTION
5100 + *   Datatype declaration for IDT 79EB365/336 PCI
5101 + *
5102 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5103 + *
5104 + *  This program is free software; you can redistribute  it and/or modify it
5105 + *  under  the terms of  the GNU General  Public License as published by the
5106 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5107 + *  option) any later version.
5108 + *
5109 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5110 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5111 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5112 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5113 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5114 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5115 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5116 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5117 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5118 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5119 + *
5120 + *  You should have received a copy of the  GNU General Public License along
5121 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5122 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5123 + *
5124 + *
5125 + **************************************************************************
5126 + * May 2004 P. Sadik.
5127 + *
5128 + * Initial Release
5129 + *
5130 + *
5131 + *
5132 + **************************************************************************
5133 + */
5134 +
5135 +#ifndef __IDT_RC32365_PCI_H__
5136 +#define __IDT_RC32365_PCI_H__
5137 +
5138 +enum
5139 +{
5140 +       PCI0_PhysicalAddress    = 0x18068000,
5141 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
5142 +
5143 +       PCI0_VirtualAddress     = 0xb8068000,
5144 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
5145 +} ;
5146 +
5147 +enum
5148 +{
5149 +       PCI_LbaCount    = 4,            // Local base addresses.
5150 +} ;
5151 +
5152 +typedef struct
5153 +{
5154 +       u32     a ;             // Address.
5155 +       u32     c ;             // Control.
5156 +       u32     m ;             // mapping.
5157 +} PCI_Map_s ;
5158 +
5159 +typedef struct
5160 +{
5161 +       u32             pcic ;
5162 +       u32             pcis ;
5163 +       u32             pcism ;
5164 +       u32             pcicfga ;
5165 +       u32             pcicfgd ;
5166 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
5167 +       u32             pcidac ;
5168 +       u32             pcidas ;
5169 +       u32             pcidasm ;
5170 +       u32             pcidad ;
5171 +       u32             pcidma8c ;
5172 +       u32             pcidma9c ;
5173 +       u32             pcitc ;
5174 +} volatile *PCI_t ;
5175 +
5176 +// PCI messaging unit.
5177 +enum
5178 +{
5179 +       PCIM_Count      = 2,
5180 +} ;
5181 +typedef struct
5182 +{
5183 +       u32             pciim [PCIM_Count] ;
5184 +       u32             pciom [PCIM_Count] ;
5185 +       u32             pciid ;
5186 +       u32             pciiic ;
5187 +       u32             pciiim ;
5188 +       u32             pciiod ;
5189 +       u32             pciioic ;
5190 +       u32             pciioim ;
5191 +} volatile *PCIM_t ;
5192 +
5193 +/*******************************************************************************
5194 + *
5195 + * PCI Control Register
5196 + *
5197 + ******************************************************************************/
5198 +enum
5199 +{
5200 +       PCIC_en_b       = 0,
5201 +       PCIC_en_m       = 0x00000001,
5202 +       PCIC_tnr_b      = 1,
5203 +       PCIC_tnr_m      = 0x00000002,
5204 +       PCIC_sce_b      = 2,
5205 +       PCIC_sce_m      = 0x00000004,
5206 +       PCIC_ien_b      = 3,
5207 +       PCIC_ien_m      = 0x00000008,
5208 +       PCIC_aaa_b      = 4,
5209 +       PCIC_aaa_m      = 0x00000010,
5210 +       PCIC_eap_b      = 5,
5211 +       PCIC_eap_m      = 0x00000020,
5212 +       PCIC_pcim_b     = 6,
5213 +       PCIC_pcim_m     = 0x000001c0,
5214 +               PCIC_pcim_disabled_v    = 0,
5215 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
5216 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
5217 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
5218 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
5219 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
5220 +               PCIC_pcim_reserved6_v   = 6,
5221 +               PCIC_pcim_reserved7_v   = 7,
5222 +       PCIC_igm_b      = 9,
5223 +       PCIC_igm_m      = 0x00000200,
5224 +} ;
5225 +
5226 +/*******************************************************************************
5227 + *
5228 + * PCI Status Register
5229 + *
5230 + ******************************************************************************/
5231 +enum {
5232 +       PCIS_eed_b      = 0,
5233 +       PCIS_eed_m      = 0x00000001,
5234 +       PCIS_wr_b       = 1,
5235 +       PCIS_wr_m       = 0x00000002,
5236 +       PCIS_nmi_b      = 2,
5237 +       PCIS_nmi_m      = 0x00000004,
5238 +       PCIS_ii_b       = 3,
5239 +       PCIS_ii_m       = 0x00000008,
5240 +       PCIS_cwe_b      = 4,
5241 +       PCIS_cwe_m      = 0x00000010,
5242 +       PCIS_cre_b      = 5,
5243 +       PCIS_cre_m      = 0x00000020,
5244 +       PCIS_mdpe_b     = 6,
5245 +       PCIS_mdpe_m     = 0x00000040,
5246 +       PCIS_sta_b      = 7,
5247 +       PCIS_sta_m      = 0x00000080,
5248 +       PCIS_rta_b      = 8,
5249 +       PCIS_rta_m      = 0x00000100,
5250 +       PCIS_rma_b      = 9,
5251 +       PCIS_rma_m      = 0x00000200,
5252 +       PCIS_sse_b      = 10,
5253 +       PCIS_sse_m      = 0x00000400,
5254 +       PCIS_ose_b      = 11,
5255 +       PCIS_ose_m      = 0x00000800,
5256 +       PCIS_pe_b       = 12,
5257 +       PCIS_pe_m       = 0x00001000,
5258 +       PCIS_tae_b      = 13,
5259 +       PCIS_tae_m      = 0x00002000,
5260 +       PCIS_rle_b      = 14,
5261 +       PCIS_rle_m      = 0x00004000,
5262 +       PCIS_bme_b      = 15,
5263 +       PCIS_bme_m      = 0x00008000,
5264 +       PCIS_prd_b      = 16,
5265 +       PCIS_prd_m      = 0x00010000,
5266 +       PCIS_rip_b      = 17,
5267 +       PCIS_rip_m      = 0x00020000,
5268 +} ;
5269 +
5270 +/*******************************************************************************
5271 + *
5272 + * PCI Status Mask Register
5273 + *
5274 + ******************************************************************************/
5275 +enum {
5276 +       PCISM_eed_b             = 0,
5277 +       PCISM_eed_m             = 0x00000001,
5278 +       PCISM_wr_b              = 1,
5279 +       PCISM_wr_m              = 0x00000002,
5280 +       PCISM_nmi_b             = 2,
5281 +       PCISM_nmi_m             = 0x00000004,
5282 +       PCISM_ii_b              = 3,
5283 +       PCISM_ii_m              = 0x00000008,
5284 +       PCISM_cwe_b             = 4,
5285 +       PCISM_cwe_m             = 0x00000010,
5286 +       PCISM_cre_b             = 5,
5287 +       PCISM_cre_m             = 0x00000020,
5288 +       PCISM_mdpe_b            = 6,
5289 +       PCISM_mdpe_m            = 0x00000040,
5290 +       PCISM_sta_b             = 7,
5291 +       PCISM_sta_m             = 0x00000080,
5292 +       PCISM_rta_b             = 8,
5293 +       PCISM_rta_m             = 0x00000100,
5294 +       PCISM_rma_b             = 9,
5295 +       PCISM_rma_m             = 0x00000200,
5296 +       PCISM_sse_b             = 10,
5297 +       PCISM_sse_m             = 0x00000400,
5298 +       PCISM_ose_b             = 11,
5299 +       PCISM_ose_m             = 0x00000800,
5300 +       PCISM_pe_b              = 12,
5301 +       PCISM_pe_m              = 0x00001000,
5302 +       PCISM_tae_b             = 13,
5303 +       PCISM_tae_m             = 0x00002000,
5304 +       PCISM_rle_b             = 14,
5305 +       PCISM_rle_m             = 0x00004000,
5306 +       PCISM_bme_b             = 15,
5307 +       PCISM_bme_m             = 0x00008000,
5308 +       PCISM_prd_b             = 16,
5309 +       PCISM_prd_m             = 0x00010000,
5310 +       PCISM_rip_b             = 17,
5311 +       PCISM_rip_m             = 0x00020000,
5312 +} ;
5313 +
5314 +/*******************************************************************************
5315 + *
5316 + * PCI Configuration Address Register
5317 + *
5318 + ******************************************************************************/
5319 +enum {
5320 +       PCICFGA_reg_b           = 2,
5321 +       PCICFGA_reg_m           = 0x000000fc,
5322 +       PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
5323 +       PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
5324 +       PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
5325 +       PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
5326 +       PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
5327 +       PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
5328 +       PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
5329 +       PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
5330 +       PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
5331 +       PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
5332 +       PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
5333 +       PCICFGA_reg_pba0m_v     = 0x48>>2,
5334 +       PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
5335 +       PCICFGA_reg_pba1m_v     = 0x50>>2,
5336 +       PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
5337 +       PCICFGA_reg_pba2m_v     = 0x58>>2,
5338 +       PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
5339 +       PCICFGA_reg_pba3m_v     = 0x60>>2,
5340 +       PCICFGA_reg_pmgt_v      = 0x64>>2,
5341 +       PCICFGA_func_b          = 8,
5342 +       PCICFGA_func_m          = 0x00000700,
5343 +       PCICFGA_dev_b           = 11,
5344 +       PCICFGA_dev_m           = 0x0000f800,
5345 +       PCICFGA_dev_internal_v  = 0,
5346 +       PCICFGA_bus_b           = 16,
5347 +       PCICFGA_bus_m           = 0x00ff0000,
5348 +       PCICFGA_bus_type0_v     = 0,    //local bus
5349 +       PCICFGA_en_b            = 31,           // read only
5350 +       PCICFGA_en_m            = 0x80000000,
5351 +} ;
5352 +
5353 +enum {
5354 +       PCFGID_vendor_b         = 0,
5355 +       PCFGID_vendor_m         = 0x0000ffff,
5356 +       PCFGID_vendor_IDT_v             = 0x111d,
5357 +       PCFGID_device_b         = 16,
5358 +       PCFGID_device_m         = 0xffff0000,
5359 +       PCFGID_device_Acaciade_v        = 0x0207,
5360 +
5361 +       PCFG04_command_ioena_b          = 1,
5362 +       PCFG04_command_ioena_m          = 0x00000001,
5363 +       PCFG04_command_memena_b         = 2,
5364 +       PCFG04_command_memena_m         = 0x00000002,
5365 +       PCFG04_command_bmena_b          = 3,
5366 +       PCFG04_command_bmena_m          = 0x00000004,
5367 +       PCFG04_command_mwinv_b          = 5,
5368 +       PCFG04_command_mwinv_m          = 0x00000010,
5369 +       PCFG04_command_parena_b         = 7,
5370 +       PCFG04_command_parena_m         = 0x00000040,
5371 +       PCFG04_command_serrena_b        = 9,
5372 +       PCFG04_command_serrena_m        = 0x00000100,
5373 +       PCFG04_command_fastbbena_b      = 10,
5374 +       PCFG04_command_fastbbena_m      = 0x00000200,
5375 +       PCFG04_status_b                 = 16,
5376 +       PCFG04_status_m                 = 0xffff0000,
5377 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
5378 +       PCFG04_status_66MHz_m           = 0x00200000,
5379 +       PCFG04_status_fbb_b             = 23,
5380 +       PCFG04_status_fbb_m             = 0x00800000,
5381 +       PCFG04_status_mdpe_b            = 24,
5382 +       PCFG04_status_mdpe_m            = 0x01000000,
5383 +       PCFG04_status_dst_b             = 25,
5384 +       PCFG04_status_dst_m             = 0x06000000,
5385 +       PCFG04_status_sta_b             = 27,
5386 +       PCFG04_status_sta_m             = 0x08000000,
5387 +       PCFG04_status_rta_b             = 28,
5388 +       PCFG04_status_rta_m             = 0x10000000,
5389 +       PCFG04_status_rma_b             = 29,
5390 +       PCFG04_status_rma_m             = 0x20000000,
5391 +       PCFG04_status_sse_b             = 30,
5392 +       PCFG04_status_sse_m             = 0x40000000,
5393 +       PCFG04_status_pe_b              = 31,
5394 +       PCFG04_status_pe_m              = 0x40000000,
5395 +
5396 +       PCFG08_revId_b                  = 0,
5397 +       PCFG08_revId_m                  = 0x000000ff,
5398 +       PCFG08_classCode_b              = 0,
5399 +       PCFG08_classCode_m              = 0xffffff00,
5400 +       PCFG08_classCode_bridge_v       = 06,
5401 +       PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
5402 +       PCFG0C_cacheline_b              = 0,
5403 +       PCFG0C_cacheline_m              = 0x000000ff,
5404 +       PCFG0C_masterLatency_b          = 8,
5405 +       PCFG0C_masterLatency_m          = 0x0000ff00,
5406 +       PCFG0C_headerType_b             = 16,
5407 +       PCFG0C_headerType_m             = 0x00ff0000,
5408 +       PCFG0C_bist_b                   = 24,
5409 +       PCFG0C_bist_m                   = 0xff000000,
5410 +
5411 +       PCIPBA_msi_b                    = 0,
5412 +       PCIPBA_msi_m                    = 0x00000001,
5413 +       PCIPBA_p_b                      = 3,
5414 +       PCIPBA_p_m                      = 0x00000004,
5415 +       PCIPBA_baddr_b                  = 8,
5416 +       PCIPBA_baddr_m                  = 0xffffff00,
5417 +
5418 +       PCFGSS_vendorId_b               = 0,
5419 +       PCFGSS_vendorId_m               = 0x0000ffff,
5420 +       PCFGSS_id_b                     = 16,
5421 +       PCFGSS_id_m                     = 0xffff0000,
5422 +
5423 +       PCFG3C_interruptLine_b          = 0,
5424 +       PCFG3C_interruptLine_m          = 0x000000ff,
5425 +       PCFG3C_interruptPin_b           = 8,
5426 +       PCFG3C_interruptPin_m           = 0x0000ff00,
5427 +       PCFG3C_minGrant_b               = 16,
5428 +       PCFG3C_minGrant_m               = 0x00ff0000,
5429 +       PCFG3C_maxLat_b                 = 24,
5430 +       PCFG3C_maxLat_m                 = 0xff000000,
5431 +
5432 +       PCIPBAC_msi_b                   = 0,
5433 +       PCIPBAC_msi_m                   = 0x00000001,
5434 +       PCIPBAC_p_b                     = 1,
5435 +       PCIPBAC_p_m                     = 0x00000002,
5436 +       PCIPBAC_size_b                  = 2,
5437 +       PCIPBAC_size_m                  = 0x0000007c,
5438 +       PCIPBAC_sb_b                    = 7,
5439 +       PCIPBAC_sb_m                    = 0x00000080,
5440 +       PCIPBAC_pp_b                    = 8,
5441 +       PCIPBAC_pp_m                    = 0x00000100,
5442 +       PCIPBAC_mr_b                    = 9,
5443 +       PCIPBAC_mr_m                    = 0x00000600,
5444 +       PCIPBAC_mr_read_v       =0,     //no prefetching
5445 +       PCIPBAC_mr_readLine_v   =1,
5446 +       PCIPBAC_mr_readMult_v   =2,
5447 +       PCIPBAC_mrl_b                   = 11,
5448 +       PCIPBAC_mrl_m                   = 0x00000800,
5449 +       PCIPBAC_mrm_b                   = 12,
5450 +       PCIPBAC_mrm_m                   = 0x00001000,
5451 +       PCIPBAC_trp_b                   = 13,
5452 +       PCIPBAC_trp_m                   = 0x00002000,
5453 +
5454 +       PCFG40_trdyTimeout_b            = 0,
5455 +       PCFG40_trdyTimeout_m            = 0x000000ff,
5456 +       PCFG40_retryLim_b               = 8,
5457 +       PCFG40_retryLim_m               = 0x0000ff00,
5458 +};
5459 +
5460 +/*******************************************************************************
5461 + *
5462 + * PCI Local Base Address [0|1|2|3] Register
5463 + *
5464 + ******************************************************************************/
5465 +enum {
5466 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
5467 +       PCILBA_baddr_m          = 0xffffff00,
5468 +} ;
5469 +/*******************************************************************************
5470 + *
5471 + * PCI Local Base Address Control Register
5472 + *
5473 + ******************************************************************************/
5474 +enum {
5475 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
5476 +       PCILBAC_msi_m           = 0x00000001,
5477 +       PCILBAC_msi_mem_v       = 0,
5478 +       PCILBAC_msi_io_v        = 1,
5479 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
5480 +       PCILBAC_size_m          = 0x0000007c,
5481 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
5482 +       PCILBAC_sb_m            = 0x00000080,
5483 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
5484 +       PCILBAC_rt_m            = 0x00000100,
5485 +       PCILBAC_rt_noprefetch_v = 0, // mem read
5486 +       PCILBAC_rt_prefetch_v   = 1, // mem readline
5487 +} ;
5488 +
5489 +/*******************************************************************************
5490 + *
5491 + * PCI Local Base Address [0|1|2|3] Mapping Register
5492 + *
5493 + ******************************************************************************/
5494 +enum {
5495 +       PCILBAM_maddr_b         = 8,
5496 +       PCILBAM_maddr_m         = 0xffffff00,
5497 +} ;
5498 +
5499 +/*******************************************************************************
5500 + *
5501 + * PCI Decoupled Access Control Register
5502 + *
5503 + ******************************************************************************/
5504 +enum {
5505 +       PCIDAC_den_b            = 0,
5506 +       PCIDAC_den_m            = 0x00000001,
5507 +} ;
5508 +
5509 +/*******************************************************************************
5510 + *
5511 + * PCI Decoupled Access Status Register
5512 + *
5513 + ******************************************************************************/
5514 +enum {
5515 +       PCIDAS_d_b      = 0,
5516 +       PCIDAS_d_m      = 0x00000001,
5517 +       PCIDAS_b_b      = 1,
5518 +       PCIDAS_b_m      = 0x00000002,
5519 +       PCIDAS_e_b      = 2,
5520 +       PCIDAS_e_m      = 0x00000004,
5521 +       PCIDAS_ofe_b    = 3,
5522 +       PCIDAS_ofe_m    = 0x00000008,
5523 +       PCIDAS_off_b    = 4,
5524 +       PCIDAS_off_m    = 0x00000010,
5525 +       PCIDAS_ife_b    = 5,
5526 +       PCIDAS_ife_m    = 0x00000020,
5527 +       PCIDAS_iff_b    = 6,
5528 +       PCIDAS_iff_m    = 0x00000040,
5529 +} ;
5530 +
5531 +/*******************************************************************************
5532 + *
5533 + * PCI DMA Channel 8 Configuration Register
5534 + *
5535 + ******************************************************************************/
5536 +enum
5537 +{
5538 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
5539 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
5540 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
5541 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
5542 +} ;
5543 +
5544 +/*******************************************************************************
5545 + *
5546 + * PCI DMA Channel 9 Configuration Register
5547 + *
5548 + ******************************************************************************/
5549 +enum
5550 +{
5551 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
5552 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
5553 +} ;
5554 +
5555 +/*******************************************************************************
5556 + *
5557 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
5558 + *
5559 + ******************************************************************************/
5560 +enum {
5561 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
5562 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
5563 +       // These are for reads (DMA channel 8)
5564 +       PCIDMAD_devcmd_mr_v     = 0,    //memory read
5565 +       PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
5566 +       PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
5567 +       PCIDMAD_devcmd_ior_v    = 3,    //I/O read
5568 +       // These are for writes (DMA channel 9)
5569 +       PCIDMAD_devcmd_mw_v     = 0,    //memory write
5570 +       PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
5571 +       PCIDMAD_devcmd_iow_v    = 3,    //I/O write
5572 +
5573 +       // Swap byte field applies to both DMA channel 8 and 9
5574 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
5575 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
5576 +} ;
5577 +
5578 +
5579 +/*******************************************************************************
5580 + *
5581 + * PCI Target Control Register
5582 + *
5583 + ******************************************************************************/
5584 +enum
5585 +{
5586 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
5587 +       PCITC_rtimer_m          = 0x000000ff,
5588 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
5589 +       PCITC_dtimer_m          = 0x0000ff00,
5590 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
5591 +       PCITC_rdr_m             = 0x00040000,
5592 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
5593 +       PCITC_ddt_m             = 0x00080000,
5594 +} ;
5595 +/*******************************************************************************
5596 + *
5597 + * PCI messaging unit [applies to both inbound and outbound registers ]
5598 + *
5599 + ******************************************************************************/
5600 +enum
5601 +{
5602 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5603 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
5604 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5605 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
5606 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5607 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
5608 +};
5609 +
5610 +
5611 +#endif // __IDT_RC32365_PCI_H__
5612 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
5613 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h    1970-01-01 01:00:00.000000000 +0100
5614 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h       2006-06-18 12:44:28.000000000 +0200
5615 @@ -0,0 +1,217 @@
5616 +/**************************************************************************
5617 + *
5618 + *  BRIEF MODULE DESCRIPTION
5619 + *   PCI header values for IDT 79EB365/336
5620 + *
5621 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5622 + *
5623 + *  This program is free software; you can redistribute  it and/or modify it
5624 + *  under  the terms of  the GNU General  Public License as published by the
5625 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5626 + *  option) any later version.
5627 + *
5628 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5629 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5630 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5631 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5632 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5633 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5634 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5635 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5636 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5637 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5638 + *
5639 + *  You should have received a copy of the  GNU General Public License along
5640 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5641 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5642 + *
5643 + *
5644 + **************************************************************************
5645 + * May 2004 P. Sadik.
5646 + *
5647 + * Initial Release
5648 + *
5649 + *
5650 + *
5651 + **************************************************************************
5652 + */
5653 +
5654 +#ifndef __IDT_RC32365_PCI_V_H__
5655 +#define __IDT_RC32365_PCI_V_H__
5656 +
5657 +
5658 +#define PCI_MSG_VirtualAddress 0xB806C010
5659 +#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
5660 +#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
5661 +
5662 +#define PCIM_SHFT              0x6
5663 +#define PCIM_BIT_LEN           0x7
5664 +#define PCIM_H_EA              0x3
5665 +#define PCIM_H_IA_FIX          0x4
5666 +#define PCIM_H_IA_RR           0x5
5667 +
5668 +#define PCI_ADDR_START         0x50000000
5669 +
5670 +#define CPUTOPCI_MEM_WIN       0x02000000
5671 +#define CPUTOPCI_IO_WIN                0x00100000
5672 +#define PCILBA_SIZE_SHFT       2
5673 +#define PCILBA_SIZE_MASK       0x1F
5674 +#define SIZE_256MB             0x1C
5675 +#define SIZE_128MB             0x1B
5676 +#define SIZE_64MB               0x1A
5677 +#define SIZE_32MB              0x19
5678 +#define SIZE_16MB               0x18
5679 +#define SIZE_4MB               0x16
5680 +#define SIZE_2MB               0x15
5681 +#define SIZE_1MB               0x14
5682 +#define CEDAR_CONFIG0_ADDR     0x80000000
5683 +#define CEDAR_CONFIG1_ADDR     0x80000004
5684 +#define CEDAR_CONFIG2_ADDR     0x80000008
5685 +#define CEDAR_CONFIG3_ADDR     0x8000000C
5686 +#define CEDAR_CONFIG4_ADDR     0x80000010
5687 +#define CEDAR_CONFIG5_ADDR     0x80000014
5688 +#define CEDAR_CONFIG6_ADDR     0x80000018
5689 +#define CEDAR_CONFIG7_ADDR     0x8000001C
5690 +#define CEDAR_CONFIG8_ADDR     0x80000020
5691 +#define CEDAR_CONFIG9_ADDR     0x80000024
5692 +#define CEDAR_CONFIG10_ADDR    0x80000028
5693 +#define CEDAR_CONFIG11_ADDR    0x8000002C
5694 +#define CEDAR_CONFIG12_ADDR    0x80000030
5695 +#define CEDAR_CONFIG13_ADDR    0x80000034
5696 +#define CEDAR_CONFIG14_ADDR    0x80000038
5697 +#define CEDAR_CONFIG15_ADDR    0x8000003C
5698 +#define CEDAR_CONFIG16_ADDR    0x80000040
5699 +#define CEDAR_CONFIG17_ADDR    0x80000044
5700 +#define CEDAR_CONFIG18_ADDR    0x80000048
5701 +#define CEDAR_CONFIG19_ADDR    0x8000004C
5702 +#define CEDAR_CONFIG20_ADDR    0x80000050
5703 +#define CEDAR_CONFIG21_ADDR    0x80000054
5704 +#define CEDAR_CONFIG22_ADDR    0x80000058
5705 +#define CEDAR_CONFIG23_ADDR    0x8000005C
5706 +#define CEDAR_CONFIG24_ADDR    0x80000060
5707 +#define CEDAR_CONFIG25_ADDR    0x80000064
5708 +#define CEDAR_CMD             (PCFG04_command_ioena_m  | \
5709 +                               PCFG04_command_memena_m | \
5710 +                               PCFG04_command_bmena_m  | \
5711 +                               PCFG04_command_mwinv_m  | \
5712 +                               PCFG04_command_parena_m | \
5713 +                               PCFG04_command_serrena_m )
5714 +
5715 +#define CEDAR_STAT            (PCFG04_status_mdpe_m | \
5716 +                               PCFG04_status_sta_m  | \
5717 +                               PCFG04_status_rta_m  | \
5718 +                               PCFG04_status_rma_m  | \
5719 +                               PCFG04_status_sse_m  | \
5720 +                               PCFG04_status_pe_m)
5721 +
5722 +#define CEDAR_CNFG1          ((CEDAR_STAT << 16) | \
5723 +                                CEDAR_CMD)
5724 +
5725 +#define CEDAR_REVID            0
5726 +#define CEDAR_CLASS_CODE       0
5727 +#define CEDAR_CNFG2          ((CEDAR_CLASS_CODE << 8) | \
5728 +                               CEDAR_REVID)
5729 +
5730 +#define CEDAR_CACHE_LINE_SIZE  4
5731 +#define CEDAR_MASTER_LAT       0x3c
5732 +#define CEDAR_HEADER_TYPE      0
5733 +#define CEDAR_BIST             0
5734 +
5735 +#define CEDAR_CNFG3           ((CEDAR_BIST        << 24) | \
5736 +                              (CEDAR_HEADER_TYPE << 16) | \
5737 +                              (CEDAR_MASTER_LAT  <<  8) | \
5738 +                               CEDAR_CACHE_LINE_SIZE)
5739 +
5740 +#define CEDAR_BAR0             0x00000008 /* 128 MB Memory */
5741 +#define CEDAR_BAR1             0x18800001 /* 1 MB IO */
5742 +#define CEDAR_BAR2             0x18000001 /* 2 MB IO window for Cedar
5743 +                                             internal Registers */
5744 +#define CEDAR_BAR3             0x48000008 /* Spare 128 MB Memory */
5745 +
5746 +#define CEDAR_CNFG4            CEDAR_BAR0
5747 +#define CEDAR_CNFG5             CEDAR_BAR1
5748 +#define CEDAR_CNFG6            CEDAR_BAR2
5749 +#define CEDAR_CNFG7            CEDAR_BAR3
5750 +
5751 +#define CEDAR_SUBSYS_VENDOR_ID  0
5752 +#define CEDAR_SUBSYSTEM_ID     0
5753 +#define CEDAR_CNFG8            0
5754 +#define CEDAR_CNFG9            0
5755 +#define CEDAR_CNFG10           0
5756 +#define CEDAR_CNFG11         ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
5757 +                               CEDAR_SUBSYSTEM_ID)
5758 +#define CEDAR_INT_LINE         1
5759 +#define CEDAR_INT_PIN          1
5760 +#define CEDAR_MIN_GNT          8
5761 +#define CEDAR_MAX_LAT          0x38
5762 +#define CEDAR_CNFG12           0
5763 +#define CEDAR_CNFG13           0
5764 +#define CEDAR_CNFG14           0
5765 +#define CEDAR_CNFG15         ((CEDAR_MAX_LAT << 24) | \
5766 +                              (CEDAR_MIN_GNT << 16) | \
5767 +                              (CEDAR_INT_PIN <<  8) | \
5768 +                               CEDAR_INT_LINE)
5769 +#define        CEDAR_RETRY_LIMIT       0x80
5770 +#define CEDAR_TRDY_LIMIT       0x80
5771 +#define CEDAR_CNFG16          ((CEDAR_RETRY_LIMIT << 8) | \
5772 +                               CEDAR_TRDY_LIMIT)
5773 +#define PCI_PBAxC_R            0x0
5774 +#define PCI_PBAxC_RL           0x1
5775 +#define PCI_PBAxC_RM           0x2
5776 +#define SIZE_SHFT              2
5777 +#ifdef __MIPSEB__
5778 +#define CEDAR_PBA0C           (((1 & 0x3) << PCIPBAC_mr_b) | \
5779 +                               PCIPBAC_pp_m | \
5780 +                               PCIPBAC_sb_m | \
5781 +                              (SIZE_128MB << SIZE_SHFT) | \
5782 +                               PCIPBAC_p_m)
5783 +#else
5784 +
5785 +#define CEDAR_PBA0C           (((1 & 0x3) << PCIPBAC_mr_b) | \
5786 +                               PCIPBAC_pp_m | \
5787 +                              (SIZE_128MB << SIZE_SHFT) | \
5788 +                               PCIPBAC_p_m)
5789 +#endif
5790 +#define CEDAR_CNFG17           CEDAR_PBA0C
5791 +#define CEDAR_PBA0M            0x0
5792 +#define CEDAR_CNFG18           CEDAR_PBA0M
5793 +
5794 +#ifdef __MIPSEB__
5795 +#define CEDAR_PBA1C          ((SIZE_1MB << SIZE_SHFT) | \
5796 +                               PCIPBAC_sb_m | \
5797 +                               PCIPBAC_msi_m)
5798 +#else
5799 +#define CEDAR_PBA1C          ((SIZE_1MB << SIZE_SHFT) | \
5800 +                               PCIPBAC_msi_m)
5801 +#endif
5802 +#define CEDAR_CNFG19           CEDAR_PBA1C
5803 +#define CEDAR_PBA1M            0x0
5804 +#define CEDAR_CNFG20           CEDAR_PBA1M
5805 +
5806 +#ifdef __MIPSEB__
5807 +#define CEDAR_PBA2C          ((SIZE_2MB << SIZE_SHFT) |  \
5808 +                               PCIPBAC_sb_m | \
5809 +                               PCIPBAC_msi_m)
5810 +#else
5811 +#define CEDAR_PBA2C          ((SIZE_2MB << SIZE_SHFT) |  \
5812 +                               PCIPBAC_msi_m)
5813 +#endif
5814 +
5815 +#define CEDAR_CNFG21           CEDAR_PBA2C
5816 +#define CEDAR_PBA2M            0x18000000
5817 +#define CEDAR_CNFG22           CEDAR_PBA2M
5818 +
5819 +#ifdef __MIPSEB__
5820 +#define CEDAR_PBA3C            PCIPBAC_sb_m
5821 +#else
5822 +#define CEDAR_PBA3C            0
5823 +#endif
5824 +
5825 +#define CEDAR_CNFG23           CEDAR_PBA3C
5826 +#define CEDAR_PBA3M            0
5827 +#define CEDAR_CNFG24           CEDAR_PBA3M
5828 +
5829 +#define        PCITC_DTIMER_VAL        8
5830 +#define PCITC_RTIMER_VAL       0x10
5831 +
5832 +#endif //__IDT_RC32365_PCI_V_H__
5833 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
5834 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma.h      1970-01-01 01:00:00.000000000 +0100
5835 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 2006-06-18 12:44:28.000000000 +0200
5836 @@ -0,0 +1,205 @@
5837 +/**************************************************************************
5838 + *
5839 + *  BRIEF MODULE DESCRIPTION
5840 + *   DMA register definition
5841 + *
5842 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5843 + *
5844 + *  This program is free software; you can redistribute  it and/or modify it
5845 + *  under  the terms of  the GNU General  Public License as published by the
5846 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5847 + *  option) any later version.
5848 + *
5849 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5850 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5851 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5852 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5853 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5854 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5855 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5856 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5857 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5858 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5859 + *
5860 + *  You should have received a copy of the  GNU General Public License along
5861 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5862 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5863 + *
5864 + *
5865 + **************************************************************************
5866 + * May 2004 rkt, neb
5867 + *
5868 + * Initial Release
5869 + *
5870 + *
5871 + *
5872 + **************************************************************************
5873 + */
5874 +
5875 +#ifndef __IDT_DMA_H__
5876 +#define __IDT_DMA_H__
5877 +
5878 +enum
5879 +{
5880 +       DMA0_PhysicalAddress    = 0x18040000,
5881 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
5882 +
5883 +       DMA0_VirtualAddress     = 0xb8040000,
5884 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
5885 +} ;
5886 +
5887 +/*
5888 + * DMA descriptor (in physical memory).
5889 + */
5890 +
5891 +typedef struct DMAD_s
5892 +{
5893 +       u32                     control ;       // Control. use DMAD_*
5894 +       u32                     ca ;            // Current Address.
5895 +       u32                     devcs ;         // Device control and status.
5896 +       u32                     link ;          // Next descriptor in chain.
5897 +} volatile *DMAD_t ;
5898 +
5899 +enum
5900 +{
5901 +       DMAD_size               = sizeof (struct DMAD_s),
5902 +       DMAD_count_b            = 0,            // in DMAD_t -> control
5903 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
5904 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
5905 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
5906 +               DMAD_ds_ethRcv0_v       = 0,
5907 +               DMAD_ds_ethXmt0_v       = 0,
5908 +               DMAD_ds_memToFifo_v     = 0,
5909 +               DMAD_ds_fifoToMem_v     = 0,
5910 +               DMAD_ds_pciToMem_v      = 0,
5911 +               DMAD_ds_memToPci_v      = 0,
5912 +
5913 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
5914 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
5915 +               DMAD_devcmd_byte_v      = 0,    //memory-to-memory
5916 +               DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
5917 +               DMAD_devcmd_word_v      = 2,    //memory-to-memory
5918 +               DMAD_devcmd_2words_v    = 3,    //memory-to-memory
5919 +               DMAD_devcmd_4words_v    = 4,    //memory-to-memory
5920 +               DMAD_devcmd_6words_v    = 5,    //memory-to-memory
5921 +               DMAD_devcmd_8words_v    = 6,    //memory-to-memory
5922 +               DMAD_devcmd_16words_v   = 7,    //memory-to-memory
5923 +       DMAD_cof_b              = 25,           // chain on finished
5924 +       DMAD_cof_m              = 0x02000000,   //
5925 +       DMAD_cod_b              = 26,           // chain on done
5926 +       DMAD_cod_m              = 0x04000000,   //
5927 +       DMAD_iof_b              = 27,           // interrupt on finished
5928 +       DMAD_iof_m              = 0x08000000,   //
5929 +       DMAD_iod_b              = 28,           // interrupt on done
5930 +       DMAD_iod_m              = 0x10000000,   //
5931 +       DMAD_t_b                = 29,           // terminated
5932 +       DMAD_t_m                = 0x20000000,   //
5933 +       DMAD_d_b                = 30,           // done
5934 +       DMAD_d_m                = 0x40000000,   //
5935 +       DMAD_f_b                = 31,           // finished
5936 +       DMAD_f_m                = 0x80000000,   //
5937 +} ;
5938 +
5939 +/*
5940 + * DMA register (within Internal Register Map).
5941 + */
5942 +
5943 +struct DMA_Chan_s
5944 +{
5945 +       u32             dmac ;          // Control.
5946 +       u32             dmas ;          // Status.
5947 +       u32             dmasm ;         // Mask.
5948 +       u32             dmadptr ;       // Descriptor pointer.
5949 +       u32             dmandptr ;      // Next descriptor pointer.
5950 +};
5951 +
5952 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
5953 +
5954 +//DMA_Channels   use DMACH_count instead
5955 +
5956 +enum
5957 +{
5958 +       DMAC_run_b      = 0,            //
5959 +       DMAC_run_m      = 0x00000001,   //
5960 +       DMAC_dm_b       = 1,            // done mask
5961 +       DMAC_dm_m       = 0x00000002,   //
5962 +       DMAC_mode_b     = 2,            //
5963 +       DMAC_mode_m     = 0x0000000c,   //
5964 +               DMAC_mode_auto_v        = 0,
5965 +               DMAC_mode_burst_v       = 1,
5966 +               DMAC_mode_transfer_v    = 2, //usually used
5967 +               DMAC_mode_reserved_v    = 3,
5968 +       DMAC_a_b        = 4,            //
5969 +       DMAC_a_m        = 0x00000010,   //
5970 +
5971 +       DMAS_f_b        = 0,            // finished (sticky)
5972 +       DMAS_f_m        = 0x00000001,   //
5973 +       DMAS_d_b        = 1,            // done (sticky)
5974 +       DMAS_d_m        = 0x00000002,   //
5975 +       DMAS_c_b        = 2,            // chain (sticky)
5976 +       DMAS_c_m        = 0x00000004,   //
5977 +       DMAS_e_b        = 3,            // error (sticky)
5978 +       DMAS_e_m        = 0x00000008,   //
5979 +       DMAS_h_b        = 4,            // halt (sticky)
5980 +       DMAS_h_m        = 0x00000010,   //
5981 +
5982 +       DMASM_f_b       = 0,            // finished (1=mask)
5983 +       DMASM_f_m       = 0x00000001,   //
5984 +       DMASM_d_b       = 1,            // done (1=mask)
5985 +       DMASM_d_m       = 0x00000002,   //
5986 +       DMASM_c_b       = 2,            // chain (1=mask)
5987 +       DMASM_c_m       = 0x00000004,   //
5988 +       DMASM_e_b       = 3,            // error (1=mask)
5989 +       DMASM_e_m       = 0x00000008,   //
5990 +       DMASM_h_b       = 4,            // halt (1=mask)
5991 +       DMASM_h_m       = 0x00000010,   //
5992 +} ;
5993 +
5994 +/*
5995 + * DMA channel definitions
5996 + */
5997 +
5998 +enum
5999 +{
6000 +       DMACH_ethRcv0 = 0,
6001 +       DMACH_ethXmt0 = 1,
6002 +       DMACH_memToFifo = 2,
6003 +       DMACH_fifoToMem = 3,
6004 +       DMACH_pciToMem = 4,
6005 +       DMACH_memToPci = 5,
6006 +
6007 +       DMACH_count //must be last
6008 +};
6009 +
6010 +
6011 +typedef struct DMAC_s
6012 +{
6013 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
6014 +} volatile *DMA_t ;
6015 +
6016 +
6017 +/*
6018 + * External DMA parameters
6019 +*/
6020 +
6021 +enum
6022 +{
6023 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
6024 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
6025 +               DMADEVCMD_ts_byte_v     = 0,
6026 +               DMADEVCMD_ts_halfword_v = 1,
6027 +               DMADEVCMD_ts_word_v     = 2,
6028 +               DMADEVCMD_ts_2word_v    = 3,
6029 +               DMADEVCMD_ts_4word_v    = 4,
6030 +               DMADEVCMD_ts_6word_v    = 5,
6031 +               DMADEVCMD_ts_8word_v    = 6,
6032 +               DMADEVCMD_ts_16word_v   = 7
6033 +};
6034 +
6035 +
6036 +#endif // __IDT_DMA_H__
6037 +
6038 +
6039 +
6040 +
6041 +
6042 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
6043 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h    1970-01-01 01:00:00.000000000 +0100
6044 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h       2006-06-18 12:44:28.000000000 +0200
6045 @@ -0,0 +1,89 @@
6046 +/**************************************************************************
6047 + *
6048 + *  BRIEF MODULE DESCRIPTION
6049 + *   Definitions for DMA controller.
6050 + *
6051 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6052 + *
6053 + *  This program is free software; you can redistribute  it and/or modify it
6054 + *  under  the terms of  the GNU General  Public License as published by the
6055 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6056 + *  option) any later version.
6057 + *
6058 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6059 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6060 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6061 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6062 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6063 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6064 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6065 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6066 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6067 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6068 + *
6069 + *  You should have received a copy of the  GNU General Public License along
6070 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6071 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6072 + *
6073 + *
6074 + **************************************************************************
6075 + * May 2004 rkt, neb.
6076 + *
6077 + * Initial Release
6078 + *
6079 + *
6080 + *
6081 + **************************************************************************
6082 + */
6083 +
6084 +#ifndef __IDT_DMA_V_H__
6085 +#define __IDT_DMA_V_H__
6086 +
6087 +#include  <asm/idt-boards/rc32434/rc32434_dma.h>
6088 +#include  <asm/idt-boards/rc32434/rc32434.h>
6089 +
6090 +#define DMA_CHAN_OFFSET  0x14
6091 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
6092 +#define DMA_COUNT(count)   \
6093 +  ((count) & DMAD_count_m)
6094 +
6095 +#define DMA_HALT_TIMEOUT 500
6096 +
6097 +
6098 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
6099 +{
6100 +       int timeout=1;
6101 +       if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
6102 +               rc32434_writel(0, &ch->dmac);
6103 +
6104 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
6105 +                       if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
6106 +                               rc32434_writel(0, &ch->dmas);
6107 +                               break;
6108 +                       }
6109 +               }
6110 +
6111 +       }
6112 +
6113 +       return timeout ? 0 : 1;
6114 +}
6115 +
6116 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
6117 +{
6118 +       rc32434_writel(0, &ch->dmandptr);
6119 +       rc32434_writel(dma_addr, &ch->dmadptr);
6120 +}
6121 +
6122 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
6123 +{
6124 +       rc32434_writel(dma_addr, &ch->dmandptr);
6125 +}
6126 +
6127 +#endif // __IDT_DMA_V_H__
6128 +
6129 +
6130 +
6131 +
6132 +
6133 +
6134 +
6135 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
6136 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth.h      1970-01-01 01:00:00.000000000 +0100
6137 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
6138 @@ -0,0 +1,333 @@
6139 +/**************************************************************************
6140 + *
6141 + *  BRIEF MODULE DESCRIPTION
6142 + *   Ethernet register definition
6143 + *
6144 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6145 + *
6146 + *  This program is free software; you can redistribute  it and/or modify it
6147 + *  under  the terms of  the GNU General  Public License as published by the
6148 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6149 + *  option) any later version.
6150 + *
6151 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6152 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6153 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6154 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6155 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6156 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6157 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6158 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6159 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6160 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6161 + *
6162 + *  You should have received a copy of the  GNU General Public License along
6163 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6164 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6165 + *
6166 + *
6167 + **************************************************************************
6168 + * May 2004 rkt, neb.
6169 + *
6170 + * Initial Release
6171 + *
6172 + *
6173 + *
6174 + **************************************************************************
6175 + */
6176 +
6177 +#ifndef        __IDT_ETH_H__
6178 +#define        __IDT_ETH_H__
6179 +
6180 +
6181 +enum
6182 +{
6183 +       ETH0_PhysicalAddress    = 0x18060000,
6184 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
6185 +
6186 +       ETH0_VirtualAddress     = 0xb8060000,
6187 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
6188 +} ;
6189 +
6190 +typedef struct
6191 +{
6192 +       u32 ethintfc            ;
6193 +       u32 ethfifott           ;
6194 +       u32 etharc              ;
6195 +       u32 ethhash0            ;
6196 +       u32 ethhash1            ;
6197 +       u32 ethu0 [4]           ;       // Reserved.
6198 +       u32 ethpfs              ;
6199 +       u32 ethmcp              ;
6200 +       u32 eth_u1 [10]         ;       // Reserved.
6201 +       u32 ethspare            ;
6202 +       u32 eth_u2 [42]         ;       // Reserved.
6203 +       u32 ethsal0             ;
6204 +       u32 ethsah0             ;
6205 +       u32 ethsal1             ;
6206 +       u32 ethsah1             ;
6207 +       u32 ethsal2             ;
6208 +       u32 ethsah2             ;
6209 +       u32 ethsal3             ;
6210 +       u32 ethsah3             ;
6211 +       u32 ethrbc              ;
6212 +       u32 ethrpc              ;
6213 +       u32 ethrupc             ;
6214 +       u32 ethrfc              ;
6215 +       u32 ethtbc              ;
6216 +       u32 ethgpf              ;
6217 +       u32 eth_u9 [50]         ;       // Reserved.
6218 +       u32 ethmac1             ;
6219 +       u32 ethmac2             ;
6220 +       u32 ethipgt             ;
6221 +       u32 ethipgr             ;
6222 +       u32 ethclrt             ;
6223 +       u32 ethmaxf             ;
6224 +       u32 eth_u10             ;       // Reserved.
6225 +       u32 ethmtest            ;
6226 +       u32 miimcfg             ;
6227 +       u32 miimcmd             ;
6228 +       u32 miimaddr            ;
6229 +       u32 miimwtd             ;
6230 +       u32 miimrdd             ;
6231 +       u32 miimind             ;
6232 +       u32 eth_u11             ;       // Reserved.
6233 +       u32 eth_u12             ;       // Reserved.
6234 +       u32 ethcfsa0            ;
6235 +       u32 ethcfsa1            ;
6236 +       u32 ethcfsa2            ;
6237 +} volatile *ETH_t;
6238 +
6239 +enum
6240 +{
6241 +       ETHINTFC_en_b           = 0,
6242 +       ETHINTFC_en_m           = 0x00000001,
6243 +       ETHINTFC_its_b          = 1,
6244 +       ETHINTFC_its_m          = 0x00000002,
6245 +       ETHINTFC_rip_b          = 2,
6246 +       ETHINTFC_rip_m          = 0x00000004,
6247 +       ETHINTFC_jam_b          = 3,
6248 +       ETHINTFC_jam_m          = 0x00000008,
6249 +       ETHINTFC_ovr_b          = 4,
6250 +       ETHINTFC_ovr_m          = 0x00000010,
6251 +       ETHINTFC_und_b          = 5,
6252 +       ETHINTFC_und_m          = 0x00000020,
6253 +
6254 +       ETHFIFOTT_tth_b         = 0,
6255 +       ETHFIFOTT_tth_m         = 0x0000007f,
6256 +
6257 +       ETHARC_pro_b            = 0,
6258 +       ETHARC_pro_m            = 0x00000001,
6259 +       ETHARC_am_b             = 1,
6260 +       ETHARC_am_m             = 0x00000002,
6261 +       ETHARC_afm_b            = 2,
6262 +       ETHARC_afm_m            = 0x00000004,
6263 +       ETHARC_ab_b             = 3,
6264 +       ETHARC_ab_m             = 0x00000008,
6265 +
6266 +       ETHSAL_byte5_b          = 0,
6267 +       ETHSAL_byte5_m          = 0x000000ff,
6268 +       ETHSAL_byte4_b          = 8,
6269 +       ETHSAL_byte4_m          = 0x0000ff00,
6270 +       ETHSAL_byte3_b          = 16,
6271 +       ETHSAL_byte3_m          = 0x00ff0000,
6272 +       ETHSAL_byte2_b          = 24,
6273 +       ETHSAL_byte2_m          = 0xff000000,
6274 +
6275 +       ETHSAH_byte1_b          = 0,
6276 +       ETHSAH_byte1_m          = 0x000000ff,
6277 +       ETHSAH_byte0_b          = 8,
6278 +       ETHSAH_byte0_m          = 0x0000ff00,
6279 +
6280 +       ETHGPF_ptv_b            = 0,
6281 +       ETHGPF_ptv_m            = 0x0000ffff,
6282 +
6283 +       ETHPFS_pfd_b            = 0,
6284 +       ETHPFS_pfd_m            = 0x00000001,
6285 +
6286 +       ETHCFSA0_cfsa4_b        = 0,
6287 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
6288 +       ETHCFSA0_cfsa5_b        = 8,
6289 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
6290 +
6291 +       ETHCFSA1_cfsa2_b        = 0,
6292 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
6293 +       ETHCFSA1_cfsa3_b        = 8,
6294 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
6295 +
6296 +       ETHCFSA2_cfsa0_b        = 0,
6297 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
6298 +       ETHCFSA2_cfsa1_b        = 8,
6299 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
6300 +
6301 +       ETHMAC1_re_b            = 0,
6302 +       ETHMAC1_re_m            = 0x00000001,
6303 +       ETHMAC1_paf_b           = 1,
6304 +       ETHMAC1_paf_m           = 0x00000002,
6305 +       ETHMAC1_rfc_b           = 2,
6306 +       ETHMAC1_rfc_m           = 0x00000004,
6307 +       ETHMAC1_tfc_b           = 3,
6308 +       ETHMAC1_tfc_m           = 0x00000008,
6309 +       ETHMAC1_lb_b            = 4,
6310 +       ETHMAC1_lb_m            = 0x00000010,
6311 +       ETHMAC1_mr_b            = 31,
6312 +       ETHMAC1_mr_m            = 0x80000000,
6313 +
6314 +       ETHMAC2_fd_b            = 0,
6315 +       ETHMAC2_fd_m            = 0x00000001,
6316 +       ETHMAC2_flc_b           = 1,
6317 +       ETHMAC2_flc_m           = 0x00000002,
6318 +       ETHMAC2_hfe_b           = 2,
6319 +       ETHMAC2_hfe_m           = 0x00000004,
6320 +       ETHMAC2_dc_b            = 3,
6321 +       ETHMAC2_dc_m            = 0x00000008,
6322 +       ETHMAC2_cen_b           = 4,
6323 +       ETHMAC2_cen_m           = 0x00000010,
6324 +       ETHMAC2_pe_b            = 5,
6325 +       ETHMAC2_pe_m            = 0x00000020,
6326 +       ETHMAC2_vpe_b           = 6,
6327 +       ETHMAC2_vpe_m           = 0x00000040,
6328 +       ETHMAC2_ape_b           = 7,
6329 +       ETHMAC2_ape_m           = 0x00000080,
6330 +       ETHMAC2_ppe_b           = 8,
6331 +       ETHMAC2_ppe_m           = 0x00000100,
6332 +       ETHMAC2_lpe_b           = 9,
6333 +       ETHMAC2_lpe_m           = 0x00000200,
6334 +       ETHMAC2_nb_b            = 12,
6335 +       ETHMAC2_nb_m            = 0x00001000,
6336 +       ETHMAC2_bp_b            = 13,
6337 +       ETHMAC2_bp_m            = 0x00002000,
6338 +       ETHMAC2_ed_b            = 14,
6339 +       ETHMAC2_ed_m            = 0x00004000,
6340 +
6341 +       ETHIPGT_ipgt_b          = 0,
6342 +       ETHIPGT_ipgt_m          = 0x0000007f,
6343 +
6344 +       ETHIPGR_ipgr2_b         = 0,
6345 +       ETHIPGR_ipgr2_m         = 0x0000007f,
6346 +       ETHIPGR_ipgr1_b         = 8,
6347 +       ETHIPGR_ipgr1_m         = 0x00007f00,
6348 +
6349 +       ETHCLRT_maxret_b        = 0,
6350 +       ETHCLRT_maxret_m        = 0x0000000f,
6351 +       ETHCLRT_colwin_b        = 8,
6352 +       ETHCLRT_colwin_m        = 0x00003f00,
6353 +
6354 +       ETHMAXF_maxf_b          = 0,
6355 +       ETHMAXF_maxf_m          = 0x0000ffff,
6356 +
6357 +       ETHMTEST_tb_b           = 2,
6358 +       ETHMTEST_tb_m           = 0x00000004,
6359 +
6360 +       ETHMCP_div_b            = 0,
6361 +       ETHMCP_div_m            = 0x000000ff,
6362 +
6363 +       MIIMCFG_rsv_b           = 0,
6364 +       MIIMCFG_rsv_m           = 0x0000000c,
6365 +
6366 +       MIIMCMD_rd_b            = 0,
6367 +       MIIMCMD_rd_m            = 0x00000001,
6368 +       MIIMCMD_scn_b           = 1,
6369 +       MIIMCMD_scn_m           = 0x00000002,
6370 +
6371 +       MIIMADDR_regaddr_b      = 0,
6372 +       MIIMADDR_regaddr_m      = 0x0000001f,
6373 +       MIIMADDR_phyaddr_b      = 8,
6374 +       MIIMADDR_phyaddr_m      = 0x00001f00,
6375 +
6376 +       MIIMWTD_wdata_b         = 0,
6377 +       MIIMWTD_wdata_m         = 0x0000ffff,
6378 +
6379 +       MIIMRDD_rdata_b         = 0,
6380 +       MIIMRDD_rdata_m         = 0x0000ffff,
6381 +
6382 +       MIIMIND_bsy_b           = 0,
6383 +       MIIMIND_bsy_m           = 0x00000001,
6384 +       MIIMIND_scn_b           = 1,
6385 +       MIIMIND_scn_m           = 0x00000002,
6386 +       MIIMIND_nv_b            = 2,
6387 +       MIIMIND_nv_m            = 0x00000004,
6388 +
6389 +} ;
6390 +
6391 +/*
6392 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
6393 + */
6394 +enum
6395 +{
6396 +       ETHRX_fd_b              = 0,
6397 +       ETHRX_fd_m              = 0x00000001,
6398 +       ETHRX_ld_b              = 1,
6399 +       ETHRX_ld_m              = 0x00000002,
6400 +       ETHRX_rok_b             = 2,
6401 +       ETHRX_rok_m             = 0x00000004,
6402 +       ETHRX_fm_b              = 3,
6403 +       ETHRX_fm_m              = 0x00000008,
6404 +       ETHRX_mp_b              = 4,
6405 +       ETHRX_mp_m              = 0x00000010,
6406 +       ETHRX_bp_b              = 5,
6407 +       ETHRX_bp_m              = 0x00000020,
6408 +       ETHRX_vlt_b             = 6,
6409 +       ETHRX_vlt_m             = 0x00000040,
6410 +       ETHRX_cf_b              = 7,
6411 +       ETHRX_cf_m              = 0x00000080,
6412 +       ETHRX_ovr_b             = 8,
6413 +       ETHRX_ovr_m             = 0x00000100,
6414 +       ETHRX_crc_b             = 9,
6415 +       ETHRX_crc_m             = 0x00000200,
6416 +       ETHRX_cv_b              = 10,
6417 +       ETHRX_cv_m              = 0x00000400,
6418 +       ETHRX_db_b              = 11,
6419 +       ETHRX_db_m              = 0x00000800,
6420 +       ETHRX_le_b              = 12,
6421 +       ETHRX_le_m              = 0x00001000,
6422 +       ETHRX_lor_b             = 13,
6423 +       ETHRX_lor_m             = 0x00002000,
6424 +       ETHRX_ces_b             = 14,
6425 +       ETHRX_ces_m             = 0x00004000,
6426 +       ETHRX_length_b          = 16,
6427 +       ETHRX_length_m          = 0xffff0000,
6428 +
6429 +       ETHTX_fd_b              = 0,
6430 +       ETHTX_fd_m              = 0x00000001,
6431 +       ETHTX_ld_b              = 1,
6432 +       ETHTX_ld_m              = 0x00000002,
6433 +       ETHTX_oen_b             = 2,
6434 +       ETHTX_oen_m             = 0x00000004,
6435 +       ETHTX_pen_b             = 3,
6436 +       ETHTX_pen_m             = 0x00000008,
6437 +       ETHTX_cen_b             = 4,
6438 +       ETHTX_cen_m             = 0x00000010,
6439 +       ETHTX_hen_b             = 5,
6440 +       ETHTX_hen_m             = 0x00000020,
6441 +       ETHTX_tok_b             = 6,
6442 +       ETHTX_tok_m             = 0x00000040,
6443 +       ETHTX_mp_b              = 7,
6444 +       ETHTX_mp_m              = 0x00000080,
6445 +       ETHTX_bp_b              = 8,
6446 +       ETHTX_bp_m              = 0x00000100,
6447 +       ETHTX_und_b             = 9,
6448 +       ETHTX_und_m             = 0x00000200,
6449 +       ETHTX_of_b              = 10,
6450 +       ETHTX_of_m              = 0x00000400,
6451 +       ETHTX_ed_b              = 11,
6452 +       ETHTX_ed_m              = 0x00000800,
6453 +       ETHTX_ec_b              = 12,
6454 +       ETHTX_ec_m              = 0x00001000,
6455 +       ETHTX_lc_b              = 13,
6456 +       ETHTX_lc_m              = 0x00002000,
6457 +       ETHTX_td_b              = 14,
6458 +       ETHTX_td_m              = 0x00004000,
6459 +       ETHTX_crc_b             = 15,
6460 +       ETHTX_crc_m             = 0x00008000,
6461 +       ETHTX_le_b              = 16,
6462 +       ETHTX_le_m              = 0x00010000,
6463 +       ETHTX_cc_b              = 17,
6464 +       ETHTX_cc_m              = 0x001E0000,
6465 +} ;
6466 +
6467 +#endif // __IDT_ETH_H__
6468 +
6469 +
6470 +
6471 +
6472 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
6473 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h    1970-01-01 01:00:00.000000000 +0100
6474 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h       2006-06-18 12:44:28.000000000 +0200
6475 @@ -0,0 +1,77 @@
6476 +/**************************************************************************
6477 + *
6478 + *  BRIEF MODULE DESCRIPTION
6479 + *   Ethernet register definition
6480 + *
6481 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6482 + *
6483 + *  This program is free software; you can redistribute  it and/or modify it
6484 + *  under  the terms of  the GNU General  Public License as published by the
6485 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6486 + *  option) any later version.
6487 + *
6488 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6489 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6490 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6491 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6492 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6493 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6494 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6495 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6496 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6497 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6498 + *
6499 + *  You should have received a copy of the  GNU General Public License along
6500 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6501 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6502 + *
6503 + *
6504 + **************************************************************************
6505 + * May 2004 rkt, neb.
6506 + *
6507 + * Initial Release
6508 + *
6509 + *
6510 + *
6511 + **************************************************************************
6512 + */
6513 +
6514 +#ifndef        __IDT_ETH_V_H__
6515 +#define        __IDT_ETH_V_H__
6516 +
6517 +#include  <asm/idt-boards/rc32434/rc32434_eth.h>
6518 +
6519 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
6520 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
6521 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
6522 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
6523 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
6524 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
6525 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
6526 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
6527 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
6528 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
6529 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
6530 +
6531 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
6532 +
6533 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
6534 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
6535 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
6536 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
6537 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
6538 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
6539 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
6540 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
6541 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
6542 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
6543 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
6544 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
6545 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
6546 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
6547 +#endif // __IDT_ETH_V_H__
6548 +
6549 +
6550 +
6551 +
6552 +
6553 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
6554 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h     1970-01-01 01:00:00.000000000 +0100
6555 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h        2006-06-18 12:44:28.000000000 +0200
6556 @@ -0,0 +1,167 @@
6557 +/**************************************************************************
6558 + *
6559 + *  BRIEF MODULE DESCRIPTION
6560 + *   GPIO register definition
6561 + *
6562 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6563 + *
6564 + *  This program is free software; you can redistribute  it and/or modify it
6565 + *  under  the terms of  the GNU General  Public License as published by the
6566 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6567 + *  option) any later version.
6568 + *
6569 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6570 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6571 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6572 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6573 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6574 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6575 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6576 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6577 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6578 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6579 + *
6580 + *  You should have received a copy of the  GNU General Public License along
6581 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6582 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6583 + *
6584 + *
6585 + **************************************************************************
6586 + * May 2004 rkt, neb.
6587 + *
6588 + * Initial Release
6589 + *
6590 + *
6591 + *
6592 + **************************************************************************
6593 + */
6594 +
6595 +#ifndef __IDT_GPIO_H__
6596 +#define __IDT_GPIO_H__
6597 +
6598 +enum
6599 +{
6600 +       GPIO0_PhysicalAddress   = 0x18050000,
6601 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
6602 +
6603 +       GPIO0_VirtualAddress    = 0xb8050000,
6604 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
6605 +} ;
6606 +
6607 +typedef struct
6608 +{
6609 +       u32   gpiofunc;   /* GPIO Function Register
6610 +                          * gpiofunc[x]==0 bit = gpio
6611 +                          * func[x]==1  bit = altfunc
6612 +                          */
6613 +       u32   gpiocfg;    /* GPIO Configuration Register
6614 +                          * gpiocfg[x]==0 bit = input
6615 +                          * gpiocfg[x]==1 bit = output
6616 +                          */
6617 +       u32   gpiod;      /* GPIO Data Register
6618 +                          * gpiod[x] read/write gpio pinX status
6619 +                          */
6620 +       u32   gpioilevel; /* GPIO Interrupt Status Register
6621 +                          * interrupt level (see gpioistat)
6622 +                          */
6623 +       u32   gpioistat;  /* Gpio Interrupt Status Register
6624 +                          * istat[x] = (gpiod[x] == level[x])
6625 +                          * cleared in ISR (STICKY bits)
6626 +                          */
6627 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
6628 +} volatile * GPIO_t ;
6629 +
6630 +typedef enum
6631 +{
6632 +       GPIO_gpio_v             = 0,            // gpiofunc use pin as GPIO.
6633 +       GPIO_alt_v              = 1,            // gpiofunc use pin as alt.
6634 +       GPIO_input_v            = 0,            // gpiocfg use pin as input.
6635 +       GPIO_output_v           = 1,            // gpiocfg use pin as output.
6636 +       GPIO_pin0_b             = 0,
6637 +       GPIO_pin0_m             = 0x00000001,
6638 +       GPIO_pin1_b             = 1,
6639 +       GPIO_pin1_m             = 0x00000002,
6640 +       GPIO_pin2_b             = 2,
6641 +       GPIO_pin2_m             = 0x00000004,
6642 +       GPIO_pin3_b             = 3,
6643 +       GPIO_pin3_m             = 0x00000008,
6644 +       GPIO_pin4_b             = 4,
6645 +       GPIO_pin4_m             = 0x00000010,
6646 +       GPIO_pin5_b             = 5,
6647 +       GPIO_pin5_m             = 0x00000020,
6648 +       GPIO_pin6_b             = 6,
6649 +       GPIO_pin6_m             = 0x00000040,
6650 +       GPIO_pin7_b             = 7,
6651 +       GPIO_pin7_m             = 0x00000080,
6652 +       GPIO_pin8_b             = 8,
6653 +       GPIO_pin8_m             = 0x00000100,
6654 +       GPIO_pin9_b             = 9,
6655 +       GPIO_pin9_m             = 0x00000200,
6656 +       GPIO_pin10_b            = 10,
6657 +       GPIO_pin10_m            = 0x00000400,
6658 +       GPIO_pin11_b            = 11,
6659 +       GPIO_pin11_m            = 0x00000800,
6660 +       GPIO_pin12_b            = 12,
6661 +       GPIO_pin12_m            = 0x00001000,
6662 +       GPIO_pin13_b            = 13,
6663 +       GPIO_pin13_m            = 0x00002000,
6664 +
6665 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
6666 +
6667 +       GPIO_u0sout_b           = GPIO_pin0_b,          // UART 0 serial out.
6668 +       GPIO_u0sout_m           = GPIO_pin0_m,
6669 +               GPIO_u0sout_cfg_v       = GPIO_output_v,
6670 +       GPIO_u0sinp_b   = GPIO_pin1_b,                  // UART 0 serial in.
6671 +       GPIO_u0sinp_m   = GPIO_pin1_m,
6672 +               GPIO_u0sinp_cfg_v       = GPIO_input_v,
6673 +       GPIO_u0rtsn_b   = GPIO_pin2_b,                  // UART 0 req. to send.
6674 +       GPIO_u0rtsn_m   = GPIO_pin2_m,
6675 +               GPIO_u0rtsn_cfg_v       = GPIO_output_v,
6676 +       GPIO_u0ctsn_b   = GPIO_pin3_b,                  // UART 0 clear to send.
6677 +       GPIO_u0ctsn_m   = GPIO_pin3_m,
6678 +               GPIO_u0ctsn_cfg_v       = GPIO_input_v,
6679 +
6680 +       GPIO_maddr22_b          = GPIO_pin4_b,  // M&P bus bit 22.
6681 +       GPIO_maddr22_m          = GPIO_pin4_m,
6682 +               GPIO_maddr22_cfg_v      = GPIO_output_v,
6683 +
6684 +       GPIO_maddr23_b          = GPIO_pin5_b,  // M&P bus bit 23.
6685 +       GPIO_maddr23_m          = GPIO_pin5_m,
6686 +               GPIO_maddr23_cfg_v      = GPIO_output_v,
6687 +
6688 +       GPIO_maddr24_b          = GPIO_pin6_b,  // M&P bus bit 24.
6689 +       GPIO_maddr24_m          = GPIO_pin6_m,
6690 +               GPIO_maddr24_cfg_v      = GPIO_output_v,
6691 +
6692 +       GPIO_maddr25_b          = GPIO_pin7_b,  // M&P bus bit 25.
6693 +       GPIO_maddr25_m          = GPIO_pin7_m,
6694 +               GPIO_maddr25_cfg_v      = GPIO_output_v,
6695 +
6696 +       GPIO_cpudmadebug_b      = GPIO_pin8_b,  // CPU or DMA debug pin
6697 +       GPIO_cpudmadebug_m      = GPIO_pin8_m,
6698 +               GPIO_cpudmadebug_cfg_v  = GPIO_output_v,
6699 +
6700 +       GPIO_pcireq4_b  = GPIO_pin9_b,  // PCI Request 4
6701 +       GPIO_pcireq4_m  = GPIO_pin9_m,
6702 +               GPIO_pcireq4_cfg_v      = GPIO_input_v,
6703 +
6704 +       GPIO_pcigrant4_b        = GPIO_pin10_b,         // PCI Grant 4
6705 +       GPIO_pcigrant4_m        = GPIO_pin10_m,
6706 +               GPIO_pcigrant4_cfg_v    = GPIO_output_v,
6707 +
6708 +       GPIO_pcireq5_b  = GPIO_pin11_b,         // PCI Request 5
6709 +       GPIO_pcireq5_m  = GPIO_pin11_m,
6710 +               GPIO_pcireq5_cfg_v      = GPIO_input_v,
6711 +
6712 +       GPIO_pcigrant5_b        = GPIO_pin12_b,         // PCI Grant 5
6713 +       GPIO_pcigrant5_m        = GPIO_pin12_m,
6714 +               GPIO_pcigrant5_cfg_v    = GPIO_output_v,
6715 +
6716 +       GPIO_pcimuintn_b        = GPIO_pin13_b,         // PCI messaging int.
6717 +       GPIO_pcimuintn_m        = GPIO_pin13_m,
6718 +               GPIO_pcimuintn_cfg_v    = GPIO_output_v,
6719 +
6720 +} GPIO_DEFS_t;
6721 +
6722 +#endif // __IDT_GPIO_H__
6723 +
6724 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h
6725 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434.h  1970-01-01 01:00:00.000000000 +0100
6726 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h     2006-06-18 12:44:28.000000000 +0200
6727 @@ -0,0 +1,199 @@
6728 + /**************************************************************************
6729 + *
6730 + *  BRIEF MODULE DESCRIPTION
6731 + *   Definitions for IDT RC32434 CPU
6732 + *
6733 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6734 + *
6735 + *  This program is free software; you can redistribute  it and/or modify it
6736 + *  under  the terms of  the GNU General  Public License as published by the
6737 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6738 + *  option) any later version.
6739 + *
6740 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6741 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6742 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6743 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6744 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6745 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6746 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6747 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6748 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6749 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6750 + *
6751 + *  You should have received a copy of the  GNU General Public License along
6752 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6753 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6754 + *
6755 + *
6756 + **************************************************************************
6757 + * May 2004 rkt, neb.
6758 + *
6759 + * Initial Release
6760 + *
6761 + *
6762 + *
6763 + **************************************************************************
6764 + */
6765 +
6766 +#ifndef _RC32434_H_
6767 +#define _RC32434_H_
6768 +
6769 +#include <linux/autoconf.h>
6770 +#include <linux/delay.h>
6771 +#include <asm/io.h>
6772 +#include <asm/idt-boards/rc32434/rc32434_timer.h>
6773 +
6774 +#define RC32434_REG_BASE   0x18000000
6775 +
6776 +
6777 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
6778 +#define idt_timer     ((volatile TIM_t)  TIM0_VirtualAddress)
6779 +#define idt_gpio         ((volatile GPIO_t) GPIO0_VirtualAddress)
6780 +
6781 +#define IDT_CLOCK_MULT 2
6782 +#define MIPS_CPU_TIMER_IRQ 7
6783 +/* Interrupt Controller */
6784 +#define IC_GROUP0_PEND     (RC32434_REG_BASE + 0x38000)
6785 +#define IC_GROUP0_MASK     (RC32434_REG_BASE + 0x38008)
6786 +#define IC_GROUP_OFFSET    0x0C
6787 +#define RTC_BASE           0xBA001FF0
6788 +
6789 +#define NUM_INTR_GROUPS    5
6790 +/* 16550 UARTs */
6791 +
6792 +#define GROUP0_IRQ_BASE 8              /* GRP2 IRQ numbers start here */
6793 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
6794 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
6795 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
6796 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
6797 +
6798 +#ifdef __MIPSEB__
6799 +
6800 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
6801 +#define EB434_UART1_BASE   (0x19800003)
6802 +
6803 +#else
6804 +
6805 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
6806 +#define EB434_UART1_BASE   (0x19800000)
6807 +
6808 +#endif
6809 +
6810 +#define RC32434_UART0_IRQ  GROUP3_IRQ_BASE + 0
6811 +#define EB434_UART1_IRQ    GROUP4_IRQ_BASE + 11
6812 +
6813 +#define RC32434_NR_IRQS  (GROUP4_IRQ_BASE + 32)
6814 +
6815 +/* cpu pipeline flush */
6816 +static inline void rc32434_sync(void)
6817 +{
6818 +        __asm__ volatile ("sync");
6819 +}
6820 +
6821 +static inline void rc32434_sync_udelay(int us)
6822 +{
6823 +        __asm__ volatile ("sync");
6824 +        udelay(us);
6825 +}
6826 +
6827 +static inline void rc32434_sync_delay(int ms)
6828 +{
6829 +        __asm__ volatile ("sync");
6830 +        mdelay(ms);
6831 +}
6832 +
6833 +
6834 +
6835 +/*
6836 + * Macros to access internal RC32434 registers. No byte
6837 + * swapping should be done when accessing the internal
6838 + * registers.
6839 + */
6840 +
6841 +#define rc32434_readb __raw_readb
6842 +#define rc32434_readw __raw_readw
6843 +#define rc32434_readl __raw_readl
6844 +
6845 +#define rc32434_writeb __raw_writeb
6846 +#define rc32434_writew __raw_writew
6847 +#define rc32434_writel __raw_writel
6848 +
6849 +#if 0
6850 +static inline u8 rc32434_readb(unsigned long pa)
6851 +{
6852 +       return *((volatile u8 *)KSEG1ADDR(pa));
6853 +}
6854 +static inline u16 rc32434_readw(unsigned long pa)
6855 +{
6856 +       return *((volatile u16 *)KSEG1ADDR(pa));
6857 +}
6858 +static inline u32 rc32434_readl(unsigned long pa)
6859 +{
6860 +       return *((volatile u32 *)KSEG1ADDR(pa));
6861 +}
6862 +static inline void rc32434_writeb(u8 val, unsigned long pa)
6863 +{
6864 +       *((volatile u8 *)KSEG1ADDR(pa)) = val;
6865 +}
6866 +static inline void rc32434_writew(u16 val, unsigned long pa)
6867 +{
6868 +       *((volatile u16 *)KSEG1ADDR(pa)) = val;
6869 +}
6870 +static inline void rc32434_writel(u32 val, unsigned long pa)
6871 +{
6872 +       *((volatile u32 *)KSEG1ADDR(pa)) = val;
6873 +}
6874 +
6875 +#endif
6876 +
6877 +
6878 +/*
6879 + * C access to CLZ and CLO instructions
6880 + * (count leading zeroes/ones).
6881 + */
6882 +static inline int rc32434_clz(unsigned long val)
6883 +{
6884 +       int ret;
6885 +        __asm__ volatile (
6886 +               ".set\tnoreorder\n\t"
6887 +               ".set\tnoat\n\t"
6888 +               ".set\tmips32\n\t"
6889 +               "clz\t%0,%1\n\t"
6890 +                ".set\tmips0\n\t"
6891 +                ".set\tat\n\t"
6892 +                ".set\treorder"
6893 +                : "=r" (ret)
6894 +               : "r" (val));
6895 +
6896 +       return ret;
6897 +}
6898 +static inline int rc32434_clo(unsigned long val)
6899 +{
6900 +       int ret;
6901 +        __asm__ volatile (
6902 +               ".set\tnoreorder\n\t"
6903 +               ".set\tnoat\n\t"
6904 +               ".set\tmips32\n\t"
6905 +               "clo\t%0,%1\n\t"
6906 +                ".set\tmips0\n\t"
6907 +                ".set\tat\n\t"
6908 +                ".set\treorder"
6909 +                : "=r" (ret)
6910 +               : "r" (val));
6911 +
6912 +       return ret;
6913 +}
6914 +#endif /* _RC32434_H_ */
6915 +
6916 +
6917 +
6918 +
6919 +
6920 +
6921 +
6922 +
6923 +
6924 +
6925 +
6926 +
6927 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
6928 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_integ.h    1970-01-01 01:00:00.000000000 +0100
6929 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h       2006-06-18 12:44:28.000000000 +0200
6930 @@ -0,0 +1,90 @@
6931 +/**************************************************************************
6932 + *
6933 + *  BRIEF MODULE DESCRIPTION
6934 + *   System Integrity register definition
6935 + *
6936 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6937 + *
6938 + *  This program is free software; you can redistribute  it and/or modify it
6939 + *  under  the terms of  the GNU General  Public License as published by the
6940 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6941 + *  option) any later version.
6942 + *
6943 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6944 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6945 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6946 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6947 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6948 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6949 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6950 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6951 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6952 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6953 + *
6954 + *  You should have received a copy of the  GNU General Public License along
6955 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6956 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6957 + *
6958 + *
6959 + **************************************************************************
6960 + * May 2004 rkt, neb
6961 + *
6962 + * Initial Release
6963 + *
6964 + *
6965 + *
6966 + **************************************************************************
6967 + */
6968 +
6969 +#ifndef __IDT_INTEG_H__
6970 +#define __IDT_INTEG_H__
6971 +
6972 +enum
6973 +{
6974 +       INTEG0_PhysicalAddress  = 0x18030000,
6975 +       INTEG_PhysicalAddress   = INTEG0_PhysicalAddress,       // Default
6976 +
6977 +       INTEG0_VirtualAddress   = 0xB8030000,
6978 +       INTEG_VirtualAddress    = INTEG0_VirtualAddress,        // Default
6979 +} ;
6980 +
6981 +// if you are looking for CEA, try rst.h
6982 +typedef struct
6983 +{
6984 +       u32 filler [0xc] ;              // 0x30 bytes unused.
6985 +       u32 errcs ;                     // sticky use ERRCS_
6986 +       u32 wtcount ;                   // Watchdog timer count reg.
6987 +       u32 wtcompare ;                 // Watchdog timer timeout value.
6988 +       u32 wtc ;                       // Watchdog timer control. use WTC_
6989 +} volatile *INTEG_t ;
6990 +
6991 +enum
6992 +{
6993 +       ERRCS_wto_b             = 0,            // In INTEG_t -> errcs
6994 +       ERRCS_wto_m             = 0x00000001,
6995 +       ERRCS_wne_b             = 1,            // In INTEG_t -> errcs
6996 +       ERRCS_wne_m             = 0x00000002,
6997 +       ERRCS_ucw_b             = 2,            // In INTEG_t -> errcs
6998 +       ERRCS_ucw_m             = 0x00000004,
6999 +       ERRCS_ucr_b             = 3,            // In INTEG_t -> errcs
7000 +       ERRCS_ucr_m             = 0x00000008,
7001 +       ERRCS_upw_b             = 4,            // In INTEG_t -> errcs
7002 +       ERRCS_upw_m             = 0x00000010,
7003 +       ERRCS_upr_b             = 5,            // In INTEG_t -> errcs
7004 +       ERRCS_upr_m             = 0x00000020,
7005 +       ERRCS_udw_b             = 6,            // In INTEG_t -> errcs
7006 +       ERRCS_udw_m             = 0x00000040,
7007 +       ERRCS_udr_b             = 7,            // In INTEG_t -> errcs
7008 +       ERRCS_udr_m             = 0x00000080,
7009 +       ERRCS_sae_b             = 8,            // In INTEG_t -> errcs
7010 +       ERRCS_sae_m             = 0x00000100,
7011 +       ERRCS_wre_b             = 9,            // In INTEG_t -> errcs
7012 +       ERRCS_wre_m             = 0x00000200,
7013 +
7014 +       WTC_en_b                = 0,            // In INTEG_t -> wtc
7015 +       WTC_en_m                = 0x00000001,
7016 +       WTC_to_b                = 1,            // In INTEG_t -> wtc
7017 +       WTC_to_m                = 0x00000002,
7018 +} ;
7019 +
7020 +#endif // __IDT_INTEG_H__
7021 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h
7022 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_int.h      1970-01-01 01:00:00.000000000 +0100
7023 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h 2006-06-18 12:44:28.000000000 +0200
7024 @@ -0,0 +1,174 @@
7025 +/**************************************************************************
7026 + *
7027 + *  BRIEF MODULE DESCRIPTION
7028 + *   Interrupt Controller register definition.
7029 + *
7030 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
7031 + *
7032 + *  This program is free software; you can redistribute  it and/or modify it
7033 + *  under  the terms of  the GNU General  Public License as published by the
7034 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7035 + *  option) any later version.
7036 + *
7037 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7038 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7039 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7040 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7041 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7042 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7043 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7044 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7045 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7046 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7047 + *
7048 + *  You should have received a copy of the  GNU General Public License along
7049 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7050 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7051 + *
7052 + *
7053 + **************************************************************************
7054 + * May 2004 rkt, neb.
7055 + *
7056 + * Initial Release
7057 + *
7058 + *
7059 + *
7060 + **************************************************************************
7061 + */
7062 +
7063 +#ifndef __IDT_INT_H__
7064 +#define __IDT_INT_H__
7065 +
7066 +enum
7067 +{
7068 +       INT0_PhysicalAddress    = 0x18038000,
7069 +       INT_PhysicalAddress     = INT0_PhysicalAddress,         // Default
7070 +
7071 +       INT0_VirtualAddress     = 0xB8038000,
7072 +       INT_VirtualAddress      = INT0_VirtualAddress,          // Default
7073 +} ;
7074 +
7075 +struct INT_s
7076 +{
7077 +       u32             ipend ;         //Pending interrupts. use INT?_
7078 +       u32             itest ;         //Test bits.            use INT?_
7079 +       u32             imask ;         //Interrupt disabled when set. use INT?_
7080 +} ;
7081 +
7082 +enum
7083 +{
7084 +       IPEND2  = 0,                    // HW 2 interrupt to core. use INT2_
7085 +       IPEND3  = 1,                    // HW 3 interrupt to core. use INT3_
7086 +       IPEND4  = 2,                    // HW 4 interrupt to core. use INT4_
7087 +       IPEND5  = 3,                    // HW 5 interrupt to core. use INT5_
7088 +       IPEND6  = 4,                    // HW 6 interrupt to core. use INT6_
7089 +
7090 +       IPEND_count,                    // must be last (used in loops)
7091 +       IPEND_min       = IPEND2        // min IPEND (used in loops)
7092 +};
7093 +
7094 +typedef struct INTC_s
7095 +{
7096 +       struct INT_s    i [IPEND_count] ;// use i[IPEND?] = INT?_
7097 +       u32             nmips ;         // use NMIPS_
7098 +} volatile *INT_t ;
7099 +
7100 +enum
7101 +{
7102 +       INT2_timer0_b                   = 0,
7103 +       INT2_timer0_m                   = 0x00000001,
7104 +       INT2_timer1_b                   = 1,
7105 +       INT2_timer1_m                   = 0x00000002,
7106 +       INT2_timer2_b                   = 2,
7107 +       INT2_timer2_m                   = 0x00000004,
7108 +       INT2_refresh_b                  = 3,
7109 +       INT2_refresh_m                  = 0x00000008,
7110 +       INT2_watchdogTimeout_b          = 4,
7111 +       INT2_watchdogTimeout_m          = 0x00000010,
7112 +       INT2_undecodedCpuWrite_b        = 5,
7113 +       INT2_undecodedCpuWrite_m        = 0x00000020,
7114 +       INT2_undecodedCpuRead_b         = 6,
7115 +       INT2_undecodedCpuRead_m         = 0x00000040,
7116 +       INT2_undecodedPciWrite_b        = 7,
7117 +       INT2_undecodedPciWrite_m        = 0x00000080,
7118 +       INT2_undecodedPciRead_b         = 8,
7119 +       INT2_undecodedPciRead_m         = 0x00000100,
7120 +       INT2_undecodedDmaWrite_b        = 9,
7121 +       INT2_undecodedDmaWrite_m        = 0x00000200,
7122 +       INT2_undecodedDmaRead_b         = 10,
7123 +       INT2_undecodedDmaRead_m         = 0x00000400,
7124 +       INT2_ipBusSlaveAckError_b       = 11,
7125 +       INT2_ipBusSlaveAckError_m       = 0x00000800,
7126 +
7127 +       INT3_dmaChannel0_b              = 0,
7128 +       INT3_dmaChannel0_m              = 0x00000001,
7129 +       INT3_dmaChannel1_b              = 1,
7130 +       INT3_dmaChannel1_m              = 0x00000002,
7131 +       INT3_dmaChannel2_b              = 2,
7132 +       INT3_dmaChannel2_m              = 0x00000004,
7133 +       INT3_dmaChannel3_b              = 3,
7134 +       INT3_dmaChannel3_m              = 0x00000008,
7135 +       INT3_dmaChannel4_b              = 4,
7136 +       INT3_dmaChannel4_m              = 0x00000010,
7137 +       INT3_dmaChannel5_b              = 5,
7138 +       INT3_dmaChannel5_m              = 0x00000020,
7139 +
7140 +       INT5_uartGeneral0_b             = 0,
7141 +       INT5_uartGeneral0_m             = 0x00000001,
7142 +       INT5_uartTxrdy0_b               = 1,
7143 +       INT5_uartTxrdy0_m               = 0x00000002,
7144 +       INT5_uartRxrdy0_b               = 2,
7145 +       INT5_uartRxrdy0_m               = 0x00000004,
7146 +       INT5_pci_b                      = 3,
7147 +       INT5_pci_m                      = 0x00000008,
7148 +       INT5_pciDecoupled_b             = 4,
7149 +       INT5_pciDecoupled_m             = 0x00000010,
7150 +       INT5_spi_b                      = 5,
7151 +       INT5_spi_m                      = 0x00000020,
7152 +       INT5_deviceDecoupled_b          = 6,
7153 +       INT5_deviceDecoupled_m          = 0x00000040,
7154 +       INT5_eth0Ovr_b                  = 9,
7155 +       INT5_eth0Ovr_m                  = 0x00000200,
7156 +       INT5_eth0Und_b                  = 10,
7157 +       INT5_eth0Und_m                  = 0x00000400,
7158 +       INT5_eth0Pfd_b                  = 11,
7159 +       INT5_eth0Pfd_m                  = 0x00000800,
7160 +       INT5_nvram_b                    = 12,
7161 +       INT5_nvram_m                    = 0x00001000,
7162 +
7163 +       INT6_gpio0_b                    = 0,
7164 +       INT6_gpio0_m                    = 0x00000001,
7165 +       INT6_gpio1_b                    = 1,
7166 +       INT6_gpio1_m                    = 0x00000002,
7167 +       INT6_gpio2_b                    = 2,
7168 +       INT6_gpio2_m                    = 0x00000004,
7169 +       INT6_gpio3_b                    = 3,
7170 +       INT6_gpio3_m                    = 0x00000008,
7171 +       INT6_gpio4_b                    = 4,
7172 +       INT6_gpio4_m                    = 0x00000010,
7173 +       INT6_gpio5_b                    = 5,
7174 +       INT6_gpio5_m                    = 0x00000020,
7175 +       INT6_gpio6_b                    = 6,
7176 +       INT6_gpio6_m                    = 0x00000040,
7177 +       INT6_gpio7_b                    = 7,
7178 +       INT6_gpio7_m                    = 0x00000080,
7179 +       INT6_gpio8_b                    = 8,
7180 +       INT6_gpio8_m                    = 0x00000100,
7181 +       INT6_gpio9_b                    = 9,
7182 +       INT6_gpio9_m                    = 0x00000200,
7183 +       INT6_gpio10_b                   = 10,
7184 +       INT6_gpio10_m                   = 0x00000400,
7185 +       INT6_gpio11_b                   = 11,
7186 +       INT6_gpio11_m                   = 0x00000800,
7187 +       INT6_gpio12_b                   = 12,
7188 +       INT6_gpio12_m                   = 0x00001000,
7189 +       INT6_gpio13_b                   = 13,
7190 +       INT6_gpio13_m                   = 0x00002000,
7191 +
7192 +       NMIPS_gpio_b                    = 0,
7193 +       NMIPS_gpio_m                    = 0x00000001,
7194 +} ;
7195 +
7196 +#endif // __IDT_INT_H__
7197 +
7198 +
7199 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
7200 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h    1970-01-01 01:00:00.000000000 +0100
7201 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h       2006-06-18 12:44:28.000000000 +0200
7202 @@ -0,0 +1,111 @@
7203 +/**************************************************************************
7204 + *
7205 + *  BRIEF MODULE DESCRIPTION
7206 + *   IP Arbiter register definitions
7207 + *
7208 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
7209 + *
7210 + *  This program is free software; you can redistribute  it and/or modify it
7211 + *  under  the terms of  the GNU General  Public License as published by the
7212 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7213 + *  option) any later version.
7214 + *
7215 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7216 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7217 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7218 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7219 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7220 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7221 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7222 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7223 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7224 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7225 + *
7226 + *  You should have received a copy of the  GNU General Public License along
7227 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7228 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7229 + *
7230 + *
7231 + **************************************************************************
7232 + * May 2004 rkt,neb
7233 + *
7234 + * Initial Release
7235 + *
7236 + *
7237 + *
7238 + **************************************************************************
7239 + */
7240 +
7241 +#ifndef __IDT_IPARB_H__
7242 +#define __IDT_IPARB_H__
7243 +
7244 +enum
7245 +{
7246 +       IPARB0_PhysicalAddress  = 0x18048000,
7247 +       IPARB_PhysicalAddress   = IPARB0_PhysicalAddress,       // Default
7248 +
7249 +       IPARB0_VirtualAddress   = 0xB8048000,
7250 +       IPARB_VirtualAddress    = IPARB0_VirtualAddress,        // Default
7251 +} ;
7252 +
7253 +enum
7254 +{
7255 +       IPABMXC_ethernet0Receive        = 0,
7256 +       IPABMXC_ethernet0Transmit       = 1,
7257 +       IPABMXC_memoryToHoldFifo        = 2,
7258 +       IPABMXC_holdFifoToMemory        = 3,
7259 +       IPABMXC_pciToMemory             = 4,
7260 +       IPABMXC_memoryToPci             = 5,
7261 +       IPABMXC_pciTarget               = 6,
7262 +       IPABMXC_pciTargetStart          = 7,
7263 +       IPABMXC_cpuToIpBus              = 8,
7264 +
7265 +       IPABMXC_Count,                          // Must be last in list !
7266 +       IPABMXC_Min                     = IPABMXC_ethernet0Receive,
7267 +
7268 +       IPAPXC_PriorityCount    = 4,            // 3-highest, 0-lowest.
7269 +} ;
7270 +
7271 +typedef struct
7272 +{
7273 +       u32     ipapc [IPAPXC_PriorityCount] ;  // ipapc[IPAPXC_] = IPAPC_
7274 +       u32     ipabmc [IPABMXC_Count] ;        // ipabmc[IPABMXC_] = IPABMC_
7275 +       u32     ipac ;                          // use IPAC_
7276 +       u32     ipaitcc;                        // use IPAITCC_
7277 +       u32     ipaspare ;
7278 +} volatile * IPARB_t ;
7279 +
7280 +enum
7281 +{
7282 +       IPAC_dp_b                       = 0,
7283 +       IPAC_dp_m                       = 0x00000001,
7284 +       IPAC_dep_b                      = 1,
7285 +       IPAC_dep_m                      = 0x00000002,
7286 +       IPAC_drm_b                      = 2,
7287 +       IPAC_drm_m                      = 0x00000004,
7288 +       IPAC_dwm_b                      = 3,
7289 +       IPAC_dwm_m                      = 0x00000008,
7290 +       IPAC_msk_b                      = 4,
7291 +       IPAC_msk_m                      = 0x00000010,
7292 +
7293 +       IPAPC_ptc_b                     = 0,
7294 +       IPAPC_ptc_m                     = 0x00003fff,
7295 +       IPAPC_mf_b                      = 14,
7296 +       IPAPC_mf_m                      = 0x00004000,
7297 +       IPAPC_cptc_b                    = 16,
7298 +       IPAPC_cptc_m                    = 0x3fff0000,
7299 +
7300 +       IPAITCC_itcc                    = 0,
7301 +       IPAITCC_itcc,                   = 0x000001ff,
7302 +
7303 +       IPABMC_mtc_b                    = 0,
7304 +       IPABMC_mtc_m                    = 0x00000fff,
7305 +       IPABMC_p_b                      = 12,
7306 +       IPABMC_p_m                      = 0x00003000,
7307 +       IPABMC_msk_b                    = 14,
7308 +       IPABMC_msk_m                    = 0x00004000,
7309 +       IPABMC_cmtc_b                   = 16,
7310 +       IPABMC_cmtc_m                   = 0x0fff0000,
7311 +};
7312 +
7313 +#endif // __IDT_IPARB_H__
7314 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
7315 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_pci.h      1970-01-01 01:00:00.000000000 +0100
7316 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 2006-06-18 12:44:28.000000000 +0200
7317 @@ -0,0 +1,695 @@
7318 +/**************************************************************************
7319 + *
7320 + *  BRIEF MODULE DESCRIPTION
7321 + *   PCI register definitio
7322 + *
7323 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
7324 + *
7325 + *  This program is free software; you can redistribute  it and/or modify it
7326 + *  under  the terms of  the GNU General  Public License as published by the
7327 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7328 + *  option) any later version.
7329 + *
7330 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7331 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7332 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7333 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7334 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7335 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7336 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7337 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7338 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7339 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7340 + *
7341 + *  You should have received a copy of the  GNU General Public License along
7342 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7343 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7344 + *
7345 + *
7346 + **************************************************************************
7347 + * May 2004 rkt, neb.
7348 + *
7349 + * Initial Release
7350 + *
7351 + *
7352 + *
7353 + **************************************************************************
7354 + */
7355 +
7356 +#ifndef __IDT_PCI_H__
7357 +#define __IDT_PCI_H__
7358 +
7359 +enum
7360 +{
7361 +       PCI0_PhysicalAddress    = 0x18080000,
7362 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
7363 +
7364 +       PCI0_VirtualAddress     = 0xB8080000,
7365 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
7366 +} ;
7367 +
7368 +enum
7369 +{
7370 +       PCI_LbaCount    = 4,            // Local base addresses.
7371 +} ;
7372 +
7373 +typedef struct
7374 +{
7375 +       u32     a ;             // Address.
7376 +       u32     c ;             // Control.
7377 +       u32     m ;             // mapping.
7378 +} PCI_Map_s ;
7379 +
7380 +typedef struct
7381 +{
7382 +       u32             pcic ;
7383 +       u32             pcis ;
7384 +       u32             pcism ;
7385 +       u32             pcicfga ;
7386 +       u32             pcicfgd ;
7387 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
7388 +       u32             pcidac ;
7389 +       u32             pcidas ;
7390 +       u32             pcidasm ;
7391 +       u32             pcidad ;
7392 +       u32             pcidma8c ;
7393 +       u32             pcidma9c ;
7394 +       u32             pcitc ;
7395 +} volatile *PCI_t ;
7396 +
7397 +// PCI messaging unit.
7398 +enum
7399 +{
7400 +       PCIM_Count      = 2,
7401 +} ;
7402 +typedef struct
7403 +{
7404 +       u32             pciim [PCIM_Count] ;
7405 +       u32             pciom [PCIM_Count] ;
7406 +       u32             pciid ;
7407 +       u32             pciiic ;
7408 +       u32             pciiim ;
7409 +       u32             pciiod ;
7410 +       u32             pciioic ;
7411 +       u32             pciioim ;
7412 +} volatile *PCIM_t ;
7413 +
7414 +/*******************************************************************************
7415 + *
7416 + * PCI Control Register
7417 + *
7418 + ******************************************************************************/
7419 +enum
7420 +{
7421 +       PCIC_en_b       = 0,
7422 +       PCIC_en_m       = 0x00000001,
7423 +       PCIC_tnr_b      = 1,
7424 +       PCIC_tnr_m      = 0x00000002,
7425 +       PCIC_sce_b      = 2,
7426 +       PCIC_sce_m      = 0x00000004,
7427 +       PCIC_ien_b      = 3,
7428 +       PCIC_ien_m      = 0x00000008,
7429 +       PCIC_aaa_b      = 4,
7430 +       PCIC_aaa_m      = 0x00000010,
7431 +       PCIC_eap_b      = 5,
7432 +       PCIC_eap_m      = 0x00000020,
7433 +       PCIC_pcim_b     = 6,
7434 +       PCIC_pcim_m     = 0x000001c0,
7435 +               PCIC_pcim_disabled_v    = 0,
7436 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
7437 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
7438 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
7439 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
7440 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
7441 +               PCIC_pcim_reserved6_v   = 6,
7442 +               PCIC_pcim_reserved7_v   = 7,
7443 +       PCIC_igm_b      = 9,
7444 +       PCIC_igm_m      = 0x00000200,
7445 +} ;
7446 +
7447 +/*******************************************************************************
7448 + *
7449 + * PCI Status Register
7450 + *
7451 + ******************************************************************************/
7452 +enum {
7453 +       PCIS_eed_b      = 0,
7454 +       PCIS_eed_m      = 0x00000001,
7455 +       PCIS_wr_b       = 1,
7456 +       PCIS_wr_m       = 0x00000002,
7457 +       PCIS_nmi_b      = 2,
7458 +       PCIS_nmi_m      = 0x00000004,
7459 +       PCIS_ii_b       = 3,
7460 +       PCIS_ii_m       = 0x00000008,
7461 +       PCIS_cwe_b      = 4,
7462 +       PCIS_cwe_m      = 0x00000010,
7463 +       PCIS_cre_b      = 5,
7464 +       PCIS_cre_m      = 0x00000020,
7465 +       PCIS_mdpe_b     = 6,
7466 +       PCIS_mdpe_m     = 0x00000040,
7467 +       PCIS_sta_b      = 7,
7468 +       PCIS_sta_m      = 0x00000080,
7469 +       PCIS_rta_b      = 8,
7470 +       PCIS_rta_m      = 0x00000100,
7471 +       PCIS_rma_b      = 9,
7472 +       PCIS_rma_m      = 0x00000200,
7473 +       PCIS_sse_b      = 10,
7474 +       PCIS_sse_m      = 0x00000400,
7475 +       PCIS_ose_b      = 11,
7476 +       PCIS_ose_m      = 0x00000800,
7477 +       PCIS_pe_b       = 12,
7478 +       PCIS_pe_m       = 0x00001000,
7479 +       PCIS_tae_b      = 13,
7480 +       PCIS_tae_m      = 0x00002000,
7481 +       PCIS_rle_b      = 14,
7482 +       PCIS_rle_m      = 0x00004000,
7483 +       PCIS_bme_b      = 15,
7484 +       PCIS_bme_m      = 0x00008000,
7485 +       PCIS_prd_b      = 16,
7486 +       PCIS_prd_m      = 0x00010000,
7487 +       PCIS_rip_b      = 17,
7488 +       PCIS_rip_m      = 0x00020000,
7489 +} ;
7490 +
7491 +/*******************************************************************************
7492 + *
7493 + * PCI Status Mask Register
7494 + *
7495 + ******************************************************************************/
7496 +enum {
7497 +       PCISM_eed_b             = 0,
7498 +       PCISM_eed_m             = 0x00000001,
7499 +       PCISM_wr_b              = 1,
7500 +       PCISM_wr_m              = 0x00000002,
7501 +       PCISM_nmi_b             = 2,
7502 +       PCISM_nmi_m             = 0x00000004,
7503 +       PCISM_ii_b              = 3,
7504 +       PCISM_ii_m              = 0x00000008,
7505 +       PCISM_cwe_b             = 4,
7506 +       PCISM_cwe_m             = 0x00000010,
7507 +       PCISM_cre_b             = 5,
7508 +       PCISM_cre_m             = 0x00000020,
7509 +       PCISM_mdpe_b            = 6,
7510 +       PCISM_mdpe_m            = 0x00000040,
7511 +       PCISM_sta_b             = 7,
7512 +       PCISM_sta_m             = 0x00000080,
7513 +       PCISM_rta_b             = 8,
7514 +       PCISM_rta_m             = 0x00000100,
7515 +       PCISM_rma_b             = 9,
7516 +       PCISM_rma_m             = 0x00000200,
7517 +       PCISM_sse_b             = 10,
7518 +       PCISM_sse_m             = 0x00000400,
7519 +       PCISM_ose_b             = 11,
7520 +       PCISM_ose_m             = 0x00000800,
7521 +       PCISM_pe_b              = 12,
7522 +       PCISM_pe_m              = 0x00001000,
7523 +       PCISM_tae_b             = 13,
7524 +       PCISM_tae_m             = 0x00002000,
7525 +       PCISM_rle_b             = 14,
7526 +       PCISM_rle_m             = 0x00004000,
7527 +       PCISM_bme_b             = 15,
7528 +       PCISM_bme_m             = 0x00008000,
7529 +       PCISM_prd_b             = 16,
7530 +       PCISM_prd_m             = 0x00010000,
7531 +       PCISM_rip_b             = 17,
7532 +       PCISM_rip_m             = 0x00020000,
7533 +} ;
7534 +
7535 +/*******************************************************************************
7536 + *
7537 + * PCI Configuration Address Register
7538 + *
7539 + ******************************************************************************/
7540 +enum {
7541 +       PCICFGA_reg_b           = 2,
7542 +       PCICFGA_reg_m           = 0x000000fc,
7543 +               PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
7544 +               PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
7545 +               PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
7546 +               PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
7547 +               PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
7548 +               PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
7549 +               PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
7550 +               PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
7551 +               PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
7552 +               PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
7553 +               PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
7554 +               PCICFGA_reg_pba0m_v     = 0x48>>2,
7555 +               PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
7556 +               PCICFGA_reg_pba1m_v     = 0x50>>2,
7557 +               PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
7558 +               PCICFGA_reg_pba2m_v     = 0x58>>2,
7559 +               PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
7560 +               PCICFGA_reg_pba3m_v     = 0x60>>2,
7561 +               PCICFGA_reg_pmgt_v      = 0x64>>2,
7562 +       PCICFGA_func_b          = 8,
7563 +       PCICFGA_func_m          = 0x00000700,
7564 +       PCICFGA_dev_b           = 11,
7565 +       PCICFGA_dev_m           = 0x0000f800,
7566 +               PCICFGA_dev_internal_v  = 0,
7567 +       PCICFGA_bus_b           = 16,
7568 +       PCICFGA_bus_m           = 0x00ff0000,
7569 +               PCICFGA_bus_type0_v     = 0,    //local bus
7570 +       PCICFGA_en_b            = 31,           // read only
7571 +       PCICFGA_en_m            = 0x80000000,
7572 +} ;
7573 +
7574 +enum {
7575 +       PCFGID_vendor_b         = 0,
7576 +       PCFGID_vendor_m         = 0x0000ffff,
7577 +               PCFGID_vendor_IDT_v             = 0x111d,
7578 +       PCFGID_device_b         = 16,
7579 +       PCFGID_device_m         = 0xffff0000,
7580 +               PCFGID_device_Korinade_v        = 0x0214,
7581 +
7582 +       PCFG04_command_ioena_b          = 1,
7583 +       PCFG04_command_ioena_m          = 0x00000001,
7584 +       PCFG04_command_memena_b         = 2,
7585 +       PCFG04_command_memena_m         = 0x00000002,
7586 +       PCFG04_command_bmena_b          = 3,
7587 +       PCFG04_command_bmena_m          = 0x00000004,
7588 +       PCFG04_command_mwinv_b          = 5,
7589 +       PCFG04_command_mwinv_m          = 0x00000010,
7590 +       PCFG04_command_parena_b         = 7,
7591 +       PCFG04_command_parena_m         = 0x00000040,
7592 +       PCFG04_command_serrena_b        = 9,
7593 +       PCFG04_command_serrena_m        = 0x00000100,
7594 +       PCFG04_command_fastbbena_b      = 10,
7595 +       PCFG04_command_fastbbena_m      = 0x00000200,
7596 +       PCFG04_status_b                 = 16,
7597 +       PCFG04_status_m                 = 0xffff0000,
7598 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
7599 +       PCFG04_status_66MHz_m           = 0x00200000,
7600 +       PCFG04_status_fbb_b             = 23,
7601 +       PCFG04_status_fbb_m             = 0x00800000,
7602 +       PCFG04_status_mdpe_b            = 24,
7603 +       PCFG04_status_mdpe_m            = 0x01000000,
7604 +       PCFG04_status_dst_b             = 25,
7605 +       PCFG04_status_dst_m             = 0x06000000,
7606 +       PCFG04_status_sta_b             = 27,
7607 +       PCFG04_status_sta_m             = 0x08000000,
7608 +       PCFG04_status_rta_b             = 28,
7609 +       PCFG04_status_rta_m             = 0x10000000,
7610 +       PCFG04_status_rma_b             = 29,
7611 +       PCFG04_status_rma_m             = 0x20000000,
7612 +       PCFG04_status_sse_b             = 30,
7613 +       PCFG04_status_sse_m             = 0x40000000,
7614 +       PCFG04_status_pe_b              = 31,
7615 +       PCFG04_status_pe_m              = 0x40000000,
7616 +
7617 +       PCFG08_revId_b                  = 0,
7618 +       PCFG08_revId_m                  = 0x000000ff,
7619 +       PCFG08_classCode_b              = 0,
7620 +       PCFG08_classCode_m              = 0xffffff00,
7621 +               PCFG08_classCode_bridge_v       = 06,
7622 +               PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
7623 +       PCFG0C_cacheline_b              = 0,
7624 +       PCFG0C_cacheline_m              = 0x000000ff,
7625 +       PCFG0C_masterLatency_b          = 8,
7626 +       PCFG0C_masterLatency_m          = 0x0000ff00,
7627 +       PCFG0C_headerType_b             = 16,
7628 +       PCFG0C_headerType_m             = 0x00ff0000,
7629 +       PCFG0C_bist_b                   = 24,
7630 +       PCFG0C_bist_m                   = 0xff000000,
7631 +
7632 +       PCIPBA_msi_b                    = 0,
7633 +       PCIPBA_msi_m                    = 0x00000001,
7634 +       PCIPBA_p_b                      = 3,
7635 +       PCIPBA_p_m                      = 0x00000004,
7636 +       PCIPBA_baddr_b                  = 8,
7637 +       PCIPBA_baddr_m                  = 0xffffff00,
7638 +
7639 +       PCFGSS_vendorId_b               = 0,
7640 +       PCFGSS_vendorId_m               = 0x0000ffff,
7641 +       PCFGSS_id_b                     = 16,
7642 +       PCFGSS_id_m                     = 0xffff0000,
7643 +
7644 +       PCFG3C_interruptLine_b          = 0,
7645 +       PCFG3C_interruptLine_m          = 0x000000ff,
7646 +       PCFG3C_interruptPin_b           = 8,
7647 +       PCFG3C_interruptPin_m           = 0x0000ff00,
7648 +       PCFG3C_minGrant_b               = 16,
7649 +       PCFG3C_minGrant_m               = 0x00ff0000,
7650 +       PCFG3C_maxLat_b                 = 24,
7651 +       PCFG3C_maxLat_m                 = 0xff000000,
7652 +
7653 +       PCIPBAC_msi_b                   = 0,
7654 +       PCIPBAC_msi_m                   = 0x00000001,
7655 +       PCIPBAC_p_b                     = 1,
7656 +       PCIPBAC_p_m                     = 0x00000002,
7657 +       PCIPBAC_size_b                  = 2,
7658 +       PCIPBAC_size_m                  = 0x0000007c,
7659 +       PCIPBAC_sb_b                    = 7,
7660 +       PCIPBAC_sb_m                    = 0x00000080,
7661 +       PCIPBAC_pp_b                    = 8,
7662 +       PCIPBAC_pp_m                    = 0x00000100,
7663 +       PCIPBAC_mr_b                    = 9,
7664 +       PCIPBAC_mr_m                    = 0x00000600,
7665 +               PCIPBAC_mr_read_v       =0,     //no prefetching
7666 +               PCIPBAC_mr_readLine_v   =1,
7667 +               PCIPBAC_mr_readMult_v   =2,
7668 +       PCIPBAC_mrl_b                   = 11,
7669 +       PCIPBAC_mrl_m                   = 0x00000800,
7670 +       PCIPBAC_mrm_b                   = 12,
7671 +       PCIPBAC_mrm_m                   = 0x00001000,
7672 +       PCIPBAC_trp_b                   = 13,
7673 +       PCIPBAC_trp_m                   = 0x00002000,
7674 +
7675 +       PCFG40_trdyTimeout_b            = 0,
7676 +       PCFG40_trdyTimeout_m            = 0x000000ff,
7677 +       PCFG40_retryLim_b               = 8,
7678 +       PCFG40_retryLim_m               = 0x0000ff00,
7679 +};
7680 +
7681 +/*******************************************************************************
7682 + *
7683 + * PCI Local Base Address [0|1|2|3] Register
7684 + *
7685 + ******************************************************************************/
7686 +enum {
7687 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
7688 +       PCILBA_baddr_m          = 0xffffff00,
7689 +} ;
7690 +/*******************************************************************************
7691 + *
7692 + * PCI Local Base Address Control Register
7693 + *
7694 + ******************************************************************************/
7695 +enum {
7696 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
7697 +       PCILBAC_msi_m           = 0x00000001,
7698 +               PCILBAC_msi_mem_v       = 0,
7699 +               PCILBAC_msi_io_v        = 1,
7700 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
7701 +       PCILBAC_size_m          = 0x0000007c,
7702 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
7703 +       PCILBAC_sb_m            = 0x00000080,
7704 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
7705 +       PCILBAC_rt_m            = 0x00000100,
7706 +               PCILBAC_rt_noprefetch_v = 0, // mem read
7707 +               PCILBAC_rt_prefetch_v   = 1, // mem readline
7708 +} ;
7709 +
7710 +/*******************************************************************************
7711 + *
7712 + * PCI Local Base Address [0|1|2|3] Mapping Register
7713 + *
7714 + ******************************************************************************/
7715 +enum {
7716 +       PCILBAM_maddr_b         = 8,
7717 +       PCILBAM_maddr_m         = 0xffffff00,
7718 +} ;
7719 +
7720 +/*******************************************************************************
7721 + *
7722 + * PCI Decoupled Access Control Register
7723 + *
7724 + ******************************************************************************/
7725 +enum {
7726 +       PCIDAC_den_b            = 0,
7727 +       PCIDAC_den_m            = 0x00000001,
7728 +} ;
7729 +
7730 +/*******************************************************************************
7731 + *
7732 + * PCI Decoupled Access Status Register
7733 + *
7734 + ******************************************************************************/
7735 +enum {
7736 +       PCIDAS_d_b      = 0,
7737 +       PCIDAS_d_m      = 0x00000001,
7738 +       PCIDAS_b_b      = 1,
7739 +       PCIDAS_b_m      = 0x00000002,
7740 +       PCIDAS_e_b      = 2,
7741 +       PCIDAS_e_m      = 0x00000004,
7742 +       PCIDAS_ofe_b    = 3,
7743 +       PCIDAS_ofe_m    = 0x00000008,
7744 +       PCIDAS_off_b    = 4,
7745 +       PCIDAS_off_m    = 0x00000010,
7746 +       PCIDAS_ife_b    = 5,
7747 +       PCIDAS_ife_m    = 0x00000020,
7748 +       PCIDAS_iff_b    = 6,
7749 +       PCIDAS_iff_m    = 0x00000040,
7750 +} ;
7751 +
7752 +/*******************************************************************************
7753 + *
7754 + * PCI DMA Channel 8 Configuration Register
7755 + *
7756 + ******************************************************************************/
7757 +enum
7758 +{
7759 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
7760 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
7761 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
7762 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
7763 +} ;
7764 +
7765 +/*******************************************************************************
7766 + *
7767 + * PCI DMA Channel 9 Configuration Register
7768 + *
7769 + ******************************************************************************/
7770 +enum
7771 +{
7772 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
7773 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
7774 +} ;
7775 +
7776 +/*******************************************************************************
7777 + *
7778 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
7779 + *
7780 + ******************************************************************************/
7781 +enum {
7782 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
7783 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
7784 +               // These are for reads (DMA channel 8)
7785 +               PCIDMAD_devcmd_mr_v     = 0,    //memory read
7786 +               PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
7787 +               PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
7788 +               PCIDMAD_devcmd_ior_v    = 3,    //I/O read
7789 +               // These are for writes (DMA channel 9)
7790 +               PCIDMAD_devcmd_mw_v     = 0,    //memory write
7791 +               PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
7792 +               PCIDMAD_devcmd_iow_v    = 3,    //I/O write
7793 +
7794 +       // Swap byte field applies to both DMA channel 8 and 9
7795 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
7796 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
7797 +} ;
7798 +
7799 +
7800 +/*******************************************************************************
7801 + *
7802 + * PCI Target Control Register
7803 + *
7804 + ******************************************************************************/
7805 +enum
7806 +{
7807 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
7808 +       PCITC_rtimer_m          = 0x000000ff,
7809 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
7810 +       PCITC_dtimer_m          = 0x0000ff00,
7811 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
7812 +       PCITC_rdr_m             = 0x00040000,
7813 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
7814 +       PCITC_ddt_m             = 0x00080000,
7815 +} ;
7816 +/*******************************************************************************
7817 + *
7818 + * PCI messaging unit [applies to both inbound and outbound registers ]
7819 + *
7820 + ******************************************************************************/
7821 +enum
7822 +{
7823 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7824 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
7825 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7826 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
7827 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7828 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
7829 +};
7830 +
7831 +
7832 +
7833 +
7834 +
7835 +
7836 +#define PCI_MSG_VirtualAddress      0xB8088010
7837 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
7838 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
7839 +
7840 +#define PCIM_SHFT              0x6
7841 +#define PCIM_BIT_LEN           0x7
7842 +#define PCIM_H_EA              0x3
7843 +#define PCIM_H_IA_FIX          0x4
7844 +#define PCIM_H_IA_RR           0x5
7845 +#if 0
7846 +#define PCI_ADDR_START         0x13000000
7847 +#endif
7848 +
7849 +#define PCI_ADDR_START         0x50000000
7850 +
7851 +#define CPUTOPCI_MEM_WIN       0x02000000
7852 +#define CPUTOPCI_IO_WIN                0x00100000
7853 +#define PCILBA_SIZE_SHFT       2
7854 +#define PCILBA_SIZE_MASK       0x1F
7855 +#define SIZE_256MB             0x1C
7856 +#define SIZE_128MB             0x1B
7857 +#define SIZE_64MB               0x1A
7858 +#define SIZE_32MB              0x19
7859 +#define SIZE_16MB               0x18
7860 +#define SIZE_4MB               0x16
7861 +#define SIZE_2MB               0x15
7862 +#define SIZE_1MB               0x14
7863 +#define KORINA_CONFIG0_ADDR    0x80000000
7864 +#define KORINA_CONFIG1_ADDR    0x80000004
7865 +#define KORINA_CONFIG2_ADDR    0x80000008
7866 +#define KORINA_CONFIG3_ADDR    0x8000000C
7867 +#define KORINA_CONFIG4_ADDR    0x80000010
7868 +#define KORINA_CONFIG5_ADDR    0x80000014
7869 +#define KORINA_CONFIG6_ADDR    0x80000018
7870 +#define KORINA_CONFIG7_ADDR    0x8000001C
7871 +#define KORINA_CONFIG8_ADDR    0x80000020
7872 +#define KORINA_CONFIG9_ADDR    0x80000024
7873 +#define KORINA_CONFIG10_ADDR   0x80000028
7874 +#define KORINA_CONFIG11_ADDR   0x8000002C
7875 +#define KORINA_CONFIG12_ADDR   0x80000030
7876 +#define KORINA_CONFIG13_ADDR   0x80000034
7877 +#define KORINA_CONFIG14_ADDR   0x80000038
7878 +#define KORINA_CONFIG15_ADDR   0x8000003C
7879 +#define KORINA_CONFIG16_ADDR   0x80000040
7880 +#define KORINA_CONFIG17_ADDR   0x80000044
7881 +#define KORINA_CONFIG18_ADDR   0x80000048
7882 +#define KORINA_CONFIG19_ADDR   0x8000004C
7883 +#define KORINA_CONFIG20_ADDR   0x80000050
7884 +#define KORINA_CONFIG21_ADDR   0x80000054
7885 +#define KORINA_CONFIG22_ADDR   0x80000058
7886 +#define KORINA_CONFIG23_ADDR   0x8000005C
7887 +#define KORINA_CONFIG24_ADDR   0x80000060
7888 +#define KORINA_CONFIG25_ADDR   0x80000064
7889 +#define KORINA_CMD             (PCFG04_command_ioena_m | \
7890 +                                PCFG04_command_memena_m | \
7891 +                                PCFG04_command_bmena_m | \
7892 +                                PCFG04_command_mwinv_m | \
7893 +                                PCFG04_command_parena_m | \
7894 +                                PCFG04_command_serrena_m )
7895 +
7896 +#define KORINA_STAT            (PCFG04_status_mdpe_m | \
7897 +                                PCFG04_status_sta_m  | \
7898 +                                PCFG04_status_rta_m  | \
7899 +                                PCFG04_status_rma_m  | \
7900 +                                PCFG04_status_sse_m  | \
7901 +                                PCFG04_status_pe_m)
7902 +
7903 +#define KORINA_CNFG1           ((KORINA_STAT<<16)|KORINA_CMD)
7904 +
7905 +#define KORINA_REVID           0
7906 +#define KORINA_CLASS_CODE      0
7907 +#define KORINA_CNFG2           ((KORINA_CLASS_CODE<<8) | \
7908 +                                 KORINA_REVID)
7909 +
7910 +#define KORINA_CACHE_LINE_SIZE 4
7911 +#define KORINA_MASTER_LAT      0x3c
7912 +#define KORINA_HEADER_TYPE     0
7913 +#define KORINA_BIST            0
7914 +
7915 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
7916 +                     (KORINA_HEADER_TYPE<<16) | \
7917 +                     (KORINA_MASTER_LAT<<8) | \
7918 +                     KORINA_CACHE_LINE_SIZE )
7919 +
7920 +#define KORINA_BAR0    0x00000008 /* 128 MB Memory */
7921 +#define KORINA_BAR1    0x18800001 /* 1 MB IO */
7922 +#define KORINA_BAR2    0x18000001 /* 2 MB IO window for Korina
7923 +                                       internal Registers */
7924 +#define KORINA_BAR3    0x48000008 /* Spare 128 MB Memory */
7925 +
7926 +#define KORINA_CNFG4   KORINA_BAR0
7927 +#define KORINA_CNFG5    KORINA_BAR1
7928 +#define KORINA_CNFG6   KORINA_BAR2
7929 +#define KORINA_CNFG7   KORINA_BAR3
7930 +
7931 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
7932 +#define KORINA_SUBSYSTEM_ID    0x0214
7933 +#define KORINA_CNFG8           0
7934 +#define KORINA_CNFG9           0
7935 +#define KORINA_CNFG10          0
7936 +#define KORINA_CNFG11  ((KORINA_SUBSYS_VENDOR_ID<<16) | \
7937 +                         KORINA_SUBSYSTEM_ID)
7938 +#define KORINA_INT_LINE                1
7939 +#define KORINA_INT_PIN         1
7940 +#define KORINA_MIN_GNT         8
7941 +#define KORINA_MAX_LAT         0x38
7942 +#define KORINA_CNFG12          0
7943 +#define KORINA_CNFG13          0
7944 +#define KORINA_CNFG14          0
7945 +#define KORINA_CNFG15  ((KORINA_MAX_LAT<<24) | \
7946 +                        (KORINA_MIN_GNT<<16) | \
7947 +                        (KORINA_INT_PIN<<8)  | \
7948 +                         KORINA_INT_LINE)
7949 +#define        KORINA_RETRY_LIMIT      0x80
7950 +#define KORINA_TRDY_LIMIT      0x80
7951 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
7952 +                       KORINA_TRDY_LIMIT)
7953 +#define PCI_PBAxC_R            0x0
7954 +#define PCI_PBAxC_RL           0x1
7955 +#define PCI_PBAxC_RM           0x2
7956 +#define SIZE_SHFT              2
7957 +
7958 +#if defined(__MIPSEB__)
7959 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
7960 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7961 +                         PCIPBAC_pp_m | \
7962 +                         (SIZE_128MB<<SIZE_SHFT) | \
7963 +                          PCIPBAC_p_m)
7964 +#else
7965 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | \
7966 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7967 +                         PCIPBAC_pp_m | \
7968 +                         (SIZE_128MB<<SIZE_SHFT) | \
7969 +                          PCIPBAC_p_m)
7970 +#endif
7971 +#define KORINA_CNFG17  KORINA_PBA0C
7972 +#define KORINA_PBA0M   0x0
7973 +#define KORINA_CNFG18  KORINA_PBA0M
7974 +
7975 +#if defined(__MIPSEB__)
7976 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7977 +                         PCIPBAC_msi_m)
7978 +#else
7979 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | \
7980 +                         PCIPBAC_msi_m)
7981 +#endif
7982 +#define KORINA_CNFG19  KORINA_PBA1C
7983 +#define KORINA_PBA1M   0x0
7984 +#define KORINA_CNFG20  KORINA_PBA1M
7985 +
7986 +#if defined(__MIPSEB__)
7987 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7988 +                         PCIPBAC_msi_m)
7989 +#else
7990 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | \
7991 +                         PCIPBAC_msi_m)
7992 +#endif
7993 +#define KORINA_CNFG21  KORINA_PBA2C
7994 +#define KORINA_PBA2M   0x18000000
7995 +#define KORINA_CNFG22  KORINA_PBA2M
7996 +#define KORINA_PBA3C   0
7997 +#define KORINA_CNFG23  KORINA_PBA3C
7998 +#define KORINA_PBA3M   0
7999 +#define KORINA_CNFG24  KORINA_PBA3M
8000 +
8001 +
8002 +
8003 +#define        PCITC_DTIMER_VAL        8
8004 +#define PCITC_RTIMER_VAL       0x10
8005 +
8006 +
8007 +
8008 +
8009 +#endif // __IDT_PCI_H__
8010 +
8011 +
8012 +
8013 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
8014 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_rst.h      1970-01-01 01:00:00.000000000 +0100
8015 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 2006-06-18 12:44:28.000000000 +0200
8016 @@ -0,0 +1,119 @@
8017 +/**************************************************************************
8018 + *
8019 + *  BRIEF MODULE DESCRIPTION
8020 + *   Reset register definitions.
8021 + *
8022 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8023 + *
8024 + *  This program is free software; you can redistribute  it and/or modify it
8025 + *  under  the terms of  the GNU General  Public License as published by the
8026 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8027 + *  option) any later version.
8028 + *
8029 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8030 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8031 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8032 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8033 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8034 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8035 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8036 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8037 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8038 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8039 + *
8040 + *  You should have received a copy of the  GNU General Public License along
8041 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8042 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8043 + *
8044 + *
8045 + **************************************************************************
8046 + * May 2004 rkt, neb.
8047 + *
8048 + * Initial Release
8049 + *
8050 + *
8051 + *
8052 + **************************************************************************
8053 + */
8054 +
8055 +#ifndef __IDT_RST_H__
8056 +#define __IDT_RST_H__
8057 +
8058 +enum
8059 +{
8060 +       RST0_PhysicalAddress    = 0x18000000,
8061 +       RST_PhysicalAddress     = RST0_PhysicalAddress,         // Default
8062 +
8063 +       RST0_VirtualAddress     = 0xb8000000,
8064 +       RST_VirtualAddress      = RST0_VirtualAddress,          // Default
8065 +} ;
8066 +
8067 +typedef struct RST_s
8068 +{
8069 +       u32     filler [0x0006] ;
8070 +       u32     sysid ;
8071 +       u32     filler2 [0x2000-8] ;            // Pad out to offset 0x8000
8072 +       u32     reset ;
8073 +       u32     bcv ;
8074 +       u32     cea ;
8075 +} volatile * RST_t ;
8076 +
8077 +enum
8078 +{
8079 +       SYSID_rev_b             = 0,
8080 +       SYSID_rev_m             = 0x000000ff,
8081 +       SYSID_imp_b             = 8,
8082 +       SYSID_imp_m             = 0x000fff00,
8083 +       SYSID_vendor_b          = 8,
8084 +       SYSID_vendor_m          = 0xfff00000,
8085 +
8086 +       BCV_pll_b               = 0,
8087 +       BCV_pll_m               = 0x0000000f,
8088 +               BCV_pll_PLLBypass_v     = 0x0,  // PCLK=1*CLK.
8089 +               BCV_pll_Mul3_v          = 0x1,  // PCLK=3*CLK.
8090 +               BCV_pll_Mul4_v          = 0x2,  // PCLK=4*CLK.
8091 +               BCV_pll_SlowMul5_v      = 0x3,  // PCLK=5*CLK.
8092 +               BCV_pll_Mul5_v          = 0x4,  // PCLK=5*CLK.
8093 +               BCV_pll_SlowMul6_v      = 0x5,  // PCLK=6*CLK.
8094 +               BCV_pll_Mul6_v          = 0x6,  // PCLK=6*CLK.
8095 +               BCV_pll_Mul8_v          = 0x7,  // PCLK=8*CLK.
8096 +               BCV_pll_Mul10_v         = 0x8,  // PCLK=10*CLK.
8097 +               BCV_pll_Res9_v          = 0x9,
8098 +               BCV_pll_Res10_v         = 0xa,
8099 +               BCV_pll_Res11_v         = 0xb,
8100 +               BCV_pll_Res12_v         = 0xc,
8101 +               BCV_pll_Res13_v         = 0xd,
8102 +               BCV_pll_Res14_v         = 0xe,
8103 +               BCV_pll_Res15_v         = 0xf,
8104 +       BCV_clkDiv_b            = 4,
8105 +       BCV_clkDiv_m            = 0x00000030,
8106 +               BCV_clkDiv_Div1_v       = 0x0,
8107 +               BCV_clkDiv_Div2_v       = 0x1,
8108 +               BCV_clkDiv_Div4_v       = 0x2,
8109 +               BCV_clkDiv_Res3_v       = 0x3,
8110 +       BCV_bigEndian_b         = 6,
8111 +       BCV_bigEndian_m         = 0x00000040,
8112 +       BCV_resetFast_b         = 7,
8113 +       BCV_resetFast_m         = 0x00000080,
8114 +       BCV_pciMode_b           = 8,
8115 +       BCV_pciMode_m           = 0x00000700,
8116 +               BCV_pciMode_disabled_v  = 0,    // PCI is disabled.
8117 +               BCV_pciMode_tnr_v       = 1,    // satellite Target Not Ready.
8118 +               BCV_pciMode_suspended_v = 2,    // satellite with suspended CPU.
8119 +               BCV_pciMode_external_v  = 3,    // host, external arbiter.
8120 +               BCV_pciMode_fixed_v     = 4,    // host, fixed priority arbiter.
8121 +               BCV_pciMode_roundRobin_v= 5,    // host, round robin arbiter.
8122 +               BCV_pciMode_res6_v      = 6,
8123 +               BCV_pciMode_res7_v      = 7,
8124 +       BCV_watchDisable_b      = 11,
8125 +       BCV_watchDisable_m      = 0x00000800,
8126 +       BCV_res12_b             = 12,
8127 +       BCV_res12_m             = 0x00001000,
8128 +       BCV_res13_b             = 13,
8129 +       BCV_res13_m             = 0x00002000,
8130 +       BCV_res14_b             = 14,
8131 +       BCV_res14_m             = 0x00004000,
8132 +       BCV_res15_b             = 15,
8133 +       BCV_res15_m             = 0x00008000,
8134 +} ;
8135 +#endif // __IDT_RST_H__
8136 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
8137 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_spi.h      1970-01-01 01:00:00.000000000 +0100
8138 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 2006-06-18 12:44:28.000000000 +0200
8139 @@ -0,0 +1,120 @@
8140 +/**************************************************************************
8141 + *
8142 + *  BRIEF MODULE DESCRIPTION
8143 + *   Serial Peripheral Interface register definitions.
8144 + *
8145 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8146 + *
8147 + *  This program is free software; you can redistribute  it and/or modify it
8148 + *  under  the terms of  the GNU General  Public License as published by the
8149 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8150 + *  option) any later version.
8151 + *
8152 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8153 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8154 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8155 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8156 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8157 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8158 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8159 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8160 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8161 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8162 + *
8163 + *  You should have received a copy of the  GNU General Public License along
8164 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8165 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8166 + *
8167 + *
8168 + **************************************************************************
8169 + * May 2004 rkt, neb.
8170 + *
8171 + * Initial Release
8172 + *
8173 + *
8174 + *
8175 + **************************************************************************
8176 + */
8177 +
8178 +#ifndef __IDT_SPI_H__
8179 +#define __IDT_SPI_H__
8180 +
8181 +enum
8182 +{
8183 +       SPI0_PhysicalAddress    = 0x18070000,
8184 +       SPI_PhysicalAddress     = SPI0_PhysicalAddress,
8185 +
8186 +       SPI0_VirtualAddress     = 0xB8070000,
8187 +       SPI_VirtualAddress      = SPI0_VirtualAddress,
8188 +} ;
8189 +
8190 +typedef struct
8191 +{
8192 +       u32 spcp ;      // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
8193 +       u32 spc ;       // spi control reg use SPC_
8194 +       u32 sps ;       // spi status reg use SPS_
8195 +       u32 spd ;       // spi data reg use SPD_
8196 +       u32 siofunc ;   // serial IO function use SIOFUNC_
8197 +       u32 siocfg ;    // serial IO config use SIOCFG_
8198 +       u32 siod;       // serial IO data use SIOD_
8199 +} volatile *SPI_t ;
8200 +
8201 +enum
8202 +{
8203 +       SPCP_div_b       = 0,
8204 +       SPCP_div_m       = 0x000000ff,
8205 +       SPC_spr_b       = 0,
8206 +       SPC_spr_m       = 0x00000003,
8207 +            SPC_spr_div2_v  = 0,
8208 +            SPC_spr_div4_v  = 1,
8209 +            SPC_spr_div16_v = 2,
8210 +            SPC_spr_div32_v = 3,
8211 +       SPC_cpha_b      = 2,
8212 +       SPC_cpha_m      = 0x00000004,
8213 +       SPC_cpol_b      = 3,
8214 +       SPC_cpol_m      = 0x00000008,
8215 +       SPC_mstr_b      = 4,
8216 +       SPC_mstr_m      = 0x00000010,
8217 +       SPC_spe_b       = 6,
8218 +       SPC_spe_m       = 0x00000040,
8219 +       SPC_spie_b      = 7,
8220 +       SPC_spie_m      = 0x00000080,
8221 +
8222 +       SPS_modf_b      = 4,
8223 +       SPS_modf_m      = 0x00000010,
8224 +       SPS_wcol_b      = 6,
8225 +       SPS_wcol_m      = 0x00000040,
8226 +       SPS_spif_b      = 7,
8227 +       SPS_spif_m      = 0x00000070,
8228 +
8229 +       SPD_data_b      = 0,
8230 +       SPD_data_m      = 0x000000ff,
8231 +
8232 +       SIOFUNC_sdo_b       = 0,
8233 +       SIOFUNC_sdo_m       = 0x00000001,
8234 +       SIOFUNC_sdi_b       = 1,
8235 +       SIOFUNC_sdi_m       = 0x00000002,
8236 +       SIOFUNC_sck_b       = 2,
8237 +       SIOFUNC_sck_m       = 0x00000004,
8238 +       SIOFUNC_pci_b       = 3,
8239 +       SIOFUNC_pci_m       = 0x00000008,
8240 +
8241 +       SIOCFG_sdo_b       = 0,
8242 +       SIOCFG_sdo_m       = 0x00000001,
8243 +       SIOCFG_sdi_b       = 1,
8244 +       SIOCFG_sdi_m       = 0x00000002,
8245 +       SIOCFG_sck_b       = 2,
8246 +       SIOCFG_sck_m       = 0x00000004,
8247 +       SIOCFG_pci_b       = 3,
8248 +       SIOCFG_pci_m       = 0x00000008,
8249 +
8250 +       SIOD_sdo_b       = 0,
8251 +       SIOD_sdo_m       = 0x00000001,
8252 +       SIOD_sdi_b       = 1,
8253 +       SIOD_sdi_m       = 0x00000002,
8254 +       SIOD_sck_b       = 2,
8255 +       SIOD_sck_m       = 0x00000004,
8256 +       SIOD_pci_b       = 3,
8257 +       SIOD_pci_m       = 0x00000008,
8258 +} ;
8259 +#endif // __IDT_SPI_H__
8260 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
8261 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_timer.h    1970-01-01 01:00:00.000000000 +0100
8262 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h       2006-06-18 12:44:28.000000000 +0200
8263 @@ -0,0 +1,91 @@
8264 +/**************************************************************************
8265 + *
8266 + *  BRIEF MODULE DESCRIPTION
8267 + *   Definitions for timer registers
8268 + *
8269 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8270 + *
8271 + *  This program is free software; you can redistribute  it and/or modify it
8272 + *  under  the terms of  the GNU General  Public License as published by the
8273 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8274 + *  option) any later version.
8275 + *
8276 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8277 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8278 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8279 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8280 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8281 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8282 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8283 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8284 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8285 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8286 + *
8287 + *  You should have received a copy of the  GNU General Public License along
8288 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8289 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8290 + *
8291 + *
8292 + **************************************************************************
8293 + * May 2004 rkt,neb.
8294 + *
8295 + * Initial Release
8296 + *
8297 + *
8298 + *
8299 + **************************************************************************
8300 + */
8301 +
8302 +#ifndef __IDT_TIM_H__
8303 +#define __IDT_TIM_H__
8304 +
8305 +enum
8306 +{
8307 +       TIM0_PhysicalAddress    = 0x18028000,
8308 +       TIM_PhysicalAddress     = TIM0_PhysicalAddress,         // Default
8309 +
8310 +       TIM0_VirtualAddress     = 0xb8028000,
8311 +       TIM_VirtualAddress      = TIM0_VirtualAddress,          // Default
8312 +} ;
8313 +
8314 +enum
8315 +{
8316 +       TIM_Count = 3,
8317 +} ;
8318 +
8319 +struct TIM_CNTR_s
8320 +{
8321 +  u32 count ;
8322 +  u32 compare ;
8323 +  u32 ctc ;    //use CTC_
8324 +} ;
8325 +
8326 +typedef struct TIM_s
8327 +{
8328 +  struct TIM_CNTR_s    tim [TIM_Count] ;
8329 +  u32                  rcount ;        //use RCOUNT_
8330 +  u32                  rcompare ;      //use RCOMPARE_
8331 +  u32                  rtc ;           //use RTC_
8332 +} volatile * TIM_t ;
8333 +
8334 +enum
8335 +{
8336 +  CTC_en_b     = 0,
8337 +  CTC_en_m     = 0x00000001,
8338 +  CTC_to_b     = 1,
8339 +  CTC_to_m     = 0x00000002,
8340 +
8341 +  RCOUNT_count_b               = 0,
8342 +  RCOUNT_count_m               = 0x0000ffff,
8343 +  RCOMPARE_compare_b   = 0,
8344 +  RCOMPARE_compare_m   = 0x0000ffff,
8345 +  RTC_ce_b             = 0,
8346 +  RTC_ce_m             = 0x00000001,
8347 +  RTC_to_b             = 1,
8348 +  RTC_to_m             = 0x00000002,
8349 +  RTC_rqe_b            = 2,
8350 +  RTC_rqe_m            = 0x00000004,
8351 +
8352 +} ;
8353 +#endif // __IDT_TIM_H__
8354 +
8355 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
8356 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_uart.h     1970-01-01 01:00:00.000000000 +0100
8357 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h        2006-06-18 12:44:28.000000000 +0200
8358 @@ -0,0 +1,189 @@
8359 +/**************************************************************************
8360 + *
8361 + *  BRIEF MODULE DESCRIPTION
8362 + *   UART register definitions
8363 + *
8364 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8365 + *
8366 + *  This program is free software; you can redistribute  it and/or modify it
8367 + *  under  the terms of  the GNU General  Public License as published by the
8368 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8369 + *  option) any later version.
8370 + *
8371 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8372 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8373 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8374 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8375 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8376 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8377 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8378 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8379 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8380 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8381 + *
8382 + *  You should have received a copy of the  GNU General Public License along
8383 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8384 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8385 + *
8386 + *
8387 + **************************************************************************
8388 + * May 2004 rkt, neb.
8389 + *
8390 + * Initial Release
8391 + *
8392 + *
8393 + *
8394 + **************************************************************************
8395 + */
8396 +
8397 +#ifndef __IDT_UART_H__
8398 +#define __IDT_UART_H__
8399 +
8400 +enum
8401 +{
8402 +       UART0_PhysicalAddress   = 0x1c000000,
8403 +       UART_PhysicalAddress    = UART0_PhysicalAddress,        // Default
8404 +
8405 +       UART0_VirtualAddress    = 0xbc000000,
8406 +       UART_VirtualAddress     = UART0_VirtualAddress,         // Default
8407 +} ;
8408 +
8409 +/*
8410 + * Register definitions are in bytes so we can handle endian problems.
8411 + */
8412 +
8413 +typedef struct UART_s
8414 +{
8415 +       union
8416 +       {
8417 +               u32 const       uartrb ;        // 0x00 - DLAB=0, read.
8418 +               u32             uartth ;        // 0x00 - DLAB=0, write.
8419 +               u32             uartdll ;       // 0x00 - DLAB=1, read/write.
8420 +       } ;
8421 +
8422 +       union
8423 +       {
8424 +               u32             uartie ;        // 0x04 - DLAB=0, read/write.
8425 +               u32             uartdlh ;       // 0x04 - DLAB=1, read/write.
8426 +       } ;
8427 +       union
8428 +       {
8429 +               u32 const       uartii ;        // 0x08 - DLAB=0, read.
8430 +               u32             uartfc ;        // 0x08 - DLAB=0, write.
8431 +       } ;
8432 +
8433 +       u32             uartlc ;                // 0x0c
8434 +       u32             uartmc ;                // 0x10
8435 +       u32             uartls ;                // 0x14
8436 +       u32             uartms ;                // 0x18
8437 +       u32             uarts ;                 // 0x1c
8438 +} volatile *UART_t ;
8439 +
8440 +// Reset registers.
8441 +typedef u32    volatile *UARTRR_t ;
8442 +
8443 +enum
8444 +{
8445 +       UARTIE_rda_b    = 0,
8446 +       UARTIE_rda_m    = 0x00000001,
8447 +       UARTIE_the_b    = 1,
8448 +       UARTIE_the_m    = 0x00000002,
8449 +       UARTIE_rls_b    = 2,
8450 +       UARTIE_rls_m    = 0x00000004,
8451 +       UARTIE_ems_b    = 3,
8452 +       UARTIE_ems_m    = 0x00000008,
8453 +
8454 +       UARTII_pi_b     = 0,
8455 +       UARTII_pi_m     = 0x00000001,
8456 +       UARTII_iid_b    = 1,
8457 +       UARTII_iid_m    = 0x0000000e,
8458 +               UARTII_iid_ms_v         = 0,    // Modem stat-CTS,DSR,RI or DCD.
8459 +               UARTII_iid_thre_v       = 1,    // Trans. Holding Reg. empty.
8460 +               UARTII_iid_rda_v        = 2,    // Receive data available
8461 +               UARTII_iid_rls_v        = 3,    // Overrun, parity, etc, error.
8462 +               UARTII_iid_res4_v       = 4,    // reserved.
8463 +               UARTII_iid_res5_v       = 5,    // reserved.
8464 +               UARTII_iid_cto_v        = 6,    // Character timeout.
8465 +               UARTII_iid_res7_v       = 7,    // reserved.
8466 +
8467 +       UARTFC_en_b     = 0,
8468 +       UARTFC_en_m     = 0x00000001,
8469 +       UARTFC_rr_b     = 1,
8470 +       UARTFC_rr_m     = 0x00000002,
8471 +       UARTFC_tr_b     = 2,
8472 +       UARTFC_tr_m     = 0x00000004,
8473 +       UARTFC_dms_b    = 3,
8474 +       UARTFC_dms_m    = 0x00000008,
8475 +       UARTFC_rt_b     = 6,
8476 +       UARTFC_rt_m     = 0x000000c0,
8477 +               UARTFC_rt_1Byte_v       = 0,
8478 +               UARTFC_rt_4Byte_v       = 1,
8479 +               UARTFC_rt_8Byte_v       = 2,
8480 +               UARTFC_rt_14Byte_v      = 3,
8481 +
8482 +       UARTLC_wls_b    = 0,
8483 +       UARTLC_wls_m    = 0x00000003,
8484 +               UARTLC_wls_5Bits_v      = 0,
8485 +               UARTLC_wls_6Bits_v      = 1,
8486 +               UARTLC_wls_7Bits_v      = 2,
8487 +               UARTLC_wls_8Bits_v      = 3,
8488 +       UARTLC_stb_b    = 2,
8489 +       UARTLC_stb_m    = 0x00000004,
8490 +       UARTLC_pen_b    = 3,
8491 +       UARTLC_pen_m    = 0x00000008,
8492 +       UARTLC_eps_b    = 4,
8493 +       UARTLC_eps_m    = 0x00000010,
8494 +       UARTLC_sp_b     = 5,
8495 +       UARTLC_sp_m     = 0x00000020,
8496 +       UARTLC_sb_b     = 6,
8497 +       UARTLC_sb_m     = 0x00000040,
8498 +       UARTLC_dlab_b   = 7,
8499 +       UARTLC_dlab_m   = 0x00000080,
8500 +
8501 +       UARTMC_dtr_b    = 0,
8502 +       UARTMC_dtr_m    = 0x00000001,
8503 +       UARTMC_rts_b    = 1,
8504 +       UARTMC_rts_m    = 0x00000002,
8505 +       UARTMC_o1_b     = 2,
8506 +       UARTMC_o1_m     = 0x00000004,
8507 +       UARTMC_o2_b     = 3,
8508 +       UARTMC_o2_m     = 0x00000008,
8509 +       UARTMC_lp_b     = 4,
8510 +       UARTMC_lp_m     = 0x00000010,
8511 +
8512 +       UARTLS_dr_b     = 0,
8513 +       UARTLS_dr_m     = 0x00000001,
8514 +       UARTLS_oe_b     = 1,
8515 +       UARTLS_oe_m     = 0x00000002,
8516 +       UARTLS_pe_b     = 2,
8517 +       UARTLS_pe_m     = 0x00000004,
8518 +       UARTLS_fe_b     = 3,
8519 +       UARTLS_fe_m     = 0x00000008,
8520 +       UARTLS_bi_b     = 4,
8521 +       UARTLS_bi_m     = 0x00000010,
8522 +       UARTLS_thr_b    = 5,
8523 +       UARTLS_thr_m    = 0x00000020,
8524 +       UARTLS_te_b     = 6,
8525 +       UARTLS_te_m     = 0x00000040,
8526 +       UARTLS_rfe_b    = 7,
8527 +       UARTLS_rfe_m    = 0x00000080,
8528 +
8529 +       UARTMS_dcts_b   = 0,
8530 +       UARTMS_dcts_m   = 0x00000001,
8531 +       UARTMS_ddsr_b   = 1,
8532 +       UARTMS_ddsr_m   = 0x00000002,
8533 +       UARTMS_teri_b   = 2,
8534 +       UARTMS_teri_m   = 0x00000004,
8535 +       UARTMS_ddcd_b   = 3,
8536 +       UARTMS_ddcd_m   = 0x00000008,
8537 +       UARTMS_cts_b    = 4,
8538 +       UARTMS_cts_m    = 0x00000010,
8539 +       UARTMS_dsr_b    = 5,
8540 +       UARTMS_dsr_m    = 0x00000020,
8541 +       UARTMS_ri_b     = 6,
8542 +       UARTMS_ri_m     = 0x00000040,
8543 +       UARTMS_dcd_b    = 7,
8544 +       UARTMS_dcd_m    = 0x00000080,
8545 +} ;
8546 +
8547 +#endif // __IDT_UART_H__
8548 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
8549 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma.h      1970-01-01 01:00:00.000000000 +0100
8550 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 2006-06-18 12:44:28.000000000 +0200
8551 @@ -0,0 +1,231 @@
8552 +/**************************************************************************
8553 + *
8554 + *  BRIEF MODULE DESCRIPTION
8555 + *   Register definitions for  IDT RC32438 DMA.
8556 + *
8557 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8558 + *
8559 + *  This program is free software; you can redistribute  it and/or modify it
8560 + *  under  the terms of  the GNU General  Public License as published by the
8561 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8562 + *  option) any later version.
8563 + *
8564 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8565 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8566 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8567 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8568 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8569 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8570 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8571 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8572 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8573 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8574 + *
8575 + *  You should have received a copy of the  GNU General Public License along
8576 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8577 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8578 + *
8579 + *
8580 + **************************************************************************
8581 + * May 2004 P. Sadik.
8582 + *
8583 + * Initial Release
8584 + *
8585 + *
8586 + *
8587 + **************************************************************************
8588 + */
8589 +#ifndef __IDT_RC32438_DMA_H__
8590 +#define __IDT_RC32438_DMA_H__
8591 +enum
8592 +{
8593 +       DMA0_PhysicalAddress    = 0x18040000,
8594 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
8595 +
8596 +       DMA0_VirtualAddress     = 0xb8040000,
8597 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
8598 +} ;
8599 +
8600 +/*
8601 + * DMA descriptor (in physical memory).
8602 + */
8603 +
8604 +typedef struct DMAD_s
8605 +{
8606 +       u32                     control ;       // Control. use DMAD_*
8607 +       u32                     ca ;            // Current Address.
8608 +       u32                     devcs ;         // Device control and status.
8609 +       u32                     link ;          // Next descriptor in chain.
8610 +} volatile *DMAD_t ;
8611 +
8612 +enum
8613 +{
8614 +       DMAD_size               = sizeof (struct DMAD_s),
8615 +       DMAD_count_b            = 0,            // in DMAD_t -> control
8616 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
8617 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
8618 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
8619 +               DMAD_ds_extToMem0_v     = 0,
8620 +               DMAD_ds_memToExt0_v     = 1,
8621 +               DMAD_ds_extToMem1_v     = 0,
8622 +               DMAD_ds_memToExt1_v     = 1,
8623 +               DMAD_ds_ethRcv0_v       = 0,
8624 +               DMAD_ds_ethXmt0_v       = 0,
8625 +               DMAD_ds_ethRcv1_v       = 0,
8626 +               DMAD_ds_ethXmt2_v       = 0,
8627 +               DMAD_ds_memToFifo_v     = 0,
8628 +               DMAD_ds_fifoToMem_v     = 0,
8629 +               DMAD_ds_rng_de_v           = 1,//randomNumberGenerator on LC/DE
8630 +               DMAD_ds_pciToMem_v      = 0,
8631 +               DMAD_ds_memToPci_v      = 0,
8632 +               DMAD_ds_securityInput_v = 0,
8633 +               DMAD_ds_securityOutput_v = 0,
8634 +               DMAD_ds_rng_se_v        = 0,//randomNumberGenerator on SE
8635 +
8636 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
8637 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
8638 +               DMAD_devcmd_byte_v      = 0,    //memory-to-memory
8639 +               DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
8640 +               DMAD_devcmd_word_v      = 2,    //memory-to-memory
8641 +               DMAD_devcmd_2words_v    = 3,    //memory-to-memory
8642 +               DMAD_devcmd_4words_v    = 4,    //memory-to-memory
8643 +               DMAD_devcmd_6words_v    = 5,    //memory-to-memory
8644 +               DMAD_devcmd_8words_v    = 6,    //memory-to-memory
8645 +               DMAD_devcmd_16words_v   = 7,    //memory-to-memory
8646 +       DMAD_cof_b              = 25,           // chain on finished
8647 +       DMAD_cof_m              = 0x02000000,   //
8648 +       DMAD_cod_b              = 26,           // chain on done
8649 +       DMAD_cod_m              = 0x04000000,   //
8650 +       DMAD_iof_b              = 27,           // interrupt on finished
8651 +       DMAD_iof_m              = 0x08000000,   //
8652 +       DMAD_iod_b              = 28,           // interrupt on done
8653 +       DMAD_iod_m              = 0x10000000,   //
8654 +       DMAD_t_b                = 29,           // terminated
8655 +       DMAD_t_m                = 0x20000000,   //
8656 +       DMAD_d_b                = 30,           // done
8657 +       DMAD_d_m                = 0x40000000,   //
8658 +       DMAD_f_b                = 31,           // finished
8659 +       DMAD_f_m                = 0x80000000,   //
8660 +} ;
8661 +
8662 +/*
8663 + * DMA register (within Internal Register Map).
8664 + */
8665 +
8666 +struct DMA_Chan_s
8667 +{
8668 +       u32             dmac ;          // Control.
8669 +       u32             dmas ;          // Status.
8670 +       u32             dmasm ;         // Mask.
8671 +       u32             dmadptr ;       // Descriptor pointer.
8672 +       u32             dmandptr ;      // Next descriptor pointer.
8673 +};
8674 +
8675 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
8676 +
8677 +//DMA_Channels   use DMACH_count instead
8678 +
8679 +enum
8680 +{
8681 +       DMAC_run_b      = 0,            //
8682 +       DMAC_run_m      = 0x00000001,   //
8683 +       DMAC_dm_b       = 1,            // done mask
8684 +       DMAC_dm_m       = 0x00000002,   //
8685 +       DMAC_mode_b     = 2,            //
8686 +       DMAC_mode_m     = 0x0000000c,   //
8687 +               DMAC_mode_auto_v        = 0,
8688 +               DMAC_mode_burst_v       = 1,
8689 +               DMAC_mode_transfer_v    = 2, //usually used
8690 +               DMAC_mode_reserved_v    = 3,
8691 +       DMAC_a_b        = 4,            //
8692 +       DMAC_a_m        = 0x00000010,   //
8693 +
8694 +       DMAS_f_b        = 0,            // finished (sticky)
8695 +       DMAS_f_m        = 0x00000001,   //
8696 +       DMAS_d_b        = 1,            // done (sticky)
8697 +       DMAS_d_m        = 0x00000002,   //
8698 +       DMAS_c_b        = 2,            // chain (sticky)
8699 +       DMAS_c_m        = 0x00000004,   //
8700 +       DMAS_e_b        = 3,            // error (sticky)
8701 +       DMAS_e_m        = 0x00000008,   //
8702 +       DMAS_h_b        = 4,            // halt (sticky)
8703 +       DMAS_h_m        = 0x00000010,   //
8704 +
8705 +       DMASM_f_b       = 0,            // finished (1=mask)
8706 +       DMASM_f_m       = 0x00000001,   //
8707 +       DMASM_d_b       = 1,            // done (1=mask)
8708 +       DMASM_d_m       = 0x00000002,   //
8709 +       DMASM_c_b       = 2,            // chain (1=mask)
8710 +       DMASM_c_m       = 0x00000004,   //
8711 +       DMASM_e_b       = 3,            // error (1=mask)
8712 +       DMASM_e_m       = 0x00000008,   //
8713 +       DMASM_h_b       = 4,            // halt (1=mask)
8714 +       DMASM_h_m       = 0x00000010,   //
8715 +} ;
8716 +
8717 +/*
8718 + * DMA channel definitions
8719 + */
8720 +
8721 +enum
8722 +{
8723 +       DMACH_extToMem0 = 0,
8724 +       DMACH_memToExt0 = 0,
8725 +       DMACH_extToMem1 = 1,
8726 +       DMACH_memToExt1 = 1,
8727 +       DMACH_ethRcv0 = 2,
8728 +       DMACH_ethXmt0 = 3,
8729 +       DMACH_ethRcv1 = 4,
8730 +       DMACH_ethXmt2 = 5,
8731 +       DMACH_memToFifo = 6,
8732 +       DMACH_fifoToMem = 7,
8733 +       DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
8734 +       DMACH_pciToMem = 8,
8735 +       DMACH_memToPci = 9,
8736 +       DMACH_securityInput = 10,
8737 +       DMACH_securityOutput = 11,
8738 +       DMACH_rng_se = 12, //randomNumberGenerator on SE
8739 +
8740 +       DMACH_count //must be last
8741 +};
8742 +
8743 +
8744 +typedef struct DMAC_s
8745 +{
8746 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
8747 +} volatile *DMA_t ;
8748 +
8749 +
8750 +/*
8751 + * External DMA parameters
8752 +*/
8753 +
8754 +enum
8755 +{
8756 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
8757 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
8758 +               DMADEVCMD_ts_byte_v     = 0,
8759 +               DMADEVCMD_ts_halfword_v = 1,
8760 +               DMADEVCMD_ts_word_v     = 2,
8761 +               DMADEVCMD_ts_2word_v    = 3,
8762 +               DMADEVCMD_ts_4word_v    = 4,
8763 +               DMADEVCMD_ts_6word_v    = 5,
8764 +               DMADEVCMD_ts_8word_v    = 6,
8765 +               DMADEVCMD_ts_16word_v   = 7
8766 +};
8767 +
8768 +
8769 +#if 1  // aws - Compatibility.
8770 +#      define  EXTDMA_ts_b             DMADEVCMD_ts_b
8771 +#      define  EXTDMA_ts_m             DMADEVCMD_ts_m
8772 +#      define  EXTDMA_ts_byte_v        DMADEVCMD_ts_byte_v
8773 +#      define  EXTDMA_ts_halfword_v    DMADEVCMD_ts_halfword_v
8774 +#      define  EXTDMA_ts_word_v        DMADEVCMD_ts_word_v
8775 +#      define  EXTDMA_ts_2word_v       DMADEVCMD_ts_2word_v
8776 +#      define  EXTDMA_ts_4word_v       DMADEVCMD_ts_4word_v
8777 +#      define  EXTDMA_ts_6word_v       DMADEVCMD_ts_6word_v
8778 +#      define  EXTDMA_ts_8word_v       DMADEVCMD_ts_8word_v
8779 +#      define  EXTDMA_ts_16word_v      DMADEVCMD_ts_16word_v
8780 +#endif // aws - Compatibility.
8781 +
8782 +#endif //__IDT_RC32438_DMA_H__
8783 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
8784 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h    1970-01-01 01:00:00.000000000 +0100
8785 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h       2006-06-18 12:44:28.000000000 +0200
8786 @@ -0,0 +1,82 @@
8787 +/**************************************************************************
8788 + *
8789 + *  BRIEF MODULE DESCRIPTION
8790 + *   DMA operations for IDT RC32438.
8791 + *
8792 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8793 + *
8794 + *  This program is free software; you can redistribute  it and/or modify it
8795 + *  under  the terms of  the GNU General  Public License as published by the
8796 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8797 + *  option) any later version.
8798 + *
8799 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8800 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8801 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8802 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8803 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8804 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8805 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8806 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8807 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8808 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8809 + *
8810 + *  You should have received a copy of the  GNU General Public License along
8811 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8812 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8813 + *
8814 + *
8815 + **************************************************************************
8816 + * May 2004 P. Sadik.
8817 + *
8818 + * Initial Release
8819 + *
8820 + *
8821 + *
8822 + **************************************************************************
8823 + */
8824 +
8825 +#ifndef __IDT_RC32438_DMA_V_H__
8826 +#define __IDT_RC32438_DMA_V_H__
8827 +#include  <asm/idt-boards/rc32438/rc32438_dma.h>
8828 +
8829 +#define DMA_CHAN_OFFSET  0x14
8830 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
8831 +#define DMA_COUNT(count)   \
8832 +  ((count) & DMAD_count_m)
8833 +
8834 +#define DMA_HALT_TIMEOUT 500
8835 +
8836 +
8837 +static inline int rc32438_halt_dma(DMA_Chan_t ch)
8838 +{
8839 +       int timeout=1;
8840 +       if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
8841 +               rc32438_writel(0, &ch->dmac);
8842 +
8843 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
8844 +                       if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
8845 +                               rc32438_writel(0, &ch->dmas);
8846 +                               break;
8847 +                       }
8848 +               }
8849 +
8850 +       }
8851 +
8852 +       return timeout ? 0 : 1;
8853 +}
8854 +
8855 +
8856 +
8857 +
8858 +static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
8859 +{
8860 +       rc32438_writel(0, &ch->dmandptr);
8861 +       rc32438_writel(dma_addr, &ch->dmadptr);
8862 +}
8863 +
8864 +static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
8865 +{
8866 +       rc32438_writel(dma_addr, &ch->dmandptr);
8867 +}
8868 +#endif //__IDT_RC32438_DMA_V_H__
8869 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
8870 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth.h      1970-01-01 01:00:00.000000000 +0100
8871 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 2006-06-18 12:44:28.000000000 +0200
8872 @@ -0,0 +1,328 @@
8873 +/**************************************************************************
8874 + *
8875 + *  BRIEF MODULE DESCRIPTION
8876 + *   Definitions for IDT EB438 ethernet
8877 + *
8878 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8879 + *
8880 + *  This program is free software; you can redistribute  it and/or modify it
8881 + *  under  the terms of  the GNU General  Public License as published by the
8882 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8883 + *  option) any later version.
8884 + *
8885 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8886 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8887 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8888 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8889 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8890 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8891 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8892 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8893 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8894 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8895 + *
8896 + *  You should have received a copy of the  GNU General Public License along
8897 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8898 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8899 + *
8900 + *
8901 + **************************************************************************
8902 + * May 2004 P. Sadik.
8903 + *
8904 + * Initial Release
8905 + *
8906 + *
8907 + *
8908 + **************************************************************************
8909 + */
8910 +
8911 +#ifndef __IDT_RC32438_ETH_H__
8912 +#define __IDT_RC32438_ETH_H__
8913 +enum
8914 +{
8915 +       ETH0_PhysicalAddress    = 0x18058000,
8916 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
8917 +
8918 +       ETH0_VirtualAddress     = 0xb8058000,
8919 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
8920 +       ETH1_PhysicalAddress    = 0x18060000,
8921 +       ETH1_VirtualAddress     = 0xb8060000,                   // Default
8922 +} ;
8923 +
8924 +typedef struct
8925 +{
8926 +       u32 ethintfc            ;
8927 +       u32 ethfifott           ;
8928 +       u32 etharc              ;
8929 +       u32 ethhash0            ;
8930 +       u32 ethhash1            ;
8931 +       u32 ethu0 [4]           ;       // Reserved.
8932 +       u32 ethpfs              ;
8933 +       u32 ethmcp              ;
8934 +       u32 eth_u1 [10]         ;       // Reserved.
8935 +       u32 ethspare            ;
8936 +       u32 eth_u2 [42]         ;       // Reserved.
8937 +       u32 ethsal0             ;
8938 +       u32 ethsah0             ;
8939 +       u32 ethsal1             ;
8940 +       u32 ethsah1             ;
8941 +       u32 ethsal2             ;
8942 +       u32 ethsah2             ;
8943 +       u32 ethsal3             ;
8944 +       u32 ethsah3             ;
8945 +       u32 ethrbc              ;
8946 +       u32 ethrpc              ;
8947 +       u32 ethrupc             ;
8948 +       u32 ethrfc              ;
8949 +       u32 ethtbc              ;
8950 +       u32 ethgpf              ;
8951 +       u32 eth_u9 [50]         ;       // Reserved.
8952 +       u32 ethmac1             ;
8953 +       u32 ethmac2             ;
8954 +       u32 ethipgt             ;
8955 +       u32 ethipgr             ;
8956 +       u32 ethclrt             ;
8957 +       u32 ethmaxf             ;
8958 +       u32 eth_u10             ;       // Reserved.
8959 +       u32 ethmtest            ;
8960 +       u32 miimcfg             ;
8961 +       u32 miimcmd             ;
8962 +       u32 miimaddr            ;
8963 +       u32 miimwtd             ;
8964 +       u32 miimrdd             ;
8965 +       u32 miimind             ;
8966 +       u32 eth_u11             ;       // Reserved.
8967 +       u32 eth_u12             ;       // Reserved.
8968 +       u32 ethcfsa0            ;
8969 +       u32 ethcfsa1            ;
8970 +       u32 ethcfsa2            ;
8971 +} volatile *ETH_t;
8972 +
8973 +enum
8974 +{
8975 +       ETHINTFC_en_b           = 0,
8976 +       ETHINTFC_en_m           = 0x00000001,
8977 +       ETHINTFC_its_b          = 1,
8978 +       ETHINTFC_its_m          = 0x00000002,
8979 +       ETHINTFC_rip_b          = 2,
8980 +       ETHINTFC_rip_m          = 0x00000004,
8981 +       ETHINTFC_jam_b          = 3,
8982 +       ETHINTFC_jam_m          = 0x00000008,
8983 +       ETHINTFC_ovr_b          = 4,
8984 +       ETHINTFC_ovr_m          = 0x00000010,
8985 +       ETHINTFC_und_b          = 5,
8986 +       ETHINTFC_und_m          = 0x00000020,
8987 +
8988 +       ETHFIFOTT_tth_b         = 0,
8989 +       ETHFIFOTT_tth_m         = 0x0000007f,
8990 +
8991 +       ETHARC_pro_b            = 0,
8992 +       ETHARC_pro_m            = 0x00000001,
8993 +       ETHARC_am_b             = 1,
8994 +       ETHARC_am_m             = 0x00000002,
8995 +       ETHARC_afm_b            = 2,
8996 +       ETHARC_afm_m            = 0x00000004,
8997 +       ETHARC_ab_b             = 3,
8998 +       ETHARC_ab_m             = 0x00000008,
8999 +
9000 +       ETHSAL_byte5_b          = 0,
9001 +       ETHSAL_byte5_m          = 0x000000ff,
9002 +       ETHSAL_byte4_b          = 8,
9003 +       ETHSAL_byte4_m          = 0x0000ff00,
9004 +       ETHSAL_byte3_b          = 16,
9005 +       ETHSAL_byte3_m          = 0x00ff0000,
9006 +       ETHSAL_byte2_b          = 24,
9007 +       ETHSAL_byte2_m          = 0xff000000,
9008 +
9009 +       ETHSAH_byte1_b          = 0,
9010 +       ETHSAH_byte1_m          = 0x000000ff,
9011 +       ETHSAH_byte0_b          = 8,
9012 +       ETHSAH_byte0_m          = 0x0000ff00,
9013 +
9014 +       ETHGPF_ptv_b            = 0,
9015 +       ETHGPF_ptv_m            = 0x0000ffff,
9016 +
9017 +       ETHPFS_pfd_b            = 0,
9018 +       ETHPFS_pfd_m            = 0x00000001,
9019 +
9020 +       ETHCFSA0_cfsa4_b        = 0,
9021 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
9022 +       ETHCFSA0_cfsa5_b        = 8,
9023 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
9024 +
9025 +       ETHCFSA1_cfsa2_b        = 0,
9026 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
9027 +       ETHCFSA1_cfsa3_b        = 8,
9028 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
9029 +
9030 +       ETHCFSA2_cfsa0_b        = 0,
9031 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
9032 +       ETHCFSA2_cfsa1_b        = 8,
9033 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
9034 +
9035 +       ETHMAC1_re_b            = 0,
9036 +       ETHMAC1_re_m            = 0x00000001,
9037 +       ETHMAC1_paf_b           = 1,
9038 +       ETHMAC1_paf_m           = 0x00000002,
9039 +       ETHMAC1_rfc_b           = 2,
9040 +       ETHMAC1_rfc_m           = 0x00000004,
9041 +       ETHMAC1_tfc_b           = 3,
9042 +       ETHMAC1_tfc_m           = 0x00000008,
9043 +       ETHMAC1_lb_b            = 4,
9044 +       ETHMAC1_lb_m            = 0x00000010,
9045 +       ETHMAC1_mr_b            = 31,
9046 +       ETHMAC1_mr_m            = 0x80000000,
9047 +
9048 +       ETHMAC2_fd_b            = 0,
9049 +       ETHMAC2_fd_m            = 0x00000001,
9050 +       ETHMAC2_flc_b           = 1,
9051 +       ETHMAC2_flc_m           = 0x00000002,
9052 +       ETHMAC2_hfe_b           = 2,
9053 +       ETHMAC2_hfe_m           = 0x00000004,
9054 +       ETHMAC2_dc_b            = 3,
9055 +       ETHMAC2_dc_m            = 0x00000008,
9056 +       ETHMAC2_cen_b           = 4,
9057 +       ETHMAC2_cen_m           = 0x00000010,
9058 +       ETHMAC2_pe_b            = 5,
9059 +       ETHMAC2_pe_m            = 0x00000020,
9060 +       ETHMAC2_vpe_b           = 6,
9061 +       ETHMAC2_vpe_m           = 0x00000040,
9062 +       ETHMAC2_ape_b           = 7,
9063 +       ETHMAC2_ape_m           = 0x00000080,
9064 +       ETHMAC2_ppe_b           = 8,
9065 +       ETHMAC2_ppe_m           = 0x00000100,
9066 +       ETHMAC2_lpe_b           = 9,
9067 +       ETHMAC2_lpe_m           = 0x00000200,
9068 +       ETHMAC2_nb_b            = 12,
9069 +       ETHMAC2_nb_m            = 0x00001000,
9070 +       ETHMAC2_bp_b            = 13,
9071 +       ETHMAC2_bp_m            = 0x00002000,
9072 +       ETHMAC2_ed_b            = 14,
9073 +       ETHMAC2_ed_m            = 0x00004000,
9074 +
9075 +       ETHIPGT_ipgt_b          = 0,
9076 +       ETHIPGT_ipgt_m          = 0x0000007f,
9077 +
9078 +       ETHIPGR_ipgr2_b         = 0,
9079 +       ETHIPGR_ipgr2_m         = 0x0000007f,
9080 +       ETHIPGR_ipgr1_b         = 8,
9081 +       ETHIPGR_ipgr1_m         = 0x00007f00,
9082 +
9083 +       ETHCLRT_maxret_b        = 0,
9084 +       ETHCLRT_maxret_m        = 0x0000000f,
9085 +       ETHCLRT_colwin_b        = 8,
9086 +       ETHCLRT_colwin_m        = 0x00003f00,
9087 +
9088 +       ETHMAXF_maxf_b          = 0,
9089 +       ETHMAXF_maxf_m          = 0x0000ffff,
9090 +
9091 +       ETHMTEST_tb_b           = 2,
9092 +       ETHMTEST_tb_m           = 0x00000004,
9093 +
9094 +       ETHMCP_div_b            = 0,
9095 +       ETHMCP_div_m            = 0x000000ff,
9096 +
9097 +       MIIMCFG_rsv_b           = 0,
9098 +       MIIMCFG_rsv_m           = 0x0000000c,
9099 +
9100 +       MIIMCMD_rd_b            = 0,
9101 +       MIIMCMD_rd_m            = 0x00000001,
9102 +       MIIMCMD_scn_b           = 1,
9103 +       MIIMCMD_scn_m           = 0x00000002,
9104 +
9105 +       MIIMADDR_regaddr_b      = 0,
9106 +       MIIMADDR_regaddr_m      = 0x0000001f,
9107 +       MIIMADDR_phyaddr_b      = 8,
9108 +       MIIMADDR_phyaddr_m      = 0x00001f00,
9109 +
9110 +       MIIMWTD_wdata_b         = 0,
9111 +       MIIMWTD_wdata_m         = 0x0000ffff,
9112 +
9113 +       MIIMRDD_rdata_b         = 0,
9114 +       MIIMRDD_rdata_m         = 0x0000ffff,
9115 +
9116 +       MIIMIND_bsy_b           = 0,
9117 +       MIIMIND_bsy_m           = 0x00000001,
9118 +       MIIMIND_scn_b           = 1,
9119 +       MIIMIND_scn_m           = 0x00000002,
9120 +       MIIMIND_nv_b            = 2,
9121 +       MIIMIND_nv_m            = 0x00000004,
9122 +
9123 +} ;
9124 +
9125 +/*
9126 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
9127 + */
9128 +enum
9129 +{
9130 +       ETHRX_fd_b              = 0,
9131 +       ETHRX_fd_m              = 0x00000001,
9132 +       ETHRX_ld_b              = 1,
9133 +       ETHRX_ld_m              = 0x00000002,
9134 +       ETHRX_rok_b             = 2,
9135 +       ETHRX_rok_m             = 0x00000004,
9136 +       ETHRX_fm_b              = 3,
9137 +       ETHRX_fm_m              = 0x00000008,
9138 +       ETHRX_mp_b              = 4,
9139 +       ETHRX_mp_m              = 0x00000010,
9140 +       ETHRX_bp_b              = 5,
9141 +       ETHRX_bp_m              = 0x00000020,
9142 +       ETHRX_vlt_b             = 6,
9143 +       ETHRX_vlt_m             = 0x00000040,
9144 +       ETHRX_cf_b              = 7,
9145 +       ETHRX_cf_m              = 0x00000080,
9146 +       ETHRX_ovr_b             = 8,
9147 +       ETHRX_ovr_m             = 0x00000100,
9148 +       ETHRX_crc_b             = 9,
9149 +       ETHRX_crc_m             = 0x00000200,
9150 +       ETHRX_cv_b              = 10,
9151 +       ETHRX_cv_m              = 0x00000400,
9152 +       ETHRX_db_b              = 11,
9153 +       ETHRX_db_m              = 0x00000800,
9154 +       ETHRX_le_b              = 12,
9155 +       ETHRX_le_m              = 0x00001000,
9156 +       ETHRX_lor_b             = 13,
9157 +       ETHRX_lor_m             = 0x00002000,
9158 +       ETHRX_ces_b             = 14,
9159 +       ETHRX_ces_m             = 0x00004000,
9160 +       ETHRX_length_b          = 16,
9161 +       ETHRX_length_m          = 0xffff0000,
9162 +
9163 +       ETHTX_fd_b              = 0,
9164 +       ETHTX_fd_m              = 0x00000001,
9165 +       ETHTX_ld_b              = 1,
9166 +       ETHTX_ld_m              = 0x00000002,
9167 +       ETHTX_oen_b             = 2,
9168 +       ETHTX_oen_m             = 0x00000004,
9169 +       ETHTX_pen_b             = 3,
9170 +       ETHTX_pen_m             = 0x00000008,
9171 +       ETHTX_cen_b             = 4,
9172 +       ETHTX_cen_m             = 0x00000010,
9173 +       ETHTX_hen_b             = 5,
9174 +       ETHTX_hen_m             = 0x00000020,
9175 +       ETHTX_tok_b             = 6,
9176 +       ETHTX_tok_m             = 0x00000040,
9177 +       ETHTX_mp_b              = 7,
9178 +       ETHTX_mp_m              = 0x00000080,
9179 +       ETHTX_bp_b              = 8,
9180 +       ETHTX_bp_m              = 0x00000100,
9181 +       ETHTX_und_b             = 9,
9182 +       ETHTX_und_m             = 0x00000200,
9183 +       ETHTX_of_b              = 10,
9184 +       ETHTX_of_m              = 0x00000400,
9185 +       ETHTX_ed_b              = 11,
9186 +       ETHTX_ed_m              = 0x00000800,
9187 +       ETHTX_ec_b              = 12,
9188 +       ETHTX_ec_m              = 0x00001000,
9189 +       ETHTX_lc_b              = 13,
9190 +       ETHTX_lc_m              = 0x00002000,
9191 +       ETHTX_td_b              = 14,
9192 +       ETHTX_td_m              = 0x00004000,
9193 +       ETHTX_crc_b             = 15,
9194 +       ETHTX_crc_m             = 0x00008000,
9195 +       ETHTX_le_b              = 16,
9196 +       ETHTX_le_m              = 0x00010000,
9197 +       ETHTX_cc_b              = 17,
9198 +       ETHTX_cc_m              = 0x001E0000,
9199 +} ;
9200 +#endif //__IDT_RC32438_ETH_H__
9201 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
9202 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h    1970-01-01 01:00:00.000000000 +0100
9203 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h       2006-06-18 12:44:28.000000000 +0200
9204 @@ -0,0 +1,72 @@
9205 +/**************************************************************************
9206 + *
9207 + *  BRIEF MODULE DESCRIPTION
9208 + *   macros for IDT EB438 ethernet
9209 + *
9210 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9211 + *
9212 + *  This program is free software; you can redistribute  it and/or modify it
9213 + *  under  the terms of  the GNU General  Public License as published by the
9214 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9215 + *  option) any later version.
9216 + *
9217 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9218 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9219 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9220 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9221 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9222 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9223 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9224 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9225 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9226 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9227 + *
9228 + *  You should have received a copy of the  GNU General Public License along
9229 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9230 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9231 + *
9232 + *
9233 + **************************************************************************
9234 + * May 2004 P. Sadik.
9235 + *
9236 + * Initial Release
9237 + *
9238 + *
9239 + *
9240 + **************************************************************************
9241 + */
9242 +
9243 +#ifndef __IDT_RC32438_ETH_V_H__
9244 +#define __IDT_RC32438_ETH_V_H__
9245 +#include  <asm/idt-boards/rc32438/rc32438_eth.h>
9246 +
9247 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
9248 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
9249 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
9250 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
9251 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
9252 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
9253 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
9254 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
9255 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
9256 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
9257 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
9258 +
9259 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
9260 +
9261 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
9262 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
9263 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
9264 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
9265 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
9266 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
9267 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
9268 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
9269 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
9270 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
9271 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
9272 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
9273 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
9274 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
9275 +
9276 +#endif //__IDT_RC32438_ETH_V_H__
9277 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
9278 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h     1970-01-01 01:00:00.000000000 +0100
9279 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h        2006-06-18 12:44:28.000000000 +0200
9280 @@ -0,0 +1,257 @@
9281 +/**************************************************************************
9282 + *
9283 + *  BRIEF MODULE DESCRIPTION
9284 + *   Definitions for IDT RC32438 GPIO.
9285 + *
9286 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9287 + *
9288 + *  This program is free software; you can redistribute  it and/or modify it
9289 + *  under  the terms of  the GNU General  Public License as published by the
9290 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9291 + *  option) any later version.
9292 + *
9293 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9294 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9295 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9296 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9297 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9298 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9299 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9300 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9301 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9302 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9303 + *
9304 + *  You should have received a copy of the  GNU General Public License along
9305 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9306 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9307 + *
9308 + *
9309 + **************************************************************************
9310 + * May 2004 P. Sadik.
9311 + *
9312 + * Initial Release
9313 + *
9314 + *
9315 + *
9316 + **************************************************************************
9317 + */
9318 +#ifndef __IDT_RC32438_GPIO_H__
9319 +#define __IDT_RC32438_GPIO_H__
9320 +enum
9321 +{
9322 +       GPIO0_PhysicalAddress   = 0x18048000,
9323 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
9324 +
9325 +       GPIO0_VirtualAddress    = 0xb8048000,
9326 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
9327 +} ;
9328 +
9329 +typedef struct
9330 +{
9331 +       u32   gpiofunc;   /* GPIO Function Register
9332 +                          * gpiofunc[x]==0 bit = gpio
9333 +                          * func[x]==1  bit = altfunc
9334 +                          */
9335 +       u32   gpiocfg;    /* GPIO Configuration Register
9336 +                          * gpiocfg[x]==0 bit = input
9337 +                          * gpiocfg[x]==1 bit = output
9338 +                          */
9339 +       u32   gpiod;      /* GPIO Data Register
9340 +                          * gpiod[x] read/write gpio pinX status
9341 +                          */
9342 +       u32   gpioilevel; /* GPIO Interrupt Status Register
9343 +                          * interrupt level (see gpioistat)
9344 +                          */
9345 +       u32   gpioistat;  /* Gpio Interrupt Status Register
9346 +                          * istat[x] = (gpiod[x] == level[x])
9347 +                          * cleared in ISR (STICKY bits)
9348 +                          */
9349 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
9350 +} volatile * GPIO_t ;
9351 +
9352 +typedef enum
9353 +{
9354 +       GPIO_gpio_v             = 0,            // gpiofunc use pin as GPIO.
9355 +       GPIO_alt_v              = 1,            // gpiofunc use pin as alt.
9356 +       GPIO_input_v            = 0,            // gpiocfg use pin as input.
9357 +       GPIO_output_v           = 1,            // gpiocfg use pin as output.
9358 +       GPIO_pin0_b             = 0,
9359 +       GPIO_pin0_m             = 0x00000001,
9360 +       GPIO_pin1_b             = 1,
9361 +       GPIO_pin1_m             = 0x00000002,
9362 +       GPIO_pin2_b             = 2,
9363 +       GPIO_pin2_m             = 0x00000004,
9364 +       GPIO_pin3_b             = 3,
9365 +       GPIO_pin3_m             = 0x00000008,
9366 +       GPIO_pin4_b             = 4,
9367 +       GPIO_pin4_m             = 0x00000010,
9368 +       GPIO_pin5_b             = 5,
9369 +       GPIO_pin5_m             = 0x00000020,
9370 +       GPIO_pin6_b             = 6,
9371 +       GPIO_pin6_m             = 0x00000040,
9372 +       GPIO_pin7_b             = 7,
9373 +       GPIO_pin7_m             = 0x00000080,
9374 +       GPIO_pin8_b             = 8,
9375 +       GPIO_pin8_m             = 0x00000100,
9376 +       GPIO_pin9_b             = 9,
9377 +       GPIO_pin9_m             = 0x00000200,
9378 +       GPIO_pin10_b            = 10,
9379 +       GPIO_pin10_m            = 0x00000400,
9380 +       GPIO_pin11_b            = 11,
9381 +       GPIO_pin11_m            = 0x00000800,
9382 +       GPIO_pin12_b            = 12,
9383 +       GPIO_pin12_m            = 0x00001000,
9384 +       GPIO_pin13_b            = 13,
9385 +       GPIO_pin13_m            = 0x00002000,
9386 +       GPIO_pin14_b            = 14,
9387 +       GPIO_pin14_m            = 0x00004000,
9388 +       GPIO_pin15_b            = 15,
9389 +       GPIO_pin15_m            = 0x00008000,
9390 +       GPIO_pin16_b            = 16,
9391 +       GPIO_pin16_m            = 0x00010000,
9392 +       GPIO_pin17_b            = 17,
9393 +       GPIO_pin17_m            = 0x00020000,
9394 +       GPIO_pin18_b            = 18,
9395 +       GPIO_pin18_m            = 0x00040000,
9396 +       GPIO_pin19_b            = 19,
9397 +       GPIO_pin19_m            = 0x00080000,
9398 +       GPIO_pin20_b            = 20,
9399 +       GPIO_pin20_m            = 0x00100000,
9400 +       GPIO_pin21_b            = 21,
9401 +       GPIO_pin21_m            = 0x00200000,
9402 +       GPIO_pin22_b            = 22,
9403 +       GPIO_pin22_m            = 0x00400000,
9404 +       GPIO_pin23_b            = 23,
9405 +       GPIO_pin23_m            = 0x00800000,
9406 +       GPIO_pin24_b            = 24,
9407 +       GPIO_pin24_m            = 0x01000000,
9408 +       GPIO_pin25_b            = 25,
9409 +       GPIO_pin25_m            = 0x02000000,
9410 +       GPIO_pin26_b            = 26,
9411 +       GPIO_pin26_m            = 0x04000000,
9412 +       GPIO_pin27_b            = 27,
9413 +       GPIO_pin27_m            = 0x08000000,
9414 +       GPIO_pin28_b            = 28,
9415 +       GPIO_pin28_m            = 0x10000000,
9416 +       GPIO_pin29_b            = 29,
9417 +       GPIO_pin29_m            = 0x20000000,
9418 +       GPIO_pin30_b            = 30,
9419 +       GPIO_pin30_m            = 0x40000000,
9420 +       GPIO_pin31_b            = 31,
9421 +       GPIO_pin31_m            = 0x80000000,
9422 +
9423 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
9424 +
9425 +       GPIO_u0sout_b           = GPIO_pin0_b,          // UART 0 serial out.
9426 +       GPIO_u0sout_m           = GPIO_pin0_m,
9427 +               GPIO_u0sout_cfg_v       = GPIO_output_v,
9428 +       GPIO_u0sinp_b   = GPIO_pin1_b,                  // UART 0 serial in.
9429 +       GPIO_u0sinp_m   = GPIO_pin1_m,
9430 +               GPIO_u0sinp_cfg_v       = GPIO_input_v,
9431 +       GPIO_u0rin_b    = GPIO_pin2_b,                  // UART 0 ring indic.
9432 +       GPIO_u0rin_m    = GPIO_pin2_m,
9433 +               GPIO_u0rin_cfg_v        = GPIO_input_v,
9434 +       GPIO_u0dcdn_b   = GPIO_pin3_b,                  // UART 0 data carr.det.
9435 +       GPIO_u0dcdn_m   = GPIO_pin3_m,
9436 +               GPIO_u0dcdn_cfg_v       = GPIO_input_v,
9437 +       GPIO_u0dtrn_b   = GPIO_pin4_b,                  // UART 0 data term rdy.
9438 +       GPIO_u0dtrn_m   = GPIO_pin4_m,
9439 +               GPIO_u0dtrn_cfg_v       = GPIO_output_v,
9440 +       GPIO_u0dsrn_b   = GPIO_pin5_b,                  // UART 0 data set rdy.
9441 +       GPIO_u0dsrn_m   = GPIO_pin5_m,
9442 +               GPIO_u0dsrn_cfg_v       = GPIO_input_v,
9443 +       GPIO_u0rtsn_b   = GPIO_pin6_b,                  // UART 0 req. to send.
9444 +       GPIO_u0rtsn_m   = GPIO_pin6_m,
9445 +               GPIO_u0rtsn_cfg_v       = GPIO_output_v,
9446 +       GPIO_u0ctsn_b   = GPIO_pin7_b,                  // UART 0 clear to send.
9447 +       GPIO_u0ctsn_m   = GPIO_pin7_m,
9448 +               GPIO_u0ctsn_cfg_v       = GPIO_input_v,
9449 +
9450 +       GPIO_u1sout_b           = GPIO_pin8_b,          // UART 1 serial out.
9451 +       GPIO_u1sout_m           = GPIO_pin8_m,
9452 +               GPIO_u1sout_cfg_v       = GPIO_output_v,
9453 +       GPIO_u1sinp_b           = GPIO_pin9_b,          // UART 1 serial in.
9454 +       GPIO_u1sinp_m           = GPIO_pin9_m,
9455 +               GPIO_u1sinp_cfg_v       = GPIO_input_v,
9456 +       GPIO_u1dtrn_b           = GPIO_pin10_b,         // UART 1 data term rdy.
9457 +       GPIO_u1dtrn_m           = GPIO_pin10_m,
9458 +               GPIO_u1dtrn_cfg_v       = GPIO_output_v,
9459 +       GPIO_u1dsrn_b           = GPIO_pin11_b,         // UART 1 data set rdy.
9460 +       GPIO_u1dsrn_m           = GPIO_pin11_m,
9461 +               GPIO_u1dsrn_cfg_v       = GPIO_input_v,
9462 +       GPIO_u1rtsn_b           = GPIO_pin12_b,         // UART 1 req. to send.
9463 +       GPIO_u1rtsn_m           = GPIO_pin12_m,
9464 +               GPIO_u1rtsn_cfg_v       = GPIO_output_v,
9465 +       GPIO_u1ctsn_b           = GPIO_pin13_b,         // UART 1 clear to send.
9466 +       GPIO_u1ctsn_m           = GPIO_pin13_m,
9467 +               GPIO_u1ctsn_cfg_v       = GPIO_input_v,
9468 +
9469 +       GPIO_dmareqn0_b         = GPIO_pin14_b,         // Ext. DMA 0 request
9470 +       GPIO_dmareqn0_m         = GPIO_pin14_m,
9471 +               GPIO_dmareqn0_cfg_v     = GPIO_input_v,
9472 +
9473 +       GPIO_dmareqn1_b         = GPIO_pin15_b,         // Ext. DMA 1 request
9474 +       GPIO_dmareqn1_m         = GPIO_pin15_m,
9475 +               GPIO_dmareqn1_cfg_v     = GPIO_input_v,
9476 +
9477 +       GPIO_dmadonen0_b        = GPIO_pin16_b,         // Ext. DMA 0 done
9478 +       GPIO_dmadonen0_m        = GPIO_pin16_m,
9479 +               GPIO_dmadonen0_cfg_v    = GPIO_input_v,
9480 +
9481 +       GPIO_dmadonen1_b        = GPIO_pin17_b,         // Ext. DMA 1 done
9482 +       GPIO_dmadonen1_m        = GPIO_pin17_m,
9483 +               GPIO_dmadonen1_cfg_v    = GPIO_input_v,
9484 +
9485 +       GPIO_dmafinn0_b         = GPIO_pin18_b,         // Ext. DMA 0 finished
9486 +       GPIO_dmafinn0_m         = GPIO_pin18_m,
9487 +               GPIO_dmafinn0_cfg_v     = GPIO_output_v,
9488 +
9489 +       GPIO_dmafinn1_b         = GPIO_pin19_b,         // Ext. DMA 1 finished
9490 +       GPIO_dmafinn1_m         = GPIO_pin19_m,
9491 +               GPIO_dmafinn1_cfg_v     = GPIO_output_v,
9492 +
9493 +       GPIO_maddr22_b          = GPIO_pin20_b,         // M&P bus bit 22.
9494 +       GPIO_maddr22_m          = GPIO_pin20_m,
9495 +               GPIO_maddr22_cfg_v      = GPIO_output_v,
9496 +
9497 +       GPIO_maddr23_b          = GPIO_pin21_b,         // M&P bus bit 23.
9498 +       GPIO_maddr23_m          = GPIO_pin21_m,
9499 +               GPIO_maddr23_cfg_v      = GPIO_output_v,
9500 +
9501 +       GPIO_maddr24_b          = GPIO_pin22_b,         // M&P bus bit 24.
9502 +       GPIO_maddr24_m          = GPIO_pin22_m,
9503 +               GPIO_maddr24_cfg_v      = GPIO_output_v,
9504 +
9505 +       GPIO_maddr25_b          = GPIO_pin23_b,         // M&P bus bit 25.
9506 +       GPIO_maddr25_m          = GPIO_pin23_m,
9507 +               GPIO_maddr25_cfg_v      = GPIO_output_v,
9508 +
9509 +       GPIO_afspare6_b         = GPIO_pin24_b,         // reserved.
9510 +       GPIO_afspare6_m         = GPIO_pin24_m,
9511 +               GPIO_afspare6_cfg_v     = GPIO_input_v,
9512 +       GPIO_afspare5_b         = GPIO_pin25_b,         // reserved.
9513 +       GPIO_afspare5_m         = GPIO_pin25_m,
9514 +               GPIO_afspare5_cfg_v     = GPIO_input_v,
9515 +       GPIO_afspare4_b         = GPIO_pin26_b,         // reserved.
9516 +       GPIO_afspare4_m         = GPIO_pin26_m,
9517 +               GPIO_afspare4_cfg_v     = GPIO_input_v,
9518 +       GPIO_afspare3_b         = GPIO_pin27_b,         // reserved.
9519 +       GPIO_afspare3_m         = GPIO_pin27_m,
9520 +               GPIO_afspare3_cfg_v     = GPIO_input_v,
9521 +       GPIO_afspare2_b         = GPIO_pin28_b,         // reserved.
9522 +       GPIO_afspare2_m         = GPIO_pin28_m,
9523 +               GPIO_afspare2_cfg_v     = GPIO_input_v,
9524 +       GPIO_afspare1_b         = GPIO_pin29_b,         // reserved.
9525 +       GPIO_afspare1_m         = GPIO_pin29_m,
9526 +               GPIO_afspare1_cfg_v     = GPIO_input_v,
9527 +
9528 +       GPIO_pcimuintn_b        = GPIO_pin30_b,         // PCI messaging int.
9529 +       GPIO_pcimuintn_m        = GPIO_pin30_m,
9530 +               GPIO_pcimuintn_cfg_v    = GPIO_output_v,
9531 +
9532 +       GPIO_rngclk_b           = GPIO_pin31_b,         // RNG external clock
9533 +       GPIO_rngclk_m           = GPIO_pin31_m,
9534 +               GPIO_rncclk_cfg_v       = GPIO_input_v,
9535 +} GPIO_DEFS_t;
9536 +
9537 +#endif //__IDT_RC32438_GPIO_H__
9538 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h
9539 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438.h  1970-01-01 01:00:00.000000000 +0100
9540 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h     2006-06-18 12:44:28.000000000 +0200
9541 @@ -0,0 +1,152 @@
9542 +/**************************************************************************
9543 + *
9544 + *  BRIEF MODULE DESCRIPTION
9545 + *   Definitions for IDT RC32438 CPU.
9546 + *
9547 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9548 + *
9549 + *  This program is free software; you can redistribute  it and/or modify it
9550 + *  under  the terms of  the GNU General  Public License as published by the
9551 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9552 + *  option) any later version.
9553 + *
9554 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9555 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9556 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9557 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9558 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9559 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9560 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9561 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9562 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9563 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9564 + *
9565 + *  You should have received a copy of the  GNU General Public License along
9566 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9567 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9568 + *
9569 + *
9570 + **************************************************************************
9571 + * May 2004 P. Sadik.
9572 + *
9573 + * Initial Release
9574 + *
9575 + *
9576 + *
9577 + **************************************************************************
9578 + */
9579 +
9580 +#ifndef __IDT_RC32438_H__
9581 +#define  __IDT_RC32438_H__
9582 +#include <linux/autoconf.h>
9583 +#include <linux/delay.h>
9584 +#include <asm/io.h>
9585 +#include <asm/idt-boards/rc32438/rc32438_timer.h>
9586 +
9587 +#define RC32438_REG_BASE   0x18000000
9588 +
9589 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
9590 +#define idttimer     ((volatile TIM_t)  TIM0_VirtualAddress)
9591 +#define idt_gpio         ((volatile GPIO_t) GPIO0_VirtualAddress)
9592 +
9593 +#define IDT_CLOCK_MULT 2
9594 +#define MIPS_CPU_TIMER_IRQ 7
9595 +/* Interrupt Controller */
9596 +#define IC_GROUP0_PEND     (RC32438_REG_BASE + 0x38000)
9597 +#define IC_GROUP0_MASK     (RC32438_REG_BASE + 0x38008)
9598 +#define IC_GROUP_OFFSET    0x0C
9599 +#define RTC_BASE           0xAC0801FF0
9600 +
9601 +#define NUM_INTR_GROUPS    5
9602 +/* 16550 UARTs */
9603 +
9604 +#define GROUP0_IRQ_BASE 8              /* GRP2 IRQ numbers start here */
9605 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
9606 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
9607 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
9608 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
9609 +
9610 +#ifdef __MIPSEB__
9611 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
9612 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
9613 +#else
9614 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
9615 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
9616 +#endif
9617 +
9618 +#define RC32438_UART0_IRQ  GROUP3_IRQ_BASE + 0
9619 +#define RC32438_UART1_IRQ  GROUP3_IRQ_BASE + 3
9620 +
9621 +#define RC32438_NR_IRQS  (GROUP4_IRQ_BASE + 32)
9622 +
9623 +
9624 +
9625 +/* cpu pipeline flush */
9626 +static inline void rc32438_sync(void)
9627 +{
9628 +        __asm__ volatile ("sync");
9629 +}
9630 +
9631 +static inline void rc32438_sync_udelay(int us)
9632 +{
9633 +        __asm__ volatile ("sync");
9634 +        udelay(us);
9635 +}
9636 +
9637 +static inline void rc32438_sync_delay(int ms)
9638 +{
9639 +        __asm__ volatile ("sync");
9640 +        mdelay(ms);
9641 +}
9642 +
9643 +/*
9644 + * Macros to access internal RC32438 registers. No byte
9645 + * swapping should be done when accessing the internal
9646 + * registers.
9647 + */
9648 +
9649 +#define rc32438_readb __raw_readb
9650 +#define rc32438_readw __raw_readw
9651 +#define rc32438_readl __raw_readl
9652 +
9653 +#define rc32438_writeb __raw_writeb
9654 +#define rc32438_writew __raw_writew
9655 +#define rc32438_writel __raw_writel
9656 +
9657 +/*
9658 + * C access to CLZ and CLO instructions
9659 + * (count leading zeroes/ones).
9660 + */
9661 +static inline int rc32438_clz(unsigned long val)
9662 +{
9663 +       int ret;
9664 +        __asm__ volatile (
9665 +               ".set\tnoreorder\n\t"
9666 +               ".set\tnoat\n\t"
9667 +               ".set\tmips32\n\t"
9668 +               "clz\t%0,%1\n\t"
9669 +                ".set\tmips0\n\t"
9670 +                ".set\tat\n\t"
9671 +                ".set\treorder"
9672 +                : "=r" (ret)
9673 +               : "r" (val));
9674 +
9675 +       return ret;
9676 +}
9677 +static inline int rc32438_clo(unsigned long val)
9678 +{
9679 +       int ret;
9680 +        __asm__ volatile (
9681 +               ".set\tnoreorder\n\t"
9682 +               ".set\tnoat\n\t"
9683 +               ".set\tmips32\n\t"
9684 +               "clo\t%0,%1\n\t"
9685 +                ".set\tmips0\n\t"
9686 +                ".set\tat\n\t"
9687 +                ".set\treorder"
9688 +                : "=r" (ret)
9689 +               : "r" (val));
9690 +
9691 +       return ret;
9692 +}
9693 +#endif //__IDT_RC32438_H__
9694 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
9695 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci.h      1970-01-01 01:00:00.000000000 +0100
9696 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 2006-06-18 12:44:28.000000000 +0200
9697 @@ -0,0 +1,510 @@
9698 +/**************************************************************************
9699 + *
9700 + *  BRIEF MODULE DESCRIPTION
9701 + *   Definitions for IDT RC32438 PCI.
9702 + *
9703 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9704 + *
9705 + *  This program is free software; you can redistribute  it and/or modify it
9706 + *  under  the terms of  the GNU General  Public License as published by the
9707 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9708 + *  option) any later version.
9709 + *
9710 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9711 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9712 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9713 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9714 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9715 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9716 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9717 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9718 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9719 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9720 + *
9721 + *  You should have received a copy of the  GNU General Public License along
9722 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9723 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9724 + *
9725 + *
9726 + **************************************************************************
9727 + * May 2004 P. Sadik
9728 + *
9729 + * Initial Release
9730 + *
9731 + *
9732 + *
9733 + **************************************************************************
9734 + */
9735 +
9736 +enum
9737 +{
9738 +       PCI0_PhysicalAddress    = 0x18080000,
9739 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
9740 +
9741 +       PCI0_VirtualAddress     = 0xb8080000,
9742 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
9743 +} ;
9744 +
9745 +enum
9746 +{
9747 +       PCI_LbaCount    = 4,            // Local base addresses.
9748 +} ;
9749 +
9750 +typedef struct
9751 +{
9752 +       u32     a ;             // Address.
9753 +       u32     c ;             // Control.
9754 +       u32     m ;             // mapping.
9755 +} PCI_Map_s ;
9756 +
9757 +typedef struct
9758 +{
9759 +       u32             pcic ;
9760 +       u32             pcis ;
9761 +       u32             pcism ;
9762 +       u32             pcicfga ;
9763 +       u32             pcicfgd ;
9764 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
9765 +       u32             pcidac ;
9766 +       u32             pcidas ;
9767 +       u32             pcidasm ;
9768 +       u32             pcidad ;
9769 +       u32             pcidma8c ;
9770 +       u32             pcidma9c ;
9771 +       u32             pcitc ;
9772 +} volatile *PCI_t ;
9773 +
9774 +// PCI messaging unit.
9775 +enum
9776 +{
9777 +       PCIM_Count      = 2,
9778 +} ;
9779 +typedef struct
9780 +{
9781 +       u32             pciim [PCIM_Count] ;
9782 +       u32             pciom [PCIM_Count] ;
9783 +       u32             pciid ;
9784 +       u32             pciiic ;
9785 +       u32             pciiim ;
9786 +       u32             pciiod ;
9787 +       u32             pciioic ;
9788 +       u32             pciioim ;
9789 +} volatile *PCIM_t ;
9790 +
9791 +/*******************************************************************************
9792 + *
9793 + * PCI Control Register
9794 + *
9795 + ******************************************************************************/
9796 +enum
9797 +{
9798 +       PCIC_en_b       = 0,
9799 +       PCIC_en_m       = 0x00000001,
9800 +       PCIC_tnr_b      = 1,
9801 +       PCIC_tnr_m      = 0x00000002,
9802 +       PCIC_sce_b      = 2,
9803 +       PCIC_sce_m      = 0x00000004,
9804 +       PCIC_ien_b      = 3,
9805 +       PCIC_ien_m      = 0x00000008,
9806 +       PCIC_aaa_b      = 4,
9807 +       PCIC_aaa_m      = 0x00000010,
9808 +       PCIC_eap_b      = 5,
9809 +       PCIC_eap_m      = 0x00000020,
9810 +       PCIC_pcim_b     = 6,
9811 +       PCIC_pcim_m     = 0x000001c0,
9812 +               PCIC_pcim_disabled_v    = 0,
9813 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
9814 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
9815 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
9816 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
9817 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
9818 +               PCIC_pcim_reserved6_v   = 6,
9819 +               PCIC_pcim_reserved7_v   = 7,
9820 +       PCIC_igm_b      = 9,
9821 +       PCIC_igm_m      = 0x00000200,
9822 +} ;
9823 +
9824 +/*******************************************************************************
9825 + *
9826 + * PCI Status Register
9827 + *
9828 + ******************************************************************************/
9829 +enum {
9830 +       PCIS_eed_b      = 0,
9831 +       PCIS_eed_m      = 0x00000001,
9832 +       PCIS_wr_b       = 1,
9833 +       PCIS_wr_m       = 0x00000002,
9834 +       PCIS_nmi_b      = 2,
9835 +       PCIS_nmi_m      = 0x00000004,
9836 +       PCIS_ii_b       = 3,
9837 +       PCIS_ii_m       = 0x00000008,
9838 +       PCIS_cwe_b      = 4,
9839 +       PCIS_cwe_m      = 0x00000010,
9840 +       PCIS_cre_b      = 5,
9841 +       PCIS_cre_m      = 0x00000020,
9842 +       PCIS_mdpe_b     = 6,
9843 +       PCIS_mdpe_m     = 0x00000040,
9844 +       PCIS_sta_b      = 7,
9845 +       PCIS_sta_m      = 0x00000080,
9846 +       PCIS_rta_b      = 8,
9847 +       PCIS_rta_m      = 0x00000100,
9848 +       PCIS_rma_b      = 9,
9849 +       PCIS_rma_m      = 0x00000200,
9850 +       PCIS_sse_b      = 10,
9851 +       PCIS_sse_m      = 0x00000400,
9852 +       PCIS_ose_b      = 11,
9853 +       PCIS_ose_m      = 0x00000800,
9854 +       PCIS_pe_b       = 12,
9855 +       PCIS_pe_m       = 0x00001000,
9856 +       PCIS_tae_b      = 13,
9857 +       PCIS_tae_m      = 0x00002000,
9858 +       PCIS_rle_b      = 14,
9859 +       PCIS_rle_m      = 0x00004000,
9860 +       PCIS_bme_b      = 15,
9861 +       PCIS_bme_m      = 0x00008000,
9862 +       PCIS_prd_b      = 16,
9863 +       PCIS_prd_m      = 0x00010000,
9864 +       PCIS_rip_b      = 17,
9865 +       PCIS_rip_m      = 0x00020000,
9866 +} ;
9867 +
9868 +/*******************************************************************************
9869 + *
9870 + * PCI Status Mask Register
9871 + *
9872 + ******************************************************************************/
9873 +enum {
9874 +       PCISM_eed_b             = 0,
9875 +       PCISM_eed_m             = 0x00000001,
9876 +       PCISM_wr_b              = 1,
9877 +       PCISM_wr_m              = 0x00000002,
9878 +       PCISM_nmi_b             = 2,
9879 +       PCISM_nmi_m             = 0x00000004,
9880 +       PCISM_ii_b              = 3,
9881 +       PCISM_ii_m              = 0x00000008,
9882 +       PCISM_cwe_b             = 4,
9883 +       PCISM_cwe_m             = 0x00000010,
9884 +       PCISM_cre_b             = 5,
9885 +       PCISM_cre_m             = 0x00000020,
9886 +       PCISM_mdpe_b            = 6,
9887 +       PCISM_mdpe_m            = 0x00000040,
9888 +       PCISM_sta_b             = 7,
9889 +       PCISM_sta_m             = 0x00000080,
9890 +       PCISM_rta_b             = 8,
9891 +       PCISM_rta_m             = 0x00000100,
9892 +       PCISM_rma_b             = 9,
9893 +       PCISM_rma_m             = 0x00000200,
9894 +       PCISM_sse_b             = 10,
9895 +       PCISM_sse_m             = 0x00000400,
9896 +       PCISM_ose_b             = 11,
9897 +       PCISM_ose_m             = 0x00000800,
9898 +       PCISM_pe_b              = 12,
9899 +       PCISM_pe_m              = 0x00001000,
9900 +       PCISM_tae_b             = 13,
9901 +       PCISM_tae_m             = 0x00002000,
9902 +       PCISM_rle_b             = 14,
9903 +       PCISM_rle_m             = 0x00004000,
9904 +       PCISM_bme_b             = 15,
9905 +       PCISM_bme_m             = 0x00008000,
9906 +       PCISM_prd_b             = 16,
9907 +       PCISM_prd_m             = 0x00010000,
9908 +       PCISM_rip_b             = 17,
9909 +       PCISM_rip_m             = 0x00020000,
9910 +} ;
9911 +
9912 +/*******************************************************************************
9913 + *
9914 + * PCI Configuration Address Register
9915 + *
9916 + ******************************************************************************/
9917 +enum {
9918 +       PCICFGA_reg_b           = 2,
9919 +       PCICFGA_reg_m           = 0x000000fc,
9920 +               PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
9921 +               PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
9922 +               PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
9923 +               PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
9924 +               PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
9925 +               PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
9926 +               PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
9927 +               PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
9928 +               PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
9929 +               PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
9930 +               PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
9931 +               PCICFGA_reg_pba0m_v     = 0x48>>2,
9932 +               PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
9933 +               PCICFGA_reg_pba1m_v     = 0x50>>2,
9934 +               PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
9935 +               PCICFGA_reg_pba2m_v     = 0x58>>2,
9936 +               PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
9937 +               PCICFGA_reg_pba3m_v     = 0x60>>2,
9938 +               PCICFGA_reg_pmgt_v      = 0x64>>2,
9939 +       PCICFGA_func_b          = 8,
9940 +       PCICFGA_func_m          = 0x00000700,
9941 +       PCICFGA_dev_b           = 11,
9942 +       PCICFGA_dev_m           = 0x0000f800,
9943 +               PCICFGA_dev_internal_v  = 0,
9944 +       PCICFGA_bus_b           = 16,
9945 +       PCICFGA_bus_m           = 0x00ff0000,
9946 +               PCICFGA_bus_type0_v     = 0,    //local bus
9947 +       PCICFGA_en_b            = 31,           // read only
9948 +       PCICFGA_en_m            = 0x80000000,
9949 +} ;
9950 +
9951 +enum {
9952 +       PCFGID_vendor_b         = 0,
9953 +       PCFGID_vendor_m         = 0x0000ffff,
9954 +               PCFGID_vendor_IDT_v             = 0x111d,
9955 +       PCFGID_device_b         = 16,
9956 +       PCFGID_device_m         = 0xffff0000,
9957 +               PCFGID_device_Acaciade_v        = 0x0207,
9958 +
9959 +       PCFG04_command_ioena_b          = 1,
9960 +       PCFG04_command_ioena_m          = 0x00000001,
9961 +       PCFG04_command_memena_b         = 2,
9962 +       PCFG04_command_memena_m         = 0x00000002,
9963 +       PCFG04_command_bmena_b          = 3,
9964 +       PCFG04_command_bmena_m          = 0x00000004,
9965 +       PCFG04_command_mwinv_b          = 5,
9966 +       PCFG04_command_mwinv_m          = 0x00000010,
9967 +       PCFG04_command_parena_b         = 7,
9968 +       PCFG04_command_parena_m         = 0x00000040,
9969 +       PCFG04_command_serrena_b        = 9,
9970 +       PCFG04_command_serrena_m        = 0x00000100,
9971 +       PCFG04_command_fastbbena_b      = 10,
9972 +       PCFG04_command_fastbbena_m      = 0x00000200,
9973 +       PCFG04_status_b                 = 16,
9974 +       PCFG04_status_m                 = 0xffff0000,
9975 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
9976 +       PCFG04_status_66MHz_m           = 0x00200000,
9977 +       PCFG04_status_fbb_b             = 23,
9978 +       PCFG04_status_fbb_m             = 0x00800000,
9979 +       PCFG04_status_mdpe_b            = 24,
9980 +       PCFG04_status_mdpe_m            = 0x01000000,
9981 +       PCFG04_status_dst_b             = 25,
9982 +       PCFG04_status_dst_m             = 0x06000000,
9983 +       PCFG04_status_sta_b             = 27,
9984 +       PCFG04_status_sta_m             = 0x08000000,
9985 +       PCFG04_status_rta_b             = 28,
9986 +       PCFG04_status_rta_m             = 0x10000000,
9987 +       PCFG04_status_rma_b             = 29,
9988 +       PCFG04_status_rma_m             = 0x20000000,
9989 +       PCFG04_status_sse_b             = 30,
9990 +       PCFG04_status_sse_m             = 0x40000000,
9991 +       PCFG04_status_pe_b              = 31,
9992 +       PCFG04_status_pe_m              = 0x40000000,
9993 +
9994 +       PCFG08_revId_b                  = 0,
9995 +       PCFG08_revId_m                  = 0x000000ff,
9996 +       PCFG08_classCode_b              = 0,
9997 +       PCFG08_classCode_m              = 0xffffff00,
9998 +               PCFG08_classCode_bridge_v       = 06,
9999 +               PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
10000 +       PCFG0C_cacheline_b              = 0,
10001 +       PCFG0C_cacheline_m              = 0x000000ff,
10002 +       PCFG0C_masterLatency_b          = 8,
10003 +       PCFG0C_masterLatency_m          = 0x0000ff00,
10004 +       PCFG0C_headerType_b             = 16,
10005 +       PCFG0C_headerType_m             = 0x00ff0000,
10006 +       PCFG0C_bist_b                   = 24,
10007 +       PCFG0C_bist_m                   = 0xff000000,
10008 +
10009 +       PCIPBA_msi_b                    = 0,
10010 +       PCIPBA_msi_m                    = 0x00000001,
10011 +       PCIPBA_p_b                      = 3,
10012 +       PCIPBA_p_m                      = 0x00000004,
10013 +       PCIPBA_baddr_b                  = 8,
10014 +       PCIPBA_baddr_m                  = 0xffffff00,
10015 +
10016 +       PCFGSS_vendorId_b               = 0,
10017 +       PCFGSS_vendorId_m               = 0x0000ffff,
10018 +       PCFGSS_id_b                     = 16,
10019 +       PCFGSS_id_m                     = 0xffff0000,
10020 +
10021 +       PCFG3C_interruptLine_b          = 0,
10022 +       PCFG3C_interruptLine_m          = 0x000000ff,
10023 +       PCFG3C_interruptPin_b           = 8,
10024 +       PCFG3C_interruptPin_m           = 0x0000ff00,
10025 +       PCFG3C_minGrant_b               = 16,
10026 +       PCFG3C_minGrant_m               = 0x00ff0000,
10027 +       PCFG3C_maxLat_b                 = 24,
10028 +       PCFG3C_maxLat_m                 = 0xff000000,
10029 +
10030 +       PCIPBAC_msi_b                   = 0,
10031 +       PCIPBAC_msi_m                   = 0x00000001,
10032 +       PCIPBAC_p_b                     = 1,
10033 +       PCIPBAC_p_m                     = 0x00000002,
10034 +       PCIPBAC_size_b                  = 2,
10035 +       PCIPBAC_size_m                  = 0x0000007c,
10036 +       PCIPBAC_sb_b                    = 7,
10037 +       PCIPBAC_sb_m                    = 0x00000080,
10038 +       PCIPBAC_pp_b                    = 8,
10039 +       PCIPBAC_pp_m                    = 0x00000100,
10040 +       PCIPBAC_mr_b                    = 9,
10041 +       PCIPBAC_mr_m                    = 0x00000600,
10042 +               PCIPBAC_mr_read_v       =0,     //no prefetching
10043 +               PCIPBAC_mr_readLine_v   =1,
10044 +               PCIPBAC_mr_readMult_v   =2,
10045 +       PCIPBAC_mrl_b                   = 11,
10046 +       PCIPBAC_mrl_m                   = 0x00000800,
10047 +       PCIPBAC_mrm_b                   = 12,
10048 +       PCIPBAC_mrm_m                   = 0x00001000,
10049 +       PCIPBAC_trp_b                   = 13,
10050 +       PCIPBAC_trp_m                   = 0x00002000,
10051 +
10052 +       PCFG40_trdyTimeout_b            = 0,
10053 +       PCFG40_trdyTimeout_m            = 0x000000ff,
10054 +       PCFG40_retryLim_b               = 8,
10055 +       PCFG40_retryLim_m               = 0x0000ff00,
10056 +};
10057 +
10058 +/*******************************************************************************
10059 + *
10060 + * PCI Local Base Address [0|1|2|3] Register
10061 + *
10062 + ******************************************************************************/
10063 +enum {
10064 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
10065 +       PCILBA_baddr_m          = 0xffffff00,
10066 +} ;
10067 +/*******************************************************************************
10068 + *
10069 + * PCI Local Base Address Control Register
10070 + *
10071 + ******************************************************************************/
10072 +enum {
10073 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
10074 +       PCILBAC_msi_m           = 0x00000001,
10075 +               PCILBAC_msi_mem_v       = 0,
10076 +               PCILBAC_msi_io_v        = 1,
10077 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
10078 +       PCILBAC_size_m          = 0x0000007c,
10079 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
10080 +       PCILBAC_sb_m            = 0x00000080,
10081 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
10082 +       PCILBAC_rt_m            = 0x00000100,
10083 +               PCILBAC_rt_noprefetch_v = 0, // mem read
10084 +               PCILBAC_rt_prefetch_v   = 1, // mem readline
10085 +} ;
10086 +
10087 +/*******************************************************************************
10088 + *
10089 + * PCI Local Base Address [0|1|2|3] Mapping Register
10090 + *
10091 + ******************************************************************************/
10092 +enum {
10093 +       PCILBAM_maddr_b         = 8,
10094 +       PCILBAM_maddr_m         = 0xffffff00,
10095 +} ;
10096 +
10097 +/*******************************************************************************
10098 + *
10099 + * PCI Decoupled Access Control Register
10100 + *
10101 + ******************************************************************************/
10102 +enum {
10103 +       PCIDAC_den_b            = 0,
10104 +       PCIDAC_den_m            = 0x00000001,
10105 +} ;
10106 +
10107 +/*******************************************************************************
10108 + *
10109 + * PCI Decoupled Access Status Register
10110 + *
10111 + ******************************************************************************/
10112 +enum {
10113 +       PCIDAS_d_b      = 0,
10114 +       PCIDAS_d_m      = 0x00000001,
10115 +       PCIDAS_b_b      = 1,
10116 +       PCIDAS_b_m      = 0x00000002,
10117 +       PCIDAS_e_b      = 2,
10118 +       PCIDAS_e_m      = 0x00000004,
10119 +       PCIDAS_ofe_b    = 3,
10120 +       PCIDAS_ofe_m    = 0x00000008,
10121 +       PCIDAS_off_b    = 4,
10122 +       PCIDAS_off_m    = 0x00000010,
10123 +       PCIDAS_ife_b    = 5,
10124 +       PCIDAS_ife_m    = 0x00000020,
10125 +       PCIDAS_iff_b    = 6,
10126 +       PCIDAS_iff_m    = 0x00000040,
10127 +} ;
10128 +
10129 +/*******************************************************************************
10130 + *
10131 + * PCI DMA Channel 8 Configuration Register
10132 + *
10133 + ******************************************************************************/
10134 +enum
10135 +{
10136 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
10137 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
10138 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
10139 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
10140 +} ;
10141 +
10142 +/*******************************************************************************
10143 + *
10144 + * PCI DMA Channel 9 Configuration Register
10145 + *
10146 + ******************************************************************************/
10147 +enum
10148 +{
10149 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
10150 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
10151 +} ;
10152 +
10153 +/*******************************************************************************
10154 + *
10155 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
10156 + *
10157 + ******************************************************************************/
10158 +enum {
10159 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
10160 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
10161 +               // These are for reads (DMA channel 8)
10162 +               PCIDMAD_devcmd_mr_v     = 0,    //memory read
10163 +               PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
10164 +               PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
10165 +               PCIDMAD_devcmd_ior_v    = 3,    //I/O read
10166 +               // These are for writes (DMA channel 9)
10167 +               PCIDMAD_devcmd_mw_v     = 0,    //memory write
10168 +               PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
10169 +               PCIDMAD_devcmd_iow_v    = 3,    //I/O write
10170 +
10171 +       // Swap byte field applies to both DMA channel 8 and 9
10172 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
10173 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
10174 +} ;
10175 +
10176 +
10177 +/*******************************************************************************
10178 + *
10179 + * PCI Target Control Register
10180 + *
10181 + ******************************************************************************/
10182 +enum
10183 +{
10184 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
10185 +       PCITC_rtimer_m          = 0x000000ff,
10186 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
10187 +       PCITC_dtimer_m          = 0x0000ff00,
10188 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
10189 +       PCITC_rdr_m             = 0x00040000,
10190 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
10191 +       PCITC_ddt_m             = 0x00080000,
10192 +} ;
10193 +/*******************************************************************************
10194 + *
10195 + * PCI messaging unit [applies to both inbound and outbound registers ]
10196 + *
10197 + ******************************************************************************/
10198 +enum
10199 +{
10200 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10201 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
10202 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10203 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
10204 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10205 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
10206 +};
10207 +
10208 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
10209 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h    1970-01-01 01:00:00.000000000 +0100
10210 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h       2006-06-18 12:44:28.000000000 +0200
10211 @@ -0,0 +1,190 @@
10212 +/**************************************************************************
10213 + *
10214 + *  BRIEF MODULE DESCRIPTION
10215 + *   Definitions for IDT RC32438 PCI setup.
10216 + *
10217 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
10218 + *
10219 + *  This program is free software; you can redistribute  it and/or modify it
10220 + *  under  the terms of  the GNU General  Public License as published by the
10221 + *  Free Software Foundation;  either version 2 of the  License, or (at your
10222 + *  option) any later version.
10223 + *
10224 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
10225 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
10226 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
10227 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
10228 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10229 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
10230 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10231 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
10232 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10233 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10234 + *
10235 + *  You should have received a copy of the  GNU General Public License along
10236 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
10237 + *  675 Mass Ave, Cambridge, MA 02139, USA.
10238 + *
10239 + *
10240 + **************************************************************************
10241 + * May 2004 P. Sadik
10242 + *
10243 + * Initial Release
10244 + *
10245 + *
10246 + *
10247 + **************************************************************************
10248 + */
10249 +
10250 +#define PCI_MSG_VirtualAddress      0xB8088010
10251 +#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
10252 +#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
10253 +
10254 +#define PCIM_SHFT              0x6
10255 +#define PCIM_BIT_LEN           0x7
10256 +#define PCIM_H_EA              0x3
10257 +#define PCIM_H_IA_FIX          0x4
10258 +#define PCIM_H_IA_RR           0x5
10259 +
10260 +#define PCI_ADDR_START         0x50000000
10261 +
10262 +#define CPUTOPCI_MEM_WIN       0x02000000
10263 +#define CPUTOPCI_IO_WIN                0x00100000
10264 +#define PCILBA_SIZE_SHFT       2
10265 +#define PCILBA_SIZE_MASK       0x1F
10266 +#define SIZE_256MB             0x1C
10267 +#define SIZE_128MB             0x1B
10268 +#define SIZE_64MB               0x1A
10269 +#define SIZE_32MB              0x19
10270 +#define SIZE_16MB               0x18
10271 +#define SIZE_4MB               0x16
10272 +#define SIZE_2MB               0x15
10273 +#define SIZE_1MB               0x14
10274 +#define ACACIA_CONFIG0_ADDR    0x80000000
10275 +#define ACACIA_CONFIG1_ADDR    0x80000004
10276 +#define ACACIA_CONFIG2_ADDR    0x80000008
10277 +#define ACACIA_CONFIG3_ADDR    0x8000000C
10278 +#define ACACIA_CONFIG4_ADDR    0x80000010
10279 +#define ACACIA_CONFIG5_ADDR    0x80000014
10280 +#define ACACIA_CONFIG6_ADDR    0x80000018
10281 +#define ACACIA_CONFIG7_ADDR    0x8000001C
10282 +#define ACACIA_CONFIG8_ADDR    0x80000020
10283 +#define ACACIA_CONFIG9_ADDR    0x80000024
10284 +#define ACACIA_CONFIG10_ADDR   0x80000028
10285 +#define ACACIA_CONFIG11_ADDR   0x8000002C
10286 +#define ACACIA_CONFIG12_ADDR   0x80000030
10287 +#define ACACIA_CONFIG13_ADDR   0x80000034
10288 +#define ACACIA_CONFIG14_ADDR   0x80000038
10289 +#define ACACIA_CONFIG15_ADDR   0x8000003C
10290 +#define ACACIA_CONFIG16_ADDR   0x80000040
10291 +#define ACACIA_CONFIG17_ADDR   0x80000044
10292 +#define ACACIA_CONFIG18_ADDR   0x80000048
10293 +#define ACACIA_CONFIG19_ADDR   0x8000004C
10294 +#define ACACIA_CONFIG20_ADDR   0x80000050
10295 +#define ACACIA_CONFIG21_ADDR   0x80000054
10296 +#define ACACIA_CONFIG22_ADDR   0x80000058
10297 +#define ACACIA_CONFIG23_ADDR   0x8000005C
10298 +#define ACACIA_CONFIG24_ADDR   0x80000060
10299 +#define ACACIA_CONFIG25_ADDR   0x80000064
10300 +#define ACACIA_CMD             (PCFG04_command_ioena_m | \
10301 +                                PCFG04_command_memena_m | \
10302 +                                PCFG04_command_bmena_m | \
10303 +                                PCFG04_command_mwinv_m | \
10304 +                                PCFG04_command_parena_m | \
10305 +                                PCFG04_command_serrena_m )
10306 +
10307 +#define ACACIA_STAT            (PCFG04_status_mdpe_m | \
10308 +                                PCFG04_status_sta_m  | \
10309 +                                PCFG04_status_rta_m  | \
10310 +                                PCFG04_status_rma_m  | \
10311 +                                PCFG04_status_sse_m  | \
10312 +                                PCFG04_status_pe_m)
10313 +
10314 +#define ACACIA_CNFG1           ((ACACIA_STAT<<16)|ACACIA_CMD)
10315 +
10316 +#define ACACIA_REVID           0
10317 +#define ACACIA_CLASS_CODE      0
10318 +#define ACACIA_CNFG2           ((ACACIA_CLASS_CODE<<8) | \
10319 +                                 ACACIA_REVID)
10320 +
10321 +#define ACACIA_CACHE_LINE_SIZE 4
10322 +#define ACACIA_MASTER_LAT      0x3c
10323 +#define ACACIA_HEADER_TYPE     0
10324 +#define ACACIA_BIST            0
10325 +
10326 +#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
10327 +                     (ACACIA_HEADER_TYPE<<16) | \
10328 +                     (ACACIA_MASTER_LAT<<8) | \
10329 +                     ACACIA_CACHE_LINE_SIZE )
10330 +
10331 +#define ACACIA_BAR0    0x00000008 /* 128 MB Memory */
10332 +#define ACACIA_BAR1    0x18800001 /* 1 MB IO */
10333 +#define ACACIA_BAR2    0x18000001 /* 2 MB IO window for Acacia
10334 +                                       internal Registers */
10335 +#define ACACIA_BAR3    0x48000008 /* Spare 128 MB Memory */
10336 +
10337 +#define ACACIA_CNFG4   ACACIA_BAR0
10338 +#define ACACIA_CNFG5    ACACIA_BAR1
10339 +#define ACACIA_CNFG6   ACACIA_BAR2
10340 +#define ACACIA_CNFG7   ACACIA_BAR3
10341 +
10342 +#define ACACIA_SUBSYS_VENDOR_ID 0
10343 +#define ACACIA_SUBSYSTEM_ID    0
10344 +#define ACACIA_CNFG8           0
10345 +#define ACACIA_CNFG9           0
10346 +#define ACACIA_CNFG10          0
10347 +#define ACACIA_CNFG11  ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
10348 +                         ACACIA_SUBSYSTEM_ID)
10349 +#define ACACIA_INT_LINE                1
10350 +#define ACACIA_INT_PIN         1
10351 +#define ACACIA_MIN_GNT         8
10352 +#define ACACIA_MAX_LAT         0x38
10353 +#define ACACIA_CNFG12          0
10354 +#define ACACIA_CNFG13          0
10355 +#define ACACIA_CNFG14          0
10356 +#define ACACIA_CNFG15  ((ACACIA_MAX_LAT<<24) | \
10357 +                        (ACACIA_MIN_GNT<<16) | \
10358 +                        (ACACIA_INT_PIN<<8)  | \
10359 +                         ACACIA_INT_LINE)
10360 +#define        ACACIA_RETRY_LIMIT      0x80
10361 +#define ACACIA_TRDY_LIMIT      0x80
10362 +#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
10363 +                       ACACIA_TRDY_LIMIT)
10364 +#define PCI_PBAxC_R            0x0
10365 +#define PCI_PBAxC_RL           0x1
10366 +#define PCI_PBAxC_RM           0x2
10367 +#define SIZE_SHFT              2
10368 +
10369 +#define ACACIA_PBA0C   ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
10370 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
10371 +                         PCIPBAC_pp_m | \
10372 +                         (SIZE_128MB<<SIZE_SHFT) | \
10373 +                          PCIPBAC_p_m)
10374 +
10375 +#define ACACIA_CNFG17  ACACIA_PBA0C
10376 +#define ACACIA_PBA0M   0x0
10377 +#define ACACIA_CNFG18  ACACIA_PBA0M
10378 +
10379 +#define ACACIA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10380 +                         PCIPBAC_msi_m)
10381 +
10382 +#define ACACIA_CNFG19  ACACIA_PBA1C
10383 +#define ACACIA_PBA1M   0x0
10384 +#define ACACIA_CNFG20  ACACIA_PBA1M
10385 +
10386 +#define ACACIA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10387 +                         PCIPBAC_msi_m)
10388 +
10389 +#define ACACIA_CNFG21  ACACIA_PBA2C
10390 +#define ACACIA_PBA2M   0x18000000
10391 +#define ACACIA_CNFG22  ACACIA_PBA2M
10392 +#define ACACIA_PBA3C   0
10393 +#define ACACIA_CNFG23  ACACIA_PBA3C
10394 +#define ACACIA_PBA3M   0
10395 +#define ACACIA_CNFG24  ACACIA_PBA3M
10396 +
10397 +
10398 +
10399 +#define        PCITC_DTIMER_VAL        8
10400 +#define PCITC_RTIMER_VAL       0x10
10401 +
10402 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
10403 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_timer.h    1970-01-01 01:00:00.000000000 +0100
10404 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h       2006-06-18 12:44:28.000000000 +0200
10405 @@ -0,0 +1,91 @@
10406 +/**************************************************************************
10407 + *
10408 + *  BRIEF MODULE DESCRIPTION
10409 + *    Timer register definition IDT RC32438 CPU.
10410 + *
10411 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
10412 + *
10413 + *  This program is free software; you can redistribute  it and/or modify it
10414 + *  under  the terms of  the GNU General  Public License as published by the
10415 + *  Free Software Foundation;  either version 2 of the  License, or (at your
10416 + *  option) any later version.
10417 + *
10418 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
10419 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
10420 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
10421 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
10422 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10423 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
10424 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10425 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
10426 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10427 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10428 + *
10429 + *  You should have received a copy of the  GNU General Public License along
10430 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
10431 + *  675 Mass Ave, Cambridge, MA 02139, USA.
10432 + *
10433 + *
10434 + **************************************************************************
10435 + * May 2004 P. Sadik.
10436 + *
10437 + * Initial Release
10438 + *
10439 + *
10440 + *
10441 + **************************************************************************
10442 + */
10443 +
10444 +#ifndef __IDT_RC32438_TIM_H__
10445 +#define __IDT_RC32438_TIM_H__
10446 +
10447 +enum
10448 +{
10449 +       TIM0_PhysicalAddress    = 0x18028000,
10450 +       TIM_PhysicalAddress     = TIM0_PhysicalAddress,         // Default
10451 +
10452 +       TIM0_VirtualAddress     = 0xb8028000,
10453 +       TIM_VirtualAddress      = TIM0_VirtualAddress,          // Default
10454 +} ;
10455 +
10456 +enum
10457 +{
10458 +       TIM_Count = 3,
10459 +} ;
10460 +
10461 +struct TIM_CNTR_s
10462 +{
10463 +       u32 count ;
10464 +       u32 compare ;
10465 +       u32 ctc ;       //use CTC_
10466 +} ;
10467 +
10468 +typedef struct TIM_s
10469 +{
10470 +       struct TIM_CNTR_s       tim [TIM_Count] ;
10471 +       u32                     rcount ;        //use RCOUNT_
10472 +       u32                     rcompare ;      //use RCOMPARE_
10473 +       u32                     rtc ;           //use RTC_
10474 +} volatile * TIM_t ;
10475 +
10476 +enum
10477 +{
10478 +       CTC_en_b        = 0,
10479 +       CTC_en_m        = 0x00000001,
10480 +       CTC_to_b        = 1,
10481 +       CTC_to_m        = 0x00000002,
10482 +
10483 +       RCOUNT_count_b          = 0,
10484 +       RCOUNT_count_m          = 0x0000ffff,
10485 +       RCOMPARE_compare_b      = 0,
10486 +       RCOMPARE_compare_m      = 0x0000ffff,
10487 +       RTC_ce_b                = 0,
10488 +       RTC_ce_m                = 0x00000001,
10489 +       RTC_to_b                = 1,
10490 +       RTC_to_m                = 0x00000002,
10491 +       RTC_rqe_b               = 2,
10492 +       RTC_rqe_m               = 0x00000004,
10493 +
10494 +} ;
10495 +#endif //__IDT_RC32438_TIM_H__
10496 +
10497 diff -Nur linux-2.6.17/include/asm-mips/mach-generic/irq.h linux-2.6.17-owrt/include/asm-mips/mach-generic/irq.h
10498 --- linux-2.6.17/include/asm-mips/mach-generic/irq.h    2006-06-18 03:49:35.000000000 +0200
10499 +++ linux-2.6.17-owrt/include/asm-mips/mach-generic/irq.h       2006-06-18 12:44:28.000000000 +0200
10500 @@ -8,6 +8,6 @@
10501  #ifndef __ASM_MACH_GENERIC_IRQ_H
10502  #define __ASM_MACH_GENERIC_IRQ_H
10503
10504 -#define NR_IRQS        128
10505 +#define NR_IRQS        256
10506
10507  #endif /* __ASM_MACH_GENERIC_IRQ_H */
10508 diff -Nur linux-2.6.17/include/linux/kernel.h linux-2.6.17-owrt/include/linux/kernel.h
10509 --- linux-2.6.17/include/linux/kernel.h 2006-06-18 03:49:35.000000000 +0200
10510 +++ linux-2.6.17-owrt/include/linux/kernel.h    2006-06-18 12:44:28.000000000 +0200
10511 @@ -329,6 +329,7 @@
10512  };
10513
10514  /* Force a compilation error if condition is true */
10515 +extern void BUILD_BUG(void);
10516  #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
10517
10518  /* Trap pasters of __FUNCTION__ at compile-time */