target/linux/ar71xx/patches-4.1/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch

   1 From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
   2 Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
   3 From: Matthias Schiffer <mschiffer@universe-factory.net>
   4 Date: Sat, 29 Mar 2014 20:26:08 +0100
   5 Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
   6
   7 Note that the clock calculation looks very similar to the QCA955x, but the
   8 meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
   9 ---
  10  arch/mips/ath79/Kconfig                        |  6 +-
  11  arch/mips/ath79/clock.c                        | 78 ++++++++++++++++++++++++++
  12  arch/mips/ath79/common.c                       |  4 ++
  13  arch/mips/ath79/dev-common.c                   |  1 +
  14  arch/mips/ath79/dev-wmac.c                     | 20 +++++++
  15  arch/mips/ath79/early_printk.c                 |  1 +
  16  arch/mips/ath79/gpio.c                         |  4 +-
  17  arch/mips/ath79/irq.c                          |  4 ++
  18  arch/mips/ath79/setup.c                        |  8 ++-
  19  arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
  20  arch/mips/include/asm/mach-ath79/ath79.h       | 11 ++++
  21  11 files changed, 182 insertions(+), 3 deletions(-)
  22
  23 --- a/arch/mips/ath79/Kconfig
  24 +++ b/arch/mips/ath79/Kconfig
  25 @@ -1229,6 +1229,10 @@ config SOC_AR934X
  26         select PCI_AR724X if PCI
  27         def_bool n
  28
  29 +config SOC_QCA953X
  30 +       select USB_ARCH_HAS_EHCI
  31 +       def_bool n
  32 +
  33  config SOC_QCA955X
  34         select HW_HAS_PCI
  35         select PCI_AR724X if PCI
  36 @@ -1271,7 +1275,7 @@ config ATH79_DEV_USB
  37         def_bool n
  38
  39  config ATH79_DEV_WMAC
  40 -       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
  41 +       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
  42         def_bool n
  43
  44  config ATH79_NVRAM
  45 --- a/arch/mips/ath79/clock.c
  46 +++ b/arch/mips/ath79/clock.c
  47 @@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(vo
  48         iounmap(dpll_base);
  49  }
  50
  51 +static void __init qca953x_clocks_init(void)
  52 +{
  53 +       unsigned long ref_rate;
  54 +       unsigned long cpu_rate;
  55 +       unsigned long ddr_rate;
  56 +       unsigned long ahb_rate;
  57 +       u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
  58 +       u32 cpu_pll, ddr_pll;
  59 +       u32 bootstrap;
  60 +
  61 +       bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
  62 +       if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
  63 +               ref_rate = 40 * 1000 * 1000;
  64 +       else
  65 +               ref_rate = 25 * 1000 * 1000;
  66 +
  67 +       pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
  68 +       out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  69 +                 QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
  70 +       ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  71 +                 QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
  72 +       nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
  73 +              QCA953X_PLL_CPU_CONFIG_NINT_MASK;
  74 +       frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
  75 +              QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
  76 +
  77 +       cpu_pll = nint * ref_rate / ref_div;
  78 +       cpu_pll += frac * (ref_rate >> 6) / ref_div;
  79 +       cpu_pll /= (1 << out_div);
  80 +
  81 +       pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
  82 +       out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  83 +                 QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
  84 +       ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  85 +                 QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
  86 +       nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
  87 +              QCA953X_PLL_DDR_CONFIG_NINT_MASK;
  88 +       frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  89 +              QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
  90 +
  91 +       ddr_pll = nint * ref_rate / ref_div;
  92 +       ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
  93 +       ddr_pll /= (1 << out_div);
  94 +
  95 +       clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
  96 +
  97 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  98 +                 QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  99 +
 100 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
 101 +               cpu_rate = ref_rate;
 102 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
 103 +               cpu_rate = cpu_pll / (postdiv + 1);
 104 +       else
 105 +               cpu_rate = ddr_pll / (postdiv + 1);
 106 +
 107 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 108 +                 QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
 109 +
 110 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
 111 +               ddr_rate = ref_rate;
 112 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 113 +               ddr_rate = ddr_pll / (postdiv + 1);
 114 +       else
 115 +               ddr_rate = cpu_pll / (postdiv + 1);
 116 +
 117 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 118 +                 QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 119 +
 120 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
 121 +               ahb_rate = ref_rate;
 122 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 123 +               ahb_rate = ddr_pll / (postdiv + 1);
 124 +       else
 125 +               ahb_rate = cpu_pll / (postdiv + 1);
 126 +
 127 +       ath79_add_sys_clkdev("ref", ref_rate);
 128 +       ath79_add_sys_clkdev("cpu", cpu_rate);
 129 +       ath79_add_sys_clkdev("ddr", ddr_rate);
 130 +       ath79_add_sys_clkdev("ahb", ahb_rate);
 131 +
 132 +       clk_add_alias("wdt", NULL, "ref", NULL);
 133 +       clk_add_alias("uart", NULL, "ref", NULL);
 134 +}
 135 +
 136  static void __init qca955x_clocks_init(void)
 137  {
 138         unsigned long ref_rate;
 139 @@ -447,6 +532,8 @@ void __init ath79_clocks_init(void)
 140                 ar933x_clocks_init();
 141         else if (soc_is_ar934x())
 142                 ar934x_clocks_init();
 143 +       else if (soc_is_qca953x())
 144 +               qca953x_clocks_init();
 145         else if (soc_is_qca955x())
 146                 qca955x_clocks_init();
 147         else
 148 --- a/arch/mips/ath79/common.c
 149 +++ b/arch/mips/ath79/common.c
 150 @@ -73,6 +73,8 @@ void ath79_device_reset_set(u32 mask)
 151                 reg = AR933X_RESET_REG_RESET_MODULE;
 152         else if (soc_is_ar934x())
 153                 reg = AR934X_RESET_REG_RESET_MODULE;
 154 +       else if (soc_is_qca953x())
 155 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 156         else if (soc_is_qca955x())
 157                 reg = QCA955X_RESET_REG_RESET_MODULE;
 158         else
 159 @@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask)
 160                 reg = AR933X_RESET_REG_RESET_MODULE;
 161         else if (soc_is_ar934x())
 162                 reg = AR934X_RESET_REG_RESET_MODULE;
 163 +       else if (soc_is_qca953x())
 164 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 165         else if (soc_is_qca955x())
 166                 reg = QCA955X_RESET_REG_RESET_MODULE;
 167         else
 168 --- a/arch/mips/ath79/dev-common.c
 169 +++ b/arch/mips/ath79/dev-common.c
 170 @@ -93,6 +93,7 @@ void __init ath79_register_uart(void)
 171             soc_is_ar724x() ||
 172             soc_is_ar913x() ||
 173             soc_is_ar934x() ||
 174 +           soc_is_qca953x() ||
 175             soc_is_qca955x()) {
 176                 ath79_uart_data[0].uartclk = uart_clk_rate;
 177                 platform_device_register(&ath79_uart_device);
 178 --- a/arch/mips/ath79/dev-usb.c
 179 +++ b/arch/mips/ath79/dev-usb.c
 180 @@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void
 181                            &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 182  }
 183
 184 +static void __init qca953x_usb_setup(void)
 185 +{
 186 +       u32 bootstrap;
 187 +
 188 +       bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
 189 +
 190 +       ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE);
 191 +       udelay(1000);
 192 +
 193 +       ath79_device_reset_clear(QCA953X_RESET_USB_PHY);
 194 +       udelay(1000);
 195 +
 196 +       ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG);
 197 +       udelay(1000);
 198 +
 199 +       ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
 200 +       udelay(1000);
 201 +
 202 +       ath79_usb_register("ehci-platform", -1,
 203 +                          QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
 204 +                          ATH79_CPU_IRQ(3),
 205 +                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 206 +}
 207 +
 208  static void qca955x_usb_reset_notifier(struct platform_device *pdev)
 209  {
 210         u32 base;
 211 @@ -286,6 +310,8 @@ void __init ath79_register_usb(void)
 212                 ar933x_usb_setup();
 213         else if (soc_is_ar934x())
 214                 ar934x_usb_setup();
 215 +       else if (soc_is_qca953x())
 216 +               qca953x_usb_setup();
 217         else if (soc_is_qca955x())
 218                 qca955x_usb_setup();
 219         else
 220 --- a/arch/mips/ath79/dev-wmac.c
 221 +++ b/arch/mips/ath79/dev-wmac.c
 222 @@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
 223         return -ETIMEDOUT;
 224  }
 225
 226 -static int ar933x_r1_get_wmac_revision(void)
 227 +static int ar93xx_get_soc_revision(void)
 228  {
 229         return ath79_soc_rev;
 230  }
 231 @@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
 232                 ath79_wmac_data.is_clk_25mhz = true;
 233
 234         if (ath79_soc_rev == 1)
 235 -               ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
 236 +               ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
 237
 238         ath79_wmac_data.external_reset = ar933x_wmac_reset;
 239  }
 240 @@ -149,6 +149,26 @@ static void ar934x_wmac_setup(void)
 241                 ath79_wmac_data.is_clk_25mhz = true;
 242  }
 243
 244 +static void qca953x_wmac_setup(void)
 245 +{
 246 +       u32 t;
 247 +
 248 +       ath79_wmac_device.name = "qca953x_wmac";
 249 +
 250 +       ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
 251 +       ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
 252 +       ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
 253 +       ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
 254 +
 255 +       t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
 256 +       if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
 257 +               ath79_wmac_data.is_clk_25mhz = false;
 258 +       else
 259 +               ath79_wmac_data.is_clk_25mhz = true;
 260 +
 261 +       ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
 262 +}
 263 +
 264  static void qca955x_wmac_setup(void)
 265  {
 266         u32 t;
 267 @@ -366,6 +386,8 @@ void __init ath79_register_wmac(u8 *cal_
 268                 ar933x_wmac_setup();
 269         else if (soc_is_ar934x())
 270                 ar934x_wmac_setup();
 271 +       else if (soc_is_qca953x())
 272 +               qca953x_wmac_setup();
 273         else if (soc_is_qca955x())
 274                 qca955x_wmac_setup();
 275         else
 276 --- a/arch/mips/ath79/early_printk.c
 277 +++ b/arch/mips/ath79/early_printk.c
 278 @@ -114,6 +114,8 @@ static void prom_putchar_init(void)
 279         case REV_ID_MAJOR_AR9341:
 280         case REV_ID_MAJOR_AR9342:
 281         case REV_ID_MAJOR_AR9344:
 282 +       case REV_ID_MAJOR_QCA9533:
 283 +       case REV_ID_MAJOR_QCA9533_V2:
 284         case REV_ID_MAJOR_QCA9556:
 285         case REV_ID_MAJOR_QCA9558:
 286                 _prom_putchar = prom_putchar_ar71xx;
 287 --- a/arch/mips/ath79/gpio.c
 288 +++ b/arch/mips/ath79/gpio.c
 289 @@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_func
 290             soc_is_ar913x() ||
 291             soc_is_ar933x())
 292                 reg = AR71XX_GPIO_REG_FUNC;
 293 -       else if (soc_is_ar934x())
 294 +       else if (soc_is_ar934x() || soc_is_qca953x())
 295                 reg = AR934X_GPIO_REG_FUNC;
 296         else
 297                 BUG();
 298 @@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(uns
 299         unsigned int reg;
 300         u32 t, s;
 301
 302 -       BUG_ON(!soc_is_ar934x());
 303 +       BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
 304
 305         if (gpio >= AR934X_GPIO_COUNT)
 306                 return;
 307 @@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
 308                 ath79_gpio_count = AR933X_GPIO_COUNT;
 309         else if (soc_is_ar934x())
 310                 ath79_gpio_count = AR934X_GPIO_COUNT;
 311 +       else if (soc_is_qca953x())
 312 +               ath79_gpio_count = QCA953X_GPIO_COUNT;
 313         else if (soc_is_qca955x())
 314                 ath79_gpio_count = QCA955X_GPIO_COUNT;
 315         else
 316 @@ -231,7 +233,7 @@ void __init ath79_gpio_init(void)
 317
 318         ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 319         ath79_gpio_chip.ngpio = ath79_gpio_count;
 320 -       if (soc_is_ar934x() || soc_is_qca955x()) {
 321 +       if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
 322                 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
 323                 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
 324         }
 325 --- a/arch/mips/ath79/irq.c
 326 +++ b/arch/mips/ath79/irq.c
 327 @@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
 328         else if (soc_is_ar724x() ||
 329                  soc_is_ar933x() ||
 330                  soc_is_ar934x() ||
 331 +                soc_is_qca953x() ||
 332                  soc_is_qca955x())
 333                 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
 334         else
 335 @@ -153,6 +154,38 @@ static void ar934x_ip2_irq_init(void)
 336         irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
 337  }
 338
 339 +static void qca953x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 340 +{
 341 +       u32 status;
 342 +
 343 +       disable_irq_nosync(irq);
 344 +
 345 +       status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
 346 +
 347 +       if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
 348 +               ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE);
 349 +               generic_handle_irq(ATH79_IP2_IRQ(0));
 350 +       } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
 351 +               ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC);
 352 +               generic_handle_irq(ATH79_IP2_IRQ(1));
 353 +       } else {
 354 +               spurious_interrupt();
 355 +       }
 356 +
 357 +       enable_irq(irq);
 358 +}
 359 +
 360 +static void qca953x_irq_init(void)
 361 +{
 362 +       int i;
 363 +
 364 +       for (i = ATH79_IP2_IRQ_BASE;
 365 +            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 366 +               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 367 +
 368 +       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
 369 +}
 370 +
 371  static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 372  {
 373         u32 status;
 374 @@ -335,6 +368,12 @@ static void ar934x_ip3_handler(void)
 375         do_IRQ(ATH79_CPU_IRQ(3));
 376  }
 377
 378 +static void qca953x_ip3_handler(void)
 379 +{
 380 +       ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_USB);
 381 +       do_IRQ(ATH79_CPU_IRQ(3));
 382 +}
 383 +
 384  void __init arch_init_irq(void)
 385  {
 386         if (soc_is_ar71xx()) {
 387 @@ -352,6 +391,9 @@ void __init arch_init_irq(void)
 388         } else if (soc_is_ar934x()) {
 389                 ath79_ip2_handler = ath79_default_ip2_handler;
 390                 ath79_ip3_handler = ar934x_ip3_handler;
 391 +       } else if (soc_is_qca953x()) {
 392 +               ath79_ip2_handler = ath79_default_ip2_handler;
 393 +               ath79_ip3_handler = qca953x_ip3_handler;
 394         } else if (soc_is_qca955x()) {
 395                 ath79_ip2_handler = ath79_default_ip2_handler;
 396                 ath79_ip3_handler = ath79_default_ip3_handler;
 397 @@ -364,6 +406,8 @@ void __init arch_init_irq(void)
 398
 399         if (soc_is_ar934x())
 400                 ar934x_ip2_irq_init();
 401 +       else if (soc_is_qca953x())
 402 +               qca953x_irq_init();
 403         else if (soc_is_qca955x())
 404                 qca955x_irq_init();
 405  }
 406 --- a/arch/mips/ath79/setup.c
 407 +++ b/arch/mips/ath79/setup.c
 408 @@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
 409         u32 major;
 410         u32 minor;
 411         u32 rev = 0;
 412 +       u32 ver = 1;
 413
 414         id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
 415         major = id & REV_ID_MAJOR_MASK;
 416 @@ -151,6 +152,16 @@ static void __init ath79_detect_sys_type
 417                 rev = id & AR934X_REV_ID_REVISION_MASK;
 418                 break;
 419
 420 +       case REV_ID_MAJOR_QCA9533_V2:
 421 +               ver = 2;
 422 +               /* drop through */
 423 +
 424 +       case REV_ID_MAJOR_QCA9533:
 425 +               ath79_soc = ATH79_SOC_QCA9533;
 426 +               chip = "9533";
 427 +               rev = id & QCA953X_REV_ID_REVISION_MASK;
 428 +               break;
 429 +
 430         case REV_ID_MAJOR_QCA9556:
 431                 ath79_soc = ATH79_SOC_QCA9556;
 432                 chip = "9556";
 433 @@ -169,7 +180,7 @@ static void __init ath79_detect_sys_type
 434
 435         ath79_soc_rev = rev;
 436
 437 -       if (soc_is_qca955x())
 438 +       if (soc_is_qca953x() || soc_is_qca955x())
 439                 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
 440                         chip, rev);
 441         else
 442 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 443 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 444 @@ -105,6 +105,21 @@
 445  #define AR934X_SRIF_BASE       (AR71XX_APB_BASE + 0x00116000)
 446  #define AR934X_SRIF_SIZE       0x1000
 447
 448 +#define QCA953X_GMAC_BASE      (AR71XX_APB_BASE + 0x00070000)
 449 +#define QCA953X_GMAC_SIZE      0x14
 450 +#define QCA953X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
 451 +#define QCA953X_WMAC_SIZE      0x20000
 452 +#define QCA953X_EHCI_BASE      0x1b000000
 453 +#define QCA953X_EHCI_SIZE      0x200
 454 +#define QCA953X_SRIF_BASE      (AR71XX_APB_BASE + 0x00116000)
 455 +#define QCA953X_SRIF_SIZE      0x1000
 456 +
 457 +#define QCA953X_PCI_CFG_BASE0  0x14000000
 458 +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
 459 +#define QCA953X_PCI_CRP_BASE0  (AR71XX_APB_BASE + 0x000c0000)
 460 +#define QCA953X_PCI_MEM_BASE0  0x10000000
 461 +#define QCA953X_PCI_MEM_SIZE   0x02000000
 462 +
 463  #define QCA955X_PCI_MEM_BASE0  0x10000000
 464  #define QCA955X_PCI_MEM_BASE1  0x12000000
 465  #define QCA955X_PCI_MEM_SIZE   0x02000000
 466 @@ -173,6 +188,12 @@
 467  #define AR934X_DDR_REG_FLUSH_PCIE      0xa8
 468  #define AR934X_DDR_REG_FLUSH_WMAC      0xac
 469
 470 +#define QCA953X_DDR_REG_FLUSH_GE0      0x9c
 471 +#define QCA953X_DDR_REG_FLUSH_GE1      0xa0
 472 +#define QCA953X_DDR_REG_FLUSH_USB      0xa4
 473 +#define QCA953X_DDR_REG_FLUSH_PCIE     0xa8
 474 +#define QCA953X_DDR_REG_FLUSH_WMAC     0xac
 475 +
 476  /*
 477   * PLL block
 478   */
 479 @@ -279,6 +300,44 @@
 480
 481  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   BIT(6)
 482
 483 +#define QCA953X_PLL_CPU_CONFIG_REG             0x00
 484 +#define QCA953X_PLL_DDR_CONFIG_REG             0x04
 485 +#define QCA953X_PLL_CLK_CTRL_REG               0x08
 486 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG   0x24
 487 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG       0x2c
 488 +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG      0x48
 489 +
 490 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
 491 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
 492 +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT      6
 493 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK       0x3f
 494 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT    12
 495 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK     0x1f
 496 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT    19
 497 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK     0x7
 498 +
 499 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT     0
 500 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK      0x3ff
 501 +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT      10
 502 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK       0x3f
 503 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT    16
 504 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK     0x1f
 505 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT    23
 506 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK     0x7
 507 +
 508 +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS            BIT(2)
 509 +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS            BIT(3)
 510 +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS            BIT(4)
 511 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT                5
 512 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK         0x1f
 513 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT                10
 514 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK         0x1f
 515 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT                15
 516 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK         0x1f
 517 +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL                BIT(20)
 518 +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL                BIT(21)
 519 +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
 520 +
 521  #define QCA955X_PLL_CPU_CONFIG_REG             0x00
 522  #define QCA955X_PLL_DDR_CONFIG_REG             0x04
 523  #define QCA955X_PLL_CLK_CTRL_REG               0x08
 524 @@ -355,6 +414,10 @@
 525  #define AR934X_RESET_REG_BOOTSTRAP             0xb0
 526  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS  0xac
 527
 528 +#define QCA953X_RESET_REG_RESET_MODULE         0x1c
 529 +#define QCA953X_RESET_REG_BOOTSTRAP            0xb0
 530 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
 531 +
 532  #define QCA955X_RESET_REG_RESET_MODULE         0x1c
 533  #define QCA955X_RESET_REG_BOOTSTRAP            0xb0
 534  #define QCA955X_RESET_REG_EXT_INT_STATUS       0xac
 535 @@ -450,6 +513,27 @@
 536  #define AR934X_RESET_MBOX              BIT(1)
 537  #define AR934X_RESET_I2S               BIT(0)
 538
 539 +#define QCA953X_RESET_USB_EXT_PWR      BIT(29)
 540 +#define QCA953X_RESET_EXTERNAL         BIT(28)
 541 +#define QCA953X_RESET_RTC              BIT(27)
 542 +#define QCA953X_RESET_FULL_CHIP                BIT(24)
 543 +#define QCA953X_RESET_GE1_MDIO         BIT(23)
 544 +#define QCA953X_RESET_GE0_MDIO         BIT(22)
 545 +#define QCA953X_RESET_CPU_NMI          BIT(21)
 546 +#define QCA953X_RESET_CPU_COLD         BIT(20)
 547 +#define QCA953X_RESET_DDR              BIT(16)
 548 +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
 549 +#define QCA953X_RESET_GE1_MAC          BIT(13)
 550 +#define QCA953X_RESET_ETH_SWITCH_ANALOG        BIT(12)
 551 +#define QCA953X_RESET_USB_PHY_ANALOG   BIT(11)
 552 +#define QCA953X_RESET_GE0_MAC          BIT(9)
 553 +#define QCA953X_RESET_ETH_SWITCH       BIT(8)
 554 +#define QCA953X_RESET_PCIE_PHY         BIT(7)
 555 +#define QCA953X_RESET_PCIE             BIT(6)
 556 +#define QCA953X_RESET_USB_HOST         BIT(5)
 557 +#define QCA953X_RESET_USB_PHY          BIT(4)
 558 +#define QCA953X_RESET_USBSUS_OVERRIDE  BIT(3)
 559 +
 560  #define QCA955X_RESET_HOST             BIT(31)
 561  #define QCA955X_RESET_SLIC             BIT(30)
 562  #define QCA955X_RESET_HDMA             BIT(29)
 563 @@ -503,6 +587,13 @@
 564  #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
 565  #define AR934X_BOOTSTRAP_DDR1          BIT(0)
 566
 567 +#define QCA953X_BOOTSTRAP_SW_OPTION2   BIT(12)
 568 +#define QCA953X_BOOTSTRAP_SW_OPTION1   BIT(11)
 569 +#define QCA953X_BOOTSTRAP_EJTAG_MODE   BIT(5)
 570 +#define QCA953X_BOOTSTRAP_REF_CLK_40   BIT(4)
 571 +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
 572 +#define QCA953X_BOOTSTRAP_DDR1         BIT(0)
 573 +
 574  #define QCA955X_BOOTSTRAP_REF_CLK_40   BIT(4)
 575
 576  #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
 577 @@ -523,6 +614,24 @@
 578          AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
 579          AR934X_PCIE_WMAC_INT_PCIE_RC3)
 580
 581 +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
 582 +#define QCA953X_PCIE_WMAC_INT_WMAC_TX          BIT(1)
 583 +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP                BIT(2)
 584 +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP                BIT(3)
 585 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC          BIT(4)
 586 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0         BIT(5)
 587 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1         BIT(6)
 588 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2         BIT(7)
 589 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3         BIT(8)
 590 +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
 591 +       (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
 592 +        QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
 593 +
 594 +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
 595 +       (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
 596 +        QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
 597 +        QCA953X_PCIE_WMAC_INT_PCIE_RC3)
 598 +
 599  #define QCA955X_EXT_INT_WMAC_MISC              BIT(0)
 600  #define QCA955X_EXT_INT_WMAC_TX                        BIT(1)
 601  #define QCA955X_EXT_INT_WMAC_RXLP              BIT(2)
 602 @@ -565,6 +674,8 @@
 603  #define REV_ID_MAJOR_AR9341            0x0120
 604  #define REV_ID_MAJOR_AR9342            0x1120
 605  #define REV_ID_MAJOR_AR9344            0x2120
 606 +#define REV_ID_MAJOR_QCA9533           0x0140
 607 +#define REV_ID_MAJOR_QCA9533_V2                0x0160
 608  #define REV_ID_MAJOR_QCA9556           0x0130
 609  #define REV_ID_MAJOR_QCA9558           0x1130
 610
 611 @@ -587,6 +698,8 @@
 612
 613  #define AR934X_REV_ID_REVISION_MASK    0xf
 614
 615 +#define QCA953X_REV_ID_REVISION_MASK   0xf
 616 +
 617  #define QCA955X_REV_ID_REVISION_MASK   0xf
 618
 619  /*
 620 @@ -634,12 +747,32 @@
 621  #define AR934X_GPIO_REG_OUT_FUNC5      0x40
 622  #define AR934X_GPIO_REG_FUNC           0x6c
 623
 624 +#define QCA953X_GPIO_REG_OUT_FUNC0     0x2c
 625 +#define QCA953X_GPIO_REG_OUT_FUNC1     0x30
 626 +#define QCA953X_GPIO_REG_OUT_FUNC2     0x34
 627 +#define QCA953X_GPIO_REG_OUT_FUNC3     0x38
 628 +#define QCA953X_GPIO_REG_OUT_FUNC4     0x3c
 629 +#define QCA953X_GPIO_REG_IN_ENABLE0    0x44
 630 +#define QCA953X_GPIO_REG_FUNC          0x6c
 631 +
 632 +#define QCA953X_GPIO_OUT_MUX_SPI_CS1           10
 633 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2           11
 634 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0           9
 635 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK           8
 636 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI          12
 637 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1         41
 638 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2         42
 639 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3         43
 640 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4         44
 641 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5         45
 642 +
 643  #define AR71XX_GPIO_COUNT              16
 644  #define AR7240_GPIO_COUNT              18
 645  #define AR7241_GPIO_COUNT              20
 646  #define AR913X_GPIO_COUNT              22
 647  #define AR933X_GPIO_COUNT              30
 648  #define AR934X_GPIO_COUNT              23
 649 +#define QCA953X_GPIO_COUNT             18
 650  #define QCA955X_GPIO_COUNT             24
 651
 652  /*
 653 @@ -663,6 +796,24 @@
 654  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
 655  #define AR934X_SRIF_DPLL2_OUTDIV_MASK  0x7
 656
 657 +#define QCA953X_SRIF_CPU_DPLL1_REG     0x1c0
 658 +#define QCA953X_SRIF_CPU_DPLL2_REG     0x1c4
 659 +#define QCA953X_SRIF_CPU_DPLL3_REG     0x1c8
 660 +
 661 +#define QCA953X_SRIF_DDR_DPLL1_REG     0x240
 662 +#define QCA953X_SRIF_DDR_DPLL2_REG     0x244
 663 +#define QCA953X_SRIF_DDR_DPLL3_REG     0x248
 664 +
 665 +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT        27
 666 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
 667 +#define QCA953X_SRIF_DPLL1_NINT_SHIFT  18
 668 +#define QCA953X_SRIF_DPLL1_NINT_MASK   0x1ff
 669 +#define QCA953X_SRIF_DPLL1_NFRAC_MASK  0x0003ffff
 670 +
 671 +#define QCA953X_SRIF_DPLL2_LOCAL_PLL   BIT(30)
 672 +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT        13
 673 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
 674 +
 675  #define AR71XX_GPIO_FUNC_STEREO_EN             BIT(17)
 676  #define AR71XX_GPIO_FUNC_SLIC_EN               BIT(16)
 677  #define AR71XX_GPIO_FUNC_SPI_CS2_EN            BIT(13)
 678 @@ -804,6 +955,16 @@
 679  #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
 680
 681  /*
 682 + * QCA953X GMAC Interface
 683 + */
 684 +#define QCA953X_GMAC_REG_ETH_CFG               0x00
 685 +
 686 +#define QCA953X_ETH_CFG_SW_ONLY_MODE           BIT(6)
 687 +#define QCA953X_ETH_CFG_SW_PHY_SWAP            BIT(7)
 688 +#define QCA953X_ETH_CFG_SW_APB_ACCESS          BIT(9)
 689 +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST       BIT(13)
 690 +
 691 +/*
 692   * QCA955X GMAC Interface
 693   */
 694
 695 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 696 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 697 @@ -32,6 +32,7 @@ enum ath79_soc_type {
 698         ATH79_SOC_AR9341,
 699         ATH79_SOC_AR9342,
 700         ATH79_SOC_AR9344,
 701 +       ATH79_SOC_QCA9533,
 702         ATH79_SOC_QCA9556,
 703         ATH79_SOC_QCA9558,
 704  };
 705 @@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
 706         return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
 707  }
 708
 709 +static inline int soc_is_qca9533(void)
 710 +{
 711 +       return ath79_soc == ATH79_SOC_QCA9533;
 712 +}
 713 +
 714 +static inline int soc_is_qca953x(void)
 715 +{
 716 +       return soc_is_qca9533();
 717 +}
 718 +
 719  static inline int soc_is_qca9556(void)
 720  {
 721         return ath79_soc == ATH79_SOC_QCA9556;