target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch

   1 From 281db30007b5836ce8acf5a45160fde6b176eda4 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Fri, 15 Feb 2013 13:38:24 +0000
   4 Subject: [PATCH] MIPS: ath79: add USB controller registration code for the
   5  QCA955X SoCs
   6
   7 commit 82c46840ae6bd8a147c59cd51f636d913989324a upstream.
   8
   9 Register platfom devices for the built-in USB
  10 controllers of the SoCs.
  11
  12 Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
  13 Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
  14 Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
  15 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  16 Patchwork: http://patchwork.linux-mips.org/patch/4952/
  17 Signed-off-by: John Crispin <blogic@openwrt.org>
  18 ---
  19  arch/mips/ath79/dev-usb.c                      |   15 +++++++++++++++
  20  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    3 +++
  21  2 files changed, 18 insertions(+)
  22
  23 --- a/arch/mips/ath79/dev-usb.c
  24 +++ b/arch/mips/ath79/dev-usb.c
  25 @@ -208,6 +208,19 @@ static void __init ar934x_usb_setup(void
  26                            &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  27  }
  28
  29 +static void __init qca955x_usb_setup(void)
  30 +{
  31 +       ath79_usb_register("ehci-platform", 0,
  32 +                          QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
  33 +                          ATH79_IP3_IRQ(0),
  34 +                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  35 +
  36 +       ath79_usb_register("ehci-platform", 1,
  37 +                          QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
  38 +                          ATH79_IP3_IRQ(1),
  39 +                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  40 +}
  41 +
  42  void __init ath79_register_usb(void)
  43  {
  44         if (soc_is_ar71xx())
  45 @@ -222,6 +235,8 @@ void __init ath79_register_usb(void)
  46                 ar933x_usb_setup();
  47         else if (soc_is_ar934x())
  48                 ar934x_usb_setup();
  49 +       else if (soc_is_qca955x())
  50 +               qca955x_usb_setup();
  51         else
  52                 BUG();
  53  }
  54 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  55 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  56 @@ -109,6 +109,9 @@
  57
  58  #define QCA955X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
  59  #define QCA955X_WMAC_SIZE      0x20000
  60 +#define QCA955X_EHCI0_BASE     0x1b000000
  61 +#define QCA955X_EHCI1_BASE     0x1b400000
  62 +#define QCA955X_EHCI_SIZE      0x1000
  63
  64  /*
  65   * DDR_CTRL block