target/linux/ar71xx/patches-3.8/032-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch

   1 From 8817bcbbaf64d54bd4d06659cc77d1bfc9e53dad Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Fri, 15 Feb 2013 13:38:19 +0000
   4 Subject: [PATCH] MIPS: ath79: add GPIO setup code for the QCA955X SoCs
   5
   6 commit f818ca3e6894d4a630a1ecc673c91df8fb6f6898 upstream.
   7
   8 The existing code can handle the GPIO controller of
   9 the QCA955x SoCs. Add a minimal glue code to make it
  10 working.
  11
  12 Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
  13 Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
  14 Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
  15 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  16 Patchwork: http://patchwork.linux-mips.org/patch/4947/
  17 Signed-off-by: John Crispin <blogic@openwrt.org>
  18 ---
  19  arch/mips/ath79/gpio.c                         |    4 +++-
  20  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    1 +
  21  2 files changed, 4 insertions(+), 1 deletion(-)
  22
  23 --- a/arch/mips/ath79/gpio.c
  24 +++ b/arch/mips/ath79/gpio.c
  25 @@ -194,12 +194,14 @@ void __init ath79_gpio_init(void)
  26                 ath79_gpio_count = AR933X_GPIO_COUNT;
  27         else if (soc_is_ar934x())
  28                 ath79_gpio_count = AR934X_GPIO_COUNT;
  29 +       else if (soc_is_qca955x())
  30 +               ath79_gpio_count = QCA955X_GPIO_COUNT;
  31         else
  32                 BUG();
  33
  34         ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
  35         ath79_gpio_chip.ngpio = ath79_gpio_count;
  36 -       if (soc_is_ar934x()) {
  37 +       if (soc_is_ar934x() || soc_is_qca955x()) {
  38                 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
  39                 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
  40         }
  41 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  42 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  43 @@ -510,6 +510,7 @@
  44  #define AR913X_GPIO_COUNT              22
  45  #define AR933X_GPIO_COUNT              30
  46  #define AR934X_GPIO_COUNT              23
  47 +#define QCA955X_GPIO_COUNT             24
  48
  49  /*
  50   * SRIF block