target/linux/ar71xx/patches-3.6/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch

   1 From c3a8b5fa196cedc4b940c1e5ec482dd875aa3180 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Mon, 11 Jun 2012 13:38:06 +0200
   4 Subject: [PATCH 06/34] MIPS: ath79: move global PCI defines into a common header
   5
   6 The constants will be used by a subsequent patch.
   7
   8 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   9 ---
  10  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   24 ++++++++++++++++++++++++
  11  arch/mips/pci/pci-ar71xx.c                     |   16 ----------------
  12  arch/mips/pci/pci-ar724x.c                     |    8 --------
  13  3 files changed, 24 insertions(+), 24 deletions(-)
  14
  15 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  16 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  17 @@ -41,11 +41,35 @@
  18  #define AR71XX_RESET_BASE      (AR71XX_APB_BASE + 0x00060000)
  19  #define AR71XX_RESET_SIZE      0x100
  20
  21 +#define AR71XX_PCI_MEM_BASE    0x10000000
  22 +#define AR71XX_PCI_MEM_SIZE    0x07000000
  23 +
  24 +#define AR71XX_PCI_WIN0_OFFS   0x10000000
  25 +#define AR71XX_PCI_WIN1_OFFS   0x11000000
  26 +#define AR71XX_PCI_WIN2_OFFS   0x12000000
  27 +#define AR71XX_PCI_WIN3_OFFS   0x13000000
  28 +#define AR71XX_PCI_WIN4_OFFS   0x14000000
  29 +#define AR71XX_PCI_WIN5_OFFS   0x15000000
  30 +#define AR71XX_PCI_WIN6_OFFS   0x16000000
  31 +#define AR71XX_PCI_WIN7_OFFS   0x07000000
  32 +
  33 +#define AR71XX_PCI_CFG_BASE    \
  34 +       (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
  35 +#define AR71XX_PCI_CFG_SIZE    0x100
  36 +
  37  #define AR7240_USB_CTRL_BASE   (AR71XX_APB_BASE + 0x00030000)
  38  #define AR7240_USB_CTRL_SIZE   0x100
  39  #define AR7240_OHCI_BASE       0x1b000000
  40  #define AR7240_OHCI_SIZE       0x1000
  41
  42 +#define AR724X_PCI_MEM_BASE    0x10000000
  43 +#define AR724X_PCI_MEM_SIZE    0x04000000
  44 +
  45 +#define AR724X_PCI_CFG_BASE    0x14000000
  46 +#define AR724X_PCI_CFG_SIZE    0x1000
  47 +#define AR724X_PCI_CTRL_BASE   (AR71XX_APB_BASE + 0x000f0000)
  48 +#define AR724X_PCI_CTRL_SIZE   0x100
  49 +
  50  #define AR724X_EHCI_BASE       0x1b000000
  51  #define AR724X_EHCI_SIZE       0x1000
  52
  53 --- a/arch/mips/pci/pci-ar71xx.c
  54 +++ b/arch/mips/pci/pci-ar71xx.c
  55 @@ -25,22 +25,6 @@
  56  #include <asm/mach-ath79/ath79.h>
  57  #include <asm/mach-ath79/pci.h>
  58
  59 -#define AR71XX_PCI_MEM_BASE    0x10000000
  60 -#define AR71XX_PCI_MEM_SIZE    0x07000000
  61 -
  62 -#define AR71XX_PCI_WIN0_OFFS           0x10000000
  63 -#define AR71XX_PCI_WIN1_OFFS           0x11000000
  64 -#define AR71XX_PCI_WIN2_OFFS           0x12000000
  65 -#define AR71XX_PCI_WIN3_OFFS           0x13000000
  66 -#define AR71XX_PCI_WIN4_OFFS           0x14000000
  67 -#define AR71XX_PCI_WIN5_OFFS           0x15000000
  68 -#define AR71XX_PCI_WIN6_OFFS           0x16000000
  69 -#define AR71XX_PCI_WIN7_OFFS           0x07000000
  70 -
  71 -#define AR71XX_PCI_CFG_BASE            \
  72 -       (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
  73 -#define AR71XX_PCI_CFG_SIZE            0x100
  74 -
  75  #define AR71XX_PCI_REG_CRP_AD_CBE      0x00
  76  #define AR71XX_PCI_REG_CRP_WRDATA      0x04
  77  #define AR71XX_PCI_REG_CRP_RDDATA      0x08
  78 --- a/arch/mips/pci/pci-ar724x.c
  79 +++ b/arch/mips/pci/pci-ar724x.c
  80 @@ -17,14 +17,6 @@
  81  #include <asm/mach-ath79/ar71xx_regs.h>
  82  #include <asm/mach-ath79/pci.h>
  83
  84 -#define AR724X_PCI_CFG_BASE    0x14000000
  85 -#define AR724X_PCI_CFG_SIZE    0x1000
  86 -#define AR724X_PCI_CTRL_BASE   (AR71XX_APB_BASE + 0x000f0000)
  87 -#define AR724X_PCI_CTRL_SIZE   0x100
  88 -
  89 -#define AR724X_PCI_MEM_BASE    0x10000000
  90 -#define AR724X_PCI_MEM_SIZE    0x04000000
  91 -
  92  #define AR724X_PCI_REG_RESET           0x18
  93  #define AR724X_PCI_REG_INT_STATUS      0x4c
  94  #define AR724X_PCI_REG_INT_MASK                0x50