target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch

   1 From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
   2 Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
   3 From: Matthias Schiffer <mschiffer@universe-factory.net>
   4 Date: Sat, 29 Mar 2014 20:26:08 +0100
   5 Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
   6
   7 Note that the clock calculation looks very similar to the QCA955x, but the
   8 meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
   9 ---
  10  arch/mips/ath79/Kconfig                        |  6 +-
  11  arch/mips/ath79/clock.c                        | 78 ++++++++++++++++++++++++++
  12  arch/mips/ath79/common.c                       |  4 ++
  13  arch/mips/ath79/dev-common.c                   |  1 +
  14  arch/mips/ath79/dev-wmac.c                     | 20 +++++++
  15  arch/mips/ath79/early_printk.c                 |  1 +
  16  arch/mips/ath79/gpio.c                         |  4 +-
  17  arch/mips/ath79/irq.c                          |  4 ++
  18  arch/mips/ath79/setup.c                        |  8 ++-
  19  arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
  20  arch/mips/include/asm/mach-ath79/ath79.h       | 11 ++++
  21  11 files changed, 182 insertions(+), 3 deletions(-)
  22
  23 --- a/arch/mips/ath79/Kconfig
  24 +++ b/arch/mips/ath79/Kconfig
  25 @@ -1178,6 +1178,10 @@ config SOC_AR934X
  26         select PCI_AR724X if PCI
  27         def_bool n
  28
  29 +config SOC_QCA953X
  30 +       select USB_ARCH_HAS_EHCI
  31 +       def_bool n
  32 +
  33  config SOC_QCA955X
  34         select HW_HAS_PCI
  35         select PCI_AR724X if PCI
  36 @@ -1220,7 +1224,7 @@ config ATH79_DEV_USB
  37         def_bool n
  38
  39  config ATH79_DEV_WMAC
  40 -       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
  41 +       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
  42         def_bool n
  43
  44  config ATH79_NVRAM
  45 --- a/arch/mips/ath79/clock.c
  46 +++ b/arch/mips/ath79/clock.c
  47 @@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(vo
  48         iounmap(dpll_base);
  49  }
  50
  51 +static void __init qca953x_clocks_init(void)
  52 +{
  53 +       unsigned long ref_rate;
  54 +       unsigned long cpu_rate;
  55 +       unsigned long ddr_rate;
  56 +       unsigned long ahb_rate;
  57 +       u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
  58 +       u32 cpu_pll, ddr_pll;
  59 +       u32 bootstrap;
  60 +
  61 +       bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
  62 +       if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
  63 +               ref_rate = 40 * 1000 * 1000;
  64 +       else
  65 +               ref_rate = 25 * 1000 * 1000;
  66 +
  67 +       pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
  68 +       out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  69 +                 QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
  70 +       ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  71 +                 QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
  72 +       nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
  73 +              QCA953X_PLL_CPU_CONFIG_NINT_MASK;
  74 +       frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
  75 +              QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
  76 +
  77 +       cpu_pll = nint * ref_rate / ref_div;
  78 +       cpu_pll += frac * (ref_rate >> 6) / ref_div;
  79 +       cpu_pll /= (1 << out_div);
  80 +
  81 +       pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
  82 +       out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  83 +                 QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
  84 +       ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  85 +                 QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
  86 +       nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
  87 +              QCA953X_PLL_DDR_CONFIG_NINT_MASK;
  88 +       frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  89 +              QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
  90 +
  91 +       ddr_pll = nint * ref_rate / ref_div;
  92 +       ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
  93 +       ddr_pll /= (1 << out_div);
  94 +
  95 +       clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
  96 +
  97 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  98 +                 QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  99 +
 100 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
 101 +               cpu_rate = ref_rate;
 102 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
 103 +               cpu_rate = cpu_pll / (postdiv + 1);
 104 +       else
 105 +               cpu_rate = ddr_pll / (postdiv + 1);
 106 +
 107 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 108 +                 QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
 109 +
 110 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
 111 +               ddr_rate = ref_rate;
 112 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 113 +               ddr_rate = ddr_pll / (postdiv + 1);
 114 +       else
 115 +               ddr_rate = cpu_pll / (postdiv + 1);
 116 +
 117 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 118 +                 QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 119 +
 120 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
 121 +               ahb_rate = ref_rate;
 122 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 123 +               ahb_rate = ddr_pll / (postdiv + 1);
 124 +       else
 125 +               ahb_rate = cpu_pll / (postdiv + 1);
 126 +
 127 +       ath79_add_sys_clkdev("ref", ref_rate);
 128 +       ath79_add_sys_clkdev("cpu", cpu_rate);
 129 +       ath79_add_sys_clkdev("ddr", ddr_rate);
 130 +       ath79_add_sys_clkdev("ahb", ahb_rate);
 131 +
 132 +       clk_add_alias("wdt", NULL, "ref", NULL);
 133 +       clk_add_alias("uart", NULL, "ref", NULL);
 134 +}
 135 +
 136  static void __init qca955x_clocks_init(void)
 137  {
 138         unsigned long ref_rate;
 139 @@ -447,6 +532,8 @@ void __init ath79_clocks_init(void)
 140                 ar933x_clocks_init();
 141         else if (soc_is_ar934x())
 142                 ar934x_clocks_init();
 143 +       else if (soc_is_qca953x())
 144 +               qca953x_clocks_init();
 145         else if (soc_is_qca955x())
 146                 qca955x_clocks_init();
 147         else
 148 --- a/arch/mips/ath79/common.c
 149 +++ b/arch/mips/ath79/common.c
 150 @@ -73,6 +73,8 @@ void ath79_device_reset_set(u32 mask)
 151                 reg = AR933X_RESET_REG_RESET_MODULE;
 152         else if (soc_is_ar934x())
 153                 reg = AR934X_RESET_REG_RESET_MODULE;
 154 +       else if (soc_is_qca953x())
 155 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 156         else if (soc_is_qca955x())
 157                 reg = QCA955X_RESET_REG_RESET_MODULE;
 158         else
 159 @@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask)
 160                 reg = AR933X_RESET_REG_RESET_MODULE;
 161         else if (soc_is_ar934x())
 162                 reg = AR934X_RESET_REG_RESET_MODULE;
 163 +       else if (soc_is_qca953x())
 164 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 165         else if (soc_is_qca955x())
 166                 reg = QCA955X_RESET_REG_RESET_MODULE;
 167         else
 168 --- a/arch/mips/ath79/dev-common.c
 169 +++ b/arch/mips/ath79/dev-common.c
 170 @@ -93,6 +93,7 @@ void __init ath79_register_uart(void)
 171             soc_is_ar724x() ||
 172             soc_is_ar913x() ||
 173             soc_is_ar934x() ||
 174 +           soc_is_qca953x() ||
 175             soc_is_qca955x()) {
 176                 ath79_uart_data[0].uartclk = uart_clk_rate;
 177                 platform_device_register(&ath79_uart_device);
 178 --- a/arch/mips/ath79/dev-wmac.c
 179 +++ b/arch/mips/ath79/dev-wmac.c
 180 @@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
 181         return -ETIMEDOUT;
 182  }
 183
 184 -static int ar933x_r1_get_wmac_revision(void)
 185 +static int ar93xx_get_soc_revision(void)
 186  {
 187         return ath79_soc_rev;
 188  }
 189 @@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
 190                 ath79_wmac_data.is_clk_25mhz = true;
 191
 192         if (ath79_soc_rev == 1)
 193 -               ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
 194 +               ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
 195
 196         ath79_wmac_data.external_reset = ar933x_wmac_reset;
 197  }
 198 @@ -149,6 +149,26 @@ static void ar934x_wmac_setup(void)
 199                 ath79_wmac_data.is_clk_25mhz = true;
 200  }
 201
 202 +static void qca953x_wmac_setup(void)
 203 +{
 204 +       u32 t;
 205 +
 206 +       ath79_wmac_device.name = "qca953x_wmac";
 207 +
 208 +       ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
 209 +       ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
 210 +       ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
 211 +       ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
 212 +
 213 +       t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
 214 +       if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
 215 +               ath79_wmac_data.is_clk_25mhz = false;
 216 +       else
 217 +               ath79_wmac_data.is_clk_25mhz = true;
 218 +
 219 +       ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
 220 +}
 221 +
 222  static void qca955x_wmac_setup(void)
 223  {
 224         u32 t;
 225 @@ -366,6 +386,8 @@ void __init ath79_register_wmac(u8 *cal_
 226                 ar933x_wmac_setup();
 227         else if (soc_is_ar934x())
 228                 ar934x_wmac_setup();
 229 +       else if (soc_is_qca953x())
 230 +               qca953x_wmac_setup();
 231         else if (soc_is_qca955x())
 232                 qca955x_wmac_setup();
 233         else
 234 --- a/arch/mips/ath79/early_printk.c
 235 +++ b/arch/mips/ath79/early_printk.c
 236 @@ -114,6 +114,8 @@ static void prom_putchar_init(void)
 237         case REV_ID_MAJOR_AR9341:
 238         case REV_ID_MAJOR_AR9342:
 239         case REV_ID_MAJOR_AR9344:
 240 +       case REV_ID_MAJOR_QCA9533:
 241 +       case REV_ID_MAJOR_QCA9533_V2:
 242         case REV_ID_MAJOR_QCA9556:
 243         case REV_ID_MAJOR_QCA9558:
 244                 _prom_putchar = prom_putchar_ar71xx;
 245 --- a/arch/mips/ath79/gpio.c
 246 +++ b/arch/mips/ath79/gpio.c
 247 @@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
 248                 ath79_gpio_count = AR933X_GPIO_COUNT;
 249         else if (soc_is_ar934x())
 250                 ath79_gpio_count = AR934X_GPIO_COUNT;
 251 +       else if (soc_is_qca953x())
 252 +               ath79_gpio_count = QCA953X_GPIO_COUNT;
 253         else if (soc_is_qca955x())
 254                 ath79_gpio_count = QCA955X_GPIO_COUNT;
 255         else
 256 @@ -231,7 +233,7 @@ void __init ath79_gpio_init(void)
 257
 258         ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 259         ath79_gpio_chip.ngpio = ath79_gpio_count;
 260 -       if (soc_is_ar934x() || soc_is_qca955x()) {
 261 +       if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
 262                 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
 263                 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
 264         }
 265 --- a/arch/mips/ath79/irq.c
 266 +++ b/arch/mips/ath79/irq.c
 267 @@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
 268         else if (soc_is_ar724x() ||
 269                  soc_is_ar933x() ||
 270                  soc_is_ar934x() ||
 271 +                soc_is_qca953x() ||
 272                  soc_is_qca955x())
 273                 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
 274         else
 275 @@ -352,6 +353,9 @@ void __init arch_init_irq(void)
 276         } else if (soc_is_ar934x()) {
 277                 ath79_ip2_handler = ath79_default_ip2_handler;
 278                 ath79_ip3_handler = ar934x_ip3_handler;
 279 +       } else if (soc_is_qca953x()) {
 280 +               ath79_ip2_handler = ath79_default_ip2_handler;
 281 +               ath79_ip3_handler = ath79_default_ip3_handler;
 282         } else if (soc_is_qca955x()) {
 283                 ath79_ip2_handler = ath79_default_ip2_handler;
 284                 ath79_ip3_handler = ath79_default_ip3_handler;
 285 --- a/arch/mips/ath79/setup.c
 286 +++ b/arch/mips/ath79/setup.c
 287 @@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
 288         u32 major;
 289         u32 minor;
 290         u32 rev = 0;
 291 +       u32 ver = 1;
 292
 293         id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
 294         major = id & REV_ID_MAJOR_MASK;
 295 @@ -151,6 +152,16 @@ static void __init ath79_detect_sys_type
 296                 rev = id & AR934X_REV_ID_REVISION_MASK;
 297                 break;
 298
 299 +       case REV_ID_MAJOR_QCA9533_V2:
 300 +               ver = 2;
 301 +               /* drop through */
 302 +
 303 +       case REV_ID_MAJOR_QCA9533:
 304 +               ath79_soc = ATH79_SOC_QCA9533;
 305 +               chip = "9533";
 306 +               rev = id & QCA953X_REV_ID_REVISION_MASK;
 307 +               break;
 308 +
 309         case REV_ID_MAJOR_QCA9556:
 310                 ath79_soc = ATH79_SOC_QCA9556;
 311                 chip = "9556";
 312 @@ -169,9 +180,9 @@ static void __init ath79_detect_sys_type
 313
 314         ath79_soc_rev = rev;
 315
 316 -       if (soc_is_qca955x())
 317 -               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
 318 -                       chip, rev);
 319 +       if (soc_is_qca953x() || soc_is_qca955x())
 320 +               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
 321 +                       chip, ver, rev);
 322         else
 323                 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
 324         pr_info("SoC: %s\n", ath79_sys_type);
 325 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 326 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 327 @@ -105,6 +105,9 @@
 328  #define AR934X_SRIF_BASE       (AR71XX_APB_BASE + 0x00116000)
 329  #define AR934X_SRIF_SIZE       0x1000
 330
 331 +#define QCA953X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
 332 +#define QCA953X_WMAC_SIZE      0x20000
 333 +
 334  #define QCA955X_PCI_MEM_BASE0  0x10000000
 335  #define QCA955X_PCI_MEM_BASE1  0x12000000
 336  #define QCA955X_PCI_MEM_SIZE   0x02000000
 337 @@ -279,6 +282,43 @@
 338
 339  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   BIT(6)
 340
 341 +#define QCA953X_PLL_CPU_CONFIG_REG             0x00
 342 +#define QCA953X_PLL_DDR_CONFIG_REG             0x04
 343 +#define QCA953X_PLL_CLK_CTRL_REG               0x08
 344 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG       0x2c
 345 +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG      0x48
 346 +
 347 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
 348 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
 349 +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT      6
 350 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK       0x3f
 351 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT    12
 352 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK     0x1f
 353 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT    19
 354 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK     0x3
 355 +
 356 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT     0
 357 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK      0x3ff
 358 +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT      10
 359 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK       0x3f
 360 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT    16
 361 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK     0x1f
 362 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT    23
 363 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK     0x7
 364 +
 365 +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS            BIT(2)
 366 +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS            BIT(3)
 367 +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS            BIT(4)
 368 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT                5
 369 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK         0x1f
 370 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT                10
 371 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK         0x1f
 372 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT                15
 373 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK         0x1f
 374 +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL                BIT(20)
 375 +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL                BIT(21)
 376 +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
 377 +
 378  #define QCA955X_PLL_CPU_CONFIG_REG             0x00
 379  #define QCA955X_PLL_DDR_CONFIG_REG             0x04
 380  #define QCA955X_PLL_CLK_CTRL_REG               0x08
 381 @@ -355,6 +395,10 @@
 382  #define AR934X_RESET_REG_BOOTSTRAP             0xb0
 383  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS  0xac
 384
 385 +#define QCA953X_RESET_REG_RESET_MODULE         0x1c
 386 +#define QCA953X_RESET_REG_BOOTSTRAP            0xb0
 387 +#define QCA953X_RESET_REG_EXT_INT_STATUS       0xac
 388 +
 389  #define QCA955X_RESET_REG_RESET_MODULE         0x1c
 390  #define QCA955X_RESET_REG_BOOTSTRAP            0xb0
 391  #define QCA955X_RESET_REG_EXT_INT_STATUS       0xac
 392 @@ -503,6 +547,8 @@
 393  #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
 394  #define AR934X_BOOTSTRAP_DDR1          BIT(0)
 395
 396 +#define QCA953X_BOOTSTRAP_REF_CLK_40   BIT(4)
 397 +
 398  #define QCA955X_BOOTSTRAP_REF_CLK_40   BIT(4)
 399
 400  #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
 401 @@ -565,6 +611,8 @@
 402  #define REV_ID_MAJOR_AR9341            0x0120
 403  #define REV_ID_MAJOR_AR9342            0x1120
 404  #define REV_ID_MAJOR_AR9344            0x2120
 405 +#define REV_ID_MAJOR_QCA9533           0x0140
 406 +#define REV_ID_MAJOR_QCA9533_V2                0x0160
 407  #define REV_ID_MAJOR_QCA9556           0x0130
 408  #define REV_ID_MAJOR_QCA9558           0x1130
 409
 410 @@ -587,6 +635,8 @@
 411
 412  #define AR934X_REV_ID_REVISION_MASK    0xf
 413
 414 +#define QCA953X_REV_ID_REVISION_MASK   0xf
 415 +
 416  #define QCA955X_REV_ID_REVISION_MASK   0xf
 417
 418  /*
 419 @@ -640,6 +690,7 @@
 420  #define AR913X_GPIO_COUNT              22
 421  #define AR933X_GPIO_COUNT              30
 422  #define AR934X_GPIO_COUNT              23
 423 +#define QCA953X_GPIO_COUNT             24
 424  #define QCA955X_GPIO_COUNT             24
 425
 426  /*
 427 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 428 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 429 @@ -32,6 +32,7 @@ enum ath79_soc_type {
 430         ATH79_SOC_AR9341,
 431         ATH79_SOC_AR9342,
 432         ATH79_SOC_AR9344,
 433 +       ATH79_SOC_QCA9533,
 434         ATH79_SOC_QCA9556,
 435         ATH79_SOC_QCA9558,
 436  };
 437 @@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
 438         return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
 439  }
 440
 441 +static inline int soc_is_qca9533(void)
 442 +{
 443 +       return ath79_soc == ATH79_SOC_QCA9533;
 444 +}
 445 +
 446 +static inline int soc_is_qca953x(void)
 447 +{
 448 +       return soc_is_qca9533();
 449 +}
 450 +
 451  static inline int soc_is_qca9556(void)
 452  {
 453         return ath79_soc == ATH79_SOC_QCA9556;