target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c

   1 /*
   2  *  NAND flash driver for the MikroTik RouterBOARD 91x series
   3  *
   4  *  Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/spinlock.h>
  13 #include <linux/module.h>
  14 #include <linux/mtd/nand.h>
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/partitions.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/io.h>
  19 #include <linux/slab.h>
  20
  21 #include <asm/mach-ath79/ar71xx_regs.h>
  22 #include <asm/mach-ath79/ath79.h>
  23
  24 #define DRV_NAME        "rb91x-nand"
  25 #define DRV_DESC        "NAND flash driver for the RouterBOARD 91x series"
  26
  27 #define RB91X_NAND_NRE_ENABLE   BIT(3)
  28 #define RB91X_NAND_RDY          BIT(4)
  29 #define RB91X_LATCH_ENABLE      BIT(11)
  30 #define RB91X_NAND_NRWE         BIT(12)
  31 #define RB91X_NAND_NCE          BIT(13)
  32 #define RB91X_NAND_CLE          BIT(14)
  33 #define RB91X_NAND_ALE          BIT(15)
  34
  35 #define RB91X_NAND_DATA_BITS    (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\
  36                                  BIT(13) | BIT(14) | BIT(15))
  37
  38 #define RB91X_NAND_INPUT_BITS   (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY)
  39 #define RB91X_NAND_OUTPUT_BITS  \
  40         (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE)
  41
  42 #define RB91X_NAND_LOW_DATA_MASK        0x1f
  43 #define RB91X_NAND_HIGH_DATA_MASK       0xe0
  44 #define RB91X_NAND_HIGH_DATA_SHIFT      8
  45
  46 struct rb91x_nand_info {
  47         struct nand_chip        chip;
  48         struct mtd_info         mtd;
  49 };
  50
  51 static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
  52 {
  53         return container_of(mtd, struct rb91x_nand_info, mtd);
  54 }
  55
  56 /*
  57  * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
  58  * will not be able to find the kernel that we load.
  59  */
  60 static struct nand_ecclayout rb91x_nand_ecclayout = {
  61         .eccbytes       = 6,
  62         .eccpos         = { 8, 9, 10, 13, 14, 15 },
  63         .oobavail       = 9,
  64         .oobfree        = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
  65 };
  66
  67 static struct mtd_partition rb91x_nand_partitions[] = {
  68         {
  69                 .name   = "booter",
  70                 .offset = 0,
  71                 .size   = (256 * 1024),
  72                 .mask_flags = MTD_WRITEABLE,
  73         }, {
  74                 .name   = "kernel",
  75                 .offset = (256 * 1024),
  76                 .size   = (4 * 1024 * 1024) - (256 * 1024),
  77         }, {
  78                 .name   = "rootfs",
  79                 .offset = MTDPART_OFS_NXTBLK,
  80                 .size   = MTDPART_SIZ_FULL,
  81         },
  82 };
  83
  84 static void rb91x_change_gpo(u32 clear, u32 set)
  85 {
  86         void __iomem *base = ath79_gpio_base;
  87         static unsigned on = 0xE002800;
  88         static unsigned off = 0x0000C008;
  89         static unsigned oe = 0;
  90         static DEFINE_SPINLOCK(lock);
  91         unsigned long flags;
  92
  93         spin_lock_irqsave(&lock, flags);
  94
  95         on = (on | set) & ~clear;
  96         off = (off | clear) & ~set;
  97
  98         if (!oe)
  99                 oe = __raw_readl(base + AR71XX_GPIO_REG_OE);
 100
 101         if (on & RB91X_LATCH_ENABLE) {
 102                 u32 t;
 103
 104                 t = oe & __raw_readl(base + AR71XX_GPIO_REG_OE);
 105                 t &= ~(on | off);
 106                 __raw_writel(t, base + AR71XX_GPIO_REG_OE);
 107                 __raw_writel(off, base + AR71XX_GPIO_REG_CLEAR);
 108                 __raw_writel(on, base + AR71XX_GPIO_REG_SET);
 109         } else if (clear & RB91X_LATCH_ENABLE) {
 110                 oe = __raw_readl(base + AR71XX_GPIO_REG_OE);
 111                 __raw_writel(RB91X_LATCH_ENABLE,
 112                              base + AR71XX_GPIO_REG_CLEAR);
 113                 /* flush write */
 114                 __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
 115         }
 116
 117         spin_unlock_irqrestore(&lock, flags);
 118 }
 119
 120 static inline void rb91x_latch_enable(void)
 121 {
 122         rb91x_change_gpo(RB91X_LATCH_ENABLE, 0);
 123 }
 124
 125 static inline void rb91x_latch_disable(void)
 126 {
 127         rb91x_change_gpo(0, RB91X_LATCH_ENABLE);
 128 }
 129
 130 static void rb91x_nand_write(const u8 *buf, unsigned len)
 131 {
 132         void __iomem *base = ath79_gpio_base;
 133         u32 oe_reg;
 134         u32 out_reg;
 135         u32 out;
 136         unsigned i;
 137
 138         rb91x_latch_enable();
 139
 140         oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
 141         out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
 142
 143         /* set data lines to output mode */
 144         __raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE),
 145                      base + AR71XX_GPIO_REG_OE);
 146
 147         out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE);
 148         for (i = 0; i != len; i++) {
 149                 u32 data;
 150
 151                 data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
 152                         RB91X_NAND_HIGH_DATA_SHIFT;
 153                 data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
 154                 data |= out;
 155                 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
 156
 157                 /* deactivate WE line */
 158                 data |= RB91X_NAND_NRWE;
 159                 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
 160                 /* flush write */
 161                 __raw_readl(base + AR71XX_GPIO_REG_OUT);
 162         }
 163
 164         /* restore  registers */
 165         __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
 166         __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
 167         /* flush write */
 168         __raw_readl(base + AR71XX_GPIO_REG_OUT);
 169
 170         rb91x_latch_disable();
 171 }
 172
 173 static void rb91x_nand_read(u8 *read_buf, unsigned len)
 174 {
 175         void __iomem *base = ath79_gpio_base;
 176         u32 oe_reg;
 177         u32 out_reg;
 178         unsigned i;
 179
 180         /* save registers */
 181         oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
 182
 183         /* select nRE mode */
 184         rb91x_change_gpo(0, RB91X_NAND_NRE_ENABLE);
 185
 186         /* enable latch */
 187         rb91x_latch_enable();
 188
 189         out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
 190
 191         /* set data lines to input mode */
 192         __raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
 193                      base + AR71XX_GPIO_REG_OE);
 194
 195         for (i = 0; i < len; i++) {
 196                 u32 in;
 197                 u8 data;
 198
 199                 /* activate RE line */
 200                 __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_CLEAR);
 201                 /* flush write */
 202                 __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
 203
 204                 /* read input lines */
 205                 in = __raw_readl(base + AR71XX_GPIO_REG_IN);
 206
 207                 /* deactivate RE line */
 208                 __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_SET);
 209
 210                 data = (in & RB91X_NAND_LOW_DATA_MASK);
 211                 data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
 212                         RB91X_NAND_HIGH_DATA_MASK;
 213
 214                 read_buf[i] = data;
 215         }
 216
 217         /* restore  registers */
 218         __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
 219         __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
 220         /* flush write */
 221         __raw_readl(base + AR71XX_GPIO_REG_OUT);
 222
 223         /* disable latch */
 224         rb91x_latch_disable();
 225
 226         /* deselect nRE mode */
 227         rb91x_change_gpo(RB91X_NAND_NRE_ENABLE, 0);
 228 }
 229
 230 static int rb91x_nand_dev_ready(struct mtd_info *mtd)
 231 {
 232         void __iomem *base = ath79_gpio_base;
 233
 234         return !!(__raw_readl(base + AR71XX_GPIO_REG_IN) & RB91X_NAND_RDY);
 235 }
 236
 237 static void rb91x_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 238                                 unsigned int ctrl)
 239 {
 240         if (ctrl & NAND_CTRL_CHANGE) {
 241                 u32 on = 0;
 242                 u32 off;
 243
 244                 if (!(ctrl & NAND_NCE))
 245                         on |= RB91X_NAND_NCE;
 246
 247                 if (ctrl & NAND_CLE)
 248                         on |= RB91X_NAND_CLE;
 249
 250                 if (ctrl & NAND_ALE)
 251                         on |= RB91X_NAND_ALE;
 252
 253                 off = on ^ (RB91X_NAND_ALE | RB91X_NAND_NCE | RB91X_NAND_CLE);
 254                 rb91x_change_gpo(off, on);
 255         }
 256
 257         if (cmd != NAND_CMD_NONE) {
 258                 u8 t = cmd;
 259
 260                 rb91x_nand_write(&t, 1);
 261         }
 262 }
 263
 264 static u8 rb91x_nand_read_byte(struct mtd_info *mtd)
 265 {
 266         u8 data = 0xff;
 267
 268         rb91x_nand_read(&data, 1);
 269
 270         return data;
 271 }
 272
 273 static void rb91x_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 274 {
 275         rb91x_nand_read(buf, len);
 276 }
 277
 278 static void rb91x_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 279 {
 280         rb91x_nand_write(buf, len);
 281 }
 282
 283 static int rb91x_nand_probe(struct platform_device *pdev)
 284 {
 285         struct rb91x_nand_info  *info;
 286         int ret;
 287
 288         pr_info(DRV_DESC "\n");
 289
 290         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
 291         if (!info)
 292                 return -ENOMEM;
 293
 294         info->chip.priv = &info;
 295         info->mtd.priv  = &info->chip;
 296         info->mtd.owner = THIS_MODULE;
 297
 298         info->chip.cmd_ctrl     = rb91x_nand_cmd_ctrl;
 299         info->chip.dev_ready    = rb91x_nand_dev_ready;
 300         info->chip.read_byte    = rb91x_nand_read_byte;
 301         info->chip.write_buf    = rb91x_nand_write_buf;
 302         info->chip.read_buf     = rb91x_nand_read_buf;
 303
 304         info->chip.chip_delay   = 25;
 305         info->chip.ecc.mode     = NAND_ECC_SOFT;
 306
 307         platform_set_drvdata(pdev, info);
 308
 309         ret = nand_scan_ident(&info->mtd, 1, NULL);
 310         if (ret)
 311                 return ret;
 312
 313         if (info->mtd.writesize == 512)
 314                 info->chip.ecc.layout = &rb91x_nand_ecclayout;
 315
 316         ret = nand_scan_tail(&info->mtd);
 317         if (ret)
 318                 return ret;
 319
 320         ret = mtd_device_register(&info->mtd, rb91x_nand_partitions,
 321                                  ARRAY_SIZE(rb91x_nand_partitions));
 322         if (ret)
 323                 goto err_release_nand;
 324
 325         return 0;
 326
 327 err_release_nand:
 328         nand_release(&info->mtd);
 329         return ret;
 330 }
 331
 332 static int rb91x_nand_remove(struct platform_device *pdev)
 333 {
 334         struct rb91x_nand_info *info = platform_get_drvdata(pdev);
 335
 336         nand_release(&info->mtd);
 337
 338         return 0;
 339 }
 340
 341 static struct platform_driver rb91x_nand_driver = {
 342         .probe  = rb91x_nand_probe,
 343         .remove = rb91x_nand_remove,
 344         .driver = {
 345                 .name   = DRV_NAME,
 346                 .owner  = THIS_MODULE,
 347         },
 348 };
 349
 350 module_platform_driver(rb91x_nand_driver);
 351
 352 MODULE_DESCRIPTION(DRV_DESC);
 353 MODULE_VERSION(DRV_VERSION);
 354 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 355 MODULE_LICENSE("GPL v2");