target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c

   1 /*
   2  * TP-LINK TL-WR1043ND v2 board support
   3  *
   4  * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * Based on the Qualcomm Atheros AP135/AP136 reference board support code
   7  *   Copyright (c) 2012 Qualcomm Atheros
   8  *
   9  * Permission to use, copy, modify, and/or distribute this software for any
  10  * purpose with or without fee is hereby granted, provided that the above
  11  * copyright notice and this permission notice appear in all copies.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  16  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  18  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  19  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  20  *
  21  */
  22
  23 #include <linux/phy.h>
  24 #include <linux/gpio.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/ar8216_platform.h>
  27
  28 #include <asm/mach-ath79/ar71xx_regs.h>
  29
  30 #include "common.h"
  31 #include "dev-eth.h"
  32 #include "dev-gpio-buttons.h"
  33 #include "dev-leds-gpio.h"
  34 #include "dev-m25p80.h"
  35 #include "dev-spi.h"
  36 #include "dev-usb.h"
  37 #include "dev-wmac.h"
  38 #include "machtypes.h"
  39
  40 #define TL_WR1043_V2_GPIO_LED_WLAN      12
  41 #define TL_WR1043_V2_GPIO_LED_USB       15
  42 #define TL_WR1043_V2_GPIO_LED_WPS       18
  43 #define TL_WR1043_V2_GPIO_LED_SYSTEM    19
  44
  45 #define TL_WR1043_V2_GPIO_BTN_RESET     16
  46 #define TL_WR1043_V2_GPIO_BTN_WLAN      17
  47
  48 #define TL_WR1043_V2_GPIO_USB_POWER     21
  49
  50 #define TL_WR1043_V2_KEYS_POLL_INTERVAL 20      /* msecs */
  51 #define TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043_V2_KEYS_POLL_INTERVAL)
  52
  53 #define TL_WR1043_V2_WMAC_CALDATA_OFFSET        0x1000
  54
  55 static const char *wr1043nd_v2_part_probes[] = {
  56         "tp-link",
  57         NULL,
  58 };
  59
  60 static struct flash_platform_data wr1043nd_v2_flash_data = {
  61         .part_probes    = wr1043nd_v2_part_probes,
  62 };
  63
  64 static struct gpio_led tl_wr1043_v2_leds_gpio[] __initdata = {
  65         {
  66                 .name           = "tp-link:green:wps",
  67                 .gpio           = TL_WR1043_V2_GPIO_LED_WPS,
  68                 .active_low     = 1,
  69         },
  70         {
  71                 .name           = "tp-link:green:system",
  72                 .gpio           = TL_WR1043_V2_GPIO_LED_SYSTEM,
  73                 .active_low     = 1,
  74         },
  75         {
  76                 .name           = "tp-link:green:wlan",
  77                 .gpio           = TL_WR1043_V2_GPIO_LED_WLAN,
  78                 .active_low     = 1,
  79         },
  80         {
  81                 .name           = "tp-link:green:usb",
  82                 .gpio           = TL_WR1043_V2_GPIO_LED_USB,
  83                 .active_low     = 1,
  84         },
  85 };
  86
  87 static struct gpio_keys_button tl_wr1043_v2_gpio_keys[] __initdata = {
  88         {
  89                 .desc           = "Reset button",
  90                 .type           = EV_KEY,
  91                 .code           = KEY_RESTART,
  92                 .debounce_interval = TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL,
  93                 .gpio           = TL_WR1043_V2_GPIO_BTN_RESET,
  94                 .active_low     = 1,
  95         },
  96         {
  97                 .desc           = "WLAN button",
  98                 .type           = EV_KEY,
  99                 .code           = KEY_WLAN,
 100                 .debounce_interval = TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL,
 101                 .gpio           = TL_WR1043_V2_GPIO_BTN_WLAN,
 102                 .active_low     = 1,
 103         },
 104 };
 105
 106 /* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */
 107 static struct ar8327_pad_cfg wr1043nd_v2_ar8327_pad0_cfg = {
 108         .mode = AR8327_PAD_MAC_SGMII,
 109         .sgmii_delay_en = true,
 110 };
 111
 112 /* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */
 113 static struct ar8327_pad_cfg wr1043nd_v2_ar8327_pad6_cfg = {
 114         .mode = AR8327_PAD_MAC_RGMII,
 115         .txclk_delay_en = true,
 116         .rxclk_delay_en = true,
 117         .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
 118         .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
 119 };
 120
 121 static struct ar8327_led_cfg wr1043nd_v2_ar8327_led_cfg = {
 122         .led_ctrl0 = 0xcc35cc35,
 123         .led_ctrl1 = 0xca35ca35,
 124         .led_ctrl2 = 0xc935c935,
 125         .led_ctrl3 = 0x03ffff00,
 126         .open_drain = true,
 127 };
 128
 129 static struct ar8327_platform_data wr1043nd_v2_ar8327_data = {
 130         .pad0_cfg = &wr1043nd_v2_ar8327_pad0_cfg,
 131         .pad6_cfg = &wr1043nd_v2_ar8327_pad6_cfg,
 132         .port0_cfg = {
 133                 .force_link = 1,
 134                 .speed = AR8327_PORT_SPEED_1000,
 135                 .duplex = 1,
 136                 .txpause = 1,
 137                 .rxpause = 1,
 138         },
 139         .port6_cfg = {
 140                 .force_link = 1,
 141                 .speed = AR8327_PORT_SPEED_1000,
 142                 .duplex = 1,
 143                 .txpause = 1,
 144                 .rxpause = 1,
 145         },
 146         .led_cfg = &wr1043nd_v2_ar8327_led_cfg,
 147 };
 148
 149 static struct mdio_board_info wr1043nd_v2_mdio0_info[] = {
 150         {
 151                 .bus_id = "ag71xx-mdio.0",
 152                 .phy_addr = 0,
 153                 .platform_data = &wr1043nd_v2_ar8327_data,
 154         },
 155 };
 156
 157 static void __init wr1043nd_v2_gmac_setup(void)
 158 {
 159         void __iomem *base;
 160         u32 t;
 161
 162         base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
 163
 164         t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
 165
 166         t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
 167         t |= QCA955X_ETH_CFG_RGMII_EN;
 168
 169         __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
 170
 171         iounmap(base);
 172 }
 173
 174 static void __init tl_wr1043nd_v2_setup(void)
 175 {
 176         u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
 177         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 178         u8 tmpmac[ETH_ALEN];
 179
 180         ath79_register_m25p80(&wr1043nd_v2_flash_data);
 181
 182         ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043_v2_leds_gpio),
 183                                  tl_wr1043_v2_leds_gpio);
 184         ath79_register_gpio_keys_polled(-1, TL_WR1043_V2_KEYS_POLL_INTERVAL,
 185                                         ARRAY_SIZE(tl_wr1043_v2_gpio_keys),
 186                                         tl_wr1043_v2_gpio_keys);
 187
 188         ath79_init_mac(tmpmac, mac, -1);
 189         ath79_register_wmac(art + TL_WR1043_V2_WMAC_CALDATA_OFFSET, tmpmac);
 190
 191         mdiobus_register_board_info(wr1043nd_v2_mdio0_info,
 192                                     ARRAY_SIZE(wr1043nd_v2_mdio0_info));
 193         ath79_register_mdio(0, 0x0);
 194
 195         wr1043nd_v2_gmac_setup();
 196
 197         /* GMAC0 is connected to the RMGII interface */
 198         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 199         ath79_eth0_data.phy_mask = BIT(0);
 200         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 201         ath79_eth0_pll_data.pll_1000 = 0x56000000;
 202
 203         ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
 204         ath79_register_eth(0);
 205
 206         /* GMAC1 is connected to the SGMII interface */
 207         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
 208         ath79_eth1_data.speed = SPEED_1000;
 209         ath79_eth1_data.duplex = DUPLEX_FULL;
 210         ath79_eth1_pll_data.pll_1000 = 0x03000101;
 211
 212         ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
 213         ath79_register_eth(1);
 214
 215         ath79_register_usb();
 216
 217         gpio_request_one(TL_WR1043_V2_GPIO_USB_POWER,
 218                          GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
 219                          "USB power");
 220 }
 221
 222 MIPS_MACHINE(ATH79_MACH_TL_WR1043ND_V2, "TL-WR1043ND-v2",
 223              "TP-LINK TL-WR1043ND v2", tl_wr1043nd_v2_setup);
 224