ar71xx: Clear bits in ath79_setup_qca955x_eth_cfg
[openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-mr1750.c
1 /*
2  * MR1750 board support
3  *
4  * Copyright (c) 2012 Qualcomm Atheros
5  * Copyright (c) 2012-2013 Marek Lindner <marek@open-mesh.com>
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/ar8216_platform.h>
23
24 #include <asm/mach-ath79/ar71xx_regs.h>
25
26 #include "common.h"
27 #include "dev-ap9x-pci.h"
28 #include "dev-gpio-buttons.h"
29 #include "dev-eth.h"
30 #include "dev-leds-gpio.h"
31 #include "dev-m25p80.h"
32 #include "dev-wmac.h"
33 #include "machtypes.h"
34 #include "pci.h"
35
36 #define MR1750_GPIO_LED_LAN             12
37 #define MR1750_GPIO_LED_WLAN_2G         13
38 #define MR1750_GPIO_LED_STATUS_GREEN    19
39 #define MR1750_GPIO_LED_STATUS_RED      21
40 #define MR1750_GPIO_LED_POWER           22
41 #define MR1750_GPIO_LED_WLAN_5G         23
42
43 #define MR1750_GPIO_BTN_RESET           17
44
45 #define MR1750_KEYS_POLL_INTERVAL       20      /* msecs */
46 #define MR1750_KEYS_DEBOUNCE_INTERVAL   (3 * MR1750_KEYS_POLL_INTERVAL)
47
48 #define MR1750_MAC0_OFFSET              0
49 #define MR1750_WMAC_CALDATA_OFFSET      0x1000
50
51 static struct gpio_led mr1750_leds_gpio[] __initdata = {
52         {
53                 .name           = "mr1750:blue:power",
54                 .gpio           = MR1750_GPIO_LED_POWER,
55                 .active_low     = 1,
56         },
57         {
58                 .name           = "mr1750:blue:wan",
59                 .gpio           = MR1750_GPIO_LED_LAN,
60                 .active_low     = 1,
61         },
62         {
63                 .name           = "mr1750:blue:wlan24",
64                 .gpio           = MR1750_GPIO_LED_WLAN_2G,
65                 .active_low     = 1,
66         },
67         {
68                 .name           = "mr1750:blue:wlan58",
69                 .gpio           = MR1750_GPIO_LED_WLAN_5G,
70                 .active_low     = 1,
71         },
72         {
73                 .name           = "mr1750:green:status",
74                 .gpio           = MR1750_GPIO_LED_STATUS_GREEN,
75                 .active_low     = 1,
76         },
77         {
78                 .name           = "mr1750:red:status",
79                 .gpio           = MR1750_GPIO_LED_STATUS_RED,
80                 .active_low     = 1,
81         },
82 };
83
84 static struct gpio_keys_button mr1750_gpio_keys[] __initdata = {
85         {
86                 .desc           = "Reset button",
87                 .type           = EV_KEY,
88                 .code           = KEY_RESTART,
89                 .debounce_interval = MR1750_KEYS_DEBOUNCE_INTERVAL,
90                 .gpio           = MR1750_GPIO_BTN_RESET,
91                 .active_low     = 1,
92         },
93 };
94
95 static void __init mr1750_setup(void)
96 {
97         u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
98         u8 mac[6];
99
100         ath79_eth0_pll_data.pll_1000 = 0xbe000101;
101         ath79_eth0_pll_data.pll_100 = 0x80000101;
102         ath79_eth0_pll_data.pll_10 = 0x80001313;
103
104         ath79_register_m25p80(NULL);
105
106         ath79_register_leds_gpio(-1, ARRAY_SIZE(mr1750_leds_gpio),
107                                  mr1750_leds_gpio);
108         ath79_register_gpio_keys_polled(-1, MR1750_KEYS_POLL_INTERVAL,
109                                         ARRAY_SIZE(mr1750_gpio_keys),
110                                         mr1750_gpio_keys);
111
112         ath79_init_mac(mac, art + MR1750_MAC0_OFFSET, 1);
113         ath79_register_wmac(art + MR1750_WMAC_CALDATA_OFFSET, mac);
114         ath79_register_pci();
115
116         ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
117         ath79_register_mdio(0, 0x0);
118
119         ath79_init_mac(ath79_eth0_data.mac_addr, art + MR1750_MAC0_OFFSET, 0);
120
121         /* GMAC0 is connected to the RMGII interface */
122         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
123         ath79_eth0_data.phy_mask = BIT(5);
124         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
125
126         ath79_register_eth(0);
127 }
128
129 MIPS_MACHINE(ATH79_MACH_MR1750, "MR1750", "OpenMesh MR1750", mr1750_setup);