target/linux/ar71xx/files/arch/mips/ath79/mach-cr5000.c

   1 /*
   2  * PowerCloud CR5000 support
   3  *
   4  * Copyright (c) 2011 Qualcomm Atheros
   5  * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  * Copyright (c) 2012-2013 PowerCloud Systems
   7  * Copyright (c) 2015 Daniel Dickinson <openwrt@daniel.thecshore.com>
   8  *
   9  * Permission to use, copy, modify, and/or distribute this software for any
  10  * purpose with or without fee is hereby granted, provided that the above
  11  * copyright notice and this permission notice appear in all copies.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  16  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  18  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  19  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  20  *
  21  */
  22
  23 #include <linux/gpio.h>
  24 #include <linux/pci.h>
  25 #include <linux/phy.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/ath9k_platform.h>
  28 #include <linux/ar8216_platform.h>
  29
  30 #include <asm/mach-ath79/ar71xx_regs.h>
  31 #include <asm/mach-ath79/ath79.h>
  32
  33 #include "common.h"
  34 #include "dev-ap9x-pci.h"
  35 #include "dev-eth.h"
  36 #include "dev-gpio-buttons.h"
  37 #include "dev-leds-gpio.h"
  38 #include "dev-m25p80.h"
  39 #include "dev-spi.h"
  40 #include "dev-usb.h"
  41 #include "dev-wmac.h"
  42 #include "machtypes.h"
  43
  44 #define CR5000_GPIO_LED_WLAN_2G         14
  45 #define CR5000_GPIO_LED_WPS             12
  46 #define CR5000_GPIO_LED_POWER_AMBER      4
  47 /* GPIO2 has to have JTAG disabled as it is also to
  48  * power led
  49  */
  50 #define CR5000_GPIO_LED_POWER_ENABLE     2
  51 #define CR5000_GPIO_BTN_WPS             16
  52 #define CR5000_GPIO_BTN_RESET           17
  53
  54 #define CR5000_KEYS_POLL_INTERVAL       20      /* msecs */
  55 #define CR5000_KEYS_DEBOUNCE_INTERVAL   (3 * CR5000_KEYS_POLL_INTERVAL)
  56
  57 #define CR5000_MAC0_OFFSET              0
  58 #define CR5000_WMAC_CALDATA_OFFSET      0x1000
  59 #define CR5000_WMAC_MAC_OFFSET          0x1002
  60 #define CR5000_PCIE_CALDATA_OFFSET      0x5000
  61 #define CR5000_PCIE_MAC_OFFSET          0x5002
  62
  63 static struct gpio_led cr5000_leds_gpio[] __initdata = {
  64         {
  65                 .name           = "pcs:amber:power",
  66                 .gpio           = CR5000_GPIO_LED_POWER_AMBER,
  67                 .active_low     = 1,
  68         },
  69         {
  70                 .name           = "pcs:white:wps",
  71                 .gpio           = CR5000_GPIO_LED_WPS,
  72                 .active_low     = 1,
  73         },
  74         {
  75                 .name           = "pcs:blue:wlan",
  76                 .gpio           = CR5000_GPIO_LED_WLAN_2G,
  77                 .active_low     = 1,
  78         },
  79 };
  80
  81 static struct gpio_keys_button cr5000_gpio_keys[] __initdata = {
  82         {
  83                 .desc           = "WPS button",
  84                 .type           = EV_KEY,
  85                 .code           = KEY_WPS_BUTTON,
  86                 .debounce_interval = CR5000_KEYS_DEBOUNCE_INTERVAL,
  87                 .gpio           = CR5000_GPIO_BTN_WPS,
  88                 .active_low     = 1,
  89         },
  90         {
  91                 .desc           = "Reset button",
  92                 .type           = EV_KEY,
  93                 .code           = KEY_WPS_BUTTON,
  94                 .debounce_interval = CR5000_KEYS_DEBOUNCE_INTERVAL,
  95                 .gpio           = CR5000_GPIO_BTN_RESET,
  96                 .active_low     = 1,
  97         },
  98 };
  99
 100 static struct ar8327_pad_cfg cr5000_ar8327_pad0_cfg = {
 101         .mode = AR8327_PAD_MAC_RGMII,
 102         .txclk_delay_en = true,
 103         .rxclk_delay_en = true,
 104         .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
 105         .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
 106 };
 107
 108 static struct ar8327_led_cfg cr5000_ar8327_led_cfg = {
 109         .led_ctrl0 = 0x00000000,
 110         .led_ctrl1 = 0xc737c737,
 111         .led_ctrl2 = 0x00000000,
 112         .led_ctrl3 = 0x00c30c00,
 113         .open_drain = true,
 114 };
 115
 116 static struct ar8327_platform_data cr5000_ar8327_data = {
 117         .pad0_cfg = &cr5000_ar8327_pad0_cfg,
 118         .port0_cfg = {
 119                 .force_link = 1,
 120                 .speed = AR8327_PORT_SPEED_1000,
 121                 .duplex = 1,
 122                 .txpause = 1,
 123                 .rxpause = 1,
 124         },
 125         .led_cfg = &cr5000_ar8327_led_cfg,
 126 };
 127
 128 static struct mdio_board_info cr5000_mdio0_info[] = {
 129         {
 130                 .bus_id = "ag71xx-mdio.0",
 131                 .phy_addr = 0,
 132                 .platform_data = &cr5000_ar8327_data,
 133         },
 134 };
 135
 136 static void __init cr5000_setup(void)
 137 {
 138         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 139
 140         ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
 141         gpio_request_one(CR5000_GPIO_LED_POWER_ENABLE,
 142         GPIOF_OUT_INIT_LOW, "Power LED enable");
 143         ath79_gpio_output_select(CR5000_GPIO_LED_POWER_AMBER, AR934X_GPIO_OUT_GPIO);
 144         ath79_gpio_output_select(CR5000_GPIO_LED_WLAN_2G, AR934X_GPIO_OUT_GPIO);
 145         ath79_gpio_output_select(CR5000_GPIO_LED_WPS, AR934X_GPIO_OUT_GPIO);
 146
 147         ath79_register_m25p80(NULL);
 148
 149         ath79_register_leds_gpio(-1, ARRAY_SIZE(cr5000_leds_gpio),
 150                                  cr5000_leds_gpio);
 151         ath79_register_gpio_keys_polled(-1, CR5000_KEYS_POLL_INTERVAL,
 152                                         ARRAY_SIZE(cr5000_gpio_keys),
 153                                         cr5000_gpio_keys);
 154         ath79_register_usb();
 155         ath79_register_wmac(art + CR5000_WMAC_CALDATA_OFFSET, art + CR5000_WMAC_MAC_OFFSET);
 156         ap94_pci_init(NULL, NULL, NULL, art + CR5000_PCIE_MAC_OFFSET);
 157
 158         ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
 159
 160         ath79_register_mdio(0, 0x0);
 161
 162         ath79_init_mac(ath79_eth0_data.mac_addr, art + CR5000_MAC0_OFFSET, 0);
 163
 164         mdiobus_register_board_info(cr5000_mdio0_info,
 165                                     ARRAY_SIZE(cr5000_mdio0_info));
 166
 167         /* GMAC0 is connected to an AR8327 switch */
 168         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 169         ath79_eth0_data.phy_mask = BIT(0);
 170         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 171         ath79_eth0_pll_data.pll_1000 = 0x06000000;
 172         ath79_register_eth(0);
 173 }
 174
 175 MIPS_MACHINE(ATH79_MACH_CR5000, "CR5000", "PowerCloud CR5000",
 176              cr5000_setup);