target/linux/adm5120/patches-3.7/200-amba_pl010_hacks.patch

   1 --- a/drivers/tty/serial/amba-pl010.c
   2 +++ b/drivers/tty/serial/amba-pl010.c
   3 @@ -49,11 +49,9 @@
   4
   5  #include <asm/io.h>
   6
   7 -#define UART_NR                8
   8 -
   9  #define SERIAL_AMBA_MAJOR      204
  10  #define SERIAL_AMBA_MINOR      16
  11 -#define SERIAL_AMBA_NR         UART_NR
  12 +#define SERIAL_AMBA_NR         CONFIG_SERIAL_AMBA_PL010_NUMPORTS
  13
  14  #define AMBA_ISR_PASS_LIMIT    256
  15
  16 @@ -79,9 +77,9 @@ static void pl010_stop_tx(struct uart_po
  17         struct uart_amba_port *uap = (struct uart_amba_port *)port;
  18         unsigned int cr;
  19
  20 -       cr = readb(uap->port.membase + UART010_CR);
  21 +       cr = __raw_readl(uap->port.membase + UART010_CR);
  22         cr &= ~UART010_CR_TIE;
  23 -       writel(cr, uap->port.membase + UART010_CR);
  24 +       __raw_writel(cr, uap->port.membase + UART010_CR);
  25  }
  26
  27  static void pl010_start_tx(struct uart_port *port)
  28 @@ -89,9 +87,9 @@ static void pl010_start_tx(struct uart_p
  29         struct uart_amba_port *uap = (struct uart_amba_port *)port;
  30         unsigned int cr;
  31
  32 -       cr = readb(uap->port.membase + UART010_CR);
  33 +       cr = __raw_readl(uap->port.membase + UART010_CR);
  34         cr |= UART010_CR_TIE;
  35 -       writel(cr, uap->port.membase + UART010_CR);
  36 +       __raw_writel(cr, uap->port.membase + UART010_CR);
  37  }
  38
  39  static void pl010_stop_rx(struct uart_port *port)
  40 @@ -99,9 +97,9 @@ static void pl010_stop_rx(struct uart_po
  41         struct uart_amba_port *uap = (struct uart_amba_port *)port;
  42         unsigned int cr;
  43
  44 -       cr = readb(uap->port.membase + UART010_CR);
  45 +       cr = __raw_readl(uap->port.membase + UART010_CR);
  46         cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
  47 -       writel(cr, uap->port.membase + UART010_CR);
  48 +       __raw_writel(cr, uap->port.membase + UART010_CR);
  49  }
  50
  51  static void pl010_enable_ms(struct uart_port *port)
  52 @@ -109,9 +107,9 @@ static void pl010_enable_ms(struct uart_
  53         struct uart_amba_port *uap = (struct uart_amba_port *)port;
  54         unsigned int cr;
  55
  56 -       cr = readb(uap->port.membase + UART010_CR);
  57 +       cr = __raw_readl(uap->port.membase + UART010_CR);
  58         cr |= UART010_CR_MSIE;
  59 -       writel(cr, uap->port.membase + UART010_CR);
  60 +       __raw_writel(cr, uap->port.membase + UART010_CR);
  61  }
  62
  63  static void pl010_rx_chars(struct uart_amba_port *uap)
  64 @@ -119,9 +117,9 @@ static void pl010_rx_chars(struct uart_a
  65         struct tty_struct *tty = uap->port.state->port.tty;
  66         unsigned int status, ch, flag, rsr, max_count = 256;
  67
  68 -       status = readb(uap->port.membase + UART01x_FR);
  69 +       status = __raw_readl(uap->port.membase + UART01x_FR);
  70         while (UART_RX_DATA(status) && max_count--) {
  71 -               ch = readb(uap->port.membase + UART01x_DR);
  72 +               ch = __raw_readl(uap->port.membase + UART01x_DR);
  73                 flag = TTY_NORMAL;
  74
  75                 uap->port.icount.rx++;
  76 @@ -130,9 +128,9 @@ static void pl010_rx_chars(struct uart_a
  77                  * Note that the error handling code is
  78                  * out of the main execution path
  79                  */
  80 -               rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
  81 +               rsr = __raw_readl(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
  82                 if (unlikely(rsr & UART01x_RSR_ANY)) {
  83 -                       writel(0, uap->port.membase + UART01x_ECR);
  84 +                       __raw_writel(0, uap->port.membase + UART01x_ECR);
  85
  86                         if (rsr & UART01x_RSR_BE) {
  87                                 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
  88 @@ -162,7 +160,7 @@ static void pl010_rx_chars(struct uart_a
  89                 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
  90
  91         ignore_char:
  92 -               status = readb(uap->port.membase + UART01x_FR);
  93 +               status = __raw_readl(uap->port.membase + UART01x_FR);
  94         }
  95         spin_unlock(&uap->port.lock);
  96         tty_flip_buffer_push(tty);
  97 @@ -175,7 +173,7 @@ static void pl010_tx_chars(struct uart_a
  98         int count;
  99
 100         if (uap->port.x_char) {
 101 -               writel(uap->port.x_char, uap->port.membase + UART01x_DR);
 102 +               __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR);
 103                 uap->port.icount.tx++;
 104                 uap->port.x_char = 0;
 105                 return;
 106 @@ -187,7 +185,7 @@ static void pl010_tx_chars(struct uart_a
 107
 108         count = uap->port.fifosize >> 1;
 109         do {
 110 -               writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
 111 +               __raw_writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
 112                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 113                 uap->port.icount.tx++;
 114                 if (uart_circ_empty(xmit))
 115 @@ -205,9 +203,9 @@ static void pl010_modem_status(struct ua
 116  {
 117         unsigned int status, delta;
 118
 119 -       writel(0, uap->port.membase + UART010_ICR);
 120 +       __raw_writel(0, uap->port.membase + UART010_ICR);
 121
 122 -       status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
 123 +       status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
 124
 125         delta = status ^ uap->old_status;
 126         uap->old_status = status;
 127 @@ -235,7 +233,7 @@ static irqreturn_t pl010_int(int irq, vo
 128
 129         spin_lock(&uap->port.lock);
 130
 131 -       status = readb(uap->port.membase + UART010_IIR);
 132 +       status = __raw_readl(uap->port.membase + UART010_IIR);
 133         if (status) {
 134                 do {
 135                         if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
 136 @@ -248,7 +246,7 @@ static irqreturn_t pl010_int(int irq, vo
 137                         if (pass_counter-- == 0)
 138                                 break;
 139
 140 -                       status = readb(uap->port.membase + UART010_IIR);
 141 +                       status = __raw_readl(uap->port.membase + UART010_IIR);
 142                 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
 143                                    UART010_IIR_TIS));
 144                 handled = 1;
 145 @@ -262,7 +260,7 @@ static irqreturn_t pl010_int(int irq, vo
 146  static unsigned int pl010_tx_empty(struct uart_port *port)
 147  {
 148         struct uart_amba_port *uap = (struct uart_amba_port *)port;
 149 -       unsigned int status = readb(uap->port.membase + UART01x_FR);
 150 +       unsigned int status = __raw_readl(uap->port.membase + UART01x_FR);
 151         return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
 152  }
 153
 154 @@ -272,7 +270,7 @@ static unsigned int pl010_get_mctrl(stru
 155         unsigned int result = 0;
 156         unsigned int status;
 157
 158 -       status = readb(uap->port.membase + UART01x_FR);
 159 +       status = __raw_readl(uap->port.membase + UART01x_FR);
 160         if (status & UART01x_FR_DCD)
 161                 result |= TIOCM_CAR;
 162         if (status & UART01x_FR_DSR)
 163 @@ -298,12 +296,12 @@ static void pl010_break_ctl(struct uart_
 164         unsigned int lcr_h;
 165
 166         spin_lock_irqsave(&uap->port.lock, flags);
 167 -       lcr_h = readb(uap->port.membase + UART010_LCRH);
 168 +       lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
 169         if (break_state == -1)
 170                 lcr_h |= UART01x_LCRH_BRK;
 171         else
 172                 lcr_h &= ~UART01x_LCRH_BRK;
 173 -       writel(lcr_h, uap->port.membase + UART010_LCRH);
 174 +       __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
 175         spin_unlock_irqrestore(&uap->port.lock, flags);
 176  }
 177
 178 @@ -331,12 +329,12 @@ static int pl010_startup(struct uart_por
 179         /*
 180          * initialise the old status of the modem signals
 181          */
 182 -       uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
 183 +       uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
 184
 185         /*
 186          * Finally, enable interrupts
 187          */
 188 -       writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
 189 +       __raw_writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
 190                uap->port.membase + UART010_CR);
 191
 192         return 0;
 193 @@ -359,10 +357,10 @@ static void pl010_shutdown(struct uart_p
 194         /*
 195          * disable all interrupts, disable the port
 196          */
 197 -       writel(0, uap->port.membase + UART010_CR);
 198 +       __raw_writel(0, uap->port.membase + UART010_CR);
 199
 200         /* disable break condition and fifos */
 201 -       writel(readb(uap->port.membase + UART010_LCRH) &
 202 +       __raw_writel(__raw_readl(uap->port.membase + UART010_LCRH) &
 203                 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
 204                uap->port.membase + UART010_LCRH);
 205
 206 @@ -384,7 +382,7 @@ pl010_set_termios(struct uart_port *port
 207         /*
 208          * Ask the core to calculate the divisor for us.
 209          */
 210 -       baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
 211 +       baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
 212         quot = uart_get_divisor(port, baud);
 213
 214         switch (termios->c_cflag & CSIZE) {
 215 @@ -447,25 +445,25 @@ pl010_set_termios(struct uart_port *port
 216                 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
 217
 218         /* first, disable everything */
 219 -       old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
 220 +       old_cr = __raw_readl(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
 221
 222         if (UART_ENABLE_MS(port, termios->c_cflag))
 223                 old_cr |= UART010_CR_MSIE;
 224
 225 -       writel(0, uap->port.membase + UART010_CR);
 226 +       __raw_writel(0, uap->port.membase + UART010_CR);
 227
 228         /* Set baud rate */
 229         quot -= 1;
 230 -       writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
 231 -       writel(quot & 0xff, uap->port.membase + UART010_LCRL);
 232 +       __raw_writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
 233 +       __raw_writel(quot & 0xff, uap->port.membase + UART010_LCRL);
 234
 235         /*
 236          * ----------v----------v----------v----------v-----
 237          * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
 238          * ----------^----------^----------^----------^-----
 239          */
 240 -       writel(lcr_h, uap->port.membase + UART010_LCRH);
 241 -       writel(old_cr, uap->port.membase + UART010_CR);
 242 +       __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
 243 +       __raw_writel(old_cr, uap->port.membase + UART010_CR);
 244
 245         spin_unlock_irqrestore(&uap->port.lock, flags);
 246  }
 247 @@ -547,7 +545,7 @@ static struct uart_ops amba_pl010_pops =
 248         .verify_port    = pl010_verify_port,
 249  };
 250
 251 -static struct uart_amba_port *amba_ports[UART_NR];
 252 +static struct uart_amba_port *amba_ports[SERIAL_AMBA_NR];
 253
 254  #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
 255
 256 @@ -557,10 +555,10 @@ static void pl010_console_putchar(struct
 257         unsigned int status;
 258
 259         do {
 260 -               status = readb(uap->port.membase + UART01x_FR);
 261 +               status = __raw_readl(uap->port.membase + UART01x_FR);
 262                 barrier();
 263         } while (!UART_TX_READY(status));
 264 -       writel(ch, uap->port.membase + UART01x_DR);
 265 +       __raw_writel(ch, uap->port.membase + UART01x_DR);
 266  }
 267
 268  static void
 269 @@ -574,8 +572,8 @@ pl010_console_write(struct console *co,
 270         /*
 271          *      First save the CR then disable the interrupts
 272          */
 273 -       old_cr = readb(uap->port.membase + UART010_CR);
 274 -       writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
 275 +       old_cr = __raw_readl(uap->port.membase + UART010_CR);
 276 +       __raw_writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
 277
 278         uart_console_write(&uap->port, s, count, pl010_console_putchar);
 279
 280 @@ -584,10 +582,10 @@ pl010_console_write(struct console *co,
 281          *      and restore the TCR
 282          */
 283         do {
 284 -               status = readb(uap->port.membase + UART01x_FR);
 285 +               status = __raw_readl(uap->port.membase + UART01x_FR);
 286                 barrier();
 287         } while (status & UART01x_FR_BUSY);
 288 -       writel(old_cr, uap->port.membase + UART010_CR);
 289 +       __raw_writel(old_cr, uap->port.membase + UART010_CR);
 290
 291         clk_disable(uap->clk);
 292  }
 293 @@ -596,9 +594,9 @@ static void __init
 294  pl010_console_get_options(struct uart_amba_port *uap, int *baud,
 295                              int *parity, int *bits)
 296  {
 297 -       if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
 298 +       if (__raw_readl(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
 299                 unsigned int lcr_h, quot;
 300 -               lcr_h = readb(uap->port.membase + UART010_LCRH);
 301 +               lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
 302
 303                 *parity = 'n';
 304                 if (lcr_h & UART01x_LCRH_PEN) {
 305 @@ -613,8 +611,8 @@ pl010_console_get_options(struct uart_am
 306                 else
 307                         *bits = 8;
 308
 309 -               quot = readb(uap->port.membase + UART010_LCRL) |
 310 -                      readb(uap->port.membase + UART010_LCRM) << 8;
 311 +               quot = __raw_readl(uap->port.membase + UART010_LCRL) |
 312 +                      __raw_readl(uap->port.membase + UART010_LCRM) << 8;
 313                 *baud = uap->port.uartclk / (16 * (quot + 1));
 314         }
 315  }
 316 @@ -633,7 +631,7 @@ static int __init pl010_console_setup(st
 317          * if so, search for the first available port that does have
 318          * console support.
 319          */
 320 -       if (co->index >= UART_NR)
 321 +       if (co->index >= SERIAL_AMBA_NR)
 322                 co->index = 0;
 323         uap = amba_ports[co->index];
 324         if (!uap)
 325 @@ -675,7 +673,7 @@ static struct uart_driver amba_reg = {
 326         .dev_name               = "ttyAM",
 327         .major                  = SERIAL_AMBA_MAJOR,
 328         .minor                  = SERIAL_AMBA_MINOR,
 329 -       .nr                     = UART_NR,
 330 +       .nr                     = SERIAL_AMBA_NR,
 331         .cons                   = AMBA_CONSOLE,
 332  };
 333
 334 --- a/drivers/tty/serial/Kconfig
 335 +++ b/drivers/tty/serial/Kconfig
 336 @@ -16,10 +16,18 @@ config SERIAL_AMBA_PL010
 337         help
 338           This selects the ARM(R) AMBA(R) PrimeCell PL010 UART.  If you have
 339           an Integrator/AP or Integrator/PP2 platform, or if you have a
 340 -         Cirrus Logic EP93xx CPU, say Y or M here.
 341 +         Cirrus Logic EP93xx CPU or an Infineon ADM5120 SOC, say Y or M here.
 342
 343           If unsure, say N.
 344
 345 +config SERIAL_AMBA_PL010_NUMPORTS
 346 +       int "Maximum number of AMBA PL010 serial ports"
 347 +       depends on SERIAL_AMBA_PL010
 348 +       default "8"
 349 +       ---help---
 350 +         Set this to the number of serial ports you want the AMBA PL010 driver
 351 +         to support.
 352 +
 353  config SERIAL_AMBA_PL010_CONSOLE
 354         bool "Support for console on AMBA serial port"
 355         depends on SERIAL_AMBA_PL010=y