package/ltq-dsl/src/ifxmips_atm_ppe_amazon_se.h

   1 #ifndef IFXMIPS_ATM_PPE_AMAZON_SE_H
   2 #define IFXMIPS_ATM_PPE_AMAZON_SE_H
   3
   4
   5
   6 /*
   7  *  FPI Configuration Bus Register and Memory Address Mapping
   8  */
   9 #define IFX_PPE                         (KSEG1 | 0x1E180000)
  10 #define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))
  11 #define PPM_INT_REG_ADDR(i, x)          ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))
  12 #define PP32_INTERNAL_RES_ADDR(i, x)    ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))
  13 #define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))
  14 #define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))
  15 #define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))
  16 #define PPM_INT_UNIT_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))
  17 #define PPM_TIMER0_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))
  18 #define PPM_TASK_IND_REG_ADDR(x)        ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))
  19 #define PPS_BRK_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))
  20 #define PPM_TIMER1_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))
  21 #define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8200) << 2)))
  22 #define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))
  23 #define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))
  24
  25 /*
  26  *  DWORD-Length of Memory Blocks
  27  */
  28 #define PP32_DEBUG_REG_DWLEN            0x0030
  29 #define PPM_INT_REG_DWLEN               0x0010
  30 #define PP32_INTERNAL_RES_DWLEN         0x00C0
  31 #define CDM_CODE_MEMORYn_DWLEN(n)       ((n) == 0 ? 0x1000 : 0x0800)
  32 #define PPE_REG_DWLEN                   0x1000
  33 #define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)
  34 #define PPM_INT_UNIT_DWLEN              0x0100
  35 #define PPM_TIMER0_DWLEN                0x0100
  36 #define PPM_TASK_IND_REG_DWLEN          0x0100
  37 #define PPS_BRK_DWLEN                   0x0100
  38 #define PPM_TIMER1_DWLEN                0x0100
  39 #define SB_RAM0_DWLEN                   0x0A00
  40 #define SB_RAM1_DWLEN                   0x0A00
  41 #define QSB_CONF_REG_DWLEN              0x0100
  42
  43 /*
  44  *  PP32 to FPI Address Mapping
  45  */
  46 #define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x2200) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2200) :   \
  47                                                                    (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2C00) :   \
  48                                                                 0))
  49
  50 /*
  51  *  PP32 Debug Control Register
  52  */
  53 #define PP32_DBG_CTRL                   PP32_DEBUG_REG_ADDR(0, 0x0000)
  54
  55 #define DBG_CTRL_RESTART                0
  56 #define DBG_CTRL_STOP                   1
  57
  58 #define PP32_HALT_STAT                  PP32_DEBUG_REG_ADDR(0, 0x0D00)
  59 #define PP32_BREAKPOINT_REASONS         PP32_DEBUG_REG_ADDR(0, 0x0A00)
  60
  61 #define PP32_BRK_SRC                    PP32_DEBUG_REG_ADDR(0, 0x0F00)
  62
  63 #define PP32_DBG_CUR_PC                 PP32_DEBUG_REG_ADDR(0, 0x0F80)
  64
  65 #define PP32_DBG_TASK_NO                PP32_DEBUG_REG_ADDR(0, 0x0F81)
  66
  67 /*
  68  *  Share Buffer
  69  */
  70 #define SB_MST_PRI0                     PPE_REG_ADDR(0x0300)
  71 #define SB_MST_PRI1                     PPE_REG_ADDR(0x0301)
  72
  73 /*
  74  *  EMA Registers
  75  */
  76 #define EMA_CMDCFG                      PPE_REG_ADDR(0x0A00)
  77 #define EMA_DATACFG                     PPE_REG_ADDR(0x0A01)
  78 #define EMA_CMDCNT                      PPE_REG_ADDR(0x0A02)
  79 #define EMA_DATACNT                     PPE_REG_ADDR(0x0A03)
  80 #define EMA_ISR                         PPE_REG_ADDR(0x0A04)
  81 #define EMA_IER                         PPE_REG_ADDR(0x0A05)
  82 #define EMA_CFG                         PPE_REG_ADDR(0x0A06)
  83 #define EMA_SUBID                       PPE_REG_ADDR(0x0A07)
  84
  85 #define EMA_ALIGNMENT                   4
  86
  87 /*
  88  *  Mailbox IGU1 Interrupt
  89  */
  90 #define PPE_MAILBOX_IGU1_INT            (INT_NUM_IM2_IRL0 + 13)
  91
  92
  93
  94 #endif  //  IFXMIPS_ATM_PPE_AMAZON_SE_H