package/kernel/mac80211/patches/300-pending_work.patch

   1 --- a/drivers/net/wireless/ath/ath10k/mac.c
   2 +++ b/drivers/net/wireless/ath/ath10k/mac.c
   3 @@ -1351,12 +1351,12 @@ static int ath10k_update_channel_list(st
   4                         ch->allow_vht = true;
   5
   6                         ch->allow_ibss =
   7 -                               !(channel->flags & IEEE80211_CHAN_NO_IBSS);
   8 +                               !(channel->flags & IEEE80211_CHAN_NO_IR);
   9
  10                         ch->ht40plus =
  11                                 !(channel->flags & IEEE80211_CHAN_NO_HT40PLUS);
  12
  13 -                       passive = channel->flags & IEEE80211_CHAN_PASSIVE_SCAN;
  14 +                       passive = channel->flags & IEEE80211_CHAN_NO_IR;
  15                         ch->passive = passive;
  16
  17                         ch->freq = channel->center_freq;
  18 --- a/drivers/net/wireless/ath/ath9k/Kconfig
  19 +++ b/drivers/net/wireless/ath/ath9k/Kconfig
  20 @@ -90,7 +90,7 @@ config ATH9K_DFS_CERTIFIED
  21
  22  config ATH9K_TX99
  23         bool "Atheros ath9k TX99 testing support"
  24 -       depends on CFG80211_CERTIFICATION_ONUS
  25 +       depends on ATH9K_DEBUGFS && CFG80211_CERTIFICATION_ONUS
  26         default n
  27         ---help---
  28           Say N. This should only be enabled on systems undergoing
  29 @@ -108,6 +108,14 @@ config ATH9K_TX99
  30           be evaluated to meet the RF exposure limits set forth in the
  31           governmental SAR regulations.
  32
  33 +config ATH9K_WOW
  34 +       bool "Wake on Wireless LAN support (EXPERIMENTAL)"
  35 +       depends on ATH9K && PM
  36 +       default n
  37 +       ---help---
  38 +         This option enables Wake on Wireless LAN support for certain cards.
  39 +         Currently, AR9462 is supported.
  40 +
  41  config ATH9K_LEGACY_RATE_CONTROL
  42         bool "Atheros ath9k rate control"
  43         depends on ATH9K
  44 --- a/drivers/net/wireless/ath/ath9k/Makefile
  45 +++ b/drivers/net/wireless/ath/ath9k/Makefile
  46 @@ -13,9 +13,9 @@ ath9k-$(CPTCFG_ATH9K_PCI) += pci.o
  47  ath9k-$(CPTCFG_ATH9K_AHB) += ahb.o
  48  ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o
  49  ath9k-$(CPTCFG_ATH9K_DFS_DEBUGFS) += dfs_debug.o
  50 -ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += \
  51 -               dfs.o
  52 -ath9k-$(CONFIG_PM_SLEEP) += wow.o
  53 +ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += dfs.o
  54 +ath9k-$(CPTCFG_ATH9K_TX99) += tx99.o
  55 +ath9k-$(CPTCFG_ATH9K_WOW) += wow.o
  56
  57  obj-$(CPTCFG_ATH9K) += ath9k.o
  58
  59 @@ -41,6 +41,8 @@ ath9k_hw-y:=  \
  60                 ar9003_eeprom.o \
  61                 ar9003_paprd.o
  62
  63 +ath9k_hw-$(CPTCFG_ATH9K_WOW) += ar9003_wow.o
  64 +
  65  ath9k_hw-$(CPTCFG_ATH9K_BTCOEX_SUPPORT) += btcoex.o \
  66                                            ar9003_mci.o
  67  obj-$(CPTCFG_ATH9K_HW) += ath9k_hw.o
  68 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
  69 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
  70 @@ -17,6 +17,7 @@
  71  #include "hw.h"
  72  #include "ar9003_mac.h"
  73  #include "ar9003_2p2_initvals.h"
  74 +#include "ar9003_buffalo_initvals.h"
  75  #include "ar9485_initvals.h"
  76  #include "ar9340_initvals.h"
  77  #include "ar9330_1p1_initvals.h"
  78 @@ -26,6 +27,7 @@
  79  #include "ar9462_2p0_initvals.h"
  80  #include "ar9462_2p1_initvals.h"
  81  #include "ar9565_1p0_initvals.h"
  82 +#include "ar9565_1p1_initvals.h"
  83
  84  /* General hardware code for the AR9003 hadware family */
  85
  86 @@ -148,7 +150,11 @@ static void ar9003_hw_init_mode_regs(str
  87                                 ar9340Modes_high_ob_db_tx_gain_table_1p0);
  88
  89                 INIT_INI_ARRAY(&ah->iniModesFastClock,
  90 -                               ar9340Modes_fast_clock_1p0);
  91 +                              ar9340Modes_fast_clock_1p0);
  92 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  93 +                              ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
  94 +               INIT_INI_ARRAY(&ah->ini_dfs,
  95 +                              ar9340_1p0_baseband_postamble_dfs_channel);
  96
  97                 if (!ah->is_clk_25mhz)
  98                         INIT_INI_ARRAY(&ah->iniAdditional,
  99 @@ -187,17 +193,17 @@ static void ar9003_hw_init_mode_regs(str
 100                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 101                                ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
 102
 103 -               /* Load PCIE SERDES settings from INI */
 104 -
 105 -               /* Awake Setting */
 106 -
 107 -               INIT_INI_ARRAY(&ah->iniPcieSerdes,
 108 -                               ar9485_1_1_pcie_phy_clkreq_disable_L1);
 109 -
 110 -               /* Sleep Setting */
 111 -
 112 -               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 113 -                               ar9485_1_1_pcie_phy_clkreq_disable_L1);
 114 +               if (ah->config.no_pll_pwrsave) {
 115 +                       INIT_INI_ARRAY(&ah->iniPcieSerdes,
 116 +                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
 117 +                       INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 118 +                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
 119 +               } else {
 120 +                       INIT_INI_ARRAY(&ah->iniPcieSerdes,
 121 +                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 122 +                       INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 123 +                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 124 +               }
 125         } else if (AR_SREV_9462_21(ah)) {
 126                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 127                                ar9462_2p1_mac_core);
 128 @@ -223,6 +229,10 @@ static void ar9003_hw_init_mode_regs(str
 129                                ar9462_2p1_modes_fast_clock);
 130                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 131                                ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
 132 +               INIT_INI_ARRAY(&ah->iniPcieSerdes,
 133 +                              ar9462_2p1_pciephy_clkreq_disable_L1);
 134 +               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 135 +                              ar9462_2p1_pciephy_clkreq_disable_L1);
 136         } else if (AR_SREV_9462_20(ah)) {
 137
 138                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
 139 @@ -247,18 +257,18 @@ static void ar9003_hw_init_mode_regs(str
 140                                 ar9462_2p0_soc_postamble);
 141
 142                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 143 -                               ar9462_common_rx_gain_table_2p0);
 144 +                               ar9462_2p0_common_rx_gain);
 145
 146                 /* Awake -> Sleep Setting */
 147                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 148 -                              ar9462_pciephy_clkreq_disable_L1_2p0);
 149 +                              ar9462_2p0_pciephy_clkreq_disable_L1);
 150                 /* Sleep -> Awake Setting */
 151                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 152 -                              ar9462_pciephy_clkreq_disable_L1_2p0);
 153 +                              ar9462_2p0_pciephy_clkreq_disable_L1);
 154
 155                 /* Fast clock modal settings */
 156                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 157 -                               ar9462_modes_fast_clock_2p0);
 158 +                               ar9462_2p0_modes_fast_clock);
 159
 160                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 161                                ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
 162 @@ -330,7 +340,46 @@ static void ar9003_hw_init_mode_regs(str
 163                                 ar9580_1p0_low_ob_db_tx_gain_table);
 164
 165                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 166 -                               ar9580_1p0_modes_fast_clock);
 167 +                              ar9580_1p0_modes_fast_clock);
 168 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 169 +                              ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
 170 +               INIT_INI_ARRAY(&ah->ini_dfs,
 171 +                              ar9580_1p0_baseband_postamble_dfs_channel);
 172 +       } else if (AR_SREV_9565_11_OR_LATER(ah)) {
 173 +               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 174 +                              ar9565_1p1_mac_core);
 175 +               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 176 +                              ar9565_1p1_mac_postamble);
 177 +
 178 +               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 179 +                              ar9565_1p1_baseband_core);
 180 +               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 181 +                              ar9565_1p1_baseband_postamble);
 182 +
 183 +               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 184 +                              ar9565_1p1_radio_core);
 185 +               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 186 +                              ar9565_1p1_radio_postamble);
 187 +
 188 +               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 189 +                              ar9565_1p1_soc_preamble);
 190 +               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 191 +                              ar9565_1p1_soc_postamble);
 192 +
 193 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
 194 +                              ar9565_1p1_Common_rx_gain_table);
 195 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 196 +                              ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
 197 +
 198 +               INIT_INI_ARRAY(&ah->iniPcieSerdes,
 199 +                              ar9565_1p1_pciephy_clkreq_disable_L1);
 200 +               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 201 +                              ar9565_1p1_pciephy_clkreq_disable_L1);
 202 +
 203 +               INIT_INI_ARRAY(&ah->iniModesFastClock,
 204 +                               ar9565_1p1_modes_fast_clock);
 205 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 206 +                              ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
 207         } else if (AR_SREV_9565(ah)) {
 208                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 209                                ar9565_1p0_mac_core);
 210 @@ -411,7 +460,11 @@ static void ar9003_hw_init_mode_regs(str
 211
 212                 /* Fast clock modal settings */
 213                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 214 -                               ar9300Modes_fast_clock_2p2);
 215 +                              ar9300Modes_fast_clock_2p2);
 216 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 217 +                              ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
 218 +               INIT_INI_ARRAY(&ah->ini_dfs,
 219 +                              ar9300_2p2_baseband_postamble_dfs_channel);
 220         }
 221  }
 222
 223 @@ -440,7 +493,10 @@ static void ar9003_tx_gain_table_mode0(s
 224                         ar9462_2p1_modes_low_ob_db_tx_gain);
 225         else if (AR_SREV_9462_20(ah))
 226                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 227 -                       ar9462_modes_low_ob_db_tx_gain_table_2p0);
 228 +                       ar9462_2p0_modes_low_ob_db_tx_gain);
 229 +       else if (AR_SREV_9565_11(ah))
 230 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 231 +                              ar9565_1p1_modes_low_ob_db_tx_gain_table);
 232         else if (AR_SREV_9565(ah))
 233                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 234                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 235 @@ -474,7 +530,10 @@ static void ar9003_tx_gain_table_mode1(s
 236                         ar9462_2p1_modes_high_ob_db_tx_gain);
 237         else if (AR_SREV_9462_20(ah))
 238                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 239 -                       ar9462_modes_high_ob_db_tx_gain_table_2p0);
 240 +                       ar9462_2p0_modes_high_ob_db_tx_gain);
 241 +       else if (AR_SREV_9565_11(ah))
 242 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 243 +                              ar9565_1p1_modes_high_ob_db_tx_gain_table);
 244         else if (AR_SREV_9565(ah))
 245                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 246                                ar9565_1p0_modes_high_ob_db_tx_gain_table);
 247 @@ -500,6 +559,9 @@ static void ar9003_tx_gain_table_mode2(s
 248         else if (AR_SREV_9580(ah))
 249                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 250                         ar9580_1p0_low_ob_db_tx_gain_table);
 251 +       else if (AR_SREV_9565_11(ah))
 252 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 253 +                              ar9565_1p1_modes_low_ob_db_tx_gain_table);
 254         else if (AR_SREV_9565(ah))
 255                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 256                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 257 @@ -525,12 +587,20 @@ static void ar9003_tx_gain_table_mode3(s
 258         else if (AR_SREV_9580(ah))
 259                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 260                         ar9580_1p0_high_power_tx_gain_table);
 261 +       else if (AR_SREV_9565_11(ah))
 262 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 263 +                              ar9565_1p1_modes_high_power_tx_gain_table);
 264         else if (AR_SREV_9565(ah))
 265                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 266                                ar9565_1p0_modes_high_power_tx_gain_table);
 267 -       else
 268 -               INIT_INI_ARRAY(&ah->iniModesTxGain,
 269 -                       ar9300Modes_high_power_tx_gain_table_2p2);
 270 +       else {
 271 +               if (ah->config.tx_gain_buffalo)
 272 +                       INIT_INI_ARRAY(&ah->iniModesTxGain,
 273 +                                      ar9300Modes_high_power_tx_gain_table_buffalo);
 274 +               else
 275 +                       INIT_INI_ARRAY(&ah->iniModesTxGain,
 276 +                                      ar9300Modes_high_power_tx_gain_table_2p2);
 277 +       }
 278  }
 279
 280  static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
 281 @@ -546,7 +616,7 @@ static void ar9003_tx_gain_table_mode4(s
 282                        ar9462_2p1_modes_mix_ob_db_tx_gain);
 283         else if (AR_SREV_9462_20(ah))
 284                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 285 -                      ar9462_modes_mix_ob_db_tx_gain_table_2p0);
 286 +                      ar9462_2p0_modes_mix_ob_db_tx_gain);
 287         else
 288                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 289                         ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
 290 @@ -581,6 +651,13 @@ static void ar9003_tx_gain_table_mode6(s
 291                         ar9580_1p0_type6_tx_gain_table);
 292  }
 293
 294 +static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
 295 +{
 296 +       if (AR_SREV_9340(ah))
 297 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 298 +                              ar9340_cus227_tx_gain_table_1p0);
 299 +}
 300 +
 301  typedef void (*ath_txgain_tab)(struct ath_hw *ah);
 302
 303  static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 304 @@ -593,6 +670,7 @@ static void ar9003_tx_gain_table_apply(s
 305                 ar9003_tx_gain_table_mode4,
 306                 ar9003_tx_gain_table_mode5,
 307                 ar9003_tx_gain_table_mode6,
 308 +               ar9003_tx_gain_table_mode7,
 309         };
 310         int idx = ar9003_hw_get_tx_gain_idx(ah);
 311
 312 @@ -629,7 +707,10 @@ static void ar9003_rx_gain_table_mode0(s
 313                                 ar9462_2p1_common_rx_gain);
 314         else if (AR_SREV_9462_20(ah))
 315                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 316 -                               ar9462_common_rx_gain_table_2p0);
 317 +                               ar9462_2p0_common_rx_gain);
 318 +       else if (AR_SREV_9565_11(ah))
 319 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
 320 +                              ar9565_1p1_Common_rx_gain_table);
 321         else if (AR_SREV_9565(ah))
 322                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 323                                ar9565_1p0_Common_rx_gain_table);
 324 @@ -657,7 +738,7 @@ static void ar9003_rx_gain_table_mode1(s
 325                         ar9462_2p1_common_wo_xlna_rx_gain);
 326         else if (AR_SREV_9462_20(ah))
 327                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 328 -                       ar9462_common_wo_xlna_rx_gain_table_2p0);
 329 +                       ar9462_2p0_common_wo_xlna_rx_gain);
 330         else if (AR_SREV_9550(ah)) {
 331                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 332                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 333 @@ -666,6 +747,9 @@ static void ar9003_rx_gain_table_mode1(s
 334         } else if (AR_SREV_9580(ah))
 335                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 336                         ar9580_1p0_wo_xlna_rx_gain_table);
 337 +       else if (AR_SREV_9565_11(ah))
 338 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
 339 +                              ar9565_1p1_common_wo_xlna_rx_gain_table);
 340         else if (AR_SREV_9565(ah))
 341                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 342                                ar9565_1p0_common_wo_xlna_rx_gain_table);
 343 @@ -687,7 +771,7 @@ static void ar9003_rx_gain_table_mode2(s
 344                                ar9462_2p1_baseband_postamble_5g_xlna);
 345         } else if (AR_SREV_9462_20(ah)) {
 346                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 347 -                              ar9462_common_mixed_rx_gain_table_2p0);
 348 +                              ar9462_2p0_common_mixed_rx_gain);
 349                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 350                                ar9462_2p0_baseband_core_mix_rxgain);
 351                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 352 @@ -701,12 +785,12 @@ static void ar9003_rx_gain_table_mode3(s
 353  {
 354         if (AR_SREV_9462_21(ah)) {
 355                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 356 -                              ar9462_2p1_common_5g_xlna_only_rx_gain);
 357 +                              ar9462_2p1_common_5g_xlna_only_rxgain);
 358                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 359                                ar9462_2p1_baseband_postamble_5g_xlna);
 360         } else if (AR_SREV_9462_20(ah)) {
 361                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 362 -                              ar9462_2p0_5g_xlna_only_rxgain);
 363 +                              ar9462_2p0_common_5g_xlna_only_rxgain);
 364                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 365                                ar9462_2p0_baseband_postamble_5g_xlna);
 366         }
 367 @@ -750,6 +834,9 @@ static void ar9003_hw_init_mode_gain_reg
 368  static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
 369                                          bool power_off)
 370  {
 371 +       unsigned int i;
 372 +       struct ar5416IniArray *array;
 373 +
 374         /*
 375          * Increase L1 Entry Latency. Some WB222 boards don't have
 376          * this change in eeprom/OTP.
 377 @@ -775,18 +862,13 @@ static void ar9003_hw_configpcipowersave
 378          * Configire PCIE after Ini init. SERDES values now come from ini file
 379          * This enables PCIe low power mode.
 380          */
 381 -       if (ah->config.pcieSerDesWrite) {
 382 -               unsigned int i;
 383 -               struct ar5416IniArray *array;
 384 -
 385 -               array = power_off ? &ah->iniPcieSerdes :
 386 -                                   &ah->iniPcieSerdesLowPower;
 387 -
 388 -               for (i = 0; i < array->ia_rows; i++) {
 389 -                       REG_WRITE(ah,
 390 -                                 INI_RA(array, i, 0),
 391 -                                 INI_RA(array, i, 1));
 392 -               }
 393 +       array = power_off ? &ah->iniPcieSerdes :
 394 +               &ah->iniPcieSerdesLowPower;
 395 +
 396 +       for (i = 0; i < array->ia_rows; i++) {
 397 +               REG_WRITE(ah,
 398 +                         INI_RA(array, i, 0),
 399 +                         INI_RA(array, i, 1));
 400         }
 401  }
 402
 403 --- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
 404 +++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
 405 @@ -18,6 +18,20 @@
 406  #ifndef INITVALS_9340_H
 407  #define INITVALS_9340_H
 408
 409 +#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
 410 +
 411 +#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
 412 +
 413 +#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
 414 +
 415 +#define ar9340Common_rx_gain_table_1p0 ar9300Common_rx_gain_table_2p2
 416 +
 417 +#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
 418 +
 419 +#define ar9340_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
 420 +
 421 +#define ar9340_1p0_baseband_postamble_dfs_channel ar9300_2p2_baseband_postamble_dfs_channel
 422 +
 423  static const u32 ar9340_1p0_radio_postamble[][5] = {
 424         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 425         {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
 426 @@ -100,8 +114,6 @@ static const u32 ar9340Modes_lowest_ob_d
 427         {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
 428  };
 429
 430 -#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
 431 -
 432  static const u32 ar9340_1p0_radio_core[][2] = {
 433         /* Addr      allmodes  */
 434         {0x00016000, 0x36db6db6},
 435 @@ -215,16 +227,12 @@ static const u32 ar9340_1p0_radio_core_4
 436         {0x0000824c, 0x0001e800},
 437  };
 438
 439 -#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
 440 -
 441 -#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
 442 -
 443  static const u32 ar9340_1p0_baseband_postamble[][5] = {
 444         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 445         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
 446         {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e},
 447         {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
 448 -       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
 449 +       {0x00009828, 0x06903081, 0x06903081, 0x09103881, 0x09103881},
 450         {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
 451         {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
 452         {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
 453 @@ -340,9 +348,9 @@ static const u32 ar9340_1p0_baseband_cor
 454         {0x0000a370, 0x00000000},
 455         {0x0000a390, 0x00000001},
 456         {0x0000a394, 0x00000444},
 457 -       {0x0000a398, 0x001f0e0f},
 458 -       {0x0000a39c, 0x0075393f},
 459 -       {0x0000a3a0, 0xb79f6427},
 460 +       {0x0000a398, 0x00000000},
 461 +       {0x0000a39c, 0x210d0401},
 462 +       {0x0000a3a0, 0xab9a7144},
 463         {0x0000a3a4, 0x00000000},
 464         {0x0000a3a8, 0xaaaaaaaa},
 465         {0x0000a3ac, 0x3c466478},
 466 @@ -714,266 +722,6 @@ static const u32 ar9340Modes_ub124_tx_ga
 467         {0x0000b2e8, 0xfffe0000, 0xfffe0000, 0xfffc0000, 0xfffc0000},
 468  };
 469
 470 -static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
 471 -       /* Addr      allmodes  */
 472 -       {0x0000a000, 0x00010000},
 473 -       {0x0000a004, 0x00030002},
 474 -       {0x0000a008, 0x00050004},
 475 -       {0x0000a00c, 0x00810080},
 476 -       {0x0000a010, 0x00830082},
 477 -       {0x0000a014, 0x01810180},
 478 -       {0x0000a018, 0x01830182},
 479 -       {0x0000a01c, 0x01850184},
 480 -       {0x0000a020, 0x01890188},
 481 -       {0x0000a024, 0x018b018a},
 482 -       {0x0000a028, 0x018d018c},
 483 -       {0x0000a02c, 0x01910190},
 484 -       {0x0000a030, 0x01930192},
 485 -       {0x0000a034, 0x01950194},
 486 -       {0x0000a038, 0x038a0196},
 487 -       {0x0000a03c, 0x038c038b},
 488 -       {0x0000a040, 0x0390038d},
 489 -       {0x0000a044, 0x03920391},
 490 -       {0x0000a048, 0x03940393},
 491 -       {0x0000a04c, 0x03960395},
 492 -       {0x0000a050, 0x00000000},
 493 -       {0x0000a054, 0x00000000},
 494 -       {0x0000a058, 0x00000000},
 495 -       {0x0000a05c, 0x00000000},
 496 -       {0x0000a060, 0x00000000},
 497 -       {0x0000a064, 0x00000000},
 498 -       {0x0000a068, 0x00000000},
 499 -       {0x0000a06c, 0x00000000},
 500 -       {0x0000a070, 0x00000000},
 501 -       {0x0000a074, 0x00000000},
 502 -       {0x0000a078, 0x00000000},
 503 -       {0x0000a07c, 0x00000000},
 504 -       {0x0000a080, 0x22222229},
 505 -       {0x0000a084, 0x1d1d1d1d},
 506 -       {0x0000a088, 0x1d1d1d1d},
 507 -       {0x0000a08c, 0x1d1d1d1d},
 508 -       {0x0000a090, 0x171d1d1d},
 509 -       {0x0000a094, 0x11111717},
 510 -       {0x0000a098, 0x00030311},
 511 -       {0x0000a09c, 0x00000000},
 512 -       {0x0000a0a0, 0x00000000},
 513 -       {0x0000a0a4, 0x00000000},
 514 -       {0x0000a0a8, 0x00000000},
 515 -       {0x0000a0ac, 0x00000000},
 516 -       {0x0000a0b0, 0x00000000},
 517 -       {0x0000a0b4, 0x00000000},
 518 -       {0x0000a0b8, 0x00000000},
 519 -       {0x0000a0bc, 0x00000000},
 520 -       {0x0000a0c0, 0x001f0000},
 521 -       {0x0000a0c4, 0x01000101},
 522 -       {0x0000a0c8, 0x011e011f},
 523 -       {0x0000a0cc, 0x011c011d},
 524 -       {0x0000a0d0, 0x02030204},
 525 -       {0x0000a0d4, 0x02010202},
 526 -       {0x0000a0d8, 0x021f0200},
 527 -       {0x0000a0dc, 0x0302021e},
 528 -       {0x0000a0e0, 0x03000301},
 529 -       {0x0000a0e4, 0x031e031f},
 530 -       {0x0000a0e8, 0x0402031d},
 531 -       {0x0000a0ec, 0x04000401},
 532 -       {0x0000a0f0, 0x041e041f},
 533 -       {0x0000a0f4, 0x0502041d},
 534 -       {0x0000a0f8, 0x05000501},
 535 -       {0x0000a0fc, 0x051e051f},
 536 -       {0x0000a100, 0x06010602},
 537 -       {0x0000a104, 0x061f0600},
 538 -       {0x0000a108, 0x061d061e},
 539 -       {0x0000a10c, 0x07020703},
 540 -       {0x0000a110, 0x07000701},
 541 -       {0x0000a114, 0x00000000},
 542 -       {0x0000a118, 0x00000000},
 543 -       {0x0000a11c, 0x00000000},
 544 -       {0x0000a120, 0x00000000},
 545 -       {0x0000a124, 0x00000000},
 546 -       {0x0000a128, 0x00000000},
 547 -       {0x0000a12c, 0x00000000},
 548 -       {0x0000a130, 0x00000000},
 549 -       {0x0000a134, 0x00000000},
 550 -       {0x0000a138, 0x00000000},
 551 -       {0x0000a13c, 0x00000000},
 552 -       {0x0000a140, 0x001f0000},
 553 -       {0x0000a144, 0x01000101},
 554 -       {0x0000a148, 0x011e011f},
 555 -       {0x0000a14c, 0x011c011d},
 556 -       {0x0000a150, 0x02030204},
 557 -       {0x0000a154, 0x02010202},
 558 -       {0x0000a158, 0x021f0200},
 559 -       {0x0000a15c, 0x0302021e},
 560 -       {0x0000a160, 0x03000301},
 561 -       {0x0000a164, 0x031e031f},
 562 -       {0x0000a168, 0x0402031d},
 563 -       {0x0000a16c, 0x04000401},
 564 -       {0x0000a170, 0x041e041f},
 565 -       {0x0000a174, 0x0502041d},
 566 -       {0x0000a178, 0x05000501},
 567 -       {0x0000a17c, 0x051e051f},
 568 -       {0x0000a180, 0x06010602},
 569 -       {0x0000a184, 0x061f0600},
 570 -       {0x0000a188, 0x061d061e},
 571 -       {0x0000a18c, 0x07020703},
 572 -       {0x0000a190, 0x07000701},
 573 -       {0x0000a194, 0x00000000},
 574 -       {0x0000a198, 0x00000000},
 575 -       {0x0000a19c, 0x00000000},
 576 -       {0x0000a1a0, 0x00000000},
 577 -       {0x0000a1a4, 0x00000000},
 578 -       {0x0000a1a8, 0x00000000},
 579 -       {0x0000a1ac, 0x00000000},
 580 -       {0x0000a1b0, 0x00000000},
 581 -       {0x0000a1b4, 0x00000000},
 582 -       {0x0000a1b8, 0x00000000},
 583 -       {0x0000a1bc, 0x00000000},
 584 -       {0x0000a1c0, 0x00000000},
 585 -       {0x0000a1c4, 0x00000000},
 586 -       {0x0000a1c8, 0x00000000},
 587 -       {0x0000a1cc, 0x00000000},
 588 -       {0x0000a1d0, 0x00000000},
 589 -       {0x0000a1d4, 0x00000000},
 590 -       {0x0000a1d8, 0x00000000},
 591 -       {0x0000a1dc, 0x00000000},
 592 -       {0x0000a1e0, 0x00000000},
 593 -       {0x0000a1e4, 0x00000000},
 594 -       {0x0000a1e8, 0x00000000},
 595 -       {0x0000a1ec, 0x00000000},
 596 -       {0x0000a1f0, 0x00000396},
 597 -       {0x0000a1f4, 0x00000396},
 598 -       {0x0000a1f8, 0x00000396},
 599 -       {0x0000a1fc, 0x00000196},
 600 -       {0x0000b000, 0x00010000},
 601 -       {0x0000b004, 0x00030002},
 602 -       {0x0000b008, 0x00050004},
 603 -       {0x0000b00c, 0x00810080},
 604 -       {0x0000b010, 0x00830082},
 605 -       {0x0000b014, 0x01810180},
 606 -       {0x0000b018, 0x01830182},
 607 -       {0x0000b01c, 0x01850184},
 608 -       {0x0000b020, 0x02810280},
 609 -       {0x0000b024, 0x02830282},
 610 -       {0x0000b028, 0x02850284},
 611 -       {0x0000b02c, 0x02890288},
 612 -       {0x0000b030, 0x028b028a},
 613 -       {0x0000b034, 0x0388028c},
 614 -       {0x0000b038, 0x038a0389},
 615 -       {0x0000b03c, 0x038c038b},
 616 -       {0x0000b040, 0x0390038d},
 617 -       {0x0000b044, 0x03920391},
 618 -       {0x0000b048, 0x03940393},
 619 -       {0x0000b04c, 0x03960395},
 620 -       {0x0000b050, 0x00000000},
 621 -       {0x0000b054, 0x00000000},
 622 -       {0x0000b058, 0x00000000},
 623 -       {0x0000b05c, 0x00000000},
 624 -       {0x0000b060, 0x00000000},
 625 -       {0x0000b064, 0x00000000},
 626 -       {0x0000b068, 0x00000000},
 627 -       {0x0000b06c, 0x00000000},
 628 -       {0x0000b070, 0x00000000},
 629 -       {0x0000b074, 0x00000000},
 630 -       {0x0000b078, 0x00000000},
 631 -       {0x0000b07c, 0x00000000},
 632 -       {0x0000b080, 0x23232323},
 633 -       {0x0000b084, 0x21232323},
 634 -       {0x0000b088, 0x19191c1e},
 635 -       {0x0000b08c, 0x12141417},
 636 -       {0x0000b090, 0x07070e0e},
 637 -       {0x0000b094, 0x03030305},
 638 -       {0x0000b098, 0x00000003},
 639 -       {0x0000b09c, 0x00000000},
 640 -       {0x0000b0a0, 0x00000000},
 641 -       {0x0000b0a4, 0x00000000},
 642 -       {0x0000b0a8, 0x00000000},
 643 -       {0x0000b0ac, 0x00000000},
 644 -       {0x0000b0b0, 0x00000000},
 645 -       {0x0000b0b4, 0x00000000},
 646 -       {0x0000b0b8, 0x00000000},
 647 -       {0x0000b0bc, 0x00000000},
 648 -       {0x0000b0c0, 0x003f0020},
 649 -       {0x0000b0c4, 0x00400041},
 650 -       {0x0000b0c8, 0x0140005f},
 651 -       {0x0000b0cc, 0x0160015f},
 652 -       {0x0000b0d0, 0x017e017f},
 653 -       {0x0000b0d4, 0x02410242},
 654 -       {0x0000b0d8, 0x025f0240},
 655 -       {0x0000b0dc, 0x027f0260},
 656 -       {0x0000b0e0, 0x0341027e},
 657 -       {0x0000b0e4, 0x035f0340},
 658 -       {0x0000b0e8, 0x037f0360},
 659 -       {0x0000b0ec, 0x04400441},
 660 -       {0x0000b0f0, 0x0460045f},
 661 -       {0x0000b0f4, 0x0541047f},
 662 -       {0x0000b0f8, 0x055f0540},
 663 -       {0x0000b0fc, 0x057f0560},
 664 -       {0x0000b100, 0x06400641},
 665 -       {0x0000b104, 0x0660065f},
 666 -       {0x0000b108, 0x067e067f},
 667 -       {0x0000b10c, 0x07410742},
 668 -       {0x0000b110, 0x075f0740},
 669 -       {0x0000b114, 0x077f0760},
 670 -       {0x0000b118, 0x07800781},
 671 -       {0x0000b11c, 0x07a0079f},
 672 -       {0x0000b120, 0x07c107bf},
 673 -       {0x0000b124, 0x000007c0},
 674 -       {0x0000b128, 0x00000000},
 675 -       {0x0000b12c, 0x00000000},
 676 -       {0x0000b130, 0x00000000},
 677 -       {0x0000b134, 0x00000000},
 678 -       {0x0000b138, 0x00000000},
 679 -       {0x0000b13c, 0x00000000},
 680 -       {0x0000b140, 0x003f0020},
 681 -       {0x0000b144, 0x00400041},
 682 -       {0x0000b148, 0x0140005f},
 683 -       {0x0000b14c, 0x0160015f},
 684 -       {0x0000b150, 0x017e017f},
 685 -       {0x0000b154, 0x02410242},
 686 -       {0x0000b158, 0x025f0240},
 687 -       {0x0000b15c, 0x027f0260},
 688 -       {0x0000b160, 0x0341027e},
 689 -       {0x0000b164, 0x035f0340},
 690 -       {0x0000b168, 0x037f0360},
 691 -       {0x0000b16c, 0x04400441},
 692 -       {0x0000b170, 0x0460045f},
 693 -       {0x0000b174, 0x0541047f},
 694 -       {0x0000b178, 0x055f0540},
 695 -       {0x0000b17c, 0x057f0560},
 696 -       {0x0000b180, 0x06400641},
 697 -       {0x0000b184, 0x0660065f},
 698 -       {0x0000b188, 0x067e067f},
 699 -       {0x0000b18c, 0x07410742},
 700 -       {0x0000b190, 0x075f0740},
 701 -       {0x0000b194, 0x077f0760},
 702 -       {0x0000b198, 0x07800781},
 703 -       {0x0000b19c, 0x07a0079f},
 704 -       {0x0000b1a0, 0x07c107bf},
 705 -       {0x0000b1a4, 0x000007c0},
 706 -       {0x0000b1a8, 0x00000000},
 707 -       {0x0000b1ac, 0x00000000},
 708 -       {0x0000b1b0, 0x00000000},
 709 -       {0x0000b1b4, 0x00000000},
 710 -       {0x0000b1b8, 0x00000000},
 711 -       {0x0000b1bc, 0x00000000},
 712 -       {0x0000b1c0, 0x00000000},
 713 -       {0x0000b1c4, 0x00000000},
 714 -       {0x0000b1c8, 0x00000000},
 715 -       {0x0000b1cc, 0x00000000},
 716 -       {0x0000b1d0, 0x00000000},
 717 -       {0x0000b1d4, 0x00000000},
 718 -       {0x0000b1d8, 0x00000000},
 719 -       {0x0000b1dc, 0x00000000},
 720 -       {0x0000b1e0, 0x00000000},
 721 -       {0x0000b1e4, 0x00000000},
 722 -       {0x0000b1e8, 0x00000000},
 723 -       {0x0000b1ec, 0x00000000},
 724 -       {0x0000b1f0, 0x00000396},
 725 -       {0x0000b1f4, 0x00000396},
 726 -       {0x0000b1f8, 0x00000396},
 727 -       {0x0000b1fc, 0x00000196},
 728 -};
 729 -
 730  static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
 731         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 732         {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
 733 @@ -1437,8 +1185,6 @@ static const u32 ar9340_1p0_mac_core[][2
 734         {0x000083d0, 0x000101ff},
 735  };
 736
 737 -#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
 738 -
 739  static const u32 ar9340_1p0_soc_preamble[][2] = {
 740         /* Addr      allmodes  */
 741         {0x00007008, 0x00000000},
 742 @@ -1447,4 +1193,106 @@ static const u32 ar9340_1p0_soc_preamble
 743         {0x00007038, 0x000004c2},
 744  };
 745
 746 +static const u32 ar9340_cus227_tx_gain_table_1p0[][5] = {
 747 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 748 +       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
 749 +       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
 750 +       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
 751 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
 752 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
 753 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 754 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
 755 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
 756 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
 757 +       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
 758 +       {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400},
 759 +       {0x0000a518, 0x21002220, 0x21002220, 0x15000402, 0x15000402},
 760 +       {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
 761 +       {0x0000a520, 0x2c022220, 0x2c022220, 0x1b000603, 0x1b000603},
 762 +       {0x0000a524, 0x30022222, 0x30022222, 0x1f000a02, 0x1f000a02},
 763 +       {0x0000a528, 0x35022225, 0x35022225, 0x23000a04, 0x23000a04},
 764 +       {0x0000a52c, 0x3b02222a, 0x3b02222a, 0x26000a20, 0x26000a20},
 765 +       {0x0000a530, 0x3f02222c, 0x3f02222c, 0x2a000e20, 0x2a000e20},
 766 +       {0x0000a534, 0x4202242a, 0x4202242a, 0x2e000e22, 0x2e000e22},
 767 +       {0x0000a538, 0x4702244a, 0x4702244a, 0x31000e24, 0x31000e24},
 768 +       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x34001640, 0x34001640},
 769 +       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660},
 770 +       {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861},
 771 +       {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81},
 772 +       {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x42001a83, 0x42001a83},
 773 +       {0x0000a550, 0x61024a6c, 0x61024a6c, 0x44001c84, 0x44001c84},
 774 +       {0x0000a554, 0x66026a6c, 0x66026a6c, 0x48001ce3, 0x48001ce3},
 775 +       {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x4c001ce5, 0x4c001ce5},
 776 +       {0x0000a55c, 0x7002708c, 0x7002708c, 0x50001ce9, 0x50001ce9},
 777 +       {0x0000a560, 0x7302b08a, 0x7302b08a, 0x54001ceb, 0x54001ceb},
 778 +       {0x0000a564, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 779 +       {0x0000a568, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 780 +       {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 781 +       {0x0000a570, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 782 +       {0x0000a574, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 783 +       {0x0000a578, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 784 +       {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 785 +       {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
 786 +       {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
 787 +       {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
 788 +       {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
 789 +       {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
 790 +       {0x0000a594, 0x1c800223, 0x1c800223, 0x11800400, 0x11800400},
 791 +       {0x0000a598, 0x21820220, 0x21820220, 0x15800402, 0x15800402},
 792 +       {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
 793 +       {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800603, 0x1b800603},
 794 +       {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800a02, 0x1f800a02},
 795 +       {0x0000a5a8, 0x34822225, 0x34822225, 0x23800a04, 0x23800a04},
 796 +       {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x26800a20, 0x26800a20},
 797 +       {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2a800e20, 0x2a800e20},
 798 +       {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2e800e22, 0x2e800e22},
 799 +       {0x0000a5b8, 0x4782244a, 0x4782244a, 0x31800e24, 0x31800e24},
 800 +       {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x34801640, 0x34801640},
 801 +       {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38801660, 0x38801660},
 802 +       {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3b801861, 0x3b801861},
 803 +       {0x0000a5c8, 0x5782286c, 0x5782286c, 0x3e801a81, 0x3e801a81},
 804 +       {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x42801a83, 0x42801a83},
 805 +       {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x44801c84, 0x44801c84},
 806 +       {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x48801ce3, 0x48801ce3},
 807 +       {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x4c801ce5, 0x4c801ce5},
 808 +       {0x0000a5dc, 0x7086308c, 0x7086308c, 0x50801ce9, 0x50801ce9},
 809 +       {0x0000a5e0, 0x738a308a, 0x738a308a, 0x54801ceb, 0x54801ceb},
 810 +       {0x0000a5e4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 811 +       {0x0000a5e8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 812 +       {0x0000a5ec, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 813 +       {0x0000a5f0, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 814 +       {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 815 +       {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 816 +       {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 817 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 818 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 819 +       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 820 +       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 821 +       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 822 +       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
 823 +       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
 824 +       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
 825 +       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
 826 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
 827 +       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
 828 +       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
 829 +       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
 830 +       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
 831 +       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
 832 +       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
 833 +       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
 834 +       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
 835 +       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
 836 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
 837 +       {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
 838 +       {0x00016048, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
 839 +       {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
 840 +       {0x00016288, 0x30318000, 0x30318000, 0x00318000, 0x00318000},
 841 +       {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
 842 +       {0x00016448, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
 843 +       {0x0000a3a4, 0x00000011, 0x00000011, 0x00000011, 0x00000011},
 844 +       {0x0000a3a8, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c},
 845 +       {0x0000a3ac, 0x30303030, 0x30303030, 0x30303030, 0x30303030},
 846 +};
 847 +
 848  #endif /* INITVALS_9340_H */
 849 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
 850 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
 851 @@ -459,6 +459,7 @@ void ath_check_ani(struct ath_softc *sc)
 852  int ath_update_survey_stats(struct ath_softc *sc);
 853  void ath_update_survey_nf(struct ath_softc *sc, int channel);
 854  void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
 855 +void ath_ps_full_sleep(unsigned long data);
 856
 857  /**********/
 858  /* BTCOEX */
 859 @@ -476,20 +477,19 @@ enum bt_op_flags {
 860  };
 861
 862  struct ath_btcoex {
 863 -       bool hw_timer_enabled;
 864         spinlock_t btcoex_lock;
 865         struct timer_list period_timer; /* Timer for BT period */
 866 +       struct timer_list no_stomp_timer;
 867         u32 bt_priority_cnt;
 868         unsigned long bt_priority_time;
 869         unsigned long op_flags;
 870         int bt_stomp_type; /* Types of BT stomping */
 871 -       u32 btcoex_no_stomp; /* in usec */
 872 +       u32 btcoex_no_stomp; /* in msec */
 873         u32 btcoex_period; /* in msec */
 874 -       u32 btscan_no_stomp; /* in usec */
 875 +       u32 btscan_no_stomp; /* in msec */
 876         u32 duty_cycle;
 877         u32 bt_wait_time;
 878         int rssi_count;
 879 -       struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
 880         struct ath_mci_profile mci;
 881         u8 stomp_audio;
 882  };
 883 @@ -570,6 +570,34 @@ static inline void ath_fill_led_pin(stru
 884  }
 885  #endif
 886
 887 +/************************/
 888 +/* Wake on Wireless LAN */
 889 +/************************/
 890 +
 891 +#ifdef CONFIG_ATH9K_WOW
 892 +void ath9k_init_wow(struct ieee80211_hw *hw);
 893 +int ath9k_suspend(struct ieee80211_hw *hw,
 894 +                 struct cfg80211_wowlan *wowlan);
 895 +int ath9k_resume(struct ieee80211_hw *hw);
 896 +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
 897 +#else
 898 +static inline void ath9k_init_wow(struct ieee80211_hw *hw)
 899 +{
 900 +}
 901 +static inline int ath9k_suspend(struct ieee80211_hw *hw,
 902 +                               struct cfg80211_wowlan *wowlan)
 903 +{
 904 +       return 0;
 905 +}
 906 +static inline int ath9k_resume(struct ieee80211_hw *hw)
 907 +{
 908 +       return 0;
 909 +}
 910 +static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
 911 +{
 912 +}
 913 +#endif /* CONFIG_ATH9K_WOW */
 914 +
 915  /*******************************/
 916  /* Antenna diversity/combining */
 917  /*******************************/
 918 @@ -632,15 +660,16 @@ void ath_ant_comb_scan(struct ath_softc
 919  /* Main driver core */
 920  /********************/
 921
 922 -#define ATH9K_PCI_CUS198      0x0001
 923 -#define ATH9K_PCI_CUS230      0x0002
 924 -#define ATH9K_PCI_CUS217      0x0004
 925 -#define ATH9K_PCI_CUS252      0x0008
 926 -#define ATH9K_PCI_WOW         0x0010
 927 -#define ATH9K_PCI_BT_ANT_DIV  0x0020
 928 -#define ATH9K_PCI_D3_L1_WAR   0x0040
 929 -#define ATH9K_PCI_AR9565_1ANT 0x0080
 930 -#define ATH9K_PCI_AR9565_2ANT 0x0100
 931 +#define ATH9K_PCI_CUS198          0x0001
 932 +#define ATH9K_PCI_CUS230          0x0002
 933 +#define ATH9K_PCI_CUS217          0x0004
 934 +#define ATH9K_PCI_CUS252          0x0008
 935 +#define ATH9K_PCI_WOW             0x0010
 936 +#define ATH9K_PCI_BT_ANT_DIV      0x0020
 937 +#define ATH9K_PCI_D3_L1_WAR       0x0040
 938 +#define ATH9K_PCI_AR9565_1ANT     0x0080
 939 +#define ATH9K_PCI_AR9565_2ANT     0x0100
 940 +#define ATH9K_PCI_NO_PLL_PWRSAVE  0x0200
 941
 942  /*
 943   * Default cache line size, in bytes.
 944 @@ -723,6 +752,7 @@ struct ath_softc {
 945         struct work_struct hw_check_work;
 946         struct work_struct hw_reset_work;
 947         struct completion paprd_complete;
 948 +       wait_queue_head_t tx_wait;
 949
 950         unsigned int hw_busy_count;
 951         unsigned long sc_flags;
 952 @@ -759,6 +789,7 @@ struct ath_softc {
 953         struct delayed_work tx_complete_work;
 954         struct delayed_work hw_pll_work;
 955         struct timer_list rx_poll_timer;
 956 +       struct timer_list sleep_timer;
 957
 958  #ifdef CPTCFG_ATH9K_BTCOEX_SUPPORT
 959         struct ath_btcoex btcoex;
 960 @@ -783,7 +814,7 @@ struct ath_softc {
 961         bool tx99_state;
 962         s16 tx99_power;
 963
 964 -#ifdef CONFIG_PM_SLEEP
 965 +#ifdef CONFIG_ATH9K_WOW
 966         atomic_t wow_got_bmiss_intr;
 967         atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
 968         u32 wow_intr_before_sleep;
 969 @@ -946,10 +977,25 @@ struct fft_sample_ht20_40 {
 970         u8 data[SPECTRAL_HT20_40_NUM_BINS];
 971  } __packed;
 972
 973 -int ath9k_tx99_init(struct ath_softc *sc);
 974 -void ath9k_tx99_deinit(struct ath_softc *sc);
 975 +/********/
 976 +/* TX99 */
 977 +/********/
 978 +
 979 +#ifdef CONFIG_ATH9K_TX99
 980 +void ath9k_tx99_init_debug(struct ath_softc *sc);
 981  int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
 982                     struct ath_tx_control *txctl);
 983 +#else
 984 +static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
 985 +{
 986 +}
 987 +static inline int ath9k_tx99_send(struct ath_softc *sc,
 988 +                                 struct sk_buff *skb,
 989 +                                 struct ath_tx_control *txctl)
 990 +{
 991 +       return 0;
 992 +}
 993 +#endif /* CONFIG_ATH9K_TX99 */
 994
 995  void ath9k_tasklet(unsigned long data);
 996  int ath_cabq_update(struct ath_softc *);
 997 @@ -966,6 +1012,9 @@ extern bool is_ath9k_unloaded;
 998
 999  u8 ath9k_parse_mpdudensity(u8 mpdudensity);
1000  irqreturn_t ath_isr(int irq, void *dev);
1001 +int ath_reset(struct ath_softc *sc);
1002 +void ath_cancel_work(struct ath_softc *sc);
1003 +void ath_restart_work(struct ath_softc *sc);
1004  int ath9k_init_device(u16 devid, struct ath_softc *sc,
1005                     const struct ath_bus_ops *bus_ops);
1006  void ath9k_deinit_device(struct ath_softc *sc);
1007 --- a/drivers/net/wireless/ath/ath9k/debug.c
1008 +++ b/drivers/net/wireless/ath/ath9k/debug.c
1009 @@ -1782,111 +1782,6 @@ void ath9k_deinit_debug(struct ath_softc
1010         }
1011  }
1012
1013 -static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
1014 -                             size_t count, loff_t *ppos)
1015 -{
1016 -       struct ath_softc *sc = file->private_data;
1017 -       char buf[3];
1018 -       unsigned int len;
1019 -
1020 -       len = sprintf(buf, "%d\n", sc->tx99_state);
1021 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1022 -}
1023 -
1024 -static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
1025 -                              size_t count, loff_t *ppos)
1026 -{
1027 -       struct ath_softc *sc = file->private_data;
1028 -       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1029 -       char buf[32];
1030 -       bool start;
1031 -       ssize_t len;
1032 -       int r;
1033 -
1034 -       if (sc->nvifs > 1)
1035 -               return -EOPNOTSUPP;
1036 -
1037 -       len = min(count, sizeof(buf) - 1);
1038 -       if (copy_from_user(buf, user_buf, len))
1039 -               return -EFAULT;
1040 -
1041 -       if (strtobool(buf, &start))
1042 -               return -EINVAL;
1043 -
1044 -       if (start == sc->tx99_state) {
1045 -               if (!start)
1046 -                       return count;
1047 -               ath_dbg(common, XMIT, "Resetting TX99\n");
1048 -               ath9k_tx99_deinit(sc);
1049 -       }
1050 -
1051 -       if (!start) {
1052 -               ath9k_tx99_deinit(sc);
1053 -               return count;
1054 -       }
1055 -
1056 -       r = ath9k_tx99_init(sc);
1057 -       if (r)
1058 -               return r;
1059 -
1060 -       return count;
1061 -}
1062 -
1063 -static const struct file_operations fops_tx99 = {
1064 -       .read = read_file_tx99,
1065 -       .write = write_file_tx99,
1066 -       .open = simple_open,
1067 -       .owner = THIS_MODULE,
1068 -       .llseek = default_llseek,
1069 -};
1070 -
1071 -static ssize_t read_file_tx99_power(struct file *file,
1072 -                                   char __user *user_buf,
1073 -                                   size_t count, loff_t *ppos)
1074 -{
1075 -       struct ath_softc *sc = file->private_data;
1076 -       char buf[32];
1077 -       unsigned int len;
1078 -
1079 -       len = sprintf(buf, "%d (%d dBm)\n",
1080 -                     sc->tx99_power,
1081 -                     sc->tx99_power / 2);
1082 -
1083 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1084 -}
1085 -
1086 -static ssize_t write_file_tx99_power(struct file *file,
1087 -                                    const char __user *user_buf,
1088 -                                    size_t count, loff_t *ppos)
1089 -{
1090 -       struct ath_softc *sc = file->private_data;
1091 -       int r;
1092 -       u8 tx_power;
1093 -
1094 -       r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
1095 -       if (r)
1096 -               return r;
1097 -
1098 -       if (tx_power > MAX_RATE_POWER)
1099 -               return -EINVAL;
1100 -
1101 -       sc->tx99_power = tx_power;
1102 -
1103 -       ath9k_ps_wakeup(sc);
1104 -       ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
1105 -       ath9k_ps_restore(sc);
1106 -
1107 -       return count;
1108 -}
1109 -
1110 -static const struct file_operations fops_tx99_power = {
1111 -       .read = read_file_tx99_power,
1112 -       .write = write_file_tx99_power,
1113 -       .open = simple_open,
1114 -       .owner = THIS_MODULE,
1115 -       .llseek = default_llseek,
1116 -};
1117 -
1118  int ath9k_init_debug(struct ath_hw *ah)
1119  {
1120         struct ath_common *common = ath9k_hw_common(ah);
1121 @@ -1903,6 +1798,7 @@ int ath9k_init_debug(struct ath_hw *ah)
1122  #endif
1123
1124         ath9k_dfs_init_debug(sc);
1125 +       ath9k_tx99_init_debug(sc);
1126
1127         debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
1128                             &fops_dma);
1129 @@ -1978,15 +1874,6 @@ int ath9k_init_debug(struct ath_hw *ah)
1130         debugfs_create_file("btcoex", S_IRUSR, sc->debug.debugfs_phy, sc,
1131                             &fops_btcoex);
1132  #endif
1133 -       if (config_enabled(CPTCFG_ATH9K_TX99) &&
1134 -           AR_SREV_9300_20_OR_LATER(ah)) {
1135 -               debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
1136 -                                   sc->debug.debugfs_phy, sc,
1137 -                                   &fops_tx99);
1138 -               debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
1139 -                                   sc->debug.debugfs_phy, sc,
1140 -                                   &fops_tx99_power);
1141 -       }
1142
1143         return 0;
1144  }
1145 --- a/drivers/net/wireless/ath/ath9k/hw.c
1146 +++ b/drivers/net/wireless/ath/ath9k/hw.c
1147 @@ -17,6 +17,8 @@
1148  #include <linux/io.h>
1149  #include <linux/slab.h>
1150  #include <linux/module.h>
1151 +#include <linux/time.h>
1152 +#include <linux/bitops.h>
1153  #include <asm/unaligned.h>
1154
1155  #include "hw.h"
1156 @@ -438,23 +440,13 @@ static bool ath9k_hw_chip_test(struct at
1157
1158  static void ath9k_hw_init_config(struct ath_hw *ah)
1159  {
1160 -       int i;
1161 -
1162         ah->config.dma_beacon_response_time = 1;
1163         ah->config.sw_beacon_response_time = 6;
1164 -       ah->config.additional_swba_backoff = 0;
1165         ah->config.ack_6mb = 0x0;
1166         ah->config.cwm_ignore_extcca = 0;
1167 -       ah->config.pcie_clock_req = 0;
1168         ah->config.analog_shiftreg = 1;
1169
1170 -       for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1171 -               ah->config.spurchans[i][0] = AR_NO_SPUR;
1172 -               ah->config.spurchans[i][1] = AR_NO_SPUR;
1173 -       }
1174 -
1175         ah->config.rx_intr_mitigation = true;
1176 -       ah->config.pcieSerDesWrite = true;
1177
1178         /*
1179          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
1180 @@ -486,7 +478,6 @@ static void ath9k_hw_init_defaults(struc
1181         ah->hw_version.magic = AR5416_MAGIC;
1182         ah->hw_version.subvendorid = 0;
1183
1184 -       ah->atim_window = 0;
1185         ah->sta_id1_defaults =
1186                 AR_STA_ID1_CRPT_MIC_ENABLE |
1187                 AR_STA_ID1_MCAST_KSRCH;
1188 @@ -549,11 +540,11 @@ static int ath9k_hw_post_init(struct ath
1189          * EEPROM needs to be initialized before we do this.
1190          * This is required for regulatory compliance.
1191          */
1192 -       if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1193 +       if (AR_SREV_9300_20_OR_LATER(ah)) {
1194                 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1195                 if ((regdmn & 0xF0) == CTL_FCC) {
1196 -                       ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ;
1197 -                       ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ;
1198 +                       ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
1199 +                       ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
1200                 }
1201         }
1202
1203 @@ -1502,8 +1493,9 @@ static bool ath9k_hw_channel_change(stru
1204         int r;
1205
1206         if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1207 -               band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
1208 -               mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
1209 +               u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1210 +               band_switch = !!(flags_diff & CHANNEL_5GHZ);
1211 +               mode_diff = !!(flags_diff & ~CHANNEL_HT);
1212         }
1213
1214         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1215 @@ -1815,7 +1807,7 @@ static int ath9k_hw_do_fastcc(struct ath
1216          * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1217          */
1218         if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1219 -           chan->channelFlags != ah->curchan->channelFlags)
1220 +           ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1221                 goto fail;
1222
1223         if (!ath9k_hw_check_alive(ah))
1224 @@ -1856,10 +1848,12 @@ int ath9k_hw_reset(struct ath_hw *ah, st
1225                    struct ath9k_hw_cal_data *caldata, bool fastcc)
1226  {
1227         struct ath_common *common = ath9k_hw_common(ah);
1228 +       struct timespec ts;
1229         u32 saveLedState;
1230         u32 saveDefAntenna;
1231         u32 macStaId1;
1232         u64 tsf = 0;
1233 +       s64 usec = 0;
1234         int r;
1235         bool start_mci_reset = false;
1236         bool save_fullsleep = ah->chip_fullsleep;
1237 @@ -1902,10 +1896,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
1238
1239         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1240
1241 -       /* For chips on which RTC reset is done, save TSF before it gets cleared */
1242 -       if (AR_SREV_9100(ah) ||
1243 -           (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1244 -               tsf = ath9k_hw_gettsf64(ah);
1245 +       /* Save TSF before chip reset, a cold reset clears it */
1246 +       tsf = ath9k_hw_gettsf64(ah);
1247 +       getrawmonotonic(&ts);
1248 +       usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000;
1249
1250         saveLedState = REG_READ(ah, AR_CFG_LED) &
1251                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1252 @@ -1938,8 +1932,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
1253         }
1254
1255         /* Restore TSF */
1256 -       if (tsf)
1257 -               ath9k_hw_settsf64(ah, tsf);
1258 +       getrawmonotonic(&ts);
1259 +       usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec;
1260 +       ath9k_hw_settsf64(ah, tsf + usec);
1261
1262         if (AR_SREV_9280_20_OR_LATER(ah))
1263                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1264 @@ -2261,9 +2256,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
1265         case NL80211_IFTYPE_ADHOC:
1266                 REG_SET_BIT(ah, AR_TXCFG,
1267                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1268 -               REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1269 -                         TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1270 -               flags |= AR_NDP_TIMER_EN;
1271         case NL80211_IFTYPE_MESH_POINT:
1272         case NL80211_IFTYPE_AP:
1273                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1274 @@ -2284,7 +2276,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
1275         REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1276         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1277         REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1278 -       REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1279
1280         REGWRITE_BUFFER_FLUSH(ah);
1281
1282 @@ -2301,12 +2292,9 @@ void ath9k_hw_set_sta_beacon_timers(stru
1283
1284         ENABLE_REGWRITE_BUFFER(ah);
1285
1286 -       REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1287 -
1288 -       REG_WRITE(ah, AR_BEACON_PERIOD,
1289 -                 TU_TO_USEC(bs->bs_intval));
1290 -       REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1291 -                 TU_TO_USEC(bs->bs_intval));
1292 +       REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
1293 +       REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
1294 +       REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
1295
1296         REGWRITE_BUFFER_FLUSH(ah);
1297
1298 @@ -2334,9 +2322,8 @@ void ath9k_hw_set_sta_beacon_timers(stru
1299
1300         ENABLE_REGWRITE_BUFFER(ah);
1301
1302 -       REG_WRITE(ah, AR_NEXT_DTIM,
1303 -                 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1304 -       REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1305 +       REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
1306 +       REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
1307
1308         REG_WRITE(ah, AR_SLEEP1,
1309                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1310 @@ -2350,8 +2337,8 @@ void ath9k_hw_set_sta_beacon_timers(stru
1311         REG_WRITE(ah, AR_SLEEP2,
1312                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1313
1314 -       REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1315 -       REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1316 +       REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
1317 +       REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
1318
1319         REGWRITE_BUFFER_FLUSH(ah);
1320
1321 @@ -2987,20 +2974,6 @@ static const struct ath_gen_timer_config
1322
1323  /* HW generic timer primitives */
1324
1325 -/* compute and clear index of rightmost 1 */
1326 -static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
1327 -{
1328 -       u32 b;
1329 -
1330 -       b = *mask;
1331 -       b &= (0-b);
1332 -       *mask &= ~b;
1333 -       b *= debruijn32;
1334 -       b >>= 27;
1335 -
1336 -       return timer_table->gen_timer_index[b];
1337 -}
1338 -
1339  u32 ath9k_hw_gettsf32(struct ath_hw *ah)
1340  {
1341         return REG_READ(ah, AR_TSF_L32);
1342 @@ -3016,6 +2989,10 @@ struct ath_gen_timer *ath_gen_timer_allo
1343         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1344         struct ath_gen_timer *timer;
1345
1346 +       if ((timer_index < AR_FIRST_NDP_TIMER) ||
1347 +               (timer_index >= ATH_MAX_GEN_TIMER))
1348 +               return NULL;
1349 +
1350         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
1351         if (timer == NULL)
1352                 return NULL;
1353 @@ -3033,23 +3010,13 @@ EXPORT_SYMBOL(ath_gen_timer_alloc);
1354
1355  void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1356                               struct ath_gen_timer *timer,
1357 -                             u32 trig_timeout,
1358 +                             u32 timer_next,
1359                               u32 timer_period)
1360  {
1361         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1362 -       u32 tsf, timer_next;
1363 -
1364 -       BUG_ON(!timer_period);
1365 -
1366 -       set_bit(timer->index, &timer_table->timer_mask.timer_bits);
1367 -
1368 -       tsf = ath9k_hw_gettsf32(ah);
1369 +       u32 mask = 0;
1370
1371 -       timer_next = tsf + trig_timeout;
1372 -
1373 -       ath_dbg(ath9k_hw_common(ah), BTCOEX,
1374 -               "current tsf %x period %x timer_next %x\n",
1375 -               tsf, timer_period, timer_next);
1376 +       timer_table->timer_mask |= BIT(timer->index);
1377
1378         /*
1379          * Program generic timer registers
1380 @@ -3075,10 +3042,19 @@ void ath9k_hw_gen_timer_start(struct ath
1381                                        (1 << timer->index));
1382         }
1383
1384 -       /* Enable both trigger and thresh interrupt masks */
1385 -       REG_SET_BIT(ah, AR_IMR_S5,
1386 -               (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
1387 -               SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
1388 +       if (timer->trigger)
1389 +               mask |= SM(AR_GENTMR_BIT(timer->index),
1390 +                          AR_IMR_S5_GENTIMER_TRIG);
1391 +       if (timer->overflow)
1392 +               mask |= SM(AR_GENTMR_BIT(timer->index),
1393 +                          AR_IMR_S5_GENTIMER_THRESH);
1394 +
1395 +       REG_SET_BIT(ah, AR_IMR_S5, mask);
1396 +
1397 +       if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
1398 +               ah->imask |= ATH9K_INT_GENTIMER;
1399 +               ath9k_hw_set_interrupts(ah);
1400 +       }
1401  }
1402  EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
1403
1404 @@ -3086,11 +3062,6 @@ void ath9k_hw_gen_timer_stop(struct ath_
1405  {
1406         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1407
1408 -       if ((timer->index < AR_FIRST_NDP_TIMER) ||
1409 -               (timer->index >= ATH_MAX_GEN_TIMER)) {
1410 -               return;
1411 -       }
1412 -
1413         /* Clear generic timer enable bits. */
1414         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
1415                         gen_tmr_configuration[timer->index].mode_mask);
1416 @@ -3110,7 +3081,12 @@ void ath9k_hw_gen_timer_stop(struct ath_
1417                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
1418                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
1419
1420 -       clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
1421 +       timer_table->timer_mask &= ~BIT(timer->index);
1422 +
1423 +       if (timer_table->timer_mask == 0) {
1424 +               ah->imask &= ~ATH9K_INT_GENTIMER;
1425 +               ath9k_hw_set_interrupts(ah);
1426 +       }
1427  }
1428  EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
1429
1430 @@ -3131,32 +3107,32 @@ void ath_gen_timer_isr(struct ath_hw *ah
1431  {
1432         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1433         struct ath_gen_timer *timer;
1434 -       struct ath_common *common = ath9k_hw_common(ah);
1435 -       u32 trigger_mask, thresh_mask, index;
1436 +       unsigned long trigger_mask, thresh_mask;
1437 +       unsigned int index;
1438
1439         /* get hardware generic timer interrupt status */
1440         trigger_mask = ah->intr_gen_timer_trigger;
1441         thresh_mask = ah->intr_gen_timer_thresh;
1442 -       trigger_mask &= timer_table->timer_mask.val;
1443 -       thresh_mask &= timer_table->timer_mask.val;
1444 +       trigger_mask &= timer_table->timer_mask;
1445 +       thresh_mask &= timer_table->timer_mask;
1446
1447         trigger_mask &= ~thresh_mask;
1448
1449 -       while (thresh_mask) {
1450 -               index = rightmost_index(timer_table, &thresh_mask);
1451 +       for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
1452                 timer = timer_table->timers[index];
1453 -               BUG_ON(!timer);
1454 -               ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n",
1455 -                       index);
1456 +               if (!timer)
1457 +                   continue;
1458 +               if (!timer->overflow)
1459 +                   continue;
1460                 timer->overflow(timer->arg);
1461         }
1462
1463 -       while (trigger_mask) {
1464 -               index = rightmost_index(timer_table, &trigger_mask);
1465 +       for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
1466                 timer = timer_table->timers[index];
1467 -               BUG_ON(!timer);
1468 -               ath_dbg(common, BTCOEX,
1469 -                       "Gen timer[%d] trigger\n", index);
1470 +               if (!timer)
1471 +                   continue;
1472 +               if (!timer->trigger)
1473 +                   continue;
1474                 timer->trigger(timer->arg);
1475         }
1476  }
1477 --- a/drivers/net/wireless/ath/ath9k/hw.h
1478 +++ b/drivers/net/wireless/ath/ath9k/hw.h
1479 @@ -168,7 +168,7 @@
1480  #define CAB_TIMEOUT_VAL             10
1481  #define BEACON_TIMEOUT_VAL          10
1482  #define MIN_BEACON_TIMEOUT_VAL      1
1483 -#define SLEEP_SLOP                  3
1484 +#define SLEEP_SLOP                  TU_TO_USEC(3)
1485
1486  #define INIT_CONFIG_STATUS          0x00000000
1487  #define INIT_RSSI_THR               0x00000700
1488 @@ -280,11 +280,8 @@ struct ath9k_hw_capabilities {
1489  struct ath9k_ops_config {
1490         int dma_beacon_response_time;
1491         int sw_beacon_response_time;
1492 -       int additional_swba_backoff;
1493         int ack_6mb;
1494         u32 cwm_ignore_extcca;
1495 -       bool pcieSerDesWrite;
1496 -       u8 pcie_clock_req;
1497         u32 pcie_waen;
1498         u8 analog_shiftreg;
1499         u32 ofdm_trig_low;
1500 @@ -295,18 +292,11 @@ struct ath9k_ops_config {
1501         int serialize_regmode;
1502         bool rx_intr_mitigation;
1503         bool tx_intr_mitigation;
1504 -#define SPUR_DISABLE           0
1505 -#define SPUR_ENABLE_IOCTL      1
1506 -#define SPUR_ENABLE_EEPROM     2
1507 -#define AR_SPUR_5413_1         1640
1508 -#define AR_SPUR_5413_2         1200
1509  #define AR_NO_SPUR             0x8000
1510  #define AR_BASE_FREQ_2GHZ      2300
1511  #define AR_BASE_FREQ_5GHZ      4900
1512  #define AR_SPUR_FEEQ_BOUND_HT40 19
1513  #define AR_SPUR_FEEQ_BOUND_HT20 10
1514 -       int spurmode;
1515 -       u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
1516         u8 max_txtrig_level;
1517         u16 ani_poll_interval; /* ANI poll interval in ms */
1518
1519 @@ -316,6 +306,8 @@ struct ath9k_ops_config {
1520         u32 ant_ctrl_comm2g_switch_enable;
1521         bool xatten_margin_cfg;
1522         bool alt_mingainidx;
1523 +       bool no_pll_pwrsave;
1524 +       bool tx_gain_buffalo;
1525  };
1526
1527  enum ath9k_int {
1528 @@ -459,10 +451,6 @@ struct ath9k_beacon_state {
1529         u32 bs_intval;
1530  #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
1531         u32 bs_dtimperiod;
1532 -       u16 bs_cfpperiod;
1533 -       u16 bs_cfpmaxduration;
1534 -       u32 bs_cfpnext;
1535 -       u16 bs_timoffset;
1536         u16 bs_bmissthreshold;
1537         u32 bs_sleepduration;
1538         u32 bs_tsfoor_threshold;
1539 @@ -498,12 +486,6 @@ struct ath9k_hw_version {
1540
1541  #define AR_GENTMR_BIT(_index)  (1 << (_index))
1542
1543 -/*
1544 - * Using de Bruijin sequence to look up 1's index in a 32 bit number
1545 - * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
1546 - */
1547 -#define debruijn32 0x077CB531U
1548 -
1549  struct ath_gen_timer_configuration {
1550         u32 next_addr;
1551         u32 period_addr;
1552 @@ -519,12 +501,8 @@ struct ath_gen_timer {
1553  };
1554
1555  struct ath_gen_timer_table {
1556 -       u32 gen_timer_index[32];
1557         struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
1558 -       union {
1559 -               unsigned long timer_bits;
1560 -               u16 val;
1561 -       } timer_mask;
1562 +       u16 timer_mask;
1563  };
1564
1565  struct ath_hw_antcomb_conf {
1566 @@ -785,7 +763,6 @@ struct ath_hw {
1567         u32 txurn_interrupt_mask;
1568         atomic_t intr_ref_cnt;
1569         bool chip_fullsleep;
1570 -       u32 atim_window;
1571         u32 modes_index;
1572
1573         /* Calibration */
1574 @@ -864,6 +841,7 @@ struct ath_hw {
1575         u32 gpio_mask;
1576         u32 gpio_val;
1577
1578 +       struct ar5416IniArray ini_dfs;
1579         struct ar5416IniArray iniModes;
1580         struct ar5416IniArray iniCommon;
1581         struct ar5416IniArray iniBB_RfGain;
1582 @@ -920,7 +898,7 @@ struct ath_hw {
1583         /* Enterprise mode cap */
1584         u32 ent_mode;
1585
1586 -#ifdef CONFIG_PM_SLEEP
1587 +#ifdef CONFIG_ATH9K_WOW
1588         u32 wow_event_mask;
1589  #endif
1590         bool is_clk_25mhz;
1591 @@ -1126,7 +1104,7 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw
1592  #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */
1593
1594
1595 -#ifdef CONFIG_PM_SLEEP
1596 +#ifdef CONFIG_ATH9K_WOW
1597  const char *ath9k_hw_wow_event_to_string(u32 wow_event);
1598  void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1599                                 u8 *user_mask, int pattern_count,
1600 --- a/drivers/net/wireless/ath/ath9k/init.c
1601 +++ b/drivers/net/wireless/ath/ath9k/init.c
1602 @@ -554,7 +554,7 @@ static void ath9k_init_misc(struct ath_s
1603         sc->spec_config.fft_period = 0xF;
1604  }
1605
1606 -static void ath9k_init_platform(struct ath_softc *sc)
1607 +static void ath9k_init_pcoem_platform(struct ath_softc *sc)
1608  {
1609         struct ath_hw *ah = sc->sc_ah;
1610         struct ath9k_hw_capabilities *pCap = &ah->caps;
1611 @@ -609,6 +609,11 @@ static void ath9k_init_platform(struct a
1612                 ah->config.pcie_waen = 0x0040473b;
1613                 ath_info(common, "Enable WAR for ASPM D3/L1\n");
1614         }
1615 +
1616 +       if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
1617 +               ah->config.no_pll_pwrsave = true;
1618 +               ath_info(common, "Disable PLL PowerSave\n");
1619 +       }
1620  }
1621
1622  static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
1623 @@ -656,6 +661,27 @@ static void ath9k_eeprom_release(struct
1624         release_firmware(sc->sc_ah->eeprom_blob);
1625  }
1626
1627 +static int ath9k_init_soc_platform(struct ath_softc *sc)
1628 +{
1629 +       struct ath9k_platform_data *pdata = sc->dev->platform_data;
1630 +       struct ath_hw *ah = sc->sc_ah;
1631 +       int ret = 0;
1632 +
1633 +       if (!pdata)
1634 +               return 0;
1635 +
1636 +       if (pdata->eeprom_name) {
1637 +               ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
1638 +               if (ret)
1639 +                       return ret;
1640 +       }
1641 +
1642 +       if (pdata->tx_gain_buffalo)
1643 +               ah->config.tx_gain_buffalo = true;
1644 +
1645 +       return ret;
1646 +}
1647 +
1648  static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
1649                             const struct ath_bus_ops *bus_ops)
1650  {
1651 @@ -683,6 +709,7 @@ static int ath9k_init_softc(u16 devid, s
1652         common = ath9k_hw_common(ah);
1653         sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
1654         sc->tx99_power = MAX_RATE_POWER + 1;
1655 +       init_waitqueue_head(&sc->tx_wait);
1656
1657         if (!pdata) {
1658                 ah->ah_flags |= AH_USE_EEPROM;
1659 @@ -708,7 +735,11 @@ static int ath9k_init_softc(u16 devid, s
1660         /*
1661          * Platform quirks.
1662          */
1663 -       ath9k_init_platform(sc);
1664 +       ath9k_init_pcoem_platform(sc);
1665 +
1666 +       ret = ath9k_init_soc_platform(sc);
1667 +       if (ret)
1668 +               return ret;
1669
1670         /*
1671          * Enable WLAN/BT RX Antenna diversity only when:
1672 @@ -722,7 +753,6 @@ static int ath9k_init_softc(u16 devid, s
1673                 common->bt_ant_diversity = 1;
1674
1675         spin_lock_init(&common->cc_lock);
1676 -
1677         spin_lock_init(&sc->sc_serial_rw);
1678         spin_lock_init(&sc->sc_pm_lock);
1679         mutex_init(&sc->mutex);
1680 @@ -730,6 +760,7 @@ static int ath9k_init_softc(u16 devid, s
1681         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1682                      (unsigned long)sc);
1683
1684 +       setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
1685         INIT_WORK(&sc->hw_reset_work, ath_reset_work);
1686         INIT_WORK(&sc->hw_check_work, ath_hw_check);
1687         INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
1688 @@ -743,12 +774,6 @@ static int ath9k_init_softc(u16 devid, s
1689         ath_read_cachesize(common, &csz);
1690         common->cachelsz = csz << 2; /* convert to bytes */
1691
1692 -       if (pdata && pdata->eeprom_name) {
1693 -               ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
1694 -               if (ret)
1695 -                       return ret;
1696 -       }
1697 -
1698         /* Initializes the hardware for all supported chipsets */
1699         ret = ath9k_hw_init(ah);
1700         if (ret)
1701 @@ -845,7 +870,8 @@ static const struct ieee80211_iface_limi
1702  };
1703
1704  static const struct ieee80211_iface_limit if_dfs_limits[] = {
1705 -       { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) },
1706 +       { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) |
1707 +                                BIT(NL80211_IFTYPE_ADHOC) },
1708  };
1709
1710  static const struct ieee80211_iface_combination if_comb[] = {
1711 @@ -862,20 +888,11 @@ static const struct ieee80211_iface_comb
1712                 .max_interfaces = 1,
1713                 .num_different_channels = 1,
1714                 .beacon_int_infra_match = true,
1715 -               .radar_detect_widths =  BIT(NL80211_CHAN_NO_HT) |
1716 -                                       BIT(NL80211_CHAN_HT20),
1717 +               .radar_detect_widths =  BIT(NL80211_CHAN_WIDTH_20_NOHT) |
1718 +                                       BIT(NL80211_CHAN_WIDTH_20),
1719         }
1720  };
1721
1722 -#ifdef CONFIG_PM
1723 -static const struct wiphy_wowlan_support ath9k_wowlan_support = {
1724 -       .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
1725 -       .n_patterns = MAX_NUM_USER_PATTERN,
1726 -       .pattern_min_len = 1,
1727 -       .pattern_max_len = MAX_PATTERN_SIZE,
1728 -};
1729 -#endif
1730 -
1731  void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1732  {
1733         struct ath_hw *ah = sc->sc_ah;
1734 @@ -925,16 +942,6 @@ void ath9k_set_hw_capab(struct ath_softc
1735         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
1736         hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
1737
1738 -#ifdef CONFIG_PM_SLEEP
1739 -       if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
1740 -           (sc->driver_data & ATH9K_PCI_WOW) &&
1741 -           device_can_wakeup(sc->dev))
1742 -               hw->wiphy->wowlan = &ath9k_wowlan_support;
1743 -
1744 -       atomic_set(&sc->wow_sleep_proc_intr, -1);
1745 -       atomic_set(&sc->wow_got_bmiss_intr, -1);
1746 -#endif
1747 -
1748         hw->queues = 4;
1749         hw->max_rates = 4;
1750         hw->channel_change_time = 5000;
1751 @@ -960,6 +967,7 @@ void ath9k_set_hw_capab(struct ath_softc
1752                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1753                         &sc->sbands[IEEE80211_BAND_5GHZ];
1754
1755 +       ath9k_init_wow(hw);
1756         ath9k_reload_chainmask_settings(sc);
1757
1758         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1759 @@ -1058,6 +1066,7 @@ static void ath9k_deinit_softc(struct at
1760                 if (ATH_TXQ_SETUP(sc, i))
1761                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1762
1763 +       del_timer_sync(&sc->sleep_timer);
1764         ath9k_hw_deinit(sc->sc_ah);
1765         if (sc->dfs_detector != NULL)
1766                 sc->dfs_detector->exit(sc->dfs_detector);
1767 --- a/drivers/net/wireless/ath/ath9k/main.c
1768 +++ b/drivers/net/wireless/ath/ath9k/main.c
1769 @@ -82,6 +82,22 @@ static bool ath9k_setpower(struct ath_so
1770         return ret;
1771  }
1772
1773 +void ath_ps_full_sleep(unsigned long data)
1774 +{
1775 +       struct ath_softc *sc = (struct ath_softc *) data;
1776 +       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1777 +       bool reset;
1778 +
1779 +       spin_lock(&common->cc_lock);
1780 +       ath_hw_cycle_counters_update(common);
1781 +       spin_unlock(&common->cc_lock);
1782 +
1783 +       ath9k_hw_setrxabort(sc->sc_ah, 1);
1784 +       ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
1785 +
1786 +       ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
1787 +}
1788 +
1789  void ath9k_ps_wakeup(struct ath_softc *sc)
1790  {
1791         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1792 @@ -92,6 +108,7 @@ void ath9k_ps_wakeup(struct ath_softc *s
1793         if (++sc->ps_usecount != 1)
1794                 goto unlock;
1795
1796 +       del_timer_sync(&sc->sleep_timer);
1797         power_mode = sc->sc_ah->power_mode;
1798         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1799
1800 @@ -117,17 +134,17 @@ void ath9k_ps_restore(struct ath_softc *
1801         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1802         enum ath9k_power_mode mode;
1803         unsigned long flags;
1804 -       bool reset;
1805
1806         spin_lock_irqsave(&sc->sc_pm_lock, flags);
1807         if (--sc->ps_usecount != 0)
1808                 goto unlock;
1809
1810         if (sc->ps_idle) {
1811 -               ath9k_hw_setrxabort(sc->sc_ah, 1);
1812 -               ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
1813 -               mode = ATH9K_PM_FULL_SLEEP;
1814 -       } else if (sc->ps_enabled &&
1815 +               mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
1816 +               goto unlock;
1817 +       }
1818 +
1819 +       if (sc->ps_enabled &&
1820                    !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1821                                      PS_WAIT_FOR_CAB |
1822                                      PS_WAIT_FOR_PSPOLL_DATA |
1823 @@ -163,13 +180,13 @@ static void __ath_cancel_work(struct ath
1824  #endif
1825  }
1826
1827 -static void ath_cancel_work(struct ath_softc *sc)
1828 +void ath_cancel_work(struct ath_softc *sc)
1829  {
1830         __ath_cancel_work(sc);
1831         cancel_work_sync(&sc->hw_reset_work);
1832  }
1833
1834 -static void ath_restart_work(struct ath_softc *sc)
1835 +void ath_restart_work(struct ath_softc *sc)
1836  {
1837         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
1838
1839 @@ -487,8 +504,13 @@ void ath9k_tasklet(unsigned long data)
1840                         ath_tx_edma_tasklet(sc);
1841                 else
1842                         ath_tx_tasklet(sc);
1843 +
1844 +               wake_up(&sc->tx_wait);
1845         }
1846
1847 +       if (status & ATH9K_INT_GENTIMER)
1848 +               ath_gen_timer_isr(sc->sc_ah);
1849 +
1850         ath9k_btcoex_handle_interrupt(sc, status);
1851
1852         /* re-enable hardware interrupt */
1853 @@ -579,7 +601,8 @@ irqreturn_t ath_isr(int irq, void *dev)
1854
1855                 goto chip_reset;
1856         }
1857 -#ifdef CONFIG_PM_SLEEP
1858 +
1859 +#ifdef CONFIG_ATH9K_WOW
1860         if (status & ATH9K_INT_BMISS) {
1861                 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
1862                         ath_dbg(common, ANY, "during WoW we got a BMISS\n");
1863 @@ -588,6 +611,8 @@ irqreturn_t ath_isr(int irq, void *dev)
1864                 }
1865         }
1866  #endif
1867 +
1868 +
1869         if (status & ATH9K_INT_SWBA)
1870                 tasklet_schedule(&sc->bcon_tasklet);
1871
1872 @@ -627,7 +652,7 @@ chip_reset:
1873  #undef SCHED_INTR
1874  }
1875
1876 -static int ath_reset(struct ath_softc *sc)
1877 +int ath_reset(struct ath_softc *sc)
1878  {
1879         int r;
1880
1881 @@ -735,6 +760,8 @@ static int ath9k_start(struct ieee80211_
1882          */
1883         ath9k_cmn_init_crypto(sc->sc_ah);
1884
1885 +       ath9k_hw_reset_tsf(ah);
1886 +
1887         spin_unlock_bh(&sc->sc_pcu_lock);
1888
1889         mutex_unlock(&sc->mutex);
1890 @@ -1817,13 +1844,31 @@ static void ath9k_set_coverage_class(str
1891         mutex_unlock(&sc->mutex);
1892  }
1893
1894 +static bool ath9k_has_tx_pending(struct ath_softc *sc)
1895 +{
1896 +       int i, npend;
1897 +
1898 +       for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1899 +               if (!ATH_TXQ_SETUP(sc, i))
1900 +                       continue;
1901 +
1902 +               if (!sc->tx.txq[i].axq_depth)
1903 +                       continue;
1904 +
1905 +               npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1906 +               if (npend)
1907 +                       break;
1908 +       }
1909 +
1910 +       return !!npend;
1911 +}
1912 +
1913  static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1914  {
1915         struct ath_softc *sc = hw->priv;
1916         struct ath_hw *ah = sc->sc_ah;
1917         struct ath_common *common = ath9k_hw_common(ah);
1918 -       int timeout = 200; /* ms */
1919 -       int i, j;
1920 +       int timeout = HZ / 5; /* 200 ms */
1921         bool drain_txq;
1922
1923         mutex_lock(&sc->mutex);
1924 @@ -1841,25 +1886,9 @@ static void ath9k_flush(struct ieee80211
1925                 return;
1926         }
1927
1928 -       for (j = 0; j < timeout; j++) {
1929 -               bool npend = false;
1930 -
1931 -               if (j)
1932 -                       usleep_range(1000, 2000);
1933 -
1934 -               for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1935 -                       if (!ATH_TXQ_SETUP(sc, i))
1936 -                               continue;
1937 -
1938 -                       npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1939 -
1940 -                       if (npend)
1941 -                               break;
1942 -               }
1943 -
1944 -               if (!npend)
1945 -                   break;
1946 -       }
1947 +       if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
1948 +                              timeout) > 0)
1949 +               drop = false;
1950
1951         if (drop) {
1952                 ath9k_ps_wakeup(sc);
1953 @@ -2021,333 +2050,6 @@ static int ath9k_get_antenna(struct ieee
1954         return 0;
1955  }
1956
1957 -#ifdef CONFIG_PM_SLEEP
1958 -
1959 -static void ath9k_wow_map_triggers(struct ath_softc *sc,
1960 -                                  struct cfg80211_wowlan *wowlan,
1961 -                                  u32 *wow_triggers)
1962 -{
1963 -       if (wowlan->disconnect)
1964 -               *wow_triggers |= AH_WOW_LINK_CHANGE |
1965 -                                AH_WOW_BEACON_MISS;
1966 -       if (wowlan->magic_pkt)
1967 -               *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
1968 -
1969 -       if (wowlan->n_patterns)
1970 -               *wow_triggers |= AH_WOW_USER_PATTERN_EN;
1971 -
1972 -       sc->wow_enabled = *wow_triggers;
1973 -
1974 -}
1975 -
1976 -static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
1977 -{
1978 -       struct ath_hw *ah = sc->sc_ah;
1979 -       struct ath_common *common = ath9k_hw_common(ah);
1980 -       int pattern_count = 0;
1981 -       int i, byte_cnt;
1982 -       u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
1983 -       u8 dis_deauth_mask[MAX_PATTERN_SIZE];
1984 -
1985 -       memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
1986 -       memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
1987 -
1988 -       /*
1989 -        * Create Dissassociate / Deauthenticate packet filter
1990 -        *
1991 -        *     2 bytes        2 byte    6 bytes   6 bytes  6 bytes
1992 -        *  +--------------+----------+---------+--------+--------+----
1993 -        *  + Frame Control+ Duration +   DA    +  SA    +  BSSID +
1994 -        *  +--------------+----------+---------+--------+--------+----
1995 -        *
1996 -        * The above is the management frame format for disassociate/
1997 -        * deauthenticate pattern, from this we need to match the first byte
1998 -        * of 'Frame Control' and DA, SA, and BSSID fields
1999 -        * (skipping 2nd byte of FC and Duration feild.
2000 -        *
2001 -        * Disassociate pattern
2002 -        * --------------------
2003 -        * Frame control = 00 00 1010
2004 -        * DA, SA, BSSID = x:x:x:x:x:x
2005 -        * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2006 -        *                          | x:x:x:x:x:x  -- 22 bytes
2007 -        *
2008 -        * Deauthenticate pattern
2009 -        * ----------------------
2010 -        * Frame control = 00 00 1100
2011 -        * DA, SA, BSSID = x:x:x:x:x:x
2012 -        * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2013 -        *                          | x:x:x:x:x:x  -- 22 bytes
2014 -        */
2015 -
2016 -       /* Create Disassociate Pattern first */
2017 -
2018 -       byte_cnt = 0;
2019 -
2020 -       /* Fill out the mask with all FF's */
2021 -
2022 -       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2023 -               dis_deauth_mask[i] = 0xff;
2024 -
2025 -       /* copy the first byte of frame control field */
2026 -       dis_deauth_pattern[byte_cnt] = 0xa0;
2027 -       byte_cnt++;
2028 -
2029 -       /* skip 2nd byte of frame control and Duration field */
2030 -       byte_cnt += 3;
2031 -
2032 -       /*
2033 -        * need not match the destination mac address, it can be a broadcast
2034 -        * mac address or an unicast to this station
2035 -        */
2036 -       byte_cnt += 6;
2037 -
2038 -       /* copy the source mac address */
2039 -       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2040 -
2041 -       byte_cnt += 6;
2042 -
2043 -       /* copy the bssid, its same as the source mac address */
2044 -
2045 -       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2046 -
2047 -       /* Create Disassociate pattern mask */
2048 -
2049 -       dis_deauth_mask[0] = 0xfe;
2050 -       dis_deauth_mask[1] = 0x03;
2051 -       dis_deauth_mask[2] = 0xc0;
2052 -
2053 -       ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2054 -
2055 -       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2056 -                                  pattern_count, byte_cnt);
2057 -
2058 -       pattern_count++;
2059 -       /*
2060 -        * for de-authenticate pattern, only the first byte of the frame
2061 -        * control field gets changed from 0xA0 to 0xC0
2062 -        */
2063 -       dis_deauth_pattern[0] = 0xC0;
2064 -
2065 -       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2066 -                                  pattern_count, byte_cnt);
2067 -
2068 -}
2069 -
2070 -static void ath9k_wow_add_pattern(struct ath_softc *sc,
2071 -                                 struct cfg80211_wowlan *wowlan)
2072 -{
2073 -       struct ath_hw *ah = sc->sc_ah;
2074 -       struct ath9k_wow_pattern *wow_pattern = NULL;
2075 -       struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
2076 -       int mask_len;
2077 -       s8 i = 0;
2078 -
2079 -       if (!wowlan->n_patterns)
2080 -               return;
2081 -
2082 -       /*
2083 -        * Add the new user configured patterns
2084 -        */
2085 -       for (i = 0; i < wowlan->n_patterns; i++) {
2086 -
2087 -               wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2088 -
2089 -               if (!wow_pattern)
2090 -                       return;
2091 -
2092 -               /*
2093 -                * TODO: convert the generic user space pattern to
2094 -                * appropriate chip specific/802.11 pattern.
2095 -                */
2096 -
2097 -               mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2098 -               memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2099 -               memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2100 -               memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2101 -                      patterns[i].pattern_len);
2102 -               memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2103 -               wow_pattern->pattern_len = patterns[i].pattern_len;
2104 -
2105 -               /*
2106 -                * just need to take care of deauth and disssoc pattern,
2107 -                * make sure we don't overwrite them.
2108 -                */
2109 -
2110 -               ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2111 -                                          wow_pattern->mask_bytes,
2112 -                                          i + 2,
2113 -                                          wow_pattern->pattern_len);
2114 -               kfree(wow_pattern);
2115 -
2116 -       }
2117 -
2118 -}
2119 -
2120 -static int ath9k_suspend(struct ieee80211_hw *hw,
2121 -                        struct cfg80211_wowlan *wowlan)
2122 -{
2123 -       struct ath_softc *sc = hw->priv;
2124 -       struct ath_hw *ah = sc->sc_ah;
2125 -       struct ath_common *common = ath9k_hw_common(ah);
2126 -       u32 wow_triggers_enabled = 0;
2127 -       int ret = 0;
2128 -
2129 -       mutex_lock(&sc->mutex);
2130 -
2131 -       ath_cancel_work(sc);
2132 -       ath_stop_ani(sc);
2133 -       del_timer_sync(&sc->rx_poll_timer);
2134 -
2135 -       if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2136 -               ath_dbg(common, ANY, "Device not present\n");
2137 -               ret = -EINVAL;
2138 -               goto fail_wow;
2139 -       }
2140 -
2141 -       if (WARN_ON(!wowlan)) {
2142 -               ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2143 -               ret = -EINVAL;
2144 -               goto fail_wow;
2145 -       }
2146 -
2147 -       if (!device_can_wakeup(sc->dev)) {
2148 -               ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2149 -               ret = 1;
2150 -               goto fail_wow;
2151 -       }
2152 -
2153 -       /*
2154 -        * none of the sta vifs are associated
2155 -        * and we are not currently handling multivif
2156 -        * cases, for instance we have to seperately
2157 -        * configure 'keep alive frame' for each
2158 -        * STA.
2159 -        */
2160 -
2161 -       if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2162 -               ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2163 -               ret = 1;
2164 -               goto fail_wow;
2165 -       }
2166 -
2167 -       if (sc->nvifs > 1) {
2168 -               ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2169 -               ret = 1;
2170 -               goto fail_wow;
2171 -       }
2172 -
2173 -       ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2174 -
2175 -       ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2176 -               wow_triggers_enabled);
2177 -
2178 -       ath9k_ps_wakeup(sc);
2179 -
2180 -       ath9k_stop_btcoex(sc);
2181 -
2182 -       /*
2183 -        * Enable wake up on recieving disassoc/deauth
2184 -        * frame by default.
2185 -        */
2186 -       ath9k_wow_add_disassoc_deauth_pattern(sc);
2187 -
2188 -       if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2189 -               ath9k_wow_add_pattern(sc, wowlan);
2190 -
2191 -       spin_lock_bh(&sc->sc_pcu_lock);
2192 -       /*
2193 -        * To avoid false wake, we enable beacon miss interrupt only
2194 -        * when we go to sleep. We save the current interrupt mask
2195 -        * so we can restore it after the system wakes up
2196 -        */
2197 -       sc->wow_intr_before_sleep = ah->imask;
2198 -       ah->imask &= ~ATH9K_INT_GLOBAL;
2199 -       ath9k_hw_disable_interrupts(ah);
2200 -       ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2201 -       ath9k_hw_set_interrupts(ah);
2202 -       ath9k_hw_enable_interrupts(ah);
2203 -
2204 -       spin_unlock_bh(&sc->sc_pcu_lock);
2205 -
2206 -       /*
2207 -        * we can now sync irq and kill any running tasklets, since we already
2208 -        * disabled interrupts and not holding a spin lock
2209 -        */
2210 -       synchronize_irq(sc->irq);
2211 -       tasklet_kill(&sc->intr_tq);
2212 -
2213 -       ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2214 -
2215 -       ath9k_ps_restore(sc);
2216 -       ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2217 -       atomic_inc(&sc->wow_sleep_proc_intr);
2218 -
2219 -fail_wow:
2220 -       mutex_unlock(&sc->mutex);
2221 -       return ret;
2222 -}
2223 -
2224 -static int ath9k_resume(struct ieee80211_hw *hw)
2225 -{
2226 -       struct ath_softc *sc = hw->priv;
2227 -       struct ath_hw *ah = sc->sc_ah;
2228 -       struct ath_common *common = ath9k_hw_common(ah);
2229 -       u32 wow_status;
2230 -
2231 -       mutex_lock(&sc->mutex);
2232 -
2233 -       ath9k_ps_wakeup(sc);
2234 -
2235 -       spin_lock_bh(&sc->sc_pcu_lock);
2236 -
2237 -       ath9k_hw_disable_interrupts(ah);
2238 -       ah->imask = sc->wow_intr_before_sleep;
2239 -       ath9k_hw_set_interrupts(ah);
2240 -       ath9k_hw_enable_interrupts(ah);
2241 -
2242 -       spin_unlock_bh(&sc->sc_pcu_lock);
2243 -
2244 -       wow_status = ath9k_hw_wow_wakeup(ah);
2245 -
2246 -       if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2247 -               /*
2248 -                * some devices may not pick beacon miss
2249 -                * as the reason they woke up so we add
2250 -                * that here for that shortcoming.
2251 -                */
2252 -               wow_status |= AH_WOW_BEACON_MISS;
2253 -               atomic_dec(&sc->wow_got_bmiss_intr);
2254 -               ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2255 -       }
2256 -
2257 -       atomic_dec(&sc->wow_sleep_proc_intr);
2258 -
2259 -       if (wow_status) {
2260 -               ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2261 -                       ath9k_hw_wow_event_to_string(wow_status), wow_status);
2262 -       }
2263 -
2264 -       ath_restart_work(sc);
2265 -       ath9k_start_btcoex(sc);
2266 -
2267 -       ath9k_ps_restore(sc);
2268 -       mutex_unlock(&sc->mutex);
2269 -
2270 -       return 0;
2271 -}
2272 -
2273 -static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2274 -{
2275 -       struct ath_softc *sc = hw->priv;
2276 -
2277 -       mutex_lock(&sc->mutex);
2278 -       device_init_wakeup(sc->dev, 1);
2279 -       device_set_wakeup_enable(sc->dev, enabled);
2280 -       mutex_unlock(&sc->mutex);
2281 -}
2282 -
2283 -#endif
2284  static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2285  {
2286         struct ath_softc *sc = hw->priv;
2287 @@ -2373,134 +2075,6 @@ static void ath9k_channel_switch_beacon(
2288         sc->csa_vif = vif;
2289  }
2290
2291 -static void ath9k_tx99_stop(struct ath_softc *sc)
2292 -{
2293 -       struct ath_hw *ah = sc->sc_ah;
2294 -       struct ath_common *common = ath9k_hw_common(ah);
2295 -
2296 -       ath_drain_all_txq(sc);
2297 -       ath_startrecv(sc);
2298 -
2299 -       ath9k_hw_set_interrupts(ah);
2300 -       ath9k_hw_enable_interrupts(ah);
2301 -
2302 -       ieee80211_wake_queues(sc->hw);
2303 -
2304 -       kfree_skb(sc->tx99_skb);
2305 -       sc->tx99_skb = NULL;
2306 -       sc->tx99_state = false;
2307 -
2308 -       ath9k_hw_tx99_stop(sc->sc_ah);
2309 -       ath_dbg(common, XMIT, "TX99 stopped\n");
2310 -}
2311 -
2312 -static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
2313 -{
2314 -       static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
2315 -                              0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
2316 -                              0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
2317 -                              0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
2318 -                              0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
2319 -                              0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
2320 -                              0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
2321 -                              0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
2322 -       u32 len = 1200;
2323 -       struct ieee80211_hw *hw = sc->hw;
2324 -       struct ieee80211_hdr *hdr;
2325 -       struct ieee80211_tx_info *tx_info;
2326 -       struct sk_buff *skb;
2327 -
2328 -       skb = alloc_skb(len, GFP_KERNEL);
2329 -       if (!skb)
2330 -               return NULL;
2331 -
2332 -       skb_put(skb, len);
2333 -
2334 -       memset(skb->data, 0, len);
2335 -
2336 -       hdr = (struct ieee80211_hdr *)skb->data;
2337 -       hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
2338 -       hdr->duration_id = 0;
2339 -
2340 -       memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
2341 -       memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
2342 -       memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
2343 -
2344 -       hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2345 -
2346 -       tx_info = IEEE80211_SKB_CB(skb);
2347 -       memset(tx_info, 0, sizeof(*tx_info));
2348 -       tx_info->band = hw->conf.chandef.chan->band;
2349 -       tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
2350 -       tx_info->control.vif = sc->tx99_vif;
2351 -
2352 -       memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
2353 -
2354 -       return skb;
2355 -}
2356 -
2357 -void ath9k_tx99_deinit(struct ath_softc *sc)
2358 -{
2359 -       ath_reset(sc);
2360 -
2361 -       ath9k_ps_wakeup(sc);
2362 -       ath9k_tx99_stop(sc);
2363 -       ath9k_ps_restore(sc);
2364 -}
2365 -
2366 -int ath9k_tx99_init(struct ath_softc *sc)
2367 -{
2368 -       struct ieee80211_hw *hw = sc->hw;
2369 -       struct ath_hw *ah = sc->sc_ah;
2370 -       struct ath_common *common = ath9k_hw_common(ah);
2371 -       struct ath_tx_control txctl;
2372 -       int r;
2373 -
2374 -       if (sc->sc_flags & SC_OP_INVALID) {
2375 -               ath_err(common,
2376 -                       "driver is in invalid state unable to use TX99");
2377 -               return -EINVAL;
2378 -       }
2379 -
2380 -       sc->tx99_skb = ath9k_build_tx99_skb(sc);
2381 -       if (!sc->tx99_skb)
2382 -               return -ENOMEM;
2383 -
2384 -       memset(&txctl, 0, sizeof(txctl));
2385 -       txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
2386 -
2387 -       ath_reset(sc);
2388 -
2389 -       ath9k_ps_wakeup(sc);
2390 -
2391 -       ath9k_hw_disable_interrupts(ah);
2392 -       atomic_set(&ah->intr_ref_cnt, -1);
2393 -       ath_drain_all_txq(sc);
2394 -       ath_stoprecv(sc);
2395 -
2396 -       sc->tx99_state = true;
2397 -
2398 -       ieee80211_stop_queues(hw);
2399 -
2400 -       if (sc->tx99_power == MAX_RATE_POWER + 1)
2401 -               sc->tx99_power = MAX_RATE_POWER;
2402 -
2403 -       ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
2404 -       r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
2405 -       if (r) {
2406 -               ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
2407 -               return r;
2408 -       }
2409 -
2410 -       ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
2411 -               sc->tx99_power,
2412 -               sc->tx99_power / 2);
2413 -
2414 -       /* We leave the harware awake as it will be chugging on */
2415 -
2416 -       return 0;
2417 -}
2418 -
2419  struct ieee80211_ops ath9k_ops = {
2420         .tx                 = ath9k_tx,
2421         .start              = ath9k_start,
2422 @@ -2531,7 +2105,7 @@ struct ieee80211_ops ath9k_ops = {
2423         .set_antenna        = ath9k_set_antenna,
2424         .get_antenna        = ath9k_get_antenna,
2425
2426 -#ifdef CONFIG_PM_SLEEP
2427 +#ifdef CONFIG_ATH9K_WOW
2428         .suspend            = ath9k_suspend,
2429         .resume             = ath9k_resume,
2430         .set_wakeup         = ath9k_set_wakeup,
2431 --- a/drivers/net/wireless/ath/ath9k/wow.c
2432 +++ b/drivers/net/wireless/ath/ath9k/wow.c
2433 @@ -1,5 +1,5 @@
2434  /*
2435 - * Copyright (c) 2012 Qualcomm Atheros, Inc.
2436 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
2437   *
2438   * Permission to use, copy, modify, and/or distribute this software for any
2439   * purpose with or without fee is hereby granted, provided that the above
2440 @@ -14,409 +14,348 @@
2441   * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
2442   */
2443
2444 -#include <linux/export.h>
2445  #include "ath9k.h"
2446 -#include "reg.h"
2447 -#include "hw-ops.h"
2448
2449 -const char *ath9k_hw_wow_event_to_string(u32 wow_event)
2450 +static const struct wiphy_wowlan_support ath9k_wowlan_support = {
2451 +       .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2452 +       .n_patterns = MAX_NUM_USER_PATTERN,
2453 +       .pattern_min_len = 1,
2454 +       .pattern_max_len = MAX_PATTERN_SIZE,
2455 +};
2456 +
2457 +static void ath9k_wow_map_triggers(struct ath_softc *sc,
2458 +                                  struct cfg80211_wowlan *wowlan,
2459 +                                  u32 *wow_triggers)
2460  {
2461 -       if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
2462 -               return "Magic pattern";
2463 -       if (wow_event & AH_WOW_USER_PATTERN_EN)
2464 -               return "User pattern";
2465 -       if (wow_event & AH_WOW_LINK_CHANGE)
2466 -               return "Link change";
2467 -       if (wow_event & AH_WOW_BEACON_MISS)
2468 -               return "Beacon miss";
2469 +       if (wowlan->disconnect)
2470 +               *wow_triggers |= AH_WOW_LINK_CHANGE |
2471 +                                AH_WOW_BEACON_MISS;
2472 +       if (wowlan->magic_pkt)
2473 +               *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
2474 +
2475 +       if (wowlan->n_patterns)
2476 +               *wow_triggers |= AH_WOW_USER_PATTERN_EN;
2477 +
2478 +       sc->wow_enabled = *wow_triggers;
2479
2480 -       return  "unknown reason";
2481  }
2482 -EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
2483
2484 -static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
2485 +static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
2486  {
2487 +       struct ath_hw *ah = sc->sc_ah;
2488         struct ath_common *common = ath9k_hw_common(ah);
2489 +       int pattern_count = 0;
2490 +       int i, byte_cnt;
2491 +       u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
2492 +       u8 dis_deauth_mask[MAX_PATTERN_SIZE];
2493
2494 -       REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2495 +       memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
2496 +       memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
2497
2498 -       /* set rx disable bit */
2499 -       REG_WRITE(ah, AR_CR, AR_CR_RXD);
2500 +       /*
2501 +        * Create Dissassociate / Deauthenticate packet filter
2502 +        *
2503 +        *     2 bytes        2 byte    6 bytes   6 bytes  6 bytes
2504 +        *  +--------------+----------+---------+--------+--------+----
2505 +        *  + Frame Control+ Duration +   DA    +  SA    +  BSSID +
2506 +        *  +--------------+----------+---------+--------+--------+----
2507 +        *
2508 +        * The above is the management frame format for disassociate/
2509 +        * deauthenticate pattern, from this we need to match the first byte
2510 +        * of 'Frame Control' and DA, SA, and BSSID fields
2511 +        * (skipping 2nd byte of FC and Duration feild.
2512 +        *
2513 +        * Disassociate pattern
2514 +        * --------------------
2515 +        * Frame control = 00 00 1010
2516 +        * DA, SA, BSSID = x:x:x:x:x:x
2517 +        * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2518 +        *                          | x:x:x:x:x:x  -- 22 bytes
2519 +        *
2520 +        * Deauthenticate pattern
2521 +        * ----------------------
2522 +        * Frame control = 00 00 1100
2523 +        * DA, SA, BSSID = x:x:x:x:x:x
2524 +        * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2525 +        *                          | x:x:x:x:x:x  -- 22 bytes
2526 +        */
2527
2528 -       if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
2529 -               ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
2530 -                       REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
2531 -               return;
2532 -       }
2533 +       /* Create Disassociate Pattern first */
2534
2535 -       REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
2536 -}
2537 +       byte_cnt = 0;
2538
2539 -static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
2540 -{
2541 -       struct ath_common *common = ath9k_hw_common(ah);
2542 -       u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
2543 -       u32 ctl[13] = {0};
2544 -       u32 data_word[KAL_NUM_DATA_WORDS];
2545 -       u8 i;
2546 -       u32 wow_ka_data_word0;
2547 -
2548 -       memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
2549 -       memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
2550 -
2551 -       /* set the transmit buffer */
2552 -       ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
2553 -       ctl[1] = 0;
2554 -       ctl[3] = 0xb;   /* OFDM_6M hardware value for this rate */
2555 -       ctl[4] = 0;
2556 -       ctl[7] = (ah->txchainmask) << 2;
2557 -       ctl[2] = 0xf << 16; /* tx_tries 0 */
2558 -
2559 -       for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
2560 -               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
2561 -
2562 -       REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
2563 -
2564 -       data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
2565 -                      (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
2566 -       data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
2567 -                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
2568 -       data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
2569 -                      (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
2570 -       data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
2571 -                      (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
2572 -       data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
2573 -                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
2574 -       data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
2575 -
2576 -       if (AR_SREV_9462_20(ah)) {
2577 -               /* AR9462 2.0 has an extra descriptor word (time based
2578 -                * discard) compared to other chips */
2579 -               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
2580 -               wow_ka_data_word0 = AR_WOW_TXBUF(13);
2581 -       } else {
2582 -               wow_ka_data_word0 = AR_WOW_TXBUF(12);
2583 -       }
2584 +       /* Fill out the mask with all FF's */
2585
2586 -       for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
2587 -               REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
2588 +       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2589 +               dis_deauth_mask[i] = 0xff;
2590
2591 -}
2592 +       /* copy the first byte of frame control field */
2593 +       dis_deauth_pattern[byte_cnt] = 0xa0;
2594 +       byte_cnt++;
2595
2596 -void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
2597 -                               u8 *user_mask, int pattern_count,
2598 -                               int pattern_len)
2599 -{
2600 -       int i;
2601 -       u32 pattern_val, mask_val;
2602 -       u32 set, clr;
2603 +       /* skip 2nd byte of frame control and Duration field */
2604 +       byte_cnt += 3;
2605
2606 -       /* FIXME: should check count by querying the hardware capability */
2607 -       if (pattern_count >= MAX_NUM_PATTERN)
2608 -               return;
2609 +       /*
2610 +        * need not match the destination mac address, it can be a broadcast
2611 +        * mac address or an unicast to this station
2612 +        */
2613 +       byte_cnt += 6;
2614
2615 -       REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
2616 +       /* copy the source mac address */
2617 +       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2618
2619 -       /* set the registers for pattern */
2620 -       for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
2621 -               memcpy(&pattern_val, user_pattern, 4);
2622 -               REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
2623 -                         pattern_val);
2624 -               user_pattern += 4;
2625 -       }
2626 +       byte_cnt += 6;
2627
2628 -       /* set the registers for mask */
2629 -       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
2630 -               memcpy(&mask_val, user_mask, 4);
2631 -               REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
2632 -               user_mask += 4;
2633 -       }
2634 +       /* copy the bssid, its same as the source mac address */
2635
2636 -       /* set the pattern length to be matched
2637 -        *
2638 -        * AR_WOW_LENGTH1_REG1
2639 -        * bit 31:24 pattern 0 length
2640 -        * bit 23:16 pattern 1 length
2641 -        * bit 15:8 pattern 2 length
2642 -        * bit 7:0 pattern 3 length
2643 -        *
2644 -        * AR_WOW_LENGTH1_REG2
2645 -        * bit 31:24 pattern 4 length
2646 -        * bit 23:16 pattern 5 length
2647 -        * bit 15:8 pattern 6 length
2648 -        * bit 7:0 pattern 7 length
2649 -        *
2650 -        * the below logic writes out the new
2651 -        * pattern length for the corresponding
2652 -        * pattern_count, while masking out the
2653 -        * other fields
2654 -        */
2655 +       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2656
2657 -       ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
2658 +       /* Create Disassociate pattern mask */
2659
2660 -       if (pattern_count < 4) {
2661 -               /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
2662 -               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
2663 -                      AR_WOW_LEN1_SHIFT(pattern_count);
2664 -               clr = AR_WOW_LENGTH1_MASK(pattern_count);
2665 -               REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
2666 -       } else {
2667 -               /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
2668 -               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
2669 -                      AR_WOW_LEN2_SHIFT(pattern_count);
2670 -               clr = AR_WOW_LENGTH2_MASK(pattern_count);
2671 -               REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
2672 -       }
2673 +       dis_deauth_mask[0] = 0xfe;
2674 +       dis_deauth_mask[1] = 0x03;
2675 +       dis_deauth_mask[2] = 0xc0;
2676
2677 -}
2678 -EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
2679 +       ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2680
2681 -u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
2682 -{
2683 -       u32 wow_status = 0;
2684 -       u32 val = 0, rval;
2685 +       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2686 +                                  pattern_count, byte_cnt);
2687
2688 +       pattern_count++;
2689         /*
2690 -        * read the WoW status register to know
2691 -        * the wakeup reason
2692 +        * for de-authenticate pattern, only the first byte of the frame
2693 +        * control field gets changed from 0xA0 to 0xC0
2694          */
2695 -       rval = REG_READ(ah, AR_WOW_PATTERN);
2696 -       val = AR_WOW_STATUS(rval);
2697 +       dis_deauth_pattern[0] = 0xC0;
2698
2699 -       /*
2700 -        * mask only the WoW events that we have enabled. Sometimes
2701 -        * we have spurious WoW events from the AR_WOW_PATTERN
2702 -        * register. This mask will clean it up.
2703 -        */
2704 +       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2705 +                                  pattern_count, byte_cnt);
2706
2707 -       val &= ah->wow_event_mask;
2708 +}
2709
2710 -       if (val) {
2711 -               if (val & AR_WOW_MAGIC_PAT_FOUND)
2712 -                       wow_status |= AH_WOW_MAGIC_PATTERN_EN;
2713 -               if (AR_WOW_PATTERN_FOUND(val))
2714 -                       wow_status |= AH_WOW_USER_PATTERN_EN;
2715 -               if (val & AR_WOW_KEEP_ALIVE_FAIL)
2716 -                       wow_status |= AH_WOW_LINK_CHANGE;
2717 -               if (val & AR_WOW_BEACON_FAIL)
2718 -                       wow_status |= AH_WOW_BEACON_MISS;
2719 -       }
2720 +static void ath9k_wow_add_pattern(struct ath_softc *sc,
2721 +                                 struct cfg80211_wowlan *wowlan)
2722 +{
2723 +       struct ath_hw *ah = sc->sc_ah;
2724 +       struct ath9k_wow_pattern *wow_pattern = NULL;
2725 +       struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
2726 +       int mask_len;
2727 +       s8 i = 0;
2728 +
2729 +       if (!wowlan->n_patterns)
2730 +               return;
2731
2732         /*
2733 -        * set and clear WOW_PME_CLEAR registers for the chip to
2734 -        * generate next wow signal.
2735 -        * disable D3 before accessing other registers ?
2736 +        * Add the new user configured patterns
2737          */
2738 +       for (i = 0; i < wowlan->n_patterns; i++) {
2739
2740 -       /* do we need to check the bit value 0x01000000 (7-10) ?? */
2741 -       REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
2742 -               AR_PMCTRL_PWR_STATE_D1D3);
2743 +               wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2744
2745 -       /*
2746 -        * clear all events
2747 -        */
2748 -       REG_WRITE(ah, AR_WOW_PATTERN,
2749 -                 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
2750 +               if (!wow_pattern)
2751 +                       return;
2752
2753 -       /*
2754 -        * restore the beacon threshold to init value
2755 -        */
2756 -       REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2757 +               /*
2758 +                * TODO: convert the generic user space pattern to
2759 +                * appropriate chip specific/802.11 pattern.
2760 +                */
2761
2762 -       /*
2763 -        * Restore the way the PCI-E reset, Power-On-Reset, external
2764 -        * PCIE_POR_SHORT pins are tied to its original value.
2765 -        * Previously just before WoW sleep, we untie the PCI-E
2766 -        * reset to our Chip's Power On Reset so that any PCI-E
2767 -        * reset from the bus will not reset our chip
2768 -        */
2769 -       if (ah->is_pciexpress)
2770 -               ath9k_hw_configpcipowersave(ah, false);
2771 +               mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2772 +               memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2773 +               memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2774 +               memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2775 +                      patterns[i].pattern_len);
2776 +               memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2777 +               wow_pattern->pattern_len = patterns[i].pattern_len;
2778 +
2779 +               /*
2780 +                * just need to take care of deauth and disssoc pattern,
2781 +                * make sure we don't overwrite them.
2782 +                */
2783 +
2784 +               ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2785 +                                          wow_pattern->mask_bytes,
2786 +                                          i + 2,
2787 +                                          wow_pattern->pattern_len);
2788 +               kfree(wow_pattern);
2789
2790 -       ah->wow_event_mask = 0;
2791 +       }
2792
2793 -       return wow_status;
2794  }
2795 -EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
2796
2797 -void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
2798 +int ath9k_suspend(struct ieee80211_hw *hw,
2799 +                 struct cfg80211_wowlan *wowlan)
2800  {
2801 -       u32 wow_event_mask;
2802 -       u32 set, clr;
2803 +       struct ath_softc *sc = hw->priv;
2804 +       struct ath_hw *ah = sc->sc_ah;
2805 +       struct ath_common *common = ath9k_hw_common(ah);
2806 +       u32 wow_triggers_enabled = 0;
2807 +       int ret = 0;
2808
2809 -       /*
2810 -        * wow_event_mask is a mask to the AR_WOW_PATTERN register to
2811 -        * indicate which WoW events we have enabled. The WoW events
2812 -        * are from the 'pattern_enable' in this function and
2813 -        * 'pattern_count' of ath9k_hw_wow_apply_pattern()
2814 -        */
2815 -       wow_event_mask = ah->wow_event_mask;
2816 +       mutex_lock(&sc->mutex);
2817
2818 -       /*
2819 -        * Untie Power-on-Reset from the PCI-E-Reset. When we are in
2820 -        * WOW sleep, we do want the Reset from the PCI-E to disturb
2821 -        * our hw state
2822 -        */
2823 -       if (ah->is_pciexpress) {
2824 -               /*
2825 -                * we need to untie the internal POR (power-on-reset)
2826 -                * to the external PCI-E reset. We also need to tie
2827 -                * the PCI-E Phy reset to the PCI-E reset.
2828 -                */
2829 -               set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
2830 -               clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
2831 -               REG_RMW(ah, AR_WA, set, clr);
2832 +       ath_cancel_work(sc);
2833 +       ath_stop_ani(sc);
2834 +       del_timer_sync(&sc->rx_poll_timer);
2835 +
2836 +       if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2837 +               ath_dbg(common, ANY, "Device not present\n");
2838 +               ret = -EINVAL;
2839 +               goto fail_wow;
2840         }
2841
2842 -       /*
2843 -        * set the power states appropriately and enable PME
2844 -        */
2845 -       set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
2846 -             AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
2847 +       if (WARN_ON(!wowlan)) {
2848 +               ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2849 +               ret = -EINVAL;
2850 +               goto fail_wow;
2851 +       }
2852
2853 -       /*
2854 -        * set and clear WOW_PME_CLEAR registers for the chip
2855 -        * to generate next wow signal.
2856 -        */
2857 -       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
2858 -       clr = AR_PMCTRL_WOW_PME_CLR;
2859 -       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
2860 +       if (!device_can_wakeup(sc->dev)) {
2861 +               ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2862 +               ret = 1;
2863 +               goto fail_wow;
2864 +       }
2865
2866         /*
2867 -        * Setup for:
2868 -        *      - beacon misses
2869 -        *      - magic pattern
2870 -        *      - keep alive timeout
2871 -        *      - pattern matching
2872 +        * none of the sta vifs are associated
2873 +        * and we are not currently handling multivif
2874 +        * cases, for instance we have to seperately
2875 +        * configure 'keep alive frame' for each
2876 +        * STA.
2877          */
2878
2879 -       /*
2880 -        * Program default values for pattern backoff, aifs/slot/KAL count,
2881 -        * beacon miss timeout, KAL timeout, etc.
2882 -        */
2883 -       set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
2884 -       REG_SET_BIT(ah, AR_WOW_PATTERN, set);
2885 +       if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2886 +               ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2887 +               ret = 1;
2888 +               goto fail_wow;
2889 +       }
2890 +
2891 +       if (sc->nvifs > 1) {
2892 +               ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2893 +               ret = 1;
2894 +               goto fail_wow;
2895 +       }
2896
2897 -       set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
2898 -             AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
2899 -             AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
2900 -       REG_SET_BIT(ah, AR_WOW_COUNT, set);
2901 -
2902 -       if (pattern_enable & AH_WOW_BEACON_MISS)
2903 -               set = AR_WOW_BEACON_TIMO;
2904 -       /* We are not using beacon miss, program a large value */
2905 -       else
2906 -               set = AR_WOW_BEACON_TIMO_MAX;
2907 +       ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2908
2909 -       REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
2910 +       ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2911 +               wow_triggers_enabled);
2912
2913 -       /*
2914 -        * Keep alive timo in ms except AR9280
2915 -        */
2916 -       if (!pattern_enable)
2917 -               set = AR_WOW_KEEP_ALIVE_NEVER;
2918 -       else
2919 -               set = KAL_TIMEOUT * 32;
2920 +       ath9k_ps_wakeup(sc);
2921
2922 -       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
2923 +       ath9k_stop_btcoex(sc);
2924
2925         /*
2926 -        * Keep alive delay in us. based on 'power on clock',
2927 -        * therefore in usec
2928 +        * Enable wake up on recieving disassoc/deauth
2929 +        * frame by default.
2930          */
2931 -       set = KAL_DELAY * 1000;
2932 -       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
2933 +       ath9k_wow_add_disassoc_deauth_pattern(sc);
2934
2935 -       /*
2936 -        * Create keep alive pattern to respond to beacons
2937 -        */
2938 -       ath9k_wow_create_keep_alive_pattern(ah);
2939 +       if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2940 +               ath9k_wow_add_pattern(sc, wowlan);
2941
2942 +       spin_lock_bh(&sc->sc_pcu_lock);
2943         /*
2944 -        * Configure MAC WoW Registers
2945 +        * To avoid false wake, we enable beacon miss interrupt only
2946 +        * when we go to sleep. We save the current interrupt mask
2947 +        * so we can restore it after the system wakes up
2948          */
2949 -       set = 0;
2950 -       /* Send keep alive timeouts anyway */
2951 -       clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
2952 -
2953 -       if (pattern_enable & AH_WOW_LINK_CHANGE)
2954 -               wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
2955 -       else
2956 -               set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
2957 +       sc->wow_intr_before_sleep = ah->imask;
2958 +       ah->imask &= ~ATH9K_INT_GLOBAL;
2959 +       ath9k_hw_disable_interrupts(ah);
2960 +       ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2961 +       ath9k_hw_set_interrupts(ah);
2962 +       ath9k_hw_enable_interrupts(ah);
2963
2964 -       set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
2965 -       REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
2966 +       spin_unlock_bh(&sc->sc_pcu_lock);
2967
2968         /*
2969 -        * we are relying on a bmiss failure. ensure we have
2970 -        * enough threshold to prevent false positives
2971 +        * we can now sync irq and kill any running tasklets, since we already
2972 +        * disabled interrupts and not holding a spin lock
2973          */
2974 -       REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
2975 -                     AR_WOW_BMISSTHRESHOLD);
2976 +       synchronize_irq(sc->irq);
2977 +       tasklet_kill(&sc->intr_tq);
2978 +
2979 +       ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2980
2981 -       set = 0;
2982 -       clr = 0;
2983 +       ath9k_ps_restore(sc);
2984 +       ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2985 +       atomic_inc(&sc->wow_sleep_proc_intr);
2986
2987 -       if (pattern_enable & AH_WOW_BEACON_MISS) {
2988 -               set = AR_WOW_BEACON_FAIL_EN;
2989 -               wow_event_mask |= AR_WOW_BEACON_FAIL;
2990 -       } else {
2991 -               clr = AR_WOW_BEACON_FAIL_EN;
2992 +fail_wow:
2993 +       mutex_unlock(&sc->mutex);
2994 +       return ret;
2995 +}
2996 +
2997 +int ath9k_resume(struct ieee80211_hw *hw)
2998 +{
2999 +       struct ath_softc *sc = hw->priv;
3000 +       struct ath_hw *ah = sc->sc_ah;
3001 +       struct ath_common *common = ath9k_hw_common(ah);
3002 +       u32 wow_status;
3003 +
3004 +       mutex_lock(&sc->mutex);
3005 +
3006 +       ath9k_ps_wakeup(sc);
3007 +
3008 +       spin_lock_bh(&sc->sc_pcu_lock);
3009 +
3010 +       ath9k_hw_disable_interrupts(ah);
3011 +       ah->imask = sc->wow_intr_before_sleep;
3012 +       ath9k_hw_set_interrupts(ah);
3013 +       ath9k_hw_enable_interrupts(ah);
3014 +
3015 +       spin_unlock_bh(&sc->sc_pcu_lock);
3016 +
3017 +       wow_status = ath9k_hw_wow_wakeup(ah);
3018 +
3019 +       if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
3020 +               /*
3021 +                * some devices may not pick beacon miss
3022 +                * as the reason they woke up so we add
3023 +                * that here for that shortcoming.
3024 +                */
3025 +               wow_status |= AH_WOW_BEACON_MISS;
3026 +               atomic_dec(&sc->wow_got_bmiss_intr);
3027 +               ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
3028         }
3029
3030 -       REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
3031 +       atomic_dec(&sc->wow_sleep_proc_intr);
3032
3033 -       set = 0;
3034 -       clr = 0;
3035 -       /*
3036 -        * Enable the magic packet registers
3037 -        */
3038 -       if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
3039 -               set = AR_WOW_MAGIC_EN;
3040 -               wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
3041 -       } else {
3042 -               clr = AR_WOW_MAGIC_EN;
3043 +       if (wow_status) {
3044 +               ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
3045 +                       ath9k_hw_wow_event_to_string(wow_status), wow_status);
3046         }
3047 -       set |= AR_WOW_MAC_INTR_EN;
3048 -       REG_RMW(ah, AR_WOW_PATTERN, set, clr);
3049
3050 -       REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
3051 -                 AR_WOW_PATTERN_SUPPORTED);
3052 +       ath_restart_work(sc);
3053 +       ath9k_start_btcoex(sc);
3054
3055 -       /*
3056 -        * Set the power states appropriately and enable PME
3057 -        */
3058 -       clr = 0;
3059 -       set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
3060 -             AR_PMCTRL_PWR_PM_CTRL_ENA;
3061 +       ath9k_ps_restore(sc);
3062 +       mutex_unlock(&sc->mutex);
3063
3064 -       clr = AR_PCIE_PM_CTRL_ENA;
3065 -       REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
3066 +       return 0;
3067 +}
3068
3069 -       /*
3070 -        * this is needed to prevent the chip waking up
3071 -        * the host within 3-4 seconds with certain
3072 -        * platform/BIOS. The fix is to enable
3073 -        * D1 & D3 to match original definition and
3074 -        * also match the OTP value. Anyway this
3075 -        * is more related to SW WOW.
3076 -        */
3077 -       clr = AR_PMCTRL_PWR_STATE_D1D3;
3078 -       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
3079 +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
3080 +{
3081 +       struct ath_softc *sc = hw->priv;
3082
3083 -       set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
3084 -       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
3085 +       mutex_lock(&sc->mutex);
3086 +       device_init_wakeup(sc->dev, 1);
3087 +       device_set_wakeup_enable(sc->dev, enabled);
3088 +       mutex_unlock(&sc->mutex);
3089 +}
3090
3091 -       REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
3092 +void ath9k_init_wow(struct ieee80211_hw *hw)
3093 +{
3094 +       struct ath_softc *sc = hw->priv;
3095
3096 -       /* to bring down WOW power low margin */
3097 -       set = BIT(13);
3098 -       REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
3099 -       /* HW WoW */
3100 -       clr = BIT(5);
3101 -       REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
3102 +       if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
3103 +           (sc->driver_data & ATH9K_PCI_WOW) &&
3104 +           device_can_wakeup(sc->dev))
3105 +               hw->wiphy->wowlan = &ath9k_wowlan_support;
3106
3107 -       ath9k_hw_set_powermode_wow_sleep(ah);
3108 -       ah->wow_event_mask = wow_event_mask;
3109 +       atomic_set(&sc->wow_sleep_proc_intr, -1);
3110 +       atomic_set(&sc->wow_got_bmiss_intr, -1);
3111  }
3112 -EXPORT_SYMBOL(ath9k_hw_wow_enable);
3113 --- a/drivers/net/wireless/ath/ath9k/xmit.c
3114 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
3115 @@ -1276,6 +1276,10 @@ static void ath_tx_fill_desc(struct ath_
3116                                 if (!rts_thresh || (len > rts_thresh))
3117                                         rts = true;
3118                         }
3119 +
3120 +                       if (!aggr)
3121 +                               len = fi->framelen;
3122 +
3123                         ath_buf_set_rate(sc, bf, &info, len, rts);
3124                 }
3125
3126 @@ -1786,6 +1790,9 @@ bool ath_drain_all_txq(struct ath_softc
3127                 if (!ATH_TXQ_SETUP(sc, i))
3128                         continue;
3129
3130 +               if (!sc->tx.txq[i].axq_depth)
3131 +                       continue;
3132 +
3133                 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
3134                         npend |= BIT(i);
3135         }
3136 @@ -2749,6 +2756,8 @@ void ath_tx_node_cleanup(struct ath_soft
3137         }
3138  }
3139
3140 +#ifdef CONFIG_ATH9K_TX99
3141 +
3142  int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
3143                     struct ath_tx_control *txctl)
3144  {
3145 @@ -2791,3 +2800,5 @@ int ath9k_tx99_send(struct ath_softc *sc
3146
3147         return 0;
3148  }
3149 +
3150 +#endif /* CONFIG_ATH9K_TX99 */
3151 --- a/drivers/net/wireless/ath/regd.c
3152 +++ b/drivers/net/wireless/ath/regd.c
3153 @@ -37,17 +37,17 @@ static int __ath_regd_init(struct ath_re
3154
3155  /* We enable active scan on these a case by case basis by regulatory domain */
3156  #define ATH9K_2GHZ_CH12_13     REG_RULE(2467-10, 2472+10, 40, 0, 20,\
3157 -                                       NL80211_RRF_PASSIVE_SCAN)
3158 +                                       NL80211_RRF_NO_IR)
3159  #define ATH9K_2GHZ_CH14                REG_RULE(2484-10, 2484+10, 40, 0, 20,\
3160 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_OFDM)
3161 +                               NL80211_RRF_NO_IR | NL80211_RRF_NO_OFDM)
3162
3163  /* We allow IBSS on these on a case by case basis by regulatory domain */
3164  #define ATH9K_5GHZ_5150_5350   REG_RULE(5150-10, 5350+10, 80, 0, 30,\
3165 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
3166 +                               NL80211_RRF_NO_IR)
3167  #define ATH9K_5GHZ_5470_5850   REG_RULE(5470-10, 5850+10, 80, 0, 30,\
3168 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
3169 +                               NL80211_RRF_NO_IR)
3170  #define ATH9K_5GHZ_5725_5850   REG_RULE(5725-10, 5850+10, 80, 0, 30,\
3171 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
3172 +                               NL80211_RRF_NO_IR)
3173
3174  #define ATH9K_2GHZ_ALL         ATH9K_2GHZ_CH01_11, \
3175                                 ATH9K_2GHZ_CH12_13, \
3176 @@ -224,17 +224,16 @@ ath_reg_apply_beaconing_flags(struct wip
3177                                  * regulatory_hint().
3178                                  */
3179                                 if (!(reg_rule->flags &
3180 -                                   NL80211_RRF_NO_IBSS))
3181 +                                   NL80211_RRF_NO_IR))
3182                                         ch->flags &=
3183 -                                         ~IEEE80211_CHAN_NO_IBSS;
3184 +                                         ~IEEE80211_CHAN_NO_IR;
3185                                 if (!(reg_rule->flags &
3186 -                                   NL80211_RRF_PASSIVE_SCAN))
3187 +                                   NL80211_RRF_NO_IR))
3188                                         ch->flags &=
3189 -                                         ~IEEE80211_CHAN_PASSIVE_SCAN;
3190 +                                         ~IEEE80211_CHAN_NO_IR;
3191                         } else {
3192                                 if (ch->beacon_found)
3193 -                                       ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
3194 -                                         IEEE80211_CHAN_PASSIVE_SCAN);
3195 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
3196                         }
3197                 }
3198         }
3199 @@ -260,11 +259,11 @@ ath_reg_apply_active_scan_flags(struct w
3200          */
3201         if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
3202                 ch = &sband->channels[11]; /* CH 12 */
3203 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3204 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3205 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
3206 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
3207                 ch = &sband->channels[12]; /* CH 13 */
3208 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3209 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3210 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
3211 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
3212                 return;
3213         }
3214
3215 @@ -278,17 +277,17 @@ ath_reg_apply_active_scan_flags(struct w
3216         ch = &sband->channels[11]; /* CH 12 */
3217         reg_rule = freq_reg_info(wiphy, ch->center_freq);
3218         if (!IS_ERR(reg_rule)) {
3219 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
3220 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3221 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3222 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
3223 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
3224 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
3225         }
3226
3227         ch = &sband->channels[12]; /* CH 13 */
3228         reg_rule = freq_reg_info(wiphy, ch->center_freq);
3229         if (!IS_ERR(reg_rule)) {
3230 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
3231 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3232 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3233 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
3234 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
3235 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
3236         }
3237  }
3238
3239 @@ -320,8 +319,8 @@ static void ath_reg_apply_radar_flags(st
3240                  */
3241                 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
3242                         ch->flags |= IEEE80211_CHAN_RADAR |
3243 -                                    IEEE80211_CHAN_NO_IBSS |
3244 -                                    IEEE80211_CHAN_PASSIVE_SCAN;
3245 +                                    IEEE80211_CHAN_NO_IR |
3246 +                                    IEEE80211_CHAN_NO_IR;
3247         }
3248  }
3249
3250 --- a/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
3251 +++ b/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
3252 @@ -812,7 +812,7 @@ static s32 brcmf_p2p_run_escan(struct br
3253                         struct ieee80211_channel *chan = request->channels[i];
3254
3255                         if (chan->flags & (IEEE80211_CHAN_RADAR |
3256 -                                          IEEE80211_CHAN_PASSIVE_SCAN))
3257 +                                          IEEE80211_CHAN_NO_IR))
3258                                 continue;
3259
3260                         chanspecs[i] = channel_to_chanspec(&p2p->cfg->d11inf,
3261 --- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
3262 +++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
3263 @@ -202,9 +202,9 @@ static struct ieee80211_supported_band _
3264
3265  /* This is to override regulatory domains defined in cfg80211 module (reg.c)
3266   * By default world regulatory domain defined in reg.c puts the flags
3267 - * NL80211_RRF_PASSIVE_SCAN and NL80211_RRF_NO_IBSS for 5GHz channels (for
3268 - * 36..48 and 149..165). With respect to these flags, wpa_supplicant doesn't
3269 - * start p2p operations on 5GHz channels. All the changes in world regulatory
3270 + * NL80211_RRF_NO_IR for 5GHz channels (for * 36..48 and 149..165).
3271 + * With respect to these flags, wpa_supplicant doesn't * start p2p
3272 + * operations on 5GHz channels. All the changes in world regulatory
3273   * domain are to be done here.
3274   */
3275  static const struct ieee80211_regdomain brcmf_regdom = {
3276 @@ -5197,10 +5197,10 @@ static s32 brcmf_construct_reginfo(struc
3277                                         if (channel & WL_CHAN_RADAR)
3278                                                 band_chan_arr[index].flags |=
3279                                                         (IEEE80211_CHAN_RADAR |
3280 -                                                       IEEE80211_CHAN_NO_IBSS);
3281 +                                                       IEEE80211_CHAN_NO_IR);
3282                                         if (channel & WL_CHAN_PASSIVE)
3283                                                 band_chan_arr[index].flags |=
3284 -                                                   IEEE80211_CHAN_PASSIVE_SCAN;
3285 +                                                   IEEE80211_CHAN_NO_IR;
3286                                 }
3287                         }
3288                         if (!update)
3289 --- a/drivers/net/wireless/brcm80211/brcmsmac/channel.c
3290 +++ b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
3291 @@ -59,23 +59,20 @@
3292
3293  #define BRCM_2GHZ_2412_2462    REG_RULE(2412-10, 2462+10, 40, 0, 19, 0)
3294  #define BRCM_2GHZ_2467_2472    REG_RULE(2467-10, 2472+10, 20, 0, 19, \
3295 -                                        NL80211_RRF_PASSIVE_SCAN | \
3296 -                                        NL80211_RRF_NO_IBSS)
3297 +                                        NL80211_RRF_NO_IR)
3298
3299  #define BRCM_5GHZ_5180_5240    REG_RULE(5180-10, 5240+10, 40, 0, 21, \
3300 -                                        NL80211_RRF_PASSIVE_SCAN | \
3301 -                                        NL80211_RRF_NO_IBSS)
3302 +                                        NL80211_RRF_NO_IR)
3303  #define BRCM_5GHZ_5260_5320    REG_RULE(5260-10, 5320+10, 40, 0, 21, \
3304 -                                        NL80211_RRF_PASSIVE_SCAN | \
3305 +                                        NL80211_RRF_NO_IR | \
3306                                          NL80211_RRF_DFS | \
3307 -                                        NL80211_RRF_NO_IBSS)
3308 +                                        NL80211_RRF_NO_IR)
3309  #define BRCM_5GHZ_5500_5700    REG_RULE(5500-10, 5700+10, 40, 0, 21, \
3310 -                                        NL80211_RRF_PASSIVE_SCAN | \
3311 +                                        NL80211_RRF_NO_IR | \
3312                                          NL80211_RRF_DFS | \
3313 -                                        NL80211_RRF_NO_IBSS)
3314 +                                        NL80211_RRF_NO_IR)
3315  #define BRCM_5GHZ_5745_5825    REG_RULE(5745-10, 5825+10, 40, 0, 21, \
3316 -                                        NL80211_RRF_PASSIVE_SCAN | \
3317 -                                        NL80211_RRF_NO_IBSS)
3318 +                                        NL80211_RRF_NO_IR)
3319
3320  static const struct ieee80211_regdomain brcms_regdom_x2 = {
3321         .n_reg_rules = 6,
3322 @@ -395,7 +392,7 @@ brcms_c_channel_set_chanspec(struct brcm
3323                 brcms_c_set_gmode(wlc, wlc->protection->gmode_user, false);
3324
3325         brcms_b_set_chanspec(wlc->hw, chanspec,
3326 -                             !!(ch->flags & IEEE80211_CHAN_PASSIVE_SCAN),
3327 +                             !!(ch->flags & IEEE80211_CHAN_NO_IR),
3328                               &txpwr);
3329  }
3330
3331 @@ -657,8 +654,8 @@ static void brcms_reg_apply_radar_flags(
3332                  */
3333                 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
3334                         ch->flags |= IEEE80211_CHAN_RADAR |
3335 -                                    IEEE80211_CHAN_NO_IBSS |
3336 -                                    IEEE80211_CHAN_PASSIVE_SCAN;
3337 +                                    IEEE80211_CHAN_NO_IR |
3338 +                                    IEEE80211_CHAN_NO_IR;
3339         }
3340  }
3341
3342 @@ -688,14 +685,13 @@ brcms_reg_apply_beaconing_flags(struct w
3343                                 if (IS_ERR(rule))
3344                                         continue;
3345
3346 -                               if (!(rule->flags & NL80211_RRF_NO_IBSS))
3347 -                                       ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
3348 -                               if (!(rule->flags & NL80211_RRF_PASSIVE_SCAN))
3349 +                               if (!(rule->flags & NL80211_RRF_NO_IR))
3350 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
3351 +                               if (!(rule->flags & NL80211_RRF_NO_IR))
3352                                         ch->flags &=
3353 -                                               ~IEEE80211_CHAN_PASSIVE_SCAN;
3354 +                                               ~IEEE80211_CHAN_NO_IR;
3355                         } else if (ch->beacon_found) {
3356 -                               ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
3357 -                                              IEEE80211_CHAN_PASSIVE_SCAN);
3358 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
3359                         }
3360                 }
3361         }
3362 --- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
3363 +++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
3364 @@ -125,13 +125,13 @@ static struct ieee80211_channel brcms_2g
3365         CHAN2GHZ(10, 2457, IEEE80211_CHAN_NO_HT40PLUS),
3366         CHAN2GHZ(11, 2462, IEEE80211_CHAN_NO_HT40PLUS),
3367         CHAN2GHZ(12, 2467,
3368 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
3369 +                IEEE80211_CHAN_NO_IR |
3370                  IEEE80211_CHAN_NO_HT40PLUS),
3371         CHAN2GHZ(13, 2472,
3372 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
3373 +                IEEE80211_CHAN_NO_IR |
3374                  IEEE80211_CHAN_NO_HT40PLUS),
3375         CHAN2GHZ(14, 2484,
3376 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
3377 +                IEEE80211_CHAN_NO_IR |
3378                  IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS |
3379                  IEEE80211_CHAN_NO_OFDM)
3380  };
3381 @@ -144,51 +144,51 @@ static struct ieee80211_channel brcms_5g
3382         CHAN5GHZ(48, IEEE80211_CHAN_NO_HT40PLUS),
3383         /* UNII-2 */
3384         CHAN5GHZ(52,
3385 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3386 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3387 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3388 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3389         CHAN5GHZ(56,
3390 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3391 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3392 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3393 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3394         CHAN5GHZ(60,
3395 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3396 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3397 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3398 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3399         CHAN5GHZ(64,
3400 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3401 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3402 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3403 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3404         /* MID */
3405         CHAN5GHZ(100,
3406 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3407 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3408 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3409 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3410         CHAN5GHZ(104,
3411 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3412 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3413 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3414 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3415         CHAN5GHZ(108,
3416 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3417 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3418 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3419 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3420         CHAN5GHZ(112,
3421 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3422 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3423 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3424 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3425         CHAN5GHZ(116,
3426 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3427 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3428 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3429 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3430         CHAN5GHZ(120,
3431 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3432 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3433 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3434 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3435         CHAN5GHZ(124,
3436 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3437 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3438 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3439 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3440         CHAN5GHZ(128,
3441 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3442 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3443 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3444 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3445         CHAN5GHZ(132,
3446 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3447 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3448 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3449 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3450         CHAN5GHZ(136,
3451 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3452 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3453 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3454 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3455         CHAN5GHZ(140,
3456 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3457 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS |
3458 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3459 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS |
3460                  IEEE80211_CHAN_NO_HT40MINUS),
3461         /* UNII-3 */
3462         CHAN5GHZ(149, IEEE80211_CHAN_NO_HT40MINUS),
3463 --- a/drivers/net/wireless/cw1200/scan.c
3464 +++ b/drivers/net/wireless/cw1200/scan.c
3465 @@ -197,9 +197,9 @@ void cw1200_scan_work(struct work_struct
3466                         if ((*it)->band != first->band)
3467                                 break;
3468                         if (((*it)->flags ^ first->flags) &
3469 -                                       IEEE80211_CHAN_PASSIVE_SCAN)
3470 +                                       IEEE80211_CHAN_NO_IR)
3471                                 break;
3472 -                       if (!(first->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
3473 +                       if (!(first->flags & IEEE80211_CHAN_NO_IR) &&
3474                             (*it)->max_power != first->max_power)
3475                                 break;
3476                 }
3477 @@ -210,7 +210,7 @@ void cw1200_scan_work(struct work_struct
3478                 else
3479                         scan.max_tx_rate = WSM_TRANSMIT_RATE_1;
3480                 scan.num_probes =
3481 -                       (first->flags & IEEE80211_CHAN_PASSIVE_SCAN) ? 0 : 2;
3482 +                       (first->flags & IEEE80211_CHAN_NO_IR) ? 0 : 2;
3483                 scan.num_ssids = priv->scan.n_ssids;
3484                 scan.ssids = &priv->scan.ssids[0];
3485                 scan.num_channels = it - priv->scan.curr;
3486 @@ -233,7 +233,7 @@ void cw1200_scan_work(struct work_struct
3487                 }
3488                 for (i = 0; i < scan.num_channels; ++i) {
3489                         scan.ch[i].number = priv->scan.curr[i]->hw_value;
3490 -                       if (priv->scan.curr[i]->flags & IEEE80211_CHAN_PASSIVE_SCAN) {
3491 +                       if (priv->scan.curr[i]->flags & IEEE80211_CHAN_NO_IR) {
3492                                 scan.ch[i].min_chan_time = 50;
3493                                 scan.ch[i].max_chan_time = 100;
3494                         } else {
3495 @@ -241,7 +241,7 @@ void cw1200_scan_work(struct work_struct
3496                                 scan.ch[i].max_chan_time = 25;
3497                         }
3498                 }
3499 -               if (!(first->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
3500 +               if (!(first->flags & IEEE80211_CHAN_NO_IR) &&
3501                     priv->scan.output_power != first->max_power) {
3502                         priv->scan.output_power = first->max_power;
3503                         wsm_set_output_power(priv,
3504 --- a/drivers/net/wireless/ipw2x00/ipw2100.c
3505 +++ b/drivers/net/wireless/ipw2x00/ipw2100.c
3506 @@ -1934,10 +1934,10 @@ static int ipw2100_wdev_init(struct net_
3507                         bg_band->channels[i].max_power = geo->bg[i].max_power;
3508                         if (geo->bg[i].flags & LIBIPW_CH_PASSIVE_ONLY)
3509                                 bg_band->channels[i].flags |=
3510 -                                       IEEE80211_CHAN_PASSIVE_SCAN;
3511 +                                       IEEE80211_CHAN_NO_IR;
3512                         if (geo->bg[i].flags & LIBIPW_CH_NO_IBSS)
3513                                 bg_band->channels[i].flags |=
3514 -                                       IEEE80211_CHAN_NO_IBSS;
3515 +                                       IEEE80211_CHAN_NO_IR;
3516                         if (geo->bg[i].flags & LIBIPW_CH_RADAR_DETECT)
3517                                 bg_band->channels[i].flags |=
3518                                         IEEE80211_CHAN_RADAR;
3519 --- a/drivers/net/wireless/ipw2x00/ipw2200.c
3520 +++ b/drivers/net/wireless/ipw2x00/ipw2200.c
3521 @@ -11472,10 +11472,10 @@ static int ipw_wdev_init(struct net_devi
3522                         bg_band->channels[i].max_power = geo->bg[i].max_power;
3523                         if (geo->bg[i].flags & LIBIPW_CH_PASSIVE_ONLY)
3524                                 bg_band->channels[i].flags |=
3525 -                                       IEEE80211_CHAN_PASSIVE_SCAN;
3526 +                                       IEEE80211_CHAN_NO_IR;
3527                         if (geo->bg[i].flags & LIBIPW_CH_NO_IBSS)
3528                                 bg_band->channels[i].flags |=
3529 -                                       IEEE80211_CHAN_NO_IBSS;
3530 +                                       IEEE80211_CHAN_NO_IR;
3531                         if (geo->bg[i].flags & LIBIPW_CH_RADAR_DETECT)
3532                                 bg_band->channels[i].flags |=
3533                                         IEEE80211_CHAN_RADAR;
3534 @@ -11511,10 +11511,10 @@ static int ipw_wdev_init(struct net_devi
3535                         a_band->channels[i].max_power = geo->a[i].max_power;
3536                         if (geo->a[i].flags & LIBIPW_CH_PASSIVE_ONLY)
3537                                 a_band->channels[i].flags |=
3538 -                                       IEEE80211_CHAN_PASSIVE_SCAN;
3539 +                                       IEEE80211_CHAN_NO_IR;
3540                         if (geo->a[i].flags & LIBIPW_CH_NO_IBSS)
3541                                 a_band->channels[i].flags |=
3542 -                                       IEEE80211_CHAN_NO_IBSS;
3543 +                                       IEEE80211_CHAN_NO_IR;
3544                         if (geo->a[i].flags & LIBIPW_CH_RADAR_DETECT)
3545                                 a_band->channels[i].flags |=
3546                                         IEEE80211_CHAN_RADAR;
3547 --- a/drivers/net/wireless/iwlegacy/3945-mac.c
3548 +++ b/drivers/net/wireless/iwlegacy/3945-mac.c
3549 @@ -1595,7 +1595,7 @@ il3945_get_channels_for_scan(struct il_p
3550                  *  and use long active_dwell time.
3551                  */
3552                 if (!is_active || il_is_channel_passive(ch_info) ||
3553 -                   (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
3554 +                   (chan->flags & IEEE80211_CHAN_NO_IR)) {
3555                         scan_ch->type = 0;      /* passive */
3556                         if (IL_UCODE_API(il->ucode_ver) == 1)
3557                                 scan_ch->active_dwell =
3558 --- a/drivers/net/wireless/iwlegacy/4965-mac.c
3559 +++ b/drivers/net/wireless/iwlegacy/4965-mac.c
3560 @@ -805,7 +805,7 @@ il4965_get_channels_for_scan(struct il_p
3561                 }
3562
3563                 if (!is_active || il_is_channel_passive(ch_info) ||
3564 -                   (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
3565 +                   (chan->flags & IEEE80211_CHAN_NO_IR))
3566                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
3567                 else
3568                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
3569 --- a/drivers/net/wireless/iwlegacy/common.c
3570 +++ b/drivers/net/wireless/iwlegacy/common.c
3571 @@ -3447,10 +3447,10 @@ il_init_geos(struct il_priv *il)
3572
3573                 if (il_is_channel_valid(ch)) {
3574                         if (!(ch->flags & EEPROM_CHANNEL_IBSS))
3575 -                               geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
3576 +                               geo_ch->flags |= IEEE80211_CHAN_NO_IR;
3577
3578                         if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
3579 -                               geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
3580 +                               geo_ch->flags |= IEEE80211_CHAN_NO_IR;
3581
3582                         if (ch->flags & EEPROM_CHANNEL_RADAR)
3583                                 geo_ch->flags |= IEEE80211_CHAN_RADAR;
3584 --- a/drivers/net/wireless/iwlegacy/debug.c
3585 +++ b/drivers/net/wireless/iwlegacy/debug.c
3586 @@ -567,12 +567,12 @@ il_dbgfs_channels_read(struct file *file
3587                                       flags & IEEE80211_CHAN_RADAR ?
3588                                       " (IEEE 802.11h required)" : "",
3589                                       ((channels[i].
3590 -                                       flags & IEEE80211_CHAN_NO_IBSS) ||
3591 +                                       flags & IEEE80211_CHAN_NO_IR) ||
3592                                        (channels[i].
3593                                         flags & IEEE80211_CHAN_RADAR)) ? "" :
3594                                       ", IBSS",
3595                                       channels[i].
3596 -                                     flags & IEEE80211_CHAN_PASSIVE_SCAN ?
3597 +                                     flags & IEEE80211_CHAN_NO_IR ?
3598                                       "passive only" : "active/passive");
3599         }
3600         supp_band = il_get_hw_mode(il, IEEE80211_BAND_5GHZ);
3601 @@ -594,12 +594,12 @@ il_dbgfs_channels_read(struct file *file
3602                                       flags & IEEE80211_CHAN_RADAR ?
3603                                       " (IEEE 802.11h required)" : "",
3604                                       ((channels[i].
3605 -                                       flags & IEEE80211_CHAN_NO_IBSS) ||
3606 +                                       flags & IEEE80211_CHAN_NO_IR) ||
3607                                        (channels[i].
3608                                         flags & IEEE80211_CHAN_RADAR)) ? "" :
3609                                       ", IBSS",
3610                                       channels[i].
3611 -                                     flags & IEEE80211_CHAN_PASSIVE_SCAN ?
3612 +                                     flags & IEEE80211_CHAN_NO_IR ?
3613                                       "passive only" : "active/passive");
3614         }
3615         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
3616 --- a/drivers/net/wireless/iwlwifi/dvm/debugfs.c
3617 +++ b/drivers/net/wireless/iwlwifi/dvm/debugfs.c
3618 @@ -352,12 +352,12 @@ static ssize_t iwl_dbgfs_channels_read(s
3619                                         channels[i].max_power,
3620                                         channels[i].flags & IEEE80211_CHAN_RADAR ?
3621                                         " (IEEE 802.11h required)" : "",
3622 -                                       ((channels[i].flags & IEEE80211_CHAN_NO_IBSS)
3623 +                                       ((channels[i].flags & IEEE80211_CHAN_NO_IR)
3624                                         || (channels[i].flags &
3625                                         IEEE80211_CHAN_RADAR)) ? "" :
3626                                         ", IBSS",
3627                                         channels[i].flags &
3628 -                                       IEEE80211_CHAN_PASSIVE_SCAN ?
3629 +                                       IEEE80211_CHAN_NO_IR ?
3630                                         "passive only" : "active/passive");
3631         }
3632         supp_band = iwl_get_hw_mode(priv, IEEE80211_BAND_5GHZ);
3633 @@ -375,12 +375,12 @@ static ssize_t iwl_dbgfs_channels_read(s
3634                                         channels[i].max_power,
3635                                         channels[i].flags & IEEE80211_CHAN_RADAR ?
3636                                         " (IEEE 802.11h required)" : "",
3637 -                                       ((channels[i].flags & IEEE80211_CHAN_NO_IBSS)
3638 +                                       ((channels[i].flags & IEEE80211_CHAN_NO_IR)
3639                                         || (channels[i].flags &
3640                                         IEEE80211_CHAN_RADAR)) ? "" :
3641                                         ", IBSS",
3642                                         channels[i].flags &
3643 -                                       IEEE80211_CHAN_PASSIVE_SCAN ?
3644 +                                       IEEE80211_CHAN_NO_IR ?
3645                                         "passive only" : "active/passive");
3646         }
3647         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
3648 --- a/drivers/net/wireless/iwlwifi/dvm/scan.c
3649 +++ b/drivers/net/wireless/iwlwifi/dvm/scan.c
3650 @@ -544,7 +544,7 @@ static int iwl_get_channels_for_scan(str
3651                 channel = chan->hw_value;
3652                 scan_ch->channel = cpu_to_le16(channel);
3653
3654 -               if (!is_active || (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
3655 +               if (!is_active || (chan->flags & IEEE80211_CHAN_NO_IR))
3656                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
3657                 else
3658                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
3659 --- a/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
3660 +++ b/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
3661 @@ -614,10 +614,10 @@ static int iwl_init_channel_map(struct d
3662                         channel->flags = IEEE80211_CHAN_NO_HT40;
3663
3664                         if (!(eeprom_ch->flags & EEPROM_CHANNEL_IBSS))
3665 -                               channel->flags |= IEEE80211_CHAN_NO_IBSS;
3666 +                               channel->flags |= IEEE80211_CHAN_NO_IR;
3667
3668                         if (!(eeprom_ch->flags & EEPROM_CHANNEL_ACTIVE))
3669 -                               channel->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
3670 +                               channel->flags |= IEEE80211_CHAN_NO_IR;
3671
3672                         if (eeprom_ch->flags & EEPROM_CHANNEL_RADAR)
3673                                 channel->flags |= IEEE80211_CHAN_RADAR;
3674 --- a/drivers/net/wireless/iwlwifi/iwl-nvm-parse.c
3675 +++ b/drivers/net/wireless/iwlwifi/iwl-nvm-parse.c
3676 @@ -223,10 +223,10 @@ static int iwl_init_channel_map(struct d
3677                         channel->flags |= IEEE80211_CHAN_NO_160MHZ;
3678
3679                 if (!(ch_flags & NVM_CHANNEL_IBSS))
3680 -                       channel->flags |= IEEE80211_CHAN_NO_IBSS;
3681 +                       channel->flags |= IEEE80211_CHAN_NO_IR;
3682
3683                 if (!(ch_flags & NVM_CHANNEL_ACTIVE))
3684 -                       channel->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
3685 +                       channel->flags |= IEEE80211_CHAN_NO_IR;
3686
3687                 if (ch_flags & NVM_CHANNEL_RADAR)
3688                         channel->flags |= IEEE80211_CHAN_RADAR;
3689 --- a/drivers/net/wireless/iwlwifi/mvm/scan.c
3690 +++ b/drivers/net/wireless/iwlwifi/mvm/scan.c
3691 @@ -192,7 +192,7 @@ static void iwl_mvm_scan_fill_channels(s
3692         for (i = 0; i < cmd->channel_count; i++) {
3693                 chan->channel = cpu_to_le16(req->channels[i]->hw_value);
3694                 chan->type = cpu_to_le32(type);
3695 -               if (req->channels[i]->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3696 +               if (req->channels[i]->flags & IEEE80211_CHAN_NO_IR)
3697                         chan->type &= cpu_to_le32(~SCAN_CHANNEL_TYPE_ACTIVE);
3698                 chan->active_dwell = cpu_to_le16(active_dwell);
3699                 chan->passive_dwell = cpu_to_le16(passive_dwell);
3700 @@ -642,7 +642,7 @@ static void iwl_build_channel_cfg(struct
3701                 channels->iter_count[index] = cpu_to_le16(1);
3702                 channels->iter_interval[index] = 0;
3703
3704 -               if (!(s_band->channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
3705 +               if (!(s_band->channels[i].flags & IEEE80211_CHAN_NO_IR))
3706                         channels->type[index] |=
3707                                 cpu_to_le32(IWL_SCAN_OFFLOAD_CHANNEL_ACTIVE);
3708
3709 --- a/drivers/net/wireless/mac80211_hwsim.c
3710 +++ b/drivers/net/wireless/mac80211_hwsim.c
3711 @@ -159,7 +159,7 @@ static const struct ieee80211_regdomain
3712         .reg_rules = {
3713                 REG_RULE(2412-10, 2462+10, 40, 0, 20, 0),
3714                 REG_RULE(5725-10, 5850+10, 40, 0, 30,
3715 -                       NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
3716 +                        NL80211_RRF_NO_IR),
3717         }
3718  };
3719
3720 @@ -1485,7 +1485,7 @@ static void hw_scan_work(struct work_str
3721                     req->channels[hwsim->scan_chan_idx]->center_freq);
3722
3723         hwsim->tmp_chan = req->channels[hwsim->scan_chan_idx];
3724 -       if (hwsim->tmp_chan->flags & IEEE80211_CHAN_PASSIVE_SCAN ||
3725 +       if (hwsim->tmp_chan->flags & IEEE80211_CHAN_NO_IR ||
3726             !req->n_ssids) {
3727                 dwell = 120;
3728         } else {
3729 --- a/drivers/net/wireless/mwifiex/cfg80211.c
3730 +++ b/drivers/net/wireless/mwifiex/cfg80211.c
3731 @@ -50,24 +50,24 @@ static const struct ieee80211_regdomain
3732                 REG_RULE(2412-10, 2462+10, 40, 3, 20, 0),
3733                 /* Channel 12 - 13 */
3734                 REG_RULE(2467-10, 2472+10, 20, 3, 20,
3735 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
3736 +                        NL80211_RRF_NO_IR),
3737                 /* Channel 14 */
3738                 REG_RULE(2484-10, 2484+10, 20, 3, 20,
3739 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
3740 +                        NL80211_RRF_NO_IR |
3741                          NL80211_RRF_NO_OFDM),
3742                 /* Channel 36 - 48 */
3743                 REG_RULE(5180-10, 5240+10, 40, 3, 20,
3744 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
3745 +                        NL80211_RRF_NO_IR),
3746                 /* Channel 149 - 165 */
3747                 REG_RULE(5745-10, 5825+10, 40, 3, 20,
3748 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
3749 +                        NL80211_RRF_NO_IR),
3750                 /* Channel 52 - 64 */
3751                 REG_RULE(5260-10, 5320+10, 40, 3, 30,
3752 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
3753 +                        NL80211_RRF_NO_IR |
3754                          NL80211_RRF_DFS),
3755                 /* Channel 100 - 140 */
3756                 REG_RULE(5500-10, 5700+10, 40, 3, 30,
3757 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
3758 +                        NL80211_RRF_NO_IR |
3759                          NL80211_RRF_DFS),
3760         }
3761  };
3762 @@ -1968,7 +1968,7 @@ mwifiex_cfg80211_scan(struct wiphy *wiph
3763                 user_scan_cfg->chan_list[i].chan_number = chan->hw_value;
3764                 user_scan_cfg->chan_list[i].radio_type = chan->band;
3765
3766 -               if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3767 +               if (chan->flags & IEEE80211_CHAN_NO_IR)
3768                         user_scan_cfg->chan_list[i].scan_type =
3769                                                 MWIFIEX_SCAN_TYPE_PASSIVE;
3770                 else
3771 --- a/drivers/net/wireless/mwifiex/scan.c
3772 +++ b/drivers/net/wireless/mwifiex/scan.c
3773 @@ -515,14 +515,14 @@ mwifiex_scan_create_channel_list(struct
3774                                 scan_chan_list[chan_idx].max_scan_time =
3775                                         cpu_to_le16((u16) user_scan_in->
3776                                         chan_list[0].scan_time);
3777 -                       else if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3778 +                       else if (ch->flags & IEEE80211_CHAN_NO_IR)
3779                                 scan_chan_list[chan_idx].max_scan_time =
3780                                         cpu_to_le16(adapter->passive_scan_time);
3781                         else
3782                                 scan_chan_list[chan_idx].max_scan_time =
3783                                         cpu_to_le16(adapter->active_scan_time);
3784
3785 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3786 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
3787                                 scan_chan_list[chan_idx].chan_scan_mode_bitmap
3788                                         |= MWIFIEX_PASSIVE_SCAN;
3789                         else
3790 --- a/drivers/net/wireless/rt2x00/rt2x00lib.h
3791 +++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
3792 @@ -146,7 +146,7 @@ void rt2x00queue_remove_l2pad(struct sk_
3793   * @local: frame is not from mac80211
3794   */
3795  int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
3796 -                              bool local);
3797 +                              struct ieee80211_sta *sta, bool local);
3798
3799  /**
3800   * rt2x00queue_update_beacon - Send new beacon from mac80211
3801 --- a/drivers/net/wireless/rt2x00/rt2x00mac.c
3802 +++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
3803 @@ -90,7 +90,7 @@ static int rt2x00mac_tx_rts_cts(struct r
3804                                   frag_skb->data, data_length, tx_info,
3805                                   (struct ieee80211_rts *)(skb->data));
3806
3807 -       retval = rt2x00queue_write_tx_frame(queue, skb, true);
3808 +       retval = rt2x00queue_write_tx_frame(queue, skb, NULL, true);
3809         if (retval) {
3810                 dev_kfree_skb_any(skb);
3811                 rt2x00_warn(rt2x00dev, "Failed to send RTS/CTS frame\n");
3812 @@ -151,7 +151,7 @@ void rt2x00mac_tx(struct ieee80211_hw *h
3813                         goto exit_fail;
3814         }
3815
3816 -       if (unlikely(rt2x00queue_write_tx_frame(queue, skb, false)))
3817 +       if (unlikely(rt2x00queue_write_tx_frame(queue, skb, control->sta, false)))
3818                 goto exit_fail;
3819
3820         /*
3821 --- a/drivers/net/wireless/rt2x00/rt2x00queue.c
3822 +++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
3823 @@ -635,7 +635,7 @@ static void rt2x00queue_bar_check(struct
3824  }
3825
3826  int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
3827 -                              bool local)
3828 +                              struct ieee80211_sta *sta, bool local)
3829  {
3830         struct ieee80211_tx_info *tx_info;
3831         struct queue_entry *entry;
3832 @@ -649,7 +649,7 @@ int rt2x00queue_write_tx_frame(struct da
3833          * after that we are free to use the skb->cb array
3834          * for our information.
3835          */
3836 -       rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, NULL);
3837 +       rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, sta);
3838
3839         /*
3840          * All information is retrieved from the skb->cb array,
3841 --- a/drivers/net/wireless/rtl818x/rtl8187/dev.c
3842 +++ b/drivers/net/wireless/rtl818x/rtl8187/dev.c
3843 @@ -416,7 +416,7 @@ static int rtl8187_init_urbs(struct ieee
3844         struct rtl8187_rx_info *info;
3845         int ret = 0;
3846
3847 -       while (skb_queue_len(&priv->rx_queue) < 16) {
3848 +       while (skb_queue_len(&priv->rx_queue) < 32) {
3849                 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
3850                 if (!skb) {
3851                         ret = -ENOMEM;
3852 --- a/drivers/net/wireless/rtlwifi/base.c
3853 +++ b/drivers/net/wireless/rtlwifi/base.c
3854 @@ -1078,8 +1078,8 @@ u8 rtl_is_special_data(struct ieee80211_
3855
3856         ip = (struct iphdr *)((u8 *) skb->data + mac_hdr_len +
3857                               SNAP_SIZE + PROTOC_TYPE_SIZE);
3858 -       ether_type = *(u16 *) ((u8 *) skb->data + mac_hdr_len + SNAP_SIZE);
3859 -       /*      ether_type = ntohs(ether_type); */
3860 +       ether_type = be16_to_cpu(*(__be16 *)((u8 *)skb->data + mac_hdr_len +
3861 +                                            SNAP_SIZE));
3862
3863         if (ETH_P_IP == ether_type) {
3864                 if (IPPROTO_UDP == ip->protocol) {
3865 --- a/drivers/net/wireless/rtlwifi/regd.c
3866 +++ b/drivers/net/wireless/rtlwifi/regd.c
3867 @@ -59,30 +59,27 @@ static struct country_code_to_enum_rd al
3868   */
3869  #define RTL819x_2GHZ_CH12_13   \
3870         REG_RULE(2467-10, 2472+10, 40, 0, 20,\
3871 -       NL80211_RRF_PASSIVE_SCAN)
3872 +       NL80211_RRF_NO_IR)
3873
3874  #define RTL819x_2GHZ_CH14      \
3875         REG_RULE(2484-10, 2484+10, 40, 0, 20, \
3876 -       NL80211_RRF_PASSIVE_SCAN | \
3877 +       NL80211_RRF_NO_IR | \
3878         NL80211_RRF_NO_OFDM)
3879
3880  /* 5G chan 36 - chan 64*/
3881  #define RTL819x_5GHZ_5150_5350 \
3882         REG_RULE(5150-10, 5350+10, 40, 0, 30, \
3883 -       NL80211_RRF_PASSIVE_SCAN | \
3884 -       NL80211_RRF_NO_IBSS)
3885 +       NL80211_RRF_NO_IR)
3886
3887  /* 5G chan 100 - chan 165*/
3888  #define RTL819x_5GHZ_5470_5850 \
3889         REG_RULE(5470-10, 5850+10, 40, 0, 30, \
3890 -       NL80211_RRF_PASSIVE_SCAN | \
3891 -       NL80211_RRF_NO_IBSS)
3892 +       NL80211_RRF_NO_IR)
3893
3894  /* 5G chan 149 - chan 165*/
3895  #define RTL819x_5GHZ_5725_5850 \
3896         REG_RULE(5725-10, 5850+10, 40, 0, 30, \
3897 -       NL80211_RRF_PASSIVE_SCAN | \
3898 -       NL80211_RRF_NO_IBSS)
3899 +       NL80211_RRF_NO_IR)
3900
3901  #define RTL819x_5GHZ_ALL       \
3902         (RTL819x_5GHZ_5150_5350, RTL819x_5GHZ_5470_5850)
3903 @@ -185,16 +182,15 @@ static void _rtl_reg_apply_beaconing_fla
3904                                  *regulatory_hint().
3905                                  */
3906
3907 -                               if (!(reg_rule->flags & NL80211_RRF_NO_IBSS))
3908 -                                       ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
3909 +                               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
3910 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
3911                                 if (!(reg_rule->
3912 -                                    flags & NL80211_RRF_PASSIVE_SCAN))
3913 +                                    flags & NL80211_RRF_NO_IR))
3914                                         ch->flags &=
3915 -                                           ~IEEE80211_CHAN_PASSIVE_SCAN;
3916 +                                           ~IEEE80211_CHAN_NO_IR;
3917                         } else {
3918                                 if (ch->beacon_found)
3919 -                                       ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
3920 -                                                 IEEE80211_CHAN_PASSIVE_SCAN);
3921 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
3922                         }
3923                 }
3924         }
3925 @@ -219,11 +215,11 @@ static void _rtl_reg_apply_active_scan_f
3926          */
3927         if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
3928                 ch = &sband->channels[11];      /* CH 12 */
3929 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3930 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3931 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
3932 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
3933                 ch = &sband->channels[12];      /* CH 13 */
3934 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3935 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3936 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
3937 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
3938                 return;
3939         }
3940
3941 @@ -237,17 +233,17 @@ static void _rtl_reg_apply_active_scan_f
3942         ch = &sband->channels[11];      /* CH 12 */
3943         reg_rule = freq_reg_info(wiphy, ch->center_freq);
3944         if (!IS_ERR(reg_rule)) {
3945 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
3946 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3947 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3948 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
3949 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
3950 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
3951         }
3952
3953         ch = &sband->channels[12];      /* CH 13 */
3954         reg_rule = freq_reg_info(wiphy, ch->center_freq);
3955         if (!IS_ERR(reg_rule)) {
3956 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
3957 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3958 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3959 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
3960 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
3961 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
3962         }
3963  }
3964
3965 @@ -284,8 +280,8 @@ static void _rtl_reg_apply_radar_flags(s
3966                  */
3967                 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
3968                         ch->flags |= IEEE80211_CHAN_RADAR |
3969 -                           IEEE80211_CHAN_NO_IBSS |
3970 -                           IEEE80211_CHAN_PASSIVE_SCAN;
3971 +                           IEEE80211_CHAN_NO_IR |
3972 +                           IEEE80211_CHAN_NO_IR;
3973         }
3974  }
3975
3976 --- a/drivers/net/wireless/ti/wl12xx/scan.c
3977 +++ b/drivers/net/wireless/ti/wl12xx/scan.c
3978 @@ -47,7 +47,7 @@ static int wl1271_get_scan_channels(stru
3979                      * In active scans, we only scan channels not
3980                      * marked as passive.
3981                      */
3982 -                   (passive || !(flags & IEEE80211_CHAN_PASSIVE_SCAN))) {
3983 +                   (passive || !(flags & IEEE80211_CHAN_NO_IR))) {
3984                         wl1271_debug(DEBUG_SCAN, "band %d, center_freq %d ",
3985                                      req->channels[i]->band,
3986                                      req->channels[i]->center_freq);
3987 --- a/drivers/net/wireless/ti/wlcore/cmd.c
3988 +++ b/drivers/net/wireless/ti/wlcore/cmd.c
3989 @@ -1688,7 +1688,7 @@ int wlcore_cmd_regdomain_config_locked(s
3990
3991                         if (channel->flags & (IEEE80211_CHAN_DISABLED |
3992                                               IEEE80211_CHAN_RADAR |
3993 -                                             IEEE80211_CHAN_PASSIVE_SCAN))
3994 +                                             IEEE80211_CHAN_NO_IR))
3995                                 continue;
3996
3997                         ch_bit_idx = wlcore_get_reg_conf_ch_idx(b, ch);
3998 --- a/drivers/net/wireless/ti/wlcore/main.c
3999 +++ b/drivers/net/wireless/ti/wlcore/main.c
4000 @@ -91,8 +91,7 @@ static void wl1271_reg_notify(struct wip
4001                         continue;
4002
4003                 if (ch->flags & IEEE80211_CHAN_RADAR)
4004 -                       ch->flags |= IEEE80211_CHAN_NO_IBSS |
4005 -                                    IEEE80211_CHAN_PASSIVE_SCAN;
4006 +                       ch->flags |= IEEE80211_CHAN_NO_IR;
4007
4008         }
4009
4010 --- a/drivers/net/wireless/ti/wlcore/scan.c
4011 +++ b/drivers/net/wireless/ti/wlcore/scan.c
4012 @@ -189,14 +189,14 @@ wlcore_scan_get_channels(struct wl1271 *
4013                 flags = req_channels[i]->flags;
4014
4015                 if (force_passive)
4016 -                       flags |= IEEE80211_CHAN_PASSIVE_SCAN;
4017 +                       flags |= IEEE80211_CHAN_NO_IR;
4018
4019                 if ((req_channels[i]->band == band) &&
4020                     !(flags & IEEE80211_CHAN_DISABLED) &&
4021                     (!!(flags & IEEE80211_CHAN_RADAR) == radar) &&
4022                     /* if radar is set, we ignore the passive flag */
4023                     (radar ||
4024 -                    !!(flags & IEEE80211_CHAN_PASSIVE_SCAN) == passive)) {
4025 +                    !!(flags & IEEE80211_CHAN_NO_IR) == passive)) {
4026
4027
4028                         if (flags & IEEE80211_CHAN_RADAR) {
4029 @@ -221,7 +221,7 @@ wlcore_scan_get_channels(struct wl1271 *
4030                             (band == IEEE80211_BAND_2GHZ) &&
4031                             (channels[j].channel >= 12) &&
4032                             (channels[j].channel <= 14) &&
4033 -                           (flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
4034 +                           (flags & IEEE80211_CHAN_NO_IR) &&
4035                             !force_passive) {
4036                                 /* pactive channels treated as DFS */
4037                                 channels[j].flags = SCAN_CHANNEL_FLAGS_DFS;
4038 @@ -244,7 +244,7 @@ wlcore_scan_get_channels(struct wl1271 *
4039                                      max_dwell_time_active,
4040                                      flags & IEEE80211_CHAN_RADAR ?
4041                                         ", DFS" : "",
4042 -                                    flags & IEEE80211_CHAN_PASSIVE_SCAN ?
4043 +                                    flags & IEEE80211_CHAN_NO_IR ?
4044                                         ", PASSIVE" : "");
4045                         j++;
4046                 }
4047 --- a/include/net/cfg80211.h
4048 +++ b/include/net/cfg80211.h
4049 @@ -91,9 +91,8 @@ enum ieee80211_band {
4050   * Channel flags set by the regulatory control code.
4051   *
4052   * @IEEE80211_CHAN_DISABLED: This channel is disabled.
4053 - * @IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted
4054 - *     on this channel.
4055 - * @IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel.
4056 + * @IEEE80211_CHAN_NO_IR: do not initiate radiation, this includes
4057 + *     sending probe requests or beaconing.
4058   * @IEEE80211_CHAN_RADAR: Radar detection is required on this channel.
4059   * @IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel
4060   *     is not permitted.
4061 @@ -113,8 +112,8 @@ enum ieee80211_band {
4062   */
4063  enum ieee80211_channel_flags {
4064         IEEE80211_CHAN_DISABLED         = 1<<0,
4065 -       IEEE80211_CHAN_PASSIVE_SCAN     = 1<<1,
4066 -       IEEE80211_CHAN_NO_IBSS          = 1<<2,
4067 +       IEEE80211_CHAN_NO_IR            = 1<<1,
4068 +       /* hole at 1<<2 */
4069         IEEE80211_CHAN_RADAR            = 1<<3,
4070         IEEE80211_CHAN_NO_HT40PLUS      = 1<<4,
4071         IEEE80211_CHAN_NO_HT40MINUS     = 1<<5,
4072 @@ -4149,6 +4148,7 @@ void cfg80211_radar_event(struct wiphy *
4073  /**
4074   * cfg80211_cac_event - Channel availability check (CAC) event
4075   * @netdev: network device
4076 + * @chandef: chandef for the current channel
4077   * @event: type of event
4078   * @gfp: context flags
4079   *
4080 @@ -4157,6 +4157,7 @@ void cfg80211_radar_event(struct wiphy *
4081   * also by full-MAC drivers.
4082   */
4083  void cfg80211_cac_event(struct net_device *netdev,
4084 +                       const struct cfg80211_chan_def *chandef,
4085                         enum nl80211_radar_event event, gfp_t gfp);
4086
4087
4088 @@ -4282,7 +4283,8 @@ bool cfg80211_reg_can_beacon(struct wiph
4089   * @dev: the device which switched channels
4090   * @chandef: the new channel definition
4091   *
4092 - * Acquires wdev_lock, so must only be called from sleepable driver context!
4093 + * Caller must acquire wdev_lock, therefore must only be called from sleepable
4094 + * driver context!
4095   */
4096  void cfg80211_ch_switch_notify(struct net_device *dev,
4097                                struct cfg80211_chan_def *chandef);
4098 --- a/include/uapi/linux/nl80211.h
4099 +++ b/include/uapi/linux/nl80211.h
4100 @@ -1508,6 +1508,12 @@ enum nl80211_commands {
4101   *     to react to radar events, e.g. initiate a channel switch or leave the
4102   *     IBSS network.
4103   *
4104 + * @NL80211_ATTR_SUPPORT_5_MHZ: A flag indicating that the device supports
4105 + *     5 MHz channel bandwidth.
4106 + *
4107 + * @NL80211_ATTR_SUPPORT_10_MHZ: A flag indicating that the device supports
4108 + *     10 MHz channel bandwidth.
4109 + *
4110   * @NL80211_ATTR_MAX: highest attribute number currently defined
4111   * @__NL80211_ATTR_AFTER_LAST: internal use
4112   */
4113 @@ -1824,6 +1830,9 @@ enum nl80211_attrs {
4114
4115         NL80211_ATTR_HANDLE_DFS,
4116
4117 +       NL80211_ATTR_SUPPORT_5_MHZ,
4118 +       NL80211_ATTR_SUPPORT_10_MHZ,
4119 +
4120         /* add attributes here, update the policy in nl80211.c */
4121
4122         __NL80211_ATTR_AFTER_LAST,
4123 @@ -2224,10 +2233,9 @@ enum nl80211_band_attr {
4124   * @NL80211_FREQUENCY_ATTR_FREQ: Frequency in MHz
4125   * @NL80211_FREQUENCY_ATTR_DISABLED: Channel is disabled in current
4126   *     regulatory domain.
4127 - * @NL80211_FREQUENCY_ATTR_PASSIVE_SCAN: Only passive scanning is
4128 - *     permitted on this channel in current regulatory domain.
4129 - * @NL80211_FREQUENCY_ATTR_NO_IBSS: IBSS networks are not permitted
4130 - *     on this channel in current regulatory domain.
4131 + * @NL80211_FREQUENCY_ATTR_NO_IR: no mechanisms that initiate radiation
4132 + *     are permitted on this channel, this includes sending probe
4133 + *     requests, or modes of operation that require beaconing.
4134   * @NL80211_FREQUENCY_ATTR_RADAR: Radar detection is mandatory
4135   *     on this channel in current regulatory domain.
4136   * @NL80211_FREQUENCY_ATTR_MAX_TX_POWER: Maximum transmission power in mBm
4137 @@ -2254,8 +2262,8 @@ enum nl80211_frequency_attr {
4138         __NL80211_FREQUENCY_ATTR_INVALID,
4139         NL80211_FREQUENCY_ATTR_FREQ,
4140         NL80211_FREQUENCY_ATTR_DISABLED,
4141 -       NL80211_FREQUENCY_ATTR_PASSIVE_SCAN,
4142 -       NL80211_FREQUENCY_ATTR_NO_IBSS,
4143 +       NL80211_FREQUENCY_ATTR_NO_IR,
4144 +       __NL80211_FREQUENCY_ATTR_NO_IBSS,
4145         NL80211_FREQUENCY_ATTR_RADAR,
4146         NL80211_FREQUENCY_ATTR_MAX_TX_POWER,
4147         NL80211_FREQUENCY_ATTR_DFS_STATE,
4148 @@ -2271,6 +2279,9 @@ enum nl80211_frequency_attr {
4149  };
4150
4151  #define NL80211_FREQUENCY_ATTR_MAX_TX_POWER NL80211_FREQUENCY_ATTR_MAX_TX_POWER
4152 +#define NL80211_FREQUENCY_ATTR_PASSIVE_SCAN    NL80211_FREQUENCY_ATTR_NO_IR
4153 +#define NL80211_FREQUENCY_ATTR_NO_IBSS         NL80211_FREQUENCY_ATTR_NO_IR
4154 +#define NL80211_FREQUENCY_ATTR_NO_IR           NL80211_FREQUENCY_ATTR_NO_IR
4155
4156  /**
4157   * enum nl80211_bitrate_attr - bitrate attributes
4158 @@ -2413,8 +2424,9 @@ enum nl80211_sched_scan_match_attr {
4159   * @NL80211_RRF_DFS: DFS support is required to be used
4160   * @NL80211_RRF_PTP_ONLY: this is only for Point To Point links
4161   * @NL80211_RRF_PTMP_ONLY: this is only for Point To Multi Point links
4162 - * @NL80211_RRF_PASSIVE_SCAN: passive scan is required
4163 - * @NL80211_RRF_NO_IBSS: no IBSS is allowed
4164 + * @NL80211_RRF_NO_IR: no mechanisms that initiate radiation are allowed,
4165 + *     this includes probe requests or modes of operation that require
4166 + *     beaconing.
4167   */
4168  enum nl80211_reg_rule_flags {
4169         NL80211_RRF_NO_OFDM             = 1<<0,
4170 @@ -2424,10 +2436,17 @@ enum nl80211_reg_rule_flags {
4171         NL80211_RRF_DFS                 = 1<<4,
4172         NL80211_RRF_PTP_ONLY            = 1<<5,
4173         NL80211_RRF_PTMP_ONLY           = 1<<6,
4174 -       NL80211_RRF_PASSIVE_SCAN        = 1<<7,
4175 -       NL80211_RRF_NO_IBSS             = 1<<8,
4176 +       NL80211_RRF_NO_IR               = 1<<7,
4177 +       __NL80211_RRF_NO_IBSS           = 1<<8,
4178  };
4179
4180 +#define NL80211_RRF_PASSIVE_SCAN       NL80211_RRF_NO_IR
4181 +#define NL80211_RRF_NO_IBSS            NL80211_RRF_NO_IR
4182 +#define NL80211_RRF_NO_IR              NL80211_RRF_NO_IR
4183 +
4184 +/* For backport compatibility with older userspace */
4185 +#define NL80211_RRF_NO_IR_ALL          (NL80211_RRF_NO_IR | __NL80211_RRF_NO_IBSS)
4186 +
4187  /**
4188   * enum nl80211_dfs_regions - regulatory DFS regions
4189   *
4190 --- a/net/mac80211/cfg.c
4191 +++ b/net/mac80211/cfg.c
4192 @@ -846,7 +846,7 @@ static int ieee80211_set_probe_resp(stru
4193         if (!resp || !resp_len)
4194                 return 1;
4195
4196 -       old = rtnl_dereference(sdata->u.ap.probe_resp);
4197 +       old = sdata_dereference(sdata->u.ap.probe_resp, sdata);
4198
4199         new = kzalloc(sizeof(struct probe_resp) + resp_len, GFP_KERNEL);
4200         if (!new)
4201 @@ -870,7 +870,8 @@ int ieee80211_assign_beacon(struct ieee8
4202         int size, err;
4203         u32 changed = BSS_CHANGED_BEACON;
4204
4205 -       old = rtnl_dereference(sdata->u.ap.beacon);
4206 +       old = sdata_dereference(sdata->u.ap.beacon, sdata);
4207 +
4208
4209         /* Need to have a beacon head if we don't have one yet */
4210         if (!params->head && !old)
4211 @@ -947,7 +948,7 @@ static int ieee80211_start_ap(struct wip
4212                       BSS_CHANGED_P2P_PS;
4213         int err;
4214
4215 -       old = rtnl_dereference(sdata->u.ap.beacon);
4216 +       old = sdata_dereference(sdata->u.ap.beacon, sdata);
4217         if (old)
4218                 return -EALREADY;
4219
4220 @@ -1001,7 +1002,8 @@ static int ieee80211_start_ap(struct wip
4221
4222         err = drv_start_ap(sdata->local, sdata);
4223         if (err) {
4224 -               old = rtnl_dereference(sdata->u.ap.beacon);
4225 +               old = sdata_dereference(sdata->u.ap.beacon, sdata);
4226 +
4227                 if (old)
4228                         kfree_rcu(old, rcu_head);
4229                 RCU_INIT_POINTER(sdata->u.ap.beacon, NULL);
4230 @@ -1032,7 +1034,7 @@ static int ieee80211_change_beacon(struc
4231         if (sdata->vif.csa_active)
4232                 return -EBUSY;
4233
4234 -       old = rtnl_dereference(sdata->u.ap.beacon);
4235 +       old = sdata_dereference(sdata->u.ap.beacon, sdata);
4236         if (!old)
4237                 return -ENOENT;
4238
4239 @@ -1050,15 +1052,18 @@ static int ieee80211_stop_ap(struct wiph
4240         struct ieee80211_local *local = sdata->local;
4241         struct beacon_data *old_beacon;
4242         struct probe_resp *old_probe_resp;
4243 +       struct cfg80211_chan_def chandef;
4244
4245 -       old_beacon = rtnl_dereference(sdata->u.ap.beacon);
4246 +       old_beacon = sdata_dereference(sdata->u.ap.beacon, sdata);
4247         if (!old_beacon)
4248                 return -ENOENT;
4249 -       old_probe_resp = rtnl_dereference(sdata->u.ap.probe_resp);
4250 +       old_probe_resp = sdata_dereference(sdata->u.ap.probe_resp, sdata);
4251
4252         /* abort any running channel switch */
4253         sdata->vif.csa_active = false;
4254 -       cancel_work_sync(&sdata->csa_finalize_work);
4255 +       kfree(sdata->u.ap.next_beacon);
4256 +       sdata->u.ap.next_beacon = NULL;
4257 +
4258         cancel_work_sync(&sdata->u.ap.request_smps_work);
4259
4260         /* turn off carrier for this interface and dependent VLANs */
4261 @@ -1091,8 +1096,10 @@ static int ieee80211_stop_ap(struct wiph
4262         ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_BEACON_ENABLED);
4263
4264         if (sdata->wdev.cac_started) {
4265 +               chandef = sdata->vif.bss_conf.chandef;
4266                 cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
4267 -               cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_ABORTED,
4268 +               cfg80211_cac_event(sdata->dev, &chandef,
4269 +                                  NL80211_RADAR_CAC_ABORTED,
4270                                    GFP_KERNEL);
4271         }
4272
4273 @@ -1368,7 +1375,7 @@ static int sta_apply_parameters(struct i
4274                         changed |=
4275                               ieee80211_mps_set_sta_local_pm(sta,
4276                                                              params->local_pm);
4277 -               ieee80211_bss_info_change_notify(sdata, changed);
4278 +               ieee80211_mbss_info_change_notify(sdata, changed);
4279  #endif
4280         }
4281
4282 @@ -1953,7 +1960,7 @@ static int ieee80211_change_bss(struct w
4283         enum ieee80211_band band;
4284         u32 changed = 0;
4285
4286 -       if (!rtnl_dereference(sdata->u.ap.beacon))
4287 +       if (!sdata_dereference(sdata->u.ap.beacon, sdata))
4288                 return -ENOENT;
4289
4290         band = ieee80211_get_sdata_band(sdata);
4291 @@ -2964,27 +2971,33 @@ void ieee80211_csa_finalize_work(struct
4292         struct ieee80211_local *local = sdata->local;
4293         int err, changed = 0;
4294
4295 +       sdata_lock(sdata);
4296 +       /* AP might have been stopped while waiting for the lock. */
4297 +       if (!sdata->vif.csa_active)
4298 +               goto unlock;
4299 +
4300         if (!ieee80211_sdata_running(sdata))
4301 -               return;
4302 +               goto unlock;
4303
4304         sdata->radar_required = sdata->csa_radar_required;
4305 -       err = ieee80211_vif_change_channel(sdata, &local->csa_chandef,
4306 -                                          &changed);
4307 +       err = ieee80211_vif_change_channel(sdata, &changed);
4308         if (WARN_ON(err < 0))
4309 -               return;
4310 +               goto unlock;
4311
4312         if (!local->use_chanctx) {
4313 -               local->_oper_chandef = local->csa_chandef;
4314 +               local->_oper_chandef = sdata->csa_chandef;
4315                 ieee80211_hw_config(local, 0);
4316         }
4317
4318         ieee80211_bss_info_change_notify(sdata, changed);
4319
4320 +       sdata->vif.csa_active = false;
4321         switch (sdata->vif.type) {
4322         case NL80211_IFTYPE_AP:
4323                 err = ieee80211_assign_beacon(sdata, sdata->u.ap.next_beacon);
4324                 if (err < 0)
4325 -                       return;
4326 +                       goto unlock;
4327 +
4328                 changed |= err;
4329                 kfree(sdata->u.ap.next_beacon);
4330                 sdata->u.ap.next_beacon = NULL;
4331 @@ -2998,20 +3011,22 @@ void ieee80211_csa_finalize_work(struct
4332         case NL80211_IFTYPE_MESH_POINT:
4333                 err = ieee80211_mesh_finish_csa(sdata);
4334                 if (err < 0)
4335 -                       return;
4336 +                       goto unlock;
4337                 break;
4338  #endif
4339         default:
4340                 WARN_ON(1);
4341 -               return;
4342 +               goto unlock;
4343         }
4344 -       sdata->vif.csa_active = false;
4345
4346         ieee80211_wake_queues_by_reason(&sdata->local->hw,
4347                                         IEEE80211_MAX_QUEUE_MAP,
4348                                         IEEE80211_QUEUE_STOP_REASON_CSA);
4349
4350 -       cfg80211_ch_switch_notify(sdata->dev, &local->csa_chandef);
4351 +       cfg80211_ch_switch_notify(sdata->dev, &sdata->csa_chandef);
4352 +
4353 +unlock:
4354 +       sdata_unlock(sdata);
4355  }
4356
4357  static int ieee80211_channel_switch(struct wiphy *wiphy, struct net_device *dev,
4358 @@ -3024,6 +3039,8 @@ static int ieee80211_channel_switch(stru
4359         struct ieee80211_if_mesh __maybe_unused *ifmsh;
4360         int err, num_chanctx;
4361
4362 +       lockdep_assert_held(&sdata->wdev.mtx);
4363 +
4364         if (!list_empty(&local->roc_list) || local->scanning)
4365                 return -EBUSY;
4366
4367 @@ -3120,9 +3137,17 @@ static int ieee80211_channel_switch(stru
4368                     params->chandef.chan->band)
4369                         return -EINVAL;
4370
4371 +               ifmsh->chsw_init = true;
4372 +               if (!ifmsh->pre_value)
4373 +                       ifmsh->pre_value = 1;
4374 +               else
4375 +                       ifmsh->pre_value++;
4376 +
4377                 err = ieee80211_mesh_csa_beacon(sdata, params, true);
4378 -               if (err < 0)
4379 +               if (err < 0) {
4380 +                       ifmsh->chsw_init = false;
4381                         return err;
4382 +               }
4383                 break;
4384  #endif
4385         default:
4386 @@ -3136,7 +3161,7 @@ static int ieee80211_channel_switch(stru
4387                                 IEEE80211_MAX_QUEUE_MAP,
4388                                 IEEE80211_QUEUE_STOP_REASON_CSA);
4389
4390 -       local->csa_chandef = params->chandef;
4391 +       sdata->csa_chandef = params->chandef;
4392         sdata->vif.csa_active = true;
4393
4394         ieee80211_bss_info_change_notify(sdata, err);
4395 --- a/net/mac80211/iface.c
4396 +++ b/net/mac80211/iface.c
4397 @@ -749,6 +749,7 @@ static void ieee80211_do_stop(struct iee
4398         u32 hw_reconf_flags = 0;
4399         int i, flushed;
4400         struct ps_data *ps;
4401 +       struct cfg80211_chan_def chandef;
4402
4403         clear_bit(SDATA_STATE_RUNNING, &sdata->state);
4404
4405 @@ -828,11 +829,13 @@ static void ieee80211_do_stop(struct iee
4406         cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
4407
4408         if (sdata->wdev.cac_started) {
4409 +               chandef = sdata->vif.bss_conf.chandef;
4410                 WARN_ON(local->suspended);
4411                 mutex_lock(&local->iflist_mtx);
4412                 ieee80211_vif_release_channel(sdata);
4413                 mutex_unlock(&local->iflist_mtx);
4414 -               cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_ABORTED,
4415 +               cfg80211_cac_event(sdata->dev, &chandef,
4416 +                                  NL80211_RADAR_CAC_ABORTED,
4417                                    GFP_KERNEL);
4418         }
4419
4420 @@ -1340,7 +1343,6 @@ static void ieee80211_setup_sdata(struct
4421                 sdata->vif.bss_conf.bssid = NULL;
4422                 break;
4423         case NL80211_IFTYPE_AP_VLAN:
4424 -               break;
4425         case NL80211_IFTYPE_P2P_DEVICE:
4426                 sdata->vif.bss_conf.bssid = sdata->vif.addr;
4427                 break;
4428 --- a/net/mac80211/mlme.c
4429 +++ b/net/mac80211/mlme.c
4430 @@ -886,8 +886,7 @@ static void ieee80211_chswitch_work(stru
4431         if (!ifmgd->associated)
4432                 goto out;
4433
4434 -       ret = ieee80211_vif_change_channel(sdata, &local->csa_chandef,
4435 -                                          &changed);
4436 +       ret = ieee80211_vif_change_channel(sdata, &changed);
4437         if (ret) {
4438                 sdata_info(sdata,
4439                            "vif channel switch failed, disconnecting\n");
4440 @@ -897,7 +896,7 @@ static void ieee80211_chswitch_work(stru
4441         }
4442
4443         if (!local->use_chanctx) {
4444 -               local->_oper_chandef = local->csa_chandef;
4445 +               local->_oper_chandef = sdata->csa_chandef;
4446                 /* Call "hw_config" only if doing sw channel switch.
4447                  * Otherwise update the channel directly
4448                  */
4449 @@ -908,7 +907,7 @@ static void ieee80211_chswitch_work(stru
4450         }
4451
4452         /* XXX: shouldn't really modify cfg80211-owned data! */
4453 -       ifmgd->associated->channel = local->csa_chandef.chan;
4454 +       ifmgd->associated->channel = sdata->csa_chandef.chan;
4455
4456         /* XXX: wait for a beacon first? */
4457         ieee80211_wake_queues_by_reason(&local->hw,
4458 @@ -1035,7 +1034,7 @@ ieee80211_sta_process_chanswitch(struct
4459         }
4460         mutex_unlock(&local->chanctx_mtx);
4461
4462 -       local->csa_chandef = csa_ie.chandef;
4463 +       sdata->csa_chandef = csa_ie.chandef;
4464
4465         if (csa_ie.mode)
4466                 ieee80211_stop_queues_by_reason(&local->hw,
4467 @@ -1398,10 +1397,12 @@ void ieee80211_dfs_cac_timer_work(struct
4468         struct ieee80211_sub_if_data *sdata =
4469                 container_of(delayed_work, struct ieee80211_sub_if_data,
4470                              dfs_cac_timer_work);
4471 +       struct cfg80211_chan_def chandef = sdata->vif.bss_conf.chandef;
4472
4473         ieee80211_vif_release_channel(sdata);
4474 -
4475 -       cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_FINISHED, GFP_KERNEL);
4476 +       cfg80211_cac_event(sdata->dev, &chandef,
4477 +                          NL80211_RADAR_CAC_FINISHED,
4478 +                          GFP_KERNEL);
4479  }
4480
4481  /* MLME */
4482 --- a/net/mac80211/rx.c
4483 +++ b/net/mac80211/rx.c
4484 @@ -729,9 +729,7 @@ static void ieee80211_release_reorder_fr
4485         lockdep_assert_held(&tid_agg_rx->reorder_lock);
4486
4487         while (ieee80211_sn_less(tid_agg_rx->head_seq_num, head_seq_num)) {
4488 -               index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
4489 -                                        tid_agg_rx->ssn) %
4490 -                                                       tid_agg_rx->buf_size;
4491 +               index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
4492                 ieee80211_release_reorder_frame(sdata, tid_agg_rx, index,
4493                                                 frames);
4494         }
4495 @@ -757,8 +755,7 @@ static void ieee80211_sta_reorder_releas
4496         lockdep_assert_held(&tid_agg_rx->reorder_lock);
4497
4498         /* release the buffer until next missing frame */
4499 -       index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
4500 -                                tid_agg_rx->ssn) % tid_agg_rx->buf_size;
4501 +       index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
4502         if (!tid_agg_rx->reorder_buf[index] &&
4503             tid_agg_rx->stored_mpdu_num) {
4504                 /*
4505 @@ -793,15 +790,11 @@ static void ieee80211_sta_reorder_releas
4506         } else while (tid_agg_rx->reorder_buf[index]) {
4507                 ieee80211_release_reorder_frame(sdata, tid_agg_rx, index,
4508                                                 frames);
4509 -               index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
4510 -                                        tid_agg_rx->ssn) %
4511 -                                                       tid_agg_rx->buf_size;
4512 +               index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
4513         }
4514
4515         if (tid_agg_rx->stored_mpdu_num) {
4516 -               j = index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
4517 -                                            tid_agg_rx->ssn) %
4518 -                                                       tid_agg_rx->buf_size;
4519 +               j = index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
4520
4521                 for (; j != (index - 1) % tid_agg_rx->buf_size;
4522                      j = (j + 1) % tid_agg_rx->buf_size) {
4523 @@ -861,8 +854,7 @@ static bool ieee80211_sta_manage_reorder
4524
4525         /* Now the new frame is always in the range of the reordering buffer */
4526
4527 -       index = ieee80211_sn_sub(mpdu_seq_num,
4528 -                                tid_agg_rx->ssn) % tid_agg_rx->buf_size;
4529 +       index = mpdu_seq_num % tid_agg_rx->buf_size;
4530
4531         /* check if we already stored this frame */
4532         if (tid_agg_rx->reorder_buf[index]) {
4533 @@ -911,7 +903,8 @@ static void ieee80211_rx_reorder_ampdu(s
4534         u16 sc;
4535         u8 tid, ack_policy;
4536
4537 -       if (!ieee80211_is_data_qos(hdr->frame_control))
4538 +       if (!ieee80211_is_data_qos(hdr->frame_control) ||
4539 +           is_multicast_ether_addr(hdr->addr1))
4540                 goto dont_reorder;
4541
4542         /*
4543 --- a/net/mac80211/scan.c
4544 +++ b/net/mac80211/scan.c
4545 @@ -526,7 +526,7 @@ static int __ieee80211_start_scan(struct
4546                 ieee80211_hw_config(local, 0);
4547
4548                 if ((req->channels[0]->flags &
4549 -                    IEEE80211_CHAN_PASSIVE_SCAN) ||
4550 +                    IEEE80211_CHAN_NO_IR) ||
4551                     !local->scan_req->n_ssids) {
4552                         next_delay = IEEE80211_PASSIVE_CHANNEL_TIME;
4553                 } else {
4554 @@ -572,7 +572,7 @@ ieee80211_scan_get_channel_time(struct i
4555          * TODO: channel switching also consumes quite some time,
4556          * add that delay as well to get a better estimation
4557          */
4558 -       if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4559 +       if (chan->flags & IEEE80211_CHAN_NO_IR)
4560                 return IEEE80211_PASSIVE_CHANNEL_TIME;
4561         return IEEE80211_PROBE_DELAY + IEEE80211_CHANNEL_TIME;
4562  }
4563 @@ -696,7 +696,7 @@ static void ieee80211_scan_state_set_cha
4564          *
4565          * In any case, it is not necessary for a passive scan.
4566          */
4567 -       if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN ||
4568 +       if (chan->flags & IEEE80211_CHAN_NO_IR ||
4569             !local->scan_req->n_ssids) {
4570                 *next_delay = IEEE80211_PASSIVE_CHANNEL_TIME;
4571                 local->next_scan_state = SCAN_DECISION;
4572 @@ -881,7 +881,7 @@ int ieee80211_request_ibss_scan(struct i
4573                                 struct ieee80211_channel *tmp_ch =
4574                                     &local->hw.wiphy->bands[band]->channels[i];
4575
4576 -                               if (tmp_ch->flags & (IEEE80211_CHAN_NO_IBSS |
4577 +                               if (tmp_ch->flags & (IEEE80211_CHAN_NO_IR |
4578                                                      IEEE80211_CHAN_DISABLED))
4579                                         continue;
4580
4581 @@ -895,7 +895,7 @@ int ieee80211_request_ibss_scan(struct i
4582
4583                 local->int_scan_req->n_channels = n_ch;
4584         } else {
4585 -               if (WARN_ON_ONCE(chan->flags & (IEEE80211_CHAN_NO_IBSS |
4586 +               if (WARN_ON_ONCE(chan->flags & (IEEE80211_CHAN_NO_IR |
4587                                                 IEEE80211_CHAN_DISABLED)))
4588                         goto unlock;
4589
4590 --- a/net/mac80211/tx.c
4591 +++ b/net/mac80211/tx.c
4592 @@ -1728,8 +1728,7 @@ netdev_tx_t ieee80211_monitor_start_xmit
4593          * radar detection by itself. We can do that later by adding a
4594          * monitor flag interfaces used for AP support.
4595          */
4596 -       if ((chan->flags & (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_RADAR |
4597 -                           IEEE80211_CHAN_PASSIVE_SCAN)))
4598 +       if ((chan->flags & (IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_RADAR)))
4599                 goto fail_rcu;
4600
4601         ieee80211_xmit(sdata, skb, chan->band);
4602 --- a/net/mac80211/util.c
4603 +++ b/net/mac80211/util.c
4604 @@ -2259,14 +2259,17 @@ u64 ieee80211_calculate_rx_timestamp(str
4605  void ieee80211_dfs_cac_cancel(struct ieee80211_local *local)
4606  {
4607         struct ieee80211_sub_if_data *sdata;
4608 +       struct cfg80211_chan_def chandef;
4609
4610         mutex_lock(&local->iflist_mtx);
4611         list_for_each_entry(sdata, &local->interfaces, list) {
4612                 cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
4613
4614                 if (sdata->wdev.cac_started) {
4615 +                       chandef = sdata->vif.bss_conf.chandef;
4616                         ieee80211_vif_release_channel(sdata);
4617                         cfg80211_cac_event(sdata->dev,
4618 +                                          &chandef,
4619                                            NL80211_RADAR_CAC_ABORTED,
4620                                            GFP_KERNEL);
4621                 }
4622 @@ -2459,14 +2462,9 @@ int ieee80211_send_action_csa(struct iee
4623                           WLAN_EID_CHAN_SWITCH_PARAM_TX_RESTRICT : 0x00;
4624                 put_unaligned_le16(WLAN_REASON_MESH_CHAN, pos); /* Reason Cd */
4625                 pos += 2;
4626 -               if (!ifmsh->pre_value)
4627 -                       ifmsh->pre_value = 1;
4628 -               else
4629 -                       ifmsh->pre_value++;
4630                 pre_value = cpu_to_le16(ifmsh->pre_value);
4631                 memcpy(pos, &pre_value, 2);             /* Precedence Value */
4632                 pos += 2;
4633 -               ifmsh->chsw_init = true;
4634         }
4635
4636         ieee80211_tx_skb(sdata, skb);
4637 --- a/net/wireless/chan.c
4638 +++ b/net/wireless/chan.c
4639 @@ -277,6 +277,32 @@ void cfg80211_set_dfs_state(struct wiphy
4640                                      width, dfs_state);
4641  }
4642
4643 +static u32 cfg80211_get_start_freq(u32 center_freq,
4644 +                                  u32 bandwidth)
4645 +{
4646 +       u32 start_freq;
4647 +
4648 +       if (bandwidth <= 20)
4649 +               start_freq = center_freq;
4650 +       else
4651 +               start_freq = center_freq - bandwidth/2 + 10;
4652 +
4653 +       return start_freq;
4654 +}
4655 +
4656 +static u32 cfg80211_get_end_freq(u32 center_freq,
4657 +                                u32 bandwidth)
4658 +{
4659 +       u32 end_freq;
4660 +
4661 +       if (bandwidth <= 20)
4662 +               end_freq = center_freq;
4663 +       else
4664 +               end_freq = center_freq + bandwidth/2 - 10;
4665 +
4666 +       return end_freq;
4667 +}
4668 +
4669  static int cfg80211_get_chans_dfs_required(struct wiphy *wiphy,
4670                                             u32 center_freq,
4671                                             u32 bandwidth)
4672 @@ -284,13 +310,8 @@ static int cfg80211_get_chans_dfs_requir
4673         struct ieee80211_channel *c;
4674         u32 freq, start_freq, end_freq;
4675
4676 -       if (bandwidth <= 20) {
4677 -               start_freq = center_freq;
4678 -               end_freq = center_freq;
4679 -       } else {
4680 -               start_freq = center_freq - bandwidth/2 + 10;
4681 -               end_freq = center_freq + bandwidth/2 - 10;
4682 -       }
4683 +       start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
4684 +       end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
4685
4686         for (freq = start_freq; freq <= end_freq; freq += 20) {
4687                 c = ieee80211_get_channel(wiphy, freq);
4688 @@ -330,33 +351,159 @@ int cfg80211_chandef_dfs_required(struct
4689  }
4690  EXPORT_SYMBOL(cfg80211_chandef_dfs_required);
4691
4692 -static bool cfg80211_secondary_chans_ok(struct wiphy *wiphy,
4693 -                                       u32 center_freq, u32 bandwidth,
4694 -                                       u32 prohibited_flags)
4695 +static int cfg80211_get_chans_dfs_usable(struct wiphy *wiphy,
4696 +                                        u32 center_freq,
4697 +                                        u32 bandwidth)
4698  {
4699         struct ieee80211_channel *c;
4700         u32 freq, start_freq, end_freq;
4701 +       int count = 0;
4702
4703 -       if (bandwidth <= 20) {
4704 -               start_freq = center_freq;
4705 -               end_freq = center_freq;
4706 -       } else {
4707 -               start_freq = center_freq - bandwidth/2 + 10;
4708 -               end_freq = center_freq + bandwidth/2 - 10;
4709 +       start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
4710 +       end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
4711 +
4712 +       /*
4713 +        * Check entire range of channels for the bandwidth.
4714 +        * Check all channels are DFS channels (DFS_USABLE or
4715 +        * DFS_AVAILABLE). Return number of usable channels
4716 +        * (require CAC). Allow DFS and non-DFS channel mix.
4717 +        */
4718 +       for (freq = start_freq; freq <= end_freq; freq += 20) {
4719 +               c = ieee80211_get_channel(wiphy, freq);
4720 +               if (!c)
4721 +                       return -EINVAL;
4722 +
4723 +               if (c->flags & IEEE80211_CHAN_DISABLED)
4724 +                       return -EINVAL;
4725 +
4726 +               if (c->flags & IEEE80211_CHAN_RADAR) {
4727 +                       if (c->dfs_state == NL80211_DFS_UNAVAILABLE)
4728 +                               return -EINVAL;
4729 +
4730 +                       if (c->dfs_state == NL80211_DFS_USABLE)
4731 +                               count++;
4732 +               }
4733 +       }
4734 +
4735 +       return count;
4736 +}
4737 +
4738 +bool cfg80211_chandef_dfs_usable(struct wiphy *wiphy,
4739 +                                const struct cfg80211_chan_def *chandef)
4740 +{
4741 +       int width;
4742 +       int r1, r2 = 0;
4743 +
4744 +       if (WARN_ON(!cfg80211_chandef_valid(chandef)))
4745 +               return false;
4746 +
4747 +       width = cfg80211_chandef_get_width(chandef);
4748 +       if (width < 0)
4749 +               return false;
4750 +
4751 +       r1 = cfg80211_get_chans_dfs_usable(wiphy, chandef->center_freq1,
4752 +                                         width);
4753 +
4754 +       if (r1 < 0)
4755 +               return false;
4756 +
4757 +       switch (chandef->width) {
4758 +       case NL80211_CHAN_WIDTH_80P80:
4759 +               WARN_ON(!chandef->center_freq2);
4760 +               r2 = cfg80211_get_chans_dfs_usable(wiphy,
4761 +                                                  chandef->center_freq2,
4762 +                                                  width);
4763 +               if (r2 < 0)
4764 +                       return false;
4765 +               break;
4766 +       default:
4767 +               WARN_ON(chandef->center_freq2);
4768 +               break;
4769         }
4770
4771 +       return (r1 + r2 > 0);
4772 +}
4773 +
4774 +
4775 +static bool cfg80211_get_chans_dfs_available(struct wiphy *wiphy,
4776 +                                            u32 center_freq,
4777 +                                            u32 bandwidth)
4778 +{
4779 +       struct ieee80211_channel *c;
4780 +       u32 freq, start_freq, end_freq;
4781 +
4782 +       start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
4783 +       end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
4784 +
4785 +       /*
4786 +        * Check entire range of channels for the bandwidth.
4787 +        * If any channel in between is disabled or has not
4788 +        * had gone through CAC return false
4789 +        */
4790         for (freq = start_freq; freq <= end_freq; freq += 20) {
4791                 c = ieee80211_get_channel(wiphy, freq);
4792                 if (!c)
4793                         return false;
4794
4795 -               /* check for radar flags */
4796 -               if ((prohibited_flags & c->flags & IEEE80211_CHAN_RADAR) &&
4797 +               if (c->flags & IEEE80211_CHAN_DISABLED)
4798 +                       return false;
4799 +
4800 +               if ((c->flags & IEEE80211_CHAN_RADAR)  &&
4801                     (c->dfs_state != NL80211_DFS_AVAILABLE))
4802                         return false;
4803 +       }
4804 +
4805 +       return true;
4806 +}
4807 +
4808 +static bool cfg80211_chandef_dfs_available(struct wiphy *wiphy,
4809 +                               const struct cfg80211_chan_def *chandef)
4810 +{
4811 +       int width;
4812 +       int r;
4813 +
4814 +       if (WARN_ON(!cfg80211_chandef_valid(chandef)))
4815 +               return false;
4816
4817 -               /* check for the other flags */
4818 -               if (c->flags & prohibited_flags & ~IEEE80211_CHAN_RADAR)
4819 +       width = cfg80211_chandef_get_width(chandef);
4820 +       if (width < 0)
4821 +               return false;
4822 +
4823 +       r = cfg80211_get_chans_dfs_available(wiphy, chandef->center_freq1,
4824 +                                            width);
4825 +
4826 +       /* If any of channels unavailable for cf1 just return */
4827 +       if (!r)
4828 +               return r;
4829 +
4830 +       switch (chandef->width) {
4831 +       case NL80211_CHAN_WIDTH_80P80:
4832 +               WARN_ON(!chandef->center_freq2);
4833 +               r = cfg80211_get_chans_dfs_available(wiphy,
4834 +                                                    chandef->center_freq2,
4835 +                                                    width);
4836 +       default:
4837 +               WARN_ON(chandef->center_freq2);
4838 +               break;
4839 +       }
4840 +
4841 +       return r;
4842 +}
4843 +
4844 +
4845 +static bool cfg80211_secondary_chans_ok(struct wiphy *wiphy,
4846 +                                       u32 center_freq, u32 bandwidth,
4847 +                                       u32 prohibited_flags)
4848 +{
4849 +       struct ieee80211_channel *c;
4850 +       u32 freq, start_freq, end_freq;
4851 +
4852 +       start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
4853 +       end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
4854 +
4855 +       for (freq = start_freq; freq <= end_freq; freq += 20) {
4856 +               c = ieee80211_get_channel(wiphy, freq);
4857 +               if (!c || c->flags & prohibited_flags)
4858                         return false;
4859         }
4860
4861 @@ -462,14 +609,19 @@ bool cfg80211_reg_can_beacon(struct wiph
4862                              struct cfg80211_chan_def *chandef)
4863  {
4864         bool res;
4865 +       u32 prohibited_flags = IEEE80211_CHAN_DISABLED |
4866 +                              IEEE80211_CHAN_NO_IR |
4867 +                              IEEE80211_CHAN_RADAR;
4868
4869         trace_cfg80211_reg_can_beacon(wiphy, chandef);
4870
4871 -       res = cfg80211_chandef_usable(wiphy, chandef,
4872 -                                     IEEE80211_CHAN_DISABLED |
4873 -                                     IEEE80211_CHAN_PASSIVE_SCAN |
4874 -                                     IEEE80211_CHAN_NO_IBSS |
4875 -                                     IEEE80211_CHAN_RADAR);
4876 +       if (cfg80211_chandef_dfs_required(wiphy, chandef) > 0 &&
4877 +           cfg80211_chandef_dfs_available(wiphy, chandef)) {
4878 +               /* We can skip IEEE80211_CHAN_NO_IR if chandef dfs available */
4879 +               prohibited_flags = IEEE80211_CHAN_DISABLED;
4880 +       }
4881 +
4882 +       res = cfg80211_chandef_usable(wiphy, chandef, prohibited_flags);
4883
4884         trace_cfg80211_return_bool(res);
4885         return res;
4886 --- a/net/wireless/core.h
4887 +++ b/net/wireless/core.h
4888 @@ -382,6 +382,19 @@ int cfg80211_can_use_iftype_chan(struct
4889                                  enum cfg80211_chan_mode chanmode,
4890                                  u8 radar_detect);
4891
4892 +/**
4893 + * cfg80211_chandef_dfs_usable - checks if chandef is DFS usable
4894 + * @wiphy: the wiphy to validate against
4895 + * @chandef: the channel definition to check
4896 + *
4897 + * Checks if chandef is usable and we can/need start CAC on such channel.
4898 + *
4899 + * Return: Return true if all channels available and at least
4900 + *        one channel require CAC (NL80211_DFS_USABLE)
4901 + */
4902 +bool cfg80211_chandef_dfs_usable(struct wiphy *wiphy,
4903 +                                const struct cfg80211_chan_def *chandef);
4904 +
4905  void cfg80211_set_dfs_state(struct wiphy *wiphy,
4906                             const struct cfg80211_chan_def *chandef,
4907                             enum nl80211_dfs_state dfs_state);
4908 --- a/net/wireless/genregdb.awk
4909 +++ b/net/wireless/genregdb.awk
4910 @@ -107,10 +107,13 @@ active && /^[ \t]*\(/ {
4911                 } else if (flagarray[arg] == "PTMP-ONLY") {
4912                         flags = flags "\n\t\t\tNL80211_RRF_PTMP_ONLY | "
4913                 } else if (flagarray[arg] == "PASSIVE-SCAN") {
4914 -                       flags = flags "\n\t\t\tNL80211_RRF_PASSIVE_SCAN | "
4915 +                       flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
4916                 } else if (flagarray[arg] == "NO-IBSS") {
4917 -                       flags = flags "\n\t\t\tNL80211_RRF_NO_IBSS | "
4918 +                       flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
4919 +               } else if (flagarray[arg] == "NO-IR") {
4920 +                       flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
4921                 }
4922 +
4923         }
4924         flags = flags "0"
4925         printf "\t\tREG_RULE(%d, %d, %d, %d, %d, %s),\n", start, end, bw, gain, power, flags
4926 --- a/net/wireless/ibss.c
4927 +++ b/net/wireless/ibss.c
4928 @@ -274,7 +274,7 @@ int cfg80211_ibss_wext_join(struct cfg80
4929
4930                         for (i = 0; i < sband->n_channels; i++) {
4931                                 chan = &sband->channels[i];
4932 -                               if (chan->flags & IEEE80211_CHAN_NO_IBSS)
4933 +                               if (chan->flags & IEEE80211_CHAN_NO_IR)
4934                                         continue;
4935                                 if (chan->flags & IEEE80211_CHAN_DISABLED)
4936                                         continue;
4937 @@ -345,7 +345,7 @@ int cfg80211_ibss_wext_siwfreq(struct ne
4938                 chan = ieee80211_get_channel(wdev->wiphy, freq);
4939                 if (!chan)
4940                         return -EINVAL;
4941 -               if (chan->flags & IEEE80211_CHAN_NO_IBSS ||
4942 +               if (chan->flags & IEEE80211_CHAN_NO_IR ||
4943                     chan->flags & IEEE80211_CHAN_DISABLED)
4944                         return -EINVAL;
4945         }
4946 --- a/net/wireless/mesh.c
4947 +++ b/net/wireless/mesh.c
4948 @@ -141,8 +141,7 @@ int __cfg80211_join_mesh(struct cfg80211
4949
4950                         for (i = 0; i < sband->n_channels; i++) {
4951                                 chan = &sband->channels[i];
4952 -                               if (chan->flags & (IEEE80211_CHAN_NO_IBSS |
4953 -                                                  IEEE80211_CHAN_PASSIVE_SCAN |
4954 +                               if (chan->flags & (IEEE80211_CHAN_NO_IR |
4955                                                    IEEE80211_CHAN_DISABLED |
4956                                                    IEEE80211_CHAN_RADAR))
4957                                         continue;
4958 --- a/net/wireless/mlme.c
4959 +++ b/net/wireless/mlme.c
4960 @@ -763,12 +763,12 @@ void cfg80211_radar_event(struct wiphy *
4961  EXPORT_SYMBOL(cfg80211_radar_event);
4962
4963  void cfg80211_cac_event(struct net_device *netdev,
4964 +                       const struct cfg80211_chan_def *chandef,
4965                         enum nl80211_radar_event event, gfp_t gfp)
4966  {
4967         struct wireless_dev *wdev = netdev->ieee80211_ptr;
4968         struct wiphy *wiphy = wdev->wiphy;
4969         struct cfg80211_registered_device *rdev = wiphy_to_dev(wiphy);
4970 -       struct cfg80211_chan_def chandef;
4971         unsigned long timeout;
4972
4973         trace_cfg80211_cac_event(netdev, event);
4974 @@ -779,14 +779,12 @@ void cfg80211_cac_event(struct net_devic
4975         if (WARN_ON(!wdev->channel))
4976                 return;
4977
4978 -       cfg80211_chandef_create(&chandef, wdev->channel, NL80211_CHAN_NO_HT);
4979 -
4980         switch (event) {
4981         case NL80211_RADAR_CAC_FINISHED:
4982                 timeout = wdev->cac_start_time +
4983                           msecs_to_jiffies(IEEE80211_DFS_MIN_CAC_TIME_MS);
4984                 WARN_ON(!time_after_eq(jiffies, timeout));
4985 -               cfg80211_set_dfs_state(wiphy, &chandef, NL80211_DFS_AVAILABLE);
4986 +               cfg80211_set_dfs_state(wiphy, chandef, NL80211_DFS_AVAILABLE);
4987                 break;
4988         case NL80211_RADAR_CAC_ABORTED:
4989                 break;
4990 @@ -796,6 +794,6 @@ void cfg80211_cac_event(struct net_devic
4991         }
4992         wdev->cac_started = false;
4993
4994 -       nl80211_radar_notify(rdev, &chandef, event, netdev, gfp);
4995 +       nl80211_radar_notify(rdev, chandef, event, netdev, gfp);
4996  }
4997  EXPORT_SYMBOL(cfg80211_cac_event);
4998 --- a/net/wireless/nl80211.c
4999 +++ b/net/wireless/nl80211.c
5000 @@ -545,12 +545,12 @@ static int nl80211_msg_put_channel(struc
5001         if ((chan->flags & IEEE80211_CHAN_DISABLED) &&
5002             nla_put_flag(msg, NL80211_FREQUENCY_ATTR_DISABLED))
5003                 goto nla_put_failure;
5004 -       if ((chan->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
5005 -           nla_put_flag(msg, NL80211_FREQUENCY_ATTR_PASSIVE_SCAN))
5006 -               goto nla_put_failure;
5007 -       if ((chan->flags & IEEE80211_CHAN_NO_IBSS) &&
5008 -           nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_IBSS))
5009 -               goto nla_put_failure;
5010 +       if (chan->flags & IEEE80211_CHAN_NO_IR) {
5011 +               if (nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_IR))
5012 +                       goto nla_put_failure;
5013 +               if (nla_put_flag(msg, __NL80211_FREQUENCY_ATTR_NO_IBSS))
5014 +                       goto nla_put_failure;
5015 +       }
5016         if (chan->flags & IEEE80211_CHAN_RADAR) {
5017                 if (nla_put_flag(msg, NL80211_FREQUENCY_ATTR_RADAR))
5018                         goto nla_put_failure;
5019 @@ -1229,7 +1229,8 @@ static int nl80211_send_wiphy(struct cfg
5020                     nla_put_flag(msg, NL80211_ATTR_TDLS_EXTERNAL_SETUP))
5021                         goto nla_put_failure;
5022                 if ((dev->wiphy.flags & WIPHY_FLAG_SUPPORTS_5_10_MHZ) &&
5023 -                   nla_put_flag(msg, WIPHY_FLAG_SUPPORTS_5_10_MHZ))
5024 +                   (nla_put_flag(msg, NL80211_ATTR_SUPPORT_5_MHZ) ||
5025 +                    nla_put_flag(msg, NL80211_ATTR_SUPPORT_10_MHZ)))
5026                         goto nla_put_failure;
5027
5028                 state->split_start++;
5029 @@ -2170,7 +2171,7 @@ static inline u64 wdev_id(struct wireles
5030  }
5031
5032  static int nl80211_send_chandef(struct sk_buff *msg,
5033 -                                struct cfg80211_chan_def *chandef)
5034 +                               const struct cfg80211_chan_def *chandef)
5035  {
5036         WARN_ON(!cfg80211_chandef_valid(chandef));
5037
5038 @@ -3219,6 +3220,7 @@ static int nl80211_start_ap(struct sk_bu
5039                         return PTR_ERR(params.acl);
5040         }
5041
5042 +       wdev_lock(wdev);
5043         err = rdev_start_ap(rdev, dev, &params);
5044         if (!err) {
5045                 wdev->preset_chandef = params.chandef;
5046 @@ -3227,6 +3229,7 @@ static int nl80211_start_ap(struct sk_bu
5047                 wdev->ssid_len = params.ssid_len;
5048                 memcpy(wdev->ssid, params.ssid, wdev->ssid_len);
5049         }
5050 +       wdev_unlock(wdev);
5051
5052         kfree(params.acl);
5053
5054 @@ -3255,7 +3258,11 @@ static int nl80211_set_beacon(struct sk_
5055         if (err)
5056                 return err;
5057
5058 -       return rdev_change_beacon(rdev, dev, &params);
5059 +       wdev_lock(wdev);
5060 +       err = rdev_change_beacon(rdev, dev, &params);
5061 +       wdev_unlock(wdev);
5062 +
5063 +       return err;
5064  }
5065
5066  static int nl80211_stop_ap(struct sk_buff *skb, struct genl_info *info)
5067 @@ -4461,7 +4468,9 @@ static int nl80211_set_bss(struct sk_buf
5068  {
5069         struct cfg80211_registered_device *rdev = info->user_ptr[0];
5070         struct net_device *dev = info->user_ptr[1];
5071 +       struct wireless_dev *wdev = dev->ieee80211_ptr;
5072         struct bss_parameters params;
5073 +       int err;
5074
5075         memset(&params, 0, sizeof(params));
5076         /* default to not changing parameters */
5077 @@ -4527,7 +4536,11 @@ static int nl80211_set_bss(struct sk_buf
5078             dev->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_GO)
5079                 return -EOPNOTSUPP;
5080
5081 -       return rdev_change_bss(rdev, dev, &params);
5082 +       wdev_lock(wdev);
5083 +       err = rdev_change_bss(rdev, dev, &params);
5084 +       wdev_unlock(wdev);
5085 +
5086 +       return err;
5087  }
5088
5089  static const struct nla_policy reg_rule_policy[NL80211_REG_RULE_ATTR_MAX + 1] = {
5090 @@ -5653,7 +5666,7 @@ static int nl80211_start_radar_detection
5091         if (err == 0)
5092                 return -EINVAL;
5093
5094 -       if (chandef.chan->dfs_state != NL80211_DFS_USABLE)
5095 +       if (!cfg80211_chandef_dfs_usable(wdev->wiphy, &chandef))
5096                 return -EINVAL;
5097
5098         if (!rdev->ops->start_radar_detection)
5099 @@ -5793,7 +5806,11 @@ skip_beacons:
5100         if (info->attrs[NL80211_ATTR_CH_SWITCH_BLOCK_TX])
5101                 params.block_tx = true;
5102
5103 -       return rdev_channel_switch(rdev, dev, &params);
5104 +       wdev_lock(wdev);
5105 +       err = rdev_channel_switch(rdev, dev, &params);
5106 +       wdev_unlock(wdev);
5107 +
5108 +       return err;
5109  }
5110
5111  static int nl80211_send_bss(struct sk_buff *msg, struct netlink_callback *cb,
5112 @@ -10809,21 +10826,18 @@ void cfg80211_ch_switch_notify(struct ne
5113         struct wiphy *wiphy = wdev->wiphy;
5114         struct cfg80211_registered_device *rdev = wiphy_to_dev(wiphy);
5115
5116 -       trace_cfg80211_ch_switch_notify(dev, chandef);
5117 +       ASSERT_WDEV_LOCK(wdev);
5118
5119 -       wdev_lock(wdev);
5120 +       trace_cfg80211_ch_switch_notify(dev, chandef);
5121
5122         if (WARN_ON(wdev->iftype != NL80211_IFTYPE_AP &&
5123                     wdev->iftype != NL80211_IFTYPE_P2P_GO &&
5124                     wdev->iftype != NL80211_IFTYPE_ADHOC &&
5125                     wdev->iftype != NL80211_IFTYPE_MESH_POINT))
5126 -               goto out;
5127 +               return;
5128
5129         wdev->channel = chandef->chan;
5130         nl80211_ch_switch_notify(rdev, dev, chandef, GFP_KERNEL);
5131 -out:
5132 -       wdev_unlock(wdev);
5133 -       return;
5134  }
5135  EXPORT_SYMBOL(cfg80211_ch_switch_notify);
5136
5137 @@ -10882,7 +10896,7 @@ EXPORT_SYMBOL(cfg80211_cqm_txe_notify);
5138
5139  void
5140  nl80211_radar_notify(struct cfg80211_registered_device *rdev,
5141 -                    struct cfg80211_chan_def *chandef,
5142 +                    const struct cfg80211_chan_def *chandef,
5143                      enum nl80211_radar_event event,
5144                      struct net_device *netdev, gfp_t gfp)
5145  {
5146 --- a/net/wireless/nl80211.h
5147 +++ b/net/wireless/nl80211.h
5148 @@ -70,7 +70,7 @@ int nl80211_send_mgmt(struct cfg80211_re
5149
5150  void
5151  nl80211_radar_notify(struct cfg80211_registered_device *rdev,
5152 -                    struct cfg80211_chan_def *chandef,
5153 +                    const struct cfg80211_chan_def *chandef,
5154                      enum nl80211_radar_event event,
5155                      struct net_device *netdev, gfp_t gfp);
5156
5157 --- a/net/wireless/reg.c
5158 +++ b/net/wireless/reg.c
5159 @@ -163,35 +163,29 @@ static const struct ieee80211_regdomain
5160                 REG_RULE(2412-10, 2462+10, 40, 6, 20, 0),
5161                 /* IEEE 802.11b/g, channels 12..13. */
5162                 REG_RULE(2467-10, 2472+10, 40, 6, 20,
5163 -                       NL80211_RRF_PASSIVE_SCAN |
5164 -                       NL80211_RRF_NO_IBSS),
5165 +                       NL80211_RRF_NO_IR),
5166                 /* IEEE 802.11 channel 14 - Only JP enables
5167                  * this and for 802.11b only */
5168                 REG_RULE(2484-10, 2484+10, 20, 6, 20,
5169 -                       NL80211_RRF_PASSIVE_SCAN |
5170 -                       NL80211_RRF_NO_IBSS |
5171 +                       NL80211_RRF_NO_IR |
5172                         NL80211_RRF_NO_OFDM),
5173                 /* IEEE 802.11a, channel 36..48 */
5174                 REG_RULE(5180-10, 5240+10, 160, 6, 20,
5175 -                        NL80211_RRF_PASSIVE_SCAN |
5176 -                        NL80211_RRF_NO_IBSS),
5177 +                        NL80211_RRF_NO_IR),
5178
5179                 /* IEEE 802.11a, channel 52..64 - DFS required */
5180                 REG_RULE(5260-10, 5320+10, 160, 6, 20,
5181 -                       NL80211_RRF_PASSIVE_SCAN |
5182 -                       NL80211_RRF_NO_IBSS |
5183 +                       NL80211_RRF_NO_IR |
5184                         NL80211_RRF_DFS),
5185
5186                 /* IEEE 802.11a, channel 100..144 - DFS required */
5187                 REG_RULE(5500-10, 5720+10, 160, 6, 20,
5188 -                       NL80211_RRF_PASSIVE_SCAN |
5189 -                       NL80211_RRF_NO_IBSS |
5190 +                       NL80211_RRF_NO_IR |
5191                         NL80211_RRF_DFS),
5192
5193                 /* IEEE 802.11a, channel 149..165 */
5194                 REG_RULE(5745-10, 5825+10, 80, 6, 20,
5195 -                       NL80211_RRF_PASSIVE_SCAN |
5196 -                       NL80211_RRF_NO_IBSS),
5197 +                       NL80211_RRF_NO_IR),
5198
5199                 /* IEEE 802.11ad (60gHz), channels 1..3 */
5200                 REG_RULE(56160+2160*1-1080, 56160+2160*3+1080, 2160, 0, 0, 0),
5201 @@ -698,10 +692,8 @@ regdom_intersect(const struct ieee80211_
5202  static u32 map_regdom_flags(u32 rd_flags)
5203  {
5204         u32 channel_flags = 0;
5205 -       if (rd_flags & NL80211_RRF_PASSIVE_SCAN)
5206 -               channel_flags |= IEEE80211_CHAN_PASSIVE_SCAN;
5207 -       if (rd_flags & NL80211_RRF_NO_IBSS)
5208 -               channel_flags |= IEEE80211_CHAN_NO_IBSS;
5209 +       if (rd_flags & NL80211_RRF_NO_IR_ALL)
5210 +               channel_flags |= IEEE80211_CHAN_NO_IR;
5211         if (rd_flags & NL80211_RRF_DFS)
5212                 channel_flags |= IEEE80211_CHAN_RADAR;
5213         if (rd_flags & NL80211_RRF_NO_OFDM)
5214 @@ -1066,13 +1058,8 @@ static void handle_reg_beacon(struct wip
5215         chan_before.center_freq = chan->center_freq;
5216         chan_before.flags = chan->flags;
5217
5218 -       if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN) {
5219 -               chan->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
5220 -               channel_changed = true;
5221 -       }
5222 -
5223 -       if (chan->flags & IEEE80211_CHAN_NO_IBSS) {
5224 -               chan->flags &= ~IEEE80211_CHAN_NO_IBSS;
5225 +       if (chan->flags & IEEE80211_CHAN_NO_IR) {
5226 +               chan->flags &= ~IEEE80211_CHAN_NO_IR;
5227                 channel_changed = true;
5228         }
5229
5230 --- /dev/null
5231 +++ b/drivers/net/wireless/ath/ath9k/ar9003_wow.c
5232 @@ -0,0 +1,422 @@
5233 +/*
5234 + * Copyright (c) 2012 Qualcomm Atheros, Inc.
5235 + *
5236 + * Permission to use, copy, modify, and/or distribute this software for any
5237 + * purpose with or without fee is hereby granted, provided that the above
5238 + * copyright notice and this permission notice appear in all copies.
5239 + *
5240 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
5241 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
5242 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
5243 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
5244 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
5245 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
5246 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
5247 + */
5248 +
5249 +#include <linux/export.h>
5250 +#include "ath9k.h"
5251 +#include "reg.h"
5252 +#include "hw-ops.h"
5253 +
5254 +const char *ath9k_hw_wow_event_to_string(u32 wow_event)
5255 +{
5256 +       if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
5257 +               return "Magic pattern";
5258 +       if (wow_event & AH_WOW_USER_PATTERN_EN)
5259 +               return "User pattern";
5260 +       if (wow_event & AH_WOW_LINK_CHANGE)
5261 +               return "Link change";
5262 +       if (wow_event & AH_WOW_BEACON_MISS)
5263 +               return "Beacon miss";
5264 +
5265 +       return  "unknown reason";
5266 +}
5267 +EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
5268 +
5269 +static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
5270 +{
5271 +       struct ath_common *common = ath9k_hw_common(ah);
5272 +
5273 +       REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
5274 +
5275 +       /* set rx disable bit */
5276 +       REG_WRITE(ah, AR_CR, AR_CR_RXD);
5277 +
5278 +       if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
5279 +               ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
5280 +                       REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
5281 +               return;
5282 +       }
5283 +
5284 +       REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
5285 +}
5286 +
5287 +static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
5288 +{
5289 +       struct ath_common *common = ath9k_hw_common(ah);
5290 +       u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
5291 +       u32 ctl[13] = {0};
5292 +       u32 data_word[KAL_NUM_DATA_WORDS];
5293 +       u8 i;
5294 +       u32 wow_ka_data_word0;
5295 +
5296 +       memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
5297 +       memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
5298 +
5299 +       /* set the transmit buffer */
5300 +       ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
5301 +       ctl[1] = 0;
5302 +       ctl[3] = 0xb;   /* OFDM_6M hardware value for this rate */
5303 +       ctl[4] = 0;
5304 +       ctl[7] = (ah->txchainmask) << 2;
5305 +       ctl[2] = 0xf << 16; /* tx_tries 0 */
5306 +
5307 +       for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
5308 +               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
5309 +
5310 +       REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
5311 +
5312 +       data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
5313 +                      (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
5314 +       data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
5315 +                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
5316 +       data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
5317 +                      (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
5318 +       data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
5319 +                      (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
5320 +       data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
5321 +                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
5322 +       data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
5323 +
5324 +       if (AR_SREV_9462_20(ah)) {
5325 +               /* AR9462 2.0 has an extra descriptor word (time based
5326 +                * discard) compared to other chips */
5327 +               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
5328 +               wow_ka_data_word0 = AR_WOW_TXBUF(13);
5329 +       } else {
5330 +               wow_ka_data_word0 = AR_WOW_TXBUF(12);
5331 +       }
5332 +
5333 +       for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
5334 +               REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
5335 +
5336 +}
5337 +
5338 +void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
5339 +                               u8 *user_mask, int pattern_count,
5340 +                               int pattern_len)
5341 +{
5342 +       int i;
5343 +       u32 pattern_val, mask_val;
5344 +       u32 set, clr;
5345 +
5346 +       /* FIXME: should check count by querying the hardware capability */
5347 +       if (pattern_count >= MAX_NUM_PATTERN)
5348 +               return;
5349 +
5350 +       REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
5351 +
5352 +       /* set the registers for pattern */
5353 +       for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
5354 +               memcpy(&pattern_val, user_pattern, 4);
5355 +               REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
5356 +                         pattern_val);
5357 +               user_pattern += 4;
5358 +       }
5359 +
5360 +       /* set the registers for mask */
5361 +       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
5362 +               memcpy(&mask_val, user_mask, 4);
5363 +               REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
5364 +               user_mask += 4;
5365 +       }
5366 +
5367 +       /* set the pattern length to be matched
5368 +        *
5369 +        * AR_WOW_LENGTH1_REG1
5370 +        * bit 31:24 pattern 0 length
5371 +        * bit 23:16 pattern 1 length
5372 +        * bit 15:8 pattern 2 length
5373 +        * bit 7:0 pattern 3 length
5374 +        *
5375 +        * AR_WOW_LENGTH1_REG2
5376 +        * bit 31:24 pattern 4 length
5377 +        * bit 23:16 pattern 5 length
5378 +        * bit 15:8 pattern 6 length
5379 +        * bit 7:0 pattern 7 length
5380 +        *
5381 +        * the below logic writes out the new
5382 +        * pattern length for the corresponding
5383 +        * pattern_count, while masking out the
5384 +        * other fields
5385 +        */
5386 +
5387 +       ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
5388 +
5389 +       if (pattern_count < 4) {
5390 +               /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
5391 +               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
5392 +                      AR_WOW_LEN1_SHIFT(pattern_count);
5393 +               clr = AR_WOW_LENGTH1_MASK(pattern_count);
5394 +               REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
5395 +       } else {
5396 +               /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
5397 +               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
5398 +                      AR_WOW_LEN2_SHIFT(pattern_count);
5399 +               clr = AR_WOW_LENGTH2_MASK(pattern_count);
5400 +               REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
5401 +       }
5402 +
5403 +}
5404 +EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
5405 +
5406 +u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
5407 +{
5408 +       u32 wow_status = 0;
5409 +       u32 val = 0, rval;
5410 +
5411 +       /*
5412 +        * read the WoW status register to know
5413 +        * the wakeup reason
5414 +        */
5415 +       rval = REG_READ(ah, AR_WOW_PATTERN);
5416 +       val = AR_WOW_STATUS(rval);
5417 +
5418 +       /*
5419 +        * mask only the WoW events that we have enabled. Sometimes
5420 +        * we have spurious WoW events from the AR_WOW_PATTERN
5421 +        * register. This mask will clean it up.
5422 +        */
5423 +
5424 +       val &= ah->wow_event_mask;
5425 +
5426 +       if (val) {
5427 +               if (val & AR_WOW_MAGIC_PAT_FOUND)
5428 +                       wow_status |= AH_WOW_MAGIC_PATTERN_EN;
5429 +               if (AR_WOW_PATTERN_FOUND(val))
5430 +                       wow_status |= AH_WOW_USER_PATTERN_EN;
5431 +               if (val & AR_WOW_KEEP_ALIVE_FAIL)
5432 +                       wow_status |= AH_WOW_LINK_CHANGE;
5433 +               if (val & AR_WOW_BEACON_FAIL)
5434 +                       wow_status |= AH_WOW_BEACON_MISS;
5435 +       }
5436 +
5437 +       /*
5438 +        * set and clear WOW_PME_CLEAR registers for the chip to
5439 +        * generate next wow signal.
5440 +        * disable D3 before accessing other registers ?
5441 +        */
5442 +
5443 +       /* do we need to check the bit value 0x01000000 (7-10) ?? */
5444 +       REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
5445 +               AR_PMCTRL_PWR_STATE_D1D3);
5446 +
5447 +       /*
5448 +        * clear all events
5449 +        */
5450 +       REG_WRITE(ah, AR_WOW_PATTERN,
5451 +                 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
5452 +
5453 +       /*
5454 +        * restore the beacon threshold to init value
5455 +        */
5456 +       REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
5457 +
5458 +       /*
5459 +        * Restore the way the PCI-E reset, Power-On-Reset, external
5460 +        * PCIE_POR_SHORT pins are tied to its original value.
5461 +        * Previously just before WoW sleep, we untie the PCI-E
5462 +        * reset to our Chip's Power On Reset so that any PCI-E
5463 +        * reset from the bus will not reset our chip
5464 +        */
5465 +       if (ah->is_pciexpress)
5466 +               ath9k_hw_configpcipowersave(ah, false);
5467 +
5468 +       ah->wow_event_mask = 0;
5469 +
5470 +       return wow_status;
5471 +}
5472 +EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
5473 +
5474 +void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
5475 +{
5476 +       u32 wow_event_mask;
5477 +       u32 set, clr;
5478 +
5479 +       /*
5480 +        * wow_event_mask is a mask to the AR_WOW_PATTERN register to
5481 +        * indicate which WoW events we have enabled. The WoW events
5482 +        * are from the 'pattern_enable' in this function and
5483 +        * 'pattern_count' of ath9k_hw_wow_apply_pattern()
5484 +        */
5485 +       wow_event_mask = ah->wow_event_mask;
5486 +
5487 +       /*
5488 +        * Untie Power-on-Reset from the PCI-E-Reset. When we are in
5489 +        * WOW sleep, we do want the Reset from the PCI-E to disturb
5490 +        * our hw state
5491 +        */
5492 +       if (ah->is_pciexpress) {
5493 +               /*
5494 +                * we need to untie the internal POR (power-on-reset)
5495 +                * to the external PCI-E reset. We also need to tie
5496 +                * the PCI-E Phy reset to the PCI-E reset.
5497 +                */
5498 +               set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
5499 +               clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
5500 +               REG_RMW(ah, AR_WA, set, clr);
5501 +       }
5502 +
5503 +       /*
5504 +        * set the power states appropriately and enable PME
5505 +        */
5506 +       set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
5507 +             AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
5508 +
5509 +       /*
5510 +        * set and clear WOW_PME_CLEAR registers for the chip
5511 +        * to generate next wow signal.
5512 +        */
5513 +       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
5514 +       clr = AR_PMCTRL_WOW_PME_CLR;
5515 +       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
5516 +
5517 +       /*
5518 +        * Setup for:
5519 +        *      - beacon misses
5520 +        *      - magic pattern
5521 +        *      - keep alive timeout
5522 +        *      - pattern matching
5523 +        */
5524 +
5525 +       /*
5526 +        * Program default values for pattern backoff, aifs/slot/KAL count,
5527 +        * beacon miss timeout, KAL timeout, etc.
5528 +        */
5529 +       set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
5530 +       REG_SET_BIT(ah, AR_WOW_PATTERN, set);
5531 +
5532 +       set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
5533 +             AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
5534 +             AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
5535 +       REG_SET_BIT(ah, AR_WOW_COUNT, set);
5536 +
5537 +       if (pattern_enable & AH_WOW_BEACON_MISS)
5538 +               set = AR_WOW_BEACON_TIMO;
5539 +       /* We are not using beacon miss, program a large value */
5540 +       else
5541 +               set = AR_WOW_BEACON_TIMO_MAX;
5542 +
5543 +       REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
5544 +
5545 +       /*
5546 +        * Keep alive timo in ms except AR9280
5547 +        */
5548 +       if (!pattern_enable)
5549 +               set = AR_WOW_KEEP_ALIVE_NEVER;
5550 +       else
5551 +               set = KAL_TIMEOUT * 32;
5552 +
5553 +       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
5554 +
5555 +       /*
5556 +        * Keep alive delay in us. based on 'power on clock',
5557 +        * therefore in usec
5558 +        */
5559 +       set = KAL_DELAY * 1000;
5560 +       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
5561 +
5562 +       /*
5563 +        * Create keep alive pattern to respond to beacons
5564 +        */
5565 +       ath9k_wow_create_keep_alive_pattern(ah);
5566 +
5567 +       /*
5568 +        * Configure MAC WoW Registers
5569 +        */
5570 +       set = 0;
5571 +       /* Send keep alive timeouts anyway */
5572 +       clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
5573 +
5574 +       if (pattern_enable & AH_WOW_LINK_CHANGE)
5575 +               wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
5576 +       else
5577 +               set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
5578 +
5579 +       set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
5580 +       REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
5581 +
5582 +       /*
5583 +        * we are relying on a bmiss failure. ensure we have
5584 +        * enough threshold to prevent false positives
5585 +        */
5586 +       REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
5587 +                     AR_WOW_BMISSTHRESHOLD);
5588 +
5589 +       set = 0;
5590 +       clr = 0;
5591 +
5592 +       if (pattern_enable & AH_WOW_BEACON_MISS) {
5593 +               set = AR_WOW_BEACON_FAIL_EN;
5594 +               wow_event_mask |= AR_WOW_BEACON_FAIL;
5595 +       } else {
5596 +               clr = AR_WOW_BEACON_FAIL_EN;
5597 +       }
5598 +
5599 +       REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
5600 +
5601 +       set = 0;
5602 +       clr = 0;
5603 +       /*
5604 +        * Enable the magic packet registers
5605 +        */
5606 +       if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
5607 +               set = AR_WOW_MAGIC_EN;
5608 +               wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
5609 +       } else {
5610 +               clr = AR_WOW_MAGIC_EN;
5611 +       }
5612 +       set |= AR_WOW_MAC_INTR_EN;
5613 +       REG_RMW(ah, AR_WOW_PATTERN, set, clr);
5614 +
5615 +       REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
5616 +                 AR_WOW_PATTERN_SUPPORTED);
5617 +
5618 +       /*
5619 +        * Set the power states appropriately and enable PME
5620 +        */
5621 +       clr = 0;
5622 +       set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
5623 +             AR_PMCTRL_PWR_PM_CTRL_ENA;
5624 +
5625 +       clr = AR_PCIE_PM_CTRL_ENA;
5626 +       REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
5627 +
5628 +       /*
5629 +        * this is needed to prevent the chip waking up
5630 +        * the host within 3-4 seconds with certain
5631 +        * platform/BIOS. The fix is to enable
5632 +        * D1 & D3 to match original definition and
5633 +        * also match the OTP value. Anyway this
5634 +        * is more related to SW WOW.
5635 +        */
5636 +       clr = AR_PMCTRL_PWR_STATE_D1D3;
5637 +       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
5638 +
5639 +       set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
5640 +       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
5641 +
5642 +       REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
5643 +
5644 +       /* to bring down WOW power low margin */
5645 +       set = BIT(13);
5646 +       REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
5647 +       /* HW WoW */
5648 +       clr = BIT(5);
5649 +       REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
5650 +
5651 +       ath9k_hw_set_powermode_wow_sleep(ah);
5652 +       ah->wow_event_mask = wow_event_mask;
5653 +}
5654 +EXPORT_SYMBOL(ath9k_hw_wow_enable);
5655 --- /dev/null
5656 +++ b/drivers/net/wireless/ath/ath9k/tx99.c
5657 @@ -0,0 +1,263 @@
5658 +/*
5659 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
5660 + *
5661 + * Permission to use, copy, modify, and/or distribute this software for any
5662 + * purpose with or without fee is hereby granted, provided that the above
5663 + * copyright notice and this permission notice appear in all copies.
5664 + *
5665 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
5666 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
5667 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
5668 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
5669 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
5670 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
5671 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
5672 + */
5673 +
5674 +#include "ath9k.h"
5675 +
5676 +static void ath9k_tx99_stop(struct ath_softc *sc)
5677 +{
5678 +       struct ath_hw *ah = sc->sc_ah;
5679 +       struct ath_common *common = ath9k_hw_common(ah);
5680 +
5681 +       ath_drain_all_txq(sc);
5682 +       ath_startrecv(sc);
5683 +
5684 +       ath9k_hw_set_interrupts(ah);
5685 +       ath9k_hw_enable_interrupts(ah);
5686 +
5687 +       ieee80211_wake_queues(sc->hw);
5688 +
5689 +       kfree_skb(sc->tx99_skb);
5690 +       sc->tx99_skb = NULL;
5691 +       sc->tx99_state = false;
5692 +
5693 +       ath9k_hw_tx99_stop(sc->sc_ah);
5694 +       ath_dbg(common, XMIT, "TX99 stopped\n");
5695 +}
5696 +
5697 +static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
5698 +{
5699 +       static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
5700 +                              0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
5701 +                              0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
5702 +                              0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
5703 +                              0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
5704 +                              0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
5705 +                              0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
5706 +                              0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
5707 +       u32 len = 1200;
5708 +       struct ieee80211_hw *hw = sc->hw;
5709 +       struct ieee80211_hdr *hdr;
5710 +       struct ieee80211_tx_info *tx_info;
5711 +       struct sk_buff *skb;
5712 +
5713 +       skb = alloc_skb(len, GFP_KERNEL);
5714 +       if (!skb)
5715 +               return NULL;
5716 +
5717 +       skb_put(skb, len);
5718 +
5719 +       memset(skb->data, 0, len);
5720 +
5721 +       hdr = (struct ieee80211_hdr *)skb->data;
5722 +       hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
5723 +       hdr->duration_id = 0;
5724 +
5725 +       memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
5726 +       memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
5727 +       memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
5728 +
5729 +       hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
5730 +
5731 +       tx_info = IEEE80211_SKB_CB(skb);
5732 +       memset(tx_info, 0, sizeof(*tx_info));
5733 +       tx_info->band = hw->conf.chandef.chan->band;
5734 +       tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
5735 +       tx_info->control.vif = sc->tx99_vif;
5736 +
5737 +       memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
5738 +
5739 +       return skb;
5740 +}
5741 +
5742 +static void ath9k_tx99_deinit(struct ath_softc *sc)
5743 +{
5744 +       ath_reset(sc);
5745 +
5746 +       ath9k_ps_wakeup(sc);
5747 +       ath9k_tx99_stop(sc);
5748 +       ath9k_ps_restore(sc);
5749 +}
5750 +
5751 +static int ath9k_tx99_init(struct ath_softc *sc)
5752 +{
5753 +       struct ieee80211_hw *hw = sc->hw;
5754 +       struct ath_hw *ah = sc->sc_ah;
5755 +       struct ath_common *common = ath9k_hw_common(ah);
5756 +       struct ath_tx_control txctl;
5757 +       int r;
5758 +
5759 +       if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
5760 +               ath_err(common,
5761 +                       "driver is in invalid state unable to use TX99");
5762 +               return -EINVAL;
5763 +       }
5764 +
5765 +       sc->tx99_skb = ath9k_build_tx99_skb(sc);
5766 +       if (!sc->tx99_skb)
5767 +               return -ENOMEM;
5768 +
5769 +       memset(&txctl, 0, sizeof(txctl));
5770 +       txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
5771 +
5772 +       ath_reset(sc);
5773 +
5774 +       ath9k_ps_wakeup(sc);
5775 +
5776 +       ath9k_hw_disable_interrupts(ah);
5777 +       atomic_set(&ah->intr_ref_cnt, -1);
5778 +       ath_drain_all_txq(sc);
5779 +       ath_stoprecv(sc);
5780 +
5781 +       sc->tx99_state = true;
5782 +
5783 +       ieee80211_stop_queues(hw);
5784 +
5785 +       if (sc->tx99_power == MAX_RATE_POWER + 1)
5786 +               sc->tx99_power = MAX_RATE_POWER;
5787 +
5788 +       ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
5789 +       r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
5790 +       if (r) {
5791 +               ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
5792 +               return r;
5793 +       }
5794 +
5795 +       ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
5796 +               sc->tx99_power,
5797 +               sc->tx99_power / 2);
5798 +
5799 +       /* We leave the harware awake as it will be chugging on */
5800 +
5801 +       return 0;
5802 +}
5803 +
5804 +static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
5805 +                             size_t count, loff_t *ppos)
5806 +{
5807 +       struct ath_softc *sc = file->private_data;
5808 +       char buf[3];
5809 +       unsigned int len;
5810 +
5811 +       len = sprintf(buf, "%d\n", sc->tx99_state);
5812 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
5813 +}
5814 +
5815 +static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
5816 +                              size_t count, loff_t *ppos)
5817 +{
5818 +       struct ath_softc *sc = file->private_data;
5819 +       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
5820 +       char buf[32];
5821 +       bool start;
5822 +       ssize_t len;
5823 +       int r;
5824 +
5825 +       if (sc->nvifs > 1)
5826 +               return -EOPNOTSUPP;
5827 +
5828 +       len = min(count, sizeof(buf) - 1);
5829 +       if (copy_from_user(buf, user_buf, len))
5830 +               return -EFAULT;
5831 +
5832 +       if (strtobool(buf, &start))
5833 +               return -EINVAL;
5834 +
5835 +       if (start == sc->tx99_state) {
5836 +               if (!start)
5837 +                       return count;
5838 +               ath_dbg(common, XMIT, "Resetting TX99\n");
5839 +               ath9k_tx99_deinit(sc);
5840 +       }
5841 +
5842 +       if (!start) {
5843 +               ath9k_tx99_deinit(sc);
5844 +               return count;
5845 +       }
5846 +
5847 +       r = ath9k_tx99_init(sc);
5848 +       if (r)
5849 +               return r;
5850 +
5851 +       return count;
5852 +}
5853 +
5854 +static const struct file_operations fops_tx99 = {
5855 +       .read = read_file_tx99,
5856 +       .write = write_file_tx99,
5857 +       .open = simple_open,
5858 +       .owner = THIS_MODULE,
5859 +       .llseek = default_llseek,
5860 +};
5861 +
5862 +static ssize_t read_file_tx99_power(struct file *file,
5863 +                                   char __user *user_buf,
5864 +                                   size_t count, loff_t *ppos)
5865 +{
5866 +       struct ath_softc *sc = file->private_data;
5867 +       char buf[32];
5868 +       unsigned int len;
5869 +
5870 +       len = sprintf(buf, "%d (%d dBm)\n",
5871 +                     sc->tx99_power,
5872 +                     sc->tx99_power / 2);
5873 +
5874 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
5875 +}
5876 +
5877 +static ssize_t write_file_tx99_power(struct file *file,
5878 +                                    const char __user *user_buf,
5879 +                                    size_t count, loff_t *ppos)
5880 +{
5881 +       struct ath_softc *sc = file->private_data;
5882 +       int r;
5883 +       u8 tx_power;
5884 +
5885 +       r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
5886 +       if (r)
5887 +               return r;
5888 +
5889 +       if (tx_power > MAX_RATE_POWER)
5890 +               return -EINVAL;
5891 +
5892 +       sc->tx99_power = tx_power;
5893 +
5894 +       ath9k_ps_wakeup(sc);
5895 +       ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
5896 +       ath9k_ps_restore(sc);
5897 +
5898 +       return count;
5899 +}
5900 +
5901 +static const struct file_operations fops_tx99_power = {
5902 +       .read = read_file_tx99_power,
5903 +       .write = write_file_tx99_power,
5904 +       .open = simple_open,
5905 +       .owner = THIS_MODULE,
5906 +       .llseek = default_llseek,
5907 +};
5908 +
5909 +void ath9k_tx99_init_debug(struct ath_softc *sc)
5910 +{
5911 +       if (!AR_SREV_9300_20_OR_LATER(sc->sc_ah))
5912 +               return;
5913 +
5914 +       debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
5915 +                           sc->debug.debugfs_phy, sc,
5916 +                           &fops_tx99);
5917 +       debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
5918 +                           sc->debug.debugfs_phy, sc,
5919 +                           &fops_tx99_power);
5920 +}
5921 --- a/drivers/net/wireless/ath/ath9k/dfs_debug.c
5922 +++ b/drivers/net/wireless/ath/ath9k/dfs_debug.c
5923 @@ -44,14 +44,20 @@ static ssize_t read_file_dfs(struct file
5924         if (buf == NULL)
5925                 return -ENOMEM;
5926
5927 -       if (sc->dfs_detector)
5928 -               dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
5929 -
5930         len += scnprintf(buf + len, size - len, "DFS support for "
5931                          "macVersion = 0x%x, macRev = 0x%x: %s\n",
5932                          hw_ver->macVersion, hw_ver->macRev,
5933                          (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_DFS) ?
5934                                         "enabled" : "disabled");
5935 +
5936 +       if (!sc->dfs_detector) {
5937 +               len += scnprintf(buf + len, size - len,
5938 +                               "DFS detector not enabled\n");
5939 +               goto exit;
5940 +       }
5941 +
5942 +       dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
5943 +
5944         len += scnprintf(buf + len, size - len, "Pulse detector statistics:\n");
5945         ATH9K_DFS_STAT("pulse events reported   ", pulses_total);
5946         ATH9K_DFS_STAT("invalid pulse events    ", pulses_no_dfs);
5947 @@ -76,6 +82,7 @@ static ssize_t read_file_dfs(struct file
5948         ATH9K_DFS_POOL_STAT("Seqs. alloc error       ", pseq_alloc_error);
5949         ATH9K_DFS_POOL_STAT("Seqs. in use            ", pseq_used);
5950
5951 +exit:
5952         if (len > size)
5953                 len = size;
5954
5955 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
5956 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
5957 @@ -641,11 +641,12 @@ static void ar9003_hw_override_ini(struc
5958                 else
5959                         ah->enabled_cals &= ~TX_IQ_CAL;
5960
5961 -               if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
5962 -                       ah->enabled_cals |= TX_CL_CAL;
5963 -               else
5964 -                       ah->enabled_cals &= ~TX_CL_CAL;
5965         }
5966 +
5967 +       if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
5968 +               ah->enabled_cals |= TX_CL_CAL;
5969 +       else
5970 +               ah->enabled_cals &= ~TX_CL_CAL;
5971  }
5972
5973  static void ar9003_hw_prog_ini(struct ath_hw *ah,
5974 @@ -701,6 +702,54 @@ static int ar9550_hw_get_modes_txgain_in
5975         return ret;
5976  }
5977
5978 +static void ar9003_doubler_fix(struct ath_hw *ah)
5979 +{
5980 +       if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
5981 +               REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
5982 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
5983 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
5984 +               REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
5985 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
5986 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
5987 +               REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
5988 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
5989 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
5990 +
5991 +               udelay(200);
5992 +
5993 +               REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
5994 +                           AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
5995 +               REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
5996 +                           AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
5997 +               REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
5998 +                           AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
5999 +
6000 +               udelay(1);
6001 +
6002 +               REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
6003 +                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
6004 +               REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
6005 +                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
6006 +               REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
6007 +                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
6008 +
6009 +               udelay(200);
6010 +
6011 +               REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
6012 +                             AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
6013 +
6014 +               REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
6015 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
6016 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
6017 +               REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
6018 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
6019 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
6020 +               REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
6021 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
6022 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
6023 +       }
6024 +}
6025 +
6026  static int ar9003_hw_process_ini(struct ath_hw *ah,
6027                                  struct ath9k_channel *chan)
6028  {
6029 @@ -726,6 +775,8 @@ static int ar9003_hw_process_ini(struct
6030                                            modesIndex);
6031         }
6032
6033 +       ar9003_doubler_fix(ah);
6034 +
6035         /*
6036          * RXGAIN initvals.
6037          */
6038 @@ -1281,6 +1332,7 @@ static void ar9003_hw_ani_cache_ini_regs
6039  static void ar9003_hw_set_radar_params(struct ath_hw *ah,
6040                                        struct ath_hw_radar_conf *conf)
6041  {
6042 +       unsigned int regWrites = 0;
6043         u32 radar_0 = 0, radar_1 = 0;
6044
6045         if (!conf) {
6046 @@ -1307,6 +1359,11 @@ static void ar9003_hw_set_radar_params(s
6047                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
6048         else
6049                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
6050 +
6051 +       if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
6052 +               REG_WRITE_ARRAY(&ah->ini_dfs,
6053 +                               IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
6054 +       }
6055  }
6056
6057  static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
6058 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
6059 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
6060 @@ -341,14 +341,15 @@
6061  #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ     -95
6062  #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ     -100
6063
6064 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ -95
6065 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ -100
6066 +
6067  #define AR_PHY_CCA_NOM_VAL_9462_2GHZ          -127
6068  #define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ     -127
6069  #define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ     -60
6070 -#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ -95
6071  #define AR_PHY_CCA_NOM_VAL_9462_5GHZ          -127
6072  #define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ     -127
6073  #define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ     -60
6074 -#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ -100
6075
6076  #define AR_PHY_CCA_NOM_VAL_9330_2GHZ          -118
6077
6078 @@ -656,13 +657,24 @@
6079  #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT   ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)
6080  #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)
6081  #define AR_PHY_65NM_CH0_SYNTH7      0x16098
6082 +#define AR_PHY_65NM_CH0_SYNTH12     0x160ac
6083  #define AR_PHY_65NM_CH0_BIAS1       0x160c0
6084  #define AR_PHY_65NM_CH0_BIAS2       0x160c4
6085  #define AR_PHY_65NM_CH0_BIAS4       0x160cc
6086 +#define AR_PHY_65NM_CH0_RXTX2       0x16104
6087 +#define AR_PHY_65NM_CH1_RXTX2       0x16504
6088 +#define AR_PHY_65NM_CH2_RXTX2       0x16904
6089  #define AR_PHY_65NM_CH0_RXTX4       0x1610c
6090  #define AR_PHY_65NM_CH1_RXTX4       0x1650c
6091  #define AR_PHY_65NM_CH2_RXTX4       0x1690c
6092
6093 +#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3           0x00780000
6094 +#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S         19
6095 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK         0x00000004
6096 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S       2
6097 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK        0x00000008
6098 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S      3
6099 +
6100  #define AR_CH0_TOP     (AR_SREV_9300(ah) ? 0x16288 : \
6101                          (((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x1628c : 0x16280)))
6102  #define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
6103 --- a/drivers/net/wireless/rt2x00/rt2x00dev.c
6104 +++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
6105 @@ -181,6 +181,7 @@ static void rt2x00lib_autowakeup(struct
6106  static void rt2x00lib_bc_buffer_iter(void *data, u8 *mac,
6107                                      struct ieee80211_vif *vif)
6108  {
6109 +       struct ieee80211_tx_control control = {};
6110         struct rt2x00_dev *rt2x00dev = data;
6111         struct sk_buff *skb;
6112
6113 @@ -195,7 +196,7 @@ static void rt2x00lib_bc_buffer_iter(voi
6114          */
6115         skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
6116         while (skb) {
6117 -               rt2x00mac_tx(rt2x00dev->hw, NULL, skb);
6118 +               rt2x00mac_tx(rt2x00dev->hw, &control, skb);
6119                 skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
6120         }
6121  }
6122 --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
6123 +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
6124 @@ -898,7 +898,7 @@ static void ar9003_hw_tx_iq_cal_reload(s
6125
6126  static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g)
6127  {
6128 -       int offset[8], total = 0, test;
6129 +       int offset[8] = {0}, total = 0, test;
6130         int agc_out, i;
6131
6132         REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
6133 @@ -923,12 +923,18 @@ static void ar9003_hw_manual_peak_cal(st
6134                       AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR, 0x1);
6135         REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
6136                       AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0x1);
6137 -       if (is_2g)
6138 -               REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
6139 -                             AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0);
6140 -       else
6141 +
6142 +       if (AR_SREV_9330_11(ah)) {
6143                 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
6144 -                             AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0);
6145 +                             AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, 0x0);
6146 +       } else {
6147 +               if (is_2g)
6148 +                       REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
6149 +                                     AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0);
6150 +               else
6151 +                       REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
6152 +                                     AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0);
6153 +       }
6154
6155         for (i = 6; i > 0; i--) {
6156                 offset[i] = BIT(i - 1);
6157 @@ -964,9 +970,9 @@ static void ar9003_hw_manual_peak_cal(st
6158                       AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0);
6159  }
6160
6161 -static void ar9003_hw_do_manual_peak_cal(struct ath_hw *ah,
6162 -                                        struct ath9k_channel *chan,
6163 -                                        bool run_rtt_cal)
6164 +static void ar9003_hw_do_pcoem_manual_peak_cal(struct ath_hw *ah,
6165 +                                              struct ath9k_channel *chan,
6166 +                                              bool run_rtt_cal)
6167  {
6168         struct ath9k_hw_cal_data *caldata = ah->caldata;
6169         int i;
6170 @@ -1040,14 +1046,14 @@ static void ar9003_hw_cl_cal_post_proc(s
6171         }
6172  }
6173
6174 -static bool ar9003_hw_init_cal(struct ath_hw *ah,
6175 -                              struct ath9k_channel *chan)
6176 +static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
6177 +                                    struct ath9k_channel *chan)
6178  {
6179         struct ath_common *common = ath9k_hw_common(ah);
6180         struct ath9k_hw_cal_data *caldata = ah->caldata;
6181         bool txiqcal_done = false;
6182         bool is_reusable = true, status = true;
6183 -       bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false;
6184 +       bool run_rtt_cal = false, run_agc_cal;
6185         bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
6186         u32 rx_delay = 0;
6187         u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
6188 @@ -1119,22 +1125,12 @@ static bool ar9003_hw_init_cal(struct at
6189                         REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
6190                                     AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
6191                 txiqcal_done = run_agc_cal = true;
6192 -       } else if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags)) {
6193 -               run_agc_cal = true;
6194 -               sep_iq_cal = true;
6195         }
6196
6197  skip_tx_iqcal:
6198         if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
6199                 ar9003_mci_init_cal_req(ah, &is_reusable);
6200
6201 -       if (sep_iq_cal) {
6202 -               txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
6203 -               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
6204 -               udelay(5);
6205 -               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
6206 -       }
6207 -
6208         if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
6209                 rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);
6210                 /* Disable BB_active */
6211 @@ -1155,7 +1151,7 @@ skip_tx_iqcal:
6212                                        AR_PHY_AGC_CONTROL_CAL,
6213                                        0, AH_WAIT_TIMEOUT);
6214
6215 -               ar9003_hw_do_manual_peak_cal(ah, chan, run_rtt_cal);
6216 +               ar9003_hw_do_pcoem_manual_peak_cal(ah, chan, run_rtt_cal);
6217         }
6218
6219         if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
6220 @@ -1228,13 +1224,112 @@ skip_tx_iqcal:
6221         return true;
6222  }
6223
6224 +static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
6225 +                                  struct ath9k_channel *chan)
6226 +{
6227 +       struct ath_common *common = ath9k_hw_common(ah);
6228 +       struct ath9k_hw_cal_data *caldata = ah->caldata;
6229 +       bool txiqcal_done = false;
6230 +       bool is_reusable = true, status = true;
6231 +       bool run_agc_cal = false, sep_iq_cal = false;
6232 +
6233 +       /* Use chip chainmask only for calibration */
6234 +       ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
6235 +
6236 +       if (ah->enabled_cals & TX_CL_CAL) {
6237 +               REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
6238 +               run_agc_cal = true;
6239 +       }
6240 +
6241 +       if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
6242 +               goto skip_tx_iqcal;
6243 +
6244 +       /* Do Tx IQ Calibration */
6245 +       REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
6246 +                     AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
6247 +                     DELPT);
6248 +
6249 +       /*
6250 +        * For AR9485 or later chips, TxIQ cal runs as part of
6251 +        * AGC calibration. Specifically, AR9550 in SoC chips.
6252 +        */
6253 +       if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
6254 +               txiqcal_done = true;
6255 +               run_agc_cal = true;
6256 +       } else {
6257 +               sep_iq_cal = true;
6258 +               run_agc_cal = true;
6259 +       }
6260 +
6261 +       /*
6262 +        * In the SoC family, this will run for AR9300, AR9331 and AR9340.
6263 +        */
6264 +       if (sep_iq_cal) {
6265 +               txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
6266 +               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
6267 +               udelay(5);
6268 +               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
6269 +       }
6270 +
6271 +skip_tx_iqcal:
6272 +       if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
6273 +               if (AR_SREV_9330_11(ah))
6274 +                       ar9003_hw_manual_peak_cal(ah, 0, IS_CHAN_2GHZ(chan));
6275 +
6276 +               /* Calibrate the AGC */
6277 +               REG_WRITE(ah, AR_PHY_AGC_CONTROL,
6278 +                         REG_READ(ah, AR_PHY_AGC_CONTROL) |
6279 +                         AR_PHY_AGC_CONTROL_CAL);
6280 +
6281 +               /* Poll for offset calibration complete */
6282 +               status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
6283 +                                      AR_PHY_AGC_CONTROL_CAL,
6284 +                                      0, AH_WAIT_TIMEOUT);
6285 +       }
6286 +
6287 +       if (!status) {
6288 +               ath_dbg(common, CALIBRATE,
6289 +                       "offset calibration failed to complete in %d ms; noisy environment?\n",
6290 +                       AH_WAIT_TIMEOUT / 1000);
6291 +               return false;
6292 +       }
6293 +
6294 +       if (txiqcal_done)
6295 +               ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
6296 +
6297 +       /* Revert chainmask to runtime parameters */
6298 +       ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
6299 +
6300 +       /* Initialize list pointers */
6301 +       ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
6302 +
6303 +       INIT_CAL(&ah->iq_caldata);
6304 +       INSERT_CAL(ah, &ah->iq_caldata);
6305 +       ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
6306 +
6307 +       /* Initialize current pointer to first element in list */
6308 +       ah->cal_list_curr = ah->cal_list;
6309 +
6310 +       if (ah->cal_list_curr)
6311 +               ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
6312 +
6313 +       if (caldata)
6314 +               caldata->CalValid = 0;
6315 +
6316 +       return true;
6317 +}
6318 +
6319  void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
6320  {
6321         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
6322         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
6323
6324 +       if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9565(ah))
6325 +               priv_ops->init_cal = ar9003_hw_init_cal_pcoem;
6326 +       else
6327 +               priv_ops->init_cal = ar9003_hw_init_cal_soc;
6328 +
6329         priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
6330 -       priv_ops->init_cal = ar9003_hw_init_cal;
6331         priv_ops->setup_calibration = ar9003_hw_setup_calibration;
6332
6333         ops->calibrate = ar9003_hw_calibrate;
6334 --- a/drivers/net/wireless/ath/ath9k/common.c
6335 +++ b/drivers/net/wireless/ath/ath9k/common.c
6336 @@ -98,10 +98,8 @@ struct ath9k_channel *ath9k_cmn_get_chan
6337  {
6338         struct ieee80211_channel *curchan = chandef->chan;
6339         struct ath9k_channel *channel;
6340 -       u8 chan_idx;
6341
6342 -       chan_idx = curchan->hw_value;
6343 -       channel = &ah->channels[chan_idx];
6344 +       channel = &ah->channels[curchan->hw_value];
6345         ath9k_cmn_update_ichannel(channel, chandef);
6346
6347         return channel;
6348 --- a/net/mac80211/rc80211_minstrel_ht.c
6349 +++ b/net/mac80211/rc80211_minstrel_ht.c
6350 @@ -226,7 +226,7 @@ minstrel_ht_calc_tp(struct minstrel_ht_s
6351                 nsecs = 1000 * mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
6352
6353         nsecs += minstrel_mcs_groups[group].duration[rate];
6354 -       tp = 1000000 * ((mr->probability * 1000) / nsecs);
6355 +       tp = 1000000 * ((prob * 1000) / nsecs);
6356
6357         mr->cur_tp = MINSTREL_TRUNC(tp);
6358  }
6359 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
6360 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
6361 @@ -3965,7 +3965,7 @@ static void ar9003_hw_apply_tuning_caps(
6362         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
6363         u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
6364
6365 -       if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
6366 +       if (AR_SREV_9340(ah))
6367                 return;
6368
6369         if (eep->baseEepHeader.featureEnable & 0x40) {
6370 @@ -3984,18 +3984,20 @@ static void ar9003_hw_quick_drop_apply(s
6371         int quick_drop;
6372         s32 t[3], f[3] = {5180, 5500, 5785};
6373
6374 -       if (!(pBase->miscConfiguration & BIT(1)))
6375 +       if (!(pBase->miscConfiguration & BIT(4)))
6376                 return;
6377
6378 -       if (freq < 4000)
6379 -               quick_drop = eep->modalHeader2G.quick_drop;
6380 -       else {
6381 -               t[0] = eep->base_ext1.quick_drop_low;
6382 -               t[1] = eep->modalHeader5G.quick_drop;
6383 -               t[2] = eep->base_ext1.quick_drop_high;
6384 -               quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
6385 +       if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9340(ah)) {
6386 +               if (freq < 4000) {
6387 +                       quick_drop = eep->modalHeader2G.quick_drop;
6388 +               } else {
6389 +                       t[0] = eep->base_ext1.quick_drop_low;
6390 +                       t[1] = eep->modalHeader5G.quick_drop;
6391 +                       t[2] = eep->base_ext1.quick_drop_high;
6392 +                       quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
6393 +               }
6394 +               REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
6395         }
6396 -       REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
6397  }
6398
6399  static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
6400 @@ -4035,7 +4037,7 @@ static void ar9003_hw_xlna_bias_strength
6401         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
6402         u8 bias;
6403
6404 -       if (!(eep->baseEepHeader.featureEnable & 0x40))
6405 +       if (!(eep->baseEepHeader.miscConfiguration & 0x40))
6406                 return;
6407
6408         if (!AR_SREV_9300(ah))
6409 @@ -4120,7 +4122,7 @@ static void ath9k_hw_ar9300_set_board_va
6410         ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
6411         ar9003_hw_atten_apply(ah, chan);
6412         ar9003_hw_quick_drop_apply(ah, chan->channel);
6413 -       if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
6414 +       if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
6415                 ar9003_hw_internal_regulator_apply(ah);
6416         ar9003_hw_apply_tuning_caps(ah);
6417         ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
6418 --- a/net/mac80211/ieee80211_i.h
6419 +++ b/net/mac80211/ieee80211_i.h
6420 @@ -735,6 +735,7 @@ struct ieee80211_sub_if_data {
6421         int csa_counter_offset_beacon;
6422         int csa_counter_offset_presp;
6423         bool csa_radar_required;
6424 +       struct cfg80211_chan_def csa_chandef;
6425
6426         /* used to reconfigure hardware SM PS */
6427         struct work_struct recalc_smps;
6428 @@ -811,6 +812,9 @@ static inline void sdata_unlock(struct i
6429         __release(&sdata->wdev.mtx);
6430  }
6431
6432 +#define sdata_dereference(p, sdata) \
6433 +       rcu_dereference_protected(p, lockdep_is_held(&sdata->wdev.mtx))
6434 +
6435  static inline void
6436  sdata_assert_lock(struct ieee80211_sub_if_data *sdata)
6437  {
6438 @@ -1098,7 +1102,6 @@ struct ieee80211_local {
6439         enum mac80211_scan_state next_scan_state;
6440         struct delayed_work scan_work;
6441         struct ieee80211_sub_if_data __rcu *scan_sdata;
6442 -       struct cfg80211_chan_def csa_chandef;
6443         /* For backward compatibility only -- do not use */
6444         struct cfg80211_chan_def _oper_chandef;
6445
6446 @@ -1236,6 +1239,7 @@ struct ieee80211_csa_ie {
6447         u8 mode;
6448         u8 count;
6449         u8 ttl;
6450 +       u16 pre_value;
6451  };
6452
6453  /* Parsed Information Elements */
6454 @@ -1738,7 +1742,6 @@ ieee80211_vif_change_bandwidth(struct ie
6455  /* NOTE: only use ieee80211_vif_change_channel() for channel switch */
6456  int __must_check
6457  ieee80211_vif_change_channel(struct ieee80211_sub_if_data *sdata,
6458 -                            const struct cfg80211_chan_def *chandef,
6459                              u32 *changed);
6460  void ieee80211_vif_release_channel(struct ieee80211_sub_if_data *sdata);
6461  void ieee80211_vif_vlan_copy_chanctx(struct ieee80211_sub_if_data *sdata);
6462 --- a/net/mac80211/chan.c
6463 +++ b/net/mac80211/chan.c
6464 @@ -411,12 +411,12 @@ int ieee80211_vif_use_channel(struct iee
6465  }
6466
6467  int ieee80211_vif_change_channel(struct ieee80211_sub_if_data *sdata,
6468 -                                const struct cfg80211_chan_def *chandef,
6469                                  u32 *changed)
6470  {
6471         struct ieee80211_local *local = sdata->local;
6472         struct ieee80211_chanctx_conf *conf;
6473         struct ieee80211_chanctx *ctx;
6474 +       const struct cfg80211_chan_def *chandef = &sdata->csa_chandef;
6475         int ret;
6476         u32 chanctx_changed = 0;
6477
6478 --- a/net/mac80211/ibss.c
6479 +++ b/net/mac80211/ibss.c
6480 @@ -534,7 +534,7 @@ int ieee80211_ibss_finish_csa(struct iee
6481         int err;
6482         u16 capability;
6483
6484 -       sdata_lock(sdata);
6485 +       sdata_assert_lock(sdata);
6486         /* update cfg80211 bss information with the new channel */
6487         if (!is_zero_ether_addr(ifibss->bssid)) {
6488                 capability = WLAN_CAPABILITY_IBSS;
6489 @@ -550,16 +550,15 @@ int ieee80211_ibss_finish_csa(struct iee
6490                                         capability);
6491                 /* XXX: should not really modify cfg80211 data */
6492                 if (cbss) {
6493 -                       cbss->channel = sdata->local->csa_chandef.chan;
6494 +                       cbss->channel = sdata->csa_chandef.chan;
6495                         cfg80211_put_bss(sdata->local->hw.wiphy, cbss);
6496                 }
6497         }
6498
6499 -       ifibss->chandef = sdata->local->csa_chandef;
6500 +       ifibss->chandef = sdata->csa_chandef;
6501
6502         /* generate the beacon */
6503         err = ieee80211_ibss_csa_beacon(sdata, NULL);
6504 -       sdata_unlock(sdata);
6505         if (err < 0)
6506                 return err;
6507
6508 @@ -922,7 +921,7 @@ ieee80211_ibss_process_chanswitch(struct
6509                                 IEEE80211_MAX_QUEUE_MAP,
6510                                 IEEE80211_QUEUE_STOP_REASON_CSA);
6511
6512 -       sdata->local->csa_chandef = params.chandef;
6513 +       sdata->csa_chandef = params.chandef;
6514         sdata->vif.csa_active = true;
6515
6516         ieee80211_bss_info_change_notify(sdata, err);
6517 --- a/net/mac80211/mesh.c
6518 +++ b/net/mac80211/mesh.c
6519 @@ -943,14 +943,19 @@ ieee80211_mesh_process_chnswitch(struct
6520                  params.chandef.chan->center_freq);
6521
6522         params.block_tx = csa_ie.mode & WLAN_EID_CHAN_SWITCH_PARAM_TX_RESTRICT;
6523 -       if (beacon)
6524 +       if (beacon) {
6525                 ifmsh->chsw_ttl = csa_ie.ttl - 1;
6526 -       else
6527 -               ifmsh->chsw_ttl = 0;
6528 +               if (ifmsh->pre_value >= csa_ie.pre_value)
6529 +                       return false;
6530 +               ifmsh->pre_value = csa_ie.pre_value;
6531 +       }
6532
6533 -       if (ifmsh->chsw_ttl > 0)
6534 +       if (ifmsh->chsw_ttl < ifmsh->mshcfg.dot11MeshTTL) {
6535                 if (ieee80211_mesh_csa_beacon(sdata, &params, false) < 0)
6536                         return false;
6537 +       } else {
6538 +               return false;
6539 +       }
6540
6541         sdata->csa_radar_required = params.radar_required;
6542
6543 @@ -959,7 +964,7 @@ ieee80211_mesh_process_chnswitch(struct
6544                                 IEEE80211_MAX_QUEUE_MAP,
6545                                 IEEE80211_QUEUE_STOP_REASON_CSA);
6546
6547 -       sdata->local->csa_chandef = params.chandef;
6548 +       sdata->csa_chandef = params.chandef;
6549         sdata->vif.csa_active = true;
6550
6551         ieee80211_bss_info_change_notify(sdata, err);
6552 @@ -1163,7 +1168,6 @@ static int mesh_fwd_csa_frame(struct iee
6553         offset_ttl = (len < 42) ? 7 : 10;
6554         *(pos + offset_ttl) -= 1;
6555         *(pos + offset_ttl + 1) &= ~WLAN_EID_CHAN_SWITCH_PARAM_INITIATOR;
6556 -       sdata->u.mesh.chsw_ttl = *(pos + offset_ttl);
6557
6558         memcpy(mgmt_fwd, mgmt, len);
6559         eth_broadcast_addr(mgmt_fwd->da);
6560 @@ -1182,7 +1186,7 @@ static void mesh_rx_csa_frame(struct iee
6561         u16 pre_value;
6562         bool fwd_csa = true;
6563         size_t baselen;
6564 -       u8 *pos, ttl;
6565 +       u8 *pos;
6566
6567         if (mgmt->u.action.u.measurement.action_code !=
6568             WLAN_ACTION_SPCT_CHL_SWITCH)
6569 @@ -1193,8 +1197,8 @@ static void mesh_rx_csa_frame(struct iee
6570                            u.action.u.chan_switch.variable);
6571         ieee802_11_parse_elems(pos, len - baselen, false, &elems);
6572
6573 -       ttl = elems.mesh_chansw_params_ie->mesh_ttl;
6574 -       if (!--ttl)
6575 +       ifmsh->chsw_ttl = elems.mesh_chansw_params_ie->mesh_ttl;
6576 +       if (!--ifmsh->chsw_ttl)
6577                 fwd_csa = false;
6578
6579         pre_value = le16_to_cpu(elems.mesh_chansw_params_ie->mesh_pre_value);
6580 --- a/net/mac80211/spectmgmt.c
6581 +++ b/net/mac80211/spectmgmt.c
6582 @@ -78,6 +78,8 @@ int ieee80211_parse_ch_switch_ie(struct
6583         if (elems->mesh_chansw_params_ie) {
6584                 csa_ie->ttl = elems->mesh_chansw_params_ie->mesh_ttl;
6585                 csa_ie->mode = elems->mesh_chansw_params_ie->mesh_flags;
6586 +               csa_ie->pre_value = le16_to_cpu(
6587 +                               elems->mesh_chansw_params_ie->mesh_pre_value);
6588         }
6589
6590         new_freq = ieee80211_channel_to_frequency(new_chan_no, new_band);
6591 --- a/drivers/net/wireless/ath/ath6kl/cfg80211.c
6592 +++ b/drivers/net/wireless/ath/ath6kl/cfg80211.c
6593 @@ -1109,7 +1109,9 @@ void ath6kl_cfg80211_ch_switch_notify(st
6594                                 (mode == WMI_11G_HT20) ?
6595                                         NL80211_CHAN_HT20 : NL80211_CHAN_NO_HT);
6596
6597 +       mutex_lock(vif->wdev->mtx);
6598         cfg80211_ch_switch_notify(vif->ndev, &chandef);
6599 +       mutex_unlock(vif->wdev->mtx);
6600  }
6601
6602  static int ath6kl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
6603 --- a/drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h
6604 +++ b/drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h
6605 @@ -20,6 +20,44 @@
6606
6607  /* AR9462 2.1 */
6608
6609 +#define ar9462_2p1_mac_postamble ar9462_2p0_mac_postamble
6610 +
6611 +#define ar9462_2p1_baseband_core ar9462_2p0_baseband_core
6612 +
6613 +#define ar9462_2p1_radio_core ar9462_2p0_radio_core
6614 +
6615 +#define ar9462_2p1_radio_postamble ar9462_2p0_radio_postamble
6616 +
6617 +#define ar9462_2p1_soc_postamble ar9462_2p0_soc_postamble
6618 +
6619 +#define ar9462_2p1_radio_postamble_sys2ant ar9462_2p0_radio_postamble_sys2ant
6620 +
6621 +#define ar9462_2p1_common_rx_gain ar9462_2p0_common_rx_gain
6622 +
6623 +#define ar9462_2p1_common_mixed_rx_gain ar9462_2p0_common_mixed_rx_gain
6624 +
6625 +#define ar9462_2p1_common_5g_xlna_only_rxgain ar9462_2p0_common_5g_xlna_only_rxgain
6626 +
6627 +#define ar9462_2p1_baseband_core_mix_rxgain ar9462_2p0_baseband_core_mix_rxgain
6628 +
6629 +#define ar9462_2p1_baseband_postamble_mix_rxgain ar9462_2p0_baseband_postamble_mix_rxgain
6630 +
6631 +#define ar9462_2p1_baseband_postamble_5g_xlna ar9462_2p0_baseband_postamble_5g_xlna
6632 +
6633 +#define ar9462_2p1_common_wo_xlna_rx_gain ar9462_2p0_common_wo_xlna_rx_gain
6634 +
6635 +#define ar9462_2p1_modes_low_ob_db_tx_gain ar9462_2p0_modes_low_ob_db_tx_gain
6636 +
6637 +#define ar9462_2p1_modes_high_ob_db_tx_gain ar9462_2p0_modes_high_ob_db_tx_gain
6638 +
6639 +#define ar9462_2p1_modes_mix_ob_db_tx_gain ar9462_2p0_modes_mix_ob_db_tx_gain
6640 +
6641 +#define ar9462_2p1_modes_fast_clock ar9462_2p0_modes_fast_clock
6642 +
6643 +#define ar9462_2p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
6644 +
6645 +#define ar9462_2p1_pciephy_clkreq_disable_L1 ar9462_2p0_pciephy_clkreq_disable_L1
6646 +
6647  static const u32 ar9462_2p1_mac_core[][2] = {
6648         /* Addr      allmodes  */
6649         {0x00000008, 0x00000000},
6650 @@ -183,168 +221,6 @@ static const u32 ar9462_2p1_mac_core[][2
6651         {0x000083d0, 0x000301ff},
6652  };
6653
6654 -static const u32 ar9462_2p1_mac_postamble[][5] = {
6655 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
6656 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
6657 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
6658 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
6659 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
6660 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
6661 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
6662 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
6663 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
6664 -};
6665 -
6666 -static const u32 ar9462_2p1_baseband_core[][2] = {
6667 -       /* Addr      allmodes  */
6668 -       {0x00009800, 0xafe68e30},
6669 -       {0x00009804, 0xfd14e000},
6670 -       {0x00009808, 0x9c0a9f6b},
6671 -       {0x0000980c, 0x04900000},
6672 -       {0x00009814, 0x9280c00a},
6673 -       {0x00009818, 0x00000000},
6674 -       {0x0000981c, 0x00020028},
6675 -       {0x00009834, 0x6400a290},
6676 -       {0x00009838, 0x0108ecff},
6677 -       {0x0000983c, 0x0d000600},
6678 -       {0x00009880, 0x201fff00},
6679 -       {0x00009884, 0x00001042},
6680 -       {0x000098a4, 0x00200400},
6681 -       {0x000098b0, 0x32440bbe},
6682 -       {0x000098d0, 0x004b6a8e},
6683 -       {0x000098d4, 0x00000820},
6684 -       {0x000098dc, 0x00000000},
6685 -       {0x000098e4, 0x01ffffff},
6686 -       {0x000098e8, 0x01ffffff},
6687 -       {0x000098ec, 0x01ffffff},
6688 -       {0x000098f0, 0x00000000},
6689 -       {0x000098f4, 0x00000000},
6690 -       {0x00009bf0, 0x80000000},
6691 -       {0x00009c04, 0xff55ff55},
6692 -       {0x00009c08, 0x0320ff55},
6693 -       {0x00009c0c, 0x00000000},
6694 -       {0x00009c10, 0x00000000},
6695 -       {0x00009c14, 0x00046384},
6696 -       {0x00009c18, 0x05b6b440},
6697 -       {0x00009c1c, 0x00b6b440},
6698 -       {0x00009d00, 0xc080a333},
6699 -       {0x00009d04, 0x40206c10},
6700 -       {0x00009d08, 0x009c4060},
6701 -       {0x00009d0c, 0x9883800a},
6702 -       {0x00009d10, 0x01834061},
6703 -       {0x00009d14, 0x00c0040b},
6704 -       {0x00009d18, 0x00000000},
6705 -       {0x00009e08, 0x0038230c},
6706 -       {0x00009e24, 0x990bb515},
6707 -       {0x00009e28, 0x0c6f0000},
6708 -       {0x00009e30, 0x06336f77},
6709 -       {0x00009e34, 0x6af6532f},
6710 -       {0x00009e38, 0x0cc80c00},
6711 -       {0x00009e40, 0x15262820},
6712 -       {0x00009e4c, 0x00001004},
6713 -       {0x00009e50, 0x00ff03f1},
6714 -       {0x00009e54, 0xe4c555c2},
6715 -       {0x00009e58, 0xfd857722},
6716 -       {0x00009e5c, 0xe9198724},
6717 -       {0x00009fc0, 0x803e4788},
6718 -       {0x00009fc4, 0x0001efb5},
6719 -       {0x00009fcc, 0x40000014},
6720 -       {0x00009fd0, 0x0a193b93},
6721 -       {0x0000a20c, 0x00000000},
6722 -       {0x0000a220, 0x00000000},
6723 -       {0x0000a224, 0x00000000},
6724 -       {0x0000a228, 0x10002310},
6725 -       {0x0000a23c, 0x00000000},
6726 -       {0x0000a244, 0x0c000000},
6727 -       {0x0000a2a0, 0x00000001},
6728 -       {0x0000a2c0, 0x00000001},
6729 -       {0x0000a2c8, 0x00000000},
6730 -       {0x0000a2cc, 0x18c43433},
6731 -       {0x0000a2d4, 0x00000000},
6732 -       {0x0000a2ec, 0x00000000},
6733 -       {0x0000a2f0, 0x00000000},
6734 -       {0x0000a2f4, 0x00000000},
6735 -       {0x0000a2f8, 0x00000000},
6736 -       {0x0000a344, 0x00000000},
6737 -       {0x0000a34c, 0x00000000},
6738 -       {0x0000a350, 0x0000a000},
6739 -       {0x0000a364, 0x00000000},
6740 -       {0x0000a370, 0x00000000},
6741 -       {0x0000a390, 0x00000001},
6742 -       {0x0000a394, 0x00000444},
6743 -       {0x0000a398, 0x001f0e0f},
6744 -       {0x0000a39c, 0x0075393f},
6745 -       {0x0000a3a0, 0xb79f6427},
6746 -       {0x0000a3c0, 0x20202020},
6747 -       {0x0000a3c4, 0x22222220},
6748 -       {0x0000a3c8, 0x20200020},
6749 -       {0x0000a3cc, 0x20202020},
6750 -       {0x0000a3d0, 0x20202020},
6751 -       {0x0000a3d4, 0x20202020},
6752 -       {0x0000a3d8, 0x20202020},
6753 -       {0x0000a3dc, 0x20202020},
6754 -       {0x0000a3e0, 0x20202020},
6755 -       {0x0000a3e4, 0x20202020},
6756 -       {0x0000a3e8, 0x20202020},
6757 -       {0x0000a3ec, 0x20202020},
6758 -       {0x0000a3f0, 0x00000000},
6759 -       {0x0000a3f4, 0x00000006},
6760 -       {0x0000a3f8, 0x0c9bd380},
6761 -       {0x0000a3fc, 0x000f0f01},
6762 -       {0x0000a400, 0x8fa91f01},
6763 -       {0x0000a404, 0x00000000},
6764 -       {0x0000a408, 0x0e79e5c6},
6765 -       {0x0000a40c, 0x00820820},
6766 -       {0x0000a414, 0x1ce739ce},
6767 -       {0x0000a418, 0x2d001dce},
6768 -       {0x0000a434, 0x00000000},
6769 -       {0x0000a438, 0x00001801},
6770 -       {0x0000a43c, 0x00100000},
6771 -       {0x0000a444, 0x00000000},
6772 -       {0x0000a448, 0x05000080},
6773 -       {0x0000a44c, 0x00000001},
6774 -       {0x0000a450, 0x00010000},
6775 -       {0x0000a454, 0x07000000},
6776 -       {0x0000a644, 0xbfad9d74},
6777 -       {0x0000a648, 0x0048060a},
6778 -       {0x0000a64c, 0x00002037},
6779 -       {0x0000a670, 0x03020100},
6780 -       {0x0000a674, 0x09080504},
6781 -       {0x0000a678, 0x0d0c0b0a},
6782 -       {0x0000a67c, 0x13121110},
6783 -       {0x0000a680, 0x31301514},
6784 -       {0x0000a684, 0x35343332},
6785 -       {0x0000a688, 0x00000036},
6786 -       {0x0000a690, 0x00000838},
6787 -       {0x0000a6b0, 0x0000000a},
6788 -       {0x0000a6b4, 0x00512c01},
6789 -       {0x0000a7c0, 0x00000000},
6790 -       {0x0000a7c4, 0xfffffffc},
6791 -       {0x0000a7c8, 0x00000000},
6792 -       {0x0000a7cc, 0x00000000},
6793 -       {0x0000a7d0, 0x00000000},
6794 -       {0x0000a7d4, 0x00000004},
6795 -       {0x0000a7dc, 0x00000000},
6796 -       {0x0000a7f0, 0x80000000},
6797 -       {0x0000a8d0, 0x004b6a8e},
6798 -       {0x0000a8d4, 0x00000820},
6799 -       {0x0000a8dc, 0x00000000},
6800 -       {0x0000a8f0, 0x00000000},
6801 -       {0x0000a8f4, 0x00000000},
6802 -       {0x0000abf0, 0x80000000},
6803 -       {0x0000b2d0, 0x00000080},
6804 -       {0x0000b2d4, 0x00000000},
6805 -       {0x0000b2ec, 0x00000000},
6806 -       {0x0000b2f0, 0x00000000},
6807 -       {0x0000b2f4, 0x00000000},
6808 -       {0x0000b2f8, 0x00000000},
6809 -       {0x0000b408, 0x0e79e5c0},
6810 -       {0x0000b40c, 0x00820820},
6811 -       {0x0000b420, 0x00000000},
6812 -       {0x0000b6b0, 0x0000000a},
6813 -       {0x0000b6b4, 0x00000001},
6814 -};
6815 -
6816  static const u32 ar9462_2p1_baseband_postamble[][5] = {
6817         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
6818         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
6819 @@ -361,7 +237,7 @@ static const u32 ar9462_2p1_baseband_pos
6820         {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32365a5e},
6821         {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
6822         {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
6823 -       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
6824 +       {0x00009e20, 0x000003a5, 0x000003a5, 0x000003a5, 0x000003a5},
6825         {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
6826         {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
6827         {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27},
6828 @@ -400,1375 +276,16 @@ static const u32 ar9462_2p1_baseband_pos
6829         {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x00100000},
6830         {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
6831         {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
6832 -       {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
6833 +       {0x0000ae20, 0x000001a6, 0x000001a6, 0x000001aa, 0x000001aa},
6834         {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
6835  };
6836
6837 -static const u32 ar9462_2p1_radio_core[][2] = {
6838 -       /* Addr      allmodes  */
6839 -       {0x00016000, 0x36db6db6},
6840 -       {0x00016004, 0x6db6db40},
6841 -       {0x00016008, 0x73f00000},
6842 -       {0x0001600c, 0x00000000},
6843 -       {0x00016010, 0x6d820001},
6844 -       {0x00016040, 0x7f80fff8},
6845 -       {0x0001604c, 0x2699e04f},
6846 -       {0x00016050, 0x6db6db6c},
6847 -       {0x00016058, 0x6c200000},
6848 -       {0x00016080, 0x000c0000},
6849 -       {0x00016084, 0x9a68048c},
6850 -       {0x00016088, 0x54214514},
6851 -       {0x0001608c, 0x1203040b},
6852 -       {0x00016090, 0x24926490},
6853 -       {0x00016098, 0xd2888888},
6854 -       {0x000160a0, 0x0a108ffe},
6855 -       {0x000160a4, 0x812fc491},
6856 -       {0x000160a8, 0x423c8000},
6857 -       {0x000160b4, 0x92000000},
6858 -       {0x000160b8, 0x0285dddc},
6859 -       {0x000160bc, 0x02908888},
6860 -       {0x000160c0, 0x00adb6d0},
6861 -       {0x000160c4, 0x6db6db60},
6862 -       {0x000160c8, 0x6db6db6c},
6863 -       {0x000160cc, 0x0de6c1b0},
6864 -       {0x00016100, 0x3fffbe04},
6865 -       {0x00016104, 0xfff80000},
6866 -       {0x00016108, 0x00200400},
6867 -       {0x00016110, 0x00000000},
6868 -       {0x00016144, 0x02084080},
6869 -       {0x00016148, 0x000080c0},
6870 -       {0x00016280, 0x050a0001},
6871 -       {0x00016284, 0x3d841418},
6872 -       {0x00016288, 0x00000000},
6873 -       {0x0001628c, 0xe3000000},
6874 -       {0x00016290, 0xa1005080},
6875 -       {0x00016294, 0x00000020},
6876 -       {0x00016298, 0x54a82900},
6877 -       {0x00016340, 0x121e4276},
6878 -       {0x00016344, 0x00300000},
6879 -       {0x00016400, 0x36db6db6},
6880 -       {0x00016404, 0x6db6db40},
6881 -       {0x00016408, 0x73f00000},
6882 -       {0x0001640c, 0x00000000},
6883 -       {0x00016410, 0x6c800001},
6884 -       {0x00016440, 0x7f80fff8},
6885 -       {0x0001644c, 0x4699e04f},
6886 -       {0x00016450, 0x6db6db6c},
6887 -       {0x00016500, 0x3fffbe04},
6888 -       {0x00016504, 0xfff80000},
6889 -       {0x00016508, 0x00200400},
6890 -       {0x00016510, 0x00000000},
6891 -       {0x00016544, 0x02084080},
6892 -       {0x00016548, 0x000080c0},
6893 -};
6894 -
6895 -static const u32 ar9462_2p1_radio_postamble[][5] = {
6896 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
6897 -       {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
6898 -       {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
6899 -       {0x0001610c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
6900 -       {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
6901 -};
6902 -
6903  static const u32 ar9462_2p1_soc_preamble[][2] = {
6904         /* Addr      allmodes  */
6905 -       {0x000040a4, 0x00a0c1c9},
6906 +       {0x000040a4, 0x00a0c9c9},
6907         {0x00007020, 0x00000000},
6908         {0x00007034, 0x00000002},
6909         {0x00007038, 0x000004c2},
6910  };
6911
6912 -static const u32 ar9462_2p1_soc_postamble[][5] = {
6913 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
6914 -       {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
6915 -};
6916 -
6917 -static const u32 ar9462_2p1_radio_postamble_sys2ant[][5] = {
6918 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
6919 -       {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
6920 -       {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
6921 -       {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
6922 -};
6923 -
6924 -static const u32 ar9462_2p1_common_rx_gain[][2] = {
6925 -       /* Addr      allmodes  */
6926 -       {0x0000a000, 0x00010000},
6927 -       {0x0000a004, 0x00030002},
6928 -       {0x0000a008, 0x00050004},
6929 -       {0x0000a00c, 0x00810080},
6930 -       {0x0000a010, 0x00830082},
6931 -       {0x0000a014, 0x01810180},
6932 -       {0x0000a018, 0x01830182},
6933 -       {0x0000a01c, 0x01850184},
6934 -       {0x0000a020, 0x01890188},
6935 -       {0x0000a024, 0x018b018a},
6936 -       {0x0000a028, 0x018d018c},
6937 -       {0x0000a02c, 0x01910190},
6938 -       {0x0000a030, 0x01930192},
6939 -       {0x0000a034, 0x01950194},
6940 -       {0x0000a038, 0x038a0196},
6941 -       {0x0000a03c, 0x038c038b},
6942 -       {0x0000a040, 0x0390038d},
6943 -       {0x0000a044, 0x03920391},
6944 -       {0x0000a048, 0x03940393},
6945 -       {0x0000a04c, 0x03960395},
6946 -       {0x0000a050, 0x00000000},
6947 -       {0x0000a054, 0x00000000},
6948 -       {0x0000a058, 0x00000000},
6949 -       {0x0000a05c, 0x00000000},
6950 -       {0x0000a060, 0x00000000},
6951 -       {0x0000a064, 0x00000000},
6952 -       {0x0000a068, 0x00000000},
6953 -       {0x0000a06c, 0x00000000},
6954 -       {0x0000a070, 0x00000000},
6955 -       {0x0000a074, 0x00000000},
6956 -       {0x0000a078, 0x00000000},
6957 -       {0x0000a07c, 0x00000000},
6958 -       {0x0000a080, 0x22222229},
6959 -       {0x0000a084, 0x1d1d1d1d},
6960 -       {0x0000a088, 0x1d1d1d1d},
6961 -       {0x0000a08c, 0x1d1d1d1d},
6962 -       {0x0000a090, 0x171d1d1d},
6963 -       {0x0000a094, 0x11111717},
6964 -       {0x0000a098, 0x00030311},
6965 -       {0x0000a09c, 0x00000000},
6966 -       {0x0000a0a0, 0x00000000},
6967 -       {0x0000a0a4, 0x00000000},
6968 -       {0x0000a0a8, 0x00000000},
6969 -       {0x0000a0ac, 0x00000000},
6970 -       {0x0000a0b0, 0x00000000},
6971 -       {0x0000a0b4, 0x00000000},
6972 -       {0x0000a0b8, 0x00000000},
6973 -       {0x0000a0bc, 0x00000000},
6974 -       {0x0000a0c0, 0x001f0000},
6975 -       {0x0000a0c4, 0x01000101},
6976 -       {0x0000a0c8, 0x011e011f},
6977 -       {0x0000a0cc, 0x011c011d},
6978 -       {0x0000a0d0, 0x02030204},
6979 -       {0x0000a0d4, 0x02010202},
6980 -       {0x0000a0d8, 0x021f0200},
6981 -       {0x0000a0dc, 0x0302021e},
6982 -       {0x0000a0e0, 0x03000301},
6983 -       {0x0000a0e4, 0x031e031f},
6984 -       {0x0000a0e8, 0x0402031d},
6985 -       {0x0000a0ec, 0x04000401},
6986 -       {0x0000a0f0, 0x041e041f},
6987 -       {0x0000a0f4, 0x0502041d},
6988 -       {0x0000a0f8, 0x05000501},
6989 -       {0x0000a0fc, 0x051e051f},
6990 -       {0x0000a100, 0x06010602},
6991 -       {0x0000a104, 0x061f0600},
6992 -       {0x0000a108, 0x061d061e},
6993 -       {0x0000a10c, 0x07020703},
6994 -       {0x0000a110, 0x07000701},
6995 -       {0x0000a114, 0x00000000},
6996 -       {0x0000a118, 0x00000000},
6997 -       {0x0000a11c, 0x00000000},
6998 -       {0x0000a120, 0x00000000},
6999 -       {0x0000a124, 0x00000000},
7000 -       {0x0000a128, 0x00000000},
7001 -       {0x0000a12c, 0x00000000},
7002 -       {0x0000a130, 0x00000000},
7003 -       {0x0000a134, 0x00000000},
7004 -       {0x0000a138, 0x00000000},
7005 -       {0x0000a13c, 0x00000000},
7006 -       {0x0000a140, 0x001f0000},
7007 -       {0x0000a144, 0x01000101},
7008 -       {0x0000a148, 0x011e011f},
7009 -       {0x0000a14c, 0x011c011d},
7010 -       {0x0000a150, 0x02030204},
7011 -       {0x0000a154, 0x02010202},
7012 -       {0x0000a158, 0x021f0200},
7013 -       {0x0000a15c, 0x0302021e},
7014 -       {0x0000a160, 0x03000301},
7015 -       {0x0000a164, 0x031e031f},
7016 -       {0x0000a168, 0x0402031d},
7017 -       {0x0000a16c, 0x04000401},
7018 -       {0x0000a170, 0x041e041f},
7019 -       {0x0000a174, 0x0502041d},
7020 -       {0x0000a178, 0x05000501},
7021 -       {0x0000a17c, 0x051e051f},
7022 -       {0x0000a180, 0x06010602},
7023 -       {0x0000a184, 0x061f0600},
7024 -       {0x0000a188, 0x061d061e},
7025 -       {0x0000a18c, 0x07020703},
7026 -       {0x0000a190, 0x07000701},
7027 -       {0x0000a194, 0x00000000},
7028 -       {0x0000a198, 0x00000000},
7029 -       {0x0000a19c, 0x00000000},
7030 -       {0x0000a1a0, 0x00000000},
7031 -       {0x0000a1a4, 0x00000000},
7032 -       {0x0000a1a8, 0x00000000},
7033 -       {0x0000a1ac, 0x00000000},
7034 -       {0x0000a1b0, 0x00000000},
7035 -       {0x0000a1b4, 0x00000000},
7036 -       {0x0000a1b8, 0x00000000},
7037 -       {0x0000a1bc, 0x00000000},
7038 -       {0x0000a1c0, 0x00000000},
7039 -       {0x0000a1c4, 0x00000000},
7040 -       {0x0000a1c8, 0x00000000},
7041 -       {0x0000a1cc, 0x00000000},
7042 -       {0x0000a1d0, 0x00000000},
7043 -       {0x0000a1d4, 0x00000000},
7044 -       {0x0000a1d8, 0x00000000},
7045 -       {0x0000a1dc, 0x00000000},
7046 -       {0x0000a1e0, 0x00000000},
7047 -       {0x0000a1e4, 0x00000000},
7048 -       {0x0000a1e8, 0x00000000},
7049 -       {0x0000a1ec, 0x00000000},
7050 -       {0x0000a1f0, 0x00000396},
7051 -       {0x0000a1f4, 0x00000396},
7052 -       {0x0000a1f8, 0x00000396},
7053 -       {0x0000a1fc, 0x00000196},
7054 -       {0x0000b000, 0x00010000},
7055 -       {0x0000b004, 0x00030002},
7056 -       {0x0000b008, 0x00050004},
7057 -       {0x0000b00c, 0x00810080},
7058 -       {0x0000b010, 0x00830082},
7059 -       {0x0000b014, 0x01810180},
7060 -       {0x0000b018, 0x01830182},
7061 -       {0x0000b01c, 0x01850184},
7062 -       {0x0000b020, 0x02810280},
7063 -       {0x0000b024, 0x02830282},
7064 -       {0x0000b028, 0x02850284},
7065 -       {0x0000b02c, 0x02890288},
7066 -       {0x0000b030, 0x028b028a},
7067 -       {0x0000b034, 0x0388028c},
7068 -       {0x0000b038, 0x038a0389},
7069 -       {0x0000b03c, 0x038c038b},
7070 -       {0x0000b040, 0x0390038d},
7071 -       {0x0000b044, 0x03920391},
7072 -       {0x0000b048, 0x03940393},
7073 -       {0x0000b04c, 0x03960395},
7074 -       {0x0000b050, 0x00000000},
7075 -       {0x0000b054, 0x00000000},
7076 -       {0x0000b058, 0x00000000},
7077 -       {0x0000b05c, 0x00000000},
7078 -       {0x0000b060, 0x00000000},
7079 -       {0x0000b064, 0x00000000},
7080 -       {0x0000b068, 0x00000000},
7081 -       {0x0000b06c, 0x00000000},
7082 -       {0x0000b070, 0x00000000},
7083 -       {0x0000b074, 0x00000000},
7084 -       {0x0000b078, 0x00000000},
7085 -       {0x0000b07c, 0x00000000},
7086 -       {0x0000b080, 0x2a2d2f32},
7087 -       {0x0000b084, 0x21232328},
7088 -       {0x0000b088, 0x19191c1e},
7089 -       {0x0000b08c, 0x12141417},
7090 -       {0x0000b090, 0x07070e0e},
7091 -       {0x0000b094, 0x03030305},
7092 -       {0x0000b098, 0x00000003},
7093 -       {0x0000b09c, 0x00000000},
7094 -       {0x0000b0a0, 0x00000000},
7095 -       {0x0000b0a4, 0x00000000},
7096 -       {0x0000b0a8, 0x00000000},
7097 -       {0x0000b0ac, 0x00000000},
7098 -       {0x0000b0b0, 0x00000000},
7099 -       {0x0000b0b4, 0x00000000},
7100 -       {0x0000b0b8, 0x00000000},
7101 -       {0x0000b0bc, 0x00000000},
7102 -       {0x0000b0c0, 0x003f0020},
7103 -       {0x0000b0c4, 0x00400041},
7104 -       {0x0000b0c8, 0x0140005f},
7105 -       {0x0000b0cc, 0x0160015f},
7106 -       {0x0000b0d0, 0x017e017f},
7107 -       {0x0000b0d4, 0x02410242},
7108 -       {0x0000b0d8, 0x025f0240},
7109 -       {0x0000b0dc, 0x027f0260},
7110 -       {0x0000b0e0, 0x0341027e},
7111 -       {0x0000b0e4, 0x035f0340},
7112 -       {0x0000b0e8, 0x037f0360},
7113 -       {0x0000b0ec, 0x04400441},
7114 -       {0x0000b0f0, 0x0460045f},
7115 -       {0x0000b0f4, 0x0541047f},
7116 -       {0x0000b0f8, 0x055f0540},
7117 -       {0x0000b0fc, 0x057f0560},
7118 -       {0x0000b100, 0x06400641},
7119 -       {0x0000b104, 0x0660065f},
7120 -       {0x0000b108, 0x067e067f},
7121 -       {0x0000b10c, 0x07410742},
7122 -       {0x0000b110, 0x075f0740},
7123 -       {0x0000b114, 0x077f0760},
7124 -       {0x0000b118, 0x07800781},
7125 -       {0x0000b11c, 0x07a0079f},
7126 -       {0x0000b120, 0x07c107bf},
7127 -       {0x0000b124, 0x000007c0},
7128 -       {0x0000b128, 0x00000000},
7129 -       {0x0000b12c, 0x00000000},
7130 -       {0x0000b130, 0x00000000},
7131 -       {0x0000b134, 0x00000000},
7132 -       {0x0000b138, 0x00000000},
7133 -       {0x0000b13c, 0x00000000},
7134 -       {0x0000b140, 0x003f0020},
7135 -       {0x0000b144, 0x00400041},
7136 -       {0x0000b148, 0x0140005f},
7137 -       {0x0000b14c, 0x0160015f},
7138 -       {0x0000b150, 0x017e017f},
7139 -       {0x0000b154, 0x02410242},
7140 -       {0x0000b158, 0x025f0240},
7141 -       {0x0000b15c, 0x027f0260},
7142 -       {0x0000b160, 0x0341027e},
7143 -       {0x0000b164, 0x035f0340},
7144 -       {0x0000b168, 0x037f0360},
7145 -       {0x0000b16c, 0x04400441},
7146 -       {0x0000b170, 0x0460045f},
7147 -       {0x0000b174, 0x0541047f},
7148 -       {0x0000b178, 0x055f0540},
7149 -       {0x0000b17c, 0x057f0560},
7150 -       {0x0000b180, 0x06400641},
7151 -       {0x0000b184, 0x0660065f},
7152 -       {0x0000b188, 0x067e067f},
7153 -       {0x0000b18c, 0x07410742},
7154 -       {0x0000b190, 0x075f0740},
7155 -       {0x0000b194, 0x077f0760},
7156 -       {0x0000b198, 0x07800781},
7157 -       {0x0000b19c, 0x07a0079f},
7158 -       {0x0000b1a0, 0x07c107bf},
7159 -       {0x0000b1a4, 0x000007c0},
7160 -       {0x0000b1a8, 0x00000000},
7161 -       {0x0000b1ac, 0x00000000},
7162 -       {0x0000b1b0, 0x00000000},
7163 -       {0x0000b1b4, 0x00000000},
7164 -       {0x0000b1b8, 0x00000000},
7165 -       {0x0000b1bc, 0x00000000},
7166 -       {0x0000b1c0, 0x00000000},
7167 -       {0x0000b1c4, 0x00000000},
7168 -       {0x0000b1c8, 0x00000000},
7169 -       {0x0000b1cc, 0x00000000},
7170 -       {0x0000b1d0, 0x00000000},
7171 -       {0x0000b1d4, 0x00000000},
7172 -       {0x0000b1d8, 0x00000000},
7173 -       {0x0000b1dc, 0x00000000},
7174 -       {0x0000b1e0, 0x00000000},
7175 -       {0x0000b1e4, 0x00000000},
7176 -       {0x0000b1e8, 0x00000000},
7177 -       {0x0000b1ec, 0x00000000},
7178 -       {0x0000b1f0, 0x00000396},
7179 -       {0x0000b1f4, 0x00000396},
7180 -       {0x0000b1f8, 0x00000396},
7181 -       {0x0000b1fc, 0x00000196},
7182 -};
7183 -
7184 -static const u32 ar9462_2p1_common_mixed_rx_gain[][2] = {
7185 -       /* Addr      allmodes  */
7186 -       {0x0000a000, 0x00010000},
7187 -       {0x0000a004, 0x00030002},
7188 -       {0x0000a008, 0x00050004},
7189 -       {0x0000a00c, 0x00810080},
7190 -       {0x0000a010, 0x00830082},
7191 -       {0x0000a014, 0x01810180},
7192 -       {0x0000a018, 0x01830182},
7193 -       {0x0000a01c, 0x01850184},
7194 -       {0x0000a020, 0x01890188},
7195 -       {0x0000a024, 0x018b018a},
7196 -       {0x0000a028, 0x018d018c},
7197 -       {0x0000a02c, 0x03820190},
7198 -       {0x0000a030, 0x03840383},
7199 -       {0x0000a034, 0x03880385},
7200 -       {0x0000a038, 0x038a0389},
7201 -       {0x0000a03c, 0x038c038b},
7202 -       {0x0000a040, 0x0390038d},
7203 -       {0x0000a044, 0x03920391},
7204 -       {0x0000a048, 0x03940393},
7205 -       {0x0000a04c, 0x03960395},
7206 -       {0x0000a050, 0x00000000},
7207 -       {0x0000a054, 0x00000000},
7208 -       {0x0000a058, 0x00000000},
7209 -       {0x0000a05c, 0x00000000},
7210 -       {0x0000a060, 0x00000000},
7211 -       {0x0000a064, 0x00000000},
7212 -       {0x0000a068, 0x00000000},
7213 -       {0x0000a06c, 0x00000000},
7214 -       {0x0000a070, 0x00000000},
7215 -       {0x0000a074, 0x00000000},
7216 -       {0x0000a078, 0x00000000},
7217 -       {0x0000a07c, 0x00000000},
7218 -       {0x0000a080, 0x29292929},
7219 -       {0x0000a084, 0x29292929},
7220 -       {0x0000a088, 0x29292929},
7221 -       {0x0000a08c, 0x29292929},
7222 -       {0x0000a090, 0x22292929},
7223 -       {0x0000a094, 0x1d1d2222},
7224 -       {0x0000a098, 0x0c111117},
7225 -       {0x0000a09c, 0x00030303},
7226 -       {0x0000a0a0, 0x00000000},
7227 -       {0x0000a0a4, 0x00000000},
7228 -       {0x0000a0a8, 0x00000000},
7229 -       {0x0000a0ac, 0x00000000},
7230 -       {0x0000a0b0, 0x00000000},
7231 -       {0x0000a0b4, 0x00000000},
7232 -       {0x0000a0b8, 0x00000000},
7233 -       {0x0000a0bc, 0x00000000},
7234 -       {0x0000a0c0, 0x001f0000},
7235 -       {0x0000a0c4, 0x01000101},
7236 -       {0x0000a0c8, 0x011e011f},
7237 -       {0x0000a0cc, 0x011c011d},
7238 -       {0x0000a0d0, 0x02030204},
7239 -       {0x0000a0d4, 0x02010202},
7240 -       {0x0000a0d8, 0x021f0200},
7241 -       {0x0000a0dc, 0x0302021e},
7242 -       {0x0000a0e0, 0x03000301},
7243 -       {0x0000a0e4, 0x031e031f},
7244 -       {0x0000a0e8, 0x0402031d},
7245 -       {0x0000a0ec, 0x04000401},
7246 -       {0x0000a0f0, 0x041e041f},
7247 -       {0x0000a0f4, 0x0502041d},
7248 -       {0x0000a0f8, 0x05000501},
7249 -       {0x0000a0fc, 0x051e051f},
7250 -       {0x0000a100, 0x06010602},
7251 -       {0x0000a104, 0x061f0600},
7252 -       {0x0000a108, 0x061d061e},
7253 -       {0x0000a10c, 0x07020703},
7254 -       {0x0000a110, 0x07000701},
7255 -       {0x0000a114, 0x00000000},
7256 -       {0x0000a118, 0x00000000},
7257 -       {0x0000a11c, 0x00000000},
7258 -       {0x0000a120, 0x00000000},
7259 -       {0x0000a124, 0x00000000},
7260 -       {0x0000a128, 0x00000000},
7261 -       {0x0000a12c, 0x00000000},
7262 -       {0x0000a130, 0x00000000},
7263 -       {0x0000a134, 0x00000000},
7264 -       {0x0000a138, 0x00000000},
7265 -       {0x0000a13c, 0x00000000},
7266 -       {0x0000a140, 0x001f0000},
7267 -       {0x0000a144, 0x01000101},
7268 -       {0x0000a148, 0x011e011f},
7269 -       {0x0000a14c, 0x011c011d},
7270 -       {0x0000a150, 0x02030204},
7271 -       {0x0000a154, 0x02010202},
7272 -       {0x0000a158, 0x021f0200},
7273 -       {0x0000a15c, 0x0302021e},
7274 -       {0x0000a160, 0x03000301},
7275 -       {0x0000a164, 0x031e031f},
7276 -       {0x0000a168, 0x0402031d},
7277 -       {0x0000a16c, 0x04000401},
7278 -       {0x0000a170, 0x041e041f},
7279 -       {0x0000a174, 0x0502041d},
7280 -       {0x0000a178, 0x05000501},
7281 -       {0x0000a17c, 0x051e051f},
7282 -       {0x0000a180, 0x06010602},
7283 -       {0x0000a184, 0x061f0600},
7284 -       {0x0000a188, 0x061d061e},
7285 -       {0x0000a18c, 0x07020703},
7286 -       {0x0000a190, 0x07000701},
7287 -       {0x0000a194, 0x00000000},
7288 -       {0x0000a198, 0x00000000},
7289 -       {0x0000a19c, 0x00000000},
7290 -       {0x0000a1a0, 0x00000000},
7291 -       {0x0000a1a4, 0x00000000},
7292 -       {0x0000a1a8, 0x00000000},
7293 -       {0x0000a1ac, 0x00000000},
7294 -       {0x0000a1b0, 0x00000000},
7295 -       {0x0000a1b4, 0x00000000},
7296 -       {0x0000a1b8, 0x00000000},
7297 -       {0x0000a1bc, 0x00000000},
7298 -       {0x0000a1c0, 0x00000000},
7299 -       {0x0000a1c4, 0x00000000},
7300 -       {0x0000a1c8, 0x00000000},
7301 -       {0x0000a1cc, 0x00000000},
7302 -       {0x0000a1d0, 0x00000000},
7303 -       {0x0000a1d4, 0x00000000},
7304 -       {0x0000a1d8, 0x00000000},
7305 -       {0x0000a1dc, 0x00000000},
7306 -       {0x0000a1e0, 0x00000000},
7307 -       {0x0000a1e4, 0x00000000},
7308 -       {0x0000a1e8, 0x00000000},
7309 -       {0x0000a1ec, 0x00000000},
7310 -       {0x0000a1f0, 0x00000396},
7311 -       {0x0000a1f4, 0x00000396},
7312 -       {0x0000a1f8, 0x00000396},
7313 -       {0x0000a1fc, 0x00000196},
7314 -       {0x0000b000, 0x00010000},
7315 -       {0x0000b004, 0x00030002},
7316 -       {0x0000b008, 0x00050004},
7317 -       {0x0000b00c, 0x00810080},
7318 -       {0x0000b010, 0x00830082},
7319 -       {0x0000b014, 0x01810180},
7320 -       {0x0000b018, 0x01830182},
7321 -       {0x0000b01c, 0x01850184},
7322 -       {0x0000b020, 0x02810280},
7323 -       {0x0000b024, 0x02830282},
7324 -       {0x0000b028, 0x02850284},
7325 -       {0x0000b02c, 0x02890288},
7326 -       {0x0000b030, 0x028b028a},
7327 -       {0x0000b034, 0x0388028c},
7328 -       {0x0000b038, 0x038a0389},
7329 -       {0x0000b03c, 0x038c038b},
7330 -       {0x0000b040, 0x0390038d},
7331 -       {0x0000b044, 0x03920391},
7332 -       {0x0000b048, 0x03940393},
7333 -       {0x0000b04c, 0x03960395},
7334 -       {0x0000b050, 0x00000000},
7335 -       {0x0000b054, 0x00000000},
7336 -       {0x0000b058, 0x00000000},
7337 -       {0x0000b05c, 0x00000000},
7338 -       {0x0000b060, 0x00000000},
7339 -       {0x0000b064, 0x00000000},
7340 -       {0x0000b068, 0x00000000},
7341 -       {0x0000b06c, 0x00000000},
7342 -       {0x0000b070, 0x00000000},
7343 -       {0x0000b074, 0x00000000},
7344 -       {0x0000b078, 0x00000000},
7345 -       {0x0000b07c, 0x00000000},
7346 -       {0x0000b080, 0x2a2d2f32},
7347 -       {0x0000b084, 0x21232328},
7348 -       {0x0000b088, 0x19191c1e},
7349 -       {0x0000b08c, 0x12141417},
7350 -       {0x0000b090, 0x07070e0e},
7351 -       {0x0000b094, 0x03030305},
7352 -       {0x0000b098, 0x00000003},
7353 -       {0x0000b09c, 0x00000000},
7354 -       {0x0000b0a0, 0x00000000},
7355 -       {0x0000b0a4, 0x00000000},
7356 -       {0x0000b0a8, 0x00000000},
7357 -       {0x0000b0ac, 0x00000000},
7358 -       {0x0000b0b0, 0x00000000},
7359 -       {0x0000b0b4, 0x00000000},
7360 -       {0x0000b0b8, 0x00000000},
7361 -       {0x0000b0bc, 0x00000000},
7362 -       {0x0000b0c0, 0x003f0020},
7363 -       {0x0000b0c4, 0x00400041},
7364 -       {0x0000b0c8, 0x0140005f},
7365 -       {0x0000b0cc, 0x0160015f},
7366 -       {0x0000b0d0, 0x017e017f},
7367 -       {0x0000b0d4, 0x02410242},
7368 -       {0x0000b0d8, 0x025f0240},
7369 -       {0x0000b0dc, 0x027f0260},
7370 -       {0x0000b0e0, 0x0341027e},
7371 -       {0x0000b0e4, 0x035f0340},
7372 -       {0x0000b0e8, 0x037f0360},
7373 -       {0x0000b0ec, 0x04400441},
7374 -       {0x0000b0f0, 0x0460045f},
7375 -       {0x0000b0f4, 0x0541047f},
7376 -       {0x0000b0f8, 0x055f0540},
7377 -       {0x0000b0fc, 0x057f0560},
7378 -       {0x0000b100, 0x06400641},
7379 -       {0x0000b104, 0x0660065f},
7380 -       {0x0000b108, 0x067e067f},
7381 -       {0x0000b10c, 0x07410742},
7382 -       {0x0000b110, 0x075f0740},
7383 -       {0x0000b114, 0x077f0760},
7384 -       {0x0000b118, 0x07800781},
7385 -       {0x0000b11c, 0x07a0079f},
7386 -       {0x0000b120, 0x07c107bf},
7387 -       {0x0000b124, 0x000007c0},
7388 -       {0x0000b128, 0x00000000},
7389 -       {0x0000b12c, 0x00000000},
7390 -       {0x0000b130, 0x00000000},
7391 -       {0x0000b134, 0x00000000},
7392 -       {0x0000b138, 0x00000000},
7393 -       {0x0000b13c, 0x00000000},
7394 -       {0x0000b140, 0x003f0020},
7395 -       {0x0000b144, 0x00400041},
7396 -       {0x0000b148, 0x0140005f},
7397 -       {0x0000b14c, 0x0160015f},
7398 -       {0x0000b150, 0x017e017f},
7399 -       {0x0000b154, 0x02410242},
7400 -       {0x0000b158, 0x025f0240},
7401 -       {0x0000b15c, 0x027f0260},
7402 -       {0x0000b160, 0x0341027e},
7403 -       {0x0000b164, 0x035f0340},
7404 -       {0x0000b168, 0x037f0360},
7405 -       {0x0000b16c, 0x04400441},
7406 -       {0x0000b170, 0x0460045f},
7407 -       {0x0000b174, 0x0541047f},
7408 -       {0x0000b178, 0x055f0540},
7409 -       {0x0000b17c, 0x057f0560},
7410 -       {0x0000b180, 0x06400641},
7411 -       {0x0000b184, 0x0660065f},
7412 -       {0x0000b188, 0x067e067f},
7413 -       {0x0000b18c, 0x07410742},
7414 -       {0x0000b190, 0x075f0740},
7415 -       {0x0000b194, 0x077f0760},
7416 -       {0x0000b198, 0x07800781},
7417 -       {0x0000b19c, 0x07a0079f},
7418 -       {0x0000b1a0, 0x07c107bf},
7419 -       {0x0000b1a4, 0x000007c0},
7420 -       {0x0000b1a8, 0x00000000},
7421 -       {0x0000b1ac, 0x00000000},
7422 -       {0x0000b1b0, 0x00000000},
7423 -       {0x0000b1b4, 0x00000000},
7424 -       {0x0000b1b8, 0x00000000},
7425 -       {0x0000b1bc, 0x00000000},
7426 -       {0x0000b1c0, 0x00000000},
7427 -       {0x0000b1c4, 0x00000000},
7428 -       {0x0000b1c8, 0x00000000},
7429 -       {0x0000b1cc, 0x00000000},
7430 -       {0x0000b1d0, 0x00000000},
7431 -       {0x0000b1d4, 0x00000000},
7432 -       {0x0000b1d8, 0x00000000},
7433 -       {0x0000b1dc, 0x00000000},
7434 -       {0x0000b1e0, 0x00000000},
7435 -       {0x0000b1e4, 0x00000000},
7436 -       {0x0000b1e8, 0x00000000},
7437 -       {0x0000b1ec, 0x00000000},
7438 -       {0x0000b1f0, 0x00000396},
7439 -       {0x0000b1f4, 0x00000396},
7440 -       {0x0000b1f8, 0x00000396},
7441 -       {0x0000b1fc, 0x00000196},
7442 -};
7443 -
7444 -static const u32 ar9462_2p1_baseband_core_mix_rxgain[][2] = {
7445 -       /* Addr      allmodes  */
7446 -       {0x00009fd0, 0x0a2d6b93},
7447 -};
7448 -
7449 -static const u32 ar9462_2p1_baseband_postamble_mix_rxgain[][5] = {
7450 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
7451 -       {0x00009820, 0x206a022e, 0x206a022e, 0x206a01ae, 0x206a01ae},
7452 -       {0x00009824, 0x63c640de, 0x5ac640d0, 0x63c640da, 0x63c640da},
7453 -       {0x00009828, 0x0796be89, 0x0696b081, 0x0916be81, 0x0916be81},
7454 -       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000d8, 0x6c4000d8},
7455 -       {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec86d2e, 0x7ec86d2e},
7456 -       {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32395c5e},
7457 -};
7458 -
7459 -static const u32 ar9462_2p1_baseband_postamble_5g_xlna[][5] = {
7460 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
7461 -       {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
7462 -};
7463 -
7464 -static const u32 ar9462_2p1_common_wo_xlna_rx_gain[][2] = {
7465 -       /* Addr      allmodes  */
7466 -       {0x0000a000, 0x00010000},
7467 -       {0x0000a004, 0x00030002},
7468 -       {0x0000a008, 0x00050004},
7469 -       {0x0000a00c, 0x00810080},
7470 -       {0x0000a010, 0x00830082},
7471 -       {0x0000a014, 0x01810180},
7472 -       {0x0000a018, 0x01830182},
7473 -       {0x0000a01c, 0x01850184},
7474 -       {0x0000a020, 0x01890188},
7475 -       {0x0000a024, 0x018b018a},
7476 -       {0x0000a028, 0x018d018c},
7477 -       {0x0000a02c, 0x03820190},
7478 -       {0x0000a030, 0x03840383},
7479 -       {0x0000a034, 0x03880385},
7480 -       {0x0000a038, 0x038a0389},
7481 -       {0x0000a03c, 0x038c038b},
7482 -       {0x0000a040, 0x0390038d},
7483 -       {0x0000a044, 0x03920391},
7484 -       {0x0000a048, 0x03940393},
7485 -       {0x0000a04c, 0x03960395},
7486 -       {0x0000a050, 0x00000000},
7487 -       {0x0000a054, 0x00000000},
7488 -       {0x0000a058, 0x00000000},
7489 -       {0x0000a05c, 0x00000000},
7490 -       {0x0000a060, 0x00000000},
7491 -       {0x0000a064, 0x00000000},
7492 -       {0x0000a068, 0x00000000},
7493 -       {0x0000a06c, 0x00000000},
7494 -       {0x0000a070, 0x00000000},
7495 -       {0x0000a074, 0x00000000},
7496 -       {0x0000a078, 0x00000000},
7497 -       {0x0000a07c, 0x00000000},
7498 -       {0x0000a080, 0x29292929},
7499 -       {0x0000a084, 0x29292929},
7500 -       {0x0000a088, 0x29292929},
7501 -       {0x0000a08c, 0x29292929},
7502 -       {0x0000a090, 0x22292929},
7503 -       {0x0000a094, 0x1d1d2222},
7504 -       {0x0000a098, 0x0c111117},
7505 -       {0x0000a09c, 0x00030303},
7506 -       {0x0000a0a0, 0x00000000},
7507 -       {0x0000a0a4, 0x00000000},
7508 -       {0x0000a0a8, 0x00000000},
7509 -       {0x0000a0ac, 0x00000000},
7510 -       {0x0000a0b0, 0x00000000},
7511 -       {0x0000a0b4, 0x00000000},
7512 -       {0x0000a0b8, 0x00000000},
7513 -       {0x0000a0bc, 0x00000000},
7514 -       {0x0000a0c0, 0x001f0000},
7515 -       {0x0000a0c4, 0x01000101},
7516 -       {0x0000a0c8, 0x011e011f},
7517 -       {0x0000a0cc, 0x011c011d},
7518 -       {0x0000a0d0, 0x02030204},
7519 -       {0x0000a0d4, 0x02010202},
7520 -       {0x0000a0d8, 0x021f0200},
7521 -       {0x0000a0dc, 0x0302021e},
7522 -       {0x0000a0e0, 0x03000301},
7523 -       {0x0000a0e4, 0x031e031f},
7524 -       {0x0000a0e8, 0x0402031d},
7525 -       {0x0000a0ec, 0x04000401},
7526 -       {0x0000a0f0, 0x041e041f},
7527 -       {0x0000a0f4, 0x0502041d},
7528 -       {0x0000a0f8, 0x05000501},
7529 -       {0x0000a0fc, 0x051e051f},
7530 -       {0x0000a100, 0x06010602},
7531 -       {0x0000a104, 0x061f0600},
7532 -       {0x0000a108, 0x061d061e},
7533 -       {0x0000a10c, 0x07020703},
7534 -       {0x0000a110, 0x07000701},
7535 -       {0x0000a114, 0x00000000},
7536 -       {0x0000a118, 0x00000000},
7537 -       {0x0000a11c, 0x00000000},
7538 -       {0x0000a120, 0x00000000},
7539 -       {0x0000a124, 0x00000000},
7540 -       {0x0000a128, 0x00000000},
7541 -       {0x0000a12c, 0x00000000},
7542 -       {0x0000a130, 0x00000000},
7543 -       {0x0000a134, 0x00000000},
7544 -       {0x0000a138, 0x00000000},
7545 -       {0x0000a13c, 0x00000000},
7546 -       {0x0000a140, 0x001f0000},
7547 -       {0x0000a144, 0x01000101},
7548 -       {0x0000a148, 0x011e011f},
7549 -       {0x0000a14c, 0x011c011d},
7550 -       {0x0000a150, 0x02030204},
7551 -       {0x0000a154, 0x02010202},
7552 -       {0x0000a158, 0x021f0200},
7553 -       {0x0000a15c, 0x0302021e},
7554 -       {0x0000a160, 0x03000301},
7555 -       {0x0000a164, 0x031e031f},
7556 -       {0x0000a168, 0x0402031d},
7557 -       {0x0000a16c, 0x04000401},
7558 -       {0x0000a170, 0x041e041f},
7559 -       {0x0000a174, 0x0502041d},
7560 -       {0x0000a178, 0x05000501},
7561 -       {0x0000a17c, 0x051e051f},
7562 -       {0x0000a180, 0x06010602},
7563 -       {0x0000a184, 0x061f0600},
7564 -       {0x0000a188, 0x061d061e},
7565 -       {0x0000a18c, 0x07020703},
7566 -       {0x0000a190, 0x07000701},
7567 -       {0x0000a194, 0x00000000},
7568 -       {0x0000a198, 0x00000000},
7569 -       {0x0000a19c, 0x00000000},
7570 -       {0x0000a1a0, 0x00000000},
7571 -       {0x0000a1a4, 0x00000000},
7572 -       {0x0000a1a8, 0x00000000},
7573 -       {0x0000a1ac, 0x00000000},
7574 -       {0x0000a1b0, 0x00000000},
7575 -       {0x0000a1b4, 0x00000000},
7576 -       {0x0000a1b8, 0x00000000},
7577 -       {0x0000a1bc, 0x00000000},
7578 -       {0x0000a1c0, 0x00000000},
7579 -       {0x0000a1c4, 0x00000000},
7580 -       {0x0000a1c8, 0x00000000},
7581 -       {0x0000a1cc, 0x00000000},
7582 -       {0x0000a1d0, 0x00000000},
7583 -       {0x0000a1d4, 0x00000000},
7584 -       {0x0000a1d8, 0x00000000},
7585 -       {0x0000a1dc, 0x00000000},
7586 -       {0x0000a1e0, 0x00000000},
7587 -       {0x0000a1e4, 0x00000000},
7588 -       {0x0000a1e8, 0x00000000},
7589 -       {0x0000a1ec, 0x00000000},
7590 -       {0x0000a1f0, 0x00000396},
7591 -       {0x0000a1f4, 0x00000396},
7592 -       {0x0000a1f8, 0x00000396},
7593 -       {0x0000a1fc, 0x00000196},
7594 -       {0x0000b000, 0x00010000},
7595 -       {0x0000b004, 0x00030002},
7596 -       {0x0000b008, 0x00050004},
7597 -       {0x0000b00c, 0x00810080},
7598 -       {0x0000b010, 0x00830082},
7599 -       {0x0000b014, 0x01810180},
7600 -       {0x0000b018, 0x01830182},
7601 -       {0x0000b01c, 0x01850184},
7602 -       {0x0000b020, 0x02810280},
7603 -       {0x0000b024, 0x02830282},
7604 -       {0x0000b028, 0x02850284},
7605 -       {0x0000b02c, 0x02890288},
7606 -       {0x0000b030, 0x028b028a},
7607 -       {0x0000b034, 0x0388028c},
7608 -       {0x0000b038, 0x038a0389},
7609 -       {0x0000b03c, 0x038c038b},
7610 -       {0x0000b040, 0x0390038d},
7611 -       {0x0000b044, 0x03920391},
7612 -       {0x0000b048, 0x03940393},
7613 -       {0x0000b04c, 0x03960395},
7614 -       {0x0000b050, 0x00000000},
7615 -       {0x0000b054, 0x00000000},
7616 -       {0x0000b058, 0x00000000},
7617 -       {0x0000b05c, 0x00000000},
7618 -       {0x0000b060, 0x00000000},
7619 -       {0x0000b064, 0x00000000},
7620 -       {0x0000b068, 0x00000000},
7621 -       {0x0000b06c, 0x00000000},
7622 -       {0x0000b070, 0x00000000},
7623 -       {0x0000b074, 0x00000000},
7624 -       {0x0000b078, 0x00000000},
7625 -       {0x0000b07c, 0x00000000},
7626 -       {0x0000b080, 0x32323232},
7627 -       {0x0000b084, 0x2f2f3232},
7628 -       {0x0000b088, 0x23282a2d},
7629 -       {0x0000b08c, 0x1c1e2123},
7630 -       {0x0000b090, 0x14171919},
7631 -       {0x0000b094, 0x0e0e1214},
7632 -       {0x0000b098, 0x03050707},
7633 -       {0x0000b09c, 0x00030303},
7634 -       {0x0000b0a0, 0x00000000},
7635 -       {0x0000b0a4, 0x00000000},
7636 -       {0x0000b0a8, 0x00000000},
7637 -       {0x0000b0ac, 0x00000000},
7638 -       {0x0000b0b0, 0x00000000},
7639 -       {0x0000b0b4, 0x00000000},
7640 -       {0x0000b0b8, 0x00000000},
7641 -       {0x0000b0bc, 0x00000000},
7642 -       {0x0000b0c0, 0x003f0020},
7643 -       {0x0000b0c4, 0x00400041},
7644 -       {0x0000b0c8, 0x0140005f},
7645 -       {0x0000b0cc, 0x0160015f},
7646 -       {0x0000b0d0, 0x017e017f},
7647 -       {0x0000b0d4, 0x02410242},
7648 -       {0x0000b0d8, 0x025f0240},
7649 -       {0x0000b0dc, 0x027f0260},
7650 -       {0x0000b0e0, 0x0341027e},
7651 -       {0x0000b0e4, 0x035f0340},
7652 -       {0x0000b0e8, 0x037f0360},
7653 -       {0x0000b0ec, 0x04400441},
7654 -       {0x0000b0f0, 0x0460045f},
7655 -       {0x0000b0f4, 0x0541047f},
7656 -       {0x0000b0f8, 0x055f0540},
7657 -       {0x0000b0fc, 0x057f0560},
7658 -       {0x0000b100, 0x06400641},
7659 -       {0x0000b104, 0x0660065f},
7660 -       {0x0000b108, 0x067e067f},
7661 -       {0x0000b10c, 0x07410742},
7662 -       {0x0000b110, 0x075f0740},
7663 -       {0x0000b114, 0x077f0760},
7664 -       {0x0000b118, 0x07800781},
7665 -       {0x0000b11c, 0x07a0079f},
7666 -       {0x0000b120, 0x07c107bf},
7667 -       {0x0000b124, 0x000007c0},
7668 -       {0x0000b128, 0x00000000},
7669 -       {0x0000b12c, 0x00000000},
7670 -       {0x0000b130, 0x00000000},
7671 -       {0x0000b134, 0x00000000},
7672 -       {0x0000b138, 0x00000000},
7673 -       {0x0000b13c, 0x00000000},
7674 -       {0x0000b140, 0x003f0020},
7675 -       {0x0000b144, 0x00400041},
7676 -       {0x0000b148, 0x0140005f},
7677 -       {0x0000b14c, 0x0160015f},
7678 -       {0x0000b150, 0x017e017f},
7679 -       {0x0000b154, 0x02410242},
7680 -       {0x0000b158, 0x025f0240},
7681 -       {0x0000b15c, 0x027f0260},
7682 -       {0x0000b160, 0x0341027e},
7683 -       {0x0000b164, 0x035f0340},
7684 -       {0x0000b168, 0x037f0360},
7685 -       {0x0000b16c, 0x04400441},
7686 -       {0x0000b170, 0x0460045f},
7687 -       {0x0000b174, 0x0541047f},
7688 -       {0x0000b178, 0x055f0540},
7689 -       {0x0000b17c, 0x057f0560},
7690 -       {0x0000b180, 0x06400641},
7691 -       {0x0000b184, 0x0660065f},
7692 -       {0x0000b188, 0x067e067f},
7693 -       {0x0000b18c, 0x07410742},
7694 -       {0x0000b190, 0x075f0740},
7695 -       {0x0000b194, 0x077f0760},
7696 -       {0x0000b198, 0x07800781},
7697 -       {0x0000b19c, 0x07a0079f},
7698 -       {0x0000b1a0, 0x07c107bf},
7699 -       {0x0000b1a4, 0x000007c0},
7700 -       {0x0000b1a8, 0x00000000},
7701 -       {0x0000b1ac, 0x00000000},
7702 -       {0x0000b1b0, 0x00000000},
7703 -       {0x0000b1b4, 0x00000000},
7704 -       {0x0000b1b8, 0x00000000},
7705 -       {0x0000b1bc, 0x00000000},
7706 -       {0x0000b1c0, 0x00000000},
7707 -       {0x0000b1c4, 0x00000000},
7708 -       {0x0000b1c8, 0x00000000},
7709 -       {0x0000b1cc, 0x00000000},
7710 -       {0x0000b1d0, 0x00000000},
7711 -       {0x0000b1d4, 0x00000000},
7712 -       {0x0000b1d8, 0x00000000},
7713 -       {0x0000b1dc, 0x00000000},
7714 -       {0x0000b1e0, 0x00000000},
7715 -       {0x0000b1e4, 0x00000000},
7716 -       {0x0000b1e8, 0x00000000},
7717 -       {0x0000b1ec, 0x00000000},
7718 -       {0x0000b1f0, 0x00000396},
7719 -       {0x0000b1f4, 0x00000396},
7720 -       {0x0000b1f8, 0x00000396},
7721 -       {0x0000b1fc, 0x00000196},
7722 -};
7723 -
7724 -static const u32 ar9462_2p1_common_5g_xlna_only_rx_gain[][2] = {
7725 -       /* Addr      allmodes  */
7726 -       {0x0000a000, 0x00010000},
7727 -       {0x0000a004, 0x00030002},
7728 -       {0x0000a008, 0x00050004},
7729 -       {0x0000a00c, 0x00810080},
7730 -       {0x0000a010, 0x00830082},
7731 -       {0x0000a014, 0x01810180},
7732 -       {0x0000a018, 0x01830182},
7733 -       {0x0000a01c, 0x01850184},
7734 -       {0x0000a020, 0x01890188},
7735 -       {0x0000a024, 0x018b018a},
7736 -       {0x0000a028, 0x018d018c},
7737 -       {0x0000a02c, 0x03820190},
7738 -       {0x0000a030, 0x03840383},
7739 -       {0x0000a034, 0x03880385},
7740 -       {0x0000a038, 0x038a0389},
7741 -       {0x0000a03c, 0x038c038b},
7742 -       {0x0000a040, 0x0390038d},
7743 -       {0x0000a044, 0x03920391},
7744 -       {0x0000a048, 0x03940393},
7745 -       {0x0000a04c, 0x03960395},
7746 -       {0x0000a050, 0x00000000},
7747 -       {0x0000a054, 0x00000000},
7748 -       {0x0000a058, 0x00000000},
7749 -       {0x0000a05c, 0x00000000},
7750 -       {0x0000a060, 0x00000000},
7751 -       {0x0000a064, 0x00000000},
7752 -       {0x0000a068, 0x00000000},
7753 -       {0x0000a06c, 0x00000000},
7754 -       {0x0000a070, 0x00000000},
7755 -       {0x0000a074, 0x00000000},
7756 -       {0x0000a078, 0x00000000},
7757 -       {0x0000a07c, 0x00000000},
7758 -       {0x0000a080, 0x29292929},
7759 -       {0x0000a084, 0x29292929},
7760 -       {0x0000a088, 0x29292929},
7761 -       {0x0000a08c, 0x29292929},
7762 -       {0x0000a090, 0x22292929},
7763 -       {0x0000a094, 0x1d1d2222},
7764 -       {0x0000a098, 0x0c111117},
7765 -       {0x0000a09c, 0x00030303},
7766 -       {0x0000a0a0, 0x00000000},
7767 -       {0x0000a0a4, 0x00000000},
7768 -       {0x0000a0a8, 0x00000000},
7769 -       {0x0000a0ac, 0x00000000},
7770 -       {0x0000a0b0, 0x00000000},
7771 -       {0x0000a0b4, 0x00000000},
7772 -       {0x0000a0b8, 0x00000000},
7773 -       {0x0000a0bc, 0x00000000},
7774 -       {0x0000a0c0, 0x001f0000},
7775 -       {0x0000a0c4, 0x01000101},
7776 -       {0x0000a0c8, 0x011e011f},
7777 -       {0x0000a0cc, 0x011c011d},
7778 -       {0x0000a0d0, 0x02030204},
7779 -       {0x0000a0d4, 0x02010202},
7780 -       {0x0000a0d8, 0x021f0200},
7781 -       {0x0000a0dc, 0x0302021e},
7782 -       {0x0000a0e0, 0x03000301},
7783 -       {0x0000a0e4, 0x031e031f},
7784 -       {0x0000a0e8, 0x0402031d},
7785 -       {0x0000a0ec, 0x04000401},
7786 -       {0x0000a0f0, 0x041e041f},
7787 -       {0x0000a0f4, 0x0502041d},
7788 -       {0x0000a0f8, 0x05000501},
7789 -       {0x0000a0fc, 0x051e051f},
7790 -       {0x0000a100, 0x06010602},
7791 -       {0x0000a104, 0x061f0600},
7792 -       {0x0000a108, 0x061d061e},
7793 -       {0x0000a10c, 0x07020703},
7794 -       {0x0000a110, 0x07000701},
7795 -       {0x0000a114, 0x00000000},
7796 -       {0x0000a118, 0x00000000},
7797 -       {0x0000a11c, 0x00000000},
7798 -       {0x0000a120, 0x00000000},
7799 -       {0x0000a124, 0x00000000},
7800 -       {0x0000a128, 0x00000000},
7801 -       {0x0000a12c, 0x00000000},
7802 -       {0x0000a130, 0x00000000},
7803 -       {0x0000a134, 0x00000000},
7804 -       {0x0000a138, 0x00000000},
7805 -       {0x0000a13c, 0x00000000},
7806 -       {0x0000a140, 0x001f0000},
7807 -       {0x0000a144, 0x01000101},
7808 -       {0x0000a148, 0x011e011f},
7809 -       {0x0000a14c, 0x011c011d},
7810 -       {0x0000a150, 0x02030204},
7811 -       {0x0000a154, 0x02010202},
7812 -       {0x0000a158, 0x021f0200},
7813 -       {0x0000a15c, 0x0302021e},
7814 -       {0x0000a160, 0x03000301},
7815 -       {0x0000a164, 0x031e031f},
7816 -       {0x0000a168, 0x0402031d},
7817 -       {0x0000a16c, 0x04000401},
7818 -       {0x0000a170, 0x041e041f},
7819 -       {0x0000a174, 0x0502041d},
7820 -       {0x0000a178, 0x05000501},
7821 -       {0x0000a17c, 0x051e051f},
7822 -       {0x0000a180, 0x06010602},
7823 -       {0x0000a184, 0x061f0600},
7824 -       {0x0000a188, 0x061d061e},
7825 -       {0x0000a18c, 0x07020703},
7826 -       {0x0000a190, 0x07000701},
7827 -       {0x0000a194, 0x00000000},
7828 -       {0x0000a198, 0x00000000},
7829 -       {0x0000a19c, 0x00000000},
7830 -       {0x0000a1a0, 0x00000000},
7831 -       {0x0000a1a4, 0x00000000},
7832 -       {0x0000a1a8, 0x00000000},
7833 -       {0x0000a1ac, 0x00000000},
7834 -       {0x0000a1b0, 0x00000000},
7835 -       {0x0000a1b4, 0x00000000},
7836 -       {0x0000a1b8, 0x00000000},
7837 -       {0x0000a1bc, 0x00000000},
7838 -       {0x0000a1c0, 0x00000000},
7839 -       {0x0000a1c4, 0x00000000},
7840 -       {0x0000a1c8, 0x00000000},
7841 -       {0x0000a1cc, 0x00000000},
7842 -       {0x0000a1d0, 0x00000000},
7843 -       {0x0000a1d4, 0x00000000},
7844 -       {0x0000a1d8, 0x00000000},
7845 -       {0x0000a1dc, 0x00000000},
7846 -       {0x0000a1e0, 0x00000000},
7847 -       {0x0000a1e4, 0x00000000},
7848 -       {0x0000a1e8, 0x00000000},
7849 -       {0x0000a1ec, 0x00000000},
7850 -       {0x0000a1f0, 0x00000396},
7851 -       {0x0000a1f4, 0x00000396},
7852 -       {0x0000a1f8, 0x00000396},
7853 -       {0x0000a1fc, 0x00000196},
7854 -       {0x0000b000, 0x00010000},
7855 -       {0x0000b004, 0x00030002},
7856 -       {0x0000b008, 0x00050004},
7857 -       {0x0000b00c, 0x00810080},
7858 -       {0x0000b010, 0x00830082},
7859 -       {0x0000b014, 0x01810180},
7860 -       {0x0000b018, 0x01830182},
7861 -       {0x0000b01c, 0x01850184},
7862 -       {0x0000b020, 0x02810280},
7863 -       {0x0000b024, 0x02830282},
7864 -       {0x0000b028, 0x02850284},
7865 -       {0x0000b02c, 0x02890288},
7866 -       {0x0000b030, 0x028b028a},
7867 -       {0x0000b034, 0x0388028c},
7868 -       {0x0000b038, 0x038a0389},
7869 -       {0x0000b03c, 0x038c038b},
7870 -       {0x0000b040, 0x0390038d},
7871 -       {0x0000b044, 0x03920391},
7872 -       {0x0000b048, 0x03940393},
7873 -       {0x0000b04c, 0x03960395},
7874 -       {0x0000b050, 0x00000000},
7875 -       {0x0000b054, 0x00000000},
7876 -       {0x0000b058, 0x00000000},
7877 -       {0x0000b05c, 0x00000000},
7878 -       {0x0000b060, 0x00000000},
7879 -       {0x0000b064, 0x00000000},
7880 -       {0x0000b068, 0x00000000},
7881 -       {0x0000b06c, 0x00000000},
7882 -       {0x0000b070, 0x00000000},
7883 -       {0x0000b074, 0x00000000},
7884 -       {0x0000b078, 0x00000000},
7885 -       {0x0000b07c, 0x00000000},
7886 -       {0x0000b080, 0x2a2d2f32},
7887 -       {0x0000b084, 0x21232328},
7888 -       {0x0000b088, 0x19191c1e},
7889 -       {0x0000b08c, 0x12141417},
7890 -       {0x0000b090, 0x07070e0e},
7891 -       {0x0000b094, 0x03030305},
7892 -       {0x0000b098, 0x00000003},
7893 -       {0x0000b09c, 0x00000000},
7894 -       {0x0000b0a0, 0x00000000},
7895 -       {0x0000b0a4, 0x00000000},
7896 -       {0x0000b0a8, 0x00000000},
7897 -       {0x0000b0ac, 0x00000000},
7898 -       {0x0000b0b0, 0x00000000},
7899 -       {0x0000b0b4, 0x00000000},
7900 -       {0x0000b0b8, 0x00000000},
7901 -       {0x0000b0bc, 0x00000000},
7902 -       {0x0000b0c0, 0x003f0020},
7903 -       {0x0000b0c4, 0x00400041},
7904 -       {0x0000b0c8, 0x0140005f},
7905 -       {0x0000b0cc, 0x0160015f},
7906 -       {0x0000b0d0, 0x017e017f},
7907 -       {0x0000b0d4, 0x02410242},
7908 -       {0x0000b0d8, 0x025f0240},
7909 -       {0x0000b0dc, 0x027f0260},
7910 -       {0x0000b0e0, 0x0341027e},
7911 -       {0x0000b0e4, 0x035f0340},
7912 -       {0x0000b0e8, 0x037f0360},
7913 -       {0x0000b0ec, 0x04400441},
7914 -       {0x0000b0f0, 0x0460045f},
7915 -       {0x0000b0f4, 0x0541047f},
7916 -       {0x0000b0f8, 0x055f0540},
7917 -       {0x0000b0fc, 0x057f0560},
7918 -       {0x0000b100, 0x06400641},
7919 -       {0x0000b104, 0x0660065f},
7920 -       {0x0000b108, 0x067e067f},
7921 -       {0x0000b10c, 0x07410742},
7922 -       {0x0000b110, 0x075f0740},
7923 -       {0x0000b114, 0x077f0760},
7924 -       {0x0000b118, 0x07800781},
7925 -       {0x0000b11c, 0x07a0079f},
7926 -       {0x0000b120, 0x07c107bf},
7927 -       {0x0000b124, 0x000007c0},
7928 -       {0x0000b128, 0x00000000},
7929 -       {0x0000b12c, 0x00000000},
7930 -       {0x0000b130, 0x00000000},
7931 -       {0x0000b134, 0x00000000},
7932 -       {0x0000b138, 0x00000000},
7933 -       {0x0000b13c, 0x00000000},
7934 -       {0x0000b140, 0x003f0020},
7935 -       {0x0000b144, 0x00400041},
7936 -       {0x0000b148, 0x0140005f},
7937 -       {0x0000b14c, 0x0160015f},
7938 -       {0x0000b150, 0x017e017f},
7939 -       {0x0000b154, 0x02410242},
7940 -       {0x0000b158, 0x025f0240},
7941 -       {0x0000b15c, 0x027f0260},
7942 -       {0x0000b160, 0x0341027e},
7943 -       {0x0000b164, 0x035f0340},
7944 -       {0x0000b168, 0x037f0360},
7945 -       {0x0000b16c, 0x04400441},
7946 -       {0x0000b170, 0x0460045f},
7947 -       {0x0000b174, 0x0541047f},
7948 -       {0x0000b178, 0x055f0540},
7949 -       {0x0000b17c, 0x057f0560},
7950 -       {0x0000b180, 0x06400641},
7951 -       {0x0000b184, 0x0660065f},
7952 -       {0x0000b188, 0x067e067f},
7953 -       {0x0000b18c, 0x07410742},
7954 -       {0x0000b190, 0x075f0740},
7955 -       {0x0000b194, 0x077f0760},
7956 -       {0x0000b198, 0x07800781},
7957 -       {0x0000b19c, 0x07a0079f},
7958 -       {0x0000b1a0, 0x07c107bf},
7959 -       {0x0000b1a4, 0x000007c0},
7960 -       {0x0000b1a8, 0x00000000},
7961 -       {0x0000b1ac, 0x00000000},
7962 -       {0x0000b1b0, 0x00000000},
7963 -       {0x0000b1b4, 0x00000000},
7964 -       {0x0000b1b8, 0x00000000},
7965 -       {0x0000b1bc, 0x00000000},
7966 -       {0x0000b1c0, 0x00000000},
7967 -       {0x0000b1c4, 0x00000000},
7968 -       {0x0000b1c8, 0x00000000},
7969 -       {0x0000b1cc, 0x00000000},
7970 -       {0x0000b1d0, 0x00000000},
7971 -       {0x0000b1d4, 0x00000000},
7972 -       {0x0000b1d8, 0x00000000},
7973 -       {0x0000b1dc, 0x00000000},
7974 -       {0x0000b1e0, 0x00000000},
7975 -       {0x0000b1e4, 0x00000000},
7976 -       {0x0000b1e8, 0x00000000},
7977 -       {0x0000b1ec, 0x00000000},
7978 -       {0x0000b1f0, 0x00000396},
7979 -       {0x0000b1f4, 0x00000396},
7980 -       {0x0000b1f8, 0x00000396},
7981 -       {0x0000b1fc, 0x00000196},
7982 -};
7983 -
7984 -static const u32 ar9462_2p1_modes_low_ob_db_tx_gain[][5] = {
7985 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
7986 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
7987 -       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
7988 -       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
7989 -       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
7990 -       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
7991 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
7992 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7993 -       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7994 -       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
7995 -       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
7996 -       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
7997 -       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
7998 -       {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
7999 -       {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
8000 -       {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
8001 -       {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
8002 -       {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
8003 -       {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
8004 -       {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
8005 -       {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
8006 -       {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
8007 -       {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
8008 -       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
8009 -       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
8010 -       {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
8011 -       {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
8012 -       {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
8013 -       {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
8014 -       {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
8015 -       {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
8016 -       {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
8017 -       {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
8018 -       {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8019 -       {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8020 -       {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8021 -       {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8022 -       {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8023 -       {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8024 -       {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8025 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8026 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8027 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8028 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8029 -       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8030 -       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
8031 -       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
8032 -       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
8033 -       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
8034 -       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
8035 -       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
8036 -       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
8037 -       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
8038 -       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
8039 -       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
8040 -       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
8041 -       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
8042 -       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
8043 -       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
8044 -       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
8045 -       {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
8046 -       {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
8047 -       {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
8048 -       {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
8049 -       {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
8050 -       {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
8051 -};
8052 -
8053 -static const u32 ar9462_2p1_modes_high_ob_db_tx_gain[][5] = {
8054 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8055 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
8056 -       {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
8057 -       {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
8058 -       {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
8059 -       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
8060 -       {0x0000a410, 0x000050da, 0x000050da, 0x000050de, 0x000050de},
8061 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8062 -       {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
8063 -       {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
8064 -       {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
8065 -       {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
8066 -       {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
8067 -       {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
8068 -       {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
8069 -       {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
8070 -       {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
8071 -       {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
8072 -       {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
8073 -       {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
8074 -       {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20},
8075 -       {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22},
8076 -       {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24},
8077 -       {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640},
8078 -       {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660},
8079 -       {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861},
8080 -       {0x0000a548, 0x55025eb3, 0x55025eb3, 0x3e001a81, 0x3e001a81},
8081 -       {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x42001a83, 0x42001a83},
8082 -       {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x44001a84, 0x44001a84},
8083 -       {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3},
8084 -       {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},
8085 -       {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},
8086 -       {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},
8087 -       {0x0000a564, 0x751ffff6, 0x751ffff6, 0x56001eec, 0x56001eec},
8088 -       {0x0000a568, 0x751ffff6, 0x751ffff6, 0x58001ef0, 0x58001ef0},
8089 -       {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x5a001ef4, 0x5a001ef4},
8090 -       {0x0000a570, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
8091 -       {0x0000a574, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
8092 -       {0x0000a578, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
8093 -       {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
8094 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8095 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8096 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8097 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8098 -       {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
8099 -       {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
8100 -       {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
8101 -       {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
8102 -       {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
8103 -       {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
8104 -       {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
8105 -       {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
8106 -       {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
8107 -       {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
8108 -       {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
8109 -       {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
8110 -       {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
8111 -       {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
8112 -       {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
8113 -       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
8114 -       {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
8115 -       {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060},
8116 -       {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
8117 -       {0x00016444, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
8118 -       {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000},
8119 -       {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
8120 -};
8121 -
8122 -static const u32 ar9462_2p1_modes_mix_ob_db_tx_gain[][5] = {
8123 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8124 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
8125 -       {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
8126 -       {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
8127 -       {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
8128 -       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
8129 -       {0x0000a410, 0x0000d0da, 0x0000d0da, 0x0000d0de, 0x0000d0de},
8130 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8131 -       {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
8132 -       {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
8133 -       {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
8134 -       {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
8135 -       {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
8136 -       {0x0000a514, 0x18022622, 0x18022622, 0x12000400, 0x12000400},
8137 -       {0x0000a518, 0x1b022822, 0x1b022822, 0x16000402, 0x16000402},
8138 -       {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
8139 -       {0x0000a520, 0x22022c41, 0x22022c41, 0x1c000603, 0x1c000603},
8140 -       {0x0000a524, 0x28023042, 0x28023042, 0x21000a02, 0x21000a02},
8141 -       {0x0000a528, 0x2c023044, 0x2c023044, 0x25000a04, 0x25000a04},
8142 -       {0x0000a52c, 0x2f023644, 0x2f023644, 0x28000a20, 0x28000a20},
8143 -       {0x0000a530, 0x34025643, 0x34025643, 0x2c000e20, 0x2c000e20},
8144 -       {0x0000a534, 0x38025a44, 0x38025a44, 0x30000e22, 0x30000e22},
8145 -       {0x0000a538, 0x3b025e45, 0x3b025e45, 0x34000e24, 0x34000e24},
8146 -       {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x38001640, 0x38001640},
8147 -       {0x0000a540, 0x48025e6c, 0x48025e6c, 0x3c001660, 0x3c001660},
8148 -       {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3f001861, 0x3f001861},
8149 -       {0x0000a548, 0x55025eb3, 0x55025eb3, 0x43001a81, 0x43001a81},
8150 -       {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x47001a83, 0x47001a83},
8151 -       {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x4a001c84, 0x4a001c84},
8152 -       {0x0000a554, 0x62025f56, 0x62025f56, 0x4e001ce3, 0x4e001ce3},
8153 -       {0x0000a558, 0x66027f56, 0x66027f56, 0x52001ce5, 0x52001ce5},
8154 -       {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x56001ce9, 0x56001ce9},
8155 -       {0x0000a560, 0x70049f56, 0x70049f56, 0x5a001ceb, 0x5a001ceb},
8156 -       {0x0000a564, 0x751ffff6, 0x751ffff6, 0x5c001eec, 0x5c001eec},
8157 -       {0x0000a568, 0x751ffff6, 0x751ffff6, 0x5e001ef0, 0x5e001ef0},
8158 -       {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x60001ef4, 0x60001ef4},
8159 -       {0x0000a570, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
8160 -       {0x0000a574, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
8161 -       {0x0000a578, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
8162 -       {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
8163 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8164 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8165 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8166 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8167 -       {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
8168 -       {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
8169 -       {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
8170 -       {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
8171 -       {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
8172 -       {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
8173 -       {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
8174 -       {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
8175 -       {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
8176 -       {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
8177 -       {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
8178 -       {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
8179 -       {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
8180 -       {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
8181 -       {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
8182 -       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
8183 -};
8184 -
8185 -static const u32 ar9462_2p1_modes_fast_clock[][3] = {
8186 -       /* Addr      5G_HT20     5G_HT40   */
8187 -       {0x00001030, 0x00000268, 0x000004d0},
8188 -       {0x00001070, 0x0000018c, 0x00000318},
8189 -       {0x000010b0, 0x00000fd0, 0x00001fa0},
8190 -       {0x00008014, 0x044c044c, 0x08980898},
8191 -       {0x0000801c, 0x148ec02b, 0x148ec057},
8192 -       {0x00008318, 0x000044c0, 0x00008980},
8193 -       {0x00009e00, 0x0372131c, 0x0372131c},
8194 -       {0x0000a230, 0x0000400b, 0x00004016},
8195 -       {0x0000a254, 0x00000898, 0x00001130},
8196 -};
8197 -
8198 -static const u32 ar9462_2p1_baseband_core_txfir_coeff_japan_2484[][2] = {
8199 -       /* Addr      allmodes  */
8200 -       {0x0000a398, 0x00000000},
8201 -       {0x0000a39c, 0x6f7f0301},
8202 -       {0x0000a3a0, 0xca9228ee},
8203 -};
8204 -
8205  #endif /* INITVALS_9462_2P1_H */
8206 --- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
8207 +++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
8208 @@ -20,24 +20,11 @@
8209
8210  /* AR9485 1.1 */
8211
8212 -static const u32 ar9485_1_1_mac_postamble[][5] = {
8213 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8214 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
8215 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
8216 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
8217 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
8218 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
8219 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
8220 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
8221 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
8222 -};
8223 +#define ar9485_modes_lowest_ob_db_tx_gain_1_1 ar9485Modes_low_ob_db_tx_gain_1_1
8224
8225 -static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
8226 -       /* Addr      allmodes  */
8227 -       {0x00018c00, 0x18012e5e},
8228 -       {0x00018c04, 0x000801d8},
8229 -       {0x00018c08, 0x0000080c},
8230 -};
8231 +#define ar9485_1_1_mac_postamble ar9331_1p1_mac_postamble
8232 +
8233 +#define ar9485_1_1_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
8234
8235  static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
8236         /* Addr      allmodes  */
8237 @@ -553,100 +540,6 @@ static const u32 ar9485Modes_low_ob_db_t
8238         {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
8239  };
8240
8241 -static const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = {
8242 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8243 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
8244 -       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0x7999a83a, 0x7999a83a},
8245 -       {0x0000a2dc, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
8246 -       {0x0000a2e0, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
8247 -       {0x0000a2e4, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
8248 -       {0x0000a2e8, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
8249 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
8250 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8251 -       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
8252 -       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
8253 -       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
8254 -       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
8255 -       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
8256 -       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
8257 -       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
8258 -       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
8259 -       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
8260 -       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
8261 -       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
8262 -       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
8263 -       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
8264 -       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
8265 -       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
8266 -       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
8267 -       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
8268 -       {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
8269 -       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
8270 -       {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
8271 -       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
8272 -       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
8273 -       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
8274 -       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
8275 -       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
8276 -       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
8277 -       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
8278 -       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
8279 -       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
8280 -       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
8281 -       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
8282 -       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
8283 -       {0x0000a580, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8284 -       {0x0000a584, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8285 -       {0x0000a588, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8286 -       {0x0000a58c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8287 -       {0x0000a590, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8288 -       {0x0000a594, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8289 -       {0x0000a598, 0x00000000, 0x00000000, 0x01404501, 0x01404501},
8290 -       {0x0000a59c, 0x00000000, 0x00000000, 0x02808a02, 0x02808a02},
8291 -       {0x0000a5a0, 0x00000000, 0x00000000, 0x02808a02, 0x02808a02},
8292 -       {0x0000a5a4, 0x00000000, 0x00000000, 0x02808803, 0x02808803},
8293 -       {0x0000a5a8, 0x00000000, 0x00000000, 0x04c14b04, 0x04c14b04},
8294 -       {0x0000a5ac, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
8295 -       {0x0000a5b0, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
8296 -       {0x0000a5b4, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
8297 -       {0x0000a5b8, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
8298 -       {0x0000a5bc, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
8299 -       {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8300 -       {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8301 -       {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8302 -       {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8303 -       {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8304 -       {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8305 -       {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8306 -       {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8307 -       {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8308 -       {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8309 -       {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8310 -       {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8311 -       {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8312 -       {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8313 -       {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8314 -       {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8315 -       {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8316 -       {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8317 -       {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8318 -       {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8319 -       {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8320 -       {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8321 -       {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8322 -       {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8323 -       {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8324 -       {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8325 -       {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8326 -       {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8327 -       {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8328 -       {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8329 -       {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8330 -       {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8331 -       {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
8332 -       {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
8333 -};
8334 -
8335  static const u32 ar9485Modes_green_spur_ob_db_tx_gain_1_1[][5] = {
8336         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8337         {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
8338 @@ -1101,20 +994,6 @@ static const u32 ar9485_common_rx_gain_1
8339         {0x0000a1fc, 0x00000296},
8340  };
8341
8342 -static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
8343 -       /* Addr      allmodes  */
8344 -       {0x00018c00, 0x18052e5e},
8345 -       {0x00018c04, 0x000801d8},
8346 -       {0x00018c08, 0x0000080c},
8347 -};
8348 -
8349 -static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
8350 -       /* Addr      allmodes  */
8351 -       {0x00018c00, 0x18053e5e},
8352 -       {0x00018c04, 0x000801d8},
8353 -       {0x00018c08, 0x0000080c},
8354 -};
8355 -
8356  static const u32 ar9485_1_1_soc_preamble[][2] = {
8357         /* Addr      allmodes  */
8358         {0x00004014, 0xba280400},
8359 @@ -1173,13 +1052,6 @@ static const u32 ar9485_1_1_baseband_pos
8360         {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8361  };
8362
8363 -static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
8364 -       /* Addr      allmodes  */
8365 -       {0x00018c00, 0x18013e5e},
8366 -       {0x00018c04, 0x000801d8},
8367 -       {0x00018c08, 0x0000080c},
8368 -};
8369 -
8370  static const u32 ar9485_1_1_radio_postamble[][2] = {
8371         /* Addr      allmodes  */
8372         {0x0001609c, 0x0b283f31},
8373 @@ -1351,11 +1223,18 @@ static const u32 ar9485_1_1_mac_core[][2
8374         {0x000083d0, 0x000301ff},
8375  };
8376
8377 -static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
8378 +static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
8379         /* Addr      allmodes  */
8380 -       {0x0000a398, 0x00000000},
8381 -       {0x0000a39c, 0x6f7f0301},
8382 -       {0x0000a3a0, 0xca9228ee},
8383 +       {0x00018c00, 0x18013e5e},
8384 +       {0x00018c04, 0x000801d8},
8385 +       {0x00018c08, 0x0000080c},
8386 +};
8387 +
8388 +static const u32 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1[][2] = {
8389 +       /* Addr      allmodes  */
8390 +       {0x00018c00, 0x1801265e},
8391 +       {0x00018c04, 0x000801d8},
8392 +       {0x00018c08, 0x0000080c},
8393  };
8394
8395  #endif /* INITVALS_9485_H */
8396 --- a/drivers/net/wireless/ath/ath9k/pci.c
8397 +++ b/drivers/net/wireless/ath/ath9k/pci.c
8398 @@ -195,6 +195,93 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_i
8399                          0x3219),
8400           .driver_data = ATH9K_PCI_BT_ANT_DIV },
8401
8402 +       /* AR9485 cards with PLL power-save disabled by default. */
8403 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8404 +                        0x0032,
8405 +                        PCI_VENDOR_ID_AZWAVE,
8406 +                        0x2C97),
8407 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8408 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8409 +                        0x0032,
8410 +                        PCI_VENDOR_ID_AZWAVE,
8411 +                        0x2100),
8412 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8413 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8414 +                        0x0032,
8415 +                        0x1C56, /* ASKEY */
8416 +                        0x4001),
8417 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8418 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8419 +                        0x0032,
8420 +                        0x11AD, /* LITEON */
8421 +                        0x6627),
8422 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8423 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8424 +                        0x0032,
8425 +                        0x11AD, /* LITEON */
8426 +                        0x6628),
8427 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8428 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8429 +                        0x0032,
8430 +                        PCI_VENDOR_ID_FOXCONN,
8431 +                        0xE04E),
8432 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8433 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8434 +                        0x0032,
8435 +                        PCI_VENDOR_ID_FOXCONN,
8436 +                        0xE04F),
8437 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8438 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8439 +                        0x0032,
8440 +                        0x144F, /* ASKEY */
8441 +                        0x7197),
8442 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8443 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8444 +                        0x0032,
8445 +                        0x1B9A, /* XAVI */
8446 +                        0x2000),
8447 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8448 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8449 +                        0x0032,
8450 +                        0x1B9A, /* XAVI */
8451 +                        0x2001),
8452 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8453 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8454 +                        0x0032,
8455 +                        PCI_VENDOR_ID_AZWAVE,
8456 +                        0x1186),
8457 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8458 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8459 +                        0x0032,
8460 +                        PCI_VENDOR_ID_AZWAVE,
8461 +                        0x1F86),
8462 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8463 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8464 +                        0x0032,
8465 +                        PCI_VENDOR_ID_AZWAVE,
8466 +                        0x1195),
8467 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8468 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8469 +                        0x0032,
8470 +                        PCI_VENDOR_ID_AZWAVE,
8471 +                        0x1F95),
8472 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8473 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8474 +                        0x0032,
8475 +                        0x1B9A, /* XAVI */
8476 +                        0x1C00),
8477 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8478 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8479 +                        0x0032,
8480 +                        0x1B9A, /* XAVI */
8481 +                        0x1C01),
8482 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8483 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
8484 +                        0x0032,
8485 +                        PCI_VENDOR_ID_ASUSTEK,
8486 +                        0x850D),
8487 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
8488 +
8489         { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
8490         { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E  AR9580 */
8491
8492 --- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
8493 +++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
8494 @@ -20,7 +20,15 @@
8495
8496  /* AR9462 2.0 */
8497
8498 -static const u32 ar9462_modes_fast_clock_2p0[][3] = {
8499 +#define ar9462_2p0_mac_postamble ar9331_1p1_mac_postamble
8500 +
8501 +#define ar9462_2p0_common_wo_xlna_rx_gain ar9300Common_wo_xlna_rx_gain_table_2p2
8502 +
8503 +#define ar9462_2p0_common_5g_xlna_only_rxgain ar9462_2p0_common_mixed_rx_gain
8504 +
8505 +#define ar9462_2p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
8506 +
8507 +static const u32 ar9462_2p0_modes_fast_clock[][3] = {
8508         /* Addr      5G_HT20     5G_HT40   */
8509         {0x00001030, 0x00000268, 0x000004d0},
8510         {0x00001070, 0x0000018c, 0x00000318},
8511 @@ -33,13 +41,6 @@ static const u32 ar9462_modes_fast_clock
8512         {0x0000a254, 0x00000898, 0x00001130},
8513  };
8514
8515 -static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = {
8516 -       /* Addr      allmodes  */
8517 -       {0x00018c00, 0x18253ede},
8518 -       {0x00018c04, 0x000801d8},
8519 -       {0x00018c08, 0x0003780c},
8520 -};
8521 -
8522  static const u32 ar9462_2p0_baseband_postamble[][5] = {
8523         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8524         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
8525 @@ -99,7 +100,7 @@ static const u32 ar9462_2p0_baseband_pos
8526         {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
8527  };
8528
8529 -static const u32 ar9462_common_rx_gain_table_2p0[][2] = {
8530 +static const u32 ar9462_2p0_common_rx_gain[][2] = {
8531         /* Addr      allmodes  */
8532         {0x0000a000, 0x00010000},
8533         {0x0000a004, 0x00030002},
8534 @@ -359,20 +360,13 @@ static const u32 ar9462_common_rx_gain_t
8535         {0x0000b1fc, 0x00000196},
8536  };
8537
8538 -static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = {
8539 +static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] = {
8540         /* Addr      allmodes  */
8541         {0x00018c00, 0x18213ede},
8542         {0x00018c04, 0x000801d8},
8543         {0x00018c08, 0x0003780c},
8544  };
8545
8546 -static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = {
8547 -       /* Addr      allmodes  */
8548 -       {0x00018c00, 0x18212ede},
8549 -       {0x00018c04, 0x000801d8},
8550 -       {0x00018c08, 0x0003780c},
8551 -};
8552 -
8553  static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = {
8554         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8555         {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
8556 @@ -380,348 +374,81 @@ static const u32 ar9462_2p0_radio_postam
8557         {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
8558  };
8559
8560 -static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = {
8561 -       /* Addr      allmodes  */
8562 -       {0x0000a000, 0x00010000},
8563 -       {0x0000a004, 0x00030002},
8564 -       {0x0000a008, 0x00050004},
8565 -       {0x0000a00c, 0x00810080},
8566 -       {0x0000a010, 0x00830082},
8567 -       {0x0000a014, 0x01810180},
8568 -       {0x0000a018, 0x01830182},
8569 -       {0x0000a01c, 0x01850184},
8570 -       {0x0000a020, 0x01890188},
8571 -       {0x0000a024, 0x018b018a},
8572 -       {0x0000a028, 0x018d018c},
8573 -       {0x0000a02c, 0x03820190},
8574 -       {0x0000a030, 0x03840383},
8575 -       {0x0000a034, 0x03880385},
8576 -       {0x0000a038, 0x038a0389},
8577 -       {0x0000a03c, 0x038c038b},
8578 -       {0x0000a040, 0x0390038d},
8579 -       {0x0000a044, 0x03920391},
8580 -       {0x0000a048, 0x03940393},
8581 -       {0x0000a04c, 0x03960395},
8582 -       {0x0000a050, 0x00000000},
8583 -       {0x0000a054, 0x00000000},
8584 -       {0x0000a058, 0x00000000},
8585 -       {0x0000a05c, 0x00000000},
8586 -       {0x0000a060, 0x00000000},
8587 -       {0x0000a064, 0x00000000},
8588 -       {0x0000a068, 0x00000000},
8589 -       {0x0000a06c, 0x00000000},
8590 -       {0x0000a070, 0x00000000},
8591 -       {0x0000a074, 0x00000000},
8592 -       {0x0000a078, 0x00000000},
8593 -       {0x0000a07c, 0x00000000},
8594 -       {0x0000a080, 0x29292929},
8595 -       {0x0000a084, 0x29292929},
8596 -       {0x0000a088, 0x29292929},
8597 -       {0x0000a08c, 0x29292929},
8598 -       {0x0000a090, 0x22292929},
8599 -       {0x0000a094, 0x1d1d2222},
8600 -       {0x0000a098, 0x0c111117},
8601 -       {0x0000a09c, 0x00030303},
8602 -       {0x0000a0a0, 0x00000000},
8603 -       {0x0000a0a4, 0x00000000},
8604 -       {0x0000a0a8, 0x00000000},
8605 -       {0x0000a0ac, 0x00000000},
8606 -       {0x0000a0b0, 0x00000000},
8607 -       {0x0000a0b4, 0x00000000},
8608 -       {0x0000a0b8, 0x00000000},
8609 -       {0x0000a0bc, 0x00000000},
8610 -       {0x0000a0c0, 0x001f0000},
8611 -       {0x0000a0c4, 0x01000101},
8612 -       {0x0000a0c8, 0x011e011f},
8613 -       {0x0000a0cc, 0x011c011d},
8614 -       {0x0000a0d0, 0x02030204},
8615 -       {0x0000a0d4, 0x02010202},
8616 -       {0x0000a0d8, 0x021f0200},
8617 -       {0x0000a0dc, 0x0302021e},
8618 -       {0x0000a0e0, 0x03000301},
8619 -       {0x0000a0e4, 0x031e031f},
8620 -       {0x0000a0e8, 0x0402031d},
8621 -       {0x0000a0ec, 0x04000401},
8622 -       {0x0000a0f0, 0x041e041f},
8623 -       {0x0000a0f4, 0x0502041d},
8624 -       {0x0000a0f8, 0x05000501},
8625 -       {0x0000a0fc, 0x051e051f},
8626 -       {0x0000a100, 0x06010602},
8627 -       {0x0000a104, 0x061f0600},
8628 -       {0x0000a108, 0x061d061e},
8629 -       {0x0000a10c, 0x07020703},
8630 -       {0x0000a110, 0x07000701},
8631 -       {0x0000a114, 0x00000000},
8632 -       {0x0000a118, 0x00000000},
8633 -       {0x0000a11c, 0x00000000},
8634 -       {0x0000a120, 0x00000000},
8635 -       {0x0000a124, 0x00000000},
8636 -       {0x0000a128, 0x00000000},
8637 -       {0x0000a12c, 0x00000000},
8638 -       {0x0000a130, 0x00000000},
8639 -       {0x0000a134, 0x00000000},
8640 -       {0x0000a138, 0x00000000},
8641 -       {0x0000a13c, 0x00000000},
8642 -       {0x0000a140, 0x001f0000},
8643 -       {0x0000a144, 0x01000101},
8644 -       {0x0000a148, 0x011e011f},
8645 -       {0x0000a14c, 0x011c011d},
8646 -       {0x0000a150, 0x02030204},
8647 -       {0x0000a154, 0x02010202},
8648 -       {0x0000a158, 0x021f0200},
8649 -       {0x0000a15c, 0x0302021e},
8650 -       {0x0000a160, 0x03000301},
8651 -       {0x0000a164, 0x031e031f},
8652 -       {0x0000a168, 0x0402031d},
8653 -       {0x0000a16c, 0x04000401},
8654 -       {0x0000a170, 0x041e041f},
8655 -       {0x0000a174, 0x0502041d},
8656 -       {0x0000a178, 0x05000501},
8657 -       {0x0000a17c, 0x051e051f},
8658 -       {0x0000a180, 0x06010602},
8659 -       {0x0000a184, 0x061f0600},
8660 -       {0x0000a188, 0x061d061e},
8661 -       {0x0000a18c, 0x07020703},
8662 -       {0x0000a190, 0x07000701},
8663 -       {0x0000a194, 0x00000000},
8664 -       {0x0000a198, 0x00000000},
8665 -       {0x0000a19c, 0x00000000},
8666 -       {0x0000a1a0, 0x00000000},
8667 -       {0x0000a1a4, 0x00000000},
8668 -       {0x0000a1a8, 0x00000000},
8669 -       {0x0000a1ac, 0x00000000},
8670 -       {0x0000a1b0, 0x00000000},
8671 -       {0x0000a1b4, 0x00000000},
8672 -       {0x0000a1b8, 0x00000000},
8673 -       {0x0000a1bc, 0x00000000},
8674 -       {0x0000a1c0, 0x00000000},
8675 -       {0x0000a1c4, 0x00000000},
8676 -       {0x0000a1c8, 0x00000000},
8677 -       {0x0000a1cc, 0x00000000},
8678 -       {0x0000a1d0, 0x00000000},
8679 -       {0x0000a1d4, 0x00000000},
8680 -       {0x0000a1d8, 0x00000000},
8681 -       {0x0000a1dc, 0x00000000},
8682 -       {0x0000a1e0, 0x00000000},
8683 -       {0x0000a1e4, 0x00000000},
8684 -       {0x0000a1e8, 0x00000000},
8685 -       {0x0000a1ec, 0x00000000},
8686 -       {0x0000a1f0, 0x00000396},
8687 -       {0x0000a1f4, 0x00000396},
8688 -       {0x0000a1f8, 0x00000396},
8689 -       {0x0000a1fc, 0x00000196},
8690 -       {0x0000b000, 0x00010000},
8691 -       {0x0000b004, 0x00030002},
8692 -       {0x0000b008, 0x00050004},
8693 -       {0x0000b00c, 0x00810080},
8694 -       {0x0000b010, 0x00830082},
8695 -       {0x0000b014, 0x01810180},
8696 -       {0x0000b018, 0x01830182},
8697 -       {0x0000b01c, 0x01850184},
8698 -       {0x0000b020, 0x02810280},
8699 -       {0x0000b024, 0x02830282},
8700 -       {0x0000b028, 0x02850284},
8701 -       {0x0000b02c, 0x02890288},
8702 -       {0x0000b030, 0x028b028a},
8703 -       {0x0000b034, 0x0388028c},
8704 -       {0x0000b038, 0x038a0389},
8705 -       {0x0000b03c, 0x038c038b},
8706 -       {0x0000b040, 0x0390038d},
8707 -       {0x0000b044, 0x03920391},
8708 -       {0x0000b048, 0x03940393},
8709 -       {0x0000b04c, 0x03960395},
8710 -       {0x0000b050, 0x00000000},
8711 -       {0x0000b054, 0x00000000},
8712 -       {0x0000b058, 0x00000000},
8713 -       {0x0000b05c, 0x00000000},
8714 -       {0x0000b060, 0x00000000},
8715 -       {0x0000b064, 0x00000000},
8716 -       {0x0000b068, 0x00000000},
8717 -       {0x0000b06c, 0x00000000},
8718 -       {0x0000b070, 0x00000000},
8719 -       {0x0000b074, 0x00000000},
8720 -       {0x0000b078, 0x00000000},
8721 -       {0x0000b07c, 0x00000000},
8722 -       {0x0000b080, 0x32323232},
8723 -       {0x0000b084, 0x2f2f3232},
8724 -       {0x0000b088, 0x23282a2d},
8725 -       {0x0000b08c, 0x1c1e2123},
8726 -       {0x0000b090, 0x14171919},
8727 -       {0x0000b094, 0x0e0e1214},
8728 -       {0x0000b098, 0x03050707},
8729 -       {0x0000b09c, 0x00030303},
8730 -       {0x0000b0a0, 0x00000000},
8731 -       {0x0000b0a4, 0x00000000},
8732 -       {0x0000b0a8, 0x00000000},
8733 -       {0x0000b0ac, 0x00000000},
8734 -       {0x0000b0b0, 0x00000000},
8735 -       {0x0000b0b4, 0x00000000},
8736 -       {0x0000b0b8, 0x00000000},
8737 -       {0x0000b0bc, 0x00000000},
8738 -       {0x0000b0c0, 0x003f0020},
8739 -       {0x0000b0c4, 0x00400041},
8740 -       {0x0000b0c8, 0x0140005f},
8741 -       {0x0000b0cc, 0x0160015f},
8742 -       {0x0000b0d0, 0x017e017f},
8743 -       {0x0000b0d4, 0x02410242},
8744 -       {0x0000b0d8, 0x025f0240},
8745 -       {0x0000b0dc, 0x027f0260},
8746 -       {0x0000b0e0, 0x0341027e},
8747 -       {0x0000b0e4, 0x035f0340},
8748 -       {0x0000b0e8, 0x037f0360},
8749 -       {0x0000b0ec, 0x04400441},
8750 -       {0x0000b0f0, 0x0460045f},
8751 -       {0x0000b0f4, 0x0541047f},
8752 -       {0x0000b0f8, 0x055f0540},
8753 -       {0x0000b0fc, 0x057f0560},
8754 -       {0x0000b100, 0x06400641},
8755 -       {0x0000b104, 0x0660065f},
8756 -       {0x0000b108, 0x067e067f},
8757 -       {0x0000b10c, 0x07410742},
8758 -       {0x0000b110, 0x075f0740},
8759 -       {0x0000b114, 0x077f0760},
8760 -       {0x0000b118, 0x07800781},
8761 -       {0x0000b11c, 0x07a0079f},
8762 -       {0x0000b120, 0x07c107bf},
8763 -       {0x0000b124, 0x000007c0},
8764 -       {0x0000b128, 0x00000000},
8765 -       {0x0000b12c, 0x00000000},
8766 -       {0x0000b130, 0x00000000},
8767 -       {0x0000b134, 0x00000000},
8768 -       {0x0000b138, 0x00000000},
8769 -       {0x0000b13c, 0x00000000},
8770 -       {0x0000b140, 0x003f0020},
8771 -       {0x0000b144, 0x00400041},
8772 -       {0x0000b148, 0x0140005f},
8773 -       {0x0000b14c, 0x0160015f},
8774 -       {0x0000b150, 0x017e017f},
8775 -       {0x0000b154, 0x02410242},
8776 -       {0x0000b158, 0x025f0240},
8777 -       {0x0000b15c, 0x027f0260},
8778 -       {0x0000b160, 0x0341027e},
8779 -       {0x0000b164, 0x035f0340},
8780 -       {0x0000b168, 0x037f0360},
8781 -       {0x0000b16c, 0x04400441},
8782 -       {0x0000b170, 0x0460045f},
8783 -       {0x0000b174, 0x0541047f},
8784 -       {0x0000b178, 0x055f0540},
8785 -       {0x0000b17c, 0x057f0560},
8786 -       {0x0000b180, 0x06400641},
8787 -       {0x0000b184, 0x0660065f},
8788 -       {0x0000b188, 0x067e067f},
8789 -       {0x0000b18c, 0x07410742},
8790 -       {0x0000b190, 0x075f0740},
8791 -       {0x0000b194, 0x077f0760},
8792 -       {0x0000b198, 0x07800781},
8793 -       {0x0000b19c, 0x07a0079f},
8794 -       {0x0000b1a0, 0x07c107bf},
8795 -       {0x0000b1a4, 0x000007c0},
8796 -       {0x0000b1a8, 0x00000000},
8797 -       {0x0000b1ac, 0x00000000},
8798 -       {0x0000b1b0, 0x00000000},
8799 -       {0x0000b1b4, 0x00000000},
8800 -       {0x0000b1b8, 0x00000000},
8801 -       {0x0000b1bc, 0x00000000},
8802 -       {0x0000b1c0, 0x00000000},
8803 -       {0x0000b1c4, 0x00000000},
8804 -       {0x0000b1c8, 0x00000000},
8805 -       {0x0000b1cc, 0x00000000},
8806 -       {0x0000b1d0, 0x00000000},
8807 -       {0x0000b1d4, 0x00000000},
8808 -       {0x0000b1d8, 0x00000000},
8809 -       {0x0000b1dc, 0x00000000},
8810 -       {0x0000b1e0, 0x00000000},
8811 -       {0x0000b1e4, 0x00000000},
8812 -       {0x0000b1e8, 0x00000000},
8813 -       {0x0000b1ec, 0x00000000},
8814 -       {0x0000b1f0, 0x00000396},
8815 -       {0x0000b1f4, 0x00000396},
8816 -       {0x0000b1f8, 0x00000396},
8817 -       {0x0000b1fc, 0x00000196},
8818 -};
8819 -
8820 -static const u32 ar9462_2p0_baseband_core_txfir_coeff_japan_2484[][2] = {
8821 -       /* Addr      allmodes  */
8822 -       {0x0000a398, 0x00000000},
8823 -       {0x0000a39c, 0x6f7f0301},
8824 -       {0x0000a3a0, 0xca9228ee},
8825 -};
8826 -
8827 -static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = {
8828 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8829 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
8830 -       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
8831 -       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
8832 -       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
8833 -       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
8834 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
8835 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8836 -       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8837 -       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
8838 -       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
8839 -       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
8840 -       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
8841 -       {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
8842 -       {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
8843 -       {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
8844 -       {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
8845 -       {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
8846 -       {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
8847 -       {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
8848 -       {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
8849 -       {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
8850 -       {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
8851 -       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
8852 -       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
8853 -       {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
8854 -       {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
8855 -       {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
8856 -       {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
8857 -       {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
8858 -       {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
8859 -       {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
8860 -       {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
8861 -       {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8862 -       {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8863 -       {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8864 -       {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8865 -       {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8866 -       {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8867 -       {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8868 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8869 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8870 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8871 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8872 -       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8873 -       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
8874 -       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
8875 -       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
8876 -       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
8877 -       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
8878 -       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
8879 -       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
8880 -       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
8881 -       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
8882 -       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
8883 -       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
8884 -       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
8885 -       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
8886 -       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
8887 -       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
8888 -       {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
8889 -       {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
8890 -       {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
8891 -       {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
8892 -       {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
8893 -       {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
8894 -};
8895 -
8896 -static const u32 ar9462_2p0_soc_postamble[][5] = {
8897 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8898 -       {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
8899 -};
8900 -
8901 -static const u32 ar9462_2p0_baseband_core[][2] = {
8902 +static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = {
8903 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8904 +       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
8905 +       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
8906 +       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
8907 +       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
8908 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
8909 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
8910 +       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8911 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8912 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
8913 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
8914 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
8915 +       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
8916 +       {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
8917 +       {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
8918 +       {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
8919 +       {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
8920 +       {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
8921 +       {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
8922 +       {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
8923 +       {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
8924 +       {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
8925 +       {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
8926 +       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
8927 +       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
8928 +       {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
8929 +       {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
8930 +       {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
8931 +       {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
8932 +       {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
8933 +       {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
8934 +       {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
8935 +       {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
8936 +       {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8937 +       {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8938 +       {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8939 +       {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8940 +       {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8941 +       {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8942 +       {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
8943 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8944 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8945 +       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8946 +       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8947 +       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8948 +       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
8949 +       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
8950 +       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
8951 +       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
8952 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
8953 +       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
8954 +       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
8955 +       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
8956 +       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
8957 +       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
8958 +       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
8959 +       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
8960 +       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
8961 +       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
8962 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
8963 +       {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
8964 +       {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
8965 +       {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
8966 +       {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
8967 +       {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
8968 +       {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
8969 +};
8970 +
8971 +static const u32 ar9462_2p0_soc_postamble[][5] = {
8972 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8973 +       {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
8974 +};
8975 +
8976 +static const u32 ar9462_2p0_baseband_core[][2] = {
8977         /* Addr      allmodes  */
8978         {0x00009800, 0xafe68e30},
8979         {0x00009804, 0xfd14e000},
8980 @@ -879,7 +606,7 @@ static const u32 ar9462_2p0_radio_postam
8981         {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
8982  };
8983
8984 -static const u32 ar9462_modes_mix_ob_db_tx_gain_table_2p0[][5] = {
8985 +static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] = {
8986         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8987         {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
8988         {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
8989 @@ -942,7 +669,7 @@ static const u32 ar9462_modes_mix_ob_db_
8990         {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
8991  };
8992
8993 -static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = {
8994 +static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] = {
8995         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8996         {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
8997         {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
8998 @@ -1240,19 +967,7 @@ static const u32 ar9462_2p0_mac_core[][2
8999         {0x000083d0, 0x000301ff},
9000  };
9001
9002 -static const u32 ar9462_2p0_mac_postamble[][5] = {
9003 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9004 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
9005 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
9006 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
9007 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
9008 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
9009 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
9010 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
9011 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
9012 -};
9013 -
9014 -static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = {
9015 +static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = {
9016         /* Addr      allmodes  */
9017         {0x0000a000, 0x00010000},
9018         {0x0000a004, 0x00030002},
9019 @@ -1517,266 +1232,6 @@ static const u32 ar9462_2p0_baseband_pos
9020         {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
9021  };
9022
9023 -static const u32 ar9462_2p0_5g_xlna_only_rxgain[][2] = {
9024 -       /* Addr      allmodes  */
9025 -       {0x0000a000, 0x00010000},
9026 -       {0x0000a004, 0x00030002},
9027 -       {0x0000a008, 0x00050004},
9028 -       {0x0000a00c, 0x00810080},
9029 -       {0x0000a010, 0x00830082},
9030 -       {0x0000a014, 0x01810180},
9031 -       {0x0000a018, 0x01830182},
9032 -       {0x0000a01c, 0x01850184},
9033 -       {0x0000a020, 0x01890188},
9034 -       {0x0000a024, 0x018b018a},
9035 -       {0x0000a028, 0x018d018c},
9036 -       {0x0000a02c, 0x03820190},
9037 -       {0x0000a030, 0x03840383},
9038 -       {0x0000a034, 0x03880385},
9039 -       {0x0000a038, 0x038a0389},
9040 -       {0x0000a03c, 0x038c038b},
9041 -       {0x0000a040, 0x0390038d},
9042 -       {0x0000a044, 0x03920391},
9043 -       {0x0000a048, 0x03940393},
9044 -       {0x0000a04c, 0x03960395},
9045 -       {0x0000a050, 0x00000000},
9046 -       {0x0000a054, 0x00000000},
9047 -       {0x0000a058, 0x00000000},
9048 -       {0x0000a05c, 0x00000000},
9049 -       {0x0000a060, 0x00000000},
9050 -       {0x0000a064, 0x00000000},
9051 -       {0x0000a068, 0x00000000},
9052 -       {0x0000a06c, 0x00000000},
9053 -       {0x0000a070, 0x00000000},
9054 -       {0x0000a074, 0x00000000},
9055 -       {0x0000a078, 0x00000000},
9056 -       {0x0000a07c, 0x00000000},
9057 -       {0x0000a080, 0x29292929},
9058 -       {0x0000a084, 0x29292929},
9059 -       {0x0000a088, 0x29292929},
9060 -       {0x0000a08c, 0x29292929},
9061 -       {0x0000a090, 0x22292929},
9062 -       {0x0000a094, 0x1d1d2222},
9063 -       {0x0000a098, 0x0c111117},
9064 -       {0x0000a09c, 0x00030303},
9065 -       {0x0000a0a0, 0x00000000},
9066 -       {0x0000a0a4, 0x00000000},
9067 -       {0x0000a0a8, 0x00000000},
9068 -       {0x0000a0ac, 0x00000000},
9069 -       {0x0000a0b0, 0x00000000},
9070 -       {0x0000a0b4, 0x00000000},
9071 -       {0x0000a0b8, 0x00000000},
9072 -       {0x0000a0bc, 0x00000000},
9073 -       {0x0000a0c0, 0x001f0000},
9074 -       {0x0000a0c4, 0x01000101},
9075 -       {0x0000a0c8, 0x011e011f},
9076 -       {0x0000a0cc, 0x011c011d},
9077 -       {0x0000a0d0, 0x02030204},
9078 -       {0x0000a0d4, 0x02010202},
9079 -       {0x0000a0d8, 0x021f0200},
9080 -       {0x0000a0dc, 0x0302021e},
9081 -       {0x0000a0e0, 0x03000301},
9082 -       {0x0000a0e4, 0x031e031f},
9083 -       {0x0000a0e8, 0x0402031d},
9084 -       {0x0000a0ec, 0x04000401},
9085 -       {0x0000a0f0, 0x041e041f},
9086 -       {0x0000a0f4, 0x0502041d},
9087 -       {0x0000a0f8, 0x05000501},
9088 -       {0x0000a0fc, 0x051e051f},
9089 -       {0x0000a100, 0x06010602},
9090 -       {0x0000a104, 0x061f0600},
9091 -       {0x0000a108, 0x061d061e},
9092 -       {0x0000a10c, 0x07020703},
9093 -       {0x0000a110, 0x07000701},
9094 -       {0x0000a114, 0x00000000},
9095 -       {0x0000a118, 0x00000000},
9096 -       {0x0000a11c, 0x00000000},
9097 -       {0x0000a120, 0x00000000},
9098 -       {0x0000a124, 0x00000000},
9099 -       {0x0000a128, 0x00000000},
9100 -       {0x0000a12c, 0x00000000},
9101 -       {0x0000a130, 0x00000000},
9102 -       {0x0000a134, 0x00000000},
9103 -       {0x0000a138, 0x00000000},
9104 -       {0x0000a13c, 0x00000000},
9105 -       {0x0000a140, 0x001f0000},
9106 -       {0x0000a144, 0x01000101},
9107 -       {0x0000a148, 0x011e011f},
9108 -       {0x0000a14c, 0x011c011d},
9109 -       {0x0000a150, 0x02030204},
9110 -       {0x0000a154, 0x02010202},
9111 -       {0x0000a158, 0x021f0200},
9112 -       {0x0000a15c, 0x0302021e},
9113 -       {0x0000a160, 0x03000301},
9114 -       {0x0000a164, 0x031e031f},
9115 -       {0x0000a168, 0x0402031d},
9116 -       {0x0000a16c, 0x04000401},
9117 -       {0x0000a170, 0x041e041f},
9118 -       {0x0000a174, 0x0502041d},
9119 -       {0x0000a178, 0x05000501},
9120 -       {0x0000a17c, 0x051e051f},
9121 -       {0x0000a180, 0x06010602},
9122 -       {0x0000a184, 0x061f0600},
9123 -       {0x0000a188, 0x061d061e},
9124 -       {0x0000a18c, 0x07020703},
9125 -       {0x0000a190, 0x07000701},
9126 -       {0x0000a194, 0x00000000},
9127 -       {0x0000a198, 0x00000000},
9128 -       {0x0000a19c, 0x00000000},
9129 -       {0x0000a1a0, 0x00000000},
9130 -       {0x0000a1a4, 0x00000000},
9131 -       {0x0000a1a8, 0x00000000},
9132 -       {0x0000a1ac, 0x00000000},
9133 -       {0x0000a1b0, 0x00000000},
9134 -       {0x0000a1b4, 0x00000000},
9135 -       {0x0000a1b8, 0x00000000},
9136 -       {0x0000a1bc, 0x00000000},
9137 -       {0x0000a1c0, 0x00000000},
9138 -       {0x0000a1c4, 0x00000000},
9139 -       {0x0000a1c8, 0x00000000},
9140 -       {0x0000a1cc, 0x00000000},
9141 -       {0x0000a1d0, 0x00000000},
9142 -       {0x0000a1d4, 0x00000000},
9143 -       {0x0000a1d8, 0x00000000},
9144 -       {0x0000a1dc, 0x00000000},
9145 -       {0x0000a1e0, 0x00000000},
9146 -       {0x0000a1e4, 0x00000000},
9147 -       {0x0000a1e8, 0x00000000},
9148 -       {0x0000a1ec, 0x00000000},
9149 -       {0x0000a1f0, 0x00000396},
9150 -       {0x0000a1f4, 0x00000396},
9151 -       {0x0000a1f8, 0x00000396},
9152 -       {0x0000a1fc, 0x00000196},
9153 -       {0x0000b000, 0x00010000},
9154 -       {0x0000b004, 0x00030002},
9155 -       {0x0000b008, 0x00050004},
9156 -       {0x0000b00c, 0x00810080},
9157 -       {0x0000b010, 0x00830082},
9158 -       {0x0000b014, 0x01810180},
9159 -       {0x0000b018, 0x01830182},
9160 -       {0x0000b01c, 0x01850184},
9161 -       {0x0000b020, 0x02810280},
9162 -       {0x0000b024, 0x02830282},
9163 -       {0x0000b028, 0x02850284},
9164 -       {0x0000b02c, 0x02890288},
9165 -       {0x0000b030, 0x028b028a},
9166 -       {0x0000b034, 0x0388028c},
9167 -       {0x0000b038, 0x038a0389},
9168 -       {0x0000b03c, 0x038c038b},
9169 -       {0x0000b040, 0x0390038d},
9170 -       {0x0000b044, 0x03920391},
9171 -       {0x0000b048, 0x03940393},
9172 -       {0x0000b04c, 0x03960395},
9173 -       {0x0000b050, 0x00000000},
9174 -       {0x0000b054, 0x00000000},
9175 -       {0x0000b058, 0x00000000},
9176 -       {0x0000b05c, 0x00000000},
9177 -       {0x0000b060, 0x00000000},
9178 -       {0x0000b064, 0x00000000},
9179 -       {0x0000b068, 0x00000000},
9180 -       {0x0000b06c, 0x00000000},
9181 -       {0x0000b070, 0x00000000},
9182 -       {0x0000b074, 0x00000000},
9183 -       {0x0000b078, 0x00000000},
9184 -       {0x0000b07c, 0x00000000},
9185 -       {0x0000b080, 0x2a2d2f32},
9186 -       {0x0000b084, 0x21232328},
9187 -       {0x0000b088, 0x19191c1e},
9188 -       {0x0000b08c, 0x12141417},
9189 -       {0x0000b090, 0x07070e0e},
9190 -       {0x0000b094, 0x03030305},
9191 -       {0x0000b098, 0x00000003},
9192 -       {0x0000b09c, 0x00000000},
9193 -       {0x0000b0a0, 0x00000000},
9194 -       {0x0000b0a4, 0x00000000},
9195 -       {0x0000b0a8, 0x00000000},
9196 -       {0x0000b0ac, 0x00000000},
9197 -       {0x0000b0b0, 0x00000000},
9198 -       {0x0000b0b4, 0x00000000},
9199 -       {0x0000b0b8, 0x00000000},
9200 -       {0x0000b0bc, 0x00000000},
9201 -       {0x0000b0c0, 0x003f0020},
9202 -       {0x0000b0c4, 0x00400041},
9203 -       {0x0000b0c8, 0x0140005f},
9204 -       {0x0000b0cc, 0x0160015f},
9205 -       {0x0000b0d0, 0x017e017f},
9206 -       {0x0000b0d4, 0x02410242},
9207 -       {0x0000b0d8, 0x025f0240},
9208 -       {0x0000b0dc, 0x027f0260},
9209 -       {0x0000b0e0, 0x0341027e},
9210 -       {0x0000b0e4, 0x035f0340},
9211 -       {0x0000b0e8, 0x037f0360},
9212 -       {0x0000b0ec, 0x04400441},
9213 -       {0x0000b0f0, 0x0460045f},
9214 -       {0x0000b0f4, 0x0541047f},
9215 -       {0x0000b0f8, 0x055f0540},
9216 -       {0x0000b0fc, 0x057f0560},
9217 -       {0x0000b100, 0x06400641},
9218 -       {0x0000b104, 0x0660065f},
9219 -       {0x0000b108, 0x067e067f},
9220 -       {0x0000b10c, 0x07410742},
9221 -       {0x0000b110, 0x075f0740},
9222 -       {0x0000b114, 0x077f0760},
9223 -       {0x0000b118, 0x07800781},
9224 -       {0x0000b11c, 0x07a0079f},
9225 -       {0x0000b120, 0x07c107bf},
9226 -       {0x0000b124, 0x000007c0},
9227 -       {0x0000b128, 0x00000000},
9228 -       {0x0000b12c, 0x00000000},
9229 -       {0x0000b130, 0x00000000},
9230 -       {0x0000b134, 0x00000000},
9231 -       {0x0000b138, 0x00000000},
9232 -       {0x0000b13c, 0x00000000},
9233 -       {0x0000b140, 0x003f0020},
9234 -       {0x0000b144, 0x00400041},
9235 -       {0x0000b148, 0x0140005f},
9236 -       {0x0000b14c, 0x0160015f},
9237 -       {0x0000b150, 0x017e017f},
9238 -       {0x0000b154, 0x02410242},
9239 -       {0x0000b158, 0x025f0240},
9240 -       {0x0000b15c, 0x027f0260},
9241 -       {0x0000b160, 0x0341027e},
9242 -       {0x0000b164, 0x035f0340},
9243 -       {0x0000b168, 0x037f0360},
9244 -       {0x0000b16c, 0x04400441},
9245 -       {0x0000b170, 0x0460045f},
9246 -       {0x0000b174, 0x0541047f},
9247 -       {0x0000b178, 0x055f0540},
9248 -       {0x0000b17c, 0x057f0560},
9249 -       {0x0000b180, 0x06400641},
9250 -       {0x0000b184, 0x0660065f},
9251 -       {0x0000b188, 0x067e067f},
9252 -       {0x0000b18c, 0x07410742},
9253 -       {0x0000b190, 0x075f0740},
9254 -       {0x0000b194, 0x077f0760},
9255 -       {0x0000b198, 0x07800781},
9256 -       {0x0000b19c, 0x07a0079f},
9257 -       {0x0000b1a0, 0x07c107bf},
9258 -       {0x0000b1a4, 0x000007c0},
9259 -       {0x0000b1a8, 0x00000000},
9260 -       {0x0000b1ac, 0x00000000},
9261 -       {0x0000b1b0, 0x00000000},
9262 -       {0x0000b1b4, 0x00000000},
9263 -       {0x0000b1b8, 0x00000000},
9264 -       {0x0000b1bc, 0x00000000},
9265 -       {0x0000b1c0, 0x00000000},
9266 -       {0x0000b1c4, 0x00000000},
9267 -       {0x0000b1c8, 0x00000000},
9268 -       {0x0000b1cc, 0x00000000},
9269 -       {0x0000b1d0, 0x00000000},
9270 -       {0x0000b1d4, 0x00000000},
9271 -       {0x0000b1d8, 0x00000000},
9272 -       {0x0000b1dc, 0x00000000},
9273 -       {0x0000b1e0, 0x00000000},
9274 -       {0x0000b1e4, 0x00000000},
9275 -       {0x0000b1e8, 0x00000000},
9276 -       {0x0000b1ec, 0x00000000},
9277 -       {0x0000b1f0, 0x00000396},
9278 -       {0x0000b1f4, 0x00000396},
9279 -       {0x0000b1f8, 0x00000396},
9280 -       {0x0000b1fc, 0x00000196},
9281 -};
9282 -
9283  static const u32 ar9462_2p0_baseband_core_mix_rxgain[][2] = {
9284         /* Addr      allmodes  */
9285         {0x00009fd0, 0x0a2d6b93},
9286 --- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
9287 +++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
9288 @@ -303,7 +303,7 @@ static const u32 ar9300_2p2_mac_postambl
9289         {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
9290         {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
9291         {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
9292 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
9293 +       {0x00008120, 0x18f04800, 0x18f04800, 0x18f04810, 0x18f04810},
9294         {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
9295         {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
9296  };
9297 @@ -352,7 +352,7 @@ static const u32 ar9300_2p2_baseband_pos
9298         {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
9299         {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
9300         {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
9301 -       {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
9302 +       {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982},
9303         {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
9304         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9305         {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
9306 @@ -378,9 +378,9 @@ static const u32 ar9300_2p2_baseband_cor
9307         {0x00009814, 0x9280c00a},
9308         {0x00009818, 0x00000000},
9309         {0x0000981c, 0x00020028},
9310 -       {0x00009834, 0x6400a290},
9311 +       {0x00009834, 0x6400a190},
9312         {0x00009838, 0x0108ecff},
9313 -       {0x0000983c, 0x0d000600},
9314 +       {0x0000983c, 0x14000600},
9315         {0x00009880, 0x201fff00},
9316         {0x00009884, 0x00001042},
9317         {0x000098a4, 0x00200400},
9318 @@ -401,7 +401,7 @@ static const u32 ar9300_2p2_baseband_cor
9319         {0x00009d04, 0x40206c10},
9320         {0x00009d08, 0x009c4060},
9321         {0x00009d0c, 0x9883800a},
9322 -       {0x00009d10, 0x01834061},
9323 +       {0x00009d10, 0x01884061},
9324         {0x00009d14, 0x00c0040b},
9325         {0x00009d18, 0x00000000},
9326         {0x00009e08, 0x0038230c},
9327 @@ -459,7 +459,7 @@ static const u32 ar9300_2p2_baseband_cor
9328         {0x0000a3e8, 0x20202020},
9329         {0x0000a3ec, 0x20202020},
9330         {0x0000a3f0, 0x00000000},
9331 -       {0x0000a3f4, 0x00000246},
9332 +       {0x0000a3f4, 0x00000000},
9333         {0x0000a3f8, 0x0c9bd380},
9334         {0x0000a3fc, 0x000f0f01},
9335         {0x0000a400, 0x8fa91f01},
9336 @@ -534,107 +534,107 @@ static const u32 ar9300_2p2_baseband_cor
9337
9338  static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
9339         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9340 -       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
9341 -       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
9342 -       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
9343 +       {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
9344 +       {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
9345 +       {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
9346         {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9347 -       {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
9348 -       {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
9349 -       {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
9350 -       {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
9351 -       {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
9352 -       {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
9353 -       {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
9354 -       {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
9355 -       {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
9356 -       {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
9357 -       {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
9358 -       {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
9359 -       {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
9360 -       {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
9361 -       {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
9362 -       {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
9363 -       {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
9364 -       {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
9365 -       {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
9366 -       {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
9367 -       {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
9368 -       {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
9369 -       {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
9370 -       {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
9371 -       {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
9372 -       {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
9373 -       {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
9374 -       {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
9375 -       {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
9376 -       {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
9377 -       {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
9378 -       {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
9379 -       {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
9380 -       {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
9381 -       {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
9382 -       {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
9383 -       {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
9384 -       {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
9385 -       {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
9386 -       {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
9387 -       {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
9388 -       {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
9389 -       {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
9390 -       {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
9391 -       {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
9392 -       {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
9393 -       {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
9394 -       {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
9395 -       {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
9396 -       {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
9397 -       {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
9398 -       {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
9399 -       {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
9400 -       {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
9401 -       {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
9402 -       {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
9403 -       {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
9404 -       {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
9405 -       {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
9406 -       {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
9407 -       {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
9408 -       {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
9409 -       {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
9410 -       {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
9411 -       {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
9412 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
9413 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9414 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
9415 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
9416 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
9417 +       {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
9418 +       {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
9419 +       {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
9420 +       {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
9421 +       {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
9422 +       {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
9423 +       {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
9424 +       {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
9425 +       {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
9426 +       {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
9427 +       {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
9428 +       {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
9429 +       {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
9430 +       {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
9431 +       {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
9432 +       {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
9433 +       {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
9434 +       {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
9435 +       {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
9436 +       {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
9437 +       {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
9438 +       {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9439 +       {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9440 +       {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9441 +       {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9442 +       {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9443 +       {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9444 +       {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9445 +       {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
9446 +       {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
9447 +       {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
9448 +       {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
9449 +       {0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
9450 +       {0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
9451 +       {0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
9452 +       {0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
9453 +       {0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
9454 +       {0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
9455 +       {0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
9456 +       {0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
9457 +       {0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
9458 +       {0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
9459 +       {0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
9460 +       {0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
9461 +       {0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
9462 +       {0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
9463 +       {0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
9464 +       {0x0000a5cc, 0x5e88442e, 0x5e88442e, 0x47801a83, 0x47801a83},
9465 +       {0x0000a5d0, 0x628a4431, 0x628a4431, 0x4a801c84, 0x4a801c84},
9466 +       {0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
9467 +       {0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
9468 +       {0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
9469 +       {0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
9470 +       {0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9471 +       {0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9472 +       {0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9473 +       {0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9474 +       {0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9475 +       {0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9476 +       {0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9477         {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9478         {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9479 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9480 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9481 -       {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
9482 -       {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
9483 -       {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
9484 -       {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
9485 -       {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
9486 -       {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
9487 -       {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
9488 -       {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9489 -       {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9490 -       {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9491 -       {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9492 -       {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9493 -       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
9494 -       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
9495 -       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
9496 +       {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
9497 +       {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
9498 +       {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
9499 +       {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
9500 +       {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
9501 +       {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
9502 +       {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
9503 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
9504 +       {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
9505 +       {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
9506 +       {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
9507 +       {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
9508 +       {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
9509 +       {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
9510 +       {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
9511 +       {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
9512 +       {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
9513         {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9514 -       {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
9515 -       {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
9516 -       {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
9517 +       {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
9518 +       {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
9519 +       {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
9520         {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9521         {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
9522 -       {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
9523 +       {0x00016048, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
9524         {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
9525         {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
9526 -       {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
9527 +       {0x00016448, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
9528         {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
9529         {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
9530 -       {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
9531 +       {0x00016848, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
9532         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
9533  };
9534
9535 @@ -644,7 +644,7 @@ static const u32 ar9300Modes_high_ob_db_
9536         {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
9537         {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
9538         {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9539 -       {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
9540 +       {0x0000a410, 0x000050d4, 0x000050d4, 0x000050d9, 0x000050d9},
9541         {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
9542         {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
9543         {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
9544 @@ -1086,8 +1086,8 @@ static const u32 ar9300Common_rx_gain_ta
9545         {0x0000b074, 0x00000000},
9546         {0x0000b078, 0x00000000},
9547         {0x0000b07c, 0x00000000},
9548 -       {0x0000b080, 0x2a2d2f32},
9549 -       {0x0000b084, 0x21232328},
9550 +       {0x0000b080, 0x23232323},
9551 +       {0x0000b084, 0x21232323},
9552         {0x0000b088, 0x19191c1e},
9553         {0x0000b08c, 0x12141417},
9554         {0x0000b090, 0x07070e0e},
9555 @@ -1385,9 +1385,9 @@ static const u32 ar9300_2p2_mac_core[][2
9556         {0x000081f8, 0x00000000},
9557         {0x000081fc, 0x00000000},
9558         {0x00008240, 0x00100000},
9559 -       {0x00008244, 0x0010f424},
9560 +       {0x00008244, 0x0010f400},
9561         {0x00008248, 0x00000800},
9562 -       {0x0000824c, 0x0001e848},
9563 +       {0x0000824c, 0x0001e800},
9564         {0x00008250, 0x00000000},
9565         {0x00008254, 0x00000000},
9566         {0x00008258, 0x00000000},
9567 @@ -1726,16 +1726,30 @@ static const u32 ar9300PciePhy_pll_on_cl
9568
9569  static const u32 ar9300PciePhy_clkreq_enable_L1_2p2[][2] = {
9570         /* Addr      allmodes  */
9571 -       {0x00004040, 0x08253e5e},
9572 +       {0x00004040, 0x0825365e},
9573         {0x00004040, 0x0008003b},
9574         {0x00004044, 0x00000000},
9575  };
9576
9577  static const u32 ar9300PciePhy_clkreq_disable_L1_2p2[][2] = {
9578         /* Addr      allmodes  */
9579 -       {0x00004040, 0x08213e5e},
9580 +       {0x00004040, 0x0821365e},
9581         {0x00004040, 0x0008003b},
9582         {0x00004044, 0x00000000},
9583  };
9584
9585 +static const u32 ar9300_2p2_baseband_core_txfir_coeff_japan_2484[][2] = {
9586 +       /* Addr      allmodes  */
9587 +       {0x0000a398, 0x00000000},
9588 +       {0x0000a39c, 0x6f7f0301},
9589 +       {0x0000a3a0, 0xca9228ee},
9590 +};
9591 +
9592 +static const u32 ar9300_2p2_baseband_postamble_dfs_channel[][3] = {
9593 +       /* Addr      5G          2G        */
9594 +       {0x00009824, 0x5ac668d0, 0x5ac668d0},
9595 +       {0x00009e0c, 0x6d4000e2, 0x6d4000e2},
9596 +       {0x00009e14, 0x37b9625e, 0x37b9625e},
9597 +};
9598 +
9599  #endif /* INITVALS_9003_2P2_H */
9600 --- /dev/null
9601 +++ b/drivers/net/wireless/ath/ath9k/ar9565_1p1_initvals.h
9602 @@ -0,0 +1,64 @@
9603 +/*
9604 + * Copyright (c) 2010-2011 Atheros Communications Inc.
9605 + * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
9606 + *
9607 + * Permission to use, copy, modify, and/or distribute this software for any
9608 + * purpose with or without fee is hereby granted, provided that the above
9609 + * copyright notice and this permission notice appear in all copies.
9610 + *
9611 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9612 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9613 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
9614 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
9615 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
9616 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
9617 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
9618 + */
9619 +
9620 +#ifndef INITVALS_9565_1P1_H
9621 +#define INITVALS_9565_1P1_H
9622 +
9623 +/* AR9565 1.1 */
9624 +
9625 +#define ar9565_1p1_mac_core ar9565_1p0_mac_core
9626 +
9627 +#define ar9565_1p1_mac_postamble ar9565_1p0_mac_postamble
9628 +
9629 +#define ar9565_1p1_baseband_core ar9565_1p0_baseband_core
9630 +
9631 +#define ar9565_1p1_baseband_postamble ar9565_1p0_baseband_postamble
9632 +
9633 +#define ar9565_1p1_radio_core ar9565_1p0_radio_core
9634 +
9635 +#define ar9565_1p1_soc_preamble ar9565_1p0_soc_preamble
9636 +
9637 +#define ar9565_1p1_soc_postamble ar9565_1p0_soc_postamble
9638 +
9639 +#define ar9565_1p1_Common_rx_gain_table ar9565_1p0_Common_rx_gain_table
9640 +
9641 +#define ar9565_1p1_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_Modes_lowest_ob_db_tx_gain_table
9642 +
9643 +#define ar9565_1p1_pciephy_clkreq_disable_L1 ar9565_1p0_pciephy_clkreq_disable_L1
9644 +
9645 +#define ar9565_1p1_modes_fast_clock ar9565_1p0_modes_fast_clock
9646 +
9647 +#define ar9565_1p1_common_wo_xlna_rx_gain_table ar9565_1p0_common_wo_xlna_rx_gain_table
9648 +
9649 +#define ar9565_1p1_modes_low_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table
9650 +
9651 +#define ar9565_1p1_modes_high_ob_db_tx_gain_table ar9565_1p0_modes_high_ob_db_tx_gain_table
9652 +
9653 +#define ar9565_1p1_modes_high_power_tx_gain_table ar9565_1p0_modes_high_power_tx_gain_table
9654 +
9655 +#define ar9565_1p1_baseband_core_txfir_coeff_japan_2484 ar9565_1p0_baseband_core_txfir_coeff_japan_2484
9656 +
9657 +static const u32 ar9565_1p1_radio_postamble[][5] = {
9658 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9659 +       {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
9660 +       {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
9661 +       {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
9662 +       {0x0001610c, 0x40000000, 0x40000000, 0x40000000, 0x40000000},
9663 +       {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
9664 +};
9665 +
9666 +#endif /* INITVALS_9565_1P1_H */
9667 --- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
9668 +++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
9669 @@ -20,18 +20,34 @@
9670
9671  /* AR9580 1.0 */
9672
9673 +#define ar9580_1p0_soc_preamble ar9300_2p2_soc_preamble
9674 +
9675 +#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
9676 +
9677 +#define ar9580_1p0_radio_core ar9300_2p2_radio_core
9678 +
9679 +#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
9680 +
9681 +#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
9682 +
9683 +#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
9684 +
9685 +#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
9686 +
9687  #define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2
9688
9689 +#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
9690 +
9691  static const u32 ar9580_1p0_radio_postamble[][5] = {
9692         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9693         {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
9694         {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
9695         {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
9696 -       {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
9697 +       {0x0001610c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
9698         {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
9699 -       {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
9700 +       {0x0001650c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
9701         {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
9702 -       {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
9703 +       {0x0001690c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
9704         {0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
9705  };
9706
9707 @@ -41,12 +57,10 @@ static const u32 ar9580_1p0_baseband_cor
9708         {0x00009804, 0xfd14e000},
9709         {0x00009808, 0x9c0a9f6b},
9710         {0x0000980c, 0x04900000},
9711 -       {0x00009814, 0x3280c00a},
9712 -       {0x00009818, 0x00000000},
9713         {0x0000981c, 0x00020028},
9714 -       {0x00009834, 0x6400a290},
9715 +       {0x00009834, 0x6400a190},
9716         {0x00009838, 0x0108ecff},
9717 -       {0x0000983c, 0x0d000600},
9718 +       {0x0000983c, 0x14000600},
9719         {0x00009880, 0x201fff00},
9720         {0x00009884, 0x00001042},
9721         {0x000098a4, 0x00200400},
9722 @@ -67,7 +81,7 @@ static const u32 ar9580_1p0_baseband_cor
9723         {0x00009d04, 0x40206c10},
9724         {0x00009d08, 0x009c4060},
9725         {0x00009d0c, 0x9883800a},
9726 -       {0x00009d10, 0x01834061},
9727 +       {0x00009d10, 0x01884061},
9728         {0x00009d14, 0x00c0040b},
9729         {0x00009d18, 0x00000000},
9730         {0x00009e08, 0x0038230c},
9731 @@ -198,8 +212,6 @@ static const u32 ar9580_1p0_baseband_cor
9732         {0x0000c420, 0x00000000},
9733  };
9734
9735 -#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
9736 -
9737  static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = {
9738         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9739         {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
9740 @@ -306,7 +318,112 @@ static const u32 ar9580_1p0_low_ob_db_tx
9741         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
9742  };
9743
9744 -#define ar9580_1p0_high_power_tx_gain_table ar9580_1p0_low_ob_db_tx_gain_table
9745 +static const u32 ar9580_1p0_high_power_tx_gain_table[][5] = {
9746 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9747 +       {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
9748 +       {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
9749 +       {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
9750 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9751 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
9752 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9753 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
9754 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
9755 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
9756 +       {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
9757 +       {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
9758 +       {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
9759 +       {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
9760 +       {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
9761 +       {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
9762 +       {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
9763 +       {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
9764 +       {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
9765 +       {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
9766 +       {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
9767 +       {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
9768 +       {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
9769 +       {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
9770 +       {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
9771 +       {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
9772 +       {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
9773 +       {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
9774 +       {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
9775 +       {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
9776 +       {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
9777 +       {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9778 +       {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9779 +       {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9780 +       {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9781 +       {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9782 +       {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9783 +       {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
9784 +       {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
9785 +       {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
9786 +       {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
9787 +       {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
9788 +       {0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
9789 +       {0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
9790 +       {0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
9791 +       {0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
9792 +       {0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
9793 +       {0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
9794 +       {0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
9795 +       {0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
9796 +       {0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
9797 +       {0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
9798 +       {0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
9799 +       {0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
9800 +       {0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
9801 +       {0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
9802 +       {0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
9803 +       {0x0000a5cc, 0x5a88442e, 0x5a88442e, 0x47801a83, 0x47801a83},
9804 +       {0x0000a5d0, 0x5e8a4431, 0x5e8a4431, 0x4a801c84, 0x4a801c84},
9805 +       {0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
9806 +       {0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
9807 +       {0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
9808 +       {0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
9809 +       {0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9810 +       {0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9811 +       {0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9812 +       {0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9813 +       {0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9814 +       {0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9815 +       {0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
9816 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9817 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9818 +       {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
9819 +       {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
9820 +       {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
9821 +       {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
9822 +       {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
9823 +       {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
9824 +       {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
9825 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
9826 +       {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
9827 +       {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
9828 +       {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
9829 +       {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
9830 +       {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
9831 +       {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
9832 +       {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
9833 +       {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
9834 +       {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
9835 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9836 +       {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
9837 +       {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
9838 +       {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
9839 +       {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9840 +       {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
9841 +       {0x00016048, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
9842 +       {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
9843 +       {0x00016288, 0x05a2040a, 0x05a2040a, 0x05a20408, 0x05a20408},
9844 +       {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
9845 +       {0x00016448, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
9846 +       {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
9847 +       {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
9848 +       {0x00016848, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
9849 +       {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
9850 +};
9851
9852  static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = {
9853         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9854 @@ -414,8 +531,6 @@ static const u32 ar9580_1p0_lowest_ob_db
9855         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
9856  };
9857
9858 -#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
9859 -
9860  static const u32 ar9580_1p0_mac_core[][2] = {
9861         /* Addr      allmodes  */
9862         {0x00000008, 0x00000000},
9863 @@ -679,14 +794,6 @@ static const u32 ar9580_1p0_mixed_ob_db_
9864         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
9865  };
9866
9867 -#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
9868 -
9869 -#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
9870 -
9871 -#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
9872 -
9873 -#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
9874 -
9875  static const u32 ar9580_1p0_type6_tx_gain_table[][5] = {
9876         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9877         {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
9878 @@ -761,165 +868,271 @@ static const u32 ar9580_1p0_type6_tx_gai
9879         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
9880  };
9881
9882 -static const u32 ar9580_1p0_soc_preamble[][2] = {
9883 +static const u32 ar9580_1p0_rx_gain_table[][2] = {
9884         /* Addr      allmodes  */
9885 -       {0x000040a4, 0x00a0c1c9},
9886 -       {0x00007008, 0x00000000},
9887 -       {0x00007020, 0x00000000},
9888 -       {0x00007034, 0x00000002},
9889 -       {0x00007038, 0x000004c2},
9890 -       {0x00007048, 0x00000008},
9891 -};
9892 -
9893 -#define ar9580_1p0_rx_gain_table ar9462_common_rx_gain_table_2p0
9894 -
9895 -static const u32 ar9580_1p0_radio_core[][2] = {
9896 -       /* Addr      allmodes  */
9897 -       {0x00016000, 0x36db6db6},
9898 -       {0x00016004, 0x6db6db40},
9899 -       {0x00016008, 0x73f00000},
9900 -       {0x0001600c, 0x00000000},
9901 -       {0x00016040, 0x7f80fff8},
9902 -       {0x0001604c, 0x76d005b5},
9903 -       {0x00016050, 0x556cf031},
9904 -       {0x00016054, 0x13449440},
9905 -       {0x00016058, 0x0c51c92c},
9906 -       {0x0001605c, 0x3db7fffc},
9907 -       {0x00016060, 0xfffffffc},
9908 -       {0x00016064, 0x000f0278},
9909 -       {0x0001606c, 0x6db60000},
9910 -       {0x00016080, 0x00000000},
9911 -       {0x00016084, 0x0e48048c},
9912 -       {0x00016088, 0x54214514},
9913 -       {0x0001608c, 0x119f481e},
9914 -       {0x00016090, 0x24926490},
9915 -       {0x00016098, 0xd2888888},
9916 -       {0x000160a0, 0x0a108ffe},
9917 -       {0x000160a4, 0x812fc370},
9918 -       {0x000160a8, 0x423c8000},
9919 -       {0x000160b4, 0x92480080},
9920 -       {0x000160c0, 0x00adb6d0},
9921 -       {0x000160c4, 0x6db6db60},
9922 -       {0x000160c8, 0x6db6db6c},
9923 -       {0x000160cc, 0x01e6c000},
9924 -       {0x00016100, 0x3fffbe01},
9925 -       {0x00016104, 0xfff80000},
9926 -       {0x00016108, 0x00080010},
9927 -       {0x00016144, 0x02084080},
9928 -       {0x00016148, 0x00000000},
9929 -       {0x00016280, 0x058a0001},
9930 -       {0x00016284, 0x3d840208},
9931 -       {0x00016288, 0x05a20408},
9932 -       {0x0001628c, 0x00038c07},
9933 -       {0x00016290, 0x00000004},
9934 -       {0x00016294, 0x458aa14f},
9935 -       {0x00016380, 0x00000000},
9936 -       {0x00016384, 0x00000000},
9937 -       {0x00016388, 0x00800700},
9938 -       {0x0001638c, 0x00800700},
9939 -       {0x00016390, 0x00800700},
9940 -       {0x00016394, 0x00000000},
9941 -       {0x00016398, 0x00000000},
9942 -       {0x0001639c, 0x00000000},
9943 -       {0x000163a0, 0x00000001},
9944 -       {0x000163a4, 0x00000001},
9945 -       {0x000163a8, 0x00000000},
9946 -       {0x000163ac, 0x00000000},
9947 -       {0x000163b0, 0x00000000},
9948 -       {0x000163b4, 0x00000000},
9949 -       {0x000163b8, 0x00000000},
9950 -       {0x000163bc, 0x00000000},
9951 -       {0x000163c0, 0x000000a0},
9952 -       {0x000163c4, 0x000c0000},
9953 -       {0x000163c8, 0x14021402},
9954 -       {0x000163cc, 0x00001402},
9955 -       {0x000163d0, 0x00000000},
9956 -       {0x000163d4, 0x00000000},
9957 -       {0x00016400, 0x36db6db6},
9958 -       {0x00016404, 0x6db6db40},
9959 -       {0x00016408, 0x73f00000},
9960 -       {0x0001640c, 0x00000000},
9961 -       {0x00016440, 0x7f80fff8},
9962 -       {0x0001644c, 0x76d005b5},
9963 -       {0x00016450, 0x556cf031},
9964 -       {0x00016454, 0x13449440},
9965 -       {0x00016458, 0x0c51c92c},
9966 -       {0x0001645c, 0x3db7fffc},
9967 -       {0x00016460, 0xfffffffc},
9968 -       {0x00016464, 0x000f0278},
9969 -       {0x0001646c, 0x6db60000},
9970 -       {0x00016500, 0x3fffbe01},
9971 -       {0x00016504, 0xfff80000},
9972 -       {0x00016508, 0x00080010},
9973 -       {0x00016544, 0x02084080},
9974 -       {0x00016548, 0x00000000},
9975 -       {0x00016780, 0x00000000},
9976 -       {0x00016784, 0x00000000},
9977 -       {0x00016788, 0x00800700},
9978 -       {0x0001678c, 0x00800700},
9979 -       {0x00016790, 0x00800700},
9980 -       {0x00016794, 0x00000000},
9981 -       {0x00016798, 0x00000000},
9982 -       {0x0001679c, 0x00000000},
9983 -       {0x000167a0, 0x00000001},
9984 -       {0x000167a4, 0x00000001},
9985 -       {0x000167a8, 0x00000000},
9986 -       {0x000167ac, 0x00000000},
9987 -       {0x000167b0, 0x00000000},
9988 -       {0x000167b4, 0x00000000},
9989 -       {0x000167b8, 0x00000000},
9990 -       {0x000167bc, 0x00000000},
9991 -       {0x000167c0, 0x000000a0},
9992 -       {0x000167c4, 0x000c0000},
9993 -       {0x000167c8, 0x14021402},
9994 -       {0x000167cc, 0x00001402},
9995 -       {0x000167d0, 0x00000000},
9996 -       {0x000167d4, 0x00000000},
9997 -       {0x00016800, 0x36db6db6},
9998 -       {0x00016804, 0x6db6db40},
9999 -       {0x00016808, 0x73f00000},
10000 -       {0x0001680c, 0x00000000},
10001 -       {0x00016840, 0x7f80fff8},
10002 -       {0x0001684c, 0x76d005b5},
10003 -       {0x00016850, 0x556cf031},
10004 -       {0x00016854, 0x13449440},
10005 -       {0x00016858, 0x0c51c92c},
10006 -       {0x0001685c, 0x3db7fffc},
10007 -       {0x00016860, 0xfffffffc},
10008 -       {0x00016864, 0x000f0278},
10009 -       {0x0001686c, 0x6db60000},
10010 -       {0x00016900, 0x3fffbe01},
10011 -       {0x00016904, 0xfff80000},
10012 -       {0x00016908, 0x00080010},
10013 -       {0x00016944, 0x02084080},
10014 -       {0x00016948, 0x00000000},
10015 -       {0x00016b80, 0x00000000},
10016 -       {0x00016b84, 0x00000000},
10017 -       {0x00016b88, 0x00800700},
10018 -       {0x00016b8c, 0x00800700},
10019 -       {0x00016b90, 0x00800700},
10020 -       {0x00016b94, 0x00000000},
10021 -       {0x00016b98, 0x00000000},
10022 -       {0x00016b9c, 0x00000000},
10023 -       {0x00016ba0, 0x00000001},
10024 -       {0x00016ba4, 0x00000001},
10025 -       {0x00016ba8, 0x00000000},
10026 -       {0x00016bac, 0x00000000},
10027 -       {0x00016bb0, 0x00000000},
10028 -       {0x00016bb4, 0x00000000},
10029 -       {0x00016bb8, 0x00000000},
10030 -       {0x00016bbc, 0x00000000},
10031 -       {0x00016bc0, 0x000000a0},
10032 -       {0x00016bc4, 0x000c0000},
10033 -       {0x00016bc8, 0x14021402},
10034 -       {0x00016bcc, 0x00001402},
10035 -       {0x00016bd0, 0x00000000},
10036 -       {0x00016bd4, 0x00000000},
10037 +       {0x0000a000, 0x00010000},
10038 +       {0x0000a004, 0x00030002},
10039 +       {0x0000a008, 0x00050004},
10040 +       {0x0000a00c, 0x00810080},
10041 +       {0x0000a010, 0x00830082},
10042 +       {0x0000a014, 0x01810180},
10043 +       {0x0000a018, 0x01830182},
10044 +       {0x0000a01c, 0x01850184},
10045 +       {0x0000a020, 0x01890188},
10046 +       {0x0000a024, 0x018b018a},
10047 +       {0x0000a028, 0x018d018c},
10048 +       {0x0000a02c, 0x01910190},
10049 +       {0x0000a030, 0x01930192},
10050 +       {0x0000a034, 0x01950194},
10051 +       {0x0000a038, 0x038a0196},
10052 +       {0x0000a03c, 0x038c038b},
10053 +       {0x0000a040, 0x0390038d},
10054 +       {0x0000a044, 0x03920391},
10055 +       {0x0000a048, 0x03940393},
10056 +       {0x0000a04c, 0x03960395},
10057 +       {0x0000a050, 0x00000000},
10058 +       {0x0000a054, 0x00000000},
10059 +       {0x0000a058, 0x00000000},
10060 +       {0x0000a05c, 0x00000000},
10061 +       {0x0000a060, 0x00000000},
10062 +       {0x0000a064, 0x00000000},
10063 +       {0x0000a068, 0x00000000},
10064 +       {0x0000a06c, 0x00000000},
10065 +       {0x0000a070, 0x00000000},
10066 +       {0x0000a074, 0x00000000},
10067 +       {0x0000a078, 0x00000000},
10068 +       {0x0000a07c, 0x00000000},
10069 +       {0x0000a080, 0x22222229},
10070 +       {0x0000a084, 0x1d1d1d1d},
10071 +       {0x0000a088, 0x1d1d1d1d},
10072 +       {0x0000a08c, 0x1d1d1d1d},
10073 +       {0x0000a090, 0x171d1d1d},
10074 +       {0x0000a094, 0x11111717},
10075 +       {0x0000a098, 0x00030311},
10076 +       {0x0000a09c, 0x00000000},
10077 +       {0x0000a0a0, 0x00000000},
10078 +       {0x0000a0a4, 0x00000000},
10079 +       {0x0000a0a8, 0x00000000},
10080 +       {0x0000a0ac, 0x00000000},
10081 +       {0x0000a0b0, 0x00000000},
10082 +       {0x0000a0b4, 0x00000000},
10083 +       {0x0000a0b8, 0x00000000},
10084 +       {0x0000a0bc, 0x00000000},
10085 +       {0x0000a0c0, 0x001f0000},
10086 +       {0x0000a0c4, 0x01000101},
10087 +       {0x0000a0c8, 0x011e011f},
10088 +       {0x0000a0cc, 0x011c011d},
10089 +       {0x0000a0d0, 0x02030204},
10090 +       {0x0000a0d4, 0x02010202},
10091 +       {0x0000a0d8, 0x021f0200},
10092 +       {0x0000a0dc, 0x0302021e},
10093 +       {0x0000a0e0, 0x03000301},
10094 +       {0x0000a0e4, 0x031e031f},
10095 +       {0x0000a0e8, 0x0402031d},
10096 +       {0x0000a0ec, 0x04000401},
10097 +       {0x0000a0f0, 0x041e041f},
10098 +       {0x0000a0f4, 0x0502041d},
10099 +       {0x0000a0f8, 0x05000501},
10100 +       {0x0000a0fc, 0x051e051f},
10101 +       {0x0000a100, 0x06010602},
10102 +       {0x0000a104, 0x061f0600},
10103 +       {0x0000a108, 0x061d061e},
10104 +       {0x0000a10c, 0x07020703},
10105 +       {0x0000a110, 0x07000701},
10106 +       {0x0000a114, 0x00000000},
10107 +       {0x0000a118, 0x00000000},
10108 +       {0x0000a11c, 0x00000000},
10109 +       {0x0000a120, 0x00000000},
10110 +       {0x0000a124, 0x00000000},
10111 +       {0x0000a128, 0x00000000},
10112 +       {0x0000a12c, 0x00000000},
10113 +       {0x0000a130, 0x00000000},
10114 +       {0x0000a134, 0x00000000},
10115 +       {0x0000a138, 0x00000000},
10116 +       {0x0000a13c, 0x00000000},
10117 +       {0x0000a140, 0x001f0000},
10118 +       {0x0000a144, 0x01000101},
10119 +       {0x0000a148, 0x011e011f},
10120 +       {0x0000a14c, 0x011c011d},
10121 +       {0x0000a150, 0x02030204},
10122 +       {0x0000a154, 0x02010202},
10123 +       {0x0000a158, 0x021f0200},
10124 +       {0x0000a15c, 0x0302021e},
10125 +       {0x0000a160, 0x03000301},
10126 +       {0x0000a164, 0x031e031f},
10127 +       {0x0000a168, 0x0402031d},
10128 +       {0x0000a16c, 0x04000401},
10129 +       {0x0000a170, 0x041e041f},
10130 +       {0x0000a174, 0x0502041d},
10131 +       {0x0000a178, 0x05000501},
10132 +       {0x0000a17c, 0x051e051f},
10133 +       {0x0000a180, 0x06010602},
10134 +       {0x0000a184, 0x061f0600},
10135 +       {0x0000a188, 0x061d061e},
10136 +       {0x0000a18c, 0x07020703},
10137 +       {0x0000a190, 0x07000701},
10138 +       {0x0000a194, 0x00000000},
10139 +       {0x0000a198, 0x00000000},
10140 +       {0x0000a19c, 0x00000000},
10141 +       {0x0000a1a0, 0x00000000},
10142 +       {0x0000a1a4, 0x00000000},
10143 +       {0x0000a1a8, 0x00000000},
10144 +       {0x0000a1ac, 0x00000000},
10145 +       {0x0000a1b0, 0x00000000},
10146 +       {0x0000a1b4, 0x00000000},
10147 +       {0x0000a1b8, 0x00000000},
10148 +       {0x0000a1bc, 0x00000000},
10149 +       {0x0000a1c0, 0x00000000},
10150 +       {0x0000a1c4, 0x00000000},
10151 +       {0x0000a1c8, 0x00000000},
10152 +       {0x0000a1cc, 0x00000000},
10153 +       {0x0000a1d0, 0x00000000},
10154 +       {0x0000a1d4, 0x00000000},
10155 +       {0x0000a1d8, 0x00000000},
10156 +       {0x0000a1dc, 0x00000000},
10157 +       {0x0000a1e0, 0x00000000},
10158 +       {0x0000a1e4, 0x00000000},
10159 +       {0x0000a1e8, 0x00000000},
10160 +       {0x0000a1ec, 0x00000000},
10161 +       {0x0000a1f0, 0x00000396},
10162 +       {0x0000a1f4, 0x00000396},
10163 +       {0x0000a1f8, 0x00000396},
10164 +       {0x0000a1fc, 0x00000196},
10165 +       {0x0000b000, 0x00010000},
10166 +       {0x0000b004, 0x00030002},
10167 +       {0x0000b008, 0x00050004},
10168 +       {0x0000b00c, 0x00810080},
10169 +       {0x0000b010, 0x00830082},
10170 +       {0x0000b014, 0x01810180},
10171 +       {0x0000b018, 0x01830182},
10172 +       {0x0000b01c, 0x01850184},
10173 +       {0x0000b020, 0x02810280},
10174 +       {0x0000b024, 0x02830282},
10175 +       {0x0000b028, 0x02850284},
10176 +       {0x0000b02c, 0x02890288},
10177 +       {0x0000b030, 0x028b028a},
10178 +       {0x0000b034, 0x0388028c},
10179 +       {0x0000b038, 0x038a0389},
10180 +       {0x0000b03c, 0x038c038b},
10181 +       {0x0000b040, 0x0390038d},
10182 +       {0x0000b044, 0x03920391},
10183 +       {0x0000b048, 0x03940393},
10184 +       {0x0000b04c, 0x03960395},
10185 +       {0x0000b050, 0x00000000},
10186 +       {0x0000b054, 0x00000000},
10187 +       {0x0000b058, 0x00000000},
10188 +       {0x0000b05c, 0x00000000},
10189 +       {0x0000b060, 0x00000000},
10190 +       {0x0000b064, 0x00000000},
10191 +       {0x0000b068, 0x00000000},
10192 +       {0x0000b06c, 0x00000000},
10193 +       {0x0000b070, 0x00000000},
10194 +       {0x0000b074, 0x00000000},
10195 +       {0x0000b078, 0x00000000},
10196 +       {0x0000b07c, 0x00000000},
10197 +       {0x0000b080, 0x23232323},
10198 +       {0x0000b084, 0x21232323},
10199 +       {0x0000b088, 0x19191c1e},
10200 +       {0x0000b08c, 0x12141417},
10201 +       {0x0000b090, 0x07070e0e},
10202 +       {0x0000b094, 0x03030305},
10203 +       {0x0000b098, 0x00000003},
10204 +       {0x0000b09c, 0x00000000},
10205 +       {0x0000b0a0, 0x00000000},
10206 +       {0x0000b0a4, 0x00000000},
10207 +       {0x0000b0a8, 0x00000000},
10208 +       {0x0000b0ac, 0x00000000},
10209 +       {0x0000b0b0, 0x00000000},
10210 +       {0x0000b0b4, 0x00000000},
10211 +       {0x0000b0b8, 0x00000000},
10212 +       {0x0000b0bc, 0x00000000},
10213 +       {0x0000b0c0, 0x003f0020},
10214 +       {0x0000b0c4, 0x00400041},
10215 +       {0x0000b0c8, 0x0140005f},
10216 +       {0x0000b0cc, 0x0160015f},
10217 +       {0x0000b0d0, 0x017e017f},
10218 +       {0x0000b0d4, 0x02410242},
10219 +       {0x0000b0d8, 0x025f0240},
10220 +       {0x0000b0dc, 0x027f0260},
10221 +       {0x0000b0e0, 0x0341027e},
10222 +       {0x0000b0e4, 0x035f0340},
10223 +       {0x0000b0e8, 0x037f0360},
10224 +       {0x0000b0ec, 0x04400441},
10225 +       {0x0000b0f0, 0x0460045f},
10226 +       {0x0000b0f4, 0x0541047f},
10227 +       {0x0000b0f8, 0x055f0540},
10228 +       {0x0000b0fc, 0x057f0560},
10229 +       {0x0000b100, 0x06400641},
10230 +       {0x0000b104, 0x0660065f},
10231 +       {0x0000b108, 0x067e067f},
10232 +       {0x0000b10c, 0x07410742},
10233 +       {0x0000b110, 0x075f0740},
10234 +       {0x0000b114, 0x077f0760},
10235 +       {0x0000b118, 0x07800781},
10236 +       {0x0000b11c, 0x07a0079f},
10237 +       {0x0000b120, 0x07c107bf},
10238 +       {0x0000b124, 0x000007c0},
10239 +       {0x0000b128, 0x00000000},
10240 +       {0x0000b12c, 0x00000000},
10241 +       {0x0000b130, 0x00000000},
10242 +       {0x0000b134, 0x00000000},
10243 +       {0x0000b138, 0x00000000},
10244 +       {0x0000b13c, 0x00000000},
10245 +       {0x0000b140, 0x003f0020},
10246 +       {0x0000b144, 0x00400041},
10247 +       {0x0000b148, 0x0140005f},
10248 +       {0x0000b14c, 0x0160015f},
10249 +       {0x0000b150, 0x017e017f},
10250 +       {0x0000b154, 0x02410242},
10251 +       {0x0000b158, 0x025f0240},
10252 +       {0x0000b15c, 0x027f0260},
10253 +       {0x0000b160, 0x0341027e},
10254 +       {0x0000b164, 0x035f0340},
10255 +       {0x0000b168, 0x037f0360},
10256 +       {0x0000b16c, 0x04400441},
10257 +       {0x0000b170, 0x0460045f},
10258 +       {0x0000b174, 0x0541047f},
10259 +       {0x0000b178, 0x055f0540},
10260 +       {0x0000b17c, 0x057f0560},
10261 +       {0x0000b180, 0x06400641},
10262 +       {0x0000b184, 0x0660065f},
10263 +       {0x0000b188, 0x067e067f},
10264 +       {0x0000b18c, 0x07410742},
10265 +       {0x0000b190, 0x075f0740},
10266 +       {0x0000b194, 0x077f0760},
10267 +       {0x0000b198, 0x07800781},
10268 +       {0x0000b19c, 0x07a0079f},
10269 +       {0x0000b1a0, 0x07c107bf},
10270 +       {0x0000b1a4, 0x000007c0},
10271 +       {0x0000b1a8, 0x00000000},
10272 +       {0x0000b1ac, 0x00000000},
10273 +       {0x0000b1b0, 0x00000000},
10274 +       {0x0000b1b4, 0x00000000},
10275 +       {0x0000b1b8, 0x00000000},
10276 +       {0x0000b1bc, 0x00000000},
10277 +       {0x0000b1c0, 0x00000000},
10278 +       {0x0000b1c4, 0x00000000},
10279 +       {0x0000b1c8, 0x00000000},
10280 +       {0x0000b1cc, 0x00000000},
10281 +       {0x0000b1d0, 0x00000000},
10282 +       {0x0000b1d4, 0x00000000},
10283 +       {0x0000b1d8, 0x00000000},
10284 +       {0x0000b1dc, 0x00000000},
10285 +       {0x0000b1e0, 0x00000000},
10286 +       {0x0000b1e4, 0x00000000},
10287 +       {0x0000b1e8, 0x00000000},
10288 +       {0x0000b1ec, 0x00000000},
10289 +       {0x0000b1f0, 0x00000396},
10290 +       {0x0000b1f4, 0x00000396},
10291 +       {0x0000b1f8, 0x00000396},
10292 +       {0x0000b1fc, 0x00000196},
10293  };
10294
10295  static const u32 ar9580_1p0_baseband_postamble[][5] = {
10296         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10297         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
10298 +       {0x00009814, 0x3280c00a, 0x3280c00a, 0x3280c00a, 0x3280c00a},
10299 +       {0x00009818, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10300         {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
10301         {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
10302         {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
10303 @@ -956,7 +1169,7 @@ static const u32 ar9580_1p0_baseband_pos
10304         {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
10305         {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
10306         {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
10307 -       {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
10308 +       {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982},
10309         {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
10310         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10311         {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
10312 @@ -994,4 +1207,13 @@ static const u32 ar9580_1p0_pcie_phy_pll
10313         {0x00004044, 0x00000000},
10314  };
10315
10316 +static const u32 ar9580_1p0_baseband_postamble_dfs_channel[][3] = {
10317 +       /* Addr      5G          2G        */
10318 +       {0x00009814, 0x3400c00f, 0x3400c00f},
10319 +       {0x00009824, 0x5ac668d0, 0x5ac668d0},
10320 +       {0x00009828, 0x06903080, 0x06903080},
10321 +       {0x00009e0c, 0x6d4000e2, 0x6d4000e2},
10322 +       {0x00009e14, 0x37b9625e, 0x37b9625e},
10323 +};
10324 +
10325  #endif /* INITVALS_9580_1P0_H */
10326 --- a/drivers/net/wireless/ath/ath9k/reg.h
10327 +++ b/drivers/net/wireless/ath/ath9k/reg.h
10328 @@ -809,6 +809,8 @@
10329  #define AR_SREV_REVISION_9462_21       3
10330  #define AR_SREV_VERSION_9565            0x2C0
10331  #define AR_SREV_REVISION_9565_10        0
10332 +#define AR_SREV_REVISION_9565_101       1
10333 +#define AR_SREV_REVISION_9565_11        2
10334  #define AR_SREV_VERSION_9550           0x400
10335
10336  #define AR_SREV_5416(_ah) \
10337 @@ -881,9 +883,6 @@
10338
10339  #define AR_SREV_9330(_ah) \
10340         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9330))
10341 -#define AR_SREV_9330_10(_ah) \
10342 -       (AR_SREV_9330((_ah)) && \
10343 -        ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_10))
10344  #define AR_SREV_9330_11(_ah) \
10345         (AR_SREV_9330((_ah)) && \
10346          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_11))
10347 @@ -927,10 +926,18 @@
10348
10349  #define AR_SREV_9565(_ah) \
10350         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565))
10351 -
10352  #define AR_SREV_9565_10(_ah) \
10353         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
10354          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10))
10355 +#define AR_SREV_9565_101(_ah) \
10356 +       (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
10357 +        ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_101))
10358 +#define AR_SREV_9565_11(_ah) \
10359 +       (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
10360 +        ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_11))
10361 +#define AR_SREV_9565_11_OR_LATER(_ah) \
10362 +       (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
10363 +        ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9565_11))
10364
10365  #define AR_SREV_9550(_ah) \
10366         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550))
10367 --- a/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
10368 +++ b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
10369 @@ -18,6 +18,10 @@
10370  #ifndef INITVALS_9330_1P1_H
10371  #define INITVALS_9330_1P1_H
10372
10373 +#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
10374 +
10375 +#define ar9331_modes_high_power_tx_gain_1p1 ar9331_modes_lowest_ob_db_tx_gain_1p1
10376 +
10377  static const u32 ar9331_1p1_baseband_postamble[][5] = {
10378         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10379         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
10380 @@ -55,7 +59,7 @@ static const u32 ar9331_1p1_baseband_pos
10381         {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10382         {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10383         {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10384 -       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
10385 +       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00058d18, 0x00058d18},
10386         {0x0000a2d0, 0x00071982, 0x00071982, 0x00071982, 0x00071982},
10387         {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
10388         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10389 @@ -252,7 +256,7 @@ static const u32 ar9331_modes_low_ob_db_
10390         {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
10391         {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
10392         {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
10393 -       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
10394 +       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d4, 0x000050d4},
10395         {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
10396         {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
10397         {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
10398 @@ -337,8 +341,6 @@ static const u32 ar9331_modes_low_ob_db_
10399         {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
10400  };
10401
10402 -#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
10403 -
10404  static const u32 ar9331_1p1_xtal_25M[][2] = {
10405         /* Addr      allmodes  */
10406         {0x00007038, 0x000002f8},
10407 @@ -373,17 +375,17 @@ static const u32 ar9331_1p1_radio_core[]
10408         {0x000160b4, 0x92480040},
10409         {0x000160c0, 0x006db6db},
10410         {0x000160c4, 0x0186db60},
10411 -       {0x000160c8, 0x6db4db6c},
10412 +       {0x000160c8, 0x6db6db6c},
10413         {0x000160cc, 0x6de6c300},
10414         {0x000160d0, 0x14500820},
10415         {0x00016100, 0x04cb0001},
10416         {0x00016104, 0xfff80015},
10417         {0x00016108, 0x00080010},
10418         {0x0001610c, 0x00170000},
10419 -       {0x00016140, 0x10800000},
10420 +       {0x00016140, 0x50804000},
10421         {0x00016144, 0x01884080},
10422         {0x00016148, 0x000080c0},
10423 -       {0x00016280, 0x01000015},
10424 +       {0x00016280, 0x01001015},
10425         {0x00016284, 0x14d20000},
10426         {0x00016288, 0x00318000},
10427         {0x0001628c, 0x50000000},
10428 @@ -622,12 +624,12 @@ static const u32 ar9331_1p1_baseband_cor
10429         {0x0000a370, 0x00000000},
10430         {0x0000a390, 0x00000001},
10431         {0x0000a394, 0x00000444},
10432 -       {0x0000a398, 0x001f0e0f},
10433 -       {0x0000a39c, 0x0075393f},
10434 -       {0x0000a3a0, 0xb79f6427},
10435 -       {0x0000a3a4, 0x00000000},
10436 -       {0x0000a3a8, 0xaaaaaaaa},
10437 -       {0x0000a3ac, 0x3c466478},
10438 +       {0x0000a398, 0x00000000},
10439 +       {0x0000a39c, 0x210d0401},
10440 +       {0x0000a3a0, 0xab9a7144},
10441 +       {0x0000a3a4, 0x00000011},
10442 +       {0x0000a3a8, 0x3c3c003d},
10443 +       {0x0000a3ac, 0x30310030},
10444         {0x0000a3c0, 0x20202020},
10445         {0x0000a3c4, 0x22222220},
10446         {0x0000a3c8, 0x20200020},
10447 @@ -686,100 +688,18 @@ static const u32 ar9331_1p1_baseband_cor
10448         {0x0000a7dc, 0x00000001},
10449  };
10450
10451 -static const u32 ar9331_modes_high_power_tx_gain_1p1[][5] = {
10452 +static const u32 ar9331_1p1_mac_postamble[][5] = {
10453         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10454 -       {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
10455 -       {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
10456 -       {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
10457 -       {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
10458 -       {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
10459 -       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
10460 -       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
10461 -       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
10462 -       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
10463 -       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
10464 -       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
10465 -       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
10466 -       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
10467 -       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
10468 -       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
10469 -       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
10470 -       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
10471 -       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2d000a20, 0x2d000a20},
10472 -       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000a22, 0x31000a22},
10473 -       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000a24, 0x35000a24},
10474 -       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000a43, 0x38000a43},
10475 -       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3b000e42, 0x3b000e42},
10476 -       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x3f000e44, 0x3f000e44},
10477 -       {0x0000a544, 0x6502feca, 0x6502feca, 0x42000e64, 0x42000e64},
10478 -       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46000e66, 0x46000e66},
10479 -       {0x0000a54c, 0x7203feca, 0x7203feca, 0x4a000ea6, 0x4a000ea6},
10480 -       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4a000ea6, 0x4a000ea6},
10481 -       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4a000ea6, 0x4a000ea6},
10482 -       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x4a000ea6, 0x4a000ea6},
10483 -       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x4a000ea6, 0x4a000ea6},
10484 -       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x4a000ea6, 0x4a000ea6},
10485 -       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x4a000ea6, 0x4a000ea6},
10486 -       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
10487 -       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
10488 -       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
10489 -       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
10490 -       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
10491 -       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
10492 -       {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
10493 -       {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
10494 -       {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
10495 -       {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
10496 -       {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
10497 -       {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
10498 -       {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
10499 -       {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
10500 -       {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
10501 -       {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
10502 -       {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
10503 -       {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
10504 -       {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
10505 -       {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
10506 -       {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
10507 -       {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
10508 -       {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
10509 -       {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
10510 -       {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
10511 -       {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
10512 -       {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
10513 -       {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
10514 -       {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
10515 -       {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
10516 -       {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
10517 -       {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
10518 -       {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
10519 -       {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
10520 -       {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
10521 -       {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
10522 -       {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
10523 -       {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
10524 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10525 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10526 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10527 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10528 -       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10529 -       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
10530 -       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
10531 -       {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
10532 -       {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
10533 -       {0x0000a624, 0x03010a03, 0x03010a03, 0x03010a03, 0x03010a03},
10534 -       {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
10535 -       {0x0000a62c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
10536 -       {0x0000a630, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
10537 -       {0x0000a634, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
10538 -       {0x0000a638, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
10539 -       {0x0000a63c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
10540 -       {0x00016044, 0x034922db, 0x034922db, 0x034922db, 0x034922db},
10541 -       {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
10542 +       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
10543 +       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
10544 +       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
10545 +       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
10546 +       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
10547 +       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
10548 +       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
10549 +       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
10550  };
10551
10552 -#define ar9331_1p1_mac_postamble ar9300_2p2_mac_postamble
10553 -
10554  static const u32 ar9331_1p1_soc_preamble[][2] = {
10555         /* Addr      allmodes  */
10556         {0x00007020, 0x00000000},
10557 --- a/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
10558 +++ b/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
10559 @@ -18,6 +18,28 @@
10560  #ifndef INITVALS_9330_1P2_H
10561  #define INITVALS_9330_1P2_H
10562
10563 +#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
10564 +
10565 +#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
10566 +
10567 +#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
10568 +
10569 +#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484
10570 +
10571 +#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M
10572 +
10573 +#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M
10574 +
10575 +#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble
10576 +
10577 +#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble
10578 +
10579 +#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble
10580 +
10581 +#define ar9331_1p2_mac_core ar9331_1p1_mac_core
10582 +
10583 +#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1
10584 +
10585  static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = {
10586         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10587         {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
10588 @@ -103,57 +125,6 @@ static const u32 ar9331_modes_high_ob_db
10589         {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
10590  };
10591
10592 -#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
10593 -
10594 -#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_power_tx_gain_1p2
10595 -
10596 -#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_low_ob_db_tx_gain_1p2
10597 -
10598 -static const u32 ar9331_1p2_baseband_postamble[][5] = {
10599 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10600 -       {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
10601 -       {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
10602 -       {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
10603 -       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
10604 -       {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
10605 -       {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
10606 -       {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
10607 -       {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
10608 -       {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
10609 -       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
10610 -       {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
10611 -       {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
10612 -       {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10613 -       {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
10614 -       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
10615 -       {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
10616 -       {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
10617 -       {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
10618 -       {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
10619 -       {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
10620 -       {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
10621 -       {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
10622 -       {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
10623 -       {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
10624 -       {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
10625 -       {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
10626 -       {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
10627 -       {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
10628 -       {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
10629 -       {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
10630 -       {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
10631 -       {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
10632 -       {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10633 -       {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10634 -       {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10635 -       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
10636 -       {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
10637 -       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
10638 -       {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10639 -       {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
10640 -       {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10641 -};
10642 -
10643  static const u32 ar9331_1p2_radio_core[][2] = {
10644         /* Addr      allmodes  */
10645         {0x00016000, 0x36db6db6},
10646 @@ -219,24 +190,318 @@ static const u32 ar9331_1p2_radio_core[]
10647         {0x000163d4, 0x00000000},
10648  };
10649
10650 -#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484
10651 -
10652 -#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M
10653 -
10654 -#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M
10655 -
10656 -#define ar9331_1p2_baseband_core ar9331_1p1_baseband_core
10657 -
10658 -#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble
10659 -
10660 -#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble
10661 -
10662 -#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble
10663 -
10664 -#define ar9331_1p2_mac_core ar9331_1p1_mac_core
10665 +static const u32 ar9331_1p2_baseband_core[][2] = {
10666 +       /* Addr      allmodes  */
10667 +       {0x00009800, 0xafe68e30},
10668 +       {0x00009804, 0xfd14e000},
10669 +       {0x00009808, 0x9c0a8f6b},
10670 +       {0x0000980c, 0x04800000},
10671 +       {0x00009814, 0x9280c00a},
10672 +       {0x00009818, 0x00000000},
10673 +       {0x0000981c, 0x00020028},
10674 +       {0x00009834, 0x5f3ca3de},
10675 +       {0x00009838, 0x0108ecff},
10676 +       {0x0000983c, 0x14750600},
10677 +       {0x00009880, 0x201fff00},
10678 +       {0x00009884, 0x00001042},
10679 +       {0x000098a4, 0x00200400},
10680 +       {0x000098b0, 0x32840bbe},
10681 +       {0x000098d0, 0x004b6a8e},
10682 +       {0x000098d4, 0x00000820},
10683 +       {0x000098dc, 0x00000000},
10684 +       {0x000098f0, 0x00000000},
10685 +       {0x000098f4, 0x00000000},
10686 +       {0x00009c04, 0x00000000},
10687 +       {0x00009c08, 0x03200000},
10688 +       {0x00009c0c, 0x00000000},
10689 +       {0x00009c10, 0x00000000},
10690 +       {0x00009c14, 0x00046384},
10691 +       {0x00009c18, 0x05b6b440},
10692 +       {0x00009c1c, 0x00b6b440},
10693 +       {0x00009d00, 0xc080a333},
10694 +       {0x00009d04, 0x40206c10},
10695 +       {0x00009d08, 0x009c4060},
10696 +       {0x00009d0c, 0x1883800a},
10697 +       {0x00009d10, 0x01834061},
10698 +       {0x00009d14, 0x00c00400},
10699 +       {0x00009d18, 0x00000000},
10700 +       {0x00009e08, 0x0038233c},
10701 +       {0x00009e24, 0x9927b515},
10702 +       {0x00009e28, 0x12ef0200},
10703 +       {0x00009e30, 0x06336f77},
10704 +       {0x00009e34, 0x6af6532f},
10705 +       {0x00009e38, 0x0cc80c00},
10706 +       {0x00009e40, 0x0d261820},
10707 +       {0x00009e4c, 0x00001004},
10708 +       {0x00009e50, 0x00ff03f1},
10709 +       {0x00009fc0, 0x803e4788},
10710 +       {0x00009fc4, 0x0001efb5},
10711 +       {0x00009fcc, 0x40000014},
10712 +       {0x0000a20c, 0x00000000},
10713 +       {0x0000a220, 0x00000000},
10714 +       {0x0000a224, 0x00000000},
10715 +       {0x0000a228, 0x10002310},
10716 +       {0x0000a23c, 0x00000000},
10717 +       {0x0000a244, 0x0c000000},
10718 +       {0x0000a2a0, 0x00000001},
10719 +       {0x0000a2c0, 0x00000001},
10720 +       {0x0000a2c8, 0x00000000},
10721 +       {0x0000a2cc, 0x18c43433},
10722 +       {0x0000a2d4, 0x00000000},
10723 +       {0x0000a2dc, 0x00000000},
10724 +       {0x0000a2e0, 0x00000000},
10725 +       {0x0000a2e4, 0x00000000},
10726 +       {0x0000a2e8, 0x00000000},
10727 +       {0x0000a2ec, 0x00000000},
10728 +       {0x0000a2f0, 0x00000000},
10729 +       {0x0000a2f4, 0x00000000},
10730 +       {0x0000a2f8, 0x00000000},
10731 +       {0x0000a344, 0x00000000},
10732 +       {0x0000a34c, 0x00000000},
10733 +       {0x0000a350, 0x0000a000},
10734 +       {0x0000a364, 0x00000000},
10735 +       {0x0000a370, 0x00000000},
10736 +       {0x0000a390, 0x00000001},
10737 +       {0x0000a394, 0x00000444},
10738 +       {0x0000a398, 0x001f0e0f},
10739 +       {0x0000a39c, 0x0075393f},
10740 +       {0x0000a3a0, 0xb79f6427},
10741 +       {0x0000a3a4, 0x00000000},
10742 +       {0x0000a3a8, 0xaaaaaaaa},
10743 +       {0x0000a3ac, 0x3c466478},
10744 +       {0x0000a3c0, 0x20202020},
10745 +       {0x0000a3c4, 0x22222220},
10746 +       {0x0000a3c8, 0x20200020},
10747 +       {0x0000a3cc, 0x20202020},
10748 +       {0x0000a3d0, 0x20202020},
10749 +       {0x0000a3d4, 0x20202020},
10750 +       {0x0000a3d8, 0x20202020},
10751 +       {0x0000a3dc, 0x20202020},
10752 +       {0x0000a3e0, 0x20202020},
10753 +       {0x0000a3e4, 0x20202020},
10754 +       {0x0000a3e8, 0x20202020},
10755 +       {0x0000a3ec, 0x20202020},
10756 +       {0x0000a3f0, 0x00000000},
10757 +       {0x0000a3f4, 0x00000006},
10758 +       {0x0000a3f8, 0x0cdbd380},
10759 +       {0x0000a3fc, 0x000f0f01},
10760 +       {0x0000a400, 0x8fa91f01},
10761 +       {0x0000a404, 0x00000000},
10762 +       {0x0000a408, 0x0e79e5c6},
10763 +       {0x0000a40c, 0x00820820},
10764 +       {0x0000a414, 0x1ce739ce},
10765 +       {0x0000a418, 0x2d001dce},
10766 +       {0x0000a41c, 0x1ce739ce},
10767 +       {0x0000a420, 0x000001ce},
10768 +       {0x0000a424, 0x1ce739ce},
10769 +       {0x0000a428, 0x000001ce},
10770 +       {0x0000a42c, 0x1ce739ce},
10771 +       {0x0000a430, 0x1ce739ce},
10772 +       {0x0000a434, 0x00000000},
10773 +       {0x0000a438, 0x00001801},
10774 +       {0x0000a43c, 0x00000000},
10775 +       {0x0000a440, 0x00000000},
10776 +       {0x0000a444, 0x00000000},
10777 +       {0x0000a448, 0x04000000},
10778 +       {0x0000a44c, 0x00000001},
10779 +       {0x0000a450, 0x00010000},
10780 +       {0x0000a458, 0x00000000},
10781 +       {0x0000a640, 0x00000000},
10782 +       {0x0000a644, 0x3fad9d74},
10783 +       {0x0000a648, 0x0048060a},
10784 +       {0x0000a64c, 0x00003c37},
10785 +       {0x0000a670, 0x03020100},
10786 +       {0x0000a674, 0x09080504},
10787 +       {0x0000a678, 0x0d0c0b0a},
10788 +       {0x0000a67c, 0x13121110},
10789 +       {0x0000a680, 0x31301514},
10790 +       {0x0000a684, 0x35343332},
10791 +       {0x0000a688, 0x00000036},
10792 +       {0x0000a690, 0x00000838},
10793 +       {0x0000a7c0, 0x00000000},
10794 +       {0x0000a7c4, 0xfffffffc},
10795 +       {0x0000a7c8, 0x00000000},
10796 +       {0x0000a7cc, 0x00000000},
10797 +       {0x0000a7d0, 0x00000000},
10798 +       {0x0000a7d4, 0x00000004},
10799 +       {0x0000a7dc, 0x00000001},
10800 +};
10801
10802 -#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1
10803 +static const u32 ar9331_1p2_baseband_postamble[][5] = {
10804 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10805 +       {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
10806 +       {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
10807 +       {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
10808 +       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
10809 +       {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
10810 +       {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
10811 +       {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
10812 +       {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
10813 +       {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
10814 +       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
10815 +       {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
10816 +       {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
10817 +       {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10818 +       {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
10819 +       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
10820 +       {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
10821 +       {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
10822 +       {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
10823 +       {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
10824 +       {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
10825 +       {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
10826 +       {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
10827 +       {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
10828 +       {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
10829 +       {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
10830 +       {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
10831 +       {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
10832 +       {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
10833 +       {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
10834 +       {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
10835 +       {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
10836 +       {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
10837 +       {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10838 +       {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10839 +       {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10840 +       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
10841 +       {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
10842 +       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
10843 +       {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10844 +       {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
10845 +       {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10846 +};
10847
10848 -#define ar9331_common_rx_gain_1p2 ar9485_common_rx_gain_1_1
10849 +static const u32 ar9331_common_rx_gain_1p2[][2] = {
10850 +       /* Addr      allmodes  */
10851 +       {0x0000a000, 0x00010000},
10852 +       {0x0000a004, 0x00030002},
10853 +       {0x0000a008, 0x00050004},
10854 +       {0x0000a00c, 0x00810080},
10855 +       {0x0000a010, 0x01800082},
10856 +       {0x0000a014, 0x01820181},
10857 +       {0x0000a018, 0x01840183},
10858 +       {0x0000a01c, 0x01880185},
10859 +       {0x0000a020, 0x018a0189},
10860 +       {0x0000a024, 0x02850284},
10861 +       {0x0000a028, 0x02890288},
10862 +       {0x0000a02c, 0x03850384},
10863 +       {0x0000a030, 0x03890388},
10864 +       {0x0000a034, 0x038b038a},
10865 +       {0x0000a038, 0x038d038c},
10866 +       {0x0000a03c, 0x03910390},
10867 +       {0x0000a040, 0x03930392},
10868 +       {0x0000a044, 0x03950394},
10869 +       {0x0000a048, 0x00000396},
10870 +       {0x0000a04c, 0x00000000},
10871 +       {0x0000a050, 0x00000000},
10872 +       {0x0000a054, 0x00000000},
10873 +       {0x0000a058, 0x00000000},
10874 +       {0x0000a05c, 0x00000000},
10875 +       {0x0000a060, 0x00000000},
10876 +       {0x0000a064, 0x00000000},
10877 +       {0x0000a068, 0x00000000},
10878 +       {0x0000a06c, 0x00000000},
10879 +       {0x0000a070, 0x00000000},
10880 +       {0x0000a074, 0x00000000},
10881 +       {0x0000a078, 0x00000000},
10882 +       {0x0000a07c, 0x00000000},
10883 +       {0x0000a080, 0x28282828},
10884 +       {0x0000a084, 0x28282828},
10885 +       {0x0000a088, 0x28282828},
10886 +       {0x0000a08c, 0x28282828},
10887 +       {0x0000a090, 0x28282828},
10888 +       {0x0000a094, 0x21212128},
10889 +       {0x0000a098, 0x171c1c1c},
10890 +       {0x0000a09c, 0x02020212},
10891 +       {0x0000a0a0, 0x00000202},
10892 +       {0x0000a0a4, 0x00000000},
10893 +       {0x0000a0a8, 0x00000000},
10894 +       {0x0000a0ac, 0x00000000},
10895 +       {0x0000a0b0, 0x00000000},
10896 +       {0x0000a0b4, 0x00000000},
10897 +       {0x0000a0b8, 0x00000000},
10898 +       {0x0000a0bc, 0x00000000},
10899 +       {0x0000a0c0, 0x001f0000},
10900 +       {0x0000a0c4, 0x111f1100},
10901 +       {0x0000a0c8, 0x111d111e},
10902 +       {0x0000a0cc, 0x111b111c},
10903 +       {0x0000a0d0, 0x22032204},
10904 +       {0x0000a0d4, 0x22012202},
10905 +       {0x0000a0d8, 0x221f2200},
10906 +       {0x0000a0dc, 0x221d221e},
10907 +       {0x0000a0e0, 0x33013302},
10908 +       {0x0000a0e4, 0x331f3300},
10909 +       {0x0000a0e8, 0x4402331e},
10910 +       {0x0000a0ec, 0x44004401},
10911 +       {0x0000a0f0, 0x441e441f},
10912 +       {0x0000a0f4, 0x55015502},
10913 +       {0x0000a0f8, 0x551f5500},
10914 +       {0x0000a0fc, 0x6602551e},
10915 +       {0x0000a100, 0x66006601},
10916 +       {0x0000a104, 0x661e661f},
10917 +       {0x0000a108, 0x7703661d},
10918 +       {0x0000a10c, 0x77017702},
10919 +       {0x0000a110, 0x00007700},
10920 +       {0x0000a114, 0x00000000},
10921 +       {0x0000a118, 0x00000000},
10922 +       {0x0000a11c, 0x00000000},
10923 +       {0x0000a120, 0x00000000},
10924 +       {0x0000a124, 0x00000000},
10925 +       {0x0000a128, 0x00000000},
10926 +       {0x0000a12c, 0x00000000},
10927 +       {0x0000a130, 0x00000000},
10928 +       {0x0000a134, 0x00000000},
10929 +       {0x0000a138, 0x00000000},
10930 +       {0x0000a13c, 0x00000000},
10931 +       {0x0000a140, 0x001f0000},
10932 +       {0x0000a144, 0x111f1100},
10933 +       {0x0000a148, 0x111d111e},
10934 +       {0x0000a14c, 0x111b111c},
10935 +       {0x0000a150, 0x22032204},
10936 +       {0x0000a154, 0x22012202},
10937 +       {0x0000a158, 0x221f2200},
10938 +       {0x0000a15c, 0x221d221e},
10939 +       {0x0000a160, 0x33013302},
10940 +       {0x0000a164, 0x331f3300},
10941 +       {0x0000a168, 0x4402331e},
10942 +       {0x0000a16c, 0x44004401},
10943 +       {0x0000a170, 0x441e441f},
10944 +       {0x0000a174, 0x55015502},
10945 +       {0x0000a178, 0x551f5500},
10946 +       {0x0000a17c, 0x6602551e},
10947 +       {0x0000a180, 0x66006601},
10948 +       {0x0000a184, 0x661e661f},
10949 +       {0x0000a188, 0x7703661d},
10950 +       {0x0000a18c, 0x77017702},
10951 +       {0x0000a190, 0x00007700},
10952 +       {0x0000a194, 0x00000000},
10953 +       {0x0000a198, 0x00000000},
10954 +       {0x0000a19c, 0x00000000},
10955 +       {0x0000a1a0, 0x00000000},
10956 +       {0x0000a1a4, 0x00000000},
10957 +       {0x0000a1a8, 0x00000000},
10958 +       {0x0000a1ac, 0x00000000},
10959 +       {0x0000a1b0, 0x00000000},
10960 +       {0x0000a1b4, 0x00000000},
10961 +       {0x0000a1b8, 0x00000000},
10962 +       {0x0000a1bc, 0x00000000},
10963 +       {0x0000a1c0, 0x00000000},
10964 +       {0x0000a1c4, 0x00000000},
10965 +       {0x0000a1c8, 0x00000000},
10966 +       {0x0000a1cc, 0x00000000},
10967 +       {0x0000a1d0, 0x00000000},
10968 +       {0x0000a1d4, 0x00000000},
10969 +       {0x0000a1d8, 0x00000000},
10970 +       {0x0000a1dc, 0x00000000},
10971 +       {0x0000a1e0, 0x00000000},
10972 +       {0x0000a1e4, 0x00000000},
10973 +       {0x0000a1e8, 0x00000000},
10974 +       {0x0000a1ec, 0x00000000},
10975 +       {0x0000a1f0, 0x00000396},
10976 +       {0x0000a1f4, 0x00000396},
10977 +       {0x0000a1f8, 0x00000396},
10978 +       {0x0000a1fc, 0x00000296},
10979 +};
10980
10981  #endif /* INITVALS_9330_1P2_H */
10982 --- a/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
10983 +++ b/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
10984 @@ -20,6 +20,14 @@
10985
10986  /* AR955X 1.0 */
10987
10988 +#define ar955x_1p0_soc_postamble ar9300_2p2_soc_postamble
10989 +
10990 +#define ar955x_1p0_common_rx_gain_table ar9300Common_rx_gain_table_2p2
10991 +
10992 +#define ar955x_1p0_common_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
10993 +
10994 +#define ar955x_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
10995 +
10996  static const u32 ar955x_1p0_radio_postamble[][5] = {
10997         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10998         {0x00016098, 0xd2dd5554, 0xd2dd5554, 0xd28b3330, 0xd28b3330},
10999 @@ -37,13 +45,6 @@ static const u32 ar955x_1p0_radio_postam
11000         {0x00016940, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
11001  };
11002
11003 -static const u32 ar955x_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
11004 -       /* Addr      allmodes  */
11005 -       {0x0000a398, 0x00000000},
11006 -       {0x0000a39c, 0x6f7f0301},
11007 -       {0x0000a3a0, 0xca9228ee},
11008 -};
11009 -
11010  static const u32 ar955x_1p0_baseband_postamble[][5] = {
11011         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11012         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
11013 @@ -473,266 +474,6 @@ static const u32 ar955x_1p0_mac_core[][2
11014         {0x000083d0, 0x8c7901ff},
11015  };
11016
11017 -static const u32 ar955x_1p0_common_rx_gain_table[][2] = {
11018 -       /* Addr      allmodes  */
11019 -       {0x0000a000, 0x00010000},
11020 -       {0x0000a004, 0x00030002},
11021 -       {0x0000a008, 0x00050004},
11022 -       {0x0000a00c, 0x00810080},
11023 -       {0x0000a010, 0x00830082},
11024 -       {0x0000a014, 0x01810180},
11025 -       {0x0000a018, 0x01830182},
11026 -       {0x0000a01c, 0x01850184},
11027 -       {0x0000a020, 0x01890188},
11028 -       {0x0000a024, 0x018b018a},
11029 -       {0x0000a028, 0x018d018c},
11030 -       {0x0000a02c, 0x01910190},
11031 -       {0x0000a030, 0x01930192},
11032 -       {0x0000a034, 0x01950194},
11033 -       {0x0000a038, 0x038a0196},
11034 -       {0x0000a03c, 0x038c038b},
11035 -       {0x0000a040, 0x0390038d},
11036 -       {0x0000a044, 0x03920391},
11037 -       {0x0000a048, 0x03940393},
11038 -       {0x0000a04c, 0x03960395},
11039 -       {0x0000a050, 0x00000000},
11040 -       {0x0000a054, 0x00000000},
11041 -       {0x0000a058, 0x00000000},
11042 -       {0x0000a05c, 0x00000000},
11043 -       {0x0000a060, 0x00000000},
11044 -       {0x0000a064, 0x00000000},
11045 -       {0x0000a068, 0x00000000},
11046 -       {0x0000a06c, 0x00000000},
11047 -       {0x0000a070, 0x00000000},
11048 -       {0x0000a074, 0x00000000},
11049 -       {0x0000a078, 0x00000000},
11050 -       {0x0000a07c, 0x00000000},
11051 -       {0x0000a080, 0x22222229},
11052 -       {0x0000a084, 0x1d1d1d1d},
11053 -       {0x0000a088, 0x1d1d1d1d},
11054 -       {0x0000a08c, 0x1d1d1d1d},
11055 -       {0x0000a090, 0x171d1d1d},
11056 -       {0x0000a094, 0x11111717},
11057 -       {0x0000a098, 0x00030311},
11058 -       {0x0000a09c, 0x00000000},
11059 -       {0x0000a0a0, 0x00000000},
11060 -       {0x0000a0a4, 0x00000000},
11061 -       {0x0000a0a8, 0x00000000},
11062 -       {0x0000a0ac, 0x00000000},
11063 -       {0x0000a0b0, 0x00000000},
11064 -       {0x0000a0b4, 0x00000000},
11065 -       {0x0000a0b8, 0x00000000},
11066 -       {0x0000a0bc, 0x00000000},
11067 -       {0x0000a0c0, 0x001f0000},
11068 -       {0x0000a0c4, 0x01000101},
11069 -       {0x0000a0c8, 0x011e011f},
11070 -       {0x0000a0cc, 0x011c011d},
11071 -       {0x0000a0d0, 0x02030204},
11072 -       {0x0000a0d4, 0x02010202},
11073 -       {0x0000a0d8, 0x021f0200},
11074 -       {0x0000a0dc, 0x0302021e},
11075 -       {0x0000a0e0, 0x03000301},
11076 -       {0x0000a0e4, 0x031e031f},
11077 -       {0x0000a0e8, 0x0402031d},
11078 -       {0x0000a0ec, 0x04000401},
11079 -       {0x0000a0f0, 0x041e041f},
11080 -       {0x0000a0f4, 0x0502041d},
11081 -       {0x0000a0f8, 0x05000501},
11082 -       {0x0000a0fc, 0x051e051f},
11083 -       {0x0000a100, 0x06010602},
11084 -       {0x0000a104, 0x061f0600},
11085 -       {0x0000a108, 0x061d061e},
11086 -       {0x0000a10c, 0x07020703},
11087 -       {0x0000a110, 0x07000701},
11088 -       {0x0000a114, 0x00000000},
11089 -       {0x0000a118, 0x00000000},
11090 -       {0x0000a11c, 0x00000000},
11091 -       {0x0000a120, 0x00000000},
11092 -       {0x0000a124, 0x00000000},
11093 -       {0x0000a128, 0x00000000},
11094 -       {0x0000a12c, 0x00000000},
11095 -       {0x0000a130, 0x00000000},
11096 -       {0x0000a134, 0x00000000},
11097 -       {0x0000a138, 0x00000000},
11098 -       {0x0000a13c, 0x00000000},
11099 -       {0x0000a140, 0x001f0000},
11100 -       {0x0000a144, 0x01000101},
11101 -       {0x0000a148, 0x011e011f},
11102 -       {0x0000a14c, 0x011c011d},
11103 -       {0x0000a150, 0x02030204},
11104 -       {0x0000a154, 0x02010202},
11105 -       {0x0000a158, 0x021f0200},
11106 -       {0x0000a15c, 0x0302021e},
11107 -       {0x0000a160, 0x03000301},
11108 -       {0x0000a164, 0x031e031f},
11109 -       {0x0000a168, 0x0402031d},
11110 -       {0x0000a16c, 0x04000401},
11111 -       {0x0000a170, 0x041e041f},
11112 -       {0x0000a174, 0x0502041d},
11113 -       {0x0000a178, 0x05000501},
11114 -       {0x0000a17c, 0x051e051f},
11115 -       {0x0000a180, 0x06010602},
11116 -       {0x0000a184, 0x061f0600},
11117 -       {0x0000a188, 0x061d061e},
11118 -       {0x0000a18c, 0x07020703},
11119 -       {0x0000a190, 0x07000701},
11120 -       {0x0000a194, 0x00000000},
11121 -       {0x0000a198, 0x00000000},
11122 -       {0x0000a19c, 0x00000000},
11123 -       {0x0000a1a0, 0x00000000},
11124 -       {0x0000a1a4, 0x00000000},
11125 -       {0x0000a1a8, 0x00000000},
11126 -       {0x0000a1ac, 0x00000000},
11127 -       {0x0000a1b0, 0x00000000},
11128 -       {0x0000a1b4, 0x00000000},
11129 -       {0x0000a1b8, 0x00000000},
11130 -       {0x0000a1bc, 0x00000000},
11131 -       {0x0000a1c0, 0x00000000},
11132 -       {0x0000a1c4, 0x00000000},
11133 -       {0x0000a1c8, 0x00000000},
11134 -       {0x0000a1cc, 0x00000000},
11135 -       {0x0000a1d0, 0x00000000},
11136 -       {0x0000a1d4, 0x00000000},
11137 -       {0x0000a1d8, 0x00000000},
11138 -       {0x0000a1dc, 0x00000000},
11139 -       {0x0000a1e0, 0x00000000},
11140 -       {0x0000a1e4, 0x00000000},
11141 -       {0x0000a1e8, 0x00000000},
11142 -       {0x0000a1ec, 0x00000000},
11143 -       {0x0000a1f0, 0x00000396},
11144 -       {0x0000a1f4, 0x00000396},
11145 -       {0x0000a1f8, 0x00000396},
11146 -       {0x0000a1fc, 0x00000196},
11147 -       {0x0000b000, 0x00010000},
11148 -       {0x0000b004, 0x00030002},
11149 -       {0x0000b008, 0x00050004},
11150 -       {0x0000b00c, 0x00810080},
11151 -       {0x0000b010, 0x00830082},
11152 -       {0x0000b014, 0x01810180},
11153 -       {0x0000b018, 0x01830182},
11154 -       {0x0000b01c, 0x01850184},
11155 -       {0x0000b020, 0x02810280},
11156 -       {0x0000b024, 0x02830282},
11157 -       {0x0000b028, 0x02850284},
11158 -       {0x0000b02c, 0x02890288},
11159 -       {0x0000b030, 0x028b028a},
11160 -       {0x0000b034, 0x0388028c},
11161 -       {0x0000b038, 0x038a0389},
11162 -       {0x0000b03c, 0x038c038b},
11163 -       {0x0000b040, 0x0390038d},
11164 -       {0x0000b044, 0x03920391},
11165 -       {0x0000b048, 0x03940393},
11166 -       {0x0000b04c, 0x03960395},
11167 -       {0x0000b050, 0x00000000},
11168 -       {0x0000b054, 0x00000000},
11169 -       {0x0000b058, 0x00000000},
11170 -       {0x0000b05c, 0x00000000},
11171 -       {0x0000b060, 0x00000000},
11172 -       {0x0000b064, 0x00000000},
11173 -       {0x0000b068, 0x00000000},
11174 -       {0x0000b06c, 0x00000000},
11175 -       {0x0000b070, 0x00000000},
11176 -       {0x0000b074, 0x00000000},
11177 -       {0x0000b078, 0x00000000},
11178 -       {0x0000b07c, 0x00000000},
11179 -       {0x0000b080, 0x23232323},
11180 -       {0x0000b084, 0x21232323},
11181 -       {0x0000b088, 0x19191c1e},
11182 -       {0x0000b08c, 0x12141417},
11183 -       {0x0000b090, 0x07070e0e},
11184 -       {0x0000b094, 0x03030305},
11185 -       {0x0000b098, 0x00000003},
11186 -       {0x0000b09c, 0x00000000},
11187 -       {0x0000b0a0, 0x00000000},
11188 -       {0x0000b0a4, 0x00000000},
11189 -       {0x0000b0a8, 0x00000000},
11190 -       {0x0000b0ac, 0x00000000},
11191 -       {0x0000b0b0, 0x00000000},
11192 -       {0x0000b0b4, 0x00000000},
11193 -       {0x0000b0b8, 0x00000000},
11194 -       {0x0000b0bc, 0x00000000},
11195 -       {0x0000b0c0, 0x003f0020},
11196 -       {0x0000b0c4, 0x00400041},
11197 -       {0x0000b0c8, 0x0140005f},
11198 -       {0x0000b0cc, 0x0160015f},
11199 -       {0x0000b0d0, 0x017e017f},
11200 -       {0x0000b0d4, 0x02410242},
11201 -       {0x0000b0d8, 0x025f0240},
11202 -       {0x0000b0dc, 0x027f0260},
11203 -       {0x0000b0e0, 0x0341027e},
11204 -       {0x0000b0e4, 0x035f0340},
11205 -       {0x0000b0e8, 0x037f0360},
11206 -       {0x0000b0ec, 0x04400441},
11207 -       {0x0000b0f0, 0x0460045f},
11208 -       {0x0000b0f4, 0x0541047f},
11209 -       {0x0000b0f8, 0x055f0540},
11210 -       {0x0000b0fc, 0x057f0560},
11211 -       {0x0000b100, 0x06400641},
11212 -       {0x0000b104, 0x0660065f},
11213 -       {0x0000b108, 0x067e067f},
11214 -       {0x0000b10c, 0x07410742},
11215 -       {0x0000b110, 0x075f0740},
11216 -       {0x0000b114, 0x077f0760},
11217 -       {0x0000b118, 0x07800781},
11218 -       {0x0000b11c, 0x07a0079f},
11219 -       {0x0000b120, 0x07c107bf},
11220 -       {0x0000b124, 0x000007c0},
11221 -       {0x0000b128, 0x00000000},
11222 -       {0x0000b12c, 0x00000000},
11223 -       {0x0000b130, 0x00000000},
11224 -       {0x0000b134, 0x00000000},
11225 -       {0x0000b138, 0x00000000},
11226 -       {0x0000b13c, 0x00000000},
11227 -       {0x0000b140, 0x003f0020},
11228 -       {0x0000b144, 0x00400041},
11229 -       {0x0000b148, 0x0140005f},
11230 -       {0x0000b14c, 0x0160015f},
11231 -       {0x0000b150, 0x017e017f},
11232 -       {0x0000b154, 0x02410242},
11233 -       {0x0000b158, 0x025f0240},
11234 -       {0x0000b15c, 0x027f0260},
11235 -       {0x0000b160, 0x0341027e},
11236 -       {0x0000b164, 0x035f0340},
11237 -       {0x0000b168, 0x037f0360},
11238 -       {0x0000b16c, 0x04400441},
11239 -       {0x0000b170, 0x0460045f},
11240 -       {0x0000b174, 0x0541047f},
11241 -       {0x0000b178, 0x055f0540},
11242 -       {0x0000b17c, 0x057f0560},
11243 -       {0x0000b180, 0x06400641},
11244 -       {0x0000b184, 0x0660065f},
11245 -       {0x0000b188, 0x067e067f},
11246 -       {0x0000b18c, 0x07410742},
11247 -       {0x0000b190, 0x075f0740},
11248 -       {0x0000b194, 0x077f0760},
11249 -       {0x0000b198, 0x07800781},
11250 -       {0x0000b19c, 0x07a0079f},
11251 -       {0x0000b1a0, 0x07c107bf},
11252 -       {0x0000b1a4, 0x000007c0},
11253 -       {0x0000b1a8, 0x00000000},
11254 -       {0x0000b1ac, 0x00000000},
11255 -       {0x0000b1b0, 0x00000000},
11256 -       {0x0000b1b4, 0x00000000},
11257 -       {0x0000b1b8, 0x00000000},
11258 -       {0x0000b1bc, 0x00000000},
11259 -       {0x0000b1c0, 0x00000000},
11260 -       {0x0000b1c4, 0x00000000},
11261 -       {0x0000b1c8, 0x00000000},
11262 -       {0x0000b1cc, 0x00000000},
11263 -       {0x0000b1d0, 0x00000000},
11264 -       {0x0000b1d4, 0x00000000},
11265 -       {0x0000b1d8, 0x00000000},
11266 -       {0x0000b1dc, 0x00000000},
11267 -       {0x0000b1e0, 0x00000000},
11268 -       {0x0000b1e4, 0x00000000},
11269 -       {0x0000b1e8, 0x00000000},
11270 -       {0x0000b1ec, 0x00000000},
11271 -       {0x0000b1f0, 0x00000396},
11272 -       {0x0000b1f4, 0x00000396},
11273 -       {0x0000b1f8, 0x00000396},
11274 -       {0x0000b1fc, 0x00000196},
11275 -};
11276 -
11277  static const u32 ar955x_1p0_baseband_core[][2] = {
11278         /* Addr      allmodes  */
11279         {0x00009800, 0xafe68e30},
11280 @@ -891,266 +632,6 @@ static const u32 ar955x_1p0_baseband_cor
11281         {0x0000c420, 0x00000000},
11282  };
11283
11284 -static const u32 ar955x_1p0_common_wo_xlna_rx_gain_table[][2] = {
11285 -       /* Addr      allmodes  */
11286 -       {0x0000a000, 0x00010000},
11287 -       {0x0000a004, 0x00030002},
11288 -       {0x0000a008, 0x00050004},
11289 -       {0x0000a00c, 0x00810080},
11290 -       {0x0000a010, 0x00830082},
11291 -       {0x0000a014, 0x01810180},
11292 -       {0x0000a018, 0x01830182},
11293 -       {0x0000a01c, 0x01850184},
11294 -       {0x0000a020, 0x01890188},
11295 -       {0x0000a024, 0x018b018a},
11296 -       {0x0000a028, 0x018d018c},
11297 -       {0x0000a02c, 0x03820190},
11298 -       {0x0000a030, 0x03840383},
11299 -       {0x0000a034, 0x03880385},
11300 -       {0x0000a038, 0x038a0389},
11301 -       {0x0000a03c, 0x038c038b},
11302 -       {0x0000a040, 0x0390038d},
11303 -       {0x0000a044, 0x03920391},
11304 -       {0x0000a048, 0x03940393},
11305 -       {0x0000a04c, 0x03960395},
11306 -       {0x0000a050, 0x00000000},
11307 -       {0x0000a054, 0x00000000},
11308 -       {0x0000a058, 0x00000000},
11309 -       {0x0000a05c, 0x00000000},
11310 -       {0x0000a060, 0x00000000},
11311 -       {0x0000a064, 0x00000000},
11312 -       {0x0000a068, 0x00000000},
11313 -       {0x0000a06c, 0x00000000},
11314 -       {0x0000a070, 0x00000000},
11315 -       {0x0000a074, 0x00000000},
11316 -       {0x0000a078, 0x00000000},
11317 -       {0x0000a07c, 0x00000000},
11318 -       {0x0000a080, 0x29292929},
11319 -       {0x0000a084, 0x29292929},
11320 -       {0x0000a088, 0x29292929},
11321 -       {0x0000a08c, 0x29292929},
11322 -       {0x0000a090, 0x22292929},
11323 -       {0x0000a094, 0x1d1d2222},
11324 -       {0x0000a098, 0x0c111117},
11325 -       {0x0000a09c, 0x00030303},
11326 -       {0x0000a0a0, 0x00000000},
11327 -       {0x0000a0a4, 0x00000000},
11328 -       {0x0000a0a8, 0x00000000},
11329 -       {0x0000a0ac, 0x00000000},
11330 -       {0x0000a0b0, 0x00000000},
11331 -       {0x0000a0b4, 0x00000000},
11332 -       {0x0000a0b8, 0x00000000},
11333 -       {0x0000a0bc, 0x00000000},
11334 -       {0x0000a0c0, 0x001f0000},
11335 -       {0x0000a0c4, 0x01000101},
11336 -       {0x0000a0c8, 0x011e011f},
11337 -       {0x0000a0cc, 0x011c011d},
11338 -       {0x0000a0d0, 0x02030204},
11339 -       {0x0000a0d4, 0x02010202},
11340 -       {0x0000a0d8, 0x021f0200},
11341 -       {0x0000a0dc, 0x0302021e},
11342 -       {0x0000a0e0, 0x03000301},
11343 -       {0x0000a0e4, 0x031e031f},
11344 -       {0x0000a0e8, 0x0402031d},
11345 -       {0x0000a0ec, 0x04000401},
11346 -       {0x0000a0f0, 0x041e041f},
11347 -       {0x0000a0f4, 0x0502041d},
11348 -       {0x0000a0f8, 0x05000501},
11349 -       {0x0000a0fc, 0x051e051f},
11350 -       {0x0000a100, 0x06010602},
11351 -       {0x0000a104, 0x061f0600},
11352 -       {0x0000a108, 0x061d061e},
11353 -       {0x0000a10c, 0x07020703},
11354 -       {0x0000a110, 0x07000701},
11355 -       {0x0000a114, 0x00000000},
11356 -       {0x0000a118, 0x00000000},
11357 -       {0x0000a11c, 0x00000000},
11358 -       {0x0000a120, 0x00000000},
11359 -       {0x0000a124, 0x00000000},
11360 -       {0x0000a128, 0x00000000},
11361 -       {0x0000a12c, 0x00000000},
11362 -       {0x0000a130, 0x00000000},
11363 -       {0x0000a134, 0x00000000},
11364 -       {0x0000a138, 0x00000000},
11365 -       {0x0000a13c, 0x00000000},
11366 -       {0x0000a140, 0x001f0000},
11367 -       {0x0000a144, 0x01000101},
11368 -       {0x0000a148, 0x011e011f},
11369 -       {0x0000a14c, 0x011c011d},
11370 -       {0x0000a150, 0x02030204},
11371 -       {0x0000a154, 0x02010202},
11372 -       {0x0000a158, 0x021f0200},
11373 -       {0x0000a15c, 0x0302021e},
11374 -       {0x0000a160, 0x03000301},
11375 -       {0x0000a164, 0x031e031f},
11376 -       {0x0000a168, 0x0402031d},
11377 -       {0x0000a16c, 0x04000401},
11378 -       {0x0000a170, 0x041e041f},
11379 -       {0x0000a174, 0x0502041d},
11380 -       {0x0000a178, 0x05000501},
11381 -       {0x0000a17c, 0x051e051f},
11382 -       {0x0000a180, 0x06010602},
11383 -       {0x0000a184, 0x061f0600},
11384 -       {0x0000a188, 0x061d061e},
11385 -       {0x0000a18c, 0x07020703},
11386 -       {0x0000a190, 0x07000701},
11387 -       {0x0000a194, 0x00000000},
11388 -       {0x0000a198, 0x00000000},
11389 -       {0x0000a19c, 0x00000000},
11390 -       {0x0000a1a0, 0x00000000},
11391 -       {0x0000a1a4, 0x00000000},
11392 -       {0x0000a1a8, 0x00000000},
11393 -       {0x0000a1ac, 0x00000000},
11394 -       {0x0000a1b0, 0x00000000},
11395 -       {0x0000a1b4, 0x00000000},
11396 -       {0x0000a1b8, 0x00000000},
11397 -       {0x0000a1bc, 0x00000000},
11398 -       {0x0000a1c0, 0x00000000},
11399 -       {0x0000a1c4, 0x00000000},
11400 -       {0x0000a1c8, 0x00000000},
11401 -       {0x0000a1cc, 0x00000000},
11402 -       {0x0000a1d0, 0x00000000},
11403 -       {0x0000a1d4, 0x00000000},
11404 -       {0x0000a1d8, 0x00000000},
11405 -       {0x0000a1dc, 0x00000000},
11406 -       {0x0000a1e0, 0x00000000},
11407 -       {0x0000a1e4, 0x00000000},
11408 -       {0x0000a1e8, 0x00000000},
11409 -       {0x0000a1ec, 0x00000000},
11410 -       {0x0000a1f0, 0x00000396},
11411 -       {0x0000a1f4, 0x00000396},
11412 -       {0x0000a1f8, 0x00000396},
11413 -       {0x0000a1fc, 0x00000196},
11414 -       {0x0000b000, 0x00010000},
11415 -       {0x0000b004, 0x00030002},
11416 -       {0x0000b008, 0x00050004},
11417 -       {0x0000b00c, 0x00810080},
11418 -       {0x0000b010, 0x00830082},
11419 -       {0x0000b014, 0x01810180},
11420 -       {0x0000b018, 0x01830182},
11421 -       {0x0000b01c, 0x01850184},
11422 -       {0x0000b020, 0x02810280},
11423 -       {0x0000b024, 0x02830282},
11424 -       {0x0000b028, 0x02850284},
11425 -       {0x0000b02c, 0x02890288},
11426 -       {0x0000b030, 0x028b028a},
11427 -       {0x0000b034, 0x0388028c},
11428 -       {0x0000b038, 0x038a0389},
11429 -       {0x0000b03c, 0x038c038b},
11430 -       {0x0000b040, 0x0390038d},
11431 -       {0x0000b044, 0x03920391},
11432 -       {0x0000b048, 0x03940393},
11433 -       {0x0000b04c, 0x03960395},
11434 -       {0x0000b050, 0x00000000},
11435 -       {0x0000b054, 0x00000000},
11436 -       {0x0000b058, 0x00000000},
11437 -       {0x0000b05c, 0x00000000},
11438 -       {0x0000b060, 0x00000000},
11439 -       {0x0000b064, 0x00000000},
11440 -       {0x0000b068, 0x00000000},
11441 -       {0x0000b06c, 0x00000000},
11442 -       {0x0000b070, 0x00000000},
11443 -       {0x0000b074, 0x00000000},
11444 -       {0x0000b078, 0x00000000},
11445 -       {0x0000b07c, 0x00000000},
11446 -       {0x0000b080, 0x32323232},
11447 -       {0x0000b084, 0x2f2f3232},
11448 -       {0x0000b088, 0x23282a2d},
11449 -       {0x0000b08c, 0x1c1e2123},
11450 -       {0x0000b090, 0x14171919},
11451 -       {0x0000b094, 0x0e0e1214},
11452 -       {0x0000b098, 0x03050707},
11453 -       {0x0000b09c, 0x00030303},
11454 -       {0x0000b0a0, 0x00000000},
11455 -       {0x0000b0a4, 0x00000000},
11456 -       {0x0000b0a8, 0x00000000},
11457 -       {0x0000b0ac, 0x00000000},
11458 -       {0x0000b0b0, 0x00000000},
11459 -       {0x0000b0b4, 0x00000000},
11460 -       {0x0000b0b8, 0x00000000},
11461 -       {0x0000b0bc, 0x00000000},
11462 -       {0x0000b0c0, 0x003f0020},
11463 -       {0x0000b0c4, 0x00400041},
11464 -       {0x0000b0c8, 0x0140005f},
11465 -       {0x0000b0cc, 0x0160015f},
11466 -       {0x0000b0d0, 0x017e017f},
11467 -       {0x0000b0d4, 0x02410242},
11468 -       {0x0000b0d8, 0x025f0240},
11469 -       {0x0000b0dc, 0x027f0260},
11470 -       {0x0000b0e0, 0x0341027e},
11471 -       {0x0000b0e4, 0x035f0340},
11472 -       {0x0000b0e8, 0x037f0360},
11473 -       {0x0000b0ec, 0x04400441},
11474 -       {0x0000b0f0, 0x0460045f},
11475 -       {0x0000b0f4, 0x0541047f},
11476 -       {0x0000b0f8, 0x055f0540},
11477 -       {0x0000b0fc, 0x057f0560},
11478 -       {0x0000b100, 0x06400641},
11479 -       {0x0000b104, 0x0660065f},
11480 -       {0x0000b108, 0x067e067f},
11481 -       {0x0000b10c, 0x07410742},
11482 -       {0x0000b110, 0x075f0740},
11483 -       {0x0000b114, 0x077f0760},
11484 -       {0x0000b118, 0x07800781},
11485 -       {0x0000b11c, 0x07a0079f},
11486 -       {0x0000b120, 0x07c107bf},
11487 -       {0x0000b124, 0x000007c0},
11488 -       {0x0000b128, 0x00000000},
11489 -       {0x0000b12c, 0x00000000},
11490 -       {0x0000b130, 0x00000000},
11491 -       {0x0000b134, 0x00000000},
11492 -       {0x0000b138, 0x00000000},
11493 -       {0x0000b13c, 0x00000000},
11494 -       {0x0000b140, 0x003f0020},
11495 -       {0x0000b144, 0x00400041},
11496 -       {0x0000b148, 0x0140005f},
11497 -       {0x0000b14c, 0x0160015f},
11498 -       {0x0000b150, 0x017e017f},
11499 -       {0x0000b154, 0x02410242},
11500 -       {0x0000b158, 0x025f0240},
11501 -       {0x0000b15c, 0x027f0260},
11502 -       {0x0000b160, 0x0341027e},
11503 -       {0x0000b164, 0x035f0340},
11504 -       {0x0000b168, 0x037f0360},
11505 -       {0x0000b16c, 0x04400441},
11506 -       {0x0000b170, 0x0460045f},
11507 -       {0x0000b174, 0x0541047f},
11508 -       {0x0000b178, 0x055f0540},
11509 -       {0x0000b17c, 0x057f0560},
11510 -       {0x0000b180, 0x06400641},
11511 -       {0x0000b184, 0x0660065f},
11512 -       {0x0000b188, 0x067e067f},
11513 -       {0x0000b18c, 0x07410742},
11514 -       {0x0000b190, 0x075f0740},
11515 -       {0x0000b194, 0x077f0760},
11516 -       {0x0000b198, 0x07800781},
11517 -       {0x0000b19c, 0x07a0079f},
11518 -       {0x0000b1a0, 0x07c107bf},
11519 -       {0x0000b1a4, 0x000007c0},
11520 -       {0x0000b1a8, 0x00000000},
11521 -       {0x0000b1ac, 0x00000000},
11522 -       {0x0000b1b0, 0x00000000},
11523 -       {0x0000b1b4, 0x00000000},
11524 -       {0x0000b1b8, 0x00000000},
11525 -       {0x0000b1bc, 0x00000000},
11526 -       {0x0000b1c0, 0x00000000},
11527 -       {0x0000b1c4, 0x00000000},
11528 -       {0x0000b1c8, 0x00000000},
11529 -       {0x0000b1cc, 0x00000000},
11530 -       {0x0000b1d0, 0x00000000},
11531 -       {0x0000b1d4, 0x00000000},
11532 -       {0x0000b1d8, 0x00000000},
11533 -       {0x0000b1dc, 0x00000000},
11534 -       {0x0000b1e0, 0x00000000},
11535 -       {0x0000b1e4, 0x00000000},
11536 -       {0x0000b1e8, 0x00000000},
11537 -       {0x0000b1ec, 0x00000000},
11538 -       {0x0000b1f0, 0x00000396},
11539 -       {0x0000b1f4, 0x00000396},
11540 -       {0x0000b1f8, 0x00000396},
11541 -       {0x0000b1fc, 0x00000196},
11542 -};
11543 -
11544  static const u32 ar955x_1p0_soc_preamble[][2] = {
11545         /* Addr      allmodes  */
11546         {0x00007000, 0x00000000},
11547 @@ -1263,11 +744,6 @@ static const u32 ar955x_1p0_modes_no_xpa
11548         {0x00016848, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
11549  };
11550
11551 -static const u32 ar955x_1p0_soc_postamble[][5] = {
11552 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11553 -       {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
11554 -};
11555 -
11556  static const u32 ar955x_1p0_modes_fast_clock[][3] = {
11557         /* Addr      5G_HT20     5G_HT40   */
11558         {0x00001030, 0x00000268, 0x000004d0},
11559 --- a/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h
11560 +++ b/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h
11561 @@ -20,6 +20,12 @@
11562
11563  /* AR9565 1.0 */
11564
11565 +#define ar9565_1p0_mac_postamble ar9331_1p1_mac_postamble
11566 +
11567 +#define ar9565_1p0_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table
11568 +
11569 +#define ar9565_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
11570 +
11571  static const u32 ar9565_1p0_mac_core[][2] = {
11572         /* Addr      allmodes  */
11573         {0x00000008, 0x00000000},
11574 @@ -182,18 +188,6 @@ static const u32 ar9565_1p0_mac_core[][2
11575         {0x000083d0, 0x800301ff},
11576  };
11577
11578 -static const u32 ar9565_1p0_mac_postamble[][5] = {
11579 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11580 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
11581 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
11582 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
11583 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
11584 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
11585 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
11586 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
11587 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
11588 -};
11589 -
11590  static const u32 ar9565_1p0_baseband_core[][2] = {
11591         /* Addr      allmodes  */
11592         {0x00009800, 0xafe68e30},
11593 @@ -711,66 +705,6 @@ static const u32 ar9565_1p0_Common_rx_ga
11594         {0x0000b1fc, 0x00000196},
11595  };
11596
11597 -static const u32 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table[][5] = {
11598 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11599 -       {0x0000a2dc, 0xfc0a9380, 0xfc0a9380, 0xfdab5b52, 0xfdab5b52},
11600 -       {0x0000a2e0, 0xffecec00, 0xffecec00, 0xfd339c84, 0xfd339c84},
11601 -       {0x0000a2e4, 0xfc0f0000, 0xfc0f0000, 0xfec3e000, 0xfec3e000},
11602 -       {0x0000a2e8, 0xfc100000, 0xfc100000, 0xfffc0000, 0xfffc0000},
11603 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
11604 -       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11605 -       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
11606 -       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
11607 -       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
11608 -       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
11609 -       {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
11610 -       {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
11611 -       {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
11612 -       {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
11613 -       {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
11614 -       {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
11615 -       {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
11616 -       {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
11617 -       {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
11618 -       {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
11619 -       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
11620 -       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
11621 -       {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
11622 -       {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
11623 -       {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
11624 -       {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
11625 -       {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
11626 -       {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
11627 -       {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
11628 -       {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
11629 -       {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
11630 -       {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
11631 -       {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
11632 -       {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
11633 -       {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
11634 -       {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
11635 -       {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
11636 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11637 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11638 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11639 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11640 -       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11641 -       {0x0000a614, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11642 -       {0x0000a618, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11643 -       {0x0000a61c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11644 -       {0x0000a620, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11645 -       {0x0000a624, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11646 -       {0x0000a628, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11647 -       {0x0000a62c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11648 -       {0x0000a630, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11649 -       {0x0000a634, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11650 -       {0x0000a638, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11651 -       {0x0000a63c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11652 -       {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
11653 -       {0x00016048, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11654 -       {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11655 -};
11656 -
11657  static const u32 ar9565_1p0_pciephy_clkreq_disable_L1[][2] = {
11658         /* Addr      allmodes  */
11659         {0x00018c00, 0x18212ede},
11660 @@ -1231,11 +1165,4 @@ static const u32 ar9565_1p0_modes_high_p
11661         {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11662  };
11663
11664 -static const u32 ar9565_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
11665 -       /* Addr      allmodes  */
11666 -       {0x0000a398, 0x00000000},
11667 -       {0x0000a39c, 0x6f7f0301},
11668 -       {0x0000a3a0, 0xca9228ee},
11669 -};
11670 -
11671  #endif /* INITVALS_9565_1P0_H */
11672 --- a/include/linux/ath9k_platform.h
11673 +++ b/include/linux/ath9k_platform.h
11674 @@ -32,6 +32,8 @@ struct ath9k_platform_data {
11675         u32 gpio_val;
11676
11677         bool is_clk_25mhz;
11678 +       bool tx_gain_buffalo;
11679 +
11680         int (*get_mac_revision)(void);
11681         int (*external_reset)(void);
11682  };
11683 --- /dev/null
11684 +++ b/drivers/net/wireless/ath/ath9k/ar9003_buffalo_initvals.h
11685 @@ -0,0 +1,126 @@
11686 +/*
11687 + * Copyright (c) 2013 Qualcomm Atheros Inc.
11688 + *
11689 + * Permission to use, copy, modify, and/or distribute this software for any
11690 + * purpose with or without fee is hereby granted, provided that the above
11691 + * copyright notice and this permission notice appear in all copies.
11692 + *
11693 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11694 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11695 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11696 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11697 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
11698 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
11699 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
11700 + */
11701 +
11702 +#ifndef INITVALS_9003_BUFFALO_H
11703 +#define INITVALS_9003_BUFFALO_H
11704 +
11705 +static const u32 ar9300Modes_high_power_tx_gain_table_buffalo[][5] = {
11706 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11707 +       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
11708 +       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
11709 +       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
11710 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11711 +       {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
11712 +       {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
11713 +       {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
11714 +       {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
11715 +       {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
11716 +       {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
11717 +       {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
11718 +       {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
11719 +       {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
11720 +       {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
11721 +       {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
11722 +       {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
11723 +       {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
11724 +       {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
11725 +       {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
11726 +       {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
11727 +       {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
11728 +       {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
11729 +       {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
11730 +       {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
11731 +       {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
11732 +       {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
11733 +       {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
11734 +       {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
11735 +       {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
11736 +       {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
11737 +       {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
11738 +       {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
11739 +       {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
11740 +       {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
11741 +       {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
11742 +       {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
11743 +       {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
11744 +       {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
11745 +       {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
11746 +       {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
11747 +       {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
11748 +       {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
11749 +       {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
11750 +       {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
11751 +       {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
11752 +       {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
11753 +       {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
11754 +       {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
11755 +       {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
11756 +       {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
11757 +       {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
11758 +       {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
11759 +       {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
11760 +       {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
11761 +       {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
11762 +       {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
11763 +       {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
11764 +       {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
11765 +       {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
11766 +       {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
11767 +       {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
11768 +       {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
11769 +       {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
11770 +       {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
11771 +       {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
11772 +       {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
11773 +       {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
11774 +       {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
11775 +       {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
11776 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11777 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11778 +       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11779 +       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11780 +       {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
11781 +       {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
11782 +       {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
11783 +       {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
11784 +       {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
11785 +       {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
11786 +       {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
11787 +       {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11788 +       {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11789 +       {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11790 +       {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11791 +       {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11792 +       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
11793 +       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
11794 +       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
11795 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11796 +       {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
11797 +       {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
11798 +       {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
11799 +       {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11800 +       {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11801 +       {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
11802 +       {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11803 +       {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11804 +       {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
11805 +       {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11806 +       {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11807 +       {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
11808 +       {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11809 +};
11810 +
11811 +#endif /* INITVALS_9003_BUFFALO_H */
11812 --- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
11813 +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
11814 @@ -76,9 +76,16 @@ static bool ar9002_hw_get_isr(struct ath
11815                                 mask2 |= ATH9K_INT_CST;
11816                         if (isr2 & AR_ISR_S2_TSFOOR)
11817                                 mask2 |= ATH9K_INT_TSFOOR;
11818 +
11819 +                       if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
11820 +                               REG_WRITE(ah, AR_ISR_S2, isr2);
11821 +                               isr &= ~AR_ISR_BCNMISC;
11822 +                       }
11823                 }
11824
11825 -               isr = REG_READ(ah, AR_ISR_RAC);
11826 +               if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
11827 +                       isr = REG_READ(ah, AR_ISR_RAC);
11828 +
11829                 if (isr == 0xffffffff) {
11830                         *masked = 0;
11831                         return false;
11832 @@ -97,11 +104,23 @@ static bool ar9002_hw_get_isr(struct ath
11833
11834                         *masked |= ATH9K_INT_TX;
11835
11836 -                       s0_s = REG_READ(ah, AR_ISR_S0_S);
11837 +                       if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
11838 +                               s0_s = REG_READ(ah, AR_ISR_S0_S);
11839 +                               s1_s = REG_READ(ah, AR_ISR_S1_S);
11840 +                       } else {
11841 +                               s0_s = REG_READ(ah, AR_ISR_S0);
11842 +                               REG_WRITE(ah, AR_ISR_S0, s0_s);
11843 +                               s1_s = REG_READ(ah, AR_ISR_S1);
11844 +                               REG_WRITE(ah, AR_ISR_S1, s1_s);
11845 +
11846 +                               isr &= ~(AR_ISR_TXOK |
11847 +                                        AR_ISR_TXDESC |
11848 +                                        AR_ISR_TXERR |
11849 +                                        AR_ISR_TXEOL);
11850 +                       }
11851 +
11852                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
11853                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
11854 -
11855 -                       s1_s = REG_READ(ah, AR_ISR_S1_S);
11856                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
11857                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
11858                 }
11859 @@ -120,7 +139,12 @@ static bool ar9002_hw_get_isr(struct ath
11860         if (isr & AR_ISR_GENTMR) {
11861                 u32 s5_s;
11862
11863 -               s5_s = REG_READ(ah, AR_ISR_S5_S);
11864 +               if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
11865 +                       s5_s = REG_READ(ah, AR_ISR_S5_S);
11866 +               } else {
11867 +                       s5_s = REG_READ(ah, AR_ISR_S5);
11868 +               }
11869 +
11870                 ah->intr_gen_timer_trigger =
11871                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
11872
11873 @@ -133,6 +157,16 @@ static bool ar9002_hw_get_isr(struct ath
11874                 if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
11875                     !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
11876                         *masked |= ATH9K_INT_TIM_TIMER;
11877 +
11878 +               if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
11879 +                       REG_WRITE(ah, AR_ISR_S5, s5_s);
11880 +                       isr &= ~AR_ISR_GENTMR;
11881 +               }
11882 +       }
11883 +
11884 +       if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
11885 +               REG_WRITE(ah, AR_ISR, isr);
11886 +               REG_READ(ah, AR_ISR);
11887         }
11888
11889         if (sync_cause) {
11890 --- a/drivers/net/wireless/ath/ath9k/antenna.c
11891 +++ b/drivers/net/wireless/ath/ath9k/antenna.c
11892 @@ -724,14 +724,14 @@ void ath_ant_comb_scan(struct ath_softc
11893         struct ath_ant_comb *antcomb = &sc->ant_comb;
11894         int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
11895         int curr_main_set;
11896 -       int main_rssi = rs->rs_rssi_ctl0;
11897 -       int alt_rssi = rs->rs_rssi_ctl1;
11898 +       int main_rssi = rs->rs_rssi_ctl[0];
11899 +       int alt_rssi = rs->rs_rssi_ctl[1];
11900         int rx_ant_conf,  main_ant_conf;
11901         bool short_scan = false, ret;
11902
11903 -       rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
11904 +       rx_ant_conf = (rs->rs_rssi_ctl[2] >> ATH_ANT_RX_CURRENT_SHIFT) &
11905                        ATH_ANT_RX_MASK;
11906 -       main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
11907 +       main_ant_conf = (rs->rs_rssi_ctl[2] >> ATH_ANT_RX_MAIN_SHIFT) &
11908                          ATH_ANT_RX_MASK;
11909
11910         if (alt_rssi >= antcomb->low_rssi_thresh) {
11911 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
11912 +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
11913 @@ -32,12 +32,8 @@ static int ar9002_hw_init_mode_regs(stru
11914                 return 0;
11915         }
11916
11917 -       if (ah->config.pcie_clock_req)
11918 -               INIT_INI_ARRAY(&ah->iniPcieSerdes,
11919 -                          ar9280PciePhy_clkreq_off_L1_9280);
11920 -       else
11921 -               INIT_INI_ARRAY(&ah->iniPcieSerdes,
11922 -                          ar9280PciePhy_clkreq_always_on_L1_9280);
11923 +       INIT_INI_ARRAY(&ah->iniPcieSerdes,
11924 +                      ar9280PciePhy_clkreq_always_on_L1_9280);
11925
11926         if (AR_SREV_9287_11_OR_LATER(ah)) {
11927                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
11928 --- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
11929 +++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
11930 @@ -201,7 +201,6 @@ static void ar9002_hw_spur_mitigate(stru
11931         ath9k_hw_get_channel_centers(ah, chan, &centers);
11932         freq = centers.synth_center;
11933
11934 -       ah->config.spurmode = SPUR_ENABLE_EEPROM;
11935         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
11936                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
11937
11938 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
11939 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
11940 @@ -476,12 +476,12 @@ int ath9k_hw_process_rxdesc_edma(struct
11941
11942         /* XXX: Keycache */
11943         rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
11944 -       rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
11945 -       rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
11946 -       rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
11947 -       rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
11948 -       rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
11949 -       rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
11950 +       rxs->rs_rssi_ctl[0] = MS(rxsp->status1, AR_RxRSSIAnt00);
11951 +       rxs->rs_rssi_ctl[1] = MS(rxsp->status1, AR_RxRSSIAnt01);
11952 +       rxs->rs_rssi_ctl[2] = MS(rxsp->status1, AR_RxRSSIAnt02);
11953 +       rxs->rs_rssi_ext[0] = MS(rxsp->status5, AR_RxRSSIAnt10);
11954 +       rxs->rs_rssi_ext[1] = MS(rxsp->status5, AR_RxRSSIAnt11);
11955 +       rxs->rs_rssi_ext[2] = MS(rxsp->status5, AR_RxRSSIAnt12);
11956
11957         if (rxsp->status11 & AR_RxKeyIdxValid)
11958                 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
11959 --- a/drivers/net/wireless/ath/ath9k/beacon.c
11960 +++ b/drivers/net/wireless/ath/ath9k/beacon.c
11961 @@ -431,6 +431,33 @@ static void ath9k_beacon_init(struct ath
11962         ath9k_hw_enable_interrupts(ah);
11963  }
11964
11965 +/* Calculate the modulo of a 64 bit TSF snapshot with a TU divisor */
11966 +static u32 ath9k_mod_tsf64_tu(u64 tsf, u32 div_tu)
11967 +{
11968 +       u32 tsf_mod, tsf_hi, tsf_lo, mod_hi, mod_lo;
11969 +
11970 +       tsf_mod = tsf & (BIT(10) - 1);
11971 +       tsf_hi = tsf >> 32;
11972 +       tsf_lo = ((u32) tsf) >> 10;
11973 +
11974 +       mod_hi = tsf_hi % div_tu;
11975 +       mod_lo = ((mod_hi << 22) + tsf_lo) % div_tu;
11976 +
11977 +       return (mod_lo << 10) | tsf_mod;
11978 +}
11979 +
11980 +static u32 ath9k_get_next_tbtt(struct ath_softc *sc, u64 tsf,
11981 +                              unsigned int interval)
11982 +{
11983 +       struct ath_hw *ah = sc->sc_ah;
11984 +       unsigned int offset;
11985 +
11986 +       tsf += TU_TO_USEC(FUDGE + ah->config.sw_beacon_response_time);
11987 +       offset = ath9k_mod_tsf64_tu(tsf, interval);
11988 +
11989 +       return (u32) tsf + TU_TO_USEC(interval) - offset;
11990 +}
11991 +
11992  /*
11993   * For multi-bss ap support beacons are either staggered evenly over N slots or
11994   * burst together.  For the former arrange for the SWBA to be delivered for each
11995 @@ -446,7 +473,8 @@ static void ath9k_beacon_config_ap(struc
11996         /* NB: the beacon interval is kept internally in TU's */
11997         intval = TU_TO_USEC(conf->beacon_interval);
11998         intval /= ATH_BCBUF;
11999 -       nexttbtt = intval;
12000 +       nexttbtt = ath9k_get_next_tbtt(sc, ath9k_hw_gettsf64(ah),
12001 +                                      conf->beacon_interval);
12002
12003         if (conf->enable_beacon)
12004                 ah->imask |= ATH9K_INT_SWBA;
12005 @@ -458,7 +486,7 @@ static void ath9k_beacon_config_ap(struc
12006                 (conf->enable_beacon) ? "Enable" : "Disable",
12007                 nexttbtt, intval, conf->beacon_interval);
12008
12009 -       ath9k_beacon_init(sc, nexttbtt, intval, true);
12010 +       ath9k_beacon_init(sc, nexttbtt, intval, false);
12011  }
12012
12013  /*
12014 @@ -475,11 +503,9 @@ static void ath9k_beacon_config_sta(stru
12015         struct ath_hw *ah = sc->sc_ah;
12016         struct ath_common *common = ath9k_hw_common(ah);
12017         struct ath9k_beacon_state bs;
12018 -       int dtimperiod, dtimcount, sleepduration;
12019 -       int cfpperiod, cfpcount;
12020 -       u32 nexttbtt = 0, intval, tsftu;
12021 +       int dtim_intval, sleepduration;
12022 +       u32 nexttbtt = 0, intval;
12023         u64 tsf;
12024 -       int num_beacons, offset, dtim_dec_count, cfp_dec_count;
12025
12026         /* No need to configure beacon if we are not associated */
12027         if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
12028 @@ -492,53 +518,25 @@ static void ath9k_beacon_config_sta(stru
12029         intval = conf->beacon_interval;
12030
12031         /*
12032 -        * Setup dtim and cfp parameters according to
12033 +        * Setup dtim parameters according to
12034          * last beacon we received (which may be none).
12035          */
12036 -       dtimperiod = conf->dtim_period;
12037 -       dtimcount = conf->dtim_count;
12038 -       if (dtimcount >= dtimperiod)    /* NB: sanity check */
12039 -               dtimcount = 0;
12040 -       cfpperiod = 1;                  /* NB: no PCF support yet */
12041 -       cfpcount = 0;
12042 -
12043 +       dtim_intval = intval * conf->dtim_period;
12044         sleepduration = conf->listen_interval * intval;
12045
12046         /*
12047          * Pull nexttbtt forward to reflect the current
12048 -        * TSF and calculate dtim+cfp state for the result.
12049 +        * TSF and calculate dtim state for the result.
12050          */
12051         tsf = ath9k_hw_gettsf64(ah);
12052 -       tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
12053 -
12054 -       num_beacons = tsftu / intval + 1;
12055 -       offset = tsftu % intval;
12056 -       nexttbtt = tsftu - offset;
12057 -       if (offset)
12058 -               nexttbtt += intval;
12059 -
12060 -       /* DTIM Beacon every dtimperiod Beacon */
12061 -       dtim_dec_count = num_beacons % dtimperiod;
12062 -       /* CFP every cfpperiod DTIM Beacon */
12063 -       cfp_dec_count = (num_beacons / dtimperiod) % cfpperiod;
12064 -       if (dtim_dec_count)
12065 -               cfp_dec_count++;
12066 -
12067 -       dtimcount -= dtim_dec_count;
12068 -       if (dtimcount < 0)
12069 -               dtimcount += dtimperiod;
12070 -
12071 -       cfpcount -= cfp_dec_count;
12072 -       if (cfpcount < 0)
12073 -               cfpcount += cfpperiod;
12074 +       nexttbtt = ath9k_get_next_tbtt(sc, tsf, intval);
12075
12076 -       bs.bs_intval = intval;
12077 +       bs.bs_intval = TU_TO_USEC(intval);
12078 +       bs.bs_dtimperiod = conf->dtim_period * bs.bs_intval;
12079         bs.bs_nexttbtt = nexttbtt;
12080 -       bs.bs_dtimperiod = dtimperiod*intval;
12081 -       bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
12082 -       bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
12083 -       bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
12084 -       bs.bs_cfpmaxduration = 0;
12085 +       bs.bs_nextdtim = nexttbtt;
12086 +       if (conf->dtim_period > 1)
12087 +               bs.bs_nextdtim = ath9k_get_next_tbtt(sc, tsf, dtim_intval);
12088
12089         /*
12090          * Calculate the number of consecutive beacons to miss* before taking
12091 @@ -566,18 +564,16 @@ static void ath9k_beacon_config_sta(stru
12092          * XXX fixed at 100ms
12093          */
12094
12095 -       bs.bs_sleepduration = roundup(IEEE80211_MS_TO_TU(100), sleepduration);
12096 +       bs.bs_sleepduration = TU_TO_USEC(roundup(IEEE80211_MS_TO_TU(100),
12097 +                                                sleepduration));
12098         if (bs.bs_sleepduration > bs.bs_dtimperiod)
12099                 bs.bs_sleepduration = bs.bs_dtimperiod;
12100
12101         /* TSF out of range threshold fixed at 1 second */
12102         bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
12103
12104 -       ath_dbg(common, BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
12105 -       ath_dbg(common, BEACON,
12106 -               "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
12107 -               bs.bs_bmissthreshold, bs.bs_sleepduration,
12108 -               bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
12109 +       ath_dbg(common, BEACON, "bmiss: %u sleep: %u\n",
12110 +               bs.bs_bmissthreshold, bs.bs_sleepduration);
12111
12112         /* Set the computed STA beacon timers */
12113
12114 @@ -600,25 +596,11 @@ static void ath9k_beacon_config_adhoc(st
12115
12116         intval = TU_TO_USEC(conf->beacon_interval);
12117
12118 -       if (conf->ibss_creator) {
12119 +       if (conf->ibss_creator)
12120                 nexttbtt = intval;
12121 -       } else {
12122 -               u32 tbtt, offset, tsftu;
12123 -               u64 tsf;
12124 -
12125 -               /*
12126 -                * Pull nexttbtt forward to reflect the current
12127 -                * sync'd TSF.
12128 -                */
12129 -               tsf = ath9k_hw_gettsf64(ah);
12130 -               tsftu = TSF_TO_TU(tsf >> 32, tsf) + FUDGE;
12131 -               offset = tsftu % conf->beacon_interval;
12132 -               tbtt = tsftu - offset;
12133 -               if (offset)
12134 -                       tbtt += conf->beacon_interval;
12135 -
12136 -               nexttbtt = TU_TO_USEC(tbtt);
12137 -       }
12138 +       else
12139 +               nexttbtt = ath9k_get_next_tbtt(sc, ath9k_hw_gettsf64(ah),
12140 +                                              conf->beacon_interval);
12141
12142         if (conf->enable_beacon)
12143                 ah->imask |= ATH9K_INT_SWBA;
12144 --- a/drivers/net/wireless/ath/ath9k/btcoex.c
12145 +++ b/drivers/net/wireless/ath/ath9k/btcoex.c
12146 @@ -66,7 +66,6 @@ void ath9k_hw_init_btcoex_hw(struct ath_
12147                 .bt_first_slot_time = 5,
12148                 .bt_hold_rx_clear = true,
12149         };
12150 -       u32 i, idx;
12151         bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
12152
12153         if (AR_SREV_9300_20_OR_LATER(ah))
12154 @@ -88,11 +87,6 @@ void ath9k_hw_init_btcoex_hw(struct ath_
12155                 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
12156                 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
12157                 AR_BT_DISABLE_BT_ANT;
12158 -
12159 -       for (i = 0; i < 32; i++) {
12160 -               idx = (debruijn32 << i) >> 27;
12161 -               ah->hw_gen_timers.gen_timer_index[idx] = i;
12162 -       }
12163  }
12164  EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
12165
12166 --- a/drivers/net/wireless/ath/ath9k/dfs.c
12167 +++ b/drivers/net/wireless/ath/ath9k/dfs.c
12168 @@ -158,8 +158,8 @@ void ath9k_dfs_process_phyerr(struct ath
12169                 return;
12170         }
12171
12172 -       ard.rssi = rs->rs_rssi_ctl0;
12173 -       ard.ext_rssi = rs->rs_rssi_ext0;
12174 +       ard.rssi = rs->rs_rssi_ctl[0];
12175 +       ard.ext_rssi = rs->rs_rssi_ext[0];
12176
12177         /*
12178          * hardware stores this as 8 bit signed value.
12179 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
12180 +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
12181 @@ -1085,31 +1085,7 @@ static void ath9k_hw_4k_set_board_values
12182
12183  static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
12184  {
12185 -#define EEP_MAP4K_SPURCHAN \
12186 -       (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
12187 -       struct ath_common *common = ath9k_hw_common(ah);
12188 -
12189 -       u16 spur_val = AR_NO_SPUR;
12190 -
12191 -       ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
12192 -               i, is2GHz, ah->config.spurchans[i][is2GHz]);
12193 -
12194 -       switch (ah->config.spurmode) {
12195 -       case SPUR_DISABLE:
12196 -               break;
12197 -       case SPUR_ENABLE_IOCTL:
12198 -               spur_val = ah->config.spurchans[i][is2GHz];
12199 -               ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
12200 -                       spur_val);
12201 -               break;
12202 -       case SPUR_ENABLE_EEPROM:
12203 -               spur_val = EEP_MAP4K_SPURCHAN;
12204 -               break;
12205 -       }
12206 -
12207 -       return spur_val;
12208 -
12209 -#undef EEP_MAP4K_SPURCHAN
12210 +       return ah->eeprom.map4k.modalHeader.spurChans[i].spurChan;
12211  }
12212
12213  const struct eeprom_ops eep_4k_ops = {
12214 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
12215 +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
12216 @@ -1004,31 +1004,7 @@ static void ath9k_hw_ar9287_set_board_va
12217  static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
12218                                             u16 i, bool is2GHz)
12219  {
12220 -#define EEP_MAP9287_SPURCHAN \
12221 -       (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
12222 -
12223 -       struct ath_common *common = ath9k_hw_common(ah);
12224 -       u16 spur_val = AR_NO_SPUR;
12225 -
12226 -       ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
12227 -               i, is2GHz, ah->config.spurchans[i][is2GHz]);
12228 -
12229 -       switch (ah->config.spurmode) {
12230 -       case SPUR_DISABLE:
12231 -               break;
12232 -       case SPUR_ENABLE_IOCTL:
12233 -               spur_val = ah->config.spurchans[i][is2GHz];
12234 -               ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
12235 -                       spur_val);
12236 -               break;
12237 -       case SPUR_ENABLE_EEPROM:
12238 -               spur_val = EEP_MAP9287_SPURCHAN;
12239 -               break;
12240 -       }
12241 -
12242 -       return spur_val;
12243 -
12244 -#undef EEP_MAP9287_SPURCHAN
12245 +       return ah->eeprom.map9287.modalHeader.spurChans[i].spurChan;
12246  }
12247
12248  const struct eeprom_ops eep_ar9287_ops = {
12249 --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
12250 +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
12251 @@ -1348,31 +1348,7 @@ static void ath9k_hw_def_set_txpower(str
12252
12253  static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
12254  {
12255 -#define EEP_DEF_SPURCHAN \
12256 -       (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
12257 -       struct ath_common *common = ath9k_hw_common(ah);
12258 -
12259 -       u16 spur_val = AR_NO_SPUR;
12260 -
12261 -       ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
12262 -               i, is2GHz, ah->config.spurchans[i][is2GHz]);
12263 -
12264 -       switch (ah->config.spurmode) {
12265 -       case SPUR_DISABLE:
12266 -               break;
12267 -       case SPUR_ENABLE_IOCTL:
12268 -               spur_val = ah->config.spurchans[i][is2GHz];
12269 -               ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
12270 -                       spur_val);
12271 -               break;
12272 -       case SPUR_ENABLE_EEPROM:
12273 -               spur_val = EEP_DEF_SPURCHAN;
12274 -               break;
12275 -       }
12276 -
12277 -       return spur_val;
12278 -
12279 -#undef EEP_DEF_SPURCHAN
12280 +       return ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan;
12281  }
12282
12283  const struct eeprom_ops eep_def_ops = {
12284 --- a/drivers/net/wireless/ath/ath9k/gpio.c
12285 +++ b/drivers/net/wireless/ath/ath9k/gpio.c
12286 @@ -157,36 +157,6 @@ static void ath_detect_bt_priority(struc
12287         }
12288  }
12289
12290 -static void ath9k_gen_timer_start(struct ath_hw *ah,
12291 -                                 struct ath_gen_timer *timer,
12292 -                                 u32 trig_timeout,
12293 -                                 u32 timer_period)
12294 -{
12295 -       ath9k_hw_gen_timer_start(ah, timer, trig_timeout, timer_period);
12296 -
12297 -       if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
12298 -               ath9k_hw_disable_interrupts(ah);
12299 -               ah->imask |= ATH9K_INT_GENTIMER;
12300 -               ath9k_hw_set_interrupts(ah);
12301 -               ath9k_hw_enable_interrupts(ah);
12302 -       }
12303 -}
12304 -
12305 -static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
12306 -{
12307 -       struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
12308 -
12309 -       ath9k_hw_gen_timer_stop(ah, timer);
12310 -
12311 -       /* if no timer is enabled, turn off interrupt mask */
12312 -       if (timer_table->timer_mask.val == 0) {
12313 -               ath9k_hw_disable_interrupts(ah);
12314 -               ah->imask &= ~ATH9K_INT_GENTIMER;
12315 -               ath9k_hw_set_interrupts(ah);
12316 -               ath9k_hw_enable_interrupts(ah);
12317 -       }
12318 -}
12319 -
12320  static void ath_mci_ftp_adjust(struct ath_softc *sc)
12321  {
12322         struct ath_btcoex *btcoex = &sc->btcoex;
12323 @@ -257,19 +227,9 @@ static void ath_btcoex_period_timer(unsi
12324
12325         spin_unlock_bh(&btcoex->btcoex_lock);
12326
12327 -       /*
12328 -        * btcoex_period is in msec while (btocex/btscan_)no_stomp are in usec,
12329 -        * ensure that we properly convert btcoex_period to usec
12330 -        * for any comparision with (btcoex/btscan_)no_stomp.
12331 -        */
12332 -       if (btcoex->btcoex_period * 1000 != btcoex->btcoex_no_stomp) {
12333 -               if (btcoex->hw_timer_enabled)
12334 -                       ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
12335 -
12336 -               ath9k_gen_timer_start(ah, btcoex->no_stomp_timer, timer_period,
12337 -                                     timer_period * 10);
12338 -               btcoex->hw_timer_enabled = true;
12339 -       }
12340 +       if (btcoex->btcoex_period != btcoex->btcoex_no_stomp)
12341 +               mod_timer(&btcoex->no_stomp_timer,
12342 +                        jiffies + msecs_to_jiffies(timer_period));
12343
12344         ath9k_ps_restore(sc);
12345
12346 @@ -282,7 +242,7 @@ skip_hw_wakeup:
12347   * Generic tsf based hw timer which configures weight
12348   * registers to time slice between wlan and bt traffic
12349   */
12350 -static void ath_btcoex_no_stomp_timer(void *arg)
12351 +static void ath_btcoex_no_stomp_timer(unsigned long arg)
12352  {
12353         struct ath_softc *sc = (struct ath_softc *)arg;
12354         struct ath_hw *ah = sc->sc_ah;
12355 @@ -311,24 +271,18 @@ static int ath_init_btcoex_timer(struct
12356         struct ath_btcoex *btcoex = &sc->btcoex;
12357
12358         btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD;
12359 -       btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * 1000 *
12360 +       btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
12361                 btcoex->btcoex_period / 100;
12362 -       btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) * 1000 *
12363 +       btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) *
12364                                    btcoex->btcoex_period / 100;
12365
12366         setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
12367                         (unsigned long) sc);
12368 +       setup_timer(&btcoex->no_stomp_timer, ath_btcoex_no_stomp_timer,
12369 +                       (unsigned long) sc);
12370
12371         spin_lock_init(&btcoex->btcoex_lock);
12372
12373 -       btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
12374 -                       ath_btcoex_no_stomp_timer,
12375 -                       ath_btcoex_no_stomp_timer,
12376 -                       (void *) sc, AR_FIRST_NDP_TIMER);
12377 -
12378 -       if (!btcoex->no_stomp_timer)
12379 -               return -ENOMEM;
12380 -
12381         return 0;
12382  }
12383
12384 @@ -343,10 +297,7 @@ void ath9k_btcoex_timer_resume(struct at
12385         ath_dbg(ath9k_hw_common(ah), BTCOEX, "Starting btcoex timers\n");
12386
12387         /* make sure duty cycle timer is also stopped when resuming */
12388 -       if (btcoex->hw_timer_enabled) {
12389 -               ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
12390 -               btcoex->hw_timer_enabled = false;
12391 -       }
12392 +       del_timer_sync(&btcoex->no_stomp_timer);
12393
12394         btcoex->bt_priority_cnt = 0;
12395         btcoex->bt_priority_time = jiffies;
12396 @@ -363,24 +314,16 @@ void ath9k_btcoex_timer_resume(struct at
12397  void ath9k_btcoex_timer_pause(struct ath_softc *sc)
12398  {
12399         struct ath_btcoex *btcoex = &sc->btcoex;
12400 -       struct ath_hw *ah = sc->sc_ah;
12401
12402         del_timer_sync(&btcoex->period_timer);
12403 -
12404 -       if (btcoex->hw_timer_enabled) {
12405 -               ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
12406 -               btcoex->hw_timer_enabled = false;
12407 -       }
12408 +       del_timer_sync(&btcoex->no_stomp_timer);
12409  }
12410
12411  void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
12412  {
12413         struct ath_btcoex *btcoex = &sc->btcoex;
12414
12415 -       if (btcoex->hw_timer_enabled) {
12416 -               ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
12417 -               btcoex->hw_timer_enabled = false;
12418 -       }
12419 +       del_timer_sync(&btcoex->no_stomp_timer);
12420  }
12421
12422  u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen)
12423 @@ -400,12 +343,6 @@ u16 ath9k_btcoex_aggr_limit(struct ath_s
12424
12425  void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status)
12426  {
12427 -       struct ath_hw *ah = sc->sc_ah;
12428 -
12429 -       if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE)
12430 -               if (status & ATH9K_INT_GENTIMER)
12431 -                       ath_gen_timer_isr(sc->sc_ah);
12432 -
12433         if (status & ATH9K_INT_MCI)
12434                 ath_mci_intr(sc);
12435  }
12436 @@ -447,10 +384,6 @@ void ath9k_deinit_btcoex(struct ath_soft
12437  {
12438         struct ath_hw *ah = sc->sc_ah;
12439
12440 -        if ((sc->btcoex.no_stomp_timer) &&
12441 -           ath9k_hw_get_btcoex_scheme(sc->sc_ah) == ATH_BTCOEX_CFG_3WIRE)
12442 -               ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
12443 -
12444         if (ath9k_hw_mci_is_enabled(ah))
12445                 ath_mci_cleanup(sc);
12446  }
12447 --- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
12448 +++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
12449 @@ -70,11 +70,11 @@ static void ath9k_htc_beacon_config_sta(
12450         struct ath9k_beacon_state bs;
12451         enum ath9k_int imask = 0;
12452         int dtimperiod, dtimcount, sleepduration;
12453 -       int cfpperiod, cfpcount, bmiss_timeout;
12454 +       int bmiss_timeout;
12455         u32 nexttbtt = 0, intval, tsftu;
12456         __be32 htc_imask = 0;
12457         u64 tsf;
12458 -       int num_beacons, offset, dtim_dec_count, cfp_dec_count;
12459 +       int num_beacons, offset, dtim_dec_count;
12460         int ret __attribute__ ((unused));
12461         u8 cmd_rsp;
12462
12463 @@ -84,7 +84,7 @@ static void ath9k_htc_beacon_config_sta(
12464         bmiss_timeout = (ATH_DEFAULT_BMISS_LIMIT * bss_conf->beacon_interval);
12465
12466         /*
12467 -        * Setup dtim and cfp parameters according to
12468 +        * Setup dtim parameters according to
12469          * last beacon we received (which may be none).
12470          */
12471         dtimperiod = bss_conf->dtim_period;
12472 @@ -93,8 +93,6 @@ static void ath9k_htc_beacon_config_sta(
12473         dtimcount = 1;
12474         if (dtimcount >= dtimperiod)    /* NB: sanity check */
12475                 dtimcount = 0;
12476 -       cfpperiod = 1;                  /* NB: no PCF support yet */
12477 -       cfpcount = 0;
12478
12479         sleepduration = intval;
12480         if (sleepduration <= 0)
12481 @@ -102,7 +100,7 @@ static void ath9k_htc_beacon_config_sta(
12482
12483         /*
12484          * Pull nexttbtt forward to reflect the current
12485 -        * TSF and calculate dtim+cfp state for the result.
12486 +        * TSF and calculate dtim state for the result.
12487          */
12488         tsf = ath9k_hw_gettsf64(priv->ah);
12489         tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
12490 @@ -115,26 +113,14 @@ static void ath9k_htc_beacon_config_sta(
12491
12492         /* DTIM Beacon every dtimperiod Beacon */
12493         dtim_dec_count = num_beacons % dtimperiod;
12494 -       /* CFP every cfpperiod DTIM Beacon */
12495 -       cfp_dec_count = (num_beacons / dtimperiod) % cfpperiod;
12496 -       if (dtim_dec_count)
12497 -               cfp_dec_count++;
12498 -
12499         dtimcount -= dtim_dec_count;
12500         if (dtimcount < 0)
12501                 dtimcount += dtimperiod;
12502
12503 -       cfpcount -= cfp_dec_count;
12504 -       if (cfpcount < 0)
12505 -               cfpcount += cfpperiod;
12506 -
12507 -       bs.bs_intval = intval;
12508 -       bs.bs_nexttbtt = nexttbtt;
12509 -       bs.bs_dtimperiod = dtimperiod*intval;
12510 -       bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
12511 -       bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
12512 -       bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
12513 -       bs.bs_cfpmaxduration = 0;
12514 +       bs.bs_intval = TU_TO_USEC(intval);
12515 +       bs.bs_nexttbtt = TU_TO_USEC(nexttbtt);
12516 +       bs.bs_dtimperiod = dtimperiod * bs.bs_intval;
12517 +       bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount * bs.bs_intval;
12518
12519         /*
12520          * Calculate the number of consecutive beacons to miss* before taking
12521 @@ -161,7 +147,8 @@ static void ath9k_htc_beacon_config_sta(
12522          * XXX fixed at 100ms
12523          */
12524
12525 -       bs.bs_sleepduration = roundup(IEEE80211_MS_TO_TU(100), sleepduration);
12526 +       bs.bs_sleepduration = TU_TO_USEC(roundup(IEEE80211_MS_TO_TU(100),
12527 +                                                sleepduration));
12528         if (bs.bs_sleepduration > bs.bs_dtimperiod)
12529                 bs.bs_sleepduration = bs.bs_dtimperiod;
12530
12531 @@ -170,10 +157,8 @@ static void ath9k_htc_beacon_config_sta(
12532
12533         ath_dbg(common, CONFIG, "intval: %u tsf: %llu tsftu: %u\n",
12534                 intval, tsf, tsftu);
12535 -       ath_dbg(common, CONFIG,
12536 -               "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
12537 -               bs.bs_bmissthreshold, bs.bs_sleepduration,
12538 -               bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
12539 +       ath_dbg(common, CONFIG, "bmiss: %u sleep: %u\n",
12540 +               bs.bs_bmissthreshold, bs.bs_sleepduration);
12541
12542         /* Set the computed STA beacon timers */
12543
12544 --- a/drivers/net/wireless/ath/ath9k/mac.c
12545 +++ b/drivers/net/wireless/ath/ath9k/mac.c
12546 @@ -481,8 +481,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw
12547                             | AR_Q_MISC_CBR_INCR_DIS0);
12548                 value = (qi->tqi_readyTime -
12549                          (ah->config.sw_beacon_response_time -
12550 -                         ah->config.dma_beacon_response_time) -
12551 -                        ah->config.additional_swba_backoff) * 1024;
12552 +                         ah->config.dma_beacon_response_time)) * 1024;
12553                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
12554                           value | AR_Q_RDYTIMECFG_EN);
12555                 REG_SET_BIT(ah, AR_DMISC(q),
12556 @@ -550,25 +549,25 @@ int ath9k_hw_rxprocdesc(struct ath_hw *a
12557
12558         if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
12559                 rs->rs_rssi = ATH9K_RSSI_BAD;
12560 -               rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
12561 -               rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
12562 -               rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
12563 -               rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
12564 -               rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
12565 -               rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
12566 +               rs->rs_rssi_ctl[0] = ATH9K_RSSI_BAD;
12567 +               rs->rs_rssi_ctl[1] = ATH9K_RSSI_BAD;
12568 +               rs->rs_rssi_ctl[2] = ATH9K_RSSI_BAD;
12569 +               rs->rs_rssi_ext[0] = ATH9K_RSSI_BAD;
12570 +               rs->rs_rssi_ext[1] = ATH9K_RSSI_BAD;
12571 +               rs->rs_rssi_ext[2] = ATH9K_RSSI_BAD;
12572         } else {
12573                 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
12574 -               rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
12575 +               rs->rs_rssi_ctl[0] = MS(ads.ds_rxstatus0,
12576                                                 AR_RxRSSIAnt00);
12577 -               rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
12578 +               rs->rs_rssi_ctl[1] = MS(ads.ds_rxstatus0,
12579                                                 AR_RxRSSIAnt01);
12580 -               rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
12581 +               rs->rs_rssi_ctl[2] = MS(ads.ds_rxstatus0,
12582                                                 AR_RxRSSIAnt02);
12583 -               rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
12584 +               rs->rs_rssi_ext[0] = MS(ads.ds_rxstatus4,
12585                                                 AR_RxRSSIAnt10);
12586 -               rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
12587 +               rs->rs_rssi_ext[1] = MS(ads.ds_rxstatus4,
12588                                                 AR_RxRSSIAnt11);
12589 -               rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
12590 +               rs->rs_rssi_ext[2] = MS(ads.ds_rxstatus4,
12591                                                 AR_RxRSSIAnt12);
12592         }
12593         if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
12594 --- a/drivers/net/wireless/ath/ath9k/mac.h
12595 +++ b/drivers/net/wireless/ath/ath9k/mac.h
12596 @@ -133,12 +133,8 @@ struct ath_rx_status {
12597         u8 rs_rate;
12598         u8 rs_antenna;
12599         u8 rs_more;
12600 -       int8_t rs_rssi_ctl0;
12601 -       int8_t rs_rssi_ctl1;
12602 -       int8_t rs_rssi_ctl2;
12603 -       int8_t rs_rssi_ext0;
12604 -       int8_t rs_rssi_ext1;
12605 -       int8_t rs_rssi_ext2;
12606 +       int8_t rs_rssi_ctl[3];
12607 +       int8_t rs_rssi_ext[3];
12608         u8 rs_isaggr;
12609         u8 rs_firstaggr;
12610         u8 rs_moreaggr;
12611 --- a/drivers/net/wireless/ath/ath9k/mci.c
12612 +++ b/drivers/net/wireless/ath/ath9k/mci.c
12613 @@ -200,7 +200,7 @@ skip_tuning:
12614         if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
12615                 btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
12616
12617 -       btcoex->btcoex_no_stomp =  btcoex->btcoex_period * 1000 *
12618 +       btcoex->btcoex_no_stomp =  btcoex->btcoex_period *
12619                 (100 - btcoex->duty_cycle) / 100;
12620
12621         ath9k_hw_btcoex_enable(sc->sc_ah);
12622 --- a/drivers/net/wireless/ath/ath9k/recv.c
12623 +++ b/drivers/net/wireless/ath/ath9k/recv.c
12624 @@ -906,6 +906,7 @@ static void ath9k_process_rssi(struct at
12625         struct ath_hw *ah = common->ah;
12626         int last_rssi;
12627         int rssi = rx_stats->rs_rssi;
12628 +       int i, j;
12629
12630         /*
12631          * RSSI is not available for subframes in an A-MPDU.
12632 @@ -924,6 +925,20 @@ static void ath9k_process_rssi(struct at
12633                 return;
12634         }
12635
12636 +       for (i = 0, j = 0; i < ARRAY_SIZE(rx_stats->rs_rssi_ctl); i++) {
12637 +               s8 rssi;
12638 +
12639 +               if (!(ah->rxchainmask & BIT(i)))
12640 +                       continue;
12641 +
12642 +               rssi = rx_stats->rs_rssi_ctl[i];
12643 +               if (rssi != ATH9K_RSSI_BAD) {
12644 +                   rxs->chains |= BIT(j);
12645 +                   rxs->chain_signal[j] = ah->noise + rssi;
12646 +               }
12647 +               j++;
12648 +       }
12649 +
12650         /*
12651          * Update Beacon RSSI, this is used by ANI.
12652          */
12653 @@ -1073,14 +1088,14 @@ static int ath_process_fft(struct ath_so
12654                 fft_sample_40.channel_type = chan_type;
12655
12656                 if (chan_type == NL80211_CHAN_HT40PLUS) {
12657 -                       lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
12658 -                       upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ext0);
12659 +                       lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]);
12660 +                       upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ext[0]);
12661
12662                         fft_sample_40.lower_noise = ah->noise;
12663                         fft_sample_40.upper_noise = ext_nf;
12664                 } else {
12665 -                       lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ext0);
12666 -                       upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
12667 +                       lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ext[0]);
12668 +                       upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]);
12669
12670                         fft_sample_40.lower_noise = ext_nf;
12671                         fft_sample_40.upper_noise = ah->noise;
12672 @@ -1116,7 +1131,7 @@ static int ath_process_fft(struct ath_so
12673                 fft_sample_20.tlv.length = __cpu_to_be16(length);
12674                 fft_sample_20.freq = __cpu_to_be16(freq);
12675
12676 -               fft_sample_20.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
12677 +               fft_sample_20.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]);
12678                 fft_sample_20.noise = ah->noise;
12679
12680                 mag_info = ((struct ath_ht20_mag_info *)radar_info) - 1;