b1b5f470535de14f47f4461b77cc9a93c32eb68c
[openwrt.git] / package / kernel / mac80211 / patches / 300-pending_work.patch
1 --- a/drivers/net/wireless/ath/ath10k/mac.c
2 +++ b/drivers/net/wireless/ath/ath10k/mac.c
3 @@ -1351,12 +1351,12 @@ static int ath10k_update_channel_list(st
4                         ch->allow_vht = true;
5  
6                         ch->allow_ibss =
7 -                               !(channel->flags & IEEE80211_CHAN_NO_IBSS);
8 +                               !(channel->flags & IEEE80211_CHAN_NO_IR);
9  
10                         ch->ht40plus =
11                                 !(channel->flags & IEEE80211_CHAN_NO_HT40PLUS);
12  
13 -                       passive = channel->flags & IEEE80211_CHAN_PASSIVE_SCAN;
14 +                       passive = channel->flags & IEEE80211_CHAN_NO_IR;
15                         ch->passive = passive;
16  
17                         ch->freq = channel->center_freq;
18 --- a/drivers/net/wireless/ath/ath9k/Kconfig
19 +++ b/drivers/net/wireless/ath/ath9k/Kconfig
20 @@ -90,7 +90,7 @@ config ATH9K_DFS_CERTIFIED
21  
22  config ATH9K_TX99
23         bool "Atheros ath9k TX99 testing support"
24 -       depends on CFG80211_CERTIFICATION_ONUS
25 +       depends on ATH9K_DEBUGFS && CFG80211_CERTIFICATION_ONUS
26         default n
27         ---help---
28           Say N. This should only be enabled on systems undergoing
29 @@ -108,6 +108,14 @@ config ATH9K_TX99
30           be evaluated to meet the RF exposure limits set forth in the
31           governmental SAR regulations.
32  
33 +config ATH9K_WOW
34 +       bool "Wake on Wireless LAN support (EXPERIMENTAL)"
35 +       depends on ATH9K && PM
36 +       default n
37 +       ---help---
38 +         This option enables Wake on Wireless LAN support for certain cards.
39 +         Currently, AR9462 is supported.
40 +
41  config ATH9K_LEGACY_RATE_CONTROL
42         bool "Atheros ath9k rate control"
43         depends on ATH9K
44 --- a/drivers/net/wireless/ath/ath9k/Makefile
45 +++ b/drivers/net/wireless/ath/ath9k/Makefile
46 @@ -13,9 +13,9 @@ ath9k-$(CPTCFG_ATH9K_PCI) += pci.o
47  ath9k-$(CPTCFG_ATH9K_AHB) += ahb.o
48  ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o
49  ath9k-$(CPTCFG_ATH9K_DFS_DEBUGFS) += dfs_debug.o
50 -ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += \
51 -               dfs.o
52 -ath9k-$(CONFIG_PM_SLEEP) += wow.o
53 +ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += dfs.o
54 +ath9k-$(CPTCFG_ATH9K_TX99) += tx99.o
55 +ath9k-$(CPTCFG_ATH9K_WOW) += wow.o
56  
57  obj-$(CPTCFG_ATH9K) += ath9k.o
58  
59 @@ -41,6 +41,8 @@ ath9k_hw-y:=  \
60                 ar9003_eeprom.o \
61                 ar9003_paprd.o
62  
63 +ath9k_hw-$(CPTCFG_ATH9K_WOW) += ar9003_wow.o
64 +
65  ath9k_hw-$(CPTCFG_ATH9K_BTCOEX_SUPPORT) += btcoex.o \
66                                            ar9003_mci.o
67  obj-$(CPTCFG_ATH9K_HW) += ath9k_hw.o
68 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
69 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
70 @@ -17,6 +17,7 @@
71  #include "hw.h"
72  #include "ar9003_mac.h"
73  #include "ar9003_2p2_initvals.h"
74 +#include "ar9003_buffalo_initvals.h"
75  #include "ar9485_initvals.h"
76  #include "ar9340_initvals.h"
77  #include "ar9330_1p1_initvals.h"
78 @@ -26,6 +27,7 @@
79  #include "ar9462_2p0_initvals.h"
80  #include "ar9462_2p1_initvals.h"
81  #include "ar9565_1p0_initvals.h"
82 +#include "ar9565_1p1_initvals.h"
83  
84  /* General hardware code for the AR9003 hadware family */
85  
86 @@ -148,7 +150,11 @@ static void ar9003_hw_init_mode_regs(str
87                                 ar9340Modes_high_ob_db_tx_gain_table_1p0);
88  
89                 INIT_INI_ARRAY(&ah->iniModesFastClock,
90 -                               ar9340Modes_fast_clock_1p0);
91 +                              ar9340Modes_fast_clock_1p0);
92 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
93 +                              ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
94 +               INIT_INI_ARRAY(&ah->ini_dfs,
95 +                              ar9340_1p0_baseband_postamble_dfs_channel);
96  
97                 if (!ah->is_clk_25mhz)
98                         INIT_INI_ARRAY(&ah->iniAdditional,
99 @@ -187,17 +193,17 @@ static void ar9003_hw_init_mode_regs(str
100                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
101                                ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
102  
103 -               /* Load PCIE SERDES settings from INI */
104 -
105 -               /* Awake Setting */
106 -
107 -               INIT_INI_ARRAY(&ah->iniPcieSerdes,
108 -                               ar9485_1_1_pcie_phy_clkreq_disable_L1);
109 -
110 -               /* Sleep Setting */
111 -
112 -               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
113 -                               ar9485_1_1_pcie_phy_clkreq_disable_L1);
114 +               if (ah->config.no_pll_pwrsave) {
115 +                       INIT_INI_ARRAY(&ah->iniPcieSerdes,
116 +                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
117 +                       INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
118 +                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
119 +               } else {
120 +                       INIT_INI_ARRAY(&ah->iniPcieSerdes,
121 +                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
122 +                       INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
123 +                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
124 +               }
125         } else if (AR_SREV_9462_21(ah)) {
126                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
127                                ar9462_2p1_mac_core);
128 @@ -223,6 +229,10 @@ static void ar9003_hw_init_mode_regs(str
129                                ar9462_2p1_modes_fast_clock);
130                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
131                                ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
132 +               INIT_INI_ARRAY(&ah->iniPcieSerdes,
133 +                              ar9462_2p1_pciephy_clkreq_disable_L1);
134 +               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
135 +                              ar9462_2p1_pciephy_clkreq_disable_L1);
136         } else if (AR_SREV_9462_20(ah)) {
137  
138                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
139 @@ -247,18 +257,18 @@ static void ar9003_hw_init_mode_regs(str
140                                 ar9462_2p0_soc_postamble);
141  
142                 INIT_INI_ARRAY(&ah->iniModesRxGain,
143 -                               ar9462_common_rx_gain_table_2p0);
144 +                               ar9462_2p0_common_rx_gain);
145  
146                 /* Awake -> Sleep Setting */
147                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
148 -                              ar9462_pciephy_clkreq_disable_L1_2p0);
149 +                              ar9462_2p0_pciephy_clkreq_disable_L1);
150                 /* Sleep -> Awake Setting */
151                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
152 -                              ar9462_pciephy_clkreq_disable_L1_2p0);
153 +                              ar9462_2p0_pciephy_clkreq_disable_L1);
154  
155                 /* Fast clock modal settings */
156                 INIT_INI_ARRAY(&ah->iniModesFastClock,
157 -                               ar9462_modes_fast_clock_2p0);
158 +                               ar9462_2p0_modes_fast_clock);
159  
160                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
161                                ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
162 @@ -330,7 +340,46 @@ static void ar9003_hw_init_mode_regs(str
163                                 ar9580_1p0_low_ob_db_tx_gain_table);
164  
165                 INIT_INI_ARRAY(&ah->iniModesFastClock,
166 -                               ar9580_1p0_modes_fast_clock);
167 +                              ar9580_1p0_modes_fast_clock);
168 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
169 +                              ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
170 +               INIT_INI_ARRAY(&ah->ini_dfs,
171 +                              ar9580_1p0_baseband_postamble_dfs_channel);
172 +       } else if (AR_SREV_9565_11_OR_LATER(ah)) {
173 +               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
174 +                              ar9565_1p1_mac_core);
175 +               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
176 +                              ar9565_1p1_mac_postamble);
177 +
178 +               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
179 +                              ar9565_1p1_baseband_core);
180 +               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
181 +                              ar9565_1p1_baseband_postamble);
182 +
183 +               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
184 +                              ar9565_1p1_radio_core);
185 +               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
186 +                              ar9565_1p1_radio_postamble);
187 +
188 +               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
189 +                              ar9565_1p1_soc_preamble);
190 +               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
191 +                              ar9565_1p1_soc_postamble);
192 +
193 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
194 +                              ar9565_1p1_Common_rx_gain_table);
195 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
196 +                              ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
197 +
198 +               INIT_INI_ARRAY(&ah->iniPcieSerdes,
199 +                              ar9565_1p1_pciephy_clkreq_disable_L1);
200 +               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
201 +                              ar9565_1p1_pciephy_clkreq_disable_L1);
202 +
203 +               INIT_INI_ARRAY(&ah->iniModesFastClock,
204 +                               ar9565_1p1_modes_fast_clock);
205 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
206 +                              ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
207         } else if (AR_SREV_9565(ah)) {
208                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
209                                ar9565_1p0_mac_core);
210 @@ -411,7 +460,11 @@ static void ar9003_hw_init_mode_regs(str
211  
212                 /* Fast clock modal settings */
213                 INIT_INI_ARRAY(&ah->iniModesFastClock,
214 -                               ar9300Modes_fast_clock_2p2);
215 +                              ar9300Modes_fast_clock_2p2);
216 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
217 +                              ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
218 +               INIT_INI_ARRAY(&ah->ini_dfs,
219 +                              ar9300_2p2_baseband_postamble_dfs_channel);
220         }
221  }
222  
223 @@ -440,7 +493,10 @@ static void ar9003_tx_gain_table_mode0(s
224                         ar9462_2p1_modes_low_ob_db_tx_gain);
225         else if (AR_SREV_9462_20(ah))
226                 INIT_INI_ARRAY(&ah->iniModesTxGain,
227 -                       ar9462_modes_low_ob_db_tx_gain_table_2p0);
228 +                       ar9462_2p0_modes_low_ob_db_tx_gain);
229 +       else if (AR_SREV_9565_11(ah))
230 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
231 +                              ar9565_1p1_modes_low_ob_db_tx_gain_table);
232         else if (AR_SREV_9565(ah))
233                 INIT_INI_ARRAY(&ah->iniModesTxGain,
234                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
235 @@ -474,7 +530,10 @@ static void ar9003_tx_gain_table_mode1(s
236                         ar9462_2p1_modes_high_ob_db_tx_gain);
237         else if (AR_SREV_9462_20(ah))
238                 INIT_INI_ARRAY(&ah->iniModesTxGain,
239 -                       ar9462_modes_high_ob_db_tx_gain_table_2p0);
240 +                       ar9462_2p0_modes_high_ob_db_tx_gain);
241 +       else if (AR_SREV_9565_11(ah))
242 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
243 +                              ar9565_1p1_modes_high_ob_db_tx_gain_table);
244         else if (AR_SREV_9565(ah))
245                 INIT_INI_ARRAY(&ah->iniModesTxGain,
246                                ar9565_1p0_modes_high_ob_db_tx_gain_table);
247 @@ -500,6 +559,9 @@ static void ar9003_tx_gain_table_mode2(s
248         else if (AR_SREV_9580(ah))
249                 INIT_INI_ARRAY(&ah->iniModesTxGain,
250                         ar9580_1p0_low_ob_db_tx_gain_table);
251 +       else if (AR_SREV_9565_11(ah))
252 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
253 +                              ar9565_1p1_modes_low_ob_db_tx_gain_table);
254         else if (AR_SREV_9565(ah))
255                 INIT_INI_ARRAY(&ah->iniModesTxGain,
256                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
257 @@ -525,12 +587,20 @@ static void ar9003_tx_gain_table_mode3(s
258         else if (AR_SREV_9580(ah))
259                 INIT_INI_ARRAY(&ah->iniModesTxGain,
260                         ar9580_1p0_high_power_tx_gain_table);
261 +       else if (AR_SREV_9565_11(ah))
262 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
263 +                              ar9565_1p1_modes_high_power_tx_gain_table);
264         else if (AR_SREV_9565(ah))
265                 INIT_INI_ARRAY(&ah->iniModesTxGain,
266                                ar9565_1p0_modes_high_power_tx_gain_table);
267 -       else
268 -               INIT_INI_ARRAY(&ah->iniModesTxGain,
269 -                       ar9300Modes_high_power_tx_gain_table_2p2);
270 +       else {
271 +               if (ah->config.tx_gain_buffalo)
272 +                       INIT_INI_ARRAY(&ah->iniModesTxGain,
273 +                                      ar9300Modes_high_power_tx_gain_table_buffalo);
274 +               else
275 +                       INIT_INI_ARRAY(&ah->iniModesTxGain,
276 +                                      ar9300Modes_high_power_tx_gain_table_2p2);
277 +       }
278  }
279  
280  static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
281 @@ -546,7 +616,7 @@ static void ar9003_tx_gain_table_mode4(s
282                        ar9462_2p1_modes_mix_ob_db_tx_gain);
283         else if (AR_SREV_9462_20(ah))
284                 INIT_INI_ARRAY(&ah->iniModesTxGain,
285 -                      ar9462_modes_mix_ob_db_tx_gain_table_2p0);
286 +                      ar9462_2p0_modes_mix_ob_db_tx_gain);
287         else
288                 INIT_INI_ARRAY(&ah->iniModesTxGain,
289                         ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
290 @@ -581,6 +651,13 @@ static void ar9003_tx_gain_table_mode6(s
291                         ar9580_1p0_type6_tx_gain_table);
292  }
293  
294 +static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
295 +{
296 +       if (AR_SREV_9340(ah))
297 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
298 +                              ar9340_cus227_tx_gain_table_1p0);
299 +}
300 +
301  typedef void (*ath_txgain_tab)(struct ath_hw *ah);
302  
303  static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
304 @@ -593,6 +670,7 @@ static void ar9003_tx_gain_table_apply(s
305                 ar9003_tx_gain_table_mode4,
306                 ar9003_tx_gain_table_mode5,
307                 ar9003_tx_gain_table_mode6,
308 +               ar9003_tx_gain_table_mode7,
309         };
310         int idx = ar9003_hw_get_tx_gain_idx(ah);
311  
312 @@ -629,7 +707,10 @@ static void ar9003_rx_gain_table_mode0(s
313                                 ar9462_2p1_common_rx_gain);
314         else if (AR_SREV_9462_20(ah))
315                 INIT_INI_ARRAY(&ah->iniModesRxGain,
316 -                               ar9462_common_rx_gain_table_2p0);
317 +                               ar9462_2p0_common_rx_gain);
318 +       else if (AR_SREV_9565_11(ah))
319 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
320 +                              ar9565_1p1_Common_rx_gain_table);
321         else if (AR_SREV_9565(ah))
322                 INIT_INI_ARRAY(&ah->iniModesRxGain,
323                                ar9565_1p0_Common_rx_gain_table);
324 @@ -657,7 +738,7 @@ static void ar9003_rx_gain_table_mode1(s
325                         ar9462_2p1_common_wo_xlna_rx_gain);
326         else if (AR_SREV_9462_20(ah))
327                 INIT_INI_ARRAY(&ah->iniModesRxGain,
328 -                       ar9462_common_wo_xlna_rx_gain_table_2p0);
329 +                       ar9462_2p0_common_wo_xlna_rx_gain);
330         else if (AR_SREV_9550(ah)) {
331                 INIT_INI_ARRAY(&ah->iniModesRxGain,
332                         ar955x_1p0_common_wo_xlna_rx_gain_table);
333 @@ -666,6 +747,9 @@ static void ar9003_rx_gain_table_mode1(s
334         } else if (AR_SREV_9580(ah))
335                 INIT_INI_ARRAY(&ah->iniModesRxGain,
336                         ar9580_1p0_wo_xlna_rx_gain_table);
337 +       else if (AR_SREV_9565_11(ah))
338 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
339 +                              ar9565_1p1_common_wo_xlna_rx_gain_table);
340         else if (AR_SREV_9565(ah))
341                 INIT_INI_ARRAY(&ah->iniModesRxGain,
342                                ar9565_1p0_common_wo_xlna_rx_gain_table);
343 @@ -687,7 +771,7 @@ static void ar9003_rx_gain_table_mode2(s
344                                ar9462_2p1_baseband_postamble_5g_xlna);
345         } else if (AR_SREV_9462_20(ah)) {
346                 INIT_INI_ARRAY(&ah->iniModesRxGain,
347 -                              ar9462_common_mixed_rx_gain_table_2p0);
348 +                              ar9462_2p0_common_mixed_rx_gain);
349                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
350                                ar9462_2p0_baseband_core_mix_rxgain);
351                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
352 @@ -701,12 +785,12 @@ static void ar9003_rx_gain_table_mode3(s
353  {
354         if (AR_SREV_9462_21(ah)) {
355                 INIT_INI_ARRAY(&ah->iniModesRxGain,
356 -                              ar9462_2p1_common_5g_xlna_only_rx_gain);
357 +                              ar9462_2p1_common_5g_xlna_only_rxgain);
358                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
359                                ar9462_2p1_baseband_postamble_5g_xlna);
360         } else if (AR_SREV_9462_20(ah)) {
361                 INIT_INI_ARRAY(&ah->iniModesRxGain,
362 -                              ar9462_2p0_5g_xlna_only_rxgain);
363 +                              ar9462_2p0_common_5g_xlna_only_rxgain);
364                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
365                                ar9462_2p0_baseband_postamble_5g_xlna);
366         }
367 @@ -750,6 +834,9 @@ static void ar9003_hw_init_mode_gain_reg
368  static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
369                                          bool power_off)
370  {
371 +       unsigned int i;
372 +       struct ar5416IniArray *array;
373 +
374         /*
375          * Increase L1 Entry Latency. Some WB222 boards don't have
376          * this change in eeprom/OTP.
377 @@ -775,18 +862,13 @@ static void ar9003_hw_configpcipowersave
378          * Configire PCIE after Ini init. SERDES values now come from ini file
379          * This enables PCIe low power mode.
380          */
381 -       if (ah->config.pcieSerDesWrite) {
382 -               unsigned int i;
383 -               struct ar5416IniArray *array;
384 -
385 -               array = power_off ? &ah->iniPcieSerdes :
386 -                                   &ah->iniPcieSerdesLowPower;
387 -
388 -               for (i = 0; i < array->ia_rows; i++) {
389 -                       REG_WRITE(ah,
390 -                                 INI_RA(array, i, 0),
391 -                                 INI_RA(array, i, 1));
392 -               }
393 +       array = power_off ? &ah->iniPcieSerdes :
394 +               &ah->iniPcieSerdesLowPower;
395 +
396 +       for (i = 0; i < array->ia_rows; i++) {
397 +               REG_WRITE(ah,
398 +                         INI_RA(array, i, 0),
399 +                         INI_RA(array, i, 1));
400         }
401  }
402  
403 --- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
404 +++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
405 @@ -18,6 +18,20 @@
406  #ifndef INITVALS_9340_H
407  #define INITVALS_9340_H
408  
409 +#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
410 +
411 +#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
412 +
413 +#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
414 +
415 +#define ar9340Common_rx_gain_table_1p0 ar9300Common_rx_gain_table_2p2
416 +
417 +#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
418 +
419 +#define ar9340_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
420 +
421 +#define ar9340_1p0_baseband_postamble_dfs_channel ar9300_2p2_baseband_postamble_dfs_channel
422 +
423  static const u32 ar9340_1p0_radio_postamble[][5] = {
424         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
425         {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
426 @@ -100,8 +114,6 @@ static const u32 ar9340Modes_lowest_ob_d
427         {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
428  };
429  
430 -#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
431 -
432  static const u32 ar9340_1p0_radio_core[][2] = {
433         /* Addr      allmodes  */
434         {0x00016000, 0x36db6db6},
435 @@ -215,16 +227,12 @@ static const u32 ar9340_1p0_radio_core_4
436         {0x0000824c, 0x0001e800},
437  };
438  
439 -#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
440 -
441 -#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
442 -
443  static const u32 ar9340_1p0_baseband_postamble[][5] = {
444         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
445         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
446         {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e},
447         {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
448 -       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
449 +       {0x00009828, 0x06903081, 0x06903081, 0x09103881, 0x09103881},
450         {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
451         {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
452         {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
453 @@ -340,9 +348,9 @@ static const u32 ar9340_1p0_baseband_cor
454         {0x0000a370, 0x00000000},
455         {0x0000a390, 0x00000001},
456         {0x0000a394, 0x00000444},
457 -       {0x0000a398, 0x001f0e0f},
458 -       {0x0000a39c, 0x0075393f},
459 -       {0x0000a3a0, 0xb79f6427},
460 +       {0x0000a398, 0x00000000},
461 +       {0x0000a39c, 0x210d0401},
462 +       {0x0000a3a0, 0xab9a7144},
463         {0x0000a3a4, 0x00000000},
464         {0x0000a3a8, 0xaaaaaaaa},
465         {0x0000a3ac, 0x3c466478},
466 @@ -714,266 +722,6 @@ static const u32 ar9340Modes_ub124_tx_ga
467         {0x0000b2e8, 0xfffe0000, 0xfffe0000, 0xfffc0000, 0xfffc0000},
468  };
469  
470 -static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
471 -       /* Addr      allmodes  */
472 -       {0x0000a000, 0x00010000},
473 -       {0x0000a004, 0x00030002},
474 -       {0x0000a008, 0x00050004},
475 -       {0x0000a00c, 0x00810080},
476 -       {0x0000a010, 0x00830082},
477 -       {0x0000a014, 0x01810180},
478 -       {0x0000a018, 0x01830182},
479 -       {0x0000a01c, 0x01850184},
480 -       {0x0000a020, 0x01890188},
481 -       {0x0000a024, 0x018b018a},
482 -       {0x0000a028, 0x018d018c},
483 -       {0x0000a02c, 0x01910190},
484 -       {0x0000a030, 0x01930192},
485 -       {0x0000a034, 0x01950194},
486 -       {0x0000a038, 0x038a0196},
487 -       {0x0000a03c, 0x038c038b},
488 -       {0x0000a040, 0x0390038d},
489 -       {0x0000a044, 0x03920391},
490 -       {0x0000a048, 0x03940393},
491 -       {0x0000a04c, 0x03960395},
492 -       {0x0000a050, 0x00000000},
493 -       {0x0000a054, 0x00000000},
494 -       {0x0000a058, 0x00000000},
495 -       {0x0000a05c, 0x00000000},
496 -       {0x0000a060, 0x00000000},
497 -       {0x0000a064, 0x00000000},
498 -       {0x0000a068, 0x00000000},
499 -       {0x0000a06c, 0x00000000},
500 -       {0x0000a070, 0x00000000},
501 -       {0x0000a074, 0x00000000},
502 -       {0x0000a078, 0x00000000},
503 -       {0x0000a07c, 0x00000000},
504 -       {0x0000a080, 0x22222229},
505 -       {0x0000a084, 0x1d1d1d1d},
506 -       {0x0000a088, 0x1d1d1d1d},
507 -       {0x0000a08c, 0x1d1d1d1d},
508 -       {0x0000a090, 0x171d1d1d},
509 -       {0x0000a094, 0x11111717},
510 -       {0x0000a098, 0x00030311},
511 -       {0x0000a09c, 0x00000000},
512 -       {0x0000a0a0, 0x00000000},
513 -       {0x0000a0a4, 0x00000000},
514 -       {0x0000a0a8, 0x00000000},
515 -       {0x0000a0ac, 0x00000000},
516 -       {0x0000a0b0, 0x00000000},
517 -       {0x0000a0b4, 0x00000000},
518 -       {0x0000a0b8, 0x00000000},
519 -       {0x0000a0bc, 0x00000000},
520 -       {0x0000a0c0, 0x001f0000},
521 -       {0x0000a0c4, 0x01000101},
522 -       {0x0000a0c8, 0x011e011f},
523 -       {0x0000a0cc, 0x011c011d},
524 -       {0x0000a0d0, 0x02030204},
525 -       {0x0000a0d4, 0x02010202},
526 -       {0x0000a0d8, 0x021f0200},
527 -       {0x0000a0dc, 0x0302021e},
528 -       {0x0000a0e0, 0x03000301},
529 -       {0x0000a0e4, 0x031e031f},
530 -       {0x0000a0e8, 0x0402031d},
531 -       {0x0000a0ec, 0x04000401},
532 -       {0x0000a0f0, 0x041e041f},
533 -       {0x0000a0f4, 0x0502041d},
534 -       {0x0000a0f8, 0x05000501},
535 -       {0x0000a0fc, 0x051e051f},
536 -       {0x0000a100, 0x06010602},
537 -       {0x0000a104, 0x061f0600},
538 -       {0x0000a108, 0x061d061e},
539 -       {0x0000a10c, 0x07020703},
540 -       {0x0000a110, 0x07000701},
541 -       {0x0000a114, 0x00000000},
542 -       {0x0000a118, 0x00000000},
543 -       {0x0000a11c, 0x00000000},
544 -       {0x0000a120, 0x00000000},
545 -       {0x0000a124, 0x00000000},
546 -       {0x0000a128, 0x00000000},
547 -       {0x0000a12c, 0x00000000},
548 -       {0x0000a130, 0x00000000},
549 -       {0x0000a134, 0x00000000},
550 -       {0x0000a138, 0x00000000},
551 -       {0x0000a13c, 0x00000000},
552 -       {0x0000a140, 0x001f0000},
553 -       {0x0000a144, 0x01000101},
554 -       {0x0000a148, 0x011e011f},
555 -       {0x0000a14c, 0x011c011d},
556 -       {0x0000a150, 0x02030204},
557 -       {0x0000a154, 0x02010202},
558 -       {0x0000a158, 0x021f0200},
559 -       {0x0000a15c, 0x0302021e},
560 -       {0x0000a160, 0x03000301},
561 -       {0x0000a164, 0x031e031f},
562 -       {0x0000a168, 0x0402031d},
563 -       {0x0000a16c, 0x04000401},
564 -       {0x0000a170, 0x041e041f},
565 -       {0x0000a174, 0x0502041d},
566 -       {0x0000a178, 0x05000501},
567 -       {0x0000a17c, 0x051e051f},
568 -       {0x0000a180, 0x06010602},
569 -       {0x0000a184, 0x061f0600},
570 -       {0x0000a188, 0x061d061e},
571 -       {0x0000a18c, 0x07020703},
572 -       {0x0000a190, 0x07000701},
573 -       {0x0000a194, 0x00000000},
574 -       {0x0000a198, 0x00000000},
575 -       {0x0000a19c, 0x00000000},
576 -       {0x0000a1a0, 0x00000000},
577 -       {0x0000a1a4, 0x00000000},
578 -       {0x0000a1a8, 0x00000000},
579 -       {0x0000a1ac, 0x00000000},
580 -       {0x0000a1b0, 0x00000000},
581 -       {0x0000a1b4, 0x00000000},
582 -       {0x0000a1b8, 0x00000000},
583 -       {0x0000a1bc, 0x00000000},
584 -       {0x0000a1c0, 0x00000000},
585 -       {0x0000a1c4, 0x00000000},
586 -       {0x0000a1c8, 0x00000000},
587 -       {0x0000a1cc, 0x00000000},
588 -       {0x0000a1d0, 0x00000000},
589 -       {0x0000a1d4, 0x00000000},
590 -       {0x0000a1d8, 0x00000000},
591 -       {0x0000a1dc, 0x00000000},
592 -       {0x0000a1e0, 0x00000000},
593 -       {0x0000a1e4, 0x00000000},
594 -       {0x0000a1e8, 0x00000000},
595 -       {0x0000a1ec, 0x00000000},
596 -       {0x0000a1f0, 0x00000396},
597 -       {0x0000a1f4, 0x00000396},
598 -       {0x0000a1f8, 0x00000396},
599 -       {0x0000a1fc, 0x00000196},
600 -       {0x0000b000, 0x00010000},
601 -       {0x0000b004, 0x00030002},
602 -       {0x0000b008, 0x00050004},
603 -       {0x0000b00c, 0x00810080},
604 -       {0x0000b010, 0x00830082},
605 -       {0x0000b014, 0x01810180},
606 -       {0x0000b018, 0x01830182},
607 -       {0x0000b01c, 0x01850184},
608 -       {0x0000b020, 0x02810280},
609 -       {0x0000b024, 0x02830282},
610 -       {0x0000b028, 0x02850284},
611 -       {0x0000b02c, 0x02890288},
612 -       {0x0000b030, 0x028b028a},
613 -       {0x0000b034, 0x0388028c},
614 -       {0x0000b038, 0x038a0389},
615 -       {0x0000b03c, 0x038c038b},
616 -       {0x0000b040, 0x0390038d},
617 -       {0x0000b044, 0x03920391},
618 -       {0x0000b048, 0x03940393},
619 -       {0x0000b04c, 0x03960395},
620 -       {0x0000b050, 0x00000000},
621 -       {0x0000b054, 0x00000000},
622 -       {0x0000b058, 0x00000000},
623 -       {0x0000b05c, 0x00000000},
624 -       {0x0000b060, 0x00000000},
625 -       {0x0000b064, 0x00000000},
626 -       {0x0000b068, 0x00000000},
627 -       {0x0000b06c, 0x00000000},
628 -       {0x0000b070, 0x00000000},
629 -       {0x0000b074, 0x00000000},
630 -       {0x0000b078, 0x00000000},
631 -       {0x0000b07c, 0x00000000},
632 -       {0x0000b080, 0x23232323},
633 -       {0x0000b084, 0x21232323},
634 -       {0x0000b088, 0x19191c1e},
635 -       {0x0000b08c, 0x12141417},
636 -       {0x0000b090, 0x07070e0e},
637 -       {0x0000b094, 0x03030305},
638 -       {0x0000b098, 0x00000003},
639 -       {0x0000b09c, 0x00000000},
640 -       {0x0000b0a0, 0x00000000},
641 -       {0x0000b0a4, 0x00000000},
642 -       {0x0000b0a8, 0x00000000},
643 -       {0x0000b0ac, 0x00000000},
644 -       {0x0000b0b0, 0x00000000},
645 -       {0x0000b0b4, 0x00000000},
646 -       {0x0000b0b8, 0x00000000},
647 -       {0x0000b0bc, 0x00000000},
648 -       {0x0000b0c0, 0x003f0020},
649 -       {0x0000b0c4, 0x00400041},
650 -       {0x0000b0c8, 0x0140005f},
651 -       {0x0000b0cc, 0x0160015f},
652 -       {0x0000b0d0, 0x017e017f},
653 -       {0x0000b0d4, 0x02410242},
654 -       {0x0000b0d8, 0x025f0240},
655 -       {0x0000b0dc, 0x027f0260},
656 -       {0x0000b0e0, 0x0341027e},
657 -       {0x0000b0e4, 0x035f0340},
658 -       {0x0000b0e8, 0x037f0360},
659 -       {0x0000b0ec, 0x04400441},
660 -       {0x0000b0f0, 0x0460045f},
661 -       {0x0000b0f4, 0x0541047f},
662 -       {0x0000b0f8, 0x055f0540},
663 -       {0x0000b0fc, 0x057f0560},
664 -       {0x0000b100, 0x06400641},
665 -       {0x0000b104, 0x0660065f},
666 -       {0x0000b108, 0x067e067f},
667 -       {0x0000b10c, 0x07410742},
668 -       {0x0000b110, 0x075f0740},
669 -       {0x0000b114, 0x077f0760},
670 -       {0x0000b118, 0x07800781},
671 -       {0x0000b11c, 0x07a0079f},
672 -       {0x0000b120, 0x07c107bf},
673 -       {0x0000b124, 0x000007c0},
674 -       {0x0000b128, 0x00000000},
675 -       {0x0000b12c, 0x00000000},
676 -       {0x0000b130, 0x00000000},
677 -       {0x0000b134, 0x00000000},
678 -       {0x0000b138, 0x00000000},
679 -       {0x0000b13c, 0x00000000},
680 -       {0x0000b140, 0x003f0020},
681 -       {0x0000b144, 0x00400041},
682 -       {0x0000b148, 0x0140005f},
683 -       {0x0000b14c, 0x0160015f},
684 -       {0x0000b150, 0x017e017f},
685 -       {0x0000b154, 0x02410242},
686 -       {0x0000b158, 0x025f0240},
687 -       {0x0000b15c, 0x027f0260},
688 -       {0x0000b160, 0x0341027e},
689 -       {0x0000b164, 0x035f0340},
690 -       {0x0000b168, 0x037f0360},
691 -       {0x0000b16c, 0x04400441},
692 -       {0x0000b170, 0x0460045f},
693 -       {0x0000b174, 0x0541047f},
694 -       {0x0000b178, 0x055f0540},
695 -       {0x0000b17c, 0x057f0560},
696 -       {0x0000b180, 0x06400641},
697 -       {0x0000b184, 0x0660065f},
698 -       {0x0000b188, 0x067e067f},
699 -       {0x0000b18c, 0x07410742},
700 -       {0x0000b190, 0x075f0740},
701 -       {0x0000b194, 0x077f0760},
702 -       {0x0000b198, 0x07800781},
703 -       {0x0000b19c, 0x07a0079f},
704 -       {0x0000b1a0, 0x07c107bf},
705 -       {0x0000b1a4, 0x000007c0},
706 -       {0x0000b1a8, 0x00000000},
707 -       {0x0000b1ac, 0x00000000},
708 -       {0x0000b1b0, 0x00000000},
709 -       {0x0000b1b4, 0x00000000},
710 -       {0x0000b1b8, 0x00000000},
711 -       {0x0000b1bc, 0x00000000},
712 -       {0x0000b1c0, 0x00000000},
713 -       {0x0000b1c4, 0x00000000},
714 -       {0x0000b1c8, 0x00000000},
715 -       {0x0000b1cc, 0x00000000},
716 -       {0x0000b1d0, 0x00000000},
717 -       {0x0000b1d4, 0x00000000},
718 -       {0x0000b1d8, 0x00000000},
719 -       {0x0000b1dc, 0x00000000},
720 -       {0x0000b1e0, 0x00000000},
721 -       {0x0000b1e4, 0x00000000},
722 -       {0x0000b1e8, 0x00000000},
723 -       {0x0000b1ec, 0x00000000},
724 -       {0x0000b1f0, 0x00000396},
725 -       {0x0000b1f4, 0x00000396},
726 -       {0x0000b1f8, 0x00000396},
727 -       {0x0000b1fc, 0x00000196},
728 -};
729 -
730  static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
731         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
732         {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
733 @@ -1437,8 +1185,6 @@ static const u32 ar9340_1p0_mac_core[][2
734         {0x000083d0, 0x000101ff},
735  };
736  
737 -#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
738 -
739  static const u32 ar9340_1p0_soc_preamble[][2] = {
740         /* Addr      allmodes  */
741         {0x00007008, 0x00000000},
742 @@ -1447,4 +1193,106 @@ static const u32 ar9340_1p0_soc_preamble
743         {0x00007038, 0x000004c2},
744  };
745  
746 +static const u32 ar9340_cus227_tx_gain_table_1p0[][5] = {
747 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
748 +       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
749 +       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
750 +       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
751 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
752 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
753 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
754 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
755 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
756 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
757 +       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
758 +       {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400},
759 +       {0x0000a518, 0x21002220, 0x21002220, 0x15000402, 0x15000402},
760 +       {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
761 +       {0x0000a520, 0x2c022220, 0x2c022220, 0x1b000603, 0x1b000603},
762 +       {0x0000a524, 0x30022222, 0x30022222, 0x1f000a02, 0x1f000a02},
763 +       {0x0000a528, 0x35022225, 0x35022225, 0x23000a04, 0x23000a04},
764 +       {0x0000a52c, 0x3b02222a, 0x3b02222a, 0x26000a20, 0x26000a20},
765 +       {0x0000a530, 0x3f02222c, 0x3f02222c, 0x2a000e20, 0x2a000e20},
766 +       {0x0000a534, 0x4202242a, 0x4202242a, 0x2e000e22, 0x2e000e22},
767 +       {0x0000a538, 0x4702244a, 0x4702244a, 0x31000e24, 0x31000e24},
768 +       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x34001640, 0x34001640},
769 +       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660},
770 +       {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861},
771 +       {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81},
772 +       {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x42001a83, 0x42001a83},
773 +       {0x0000a550, 0x61024a6c, 0x61024a6c, 0x44001c84, 0x44001c84},
774 +       {0x0000a554, 0x66026a6c, 0x66026a6c, 0x48001ce3, 0x48001ce3},
775 +       {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x4c001ce5, 0x4c001ce5},
776 +       {0x0000a55c, 0x7002708c, 0x7002708c, 0x50001ce9, 0x50001ce9},
777 +       {0x0000a560, 0x7302b08a, 0x7302b08a, 0x54001ceb, 0x54001ceb},
778 +       {0x0000a564, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
779 +       {0x0000a568, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
780 +       {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
781 +       {0x0000a570, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
782 +       {0x0000a574, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
783 +       {0x0000a578, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
784 +       {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
785 +       {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
786 +       {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
787 +       {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
788 +       {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
789 +       {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
790 +       {0x0000a594, 0x1c800223, 0x1c800223, 0x11800400, 0x11800400},
791 +       {0x0000a598, 0x21820220, 0x21820220, 0x15800402, 0x15800402},
792 +       {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
793 +       {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800603, 0x1b800603},
794 +       {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800a02, 0x1f800a02},
795 +       {0x0000a5a8, 0x34822225, 0x34822225, 0x23800a04, 0x23800a04},
796 +       {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x26800a20, 0x26800a20},
797 +       {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2a800e20, 0x2a800e20},
798 +       {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2e800e22, 0x2e800e22},
799 +       {0x0000a5b8, 0x4782244a, 0x4782244a, 0x31800e24, 0x31800e24},
800 +       {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x34801640, 0x34801640},
801 +       {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38801660, 0x38801660},
802 +       {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3b801861, 0x3b801861},
803 +       {0x0000a5c8, 0x5782286c, 0x5782286c, 0x3e801a81, 0x3e801a81},
804 +       {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x42801a83, 0x42801a83},
805 +       {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x44801c84, 0x44801c84},
806 +       {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x48801ce3, 0x48801ce3},
807 +       {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x4c801ce5, 0x4c801ce5},
808 +       {0x0000a5dc, 0x7086308c, 0x7086308c, 0x50801ce9, 0x50801ce9},
809 +       {0x0000a5e0, 0x738a308a, 0x738a308a, 0x54801ceb, 0x54801ceb},
810 +       {0x0000a5e4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
811 +       {0x0000a5e8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
812 +       {0x0000a5ec, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
813 +       {0x0000a5f0, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
814 +       {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
815 +       {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
816 +       {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
817 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
818 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
819 +       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
820 +       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
821 +       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
822 +       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
823 +       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
824 +       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
825 +       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
826 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
827 +       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
828 +       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
829 +       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
830 +       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
831 +       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
832 +       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
833 +       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
834 +       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
835 +       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
836 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
837 +       {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
838 +       {0x00016048, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
839 +       {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
840 +       {0x00016288, 0x30318000, 0x30318000, 0x00318000, 0x00318000},
841 +       {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
842 +       {0x00016448, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
843 +       {0x0000a3a4, 0x00000011, 0x00000011, 0x00000011, 0x00000011},
844 +       {0x0000a3a8, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c},
845 +       {0x0000a3ac, 0x30303030, 0x30303030, 0x30303030, 0x30303030},
846 +};
847 +
848  #endif /* INITVALS_9340_H */
849 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
850 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
851 @@ -459,6 +459,7 @@ void ath_check_ani(struct ath_softc *sc)
852  int ath_update_survey_stats(struct ath_softc *sc);
853  void ath_update_survey_nf(struct ath_softc *sc, int channel);
854  void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
855 +void ath_ps_full_sleep(unsigned long data);
856  
857  /**********/
858  /* BTCOEX */
859 @@ -476,20 +477,19 @@ enum bt_op_flags {
860  };
861  
862  struct ath_btcoex {
863 -       bool hw_timer_enabled;
864         spinlock_t btcoex_lock;
865         struct timer_list period_timer; /* Timer for BT period */
866 +       struct timer_list no_stomp_timer;
867         u32 bt_priority_cnt;
868         unsigned long bt_priority_time;
869         unsigned long op_flags;
870         int bt_stomp_type; /* Types of BT stomping */
871 -       u32 btcoex_no_stomp; /* in usec */
872 +       u32 btcoex_no_stomp; /* in msec */
873         u32 btcoex_period; /* in msec */
874 -       u32 btscan_no_stomp; /* in usec */
875 +       u32 btscan_no_stomp; /* in msec */
876         u32 duty_cycle;
877         u32 bt_wait_time;
878         int rssi_count;
879 -       struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
880         struct ath_mci_profile mci;
881         u8 stomp_audio;
882  };
883 @@ -570,6 +570,34 @@ static inline void ath_fill_led_pin(stru
884  }
885  #endif
886  
887 +/************************/
888 +/* Wake on Wireless LAN */
889 +/************************/
890 +
891 +#ifdef CONFIG_ATH9K_WOW
892 +void ath9k_init_wow(struct ieee80211_hw *hw);
893 +int ath9k_suspend(struct ieee80211_hw *hw,
894 +                 struct cfg80211_wowlan *wowlan);
895 +int ath9k_resume(struct ieee80211_hw *hw);
896 +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
897 +#else
898 +static inline void ath9k_init_wow(struct ieee80211_hw *hw)
899 +{
900 +}
901 +static inline int ath9k_suspend(struct ieee80211_hw *hw,
902 +                               struct cfg80211_wowlan *wowlan)
903 +{
904 +       return 0;
905 +}
906 +static inline int ath9k_resume(struct ieee80211_hw *hw)
907 +{
908 +       return 0;
909 +}
910 +static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
911 +{
912 +}
913 +#endif /* CONFIG_ATH9K_WOW */
914 +
915  /*******************************/
916  /* Antenna diversity/combining */
917  /*******************************/
918 @@ -632,15 +660,16 @@ void ath_ant_comb_scan(struct ath_softc 
919  /* Main driver core */
920  /********************/
921  
922 -#define ATH9K_PCI_CUS198      0x0001
923 -#define ATH9K_PCI_CUS230      0x0002
924 -#define ATH9K_PCI_CUS217      0x0004
925 -#define ATH9K_PCI_CUS252      0x0008
926 -#define ATH9K_PCI_WOW         0x0010
927 -#define ATH9K_PCI_BT_ANT_DIV  0x0020
928 -#define ATH9K_PCI_D3_L1_WAR   0x0040
929 -#define ATH9K_PCI_AR9565_1ANT 0x0080
930 -#define ATH9K_PCI_AR9565_2ANT 0x0100
931 +#define ATH9K_PCI_CUS198          0x0001
932 +#define ATH9K_PCI_CUS230          0x0002
933 +#define ATH9K_PCI_CUS217          0x0004
934 +#define ATH9K_PCI_CUS252          0x0008
935 +#define ATH9K_PCI_WOW             0x0010
936 +#define ATH9K_PCI_BT_ANT_DIV      0x0020
937 +#define ATH9K_PCI_D3_L1_WAR       0x0040
938 +#define ATH9K_PCI_AR9565_1ANT     0x0080
939 +#define ATH9K_PCI_AR9565_2ANT     0x0100
940 +#define ATH9K_PCI_NO_PLL_PWRSAVE  0x0200
941  
942  /*
943   * Default cache line size, in bytes.
944 @@ -723,6 +752,7 @@ struct ath_softc {
945         struct work_struct hw_check_work;
946         struct work_struct hw_reset_work;
947         struct completion paprd_complete;
948 +       wait_queue_head_t tx_wait;
949  
950         unsigned int hw_busy_count;
951         unsigned long sc_flags;
952 @@ -759,6 +789,7 @@ struct ath_softc {
953         struct delayed_work tx_complete_work;
954         struct delayed_work hw_pll_work;
955         struct timer_list rx_poll_timer;
956 +       struct timer_list sleep_timer;
957  
958  #ifdef CPTCFG_ATH9K_BTCOEX_SUPPORT
959         struct ath_btcoex btcoex;
960 @@ -783,7 +814,7 @@ struct ath_softc {
961         bool tx99_state;
962         s16 tx99_power;
963  
964 -#ifdef CONFIG_PM_SLEEP
965 +#ifdef CONFIG_ATH9K_WOW
966         atomic_t wow_got_bmiss_intr;
967         atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
968         u32 wow_intr_before_sleep;
969 @@ -946,10 +977,25 @@ struct fft_sample_ht20_40 {
970         u8 data[SPECTRAL_HT20_40_NUM_BINS];
971  } __packed;
972  
973 -int ath9k_tx99_init(struct ath_softc *sc);
974 -void ath9k_tx99_deinit(struct ath_softc *sc);
975 +/********/
976 +/* TX99 */
977 +/********/
978 +
979 +#ifdef CONFIG_ATH9K_TX99
980 +void ath9k_tx99_init_debug(struct ath_softc *sc);
981  int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
982                     struct ath_tx_control *txctl);
983 +#else
984 +static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
985 +{
986 +}
987 +static inline int ath9k_tx99_send(struct ath_softc *sc,
988 +                                 struct sk_buff *skb,
989 +                                 struct ath_tx_control *txctl)
990 +{
991 +       return 0;
992 +}
993 +#endif /* CONFIG_ATH9K_TX99 */
994  
995  void ath9k_tasklet(unsigned long data);
996  int ath_cabq_update(struct ath_softc *);
997 @@ -966,6 +1012,9 @@ extern bool is_ath9k_unloaded;
998  
999  u8 ath9k_parse_mpdudensity(u8 mpdudensity);
1000  irqreturn_t ath_isr(int irq, void *dev);
1001 +int ath_reset(struct ath_softc *sc);
1002 +void ath_cancel_work(struct ath_softc *sc);
1003 +void ath_restart_work(struct ath_softc *sc);
1004  int ath9k_init_device(u16 devid, struct ath_softc *sc,
1005                     const struct ath_bus_ops *bus_ops);
1006  void ath9k_deinit_device(struct ath_softc *sc);
1007 --- a/drivers/net/wireless/ath/ath9k/debug.c
1008 +++ b/drivers/net/wireless/ath/ath9k/debug.c
1009 @@ -1782,111 +1782,6 @@ void ath9k_deinit_debug(struct ath_softc
1010         }
1011  }
1012  
1013 -static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
1014 -                             size_t count, loff_t *ppos)
1015 -{
1016 -       struct ath_softc *sc = file->private_data;
1017 -       char buf[3];
1018 -       unsigned int len;
1019 -
1020 -       len = sprintf(buf, "%d\n", sc->tx99_state);
1021 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1022 -}
1023 -
1024 -static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
1025 -                              size_t count, loff_t *ppos)
1026 -{
1027 -       struct ath_softc *sc = file->private_data;
1028 -       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1029 -       char buf[32];
1030 -       bool start;
1031 -       ssize_t len;
1032 -       int r;
1033 -
1034 -       if (sc->nvifs > 1)
1035 -               return -EOPNOTSUPP;
1036 -
1037 -       len = min(count, sizeof(buf) - 1);
1038 -       if (copy_from_user(buf, user_buf, len))
1039 -               return -EFAULT;
1040 -
1041 -       if (strtobool(buf, &start))
1042 -               return -EINVAL;
1043 -
1044 -       if (start == sc->tx99_state) {
1045 -               if (!start)
1046 -                       return count;
1047 -               ath_dbg(common, XMIT, "Resetting TX99\n");
1048 -               ath9k_tx99_deinit(sc);
1049 -       }
1050 -
1051 -       if (!start) {
1052 -               ath9k_tx99_deinit(sc);
1053 -               return count;
1054 -       }
1055 -
1056 -       r = ath9k_tx99_init(sc);
1057 -       if (r)
1058 -               return r;
1059 -
1060 -       return count;
1061 -}
1062 -
1063 -static const struct file_operations fops_tx99 = {
1064 -       .read = read_file_tx99,
1065 -       .write = write_file_tx99,
1066 -       .open = simple_open,
1067 -       .owner = THIS_MODULE,
1068 -       .llseek = default_llseek,
1069 -};
1070 -
1071 -static ssize_t read_file_tx99_power(struct file *file,
1072 -                                   char __user *user_buf,
1073 -                                   size_t count, loff_t *ppos)
1074 -{
1075 -       struct ath_softc *sc = file->private_data;
1076 -       char buf[32];
1077 -       unsigned int len;
1078 -
1079 -       len = sprintf(buf, "%d (%d dBm)\n",
1080 -                     sc->tx99_power,
1081 -                     sc->tx99_power / 2);
1082 -
1083 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1084 -}
1085 -
1086 -static ssize_t write_file_tx99_power(struct file *file,
1087 -                                    const char __user *user_buf,
1088 -                                    size_t count, loff_t *ppos)
1089 -{
1090 -       struct ath_softc *sc = file->private_data;
1091 -       int r;
1092 -       u8 tx_power;
1093 -
1094 -       r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
1095 -       if (r)
1096 -               return r;
1097 -
1098 -       if (tx_power > MAX_RATE_POWER)
1099 -               return -EINVAL;
1100 -
1101 -       sc->tx99_power = tx_power;
1102 -
1103 -       ath9k_ps_wakeup(sc);
1104 -       ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
1105 -       ath9k_ps_restore(sc);
1106 -
1107 -       return count;
1108 -}
1109 -
1110 -static const struct file_operations fops_tx99_power = {
1111 -       .read = read_file_tx99_power,
1112 -       .write = write_file_tx99_power,
1113 -       .open = simple_open,
1114 -       .owner = THIS_MODULE,
1115 -       .llseek = default_llseek,
1116 -};
1117 -
1118  int ath9k_init_debug(struct ath_hw *ah)
1119  {
1120         struct ath_common *common = ath9k_hw_common(ah);
1121 @@ -1903,6 +1798,7 @@ int ath9k_init_debug(struct ath_hw *ah)
1122  #endif
1123  
1124         ath9k_dfs_init_debug(sc);
1125 +       ath9k_tx99_init_debug(sc);
1126  
1127         debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
1128                             &fops_dma);
1129 @@ -1978,15 +1874,6 @@ int ath9k_init_debug(struct ath_hw *ah)
1130         debugfs_create_file("btcoex", S_IRUSR, sc->debug.debugfs_phy, sc,
1131                             &fops_btcoex);
1132  #endif
1133 -       if (config_enabled(CPTCFG_ATH9K_TX99) &&
1134 -           AR_SREV_9300_20_OR_LATER(ah)) {
1135 -               debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
1136 -                                   sc->debug.debugfs_phy, sc,
1137 -                                   &fops_tx99);
1138 -               debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
1139 -                                   sc->debug.debugfs_phy, sc,
1140 -                                   &fops_tx99_power);
1141 -       }
1142  
1143         return 0;
1144  }
1145 --- a/drivers/net/wireless/ath/ath9k/hw.c
1146 +++ b/drivers/net/wireless/ath/ath9k/hw.c
1147 @@ -17,6 +17,8 @@
1148  #include <linux/io.h>
1149  #include <linux/slab.h>
1150  #include <linux/module.h>
1151 +#include <linux/time.h>
1152 +#include <linux/bitops.h>
1153  #include <asm/unaligned.h>
1154  
1155  #include "hw.h"
1156 @@ -438,23 +440,13 @@ static bool ath9k_hw_chip_test(struct at
1157  
1158  static void ath9k_hw_init_config(struct ath_hw *ah)
1159  {
1160 -       int i;
1161 -
1162         ah->config.dma_beacon_response_time = 1;
1163         ah->config.sw_beacon_response_time = 6;
1164 -       ah->config.additional_swba_backoff = 0;
1165         ah->config.ack_6mb = 0x0;
1166         ah->config.cwm_ignore_extcca = 0;
1167 -       ah->config.pcie_clock_req = 0;
1168         ah->config.analog_shiftreg = 1;
1169  
1170 -       for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1171 -               ah->config.spurchans[i][0] = AR_NO_SPUR;
1172 -               ah->config.spurchans[i][1] = AR_NO_SPUR;
1173 -       }
1174 -
1175         ah->config.rx_intr_mitigation = true;
1176 -       ah->config.pcieSerDesWrite = true;
1177  
1178         /*
1179          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
1180 @@ -486,7 +478,6 @@ static void ath9k_hw_init_defaults(struc
1181         ah->hw_version.magic = AR5416_MAGIC;
1182         ah->hw_version.subvendorid = 0;
1183  
1184 -       ah->atim_window = 0;
1185         ah->sta_id1_defaults =
1186                 AR_STA_ID1_CRPT_MIC_ENABLE |
1187                 AR_STA_ID1_MCAST_KSRCH;
1188 @@ -549,11 +540,11 @@ static int ath9k_hw_post_init(struct ath
1189          * EEPROM needs to be initialized before we do this.
1190          * This is required for regulatory compliance.
1191          */
1192 -       if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1193 +       if (AR_SREV_9300_20_OR_LATER(ah)) {
1194                 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1195                 if ((regdmn & 0xF0) == CTL_FCC) {
1196 -                       ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ;
1197 -                       ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ;
1198 +                       ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
1199 +                       ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
1200                 }
1201         }
1202  
1203 @@ -1502,8 +1493,9 @@ static bool ath9k_hw_channel_change(stru
1204         int r;
1205  
1206         if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1207 -               band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
1208 -               mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
1209 +               u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1210 +               band_switch = !!(flags_diff & CHANNEL_5GHZ);
1211 +               mode_diff = !!(flags_diff & ~CHANNEL_HT);
1212         }
1213  
1214         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1215 @@ -1815,7 +1807,7 @@ static int ath9k_hw_do_fastcc(struct ath
1216          * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1217          */
1218         if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1219 -           chan->channelFlags != ah->curchan->channelFlags)
1220 +           ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1221                 goto fail;
1222  
1223         if (!ath9k_hw_check_alive(ah))
1224 @@ -1856,10 +1848,12 @@ int ath9k_hw_reset(struct ath_hw *ah, st
1225                    struct ath9k_hw_cal_data *caldata, bool fastcc)
1226  {
1227         struct ath_common *common = ath9k_hw_common(ah);
1228 +       struct timespec ts;
1229         u32 saveLedState;
1230         u32 saveDefAntenna;
1231         u32 macStaId1;
1232         u64 tsf = 0;
1233 +       s64 usec = 0;
1234         int r;
1235         bool start_mci_reset = false;
1236         bool save_fullsleep = ah->chip_fullsleep;
1237 @@ -1902,10 +1896,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
1238  
1239         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1240  
1241 -       /* For chips on which RTC reset is done, save TSF before it gets cleared */
1242 -       if (AR_SREV_9100(ah) ||
1243 -           (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1244 -               tsf = ath9k_hw_gettsf64(ah);
1245 +       /* Save TSF before chip reset, a cold reset clears it */
1246 +       tsf = ath9k_hw_gettsf64(ah);
1247 +       getrawmonotonic(&ts);
1248 +       usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000;
1249  
1250         saveLedState = REG_READ(ah, AR_CFG_LED) &
1251                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1252 @@ -1938,8 +1932,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
1253         }
1254  
1255         /* Restore TSF */
1256 -       if (tsf)
1257 -               ath9k_hw_settsf64(ah, tsf);
1258 +       getrawmonotonic(&ts);
1259 +       usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec;
1260 +       ath9k_hw_settsf64(ah, tsf + usec);
1261  
1262         if (AR_SREV_9280_20_OR_LATER(ah))
1263                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1264 @@ -2261,9 +2256,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
1265         case NL80211_IFTYPE_ADHOC:
1266                 REG_SET_BIT(ah, AR_TXCFG,
1267                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1268 -               REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1269 -                         TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1270 -               flags |= AR_NDP_TIMER_EN;
1271         case NL80211_IFTYPE_MESH_POINT:
1272         case NL80211_IFTYPE_AP:
1273                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1274 @@ -2284,7 +2276,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
1275         REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1276         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1277         REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1278 -       REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1279  
1280         REGWRITE_BUFFER_FLUSH(ah);
1281  
1282 @@ -2301,12 +2292,9 @@ void ath9k_hw_set_sta_beacon_timers(stru
1283  
1284         ENABLE_REGWRITE_BUFFER(ah);
1285  
1286 -       REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1287 -
1288 -       REG_WRITE(ah, AR_BEACON_PERIOD,
1289 -                 TU_TO_USEC(bs->bs_intval));
1290 -       REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1291 -                 TU_TO_USEC(bs->bs_intval));
1292 +       REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
1293 +       REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
1294 +       REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
1295  
1296         REGWRITE_BUFFER_FLUSH(ah);
1297  
1298 @@ -2334,9 +2322,8 @@ void ath9k_hw_set_sta_beacon_timers(stru
1299  
1300         ENABLE_REGWRITE_BUFFER(ah);
1301  
1302 -       REG_WRITE(ah, AR_NEXT_DTIM,
1303 -                 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1304 -       REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1305 +       REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
1306 +       REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
1307  
1308         REG_WRITE(ah, AR_SLEEP1,
1309                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1310 @@ -2350,8 +2337,8 @@ void ath9k_hw_set_sta_beacon_timers(stru
1311         REG_WRITE(ah, AR_SLEEP2,
1312                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1313  
1314 -       REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1315 -       REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1316 +       REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
1317 +       REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
1318  
1319         REGWRITE_BUFFER_FLUSH(ah);
1320  
1321 @@ -2987,20 +2974,6 @@ static const struct ath_gen_timer_config
1322  
1323  /* HW generic timer primitives */
1324  
1325 -/* compute and clear index of rightmost 1 */
1326 -static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
1327 -{
1328 -       u32 b;
1329 -
1330 -       b = *mask;
1331 -       b &= (0-b);
1332 -       *mask &= ~b;
1333 -       b *= debruijn32;
1334 -       b >>= 27;
1335 -
1336 -       return timer_table->gen_timer_index[b];
1337 -}
1338 -
1339  u32 ath9k_hw_gettsf32(struct ath_hw *ah)
1340  {
1341         return REG_READ(ah, AR_TSF_L32);
1342 @@ -3016,6 +2989,10 @@ struct ath_gen_timer *ath_gen_timer_allo
1343         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1344         struct ath_gen_timer *timer;
1345  
1346 +       if ((timer_index < AR_FIRST_NDP_TIMER) ||
1347 +               (timer_index >= ATH_MAX_GEN_TIMER))
1348 +               return NULL;
1349 +
1350         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
1351         if (timer == NULL)
1352                 return NULL;
1353 @@ -3033,23 +3010,13 @@ EXPORT_SYMBOL(ath_gen_timer_alloc);
1354  
1355  void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1356                               struct ath_gen_timer *timer,
1357 -                             u32 trig_timeout,
1358 +                             u32 timer_next,
1359                               u32 timer_period)
1360  {
1361         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1362 -       u32 tsf, timer_next;
1363 -
1364 -       BUG_ON(!timer_period);
1365 -
1366 -       set_bit(timer->index, &timer_table->timer_mask.timer_bits);
1367 -
1368 -       tsf = ath9k_hw_gettsf32(ah);
1369 +       u32 mask = 0;
1370  
1371 -       timer_next = tsf + trig_timeout;
1372 -
1373 -       ath_dbg(ath9k_hw_common(ah), BTCOEX,
1374 -               "current tsf %x period %x timer_next %x\n",
1375 -               tsf, timer_period, timer_next);
1376 +       timer_table->timer_mask |= BIT(timer->index);
1377  
1378         /*
1379          * Program generic timer registers
1380 @@ -3075,10 +3042,19 @@ void ath9k_hw_gen_timer_start(struct ath
1381                                        (1 << timer->index));
1382         }
1383  
1384 -       /* Enable both trigger and thresh interrupt masks */
1385 -       REG_SET_BIT(ah, AR_IMR_S5,
1386 -               (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
1387 -               SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
1388 +       if (timer->trigger)
1389 +               mask |= SM(AR_GENTMR_BIT(timer->index),
1390 +                          AR_IMR_S5_GENTIMER_TRIG);
1391 +       if (timer->overflow)
1392 +               mask |= SM(AR_GENTMR_BIT(timer->index),
1393 +                          AR_IMR_S5_GENTIMER_THRESH);
1394 +
1395 +       REG_SET_BIT(ah, AR_IMR_S5, mask);
1396 +
1397 +       if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
1398 +               ah->imask |= ATH9K_INT_GENTIMER;
1399 +               ath9k_hw_set_interrupts(ah);
1400 +       }
1401  }
1402  EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
1403  
1404 @@ -3086,11 +3062,6 @@ void ath9k_hw_gen_timer_stop(struct ath_
1405  {
1406         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1407  
1408 -       if ((timer->index < AR_FIRST_NDP_TIMER) ||
1409 -               (timer->index >= ATH_MAX_GEN_TIMER)) {
1410 -               return;
1411 -       }
1412 -
1413         /* Clear generic timer enable bits. */
1414         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
1415                         gen_tmr_configuration[timer->index].mode_mask);
1416 @@ -3110,7 +3081,12 @@ void ath9k_hw_gen_timer_stop(struct ath_
1417                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
1418                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
1419  
1420 -       clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
1421 +       timer_table->timer_mask &= ~BIT(timer->index);
1422 +
1423 +       if (timer_table->timer_mask == 0) {
1424 +               ah->imask &= ~ATH9K_INT_GENTIMER;
1425 +               ath9k_hw_set_interrupts(ah);
1426 +       }
1427  }
1428  EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
1429  
1430 @@ -3131,32 +3107,32 @@ void ath_gen_timer_isr(struct ath_hw *ah
1431  {
1432         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1433         struct ath_gen_timer *timer;
1434 -       struct ath_common *common = ath9k_hw_common(ah);
1435 -       u32 trigger_mask, thresh_mask, index;
1436 +       unsigned long trigger_mask, thresh_mask;
1437 +       unsigned int index;
1438  
1439         /* get hardware generic timer interrupt status */
1440         trigger_mask = ah->intr_gen_timer_trigger;
1441         thresh_mask = ah->intr_gen_timer_thresh;
1442 -       trigger_mask &= timer_table->timer_mask.val;
1443 -       thresh_mask &= timer_table->timer_mask.val;
1444 +       trigger_mask &= timer_table->timer_mask;
1445 +       thresh_mask &= timer_table->timer_mask;
1446  
1447         trigger_mask &= ~thresh_mask;
1448  
1449 -       while (thresh_mask) {
1450 -               index = rightmost_index(timer_table, &thresh_mask);
1451 +       for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
1452                 timer = timer_table->timers[index];
1453 -               BUG_ON(!timer);
1454 -               ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n",
1455 -                       index);
1456 +               if (!timer)
1457 +                   continue;
1458 +               if (!timer->overflow)
1459 +                   continue;
1460                 timer->overflow(timer->arg);
1461         }
1462  
1463 -       while (trigger_mask) {
1464 -               index = rightmost_index(timer_table, &trigger_mask);
1465 +       for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
1466                 timer = timer_table->timers[index];
1467 -               BUG_ON(!timer);
1468 -               ath_dbg(common, BTCOEX,
1469 -                       "Gen timer[%d] trigger\n", index);
1470 +               if (!timer)
1471 +                   continue;
1472 +               if (!timer->trigger)
1473 +                   continue;
1474                 timer->trigger(timer->arg);
1475         }
1476  }
1477 --- a/drivers/net/wireless/ath/ath9k/hw.h
1478 +++ b/drivers/net/wireless/ath/ath9k/hw.h
1479 @@ -168,7 +168,7 @@
1480  #define CAB_TIMEOUT_VAL             10
1481  #define BEACON_TIMEOUT_VAL          10
1482  #define MIN_BEACON_TIMEOUT_VAL      1
1483 -#define SLEEP_SLOP                  3
1484 +#define SLEEP_SLOP                  TU_TO_USEC(3)
1485  
1486  #define INIT_CONFIG_STATUS          0x00000000
1487  #define INIT_RSSI_THR               0x00000700
1488 @@ -280,11 +280,8 @@ struct ath9k_hw_capabilities {
1489  struct ath9k_ops_config {
1490         int dma_beacon_response_time;
1491         int sw_beacon_response_time;
1492 -       int additional_swba_backoff;
1493         int ack_6mb;
1494         u32 cwm_ignore_extcca;
1495 -       bool pcieSerDesWrite;
1496 -       u8 pcie_clock_req;
1497         u32 pcie_waen;
1498         u8 analog_shiftreg;
1499         u32 ofdm_trig_low;
1500 @@ -295,18 +292,11 @@ struct ath9k_ops_config {
1501         int serialize_regmode;
1502         bool rx_intr_mitigation;
1503         bool tx_intr_mitigation;
1504 -#define SPUR_DISABLE           0
1505 -#define SPUR_ENABLE_IOCTL      1
1506 -#define SPUR_ENABLE_EEPROM     2
1507 -#define AR_SPUR_5413_1         1640
1508 -#define AR_SPUR_5413_2         1200
1509  #define AR_NO_SPUR             0x8000
1510  #define AR_BASE_FREQ_2GHZ      2300
1511  #define AR_BASE_FREQ_5GHZ      4900
1512  #define AR_SPUR_FEEQ_BOUND_HT40 19
1513  #define AR_SPUR_FEEQ_BOUND_HT20 10
1514 -       int spurmode;
1515 -       u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
1516         u8 max_txtrig_level;
1517         u16 ani_poll_interval; /* ANI poll interval in ms */
1518  
1519 @@ -316,6 +306,8 @@ struct ath9k_ops_config {
1520         u32 ant_ctrl_comm2g_switch_enable;
1521         bool xatten_margin_cfg;
1522         bool alt_mingainidx;
1523 +       bool no_pll_pwrsave;
1524 +       bool tx_gain_buffalo;
1525  };
1526  
1527  enum ath9k_int {
1528 @@ -459,10 +451,6 @@ struct ath9k_beacon_state {
1529         u32 bs_intval;
1530  #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
1531         u32 bs_dtimperiod;
1532 -       u16 bs_cfpperiod;
1533 -       u16 bs_cfpmaxduration;
1534 -       u32 bs_cfpnext;
1535 -       u16 bs_timoffset;
1536         u16 bs_bmissthreshold;
1537         u32 bs_sleepduration;
1538         u32 bs_tsfoor_threshold;
1539 @@ -498,12 +486,6 @@ struct ath9k_hw_version {
1540  
1541  #define AR_GENTMR_BIT(_index)  (1 << (_index))
1542  
1543 -/*
1544 - * Using de Bruijin sequence to look up 1's index in a 32 bit number
1545 - * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
1546 - */
1547 -#define debruijn32 0x077CB531U
1548 -
1549  struct ath_gen_timer_configuration {
1550         u32 next_addr;
1551         u32 period_addr;
1552 @@ -519,12 +501,8 @@ struct ath_gen_timer {
1553  };
1554  
1555  struct ath_gen_timer_table {
1556 -       u32 gen_timer_index[32];
1557         struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
1558 -       union {
1559 -               unsigned long timer_bits;
1560 -               u16 val;
1561 -       } timer_mask;
1562 +       u16 timer_mask;
1563  };
1564  
1565  struct ath_hw_antcomb_conf {
1566 @@ -785,7 +763,6 @@ struct ath_hw {
1567         u32 txurn_interrupt_mask;
1568         atomic_t intr_ref_cnt;
1569         bool chip_fullsleep;
1570 -       u32 atim_window;
1571         u32 modes_index;
1572  
1573         /* Calibration */
1574 @@ -864,6 +841,7 @@ struct ath_hw {
1575         u32 gpio_mask;
1576         u32 gpio_val;
1577  
1578 +       struct ar5416IniArray ini_dfs;
1579         struct ar5416IniArray iniModes;
1580         struct ar5416IniArray iniCommon;
1581         struct ar5416IniArray iniBB_RfGain;
1582 @@ -920,7 +898,7 @@ struct ath_hw {
1583         /* Enterprise mode cap */
1584         u32 ent_mode;
1585  
1586 -#ifdef CONFIG_PM_SLEEP
1587 +#ifdef CONFIG_ATH9K_WOW
1588         u32 wow_event_mask;
1589  #endif
1590         bool is_clk_25mhz;
1591 @@ -1126,7 +1104,7 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw
1592  #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */
1593  
1594  
1595 -#ifdef CONFIG_PM_SLEEP
1596 +#ifdef CONFIG_ATH9K_WOW
1597  const char *ath9k_hw_wow_event_to_string(u32 wow_event);
1598  void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1599                                 u8 *user_mask, int pattern_count,
1600 --- a/drivers/net/wireless/ath/ath9k/init.c
1601 +++ b/drivers/net/wireless/ath/ath9k/init.c
1602 @@ -554,7 +554,7 @@ static void ath9k_init_misc(struct ath_s
1603         sc->spec_config.fft_period = 0xF;
1604  }
1605  
1606 -static void ath9k_init_platform(struct ath_softc *sc)
1607 +static void ath9k_init_pcoem_platform(struct ath_softc *sc)
1608  {
1609         struct ath_hw *ah = sc->sc_ah;
1610         struct ath9k_hw_capabilities *pCap = &ah->caps;
1611 @@ -609,6 +609,11 @@ static void ath9k_init_platform(struct a
1612                 ah->config.pcie_waen = 0x0040473b;
1613                 ath_info(common, "Enable WAR for ASPM D3/L1\n");
1614         }
1615 +
1616 +       if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
1617 +               ah->config.no_pll_pwrsave = true;
1618 +               ath_info(common, "Disable PLL PowerSave\n");
1619 +       }
1620  }
1621  
1622  static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
1623 @@ -656,6 +661,27 @@ static void ath9k_eeprom_release(struct 
1624         release_firmware(sc->sc_ah->eeprom_blob);
1625  }
1626  
1627 +static int ath9k_init_soc_platform(struct ath_softc *sc)
1628 +{
1629 +       struct ath9k_platform_data *pdata = sc->dev->platform_data;
1630 +       struct ath_hw *ah = sc->sc_ah;
1631 +       int ret = 0;
1632 +
1633 +       if (!pdata)
1634 +               return 0;
1635 +
1636 +       if (pdata->eeprom_name) {
1637 +               ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
1638 +               if (ret)
1639 +                       return ret;
1640 +       }
1641 +
1642 +       if (pdata->tx_gain_buffalo)
1643 +               ah->config.tx_gain_buffalo = true;
1644 +
1645 +       return ret;
1646 +}
1647 +
1648  static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
1649                             const struct ath_bus_ops *bus_ops)
1650  {
1651 @@ -683,6 +709,7 @@ static int ath9k_init_softc(u16 devid, s
1652         common = ath9k_hw_common(ah);
1653         sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
1654         sc->tx99_power = MAX_RATE_POWER + 1;
1655 +       init_waitqueue_head(&sc->tx_wait);
1656  
1657         if (!pdata) {
1658                 ah->ah_flags |= AH_USE_EEPROM;
1659 @@ -708,7 +735,11 @@ static int ath9k_init_softc(u16 devid, s
1660         /*
1661          * Platform quirks.
1662          */
1663 -       ath9k_init_platform(sc);
1664 +       ath9k_init_pcoem_platform(sc);
1665 +
1666 +       ret = ath9k_init_soc_platform(sc);
1667 +       if (ret)
1668 +               return ret;
1669  
1670         /*
1671          * Enable WLAN/BT RX Antenna diversity only when:
1672 @@ -722,7 +753,6 @@ static int ath9k_init_softc(u16 devid, s
1673                 common->bt_ant_diversity = 1;
1674  
1675         spin_lock_init(&common->cc_lock);
1676 -
1677         spin_lock_init(&sc->sc_serial_rw);
1678         spin_lock_init(&sc->sc_pm_lock);
1679         mutex_init(&sc->mutex);
1680 @@ -730,6 +760,7 @@ static int ath9k_init_softc(u16 devid, s
1681         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1682                      (unsigned long)sc);
1683  
1684 +       setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
1685         INIT_WORK(&sc->hw_reset_work, ath_reset_work);
1686         INIT_WORK(&sc->hw_check_work, ath_hw_check);
1687         INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
1688 @@ -743,12 +774,6 @@ static int ath9k_init_softc(u16 devid, s
1689         ath_read_cachesize(common, &csz);
1690         common->cachelsz = csz << 2; /* convert to bytes */
1691  
1692 -       if (pdata && pdata->eeprom_name) {
1693 -               ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
1694 -               if (ret)
1695 -                       return ret;
1696 -       }
1697 -
1698         /* Initializes the hardware for all supported chipsets */
1699         ret = ath9k_hw_init(ah);
1700         if (ret)
1701 @@ -845,7 +870,8 @@ static const struct ieee80211_iface_limi
1702  };
1703  
1704  static const struct ieee80211_iface_limit if_dfs_limits[] = {
1705 -       { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) },
1706 +       { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) |
1707 +                                BIT(NL80211_IFTYPE_ADHOC) },
1708  };
1709  
1710  static const struct ieee80211_iface_combination if_comb[] = {
1711 @@ -862,20 +888,11 @@ static const struct ieee80211_iface_comb
1712                 .max_interfaces = 1,
1713                 .num_different_channels = 1,
1714                 .beacon_int_infra_match = true,
1715 -               .radar_detect_widths =  BIT(NL80211_CHAN_NO_HT) |
1716 -                                       BIT(NL80211_CHAN_HT20),
1717 +               .radar_detect_widths =  BIT(NL80211_CHAN_WIDTH_20_NOHT) |
1718 +                                       BIT(NL80211_CHAN_WIDTH_20),
1719         }
1720  };
1721  
1722 -#ifdef CONFIG_PM
1723 -static const struct wiphy_wowlan_support ath9k_wowlan_support = {
1724 -       .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
1725 -       .n_patterns = MAX_NUM_USER_PATTERN,
1726 -       .pattern_min_len = 1,
1727 -       .pattern_max_len = MAX_PATTERN_SIZE,
1728 -};
1729 -#endif
1730 -
1731  void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1732  {
1733         struct ath_hw *ah = sc->sc_ah;
1734 @@ -925,16 +942,6 @@ void ath9k_set_hw_capab(struct ath_softc
1735         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
1736         hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
1737  
1738 -#ifdef CONFIG_PM_SLEEP
1739 -       if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
1740 -           (sc->driver_data & ATH9K_PCI_WOW) &&
1741 -           device_can_wakeup(sc->dev))
1742 -               hw->wiphy->wowlan = &ath9k_wowlan_support;
1743 -
1744 -       atomic_set(&sc->wow_sleep_proc_intr, -1);
1745 -       atomic_set(&sc->wow_got_bmiss_intr, -1);
1746 -#endif
1747 -
1748         hw->queues = 4;
1749         hw->max_rates = 4;
1750         hw->channel_change_time = 5000;
1751 @@ -960,6 +967,7 @@ void ath9k_set_hw_capab(struct ath_softc
1752                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1753                         &sc->sbands[IEEE80211_BAND_5GHZ];
1754  
1755 +       ath9k_init_wow(hw);
1756         ath9k_reload_chainmask_settings(sc);
1757  
1758         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1759 @@ -1058,6 +1066,7 @@ static void ath9k_deinit_softc(struct at
1760                 if (ATH_TXQ_SETUP(sc, i))
1761                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1762  
1763 +       del_timer_sync(&sc->sleep_timer);
1764         ath9k_hw_deinit(sc->sc_ah);
1765         if (sc->dfs_detector != NULL)
1766                 sc->dfs_detector->exit(sc->dfs_detector);
1767 --- a/drivers/net/wireless/ath/ath9k/main.c
1768 +++ b/drivers/net/wireless/ath/ath9k/main.c
1769 @@ -82,6 +82,22 @@ static bool ath9k_setpower(struct ath_so
1770         return ret;
1771  }
1772  
1773 +void ath_ps_full_sleep(unsigned long data)
1774 +{
1775 +       struct ath_softc *sc = (struct ath_softc *) data;
1776 +       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1777 +       bool reset;
1778 +
1779 +       spin_lock(&common->cc_lock);
1780 +       ath_hw_cycle_counters_update(common);
1781 +       spin_unlock(&common->cc_lock);
1782 +
1783 +       ath9k_hw_setrxabort(sc->sc_ah, 1);
1784 +       ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
1785 +
1786 +       ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
1787 +}
1788 +
1789  void ath9k_ps_wakeup(struct ath_softc *sc)
1790  {
1791         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1792 @@ -92,6 +108,7 @@ void ath9k_ps_wakeup(struct ath_softc *s
1793         if (++sc->ps_usecount != 1)
1794                 goto unlock;
1795  
1796 +       del_timer_sync(&sc->sleep_timer);
1797         power_mode = sc->sc_ah->power_mode;
1798         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1799  
1800 @@ -117,17 +134,17 @@ void ath9k_ps_restore(struct ath_softc *
1801         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1802         enum ath9k_power_mode mode;
1803         unsigned long flags;
1804 -       bool reset;
1805  
1806         spin_lock_irqsave(&sc->sc_pm_lock, flags);
1807         if (--sc->ps_usecount != 0)
1808                 goto unlock;
1809  
1810         if (sc->ps_idle) {
1811 -               ath9k_hw_setrxabort(sc->sc_ah, 1);
1812 -               ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
1813 -               mode = ATH9K_PM_FULL_SLEEP;
1814 -       } else if (sc->ps_enabled &&
1815 +               mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
1816 +               goto unlock;
1817 +       }
1818 +
1819 +       if (sc->ps_enabled &&
1820                    !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1821                                      PS_WAIT_FOR_CAB |
1822                                      PS_WAIT_FOR_PSPOLL_DATA |
1823 @@ -163,13 +180,13 @@ static void __ath_cancel_work(struct ath
1824  #endif
1825  }
1826  
1827 -static void ath_cancel_work(struct ath_softc *sc)
1828 +void ath_cancel_work(struct ath_softc *sc)
1829  {
1830         __ath_cancel_work(sc);
1831         cancel_work_sync(&sc->hw_reset_work);
1832  }
1833  
1834 -static void ath_restart_work(struct ath_softc *sc)
1835 +void ath_restart_work(struct ath_softc *sc)
1836  {
1837         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
1838  
1839 @@ -487,8 +504,13 @@ void ath9k_tasklet(unsigned long data)
1840                         ath_tx_edma_tasklet(sc);
1841                 else
1842                         ath_tx_tasklet(sc);
1843 +
1844 +               wake_up(&sc->tx_wait);
1845         }
1846  
1847 +       if (status & ATH9K_INT_GENTIMER)
1848 +               ath_gen_timer_isr(sc->sc_ah);
1849 +
1850         ath9k_btcoex_handle_interrupt(sc, status);
1851  
1852         /* re-enable hardware interrupt */
1853 @@ -579,7 +601,8 @@ irqreturn_t ath_isr(int irq, void *dev)
1854  
1855                 goto chip_reset;
1856         }
1857 -#ifdef CONFIG_PM_SLEEP
1858 +
1859 +#ifdef CONFIG_ATH9K_WOW
1860         if (status & ATH9K_INT_BMISS) {
1861                 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
1862                         ath_dbg(common, ANY, "during WoW we got a BMISS\n");
1863 @@ -588,6 +611,8 @@ irqreturn_t ath_isr(int irq, void *dev)
1864                 }
1865         }
1866  #endif
1867 +
1868 +
1869         if (status & ATH9K_INT_SWBA)
1870                 tasklet_schedule(&sc->bcon_tasklet);
1871  
1872 @@ -627,7 +652,7 @@ chip_reset:
1873  #undef SCHED_INTR
1874  }
1875  
1876 -static int ath_reset(struct ath_softc *sc)
1877 +int ath_reset(struct ath_softc *sc)
1878  {
1879         int r;
1880  
1881 @@ -735,6 +760,8 @@ static int ath9k_start(struct ieee80211_
1882          */
1883         ath9k_cmn_init_crypto(sc->sc_ah);
1884  
1885 +       ath9k_hw_reset_tsf(ah);
1886 +
1887         spin_unlock_bh(&sc->sc_pcu_lock);
1888  
1889         mutex_unlock(&sc->mutex);
1890 @@ -1817,13 +1844,31 @@ static void ath9k_set_coverage_class(str
1891         mutex_unlock(&sc->mutex);
1892  }
1893  
1894 +static bool ath9k_has_tx_pending(struct ath_softc *sc)
1895 +{
1896 +       int i, npend;
1897 +
1898 +       for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1899 +               if (!ATH_TXQ_SETUP(sc, i))
1900 +                       continue;
1901 +
1902 +               if (!sc->tx.txq[i].axq_depth)
1903 +                       continue;
1904 +
1905 +               npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1906 +               if (npend)
1907 +                       break;
1908 +       }
1909 +
1910 +       return !!npend;
1911 +}
1912 +
1913  static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1914  {
1915         struct ath_softc *sc = hw->priv;
1916         struct ath_hw *ah = sc->sc_ah;
1917         struct ath_common *common = ath9k_hw_common(ah);
1918 -       int timeout = 200; /* ms */
1919 -       int i, j;
1920 +       int timeout = HZ / 5; /* 200 ms */
1921         bool drain_txq;
1922  
1923         mutex_lock(&sc->mutex);
1924 @@ -1841,25 +1886,9 @@ static void ath9k_flush(struct ieee80211
1925                 return;
1926         }
1927  
1928 -       for (j = 0; j < timeout; j++) {
1929 -               bool npend = false;
1930 -
1931 -               if (j)
1932 -                       usleep_range(1000, 2000);
1933 -
1934 -               for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1935 -                       if (!ATH_TXQ_SETUP(sc, i))
1936 -                               continue;
1937 -
1938 -                       npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1939 -
1940 -                       if (npend)
1941 -                               break;
1942 -               }
1943 -
1944 -               if (!npend)
1945 -                   break;
1946 -       }
1947 +       if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
1948 +                              timeout) > 0)
1949 +               drop = false;
1950  
1951         if (drop) {
1952                 ath9k_ps_wakeup(sc);
1953 @@ -2021,333 +2050,6 @@ static int ath9k_get_antenna(struct ieee
1954         return 0;
1955  }
1956  
1957 -#ifdef CONFIG_PM_SLEEP
1958 -
1959 -static void ath9k_wow_map_triggers(struct ath_softc *sc,
1960 -                                  struct cfg80211_wowlan *wowlan,
1961 -                                  u32 *wow_triggers)
1962 -{
1963 -       if (wowlan->disconnect)
1964 -               *wow_triggers |= AH_WOW_LINK_CHANGE |
1965 -                                AH_WOW_BEACON_MISS;
1966 -       if (wowlan->magic_pkt)
1967 -               *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
1968 -
1969 -       if (wowlan->n_patterns)
1970 -               *wow_triggers |= AH_WOW_USER_PATTERN_EN;
1971 -
1972 -       sc->wow_enabled = *wow_triggers;
1973 -
1974 -}
1975 -
1976 -static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
1977 -{
1978 -       struct ath_hw *ah = sc->sc_ah;
1979 -       struct ath_common *common = ath9k_hw_common(ah);
1980 -       int pattern_count = 0;
1981 -       int i, byte_cnt;
1982 -       u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
1983 -       u8 dis_deauth_mask[MAX_PATTERN_SIZE];
1984 -
1985 -       memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
1986 -       memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
1987 -
1988 -       /*
1989 -        * Create Dissassociate / Deauthenticate packet filter
1990 -        *
1991 -        *     2 bytes        2 byte    6 bytes   6 bytes  6 bytes
1992 -        *  +--------------+----------+---------+--------+--------+----
1993 -        *  + Frame Control+ Duration +   DA    +  SA    +  BSSID +
1994 -        *  +--------------+----------+---------+--------+--------+----
1995 -        *
1996 -        * The above is the management frame format for disassociate/
1997 -        * deauthenticate pattern, from this we need to match the first byte
1998 -        * of 'Frame Control' and DA, SA, and BSSID fields
1999 -        * (skipping 2nd byte of FC and Duration feild.
2000 -        *
2001 -        * Disassociate pattern
2002 -        * --------------------
2003 -        * Frame control = 00 00 1010
2004 -        * DA, SA, BSSID = x:x:x:x:x:x
2005 -        * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2006 -        *                          | x:x:x:x:x:x  -- 22 bytes
2007 -        *
2008 -        * Deauthenticate pattern
2009 -        * ----------------------
2010 -        * Frame control = 00 00 1100
2011 -        * DA, SA, BSSID = x:x:x:x:x:x
2012 -        * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2013 -        *                          | x:x:x:x:x:x  -- 22 bytes
2014 -        */
2015 -
2016 -       /* Create Disassociate Pattern first */
2017 -
2018 -       byte_cnt = 0;
2019 -
2020 -       /* Fill out the mask with all FF's */
2021 -
2022 -       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2023 -               dis_deauth_mask[i] = 0xff;
2024 -
2025 -       /* copy the first byte of frame control field */
2026 -       dis_deauth_pattern[byte_cnt] = 0xa0;
2027 -       byte_cnt++;
2028 -
2029 -       /* skip 2nd byte of frame control and Duration field */
2030 -       byte_cnt += 3;
2031 -
2032 -       /*
2033 -        * need not match the destination mac address, it can be a broadcast
2034 -        * mac address or an unicast to this station
2035 -        */
2036 -       byte_cnt += 6;
2037 -
2038 -       /* copy the source mac address */
2039 -       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2040 -
2041 -       byte_cnt += 6;
2042 -
2043 -       /* copy the bssid, its same as the source mac address */
2044 -
2045 -       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2046 -
2047 -       /* Create Disassociate pattern mask */
2048 -
2049 -       dis_deauth_mask[0] = 0xfe;
2050 -       dis_deauth_mask[1] = 0x03;
2051 -       dis_deauth_mask[2] = 0xc0;
2052 -
2053 -       ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2054 -
2055 -       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2056 -                                  pattern_count, byte_cnt);
2057 -
2058 -       pattern_count++;
2059 -       /*
2060 -        * for de-authenticate pattern, only the first byte of the frame
2061 -        * control field gets changed from 0xA0 to 0xC0
2062 -        */
2063 -       dis_deauth_pattern[0] = 0xC0;
2064 -
2065 -       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2066 -                                  pattern_count, byte_cnt);
2067 -
2068 -}
2069 -
2070 -static void ath9k_wow_add_pattern(struct ath_softc *sc,
2071 -                                 struct cfg80211_wowlan *wowlan)
2072 -{
2073 -       struct ath_hw *ah = sc->sc_ah;
2074 -       struct ath9k_wow_pattern *wow_pattern = NULL;
2075 -       struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
2076 -       int mask_len;
2077 -       s8 i = 0;
2078 -
2079 -       if (!wowlan->n_patterns)
2080 -               return;
2081 -
2082 -       /*
2083 -        * Add the new user configured patterns
2084 -        */
2085 -       for (i = 0; i < wowlan->n_patterns; i++) {
2086 -
2087 -               wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2088 -
2089 -               if (!wow_pattern)
2090 -                       return;
2091 -
2092 -               /*
2093 -                * TODO: convert the generic user space pattern to
2094 -                * appropriate chip specific/802.11 pattern.
2095 -                */
2096 -
2097 -               mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2098 -               memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2099 -               memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2100 -               memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2101 -                      patterns[i].pattern_len);
2102 -               memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2103 -               wow_pattern->pattern_len = patterns[i].pattern_len;
2104 -
2105 -               /*
2106 -                * just need to take care of deauth and disssoc pattern,
2107 -                * make sure we don't overwrite them.
2108 -                */
2109 -
2110 -               ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2111 -                                          wow_pattern->mask_bytes,
2112 -                                          i + 2,
2113 -                                          wow_pattern->pattern_len);
2114 -               kfree(wow_pattern);
2115 -
2116 -       }
2117 -
2118 -}
2119 -
2120 -static int ath9k_suspend(struct ieee80211_hw *hw,
2121 -                        struct cfg80211_wowlan *wowlan)
2122 -{
2123 -       struct ath_softc *sc = hw->priv;
2124 -       struct ath_hw *ah = sc->sc_ah;
2125 -       struct ath_common *common = ath9k_hw_common(ah);
2126 -       u32 wow_triggers_enabled = 0;
2127 -       int ret = 0;
2128 -
2129 -       mutex_lock(&sc->mutex);
2130 -
2131 -       ath_cancel_work(sc);
2132 -       ath_stop_ani(sc);
2133 -       del_timer_sync(&sc->rx_poll_timer);
2134 -
2135 -       if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2136 -               ath_dbg(common, ANY, "Device not present\n");
2137 -               ret = -EINVAL;
2138 -               goto fail_wow;
2139 -       }
2140 -
2141 -       if (WARN_ON(!wowlan)) {
2142 -               ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2143 -               ret = -EINVAL;
2144 -               goto fail_wow;
2145 -       }
2146 -
2147 -       if (!device_can_wakeup(sc->dev)) {
2148 -               ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2149 -               ret = 1;
2150 -               goto fail_wow;
2151 -       }
2152 -
2153 -       /*
2154 -        * none of the sta vifs are associated
2155 -        * and we are not currently handling multivif
2156 -        * cases, for instance we have to seperately
2157 -        * configure 'keep alive frame' for each
2158 -        * STA.
2159 -        */
2160 -
2161 -       if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2162 -               ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2163 -               ret = 1;
2164 -               goto fail_wow;
2165 -       }
2166 -
2167 -       if (sc->nvifs > 1) {
2168 -               ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2169 -               ret = 1;
2170 -               goto fail_wow;
2171 -       }
2172 -
2173 -       ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2174 -
2175 -       ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2176 -               wow_triggers_enabled);
2177 -
2178 -       ath9k_ps_wakeup(sc);
2179 -
2180 -       ath9k_stop_btcoex(sc);
2181 -
2182 -       /*
2183 -        * Enable wake up on recieving disassoc/deauth
2184 -        * frame by default.
2185 -        */
2186 -       ath9k_wow_add_disassoc_deauth_pattern(sc);
2187 -
2188 -       if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2189 -               ath9k_wow_add_pattern(sc, wowlan);
2190 -
2191 -       spin_lock_bh(&sc->sc_pcu_lock);
2192 -       /*
2193 -        * To avoid false wake, we enable beacon miss interrupt only
2194 -        * when we go to sleep. We save the current interrupt mask
2195 -        * so we can restore it after the system wakes up
2196 -        */
2197 -       sc->wow_intr_before_sleep = ah->imask;
2198 -       ah->imask &= ~ATH9K_INT_GLOBAL;
2199 -       ath9k_hw_disable_interrupts(ah);
2200 -       ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2201 -       ath9k_hw_set_interrupts(ah);
2202 -       ath9k_hw_enable_interrupts(ah);
2203 -
2204 -       spin_unlock_bh(&sc->sc_pcu_lock);
2205 -
2206 -       /*
2207 -        * we can now sync irq and kill any running tasklets, since we already
2208 -        * disabled interrupts and not holding a spin lock
2209 -        */
2210 -       synchronize_irq(sc->irq);
2211 -       tasklet_kill(&sc->intr_tq);
2212 -
2213 -       ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2214 -
2215 -       ath9k_ps_restore(sc);
2216 -       ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2217 -       atomic_inc(&sc->wow_sleep_proc_intr);
2218 -
2219 -fail_wow:
2220 -       mutex_unlock(&sc->mutex);
2221 -       return ret;
2222 -}
2223 -
2224 -static int ath9k_resume(struct ieee80211_hw *hw)
2225 -{
2226 -       struct ath_softc *sc = hw->priv;
2227 -       struct ath_hw *ah = sc->sc_ah;
2228 -       struct ath_common *common = ath9k_hw_common(ah);
2229 -       u32 wow_status;
2230 -
2231 -       mutex_lock(&sc->mutex);
2232 -
2233 -       ath9k_ps_wakeup(sc);
2234 -
2235 -       spin_lock_bh(&sc->sc_pcu_lock);
2236 -
2237 -       ath9k_hw_disable_interrupts(ah);
2238 -       ah->imask = sc->wow_intr_before_sleep;
2239 -       ath9k_hw_set_interrupts(ah);
2240 -       ath9k_hw_enable_interrupts(ah);
2241 -
2242 -       spin_unlock_bh(&sc->sc_pcu_lock);
2243 -
2244 -       wow_status = ath9k_hw_wow_wakeup(ah);
2245 -
2246 -       if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2247 -               /*
2248 -                * some devices may not pick beacon miss
2249 -                * as the reason they woke up so we add
2250 -                * that here for that shortcoming.
2251 -                */
2252 -               wow_status |= AH_WOW_BEACON_MISS;
2253 -               atomic_dec(&sc->wow_got_bmiss_intr);
2254 -               ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2255 -       }
2256 -
2257 -       atomic_dec(&sc->wow_sleep_proc_intr);
2258 -
2259 -       if (wow_status) {
2260 -               ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2261 -                       ath9k_hw_wow_event_to_string(wow_status), wow_status);
2262 -       }
2263 -
2264 -       ath_restart_work(sc);
2265 -       ath9k_start_btcoex(sc);
2266 -
2267 -       ath9k_ps_restore(sc);
2268 -       mutex_unlock(&sc->mutex);
2269 -
2270 -       return 0;
2271 -}
2272 -
2273 -static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2274 -{
2275 -       struct ath_softc *sc = hw->priv;
2276 -
2277 -       mutex_lock(&sc->mutex);
2278 -       device_init_wakeup(sc->dev, 1);
2279 -       device_set_wakeup_enable(sc->dev, enabled);
2280 -       mutex_unlock(&sc->mutex);
2281 -}
2282 -
2283 -#endif
2284  static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2285  {
2286         struct ath_softc *sc = hw->priv;
2287 @@ -2373,134 +2075,6 @@ static void ath9k_channel_switch_beacon(
2288         sc->csa_vif = vif;
2289  }
2290  
2291 -static void ath9k_tx99_stop(struct ath_softc *sc)
2292 -{
2293 -       struct ath_hw *ah = sc->sc_ah;
2294 -       struct ath_common *common = ath9k_hw_common(ah);
2295 -
2296 -       ath_drain_all_txq(sc);
2297 -       ath_startrecv(sc);
2298 -
2299 -       ath9k_hw_set_interrupts(ah);
2300 -       ath9k_hw_enable_interrupts(ah);
2301 -
2302 -       ieee80211_wake_queues(sc->hw);
2303 -
2304 -       kfree_skb(sc->tx99_skb);
2305 -       sc->tx99_skb = NULL;
2306 -       sc->tx99_state = false;
2307 -
2308 -       ath9k_hw_tx99_stop(sc->sc_ah);
2309 -       ath_dbg(common, XMIT, "TX99 stopped\n");
2310 -}
2311 -
2312 -static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
2313 -{
2314 -       static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
2315 -                              0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
2316 -                              0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
2317 -                              0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
2318 -                              0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
2319 -                              0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
2320 -                              0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
2321 -                              0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
2322 -       u32 len = 1200;
2323 -       struct ieee80211_hw *hw = sc->hw;
2324 -       struct ieee80211_hdr *hdr;
2325 -       struct ieee80211_tx_info *tx_info;
2326 -       struct sk_buff *skb;
2327 -
2328 -       skb = alloc_skb(len, GFP_KERNEL);
2329 -       if (!skb)
2330 -               return NULL;
2331 -
2332 -       skb_put(skb, len);
2333 -
2334 -       memset(skb->data, 0, len);
2335 -
2336 -       hdr = (struct ieee80211_hdr *)skb->data;
2337 -       hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
2338 -       hdr->duration_id = 0;
2339 -
2340 -       memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
2341 -       memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
2342 -       memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
2343 -
2344 -       hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2345 -
2346 -       tx_info = IEEE80211_SKB_CB(skb);
2347 -       memset(tx_info, 0, sizeof(*tx_info));
2348 -       tx_info->band = hw->conf.chandef.chan->band;
2349 -       tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
2350 -       tx_info->control.vif = sc->tx99_vif;
2351 -
2352 -       memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
2353 -
2354 -       return skb;
2355 -}
2356 -
2357 -void ath9k_tx99_deinit(struct ath_softc *sc)
2358 -{
2359 -       ath_reset(sc);
2360 -
2361 -       ath9k_ps_wakeup(sc);
2362 -       ath9k_tx99_stop(sc);
2363 -       ath9k_ps_restore(sc);
2364 -}
2365 -
2366 -int ath9k_tx99_init(struct ath_softc *sc)
2367 -{
2368 -       struct ieee80211_hw *hw = sc->hw;
2369 -       struct ath_hw *ah = sc->sc_ah;
2370 -       struct ath_common *common = ath9k_hw_common(ah);
2371 -       struct ath_tx_control txctl;
2372 -       int r;
2373 -
2374 -       if (sc->sc_flags & SC_OP_INVALID) {
2375 -               ath_err(common,
2376 -                       "driver is in invalid state unable to use TX99");
2377 -               return -EINVAL;
2378 -       }
2379 -
2380 -       sc->tx99_skb = ath9k_build_tx99_skb(sc);
2381 -       if (!sc->tx99_skb)
2382 -               return -ENOMEM;
2383 -
2384 -       memset(&txctl, 0, sizeof(txctl));
2385 -       txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
2386 -
2387 -       ath_reset(sc);
2388 -
2389 -       ath9k_ps_wakeup(sc);
2390 -
2391 -       ath9k_hw_disable_interrupts(ah);
2392 -       atomic_set(&ah->intr_ref_cnt, -1);
2393 -       ath_drain_all_txq(sc);
2394 -       ath_stoprecv(sc);
2395 -
2396 -       sc->tx99_state = true;
2397 -
2398 -       ieee80211_stop_queues(hw);
2399 -
2400 -       if (sc->tx99_power == MAX_RATE_POWER + 1)
2401 -               sc->tx99_power = MAX_RATE_POWER;
2402 -
2403 -       ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
2404 -       r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
2405 -       if (r) {
2406 -               ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
2407 -               return r;
2408 -       }
2409 -
2410 -       ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
2411 -               sc->tx99_power,
2412 -               sc->tx99_power / 2);
2413 -
2414 -       /* We leave the harware awake as it will be chugging on */
2415 -
2416 -       return 0;
2417 -}
2418 -
2419  struct ieee80211_ops ath9k_ops = {
2420         .tx                 = ath9k_tx,
2421         .start              = ath9k_start,
2422 @@ -2531,7 +2105,7 @@ struct ieee80211_ops ath9k_ops = {
2423         .set_antenna        = ath9k_set_antenna,
2424         .get_antenna        = ath9k_get_antenna,
2425  
2426 -#ifdef CONFIG_PM_SLEEP
2427 +#ifdef CONFIG_ATH9K_WOW
2428         .suspend            = ath9k_suspend,
2429         .resume             = ath9k_resume,
2430         .set_wakeup         = ath9k_set_wakeup,
2431 --- a/drivers/net/wireless/ath/ath9k/wow.c
2432 +++ b/drivers/net/wireless/ath/ath9k/wow.c
2433 @@ -1,5 +1,5 @@
2434  /*
2435 - * Copyright (c) 2012 Qualcomm Atheros, Inc.
2436 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
2437   *
2438   * Permission to use, copy, modify, and/or distribute this software for any
2439   * purpose with or without fee is hereby granted, provided that the above
2440 @@ -14,409 +14,348 @@
2441   * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
2442   */
2443  
2444 -#include <linux/export.h>
2445  #include "ath9k.h"
2446 -#include "reg.h"
2447 -#include "hw-ops.h"
2448  
2449 -const char *ath9k_hw_wow_event_to_string(u32 wow_event)
2450 +static const struct wiphy_wowlan_support ath9k_wowlan_support = {
2451 +       .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2452 +       .n_patterns = MAX_NUM_USER_PATTERN,
2453 +       .pattern_min_len = 1,
2454 +       .pattern_max_len = MAX_PATTERN_SIZE,
2455 +};
2456 +
2457 +static void ath9k_wow_map_triggers(struct ath_softc *sc,
2458 +                                  struct cfg80211_wowlan *wowlan,
2459 +                                  u32 *wow_triggers)
2460  {
2461 -       if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
2462 -               return "Magic pattern";
2463 -       if (wow_event & AH_WOW_USER_PATTERN_EN)
2464 -               return "User pattern";
2465 -       if (wow_event & AH_WOW_LINK_CHANGE)
2466 -               return "Link change";
2467 -       if (wow_event & AH_WOW_BEACON_MISS)
2468 -               return "Beacon miss";
2469 +       if (wowlan->disconnect)
2470 +               *wow_triggers |= AH_WOW_LINK_CHANGE |
2471 +                                AH_WOW_BEACON_MISS;
2472 +       if (wowlan->magic_pkt)
2473 +               *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
2474 +
2475 +       if (wowlan->n_patterns)
2476 +               *wow_triggers |= AH_WOW_USER_PATTERN_EN;
2477 +
2478 +       sc->wow_enabled = *wow_triggers;
2479  
2480 -       return  "unknown reason";
2481  }
2482 -EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
2483  
2484 -static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
2485 +static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
2486  {
2487 +       struct ath_hw *ah = sc->sc_ah;
2488         struct ath_common *common = ath9k_hw_common(ah);
2489 +       int pattern_count = 0;
2490 +       int i, byte_cnt;
2491 +       u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
2492 +       u8 dis_deauth_mask[MAX_PATTERN_SIZE];
2493  
2494 -       REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2495 +       memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
2496 +       memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
2497  
2498 -       /* set rx disable bit */
2499 -       REG_WRITE(ah, AR_CR, AR_CR_RXD);
2500 +       /*
2501 +        * Create Dissassociate / Deauthenticate packet filter
2502 +        *
2503 +        *     2 bytes        2 byte    6 bytes   6 bytes  6 bytes
2504 +        *  +--------------+----------+---------+--------+--------+----
2505 +        *  + Frame Control+ Duration +   DA    +  SA    +  BSSID +
2506 +        *  +--------------+----------+---------+--------+--------+----
2507 +        *
2508 +        * The above is the management frame format for disassociate/
2509 +        * deauthenticate pattern, from this we need to match the first byte
2510 +        * of 'Frame Control' and DA, SA, and BSSID fields
2511 +        * (skipping 2nd byte of FC and Duration feild.
2512 +        *
2513 +        * Disassociate pattern
2514 +        * --------------------
2515 +        * Frame control = 00 00 1010
2516 +        * DA, SA, BSSID = x:x:x:x:x:x
2517 +        * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2518 +        *                          | x:x:x:x:x:x  -- 22 bytes
2519 +        *
2520 +        * Deauthenticate pattern
2521 +        * ----------------------
2522 +        * Frame control = 00 00 1100
2523 +        * DA, SA, BSSID = x:x:x:x:x:x
2524 +        * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2525 +        *                          | x:x:x:x:x:x  -- 22 bytes
2526 +        */
2527  
2528 -       if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
2529 -               ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
2530 -                       REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
2531 -               return;
2532 -       }
2533 +       /* Create Disassociate Pattern first */
2534  
2535 -       REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
2536 -}
2537 +       byte_cnt = 0;
2538  
2539 -static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
2540 -{
2541 -       struct ath_common *common = ath9k_hw_common(ah);
2542 -       u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
2543 -       u32 ctl[13] = {0};
2544 -       u32 data_word[KAL_NUM_DATA_WORDS];
2545 -       u8 i;
2546 -       u32 wow_ka_data_word0;
2547 -
2548 -       memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
2549 -       memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
2550 -
2551 -       /* set the transmit buffer */
2552 -       ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
2553 -       ctl[1] = 0;
2554 -       ctl[3] = 0xb;   /* OFDM_6M hardware value for this rate */
2555 -       ctl[4] = 0;
2556 -       ctl[7] = (ah->txchainmask) << 2;
2557 -       ctl[2] = 0xf << 16; /* tx_tries 0 */
2558 -
2559 -       for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
2560 -               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
2561 -
2562 -       REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
2563 -
2564 -       data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
2565 -                      (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
2566 -       data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
2567 -                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
2568 -       data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
2569 -                      (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
2570 -       data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
2571 -                      (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
2572 -       data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
2573 -                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
2574 -       data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
2575 -
2576 -       if (AR_SREV_9462_20(ah)) {
2577 -               /* AR9462 2.0 has an extra descriptor word (time based
2578 -                * discard) compared to other chips */
2579 -               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
2580 -               wow_ka_data_word0 = AR_WOW_TXBUF(13);
2581 -       } else {
2582 -               wow_ka_data_word0 = AR_WOW_TXBUF(12);
2583 -       }
2584 +       /* Fill out the mask with all FF's */
2585  
2586 -       for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
2587 -               REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
2588 +       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2589 +               dis_deauth_mask[i] = 0xff;
2590  
2591 -}
2592 +       /* copy the first byte of frame control field */
2593 +       dis_deauth_pattern[byte_cnt] = 0xa0;
2594 +       byte_cnt++;
2595  
2596 -void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
2597 -                               u8 *user_mask, int pattern_count,
2598 -                               int pattern_len)
2599 -{
2600 -       int i;
2601 -       u32 pattern_val, mask_val;
2602 -       u32 set, clr;
2603 +       /* skip 2nd byte of frame control and Duration field */
2604 +       byte_cnt += 3;
2605  
2606 -       /* FIXME: should check count by querying the hardware capability */
2607 -       if (pattern_count >= MAX_NUM_PATTERN)
2608 -               return;
2609 +       /*
2610 +        * need not match the destination mac address, it can be a broadcast
2611 +        * mac address or an unicast to this station
2612 +        */
2613 +       byte_cnt += 6;
2614  
2615 -       REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
2616 +       /* copy the source mac address */
2617 +       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2618  
2619 -       /* set the registers for pattern */
2620 -       for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
2621 -               memcpy(&pattern_val, user_pattern, 4);
2622 -               REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
2623 -                         pattern_val);
2624 -               user_pattern += 4;
2625 -       }
2626 +       byte_cnt += 6;
2627  
2628 -       /* set the registers for mask */
2629 -       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
2630 -               memcpy(&mask_val, user_mask, 4);
2631 -               REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
2632 -               user_mask += 4;
2633 -       }
2634 +       /* copy the bssid, its same as the source mac address */
2635  
2636 -       /* set the pattern length to be matched
2637 -        *
2638 -        * AR_WOW_LENGTH1_REG1
2639 -        * bit 31:24 pattern 0 length
2640 -        * bit 23:16 pattern 1 length
2641 -        * bit 15:8 pattern 2 length
2642 -        * bit 7:0 pattern 3 length
2643 -        *
2644 -        * AR_WOW_LENGTH1_REG2
2645 -        * bit 31:24 pattern 4 length
2646 -        * bit 23:16 pattern 5 length
2647 -        * bit 15:8 pattern 6 length
2648 -        * bit 7:0 pattern 7 length
2649 -        *
2650 -        * the below logic writes out the new
2651 -        * pattern length for the corresponding
2652 -        * pattern_count, while masking out the
2653 -        * other fields
2654 -        */
2655 +       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2656  
2657 -       ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
2658 +       /* Create Disassociate pattern mask */
2659  
2660 -       if (pattern_count < 4) {
2661 -               /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
2662 -               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
2663 -                      AR_WOW_LEN1_SHIFT(pattern_count);
2664 -               clr = AR_WOW_LENGTH1_MASK(pattern_count);
2665 -               REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
2666 -       } else {
2667 -               /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
2668 -               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
2669 -                      AR_WOW_LEN2_SHIFT(pattern_count);
2670 -               clr = AR_WOW_LENGTH2_MASK(pattern_count);
2671 -               REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
2672 -       }
2673 +       dis_deauth_mask[0] = 0xfe;
2674 +       dis_deauth_mask[1] = 0x03;
2675 +       dis_deauth_mask[2] = 0xc0;
2676  
2677 -}
2678 -EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
2679 +       ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2680  
2681 -u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
2682 -{
2683 -       u32 wow_status = 0;
2684 -       u32 val = 0, rval;
2685 +       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2686 +                                  pattern_count, byte_cnt);
2687  
2688 +       pattern_count++;
2689         /*
2690 -        * read the WoW status register to know
2691 -        * the wakeup reason
2692 +        * for de-authenticate pattern, only the first byte of the frame
2693 +        * control field gets changed from 0xA0 to 0xC0
2694          */
2695 -       rval = REG_READ(ah, AR_WOW_PATTERN);
2696 -       val = AR_WOW_STATUS(rval);
2697 +       dis_deauth_pattern[0] = 0xC0;
2698  
2699 -       /*
2700 -        * mask only the WoW events that we have enabled. Sometimes
2701 -        * we have spurious WoW events from the AR_WOW_PATTERN
2702 -        * register. This mask will clean it up.
2703 -        */
2704 +       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2705 +                                  pattern_count, byte_cnt);
2706  
2707 -       val &= ah->wow_event_mask;
2708 +}
2709  
2710 -       if (val) {
2711 -               if (val & AR_WOW_MAGIC_PAT_FOUND)
2712 -                       wow_status |= AH_WOW_MAGIC_PATTERN_EN;
2713 -               if (AR_WOW_PATTERN_FOUND(val))
2714 -                       wow_status |= AH_WOW_USER_PATTERN_EN;
2715 -               if (val & AR_WOW_KEEP_ALIVE_FAIL)
2716 -                       wow_status |= AH_WOW_LINK_CHANGE;
2717 -               if (val & AR_WOW_BEACON_FAIL)
2718 -                       wow_status |= AH_WOW_BEACON_MISS;
2719 -       }
2720 +static void ath9k_wow_add_pattern(struct ath_softc *sc,
2721 +                                 struct cfg80211_wowlan *wowlan)
2722 +{
2723 +       struct ath_hw *ah = sc->sc_ah;
2724 +       struct ath9k_wow_pattern *wow_pattern = NULL;
2725 +       struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
2726 +       int mask_len;
2727 +       s8 i = 0;
2728 +
2729 +       if (!wowlan->n_patterns)
2730 +               return;
2731  
2732         /*
2733 -        * set and clear WOW_PME_CLEAR registers for the chip to
2734 -        * generate next wow signal.
2735 -        * disable D3 before accessing other registers ?
2736 +        * Add the new user configured patterns
2737          */
2738 +       for (i = 0; i < wowlan->n_patterns; i++) {
2739  
2740 -       /* do we need to check the bit value 0x01000000 (7-10) ?? */
2741 -       REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
2742 -               AR_PMCTRL_PWR_STATE_D1D3);
2743 +               wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2744  
2745 -       /*
2746 -        * clear all events
2747 -        */
2748 -       REG_WRITE(ah, AR_WOW_PATTERN,
2749 -                 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
2750 +               if (!wow_pattern)
2751 +                       return;
2752  
2753 -       /*
2754 -        * restore the beacon threshold to init value
2755 -        */
2756 -       REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2757 +               /*
2758 +                * TODO: convert the generic user space pattern to
2759 +                * appropriate chip specific/802.11 pattern.
2760 +                */
2761  
2762 -       /*
2763 -        * Restore the way the PCI-E reset, Power-On-Reset, external
2764 -        * PCIE_POR_SHORT pins are tied to its original value.
2765 -        * Previously just before WoW sleep, we untie the PCI-E
2766 -        * reset to our Chip's Power On Reset so that any PCI-E
2767 -        * reset from the bus will not reset our chip
2768 -        */
2769 -       if (ah->is_pciexpress)
2770 -               ath9k_hw_configpcipowersave(ah, false);
2771 +               mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2772 +               memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2773 +               memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2774 +               memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2775 +                      patterns[i].pattern_len);
2776 +               memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2777 +               wow_pattern->pattern_len = patterns[i].pattern_len;
2778 +
2779 +               /*
2780 +                * just need to take care of deauth and disssoc pattern,
2781 +                * make sure we don't overwrite them.
2782 +                */
2783 +
2784 +               ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2785 +                                          wow_pattern->mask_bytes,
2786 +                                          i + 2,
2787 +                                          wow_pattern->pattern_len);
2788 +               kfree(wow_pattern);
2789  
2790 -       ah->wow_event_mask = 0;
2791 +       }
2792  
2793 -       return wow_status;
2794  }
2795 -EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
2796  
2797 -void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
2798 +int ath9k_suspend(struct ieee80211_hw *hw,
2799 +                 struct cfg80211_wowlan *wowlan)
2800  {
2801 -       u32 wow_event_mask;
2802 -       u32 set, clr;
2803 +       struct ath_softc *sc = hw->priv;
2804 +       struct ath_hw *ah = sc->sc_ah;
2805 +       struct ath_common *common = ath9k_hw_common(ah);
2806 +       u32 wow_triggers_enabled = 0;
2807 +       int ret = 0;
2808  
2809 -       /*
2810 -        * wow_event_mask is a mask to the AR_WOW_PATTERN register to
2811 -        * indicate which WoW events we have enabled. The WoW events
2812 -        * are from the 'pattern_enable' in this function and
2813 -        * 'pattern_count' of ath9k_hw_wow_apply_pattern()
2814 -        */
2815 -       wow_event_mask = ah->wow_event_mask;
2816 +       mutex_lock(&sc->mutex);
2817  
2818 -       /*
2819 -        * Untie Power-on-Reset from the PCI-E-Reset. When we are in
2820 -        * WOW sleep, we do want the Reset from the PCI-E to disturb
2821 -        * our hw state
2822 -        */
2823 -       if (ah->is_pciexpress) {
2824 -               /*
2825 -                * we need to untie the internal POR (power-on-reset)
2826 -                * to the external PCI-E reset. We also need to tie
2827 -                * the PCI-E Phy reset to the PCI-E reset.
2828 -                */
2829 -               set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
2830 -               clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
2831 -               REG_RMW(ah, AR_WA, set, clr);
2832 +       ath_cancel_work(sc);
2833 +       ath_stop_ani(sc);
2834 +       del_timer_sync(&sc->rx_poll_timer);
2835 +
2836 +       if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2837 +               ath_dbg(common, ANY, "Device not present\n");
2838 +               ret = -EINVAL;
2839 +               goto fail_wow;
2840         }
2841  
2842 -       /*
2843 -        * set the power states appropriately and enable PME
2844 -        */
2845 -       set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
2846 -             AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
2847 +       if (WARN_ON(!wowlan)) {
2848 +               ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2849 +               ret = -EINVAL;
2850 +               goto fail_wow;
2851 +       }
2852  
2853 -       /*
2854 -        * set and clear WOW_PME_CLEAR registers for the chip
2855 -        * to generate next wow signal.
2856 -        */
2857 -       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
2858 -       clr = AR_PMCTRL_WOW_PME_CLR;
2859 -       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
2860 +       if (!device_can_wakeup(sc->dev)) {
2861 +               ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2862 +               ret = 1;
2863 +               goto fail_wow;
2864 +       }
2865  
2866         /*
2867 -        * Setup for:
2868 -        *      - beacon misses
2869 -        *      - magic pattern
2870 -        *      - keep alive timeout
2871 -        *      - pattern matching
2872 +        * none of the sta vifs are associated
2873 +        * and we are not currently handling multivif
2874 +        * cases, for instance we have to seperately
2875 +        * configure 'keep alive frame' for each
2876 +        * STA.
2877          */
2878  
2879 -       /*
2880 -        * Program default values for pattern backoff, aifs/slot/KAL count,
2881 -        * beacon miss timeout, KAL timeout, etc.
2882 -        */
2883 -       set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
2884 -       REG_SET_BIT(ah, AR_WOW_PATTERN, set);
2885 +       if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2886 +               ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2887 +               ret = 1;
2888 +               goto fail_wow;
2889 +       }
2890 +
2891 +       if (sc->nvifs > 1) {
2892 +               ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2893 +               ret = 1;
2894 +               goto fail_wow;
2895 +       }
2896  
2897 -       set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
2898 -             AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
2899 -             AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
2900 -       REG_SET_BIT(ah, AR_WOW_COUNT, set);
2901 -
2902 -       if (pattern_enable & AH_WOW_BEACON_MISS)
2903 -               set = AR_WOW_BEACON_TIMO;
2904 -       /* We are not using beacon miss, program a large value */
2905 -       else
2906 -               set = AR_WOW_BEACON_TIMO_MAX;
2907 +       ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2908  
2909 -       REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
2910 +       ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2911 +               wow_triggers_enabled);
2912  
2913 -       /*
2914 -        * Keep alive timo in ms except AR9280
2915 -        */
2916 -       if (!pattern_enable)
2917 -               set = AR_WOW_KEEP_ALIVE_NEVER;
2918 -       else
2919 -               set = KAL_TIMEOUT * 32;
2920 +       ath9k_ps_wakeup(sc);
2921  
2922 -       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
2923 +       ath9k_stop_btcoex(sc);
2924  
2925         /*
2926 -        * Keep alive delay in us. based on 'power on clock',
2927 -        * therefore in usec
2928 +        * Enable wake up on recieving disassoc/deauth
2929 +        * frame by default.
2930          */
2931 -       set = KAL_DELAY * 1000;
2932 -       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
2933 +       ath9k_wow_add_disassoc_deauth_pattern(sc);
2934  
2935 -       /*
2936 -        * Create keep alive pattern to respond to beacons
2937 -        */
2938 -       ath9k_wow_create_keep_alive_pattern(ah);
2939 +       if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2940 +               ath9k_wow_add_pattern(sc, wowlan);
2941  
2942 +       spin_lock_bh(&sc->sc_pcu_lock);
2943         /*
2944 -        * Configure MAC WoW Registers
2945 +        * To avoid false wake, we enable beacon miss interrupt only
2946 +        * when we go to sleep. We save the current interrupt mask
2947 +        * so we can restore it after the system wakes up
2948          */
2949 -       set = 0;
2950 -       /* Send keep alive timeouts anyway */
2951 -       clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
2952 -
2953 -       if (pattern_enable & AH_WOW_LINK_CHANGE)
2954 -               wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
2955 -       else
2956 -               set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
2957 +       sc->wow_intr_before_sleep = ah->imask;
2958 +       ah->imask &= ~ATH9K_INT_GLOBAL;
2959 +       ath9k_hw_disable_interrupts(ah);
2960 +       ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2961 +       ath9k_hw_set_interrupts(ah);
2962 +       ath9k_hw_enable_interrupts(ah);
2963  
2964 -       set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
2965 -       REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
2966 +       spin_unlock_bh(&sc->sc_pcu_lock);
2967  
2968         /*
2969 -        * we are relying on a bmiss failure. ensure we have
2970 -        * enough threshold to prevent false positives
2971 +        * we can now sync irq and kill any running tasklets, since we already
2972 +        * disabled interrupts and not holding a spin lock
2973          */
2974 -       REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
2975 -                     AR_WOW_BMISSTHRESHOLD);
2976 +       synchronize_irq(sc->irq);
2977 +       tasklet_kill(&sc->intr_tq);
2978 +
2979 +       ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2980  
2981 -       set = 0;
2982 -       clr = 0;
2983 +       ath9k_ps_restore(sc);
2984 +       ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2985 +       atomic_inc(&sc->wow_sleep_proc_intr);
2986  
2987 -       if (pattern_enable & AH_WOW_BEACON_MISS) {
2988 -               set = AR_WOW_BEACON_FAIL_EN;
2989 -               wow_event_mask |= AR_WOW_BEACON_FAIL;
2990 -       } else {
2991 -               clr = AR_WOW_BEACON_FAIL_EN;
2992 +fail_wow:
2993 +       mutex_unlock(&sc->mutex);
2994 +       return ret;
2995 +}
2996 +
2997 +int ath9k_resume(struct ieee80211_hw *hw)
2998 +{
2999 +       struct ath_softc *sc = hw->priv;
3000 +       struct ath_hw *ah = sc->sc_ah;
3001 +       struct ath_common *common = ath9k_hw_common(ah);
3002 +       u32 wow_status;
3003 +
3004 +       mutex_lock(&sc->mutex);
3005 +
3006 +       ath9k_ps_wakeup(sc);
3007 +
3008 +       spin_lock_bh(&sc->sc_pcu_lock);
3009 +
3010 +       ath9k_hw_disable_interrupts(ah);
3011 +       ah->imask = sc->wow_intr_before_sleep;
3012 +       ath9k_hw_set_interrupts(ah);
3013 +       ath9k_hw_enable_interrupts(ah);
3014 +
3015 +       spin_unlock_bh(&sc->sc_pcu_lock);
3016 +
3017 +       wow_status = ath9k_hw_wow_wakeup(ah);
3018 +
3019 +       if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
3020 +               /*
3021 +                * some devices may not pick beacon miss
3022 +                * as the reason they woke up so we add
3023 +                * that here for that shortcoming.
3024 +                */
3025 +               wow_status |= AH_WOW_BEACON_MISS;
3026 +               atomic_dec(&sc->wow_got_bmiss_intr);
3027 +               ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
3028         }
3029  
3030 -       REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
3031 +       atomic_dec(&sc->wow_sleep_proc_intr);
3032  
3033 -       set = 0;
3034 -       clr = 0;
3035 -       /*
3036 -        * Enable the magic packet registers
3037 -        */
3038 -       if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
3039 -               set = AR_WOW_MAGIC_EN;
3040 -               wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
3041 -       } else {
3042 -               clr = AR_WOW_MAGIC_EN;
3043 +       if (wow_status) {
3044 +               ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
3045 +                       ath9k_hw_wow_event_to_string(wow_status), wow_status);
3046         }
3047 -       set |= AR_WOW_MAC_INTR_EN;
3048 -       REG_RMW(ah, AR_WOW_PATTERN, set, clr);
3049  
3050 -       REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
3051 -                 AR_WOW_PATTERN_SUPPORTED);
3052 +       ath_restart_work(sc);
3053 +       ath9k_start_btcoex(sc);
3054  
3055 -       /*
3056 -        * Set the power states appropriately and enable PME
3057 -        */
3058 -       clr = 0;
3059 -       set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
3060 -             AR_PMCTRL_PWR_PM_CTRL_ENA;
3061 +       ath9k_ps_restore(sc);
3062 +       mutex_unlock(&sc->mutex);
3063  
3064 -       clr = AR_PCIE_PM_CTRL_ENA;
3065 -       REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
3066 +       return 0;
3067 +}
3068  
3069 -       /*
3070 -        * this is needed to prevent the chip waking up
3071 -        * the host within 3-4 seconds with certain
3072 -        * platform/BIOS. The fix is to enable
3073 -        * D1 & D3 to match original definition and
3074 -        * also match the OTP value. Anyway this
3075 -        * is more related to SW WOW.
3076 -        */
3077 -       clr = AR_PMCTRL_PWR_STATE_D1D3;
3078 -       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
3079 +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
3080 +{
3081 +       struct ath_softc *sc = hw->priv;
3082  
3083 -       set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
3084 -       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
3085 +       mutex_lock(&sc->mutex);
3086 +       device_init_wakeup(sc->dev, 1);
3087 +       device_set_wakeup_enable(sc->dev, enabled);
3088 +       mutex_unlock(&sc->mutex);
3089 +}
3090  
3091 -       REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
3092 +void ath9k_init_wow(struct ieee80211_hw *hw)
3093 +{
3094 +       struct ath_softc *sc = hw->priv;
3095  
3096 -       /* to bring down WOW power low margin */
3097 -       set = BIT(13);
3098 -       REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
3099 -       /* HW WoW */
3100 -       clr = BIT(5);
3101 -       REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
3102 +       if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
3103 +           (sc->driver_data & ATH9K_PCI_WOW) &&
3104 +           device_can_wakeup(sc->dev))
3105 +               hw->wiphy->wowlan = &ath9k_wowlan_support;
3106  
3107 -       ath9k_hw_set_powermode_wow_sleep(ah);
3108 -       ah->wow_event_mask = wow_event_mask;
3109 +       atomic_set(&sc->wow_sleep_proc_intr, -1);
3110 +       atomic_set(&sc->wow_got_bmiss_intr, -1);
3111  }
3112 -EXPORT_SYMBOL(ath9k_hw_wow_enable);
3113 --- a/drivers/net/wireless/ath/ath9k/xmit.c
3114 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
3115 @@ -1276,6 +1276,10 @@ static void ath_tx_fill_desc(struct ath_
3116                                 if (!rts_thresh || (len > rts_thresh))
3117                                         rts = true;
3118                         }
3119 +
3120 +                       if (!aggr)
3121 +                               len = fi->framelen;
3122 +
3123                         ath_buf_set_rate(sc, bf, &info, len, rts);
3124                 }
3125  
3126 @@ -1786,6 +1790,9 @@ bool ath_drain_all_txq(struct ath_softc 
3127                 if (!ATH_TXQ_SETUP(sc, i))
3128                         continue;
3129  
3130 +               if (!sc->tx.txq[i].axq_depth)
3131 +                       continue;
3132 +
3133                 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
3134                         npend |= BIT(i);
3135         }
3136 @@ -2749,6 +2756,8 @@ void ath_tx_node_cleanup(struct ath_soft
3137         }
3138  }
3139  
3140 +#ifdef CONFIG_ATH9K_TX99
3141 +
3142  int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
3143                     struct ath_tx_control *txctl)
3144  {
3145 @@ -2791,3 +2800,5 @@ int ath9k_tx99_send(struct ath_softc *sc
3146  
3147         return 0;
3148  }
3149 +
3150 +#endif /* CONFIG_ATH9K_TX99 */
3151 --- a/drivers/net/wireless/ath/regd.c
3152 +++ b/drivers/net/wireless/ath/regd.c
3153 @@ -37,17 +37,17 @@ static int __ath_regd_init(struct ath_re
3154  
3155  /* We enable active scan on these a case by case basis by regulatory domain */
3156  #define ATH9K_2GHZ_CH12_13     REG_RULE(2467-10, 2472+10, 40, 0, 20,\
3157 -                                       NL80211_RRF_PASSIVE_SCAN)
3158 +                                       NL80211_RRF_NO_IR)
3159  #define ATH9K_2GHZ_CH14                REG_RULE(2484-10, 2484+10, 40, 0, 20,\
3160 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_OFDM)
3161 +                               NL80211_RRF_NO_IR | NL80211_RRF_NO_OFDM)
3162  
3163  /* We allow IBSS on these on a case by case basis by regulatory domain */
3164  #define ATH9K_5GHZ_5150_5350   REG_RULE(5150-10, 5350+10, 80, 0, 30,\
3165 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
3166 +                               NL80211_RRF_NO_IR)
3167  #define ATH9K_5GHZ_5470_5850   REG_RULE(5470-10, 5850+10, 80, 0, 30,\
3168 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
3169 +                               NL80211_RRF_NO_IR)
3170  #define ATH9K_5GHZ_5725_5850   REG_RULE(5725-10, 5850+10, 80, 0, 30,\
3171 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
3172 +                               NL80211_RRF_NO_IR)
3173  
3174  #define ATH9K_2GHZ_ALL         ATH9K_2GHZ_CH01_11, \
3175                                 ATH9K_2GHZ_CH12_13, \
3176 @@ -224,17 +224,16 @@ ath_reg_apply_beaconing_flags(struct wip
3177                                  * regulatory_hint().
3178                                  */
3179                                 if (!(reg_rule->flags &
3180 -                                   NL80211_RRF_NO_IBSS))
3181 +                                   NL80211_RRF_NO_IR))
3182                                         ch->flags &=
3183 -                                         ~IEEE80211_CHAN_NO_IBSS;
3184 +                                         ~IEEE80211_CHAN_NO_IR;
3185                                 if (!(reg_rule->flags &
3186 -                                   NL80211_RRF_PASSIVE_SCAN))
3187 +                                   NL80211_RRF_NO_IR))
3188                                         ch->flags &=
3189 -                                         ~IEEE80211_CHAN_PASSIVE_SCAN;
3190 +                                         ~IEEE80211_CHAN_NO_IR;
3191                         } else {
3192                                 if (ch->beacon_found)
3193 -                                       ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
3194 -                                         IEEE80211_CHAN_PASSIVE_SCAN);
3195 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
3196                         }
3197                 }
3198         }
3199 @@ -260,11 +259,11 @@ ath_reg_apply_active_scan_flags(struct w
3200          */
3201         if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
3202                 ch = &sband->channels[11]; /* CH 12 */
3203 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3204 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3205 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
3206 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
3207                 ch = &sband->channels[12]; /* CH 13 */
3208 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3209 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3210 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
3211 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
3212                 return;
3213         }
3214  
3215 @@ -278,17 +277,17 @@ ath_reg_apply_active_scan_flags(struct w
3216         ch = &sband->channels[11]; /* CH 12 */
3217         reg_rule = freq_reg_info(wiphy, ch->center_freq);
3218         if (!IS_ERR(reg_rule)) {
3219 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
3220 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3221 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3222 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
3223 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
3224 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
3225         }
3226  
3227         ch = &sband->channels[12]; /* CH 13 */
3228         reg_rule = freq_reg_info(wiphy, ch->center_freq);
3229         if (!IS_ERR(reg_rule)) {
3230 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
3231 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3232 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3233 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
3234 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
3235 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
3236         }
3237  }
3238  
3239 @@ -320,8 +319,8 @@ static void ath_reg_apply_radar_flags(st
3240                  */
3241                 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
3242                         ch->flags |= IEEE80211_CHAN_RADAR |
3243 -                                    IEEE80211_CHAN_NO_IBSS |
3244 -                                    IEEE80211_CHAN_PASSIVE_SCAN;
3245 +                                    IEEE80211_CHAN_NO_IR |
3246 +                                    IEEE80211_CHAN_NO_IR;
3247         }
3248  }
3249  
3250 --- a/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
3251 +++ b/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
3252 @@ -812,7 +812,7 @@ static s32 brcmf_p2p_run_escan(struct br
3253                         struct ieee80211_channel *chan = request->channels[i];
3254  
3255                         if (chan->flags & (IEEE80211_CHAN_RADAR |
3256 -                                          IEEE80211_CHAN_PASSIVE_SCAN))
3257 +                                          IEEE80211_CHAN_NO_IR))
3258                                 continue;
3259  
3260                         chanspecs[i] = channel_to_chanspec(&p2p->cfg->d11inf,
3261 --- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
3262 +++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
3263 @@ -202,9 +202,9 @@ static struct ieee80211_supported_band _
3264  
3265  /* This is to override regulatory domains defined in cfg80211 module (reg.c)
3266   * By default world regulatory domain defined in reg.c puts the flags
3267 - * NL80211_RRF_PASSIVE_SCAN and NL80211_RRF_NO_IBSS for 5GHz channels (for
3268 - * 36..48 and 149..165). With respect to these flags, wpa_supplicant doesn't
3269 - * start p2p operations on 5GHz channels. All the changes in world regulatory
3270 + * NL80211_RRF_NO_IR for 5GHz channels (for * 36..48 and 149..165).
3271 + * With respect to these flags, wpa_supplicant doesn't * start p2p
3272 + * operations on 5GHz channels. All the changes in world regulatory
3273   * domain are to be done here.
3274   */
3275  static const struct ieee80211_regdomain brcmf_regdom = {
3276 @@ -5197,10 +5197,10 @@ static s32 brcmf_construct_reginfo(struc
3277                                         if (channel & WL_CHAN_RADAR)
3278                                                 band_chan_arr[index].flags |=
3279                                                         (IEEE80211_CHAN_RADAR |
3280 -                                                       IEEE80211_CHAN_NO_IBSS);
3281 +                                                       IEEE80211_CHAN_NO_IR);
3282                                         if (channel & WL_CHAN_PASSIVE)
3283                                                 band_chan_arr[index].flags |=
3284 -                                                   IEEE80211_CHAN_PASSIVE_SCAN;
3285 +                                                   IEEE80211_CHAN_NO_IR;
3286                                 }
3287                         }
3288                         if (!update)
3289 --- a/drivers/net/wireless/brcm80211/brcmsmac/channel.c
3290 +++ b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
3291 @@ -59,23 +59,20 @@
3292  
3293  #define BRCM_2GHZ_2412_2462    REG_RULE(2412-10, 2462+10, 40, 0, 19, 0)
3294  #define BRCM_2GHZ_2467_2472    REG_RULE(2467-10, 2472+10, 20, 0, 19, \
3295 -                                        NL80211_RRF_PASSIVE_SCAN | \
3296 -                                        NL80211_RRF_NO_IBSS)
3297 +                                        NL80211_RRF_NO_IR)
3298  
3299  #define BRCM_5GHZ_5180_5240    REG_RULE(5180-10, 5240+10, 40, 0, 21, \
3300 -                                        NL80211_RRF_PASSIVE_SCAN | \
3301 -                                        NL80211_RRF_NO_IBSS)
3302 +                                        NL80211_RRF_NO_IR)
3303  #define BRCM_5GHZ_5260_5320    REG_RULE(5260-10, 5320+10, 40, 0, 21, \
3304 -                                        NL80211_RRF_PASSIVE_SCAN | \
3305 +                                        NL80211_RRF_NO_IR | \
3306                                          NL80211_RRF_DFS | \
3307 -                                        NL80211_RRF_NO_IBSS)
3308 +                                        NL80211_RRF_NO_IR)
3309  #define BRCM_5GHZ_5500_5700    REG_RULE(5500-10, 5700+10, 40, 0, 21, \
3310 -                                        NL80211_RRF_PASSIVE_SCAN | \
3311 +                                        NL80211_RRF_NO_IR | \
3312                                          NL80211_RRF_DFS | \
3313 -                                        NL80211_RRF_NO_IBSS)
3314 +                                        NL80211_RRF_NO_IR)
3315  #define BRCM_5GHZ_5745_5825    REG_RULE(5745-10, 5825+10, 40, 0, 21, \
3316 -                                        NL80211_RRF_PASSIVE_SCAN | \
3317 -                                        NL80211_RRF_NO_IBSS)
3318 +                                        NL80211_RRF_NO_IR)
3319  
3320  static const struct ieee80211_regdomain brcms_regdom_x2 = {
3321         .n_reg_rules = 6,
3322 @@ -395,7 +392,7 @@ brcms_c_channel_set_chanspec(struct brcm
3323                 brcms_c_set_gmode(wlc, wlc->protection->gmode_user, false);
3324  
3325         brcms_b_set_chanspec(wlc->hw, chanspec,
3326 -                             !!(ch->flags & IEEE80211_CHAN_PASSIVE_SCAN),
3327 +                             !!(ch->flags & IEEE80211_CHAN_NO_IR),
3328                               &txpwr);
3329  }
3330  
3331 @@ -657,8 +654,8 @@ static void brcms_reg_apply_radar_flags(
3332                  */
3333                 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
3334                         ch->flags |= IEEE80211_CHAN_RADAR |
3335 -                                    IEEE80211_CHAN_NO_IBSS |
3336 -                                    IEEE80211_CHAN_PASSIVE_SCAN;
3337 +                                    IEEE80211_CHAN_NO_IR |
3338 +                                    IEEE80211_CHAN_NO_IR;
3339         }
3340  }
3341  
3342 @@ -688,14 +685,13 @@ brcms_reg_apply_beaconing_flags(struct w
3343                                 if (IS_ERR(rule))
3344                                         continue;
3345  
3346 -                               if (!(rule->flags & NL80211_RRF_NO_IBSS))
3347 -                                       ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
3348 -                               if (!(rule->flags & NL80211_RRF_PASSIVE_SCAN))
3349 +                               if (!(rule->flags & NL80211_RRF_NO_IR))
3350 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
3351 +                               if (!(rule->flags & NL80211_RRF_NO_IR))
3352                                         ch->flags &=
3353 -                                               ~IEEE80211_CHAN_PASSIVE_SCAN;
3354 +                                               ~IEEE80211_CHAN_NO_IR;
3355                         } else if (ch->beacon_found) {
3356 -                               ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
3357 -                                              IEEE80211_CHAN_PASSIVE_SCAN);
3358 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
3359                         }
3360                 }
3361         }
3362 --- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
3363 +++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
3364 @@ -125,13 +125,13 @@ static struct ieee80211_channel brcms_2g
3365         CHAN2GHZ(10, 2457, IEEE80211_CHAN_NO_HT40PLUS),
3366         CHAN2GHZ(11, 2462, IEEE80211_CHAN_NO_HT40PLUS),
3367         CHAN2GHZ(12, 2467,
3368 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
3369 +                IEEE80211_CHAN_NO_IR |
3370                  IEEE80211_CHAN_NO_HT40PLUS),
3371         CHAN2GHZ(13, 2472,
3372 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
3373 +                IEEE80211_CHAN_NO_IR |
3374                  IEEE80211_CHAN_NO_HT40PLUS),
3375         CHAN2GHZ(14, 2484,
3376 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
3377 +                IEEE80211_CHAN_NO_IR |
3378                  IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS |
3379                  IEEE80211_CHAN_NO_OFDM)
3380  };
3381 @@ -144,51 +144,51 @@ static struct ieee80211_channel brcms_5g
3382         CHAN5GHZ(48, IEEE80211_CHAN_NO_HT40PLUS),
3383         /* UNII-2 */
3384         CHAN5GHZ(52,
3385 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3386 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3387 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3388 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3389         CHAN5GHZ(56,
3390 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3391 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3392 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3393 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3394         CHAN5GHZ(60,
3395 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3396 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3397 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3398 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3399         CHAN5GHZ(64,
3400 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3401 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3402 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3403 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3404         /* MID */
3405         CHAN5GHZ(100,
3406 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3407 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3408 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3409 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3410         CHAN5GHZ(104,
3411 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3412 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3413 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3414 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3415         CHAN5GHZ(108,
3416 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3417 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3418 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3419 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3420         CHAN5GHZ(112,
3421 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3422 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3423 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3424 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3425         CHAN5GHZ(116,
3426 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3427 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3428 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3429 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3430         CHAN5GHZ(120,
3431 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3432 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3433 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3434 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3435         CHAN5GHZ(124,
3436 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3437 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3438 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3439 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3440         CHAN5GHZ(128,
3441 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3442 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3443 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3444 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3445         CHAN5GHZ(132,
3446 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3447 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
3448 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3449 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
3450         CHAN5GHZ(136,
3451 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3452 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
3453 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3454 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
3455         CHAN5GHZ(140,
3456 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
3457 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS |
3458 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
3459 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS |
3460                  IEEE80211_CHAN_NO_HT40MINUS),
3461         /* UNII-3 */
3462         CHAN5GHZ(149, IEEE80211_CHAN_NO_HT40MINUS),
3463 --- a/drivers/net/wireless/cw1200/scan.c
3464 +++ b/drivers/net/wireless/cw1200/scan.c
3465 @@ -197,9 +197,9 @@ void cw1200_scan_work(struct work_struct
3466                         if ((*it)->band != first->band)
3467                                 break;
3468                         if (((*it)->flags ^ first->flags) &
3469 -                                       IEEE80211_CHAN_PASSIVE_SCAN)
3470 +                                       IEEE80211_CHAN_NO_IR)
3471                                 break;
3472 -                       if (!(first->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
3473 +                       if (!(first->flags & IEEE80211_CHAN_NO_IR) &&
3474                             (*it)->max_power != first->max_power)
3475                                 break;
3476                 }
3477 @@ -210,7 +210,7 @@ void cw1200_scan_work(struct work_struct
3478                 else
3479                         scan.max_tx_rate = WSM_TRANSMIT_RATE_1;
3480                 scan.num_probes =
3481 -                       (first->flags & IEEE80211_CHAN_PASSIVE_SCAN) ? 0 : 2;
3482 +                       (first->flags & IEEE80211_CHAN_NO_IR) ? 0 : 2;
3483                 scan.num_ssids = priv->scan.n_ssids;
3484                 scan.ssids = &priv->scan.ssids[0];
3485                 scan.num_channels = it - priv->scan.curr;
3486 @@ -233,7 +233,7 @@ void cw1200_scan_work(struct work_struct
3487                 }
3488                 for (i = 0; i < scan.num_channels; ++i) {
3489                         scan.ch[i].number = priv->scan.curr[i]->hw_value;
3490 -                       if (priv->scan.curr[i]->flags & IEEE80211_CHAN_PASSIVE_SCAN) {
3491 +                       if (priv->scan.curr[i]->flags & IEEE80211_CHAN_NO_IR) {
3492                                 scan.ch[i].min_chan_time = 50;
3493                                 scan.ch[i].max_chan_time = 100;
3494                         } else {
3495 @@ -241,7 +241,7 @@ void cw1200_scan_work(struct work_struct
3496                                 scan.ch[i].max_chan_time = 25;
3497                         }
3498                 }
3499 -               if (!(first->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
3500 +               if (!(first->flags & IEEE80211_CHAN_NO_IR) &&
3501                     priv->scan.output_power != first->max_power) {
3502                         priv->scan.output_power = first->max_power;
3503                         wsm_set_output_power(priv,
3504 --- a/drivers/net/wireless/ipw2x00/ipw2100.c
3505 +++ b/drivers/net/wireless/ipw2x00/ipw2100.c
3506 @@ -1934,10 +1934,10 @@ static int ipw2100_wdev_init(struct net_
3507                         bg_band->channels[i].max_power = geo->bg[i].max_power;
3508                         if (geo->bg[i].flags & LIBIPW_CH_PASSIVE_ONLY)
3509                                 bg_band->channels[i].flags |=
3510 -                                       IEEE80211_CHAN_PASSIVE_SCAN;
3511 +                                       IEEE80211_CHAN_NO_IR;
3512                         if (geo->bg[i].flags & LIBIPW_CH_NO_IBSS)
3513                                 bg_band->channels[i].flags |=
3514 -                                       IEEE80211_CHAN_NO_IBSS;
3515 +                                       IEEE80211_CHAN_NO_IR;
3516                         if (geo->bg[i].flags & LIBIPW_CH_RADAR_DETECT)
3517                                 bg_band->channels[i].flags |=
3518                                         IEEE80211_CHAN_RADAR;
3519 --- a/drivers/net/wireless/ipw2x00/ipw2200.c
3520 +++ b/drivers/net/wireless/ipw2x00/ipw2200.c
3521 @@ -11472,10 +11472,10 @@ static int ipw_wdev_init(struct net_devi
3522                         bg_band->channels[i].max_power = geo->bg[i].max_power;
3523                         if (geo->bg[i].flags & LIBIPW_CH_PASSIVE_ONLY)
3524                                 bg_band->channels[i].flags |=
3525 -                                       IEEE80211_CHAN_PASSIVE_SCAN;
3526 +                                       IEEE80211_CHAN_NO_IR;
3527                         if (geo->bg[i].flags & LIBIPW_CH_NO_IBSS)
3528                                 bg_band->channels[i].flags |=
3529 -                                       IEEE80211_CHAN_NO_IBSS;
3530 +                                       IEEE80211_CHAN_NO_IR;
3531                         if (geo->bg[i].flags & LIBIPW_CH_RADAR_DETECT)
3532                                 bg_band->channels[i].flags |=
3533                                         IEEE80211_CHAN_RADAR;
3534 @@ -11511,10 +11511,10 @@ static int ipw_wdev_init(struct net_devi
3535                         a_band->channels[i].max_power = geo->a[i].max_power;
3536                         if (geo->a[i].flags & LIBIPW_CH_PASSIVE_ONLY)
3537                                 a_band->channels[i].flags |=
3538 -                                       IEEE80211_CHAN_PASSIVE_SCAN;
3539 +                                       IEEE80211_CHAN_NO_IR;
3540                         if (geo->a[i].flags & LIBIPW_CH_NO_IBSS)
3541                                 a_band->channels[i].flags |=
3542 -                                       IEEE80211_CHAN_NO_IBSS;
3543 +                                       IEEE80211_CHAN_NO_IR;
3544                         if (geo->a[i].flags & LIBIPW_CH_RADAR_DETECT)
3545                                 a_band->channels[i].flags |=
3546                                         IEEE80211_CHAN_RADAR;
3547 --- a/drivers/net/wireless/iwlegacy/3945-mac.c
3548 +++ b/drivers/net/wireless/iwlegacy/3945-mac.c
3549 @@ -1595,7 +1595,7 @@ il3945_get_channels_for_scan(struct il_p
3550                  *  and use long active_dwell time.
3551                  */
3552                 if (!is_active || il_is_channel_passive(ch_info) ||
3553 -                   (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
3554 +                   (chan->flags & IEEE80211_CHAN_NO_IR)) {
3555                         scan_ch->type = 0;      /* passive */
3556                         if (IL_UCODE_API(il->ucode_ver) == 1)
3557                                 scan_ch->active_dwell =
3558 --- a/drivers/net/wireless/iwlegacy/4965-mac.c
3559 +++ b/drivers/net/wireless/iwlegacy/4965-mac.c
3560 @@ -805,7 +805,7 @@ il4965_get_channels_for_scan(struct il_p
3561                 }
3562  
3563                 if (!is_active || il_is_channel_passive(ch_info) ||
3564 -                   (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
3565 +                   (chan->flags & IEEE80211_CHAN_NO_IR))
3566                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
3567                 else
3568                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
3569 --- a/drivers/net/wireless/iwlegacy/common.c
3570 +++ b/drivers/net/wireless/iwlegacy/common.c
3571 @@ -3447,10 +3447,10 @@ il_init_geos(struct il_priv *il)
3572  
3573                 if (il_is_channel_valid(ch)) {
3574               &nb