ath9k: merge another round of upstream (or -pending) fixes and cleanups
[openwrt.git] / package / kernel / mac80211 / patches / 300-pending_work.patch
1 --- a/drivers/net/wireless/ath/ath10k/mac.c
2 +++ b/drivers/net/wireless/ath/ath10k/mac.c
3 @@ -1351,12 +1351,12 @@ static int ath10k_update_channel_list(st
4                         ch->allow_vht = true;
5  
6                         ch->allow_ibss =
7 -                               !(channel->flags & IEEE80211_CHAN_NO_IBSS);
8 +                               !(channel->flags & IEEE80211_CHAN_NO_IR);
9  
10                         ch->ht40plus =
11                                 !(channel->flags & IEEE80211_CHAN_NO_HT40PLUS);
12  
13 -                       passive = channel->flags & IEEE80211_CHAN_PASSIVE_SCAN;
14 +                       passive = channel->flags & IEEE80211_CHAN_NO_IR;
15                         ch->passive = passive;
16  
17                         ch->freq = channel->center_freq;
18 --- a/drivers/net/wireless/ath/ath9k/Kconfig
19 +++ b/drivers/net/wireless/ath/ath9k/Kconfig
20 @@ -90,7 +90,7 @@ config ATH9K_DFS_CERTIFIED
21  
22  config ATH9K_TX99
23         bool "Atheros ath9k TX99 testing support"
24 -       depends on CFG80211_CERTIFICATION_ONUS
25 +       depends on ATH9K_DEBUGFS && CFG80211_CERTIFICATION_ONUS
26         default n
27         ---help---
28           Say N. This should only be enabled on systems undergoing
29 @@ -108,6 +108,14 @@ config ATH9K_TX99
30           be evaluated to meet the RF exposure limits set forth in the
31           governmental SAR regulations.
32  
33 +config ATH9K_WOW
34 +       bool "Wake on Wireless LAN support (EXPERIMENTAL)"
35 +       depends on ATH9K && PM
36 +       default n
37 +       ---help---
38 +         This option enables Wake on Wireless LAN support for certain cards.
39 +         Currently, AR9462 is supported.
40 +
41  config ATH9K_LEGACY_RATE_CONTROL
42         bool "Atheros ath9k rate control"
43         depends on ATH9K
44 --- a/drivers/net/wireless/ath/ath9k/Makefile
45 +++ b/drivers/net/wireless/ath/ath9k/Makefile
46 @@ -11,11 +11,13 @@ ath9k-$(CPTCFG_ATH9K_BTCOEX_SUPPORT) += 
47  ath9k-$(CPTCFG_ATH9K_LEGACY_RATE_CONTROL) += rc.o
48  ath9k-$(CPTCFG_ATH9K_PCI) += pci.o
49  ath9k-$(CPTCFG_ATH9K_AHB) += ahb.o
50 -ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o
51  ath9k-$(CPTCFG_ATH9K_DFS_DEBUGFS) += dfs_debug.o
52 -ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += \
53 -               dfs.o
54 -ath9k-$(CONFIG_PM_SLEEP) += wow.o
55 +ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += dfs.o
56 +ath9k-$(CPTCFG_ATH9K_TX99) += tx99.o
57 +ath9k-$(CPTCFG_ATH9K_WOW) += wow.o
58 +
59 +ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o \
60 +                                spectral.o
61  
62  obj-$(CPTCFG_ATH9K) += ath9k.o
63  
64 @@ -41,6 +43,8 @@ ath9k_hw-y:=  \
65                 ar9003_eeprom.o \
66                 ar9003_paprd.o
67  
68 +ath9k_hw-$(CPTCFG_ATH9K_WOW) += ar9003_wow.o
69 +
70  ath9k_hw-$(CPTCFG_ATH9K_BTCOEX_SUPPORT) += btcoex.o \
71                                            ar9003_mci.o
72  obj-$(CPTCFG_ATH9K_HW) += ath9k_hw.o
73 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
74 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
75 @@ -17,6 +17,7 @@
76  #include "hw.h"
77  #include "ar9003_mac.h"
78  #include "ar9003_2p2_initvals.h"
79 +#include "ar9003_buffalo_initvals.h"
80  #include "ar9485_initvals.h"
81  #include "ar9340_initvals.h"
82  #include "ar9330_1p1_initvals.h"
83 @@ -26,6 +27,7 @@
84  #include "ar9462_2p0_initvals.h"
85  #include "ar9462_2p1_initvals.h"
86  #include "ar9565_1p0_initvals.h"
87 +#include "ar9565_1p1_initvals.h"
88  
89  /* General hardware code for the AR9003 hadware family */
90  
91 @@ -148,7 +150,11 @@ static void ar9003_hw_init_mode_regs(str
92                                 ar9340Modes_high_ob_db_tx_gain_table_1p0);
93  
94                 INIT_INI_ARRAY(&ah->iniModesFastClock,
95 -                               ar9340Modes_fast_clock_1p0);
96 +                              ar9340Modes_fast_clock_1p0);
97 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
98 +                              ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
99 +               INIT_INI_ARRAY(&ah->ini_dfs,
100 +                              ar9340_1p0_baseband_postamble_dfs_channel);
101  
102                 if (!ah->is_clk_25mhz)
103                         INIT_INI_ARRAY(&ah->iniAdditional,
104 @@ -187,17 +193,17 @@ static void ar9003_hw_init_mode_regs(str
105                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
106                                ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
107  
108 -               /* Load PCIE SERDES settings from INI */
109 -
110 -               /* Awake Setting */
111 -
112 -               INIT_INI_ARRAY(&ah->iniPcieSerdes,
113 -                               ar9485_1_1_pcie_phy_clkreq_disable_L1);
114 -
115 -               /* Sleep Setting */
116 -
117 -               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
118 -                               ar9485_1_1_pcie_phy_clkreq_disable_L1);
119 +               if (ah->config.no_pll_pwrsave) {
120 +                       INIT_INI_ARRAY(&ah->iniPcieSerdes,
121 +                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
122 +                       INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
123 +                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
124 +               } else {
125 +                       INIT_INI_ARRAY(&ah->iniPcieSerdes,
126 +                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
127 +                       INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
128 +                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
129 +               }
130         } else if (AR_SREV_9462_21(ah)) {
131                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
132                                ar9462_2p1_mac_core);
133 @@ -223,6 +229,10 @@ static void ar9003_hw_init_mode_regs(str
134                                ar9462_2p1_modes_fast_clock);
135                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
136                                ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
137 +               INIT_INI_ARRAY(&ah->iniPcieSerdes,
138 +                              ar9462_2p1_pciephy_clkreq_disable_L1);
139 +               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
140 +                              ar9462_2p1_pciephy_clkreq_disable_L1);
141         } else if (AR_SREV_9462_20(ah)) {
142  
143                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
144 @@ -247,18 +257,18 @@ static void ar9003_hw_init_mode_regs(str
145                                 ar9462_2p0_soc_postamble);
146  
147                 INIT_INI_ARRAY(&ah->iniModesRxGain,
148 -                               ar9462_common_rx_gain_table_2p0);
149 +                               ar9462_2p0_common_rx_gain);
150  
151                 /* Awake -> Sleep Setting */
152                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
153 -                              ar9462_pciephy_clkreq_disable_L1_2p0);
154 +                              ar9462_2p0_pciephy_clkreq_disable_L1);
155                 /* Sleep -> Awake Setting */
156                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
157 -                              ar9462_pciephy_clkreq_disable_L1_2p0);
158 +                              ar9462_2p0_pciephy_clkreq_disable_L1);
159  
160                 /* Fast clock modal settings */
161                 INIT_INI_ARRAY(&ah->iniModesFastClock,
162 -                               ar9462_modes_fast_clock_2p0);
163 +                               ar9462_2p0_modes_fast_clock);
164  
165                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
166                                ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
167 @@ -330,7 +340,46 @@ static void ar9003_hw_init_mode_regs(str
168                                 ar9580_1p0_low_ob_db_tx_gain_table);
169  
170                 INIT_INI_ARRAY(&ah->iniModesFastClock,
171 -                               ar9580_1p0_modes_fast_clock);
172 +                              ar9580_1p0_modes_fast_clock);
173 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
174 +                              ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
175 +               INIT_INI_ARRAY(&ah->ini_dfs,
176 +                              ar9580_1p0_baseband_postamble_dfs_channel);
177 +       } else if (AR_SREV_9565_11_OR_LATER(ah)) {
178 +               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
179 +                              ar9565_1p1_mac_core);
180 +               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
181 +                              ar9565_1p1_mac_postamble);
182 +
183 +               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
184 +                              ar9565_1p1_baseband_core);
185 +               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
186 +                              ar9565_1p1_baseband_postamble);
187 +
188 +               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
189 +                              ar9565_1p1_radio_core);
190 +               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
191 +                              ar9565_1p1_radio_postamble);
192 +
193 +               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
194 +                              ar9565_1p1_soc_preamble);
195 +               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
196 +                              ar9565_1p1_soc_postamble);
197 +
198 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
199 +                              ar9565_1p1_Common_rx_gain_table);
200 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
201 +                              ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
202 +
203 +               INIT_INI_ARRAY(&ah->iniPcieSerdes,
204 +                              ar9565_1p1_pciephy_clkreq_disable_L1);
205 +               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
206 +                              ar9565_1p1_pciephy_clkreq_disable_L1);
207 +
208 +               INIT_INI_ARRAY(&ah->iniModesFastClock,
209 +                               ar9565_1p1_modes_fast_clock);
210 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
211 +                              ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
212         } else if (AR_SREV_9565(ah)) {
213                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
214                                ar9565_1p0_mac_core);
215 @@ -411,7 +460,11 @@ static void ar9003_hw_init_mode_regs(str
216  
217                 /* Fast clock modal settings */
218                 INIT_INI_ARRAY(&ah->iniModesFastClock,
219 -                               ar9300Modes_fast_clock_2p2);
220 +                              ar9300Modes_fast_clock_2p2);
221 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
222 +                              ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
223 +               INIT_INI_ARRAY(&ah->ini_dfs,
224 +                              ar9300_2p2_baseband_postamble_dfs_channel);
225         }
226  }
227  
228 @@ -440,7 +493,10 @@ static void ar9003_tx_gain_table_mode0(s
229                         ar9462_2p1_modes_low_ob_db_tx_gain);
230         else if (AR_SREV_9462_20(ah))
231                 INIT_INI_ARRAY(&ah->iniModesTxGain,
232 -                       ar9462_modes_low_ob_db_tx_gain_table_2p0);
233 +                       ar9462_2p0_modes_low_ob_db_tx_gain);
234 +       else if (AR_SREV_9565_11(ah))
235 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
236 +                              ar9565_1p1_modes_low_ob_db_tx_gain_table);
237         else if (AR_SREV_9565(ah))
238                 INIT_INI_ARRAY(&ah->iniModesTxGain,
239                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
240 @@ -474,7 +530,10 @@ static void ar9003_tx_gain_table_mode1(s
241                         ar9462_2p1_modes_high_ob_db_tx_gain);
242         else if (AR_SREV_9462_20(ah))
243                 INIT_INI_ARRAY(&ah->iniModesTxGain,
244 -                       ar9462_modes_high_ob_db_tx_gain_table_2p0);
245 +                       ar9462_2p0_modes_high_ob_db_tx_gain);
246 +       else if (AR_SREV_9565_11(ah))
247 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
248 +                              ar9565_1p1_modes_high_ob_db_tx_gain_table);
249         else if (AR_SREV_9565(ah))
250                 INIT_INI_ARRAY(&ah->iniModesTxGain,
251                                ar9565_1p0_modes_high_ob_db_tx_gain_table);
252 @@ -500,6 +559,9 @@ static void ar9003_tx_gain_table_mode2(s
253         else if (AR_SREV_9580(ah))
254                 INIT_INI_ARRAY(&ah->iniModesTxGain,
255                         ar9580_1p0_low_ob_db_tx_gain_table);
256 +       else if (AR_SREV_9565_11(ah))
257 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
258 +                              ar9565_1p1_modes_low_ob_db_tx_gain_table);
259         else if (AR_SREV_9565(ah))
260                 INIT_INI_ARRAY(&ah->iniModesTxGain,
261                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
262 @@ -525,12 +587,20 @@ static void ar9003_tx_gain_table_mode3(s
263         else if (AR_SREV_9580(ah))
264                 INIT_INI_ARRAY(&ah->iniModesTxGain,
265                         ar9580_1p0_high_power_tx_gain_table);
266 +       else if (AR_SREV_9565_11(ah))
267 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
268 +                              ar9565_1p1_modes_high_power_tx_gain_table);
269         else if (AR_SREV_9565(ah))
270                 INIT_INI_ARRAY(&ah->iniModesTxGain,
271                                ar9565_1p0_modes_high_power_tx_gain_table);
272 -       else
273 -               INIT_INI_ARRAY(&ah->iniModesTxGain,
274 -                       ar9300Modes_high_power_tx_gain_table_2p2);
275 +       else {
276 +               if (ah->config.tx_gain_buffalo)
277 +                       INIT_INI_ARRAY(&ah->iniModesTxGain,
278 +                                      ar9300Modes_high_power_tx_gain_table_buffalo);
279 +               else
280 +                       INIT_INI_ARRAY(&ah->iniModesTxGain,
281 +                                      ar9300Modes_high_power_tx_gain_table_2p2);
282 +       }
283  }
284  
285  static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
286 @@ -546,7 +616,7 @@ static void ar9003_tx_gain_table_mode4(s
287                        ar9462_2p1_modes_mix_ob_db_tx_gain);
288         else if (AR_SREV_9462_20(ah))
289                 INIT_INI_ARRAY(&ah->iniModesTxGain,
290 -                      ar9462_modes_mix_ob_db_tx_gain_table_2p0);
291 +                      ar9462_2p0_modes_mix_ob_db_tx_gain);
292         else
293                 INIT_INI_ARRAY(&ah->iniModesTxGain,
294                         ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
295 @@ -581,6 +651,13 @@ static void ar9003_tx_gain_table_mode6(s
296                         ar9580_1p0_type6_tx_gain_table);
297  }
298  
299 +static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
300 +{
301 +       if (AR_SREV_9340(ah))
302 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
303 +                              ar9340_cus227_tx_gain_table_1p0);
304 +}
305 +
306  typedef void (*ath_txgain_tab)(struct ath_hw *ah);
307  
308  static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
309 @@ -593,6 +670,7 @@ static void ar9003_tx_gain_table_apply(s
310                 ar9003_tx_gain_table_mode4,
311                 ar9003_tx_gain_table_mode5,
312                 ar9003_tx_gain_table_mode6,
313 +               ar9003_tx_gain_table_mode7,
314         };
315         int idx = ar9003_hw_get_tx_gain_idx(ah);
316  
317 @@ -629,7 +707,10 @@ static void ar9003_rx_gain_table_mode0(s
318                                 ar9462_2p1_common_rx_gain);
319         else if (AR_SREV_9462_20(ah))
320                 INIT_INI_ARRAY(&ah->iniModesRxGain,
321 -                               ar9462_common_rx_gain_table_2p0);
322 +                               ar9462_2p0_common_rx_gain);
323 +       else if (AR_SREV_9565_11(ah))
324 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
325 +                              ar9565_1p1_Common_rx_gain_table);
326         else if (AR_SREV_9565(ah))
327                 INIT_INI_ARRAY(&ah->iniModesRxGain,
328                                ar9565_1p0_Common_rx_gain_table);
329 @@ -657,7 +738,7 @@ static void ar9003_rx_gain_table_mode1(s
330                         ar9462_2p1_common_wo_xlna_rx_gain);
331         else if (AR_SREV_9462_20(ah))
332                 INIT_INI_ARRAY(&ah->iniModesRxGain,
333 -                       ar9462_common_wo_xlna_rx_gain_table_2p0);
334 +                       ar9462_2p0_common_wo_xlna_rx_gain);
335         else if (AR_SREV_9550(ah)) {
336                 INIT_INI_ARRAY(&ah->iniModesRxGain,
337                         ar955x_1p0_common_wo_xlna_rx_gain_table);
338 @@ -666,6 +747,9 @@ static void ar9003_rx_gain_table_mode1(s
339         } else if (AR_SREV_9580(ah))
340                 INIT_INI_ARRAY(&ah->iniModesRxGain,
341                         ar9580_1p0_wo_xlna_rx_gain_table);
342 +       else if (AR_SREV_9565_11(ah))
343 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
344 +                              ar9565_1p1_common_wo_xlna_rx_gain_table);
345         else if (AR_SREV_9565(ah))
346                 INIT_INI_ARRAY(&ah->iniModesRxGain,
347                                ar9565_1p0_common_wo_xlna_rx_gain_table);
348 @@ -687,7 +771,7 @@ static void ar9003_rx_gain_table_mode2(s
349                                ar9462_2p1_baseband_postamble_5g_xlna);
350         } else if (AR_SREV_9462_20(ah)) {
351                 INIT_INI_ARRAY(&ah->iniModesRxGain,
352 -                              ar9462_common_mixed_rx_gain_table_2p0);
353 +                              ar9462_2p0_common_mixed_rx_gain);
354                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
355                                ar9462_2p0_baseband_core_mix_rxgain);
356                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
357 @@ -701,12 +785,12 @@ static void ar9003_rx_gain_table_mode3(s
358  {
359         if (AR_SREV_9462_21(ah)) {
360                 INIT_INI_ARRAY(&ah->iniModesRxGain,
361 -                              ar9462_2p1_common_5g_xlna_only_rx_gain);
362 +                              ar9462_2p1_common_5g_xlna_only_rxgain);
363                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
364                                ar9462_2p1_baseband_postamble_5g_xlna);
365         } else if (AR_SREV_9462_20(ah)) {
366                 INIT_INI_ARRAY(&ah->iniModesRxGain,
367 -                              ar9462_2p0_5g_xlna_only_rxgain);
368 +                              ar9462_2p0_common_5g_xlna_only_rxgain);
369                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
370                                ar9462_2p0_baseband_postamble_5g_xlna);
371         }
372 @@ -750,6 +834,9 @@ static void ar9003_hw_init_mode_gain_reg
373  static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
374                                          bool power_off)
375  {
376 +       unsigned int i;
377 +       struct ar5416IniArray *array;
378 +
379         /*
380          * Increase L1 Entry Latency. Some WB222 boards don't have
381          * this change in eeprom/OTP.
382 @@ -775,18 +862,13 @@ static void ar9003_hw_configpcipowersave
383          * Configire PCIE after Ini init. SERDES values now come from ini file
384          * This enables PCIe low power mode.
385          */
386 -       if (ah->config.pcieSerDesWrite) {
387 -               unsigned int i;
388 -               struct ar5416IniArray *array;
389 -
390 -               array = power_off ? &ah->iniPcieSerdes :
391 -                                   &ah->iniPcieSerdesLowPower;
392 -
393 -               for (i = 0; i < array->ia_rows; i++) {
394 -                       REG_WRITE(ah,
395 -                                 INI_RA(array, i, 0),
396 -                                 INI_RA(array, i, 1));
397 -               }
398 +       array = power_off ? &ah->iniPcieSerdes :
399 +               &ah->iniPcieSerdesLowPower;
400 +
401 +       for (i = 0; i < array->ia_rows; i++) {
402 +               REG_WRITE(ah,
403 +                         INI_RA(array, i, 0),
404 +                         INI_RA(array, i, 1));
405         }
406  }
407  
408 --- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
409 +++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
410 @@ -18,6 +18,20 @@
411  #ifndef INITVALS_9340_H
412  #define INITVALS_9340_H
413  
414 +#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
415 +
416 +#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
417 +
418 +#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
419 +
420 +#define ar9340Common_rx_gain_table_1p0 ar9300Common_rx_gain_table_2p2
421 +
422 +#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
423 +
424 +#define ar9340_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
425 +
426 +#define ar9340_1p0_baseband_postamble_dfs_channel ar9300_2p2_baseband_postamble_dfs_channel
427 +
428  static const u32 ar9340_1p0_radio_postamble[][5] = {
429         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
430         {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
431 @@ -100,8 +114,6 @@ static const u32 ar9340Modes_lowest_ob_d
432         {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
433  };
434  
435 -#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
436 -
437  static const u32 ar9340_1p0_radio_core[][2] = {
438         /* Addr      allmodes  */
439         {0x00016000, 0x36db6db6},
440 @@ -215,16 +227,12 @@ static const u32 ar9340_1p0_radio_core_4
441         {0x0000824c, 0x0001e800},
442  };
443  
444 -#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
445 -
446 -#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
447 -
448  static const u32 ar9340_1p0_baseband_postamble[][5] = {
449         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
450         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
451         {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e},
452         {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
453 -       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
454 +       {0x00009828, 0x06903081, 0x06903081, 0x09103881, 0x09103881},
455         {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
456         {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
457         {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
458 @@ -340,9 +348,9 @@ static const u32 ar9340_1p0_baseband_cor
459         {0x0000a370, 0x00000000},
460         {0x0000a390, 0x00000001},
461         {0x0000a394, 0x00000444},
462 -       {0x0000a398, 0x001f0e0f},
463 -       {0x0000a39c, 0x0075393f},
464 -       {0x0000a3a0, 0xb79f6427},
465 +       {0x0000a398, 0x00000000},
466 +       {0x0000a39c, 0x210d0401},
467 +       {0x0000a3a0, 0xab9a7144},
468         {0x0000a3a4, 0x00000000},
469         {0x0000a3a8, 0xaaaaaaaa},
470         {0x0000a3ac, 0x3c466478},
471 @@ -714,266 +722,6 @@ static const u32 ar9340Modes_ub124_tx_ga
472         {0x0000b2e8, 0xfffe0000, 0xfffe0000, 0xfffc0000, 0xfffc0000},
473  };
474  
475 -static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
476 -       /* Addr      allmodes  */
477 -       {0x0000a000, 0x00010000},
478 -       {0x0000a004, 0x00030002},
479 -       {0x0000a008, 0x00050004},
480 -       {0x0000a00c, 0x00810080},
481 -       {0x0000a010, 0x00830082},
482 -       {0x0000a014, 0x01810180},
483 -       {0x0000a018, 0x01830182},
484 -       {0x0000a01c, 0x01850184},
485 -       {0x0000a020, 0x01890188},
486 -       {0x0000a024, 0x018b018a},
487 -       {0x0000a028, 0x018d018c},
488 -       {0x0000a02c, 0x01910190},
489 -       {0x0000a030, 0x01930192},
490 -       {0x0000a034, 0x01950194},
491 -       {0x0000a038, 0x038a0196},
492 -       {0x0000a03c, 0x038c038b},
493 -       {0x0000a040, 0x0390038d},
494 -       {0x0000a044, 0x03920391},
495 -       {0x0000a048, 0x03940393},
496 -       {0x0000a04c, 0x03960395},
497 -       {0x0000a050, 0x00000000},
498 -       {0x0000a054, 0x00000000},
499 -       {0x0000a058, 0x00000000},
500 -       {0x0000a05c, 0x00000000},
501 -       {0x0000a060, 0x00000000},
502 -       {0x0000a064, 0x00000000},
503 -       {0x0000a068, 0x00000000},
504 -       {0x0000a06c, 0x00000000},
505 -       {0x0000a070, 0x00000000},
506 -       {0x0000a074, 0x00000000},
507 -       {0x0000a078, 0x00000000},
508 -       {0x0000a07c, 0x00000000},
509 -       {0x0000a080, 0x22222229},
510 -       {0x0000a084, 0x1d1d1d1d},
511 -       {0x0000a088, 0x1d1d1d1d},
512 -       {0x0000a08c, 0x1d1d1d1d},
513 -       {0x0000a090, 0x171d1d1d},
514 -       {0x0000a094, 0x11111717},
515 -       {0x0000a098, 0x00030311},
516 -       {0x0000a09c, 0x00000000},
517 -       {0x0000a0a0, 0x00000000},
518 -       {0x0000a0a4, 0x00000000},
519 -       {0x0000a0a8, 0x00000000},
520 -       {0x0000a0ac, 0x00000000},
521 -       {0x0000a0b0, 0x00000000},
522 -       {0x0000a0b4, 0x00000000},
523 -       {0x0000a0b8, 0x00000000},
524 -       {0x0000a0bc, 0x00000000},
525 -       {0x0000a0c0, 0x001f0000},
526 -       {0x0000a0c4, 0x01000101},
527 -       {0x0000a0c8, 0x011e011f},
528 -       {0x0000a0cc, 0x011c011d},
529 -       {0x0000a0d0, 0x02030204},
530 -       {0x0000a0d4, 0x02010202},
531 -       {0x0000a0d8, 0x021f0200},
532 -       {0x0000a0dc, 0x0302021e},
533 -       {0x0000a0e0, 0x03000301},
534 -       {0x0000a0e4, 0x031e031f},
535 -       {0x0000a0e8, 0x0402031d},
536 -       {0x0000a0ec, 0x04000401},
537 -       {0x0000a0f0, 0x041e041f},
538 -       {0x0000a0f4, 0x0502041d},
539 -       {0x0000a0f8, 0x05000501},
540 -       {0x0000a0fc, 0x051e051f},
541 -       {0x0000a100, 0x06010602},
542 -       {0x0000a104, 0x061f0600},
543 -       {0x0000a108, 0x061d061e},
544 -       {0x0000a10c, 0x07020703},
545 -       {0x0000a110, 0x07000701},
546 -       {0x0000a114, 0x00000000},
547 -       {0x0000a118, 0x00000000},
548 -       {0x0000a11c, 0x00000000},
549 -       {0x0000a120, 0x00000000},
550 -       {0x0000a124, 0x00000000},
551 -       {0x0000a128, 0x00000000},
552 -       {0x0000a12c, 0x00000000},
553 -       {0x0000a130, 0x00000000},
554 -       {0x0000a134, 0x00000000},
555 -       {0x0000a138, 0x00000000},
556 -       {0x0000a13c, 0x00000000},
557 -       {0x0000a140, 0x001f0000},
558 -       {0x0000a144, 0x01000101},
559 -       {0x0000a148, 0x011e011f},
560 -       {0x0000a14c, 0x011c011d},
561 -       {0x0000a150, 0x02030204},
562 -       {0x0000a154, 0x02010202},
563 -       {0x0000a158, 0x021f0200},
564 -       {0x0000a15c, 0x0302021e},
565 -       {0x0000a160, 0x03000301},
566 -       {0x0000a164, 0x031e031f},
567 -       {0x0000a168, 0x0402031d},
568 -       {0x0000a16c, 0x04000401},
569 -       {0x0000a170, 0x041e041f},
570 -       {0x0000a174, 0x0502041d},
571 -       {0x0000a178, 0x05000501},
572 -       {0x0000a17c, 0x051e051f},
573 -       {0x0000a180, 0x06010602},
574 -       {0x0000a184, 0x061f0600},
575 -       {0x0000a188, 0x061d061e},
576 -       {0x0000a18c, 0x07020703},
577 -       {0x0000a190, 0x07000701},
578 -       {0x0000a194, 0x00000000},
579 -       {0x0000a198, 0x00000000},
580 -       {0x0000a19c, 0x00000000},
581 -       {0x0000a1a0, 0x00000000},
582 -       {0x0000a1a4, 0x00000000},
583 -       {0x0000a1a8, 0x00000000},
584 -       {0x0000a1ac, 0x00000000},
585 -       {0x0000a1b0, 0x00000000},
586 -       {0x0000a1b4, 0x00000000},
587 -       {0x0000a1b8, 0x00000000},
588 -       {0x0000a1bc, 0x00000000},
589 -       {0x0000a1c0, 0x00000000},
590 -       {0x0000a1c4, 0x00000000},
591 -       {0x0000a1c8, 0x00000000},
592 -       {0x0000a1cc, 0x00000000},
593 -       {0x0000a1d0, 0x00000000},
594 -       {0x0000a1d4, 0x00000000},
595 -       {0x0000a1d8, 0x00000000},
596 -       {0x0000a1dc, 0x00000000},
597 -       {0x0000a1e0, 0x00000000},
598 -       {0x0000a1e4, 0x00000000},
599 -       {0x0000a1e8, 0x00000000},
600 -       {0x0000a1ec, 0x00000000},
601 -       {0x0000a1f0, 0x00000396},
602 -       {0x0000a1f4, 0x00000396},
603 -       {0x0000a1f8, 0x00000396},
604 -       {0x0000a1fc, 0x00000196},
605 -       {0x0000b000, 0x00010000},
606 -       {0x0000b004, 0x00030002},
607 -       {0x0000b008, 0x00050004},
608 -       {0x0000b00c, 0x00810080},
609 -       {0x0000b010, 0x00830082},
610 -       {0x0000b014, 0x01810180},
611 -       {0x0000b018, 0x01830182},
612 -       {0x0000b01c, 0x01850184},
613 -       {0x0000b020, 0x02810280},
614 -       {0x0000b024, 0x02830282},
615 -       {0x0000b028, 0x02850284},
616 -       {0x0000b02c, 0x02890288},
617 -       {0x0000b030, 0x028b028a},
618 -       {0x0000b034, 0x0388028c},
619 -       {0x0000b038, 0x038a0389},
620 -       {0x0000b03c, 0x038c038b},
621 -       {0x0000b040, 0x0390038d},
622 -       {0x0000b044, 0x03920391},
623 -       {0x0000b048, 0x03940393},
624 -       {0x0000b04c, 0x03960395},
625 -       {0x0000b050, 0x00000000},
626 -       {0x0000b054, 0x00000000},
627 -       {0x0000b058, 0x00000000},
628 -       {0x0000b05c, 0x00000000},
629 -       {0x0000b060, 0x00000000},
630 -       {0x0000b064, 0x00000000},
631 -       {0x0000b068, 0x00000000},
632 -       {0x0000b06c, 0x00000000},
633 -       {0x0000b070, 0x00000000},
634 -       {0x0000b074, 0x00000000},
635 -       {0x0000b078, 0x00000000},
636 -       {0x0000b07c, 0x00000000},
637 -       {0x0000b080, 0x23232323},
638 -       {0x0000b084, 0x21232323},
639 -       {0x0000b088, 0x19191c1e},
640 -       {0x0000b08c, 0x12141417},
641 -       {0x0000b090, 0x07070e0e},
642 -       {0x0000b094, 0x03030305},
643 -       {0x0000b098, 0x00000003},
644 -       {0x0000b09c, 0x00000000},
645 -       {0x0000b0a0, 0x00000000},
646 -       {0x0000b0a4, 0x00000000},
647 -       {0x0000b0a8, 0x00000000},
648 -       {0x0000b0ac, 0x00000000},
649 -       {0x0000b0b0, 0x00000000},
650 -       {0x0000b0b4, 0x00000000},
651 -       {0x0000b0b8, 0x00000000},
652 -       {0x0000b0bc, 0x00000000},
653 -       {0x0000b0c0, 0x003f0020},
654 -       {0x0000b0c4, 0x00400041},
655 -       {0x0000b0c8, 0x0140005f},
656 -       {0x0000b0cc, 0x0160015f},
657 -       {0x0000b0d0, 0x017e017f},
658 -       {0x0000b0d4, 0x02410242},
659 -       {0x0000b0d8, 0x025f0240},
660 -       {0x0000b0dc, 0x027f0260},
661 -       {0x0000b0e0, 0x0341027e},
662 -       {0x0000b0e4, 0x035f0340},
663 -       {0x0000b0e8, 0x037f0360},
664 -       {0x0000b0ec, 0x04400441},
665 -       {0x0000b0f0, 0x0460045f},
666 -       {0x0000b0f4, 0x0541047f},
667 -       {0x0000b0f8, 0x055f0540},
668 -       {0x0000b0fc, 0x057f0560},
669 -       {0x0000b100, 0x06400641},
670 -       {0x0000b104, 0x0660065f},
671 -       {0x0000b108, 0x067e067f},
672 -       {0x0000b10c, 0x07410742},
673 -       {0x0000b110, 0x075f0740},
674 -       {0x0000b114, 0x077f0760},
675 -       {0x0000b118, 0x07800781},
676 -       {0x0000b11c, 0x07a0079f},
677 -       {0x0000b120, 0x07c107bf},
678 -       {0x0000b124, 0x000007c0},
679 -       {0x0000b128, 0x00000000},
680 -       {0x0000b12c, 0x00000000},
681 -       {0x0000b130, 0x00000000},
682 -       {0x0000b134, 0x00000000},
683 -       {0x0000b138, 0x00000000},
684 -       {0x0000b13c, 0x00000000},
685 -       {0x0000b140, 0x003f0020},
686 -       {0x0000b144, 0x00400041},
687 -       {0x0000b148, 0x0140005f},
688 -       {0x0000b14c, 0x0160015f},
689 -       {0x0000b150, 0x017e017f},
690 -       {0x0000b154, 0x02410242},
691 -       {0x0000b158, 0x025f0240},
692 -       {0x0000b15c, 0x027f0260},
693 -       {0x0000b160, 0x0341027e},
694 -       {0x0000b164, 0x035f0340},
695 -       {0x0000b168, 0x037f0360},
696 -       {0x0000b16c, 0x04400441},
697 -       {0x0000b170, 0x0460045f},
698 -       {0x0000b174, 0x0541047f},
699 -       {0x0000b178, 0x055f0540},
700 -       {0x0000b17c, 0x057f0560},
701 -       {0x0000b180, 0x06400641},
702 -       {0x0000b184, 0x0660065f},
703 -       {0x0000b188, 0x067e067f},
704 -       {0x0000b18c, 0x07410742},
705 -       {0x0000b190, 0x075f0740},
706 -       {0x0000b194, 0x077f0760},
707 -       {0x0000b198, 0x07800781},
708 -       {0x0000b19c, 0x07a0079f},
709 -       {0x0000b1a0, 0x07c107bf},
710 -       {0x0000b1a4, 0x000007c0},
711 -       {0x0000b1a8, 0x00000000},
712 -       {0x0000b1ac, 0x00000000},
713 -       {0x0000b1b0, 0x00000000},
714 -       {0x0000b1b4, 0x00000000},
715 -       {0x0000b1b8, 0x00000000},
716 -       {0x0000b1bc, 0x00000000},
717 -       {0x0000b1c0, 0x00000000},
718 -       {0x0000b1c4, 0x00000000},
719 -       {0x0000b1c8, 0x00000000},
720 -       {0x0000b1cc, 0x00000000},
721 -       {0x0000b1d0, 0x00000000},
722 -       {0x0000b1d4, 0x00000000},
723 -       {0x0000b1d8, 0x00000000},
724 -       {0x0000b1dc, 0x00000000},
725 -       {0x0000b1e0, 0x00000000},
726 -       {0x0000b1e4, 0x00000000},
727 -       {0x0000b1e8, 0x00000000},
728 -       {0x0000b1ec, 0x00000000},
729 -       {0x0000b1f0, 0x00000396},
730 -       {0x0000b1f4, 0x00000396},
731 -       {0x0000b1f8, 0x00000396},
732 -       {0x0000b1fc, 0x00000196},
733 -};
734 -
735  static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
736         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
737         {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
738 @@ -1437,8 +1185,6 @@ static const u32 ar9340_1p0_mac_core[][2
739         {0x000083d0, 0x000101ff},
740  };
741  
742 -#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
743 -
744  static const u32 ar9340_1p0_soc_preamble[][2] = {
745         /* Addr      allmodes  */
746         {0x00007008, 0x00000000},
747 @@ -1447,4 +1193,106 @@ static const u32 ar9340_1p0_soc_preamble
748         {0x00007038, 0x000004c2},
749  };
750  
751 +static const u32 ar9340_cus227_tx_gain_table_1p0[][5] = {
752 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
753 +       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
754 +       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
755 +       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
756 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
757 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
758 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
759 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
760 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
761 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
762 +       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
763 +       {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400},
764 +       {0x0000a518, 0x21002220, 0x21002220, 0x15000402, 0x15000402},
765 +       {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
766 +       {0x0000a520, 0x2c022220, 0x2c022220, 0x1b000603, 0x1b000603},
767 +       {0x0000a524, 0x30022222, 0x30022222, 0x1f000a02, 0x1f000a02},
768 +       {0x0000a528, 0x35022225, 0x35022225, 0x23000a04, 0x23000a04},
769 +       {0x0000a52c, 0x3b02222a, 0x3b02222a, 0x26000a20, 0x26000a20},
770 +       {0x0000a530, 0x3f02222c, 0x3f02222c, 0x2a000e20, 0x2a000e20},
771 +       {0x0000a534, 0x4202242a, 0x4202242a, 0x2e000e22, 0x2e000e22},
772 +       {0x0000a538, 0x4702244a, 0x4702244a, 0x31000e24, 0x31000e24},
773 +       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x34001640, 0x34001640},
774 +       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660},
775 +       {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861},
776 +       {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81},
777 +       {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x42001a83, 0x42001a83},
778 +       {0x0000a550, 0x61024a6c, 0x61024a6c, 0x44001c84, 0x44001c84},
779 +       {0x0000a554, 0x66026a6c, 0x66026a6c, 0x48001ce3, 0x48001ce3},
780 +       {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x4c001ce5, 0x4c001ce5},
781 +       {0x0000a55c, 0x7002708c, 0x7002708c, 0x50001ce9, 0x50001ce9},
782 +       {0x0000a560, 0x7302b08a, 0x7302b08a, 0x54001ceb, 0x54001ceb},
783 +       {0x0000a564, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
784 +       {0x0000a568, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
785 +       {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
786 +       {0x0000a570, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
787 +       {0x0000a574, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
788 +       {0x0000a578, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
789 +       {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
790 +       {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
791 +       {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
792 +       {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
793 +       {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
794 +       {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
795 +       {0x0000a594, 0x1c800223, 0x1c800223, 0x11800400, 0x11800400},
796 +       {0x0000a598, 0x21820220, 0x21820220, 0x15800402, 0x15800402},
797 +       {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
798 +       {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800603, 0x1b800603},
799 +       {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800a02, 0x1f800a02},
800 +       {0x0000a5a8, 0x34822225, 0x34822225, 0x23800a04, 0x23800a04},
801 +       {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x26800a20, 0x26800a20},
802 +       {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2a800e20, 0x2a800e20},
803 +       {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2e800e22, 0x2e800e22},
804 +       {0x0000a5b8, 0x4782244a, 0x4782244a, 0x31800e24, 0x31800e24},
805 +       {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x34801640, 0x34801640},
806 +       {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38801660, 0x38801660},
807 +       {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3b801861, 0x3b801861},
808 +       {0x0000a5c8, 0x5782286c, 0x5782286c, 0x3e801a81, 0x3e801a81},
809 +       {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x42801a83, 0x42801a83},
810 +       {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x44801c84, 0x44801c84},
811 +       {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x48801ce3, 0x48801ce3},
812 +       {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x4c801ce5, 0x4c801ce5},
813 +       {0x0000a5dc, 0x7086308c, 0x7086308c, 0x50801ce9, 0x50801ce9},
814 +       {0x0000a5e0, 0x738a308a, 0x738a308a, 0x54801ceb, 0x54801ceb},
815 +       {0x0000a5e4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
816 +       {0x0000a5e8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
817 +       {0x0000a5ec, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
818 +       {0x0000a5f0, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
819 +       {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
820 +       {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
821 +       {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
822 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
823 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
824 +       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
825 +       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
826 +       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
827 +       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
828 +       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
829 +       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
830 +       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
831 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
832 +       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
833 +       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
834 +       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
835 +       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
836 +       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
837 +       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
838 +       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
839 +       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
840 +       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
841 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
842 +       {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
843 +       {0x00016048, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
844 +       {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
845 +       {0x00016288, 0x30318000, 0x30318000, 0x00318000, 0x00318000},
846 +       {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
847 +       {0x00016448, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
848 +       {0x0000a3a4, 0x00000011, 0x00000011, 0x00000011, 0x00000011},
849 +       {0x0000a3a8, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c},
850 +       {0x0000a3ac, 0x30303030, 0x30303030, 0x30303030, 0x30303030},
851 +};
852 +
853  #endif /* INITVALS_9340_H */
854 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
855 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
856 @@ -27,40 +27,15 @@
857  #include "common.h"
858  #include "mci.h"
859  #include "dfs.h"
860 -
861 -/*
862 - * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
863 - * should rely on this file or its contents.
864 - */
865 +#include "spectral.h"
866  
867  struct ath_node;
868 +struct ath_rate_table;
869  
870 -/* Macro to expand scalars to 64-bit objects */
871 -
872 -#define        ito64(x) (sizeof(x) == 1) ?                     \
873 -       (((unsigned long long int)(x)) & (0xff)) :      \
874 -       (sizeof(x) == 2) ?                              \
875 -       (((unsigned long long int)(x)) & 0xffff) :      \
876 -       ((sizeof(x) == 4) ?                             \
877 -        (((unsigned long long int)(x)) & 0xffffffff) : \
878 -        (unsigned long long int)(x))
879 -
880 -/* increment with wrap-around */
881 -#define INCR(_l, _sz)   do {                   \
882 -               (_l)++;                         \
883 -               (_l) &= ((_sz) - 1);            \
884 -       } while (0)
885 -
886 -/* decrement with wrap-around */
887 -#define DECR(_l,  _sz)  do {                   \
888 -               (_l)--;                         \
889 -               (_l) &= ((_sz) - 1);            \
890 -       } while (0)
891 -
892 -#define TSF_TO_TU(_h,_l) \
893 -       ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
894 -
895 -#define        ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
896 +extern struct ieee80211_ops ath9k_ops;
897 +extern int ath9k_modparam_nohwcrypt;
898 +extern int led_blink;
899 +extern bool is_ath9k_unloaded;
900  
901  struct ath_config {
902         u16 txpowlimit;
903 @@ -70,6 +45,17 @@ struct ath_config {
904  /* Descriptor Management */
905  /*************************/
906  
907 +#define ATH_TXSTATUS_RING_SIZE 512
908 +
909 +/* Macro to expand scalars to 64-bit objects */
910 +#define        ito64(x) (sizeof(x) == 1) ?                     \
911 +       (((unsigned long long int)(x)) & (0xff)) :      \
912 +       (sizeof(x) == 2) ?                              \
913 +       (((unsigned long long int)(x)) & 0xffff) :      \
914 +       ((sizeof(x) == 4) ?                             \
915 +        (((unsigned long long int)(x)) & 0xffffffff) : \
916 +        (unsigned long long int)(x))
917 +
918  #define ATH_TXBUF_RESET(_bf) do {                              \
919                 (_bf)->bf_lastbf = NULL;                        \
920                 (_bf)->bf_next = NULL;                          \
921 @@ -77,23 +63,6 @@ struct ath_config {
922                        sizeof(struct ath_buf_state));           \
923         } while (0)
924  
925 -/**
926 - * enum buffer_type - Buffer type flags
927 - *
928 - * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
929 - * @BUF_AGGR: Indicates whether the buffer can be aggregated
930 - *     (used in aggregation scheduling)
931 - */
932 -enum buffer_type {
933 -       BUF_AMPDU               = BIT(0),
934 -       BUF_AGGR                = BIT(1),
935 -};
936 -
937 -#define bf_isampdu(bf)         (bf->bf_state.bf_type & BUF_AMPDU)
938 -#define bf_isaggr(bf)          (bf->bf_state.bf_type & BUF_AGGR)
939 -
940 -#define ATH_TXSTATUS_RING_SIZE 512
941 -
942  #define        DS2PHYS(_dd, _ds)                                               \
943         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
944  #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
945 @@ -113,11 +82,20 @@ int ath_descdma_setup(struct ath_softc *
946  /* RX / TX */
947  /***********/
948  
949 +#define        ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
950 +
951 +/* increment with wrap-around */
952 +#define INCR(_l, _sz)   do {                   \
953 +               (_l)++;                         \
954 +               (_l) &= ((_sz) - 1);            \
955 +       } while (0)
956 +
957  #define ATH_RXBUF               512
958  #define ATH_TXBUF               512
959  #define ATH_TXBUF_RESERVE       5
960  #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
961  #define ATH_TXMAXTRY            13
962 +#define ATH_MAX_SW_RETRIES      30
963  
964  #define TID_TO_WME_AC(_tid)                            \
965         ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE :   \
966 @@ -133,6 +111,9 @@ int ath_descdma_setup(struct ath_softc *
967  #define ATH_AGGR_MIN_QDEPTH        2
968  /* minimum h/w qdepth for non-aggregated traffic */
969  #define ATH_NON_AGGR_MIN_QDEPTH    8
970 +#define ATH_TX_COMPLETE_POLL_INT   1000
971 +#define ATH_TXFIFO_DEPTH           8
972 +#define ATH_TX_ERROR               0x01
973  
974  #define IEEE80211_SEQ_SEQ_SHIFT    4
975  #define IEEE80211_SEQ_MAX          4096
976 @@ -167,9 +148,6 @@ int ath_descdma_setup(struct ath_softc *
977  
978  #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
979  
980 -#define ATH_TX_COMPLETE_POLL_INT       1000
981 -
982 -#define ATH_TXFIFO_DEPTH 8
983  struct ath_txq {
984         int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
985         u32 axq_qnum; /* ath9k hardware queue number */
986 @@ -214,6 +192,21 @@ struct ath_rxbuf {
987         dma_addr_t bf_buf_addr;
988  };
989  
990 +/**
991 + * enum buffer_type - Buffer type flags
992 + *
993 + * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
994 + * @BUF_AGGR: Indicates whether the buffer can be aggregated
995 + *     (used in aggregation scheduling)
996 + */
997 +enum buffer_type {
998 +       BUF_AMPDU               = BIT(0),
999 +       BUF_AGGR                = BIT(1),
1000 +};
1001 +
1002 +#define bf_isampdu(bf)         (bf->bf_state.bf_type & BUF_AMPDU)
1003 +#define bf_isaggr(bf)          (bf->bf_state.bf_type & BUF_AGGR)
1004 +
1005  struct ath_buf_state {
1006         u8 bf_type;
1007         u8 bfs_paprd;
1008 @@ -278,7 +271,6 @@ struct ath_tx_control {
1009         struct ieee80211_sta *sta;
1010  };
1011  
1012 -#define ATH_TX_ERROR        0x01
1013  
1014  /**
1015   * @txq_map:  Index is mac80211 queue number.  This is
1016 @@ -372,6 +364,22 @@ struct ath_vif {
1017         struct ath_buf *av_bcbuf;
1018  };
1019  
1020 +struct ath9k_vif_iter_data {
1021 +       u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
1022 +       u8 mask[ETH_ALEN]; /* bssid mask */
1023 +       bool has_hw_macaddr;
1024 +
1025 +       int naps;      /* number of AP vifs */
1026 +       int nmeshes;   /* number of mesh vifs */
1027 +       int nstations; /* number of station vifs */
1028 +       int nwds;      /* number of WDS vifs */
1029 +       int nadhocs;   /* number of adhoc vifs */
1030 +};
1031 +
1032 +void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1033 +                              struct ieee80211_vif *vif,
1034 +                              struct ath9k_vif_iter_data *iter_data);
1035 +
1036  /*******************/
1037  /* Beacon Handling */
1038  /*******************/
1039 @@ -387,6 +395,9 @@ struct ath_vif {
1040  #define ATH_DEFAULT_BMISS_LIMIT        10
1041  #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
1042  
1043 +#define TSF_TO_TU(_h,_l) \
1044 +       ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
1045 +
1046  struct ath_beacon_config {
1047         int beacon_interval;
1048         u16 listen_interval;
1049 @@ -420,12 +431,10 @@ struct ath_beacon {
1050  };
1051  
1052  void ath9k_beacon_tasklet(unsigned long data);
1053 -bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
1054  void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
1055                          u32 changed);
1056  void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
1057  void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
1058 -void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
1059  void ath9k_set_beacon(struct ath_softc *sc);
1060  bool ath9k_csa_is_finished(struct ath_softc *sc);
1061  
1062 @@ -440,10 +449,9 @@ bool ath9k_csa_is_finished(struct ath_so
1063  #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
1064  #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
1065  #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
1066 -#define ATH_ANI_MAX_SKIP_COUNT  10
1067 -
1068 -#define ATH_PAPRD_TIMEOUT      100 /* msecs */
1069 -#define ATH_PLL_WORK_INTERVAL   100
1070 +#define ATH_ANI_MAX_SKIP_COUNT    10
1071 +#define ATH_PAPRD_TIMEOUT         100 /* msecs */
1072 +#define ATH_PLL_WORK_INTERVAL     100
1073  
1074  void ath_tx_complete_poll_work(struct work_struct *work);
1075  void ath_reset_work(struct work_struct *work);
1076 @@ -459,6 +467,7 @@ void ath_check_ani(struct ath_softc *sc)
1077  int ath_update_survey_stats(struct ath_softc *sc);
1078  void ath_update_survey_nf(struct ath_softc *sc, int channel);
1079  void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
1080 +void ath_ps_full_sleep(unsigned long data);
1081  
1082  /**********/
1083  /* BTCOEX */
1084 @@ -476,20 +485,19 @@ enum bt_op_flags {
1085  };
1086  
1087  struct ath_btcoex {
1088 -       bool hw_timer_enabled;
1089         spinlock_t btcoex_lock;
1090         struct timer_list period_timer; /* Timer for BT period */
1091 +       struct timer_list no_stomp_timer;
1092         u32 bt_priority_cnt;
1093         unsigned long bt_priority_time;
1094         unsigned long op_flags;
1095         int bt_stomp_type; /* Types of BT stomping */
1096 -       u32 btcoex_no_stomp; /* in usec */
1097 +       u32 btcoex_no_stomp; /* in msec */
1098         u32 btcoex_period; /* in msec */
1099 -       u32 btscan_no_stomp; /* in usec */
1100 +       u32 btscan_no_stomp; /* in msec */
1101         u32 duty_cycle;
1102         u32 bt_wait_time;
1103         int rssi_count;
1104 -       struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
1105         struct ath_mci_profile mci;
1106         u8 stomp_audio;
1107  };
1108 @@ -537,12 +545,6 @@ static inline int ath9k_dump_btcoex(stru
1109  }
1110  #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */
1111  
1112 -struct ath9k_wow_pattern {
1113 -       u8 pattern_bytes[MAX_PATTERN_SIZE];
1114 -       u8 mask_bytes[MAX_PATTERN_SIZE];
1115 -       u32 pattern_len;
1116 -};
1117 -
1118  /********************/
1119  /*   LED Control    */
1120  /********************/
1121 @@ -570,6 +572,40 @@ static inline void ath_fill_led_pin(stru
1122  }
1123  #endif
1124  
1125 +/************************/
1126 +/* Wake on Wireless LAN */
1127 +/************************/
1128 +
1129 +struct ath9k_wow_pattern {
1130 +       u8 pattern_bytes[MAX_PATTERN_SIZE];
1131 +       u8 mask_bytes[MAX_PATTERN_SIZE];
1132 +       u32 pattern_len;
1133 +};
1134 +
1135 +#ifdef CPTCFG_ATH9K_WOW
1136 +void ath9k_init_wow(struct ieee80211_hw *hw);
1137 +int ath9k_suspend(struct ieee80211_hw *hw,
1138 +                 struct cfg80211_wowlan *wowlan);
1139 +int ath9k_resume(struct ieee80211_hw *hw);
1140 +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
1141 +#else
1142 +static inline void ath9k_init_wow(struct ieee80211_hw *hw)
1143 +{
1144 +}
1145 +static inline int ath9k_suspend(struct ieee80211_hw *hw,
1146 +                               struct cfg80211_wowlan *wowlan)
1147 +{
1148 +       return 0;
1149 +}
1150 +static inline int ath9k_resume(struct ieee80211_hw *hw)
1151 +{
1152 +       return 0;
1153 +}
1154 +static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
1155 +{
1156 +}
1157 +#endif /* CONFIG_ATH9K_WOW */
1158 +
1159  /*******************************/
1160  /* Antenna diversity/combining */
1161  /*******************************/
1162 @@ -632,28 +668,24 @@ void ath_ant_comb_scan(struct ath_softc 
1163  /* Main driver core */
1164  /********************/
1165  
1166 -#define ATH9K_PCI_CUS198      0x0001
1167 -#define ATH9K_PCI_CUS230      0x0002
1168 -#define ATH9K_PCI_CUS217      0x0004
1169 -#define ATH9K_PCI_CUS252      0x0008
1170 -#define ATH9K_PCI_WOW         0x0010
1171 -#define ATH9K_PCI_BT_ANT_DIV  0x0020
1172 -#define ATH9K_PCI_D3_L1_WAR   0x0040
1173 -#define ATH9K_PCI_AR9565_1ANT 0x0080
1174 -#define ATH9K_PCI_AR9565_2ANT 0x0100
1175 +#define ATH9K_PCI_CUS198          0x0001
1176 +#define ATH9K_PCI_CUS230          0x0002
1177 +#define ATH9K_PCI_CUS217          0x0004
1178 +#define ATH9K_PCI_CUS252          0x0008
1179 +#define ATH9K_PCI_WOW             0x0010
1180 +#define ATH9K_PCI_BT_ANT_DIV      0x0020
1181 +#define ATH9K_PCI_D3_L1_WAR       0x0040
1182 +#define ATH9K_PCI_AR9565_1ANT     0x0080
1183 +#define ATH9K_PCI_AR9565_2ANT     0x0100
1184 +#define ATH9K_PCI_NO_PLL_PWRSAVE  0x0200
1185  
1186  /*
1187   * Default cache line size, in bytes.
1188   * Used when PCI device not fully initialized by bootrom/BIOS
1189  */
1190  #define DEFAULT_CACHELINE       32
1191 -#define ATH_REGCLASSIDS_MAX     10
1192  #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
1193 -#define ATH_MAX_SW_RETRIES      30
1194 -#define ATH_CHAN_MAX            255
1195 -
1196  #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
1197 -#define ATH_RATE_DUMMY_MARKER   0
1198  
1199  enum sc_op_flags {
1200         SC_OP_INVALID,
1201 @@ -672,37 +704,6 @@ enum sc_op_flags {
1202  #define PS_BEACON_SYNC            BIT(4)
1203  #define PS_WAIT_FOR_ANI           BIT(5)
1204  
1205 -struct ath_rate_table;
1206 -
1207 -struct ath9k_vif_iter_data {
1208 -       u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
1209 -       u8 mask[ETH_ALEN]; /* bssid mask */
1210 -       bool has_hw_macaddr;
1211 -
1212 -       int naps;      /* number of AP vifs */
1213 -       int nmeshes;   /* number of mesh vifs */
1214 -       int nstations; /* number of station vifs */
1215 -       int nwds;      /* number of WDS vifs */
1216 -       int nadhocs;   /* number of adhoc vifs */
1217 -};
1218 -
1219 -/* enum spectral_mode:
1220 - *
1221 - * @SPECTRAL_DISABLED: spectral mode is disabled
1222 - * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with
1223 - *     something else.
1224 - * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples
1225 - *     is performed manually.
1226 - * @SPECTRAL_CHANSCAN: Like manual, but also triggered when changing channels
1227 - *     during a channel scan.
1228 - */
1229 -enum spectral_mode {
1230 -       SPECTRAL_DISABLED = 0,
1231 -       SPECTRAL_BACKGROUND,
1232 -       SPECTRAL_MANUAL,
1233 -       SPECTRAL_CHANSCAN,
1234 -};
1235 -
1236  struct ath_softc {
1237         struct ieee80211_hw *hw;
1238         struct device *dev;
1239 @@ -723,6 +724,7 @@ struct ath_softc {
1240         struct work_struct hw_check_work;
1241         struct work_struct hw_reset_work;
1242         struct completion paprd_complete;
1243 +       wait_queue_head_t tx_wait;
1244  
1245         unsigned int hw_busy_count;
1246         unsigned long sc_flags;
1247 @@ -759,6 +761,7 @@ struct ath_softc {
1248         struct delayed_work tx_complete_work;
1249         struct delayed_work hw_pll_work;
1250         struct timer_list rx_poll_timer;
1251 +       struct timer_list sleep_timer;
1252  
1253  #ifdef CPTCFG_ATH9K_BTCOEX_SUPPORT
1254         struct ath_btcoex btcoex;
1255 @@ -783,199 +786,54 @@ struct ath_softc {
1256         bool tx99_state;
1257         s16 tx99_power;
1258  
1259 -#ifdef CONFIG_PM_SLEEP
1260 +#ifdef CONFIG_ATH9K_WOW
1261         atomic_t wow_got_bmiss_intr;
1262         atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
1263         u32 wow_intr_before_sleep;
1264  #endif
1265  };
1266  
1267 -#define SPECTRAL_SCAN_BITMASK          0x10
1268 -/* Radar info packet format, used for DFS and spectral formats. */
1269 -struct ath_radar_info {
1270 -       u8 pulse_length_pri;
1271 -       u8 pulse_length_ext;
1272 -       u8 pulse_bw_info;
1273 -} __packed;
1274 -
1275 -/* The HT20 spectral data has 4 bytes of additional information at it's end.
1276 - *
1277 - * [7:0]: all bins {max_magnitude[1:0], bitmap_weight[5:0]}
1278 - * [7:0]: all bins  max_magnitude[9:2]
1279 - * [7:0]: all bins {max_index[5:0], max_magnitude[11:10]}
1280 - * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
1281 - */
1282 -struct ath_ht20_mag_info {
1283 -       u8 all_bins[3];
1284 -       u8 max_exp;
1285 -} __packed;
1286 -
1287 -#define SPECTRAL_HT20_NUM_BINS         56
1288 -
1289 -/* WARNING: don't actually use this struct! MAC may vary the amount of
1290 - * data by -1/+2. This struct is for reference only.
1291 - */
1292 -struct ath_ht20_fft_packet {
1293 -       u8 data[SPECTRAL_HT20_NUM_BINS];
1294 -       struct ath_ht20_mag_info mag_info;
1295 -       struct ath_radar_info radar_info;
1296 -} __packed;
1297 -
1298 -#define SPECTRAL_HT20_TOTAL_DATA_LEN   (sizeof(struct ath_ht20_fft_packet))
1299 -
1300 -/* Dynamic 20/40 mode:
1301 - *
1302 - * [7:0]: lower bins {max_magnitude[1:0], bitmap_weight[5:0]}
1303 - * [7:0]: lower bins  max_magnitude[9:2]
1304 - * [7:0]: lower bins {max_index[5:0], max_magnitude[11:10]}
1305 - * [7:0]: upper bins {max_magnitude[1:0], bitmap_weight[5:0]}
1306 - * [7:0]: upper bins  max_magnitude[9:2]
1307 - * [7:0]: upper bins {max_index[5:0], max_magnitude[11:10]}
1308 - * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
1309 - */
1310 -struct ath_ht20_40_mag_info {
1311 -       u8 lower_bins[3];
1312 -       u8 upper_bins[3];
1313 -       u8 max_exp;
1314 -} __packed;
1315 -
1316 -#define SPECTRAL_HT20_40_NUM_BINS              128
1317 -
1318 -/* WARNING: don't actually use this struct! MAC may vary the amount of
1319 - * data. This struct is for reference only.
1320 - */
1321 -struct ath_ht20_40_fft_packet {
1322 -       u8 data[SPECTRAL_HT20_40_NUM_BINS];
1323 -       struct ath_ht20_40_mag_info mag_info;
1324 -       struct ath_radar_info radar_info;
1325 -} __packed;
1326 -
1327 -
1328 -#define SPECTRAL_HT20_40_TOTAL_DATA_LEN        (sizeof(struct ath_ht20_40_fft_packet))
1329 -
1330 -/* grabs the max magnitude from the all/upper/lower bins */
1331 -static inline u16 spectral_max_magnitude(u8 *bins)
1332 -{
1333 -       return (bins[0] & 0xc0) >> 6 |
1334 -              (bins[1] & 0xff) << 2 |
1335 -              (bins[2] & 0x03) << 10;
1336 -}
1337 +/********/
1338 +/* TX99 */
1339 +/********/
1340  
1341 -/* return the max magnitude from the all/upper/lower bins */
1342 -static inline u8 spectral_max_index(u8 *bins)
1343 +#ifdef CONFIG_ATH9K_TX99
1344 +void ath9k_tx99_init_debug(struct ath_softc *sc);
1345 +int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
1346 +                   struct ath_tx_control *txctl);
1347 +#else
1348 +static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
1349  {
1350 -       s8 m = (bins[2] & 0xfc) >> 2;
1351 -
1352 -       /* TODO: this still doesn't always report the right values ... */
1353 -       if (m > 32)
1354 -               m |= 0xe0;
1355 -       else
1356 -               m &= ~0xe0;
1357 -
1358 -       return m + 29;
1359  }
1360 -
1361 -/* return the bitmap weight from the all/upper/lower bins */
1362 -static inline u8 spectral_bitmap_weight(u8 *bins)
1363 +static inline int ath9k_tx99_send(struct ath_softc *sc,
1364 +                                 struct sk_buff *skb,
1365 +                                 struct ath_tx_control *txctl)
1366  {
1367 -       return bins[0] & 0x3f;
1368 +       return 0;
1369  }
1370 -
1371 -/* FFT sample format given to userspace via debugfs.
1372 - *
1373 - * Please keep the type/length at the front position and change
1374 - * other fields after adding another sample type
1375 - *
1376 - * TODO: this might need rework when switching to nl80211-based
1377 - * interface.
1378 - */
1379 -enum ath_fft_sample_type {
1380 -       ATH_FFT_SAMPLE_HT20 = 1,
1381 -       ATH_FFT_SAMPLE_HT20_40,
1382 -};
1383 -
1384 -struct fft_sample_tlv {
1385 -       u8 type;        /* see ath_fft_sample */
1386 -       __be16 length;
1387 -       /* type dependent data follows */
1388 -} __packed;
1389 -
1390 -struct fft_sample_ht20 {
1391 -       struct fft_sample_tlv tlv;
1392 -
1393 -       u8 max_exp;
1394 -
1395 -       __be16 freq;
1396 -       s8 rssi;
1397 -       s8 noise;
1398 -
1399 -       __be16 max_magnitude;
1400 -       u8 max_index;
1401 -       u8 bitmap_weight;
1402 -
1403 -       __be64 tsf;
1404 -
1405 -       u8 data[SPECTRAL_HT20_NUM_BINS];
1406 -} __packed;
1407 -
1408 -struct fft_sample_ht20_40 {
1409 -       struct fft_sample_tlv tlv;
1410 -
1411 -       u8 channel_type;
1412 -       __be16 freq;
1413 -
1414 -       s8 lower_rssi;
1415 -       s8 upper_rssi;
1416 -
1417 -       __be64 tsf;
1418 -
1419 -       s8 lower_noise;
1420 -       s8 upper_noise;
1421 -
1422 -       __be16 lower_max_magnitude;
1423 -       __be16 upper_max_magnitude;
1424 -
1425 -       u8 lower_max_index;
1426 -       u8 upper_max_index;
1427 -
1428 -       u8 lower_bitmap_weight;
1429 -       u8 upper_bitmap_weight;
1430 -
1431 -       u8 max_exp;
1432 -
1433 -       u8 data[SPECTRAL_HT20_40_NUM_BINS];
1434 -} __packed;
1435 -
1436 -int ath9k_tx99_init(struct ath_softc *sc);
1437 -void ath9k_tx99_deinit(struct ath_softc *sc);
1438 -int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
1439 -                   struct ath_tx_control *txctl);
1440 -
1441 -void ath9k_tasklet(unsigned long data);
1442 -int ath_cabq_update(struct ath_softc *);
1443 +#endif /* CONFIG_ATH9K_TX99 */
1444  
1445  static inline void ath_read_cachesize(struct ath_common *common, int *csz)
1446  {
1447         common->bus_ops->read_cachesize(common, csz);
1448  }
1449  
1450 -extern struct ieee80211_ops ath9k_ops;
1451 -extern int ath9k_modparam_nohwcrypt;
1452 -extern int led_blink;
1453 -extern bool is_ath9k_unloaded;
1454 -
1455 +void ath9k_tasklet(unsigned long data);
1456 +int ath_cabq_update(struct ath_softc *);
1457  u8 ath9k_parse_mpdudensity(u8 mpdudensity);
1458  irqreturn_t ath_isr(int irq, void *dev);
1459 +int ath_reset(struct ath_softc *sc);
1460 +void ath_cancel_work(struct ath_softc *sc);
1461 +void ath_restart_work(struct ath_softc *sc);
1462  int ath9k_init_device(u16 devid, struct ath_softc *sc,
1463                     const struct ath_bus_ops *bus_ops);
1464  void ath9k_deinit_device(struct ath_softc *sc);
1465 -void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
1466  void ath9k_reload_chainmask_settings(struct ath_softc *sc);
1467 -
1468 -void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw);
1469 -int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
1470 -                              enum spectral_mode spectral_mode);
1471 -
1472 +u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
1473 +void ath_start_rfkill_poll(struct ath_softc *sc);
1474 +void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
1475 +void ath9k_ps_wakeup(struct ath_softc *sc);
1476 +void ath9k_ps_restore(struct ath_softc *sc);
1477  
1478  #ifdef CPTCFG_ATH9K_PCI
1479  int ath_pci_init(void);
1480 @@ -993,15 +851,4 @@ static inline int ath_ahb_init(void) { r
1481  static inline void ath_ahb_exit(void) {};
1482  #endif
1483  
1484 -void ath9k_ps_wakeup(struct ath_softc *sc);
1485 -void ath9k_ps_restore(struct ath_softc *sc);
1486 -
1487 -u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
1488 -
1489 -void ath_start_rfkill_poll(struct ath_softc *sc);
1490 -extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
1491 -void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1492 -                              struct ieee80211_vif *vif,
1493 -                              struct ath9k_vif_iter_data *iter_data);
1494 -
1495  #endif /* ATH9K_H */
1496 --- a/drivers/net/wireless/ath/ath9k/debug.c
1497 +++ b/drivers/net/wireless/ath/ath9k/debug.c
1498 @@ -17,7 +17,6 @@
1499  #include <linux/slab.h>
1500  #include <linux/vmalloc.h>
1501  #include <linux/export.h>
1502 -#include <linux/relay.h>
1503  #include <asm/unaligned.h>
1504  
1505  #include "ath9k.h"
1506 @@ -27,6 +26,47 @@
1507  #define REG_READ_D(_ah, _reg) \
1508         ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
1509  
1510 +void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
1511 +{
1512 +       if (sync_cause)
1513 +               sc->debug.stats.istats.sync_cause_all++;
1514 +       if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
1515 +               sc->debug.stats.istats.sync_rtc_irq++;
1516 +       if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
1517 +               sc->debug.stats.istats.sync_mac_irq++;
1518 +       if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
1519 +               sc->debug.stats.istats.eeprom_illegal_access++;
1520 +       if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
1521 +               sc->debug.stats.istats.apb_timeout++;
1522 +       if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
1523 +               sc->debug.stats.istats.pci_mode_conflict++;
1524 +       if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
1525 +               sc->debug.stats.istats.host1_fatal++;
1526 +       if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
1527 +               sc->debug.stats.istats.host1_perr++;
1528 +       if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
1529 +               sc->debug.stats.istats.trcv_fifo_perr++;
1530 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
1531 +               sc->debug.stats.istats.radm_cpl_ep++;
1532 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
1533 +               sc->debug.stats.istats.radm_cpl_dllp_abort++;
1534 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
1535 +               sc->debug.stats.istats.radm_cpl_tlp_abort++;
1536 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
1537 +               sc->debug.stats.istats.radm_cpl_ecrc_err++;
1538 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
1539 +               sc->debug.stats.istats.radm_cpl_timeout++;
1540 +       if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
1541 +               sc->debug.stats.istats.local_timeout++;
1542 +       if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
1543 +               sc->debug.stats.istats.pm_access++;
1544 +       if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
1545 +               sc->debug.stats.istats.mac_awake++;
1546 +       if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
1547 +               sc->debug.stats.istats.mac_asleep++;
1548 +       if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
1549 +               sc->debug.stats.istats.mac_sleep_access++;
1550 +}
1551  
1552  static ssize_t ath9k_debugfs_read_buf(struct file *file, char __user *user_buf,
1553                                       size_t count, loff_t *ppos)
1554 @@ -1016,297 +1056,6 @@ static const struct file_operations fops
1555         .llseek = default_llseek,
1556  };
1557  
1558 -static ssize_t read_file_spec_scan_ctl(struct file *file, char __user *user_buf,
1559 -                                      size_t count, loff_t *ppos)
1560 -{
1561 -       struct ath_softc *sc = file->private_data;
1562 -       char *mode = "";
1563 -       unsigned int len;
1564 -
1565 -       switch (sc->spectral_mode) {
1566 -       case SPECTRAL_DISABLED:
1567 -               mode = "disable";
1568 -               break;
1569 -       case SPECTRAL_BACKGROUND:
1570 -               mode = "background";
1571 -               break;
1572 -       case SPECTRAL_CHANSCAN:
1573 -               mode = "chanscan";
1574 -               break;
1575 -       case SPECTRAL_MANUAL:
1576 -               mode = "manual";
1577 -               break;
1578 -       }
1579 -       len = strlen(mode);
1580 -       return simple_read_from_buffer(user_buf, count, ppos, mode, len);
1581 -}
1582 -
1583 -static ssize_t write_file_spec_scan_ctl(struct file *file,
1584 -                                       const char __user *user_buf,
1585 -                                       size_t count, loff_t *ppos)
1586 -{
1587 -       struct ath_softc *sc = file->private_data;
1588 -       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1589 -       char buf[32];
1590 -       ssize_t len;
1591 -
1592 -       if (config_enabled(CPTCFG_ATH9K_TX99))
1593 -               return -EOPNOTSUPP;
1594 -
1595 -       len = min(count, sizeof(buf) - 1);
1596 -       if (copy_from_user(buf, user_buf, len))
1597 -               return -EFAULT;
1598 -
1599 -       buf[len] = '\0';
1600 -
1601 -       if (strncmp("trigger", buf, 7) == 0) {
1602 -               ath9k_spectral_scan_trigger(sc->hw);
1603 -       } else if (strncmp("background", buf, 9) == 0) {
1604 -               ath9k_spectral_scan_config(sc->hw, SPECTRAL_BACKGROUND);
1605 -               ath_dbg(common, CONFIG, "spectral scan: background mode enabled\n");
1606 -       } else if (strncmp("chanscan", buf, 8) == 0) {
1607 -               ath9k_spectral_scan_config(sc->hw, SPECTRAL_CHANSCAN);
1608 -               ath_dbg(common, CONFIG, "spectral scan: channel scan mode enabled\n");
1609 -       } else if (strncmp("manual", buf, 6) == 0) {
1610 -               ath9k_spectral_scan_config(sc->hw, SPECTRAL_MANUAL);
1611 -               ath_dbg(common, CONFIG, "spectral scan: manual mode enabled\n");
1612 -       } else if (strncmp("disable", buf, 7) == 0) {
1613 -               ath9k_spectral_scan_config(sc->hw, SPECTRAL_DISABLED);
1614 -               ath_dbg(common, CONFIG, "spectral scan: disabled\n");
1615 -       } else {
1616 -               return -EINVAL;
1617 -       }
1618 -
1619 -       return count;
1620 -}
1621 -
1622 -static const struct file_operations fops_spec_scan_ctl = {
1623 -       .read = read_file_spec_scan_ctl,
1624 -       .write = write_file_spec_scan_ctl,
1625 -       .open = simple_open,
1626 -       .owner = THIS_MODULE,
1627 -       .llseek = default_llseek,
1628 -};
1629 -
1630 -static ssize_t read_file_spectral_short_repeat(struct file *file,
1631 -                                              char __user *user_buf,
1632 -                                              size_t count, loff_t *ppos)
1633 -{
1634 -       struct ath_softc *sc = file->private_data;
1635 -       char buf[32];
1636 -       unsigned int len;
1637 -
1638 -       len = sprintf(buf, "%d\n", sc->spec_config.short_repeat);
1639 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1640 -}
1641 -
1642 -static ssize_t write_file_spectral_short_repeat(struct file *file,
1643 -                                               const char __user *user_buf,
1644 -                                               size_t count, loff_t *ppos)
1645 -{
1646 -       struct ath_softc *sc = file->private_data;
1647 -       unsigned long val;
1648 -       char buf[32];
1649 -       ssize_t len;
1650 -
1651 -       len = min(count, sizeof(buf) - 1);
1652 -       if (copy_from_user(buf, user_buf, len))
1653 -               return -EFAULT;
1654 -
1655 -       buf[len] = '\0';
1656 -       if (kstrtoul(buf, 0, &val))
1657 -               return -EINVAL;
1658 -
1659 -       if (val < 0 || val > 1)
1660 -               return -EINVAL;
1661 -
1662 -       sc->spec_config.short_repeat = val;
1663 -       return count;
1664 -}
1665 -
1666 -static const struct file_operations fops_spectral_short_repeat = {
1667 -       .read = read_file_spectral_short_repeat,
1668 -       .write = write_file_spectral_short_repeat,
1669 -       .open = simple_open,
1670 -       .owner = THIS_MODULE,
1671 -       .llseek = default_llseek,
1672 -};
1673 -
1674 -static ssize_t read_file_spectral_count(struct file *file,
1675 -                                       char __user *user_buf,
1676 -                                       size_t count, loff_t *ppos)
1677 -{
1678 -       struct ath_softc *sc = file->private_data;
1679 -       char buf[32];
1680 -       unsigned int len;
1681 -
1682 -       len = sprintf(buf, "%d\n", sc->spec_config.count);
1683 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1684 -}
1685 -
1686 -static ssize_t write_file_spectral_count(struct file *file,
1687 -                                        const char __user *user_buf,
1688 -                                        size_t count, loff_t *ppos)
1689 -{
1690 -       struct ath_softc *sc = file->private_data;
1691 -       unsigned long val;
1692 -       char buf[32];
1693 -       ssize_t len;
1694 -
1695 -       len = min(count, sizeof(buf) - 1);
1696 -       if (copy_from_user(buf, user_buf, len))
1697 -               return -EFAULT;
1698 -
1699 -       buf[len] = '\0';
1700 -       if (kstrtoul(buf, 0, &val))
1701 -               return -EINVAL;
1702 -
1703 -       if (val < 0 || val > 255)
1704 -               return -EINVAL;
1705 -
1706 -       sc->spec_config.count = val;
1707 -       return count;
1708 -}
1709 -
1710 -static const struct file_operations fops_spectral_count = {
1711 -       .read = read_file_spectral_count,
1712 -       .write = write_file_spectral_count,
1713 -       .open = simple_open,
1714 -       .owner = THIS_MODULE,
1715 -       .llseek = default_llseek,
1716 -};
1717 -
1718 -static ssize_t read_file_spectral_period(struct file *file,
1719 -                                        char __user *user_buf,
1720 -                                        size_t count, loff_t *ppos)
1721 -{
1722 -       struct ath_softc *sc = file->private_data;
1723 -       char buf[32];
1724 -       unsigned int len;
1725 -
1726 -       len = sprintf(buf, "%d\n", sc->spec_config.period);
1727 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1728 -}
1729 -
1730 -static ssize_t write_file_spectral_period(struct file *file,
1731 -                                         const char __user *user_buf,
1732 -                                         size_t count, loff_t *ppos)
1733 -{
1734 -       struct ath_softc *sc = file->private_data;
1735 -       unsigned long val;
1736 -       char buf[32];
1737 -       ssize_t len;
1738 -
1739 -       len = min(count, sizeof(buf) - 1);
1740 -       if (copy_from_user(buf, user_buf, len))
1741 -               return -EFAULT;
1742 -
1743 -       buf[len] = '\0';
1744 -       if (kstrtoul(buf, 0, &val))
1745 -               return -EINVAL;
1746 -
1747 -       if (val < 0 || val > 255)
1748 -               return -EINVAL;
1749 -
1750 -       sc->spec_config.period = val;
1751 -       return count;
1752 -}
1753 -
1754 -static const struct file_operations fops_spectral_period = {
1755 -       .read = read_file_spectral_period,
1756 -       .write = write_file_spectral_period,
1757 -       .open = simple_open,
1758 -       .owner = THIS_MODULE,
1759 -       .llseek = default_llseek,
1760 -};
1761 -
1762 -static ssize_t read_file_spectral_fft_period(struct file *file,
1763 -                                            char __user *user_buf,
1764 -                                            size_t count, loff_t *ppos)
1765 -{
1766 -       struct ath_softc *sc = file->private_data;
1767 -       char buf[32];
1768 -       unsigned int len;
1769 -
1770 -       len = sprintf(buf, "%d\n", sc->spec_config.fft_period);
1771 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1772 -}
1773 -
1774 -static ssize_t write_file_spectral_fft_period(struct file *file,
1775 -                                             const char __user *user_buf,
1776 -                                             size_t count, loff_t *ppos)
1777 -{
1778 -       struct ath_softc *sc = file->private_data;
1779 -       unsigned long val;
1780 -       char buf[32];
1781 -       ssize_t len;
1782 -
1783 -       len = min(count, sizeof(buf) - 1);
1784 -       if (copy_from_user(buf, user_buf, len))
1785 -               return -EFAULT;
1786 -
1787 -       buf[len] = '\0';
1788 -       if (kstrtoul(buf, 0, &val))
1789 -               return -EINVAL;
1790 -
1791 -       if (val < 0 || val > 15)
1792 -               return -EINVAL;
1793 -
1794 -       sc->spec_config.fft_period = val;
1795 -       return count;
1796 -}
1797 -
1798 -static const struct file_operations fops_spectral_fft_period = {
1799 -       .read = read_file_spectral_fft_period,
1800 -       .write = write_file_spectral_fft_period,
1801 -       .open = simple_open,
1802 -       .owner = THIS_MODULE,
1803 -       .llseek = default_llseek,
1804 -};
1805 -
1806 -static struct dentry *create_buf_file_handler(const char *filename,
1807 -                                             struct dentry *parent,
1808 -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0))
1809 -                                             umode_t mode,
1810 -#else
1811 -                                             int mode,
1812 -#endif
1813 -                                             struct rchan_buf *buf,
1814 -                                             int *is_global)
1815 -{
1816 -       struct dentry *buf_file;
1817 -
1818 -       buf_file = debugfs_create_file(filename, mode, parent, buf,
1819 -                                      &relay_file_operations);
1820 -       *is_global = 1;
1821 -       return buf_file;
1822 -}
1823 -
1824 -static int remove_buf_file_handler(struct dentry *dentry)
1825 -{
1826 -       debugfs_remove(dentry);
1827 -
1828 -       return 0;
1829 -}
1830 -
1831 -void ath_debug_send_fft_sample(struct ath_softc *sc,
1832 -                              struct fft_sample_tlv *fft_sample_tlv)
1833 -{
1834 -       int length;
1835 -       if (!sc->rfs_chan_spec_scan)
1836 -               return;
1837 -
1838 -       length = __be16_to_cpu(fft_sample_tlv->length) +
1839 -                sizeof(*fft_sample_tlv);
1840 -       relay_write(sc->rfs_chan_spec_scan, fft_sample_tlv, length);
1841 -}
1842 -
1843 -static struct rchan_callbacks rfs_spec_scan_cb = {
1844 -       .create_buf_file = create_buf_file_handler,
1845 -       .remove_buf_file = remove_buf_file_handler,
1846 -};
1847 -
1848 -
1849  static ssize_t read_file_regidx(struct file *file, char __user *user_buf,
1850                                  size_t count, loff_t *ppos)
1851  {
1852 @@ -1776,117 +1525,9 @@ void ath9k_get_et_stats(struct ieee80211
1853  
1854  void ath9k_deinit_debug(struct ath_softc *sc)
1855  {
1856 -       if (config_enabled(CPTCFG_ATH9K_DEBUGFS) && sc->rfs_chan_spec_scan) {
1857 -               relay_close(sc->rfs_chan_spec_scan);
1858 -               sc->rfs_chan_spec_scan = NULL;
1859 -       }
1860 +       ath9k_spectral_deinit_debug(sc);
1861  }
1862  
1863 -static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
1864 -                             size_t count, loff_t *ppos)
1865 -{
1866 -       struct ath_softc *sc = file->private_data;
1867 -       char buf[3];
1868 -       unsigned int len;
1869 -
1870 -       len = sprintf(buf, "%d\n", sc->tx99_state);
1871 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1872 -}
1873 -
1874 -static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
1875 -                              size_t count, loff_t *ppos)
1876 -{
1877 -       struct ath_softc *sc = file->private_data;
1878 -       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1879 -       char buf[32];
1880 -       bool start;
1881 -       ssize_t len;
1882 -       int r;
1883 -
1884 -       if (sc->nvifs > 1)
1885 -               return -EOPNOTSUPP;
1886 -
1887 -       len = min(count, sizeof(buf) - 1);
1888 -       if (copy_from_user(buf, user_buf, len))
1889 -               return -EFAULT;
1890 -
1891 -       if (strtobool(buf, &start))
1892 -               return -EINVAL;
1893 -
1894 -       if (start == sc->tx99_state) {
1895 -               if (!start)
1896 -                       return count;
1897 -               ath_dbg(common, XMIT, "Resetting TX99\n");
1898 -               ath9k_tx99_deinit(sc);
1899 -       }
1900 -
1901 -       if (!start) {
1902 -               ath9k_tx99_deinit(sc);
1903 -               return count;
1904 -       }
1905 -
1906 -       r = ath9k_tx99_init(sc);
1907 -       if (r)
1908 -               return r;
1909 -
1910 -       return count;
1911 -}
1912 -
1913 -static const struct file_operations fops_tx99 = {
1914 -       .read = read_file_tx99,
1915 -       .write = write_file_tx99,
1916 -       .open = simple_open,
1917 -       .owner = THIS_MODULE,
1918 -       .llseek = default_llseek,
1919 -};
1920 -
1921 -static ssize_t read_file_tx99_power(struct file *file,
1922 -                                   char __user *user_buf,
1923 -                                   size_t count, loff_t *ppos)
1924 -{
1925 -       struct ath_softc *sc = file->private_data;
1926 -       char buf[32];
1927 -       unsigned int len;
1928 -
1929 -       len = sprintf(buf, "%d (%d dBm)\n",
1930 -                     sc->tx99_power,
1931 -                     sc->tx99_power / 2);
1932 -
1933 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1934 -}
1935 -
1936 -static ssize_t write_file_tx99_power(struct file *file,
1937 -                                    const char __user *user_buf,
1938 -                                    size_t count, loff_t *ppos)
1939 -{
1940 -       struct ath_softc *sc = file->private_data;
1941 -       int r;
1942 -       u8 tx_power;
1943 -
1944 -       r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
1945 -       if (r)
1946 -               return r;
1947 -
1948 -       if (tx_power > MAX_RATE_POWER)
1949 -               return -EINVAL;
1950 -
1951 -       sc->tx99_power = tx_power;
1952 -
1953 -       ath9k_ps_wakeup(sc);
1954 -       ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
1955 -       ath9k_ps_restore(sc);
1956 -
1957 -       return count;
1958 -}
1959 -
1960 -static const struct file_operations fops_tx99_power = {
1961 -       .read = read_file_tx99_power,
1962 -       .write = write_file_tx99_power,
1963 -       .open = simple_open,
1964 -       .owner = THIS_MODULE,
1965 -       .llseek = default_llseek,
1966 -};
1967 -
1968  int ath9k_init_debug(struct ath_hw *ah)
1969  {
1970         struct ath_common *common = ath9k_hw_common(ah);
1971 @@ -1903,6 +1544,8 @@ int ath9k_init_debug(struct ath_hw *ah)
1972  #endif
1973  
1974         ath9k_dfs_init_debug(sc);
1975 +       ath9k_tx99_init_debug(sc);
1976 +       ath9k_spectral_init_debug(sc);
1977  
1978         debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
1979                             &fops_dma);
1980 @@ -1949,23 +1592,6 @@ int ath9k_init_debug(struct ath_hw *ah)
1981                             &fops_base_eeprom);
1982         debugfs_create_file("modal_eeprom", S_IRUSR, sc->debug.debugfs_phy, sc,
1983                             &fops_modal_eeprom);
1984 -       sc->rfs_chan_spec_scan = relay_open("spectral_scan",
1985 -                                           sc->debug.debugfs_phy,
1986 -                                           1024, 256, &rfs_spec_scan_cb,
1987 -                                           NULL);
1988 -       debugfs_create_file("spectral_scan_ctl", S_IRUSR | S_IWUSR,
1989 -                           sc->debug.debugfs_phy, sc,
1990 -                           &fops_spec_scan_ctl);
1991 -       debugfs_create_file("spectral_short_repeat", S_IRUSR | S_IWUSR,
1992 -                           sc->debug.debugfs_phy, sc,
1993 -                           &fops_spectral_short_repeat);
1994 -       debugfs_create_file("spectral_count", S_IRUSR | S_IWUSR,
1995 -                           sc->debug.debugfs_phy, sc, &fops_spectral_count);
1996 -       debugfs_create_file("spectral_period", S_IRUSR | S_IWUSR,
1997 -                           sc->debug.debugfs_phy, sc, &fops_spectral_period);
1998 -       debugfs_create_file("spectral_fft_period", S_IRUSR | S_IWUSR,
1999 -                           sc->debug.debugfs_phy, sc,
2000 -                           &fops_spectral_fft_period);
2001         debugfs_create_u32("gpio_mask", S_IRUSR | S_IWUSR,
2002                            sc->debug.debugfs_phy, &sc->sc_ah->gpio_mask);
2003         debugfs_create_u32("gpio_val", S_IRUSR | S_IWUSR,
2004 @@ -1978,15 +1604,6 @@ int ath9k_init_debug(struct ath_hw *ah)
2005         debugfs_create_file("btcoex", S_IRUSR, sc->debug.debugfs_phy, sc,
2006                             &fops_btcoex);
2007  #endif
2008 -       if (config_enabled(CPTCFG_ATH9K_TX99) &&
2009 -           AR_SREV_9300_20_OR_LATER(ah)) {
2010 -               debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
2011 -                                   sc->debug.debugfs_phy, sc,
2012 -                                   &fops_tx99);
2013 -               debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
2014 -                                   sc->debug.debugfs_phy, sc,
2015 -                                   &fops_tx99_power);
2016 -       }
2017  
2018         return 0;
2019  }
2020 --- a/drivers/net/wireless/ath/ath9k/hw.c
2021 +++ b/drivers/net/wireless/ath/ath9k/hw.c
2022 @@ -17,6 +17,8 @@
2023  #include <linux/io.h>
2024  #include <linux/slab.h>
2025  #include <linux/module.h>
2026 +#include <linux/time.h>
2027 +#include <linux/bitops.h>
2028  #include <asm/unaligned.h>
2029  
2030  #include "hw.h"
2031 @@ -83,48 +85,6 @@ static void ath9k_hw_ani_cache_ini_regs(
2032  
2033  #ifdef CPTCFG_ATH9K_DEBUGFS
2034  
2035 -void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
2036 -{
2037 -       struct ath_softc *sc = common->priv;
2038 -       if (sync_cause)
2039 -               sc->debug.stats.istats.sync_cause_all++;
2040 -       if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
2041 -               sc->debug.stats.istats.sync_rtc_irq++;
2042 -       if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
2043 -               sc->debug.stats.istats.sync_mac_irq++;
2044 -       if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
2045 -               sc->debug.stats.istats.eeprom_illegal_access++;
2046 -       if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
2047 -               sc->debug.stats.istats.apb_timeout++;
2048 -       if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
2049 -               sc->debug.stats.istats.pci_mode_conflict++;
2050 -       if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
2051 -               sc->debug.stats.istats.host1_fatal++;
2052 -       if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
2053 -               sc->debug.stats.istats.host1_perr++;
2054 -       if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
2055 -               sc->debug.stats.istats.trcv_fifo_perr++;
2056 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
2057 -               sc->debug.stats.istats.radm_cpl_ep++;
2058 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
2059 -               sc->debug.stats.istats.radm_cpl_dllp_abort++;
2060 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
2061 -               sc->debug.stats.istats.radm_cpl_tlp_abort++;
2062 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
2063 -               sc->debug.stats.istats.radm_cpl_ecrc_err++;
2064 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
2065 -               sc->debug.stats.istats.radm_cpl_timeout++;
2066 -       if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
2067 -               sc->debug.stats.istats.local_timeout++;
2068 -       if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
2069 -               sc->debug.stats.istats.pm_access++;
2070 -       if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
2071 -               sc->debug.stats.istats.mac_awake++;
2072 -       if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
2073 -               sc->debug.stats.istats.mac_asleep++;
2074 -       if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
2075 -               sc->debug.stats.istats.mac_sleep_access++;
2076 -}
2077  #endif
2078  
2079  
2080 @@ -438,23 +398,13 @@ static bool ath9k_hw_chip_test(struct at
2081  
2082  static void ath9k_hw_init_config(struct ath_hw *ah)
2083  {
2084 -       int i;
2085 -
2086         ah->config.dma_beacon_response_time = 1;
2087         ah->config.sw_beacon_response_time = 6;
2088 -       ah->config.additional_swba_backoff = 0;
2089         ah->config.ack_6mb = 0x0;
2090         ah->config.cwm_ignore_extcca = 0;
2091 -       ah->config.pcie_clock_req = 0;
2092         ah->config.analog_shiftreg = 1;
2093  
2094 -       for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2095 -               ah->config.spurchans[i][0] = AR_NO_SPUR;
2096 -               ah->config.spurchans[i][1] = AR_NO_SPUR;
2097 -       }
2098 -
2099         ah->config.rx_intr_mitigation = true;
2100 -       ah->config.pcieSerDesWrite = true;
2101  
2102         /*
2103          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
2104 @@ -486,7 +436,6 @@ static void ath9k_hw_init_defaults(struc
2105         ah->hw_version.magic = AR5416_MAGIC;
2106         ah->hw_version.subvendorid = 0;
2107  
2108 -       ah->atim_window = 0;
2109         ah->sta_id1_defaults =
2110                 AR_STA_ID1_CRPT_MIC_ENABLE |
2111                 AR_STA_ID1_MCAST_KSRCH;
2112 @@ -549,11 +498,11 @@ static int ath9k_hw_post_init(struct ath
2113          * EEPROM needs to be initialized before we do this.
2114          * This is required for regulatory compliance.
2115          */
2116 -       if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2117 +       if (AR_SREV_9300_20_OR_LATER(ah)) {
2118                 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2119                 if ((regdmn & 0xF0) == CTL_FCC) {
2120 -                       ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ;
2121 -                       ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ;
2122 +                       ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
2123 +                       ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
2124                 }
2125         }
2126  
2127 @@ -1282,6 +1231,42 @@ void ath9k_hw_get_delta_slope_vals(struc
2128         *coef_exponent = coef_exp - 16;
2129  }
2130  
2131 +/* AR9330 WAR:
2132 + * call external reset function to reset WMAC if:
2133 + * - doing a cold reset
2134 + * - we have pending frames in the TX queues.
2135 + */
2136 +static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
2137 +{
2138 +       int i, npend = 0;
2139 +
2140 +       for (i = 0; i < AR_NUM_QCU; i++) {
2141 +               npend = ath9k_hw_numtxpending(ah, i);
2142 +               if (npend)
2143 +                       break;
2144 +       }
2145 +
2146 +       if (ah->external_reset &&
2147 +           (npend || type == ATH9K_RESET_COLD)) {
2148 +               int reset_err = 0;
2149 +
2150 +               ath_dbg(ath9k_hw_common(ah), RESET,
2151 +                       "reset MAC via external reset\n");
2152 +
2153 +               reset_err = ah->external_reset();
2154 +               if (reset_err) {
2155 +                       ath_err(ath9k_hw_common(ah),
2156 +                               "External reset failed, err=%d\n",
2157 +                               reset_err);
2158 +                       return false;
2159 +               }
2160 +
2161 +               REG_WRITE(ah, AR_RTC_RESET, 1);
2162 +       }
2163 +
2164 +       return true;
2165 +}
2166 +
2167  static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
2168  {
2169         u32 rst_flags;
2170 @@ -1332,38 +1317,8 @@ static bool ath9k_hw_set_reset(struct at
2171         }
2172  
2173         if (AR_SREV_9330(ah)) {
2174 -               int npend = 0;
2175 -               int i;
2176 -
2177 -               /* AR9330 WAR:
2178 -                * call external reset function to reset WMAC if:
2179 -                * - doing a cold reset
2180 -                * - we have pending frames in the TX queues
2181 -                */
2182 -
2183 -               for (i = 0; i < AR_NUM_QCU; i++) {
2184 -                       npend = ath9k_hw_numtxpending(ah, i);
2185 -                       if (npend)
2186 -                               break;
2187 -               }
2188 -
2189 -               if (ah->external_reset &&
2190 -                   (npend || type == ATH9K_RESET_COLD)) {
2191 -                       int reset_err = 0;
2192 -
2193 -                       ath_dbg(ath9k_hw_common(ah), RESET,
2194 -                               "reset MAC via external reset\n");
2195 -
2196 -                       reset_err = ah->external_reset();
2197 -                       if (reset_err) {
2198 -                               ath_err(ath9k_hw_common(ah),
2199 -                                       "External reset failed, err=%d\n",
2200 -                                       reset_err);
2201 -                               return false;
2202 -                       }
2203 -
2204 -                       REG_WRITE(ah, AR_RTC_RESET, 1);
2205 -               }
2206 +               if (!ath9k_hw_ar9330_reset_war(ah, type))
2207 +                       return false;
2208         }
2209  
2210         if (ath9k_hw_mci_is_enabled(ah))
2211 @@ -1373,7 +1328,12 @@ static bool ath9k_hw_set_reset(struct at
2212  
2213         REGWRITE_BUFFER_FLUSH(ah);
2214  
2215 -       udelay(50);
2216 +       if (AR_SREV_9300_20_OR_LATER(ah))
2217 +               udelay(50);
2218 +       else if (AR_SREV_9100(ah))
2219 +               udelay(10000);
2220 +       else
2221 +               udelay(100);
2222  
2223         REG_WRITE(ah, AR_RTC_RC, 0);
2224         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
2225 @@ -1409,8 +1369,7 @@ static bool ath9k_hw_set_reset_power_on(
2226  
2227         REGWRITE_BUFFER_FLUSH(ah);
2228  
2229 -       if (!AR_SREV_9300_20_OR_LATER(ah))
2230 -               udelay(2);
2231 +       udelay(2);
2232  
2233         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2234                 REG_WRITE(ah, AR_RC, 0);
2235 @@ -1502,8 +1461,9 @@ static bool ath9k_hw_channel_change(stru
2236         int r;
2237  
2238         if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
2239 -               band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
2240 -               mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
2241 +               u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
2242 +               band_switch = !!(flags_diff & CHANNEL_5GHZ);
2243 +               mode_diff = !!(flags_diff & ~CHANNEL_HT);
2244         }
2245  
2246         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
2247 @@ -1815,7 +1775,7 @@ static int ath9k_hw_do_fastcc(struct ath
2248          * If cross-band fcc is not supoprted, bail out if channelFlags differ.
2249          */
2250         if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
2251 -           chan->channelFlags != ah->curchan->channelFlags)
2252 +           ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
2253                 goto fail;
2254  
2255         if (!ath9k_hw_check_alive(ah))
2256 @@ -1856,10 +1816,12 @@ int ath9k_hw_reset(struct ath_hw *ah, st
2257                    struct ath9k_hw_cal_data *caldata, bool fastcc)
2258  {
2259         struct ath_common *common = ath9k_hw_common(ah);
2260 +       struct timespec ts;
2261         u32 saveLedState;
2262         u32 saveDefAntenna;
2263         u32 macStaId1;
2264         u64 tsf = 0;
2265 +       s64 usec = 0;
2266         int r;
2267         bool start_mci_reset = false;
2268         bool save_fullsleep = ah->chip_fullsleep;
2269 @@ -1902,10 +1864,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
2270  
2271         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2272  
2273 -       /* For chips on which RTC reset is done, save TSF before it gets cleared */
2274 -       if (AR_SREV_9100(ah) ||
2275 -           (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
2276 -               tsf = ath9k_hw_gettsf64(ah);
2277 +       /* Save TSF before chip reset, a cold reset clears it */
2278 +       tsf = ath9k_hw_gettsf64(ah);
2279 +       getrawmonotonic(&ts);
2280 +       usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000;
2281  
2282         saveLedState = REG_READ(ah, AR_CFG_LED) &
2283                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2284 @@ -1938,8 +1900,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
2285         }
2286  
2287         /* Restore TSF */
2288 -       if (tsf)
2289 -               ath9k_hw_settsf64(ah, tsf);
2290 +       getrawmonotonic(&ts);
2291 +       usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec;
2292 +       ath9k_hw_settsf64(ah, tsf + usec);
2293  
2294         if (AR_SREV_9280_20_OR_LATER(ah))
2295                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2296 @@ -2261,9 +2224,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
2297         case NL80211_IFTYPE_ADHOC:
2298                 REG_SET_BIT(ah, AR_TXCFG,
2299                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2300 -               REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2301 -                         TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2302 -               flags |= AR_NDP_TIMER_EN;
2303         case NL80211_IFTYPE_MESH_POINT:
2304         case NL80211_IFTYPE_AP:
2305                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2306 @@ -2284,7 +2244,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
2307         REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2308         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2309         REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2310 -       REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2311  
2312         REGWRITE_BUFFER_FLUSH(ah);
2313  
2314 @@ -2301,12 +2260,9 @@ void ath9k_hw_set_sta_beacon_timers(stru
2315  
2316         ENABLE_REGWRITE_BUFFER(ah);
2317  
2318 -       REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2319 -
2320 -       REG_WRITE(ah, AR_BEACON_PERIOD,
2321 -                 TU_TO_USEC(bs->bs_intval));
2322 -       REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2323 -                 TU_TO_USEC(bs->bs_intval));
2324 +       REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2325 +       REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2326 +       REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2327  
2328         REGWRITE_BUFFER_FLUSH(ah);
2329  
2330 @@ -2334,9 +2290,8 @@ void ath9k_hw_set_sta_beacon_timers(stru
2331  
2332         ENABLE_REGWRITE_BUFFER(ah);
2333  
2334 -       REG_WRITE(ah, AR_NEXT_DTIM,
2335 -                 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2336 -       REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2337 +       REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2338 +       REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2339  
2340         REG_WRITE(ah, AR_SLEEP1,
2341                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2342 @@ -2350,8 +2305,8 @@ void ath9k_hw_set_sta_beacon_timers(stru
2343         REG_WRITE(ah, AR_SLEEP2,
2344                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2345  
2346 -       REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2347 -       REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2348 +       REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2349 +       REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2350  
2351         REGWRITE_BUFFER_FLUSH(ah);
2352  
2353 @@ -2987,20 +2942,6 @@ static const struct ath_gen_timer_config
2354  
2355  /* HW generic timer primitives */
2356  
2357 -/* compute and clear index of rightmost 1 */
2358 -static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2359 -{
2360 -       u32 b;
2361 -
2362 -       b = *mask;
2363 -       b &= (0-b);
2364 -       *mask &= ~b;
2365 -       b *= debruijn32;
2366 -       b >>= 27;
2367 -
2368 -       return timer_table->gen_timer_index[b];
2369 -}
2370 -
2371  u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2372  {
2373         return REG_READ(ah, AR_TSF_L32);
2374 @@ -3016,6 +2957,10 @@ struct ath_gen_timer *ath_gen_timer_allo
2375         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2376         struct ath_gen_timer *timer;
2377  
2378 +       if ((timer_index < AR_FIRST_NDP_TIMER) ||
2379 +               (timer_index >= ATH_MAX_GEN_TIMER))
2380 +               return NULL;
2381 +
2382         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2383         if (timer == NULL)
2384                 return NULL;
2385 @@ -3033,23 +2978,13 @@ EXPORT_SYMBOL(ath_gen_timer_alloc);
2386  
2387  void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2388                               struct ath_gen_timer *timer,
2389 -                             u32 trig_timeout,
2390 +                             u32 timer_next,
2391                               u32 timer_period)
2392  {
2393         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2394 -       u32 tsf, timer_next;
2395 -
2396 -       BUG_ON(!timer_period);
2397 -
2398 -       set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2399 +       u32 mask = 0;
2400  
2401 -       tsf = ath9k_hw_gettsf32(ah);
2402 -
2403 -       timer_next = tsf + trig_timeout;
2404 -
2405 -       ath_dbg(ath9k_hw_common(ah), BTCOEX,
2406 -               "current tsf %x period %x timer_next %x\n",
2407 -               tsf, timer_period, timer_next);
2408 +       timer_table->timer_mask |= BIT(timer->index);
2409  
2410         /*
2411          * Program generic timer registers
2412 @@ -3075,10 +3010,19 @@ void ath9k_hw_gen_timer_start(struct ath
2413                                        (1 << timer->index));
2414         }
2415  
2416 -       /* Enable both trigger and thresh interrupt masks */
2417 -       REG_SET_BIT(ah, AR_IMR_S5,
2418 -               (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2419 -               SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2420 +       if (timer->trigger)
2421 +               mask |= SM(AR_GENTMR_BIT(timer->index),
2422 +                          AR_IMR_S5_GENTIMER_TRIG);
2423 +       if (timer->overflow)
2424 +               mask |= SM(AR_GENTMR_BIT(timer->index),
2425 +                          AR_IMR_S5_GENTIMER_THRESH);
2426 +
2427 +       REG_SET_BIT(ah, AR_IMR_S5, mask);
2428 +
2429 +       if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
2430 +               ah->imask |= ATH9K_INT_GENTIMER;
2431 +               ath9k_hw_set_interrupts(ah);
2432 +       }
2433  }
2434  EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2435  
2436 @@ -3086,11 +3030,6 @@ void ath9k_hw_gen_timer_stop(struct ath_
2437  {
2438         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2439  
2440 -       if ((timer->index < AR_FIRST_NDP_TIMER) ||
2441 -               (timer->index >= ATH_MAX_GEN_TIMER)) {
2442 -               return;
2443 -       }
2444 -
2445         /* Clear generic timer enable bits. */
2446         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2447                         gen_tmr_configuration[timer->index].mode_mask);
2448 @@ -3110,7 +3049,12 @@ void ath9k_hw_gen_timer_stop(struct ath_
2449                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2450                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2451  
2452 -       clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2453 +       timer_table->timer_mask &= ~BIT(timer->index);
2454 +
2455 +       if (timer_table->timer_mask == 0) {
2456 +               ah->imask &= ~ATH9K_INT_GENTIMER;
2457 +               ath9k_hw_set_interrupts(ah);
2458 +       }
2459  }
2460  EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2461  
2462 @@ -3131,32 +3075,32 @@ void ath_gen_timer_isr(struct ath_hw *ah
2463  {
2464         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2465         struct ath_gen_timer *timer;
2466 -       struct ath_common *common = ath9k_hw_common(ah);
2467 -       u32 trigger_mask, thresh_mask, index;
2468 +       unsigned long trigger_mask, thresh_mask;
2469 +       unsigned int index;
2470  
2471         /* get hardware generic timer interrupt status */
2472         trigger_mask = ah->intr_gen_timer_trigger;
2473         thresh_mask = ah->intr_gen_timer_thresh;
2474 -       trigger_mask &= timer_table->timer_mask.val;
2475 -       thresh_mask &= timer_table->timer_mask.val;
2476 +       trigger_mask &= timer_table->timer_mask;
2477 +       thresh_mask &= timer_table->timer_mask;
2478  
2479         trigger_mask &= ~thresh_mask;
2480  
2481 -       while (thresh_mask) {
2482 -               index = rightmost_index(timer_table, &thresh_mask);
2483 +       for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
2484                 timer = timer_table->timers[index];
2485 -               BUG_ON(!timer);
2486 -               ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n",
2487 -                       index);
2488 +               if (!timer)
2489 +                   continue;
2490 +               if (!timer->overflow)
2491 +                   continue;
2492                 timer->overflow(timer->arg);
2493         }
2494  
2495 -       while (trigger_mask) {
2496 -               index = rightmost_index(timer_table, &trigger_mask);
2497 +       for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
2498                 timer = timer_table->timers[index];
2499 -               BUG_ON(!timer);
2500 -               ath_dbg(common, BTCOEX,
2501 -                       "Gen timer[%d] trigger\n", index);
2502 +               if (!timer)
2503 +                   continue;
2504 +               if (!timer->trigger)
2505 +                   continue;
2506                 timer->trigger(timer->arg);
2507         }
2508  }
2509 --- a/drivers/net/wireless/ath/ath9k/hw.h
2510 +++ b/drivers/net/wireless/ath/ath9k/hw.h
2511 @@ -168,7 +168,7 @@
2512  #define CAB_TIMEOUT_VAL             10
2513  #define BEACON_TIMEOUT_VAL          10
2514  #define MIN_BEACON_TIMEOUT_VAL      1
2515 -#define SLEEP_SLOP                  3
2516 +#define SLEEP_SLOP                  TU_TO_USEC(3)
2517  
2518  #define INIT_CONFIG_STATUS          0x00000000
2519  #define INIT_RSSI_THR               0x00000700
2520 @@ -280,11 +280,8 @@ struct ath9k_hw_capabilities {
2521  struct ath9k_ops_config {
2522         int dma_beacon_response_time;
2523         int sw_beacon_response_time;
2524 -       int additional_swba_backoff;
2525         int ack_6mb;
2526         u32 cwm_ignore_extcca;
2527 -       bool pcieSerDesWrite;
2528 -       u8 pcie_clock_req;
2529         u32 pcie_waen;
2530         u8 analog_shiftreg;
2531         u32 ofdm_trig_low;
2532 @@ -295,18 +292,11 @@ struct ath9k_ops_config {
2533         int serialize_regmode;
2534         bool rx_intr_mitigation;
2535         bool tx_intr_mitigation;
2536 -#define SPUR_DISABLE           0
2537 -#define SPUR_ENABLE_IOCTL      1
2538 -#define SPUR_ENABLE_EEPROM     2
2539 -#define AR_SPUR_5413_1         1640
2540 -#define AR_SPUR_5413_2         1200
2541  #define AR_NO_SPUR             0x8000
2542  #define AR_BASE_FREQ_2GHZ      2300
2543  #define AR_BASE_FREQ_5GHZ      4900
2544  #define AR_SPUR_FEEQ_BOUND_HT40 19
2545  #define AR_SPUR_FEEQ_BOUND_HT20 10
2546 -       int spurmode;
2547 -       u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
2548         u8 max_txtrig_level;
2549         u16 ani_poll_interval; /* ANI poll interval in ms */
2550  
2551 @@ -316,6 +306,8 @@ struct ath9k_ops_config {
2552         u32 ant_ctrl_comm2g_switch_enable;
2553         bool xatten_margin_cfg;
2554         bool alt_mingainidx;
2555 +       bool no_pll_pwrsave;
2556 +       bool tx_gain_buffalo;
2557  };
2558  
2559  enum ath9k_int {
2560 @@ -459,10 +451,6 @@ struct ath9k_beacon_state {
2561         u32 bs_intval;
2562  #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
2563         u32 bs_dtimperiod;
2564 -       u16 bs_cfpperiod;
2565 -       u16 bs_cfpmaxduration;
2566 -       u32 bs_cfpnext;
2567 -       u16 bs_timoffset;
2568         u16 bs_bmissthreshold;
2569         u32 bs_sleepduration;
2570         u32 bs_tsfoor_threshold;
2571 @@ -498,12 +486,6 @@ struct ath9k_hw_version {
2572  
2573  #define AR_GENTMR_BIT(_index)  (1 << (_index))
2574  
2575 -/*
2576 - * Using de Bruijin sequence to look up 1's index in a 32 bit number
2577 - * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
2578 - */
2579 -#define debruijn32 0x077CB531U
2580 -
2581  struct ath_gen_timer_configuration {
2582         u32 next_addr;
2583         u32 period_addr;
2584 @@ -519,12 +501,8 @@ struct ath_gen_timer {
2585  };
2586  
2587  struct ath_gen_timer_table {
2588 -       u32 gen_timer_index[32];
2589         struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
2590 -       union {
2591 -               unsigned long timer_bits;
2592 -               u16 val;
2593 -       } timer_mask;
2594 +       u16 timer_mask;
2595  };
2596  
2597  struct ath_hw_antcomb_conf {
2598 @@ -689,7 +667,8 @@ struct ath_hw_ops {
2599                           struct ath9k_channel *chan,
2600                           u8 rxchainmask,
2601                           bool longcal);
2602 -       bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
2603 +       bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked,
2604 +                       u32 *sync_cause_p);
2605         void (*set_txdesc)(struct ath_hw *ah, void *ds,
2606                            struct ath_tx_info *i);
2607         int (*proc_txdesc)(struct ath_hw *ah, void *ds,
2608 @@ -785,7 +764,6 @@ struct ath_hw {
2609         u32 txurn_interrupt_mask;
2610         atomic_t intr_ref_cnt;
2611         bool chip_fullsleep;
2612 -       u32 atim_window;
2613         u32 modes_index;
2614  
2615         /* Calibration */
2616 @@ -864,6 +842,7 @@ struct ath_hw {
2617         u32 gpio_mask;
2618         u32 gpio_val;
2619  
2620 +       struct ar5416IniArray ini_dfs;
2621         struct ar5416IniArray iniModes;
2622         struct ar5416IniArray iniCommon;
2623         struct ar5416IniArray iniBB_RfGain;
2624 @@ -920,7 +899,7 @@ struct ath_hw {
2625         /* Enterprise mode cap */
2626         u32 ent_mode;
2627  
2628 -#ifdef CONFIG_PM_SLEEP
2629 +#ifdef CONFIG_ATH9K_WOW
2630         u32 wow_event_mask;
2631  #endif
2632         bool is_clk_25mhz;
2633 @@ -1016,13 +995,6 @@ bool ath9k_hw_check_alive(struct ath_hw 
2634  
2635  bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
2636  
2637 -#ifdef CPTCFG_ATH9K_DEBUGFS
2638 -void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause);
2639 -#else
2640 -static inline void ath9k_debug_sync_cause(struct ath_common *common,
2641 -                                         u32 sync_cause) {}
2642 -#endif
2643 -
2644  /* Generic hw timer primitives */
2645  struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2646                                           void (*trigger)(void *),
2647 @@ -1126,7 +1098,7 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw
2648  #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */
2649  
2650  
2651 -#ifdef CONFIG_PM_SLEEP
2652 +#ifdef CONFIG_ATH9K_WOW
2653  const char *ath9k_hw_wow_event_to_string(u32 wow_event);
2654  void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
2655                                 u8 *user_mask, int pattern_count,
2656 --- a/drivers/net/wireless/ath/ath9k/init.c
2657 +++ b/drivers/net/wireless/ath/ath9k/init.c
2658 @@ -470,7 +470,6 @@ static int ath9k_init_queues(struct ath_
2659  
2660         sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
2661         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
2662 -
2663         ath_cabq_update(sc);
2664  
2665         sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
2666 @@ -554,7 +553,7 @@ static void ath9k_init_misc(struct ath_s
2667         sc->spec_config.fft_period = 0xF;
2668  }
2669  
2670 -static void ath9k_init_platform(struct ath_softc *sc)
2671 +static void ath9k_init_pcoem_platform(struct ath_softc *sc)
2672  {
2673         struct ath_hw *ah = sc->sc_ah;
2674         struct ath9k_hw_capabilities *pCap = &ah->caps;
2675 @@ -609,6 +608,11 @@ static void ath9k_init_platform(struct a
2676                 ah->config.pcie_waen = 0x0040473b;
2677                 ath_info(common, "Enable WAR for ASPM D3/L1\n");
2678         }
2679 +
2680 +       if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
2681 +               ah->config.no_pll_pwrsave = true;
2682 +               ath_info(common, "Disable PLL PowerSave\n");
2683 +       }
2684  }
2685  
2686  static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
2687 @@ -656,6 +660,27 @@ static void ath9k_eeprom_release(struct 
2688         release_firmware(sc->sc_ah->eeprom_blob);
2689  }
2690  
2691 +static int ath9k_init_soc_platform(struct ath_softc *sc)
2692 +{
2693 +       struct ath9k_platform_data *pdata = sc->dev->platform_data;
2694 +       struct ath_hw *ah = sc->sc_ah;
2695 +       int ret = 0;
2696 +
2697 +       if (!pdata)
2698 +               return 0;
2699 +
2700 +       if (pdata->eeprom_name) {
2701 +               ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
2702 +               if (ret)
2703 +                       return ret;
2704 +       }
2705 +
2706 +       if (pdata->tx_gain_buffalo)
2707 +               ah->config.tx_gain_buffalo = true;
2708 +
2709 +       return ret;
2710 +}
2711 +
2712  static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
2713                             const struct ath_bus_ops *bus_ops)
2714  {
2715 @@ -676,13 +701,13 @@ static int ath9k_init_softc(u16 devid, s
2716         ah->reg_ops.read = ath9k_ioread32;
2717         ah->reg_ops.write = ath9k_iowrite32;
2718         ah->reg_ops.rmw = ath9k_reg_rmw;
2719 -       atomic_set(&ah->intr_ref_cnt, -1);
2720         sc->sc_ah = ah;
2721         pCap = &ah->caps;
2722  
2723         common = ath9k_hw_common(ah);
2724         sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
2725         sc->tx99_power = MAX_RATE_POWER + 1;
2726 +       init_waitqueue_head(&sc->tx_wait);
2727  
2728         if (!pdata) {
2729                 ah->ah_flags |= AH_USE_EEPROM;
2730 @@ -708,7 +733,11 @@ static int ath9k_init_softc(u16 devid, s
2731         /*
2732          * Platform quirks.
2733          */
2734 -       ath9k_init_platform(sc);
2735 +       ath9k_init_pcoem_platform(sc);
2736 +
2737 +       ret = ath9k_init_soc_platform(sc);
2738 +       if (ret)
2739 +               return ret;
2740  
2741         /*
2742          * Enable WLAN/BT RX Antenna diversity only when:
2743 @@ -722,7 +751,6 @@ static int ath9k_init_softc(u16 devid, s
2744                 common->bt_ant_diversity = 1;
2745  
2746         spin_lock_init(&common->cc_lock);
2747 -
2748         spin_lock_init(&sc->sc_serial_rw);
2749         spin_lock_init(&sc->sc_pm_lock);
2750         mutex_init(&sc->mutex);
2751 @@ -730,6 +758,7 @@ static int ath9k_init_softc(u16 devid, s
2752         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
2753                      (unsigned long)sc);
2754  
2755 +       setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
2756         INIT_WORK(&sc->hw_reset_work, ath_reset_work);
2757         INIT_WORK(&sc->hw_check_work, ath_hw_check);
2758         INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
2759 @@ -743,12 +772,6 @@ static int ath9k_init_softc(u16 devid, s
2760         ath_read_cachesize(common, &csz);
2761         common->cachelsz = csz << 2; /* convert to bytes */
2762  
2763 -       if (pdata && pdata->eeprom_name) {
2764 -               ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
2765 -               if (ret)
2766 -                       return ret;
2767 -       }
2768 -
2769         /* Initializes the hardware for all supported chipsets */
2770         ret = ath9k_hw_init(ah);
2771         if (ret)
2772 @@ -845,7 +868,8 @@ static const struct ieee80211_iface_limi
2773  };
2774  
2775  static const struct ieee80211_iface_limit if_dfs_limits[] = {
2776 -       { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) },
2777 +       { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) |
2778 +                                BIT(NL80211_IFTYPE_ADHOC) },
2779  };
2780  
2781  static const struct ieee80211_iface_combination if_comb[] = {
2782 @@ -862,21 +886,12 @@ static const struct ieee80211_iface_comb
2783                 .max_interfaces = 1,
2784                 .num_different_channels = 1,
2785                 .beacon_int_infra_match = true,
2786 -               .radar_detect_widths =  BIT(NL80211_CHAN_NO_HT) |
2787 -                                       BIT(NL80211_CHAN_HT20),
2788 +               .radar_detect_widths =  BIT(NL80211_CHAN_WIDTH_20_NOHT) |
2789 +                                       BIT(NL80211_CHAN_WIDTH_20),
2790         }
2791  };
2792  
2793 -#ifdef CONFIG_PM
2794 -static const struct wiphy_wowlan_support ath9k_wowlan_support = {
2795 -       .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2796 -       .n_patterns = MAX_NUM_USER_PATTERN,
2797 -       .pattern_min_len = 1,
2798 -       .pattern_max_len = MAX_PATTERN_SIZE,
2799 -};
2800 -#endif
2801 -
2802 -void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
2803 +static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
2804  {
2805         struct ath_hw *ah = sc->sc_ah;
2806         struct ath_common *common = ath9k_hw_common(ah);
2807 @@ -925,16 +940,6 @@ void ath9k_set_hw_capab(struct ath_softc
2808         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
2809         hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
2810  
2811 -#ifdef CONFIG_PM_SLEEP
2812 -       if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
2813 -           (sc->driver_data & ATH9K_PCI_WOW) &&
2814 -           device_can_wakeup(sc->dev))
2815 -               hw->wiphy->wowlan = &ath9k_wowlan_support;
2816 -
2817 -       atomic_set(&sc->wow_sleep_proc_intr, -1);
2818 -       atomic_set(&sc->wow_got_bmiss_intr, -1);
2819 -#endif
2820 -
2821         hw->queues = 4;
2822         hw->max_rates = 4;
2823         hw->channel_change_time = 5000;
2824 @@ -960,6 +965,7 @@ void ath9k_set_hw_capab(struct ath_softc
2825                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2826                         &sc->sbands[IEEE80211_BAND_5GHZ];
2827  
2828 +       ath9k_init_wow(hw);
2829         ath9k_reload_chainmask_settings(sc);
2830  
2831         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
2832 @@ -1058,6 +1064,7 @@ static void ath9k_deinit_softc(struct at
2833                 if (ATH_TXQ_SETUP(sc, i))
2834                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
2835  
2836 +       del_timer_sync(&sc->sleep_timer);
2837         ath9k_hw_deinit(sc->sc_ah);
2838         if (sc->dfs_detector != NULL)
2839                 sc->dfs_detector->exit(sc->dfs_detector);
2840 --- a/drivers/net/wireless/ath/ath9k/main.c
2841 +++ b/drivers/net/wireless/ath/ath9k/main.c
2842 @@ -82,6 +82,22 @@ static bool ath9k_setpower(struct ath_so
2843         return ret;
2844  }
2845  
2846 +void ath_ps_full_sleep(unsigned long data)
2847 +{
2848 +       struct ath_softc *sc = (struct ath_softc *) data;
2849 +       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2850 +       bool reset;
2851 +
2852 +       spin_lock(&common->cc_lock);
2853 +       ath_hw_cycle_counters_update(common);
2854 +       spin_unlock(&common->cc_lock);
2855 +
2856 +       ath9k_hw_setrxabort(sc->sc_ah, 1);
2857 +       ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
2858 +
2859 +       ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
2860 +}
2861 +
2862  void ath9k_ps_wakeup(struct ath_softc *sc)
2863  {
2864         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2865 @@ -92,6 +108,7 @@ void ath9k_ps_wakeup(struct ath_softc *s
2866         if (++sc->ps_usecount != 1)
2867                 goto unlock;
2868  
2869 +       del_timer_sync(&sc->sleep_timer);
2870         power_mode = sc->sc_ah->power_mode;
2871         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2872  
2873 @@ -117,17 +134,17 @@ void ath9k_ps_restore(struct ath_softc *
2874         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2875         enum ath9k_power_mode mode;
2876         unsigned long flags;
2877 -       bool reset;
2878  
2879         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2880         if (--sc->ps_usecount != 0)
2881                 goto unlock;
2882  
2883         if (sc->ps_idle) {
2884 -               ath9k_hw_setrxabort(sc->sc_ah, 1);
2885 -               ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
2886 -               mode = ATH9K_PM_FULL_SLEEP;
2887 -       } else if (sc->ps_enabled &&
2888 +               mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
2889 +               goto unlock;
2890 +       }
2891 +
2892 +       if (sc->ps_enabled &&
2893                    !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
2894                                      PS_WAIT_FOR_CAB |
2895                                      PS_WAIT_FOR_PSPOLL_DATA |
2896 @@ -163,13 +180,13 @@ static void __ath_cancel_work(struct ath
2897  #endif
2898  }
2899  
2900 -static void ath_cancel_work(struct ath_softc *sc)
2901 +void ath_cancel_work(struct ath_softc *sc)
2902  {
2903         __ath_cancel_work(sc);
2904         cancel_work_sync(&sc->hw_reset_work);
2905  }
2906  
2907 -static void ath_restart_work(struct ath_softc *sc)
2908 +void ath_restart_work(struct ath_softc *sc)
2909  {
2910         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2911  
2912 @@ -487,8 +504,13 @@ void ath9k_tasklet(unsigned long data)
2913                         ath_tx_edma_tasklet(sc);
2914                 else
2915                         ath_tx_tasklet(sc);
2916 +
2917 +               wake_up(&sc->tx_wait);
2918         }
2919  
2920 +       if (status & ATH9K_INT_GENTIMER)
2921 +               ath_gen_timer_isr(sc->sc_ah);
2922 +
2923         ath9k_btcoex_handle_interrupt(sc, status);
2924  
2925         /* re-enable hardware interrupt */
2926 @@ -519,6 +541,7 @@ irqreturn_t ath_isr(int irq, void *dev)
2927         struct ath_hw *ah = sc->sc_ah;
2928         struct ath_common *common = ath9k_hw_common(ah);
2929         enum ath9k_int status;
2930 +       u32 sync_cause;
2931         bool sched = false;
2932  
2933         /*
2934 @@ -545,7 +568,8 @@ irqreturn_t ath_isr(int irq, void *dev)
2935          * bits we haven't explicitly enabled so we mask the
2936          * value to insure we only process bits we requested.
2937          */
2938 -       ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
2939 +       ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
2940 +       ath9k_debug_sync_cause(sc, sync_cause);
2941         status &= ah->imask;    /* discard unasked-for bits */
2942  
2943         /*
2944 @@ -579,7 +603,8 @@ irqreturn_t ath_isr(int irq, void *dev)
2945  
2946                 goto chip_reset;
2947         }
2948 -#ifdef CONFIG_PM_SLEEP
2949 +
2950 +#ifdef CONFIG_ATH9K_WOW
2951         if (status & ATH9K_INT_BMISS) {
2952                 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
2953                         ath_dbg(common, ANY, "during WoW we got a BMISS\n");
2954 @@ -588,6 +613,8 @@ irqreturn_t ath_isr(int irq, void *dev)
2955                 }
2956         }
2957  #endif
2958 +
2959 +
2960         if (status & ATH9K_INT_SWBA)
2961                 tasklet_schedule(&sc->bcon_tasklet);
2962  
2963 @@ -627,7 +654,7 @@ chip_reset:
2964  #undef SCHED_INTR
2965  }
2966  
2967 -static int ath_reset(struct ath_softc *sc)
2968 +int ath_reset(struct ath_softc *sc)
2969  {
2970         int r;
2971  
2972 @@ -735,6 +762,8 @@ static int ath9k_start(struct ieee80211_
2973          */
2974         ath9k_cmn_init_crypto(sc->sc_ah);
2975  
2976 +       ath9k_hw_reset_tsf(ah);
2977 +
2978         spin_unlock_bh(&sc->sc_pcu_lock);
2979  
2980         mutex_unlock(&sc->mutex);
2981 @@ -1635,13 +1664,8 @@ static void ath9k_bss_info_changed(struc
2982         }
2983  
2984         if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
2985 -           (changed & BSS_CHANGED_BEACON_INT)) {
2986 -               if (ah->opmode == NL80211_IFTYPE_AP &&
2987 -                   bss_conf->enable_beacon)
2988 -                       ath9k_set_tsfadjust(sc, vif);
2989 -               if (ath9k_allow_beacon_config(sc, vif))
2990 -                       ath9k_beacon_config(sc, vif, changed);
2991 -       }
2992 +           (changed & BSS_CHANGED_BEACON_INT))
2993 +               ath9k_beacon_config(sc, vif, changed);
2994  
2995         if (changed & BSS_CHANGED_ERP_SLOT) {
2996                 if (bss_conf->use_short_slot)
2997 @@ -1817,13 +1841,31 @@ static void ath9k_set_coverage_class(str
2998         mutex_unlock(&sc->mutex);
2999  }
3000  
3001 +static bool ath9k_has_tx_pending(struct ath_softc *sc)
3002 +{
3003 +       int i, npend;
3004 +
3005 +       for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
3006 +               if (!ATH_TXQ_SETUP(sc, i))
3007 +                       continue;
3008 +
3009 +               if (!sc->tx.txq[i].axq_depth)
3010 +                       continue;
3011 +
3012 +               npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
3013 +               if (npend)
3014 +                       break;
3015 +       }
3016 +
3017 +       return !!npend;
3018 +}
3019 +
3020  static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
3021  {
3022         struct ath_softc *sc = hw->priv;
3023         struct ath_hw *ah = sc->sc_ah;
3024         struct ath_common *common = ath9k_hw_common(ah);
3025 -       int timeout = 200; /* ms */
3026 -       int i, j;
3027 +       int timeout = HZ / 5; /* 200 ms */
3028         bool drain_txq;
3029  
3030         mutex_lock(&sc->mutex);
3031 @@ -1841,25 +1883,9 @@ static void ath9k_flush(struct ieee80211
3032                 return;
3033         }
3034  
3035 -       for (j = 0; j < timeout; j++) {
3036 -               bool npend = false;
3037 -
3038 -               if (j)
3039 -                       usleep_range(1000, 2000);
3040 -
3041 -               for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
3042 -                       if (!ATH_TXQ_SETUP(sc, i))
3043 -                               continue;
3044 -
3045 -                       npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
3046 -
3047 -                       if (npend)
3048 -                               break;
3049 -               }
3050 -
3051 -               if (!npend)
3052 -                   break;
3053 -       }
3054 +       if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
3055 +                              timeout) > 0)
3056 +               drop = false;
3057  
3058         if (drop) {
3059                 ath9k_ps_wakeup(sc);
3060 @@ -2021,333 +2047,6 @@ static int ath9k_get_antenna(struct ieee
3061         return 0;
3062  }
3063  
3064 -#ifdef CONFIG_PM_SLEEP
3065 -
3066 -static void ath9k_wow_map_triggers(struct ath_softc *sc,
3067 -                                  struct cfg80211_wowlan *wowlan,
3068 -                                  u32 *wow_triggers)
3069 -{
3070 -       if (wowlan->disconnect)
3071 -               *wow_triggers |= AH_WOW_LINK_CHANGE |
3072 -                                AH_WOW_BEACON_MISS;
3073 -       if (wowlan->magic_pkt)
3074 -               *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
3075 -
3076 -       if (wowlan->n_patterns)
3077 -               *wow_triggers |= AH_WOW_USER_PATTERN_EN;
3078 -
3079 -       sc->wow_enabled = *wow_triggers;
3080 -
3081 -}
3082 -
3083 -static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
3084 -{
3085 -       struct ath_hw *ah = sc->sc_ah;
3086 -       struct ath_common *common = ath9k_hw_common(ah);
3087 -       int pattern_count = 0;
3088 -       int i, byte_cnt;
3089 -       u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
3090 -       u8 dis_deauth_mask[MAX_PATTERN_SIZE];
3091 -
3092 -       memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
3093 -       memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
3094 -
3095 -       /*
3096 -        * Create Dissassociate / Deauthenticate packet filter
3097 -        *
3098 -        *     2 bytes        2 byte    6 bytes   6 bytes  6 bytes
3099 -        *  +--------------+----------+---------+--------+--------+----
3100 -        *  + Frame Control+ Duration +   DA    +  SA    +  BSSID +
3101 -        *  +--------------+----------+---------+--------+--------+----
3102 -        *
3103 -        * The above is the management frame format for disassociate/
3104 -        * deauthenticate pattern, from this we need to match the first byte
3105 -        * of 'Frame Control' and DA, SA, and BSSID fields
3106 -        * (skipping 2nd byte of FC and Duration feild.
3107 -        *
3108 -        * Disassociate pattern
3109 -        * --------------------
3110 -        * Frame control = 00 00 1010
3111 -        * DA, SA, BSSID = x:x:x:x:x:x
3112 -        * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
3113 -        *                          | x:x:x:x:x:x  -- 22 bytes
3114 -        *
3115 -        * Deauthenticate pattern
3116 -        * ----------------------
3117 -        * Frame control = 00 00 1100
3118 -        * DA, SA, BSSID = x:x:x:x:x:x
3119 -        * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
3120 -        *                          | x:x:x:x:x:x  -- 22 bytes
3121 -        */
3122 -
3123 -       /* Create Disassociate Pattern first */
3124 -
3125 -       byte_cnt = 0;
3126 -
3127 -       /* Fill out the mask with all FF's */
3128 -
3129 -       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
3130 -               dis_deauth_mask[i] = 0xff;
3131 -
3132 -       /* copy the first byte of frame control field */
3133 -       dis_deauth_pattern[byte_cnt] = 0xa0;
3134 -       byte_cnt++;
3135 -
3136 -       /* skip 2nd byte of frame control and Duration field */
3137 -       byte_cnt += 3;
3138 -
3139 -       /*
3140 -        * need not match the destination mac address, it can be a broadcast
3141 -        * mac address or an unicast to this station
3142 -        */
3143 -       byte_cnt += 6;
3144 -
3145 -       /* copy the source mac address */
3146 -       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
3147 -
3148 -       byte_cnt += 6;
3149 -
3150 -       /* copy the bssid, its same as the source mac address */
3151 -
3152 -       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
3153 -
3154 -       /* Create Disassociate pattern mask */
3155 -
3156 -       dis_deauth_mask[0] = 0xfe;
3157 -       dis_deauth_mask[1] = 0x03;
3158 -       dis_deauth_mask[2] = 0xc0;
3159 -
3160 -       ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
3161 -
3162 -       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
3163 -                                  pattern_count, byte_cnt);
3164 -
3165 -       pattern_count++;
3166 -       /*
3167 -        * for de-authenticate pattern, only the first byte of the frame
3168 -        * control field gets changed from 0xA0 to 0xC0
3169 -        */
3170 -       dis_deauth_pattern[0] = 0xC0;
3171 -
3172 -       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
3173 -                                  pattern_count, byte_cnt);
3174 -
3175 -}
3176 -
3177 -static void ath9k_wow_add_pattern(struct ath_softc *sc,
3178 -                                 struct cfg80211_wowlan *wowlan)
3179 -{
3180 -       struct ath_hw *ah = sc->sc_ah;
3181 -       struct ath9k_wow_pattern *wow_pattern = NULL;
3182 -       struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
3183 -       int mask_len;
3184 -       s8 i = 0;
3185 -
3186 -       if (!wowlan->n_patterns)
3187 -               return;
3188 -
3189 -       /*
3190 -        * Add the new user configured patterns
3191 -        */
3192 -       for (i = 0; i < wowlan->n_patterns; i++) {
3193 -
3194 -               wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
3195 -
3196 -               if (!wow_pattern)
3197 -   &nbs