target/linux/ramips/patches-3.18/0062-mt7621-add-ECHI-OCHI-XCHI-support.patch

   1 --- a/drivers/usb/core/hcd-pci.c
   2 +++ b/drivers/usb/core/hcd-pci.c
   3 @@ -214,8 +214,13 @@ int usb_hcd_pci_probe(struct pci_dev *de
   4                 goto disable_pci;
   5         }
   6
   7 +
   8 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
   9 +       hcd->amd_resume_bug = 0;
  10 +#else
  11         hcd->amd_resume_bug = (usb_hcd_amd_remote_wakeup_quirk(dev) &&
  12                         driver->flags & (HCD_USB11 | HCD_USB3)) ? 1 : 0;
  13 +#endif
  14
  15         if (driver->flags & HCD_MEMORY) {
  16                 /* EHCI, OHCI */
  17 --- a/drivers/usb/core/hub.c
  18 +++ b/drivers/usb/core/hub.c
  19 @@ -1286,7 +1286,7 @@ static void hub_quiesce(struct usb_hub *
  20         if (type != HUB_SUSPEND) {
  21                 /* Disconnect all the children */
  22                 for (i = 0; i < hdev->maxchild; ++i) {
  23 -                       if (hub->ports[i]->child)
  24 +                       if (hub->ports[i] && hub->ports[i]->child)
  25                                 usb_disconnect(&hub->ports[i]->child);
  26                 }
  27         }
  28 --- a/drivers/usb/core/port.c
  29 +++ b/drivers/usb/core/port.c
  30 @@ -480,8 +480,10 @@ void usb_hub_remove_port_device(struct u
  31         struct usb_port *port_dev = hub->ports[port1 - 1];
  32         struct usb_port *peer;
  33
  34 -       peer = port_dev->peer;
  35 -       if (peer)
  36 -               unlink_peers(port_dev, peer);
  37 -       device_unregister(&port_dev->dev);
  38 +       if(port_dev) {
  39 +               peer = port_dev->peer;
  40 +               if (peer)
  41 +                       unlink_peers(port_dev, peer);
  42 +               device_unregister(&port_dev->dev);
  43 +       }
  44  }
  45 --- a/drivers/usb/host/Kconfig
  46 +++ b/drivers/usb/host/Kconfig
  47 @@ -32,7 +32,14 @@ config USB_XHCI_PCI
  48         default y
  49
  50  config USB_XHCI_PLATFORM
  51 -       tristate
  52 +       tristate "xHCI platform"
  53 +
  54 +config USB_MT7621_XHCI_PLATFORM
  55 +       bool
  56 +       depends on USB_XHCI_PLATFORM
  57 +       depends on SOC_MT7621
  58 +       select USB_PHY
  59 +       default y
  60
  61  config USB_XHCI_MVEBU
  62         tristate "xHCI support for Marvell Armada 375/38x"
  63 @@ -589,7 +596,7 @@ endif # USB_OHCI_HCD
  64
  65  config USB_UHCI_HCD
  66         tristate "UHCI HCD (most Intel and VIA) support"
  67 -       depends on PCI || USB_UHCI_SUPPORT_NON_PCI_HC
  68 +       depends on BROKEN && (PCI || USB_UHCI_SUPPORT_NON_PCI_HC)
  69         ---help---
  70           The Universal Host Controller Interface is a standard by Intel for
  71           accessing the USB hardware in the PC (which is also called the USB
  72 --- a/drivers/usb/host/Makefile
  73 +++ b/drivers/usb/host/Makefile
  74 @@ -16,7 +16,12 @@ xhci-hcd-y := xhci.o xhci-mem.o
  75  xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
  76  xhci-hcd-y += xhci-trace.o
  77
  78 +ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
  79 +xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
  80 +endif
  81 +
  82  xhci-plat-hcd-y := xhci-plat.o
  83 +
  84  ifneq ($(CONFIG_USB_XHCI_MVEBU), )
  85         xhci-plat-hcd-y         += xhci-mvebu.o
  86  endif
  87 @@ -26,9 +31,14 @@ endif
  88
  89  obj-$(CONFIG_USB_WHCI_HCD)     += whci/
  90
  91 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
  92  obj-$(CONFIG_PCI)              += pci-quirks.o
  93 +endif
  94
  95 +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
  96  obj-$(CONFIG_USB_XHCI_PCI)     += xhci-pci.o
  97 +endif
  98 +
  99  obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
 100
 101  obj-$(CONFIG_USB_EHCI_HCD)     += ehci-hcd.o
 102 --- /dev/null
 103 +++ b/drivers/usb/host/mtk-phy-7621.c
 104 @@ -0,0 +1,445 @@
 105 +#include "mtk-phy.h"
 106 +
 107 +#ifdef CONFIG_PROJECT_7621
 108 +#include "mtk-phy-7621.h"
 109 +
 110 +//not used on SoC
 111 +PHY_INT32 phy_init(struct u3phy_info *info){
 112 +       return PHY_TRUE;
 113 +}
 114 +
 115 +//not used on SoC
 116 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
 117 +       return PHY_TRUE;
 118 +}
 119 +
 120 +//--------------------------------------------------------
 121 +//    Function : fgEyeScanHelper_CheckPtInRegion()
 122 +// Description : Check if the test point is in a rectangle region.
 123 +//               If it is in the rectangle, also check if this point
 124 +//               is on the multiple of deltaX and deltaY.
 125 +//   Parameter : strucScanRegion * prEye - the region
 126 +//               BYTE bX
 127 +//               BYTE bY
 128 +//      Return : BYTE - TRUE :  This point needs to be tested
 129 +//                      FALSE:  This point will be omitted
 130 +//        Note : First check within the rectangle.
 131 +//               Secondly, use modulous to check if the point will be tested.
 132 +//--------------------------------------------------------
 133 +static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
 134 +{
 135 +  PHY_INT8 fgValid = true;
 136 +
 137 +
 138 +  /// Be careful, the axis origin is on the TOP-LEFT corner.
 139 +  /// Therefore the top-left point has the minimum X and Y
 140 +  /// Botton-right point is the maximum X and Y
 141 +  if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
 142 +    && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
 143 +  {
 144 +    // With the region, now check whether or not the input test point is
 145 +    // on the multiples of X and Y
 146 +    // Do not have to worry about negative value, because we have already
 147 +    // check the input bX, and bY is within the region.
 148 +    if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
 149 +      || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
 150 +    {
 151 +      // if the division will have remainder, that means
 152 +      // the input test point is on the multiples of X and Y
 153 +      fgValid = false;
 154 +    }
 155 +    else
 156 +    {
 157 +    }
 158 +  }
 159 +  else
 160 +  {
 161 +
 162 +    fgValid = false;
 163 +  }
 164 +  return fgValid;
 165 +}
 166 +
 167 +//--------------------------------------------------------
 168 +//    Function : EyeScanHelper_RunTest()
 169 +// Description : Enable the test, and wait til it is completed
 170 +//   Parameter : None
 171 +//      Return : None
 172 +//        Note : None
 173 +//--------------------------------------------------------
 174 +static void EyeScanHelper_RunTest(struct u3phy_info *info)
 175 +{
 176 +       DRV_UDELAY(100);
 177 +       // Disable the test
 178 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 179 +               , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0);      //RG_SSUSB_RX_EYE_CNT_EN = 0
 180 +       DRV_UDELAY(100);
 181 +       // Run the test
 182 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 183 +               , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1);      //RG_SSUSB_RX_EYE_CNT_EN = 1
 184 +       DRV_UDELAY(100);
 185 +       // Wait til it's done
 186 +       //RGS_SSUSB_RX_EYE_CNT_RDY
 187 +       while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
 188 +               , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
 189 +}
 190 +
 191 +//--------------------------------------------------------
 192 +//    Function : fgEyeScanHelper_CalNextPoint()
 193 +// Description : Calcualte the test point for the measurement
 194 +//   Parameter : None
 195 +//      Return : BOOL - TRUE :  the next point is within the
 196 +//                              boundaryof HW limit
 197 +//                      FALSE:  the next point is out of the HW limit
 198 +//        Note : The next point is obtained by calculating
 199 +//               from the bottom left of the region rectangle
 200 +//               and then scanning up until it reaches the upper
 201 +//               limit. At this time, the x will increment, and
 202 +//               start scanning downwards until the y hits the
 203 +//               zero.
 204 +//--------------------------------------------------------
 205 +static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
 206 +{
 207 +  if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
 208 +    || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
 209 +        )
 210 +  {
 211 +    /// Reaches the limit of Y axis
 212 +    /// Increment X
 213 +    _bXcurr++;
 214 +    _fgXChged = true;
 215 +    _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
 216 +
 217 +    if (_bXcurr > MAX_X)
 218 +    {
 219 +      return false;
 220 +    }
 221 +  }
 222 +  else
 223 +  {
 224 +    _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
 225 +    _fgXChged = false;
 226 +  }
 227 +  return PHY_TRUE;
 228 +}
 229 +
 230 +PHY_INT32 eyescan_init(struct u3phy_info *info){
 231 +       //initial PHY setting
 232 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
 233 +               , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
 234 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
 235 +               , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
 236 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
 237 +               , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1);    //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
 238 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
 239 +               , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1);        //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
 240 +       return PHY_TRUE;
 241 +}
 242 +
 243 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
 244 +               , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
 245 +       PHY_INT32 cOfst = 0;
 246 +       PHY_UINT8 bIdxX = 0;
 247 +       PHY_UINT8 bIdxY = 0;
 248 +       //PHY_INT8 bCnt = 0;
 249 +       PHY_UINT8 bIdxCycCnt = 0;
 250 +       PHY_INT8 fgValid;
 251 +       PHY_INT8 cX;
 252 +       PHY_INT8 cY;
 253 +       PHY_UINT8 bExtendCnt;
 254 +       PHY_INT8 isContinue;
 255 +       //PHY_INT8 isBreak;
 256 +       PHY_UINT32 wErr0 = 0, wErr1 = 0;
 257 +       //PHY_UINT32 temp;
 258 +
 259 +       PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
 260 +       PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
 261 +
 262 +       _rEye1.bX_tl = x_t1;
 263 +       _rEye1.bY_tl = y_t1;
 264 +       _rEye1.bX_br = x_br;
 265 +       _rEye1.bY_br = y_br;
 266 +       _rEye1.bDeltaX = delta_x;
 267 +       _rEye1.bDeltaY = delta_y;
 268 +
 269 +       _rEye2.bX_tl = x_t1;
 270 +       _rEye2.bY_tl = y_t1;
 271 +       _rEye2.bX_br = x_br;
 272 +       _rEye2.bY_br = y_br;
 273 +       _rEye2.bDeltaX = delta_x;
 274 +       _rEye2.bDeltaY = delta_y;
 275 +
 276 +       _rTestCycle.wEyeCnt = eye_cnt;
 277 +       _rTestCycle.bNumOfEyeCnt = num_cnt;
 278 +       _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
 279 +       _rTestCycle.bPICalEn = PI_cal_en;
 280 +
 281 +       _bXcurr = 0;
 282 +       _bYcurr = 0;
 283 +       _eScanDir = SCAN_DN;
 284 +       _fgXChged = false;
 285 +
 286 +       printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
 287 +               eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
 288 +               x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
 289 +
 290 +       //force SIGDET to OFF
 291 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
 292 +               , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1);                                                //RG_SSUSB_RX_SIGDET_SEL = 1
 293 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
 294 +               , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0);                                                //RG_SSUSB_RX_SIGDET_EN = 0
 295 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
 296 +               , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0);                              //RG_SSUSB_RX_SIGDET = 0
 297 +
 298 +       // RX_TRI_DET_EN to Disable
 299 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
 300 +               , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0);              //RG_SSUSB_RX_TRI_DET_EN = 0
 301 +
 302 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 303 +               , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1);              //RG_SSUSB_EYE_MON_EN = 1
 304 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 305 +               , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0);            //RG_SSUSB_RX_EYE_XOFFSET = 0
 306 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 307 +               , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0);                              //RG_SSUSB_RX_EYE0_Y = 0
 308 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 309 +               , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0);                              //RG_SSUSB_RX_EYE1_Y = 0
 310 +
 311 +
 312 +       if (PI_cal_en){
 313 +               // PI Calibration
 314 +               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
 315 +                       , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1);        //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
 316 +               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
 317 +                       , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0);                //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
 318 +               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
 319 +                       , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1);                //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
 320 +
 321 +               DRV_UDELAY(20);
 322 +
 323 +               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
 324 +                       , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0);                //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
 325 +               _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
 326 +                       , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO);                         //read RGS_SSUSB_RX_PILPO
 327 +
 328 +               printk(KERN_ERR "PI result: %d\n", _bPIResult);
 329 +       }
 330 +       // Read Initial DAC
 331 +       // Set CYCLE
 332 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
 333 +               ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt);                       //RG_SSUSB_RX_EYE_CNT
 334 +
 335 +       // Eye Monitor Feature
 336 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
 337 +               , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff);              //RG_SSUSB_RX_EYE_MASK = 0x3ff
 338 +       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 339 +               , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1);              //RG_SSUSB_EYE_MON_EN = 1
 340 +
 341 +       // Move X,Y to the top-left corner
 342 +       for (cOfst = 0; cOfst >= -64; cOfst--)
 343 +       {
 344 +               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 345 +                       ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
 346 +       }
 347 +       for (cOfst = 0; cOfst < 64; cOfst++)
 348 +       {
 349 +               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 350 +                       , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);                  //RG_SSUSB_RX_EYE0_Y
 351 +               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 352 +                       , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);                  //RG_SSUSB_RX_EYE1_Y
 353 +       }
 354 +       //ClearErrorResult
 355 +       for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
 356 +               for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
 357 +               {
 358 +                       for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
 359 +                               pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
 360 +                               pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
 361 +                       }
 362 +               }
 363 +       }
 364 +       isContinue = true;
 365 +       while(isContinue){
 366 +               //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
 367 +               // The point is within the boundary, then let's check if it is within
 368 +           // the testing region.
 369 +           // The point is only test-able if one of the eye region
 370 +           // includes this point.
 371 +           fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
 372 +           || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
 373 +               // Translate bX and bY to 2's complement from where the origin was on the
 374 +               // top left corner.
 375 +               // 0x40 and 0x3F needs a bit of thinking!!!! >"<
 376 +               cX = (_bXcurr ^ 0x40);
 377 +               cY = (_bYcurr ^ 0x3F);
 378 +
 379 +               // Set X if necessary
 380 +               if (_fgXChged == true)
 381 +               {
 382 +                       U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 383 +                               , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX);           //RG_SSUSB_RX_EYE_XOFFSET
 384 +               }
 385 +               // Set Y
 386 +               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 387 +                       , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY);                     //RG_SSUSB_RX_EYE0_Y
 388 +               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 389 +                       , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY);                     //RG_SSUSB_RX_EYE1_Y
 390 +
 391 +               /// Test this point!
 392 +               if (fgValid){
 393 +                       for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
 394 +                       {
 395 +                               //run test
 396 +                               EyeScanHelper_RunTest(info);
 397 +                       }
 398 +                       for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
 399 +                       {
 400 +                               EyeScanHelper_RunTest(info);
 401 +                               wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
 402 +                                       , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
 403 +                               wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
 404 +                                       , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
 405 +
 406 +                               pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
 407 +                               pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
 408 +
 409 +                               //EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
 410 +//                             printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
 411 +//                                     , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
 412 +                       }
 413 +                       //printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
 414 +               }
 415 +               else{
 416 +
 417 +               }
 418 +               if (fgEyeScanHelper_CalNextPoint() == false){
 419 +#if 0
 420 +                       printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
 421 +                       printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
 422 +#endif
 423 +                       printk(KERN_ERR "end of eye scan\n");
 424 +                       isContinue = false;
 425 +               }
 426 +       }
 427 +       printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
 428 +               , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
 429 +               , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
 430 +
 431 +       // Move X,Y to the top-left corner
 432 +       for (cOfst = 63; cOfst >= 0; cOfst--)
 433 +       {
 434 +               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 435 +                       , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst);        //RG_SSUSB_RX_EYE_XOFFSET
 436 +       }
 437 +       for (cOfst = 63; cOfst >= 0; cOfst--)
 438 +       {
 439 +               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 440 +                       , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
 441 +               U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
 442 +                       , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
 443 +
 444 +       }
 445 +       printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
 446 +               , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
 447 +               , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
 448 +
 449 +       printk(KERN_ERR "PI result: %d\n", _bPIResult);
 450 +       printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
 451 +       printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
 452 +
 453 +       return PHY_TRUE;
 454 +}
 455 +
 456 +//not used on SoC
 457 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
 458 +       return PHY_TRUE;
 459 +}
 460 +
 461 +//not used on SoC
 462 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
 463 +       return PHY_TRUE;
 464 +}
 465 +
 466 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
 467 +       PHY_INT32 i=0;
 468 +       //PHY_INT32 j=0;
 469 +       //PHY_INT8 u1SrCalVal = 0;
 470 +       //PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
 471 +       PHY_INT32 fgRet = 0;
 472 +       PHY_INT32 u4FmOut = 0;
 473 +       PHY_INT32 u4Tmp = 0;
 474 +       //PHY_INT32 temp;
 475 +
 476 +       // => RG_USB20_HSTX_SRCAL_EN = 1
 477 +       // enable HS TX SR calibration
 478 +       U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
 479 +               , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
 480 +       DRV_MSLEEP(1);
 481 +
 482 +       // => RG_FRCK_EN = 1
 483 +       // Enable free run clock
 484 +       U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
 485 +               , RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
 486 +
 487 +       // MT6290 HS signal quality patch
 488 +       // => RG_CYCLECNT = 400
 489 +       // Setting cyclecnt =400
 490 +       U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
 491 +               , RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
 492 +
 493 +       // => RG_FREQDET_EN = 1
 494 +       // Enable frequency meter
 495 +       U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
 496 +               , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
 497 +
 498 +       // wait for FM detection done, set 10ms timeout
 499 +       for(i=0; i<10; i++){
 500 +               // => u4FmOut = USB_FM_OUT
 501 +               // read FM_OUT
 502 +               u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
 503 +               printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
 504 +
 505 +               // check if FM detection done
 506 +               if (u4FmOut != 0)
 507 +               {
 508 +                       fgRet = 0;
 509 +                       printk("FM detection done! loop = %d\n", i);
 510 +
 511 +                       break;
 512 +               }
 513 +
 514 +               fgRet = 1;
 515 +               DRV_MSLEEP(1);
 516 +       }
 517 +       // => RG_FREQDET_EN = 0
 518 +       // disable frequency meter
 519 +       U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
 520 +               , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
 521 +
 522 +       // => RG_FRCK_EN = 0
 523 +       // disable free run clock
 524 +       U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
 525 +               , RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
 526 +
 527 +       // => RG_USB20_HSTX_SRCAL_EN = 0
 528 +       // disable HS TX SR calibration
 529 +       U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
 530 +               , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
 531 +       DRV_MSLEEP(1);
 532 +
 533 +       if(u4FmOut == 0){
 534 +               U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
 535 +                       , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
 536 +
 537 +               fgRet = 1;
 538 +       }
 539 +       else{
 540 +               // set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
 541 +               u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
 542 +               printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
 543 +               U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
 544 +                       , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
 545 +       }
 546 +       return fgRet;
 547 +}
 548 +
 549 +#endif
 550 --- /dev/null
 551 +++ b/drivers/usb/host/mtk-phy-7621.h
 552 @@ -0,0 +1,2871 @@
 553 +#ifdef CONFIG_PROJECT_7621
 554 +#ifndef __MTK_PHY_7621_H
 555 +#define __MTK_PHY_7621_H
 556 +
 557 +#define U2_SR_COEF_7621 28
 558 +
 559 +///////////////////////////////////////////////////////////////////////////////
 560 +
 561 +struct u2phy_reg {
 562 +       //0x0
 563 +       PHY_LE32 u2phyac0;
 564 +       PHY_LE32 u2phyac1;
 565 +       PHY_LE32 u2phyac2;
 566 +       PHY_LE32 reserve0;
 567 +       //0x10
 568 +       PHY_LE32 u2phyacr0;
 569 +       PHY_LE32 u2phyacr1;
 570 +       PHY_LE32 u2phyacr2;
 571 +       PHY_LE32 u2phyacr3;
 572 +       //0x20
 573 +       PHY_LE32 u2phyacr4;
 574 +       PHY_LE32 u2phyamon0;
 575 +       PHY_LE32 reserve1[2];
 576 +       //0x30~0x50
 577 +       PHY_LE32 reserve2[12];
 578 +       //0x60
 579 +       PHY_LE32 u2phydcr0;
 580 +       PHY_LE32 u2phydcr1;
 581 +       PHY_LE32 u2phydtm0;
 582 +       PHY_LE32 u2phydtm1;
 583 +       //0x70
 584 +       PHY_LE32 u2phydmon0;
 585 +       PHY_LE32 u2phydmon1;
 586 +       PHY_LE32 u2phydmon2;
 587 +       PHY_LE32 u2phydmon3;
 588 +       //0x80
 589 +       PHY_LE32 u2phybc12c;
 590 +       PHY_LE32 u2phybc12c1;
 591 +       PHY_LE32 reserve3[2];
 592 +       //0x90~0xe0
 593 +       PHY_LE32 reserve4[24];
 594 +       //0xf0
 595 +       PHY_LE32 reserve6[3];
 596 +       PHY_LE32 regfcom;
 597 +};
 598 +
 599 +//U3D_U2PHYAC0
 600 +#define RG_USB20_USBPLL_DIVEN                     (0x7<<28) //30:28
 601 +#define RG_USB20_USBPLL_CKCTRL                    (0x3<<26) //27:26
 602 +#define RG_USB20_USBPLL_PREDIV                    (0x3<<24) //25:24
 603 +#define RG_USB20_USBPLL_FORCE_ON                  (0x1<<23) //23:23
 604 +#define RG_USB20_USBPLL_FBDIV                     (0x7f<<16) //22:16
 605 +#define RG_USB20_REF_EN                           (0x1<<15) //15:15
 606 +#define RG_USB20_INTR_EN                          (0x1<<14) //14:14
 607 +#define RG_USB20_BG_TRIM                          (0xf<<8) //11:8
 608 +#define RG_USB20_BG_RBSEL                         (0x3<<6) //7:6
 609 +#define RG_USB20_BG_RASEL                         (0x3<<4) //5:4
 610 +#define RG_USB20_BGR_DIV                          (0x3<<2) //3:2
 611 +#define RG_SIFSLV_CHP_EN                          (0x1<<1) //1:1
 612 +#define RG_SIFSLV_BGR_EN                          (0x1<<0) //0:0
 613 +
 614 +//U3D_U2PHYAC1
 615 +#define RG_USB20_VRT_VREF_SEL                     (0x7<<28) //30:28
 616 +#define RG_USB20_TERM_VREF_SEL                    (0x7<<24) //26:24
 617 +#define RG_USB20_MPX_SEL                          (0xff<<16) //23:16
 618 +#define RG_USB20_MPX_OUT_SEL                      (0x3<<12) //13:12
 619 +#define RG_USB20_TX_PH_ROT_SEL                    (0x7<<8) //10:8
 620 +#define RG_USB20_USBPLL_ACCEN                     (0x1<<3) //3:3
 621 +#define RG_USB20_USBPLL_LF                        (0x1<<2) //2:2
 622 +#define RG_USB20_USBPLL_BR                        (0x1<<1) //1:1
 623 +#define RG_USB20_USBPLL_BP                        (0x1<<0) //0:0
 624 +
 625 +//U3D_U2PHYAC2
 626 +#define RG_SIFSLV_MAC_BANDGAP_EN                  (0x1<<17) //17:17
 627 +#define RG_SIFSLV_MAC_CHOPPER_EN                  (0x1<<16) //16:16
 628 +#define RG_USB20_CLKREF_REV                       (0xff<<0) //7:0
 629 +
 630 +//U3D_U2PHYACR0
 631 +#define RG_USB20_ICUSB_EN                         (0x1<<24) //24:24
 632 +#define RG_USB20_HSTX_SRCAL_EN                    (0x1<<23) //23:23
 633 +#define RG_USB20_HSTX_SRCTRL                      (0x7<<16) //18:16
 634 +#define RG_USB20_LS_CR                            (0x7<<12) //14:12
 635 +#define RG_USB20_FS_CR                            (0x7<<8) //10:8
 636 +#define RG_USB20_LS_SR                            (0x7<<4) //6:4
 637 +#define RG_USB20_FS_SR                            (0x7<<0) //2:0
 638 +
 639 +//U3D_U2PHYACR1
 640 +#define RG_USB20_INIT_SQ_EN_DG                    (0x3<<28) //29:28
 641 +#define RG_USB20_SQD                              (0x3<<24) //25:24
 642 +#define RG_USB20_HSTX_TMODE_SEL                   (0x3<<20) //21:20
 643 +#define RG_USB20_HSTX_TMODE_EN                    (0x1<<19) //19:19
 644 +#define RG_USB20_PHYD_MONEN                       (0x1<<18) //18:18
 645 +#define RG_USB20_INLPBK_EN                        (0x1<<17) //17:17
 646 +#define RG_USB20_CHIRP_EN                         (0x1<<16) //16:16
 647 +#define RG_USB20_DM_ABIST_SOURCE_EN               (0x1<<15) //15:15
 648 +#define RG_USB20_DM_ABIST_SELE                    (0xf<<8) //11:8
 649 +#define RG_USB20_DP_ABIST_SOURCE_EN               (0x1<<7) //7:7
 650 +#define RG_USB20_DP_ABIST_SELE                    (0xf<<0) //3:0
 651 +
 652 +//U3D_U2PHYACR2
 653 +#define RG_USB20_OTG_ABIST_SELE                   (0x7<<29) //31:29
 654 +#define RG_USB20_OTG_ABIST_EN                     (0x1<<28) //28:28
 655 +#define RG_USB20_OTG_VBUSCMP_EN                   (0x1<<27) //27:27
 656 +#define RG_USB20_OTG_VBUSTH                       (0x7<<24) //26:24
 657 +#define RG_USB20_DISC_FIT_EN                      (0x1<<22) //22:22
 658 +#define RG_USB20_DISCD                            (0x3<<20) //21:20
 659 +#define RG_USB20_DISCTH                           (0xf<<16) //19:16
 660 +#define RG_USB20_SQCAL_EN                         (0x1<<15) //15:15
 661 +#define RG_USB20_SQCAL                            (0xf<<8) //11:8
 662 +#define RG_USB20_SQTH                             (0xf<<0) //3:0
 663 +
 664 +//U3D_U2PHYACR3
 665 +#define RG_USB20_HSTX_DBIST                       (0xf<<28) //31:28
 666 +#define RG_USB20_HSTX_BIST_EN                     (0x1<<26) //26:26
 667 +#define RG_USB20_HSTX_I_EN_MODE                   (0x3<<24) //25:24
 668 +#define RG_USB20_HSRX_TMODE_EN                    (0x1<<23) //23:23
 669 +#define RG_USB20_HSRX_BIAS_EN_SEL                 (0x3<<20) //21:20
 670 +#define RG_USB20_USB11_TMODE_EN                   (0x1<<19) //19:19
 671 +#define RG_USB20_TMODE_FS_LS_TX_EN                (0x1<<18) //18:18
 672 +#define RG_USB20_TMODE_FS_LS_RCV_EN               (0x1<<17) //17:17
 673 +#define RG_USB20_TMODE_FS_LS_MODE                 (0x1<<16) //16:16
 674 +#define RG_USB20_HS_TERM_EN_MODE                  (0x3<<13) //14:13
 675 +#define RG_USB20_PUPD_BIST_EN                     (0x1<<12) //12:12
 676 +#define RG_USB20_EN_PU_DM                         (0x1<<11) //11:11
 677 +#define RG_USB20_EN_PD_DM                         (0x1<<10) //10:10
 678 +#define RG_USB20_EN_PU_DP                         (0x1<<9) //9:9
 679 +#define RG_USB20_EN_PD_DP                         (0x1<<8) //8:8
 680 +#define RG_USB20_PHY_REV                          (0xff<<0) //7:0
 681 +
 682 +//U3D_U2PHYACR4
 683 +#define RG_USB20_DP_100K_MODE                     (0x1<<18) //18:18
 684 +#define RG_USB20_DM_100K_EN                       (0x1<<17) //17:17
 685 +#define USB20_DP_100K_EN                          (0x1<<16) //16:16
 686 +#define USB20_GPIO_DM_I                           (0x1<<15) //15:15
 687 +#define USB20_GPIO_DP_I                           (0x1<<14) //14:14
 688 +#define USB20_GPIO_DM_OE                          (0x1<<13) //13:13
 689 +#define USB20_GPIO_DP_OE                          (0x1<<12) //12:12
 690 +#define RG_USB20_GPIO_CTL                         (0x1<<9) //9:9
 691 +#define USB20_GPIO_MODE                           (0x1<<8) //8:8
 692 +#define RG_USB20_TX_BIAS_EN                       (0x1<<5) //5:5
 693 +#define RG_USB20_TX_VCMPDN_EN                     (0x1<<4) //4:4
 694 +#define RG_USB20_HS_SQ_EN_MODE                    (0x3<<2) //3:2
 695 +#define RG_USB20_HS_RCV_EN_MODE                   (0x3<<0) //1:0
 696 +
 697 +//U3D_U2PHYAMON0
 698 +#define RGO_USB20_GPIO_DM_O                       (0x1<<1) //1:1
 699 +#define RGO_USB20_GPIO_DP_O                       (0x1<<0) //0:0
 700 +
 701 +//U3D_U2PHYDCR0
 702 +#define RG_USB20_CDR_TST                          (0x3<<30) //31:30
 703 +#define RG_USB20_GATED_ENB                        (0x1<<29) //29:29
 704 +#define RG_USB20_TESTMODE                         (0x3<<26) //27:26
 705 +#define RG_USB20_PLL_STABLE                       (0x1<<25) //25:25
 706 +#define RG_USB20_PLL_FORCE_ON                     (0x1<<24) //24:24
 707 +#define RG_USB20_PHYD_RESERVE                     (0xffff<<8) //23:8
 708 +#define RG_USB20_EBTHRLD                          (0x1<<7) //7:7
 709 +#define RG_USB20_EARLY_HSTX_I                     (0x1<<6) //6:6
 710 +#define RG_USB20_TX_TST                           (0x1<<5) //5:5
 711 +#define RG_USB20_NEGEDGE_ENB                      (0x1<<4) //4:4
 712 +#define RG_USB20_CDR_FILT                         (0xf<<0) //3:0
 713 +
 714 +//U3D_U2PHYDCR1
 715 +#define RG_USB20_PROBE_SEL                        (0xff<<24) //31:24
 716 +#define RG_USB20_DRVVBUS                          (0x1<<23) //23:23
 717 +#define RG_DEBUG_EN                               (0x1<<22) //22:22
 718 +#define RG_USB20_OTG_PROBE                        (0x3<<20) //21:20
 719 +#define RG_USB20_SW_PLLMODE                       (0x3<<18) //19:18
 720 +#define RG_USB20_BERTH                            (0x3<<16) //17:16
 721 +#define RG_USB20_LBMODE                           (0x3<<13) //14:13
 722 +#define RG_USB20_FORCE_TAP                        (0x1<<12) //12:12
 723 +#define RG_USB20_TAPSEL                           (0xfff<<0) //11:0
 724 +
 725 +//U3D_U2PHYDTM0
 726 +#define RG_UART_MODE                              (0x3<<30) //31:30
 727 +#define FORCE_UART_I                              (0x1<<29) //29:29
 728 +#define FORCE_UART_BIAS_EN                        (0x1<<28) //28:28
 729 +#define FORCE_UART_TX_OE                          (0x1<<27) //27:27
 730 +#define FORCE_UART_EN                             (0x1<<26) //26:26
 731 +#define FORCE_USB_CLKEN                           (0x1<<25) //25:25
 732 +#define FORCE_DRVVBUS                             (0x1<<24) //24:24
 733 +#define FORCE_DATAIN                              (0x1<<23) //23:23
 734 +#define FORCE_TXVALID                             (0x1<<22) //22:22
 735 +#define FORCE_DM_PULLDOWN                         (0x1<<21) //21:21
 736 +#define FORCE_DP_PULLDOWN                         (0x1<<20) //20:20
 737 +#define FORCE_XCVRSEL                             (0x1<<19) //19:19
 738 +#define FORCE_SUSPENDM                            (0x1<<18) //18:18
 739 +#define FORCE_TERMSEL                             (0x1<<17) //17:17
 740 +#define FORCE_OPMODE                              (0x1<<16) //16:16
 741 +#define UTMI_MUXSEL                               (0x1<<15) //15:15
 742 +#define RG_RESET                                  (0x1<<14) //14:14
 743 +#define RG_DATAIN                                 (0xf<<10) //13:10
 744 +#define RG_TXVALIDH                               (0x1<<9) //9:9
 745 +#define RG_TXVALID                                (0x1<<8) //8:8
 746 +#define RG_DMPULLDOWN                             (0x1<<7) //7:7
 747 +#define RG_DPPULLDOWN                             (0x1<<6) //6:6
 748 +#define RG_XCVRSEL                                (0x3<<4) //5:4
 749 +#define RG_SUSPENDM                               (0x1<<3) //3:3
 750 +#define RG_TERMSEL                                (0x1<<2) //2:2
 751 +#define RG_OPMODE                                 (0x3<<0) //1:0
 752 +
 753 +//U3D_U2PHYDTM1
 754 +#define RG_USB20_PRBS7_EN                         (0x1<<31) //31:31
 755 +#define RG_USB20_PRBS7_BITCNT                     (0x3f<<24) //29:24
 756 +#define RG_USB20_CLK48M_EN                        (0x1<<23) //23:23
 757 +#define RG_USB20_CLK60M_EN                        (0x1<<22) //22:22
 758 +#define RG_UART_I                                 (0x1<<19) //19:19
 759 +#define RG_UART_BIAS_EN                           (0x1<<18) //18:18
 760 +#define RG_UART_TX_OE                             (0x1<<17) //17:17
 761 +#define RG_UART_EN                                (0x1<<16) //16:16
 762 +#define FORCE_VBUSVALID                           (0x1<<13) //13:13
 763 +#define FORCE_SESSEND                             (0x1<<12) //12:12
 764 +#define FORCE_BVALID                              (0x1<<11) //11:11
 765 +#define FORCE_AVALID                              (0x1<<10) //10:10
 766 +#define FORCE_IDDIG                               (0x1<<9) //9:9
 767 +#define FORCE_IDPULLUP                            (0x1<<8) //8:8
 768 +#define RG_VBUSVALID                              (0x1<<5) //5:5
 769 +#define RG_SESSEND                                (0x1<<4) //4:4
 770 +#define RG_BVALID                                 (0x1<<3) //3:3
 771 +#define RG_AVALID                                 (0x1<<2) //2:2
 772 +#define RG_IDDIG                                  (0x1<<1) //1:1
 773 +#define RG_IDPULLUP                               (0x1<<0) //0:0
 774 +
 775 +//U3D_U2PHYDMON0
 776 +#define RG_USB20_PRBS7_BERTH                      (0xff<<0) //7:0
 777 +
 778 +//U3D_U2PHYDMON1
 779 +#define USB20_UART_O                              (0x1<<31) //31:31
 780 +#define RGO_USB20_LB_PASS                         (0x1<<30) //30:30
 781 +#define RGO_USB20_LB_DONE                         (0x1<<29) //29:29
 782 +#define AD_USB20_BVALID                           (0x1<<28) //28:28
 783 +#define USB20_IDDIG                               (0x1<<27) //27:27
 784 +#define AD_USB20_VBUSVALID                        (0x1<<26) //26:26
 785 +#define AD_USB20_SESSEND                          (0x1<<25) //25:25
 786 +#define AD_USB20_AVALID                           (0x1<<24) //24:24
 787 +#define USB20_LINE_STATE                          (0x3<<22) //23:22
 788 +#define USB20_HST_DISCON                          (0x1<<21) //21:21
 789 +#define USB20_TX_READY                            (0x1<<20) //20:20
 790 +#define USB20_RX_ERROR                            (0x1<<19) //19:19
 791 +#define USB20_RX_ACTIVE                           (0x1<<18) //18:18
 792 +#define USB20_RX_VALIDH                           (0x1<<17) //17:17
 793 +#define USB20_RX_VALID                            (0x1<<16) //16:16
 794 +#define USB20_DATA_OUT                            (0xffff<<0) //15:0
 795 +
 796 +//U3D_U2PHYDMON2
 797 +#define RGO_TXVALID_CNT                           (0xff<<24) //31:24
 798 +#define RGO_RXACTIVE_CNT                          (0xff<<16) //23:16
 799 +#define RGO_USB20_LB_BERCNT                       (0xff<<8) //15:8
 800 +#define USB20_PROBE_OUT                           (0xff<<0) //7:0
 801 +
 802 +//U3D_U2PHYDMON3
 803 +#define RGO_USB20_PRBS7_ERRCNT                    (0xffff<<16) //31:16
 804 +#define RGO_USB20_PRBS7_DONE                      (0x1<<3) //3:3
 805 +#define RGO_USB20_PRBS7_LOCK                      (0x1<<2) //2:2
 806 +#define RGO_USB20_PRBS7_PASS                      (0x1<<1) //1:1
 807 +#define RGO_USB20_PRBS7_PASSTH                    (0x1<<0) //0:0
 808 +
 809 +//U3D_U2PHYBC12C
 810 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT                (0xf<<28) //31:28
 811 +#define RG_SIFSLV_CHGDT_CTRL_CNT                  (0xf<<24) //27:24
 812 +#define RG_SIFSLV_CHGDT_FORCE_MODE                (0x1<<16) //16:16
 813 +#define RG_CHGDT_ISRC_LEV                         (0x3<<14) //15:14
 814 +#define RG_CHGDT_VDATSRC                          (0x1<<13) //13:13
 815 +#define RG_CHGDT_BGVREF_SEL                       (0x7<<10) //12:10
 816 +#define RG_CHGDT_RDVREF_SEL                       (0x3<<8) //9:8
 817 +#define RG_CHGDT_ISRC_DP                          (0x1<<7) //7:7
 818 +#define RG_SIFSLV_CHGDT_OPOUT_DM                  (0x1<<6) //6:6
 819 +#define RG_CHGDT_VDAT_DM                          (0x1<<5) //5:5
 820 +#define RG_CHGDT_OPOUT_DP                         (0x1<<4) //4:4
 821 +#define RG_SIFSLV_CHGDT_VDAT_DP                   (0x1<<3) //3:3
 822 +#define RG_SIFSLV_CHGDT_COMP_EN                   (0x1<<2) //2:2
 823 +#define RG_SIFSLV_CHGDT_OPDRV_EN                  (0x1<<1) //1:1
 824 +#define RG_CHGDT_EN                               (0x1<<0) //0:0
 825 +
 826 +//U3D_U2PHYBC12C1
 827 +#define RG_CHGDT_REV                              (0xff<<0) //7:0
 828 +
 829 +//U3D_REGFCOM
 830 +#define RG_PAGE                                   (0xff<<24) //31:24
 831 +#define I2C_MODE                                  (0x1<<16) //16:16
 832 +
 833 +
 834 +/* OFFSET  */
 835 +
 836 +//U3D_U2PHYAC0
 837 +#define RG_USB20_USBPLL_DIVEN_OFST                (28)
 838 +#define RG_USB20_USBPLL_CKCTRL_OFST               (26)
 839 +#define RG_USB20_USBPLL_PREDIV_OFST               (24)
 840 +#define RG_USB20_USBPLL_FORCE_ON_OFST             (23)
 841 +#define RG_USB20_USBPLL_FBDIV_OFST                (16)
 842 +#define RG_USB20_REF_EN_OFST                      (15)
 843 +#define RG_USB20_INTR_EN_OFST                     (14)
 844 +#define RG_USB20_BG_TRIM_OFST                     (8)
 845 +#define RG_USB20_BG_RBSEL_OFST                    (6)
 846 +#define RG_USB20_BG_RASEL_OFST                    (4)
 847 +#define RG_USB20_BGR_DIV_OFST                     (2)
 848 +#define RG_SIFSLV_CHP_EN_OFST                     (1)
 849 +#define RG_SIFSLV_BGR_EN_OFST                     (0)
 850 +
 851 +//U3D_U2PHYAC1
 852 +#define RG_USB20_VRT_VREF_SEL_OFST                (28)
 853 +#define RG_USB20_TERM_VREF_SEL_OFST               (24)
 854 +#define RG_USB20_MPX_SEL_OFST                     (16)
 855 +#define RG_USB20_MPX_OUT_SEL_OFST                 (12)
 856 +#define RG_USB20_TX_PH_ROT_SEL_OFST               (8)
 857 +#define RG_USB20_USBPLL_ACCEN_OFST                (3)
 858 +#define RG_USB20_USBPLL_LF_OFST                   (2)
 859 +#define RG_USB20_USBPLL_BR_OFST                   (1)
 860 +#define RG_USB20_USBPLL_BP_OFST                   (0)
 861 +
 862 +//U3D_U2PHYAC2
 863 +#define RG_SIFSLV_MAC_BANDGAP_EN_OFST             (17)
 864 +#define RG_SIFSLV_MAC_CHOPPER_EN_OFST             (16)
 865 +#define RG_USB20_CLKREF_REV_OFST                  (0)
 866 +
 867 +//U3D_U2PHYACR0
 868 +#define RG_USB20_ICUSB_EN_OFST                    (24)
 869 +#define RG_USB20_HSTX_SRCAL_EN_OFST               (23)
 870 +#define RG_USB20_HSTX_SRCTRL_OFST                 (16)
 871 +#define RG_USB20_LS_CR_OFST                       (12)
 872 +#define RG_USB20_FS_CR_OFST                       (8)
 873 +#define RG_USB20_LS_SR_OFST                       (4)
 874 +#define RG_USB20_FS_SR_OFST                       (0)
 875 +
 876 +//U3D_U2PHYACR1
 877 +#define RG_USB20_INIT_SQ_EN_DG_OFST               (28)
 878 +#define RG_USB20_SQD_OFST                         (24)
 879 +#define RG_USB20_HSTX_TMODE_SEL_OFST              (20)
 880 +#define RG_USB20_HSTX_TMODE_EN_OFST               (19)
 881 +#define RG_USB20_PHYD_MONEN_OFST                  (18)
 882 +#define RG_USB20_INLPBK_EN_OFST                   (17)
 883 +#define RG_USB20_CHIRP_EN_OFST                    (16)
 884 +#define RG_USB20_DM_ABIST_SOURCE_EN_OFST          (15)
 885 +#define RG_USB20_DM_ABIST_SELE_OFST               (8)
 886 +#define RG_USB20_DP_ABIST_SOURCE_EN_OFST          (7)
 887 +#define RG_USB20_DP_ABIST_SELE_OFST               (0)
 888 +
 889 +//U3D_U2PHYACR2
 890 +#define RG_USB20_OTG_ABIST_SELE_OFST              (29)
 891 +#define RG_USB20_OTG_ABIST_EN_OFST                (28)
 892 +#define RG_USB20_OTG_VBUSCMP_EN_OFST              (27)
 893 +#define RG_USB20_OTG_VBUSTH_OFST                  (24)
 894 +#define RG_USB20_DISC_FIT_EN_OFST                 (22)
 895 +#define RG_USB20_DISCD_OFST                       (20)
 896 +#define RG_USB20_DISCTH_OFST                      (16)
 897 +#define RG_USB20_SQCAL_EN_OFST                    (15)
 898 +#define RG_USB20_SQCAL_OFST                       (8)
 899 +#define RG_USB20_SQTH_OFST                        (0)
 900 +
 901 +//U3D_U2PHYACR3
 902 +#define RG_USB20_HSTX_DBIST_OFST                  (28)
 903 +#define RG_USB20_HSTX_BIST_EN_OFST                (26)
 904 +#define RG_USB20_HSTX_I_EN_MODE_OFST              (24)
 905 +#define RG_USB20_HSRX_TMODE_EN_OFST               (23)
 906 +#define RG_USB20_HSRX_BIAS_EN_SEL_OFST            (20)
 907 +#define RG_USB20_USB11_TMODE_EN_OFST              (19)
 908 +#define RG_USB20_TMODE_FS_LS_TX_EN_OFST           (18)
 909 +#define RG_USB20_TMODE_FS_LS_RCV_EN_OFST          (17)
 910 +#define RG_USB20_TMODE_FS_LS_MODE_OFST            (16)
 911 +#define RG_USB20_HS_TERM_EN_MODE_OFST             (13)
 912 +#define RG_USB20_PUPD_BIST_EN_OFST                (12)
 913 +#define RG_USB20_EN_PU_DM_OFST                    (11)
 914 +#define RG_USB20_EN_PD_DM_OFST                    (10)
 915 +#define RG_USB20_EN_PU_DP_OFST                    (9)
 916 +#define RG_USB20_EN_PD_DP_OFST                    (8)
 917 +#define RG_USB20_PHY_REV_OFST                     (0)
 918 +
 919 +//U3D_U2PHYACR4
 920 +#define RG_USB20_DP_100K_MODE_OFST                (18)
 921 +#define RG_USB20_DM_100K_EN_OFST                  (17)
 922 +#define USB20_DP_100K_EN_OFST                     (16)
 923 +#define USB20_GPIO_DM_I_OFST                      (15)
 924 +#define USB20_GPIO_DP_I_OFST                      (14)
 925 +#define USB20_GPIO_DM_OE_OFST                     (13)
 926 +#define USB20_GPIO_DP_OE_OFST                     (12)
 927 +#define RG_USB20_GPIO_CTL_OFST                    (9)
 928 +#define USB20_GPIO_MODE_OFST                      (8)
 929 +#define RG_USB20_TX_BIAS_EN_OFST                  (5)
 930 +#define RG_USB20_TX_VCMPDN_EN_OFST                (4)
 931 +#define RG_USB20_HS_SQ_EN_MODE_OFST               (2)
 932 +#define RG_USB20_HS_RCV_EN_MODE_OFST              (0)
 933 +
 934 +//U3D_U2PHYAMON0
 935 +#define RGO_USB20_GPIO_DM_O_OFST                  (1)
 936 +#define RGO_USB20_GPIO_DP_O_OFST                  (0)
 937 +
 938 +//U3D_U2PHYDCR0
 939 +#define RG_USB20_CDR_TST_OFST                     (30)
 940 +#define RG_USB20_GATED_ENB_OFST                   (29)
 941 +#define RG_USB20_TESTMODE_OFST                    (26)
 942 +#define RG_USB20_PLL_STABLE_OFST                  (25)
 943 +#define RG_USB20_PLL_FORCE_ON_OFST                (24)
 944 +#define RG_USB20_PHYD_RESERVE_OFST                (8)
 945 +#define RG_USB20_EBTHRLD_OFST                     (7)
 946 +#define RG_USB20_EARLY_HSTX_I_OFST                (6)
 947 +#define RG_USB20_TX_TST_OFST                      (5)
 948 +#define RG_USB20_NEGEDGE_ENB_OFST                 (4)
 949 +#define RG_USB20_CDR_FILT_OFST                    (0)
 950 +
 951 +//U3D_U2PHYDCR1
 952 +#define RG_USB20_PROBE_SEL_OFST                   (24)
 953 +#define RG_USB20_DRVVBUS_OFST                     (23)
 954 +#define RG_DEBUG_EN_OFST                          (22)
 955 +#define RG_USB20_OTG_PROBE_OFST                   (20)
 956 +#define RG_USB20_SW_PLLMODE_OFST                  (18)
 957 +#define RG_USB20_BERTH_OFST                       (16)
 958 +#define RG_USB20_LBMODE_OFST                      (13)
 959 +#define RG_USB20_FORCE_TAP_OFST                   (12)
 960 +#define RG_USB20_TAPSEL_OFST                      (0)
 961 +
 962 +//U3D_U2PHYDTM0
 963 +#define RG_UART_MODE_OFST                         (30)
 964 +#define FORCE_UART_I_OFST                         (29)
 965 +#define FORCE_UART_BIAS_EN_OFST                   (28)
 966 +#define FORCE_UART_TX_OE_OFST                     (27)
 967 +#define FORCE_UART_EN_OFST                        (26)
 968 +#define FORCE_USB_CLKEN_OFST                      (25)
 969 +#define FORCE_DRVVBUS_OFST                        (24)
 970 +#define FORCE_DATAIN_OFST                         (23)
 971 +#define FORCE_TXVALID_OFST                        (22)
 972 +#define FORCE_DM_PULLDOWN_OFST                    (21)
 973 +#define FORCE_DP_PULLDOWN_OFST                    (20)
 974 +#define FORCE_XCVRSEL_OFST                        (19)
 975 +#define FORCE_SUSPENDM_OFST                       (18)
 976 +#define FORCE_TERMSEL_OFST                        (17)
 977 +#define FORCE_OPMODE_OFST                         (16)
 978 +#define UTMI_MUXSEL_OFST                          (15)
 979 +#define RG_RESET_OFST                             (14)
 980 +#define RG_DATAIN_OFST                            (10)
 981 +#define RG_TXVALIDH_OFST                          (9)
 982 +#define RG_TXVALID_OFST                           (8)
 983 +#define RG_DMPULLDOWN_OFST                        (7)
 984 +#define RG_DPPULLDOWN_OFST                        (6)
 985 +#define RG_XCVRSEL_OFST                           (4)
 986 +#define RG_SUSPENDM_OFST                          (3)
 987 +#define RG_TERMSEL_OFST                           (2)
 988 +#define RG_OPMODE_OFST                            (0)
 989 +
 990 +//U3D_U2PHYDTM1
 991 +#define RG_USB20_PRBS7_EN_OFST                    (31)
 992 +#define RG_USB20_PRBS7_BITCNT_OFST                (24)
 993 +#define RG_USB20_CLK48M_EN_OFST                   (23)
 994 +#define RG_USB20_CLK60M_EN_OFST                   (22)
 995 +#define RG_UART_I_OFST                            (19)
 996 +#define RG_UART_BIAS_EN_OFST                      (18)
 997 +#define RG_UART_TX_OE_OFST                        (17)
 998 +#define RG_UART_EN_OFST                           (16)
 999 +#define FORCE_VBUSVALID_OFST                      (13)
1000 +#define FORCE_SESSEND_OFST                        (12)
1001 +#define FORCE_BVALID_OFST                         (11)
1002 +#define FORCE_AVALID_OFST                         (10)
1003 +#define FORCE_IDDIG_OFST                          (9)
1004 +#define FORCE_IDPULLUP_OFST                       (8)
1005 +#define RG_VBUSVALID_OFST                         (5)
1006 +#define RG_SESSEND_OFST                           (4)
1007 +#define RG_BVALID_OFST                            (3)
1008 +#define RG_AVALID_OFST                            (2)
1009 +#define RG_IDDIG_OFST                             (1)
1010 +#define RG_IDPULLUP_OFST                          (0)
1011 +
1012 +//U3D_U2PHYDMON0
1013 +#define RG_USB20_PRBS7_BERTH_OFST                 (0)
1014 +
1015 +//U3D_U2PHYDMON1
1016 +#define USB20_UART_O_OFST                         (31)
1017 +#define RGO_USB20_LB_PASS_OFST                    (30)
1018 +#define RGO_USB20_LB_DONE_OFST                    (29)
1019 +#define AD_USB20_BVALID_OFST                      (28)
1020 +#define USB20_IDDIG_OFST                          (27)
1021 +#define AD_USB20_VBUSVALID_OFST                   (26)
1022 +#define AD_USB20_SESSEND_OFST                     (25)
1023 +#define AD_USB20_AVALID_OFST                      (24)
1024 +#define USB20_LINE_STATE_OFST                     (22)
1025 +#define USB20_HST_DISCON_OFST                     (21)
1026 +#define USB20_TX_READY_OFST                       (20)
1027 +#define USB20_RX_ERROR_OFST                       (19)
1028 +#define USB20_RX_ACTIVE_OFST                      (18)
1029 +#define USB20_RX_VALIDH_OFST                      (17)
1030 +#define USB20_RX_VALID_OFST                       (16)
1031 +#define USB20_DATA_OUT_OFST                       (0)
1032 +
1033 +//U3D_U2PHYDMON2
1034 +#define RGO_TXVALID_CNT_OFST                      (24)
1035 +#define RGO_RXACTIVE_CNT_OFST                     (16)
1036 +#define RGO_USB20_LB_BERCNT_OFST                  (8)
1037 +#define USB20_PROBE_OUT_OFST                      (0)
1038 +
1039 +//U3D_U2PHYDMON3
1040 +#define RGO_USB20_PRBS7_ERRCNT_OFST               (16)
1041 +#define RGO_USB20_PRBS7_DONE_OFST                 (3)
1042 +#define RGO_USB20_PRBS7_LOCK_OFST                 (2)
1043 +#define RGO_USB20_PRBS7_PASS_OFST                 (1)
1044 +#define RGO_USB20_PRBS7_PASSTH_OFST               (0)
1045 +
1046 +//U3D_U2PHYBC12C
1047 +#define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST           (28)
1048 +#define RG_SIFSLV_CHGDT_CTRL_CNT_OFST             (24)
1049 +#define RG_SIFSLV_CHGDT_FORCE_MODE_OFST           (16)
1050 +#define RG_CHGDT_ISRC_LEV_OFST                    (14)
1051 +#define RG_CHGDT_VDATSRC_OFST                     (13)
1052 +#define RG_CHGDT_BGVREF_SEL_OFST                  (10)
1053 +#define RG_CHGDT_RDVREF_SEL_OFST                  (8)
1054 +#define RG_CHGDT_ISRC_DP_OFST                     (7)
1055 +#define RG_SIFSLV_CHGDT_OPOUT_DM_OFST             (6)
1056 +#define RG_CHGDT_VDAT_DM_OFST                     (5)
1057 +#define RG_CHGDT_OPOUT_DP_OFST                    (4)
1058 +#define RG_SIFSLV_CHGDT_VDAT_DP_OFST              (3)
1059 +#define RG_SIFSLV_CHGDT_COMP_EN_OFST              (2)
1060 +#define RG_SIFSLV_CHGDT_OPDRV_EN_OFST             (1)
1061 +#define RG_CHGDT_EN_OFST                          (0)
1062 +
1063 +//U3D_U2PHYBC12C1
1064 +#define RG_CHGDT_REV_OFST                         (0)
1065 +
1066 +//U3D_REGFCOM
1067 +#define RG_PAGE_OFST                              (24)
1068 +#define I2C_MODE_OFST                             (16)
1069 +
1070 +
1071 +///////////////////////////////////////////////////////////////////////////////
1072 +
1073 +struct u3phya_reg {
1074 +       //0x0
1075 +       PHY_LE32 reg0;
1076 +       PHY_LE32 reg1;
1077 +       PHY_LE32 reg2;
1078 +       PHY_LE32 reg3;
1079 +       //0x10
1080 +       PHY_LE32 reg4;
1081 +       PHY_LE32 reg5;
1082 +       PHY_LE32 reg6;
1083 +       PHY_LE32 reg7;
1084 +       //0x20
1085 +       PHY_LE32 reg8;
1086 +       PHY_LE32 reg9;
1087 +       PHY_LE32 rega;
1088 +       PHY_LE32 regb;
1089 +       //0x30
1090 +       PHY_LE32 regc;
1091 +       PHY_LE32 regd;
1092 +       PHY_LE32 rege;
1093 +};
1094 +
1095 +//U3D_reg0
1096 +#define RG_SSUSB_BGR_EN                           (0x1<<31) //31:31
1097 +#define RG_SSUSB_CHPEN                            (0x1<<30) //30:30
1098 +#define RG_SSUSB_BG_DIV                           (0x3<<28) //29:28
1099 +#define RG_SSUSB_INTR_EN                          (0x1<<26) //26:26
1100 +#define RG_SSUSB_MPX_OUT_SEL                      (0x3<<24) //25:24
1101 +#define RG_SSUSB_MPX_SEL                          (0xff<<16) //23:16
1102 +#define RG_SSUSB_REF_EN                           (0x1<<15) //15:15
1103 +#define RG_SSUSB_VRT_VREF_SEL                     (0xf<<11) //14:11
1104 +#define RG_SSUSB_BG_RASEL                         (0x3<<9) //10:9
1105 +#define RG_SSUSB_BG_RBSEL                         (0x3<<7) //8:7
1106 +#define RG_SSUSB_BG_MONEN                         (0x1<<6) //6:6
1107 +#define RG_PCIE_CLKDRV_OFFSET                     (0x3<<0) //1:0
1108 +
1109 +//U3D_reg1
1110 +#define RG_PCIE_CLKDRV_SLEW                       (0x3<<30) //31:30
1111 +#define RG_PCIE_CLKDRV_AMP                        (0x7<<27) //29:27
1112 +#define RG_SSUSB_XTAL_TST_A2DCK_EN                (0x1<<26) //26:26
1113 +#define RG_SSUSB_XTAL_MON_EN                      (0x1<<25) //25:25
1114 +#define RG_SSUSB_XTAL_HYS                         (0x1<<24) //24:24
1115 +#define RG_SSUSB_XTAL_TOP_RESERVE                 (0xffff<<8) //23:8
1116 +#define RG_SSUSB_SYSPLL_RESERVE                   (0xf<<4) //7:4
1117 +#define RG_SSUSB_SYSPLL_FBSEL                     (0x3<<2) //3:2
1118 +#define RG_SSUSB_SYSPLL_PREDIV                    (0x3<<0) //1:0
1119 +
1120 +//U3D_reg2
1121 +#define RG_SSUSB_SYSPLL_LF                        (0x1<<31) //31:31
1122 +#define RG_SSUSB_SYSPLL_FBDIV                     (0x7f<<24) //30:24
1123 +#define RG_SSUSB_SYSPLL_POSDIV                    (0x3<<22) //23:22
1124 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL               (0x1<<21) //21:21
1125 +#define RG_SSUSB_SYSPLL_BLP                       (0x1<<20) //20:20
1126 +#define RG_SSUSB_SYSPLL_BP                        (0x1<<19) //19:19
1127 +#define RG_SSUSB_SYSPLL_BR                        (0x1<<18) //18:18
1128 +#define RG_SSUSB_SYSPLL_BC                        (0x1<<17) //17:17
1129 +#define RG_SSUSB_SYSPLL_DIVEN                     (0x7<<14) //16:14
1130 +#define RG_SSUSB_SYSPLL_FPEN                      (0x1<<13) //13:13
1131 +#define RG_SSUSB_SYSPLL_MONCK_EN                  (0x1<<12) //12:12
1132 +#define RG_SSUSB_SYSPLL_MONVC_EN                  (0x1<<11) //11:11
1133 +#define RG_SSUSB_SYSPLL_MONREF_EN                 (0x1<<10) //10:10
1134 +#define RG_SSUSB_SYSPLL_VOD_EN                    (0x1<<9) //9:9
1135 +#define RG_SSUSB_SYSPLL_CK_SEL                    (0x1<<8) //8:8
1136 +
1137 +//U3D_reg3
1138 +#define RG_SSUSB_SYSPLL_TOP_RESERVE               (0xffff<<16) //31:16
1139 +
1140 +//U3D_reg4
1141 +#define RG_SSUSB_SYSPLL_PCW_NCPO                  (0x7fffffff<<1) //31:1
1142 +
1143 +//U3D_reg5
1144 +#define RG_SSUSB_SYSPLL_DDS_PI_C                  (0x7<<29) //31:29
1145 +#define RG_SSUSB_SYSPLL_DDS_HF_EN                 (0x1<<28) //28:28
1146 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2               (0x1<<27) //27:27
1147 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2              (0x1<<26) //26:26
1148 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN              (0x1<<25) //25:25
1149 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL            (0x1<<24) //24:24
1150 +#define RG_SSUSB_SYSPLL_DDS_MONEN                 (0x1<<23) //23:23
1151 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN                (0x1<<22) //22:22
1152 +#define RG_SSUSB_SYSPLL_CLK_PH_INV                (0x1<<21) //21:21
1153 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT               (0x1<<20) //20:20
1154 +#define RG_SSUSB_SYSPLL_DDS_DMY                   (0xffff<<0) //15:0
1155 +
1156 +//U3D_reg6
1157 +#define RG_SSUSB_TX250MCK_INVB                    (0x1<<31) //31:31
1158 +#define RG_SSUSB_IDRV_ITAILOP_EN                  (0x1<<30) //30:30
1159 +#define RG_SSUSB_IDRV_CALIB                       (0x3f<<24) //29:24
1160 +#define RG_SSUSB_TX_R50_FON                       (0x1<<23) //23:23
1161 +#define RG_SSUSB_TX_SR                            (0x7<<20) //22:20
1162 +#define RG_SSUSB_TX_EIDLE_CM                      (0xf<<16) //19:16
1163 +#define RG_SSUSB_RXDET_RSEL                       (0x3<<14) //15:14
1164 +#define RG_SSUSB_RXDET_VTHSEL                     (0x3<<12) //13:12
1165 +#define RG_SSUSB_CKMON_EN                         (0x1<<11) //11:11
1166 +#define RG_SSUSB_CKMON_SEL                        (0x7<<8) //10:8
1167 +#define RG_SSUSB_TX_VLMON_EN                      (0x1<<7) //7:7
1168 +#define RG_SSUSB_TX_VLMON_SEL                     (0x1<<6) //6:6
1169 +#define RG_SSUSB_RXLBTX_EN                        (0x1<<5) //5:5
1170 +#define RG_SSUSB_TXLBRX_EN                        (0x1<<4) //4:4
1171 +
1172 +//U3D_reg7
1173 +#define RG_SSUSB_RESERVE                          (0xfffff<<12) //31:12
1174 +#define RG_SSUSB_PLL_CKCTRL                       (0x3<<10) //11:10
1175 +#define RG_SSUSB_PLL_POSDIV                       (0x3<<8) //9:8
1176 +#define RG_SSUSB_PLL_AUTOK_LOAD                   (0x1<<7) //7:7
1177 +#define RG_SSUSB_PLL_LOAD_RSTB                    (0x1<<6) //6:6
1178 +#define RG_SSUSB_PLL_EP_EN                        (0x1<<5) //5:5
1179 +#define RG_SSUSB_PLL_VOD_EN                       (0x1<<4) //4:4
1180 +#define RG_SSUSB_PLL_V11_EN                       (0x1<<3) //3:3
1181 +#define RG_SSUSB_PLL_MONREF_EN                    (0x1<<2) //2:2
1182 +#define RG_SSUSB_PLL_MONCK_EN                     (0x1<<1) //1:1
1183 +#define RG_SSUSB_PLL_MONVC_EN                     (0x1<<0) //0:0
1184 +
1185 +//U3D_reg8
1186 +#define RG_SSUSB_PLL_RESERVE                      (0xffff<<0) //15:0
1187 +
1188 +//U3D_reg9
1189 +#define RG_SSUSB_PLL_DDS_DMY                      (0xffff<<16) //31:16
1190 +#define RG_SSUSB_PLL_SSC_PRD                      (0xffff<<0) //15:0
1191 +
1192 +//U3D_regA
1193 +#define RG_SSUSB_PLL_SSC_PHASE_INI                (0x1<<31) //31:31
1194 +#define RG_SSUSB_PLL_SSC_TRI_EN                   (0x1<<30) //30:30
1195 +#define RG_SSUSB_PLL_CLK_PH_INV                   (0x1<<29) //29:29
1196 +#define RG_SSUSB_PLL_DDS_LPF_EN                   (0x1<<28) //28:28
1197 +#define RG_SSUSB_PLL_DDS_VADJ                     (0x7<<21) //23:21
1198 +#define RG_SSUSB_PLL_DDS_MONEN                    (0x1<<20) //20:20
1199 +#define RG_SSUSB_PLL_DDS_PS_VADJ                  (0x7<<17) //19:17
1200 +#define RG_SSUSB_PLL_DDS_SEL_EXT                  (0x1<<16) //16:16
1201 +#define RG_SSUSB_CDR_PD_DIV_BYPASS                (0x1<<15) //15:15
1202 +#define RG_SSUSB_CDR_PD_DIV_SEL                   (0x1<<14) //14:14
1203 +#define RG_SSUSB_CDR_CPBIAS_SEL                   (0x1<<13) //13:13
1204 +#define RG_SSUSB_CDR_OSCDET_EN                    (0x1<<12) //12:12
1205 +#define RG_SSUSB_CDR_MONMUX                       (0x1<<11) //11:11
1206 +#define RG_SSUSB_CDR_CKCTRL                       (0x3<<9) //10:9
1207 +#define RG_SSUSB_CDR_ACCEN                        (0x1<<8) //8:8
1208 +#define RG_SSUSB_CDR_BYPASS                       (0x3<<6) //7:6
1209 +#define RG_SSUSB_CDR_PI_SLEW                      (0x3<<4) //5:4
1210 +#define RG_SSUSB_CDR_EPEN                         (0x1<<3) //3:3
1211 +#define RG_SSUSB_CDR_AUTOK_LOAD                   (0x1<<2) //2:2
1212 +#define RG_SSUSB_CDR_LOAD_RSTB                    (0x1<<1) //1:1
1213 +#define RG_SSUSB_CDR_MONEN                        (0x1<<0) //0:0
1214 +
1215 +//U3D_regB
1216 +#define RG_SSUSB_CDR_MONEN_DIG                    (0x1<<31) //31:31
1217 +#define RG_SSUSB_CDR_REGOD                        (0x3<<29) //30:29
1218 +#define RG_SSUSB_RX_DAC_EN                        (0x1<<26) //26:26
1219 +#define RG_SSUSB_RX_DAC_PWD                       (0x1<<25) //25:25
1220 +#define RG_SSUSB_EQ_CURSEL                        (0x1<<24) //24:24
1221 +#define RG_SSUSB_RX_DAC_MUX                       (0x1f<<19) //23:19
1222 +#define RG_SSUSB_RX_R2T_EN                        (0x1<<18) //18:18
1223 +#define RG_SSUSB_RX_T2R_EN                        (0x1<<17) //17:17
1224 +#define RG_SSUSB_RX_50_LOWER                      (0x7<<14) //16:14
1225 +#define RG_SSUSB_RX_50_TAR                        (0x3<<12) //13:12
1226 +#define RG_SSUSB_RX_SW_CTRL                       (0xf<<7) //10:7
1227 +#define RG_PCIE_SIGDET_VTH                        (0x3<<5) //6:5
1228 +#define RG_PCIE_SIGDET_LPF                        (0x3<<3) //4:3
1229 +#define RG_SSUSB_LFPS_MON_EN                      (0x1<<2) //2:2
1230 +
1231 +//U3D_regC
1232 +#define RG_SSUSB_RXAFE_DCMON_SEL                  (0xf<<28) //31:28
1233 +#define RG_SSUSB_CDR_RESERVE                      (0xff<<16) //23:16
1234 +#define RG_SSUSB_RXAFE_RESERVE                    (0xff<<8) //15:8
1235 +#define RG_PCIE_RX_RESERVE                        (0xff<<0) //7:0
1236 +
1237 +//U3D_redD
1238 +#define RGS_SSUSB_CDR_NO_OSC                      (0x1<<8) //8:8
1239 +#define RGS_SSUSB_RX_DEBUG_RESERVE                (0xff<<0) //7:0
1240 +
1241 +//U3D_regE
1242 +#define RG_SSUSB_INT_BIAS_SEL                     (0x1<<4) //4:4
1243 +#define RG_SSUSB_EXT_BIAS_SEL                     (0x1<<3) //3:3
1244 +#define RG_SSUSB_RX_P1_ENTRY_PASS                 (0x1<<2) //2:2
1245 +#define RG_SSUSB_RX_PD_RST                        (0x1<<1) //1:1
1246 +#define RG_SSUSB_RX_PD_RST_PASS                   (0x1<<0) //0:0
1247 +
1248 +
1249 +/* OFFSET */
1250 +
1251 +//U3D_reg0
1252 +#define RG_SSUSB_BGR_EN_OFST                      (31)
1253 +#define RG_SSUSB_CHPEN_OFST                       (30)
1254 +#define RG_SSUSB_BG_DIV_OFST                      (28)
1255 +#define RG_SSUSB_INTR_EN_OFST                     (26)
1256 +#define RG_SSUSB_MPX_OUT_SEL_OFST                 (24)
1257 +#define RG_SSUSB_MPX_SEL_OFST                     (16)
1258 +#define RG_SSUSB_REF_EN_OFST                      (15)
1259 +#define RG_SSUSB_VRT_VREF_SEL_OFST                (11)
1260 +#define RG_SSUSB_BG_RASEL_OFST                    (9)
1261 +#define RG_SSUSB_BG_RBSEL_OFST                    (7)
1262 +#define RG_SSUSB_BG_MONEN_OFST                    (6)
1263 +#define RG_PCIE_CLKDRV_OFFSET_OFST                (0)
1264 +
1265 +//U3D_reg1
1266 +#define RG_PCIE_CLKDRV_SLEW_OFST                  (30)
1267 +#define RG_PCIE_CLKDRV_AMP_OFST                   (27)
1268 +#define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST           (26)
1269 +#define RG_SSUSB_XTAL_MON_EN_OFST                 (25)
1270 +#define RG_SSUSB_XTAL_HYS_OFST                    (24)
1271 +#define RG_SSUSB_XTAL_TOP_RESERVE_OFST            (8)
1272 +#define RG_SSUSB_SYSPLL_RESERVE_OFST              (4)
1273 +#define RG_SSUSB_SYSPLL_FBSEL_OFST                (2)
1274 +#define RG_SSUSB_SYSPLL_PREDIV_OFST               (0)
1275 +
1276 +//U3D_reg2
1277 +#define RG_SSUSB_SYSPLL_LF_OFST                   (31)
1278 +#define RG_SSUSB_SYSPLL_FBDIV_OFST                (24)
1279 +#define RG_SSUSB_SYSPLL_POSDIV_OFST               (22)
1280 +#define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST          (21)
1281 +#define RG_SSUSB_SYSPLL_BLP_OFST                  (20)
1282 +#define RG_SSUSB_SYSPLL_BP_OFST                   (19)
1283 +#define RG_SSUSB_SYSPLL_BR_OFST                   (18)
1284 +#define RG_SSUSB_SYSPLL_BC_OFST                   (17)
1285 +#define RG_SSUSB_SYSPLL_DIVEN_OFST                (14)
1286 +#define RG_SSUSB_SYSPLL_FPEN_OFST                 (13)
1287 +#define RG_SSUSB_SYSPLL_MONCK_EN_OFST             (12)
1288 +#define RG_SSUSB_SYSPLL_MONVC_EN_OFST             (11)
1289 +#define RG_SSUSB_SYSPLL_MONREF_EN_OFST            (10)
1290 +#define RG_SSUSB_SYSPLL_VOD_EN_OFST               (9)
1291 +#define RG_SSUSB_SYSPLL_CK_SEL_OFST               (8)
1292 +
1293 +//U3D_reg3
1294 +#define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST          (16)
1295 +
1296 +//U3D_reg4
1297 +#define RG_SSUSB_SYSPLL_PCW_NCPO_OFST             (1)
1298 +
1299 +//U3D_reg5
1300 +#define RG_SSUSB_SYSPLL_DDS_PI_C_OFST             (29)
1301 +#define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST            (28)
1302 +#define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST          (27)
1303 +#define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST         (26)
1304 +#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST         (25)
1305 +#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST       (24)
1306 +#define RG_SSUSB_SYSPLL_DDS_MONEN_OFST            (23)
1307 +#define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST           (22)
1308 +#define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST           (21)
1309 +#define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST          (20)
1310 +#define RG_SSUSB_SYSPLL_DDS_DMY_OFST              (0)
1311 +
1312 +//U3D_reg6
1313 +#define RG_SSUSB_TX250MCK_INVB_OFST               (31)
1314 +#define RG_SSUSB_IDRV_ITAILOP_EN_OFST             (30)
1315 +#define RG_SSUSB_IDRV_CALIB_OFST                  (24)
1316 +#define RG_SSUSB_TX_R50_FON_OFST                  (23)
1317 +#define RG_SSUSB_TX_SR_OFST                       (20)
1318 +#define RG_SSUSB_TX_EIDLE_CM_OFST                 (16)
1319 +#define RG_SSUSB_RXDET_RSEL_OFST                  (14)
1320 +#define RG_SSUSB_RXDET_VTHSEL_OFST                (12)
1321 +#define RG_SSUSB_CKMON_EN_OFST                    (11)
1322 +#define RG_SSUSB_CKMON_SEL_OFST                   (8)
1323 +#define RG_SSUSB_TX_VLMON_EN_OFST                 (7)
1324 +#define RG_SSUSB_TX_VLMON_SEL_OFST                (6)
1325 +#define RG_SSUSB_RXLBTX_EN_OFST                   (5)
1326 +#define RG_SSUSB_TXLBRX_EN_OFST                   (4)
1327 +
1328 +//U3D_reg7
1329 +#define RG_SSUSB_RESERVE_OFST                     (12)
1330 +#define RG_SSUSB_PLL_CKCTRL_OFST                  (10)
1331 +#define RG_SSUSB_PLL_POSDIV_OFST                  (8)
1332 +#define RG_SSUSB_PLL_AUTOK_LOAD_OFST              (7)
1333 +#define RG_SSUSB_PLL_LOAD_RSTB_OFST               (6)
1334 +#define RG_SSUSB_PLL_EP_EN_OFST                   (5)
1335 +#define RG_SSUSB_PLL_VOD_EN_OFST                  (4)
1336 +#define RG_SSUSB_PLL_V11_EN_OFST                  (3)
1337 +#define RG_SSUSB_PLL_MONREF_EN_OFST               (2)
1338 +#define RG_SSUSB_PLL_MONCK_EN_OFST                (1)
1339 +#define RG_SSUSB_PLL_MONVC_EN_OFST                (0)
1340 +
1341 +//U3D_reg8
1342 +#define RG_SSUSB_PLL_RESERVE_OFST                 (0)
1343 +
1344 +//U3D_reg9
1345 +#define RG_SSUSB_PLL_DDS_DMY_OFST                 (16)
1346 +#define RG_SSUSB_PLL_SSC_PRD_OFST                 (0)
1347 +
1348 +//U3D_regA
1349 +#define RG_SSUSB_PLL_SSC_PHASE_INI_OFST           (31)
1350 +#define RG_SSUSB_PLL_SSC_TRI_EN_OFST              (30)
1351 +#define RG_SSUSB_PLL_CLK_PH_INV_OFST              (29)
1352 +#define RG_SSUSB_PLL_DDS_LPF_EN_OFST              (28)
1353 +#define RG_SSUSB_PLL_DDS_VADJ_OFST                (21)
1354 +#define RG_SSUSB_PLL_DDS_MONEN_OFST               (20)
1355 +#define RG_SSUSB_PLL_DDS_PS_VADJ_OFST             (17)
1356 +#define RG_SSUSB_PLL_DDS_SEL_EXT_OFST             (16)
1357 +#define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST           (15)
1358 +#define RG_SSUSB_CDR_PD_DIV_SEL_OFST              (14)
1359 +#define RG_SSUSB_CDR_CPBIAS_SEL_OFST              (13)
1360 +#define RG_SSUSB_CDR_OSCDET_EN_OFST               (12)
1361 +#define RG_SSUSB_CDR_MONMUX_OFST                  (11)
1362 +#define RG_SSUSB_CDR_CKCTRL_OFST                  (9)
1363 +#define RG_SSUSB_CDR_ACCEN_OFST                   (8)
1364 +#define RG_SSUSB_CDR_BYPASS_OFST                  (6)
1365 +#define RG_SSUSB_CDR_PI_SLEW_OFST                 (4)
1366 +#define RG_SSUSB_CDR_EPEN_OFST                    (3)
1367 +#define RG_SSUSB_CDR_AUTOK_LOAD_OFST              (2)
1368 +#define RG_SSUSB_CDR_LOAD_RSTB_OFST               (1)
1369 +#define RG_SSUSB_CDR_MONEN_OFST                   (0)
1370 +
1371 +//U3D_regB
1372 +#define RG_SSUSB_CDR_MONEN_DIG_OFST               (31)
1373 +#define RG_SSUSB_CDR_REGOD_OFST                   (29)
1374 +#define RG_SSUSB_RX_DAC_EN_OFST                   (26)
1375 +#define RG_SSUSB_RX_DAC_PWD_OFST                  (25)
1376 +#define RG_SSUSB_EQ_CURSEL_OFST                   (24)
1377 +#define RG_SSUSB_RX_DAC_MUX_OFST                  (19)
1378 +#define RG_SSUSB_RX_R2T_EN_OFST                   (18)
1379 +#define RG_SSUSB_RX_T2R_EN_OFST                   (17)
1380 +#define RG_SSUSB_RX_50_LOWER_OFST                 (14)
1381 +#define RG_SSUSB_RX_50_TAR_OFST                   (12)
1382 +#define RG_SSUSB_RX_SW_CTRL_OFST                  (7)
1383 +#define RG_PCIE_SIGDET_VTH_OFST                   (5)
1384 +#define RG_PCIE_SIGDET_LPF_OFST                   (3)
1385 +#define RG_SSUSB_LFPS_MON_EN_OFST                 (2)
1386 +
1387 +//U3D_regC
1388 +#define RG_SSUSB_RXAFE_DCMON_SEL_OFST             (28)
1389 +#define RG_SSUSB_CDR_RESERVE_OFST                 (16)
1390 +#define RG_SSUSB_RXAFE_RESERVE_OFST               (8)
1391 +#define RG_PCIE_RX_RESERVE_OFST                   (0)
1392 +
1393 +//U3D_redD
1394 +#define RGS_SSUSB_CDR_NO_OSC_OFST                 (8)
1395 +#define RGS_SSUSB_RX_DEBUG_RESERVE_OFST           (0)
1396 +
1397 +//U3D_regE
1398 +#define RG_SSUSB_INT_BIAS_SEL_OFST                (4)
1399 +#define RG_SSUSB_EXT_BIAS_SEL_OFST                (3)
1400 +#define RG_SSUSB_RX_P1_ENTRY_PASS_OFST            (2)
1401 +#define RG_SSUSB_RX_PD_RST_OFST                   (1)
1402 +#define RG_SSUSB_RX_PD_RST_PASS_OFST              (0)
1403 +
1404 +///////////////////////////////////////////////////////////////////////////////
1405 +
1406 +struct u3phya_da_reg {
1407 +       //0x0
1408 +       PHY_LE32 reg0;
1409 +       PHY_LE32 reg1;
1410 +       PHY_LE32 reg4;
1411 +       PHY_LE32 reg5;
1412 +       //0x10
1413 +       PHY_LE32 reg6;
1414 +       PHY_LE32 reg7;
1415 +       PHY_LE32 reg8;
1416 +       PHY_LE32 reg9;
1417 +       //0x20
1418 +       PHY_LE32 reg10;
1419 +       PHY_LE32 reg12;
1420 +       PHY_LE32 reg13;
1421 +       PHY_LE32 reg14;
1422 +       //0x30
1423 +       PHY_LE32 reg15;
1424 +       PHY_LE32 reg16;
1425 +       PHY_LE32 reg19;
1426 +       PHY_LE32 reg20;
1427 +       //0x40
1428 +       PHY_LE32 reg21;
1429 +       PHY_LE32 reg23;
1430 +       PHY_LE32 reg25;
1431 +       PHY_LE32 reg26;
1432 +       //0x50
1433 +       PHY_LE32 reg28;
1434 +       PHY_LE32 reg29;
1435 +       PHY_LE32 reg30;
1436 +       PHY_LE32 reg31;
1437 +       //0x60
1438 +       PHY_LE32 reg32;
1439 +       PHY_LE32 reg33;
1440 +};
1441 +
1442 +//U3D_reg0
1443 +#define RG_PCIE_SPEED_PE2D                        (0x1<<24) //24:24
1444 +#define RG_PCIE_SPEED_PE2H                        (0x1<<23) //23:23
1445 +#define RG_PCIE_SPEED_PE1D                        (0x1<<22) //22:22
1446 +#define RG_PCIE_SPEED_PE1H                        (0x1<<21) //21:21
1447 +#define RG_PCIE_SPEED_U3                          (0x1<<20) //20:20
1448 +#define RG_SSUSB_XTAL_EXT_EN_PE2D                 (0x3<<18) //19:18
1449 +#define RG_SSUSB_XTAL_EXT_EN_PE2H                 (0x3<<16) //17:16
1450 +#define RG_SSUSB_XTAL_EXT_EN_PE1D                 (0x3<<14) //15:14
1451 +#define RG_SSUSB_XTAL_EXT_EN_PE1H                 (0x3<<12) //13:12
1452 +#define RG_SSUSB_XTAL_EXT_EN_U3                   (0x3<<10) //11:10
1453 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D               (0x3<<8) //9:8
1454 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H               (0x3<<6) //7:6
1455 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D               (0x3<<4) //5:4
1456 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H               (0x3<<2) //3:2
1457 +#define RG_SSUSB_CDR_REFCK_SEL_U3                 (0x3<<0) //1:0
1458 +
1459 +//U3D_reg1
1460 +#define RG_USB20_REFCK_SEL_PE2D                   (0x1<<30) //30:30
1461 +#define RG_USB20_REFCK_SEL_PE2H                   (0x1<<29) //29:29
1462 +#define RG_USB20_REFCK_SEL_PE1D                   (0x1<<28) //28:28
1463 +#define RG_USB20_REFCK_SEL_PE1H                   (0x1<<27) //27:27
1464 +#define RG_USB20_REFCK_SEL_U3                     (0x1<<26) //26:26
1465 +#define RG_PCIE_REFCK_DIV4_PE2D                   (0x1<<25) //25:25
1466 +#define RG_PCIE_REFCK_DIV4_PE2H                   (0x1<<24) //24:24
1467 +#define RG_PCIE_REFCK_DIV4_PE1D                   (0x1<<18) //18:18
1468 +#define RG_PCIE_REFCK_DIV4_PE1H                   (0x1<<17) //17:17
1469 +#define RG_PCIE_REFCK_DIV4_U3                     (0x1<<16) //16:16
1470 +#define RG_PCIE_MODE_PE2D                         (0x1<<8) //8:8
1471 +#define RG_PCIE_MODE_PE2H                         (0x1<<3) //3:3
1472 +#define RG_PCIE_MODE_PE1D                         (0x1<<2) //2:2
1473 +#define RG_PCIE_MODE_PE1H                         (0x1<<1) //1:1
1474 +#define RG_PCIE_MODE_U3                           (0x1<<0) //0:0
1475 +
1476 +//U3D_reg4
1477 +#define RG_SSUSB_PLL_DIVEN_PE2D                   (0x7<<22) //24:22
1478 +#define RG_SSUSB_PLL_DIVEN_PE2H                   (0x7<<19) //21:19
1479 +#define RG_SSUSB_PLL_DIVEN_PE1D                   (0x7<<16) //18:16
1480 +#define RG_SSUSB_PLL_DIVEN_PE1H                   (0x7<<13) //15:13
1481 +#define RG_SSUSB_PLL_DIVEN_U3                     (0x7<<10) //12:10
1482 +#define RG_SSUSB_PLL_BC_PE2D                      (0x3<<8) //9:8
1483 +#define RG_SSUSB_PLL_BC_PE2H                      (0x3<<6) //7:6
1484 +#define RG_SSUSB_PLL_BC_PE1D                      (0x3<<4) //5:4
1485 +#define RG_SSUSB_PLL_BC_PE1H                      (0x3<<2) //3:2
1486 +#define RG_SSUSB_PLL_BC_U3                        (0x3<<0) //1:0
1487 +
1488 +//U3D_reg5
1489 +#define RG_SSUSB_PLL_BR_PE2D                      (0x7<<27) //29:27
1490 +#define RG_SSUSB_PLL_BR_PE2H                      (0x7<<24) //26:24
1491 +#define RG_SSUSB_PLL_BR_PE1D                      (0x7<<21) //23:21
1492 +#define RG_SSUSB_PLL_BR_PE1H                      (0x7<<18) //20:18
1493 +#define RG_SSUSB_PLL_BR_U3                        (0x7<<15) //17:15
1494 +#define RG_SSUSB_PLL_IC_PE2D                      (0x7<<12) //14:12
1495 +#define RG_SSUSB_PLL_IC_PE2H                      (0x7<<9) //11:9
1496 +#define RG_SSUSB_PLL_IC_PE1D                      (0x7<<6) //8:6
1497 +#define RG_SSUSB_PLL_IC_PE1H                      (0x7<<3) //5:3
1498 +#define RG_SSUSB_PLL_IC_U3                        (0x7<<0) //2:0
1499 +
1500 +//U3D_reg6
1501 +#define RG_SSUSB_PLL_IR_PE2D                      (0xf<<24) //27:24
1502 +#define RG_SSUSB_PLL_IR_PE2H                      (0xf<<16) //19:16
1503 +#define RG_SSUSB_PLL_IR_PE1D                      (0xf<<8) //11:8
1504 +#define RG_SSUSB_PLL_IR_PE1H                      (0xf<<4) //7:4
1505 +#define RG_SSUSB_PLL_IR_U3                        (0xf<<0) //3:0
1506 +
1507 +//U3D_reg7
1508 +#define RG_SSUSB_PLL_BP_PE2D                      (0xf<<24) //27:24
1509 +#define RG_SSUSB_PLL_BP_PE2H                      (0xf<<16) //19:16
1510 +#define RG_SSUSB_PLL_BP_PE1D                      (0xf<<8) //11:8
1511 +#define RG_SSUSB_PLL_BP_PE1H                      (0xf<<4) //7:4
1512 +#define RG_SSUSB_PLL_BP_U3                        (0xf<<0) //3:0
1513 +
1514 +//U3D_reg8
1515 +#define RG_SSUSB_PLL_FBKSEL_PE2D                  (0x3<<24) //25:24
1516 +#define RG_SSUSB_PLL_FBKSEL_PE2H                  (0x3<<16) //17:16
1517 +#define RG_SSUSB_PLL_FBKSEL_PE1D                  (0x3<<8) //9:8
1518 +#define RG_SSUSB_PLL_FBKSEL_PE1H                  (0x3<<2) //3:2
1519 +#define RG_SSUSB_PLL_FBKSEL_U3                    (0x3<<0) //1:0
1520 +
1521 +//U3D_reg9
1522 +#define RG_SSUSB_PLL_FBKDIV_PE2H                  (0x7f<<24) //30:24
1523 +#define RG_SSUSB_PLL_FBKDIV_PE1D                  (0x7f<<16) //22:16
1524 +#define RG_SSUSB_PLL_FBKDIV_PE1H                  (0x7f<<8) //14:8
1525 +#define RG_SSUSB_PLL_FBKDIV_U3                    (0x7f<<0) //6:0
1526 +
1527 +//U3D_reg10
1528 +#define RG_SSUSB_PLL_PREDIV_PE2D                  (0x3<<26) //27:26
1529 +#define RG_SSUSB_PLL_PREDIV_PE2H                  (0x3<<24) //25:24
1530 +#define RG_SSUSB_PLL_PREDIV_PE1D                  (0x3<<18) //19:18
1531 +#define RG_SSUSB_PLL_PREDIV_PE1H                  (0x3<<16) //17:16
1532 +#define RG_SSUSB_PLL_PREDIV_U3                    (0x3<<8) //9:8
1533 +#define RG_SSUSB_PLL_FBKDIV_PE2D                  (0x7f<<0) //6:0
1534 +
1535 +//U3D_reg12
1536 +#define RG_SSUSB_PLL_PCW_NCPO_U3                  (0x7fffffff<<0) //30:0
1537 +
1538 +//U3D_reg13
1539 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H                (0x7fffffff<<0) //30:0
1540 +
1541 +//U3D_reg14
1542 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D                (0x7fffffff<<0) //30:0
1543 +
1544 +//U3D_reg15
1545 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H                (0x7fffffff<<0) //30:0
1546 +
1547 +//U3D_reg16
1548 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D                (0x7fffffff<<0) //30:0
1549 +
1550 +//U3D_reg19
1551 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H              (0xffff<<16) //31:16
1552 +#define RG_SSUSB_PLL_SSC_DELTA1_U3                (0xffff<<0) //15:0
1553 +
1554 +//U3D_reg20
1555 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H              (0xffff<<16) //31:16
1556 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D              (0xffff<<0) //15:0
1557 +
1558 +//U3D_reg21
1559 +#define RG_SSUSB_PLL_SSC_DELTA_U3                 (0xffff<<16) //31:16
1560 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D              (0xffff<<0) //15:0
1561 +
1562 +//U3D_reg23
1563 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D               (0xffff<<16) //31:16
1564 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H               (0xffff<<0) //15:0
1565 +
1566 +//U3D_reg25
1567 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D               (0xffff<<16) //31:16
1568 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H               (0xffff<<0) //15:0
1569 +
1570 +//U3D_reg26
1571 +#define RG_SSUSB_PLL_REFCKDIV_PE2D                (0x1<<25) //25:25
1572 +#define RG_SSUSB_PLL_REFCKDIV_PE2H                (0x1<<24) //24:24
1573 +#define RG_SSUSB_PLL_REFCKDIV_PE1D                (0x1<<16) //16:16
1574 +#define RG_SSUSB_PLL_REFCKDIV_PE1H                (0x1<<8) //8:8
1575 +#define RG_SSUSB_PLL_REFCKDIV_U3                  (0x1<<0) //0:0
1576 +
1577 +//U3D_reg28
1578 +#define RG_SSUSB_CDR_BPA_PE2D                     (0x3<<24) //25:24
1579 +#define RG_SSUSB_CDR_BPA_PE2H                     (0x3<<16) //17:16
1580 +#define RG_SSUSB_CDR_BPA_PE1D                     (0x3<<10) //11:10
1581 +#define RG_SSUSB_CDR_BPA_PE1H                     (0x3<<8) //9:8
1582 +#define RG_SSUSB_CDR_BPA_U3                       (0x3<<0) //1:0
1583 +
1584 +//U3D_reg29
1585 +#define RG_SSUSB_CDR_BPB_PE2D                     (0x7<<24) //26:24
1586 +#define RG_SSUSB_CDR_BPB_PE2H                     (0x7<<16) //18:16
1587 +#define RG_SSUSB_CDR_BPB_PE1D                     (0x7<<6) //8:6
1588 +#define RG_SSUSB_CDR_BPB_PE1H                     (0x7<<3) //5:3
1589 +#define RG_SSUSB_CDR_BPB_U3                       (0x7<<0) //2:0
1590 +
1591 +//U3D_reg30
1592 +#define RG_SSUSB_CDR_BR_PE2D                      (0x7<<24) //26:24
1593 +#define RG_SSUSB_CDR_BR_PE2H                      (0x7<<16) //18:16
1594 +#define RG_SSUSB_CDR_BR_PE1D                      (0x7<<6) //8:6
1595 +#define RG_SSUSB_CDR_BR_PE1H                      (0x7<<3) //5:3
1596 +#define RG_SSUSB_CDR_BR_U3                        (0x7<<0) //2:0
1597 +
1598 +//U3D_reg31
1599 +#define RG_SSUSB_CDR_FBDIV_PE2H                   (0x7f<<24) //30:24
1600 +#define RG_SSUSB_CDR_FBDIV_PE1D                   (0x7f<<16) //22:16
1601 +#define RG_SSUSB_CDR_FBDIV_PE1H                   (0x7f<<8) //14:8
1602 +#define RG_SSUSB_CDR_FBDIV_U3                     (0x7f<<0) //6:0
1603 +
1604 +//U3D_reg32
1605 +#define RG_SSUSB_EQ_RSTEP1_PE2D                   (0x3<<30) //31:30
1606 +#define RG_SSUSB_EQ_RSTEP1_PE2H                   (0x3<<28) //29:28
1607 +#define RG_SSUSB_EQ_RSTEP1_PE1D                   (0x3<<26) //27:26
1608 +#define RG_SSUSB_EQ_RSTEP1_PE1H                   (0x3<<24) //25:24
1609 +#define RG_SSUSB_EQ_RSTEP1_U3                     (0x3<<22) //23:22
1610 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D               (0x3<<20) //21:20
1611 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H               (0x3<<18) //19:18
1612 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D               (0x3<<16) //17:16
1613 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H               (0x3<<14) //15:14
1614 +#define RG_SSUSB_LFPS_DEGLITCH_U3                 (0x3<<12) //13:12
1615 +#define RG_SSUSB_CDR_KVSEL_PE2D                   (0x1<<11) //11:11
1616 +#define RG_SSUSB_CDR_KVSEL_PE2H                   (0x1<<10) //10:10
1617 +#define RG_SSUSB_CDR_KVSEL_PE1D                   (0x1<<9) //9:9
1618 +#define RG_SSUSB_CDR_KVSEL_PE1H                   (0x1<<8) //8:8
1619 +#define RG_SSUSB_CDR_KVSEL_U3                     (0x1<<7) //7:7
1620 +#define RG_SSUSB_CDR_FBDIV_PE2D                   (0x7f<<0) //6:0
1621 +
1622 +//U3D_reg33
1623 +#define RG_SSUSB_RX_CMPWD_PE2D                    (0x1<<26) //26:26
1624 +#define RG_SSUSB_RX_CMPWD_PE2H                    (0x1<<25) //25:25
1625 +#define RG_SSUSB_RX_CMPWD_PE1D                    (0x1<<24) //24:24
1626 +#define RG_SSUSB_RX_CMPWD_PE1H                    (0x1<<23) //23:23
1627 +#define RG_SSUSB_RX_CMPWD_U3                      (0x1<<16) //16:16
1628 +#define RG_SSUSB_EQ_RSTEP2_PE2D                   (0x3<<8) //9:8
1629 +#define RG_SSUSB_EQ_RSTEP2_PE2H                   (0x3<<6) //7:6
1630 +#define RG_SSUSB_EQ_RSTEP2_PE1D                   (0x3<<4) //5:4
1631 +#define RG_SSUSB_EQ_RSTEP2_PE1H                   (0x3<<2) //3:2
1632 +#define RG_SSUSB_EQ_RSTEP2_U3                     (0x3<<0) //1:0
1633 +
1634 +
1635 +/* OFFSET  */
1636 +
1637 +//U3D_reg0
1638 +#define RG_PCIE_SPEED_PE2D_OFST                   (24)
1639 +#define RG_PCIE_SPEED_PE2H_OFST                   (23)
1640 +#define RG_PCIE_SPEED_PE1D_OFST                   (22)
1641 +#define RG_PCIE_SPEED_PE1H_OFST                   (21)
1642 +#define RG_PCIE_SPEED_U3_OFST                     (20)
1643 +#define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST            (18)
1644 +#define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST            (16)
1645 +#define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST            (14)
1646 +#define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST            (12)
1647 +#define RG_SSUSB_XTAL_EXT_EN_U3_OFST              (10)
1648 +#define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST          (8)
1649 +#define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST          (6)
1650 +#define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST          (4)
1651 +#define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST          (2)
1652 +#define RG_SSUSB_CDR_REFCK_SEL_U3_OFST            (0)
1653 +
1654 +//U3D_reg1
1655 +#define RG_USB20_REFCK_SEL_PE2D_OFST              (30)
1656 +#define RG_USB20_REFCK_SEL_PE2H_OFST              (29)
1657 +#define RG_USB20_REFCK_SEL_PE1D_OFST              (28)
1658 +#define RG_USB20_REFCK_SEL_PE1H_OFST              (27)
1659 +#define RG_USB20_REFCK_SEL_U3_OFST                (26)
1660 +#define RG_PCIE_REFCK_DIV4_PE2D_OFST              (25)
1661 +#define RG_PCIE_REFCK_DIV4_PE2H_OFST              (24)
1662 +#define RG_PCIE_REFCK_DIV4_PE1D_OFST              (18)
1663 +#define RG_PCIE_REFCK_DIV4_PE1H_OFST              (17)
1664 +#define RG_PCIE_REFCK_DIV4_U3_OFST                (16)
1665 +#define RG_PCIE_MODE_PE2D_OFST                    (8)
1666 +#define RG_PCIE_MODE_PE2H_OFST                    (3)
1667 +#define RG_PCIE_MODE_PE1D_OFST                    (2)
1668 +#define RG_PCIE_MODE_PE1H_OFST                    (1)
1669 +#define RG_PCIE_MODE_U3_OFST                      (0)
1670 +
1671 +//U3D_reg4
1672 +#define RG_SSUSB_PLL_DIVEN_PE2D_OFST              (22)
1673 +#define RG_SSUSB_PLL_DIVEN_PE2H_OFST              (19)
1674 +#define RG_SSUSB_PLL_DIVEN_PE1D_OFST              (16)
1675 +#define RG_SSUSB_PLL_DIVEN_PE1H_OFST              (13)
1676 +#define RG_SSUSB_PLL_DIVEN_U3_OFST                (10)
1677 +#define RG_SSUSB_PLL_BC_PE2D_OFST                 (8)
1678 +#define RG_SSUSB_PLL_BC_PE2H_OFST                 (6)
1679 +#define RG_SSUSB_PLL_BC_PE1D_OFST                 (4)
1680 +#define RG_SSUSB_PLL_BC_PE1H_OFST                 (2)
1681 +#define RG_SSUSB_PLL_BC_U3_OFST                   (0)
1682 +
1683 +//U3D_reg5
1684 +#define RG_SSUSB_PLL_BR_PE2D_OFST                 (27)
1685 +#define RG_SSUSB_PLL_BR_PE2H_OFST                 (24)
1686 +#define RG_SSUSB_PLL_BR_PE1D_OFST                 (21)
1687 +#define RG_SSUSB_PLL_BR_PE1H_OFST                 (18)
1688 +#define RG_SSUSB_PLL_BR_U3_OFST                   (15)
1689 +#define RG_SSUSB_PLL_IC_PE2D_OFST                 (12)
1690 +#define RG_SSUSB_PLL_IC_PE2H_OFST                 (9)
1691 +#define RG_SSUSB_PLL_IC_PE1D_OFST                 (6)
1692 +#define RG_SSUSB_PLL_IC_PE1H_OFST                 (3)
1693 +#define RG_SSUSB_PLL_IC_U3_OFST                   (0)
1694 +
1695 +//U3D_reg6
1696 +#define RG_SSUSB_PLL_IR_PE2D_OFST                 (24)
1697 +#define RG_SSUSB_PLL_IR_PE2H_OFST                 (16)
1698 +#define RG_SSUSB_PLL_IR_PE1D_OFST                 (8)
1699 +#define RG_SSUSB_PLL_IR_PE1H_OFST                 (4)
1700 +#define RG_SSUSB_PLL_IR_U3_OFST                   (0)
1701 +
1702 +//U3D_reg7
1703 +#define RG_SSUSB_PLL_BP_PE2D_OFST                 (24)
1704 +#define RG_SSUSB_PLL_BP_PE2H_OFST                 (16)
1705 +#define RG_SSUSB_PLL_BP_PE1D_OFST                 (8)
1706 +#define RG_SSUSB_PLL_BP_PE1H_OFST                 (4)
1707 +#define RG_SSUSB_PLL_BP_U3_OFST                   (0)
1708 +
1709 +//U3D_reg8
1710 +#define RG_SSUSB_PLL_FBKSEL_PE2D_OFST             (24)
1711 +#define RG_SSUSB_PLL_FBKSEL_PE2H_OFST             (16)
1712 +#define RG_SSUSB_PLL_FBKSEL_PE1D_OFST             (8)
1713 +#define RG_SSUSB_PLL_FBKSEL_PE1H_OFST             (2)
1714 +#define RG_SSUSB_PLL_FBKSEL_U3_OFST               (0)
1715 +
1716 +//U3D_reg9
1717 +#define RG_SSUSB_PLL_FBKDIV_PE2H_OFST             (24)
1718 +#define RG_SSUSB_PLL_FBKDIV_PE1D_OFST             (16)
1719 +#define RG_SSUSB_PLL_FBKDIV_PE1H_OFST             (8)
1720 +#define RG_SSUSB_PLL_FBKDIV_U3_OFST               (0)
1721 +
1722 +//U3D_reg10
1723 +#define RG_SSUSB_PLL_PREDIV_PE2D_OFST             (26)
1724 +#define RG_SSUSB_PLL_PREDIV_PE2H_OFST             (24)
1725 +#define RG_SSUSB_PLL_PREDIV_PE1D_OFST             (18)
1726 +#define RG_SSUSB_PLL_PREDIV_PE1H_OFST             (16)
1727 +#define RG_SSUSB_PLL_PREDIV_U3_OFST               (8)
1728 +#define RG_SSUSB_PLL_FBKDIV_PE2D_OFST             (0)
1729 +
1730 +//U3D_reg12
1731 +#define RG_SSUSB_PLL_PCW_NCPO_U3_OFST             (0)
1732 +
1733 +//U3D_reg13
1734 +#define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST           (0)
1735 +
1736 +//U3D_reg14
1737 +#define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST           (0)
1738 +
1739 +//U3D_reg15
1740 +#define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST           (0)
1741 +
1742 +//U3D_reg16
1743 +#define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST           (0)
1744 +
1745 +//U3D_reg19
1746 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST         (16)
1747 +#define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST           (0)
1748 +
1749 +//U3D_reg20
1750 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST         (16)
1751 +#define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST         (0)
1752 +
1753 +//U3D_reg21
1754 +#define RG_SSUSB_PLL_SSC_DELTA_U3_OFST            (16)
1755 +#define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST         (0)
1756 +
1757 +//U3D_reg23
1758 +#define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST          (16)
1759 +#define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST          (0)
1760 +
1761 +//U3D_reg25
1762 +#define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST          (16)
1763 +#define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST          (0)
1764 +
1765 +//U3D_reg26
1766 +#define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST           (25)
1767 +#define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST           (24)
1768 +#define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST           (16)
1769 +#define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST           (8)
1770 +#define RG_SSUSB_PLL_REFCKDIV_U3_OFST             (0)
1771 +
1772 +//U3D_reg28
1773 +#define RG_SSUSB_CDR_BPA_PE2D_OFST                (24)
1774 +#define RG_SSUSB_CDR_BPA_PE2H_OFST                (16)
1775 +#define RG_SSUSB_CDR_BPA_PE1D_OFST                (10)
1776 +#define RG_SSUSB_CDR_BPA_PE1H_OFST                (8)
1777 +#define RG_SSUSB_CDR_BPA_U3_OFST                  (0)
1778 +
1779 +//U3D_reg29
1780 +#define RG_SSUSB_CDR_BPB_PE2D_OFST                (24)
1781 +#define RG_SSUSB_CDR_BPB_PE2H_OFST                (16)
1782 +#define RG_SSUSB_CDR_BPB_PE1D_OFST                (6)
1783 +#define RG_SSUSB_CDR_BPB_PE1H_OFST                (3)
1784 +#define RG_SSUSB_CDR_BPB_U3_OFST                  (0)
1785 +
1786 +//U3D_reg30
1787 +#define RG_SSUSB_CDR_BR_PE2D_OFST                 (24)
1788 +#define RG_SSUSB_CDR_BR_PE2H_OFST                 (16)
1789 +#define RG_SSUSB_CDR_BR_PE1D_OFST                 (6)
1790 +#define RG_SSUSB_CDR_BR_PE1H_OFST                 (3)
1791 +#define RG_SSUSB_CDR_BR_U3_OFST                   (0)
1792 +
1793 +//U3D_reg31
1794 +#define RG_SSUSB_CDR_FBDIV_PE2H_OFST              (24)
1795 +#define RG_SSUSB_CDR_FBDIV_PE1D_OFST              (16)
1796 +#define RG_SSUSB_CDR_FBDIV_PE1H_OFST              (8)
1797 +#define RG_SSUSB_CDR_FBDIV_U3_OFST                (0)
1798 +
1799 +//U3D_reg32
1800 +#define RG_SSUSB_EQ_RSTEP1_PE2D_OFST              (30)
1801 +#define RG_SSUSB_EQ_RSTEP1_PE2H_OFST              (28)
1802 +#define RG_SSUSB_EQ_RSTEP1_PE1D_OFST              (26)
1803 +#define RG_SSUSB_EQ_RSTEP1_PE1H_OFST              (24)
1804 +#define RG_SSUSB_EQ_RSTEP1_U3_OFST                (22)
1805 +#define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST          (20)
1806 +#define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST          (18)
1807 +#define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST          (16)
1808 +#define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST          (14)
1809 +#define RG_SSUSB_LFPS_DEGLITCH_U3_OFST            (12)
1810 +#define RG_SSUSB_CDR_KVSEL_PE2D_OFST              (11)
1811 +#define RG_SSUSB_CDR_KVSEL_PE2H_OFST              (10)
1812 +#define RG_SSUSB_CDR_KVSEL_PE1D_OFST              (9)
1813 +#define RG_SSUSB_CDR_KVSEL_PE1H_OFST              (8)
1814 +#define RG_SSUSB_CDR_KVSEL_U3_OFST                (7)
1815 +#define RG_SSUSB_CDR_FBDIV_PE2D_OFST              (0)
1816 +
1817 +//U3D_reg33
1818 +#define RG_SSUSB_RX_CMPWD_PE2D_OFST               (26)
1819 +#define RG_SSUSB_RX_CMPWD_PE2H_OFST               (25)
1820 +#define RG_SSUSB_RX_CMPWD_PE1D_OFST               (24)
1821 +#define RG_SSUSB_RX_CMPWD_PE1H_OFST               (23)
1822 +#define RG_SSUSB_RX_CMPWD_U3_OFST                 (16)
1823 +#define RG_SSUSB_EQ_RSTEP2_PE2D_OFST              (8)
1824 +#define RG_SSUSB_EQ_RSTEP2_PE2H_OFST              (6)
1825 +#define RG_SSUSB_EQ_RSTEP2_PE1D_OFST              (4)
1826 +#define RG_SSUSB_EQ_RSTEP2_PE1H_OFST              (2)
1827 +#define RG_SSUSB_EQ_RSTEP2_U3_OFST                (0)
1828 +
1829 +
1830 +///////////////////////////////////////////////////////////////////////////////
1831 +
1832 +struct u3phyd_reg {
1833 +       //0x0
1834 +       PHY_LE32 phyd_mix0;
1835 +       PHY_LE32 phyd_mix1;
1836 +       PHY_LE32 phyd_lfps0;
1837 +       PHY_LE32 phyd_lfps1;
1838 +       //0x10
1839 +       PHY_LE32 phyd_impcal0;
1840 +       PHY_LE32 phyd_impcal1;
1841 +       PHY_LE32 phyd_txpll0;
1842 +       PHY_LE32 phyd_txpll1;
1843 +       //0x20
1844 +       PHY_LE32 phyd_txpll2;
1845 +       PHY_LE32 phyd_fl0;
1846 +       PHY_LE32 phyd_mix2;
1847 +       PHY_LE32 phyd_rx0;
1848 +       //0x30
1849 +       PHY_LE32 phyd_t2rlb;
1850 +       PHY_LE32 phyd_cppat;
1851 +       PHY_LE32 phyd_mix3;
1852 +       PHY_LE32 phyd_ebufctl;
1853 +       //0x40
1854 +       PHY_LE32 phyd_pipe0;
1855 +       PHY_LE32 phyd_pipe1;
1856 +       PHY_LE32 phyd_mix4;
1857 +       PHY_LE32 phyd_ckgen0;
1858 +       //0x50
1859 +       PHY_LE32 phyd_mix5;
1860 +       PHY_LE32 phyd_reserved;
1861 +       PHY_LE32 phyd_cdr0;
1862 +       PHY_LE32 phyd_cdr1;
1863 +       //0x60
1864 +       PHY_LE32 phyd_pll_0;
1865 +       PHY_LE32 phyd_pll_1;
1866 +       PHY_LE32 phyd_bcn_det_1;
1867 +       PHY_LE32 phyd_bcn_det_2;
1868 +       //0x70
1869 +       PHY_LE32 eq0;
1870 +       PHY_LE32 eq1;
1871 +       PHY_LE32 eq2;
1872 +       PHY_LE32 eq3;
1873 +       //0x80
1874 +       PHY_LE32 eq_eye0;
1875 +       PHY_LE32 eq_eye1;
1876 +       PHY_LE32 eq_eye2;
1877 +       PHY_LE32 eq_dfe0;
1878 +       //0x90
1879 +       PHY_LE32 eq_dfe1;
1880 +       PHY_LE32 eq_dfe2;
1881 +       PHY_LE32 eq_dfe3;
1882 +       PHY_LE32 reserve0;
1883 +       //0xa0
1884 +       PHY_LE32 phyd_mon0;
1885 +       PHY_LE32 phyd_mon1;
1886 +       PHY_LE32 phyd_mon2;
1887 +       PHY_LE32 phyd_mon3;
1888 +       //0xb0
1889 +       PHY_LE32 phyd_mon4;
1890 +       PHY_LE32 phyd_mon5;
1891 +       PHY_LE32 phyd_mon6;
1892 +       PHY_LE32 phyd_mon7;
1893 +       //0xc0
1894 +       PHY_LE32 phya_rx_mon0;
1895 +       PHY_LE32 phya_rx_mon1;
1896 +       PHY_LE32 phya_rx_mon2;
1897 +       PHY_LE32 phya_rx_mon3;
1898 +       //0xd0
1899 +       PHY_LE32 phya_rx_mon4;
1900 +       PHY_LE32 phya_rx_mon5;
1901 +       PHY_LE32 phyd_cppat2;
1902 +       PHY_LE32 eq_eye3;
1903 +       //0xe0
1904 +       PHY_LE32 kband_out;
1905 +       PHY_LE32 kband_out1;
1906 +};
1907 +
1908 +//U3D_PHYD_MIX0
1909 +#define RG_SSUSB_P_P3_TX_NG                       (0x1<<31) //31:31
1910 +#define RG_SSUSB_TSEQ_EN                          (0x1<<30) //30:30
1911 +#define RG_SSUSB_TSEQ_POLEN                       (0x1<<29) //29:29
1912 +#define RG_SSUSB_TSEQ_POL                         (0x1<<28) //28:28
1913 +#define RG_SSUSB_P_P3_PCLK_NG                     (0x1<<27) //27:27
1914 +#define RG_SSUSB_TSEQ_TH                          (0x7<<24) //26:24
1915 +#define RG_SSUSB_PRBS_BERTH                       (0xff<<16) //23:16
1916 +#define RG_SSUSB_DISABLE_PHY_U2_ON                (0x1<<15) //15:15
1917 +#define RG_SSUSB_DISABLE_PHY_U2_OFF               (0x1<<14) //14:14
1918 +#define RG_SSUSB_PRBS_EN                          (0x1<<13) //13:13
1919 +#define RG_SSUSB_BPSLOCK                          (0x1<<12) //12:12
1920 +#define RG_SSUSB_RTCOMCNT                         (0xf<<8) //11:8
1921 +#define RG_SSUSB_COMCNT                           (0xf<<4) //7:4
1922 +#define RG_SSUSB_PRBSEL_CALIB                     (0xf<<0) //3:0
1923 +
1924 +//U3D_PHYD_MIX1
1925 +#define RG_SSUSB_SLEEP_EN                         (0x1<<31) //31:31
1926 +#define RG_SSUSB_PRBSEL_PCS                       (0x7<<28) //30:28
1927 +#define RG_SSUSB_TXLFPS_PRD                       (0xf<<24) //27:24
1928 +#define RG_SSUSB_P_RX_P0S_CK                      (0x1<<23) //23:23
1929 +#define RG_SSUSB_P_TX_P0S_CK                      (0x1<<22) //22:22
1930 +#define RG_SSUSB_PDNCTL                           (0x3f<<16) //21:16
1931 +#define RG_SSUSB_TX_DRV_EN                        (0x1<<15) //15:15
1932 +#define RG_SSUSB_TX_DRV_SEL                       (0x1<<14) //14:14
1933 +#define RG_SSUSB_TX_DRV_DLY                       (0x3f<<8) //13:8
1934 +#define RG_SSUSB_BERT_EN                          (0x1<<7) //7:7
1935 +#define RG_SSUSB_SCP_TH                           (0x7<<4) //6:4
1936 +#define RG_SSUSB_SCP_EN                           (0x1<<3) //3:3
1937 +#define RG_SSUSB_RXANSIDEC_TEST                   (0x7<<0) //2:0
1938 +
1939 +//U3D_PHYD_LFPS0
1940 +#define RG_SSUSB_LFPS_PWD                         (0x1<<30) //30:30
1941 +#define RG_SSUSB_FORCE_LFPS_PWD                   (0x1<<29) //29:29
1942 +#define RG_SSUSB_RXLFPS_OVF                       (0x1f<<24) //28:24
1943 +#define RG_SSUSB_P3_ENTRY_SEL                     (0x1<<23) //23:23
1944 +#define RG_SSUSB_P3_ENTRY                         (0x1<<22) //22:22
1945 +#define RG_SSUSB_RXLFPS_CDRSEL                    (0x3<<20) //21:20
1946 +#define RG_SSUSB_RXLFPS_CDRTH                     (0xf<<16) //19:16
1947 +#define RG_SSUSB_LOCK5G_BLOCK                     (0x1<<15) //15:15
1948 +#define RG_SSUSB_TFIFO_EXT_D_SEL                  (0x1<<14) //14:14
1949 +#define RG_SSUSB_TFIFO_NO_EXTEND                  (0x1<<13) //13:13
1950 +#define RG_SSUSB_RXLFPS_LOB                       (0x1f<<8) //12:8
1951 +#define RG_SSUSB_TXLFPS_EN                        (0x1<<7) //7:7
1952 +#define RG_SSUSB_TXLFPS_SEL                       (0x1<<6) //6:6
1953 +#define RG_SSUSB_RXLFPS_CDRLOCK                   (0x1<<5) //5:5
1954 +#define RG_SSUSB_RXLFPS_UPB                       (0x1f<<0) //4:0
1955 +
1956 +//U3D_PHYD_LFPS1
1957 +#define RG_SSUSB_RX_IMP_BIAS                      (0xf<<28) //31:28
1958 +#define RG_SSUSB_TX_IMP_BIAS                      (0xf<<24) //27:24
1959 +#define RG_SSUSB_FWAKE_TH                         (0x3f<<16) //21:16
1960 +#define RG_SSUSB_RXLFPS_UDF                       (0x1f<<8) //12:8
1961 +#define RG_SSUSB_RXLFPS_P0IDLETH                  (0xff<<0) //7:0
1962 +
1963 +//U3D_PHYD_IMPCAL0
1964 +#define RG_SSUSB_FORCE_TX_IMPSEL                  (0x1<<31) //31:31
1965 +#define RG_SSUSB_TX_IMPCAL_EN                     (0x1<<30) //30:30
1966 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN               (0x1<<29) //29:29
1967 +#define RG_SSUSB_TX_IMPSEL                        (0x1f<<24) //28:24
1968 +#define RG_SSUSB_TX_IMPCAL_CALCYC                 (0x3f<<16) //21:16
1969 +#define RG_SSUSB_TX_IMPCAL_STBCYC                 (0x1f<<10) //14:10
1970 +#define RG_SSUSB_TX_IMPCAL_CYCCNT                 (0x3ff<<0) //9:0
1971 +
1972 +//U3D_PHYD_IMPCAL1
1973 +#define RG_SSUSB_FORCE_RX_IMPSEL                  (0x1<<31) //31:31
1974 +#define RG_SSUSB_RX_IMPCAL_EN                     (0x1<<30) //30:30
1975 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN               (0x1<<29) //29:29
1976 +#define RG_SSUSB_RX_IMPSEL                        (0x1f<<24) //28:24
1977 +#define RG_SSUSB_RX_IMPCAL_CALCYC                 (0x3f<<16) //21:16
1978 +#define RG_SSUSB_RX_IMPCAL_STBCYC                 (0x1f<<10) //14:10
1979 +#define RG_SSUSB_RX_IMPCAL_CYCCNT                 (0x3ff<<0) //9:0
1980 +
1981 +//U3D_PHYD_TXPLL0
1982 +#define RG_SSUSB_TXPLL_DDSEN_CYC                  (0x1f<<27) //31:27
1983 +#define RG_SSUSB_TXPLL_ON                         (0x1<<26) //26:26
1984 +#define RG_SSUSB_FORCE_TXPLLON                    (0x1<<25) //25:25
1985 +#define RG_SSUSB_TXPLL_STBCYC                     (0x1ff<<16) //24:16
1986 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC                (0xf<<12) //15:12
1987 +#define RG_SSUSB_TXPLL_NCPOEN_CYC                 (0x3<<10) //11:10
1988 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC                (0x7<<0) //2:0
1989 +
1990 +//U3D_PHYD_TXPLL1
1991 +#define RG_SSUSB_PLL_NCPO_EN                      (0x1<<31) //31:31
1992 +#define RG_SSUSB_PLL_FIFO_START_MAN               (0x1<<30) //30:30
1993 +#define RG_SSUSB_PLL_NCPO_CHG                     (0x1<<28) //28:28
1994 +#define RG_SSUSB_PLL_DDS_RSTB                     (0x1<<27) //27:27
1995 +#define RG_SSUSB_PLL_DDS_PWDB                     (0x1<<26) //26:26
1996 +#define RG_SSUSB_PLL_DDSEN                        (0x1<<25) //25:25
1997 +#define RG_SSUSB_PLL_AUTOK_VCO                    (0x1<<24) //24:24
1998 +#define RG_SSUSB_PLL_PWD                          (0x1<<23) //23:23
1999 +#define RG_SSUSB_RX_AFE_PWD                       (0x1<<22) //22:22
2000 +#define RG_SSUSB_PLL_TCADJ                        (0x3f<<16) //21:16
2001 +#define RG_SSUSB_FORCE_CDR_TCADJ                  (0x1<<15) //15:15
2002 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO              (0x1<<14) //14:14
2003 +#define RG_SSUSB_FORCE_CDR_PWD                    (0x1<<13) //13:13
2004 +#define RG_SSUSB_FORCE_PLL_NCPO_EN                (0x1<<12) //12:12
2005 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN         (0x1<<11) //11:11
2006 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG               (0x1<<9) //9:9
2007 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB               (0x1<<8) //8:8
2008 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB               (0x1<<7) //7:7
2009 +#define RG_SSUSB_FORCE_PLL_DDSEN                  (0x1<<6) //6:6
2010 +#define RG_SSUSB_FORCE_PLL_TCADJ                  (0x1<<5) //5:5
2011 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO              (0x1<<4) //4:4
2012 +#define RG_SSUSB_FORCE_PLL_PWD                    (0x1<<3) //3:3
2013 +#define RG_SSUSB_FLT_1_DISPERR_B                  (0x1<<2) //2:2
2014 +
2015 +//U3D_PHYD_TXPLL2
2016 +#define RG_SSUSB_TX_LFPS_EN                       (0x1<<31) //31:31
2017 +#define RG_SSUSB_FORCE_TX_LFPS_EN                 (0x1<<30) //30:30
2018 +#define RG_SSUSB_TX_LFPS                          (0x1<<29) //29:29
2019 +#define RG_SSUSB_FORCE_TX_LFPS                    (0x1<<28) //28:28
2020 +#define RG_SSUSB_RXPLL_STB                        (0x1<<27) //27:27
2021 +#define RG_SSUSB_TXPLL_STB                        (0x1<<26) //26:26
2022 +#define RG_SSUSB_FORCE_RXPLL_STB                  (0x1<<25) //25:25
2023 +#define RG_SSUSB_FORCE_TXPLL_STB                  (0x1<<24) //24:24
2024 +#define RG_SSUSB_RXPLL_REFCKSEL                   (0x1<<16) //16:16
2025 +#define RG_SSUSB_RXPLL_STBMODE                    (0x1<<11) //11:11
2026 +#define RG_SSUSB_RXPLL_ON                         (0x1<<10) //10:10
2027 +#define RG_SSUSB_FORCE_RXPLLON                    (0x1<<9) //9:9
2028 +#define RG_SSUSB_FORCE_RX_AFE_PWD                 (0x1<<8) //8:8
2029 +#define RG_SSUSB_CDR_AUTOK_VCO                    (0x1<<7) //7:7
2030 +#define RG_SSUSB_CDR_PWD                          (0x1<<6) //6:6
2031 +#define RG_SSUSB_CDR_TCADJ                        (0x3f<<0) //5:0
2032 +
2033 +//U3D_PHYD_FL0
2034 +#define RG_SSUSB_RX_FL_TARGET                     (0xffff<<16) //31:16
2035 +#define RG_SSUSB_RX_FL_CYCLECNT                   (0xffff<<0) //15:0
2036 +
2037 +//U3D_PHYD_MIX2
2038 +#define RG_SSUSB_RX_EQ_RST                        (0x1<<31) //31:31
2039 +#define RG_SSUSB_RX_EQ_RST_SEL                    (0x1<<30) //30:30
2040 +#define RG_SSUSB_RXVAL_RST                        (0x1<<29) //29:29
2041 +#define RG_SSUSB_RXVAL_CNT                        (0x1f<<24) //28:24
2042 +#define RG_SSUSB_CDROS_EN                         (0x1<<18) //18:18
2043 +#define RG_SSUSB_CDR_LCKOP                        (0x3<<16) //17:16
2044 +#define RG_SSUSB_RX_FL_LOCKTH                     (0xf<<8) //11:8
2045 +#define RG_SSUSB_RX_FL_OFFSET                     (0xff<<0) //7:0
2046 +
2047 +//U3D_PHYD_RX0
2048 +#define RG_SSUSB_T2RLB_BERTH                      (0xff<<24) //31:24
2049 +#define RG_SSUSB_T2RLB_PAT                        (0xff<<16) //23:16
2050 +#define RG_SSUSB_T2RLB_EN                         (0x1<<15) //15:15
2051 +#define RG_SSUSB_T2RLB_BPSCRAMB                   (0x1<<14) //14:14
2052 +#define RG_SSUSB_T2RLB_SERIAL                     (0x1<<13) //13:13
2053 +#define RG_SSUSB_T2RLB_MODE                       (0x3<<11) //12:11
2054 +#define RG_SSUSB_RX_SAOSC_EN                      (0x1<<10) //10:10
2055 +#define RG_SSUSB_RX_SAOSC_EN_SEL                  (0x1<<9) //9:9
2056 +#define RG_SSUSB_RX_DFE_OPTION                    (0x1<<8) //8:8
2057 +#define RG_SSUSB_RX_DFE_EN                        (0x1<<7) //7:7
2058 +#define RG_SSUSB_RX_DFE_EN_SEL                    (0x1<<6) //6:6
2059 +#define RG_SSUSB_RX_EQ_EN                         (0x1<<5) //5:5
2060 +#define RG_SSUSB_RX_EQ_EN_SEL                     (0x1<<4) //4:4
2061 +#define RG_SSUSB_RX_SAOSC_RST                     (0x1<<3) //3:3
2062 +#define RG_SSUSB_RX_SAOSC_RST_SEL                 (0x1<<2) //2:2
2063 +#define RG_SSUSB_RX_DFE_RST                       (0x1<<1) //1:1
2064 +#define RG_SSUSB_RX_DFE_RST_SEL                   (0x1<<0) //0:0
2065 +
2066 +//U3D_PHYD_T2RLB
2067 +#define RG_SSUSB_EQTRAIN_CH_MODE                  (0x1<<28) //28:28
2068 +#define RG_SSUSB_PRB_OUT_CPPAT                    (0x1<<27) //27:27
2069 +#define RG_SSUSB_BPANSIENC                        (0x1<<26) //26:26
2070 +#define RG_SSUSB_VALID_EN                         (0x1<<25) //25:25
2071 +#define RG_SSUSB_EBUF_SRST                        (0x1<<24) //24:24
2072 +#define RG_SSUSB_K_EMP                            (0xf<<20) //23:20
2073 +#define RG_SSUSB_K_FUL                            (0xf<<16) //19:16
2074 +#define RG_SSUSB_T2RLB_BDATRST                    (0xf<<12) //15:12
2075 +#define RG_SSUSB_P_T2RLB_SKP_EN                   (0x1<<10) //10:10
2076 +#define RG_SSUSB_T2RLB_PATMODE                    (0x3<<8) //9:8
2077 +#define RG_SSUSB_T2RLB_TSEQCNT                    (0xff<<0) //7:0
2078 +
2079 +//U3D_PHYD_CPPAT
2080 +#define RG_SSUSB_CPPAT_PROGRAM_EN                 (0x1<<24) //24:24
2081 +#define RG_SSUSB_CPPAT_TOZ                        (0x3<<21) //22:21
2082 +#define RG_SSUSB_CPPAT_PRBS_EN                    (0x1<<20) //20:20
2083 +#define RG_SSUSB_CPPAT_OUT_TMP2                   (0xf<<16) //19:16
2084 +#define RG_SSUSB_CPPAT_OUT_TMP1                   (0xff<<8) //15:8
2085 +#define RG_SSUSB_CPPAT_OUT_TMP0                   (0xff<<0) //7:0
2086 +
2087 +//U3D_PHYD_MIX3
2088 +#define RG_SSUSB_CDR_TCADJ_MINUS                  (0x1<<31) //31:31
2089 +#define RG_SSUSB_P_CDROS_EN                       (0x1<<30) //30:30
2090 +#define RG_SSUSB_P_P2_TX_DRV_DIS                  (0x1<<28) //28:28
2091 +#define RG_SSUSB_CDR_TCADJ_OFFSET                 (0x7<<24) //26:24
2092 +#define RG_SSUSB_PLL_TCADJ_MINUS                  (0x1<<23) //23:23
2093 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN            (0x1<<20) //20:20
2094 +#define RG_SSUSB_PLL_BIAS_LPF_EN                  (0x1<<19) //19:19
2095 +#define RG_SSUSB_PLL_TCADJ_OFFSET                 (0x7<<16) //18:16
2096 +#define RG_SSUSB_FORCE_PLL_SSCEN                  (0x1<<15) //15:15
2097 +#define RG_SSUSB_PLL_SSCEN                        (0x1<<14) //14:14
2098 +#define RG_SSUSB_FORCE_CDR_PI_PWD                 (0x1<<13) //13:13
2099 +#define RG_SSUSB_CDR_PI_PWD                       (0x1<<12) //12:12
2100 +#define RG_SSUSB_CDR_PI_MODE                      (0x1<<11) //11:11
2101 +#define RG_SSUSB_TXPLL_SSCEN_CYC                  (0x3ff<<0) //9:0
2102 +
2103 +//U3D_PHYD_EBUFCTL
2104 +#define RG_SSUSB_EBUFCTL                          (0xffffffff<<0) //31:0
2105 +
2106 +//U3D_PHYD_PIPE0
2107 +#define RG_SSUSB_RXTERMINATION                    (0x1<<30) //30:30
2108 +#define RG_SSUSB_RXEQTRAINING                     (0x1<<29) //29:29
2109 +#define RG_SSUSB_RXPOLARITY                       (0x1<<28) //28:28
2110 +#define RG_SSUSB_TXDEEMPH                         (0x3<<26) //27:26
2111 +#define RG_SSUSB_POWERDOWN                        (0x3<<24) //25:24
2112 +#define RG_SSUSB_TXONESZEROS                      (0x1<<23) //23:23
2113 +#define RG_SSUSB_TXELECIDLE                       (0x1<<22) //22:22
2114 +#define RG_SSUSB_TXDETECTRX                       (0x1<<21) //21:21
2115 +#define RG_SSUSB_PIPE_SEL                         (0x1<<20) //20:20
2116 +#define RG_SSUSB_TXDATAK                          (0xf<<16) //19:16
2117 +#define RG_SSUSB_CDR_STABLE_SEL                   (0x1<<15) //15:15
2118 +#define RG_SSUSB_CDR_STABLE                       (0x1<<14) //14:14
2119 +#define RG_SSUSB_CDR_RSTB_SEL                     (0x1<<13) //13:13
2120 +#define RG_SSUSB_CDR_RSTB                         (0x1<<12) //12:12
2121 +#define RG_SSUSB_P_ERROR_SEL                      (0x3<<4) //5:4
2122 +#define RG_SSUSB_TXMARGIN                         (0x7<<1) //3:1
2123 +#define RG_SSUSB_TXCOMPLIANCE                     (0x1<<0) //0:0
2124 +
2125 +//U3D_PHYD_PIPE1
2126 +#define RG_SSUSB_TXDATA                           (0xffffffff<<0) //31:0
2127 +
2128 +//U3D_PHYD_MIX4
2129 +#define RG_SSUSB_CDROS_CNT                        (0x3f<<24) //29:24
2130 +#define RG_SSUSB_T2RLB_BER_EN                     (0x1<<16) //16:16
2131 +#define RG_SSUSB_T2RLB_BER_RATE                   (0xffff<<0) //15:0
2132 +
2133 +//U3D_PHYD_CKGEN0
2134 +#define RG_SSUSB_RFIFO_IMPLAT                     (0x1<<27) //27:27
2135 +#define RG_SSUSB_TFIFO_PSEL                       (0x7<<24) //26:24
2136 +#define RG_SSUSB_CKGEN_PSEL                       (0x3<<8) //9:8
2137 +#define RG_SSUSB_RXCK_INV                         (0x1<<0) //0:0
2138 +
2139 +//U3D_PHYD_MIX5
2140 +#define RG_SSUSB_PRB_SEL                          (0xffff<<16) //31:16
2141 +#define RG_SSUSB_RXPLL_STBCYC                     (0x7ff<<0) //10:0
2142 +
2143 +//U3D_PHYD_RESERVED
2144 +#define RG_SSUSB_PHYD_RESERVE                     (0xffffffff<<0) //31:0
2145 +//#define RG_SSUSB_RX_SIGDET_SEL                    (0x1<<11)
2146 +//#define RG_SSUSB_RX_SIGDET_EN                     (0x1<<12)
2147 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL             (0x1<<9)
2148 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN              (0x1<<10)
2149 +
2150 +//U3D_PHYD_CDR0
2151 +#define RG_SSUSB_CDR_BIC_LTR                      (0xf<<28) //31:28
2152 +#define RG_SSUSB_CDR_BIC_LTD0                     (0xf<<24) //27:24
2153 +#define RG_SSUSB_CDR_BC_LTD1                      (0x1f<<16) //20:16
2154 +#define RG_SSUSB_CDR_BC_LTR                       (0x1f<<8) //12:8
2155 +#define RG_SSUSB_CDR_BC_LTD0                      (0x1f<<0) //4:0
2156 +
2157 +//U3D_PHYD_CDR1
2158 +#define RG_SSUSB_CDR_BIR_LTD1                     (0x1f<<24) //28:24
2159 +#define RG_SSUSB_CDR_BIR_LTR                      (0x1f<<16) //20:16
2160 +#define RG_SSUSB_CDR_BIR_LTD0                     (0x1f<<8) //12:8
2161 +#define RG_SSUSB_CDR_BW_SEL                       (0x3<<6) //7:6
2162 +#define RG_SSUSB_CDR_BIC_LTD1                     (0xf<<0) //3:0
2163 +
2164 +//U3D_PHYD_PLL_0
2165 +#define RG_SSUSB_FORCE_CDR_BAND_5G                (0x1<<28) //28:28
2166 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G              (0x1<<27) //27:27
2167 +#define RG_SSUSB_FORCE_PLL_BAND_5G                (0x1<<26) //26:26
2168 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G              (0x1<<25) //25:25
2169 +#define RG_SSUSB_P_EQ_T_SEL                       (0x3ff<<15) //24:15
2170 +#define RG_SSUSB_PLL_ISO_EN_CYC                   (0x3ff<<5) //14:5
2171 +#define RG_SSUSB_PLLBAND_RECAL                    (0x1<<4) //4:4
2172 +#define RG_SSUSB_PLL_DDS_ISO_EN                   (0x1<<3) //3:3
2173 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN             (0x1<<2) //2:2
2174 +#define RG_SSUSB_PLL_DDS_PWR_ON                   (0x1<<1) //1:1
2175 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON             (0x1<<0) //0:0
2176 +
2177 +//U3D_PHYD_PLL_1
2178 +#define RG_SSUSB_CDR_BAND_5G                      (0xff<<24) //31:24
2179 +#define RG_SSUSB_CDR_BAND_2P5G                    (0xff<<16) //23:16
2180 +#define RG_SSUSB_PLL_BAND_5G                      (0xff<<8) //15:8
2181 +#define RG_SSUSB_PLL_BAND_2P5G                    (0xff<<0) //7:0
2182 +
2183 +//U3D_PHYD_BCN_DET_1
2184 +#define RG_SSUSB_P_BCN_OBS_PRD                    (0xffff<<16) //31:16
2185 +#define RG_SSUSB_U_BCN_OBS_PRD                    (0xffff<<0) //15:0
2186 +
2187 +//U3D_PHYD_BCN_DET_2
2188 +#define RG_SSUSB_P_BCN_OBS_SEL                    (0xfff<<16) //27:16
2189 +#define RG_SSUSB_BCN_DET_DIS                      (0x1<<12) //12:12
2190 +#define RG_SSUSB_U_BCN_OBS_SEL                    (0xfff<<0) //11:0
2191 +
2192 +//U3D_EQ0
2193 +#define RG_SSUSB_EQ_DLHL_LFI                      (0x7f<<24) //30:24
2194 +#define RG_SSUSB_EQ_DHHL_LFI                      (0x7f<<16) //22:16
2195 +#define RG_SSUSB_EQ_DD0HOS_LFI                    (0x7f<<8) //14:8
2196 +#define RG_SSUSB_EQ_DD0LOS_LFI                    (0x7f<<0) //6:0
2197 +
2198 +//U3D_EQ1
2199 +#define RG_SSUSB_EQ_DD1HOS_LFI                    (0x7f<<24) //30:24
2200 +#define RG_SSUSB_EQ_DD1LOS_LFI                    (0x7f<<16) //22:16
2201 +#define RG_SSUSB_EQ_DE0OS_LFI                     (0x7f<<8) //14:8
2202 +#define RG_SSUSB_EQ_DE1OS_LFI                     (0x7f<<0) //6:0
2203 +
2204 +//U3D_EQ2
2205 +#define RG_SSUSB_EQ_DLHLOS_LFI                    (0x7f<<24) //30:24
2206 +#define RG_SSUSB_EQ_DHHLOS_LFI                    (0x7f<<16) //22:16
2207 +#define RG_SSUSB_EQ_STOPTIME                      (0x1<<14) //14:14
2208 +#define RG_SSUSB_EQ_DHHL_LF_SEL                   (0x7<<11) //13:11
2209 +#define RG_SSUSB_EQ_DSAOS_LF_SEL                  (0x7<<8) //10:8
2210 +#define RG_SSUSB_EQ_STARTTIME                     (0x3<<6) //7:6
2211 +#define RG_SSUSB_EQ_DLEQ_LF_SEL                   (0x7<<3) //5:3
2212 +#define RG_SSUSB_EQ_DLHL_LF_SEL                   (0x7<<0) //2:0
2213 +
2214 +//U3D_EQ3
2215 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2                 (0xf<<28) //31:28
2216 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1                 (0xf<<24) //27:24
2217 +#define RG_SSUSB_EQ_DEYE0OS_LFI                   (0x7f<<16) //22:16
2218 +#define RG_SSUSB_EQ_DEYE1OS_LFI                   (0x7f<<8) //14:8
2219 +#define RG_SSUSB_EQ_TRI_DET_EN                    (0x1<<7) //7:7
2220 +#define RG_SSUSB_EQ_TRI_DET_TH                    (0x7f<<0) //6:0
2221 +
2222 +//U3D_EQ_EYE0
2223 +#define RG_SSUSB_EQ_EYE_XOFFSET                   (0x7f<<25) //31:25
2224 +#define RG_SSUSB_EQ_EYE_MON_EN                    (0x1<<24) //24:24
2225 +#define RG_SSUSB_EQ_EYE0_Y                        (0x7f<<16) //22:16
2226 +#define RG_SSUSB_EQ_EYE1_Y                        (0x7f<<8) //14:8
2227 +#define RG_SSUSB_EQ_PILPO_ROUT                    (0x1<<7) //7:7
2228 +#define RG_SSUSB_EQ_PI_KPGAIN                     (0x7<<4) //6:4
2229 +#define RG_SSUSB_EQ_EYE_CNT_EN                    (0x1<<3) //3:3
2230 +
2231 +//U3D_EQ_EYE1
2232 +#define RG_SSUSB_EQ_SIGDET                        (0x7f<<24) //30:24
2233 +#define RG_SSUSB_EQ_EYE_MASK                      (0x3ff<<7) //16:7
2234 +
2235 +//U3D_EQ_EYE2
2236 +#define RG_SSUSB_EQ_RX500M_CK_SEL                 (0x1<<31) //31:31
2237 +#define RG_SSUSB_EQ_SD_CNT1                       (0x3f<<24) //29:24
2238 +#define RG_SSUSB_EQ_ISIFLAG_SEL                   (0x3<<22) //23:22
2239 +#define RG_SSUSB_EQ_SD_CNT0                       (0x3f<<16) //21:16
2240 +
2241 +//U3D_EQ_DFE0
2242 +#define RG_SSUSB_EQ_LEQMAX                        (0xf<<28) //31:28
2243 +#define RG_SSUSB_EQ_DFEX_EN                       (0x1<<27) //27:27
2244 +#define RG_SSUSB_EQ_DFEX_LF_SEL                   (0x7<<24) //26:24
2245 +#define RG_SSUSB_EQ_CHK_EYE_H                     (0x1<<23) //23:23
2246 +#define RG_SSUSB_EQ_PIEYE_INI                     (0x7f<<16) //22:16
2247 +#define RG_SSUSB_EQ_PI90_INI                      (0x7f<<8) //14:8
2248 +#define RG_SSUSB_EQ_PI0_INI                       (0x7f<<0) //6:0
2249 +
2250 +//U3D_EQ_DFE1
2251 +#define RG_SSUSB_EQ_REV                           (0xffff<<16) //31:16
2252 +#define RG_SSUSB_EQ_DFEYEN_DUR                    (0x7<<12) //14:12
2253 +#define RG_SSUSB_EQ_DFEXEN_DUR                    (0x7<<8) //10:8
2254 +#define RG_SSUSB_EQ_DFEX_RST                      (0x1<<7) //7:7
2255 +#define RG_SSUSB_EQ_GATED_RXD_B                   (0x1<<6) //6:6
2256 +#define RG_SSUSB_EQ_PI90CK_SEL                    (0x3<<4) //5:4
2257 +#define RG_SSUSB_EQ_DFEX_DIS                      (0x1<<2) //2:2
2258 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS               (0x1<<1) //1:1
2259 +#define RG_SSUSB_EQ_DFEXEN_SEL                    (0x1<<0) //0:0
2260 +
2261 +//U3D_EQ_DFE2
2262 +#define RG_SSUSB_EQ_MON_SEL                       (0x1f<<24) //28:24
2263 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT                 (0x7<<16) //18:16
2264 +#define RG_SSUSB_EQ_DLEQOS_LFI                    (0x1f<<8) //12:8
2265 +#define RG_SSUSB_EQ_LEQ_STOP_TO                   (0x3<<0) //1:0
2266 +
2267 +//U3D_EQ_DFE3
2268 +#define RG_SSUSB_EQ_RESERVED                      (0xffffffff<<0) //31:0
2269 +
2270 +//U3D_PHYD_MON0
2271 +#define RGS_SSUSB_BERT_BERC                       (0xffff<<16) //31:16
2272 +#define RGS_SSUSB_LFPS                            (0xf<<12) //15:12
2273 +#define RGS_SSUSB_TRAINDEC                        (0x7<<8) //10:8
2274 +#define RGS_SSUSB_SCP_PAT                         (0xff<<0) //7:0
2275 +
2276 +//U3D_PHYD_MON1
2277 +#define RGS_SSUSB_RX_FL_OUT                       (0xffff<<0) //15:0
2278 +
2279 +//U3D_PHYD_MON2
2280 +#define RGS_SSUSB_T2RLB_ERRCNT                    (0xffff<<16) //31:16
2281 +#define RGS_SSUSB_RETRACK                         (0xf<<12) //15:12
2282 +#define RGS_SSUSB_RXPLL_LOCK                      (0x1<<10) //10:10
2283 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D               (0x1<<9) //9:9
2284 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D               (0x1<<8) //8:8
2285 +#define RGS_SSUSB_PDNCTL                          (0xff<<0) //7:0
2286 +
2287 +//U3D_PHYD_MON3
2288 +#define RGS_SSUSB_TSEQ_ERRCNT                     (0xffff<<16) //31:16
2289 +#define RGS_SSUSB_PRBS_ERRCNT                     (0xffff<<0) //15:0
2290 +
2291 +//U3D_PHYD_MON4
2292 +#define RGS_SSUSB_RX_LSLOCK_CNT                   (0xf<<24) //27:24
2293 +#define RGS_SSUSB_SCP_DETCNT                      (0xff<<16) //23:16
2294 +#define RGS_SSUSB_TSEQ_DETCNT                     (0xffff<<0) //15:0
2295 +
2296 +//U3D_PHYD_MON5
2297 +#define RGS_SSUSB_EBUFMSG                         (0xffff<<16) //31:16
2298 +#define RGS_SSUSB_BERT_LOCK                       (0x1<<15) //15:15
2299 +#define RGS_SSUSB_SCP_DET                         (0x1<<14) //14:14
2300 +#define RGS_SSUSB_TSEQ_DET                        (0x1<<13) //13:13
2301 +#define RGS_SSUSB_EBUF_UDF                        (0x1<<12) //12:12
2302 +#define RGS_SSUSB_EBUF_OVF                        (0x1<<11) //11:11
2303 +#define RGS_SSUSB_PRBS_PASSTH                     (0x1<<10) //10:10
2304 +#define RGS_SSUSB_PRBS_PASS                       (0x1<<9) //9:9
2305 +#define RGS_SSUSB_PRBS_LOCK                       (0x1<<8) //8:8
2306 +#define RGS_SSUSB_T2RLB_ERR                       (0x1<<6) //6:6
2307 +#define RGS_SSUSB_T2RLB_PASSTH                    (0x1<<5) //5:5
2308 +#define RGS_SSUSB_T2RLB_PASS                      (0x1<<4) //4:4
2309 +#define RGS_SSUSB_T2RLB_LOCK                      (0x1<<3) //3:3
2310 +#define RGS_SSUSB_RX_IMPCAL_DONE                  (0x1<<2) //2:2
2311 +#define RGS_SSUSB_TX_IMPCAL_DONE                  (0x1<<1) //1:1
2312 +#define RGS_SSUSB_RXDETECTED                      (0x1<<0) //0:0
2313 +
2314 +//U3D_PHYD_MON6
2315 +#define RGS_SSUSB_SIGCAL_DONE                     (0x1<<30) //30:30
2316 +#define RGS_SSUSB_SIGCAL_CAL_OUT                  (0x1<<29) //29:29
2317 +#define RGS_SSUSB_SIGCAL_OFFSET                   (0x1f<<24) //28:24
2318 +#define RGS_SSUSB_RX_IMP_SEL                      (0x1f<<16) //20:16
2319 +#define RGS_SSUSB_TX_IMP_SEL                      (0x1f<<8) //12:8
2320 +#define RGS_SSUSB_TFIFO_MSG                       (0xf<<4) //7:4
2321 +#define RGS_SSUSB_RFIFO_MSG                       (0xf<<0) //3:0
2322 +
2323 +//U3D_PHYD_MON7
2324 +#define RGS_SSUSB_FT_OUT                          (0xff<<8) //15:8
2325 +#define RGS_SSUSB_PRB_OUT                         (0xff<<0) //7:0
2326 +
2327 +//U3D_PHYA_RX_MON0
2328 +#define RGS_SSUSB_EQ_DCLEQ                        (0xf<<24) //27:24
2329 +#define RGS_SSUSB_EQ_DCD0H                        (0x7f<<16) //22:16
2330 +#define RGS_SSUSB_EQ_DCD0L                        (0x7f<<8) //14:8
2331 +#define RGS_SSUSB_EQ_DCD1H                        (0x7f<<0) //6:0
2332 +
2333 +//U3D_PHYA_RX_MON1
2334 +#define RGS_SSUSB_EQ_DCD1L                        (0x7f<<24) //30:24
2335 +#define RGS_SSUSB_EQ_DCE0                         (0x7f<<16) //22:16
2336 +#define RGS_SSUSB_EQ_DCE1                         (0x7f<<8) //14:8
2337 +#define RGS_SSUSB_EQ_DCHHL                        (0x7f<<0) //6:0
2338 +
2339 +//U3D_PHYA_RX_MON2
2340 +#define RGS_SSUSB_EQ_LEQ_STOP                     (0x1<<31) //31:31
2341 +#define RGS_SSUSB_EQ_DCLHL                        (0x7f<<24) //30:24
2342 +#define RGS_SSUSB_EQ_STATUS                       (0xff<<16) //23:16
2343 +#define RGS_SSUSB_EQ_DCEYE0                       (0x7f<<8) //14:8
2344 +#define RGS_SSUSB_EQ_DCEYE1                       (0x7f<<0) //6:0
2345 +
2346 +//U3D_PHYA_RX_MON3
2347 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0         (0xfffff<<0) //19:0
2348 +
2349 +//U3D_PHYA_RX_MON4
2350 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1         (0xfffff<<0) //19:0
2351 +
2352 +//U3D_PHYA_RX_MON5
2353 +#define RGS_SSUSB_EQ_DCLEQOS                      (0x1f<<8) //12:8
2354 +#define RGS_SSUSB_EQ_EYE_CNT_RDY                  (0x1<<7) //7:7
2355 +#define RGS_SSUSB_EQ_PILPO                        (0x7f<<0) //6:0
2356 +
2357 +//U3D_PHYD_CPPAT2
2358 +#define RG_SSUSB_CPPAT_OUT_H_TMP2                 (0xf<<16) //19:16
2359 +#define RG_SSUSB_CPPAT_OUT_H_TMP1                 (0xff<<8) //15:8
2360 +#define RG_SSUSB_CPPAT_OUT_H_TMP0                 (0xff<<0) //7:0
2361 +
2362 +//U3D_EQ_EYE3
2363 +#define RG_SSUSB_EQ_LEQ_SHIFT                     (0x7<<24) //26:24
2364 +#define RG_SSUSB_EQ_EYE_CNT                       (0xfffff<<0) //19:0
2365 +
2366 +//U3D_KBAND_OUT
2367 +#define RGS_SSUSB_CDR_BAND_5G                     (0xff<<24) //31:24
2368 +#define RGS_SSUSB_CDR_BAND_2P5G                   (0xff<<16) //23:16
2369 +#define RGS_SSUSB_PLL_BAND_5G                     (0xff<<8) //15:8
2370 +#define RGS_SSUSB_PLL_BAND_2P5G                   (0xff<<0) //7:0
2371 +
2372 +//U3D_KBAND_OUT1
2373 +#define RGS_SSUSB_CDR_VCOCAL_FAIL                 (0x1<<24) //24:24
2374 +#define RGS_SSUSB_CDR_VCOCAL_STATE                (0xff<<16) //23:16
2375 +#define RGS_SSUSB_PLL_VCOCAL_FAIL                 (0x1<<8) //8:8
2376 +#define RGS_SSUSB_PLL_VCOCAL_STATE                (0xff<<0) //7:0
2377 +
2378 +
2379 +/* OFFSET */
2380 +
2381 +//U3D_PHYD_MIX0
2382 +#define RG_SSUSB_P_P3_TX_NG_OFST                  (31)
2383 +#define RG_SSUSB_TSEQ_EN_OFST                     (30)
2384 +#define RG_SSUSB_TSEQ_POLEN_OFST                  (29)
2385 +#define RG_SSUSB_TSEQ_POL_OFST                    (28)
2386 +#define RG_SSUSB_P_P3_PCLK_NG_OFST                (27)
2387 +#define RG_SSUSB_TSEQ_TH_OFST                     (24)
2388 +#define RG_SSUSB_PRBS_BERTH_OFST                  (16)
2389 +#define RG_SSUSB_DISABLE_PHY_U2_ON_OFST           (15)
2390 +#define RG_SSUSB_DISABLE_PHY_U2_OFF_OFST          (14)
2391 +#define RG_SSUSB_PRBS_EN_OFST                     (13)
2392 +#define RG_SSUSB_BPSLOCK_OFST                     (12)
2393 +#define RG_SSUSB_RTCOMCNT_OFST                    (8)
2394 +#define RG_SSUSB_COMCNT_OFST                      (4)
2395 +#define RG_SSUSB_PRBSEL_CALIB_OFST                (0)
2396 +
2397 +//U3D_PHYD_MIX1
2398 +#define RG_SSUSB_SLEEP_EN_OFST                    (31)
2399 +#define RG_SSUSB_PRBSEL_PCS_OFST                  (28)
2400 +#define RG_SSUSB_TXLFPS_PRD_OFST                  (24)
2401 +#define RG_SSUSB_P_RX_P0S_CK_OFST                 (23)
2402 +#define RG_SSUSB_P_TX_P0S_CK_OFST                 (22)
2403 +#define RG_SSUSB_PDNCTL_OFST                      (16)
2404 +#define RG_SSUSB_TX_DRV_EN_OFST                   (15)
2405 +#define RG_SSUSB_TX_DRV_SEL_OFST                  (14)
2406 +#define RG_SSUSB_TX_DRV_DLY_OFST                  (8)
2407 +#define RG_SSUSB_BERT_EN_OFST                     (7)
2408 +#define RG_SSUSB_SCP_TH_OFST                      (4)
2409 +#define RG_SSUSB_SCP_EN_OFST                      (3)
2410 +#define RG_SSUSB_RXANSIDEC_TEST_OFST              (0)
2411 +
2412 +//U3D_PHYD_LFPS0
2413 +#define RG_SSUSB_LFPS_PWD_OFST                    (30)
2414 +#define RG_SSUSB_FORCE_LFPS_PWD_OFST              (29)
2415 +#define RG_SSUSB_RXLFPS_OVF_OFST                  (24)
2416 +#define RG_SSUSB_P3_ENTRY_SEL_OFST                (23)
2417 +#define RG_SSUSB_P3_ENTRY_OFST                    (22)
2418 +#define RG_SSUSB_RXLFPS_CDRSEL_OFST               (20)
2419 +#define RG_SSUSB_RXLFPS_CDRTH_OFST                (16)
2420 +#define RG_SSUSB_LOCK5G_BLOCK_OFST                (15)
2421 +#define RG_SSUSB_TFIFO_EXT_D_SEL_OFST             (14)
2422 +#define RG_SSUSB_TFIFO_NO_EXTEND_OFST             (13)
2423 +#define RG_SSUSB_RXLFPS_LOB_OFST                  (8)
2424 +#define RG_SSUSB_TXLFPS_EN_OFST                   (7)
2425 +#define RG_SSUSB_TXLFPS_SEL_OFST                  (6)
2426 +#define RG_SSUSB_RXLFPS_CDRLOCK_OFST              (5)
2427 +#define RG_SSUSB_RXLFPS_UPB_OFST                  (0)
2428 +
2429 +//U3D_PHYD_LFPS1
2430 +#define RG_SSUSB_RX_IMP_BIAS_OFST                 (28)
2431 +#define RG_SSUSB_TX_IMP_BIAS_OFST                 (24)
2432 +#define RG_SSUSB_FWAKE_TH_OFST                    (16)
2433 +#define RG_SSUSB_RXLFPS_UDF_OFST                  (8)
2434 +#define RG_SSUSB_RXLFPS_P0IDLETH_OFST             (0)
2435 +
2436 +//U3D_PHYD_IMPCAL0
2437 +#define RG_SSUSB_FORCE_TX_IMPSEL_OFST             (31)
2438 +#define RG_SSUSB_TX_IMPCAL_EN_OFST                (30)
2439 +#define RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST          (29)
2440 +#define RG_SSUSB_TX_IMPSEL_OFST                   (24)
2441 +#define RG_SSUSB_TX_IMPCAL_CALCYC_OFST            (16)
2442 +#define RG_SSUSB_TX_IMPCAL_STBCYC_OFST            (10)
2443 +#define RG_SSUSB_TX_IMPCAL_CYCCNT_OFST            (0)
2444 +
2445 +//U3D_PHYD_IMPCAL1
2446 +#define RG_SSUSB_FORCE_RX_IMPSEL_OFST             (31)
2447 +#define RG_SSUSB_RX_IMPCAL_EN_OFST                (30)
2448 +#define RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST          (29)
2449 +#define RG_SSUSB_RX_IMPSEL_OFST                   (24)
2450 +#define RG_SSUSB_RX_IMPCAL_CALCYC_OFST            (16)
2451 +#define RG_SSUSB_RX_IMPCAL_STBCYC_OFST            (10)
2452 +#define RG_SSUSB_RX_IMPCAL_CYCCNT_OFST            (0)
2453 +
2454 +//U3D_PHYD_TXPLL0
2455 +#define RG_SSUSB_TXPLL_DDSEN_CYC_OFST             (27)
2456 +#define RG_SSUSB_TXPLL_ON_OFST                    (26)
2457 +#define RG_SSUSB_FORCE_TXPLLON_OFST               (25)
2458 +#define RG_SSUSB_TXPLL_STBCYC_OFST                (16)
2459 +#define RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST           (12)
2460 +#define RG_SSUSB_TXPLL_NCPOEN_CYC_OFST            (10)
2461 +#define RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST           (0)
2462 +
2463 +//U3D_PHYD_TXPLL1
2464 +#define RG_SSUSB_PLL_NCPO_EN_OFST                 (31)
2465 +#define RG_SSUSB_PLL_FIFO_START_MAN_OFST          (30)
2466 +#define RG_SSUSB_PLL_NCPO_CHG_OFST                (28)
2467 +#define RG_SSUSB_PLL_DDS_RSTB_OFST                (27)
2468 +#define RG_SSUSB_PLL_DDS_PWDB_OFST                (26)
2469 +#define RG_SSUSB_PLL_DDSEN_OFST                   (25)
2470 +#define RG_SSUSB_PLL_AUTOK_VCO_OFST               (24)
2471 +#define RG_SSUSB_PLL_PWD_OFST                     (23)
2472 +#define RG_SSUSB_RX_AFE_PWD_OFST                  (22)
2473 +#define RG_SSUSB_PLL_TCADJ_OFST                   (16)
2474 +#define RG_SSUSB_FORCE_CDR_TCADJ_OFST             (15)
2475 +#define RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST         (14)
2476 +#define RG_SSUSB_FORCE_CDR_PWD_OFST               (13)
2477 +#define RG_SSUSB_FORCE_PLL_NCPO_EN_OFST           (12)
2478 +#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST    (11)
2479 +#define RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST          (9)
2480 +#define RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST          (8)
2481 +#define RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST          (7)
2482 +#define RG_SSUSB_FORCE_PLL_DDSEN_OFST             (6)
2483 +#define RG_SSUSB_FORCE_PLL_TCADJ_OFST             (5)
2484 +#define RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST         (4)
2485 +#define RG_SSUSB_FORCE_PLL_PWD_OFST               (3)
2486 +#define RG_SSUSB_FLT_1_DISPERR_B_OFST             (2)
2487 +
2488 +//U3D_PHYD_TXPLL2
2489 +#define RG_SSUSB_TX_LFPS_EN_OFST                  (31)
2490 +#define RG_SSUSB_FORCE_TX_LFPS_EN_OFST            (30)
2491 +#define RG_SSUSB_TX_LFPS_OFST                     (29)
2492 +#define RG_SSUSB_FORCE_TX_LFPS_OFST               (28)
2493 +#define RG_SSUSB_RXPLL_STB_OFST                   (27)
2494 +#define RG_SSUSB_TXPLL_STB_OFST                   (26)
2495 +#define RG_SSUSB_FORCE_RXPLL_STB_OFST             (25)
2496 +#define RG_SSUSB_FORCE_TXPLL_STB_OFST             (24)
2497 +#define RG_SSUSB_RXPLL_REFCKSEL_OFST              (16)
2498 +#define RG_SSUSB_RXPLL_STBMODE_OFST               (11)
2499 +#define RG_SSUSB_RXPLL_ON_OFST                    (10)
2500 +#define RG_SSUSB_FORCE_RXPLLON_OFST               (9)
2501 +#define RG_SSUSB_FORCE_RX_AFE_PWD_OFST            (8)
2502 +#define RG_SSUSB_CDR_AUTOK_VCO_OFST               (7)
2503 +#define RG_SSUSB_CDR_PWD_OFST                     (6)
2504 +#define RG_SSUSB_CDR_TCADJ_OFST                   (0)
2505 +
2506 +//U3D_PHYD_FL0
2507 +#define RG_SSUSB_RX_FL_TARGET_OFST                (16)
2508 +#define RG_SSUSB_RX_FL_CYCLECNT_OFST              (0)
2509 +
2510 +//U3D_PHYD_MIX2
2511 +#define RG_SSUSB_RX_EQ_RST_OFST                   (31)
2512 +#define RG_SSUSB_RX_EQ_RST_SEL_OFST               (30)
2513 +#define RG_SSUSB_RXVAL_RST_OFST                   (29)
2514 +#define RG_SSUSB_RXVAL_CNT_OFST                   (24)
2515 +#define RG_SSUSB_CDROS_EN_OFST                    (18)
2516 +#define RG_SSUSB_CDR_LCKOP_OFST                   (16)
2517 +#define RG_SSUSB_RX_FL_LOCKTH_OFST                (8)
2518 +#define RG_SSUSB_RX_FL_OFFSET_OFST                (0)
2519 +
2520 +//U3D_PHYD_RX0
2521 +#define RG_SSUSB_T2RLB_BERTH_OFST                 (24)
2522 +#define RG_SSUSB_T2RLB_PAT_OFST                   (16)
2523 +#define RG_SSUSB_T2RLB_EN_OFST                    (15)
2524 +#define RG_SSUSB_T2RLB_BPSCRAMB_OFST              (14)
2525 +#define RG_SSUSB_T2RLB_SERIAL_OFST                (13)
2526 +#define RG_SSUSB_T2RLB_MODE_OFST                  (11)
2527 +#define RG_SSUSB_RX_SAOSC_EN_OFST                 (10)
2528 +#define RG_SSUSB_RX_SAOSC_EN_SEL_OFST             (9)
2529 +#define RG_SSUSB_RX_DFE_OPTION_OFST               (8)
2530 +#define RG_SSUSB_RX_DFE_EN_OFST                   (7)
2531 +#define RG_SSUSB_RX_DFE_EN_SEL_OFST               (6)
2532 +#define RG_SSUSB_RX_EQ_EN_OFST                    (5)
2533 +#define RG_SSUSB_RX_EQ_EN_SEL_OFST                (4)
2534 +#define RG_SSUSB_RX_SAOSC_RST_OFST                (3)
2535 +#define RG_SSUSB_RX_SAOSC_RST_SEL_OFST            (2)
2536 +#define RG_SSUSB_RX_DFE_RST_OFST                  (1)
2537 +#define RG_SSUSB_RX_DFE_RST_SEL_OFST              (0)
2538 +
2539 +//U3D_PHYD_T2RLB
2540 +#define RG_SSUSB_EQTRAIN_CH_MODE_OFST             (28)
2541 +#define RG_SSUSB_PRB_OUT_CPPAT_OFST               (27)
2542 +#define RG_SSUSB_BPANSIENC_OFST                   (26)
2543 +#define RG_SSUSB_VALID_EN_OFST                    (25)
2544 +#define RG_SSUSB_EBUF_SRST_OFST                   (24)
2545 +#define RG_SSUSB_K_EMP_OFST                       (20)
2546 +#define RG_SSUSB_K_FUL_OFST                       (16)
2547 +#define RG_SSUSB_T2RLB_BDATRST_OFST               (12)
2548 +#define RG_SSUSB_P_T2RLB_SKP_EN_OFST              (10)
2549 +#define RG_SSUSB_T2RLB_PATMODE_OFST               (8)
2550 +#define RG_SSUSB_T2RLB_TSEQCNT_OFST               (0)
2551 +
2552 +//U3D_PHYD_CPPAT
2553 +#define RG_SSUSB_CPPAT_PROGRAM_EN_OFST            (24)
2554 +#define RG_SSUSB_CPPAT_TOZ_OFST                   (21)
2555 +#define RG_SSUSB_CPPAT_PRBS_EN_OFST               (20)
2556 +#define RG_SSUSB_CPPAT_OUT_TMP2_OFST              (16)
2557 +#define RG_SSUSB_CPPAT_OUT_TMP1_OFST              (8)
2558 +#define RG_SSUSB_CPPAT_OUT_TMP0_OFST              (0)
2559 +
2560 +//U3D_PHYD_MIX3
2561 +#define RG_SSUSB_CDR_TCADJ_MINUS_OFST             (31)
2562 +#define RG_SSUSB_P_CDROS_EN_OFST                  (30)
2563 +#define RG_SSUSB_P_P2_TX_DRV_DIS_OFST             (28)
2564 +#define RG_SSUSB_CDR_TCADJ_OFFSET_OFST            (24)
2565 +#define RG_SSUSB_PLL_TCADJ_MINUS_OFST             (23)
2566 +#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST       (20)
2567 +#define RG_SSUSB_PLL_BIAS_LPF_EN_OFST             (19)
2568 +#define RG_SSUSB_PLL_TCADJ_OFFSET_OFST            (16)
2569 +#define RG_SSUSB_FORCE_PLL_SSCEN_OFST             (15)
2570 +#define RG_SSUSB_PLL_SSCEN_OFST                   (14)
2571 +#define RG_SSUSB_FORCE_CDR_PI_PWD_OFST            (13)
2572 +#define RG_SSUSB_CDR_PI_PWD_OFST                  (12)
2573 +#define RG_SSUSB_CDR_PI_MODE_OFST                 (11)
2574 +#define RG_SSUSB_TXPLL_SSCEN_CYC_OFST             (0)
2575 +
2576 +//U3D_PHYD_EBUFCTL
2577 +#define RG_SSUSB_EBUFCTL_OFST                     (0)
2578 +
2579 +//U3D_PHYD_PIPE0
2580 +#define RG_SSUSB_RXTERMINATION_OFST               (30)
2581 +#define RG_SSUSB_RXEQTRAINING_OFST                (29)
2582 +#define RG_SSUSB_RXPOLARITY_OFST                  (28)
2583 +#define RG_SSUSB_TXDEEMPH_OFST                    (26)
2584 +#define RG_SSUSB_POWERDOWN_OFST                   (24)
2585 +#define RG_SSUSB_TXONESZEROS_OFST                 (23)
2586 +#define RG_SSUSB_TXELECIDLE_OFST                  (22)
2587 +#define RG_SSUSB_TXDETECTRX_OFST                  (21)
2588 +#define RG_SSUSB_PIPE_SEL_OFST                    (20)
2589 +#define RG_SSUSB_TXDATAK_OFST                     (16)
2590 +#define RG_SSUSB_CDR_STABLE_SEL_OFST              (15)
2591 +#define RG_SSUSB_CDR_STABLE_OFST                  (14)
2592 +#define RG_SSUSB_CDR_RSTB_SEL_OFST                (13)
2593 +#define RG_SSUSB_CDR_RSTB_OFST                    (12)
2594 +#define RG_SSUSB_P_ERROR_SEL_OFST                 (4)
2595 +#define RG_SSUSB_TXMARGIN_OFST                    (1)
2596 +#define RG_SSUSB_TXCOMPLIANCE_OFST                (0)
2597 +
2598 +//U3D_PHYD_PIPE1
2599 +#define RG_SSUSB_TXDATA_OFST                      (0)
2600 +
2601 +//U3D_PHYD_MIX4
2602 +#define RG_SSUSB_CDROS_CNT_OFST                   (24)
2603 +#define RG_SSUSB_T2RLB_BER_EN_OFST                (16)
2604 +#define RG_SSUSB_T2RLB_BER_RATE_OFST              (0)
2605 +
2606 +//U3D_PHYD_CKGEN0
2607 +#define RG_SSUSB_RFIFO_IMPLAT_OFST                (27)
2608 +#define RG_SSUSB_TFIFO_PSEL_OFST                  (24)
2609 +#define RG_SSUSB_CKGEN_PSEL_OFST                  (8)
2610 +#define RG_SSUSB_RXCK_INV_OFST                    (0)
2611 +
2612 +//U3D_PHYD_MIX5
2613 +#define RG_SSUSB_PRB_SEL_OFST                     (16)
2614 +#define RG_SSUSB_RXPLL_STBCYC_OFST                (0)
2615 +
2616 +//U3D_PHYD_RESERVED
2617 +#define RG_SSUSB_PHYD_RESERVE_OFST                (0)
2618 +//#define RG_SSUSB_RX_SIGDET_SEL_OFST               (11)
2619 +//#define RG_SSUSB_RX_SIGDET_EN_OFST                (12)
2620 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL_OFST        (9)
2621 +//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN_OFST         (10)
2622 +
2623 +//U3D_PHYD_CDR0
2624 +#define RG_SSUSB_CDR_BIC_LTR_OFST                 (28)
2625 +#define RG_SSUSB_CDR_BIC_LTD0_OFST                (24)
2626 +#define RG_SSUSB_CDR_BC_LTD1_OFST                 (16)
2627 +#define RG_SSUSB_CDR_BC_LTR_OFST                  (8)
2628 +#define RG_SSUSB_CDR_BC_LTD0_OFST                 (0)
2629 +
2630 +//U3D_PHYD_CDR1
2631 +#define RG_SSUSB_CDR_BIR_LTD1_OFST                (24)
2632 +#define RG_SSUSB_CDR_BIR_LTR_OFST                 (16)
2633 +#define RG_SSUSB_CDR_BIR_LTD0_OFST                (8)
2634 +#define RG_SSUSB_CDR_BW_SEL_OFST                  (6)
2635 +#define RG_SSUSB_CDR_BIC_LTD1_OFST                (0)
2636 +
2637 +//U3D_PHYD_PLL_0
2638 +#define RG_SSUSB_FORCE_CDR_BAND_5G_OFST           (28)
2639 +#define RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST         (27)
2640 +#define RG_SSUSB_FORCE_PLL_BAND_5G_OFST           (26)
2641 +#define RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST         (25)
2642 +#define RG_SSUSB_P_EQ_T_SEL_OFST                  (15)
2643 +#define RG_SSUSB_PLL_ISO_EN_CYC_OFST              (5)
2644 +#define RG_SSUSB_PLLBAND_RECAL_OFST               (4)
2645 +#define RG_SSUSB_PLL_DDS_ISO_EN_OFST              (3)
2646 +#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST        (2)
2647 +#define RG_SSUSB_PLL_DDS_PWR_ON_OFST              (1)
2648 +#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST        (0)
2649 +
2650 +//U3D_PHYD_PLL_1
2651 +#define RG_SSUSB_CDR_BAND_5G_OFST                 (24)
2652 +#define RG_SSUSB_CDR_BAND_2P5G_OFST               (16)
2653 +#define RG_SSUSB_PLL_BAND_5G_OFST                 (8)
2654 +#define RG_SSUSB_PLL_BAND_2P5G_OFST               (0)
2655 +
2656 +//U3D_PHYD_BCN_DET_1
2657 +#define RG_SSUSB_P_BCN_OBS_PRD_OFST               (16)
2658 +#define RG_SSUSB_U_BCN_OBS_PRD_OFST               (0)
2659 +
2660 +//U3D_PHYD_BCN_DET_2
2661 +#define RG_SSUSB_P_BCN_OBS_SEL_OFST               (16)
2662 +#define RG_SSUSB_BCN_DET_DIS_OFST                 (12)
2663 +#define RG_SSUSB_U_BCN_OBS_SEL_OFST               (0)
2664 +
2665 +//U3D_EQ0
2666 +#define RG_SSUSB_EQ_DLHL_LFI_OFST                 (24)
2667 +#define RG_SSUSB_EQ_DHHL_LFI_OFST                 (16)
2668 +#define RG_SSUSB_EQ_DD0HOS_LFI_OFST               (8)
2669 +#define RG_SSUSB_EQ_DD0LOS_LFI_OFST               (0)
2670 +
2671 +//U3D_EQ1
2672 +#define RG_SSUSB_EQ_DD1HOS_LFI_OFST               (24)
2673 +#define RG_SSUSB_EQ_DD1LOS_LFI_OFST               (16)
2674 +#define RG_SSUSB_EQ_DE0OS_LFI_OFST                (8)
2675 +#define RG_SSUSB_EQ_DE1OS_LFI_OFST                (0)
2676 +
2677 +//U3D_EQ2
2678 +#define RG_SSUSB_EQ_DLHLOS_LFI_OFST               (24)
2679 +#define RG_SSUSB_EQ_DHHLOS_LFI_OFST               (16)
2680 +#define RG_SSUSB_EQ_STOPTIME_OFST                 (14)
2681 +#define RG_SSUSB_EQ_DHHL_LF_SEL_OFST              (11)
2682 +#define RG_SSUSB_EQ_DSAOS_LF_SEL_OFST             (8)
2683 +#define RG_SSUSB_EQ_STARTTIME_OFST                (6)
2684 +#define RG_SSUSB_EQ_DLEQ_LF_SEL_OFST              (3)
2685 +#define RG_SSUSB_EQ_DLHL_LF_SEL_OFST              (0)
2686 +
2687 +//U3D_EQ3
2688 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST            (28)
2689 +#define RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST            (24)
2690 +#define RG_SSUSB_EQ_DEYE0OS_LFI_OFST              (16)
2691 +#define RG_SSUSB_EQ_DEYE1OS_LFI_OFST              (8)
2692 +#define RG_SSUSB_EQ_TRI_DET_EN_OFST               (7)
2693 +#define RG_SSUSB_EQ_TRI_DET_TH_OFST               (0)
2694 +
2695 +//U3D_EQ_EYE0
2696 +#define RG_SSUSB_EQ_EYE_XOFFSET_OFST              (25)
2697 +#define RG_SSUSB_EQ_EYE_MON_EN_OFST               (24)
2698 +#define RG_SSUSB_EQ_EYE0_Y_OFST                   (16)
2699 +#define RG_SSUSB_EQ_EYE1_Y_OFST                   (8)
2700 +#define RG_SSUSB_EQ_PILPO_ROUT_OFST               (7)
2701 +#define RG_SSUSB_EQ_PI_KPGAIN_OFST                (4)
2702 +#define RG_SSUSB_EQ_EYE_CNT_EN_OFST               (3)
2703 +
2704 +//U3D_EQ_EYE1
2705 +#define RG_SSUSB_EQ_SIGDET_OFST                   (24)
2706 +#define RG_SSUSB_EQ_EYE_MASK_OFST                 (7)
2707 +
2708 +//U3D_EQ_EYE2
2709 +#define RG_SSUSB_EQ_RX500M_CK_SEL_OFST            (31)
2710 +#define RG_SSUSB_EQ_SD_CNT1_OFST                  (24)
2711 +#define RG_SSUSB_EQ_ISIFLAG_SEL_OFST              (22)
2712 +#define RG_SSUSB_EQ_SD_CNT0_OFST                  (16)
2713 +
2714 +//U3D_EQ_DFE0
2715 +#define RG_SSUSB_EQ_LEQMAX_OFST                   (28)
2716 +#define RG_SSUSB_EQ_DFEX_EN_OFST                  (27)
2717 +#define RG_SSUSB_EQ_DFEX_LF_SEL_OFST              (24)
2718 +#define RG_SSUSB_EQ_CHK_EYE_H_OFST                (23)
2719 +#define RG_SSUSB_EQ_PIEYE_INI_OFST                (16)
2720 +#define RG_SSUSB_EQ_PI90_INI_OFST                 (8)
2721 +#define RG_SSUSB_EQ_PI0_INI_OFST                  (0)
2722 +
2723 +//U3D_EQ_DFE1
2724 +#define RG_SSUSB_EQ_REV_OFST                      (16)
2725 +#define RG_SSUSB_EQ_DFEYEN_DUR_OFST               (12)
2726 +#define RG_SSUSB_EQ_DFEXEN_DUR_OFST               (8)
2727 +#define RG_SSUSB_EQ_DFEX_RST_OFST                 (7)
2728 +#define RG_SSUSB_EQ_GATED_RXD_B_OFST              (6)
2729 +#define RG_SSUSB_EQ_PI90CK_SEL_OFST               (4)
2730 +#define RG_SSUSB_EQ_DFEX_DIS_OFST                 (2)
2731 +#define RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST          (1)
2732 +#define RG_SSUSB_EQ_DFEXEN_SEL_OFST               (0)
2733 +
2734 +//U3D_EQ_DFE2
2735 +#define RG_SSUSB_EQ_MON_SEL_OFST                  (24)
2736 +#define RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST            (16)
2737 +#define RG_SSUSB_EQ_DLEQOS_LFI_OFST               (8)
2738 +#define RG_SSUSB_EQ_LEQ_STOP_TO_OFST              (0)
2739 +
2740 +//U3D_EQ_DFE3
2741 +#define RG_SSUSB_EQ_RESERVED_OFST                 (0)
2742 +
2743 +//U3D_PHYD_MON0
2744 +#define RGS_SSUSB_BERT_BERC_OFST                  (16)
2745 +#define RGS_SSUSB_LFPS_OFST                       (12)
2746 +#define RGS_SSUSB_TRAINDEC_OFST                   (8)
2747 +#define RGS_SSUSB_SCP_PAT_OFST                    (0)
2748 +
2749 +//U3D_PHYD_MON1
2750 +#define RGS_SSUSB_RX_FL_OUT_OFST                  (0)
2751 +
2752 +//U3D_PHYD_MON2
2753 +#define RGS_SSUSB_T2RLB_ERRCNT_OFST               (16)
2754 +#define RGS_SSUSB_RETRACK_OFST                    (12)
2755 +#define RGS_SSUSB_RXPLL_LOCK_OFST                 (10)
2756 +#define RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST          (9)
2757 +#define RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST          (8)
2758 +#define RGS_SSUSB_PDNCTL_OFST                     (0)
2759 +
2760 +//U3D_PHYD_MON3
2761 +#define RGS_SSUSB_TSEQ_ERRCNT_OFST                (16)
2762 +#define RGS_SSUSB_PRBS_ERRCNT_OFST                (0)
2763 +
2764 +//U3D_PHYD_MON4
2765 +#define RGS_SSUSB_RX_LSLOCK_CNT_OFST              (24)
2766 +#define RGS_SSUSB_SCP_DETCNT_OFST                 (16)
2767 +#define RGS_SSUSB_TSEQ_DETCNT_OFST                (0)
2768 +
2769 +//U3D_PHYD_MON5
2770 +#define RGS_SSUSB_EBUFMSG_OFST                    (16)
2771 +#define RGS_SSUSB_BERT_LOCK_OFST                  (15)
2772 +#define RGS_SSUSB_SCP_DET_OFST                    (14)
2773 +#define RGS_SSUSB_TSEQ_DET_OFST                   (13)
2774 +#define RGS_SSUSB_EBUF_UDF_OFST                   (12)
2775 +#define RGS_SSUSB_EBUF_OVF_OFST                   (11)
2776 +#define RGS_SSUSB_PRBS_PASSTH_OFST                (10)
2777 +#define RGS_SSUSB_PRBS_PASS_OFST                  (9)
2778 +#define RGS_SSUSB_PRBS_LOCK_OFST                  (8)
2779 +#define RGS_SSUSB_T2RLB_ERR_OFST                  (6)
2780 +#define RGS_SSUSB_T2RLB_PASSTH_OFST               (5)
2781 +#define RGS_SSUSB_T2RLB_PASS_OFST                 (4)
2782 +#define RGS_SSUSB_T2RLB_LOCK_OFST                 (3)
2783 +#define RGS_SSUSB_RX_IMPCAL_DONE_OFST             (2)
2784 +#define RGS_SSUSB_TX_IMPCAL_DONE_OFST             (1)
2785 +#define RGS_SSUSB_RXDETECTED_OFST                 (0)
2786 +
2787 +//U3D_PHYD_MON6
2788 +#define RGS_SSUSB_SIGCAL_DONE_OFST                (30)
2789 +#define RGS_SSUSB_SIGCAL_CAL_OUT_OFST             (29)
2790 +#define RGS_SSUSB_SIGCAL_OFFSET_OFST              (24)
2791 +#define RGS_SSUSB_RX_IMP_SEL_OFST                 (16)
2792 +#define RGS_SSUSB_TX_IMP_SEL_OFST                 (8)
2793 +#define RGS_SSUSB_TFIFO_MSG_OFST                  (4)
2794 +#define RGS_SSUSB_RFIFO_MSG_OFST                  (0)
2795 +
2796 +//U3D_PHYD_MON7
2797 +#define RGS_SSUSB_FT_OUT_OFST                     (8)
2798 +#define RGS_SSUSB_PRB_OUT_OFST                    (0)
2799 +
2800 +//U3D_PHYA_RX_MON0
2801 +#define RGS_SSUSB_EQ_DCLEQ_OFST                   (24)
2802 +#define RGS_SSUSB_EQ_DCD0H_OFST                   (16)
2803 +#define RGS_SSUSB_EQ_DCD0L_OFST                   (8)
2804 +#define RGS_SSUSB_EQ_DCD1H_OFST                   (0)
2805 +
2806 +//U3D_PHYA_RX_MON1
2807 +#define RGS_SSUSB_EQ_DCD1L_OFST                   (24)
2808 +#define RGS_SSUSB_EQ_DCE0_OFST                    (16)
2809 +#define RGS_SSUSB_EQ_DCE1_OFST                    (8)
2810 +#define RGS_SSUSB_EQ_DCHHL_OFST                   (0)
2811 +
2812 +//U3D_PHYA_RX_MON2
2813 +#define RGS_SSUSB_EQ_LEQ_STOP_OFST                (31)
2814 +#define RGS_SSUSB_EQ_DCLHL_OFST                   (24)
2815 +#define RGS_SSUSB_EQ_STATUS_OFST                  (16)
2816 +#define RGS_SSUSB_EQ_DCEYE0_OFST                  (8)
2817 +#define RGS_SSUSB_EQ_DCEYE1_OFST                  (0)
2818 +
2819 +//U3D_PHYA_RX_MON3
2820 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST    (0)
2821 +
2822 +//U3D_PHYA_RX_MON4
2823 +#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST    (0)
2824 +
2825 +//U3D_PHYA_RX_MON5
2826 +#define RGS_SSUSB_EQ_DCLEQOS_OFST                 (8)
2827 +#define RGS_SSUSB_EQ_EYE_CNT_RDY_OFST             (7)
2828 +#define RGS_SSUSB_EQ_PILPO_OFST                   (0)
2829 +
2830 +//U3D_PHYD_CPPAT2
2831 +#define RG_SSUSB_CPPAT_OUT_H_TMP2_OFST            (16)
2832 +#define RG_SSUSB_CPPAT_OUT_H_TMP1_OFST            (8)
2833 +#define RG_SSUSB_CPPAT_OUT_H_TMP0_OFST            (0)
2834 +
2835 +//U3D_EQ_EYE3
2836 +#define RG_SSUSB_EQ_LEQ_SHIFT_OFST                (24)
2837 +#define RG_SSUSB_EQ_EYE_CNT_OFST                  (0)
2838 +
2839 +//U3D_KBAND_OUT
2840 +#define RGS_SSUSB_CDR_BAND_5G_OFST                (24)
2841 +#define RGS_SSUSB_CDR_BAND_2P5G_OFST              (16)
2842 +#define RGS_SSUSB_PLL_BAND_5G_OFST                (8)
2843 +#define RGS_SSUSB_PLL_BAND_2P5G_OFST              (0)
2844 +
2845 +//U3D_KBAND_OUT1
2846 +#define RGS_SSUSB_CDR_VCOCAL_FAIL_OFST            (24)
2847 +#define RGS_SSUSB_CDR_VCOCAL_STATE_OFST           (16)
2848 +#define RGS_SSUSB_PLL_VCOCAL_FAIL_OFST            (8)
2849 +#define RGS_SSUSB_PLL_VCOCAL_STATE_OFST           (0)
2850 +
2851 +
2852 +///////////////////////////////////////////////////////////////////////////////
2853 +
2854 +struct u3phyd_bank2_reg {
2855 +       //0x0
2856 +       PHY_LE32 b2_phyd_top1;
2857 +       PHY_LE32 b2_phyd_top2;
2858 +       PHY_LE32 b2_phyd_top3;
2859 +       PHY_LE32 b2_phyd_top4;
2860 +       //0x10
2861 +       PHY_LE32 b2_phyd_top5;
2862 +       PHY_LE32 b2_phyd_top6;
2863 +       PHY_LE32 b2_phyd_top7;
2864 +       PHY_LE32 b2_phyd_p_sigdet1;
2865 +       //0x20
2866 +       PHY_LE32 b2_phyd_p_sigdet2;
2867 +       PHY_LE32 b2_phyd_p_sigdet_cal1;
2868 +       PHY_LE32 b2_phyd_rxdet1;
2869 +       PHY_LE32 b2_phyd_rxdet2;
2870 +       //0x30
2871 +       PHY_LE32 b2_phyd_misc0;
2872 +       PHY_LE32 b2_phyd_misc2;
2873 +       PHY_LE32 b2_phyd_misc3;
2874 +       PHY_LE32 reserve0;
2875 +       //0x40
2876 +       PHY_LE32 b2_rosc_0;
2877 +       PHY_LE32 b2_rosc_1;
2878 +       PHY_LE32 b2_rosc_2;
2879 +       PHY_LE32 b2_rosc_3;
2880 +       //0x50
2881 +       PHY_LE32 b2_rosc_4;
2882 +       PHY_LE32 b2_rosc_5;
2883 +       PHY_LE32 b2_rosc_6;
2884 +       PHY_LE32 b2_rosc_7;
2885 +       //0x60
2886 +       PHY_LE32 b2_rosc_8;
2887 +       PHY_LE32 b2_rosc_9;
2888 +       PHY_LE32 b2_rosc_a;
2889 +       PHY_LE32 reserve1;
2890 +       //0x70~0xd0
2891 +       PHY_LE32 reserve2[28];
2892 +       //0xe0
2893 +       PHY_LE32 phyd_version;
2894 +       PHY_LE32 phyd_model;
2895 +};
2896 +
2897 +//U3D_B2_PHYD_TOP1
2898 +#define RG_SSUSB_PCIE2_K_EMP                      (0xf<<28) //31:28
2899 +#define RG_SSUSB_PCIE2_K_FUL                      (0xf<<24) //27:24
2900 +#define RG_SSUSB_TX_EIDLE_LP_EN                   (0x1<<17) //17:17
2901 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN             (0x1<<16) //16:16
2902 +#define RG_SSUSB_SIGDET_EN                        (0x1<<15) //15:15
2903 +#define RG_SSUSB_FORCE_SIGDET_EN                  (0x1<<14) //14:14
2904 +#define RG_SSUSB_CLKRX_EN                         (0x1<<13) //13:13
2905 +#define RG_SSUSB_FORCE_CLKRX_EN                   (0x1<<12) //12:12
2906 +#define RG_SSUSB_CLKTX_EN                         (0x1<<11) //11:11
2907 +#define RG_SSUSB_FORCE_CLKTX_EN                   (0x1<<10) //10:10
2908 +#define RG_SSUSB_CLK_REQ_N_I                      (0x1<<9) //9:9
2909 +#define RG_SSUSB_FORCE_CLK_REQ_N_I                (0x1<<8) //8:8
2910 +#define RG_SSUSB_RATE                             (0x1<<6) //6:6
2911 +#define RG_SSUSB_FORCE_RATE                       (0x1<<5) //5:5
2912 +#define RG_SSUSB_PCIE_MODE_SEL                    (0x1<<4) //4:4
2913 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL              (0x1<<3) //3:3
2914 +#define RG_SSUSB_PHY_MODE                         (0x3<<1) //2:1
2915 +#define RG_SSUSB_FORCE_PHY_MODE                   (0x1<<0) //0:0
2916 +
2917 +//U3D_B2_PHYD_TOP2
2918 +#define RG_SSUSB_FORCE_IDRV_6DB                   (0x1<<30) //30:30
2919 +#define RG_SSUSB_IDRV_6DB                         (0x3f<<24) //29:24
2920 +#define RG_SSUSB_FORCE_IDEM_3P5DB                 (0x1<<22) //22:22
2921 +#define RG_SSUSB_IDEM_3P5DB                       (0x3f<<16) //21:16
2922 +#define RG_SSUSB_FORCE_IDRV_3P5DB                 (0x1<<14) //14:14
2923 +#define RG_SSUSB_IDRV_3P5DB                       (0x3f<<8) //13:8
2924 +#define RG_SSUSB_FORCE_IDRV_0DB                   (0x1<<6) //6:6
2925 +#define RG_SSUSB_IDRV_0DB                         (0x3f<<0) //5:0
2926 +
2927 +//U3D_B2_PHYD_TOP3
2928 +#define RG_SSUSB_TX_BIASI                         (0x7<<25) //27:25
2929 +#define RG_SSUSB_FORCE_TX_BIASI_EN                (0x1<<24) //24:24
2930 +#define RG_SSUSB_TX_BIASI_EN                      (0x1<<16) //16:16
2931 +#define RG_SSUSB_FORCE_TX_BIASI                   (0x1<<13) //13:13
2932 +#define RG_SSUSB_FORCE_IDEM_6DB                   (0x1<<8) //8:8
2933 +#define RG_SSUSB_IDEM_6DB                         (0x3f<<0) //5:0
2934 +
2935 +//U3D_B2_PHYD_TOP4
2936 +#define RG_SSUSB_G1_CDR_BIC_LTR                   (0xf<<28) //31:28
2937 +#define RG_SSUSB_G1_CDR_BIC_LTD0                  (0xf<<24) //27:24
2938 +#define RG_SSUSB_G1_CDR_BC_LTD1                   (0x1f<<16) //20:16
2939 +#define RG_SSUSB_G1_CDR_BC_LTR                    (0x1f<<8) //12:8
2940 +#define RG_SSUSB_G1_CDR_BC_LTD0                   (0x1f<<0) //4:0
2941 +
2942 +//U3D_B2_PHYD_TOP5
2943 +#define RG_SSUSB_G1_CDR_BIR_LTD1                  (0x1f<<24) //28:24
2944 +#define RG_SSUSB_G1_CDR_BIR_LTR                   (0x1f<<16) //20:16
2945 +#define RG_SSUSB_G1_CDR_BIR_LTD0                  (0x1f<<8) //12:8
2946 +#define RG_SSUSB_G1_CDR_BIC_LTD1                  (0xf<<0) //3:0
2947 +
2948 +//U3D_B2_PHYD_TOP6
2949 +#define RG_SSUSB_G2_CDR_BIC_LTR                   (0xf<<28) //31:28
2950 +#define RG_SSUSB_G2_CDR_BIC_LTD0                  (0xf<<24) //27:24
2951 +#define RG_SSUSB_G2_CDR_BC_LTD1                   (0x1f<<16) //20:16
2952 +#define RG_SSUSB_G2_CDR_BC_LTR                    (0x1f<<8) //12:8
2953 +#define RG_SSUSB_G2_CDR_BC_LTD0                   (0x1f<<0) //4:0
2954 +
2955 +//U3D_B2_PHYD_TOP7
2956 +#define RG_SSUSB_G2_CDR_BIR_LTD1                  (0x1f<<24) //28:24
2957 +#define RG_SSUSB_G2_CDR_BIR_LTR                   (0x1f<<16) //20:16
2958 +#define RG_SSUSB_G2_CDR_BIR_LTD0                  (0x1f<<8) //12:8
2959 +#define RG_SSUSB_G2_CDR_BIC_LTD1                  (0xf<<0) //3:0
2960 +
2961 +//U3D_B2_PHYD_P_SIGDET1
2962 +#define RG_SSUSB_P_SIGDET_FLT_DIS                 (0x1<<31) //31:31
2963 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL        (0x7f<<24) //30:24
2964 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL        (0x7f<<16) //22:16
2965 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL          (0x7f<<8) //14:8
2966 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL          (0x7f<<0) //6:0
2967 +
2968 +//U3D_B2_PHYD_P_SIGDET2
2969 +#define RG_SSUSB_P_SIGDET_RX_VAL_S                (0x1<<29) //29:29
2970 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL            (0x1<<28) //28:28
2971 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S               (0x1<<27) //27:27
2972 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S            (0x3<<25) //26:25
2973 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S              (0x1<<24) //24:24
2974 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S             (0x1<<16) //16:16
2975 +#define RG_SSUSB_P_SIGDET_PRB_SEL                 (0x1<<10) //10:10
2976 +#define RG_SSUSB_P_SIGDET_BK_SIG_T                (0x3<<8) //9:8
2977 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS               (0x1<<6) //6:6
2978 +#define RG_SSUSB_P_SIGDET_NON_BK_AD               (0x1<<5) //5:5
2979 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ               (0x1<<4) //4:4
2980 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL               (0x3<<2) //3:2
2981 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL               (0x3<<0) //1:0
2982 +
2983 +//U3D_B2_PHYD_P_SIGDET_CAL1
2984 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET              (0x1f<<24) //28:24
2985 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET        (0x1<<16) //16:16
2986 +#define RG_SSUSB_P_SIGDET_CAL_EN                  (0x1<<8) //8:8
2987 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN            (0x1<<3) //3:3
2988 +#define RG_SSUSB_P_SIGDET_FLT_EN                  (0x1<<2) //2:2
2989 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD              (0x1<<1) //1:1
2990 +#define RG_SSUSB_P_SIGDET_REK                     (0x1<<0) //0:0
2991 +
2992 +//U3D_B2_PHYD_RXDET1
2993 +#define RG_SSUSB_RXDET_PRB_SEL                    (0x1<<31) //31:31
2994 +#define RG_SSUSB_FORCE_CMDET                      (0x1<<30) //30:30
2995 +#define RG_SSUSB_RXDET_EN                         (0x1<<29) //29:29
2996 +#define RG_SSUSB_FORCE_RXDET_EN                   (0x1<<28) //28:28
2997 +#define RG_SSUSB_RXDET_K_TWICE                    (0x1<<27) //27:27
2998 +#define RG_SSUSB_RXDET_STB3_SET                   (0x1ff<<18) //26:18
2999 +#define RG_SSUSB_RXDET_STB2_SET                   (0x1ff<<9) //17:9
3000 +#define RG_SSUSB_RXDET_STB1_SET                   (0x1ff<<0) //8:0
3001 +
3002 +//U3D_B2_PHYD_RXDET2
3003 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN         (0x1<<31) //31:31
3004 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN           (0x1<<30) //30:30
3005 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN            (0x1<<29) //29:29
3006 +#define RG_SSUSB_PDN_T_SEL                        (0x3<<18) //19:18
3007 +#define RG_SSUSB_RXDET_STB3_SET_P3                (0x1ff<<9) //17:9
3008 +#define RG_SSUSB_RXDET_STB2_SET_P3                (0x1ff<<0) //8:0
3009 +
3010 +//U3D_B2_PHYD_MISC0
3011 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN              (0x1<<22) //22:22
3012 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN                (0x1<<21) //21:21
3013 +#define RG_SSUSB_RXLFPS_ENTXDRV                   (0x1<<20) //20:20
3014 +#define RG_SSUSB_RX_FL_UNLOCKTH                   (0xf<<16) //19:16
3015 +#define RG_SSUSB_LFPS_PSEL                        (0x1<<15) //15:15
3016 +#define RG_SSUSB_RX_SIGDET_EN                     (0x1<<14) //14:14
3017 +#define RG_SSUSB_RX_SIGDET_EN_SEL                 (0x1<<13) //13:13
3018 +#define RG_SSUSB_RX_PI_CAL_EN                     (0x1<<12) //12:12
3019 +#define RG_SSUSB_RX_PI_CAL_EN_SEL                 (0x1<<11) //11:11
3020 +#define RG_SSUSB_P3_CLS_CK_SEL                    (0x1<<10) //10:10
3021 +#define RG_SSUSB_T2RLB_PSEL                       (0x3<<8) //9:8
3022 +#define RG_SSUSB_PPCTL_PSEL                       (0x7<<5) //7:5
3023 +#define RG_SSUSB_PHYD_TX_DATA_INV                 (0x1<<4) //4:4
3024 +#define RG_SSUSB_BERTLB_PSEL                      (0x3<<2) //3:2
3025 +#define RG_SSUSB_RETRACK_DIS                      (0x1<<1) //1:1
3026 +#define RG_SSUSB_PPERRCNT_CLR                     (0x1<<0) //0:0
3027 +
3028 +//U3D_B2_PHYD_MISC2
3029 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2              (0x1<<31) //31:31
3030 +#define RG_SSUSB_FRC_PLL_DDS_IADJ                 (0xf<<27) //30:27
3031 +#define RG_SSUSB_P_SIGDET_125FILTER               (0x1<<26) //26:26
3032 +#define RG_SSUSB_P_SIGDET_RST_FILTER              (0x1<<25) //25:25
3033 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW             (0x1<<24) //24:24
3034 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW             (0x1<<23) //23:23
3035 +#define RG_SSUSB_EIDLE_BF_RXDET                   (0x1<<22) //22:22
3036 +#define RG_SSUSB_EIDLE_LP_STBCYC                  (0x1ff<<13) //21:13
3037 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY              (0x3f<<7) //12:7
3038 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY               (0x3f<<1) //6:1
3039 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV               (0x1<<0) //0:0
3040 +
3041 +//U3D_B2_PHYD_MISC3
3042 +#define RGS_SSUSB_DDS_CALIB_C_STATE               (0x7<<16) //18:16
3043 +#define RGS_SSUSB_PPERRCNT                        (0xffff<<0) //15:0
3044 +
3045 +//U3D_B2_ROSC_0
3046 +#define RG_SSUSB_RING_OSC_CNTEND                  (0x1ff<<23) //31:23
3047 +#define RG_SSUSB_XTAL_OSC_CNTEND                  (0x7f<<16) //22:16
3048 +#define RG_SSUSB_RING_OSC_EN                      (0x1<<3) //3:3
3049 +#define RG_SSUSB_RING_OSC_FORCE_EN                (0x1<<2) //2:2
3050 +#define RG_SSUSB_FRC_RING_BYPASS_DET              (0x1<<1) //1:1
3051 +#define RG_SSUSB_RING_BYPASS_DET                  (0x1<<0) //0:0
3052 +
3053 +//U3D_B2_ROSC_1
3054 +#define RG_SSUSB_RING_OSC_FRC_P3                  (0x1<<20) //20:20
3055 +#define RG_SSUSB_RING_OSC_P3                      (0x1<<19) //19:19
3056 +#define RG_SSUSB_RING_OSC_FRC_RECAL               (0x3<<17) //18:17
3057 +#define RG_SSUSB_RING_OSC_RECAL                   (0x1<<16) //16:16
3058 +#define RG_SSUSB_RING_OSC_SEL                     (0xff<<8) //15:8
3059 +#define RG_SSUSB_RING_OSC_FRC_SEL                 (0x1<<0) //0:0
3060 +
3061 +//U3D_B2_ROSC_2
3062 +#define RG_SSUSB_RING_DET_STRCYC2                 (0xffff<<16) //31:16
3063 +#define RG_SSUSB_RING_DET_STRCYC1                 (0xffff<<0) //15:0
3064 +
3065 +//U3D_B2_ROSC_3
3066 +#define RG_SSUSB_RING_DET_DETWIN1                 (0xffff<<16) //31:16
3067 +#define RG_SSUSB_RING_DET_STRCYC3                 (0xffff<<0) //15:0
3068 +
3069 +//U3D_B2_ROSC_4
3070 +#define RG_SSUSB_RING_DET_DETWIN3                 (0xffff<<16) //31:16
3071 +#define RG_SSUSB_RING_DET_DETWIN2                 (0xffff<<0) //15:0
3072 +
3073 +//U3D_B2_ROSC_5
3074 +#define RG_SSUSB_RING_DET_LBOND1                  (0xffff<<16) //31:16
3075 +#define RG_SSUSB_RING_DET_UBOND1                  (0xffff<<0) //15:0
3076 +
3077 +//U3D_B2_ROSC_6
3078 +#define RG_SSUSB_RING_DET_LBOND2                  (0xffff<<16) //31:16
3079 +#define RG_SSUSB_RING_DET_UBOND2                  (0xffff<<0) //15:0
3080 +
3081 +//U3D_B2_ROSC_7
3082 +#define RG_SSUSB_RING_DET_LBOND3                  (0xffff<<16) //31:16
3083 +#define RG_SSUSB_RING_DET_UBOND3                  (0xffff<<0) //15:0
3084 +
3085 +//U3D_B2_ROSC_8
3086 +#define RG_SSUSB_RING_RESERVE                     (0xffff<<16) //31:16
3087 +#define RG_SSUSB_ROSC_PROB_SEL                    (0xf<<2) //5:2
3088 +#define RG_SSUSB_RING_FREQMETER_EN                (0x1<<1) //1:1
3089 +#define RG_SSUSB_RING_DET_BPS_UBOND               (0x1<<0) //0:0
3090 +
3091 +//U3D_B2_ROSC_9
3092 +#define RGS_FM_RING_CNT                           (0xffff<<16) //31:16
3093 +#define RGS_SSUSB_RING_OSC_STATE                  (0x3<<10) //11:10
3094 +#define RGS_SSUSB_RING_OSC_STABLE                 (0x1<<9) //9:9
3095 +#define RGS_SSUSB_RING_OSC_CAL_FAIL               (0x1<<8) //8:8
3096 +#define RGS_SSUSB_RING_OSC_CAL                    (0xff<<0) //7:0
3097 +
3098 +//U3D_B2_ROSC_A
3099 +#define RGS_SSUSB_ROSC_PROB_OUT                   (0xff<<0) //7:0
3100 +
3101 +//U3D_PHYD_VERSION
3102 +#define RGS_SSUSB_PHYD_VERSION                    (0xffffffff<<0) //31:0
3103 +
3104 +//U3D_PHYD_MODEL
3105 +#define RGS_SSUSB_PHYD_MODEL                      (0xffffffff<<0) //31:0
3106 +
3107 +
3108 +/* OFFSET */
3109 +
3110 +//U3D_B2_PHYD_TOP1
3111 +#define RG_SSUSB_PCIE2_K_EMP_OFST                 (28)
3112 +#define RG_SSUSB_PCIE2_K_FUL_OFST                 (24)
3113 +#define RG_SSUSB_TX_EIDLE_LP_EN_OFST              (17)
3114 +#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST        (16)
3115 +#define RG_SSUSB_SIGDET_EN_OFST                   (15)
3116 +#define RG_SSUSB_FORCE_SIGDET_EN_OFST             (14)
3117 +#define RG_SSUSB_CLKRX_EN_OFST                    (13)
3118 +#define RG_SSUSB_FORCE_CLKRX_EN_OFST              (12)
3119 +#define RG_SSUSB_CLKTX_EN_OFST                    (11)
3120 +#define RG_SSUSB_FORCE_CLKTX_EN_OFST              (10)
3121 +#define RG_SSUSB_CLK_REQ_N_I_OFST                 (9)
3122 +#define RG_SSUSB_FORCE_CLK_REQ_N_I_OFST           (8)
3123 +#define RG_SSUSB_RATE_OFST                        (6)
3124 +#define RG_SSUSB_FORCE_RATE_OFST                  (5)
3125 +#define RG_SSUSB_PCIE_MODE_SEL_OFST               (4)
3126 +#define RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST         (3)
3127 +#define RG_SSUSB_PHY_MODE_OFST                    (1)
3128 +#define RG_SSUSB_FORCE_PHY_MODE_OFST              (0)
3129 +
3130 +//U3D_B2_PHYD_TOP2
3131 +#define RG_SSUSB_FORCE_IDRV_6DB_OFST              (30)
3132 +#define RG_SSUSB_IDRV_6DB_OFST                    (24)
3133 +#define RG_SSUSB_FORCE_IDEM_3P5DB_OFST            (22)
3134 +#define RG_SSUSB_IDEM_3P5DB_OFST                  (16)
3135 +#define RG_SSUSB_FORCE_IDRV_3P5DB_OFST            (14)
3136 +#define RG_SSUSB_IDRV_3P5DB_OFST                  (8)
3137 +#define RG_SSUSB_FORCE_IDRV_0DB_OFST              (6)
3138 +#define RG_SSUSB_IDRV_0DB_OFST                    (0)
3139 +
3140 +//U3D_B2_PHYD_TOP3
3141 +#define RG_SSUSB_TX_BIASI_OFST                    (25)
3142 +#define RG_SSUSB_FORCE_TX_BIASI_EN_OFST           (24)
3143 +#define RG_SSUSB_TX_BIASI_EN_OFST                 (16)
3144 +#define RG_SSUSB_FORCE_TX_BIASI_OFST              (13)
3145 +#define RG_SSUSB_FORCE_IDEM_6DB_OFST              (8)
3146 +#define RG_SSUSB_IDEM_6DB_OFST                    (0)
3147 +
3148 +//U3D_B2_PHYD_TOP4
3149 +#define RG_SSUSB_G1_CDR_BIC_LTR_OFST              (28)
3150 +#define RG_SSUSB_G1_CDR_BIC_LTD0_OFST             (24)
3151 +#define RG_SSUSB_G1_CDR_BC_LTD1_OFST              (16)
3152 +#define RG_SSUSB_G1_CDR_BC_LTR_OFST               (8)
3153 +#define RG_SSUSB_G1_CDR_BC_LTD0_OFST              (0)
3154 +
3155 +//U3D_B2_PHYD_TOP5
3156 +#define RG_SSUSB_G1_CDR_BIR_LTD1_OFST             (24)
3157 +#define RG_SSUSB_G1_CDR_BIR_LTR_OFST              (16)
3158 +#define RG_SSUSB_G1_CDR_BIR_LTD0_OFST             (8)
3159 +#define RG_SSUSB_G1_CDR_BIC_LTD1_OFST             (0)
3160 +
3161 +//U3D_B2_PHYD_TOP6
3162 +#define RG_SSUSB_G2_CDR_BIC_LTR_OFST              (28)
3163 +#define RG_SSUSB_G2_CDR_BIC_LTD0_OFST             (24)
3164 +#define RG_SSUSB_G2_CDR_BC_LTD1_OFST              (16)
3165 +#define RG_SSUSB_G2_CDR_BC_LTR_OFST               (8)
3166 +#define RG_SSUSB_G2_CDR_BC_LTD0_OFST              (0)
3167 +
3168 +//U3D_B2_PHYD_TOP7
3169 +#define RG_SSUSB_G2_CDR_BIR_LTD1_OFST             (24)
3170 +#define RG_SSUSB_G2_CDR_BIR_LTR_OFST              (16)
3171 +#define RG_SSUSB_G2_CDR_BIR_LTD0_OFST             (8)
3172 +#define RG_SSUSB_G2_CDR_BIC_LTD1_OFST             (0)
3173 +
3174 +//U3D_B2_PHYD_P_SIGDET1
3175 +#define RG_SSUSB_P_SIGDET_FLT_DIS_OFST            (31)
3176 +#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST   (24)
3177 +#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST   (16)
3178 +#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST     (8)
3179 +#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST     (0)
3180 +
3181 +//U3D_B2_PHYD_P_SIGDET2
3182 +#define RG_SSUSB_P_SIGDET_RX_VAL_S_OFST           (29)
3183 +#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST       (28)
3184 +#define RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST          (27)
3185 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST       (25)
3186 +#define RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST         (24)
3187 +#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST        (16)
3188 +#define RG_SSUSB_P_SIGDET_PRB_SEL_OFST            (10)
3189 +#define RG_SSUSB_P_SIGDET_BK_SIG_T_OFST           (8)
3190 +#define RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST          (6)
3191 +#define RG_SSUSB_P_SIGDET_NON_BK_AD_OFST          (5)
3192 +#define RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST          (4)
3193 +#define RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST          (2)
3194 +#define RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST          (0)
3195 +
3196 +//U3D_B2_PHYD_P_SIGDET_CAL1
3197 +#define RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST         (24)
3198 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST   (16)
3199 +#define RG_SSUSB_P_SIGDET_CAL_EN_OFST             (8)
3200 +#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST       (3)
3201 +#define RG_SSUSB_P_SIGDET_FLT_EN_OFST             (2)
3202 +#define RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST         (1)
3203 +#define RG_SSUSB_P_SIGDET_REK_OFST                (0)
3204 +
3205 +//U3D_B2_PHYD_RXDET1
3206 +#define RG_SSUSB_RXDET_PRB_SEL_OFST               (31)
3207 +#define RG_SSUSB_FORCE_CMDET_OFST                 (30)
3208 +#define RG_SSUSB_RXDET_EN_OFST                    (29)
3209 +#define RG_SSUSB_FORCE_RXDET_EN_OFST              (28)
3210 +#define RG_SSUSB_RXDET_K_TWICE_OFST               (27)
3211 +#define RG_SSUSB_RXDET_STB3_SET_OFST              (18)
3212 +#define RG_SSUSB_RXDET_STB2_SET_OFST              (9)
3213 +#define RG_SSUSB_RXDET_STB1_SET_OFST              (0)
3214 +
3215 +//U3D_B2_PHYD_RXDET2
3216 +#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST    (31)
3217 +#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST      (30)
3218 +#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST       (29)
3219 +#define RG_SSUSB_PDN_T_SEL_OFST                   (18)
3220 +#define RG_SSUSB_RXDET_STB3_SET_P3_OFST           (9)
3221 +#define RG_SSUSB_RXDET_STB2_SET_P3_OFST           (0)
3222 +
3223 +//U3D_B2_PHYD_MISC0
3224 +#define RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST         (22)
3225 +#define RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST           (21)
3226 +#define RG_SSUSB_RXLFPS_ENTXDRV_OFST              (20)
3227 +#define RG_SSUSB_RX_FL_UNLOCKTH_OFST              (16)
3228 +#define RG_SSUSB_LFPS_PSEL_OFST                   (15)
3229 +#define RG_SSUSB_RX_SIGDET_EN_OFST                (14)
3230 +#define RG_SSUSB_RX_SIGDET_EN_SEL_OFST            (13)
3231 +#define RG_SSUSB_RX_PI_CAL_EN_OFST                (12)
3232 +#define RG_SSUSB_RX_PI_CAL_EN_SEL_OFST            (11)
3233 +#define RG_SSUSB_P3_CLS_CK_SEL_OFST               (10)
3234 +#define RG_SSUSB_T2RLB_PSEL_OFST                  (8)
3235 +#define RG_SSUSB_PPCTL_PSEL_OFST                  (5)
3236 +#define RG_SSUSB_PHYD_TX_DATA_INV_OFST            (4)
3237 +#define RG_SSUSB_BERTLB_PSEL_OFST                 (2)
3238 +#define RG_SSUSB_RETRACK_DIS_OFST                 (1)
3239 +#define RG_SSUSB_PPERRCNT_CLR_OFST                (0)
3240 +
3241 +//U3D_B2_PHYD_MISC2
3242 +#define RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST         (31)
3243 +#define RG_SSUSB_FRC_PLL_DDS_IADJ_OFST            (27)
3244 +#define RG_SSUSB_P_SIGDET_125FILTER_OFST          (26)
3245 +#define RG_SSUSB_P_SIGDET_RST_FILTER_OFST         (25)
3246 +#define RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST        (24)
3247 +#define RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST        (23)
3248 +#define RG_SSUSB_EIDLE_BF_RXDET_OFST              (22)
3249 +#define RG_SSUSB_EIDLE_LP_STBCYC_OFST             (13)
3250 +#define RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST         (7)
3251 +#define RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST          (1)
3252 +#define RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST          (0)
3253 +
3254 +//U3D_B2_PHYD_MISC3
3255 +#define RGS_SSUSB_DDS_CALIB_C_STATE_OFST          (16)
3256 +#define RGS_SSUSB_PPERRCNT_OFST                   (0)
3257 +
3258 +//U3D_B2_ROSC_0
3259 +#define RG_SSUSB_RING_OSC_CNTEND_OFST             (23)
3260 +#define RG_SSUSB_XTAL_OSC_CNTEND_OFST             (16)
3261 +#define RG_SSUSB_RING_OSC_EN_OFST                 (3)
3262 +#define RG_SSUSB_RING_OSC_FORCE_EN_OFST           (2)
3263 +#define RG_SSUSB_FRC_RING_BYPASS_DET_OFST         (1)
3264 +#define RG_SSUSB_RING_BYPASS_DET_OFST             (0)
3265 +
3266 +//U3D_B2_ROSC_1
3267 +#define RG_SSUSB_RING_OSC_FRC_P3_OFST             (20)
3268 +#define RG_SSUSB_RING_OSC_P3_OFST                 (19)
3269 +#define RG_SSUSB_RING_OSC_FRC_RECAL_OFST          (17)
3270 +#define RG_SSUSB_RING_OSC_RECAL_OFST              (16)
3271 +#define RG_SSUSB_RING_OSC_SEL_OFST                (8)
3272 +#define RG_SSUSB_RING_OSC_FRC_SEL_OFST            (0)
3273 +
3274 +//U3D_B2_ROSC_2
3275 +#define RG_SSUSB_RING_DET_STRCYC2_OFST            (16)
3276 +#define RG_SSUSB_RING_DET_STRCYC1_OFST            (0)
3277 +
3278 +//U3D_B2_ROSC_3
3279 +#define RG_SSUSB_RING_DET_DETWIN1_OFST            (16)
3280 +#define RG_SSUSB_RING_DET_STRCYC3_OFST            (0)
3281 +
3282 +//U3D_B2_ROSC_4
3283 +#define RG_SSUSB_RING_DET_DETWIN3_OFST            (16)
3284 +#define RG_SSUSB_RING_DET_DETWIN2_OFST            (0)
3285 +
3286 +//U3D_B2_ROSC_5
3287 +#define RG_SSUSB_RING_DET_LBOND1_OFST             (16)
3288 +#define RG_SSUSB_RING_DET_UBOND1_OFST             (0)
3289 +
3290 +//U3D_B2_ROSC_6
3291 +#define RG_SSUSB_RING_DET_LBOND2_OFST             (16)
3292 +#define RG_SSUSB_RING_DET_UBOND2_OFST             (0)
3293 +
3294 +//U3D_B2_ROSC_7
3295 +#define RG_SSUSB_RING_DET_LBOND3_OFST             (16)
3296 +#define RG_SSUSB_RING_DET_UBOND3_OFST             (0)
3297 +
3298 +//U3D_B2_ROSC_8
3299 +#define RG_SSUSB_RING_RESERVE_OFST                (16)
3300 +#define RG_SSUSB_ROSC_PROB_SEL_OFST               (2)
3301 +#define RG_SSUSB_RING_FREQMETER_EN_OFST           (1)
3302 +#define RG_SSUSB_RING_DET_BPS_UBOND_OFST          (0)
3303 +
3304 +//U3D_B2_ROSC_9
3305 +#define RGS_FM_RING_CNT_OFST                      (16)
3306 +#define RGS_SSUSB_RING_OSC_STATE_OFST             (10)
3307 +#define RGS_SSUSB_RING_OSC_STABLE_OFST            (9)
3308 +#define RGS_SSUSB_RING_OSC_CAL_FAIL_OFST          (8)
3309 +#define RGS_SSUSB_RING_OSC_CAL_OFST               (0)
3310 +
3311 +//U3D_B2_ROSC_A
3312 +#define RGS_SSUSB_ROSC_PROB_OUT_OFST              (0)
3313 +
3314 +//U3D_PHYD_VERSION
3315 +#define RGS_SSUSB_PHYD_VERSION_OFST               (0)
3316 +
3317 +//U3D_PHYD_MODEL
3318 +#define RGS_SSUSB_PHYD_MODEL_OFST                 (0)
3319 +
3320 +
3321 +///////////////////////////////////////////////////////////////////////////////
3322 +
3323 +struct sifslv_chip_reg {
3324 +       PHY_LE32 xtalbias;
3325 +       PHY_LE32 syspll1;
3326 +       PHY_LE32 gpio_ctla;
3327 +       PHY_LE32 gpio_ctlb;
3328 +       PHY_LE32 gpio_ctlc;
3329 +};
3330 +
3331 +//U3D_GPIO_CTLA
3332 +#define RG_C60802_GPIO_CTLA                       (0xffffffff<<0) //31:0
3333 +
3334 +//U3D_GPIO_CTLB
3335 +#define RG_C60802_GPIO_CTLB                       (0xffffffff<<0) //31:0
3336 +
3337 +//U3D_GPIO_CTLC
3338 +#define RG_C60802_GPIO_CTLC                       (0xffffffff<<0) //31:0
3339 +
3340 +/* OFFSET */
3341 +
3342 +//U3D_GPIO_CTLA
3343 +#define RG_C60802_GPIO_CTLA_OFST                  (0)
3344 +
3345 +//U3D_GPIO_CTLB
3346 +#define RG_C60802_GPIO_CTLB_OFST                  (0)
3347 +
3348 +//U3D_GPIO_CTLC
3349 +#define RG_C60802_GPIO_CTLC_OFST                  (0)
3350 +
3351 +///////////////////////////////////////////////////////////////////////////////
3352 +
3353 +struct sifslv_fm_feg {
3354 +       //0x0
3355 +       PHY_LE32 fmcr0;
3356 +       PHY_LE32 fmcr1;
3357 +       PHY_LE32 fmcr2;
3358 +       PHY_LE32 fmmonr0;
3359 +       //0x10
3360 +       PHY_LE32 fmmonr1;
3361 +};
3362 +
3363 +//U3D_FMCR0
3364 +#define RG_LOCKTH                                 (0xf<<28) //31:28
3365 +#define RG_MONCLK_SEL                             (0x3<<26) //27:26
3366 +#define RG_FM_MODE                                (0x1<<25) //25:25
3367 +#define RG_FREQDET_EN                             (0x1<<24) //24:24
3368 +#define RG_CYCLECNT                               (0xffffff<<0) //23:0
3369 +
3370 +//U3D_FMCR1
3371 +#define RG_TARGET                                 (0xffffffff<<0) //31:0
3372 +
3373 +//U3D_FMCR2
3374 +#define RG_OFFSET                                 (0xffffffff<<0) //31:0
3375 +
3376 +//U3D_FMMONR0
3377 +#define USB_FM_OUT                                (0xffffffff<<0) //31:0
3378 +
3379 +//U3D_FMMONR1
3380 +#define RG_MONCLK_SEL_3                           (0x1<<9) //9:9
3381 +#define RG_FRCK_EN                                (0x1<<8) //8:8
3382 +#define USBPLL_LOCK                               (0x1<<1) //1:1
3383 +#define USB_FM_VLD                                (0x1<<0) //0:0
3384 +
3385 +
3386 +/* OFFSET */
3387 +
3388 +//U3D_FMCR0
3389 +#define RG_LOCKTH_OFST                            (28)
3390 +#define RG_MONCLK_SEL_OFST                        (26)
3391 +#define RG_FM_MODE_OFST                           (25)
3392 +#define RG_FREQDET_EN_OFST                        (24)
3393 +#define RG_CYCLECNT_OFST                          (0)
3394 +
3395 +//U3D_FMCR1
3396 +#define RG_TARGET_OFST                            (0)
3397 +
3398 +//U3D_FMCR2
3399 +#define RG_OFFSET_OFST                            (0)
3400 +
3401 +//U3D_FMMONR0
3402 +#define USB_FM_OUT_OFST                           (0)
3403 +
3404 +//U3D_FMMONR1
3405 +#define RG_MONCLK_SEL_3_OFST                      (9)
3406 +#define RG_FRCK_EN_OFST                           (8)
3407 +#define USBPLL_LOCK_OFST                          (1)
3408 +#define USB_FM_VLD_OFST                           (0)
3409 +
3410 +
3411 +///////////////////////////////////////////////////////////////////////////////
3412 +
3413 +PHY_INT32 phy_init(struct u3phy_info *info);
3414 +PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3415 +PHY_INT32 eyescan_init(struct u3phy_info *info);
3416 +PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
3417 +               , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3418 +PHY_INT32 u2_save_cur_en(struct u3phy_info *info);
3419 +PHY_INT32 u2_save_cur_re(struct u3phy_info *info);
3420 +PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info);
3421 +
3422 +#endif
3423 +#endif
3424 --- /dev/null
3425 +++ b/drivers/usb/host/mtk-phy-ahb.c
3426 @@ -0,0 +1,58 @@
3427 +#include "mtk-phy.h"
3428 +#ifdef CONFIG_U3D_HAL_SUPPORT
3429 +#include "mu3d_hal_osal.h"
3430 +#endif
3431 +
3432 +#ifdef CONFIG_U3_PHY_AHB_SUPPORT
3433 +#include <linux/gfp.h>
3434 +#include <linux/kernel.h>
3435 +#include <linux/slab.h>
3436 +
3437 +#ifndef CONFIG_U3D_HAL_SUPPORT
3438 +#define os_writel(addr,data) {\
3439 +               (*((volatile PHY_UINT32*)(addr)) = data);\
3440 +       }
3441 +#define os_readl(addr)  *((volatile PHY_UINT32*)(addr))
3442 +#define os_writelmsk(addr, data, msk) \
3443 +               { os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \
3444 +       }
3445 +#define os_setmsk(addr, msk) \
3446 +       { os_writel(addr, os_readl(addr) | msk); \
3447 +       }
3448 +#define os_clrmsk(addr, msk) \
3449 +   { os_writel(addr, os_readl(addr) &~ msk); \
3450 +   }
3451 +/*msk the data first, then umsk with the umsk.*/
3452 +#define os_writelmskumsk(addr, data, msk, umsk) \
3453 +{\
3454 +   os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\
3455 +}
3456 +
3457 +#endif
3458 +
3459 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data)
3460 +{
3461 +       os_writel(addr, data);
3462 +
3463 +       return 0;
3464 +}
3465 +
3466 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr)
3467 +{
3468 +       return os_readl(addr);
3469 +}
3470 +
3471 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data)
3472 +{
3473 +       os_writelmsk(addr&0xfffffffc, data<<((addr%4)*8), 0xff<<((addr%4)*8));
3474 +
3475 +       return 0;
3476 +}
3477 +
3478 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr)
3479 +{
3480 +       return ((os_readl(addr)>>((addr%4)*8))&0xff);
3481 +}
3482 +
3483 +#endif
3484 +
3485 --- /dev/null
3486 +++ b/drivers/usb/host/mtk-phy.c
3487 @@ -0,0 +1,102 @@
3488 +#include <linux/gfp.h>
3489 +#include <linux/kernel.h>
3490 +#include <linux/slab.h>
3491 +#define U3_PHY_LIB
3492 +#include "mtk-phy.h"
3493 +#ifdef CONFIG_PROJECT_7621
3494 +#include "mtk-phy-7621.h"
3495 +#endif
3496 +#ifdef CONFIG_PROJECT_PHY
3497 +static struct u3phy_operator project_operators = {
3498 +       .init = phy_init,
3499 +       .change_pipe_phase = phy_change_pipe_phase,
3500 +       .eyescan_init = eyescan_init,
3501 +       .eyescan = phy_eyescan,
3502 +       .u2_slew_rate_calibration = u2_slew_rate_calibration,
3503 +};
3504 +#endif
3505 +
3506 +
3507 +PHY_INT32 u3phy_init(){
3508 +#ifndef CONFIG_PROJECT_PHY
3509 +       PHY_INT32 u3phy_version;
3510 +#endif
3511 +
3512 +       if(u3phy != NULL){
3513 +               return PHY_TRUE;
3514 +       }
3515 +
3516 +       u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3517 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3518 +       u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
3519 +#endif
3520 +#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
3521 +       u3phy->phyd_version_addr = 0x2000e4;
3522 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3523 +       u3phy_p1->phyd_version_addr = 0x2000e4;
3524 +#endif
3525 +#else
3526 +       u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
3527 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3528 +       u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
3529 +#endif
3530 +#endif
3531 +
3532 +#ifdef CONFIG_PROJECT_PHY
3533 +
3534 +       u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
3535 +       u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
3536 +       u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
3537 +       u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
3538 +       u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
3539 +       u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3540 +       u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3541 +       u3phy_ops = &project_operators;
3542 +
3543 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3544 +       u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
3545 +       u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
3546 +       u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
3547 +       u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
3548 +       u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
3549 +       u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
3550 +       u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
3551 +#endif
3552 +#endif
3553 +
3554 +       return PHY_TRUE;
3555 +}
3556 +
3557 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3558 +       PHY_INT8 cur_value;
3559 +       PHY_INT8 new_value;
3560 +
3561 +       cur_value = U3PhyReadReg8(addr);
3562 +       new_value = (cur_value & (~mask)) | (value << offset);
3563 +       //udelay(i2cdelayus);
3564 +       U3PhyWriteReg8(addr, new_value);
3565 +       return PHY_TRUE;
3566 +}
3567 +
3568 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
3569 +       PHY_INT32 cur_value;
3570 +       PHY_INT32 new_value;
3571 +
3572 +       cur_value = U3PhyReadReg32(addr);
3573 +       new_value = (cur_value & (~mask)) | ((value << offset) & mask);
3574 +       U3PhyWriteReg32(addr, new_value);
3575 +       //DRV_MDELAY(100);
3576 +
3577 +       return PHY_TRUE;
3578 +}
3579 +
3580 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
3581 +
3582 +       return ((U3PhyReadReg8(addr) & mask) >> offset);
3583 +}
3584 +
3585 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
3586 +
3587 +       return ((U3PhyReadReg32(addr) & mask) >> offset);
3588 +}
3589 +
3590 --- /dev/null
3591 +++ b/drivers/usb/host/mtk-phy.h
3592 @@ -0,0 +1,179 @@
3593 +#ifndef __MTK_PHY_NEW_H
3594 +#define __MTK_PHY_NEW_H
3595 +
3596 +//#define CONFIG_U3D_HAL_SUPPORT
3597 +
3598 +/* include system library */
3599 +#include <linux/gfp.h>
3600 +#include <linux/kernel.h>
3601 +#include <linux/slab.h>
3602 +#include <linux/delay.h>
3603 +
3604 +/* Choose PHY R/W implementation */
3605 +//#define CONFIG_U3_PHY_GPIO_SUPPORT   //SW I2C implemented by GPIO
3606 +#define CONFIG_U3_PHY_AHB_SUPPORT      //AHB, only on SoC
3607 +
3608 +/* Choose PHY version */
3609 +//Select your project by defining one of the followings
3610 +#define CONFIG_PROJECT_7621 //7621
3611 +#define CONFIG_PROJECT_PHY
3612 +
3613 +/* BASE ADDRESS DEFINE, should define this on ASIC */
3614 +#define PHY_BASE               0xBE1D0000
3615 +#define SIFSLV_FM_FEG_BASE     (PHY_BASE+0x100)
3616 +#define SIFSLV_CHIP_BASE       (PHY_BASE+0x700)
3617 +#define U2_PHY_BASE            (PHY_BASE+0x800)
3618 +#define U3_PHYD_BASE           (PHY_BASE+0x900)
3619 +#define U3_PHYD_B2_BASE                (PHY_BASE+0xa00)
3620 +#define U3_PHYA_BASE           (PHY_BASE+0xb00)
3621 +#define U3_PHYA_DA_BASE                (PHY_BASE+0xc00)
3622 +
3623 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3624 +#define SIFSLV_FM_FEG_BASE_P1  (PHY_BASE+0x100)
3625 +#define SIFSLV_CHIP_BASE_P1    (PHY_BASE+0x700)
3626 +#define U2_PHY_BASE_P1         (PHY_BASE+0x1000)
3627 +#define U3_PHYD_BASE_P1                (PHY_BASE+0x1100)
3628 +#define U3_PHYD_B2_BASE_P1     (PHY_BASE+0x1200)
3629 +#define U3_PHYA_BASE_P1                (PHY_BASE+0x1300)
3630 +#define U3_PHYA_DA_BASE_P1     (PHY_BASE+0x1400)
3631 +#endif
3632 +
3633 +/*
3634 +
3635 +0x00000100     MODULE  ssusb_sifslv_fmreg      ssusb_sifslv_fmreg
3636 +0x00000700     MODULE  ssusb_sifslv_ippc       ssusb_sifslv_ippc
3637 +0x00000800     MODULE  ssusb_sifslv_u2phy_com  ssusb_sifslv_u2_phy_com_T28
3638 +0x00000900     MODULE  ssusb_sifslv_u3phyd     ssusb_sifslv_u3phyd_T28
3639 +0x00000a00     MODULE  ssusb_sifslv_u3phyd_bank2       ssusb_sifslv_u3phyd_bank2_T28
3640 +0x00000b00     MODULE  ssusb_sifslv_u3phya     ssusb_sifslv_u3phya_T28
3641 +0x00000c00     MODULE  ssusb_sifslv_u3phya_da  ssusb_sifslv_u3phya_da_T28
3642 +*/
3643 +
3644 +
3645 +/* TYPE DEFINE */
3646 +typedef unsigned int   PHY_UINT32;
3647 +typedef int                            PHY_INT32;
3648 +typedef        unsigned short  PHY_UINT16;
3649 +typedef short                  PHY_INT16;
3650 +typedef unsigned char  PHY_UINT8;
3651 +typedef char                   PHY_INT8;
3652 +
3653 +typedef PHY_UINT32 __bitwise   PHY_LE32;
3654 +
3655 +/* CONSTANT DEFINE */
3656 +#define PHY_FALSE      0
3657 +#define PHY_TRUE       1
3658 +
3659 +/* MACRO DEFINE */
3660 +#define DRV_WriteReg32(addr,data)       ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
3661 +#define DRV_Reg32(addr)                 (*(volatile PHY_UINT32 *)(addr))
3662 +
3663 +#define DRV_MDELAY     mdelay
3664 +#define DRV_MSLEEP     msleep
3665 +#define DRV_UDELAY     udelay
3666 +#define DRV_USLEEP     usleep
3667 +
3668 +/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
3669 +PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
3670 +PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
3671 +PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
3672 +PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
3673 +
3674 +/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
3675 +PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3676 +PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
3677 +PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3678 +PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
3679 +
3680 +struct u3phy_info {
3681 +       PHY_INT32 phy_version;
3682 +       PHY_INT32 phyd_version_addr;
3683 +
3684 +#ifdef CONFIG_PROJECT_PHY
3685 +       struct u2phy_reg *u2phy_regs;
3686 +       struct u3phya_reg *u3phya_regs;
3687 +       struct u3phya_da_reg *u3phya_da_regs;
3688 +       struct u3phyd_reg *u3phyd_regs;
3689 +       struct u3phyd_bank2_reg *u3phyd_bank2_regs;
3690 +       struct sifslv_chip_reg *sifslv_chip_regs;
3691 +       struct sifslv_fm_feg *sifslv_fm_regs;
3692 +#endif
3693 +};
3694 +
3695 +struct u3phy_operator {
3696 +       PHY_INT32 (*init) (struct u3phy_info *info);
3697 +       PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
3698 +       PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
3699 +       PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
3700 +       PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
3701 +       PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
3702 +       PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
3703 +};
3704 +
3705 +#ifdef U3_PHY_LIB
3706 +#define AUTOEXT
3707 +#else
3708 +#define AUTOEXT extern
3709 +#endif
3710 +
3711 +AUTOEXT struct u3phy_info *u3phy;
3712 +AUTOEXT struct u3phy_info *u3phy_p1;
3713 +AUTOEXT struct u3phy_operator *u3phy_ops;
3714 +
3715 +/*********eye scan required*********/
3716 +
3717 +#define LO_BYTE(x)                   ((PHY_UINT8)((x) & 0xFF))
3718 +#define HI_BYTE(x)                   ((PHY_UINT8)(((x) & 0xFF00) >> 8))
3719 +
3720 +typedef enum
3721 +{
3722 +  SCAN_UP,
3723 +  SCAN_DN
3724 +} enumScanDir;
3725 +
3726 +struct strucScanRegion
3727 +{
3728 +  PHY_INT8 bX_tl;
3729 +  PHY_INT8 bY_tl;
3730 +  PHY_INT8 bX_br;
3731 +  PHY_INT8 bY_br;
3732 +  PHY_INT8 bDeltaX;
3733 +  PHY_INT8 bDeltaY;
3734 +};
3735 +
3736 +struct strucTestCycle
3737 +{
3738 +  PHY_UINT16 wEyeCnt;
3739 +  PHY_INT8 bNumOfEyeCnt;
3740 +  PHY_INT8 bPICalEn;
3741 +  PHY_INT8 bNumOfIgnoreCnt;
3742 +};
3743 +
3744 +#define ERRCNT_MAX             128
3745 +#define CYCLE_COUNT_MAX        15
3746 +
3747 +/// the map resolution is 128 x 128 pts
3748 +#define MAX_X                 127
3749 +#define MAX_Y                 127
3750 +#define MIN_X                 0
3751 +#define MIN_Y                 0
3752 +
3753 +PHY_INT32 u3phy_init(void);
3754 +
3755 +AUTOEXT struct strucScanRegion           _rEye1;
3756 +AUTOEXT struct strucScanRegion           _rEye2;
3757 +AUTOEXT struct strucTestCycle            _rTestCycle;
3758 +AUTOEXT PHY_UINT8                      _bXcurr;
3759 +AUTOEXT PHY_UINT8                      _bYcurr;
3760 +AUTOEXT enumScanDir               _eScanDir;
3761 +AUTOEXT PHY_INT8                      _fgXChged;
3762 +AUTOEXT PHY_INT8                      _bPIResult;
3763 +/* use local variable instead to save memory use */
3764 +#if 0
3765 +AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3766 +AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
3767 +#endif
3768 +
3769 +/***********************************/
3770 +#endif
3771 +
3772 --- a/drivers/usb/host/pci-quirks.h
3773 +++ b/drivers/usb/host/pci-quirks.h
3774 @@ -1,7 +1,7 @@
3775  #ifndef __LINUX_USB_PCI_QUIRKS_H
3776  #define __LINUX_USB_PCI_QUIRKS_H
3777
3778 -#ifdef CONFIG_PCI
3779 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3780  void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
3781  int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
3782  #endif  /* CONFIG_PCI */
3783 --- a/drivers/usb/host/xhci-dbg.c
3784 +++ b/drivers/usb/host/xhci-dbg.c
3785 @@ -21,6 +21,9 @@
3786   */
3787
3788  #include "xhci.h"
3789 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3790 +#include "xhci-mtk.h"
3791 +#endif
3792
3793  #define XHCI_INIT_VALUE 0x0
3794
3795 --- a/drivers/usb/host/xhci-mem.c
3796 +++ b/drivers/usb/host/xhci-mem.c
3797 @@ -67,6 +67,9 @@ static struct xhci_segment *xhci_segment
3798
3799  static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
3800  {
3801 +       if (!seg)
3802 +               return;
3803 +
3804         if (seg->trbs) {
3805                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
3806                 seg->trbs = NULL;
3807 @@ -1475,9 +1478,17 @@ int xhci_endpoint_init(struct xhci_hcd *
3808                         max_burst = (usb_endpoint_maxp(&ep->desc)
3809                                      & 0x1800) >> 11;
3810                 }
3811 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3812 +               if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3813 +               max_packet += 2;
3814 +#endif
3815                 break;
3816         case USB_SPEED_FULL:
3817         case USB_SPEED_LOW:
3818 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
3819 +               if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
3820 +               max_packet += 2;
3821 +#endif
3822                 break;
3823         default:
3824                 BUG();
3825 --- /dev/null
3826 +++ b/drivers/usb/host/xhci-mtk-power.c
3827 @@ -0,0 +1,115 @@
3828 +#include "xhci-mtk.h"
3829 +#include "xhci-mtk-power.h"
3830 +#include "xhci.h"
3831 +#include <linux/kernel.h>       /* printk() */
3832 +#include <linux/slab.h>
3833 +#include <linux/delay.h>
3834 +
3835 +static int g_num_u3_port;
3836 +static int g_num_u2_port;
3837 +
3838 +
3839 +void enableXhciAllPortPower(struct xhci_hcd *xhci){
3840 +       int i;
3841 +       u32 port_id, temp;
3842 +       u32 __iomem *addr;
3843 +
3844 +       g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3845 +       g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3846 +
3847 +       for(i=1; i<=g_num_u3_port; i++){
3848 +               port_id=i;
3849 +               addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3850 +               temp = readl(addr);
3851 +               temp = xhci_port_state_to_neutral(temp);
3852 +               temp |= PORT_POWER;
3853 +               writel(temp, addr);
3854 +       }
3855 +       for(i=1; i<=g_num_u2_port; i++){
3856 +               port_id=i+g_num_u3_port;
3857 +               addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
3858 +               temp = readl(addr);
3859 +               temp = xhci_port_state_to_neutral(temp);
3860 +               temp |= PORT_POWER;
3861 +               writel(temp, addr);
3862 +       }
3863 +}
3864 +
3865 +void enableAllClockPower(){
3866 +
3867 +       int i;
3868 +       u32 temp;
3869 +
3870 +       g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3871 +       g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3872 +
3873 +       //2.    Enable xHC
3874 +       writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3875 +       writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
3876 +       writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3877 +
3878 +       //1.    Enable target ports
3879 +       for(i=0; i<g_num_u3_port; i++){
3880 +               temp = readl(SSUSB_U3_CTRL(i));
3881 +               temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
3882 +               writel(temp, SSUSB_U3_CTRL(i));
3883 +       }
3884 +       for(i=0; i<g_num_u2_port; i++){
3885 +               temp = readl(SSUSB_U2_CTRL(i));
3886 +               temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
3887 +               writel(temp, SSUSB_U2_CTRL(i));
3888 +       }
3889 +       msleep(100);
3890 +}
3891 +
3892 +
3893 +//(X)disable clock/power of a port
3894 +//(X)if all ports are disabled, disable IP ctrl power
3895 +//disable all ports and IP clock/power, this is just mention HW that the power/clock of port
3896 +//and IP could be disable if suspended.
3897 +//If doesn't not disable all ports at first, the IP clock/power will never be disabled
3898 +//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
3899 +//port_index: port number
3900 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3901 +void disablePortClockPower(void){
3902 +       int i;
3903 +       u32 temp;
3904 +
3905 +       g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
3906 +       g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
3907 +
3908 +       for(i=0; i<g_num_u3_port; i++){
3909 +               temp = readl(SSUSB_U3_CTRL(i));
3910 +               temp = temp | (SSUSB_U3_PORT_PDN);
3911 +               writel(temp, SSUSB_U3_CTRL(i));
3912 +       }
3913 +       for(i=0; i<g_num_u2_port; i++){
3914 +               temp = readl(SSUSB_U2_CTRL(i));
3915 +               temp = temp | (SSUSB_U2_PORT_PDN);
3916 +               writel(temp, SSUSB_U2_CTRL(i));
3917 +       }
3918 +       writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3919 +}
3920 +
3921 +//if IP ctrl power is disabled, enable it
3922 +//enable clock/power of a port
3923 +//port_index: port number
3924 +//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
3925 +void enablePortClockPower(int port_index, int port_rev){
3926 +       int i;
3927 +       u32 temp;
3928 +
3929 +       writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
3930 +
3931 +       if(port_rev == 0x3){
3932 +               temp = readl(SSUSB_U3_CTRL(port_index));
3933 +               temp = temp & (~SSUSB_U3_PORT_PDN);
3934 +               writel(temp, SSUSB_U3_CTRL(port_index));
3935 +       }
3936 +       else if(port_rev == 0x2){
3937 +               temp = readl(SSUSB_U2_CTRL(port_index));
3938 +               temp = temp & (~SSUSB_U2_PORT_PDN);
3939 +               writel(temp, SSUSB_U2_CTRL(port_index));
3940 +       }
3941 +}
3942 +
3943 --- /dev/null
3944 +++ b/drivers/usb/host/xhci-mtk-power.h
3945 @@ -0,0 +1,13 @@
3946 +#ifndef _XHCI_MTK_POWER_H
3947 +#define _XHCI_MTK_POWER_H
3948 +
3949 +#include <linux/usb.h>
3950 +#include "xhci.h"
3951 +#include "xhci-mtk.h"
3952 +
3953 +void enableXhciAllPortPower(struct xhci_hcd *xhci);
3954 +void enableAllClockPower(void);
3955 +void disablePortClockPower(void);
3956 +void enablePortClockPower(int port_index, int port_rev);
3957 +
3958 +#endif
3959 --- /dev/null
3960 +++ b/drivers/usb/host/xhci-mtk-scheduler.c
3961 @@ -0,0 +1,608 @@
3962 +#include "xhci-mtk-scheduler.h"
3963 +#include <linux/kernel.h>       /* printk() */
3964 +
3965 +static struct sch_ep **ss_out_eps[MAX_EP_NUM];
3966 +static struct sch_ep **ss_in_eps[MAX_EP_NUM];
3967 +static struct sch_ep **hs_eps[MAX_EP_NUM];     //including tt isoc
3968 +static struct sch_ep **tt_intr_eps[MAX_EP_NUM];
3969 +
3970 +
3971 +int mtk_xhci_scheduler_init(void){
3972 +       int i;
3973 +
3974 +       for(i=0; i<MAX_EP_NUM; i++){
3975 +               ss_out_eps[i] = NULL;
3976 +       }
3977 +       for(i=0; i<MAX_EP_NUM; i++){
3978 +               ss_in_eps[i] = NULL;
3979 +       }
3980 +       for(i=0; i<MAX_EP_NUM; i++){
3981 +               hs_eps[i] = NULL;
3982 +       }
3983 +       for(i=0; i<MAX_EP_NUM; i++){
3984 +               tt_intr_eps[i] = NULL;
3985 +       }
3986 +       return 0;
3987 +}
3988 +
3989 +int add_sch_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
3990 +       , int mult, int offset, int repeat, int pkts, int cs_count, int burst_mode
3991 +       , int bw_cost, mtk_u32 *ep, struct sch_ep *tmp_ep){
3992 +
3993 +       struct sch_ep **ep_array;
3994 +       int i;
3995 +
3996 +       if(is_in && dev_speed == USB_SPEED_SUPER ){
3997 +               ep_array = (struct sch_ep **)ss_in_eps;
3998 +       }
3999 +       else if(dev_speed == USB_SPEED_SUPER){
4000 +               ep_array = (struct sch_ep **)ss_out_eps;
4001 +       }
4002 +       else if(dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)){
4003 +               ep_array = (struct sch_ep **)hs_eps;
4004 +       }
4005 +       else{
4006 +               ep_array = (struct sch_ep **)tt_intr_eps;
4007 +       }
4008 +       for(i=0; i<MAX_EP_NUM; i++){
4009 +               if(ep_array[i] == NULL){
4010 +                       tmp_ep->dev_speed = dev_speed;
4011 +                       tmp_ep->isTT = isTT;
4012 +                       tmp_ep->is_in = is_in;
4013 +                       tmp_ep->ep_type = ep_type;
4014 +                       tmp_ep->maxp = maxp;
4015 +                       tmp_ep->interval = interval;
4016 +                       tmp_ep->burst = burst;
4017 +                       tmp_ep->mult = mult;
4018 +                       tmp_ep->offset = offset;
4019 +                       tmp_ep->repeat = repeat;
4020 +                       tmp_ep->pkts = pkts;
4021 +                       tmp_ep->cs_count = cs_count;
4022 +                       tmp_ep->burst_mode = burst_mode;
4023 +                       tmp_ep->bw_cost = bw_cost;
4024 +                       tmp_ep->ep = ep;
4025 +                       ep_array[i] = tmp_ep;
4026 +                       return SCH_SUCCESS;
4027 +               }
4028 +       }
4029 +       return SCH_FAIL;
4030 +}
4031 +
4032 +int count_ss_bw(int is_in, int ep_type, int maxp, int interval, int burst, int mult, int offset, int repeat
4033 +       , int td_size){
4034 +       int i, j, k;
4035 +       int bw_required[3];
4036 +       int final_bw_required;
4037 +       int bw_required_per_repeat;
4038 +       int tmp_bw_required;
4039 +       struct sch_ep *cur_sch_ep;
4040 +       struct sch_ep **ep_array;
4041 +       int cur_offset;
4042 +       int cur_ep_offset;
4043 +       int tmp_offset;
4044 +       int tmp_interval;
4045 +       int ep_offset;
4046 +       int ep_interval;
4047 +       int ep_repeat;
4048 +       int ep_mult;
4049 +
4050 +       if(is_in){
4051 +               ep_array = (struct sch_ep **)ss_in_eps;
4052 +       }
4053 +       else{
4054 +               ep_array = (struct sch_ep **)ss_out_eps;
4055 +       }
4056 +
4057 +       bw_required[0] = 0;
4058 +       bw_required[1] = 0;
4059 +       bw_required[2] = 0;
4060 +
4061 +       if(repeat == 0){
4062 +               final_bw_required = 0;
4063 +               for(i=0; i<MAX_EP_NUM; i++){
4064 +                       cur_sch_ep = ep_array[i];
4065 +                       if(cur_sch_ep == NULL){
4066 +                               continue;
4067 +                       }
4068 +                       ep_interval = cur_sch_ep->interval;
4069 +                       ep_offset = cur_sch_ep->offset;
4070 +                       if(cur_sch_ep->repeat == 0){
4071 +                               if(ep_interval >= interval){
4072 +                                       tmp_offset = ep_offset + ep_interval - offset;
4073 +                                       tmp_interval = interval;
4074 +                               }
4075 +                               else{
4076 +                                       tmp_offset = offset + interval - ep_offset;
4077 +                                       tmp_interval = ep_interval;
4078 +                               }
4079 +                               if(tmp_offset % tmp_interval == 0){
4080 +                                       final_bw_required += cur_sch_ep->bw_cost;
4081 +                               }
4082 +                       }
4083 +                       else{
4084 +                               ep_repeat = cur_sch_ep->repeat;
4085 +                               ep_mult = cur_sch_ep->mult;
4086 +                               for(k=0; k<=ep_mult; k++){
4087 +                                       cur_ep_offset = ep_offset+(k*ep_mult);
4088 +                                       if(ep_interval >= interval){
4089 +                                               tmp_offset = cur_ep_offset + ep_interval - offset;
4090 +                                               tmp_interval = interval;
4091 +                                       }
4092 +                                       else{
4093 +                                               tmp_offset = offset + interval - cur_ep_offset;
4094 +                                               tmp_interval = ep_interval;
4095 +                                       }
4096 +                                       if(tmp_offset % tmp_interval == 0){
4097 +                                               final_bw_required += cur_sch_ep->bw_cost;
4098 +                                               break;
4099 +                                       }
4100 +                               }
4101 +                       }
4102 +               }
4103 +               final_bw_required += td_size;
4104 +       }
4105 +       else{
4106 +               bw_required_per_repeat = maxp * (burst+1);
4107 +               for(j=0; j<=mult; j++){
4108 +                       tmp_bw_required = 0;
4109 +                       cur_offset = offset+(j*repeat);
4110 +                       for(i=0; i<MAX_EP_NUM; i++){
4111 +                               cur_sch_ep = ep_array[i];
4112 +                               if(cur_sch_ep == NULL){
4113 +                                       continue;
4114 +                               }
4115 +                               ep_interval = cur_sch_ep->interval;
4116 +                               ep_offset = cur_sch_ep->offset;
4117 +                               if(cur_sch_ep->repeat == 0){
4118 +                                       if(ep_interval >= interval){
4119 +                                               tmp_offset = ep_offset + ep_interval - cur_offset;
4120 +                                               tmp_interval = interval;
4121 +                                       }
4122 +                                       else{
4123 +                                               tmp_offset = cur_offset + interval - ep_offset;
4124 +                                               tmp_interval = ep_interval;
4125 +                                       }
4126 +                                       if(tmp_offset % tmp_interval == 0){
4127 +                                               tmp_bw_required += cur_sch_ep->bw_cost;
4128 +                                       }
4129 +                               }
4130 +                               else{
4131 +                                       ep_repeat = cur_sch_ep->repeat;
4132 +                                       ep_mult = cur_sch_ep->mult;
4133 +                                       for(k=0; k<=ep_mult; k++){
4134 +                                               cur_ep_offset = ep_offset+(k*ep_repeat);
4135 +                                               if(ep_interval >= interval){
4136 +                                                       tmp_offset = cur_ep_offset + ep_interval - cur_offset;
4137 +                                                       tmp_interval = interval;
4138 +                                               }
4139 +                                               else{
4140 +                                                       tmp_offset = cur_offset + interval - cur_ep_offset;
4141 +                                                       tmp_interval = ep_interval;
4142 +                                               }
4143 +                                               if(tmp_offset % tmp_interval == 0){
4144 +                                                       tmp_bw_required += cur_sch_ep->bw_cost;
4145 +                                                       break;
4146 +                                               }
4147 +                                       }
4148 +                               }
4149 +                       }
4150 +                       bw_required[j] = tmp_bw_required;
4151 +               }
4152 +               final_bw_required = SS_BW_BOUND;
4153 +               for(j=0; j<=mult; j++){
4154 +                       if(bw_required[j] < final_bw_required){
4155 +                               final_bw_required = bw_required[j];
4156 +                       }
4157 +               }
4158 +               final_bw_required += bw_required_per_repeat;
4159 +       }
4160 +       return final_bw_required;
4161 +}
4162 +
4163 +int count_hs_bw(int ep_type, int maxp, int interval, int offset, int td_size){
4164 +       int i;
4165 +       int bw_required;
4166 +       struct sch_ep *cur_sch_ep;
4167 +       int tmp_offset;
4168 +       int tmp_interval;
4169 +       int ep_offset;
4170 +       int ep_interval;
4171 +       int cur_tt_isoc_interval;       //for isoc tt check
4172 +
4173 +       bw_required = 0;
4174 +       for(i=0; i<MAX_EP_NUM; i++){
4175 +
4176 +               cur_sch_ep = (struct sch_ep *)hs_eps[i];
4177 +               if(cur_sch_ep == NULL){
4178 +                               continue;
4179 +               }
4180 +               ep_offset = cur_sch_ep->offset;
4181 +               ep_interval = cur_sch_ep->interval;
4182 +
4183 +               if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4184 +                       cur_tt_isoc_interval = ep_interval<<3;
4185 +                       if(ep_interval >= interval){
4186 +                               tmp_offset = ep_offset + cur_tt_isoc_interval - offset;
4187 +                               tmp_interval = interval;
4188 +                       }
4189 +                       else{
4190 +                               tmp_offset = offset + interval - ep_offset;
4191 +                               tmp_interval = cur_tt_isoc_interval;
4192 +                       }
4193 +                       if(cur_sch_ep->is_in){
4194 +                               if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4195 +                                       bw_required += 188;
4196 +                               }
4197 +                       }
4198 +                       else{
4199 +                               if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4200 +                                       bw_required += 188;
4201 +                               }
4202 +                       }
4203 +               }
4204 +               else{
4205 +                       if(ep_interval >= interval){
4206 +                               tmp_offset = ep_offset + ep_interval - offset;
4207 +                               tmp_interval = interval;
4208 +                       }
4209 +                       else{
4210 +                               tmp_offset = offset + interval - ep_offset;
4211 +                               tmp_interval = ep_interval;
4212 +                       }
4213 +                       if(tmp_offset%tmp_interval == 0){
4214 +                               bw_required += cur_sch_ep->bw_cost;
4215 +                       }
4216 +               }
4217 +       }
4218 +       bw_required += td_size;
4219 +       return bw_required;
4220 +}
4221 +
4222 +int count_tt_isoc_bw(int is_in, int maxp, int interval, int offset, int td_size){
4223 +       char is_cs;
4224 +       int mframe_idx, frame_idx, s_frame, s_mframe, cur_mframe;
4225 +       int bw_required, max_bw;
4226 +       int ss_cs_count;
4227 +       int cs_mframe;
4228 +       int max_frame;
4229 +       int i,j;
4230 +       struct sch_ep *cur_sch_ep;
4231 +       int ep_offset;
4232 +       int ep_interval;
4233 +       int ep_cs_count;
4234 +       int tt_isoc_interval;   //for isoc tt check
4235 +       int cur_tt_isoc_interval;       //for isoc tt check
4236 +       int tmp_offset;
4237 +       int tmp_interval;
4238 +
4239 +       is_cs = 0;
4240 +
4241 +       tt_isoc_interval = interval<<3; //frame to mframe
4242 +       if(is_in){
4243 +               is_cs = 1;
4244 +       }
4245 +       s_frame = offset/8;
4246 +       s_mframe = offset%8;
4247 +       ss_cs_count = (maxp + (188 - 1))/188;
4248 +       if(is_cs){
4249 +               cs_mframe = offset%8 + 2 + ss_cs_count;
4250 +               if (cs_mframe <= 6)
4251 +                       ss_cs_count += 2;
4252 +               else if (cs_mframe == 7)
4253 +                       ss_cs_count++;
4254 +               else if (cs_mframe > 8)
4255 +                       return -1;
4256 +       }
4257 +       max_bw = 0;
4258 +       if(is_in){
4259 +               i=2;
4260 +       }
4261 +       for(cur_mframe = offset+i; i<ss_cs_count; cur_mframe++, i++){
4262 +               bw_required = 0;
4263 +               for(j=0; j<MAX_EP_NUM; j++){
4264 +                       cur_sch_ep = (struct sch_ep *)hs_eps[j];
4265 +                       if(cur_sch_ep == NULL){
4266 +                               continue;
4267 +                       }
4268 +                       ep_offset = cur_sch_ep->offset;
4269 +                       ep_interval = cur_sch_ep->interval;
4270 +                       if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
4271 +                               //isoc tt
4272 +                               //check if mframe offset overlap
4273 +                               //if overlap, add 188 to the bw
4274 +                               cur_tt_isoc_interval = ep_interval<<3;
4275 +                               if(cur_tt_isoc_interval >= tt_isoc_interval){
4276 +                                       tmp_offset = (ep_offset+cur_tt_isoc_interval)  - cur_mframe;
4277 +                                       tmp_interval = tt_isoc_interval;
4278 +                               }
4279 +                               else{
4280 +                                       tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4281 +                                       tmp_interval = cur_tt_isoc_interval;
4282 +                               }
4283 +                               if(cur_sch_ep->is_in){
4284 +                                       if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
4285 +                                               bw_required += 188;
4286 +                                       }
4287 +                               }
4288 +                               else{
4289 +                                       if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
4290 +                                               bw_required += 188;
4291 +                                       }
4292 +                               }
4293 +
4294 +                       }
4295 +                       else if(cur_sch_ep->ep_type == USB_EP_INT || cur_sch_ep->ep_type == USB_EP_ISOC){
4296 +                               //check if mframe
4297 +                               if(ep_interval >= tt_isoc_interval){
4298 +                                       tmp_offset = (ep_offset+ep_interval) - cur_mframe;
4299 +                                       tmp_interval = tt_isoc_interval;
4300 +                               }
4301 +                               else{
4302 +                                       tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
4303 +                                       tmp_interval = ep_interval;
4304 +                               }
4305 +                               if(tmp_offset%tmp_interval == 0){
4306 +                                       bw_required += cur_sch_ep->bw_cost;
4307 +                               }
4308 +                       }
4309 +               }
4310 +               bw_required += 188;
4311 +               if(bw_required > max_bw){
4312 +                       max_bw = bw_required;
4313 +               }
4314 +       }
4315 +       return max_bw;
4316 +}
4317 +
4318 +int count_tt_intr_bw(int interval, int frame_offset){
4319 +       //check all eps in tt_intr_eps
4320 +       int ret;
4321 +       int i,j;
4322 +       int ep_offset;
4323 +       int ep_interval;
4324 +       int tmp_offset;
4325 +       int tmp_interval;
4326 +       ret = SCH_SUCCESS;
4327 +       struct sch_ep *cur_sch_ep;
4328 +
4329 +       for(i=0; i<MAX_EP_NUM; i++){
4330 +               cur_sch_ep = (struct sch_ep *)tt_intr_eps[i];
4331 +               if(cur_sch_ep == NULL){
4332 +                       continue;
4333 +               }
4334 +               ep_offset = cur_sch_ep->offset;
4335 +               ep_interval = cur_sch_ep->interval;
4336 +               if(ep_interval  >= interval){
4337 +                       tmp_offset = ep_offset + ep_interval - frame_offset;
4338 +                       tmp_interval = interval;
4339 +               }
4340 +               else{
4341 +                       tmp_offset = frame_offset + interval - ep_offset;
4342 +                       tmp_interval = ep_interval;
4343 +               }
4344 +
4345 +               if(tmp_offset%tmp_interval==0){
4346 +                       return SCH_FAIL;
4347 +               }
4348 +       }
4349 +       return SCH_SUCCESS;
4350 +}
4351 +
4352 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep){
4353 +       int i;
4354 +       struct sch_ep **ep_array;
4355 +       struct sch_ep *cur_ep;
4356 +
4357 +       if (is_in && dev_speed == USB_SPEED_SUPER) {
4358 +               ep_array = (struct sch_ep **)ss_in_eps;
4359 +       }
4360 +       else if (dev_speed == USB_SPEED_SUPER) {
4361 +               ep_array = (struct sch_ep **)ss_out_eps;
4362 +       }
4363 +       else if (dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)) {
4364 +               ep_array = (struct sch_ep **)hs_eps;
4365 +       }
4366 +       else {
4367 +               ep_array = (struct sch_ep **)tt_intr_eps;
4368 +       }
4369 +       for (i = 0; i < MAX_EP_NUM; i++) {
4370 +               cur_ep = (struct sch_ep *)ep_array[i];
4371 +               if(cur_ep != NULL && cur_ep->ep == ep){
4372 +                       ep_array[i] = NULL;
4373 +                       return cur_ep;
4374 +               }
4375 +       }
4376 +       return NULL;
4377 +}
4378 +
4379 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4380 +       , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep){
4381 +       mtk_u32 bPkts = 0;
4382 +       mtk_u32 bCsCount = 0;
4383 +       mtk_u32 bBm = 1;
4384 +       mtk_u32 bOffset = 0;
4385 +       mtk_u32 bRepeat = 0;
4386 +       int ret;
4387 +       struct mtk_xhci_ep_ctx *temp_ep_ctx;
4388 +       int td_size;
4389 +       int mframe_idx, frame_idx;
4390 +       int bw_cost;
4391 +       int cur_bw, best_bw, best_bw_idx,repeat, max_repeat, best_bw_repeat;
4392 +       int cur_offset, cs_mframe;
4393 +       int break_out;
4394 +       int frame_interval;
4395 +
4396 +       printk(KERN_ERR "add_ep parameters, dev_speed %d, is_in %d, isTT %d, ep_type %d, maxp %d, interval %d, burst %d, mult %d, ep 0x%x, ep_ctx 0x%x, sch_ep 0x%x\n", dev_speed, is_in, isTT, ep_type, maxp
4397 +               , interval, burst, mult, ep, ep_ctx, sch_ep);
4398 +       if(isTT && ep_type == USB_EP_INT && ((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL))){
4399 +               frame_interval = interval >> 3;
4400 +               for(frame_idx=0; frame_idx<frame_interval; frame_idx++){
4401 +                       printk(KERN_ERR "check tt_intr_bw interval %d, frame_idx %d\n", frame_interval, frame_idx);
4402 +                       if(count_tt_intr_bw(frame_interval, frame_idx) == SCH_SUCCESS){
4403 +                               printk(KERN_ERR "check OK............\n");
4404 +                               bOffset = frame_idx<<3;
4405 +                               bPkts = 1;
4406 +                               bCsCount = 3;
4407 +                               bw_cost = maxp;
4408 +                               bRepeat = 0;
4409 +                               if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, frame_interval, burst, mult
4410 +                                       , bOffset, bRepeat, bPkts, bCsCount, bBm, maxp, ep, sch_ep) == SCH_FAIL){
4411 +                                       return SCH_FAIL;
4412 +                               }
4413 +                               ret = SCH_SUCCESS;
4414 +                               break;
4415 +                       }
4416 +               }
4417 +       }
4418 +       else if(isTT && ep_type == USB_EP_ISOC){
4419 +               best_bw = HS_BW_BOUND;
4420 +               best_bw_idx = -1;
4421 +               cur_bw = 0;
4422 +               td_size = maxp;
4423 +               break_out = 0;
4424 +               frame_interval = interval>>3;
4425 +               for(frame_idx=0; frame_idx<frame_interval && !break_out; frame_idx++){
4426 +                       for(mframe_idx=0; mframe_idx<8; mframe_idx++){
4427 +                               cur_offset = (frame_idx*8) + mframe_idx;
4428 +                               cur_bw = count_tt_isoc_bw(is_in, maxp, frame_interval, cur_offset, td_size);
4429 +                               if(cur_bw > 0 && cur_bw < best_bw){
4430 +                                       best_bw_idx = cur_offset;
4431 +                                       best_bw = cur_bw;
4432 +                                       if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4433 +                                               break_out = 1;
4434 +                                               break;
4435 +                                       }
4436 +                               }
4437 +                       }
4438 +               }
4439 +               if(best_bw_idx == -1){
4440 +                       return SCH_FAIL;
4441 +               }
4442 +               else{
4443 +                       bOffset = best_bw_idx;
4444 +                       bPkts = 1;
4445 +                       bCsCount = (maxp + (188 - 1)) / 188;
4446 +                       if(is_in){
4447 +                               cs_mframe = bOffset%8 + 2 + bCsCount;
4448 +                               if (cs_mframe <= 6)
4449 +                                       bCsCount += 2;
4450 +                               else if (cs_mframe == 7)
4451 +                                       bCsCount++;
4452 +                       }
4453 +                       bw_cost = 188;
4454 +                       bRepeat = 0;
4455 +                       if(add_sch_ep( dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4456 +                               , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4457 +                               return SCH_FAIL;
4458 +                       }
4459 +                       ret = SCH_SUCCESS;
4460 +               }
4461 +       }
4462 +       else if((dev_speed == USB_SPEED_FULL || dev_speed == USB_SPEED_LOW) && ep_type == USB_EP_INT){
4463 +               bPkts = 1;
4464 +               ret = SCH_SUCCESS;
4465 +       }
4466 +       else if(dev_speed == USB_SPEED_FULL && ep_type == USB_EP_ISOC){
4467 +               bPkts = 1;
4468 +               ret = SCH_SUCCESS;
4469 +       }
4470 +       else if(dev_speed == USB_SPEED_HIGH && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4471 +               best_bw = HS_BW_BOUND;
4472 +               best_bw_idx = -1;
4473 +               cur_bw = 0;
4474 +               td_size = maxp*(burst+1);
4475 +               for(cur_offset = 0; cur_offset<interval; cur_offset++){
4476 +                       cur_bw = count_hs_bw(ep_type, maxp, interval, cur_offset, td_size);
4477 +                       if(cur_bw > 0 && cur_bw < best_bw){
4478 +                               best_bw_idx = cur_offset;
4479 +                               best_bw = cur_bw;
4480 +                               if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
4481 +                                       break;
4482 +                               }
4483 +                       }
4484 +               }
4485 +               if(best_bw_idx == -1){
4486 +                       return SCH_FAIL;
4487 +               }
4488 +               else{
4489 +                       bOffset = best_bw_idx;
4490 +                       bPkts = burst + 1;
4491 +                       bCsCount = 0;
4492 +                       bw_cost = td_size;
4493 +                       bRepeat = 0;
4494 +                       if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4495 +                               , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4496 +                               return SCH_FAIL;
4497 +                       }
4498 +                       ret = SCH_SUCCESS;
4499 +               }
4500 +       }
4501 +       else if(dev_speed == USB_SPEED_SUPER && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
4502 +               best_bw = SS_BW_BOUND;
4503 +               best_bw_idx = -1;
4504 +               cur_bw = 0;
4505 +               td_size = maxp * (mult+1) * (burst+1);
4506 +               if(mult == 0){
4507 +                       max_repeat = 0;
4508 +               }
4509 +               else{
4510 +                       max_repeat = (interval-1)/(mult+1);
4511 +               }
4512 +               break_out = 0;
4513 +               for(frame_idx = 0; (frame_idx < interval) && !break_out; frame_idx++){
4514 +                       for(repeat = max_repeat; repeat >= 0; repeat--){
4515 +                               cur_bw = count_ss_bw(is_in, ep_type, maxp, interval, burst, mult, frame_idx
4516 +                                       , repeat, td_size);
4517 +                               printk(KERN_ERR "count_ss_bw, frame_idx %d, repeat %d, td_size %d, result bw %d\n"
4518 +                                       , frame_idx, repeat, td_size, cur_bw);
4519 +                               if(cur_bw > 0 && cur_bw < best_bw){
4520 +                                       best_bw_idx = frame_idx;
4521 +                                       best_bw_repeat = repeat;
4522 +                                       best_bw = cur_bw;
4523 +                                       if(cur_bw <= td_size || cur_bw < (HS_BW_BOUND>>1)){
4524 +                                               break_out = 1;
4525 +                                               break;
4526 +                                       }
4527 +                               }
4528 +                       }
4529 +               }
4530 +               printk(KERN_ERR "final best idx %d, best repeat %d\n", best_bw_idx, best_bw_repeat);
4531 +               if(best_bw_idx == -1){
4532 +                       return SCH_FAIL;
4533 +               }
4534 +               else{
4535 +                       bOffset = best_bw_idx;
4536 +                       bCsCount = 0;
4537 +                       bRepeat = best_bw_repeat;
4538 +                       if(bRepeat == 0){
4539 +                               bw_cost = (burst+1)*(mult+1)*maxp;
4540 +                               bPkts = (burst+1)*(mult+1);
4541 +                       }
4542 +                       else{
4543 +                               bw_cost = (burst+1)*maxp;
4544 +                               bPkts = (burst+1);
4545 +                       }
4546 +                       if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
4547 +                               , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
4548 +                               return SCH_FAIL;
4549 +                       }
4550 +                       ret = SCH_SUCCESS;
4551 +               }
4552 +       }
4553 +       else{
4554 +               bPkts = 1;
4555 +               ret = SCH_SUCCESS;
4556 +       }
4557 +       if(ret == SCH_SUCCESS){
4558 +               temp_ep_ctx = (struct mtk_xhci_ep_ctx *)ep_ctx;
4559 +               temp_ep_ctx->reserved[0] |= (BPKTS(bPkts) | BCSCOUNT(bCsCount) | BBM(bBm));
4560 +               temp_ep_ctx->reserved[1] |= (BOFFSET(bOffset) | BREPEAT(bRepeat));
4561 +
4562 +               printk(KERN_DEBUG "[DBG] BPKTS: %x, BCSCOUNT: %x, BBM: %x\n", bPkts, bCsCount, bBm);
4563 +               printk(KERN_DEBUG "[DBG] BOFFSET: %x, BREPEAT: %x\n", bOffset, bRepeat);
4564 +               return SCH_SUCCESS;
4565 +       }
4566 +       else{
4567 +               return SCH_FAIL;
4568 +       }
4569 +}
4570 --- /dev/null
4571 +++ b/drivers/usb/host/xhci-mtk-scheduler.h
4572 @@ -0,0 +1,77 @@
4573 +#ifndef _XHCI_MTK_SCHEDULER_H
4574 +#define _XHCI_MTK_SCHEDULER_H
4575 +
4576 +#define MTK_SCH_NEW            1
4577 +
4578 +#define SCH_SUCCESS            1
4579 +#define SCH_FAIL               0
4580 +
4581 +#define MAX_EP_NUM             64
4582 +#define SS_BW_BOUND            51000
4583 +#define HS_BW_BOUND            6144
4584 +
4585 +#define USB_EP_CONTROL         0
4586 +#define USB_EP_ISOC            1
4587 +#define USB_EP_BULK            2
4588 +#define USB_EP_INT             3
4589 +
4590 +#define USB_SPEED_LOW          1
4591 +#define USB_SPEED_FULL         2
4592 +#define USB_SPEED_HIGH         3
4593 +#define USB_SPEED_SUPER                5
4594 +
4595 +/* mtk scheduler bitmasks */
4596 +#define BPKTS(p)               ((p) & 0x3f)
4597 +#define BCSCOUNT(p)            (((p) & 0x7) << 8)
4598 +#define BBM(p)                 ((p) << 11)
4599 +#define BOFFSET(p)             ((p) & 0x3fff)
4600 +#define BREPEAT(p)             (((p) & 0x7fff) << 16)
4601 +
4602 +
4603 +#if 1
4604 +typedef unsigned int mtk_u32;
4605 +typedef unsigned long long mtk_u64;
4606 +#endif
4607 +
4608 +#define NULL ((void *)0)
4609 +
4610 +struct mtk_xhci_ep_ctx {
4611 +       mtk_u32 ep_info;
4612 +       mtk_u32 ep_info2;
4613 +       mtk_u64 deq;
4614 +       mtk_u32 tx_info;
4615 +       /* offset 0x14 - 0x1f reserved for HC internal use */
4616 +       mtk_u32 reserved[3];
4617 +};
4618 +
4619 +
4620 +struct sch_ep
4621 +{
4622 +       //device info
4623 +       int dev_speed;
4624 +       int isTT;
4625 +       //ep info
4626 +       int is_in;
4627 +       int ep_type;
4628 +       int maxp;
4629 +       int interval;
4630 +       int burst;
4631 +       int mult;
4632 +       //scheduling info
4633 +       int offset;
4634 +       int repeat;
4635 +       int pkts;
4636 +       int cs_count;
4637 +       int burst_mode;
4638 +       //other
4639 +       int bw_cost;    //bandwidth cost in each repeat; including overhead
4640 +       mtk_u32 *ep;            //address of usb_endpoint pointer
4641 +};
4642 +
4643 +int mtk_xhci_scheduler_init(void);
4644 +int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
4645 +       , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep);
4646 +struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep);
4647 +
4648 +
4649 +#endif
4650 --- /dev/null
4651 +++ b/drivers/usb/host/xhci-mtk.c
4652 @@ -0,0 +1,265 @@
4653 +#include "xhci-mtk.h"
4654 +#include "xhci-mtk-power.h"
4655 +#include "xhci.h"
4656 +#include "mtk-phy.h"
4657 +#ifdef CONFIG_C60802_SUPPORT
4658 +#include "mtk-phy-c60802.h"
4659 +#endif
4660 +#include "xhci-mtk-scheduler.h"
4661 +#include <linux/kernel.h>       /* printk() */
4662 +#include <linux/slab.h>
4663 +#include <linux/delay.h>
4664 +#include <asm/uaccess.h>
4665 +#include <linux/dma-mapping.h>
4666 +#include <linux/platform_device.h>
4667 +
4668 +void setInitialReg(void )
4669 +{
4670 +       __u32 __iomem *addr;
4671 +       u32 temp;
4672 +
4673 +       /* set SSUSB DMA burst size to 128B */
4674 +       addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
4675 +       temp = SSUSB_HDMA_CFG_MT7621_VALUE;
4676 +       writel(temp, addr);
4677 +
4678 +       /* extend U3 LTSSM Polling.LFPS timeout value */
4679 +       addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
4680 +       temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
4681 +       writel(temp, addr);
4682 +
4683 +       /* EOF */
4684 +       addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
4685 +       temp = SYNC_HS_EOF_VALUE;
4686 +       writel(temp, addr);
4687 +
4688 +#if defined (CONFIG_PERIODIC_ENP)
4689 +       /* HSCH_CFG1: SCH2_FIFO_DEPTH */
4690 +       addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
4691 +       temp = readl(addr);
4692 +       temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
4693 +       writel(temp, addr);
4694 +#endif
4695 +
4696 +       /* Doorbell handling */
4697 +       addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
4698 +       temp = 0x1;
4699 +       writel(temp, addr);
4700 +
4701 +       /* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
4702 +       /* Port 0 */
4703 +       addr = U2_PHY_BASE + U2_PHYD_CR1;
4704 +       temp = readl(addr);
4705 +       temp &= ~(0x3 << 18);
4706 +       temp |= (1 << 18);
4707 +       writel(temp, addr);
4708 +
4709 +       /* Port 1 */
4710 +       addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
4711 +       temp = readl(addr);
4712 +       temp &= ~(0x3 << 18);
4713 +       temp |= (1 << 18);
4714 +       writel(temp, addr);
4715 +}
4716 +
4717 +
4718 +void setLatchSel(void){
4719 +       __u32 __iomem *latch_sel_addr;
4720 +       u32 latch_sel_value;
4721 +       latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
4722 +       latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
4723 +       writel(latch_sel_value, latch_sel_addr);
4724 +}
4725 +
4726 +void reinitIP(void){
4727 +       __u32 __iomem *ip_reset_addr;
4728 +       u32 ip_reset_value;
4729 +
4730 +       enableAllClockPower();
4731 +       mtk_xhci_scheduler_init();
4732 +}
4733 +
4734 +void dbg_prb_out(void){
4735 +       mtk_probe_init(0x0f0f0f0f);
4736 +       mtk_probe_out(0xffffffff);
4737 +       mtk_probe_out(0x01010101);
4738 +       mtk_probe_out(0x02020202);
4739 +       mtk_probe_out(0x04040404);
4740 +       mtk_probe_out(0x08080808);
4741 +       mtk_probe_out(0x10101010);
4742 +       mtk_probe_out(0x20202020);
4743 +       mtk_probe_out(0x40404040);
4744 +       mtk_probe_out(0x80808080);
4745 +       mtk_probe_out(0x55555555);
4746 +       mtk_probe_out(0xaaaaaaaa);
4747 +}
4748 +
4749 +
4750 +
4751 +///////////////////////////////////////////////////////////////////////////////
4752 +
4753 +#define RET_SUCCESS 0
4754 +#define RET_FAIL 1
4755 +
4756 +static int dbg_u3w(int argc, char**argv)
4757 +{
4758 +       int u4TimingValue;
4759 +       char u1TimingValue;
4760 +       int u4TimingAddress;
4761 +
4762 +       if (argc<3)
4763 +    {
4764 +        printk(KERN_ERR "Arg: address value\n");
4765 +        return RET_FAIL;
4766 +    }
4767 +       u3phy_init();
4768 +
4769 +       u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4770 +       u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
4771 +       u1TimingValue = u4TimingValue & 0xff;
4772 +       /* access MMIO directly */
4773 +       writel(u1TimingValue, u4TimingAddress);
4774 +       printk(KERN_ERR "Write done\n");
4775 +       return RET_SUCCESS;
4776 +
4777 +}
4778 +
4779 +static int dbg_u3r(int argc, char**argv)
4780 +{
4781 +       char u1ReadTimingValue;
4782 +       int u4TimingAddress;
4783 +       if (argc<2)
4784 +    {
4785 +        printk(KERN_ERR "Arg: address\n");
4786 +        return 0;
4787 +    }
4788 +       u3phy_init();
4789 +       mdelay(500);
4790 +       u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
4791 +       /* access MMIO directly */
4792 +       u1ReadTimingValue = readl(u4TimingAddress);
4793 +       printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
4794 +       return 0;
4795 +}
4796 +
4797 +static int dbg_u3init(int argc, char**argv)
4798 +{
4799 +       int ret;
4800 +       ret = u3phy_init();
4801 +       printk(KERN_ERR "phy registers and operations initial done\n");
4802 +       if(u3phy_ops->u2_slew_rate_calibration){
4803 +               u3phy_ops->u2_slew_rate_calibration(u3phy);
4804 +       }
4805 +       else{
4806 +               printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
4807 +       }
4808 +       if(u3phy_ops->init(u3phy) == PHY_TRUE)
4809 +               return RET_SUCCESS;
4810 +       return RET_FAIL;
4811 +}
4812 +
4813 +void dbg_setU1U2(int argc, char**argv){
4814 +       struct xhci_hcd *xhci;
4815 +       int u1_value;
4816 +       int u2_value;
4817 +       u32 port_id, temp;
4818 +       u32 __iomem *addr;
4819 +
4820 +       if (argc<3)
4821 +    {
4822 +        printk(KERN_ERR "Arg: u1value u2value\n");
4823 +        return RET_FAIL;
4824 +    }
4825 +
4826 +       u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
4827 +       u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
4828 +       addr = (SSUSB_U3_XHCI_BASE + 0x424);
4829 +       temp = readl(addr);
4830 +       temp = temp & (~(0x0000ffff));
4831 +       temp = temp | u1_value | (u2_value<<8);
4832 +       writel(temp, addr);
4833 +}
4834 +///////////////////////////////////////////////////////////////////////////////
4835 +
4836 +int call_function(char *buf)
4837 +{
4838 +       int i;
4839 +       int argc;
4840 +       char *argv[80];
4841 +
4842 +       argc = 0;
4843 +       do
4844 +       {
4845 +               argv[argc] = strsep(&buf, " ");
4846 +               printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
4847 +               argc++;
4848 +       } while (buf);
4849 +       if (!strcmp("dbg.r", argv[0]))
4850 +               dbg_prb_out();
4851 +       else if (!strcmp("dbg.u3w", argv[0]))
4852 +               dbg_u3w(argc, argv);
4853 +       else if (!strcmp("dbg.u3r", argv[0]))
4854 +               dbg_u3r(argc, argv);
4855 +       else if (!strcmp("dbg.u3i", argv[0]))
4856 +               dbg_u3init(argc, argv);
4857 +       else if (!strcmp("pw.u1u2", argv[0]))
4858 +               dbg_setU1U2(argc, argv);
4859 +       return 0;
4860 +}
4861 +
4862 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
4863 +{
4864 +       char w_buf[200];
4865 +       char r_buf[200] = "this is a test";
4866 +       int len = 200;
4867 +
4868 +       switch (cmd) {
4869 +               case IOCTL_READ:
4870 +                       copy_to_user((char *) arg, r_buf, len);
4871 +                       printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
4872 +                       break;
4873 +               case IOCTL_WRITE:
4874 +                       copy_from_user(w_buf, (char *) arg, len);
4875 +                       printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
4876 +
4877 +                       //invoke function
4878 +                       return call_function(w_buf);
4879 +                       break;
4880 +               default:
4881 +                       return -ENOTTY;
4882 +       }
4883 +
4884 +       return len;
4885 +}
4886 +
4887 +int xhci_mtk_test_open(struct inode *inode, struct file *file)
4888 +{
4889 +
4890 +    printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
4891 +    return 0;
4892 +}
4893 +
4894 +int xhci_mtk_test_release(struct inode *inode, struct file *file)
4895 +{
4896 +
4897 +    printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
4898 +    return 0;
4899 +}
4900 +
4901 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
4902 +{
4903 +
4904 +    printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
4905 +    return 0;
4906 +}
4907 +
4908 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
4909 +{
4910 +
4911 +    printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
4912 +    return 0;
4913 +}
4914 +
4915 +
4916 +
4917 +
4918 --- /dev/null
4919 +++ b/drivers/usb/host/xhci-mtk.h
4920 @@ -0,0 +1,120 @@
4921 +#ifndef _XHCI_MTK_H
4922 +#define _XHCI_MTK_H
4923 +
4924 +#include <linux/usb.h>
4925 +#include "xhci.h"
4926 +
4927 +#define SSUSB_U3_XHCI_BASE             0xBE1C0000
4928 +#define SSUSB_U3_MAC_BASE              0xBE1C2400
4929 +#define SSUSB_U3_SYS_BASE              0xBE1C2600
4930 +#define SSUSB_U2_SYS_BASE              0xBE1C3400
4931 +#define SSUB_SIF_SLV_TOP               0xBE1D0000
4932 +#define SIFSLV_IPPC                    (SSUB_SIF_SLV_TOP + 0x700)
4933 +
4934 +#define U3_PIPE_LATCH_SEL_ADD          SSUSB_U3_MAC_BASE + 0x130
4935 +#define U3_PIPE_LATCH_TX               0
4936 +#define U3_PIPE_LATCH_RX               0
4937 +
4938 +#define U3_UX_EXIT_LFPS_TIMING_PAR     0xa0
4939 +#define U3_REF_CK_PAR                  0xb0
4940 +#define U3_RX_UX_EXIT_LFPS_REF_OFFSET  8
4941 +#define U3_RX_UX_EXIT_LFPS_REF         3
4942 +#define        U3_REF_CK_VAL                   10
4943 +
4944 +#define U3_TIMING_PULSE_CTRL           0xb4
4945 +#define CNT_1US_VALUE                  63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
4946 +
4947 +#define USB20_TIMING_PARAMETER         0x40
4948 +#define TIME_VALUE_1US                 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
4949 +
4950 +#define LINK_PM_TIMER                  0x8
4951 +#define PM_LC_TIMEOUT_VALUE            3
4952 +
4953 +#define XHCI_IMOD                      0x624
4954 +#define XHCI_IMOD_MT7621_VALUE         0x10
4955 +
4956 +#define SSUSB_HDMA_CFG                 0x950
4957 +#define SSUSB_HDMA_CFG_MT7621_VALUE    0x10E0E0C
4958 +
4959 +#define U3_LTSSM_TIMING_PARAMETER3             0x2514
4960 +#define U3_LTSSM_TIMING_PARAMETER3_VALUE       0x3E8012C
4961 +
4962 +#define U2_PHYD_CR1                    0x64
4963 +
4964 +#define SSUSB_IP_SPAR0                 0xC8
4965 +
4966 +#define SYNC_HS_EOF                    0x938
4967 +#define SYNC_HS_EOF_VALUE              0x201F3
4968 +
4969 +#define HSCH_CFG1                      0x960
4970 +#define SCH2_FIFO_DEPTH_OFFSET         16
4971 +
4972 +
4973 +#define SSUSB_IP_PW_CTRL               (SIFSLV_IPPC+0x0)
4974 +#define SSUSB_IP_SW_RST                        (1<<0)
4975 +#define SSUSB_IP_PW_CTRL_1             (SIFSLV_IPPC+0x4)
4976 +#define SSUSB_IP_PDN                   (1<<0)
4977 +#define SSUSB_U3_CTRL(p)               (SIFSLV_IPPC+0x30+(p*0x08))
4978 +#define SSUSB_U3_PORT_DIS              (1<<0)
4979 +#define SSUSB_U3_PORT_PDN              (1<<1)
4980 +#define SSUSB_U3_PORT_HOST_SEL         (1<<2)
4981 +#define SSUSB_U3_PORT_CKBG_EN          (1<<3)
4982 +#define SSUSB_U3_PORT_MAC_RST          (1<<4)
4983 +#define SSUSB_U3_PORT_PHYD_RST         (1<<5)
4984 +#define SSUSB_U2_CTRL(p)               (SIFSLV_IPPC+(0x50)+(p*0x08))
4985 +#define SSUSB_U2_PORT_DIS              (1<<0)
4986 +#define SSUSB_U2_PORT_PDN              (1<<1)
4987 +#define SSUSB_U2_PORT_HOST_SEL         (1<<2)
4988 +#define SSUSB_U2_PORT_CKBG_EN          (1<<3)
4989 +#define SSUSB_U2_PORT_MAC_RST          (1<<4)
4990 +#define SSUSB_U2_PORT_PHYD_RST         (1<<5)
4991 +#define SSUSB_IP_CAP                   (SIFSLV_IPPC+0x024)
4992 +
4993 +#define SSUSB_U3_PORT_NUM(p)           (p & 0xff)
4994 +#define SSUSB_U2_PORT_NUM(p)           ((p>>8) & 0xff)
4995 +
4996 +
4997 +#define XHCI_MTK_TEST_MAJOR            234
4998 +#define DEVICE_NAME                    "xhci_mtk_test"
4999 +
5000 +#define CLI_MAGIC                      'CLI'
5001 +#define IOCTL_READ                     _IOR(CLI_MAGIC, 0, int)
5002 +#define IOCTL_WRITE                    _IOW(CLI_MAGIC, 1, int)
5003 +
5004 +void reinitIP(void);
5005 +void setInitialReg(void);
5006 +void dbg_prb_out(void);
5007 +int call_function(char *buf);
5008 +
5009 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5010 +int xhci_mtk_test_open(struct inode *inode, struct file *file);
5011 +int xhci_mtk_test_release(struct inode *inode, struct file *file);
5012 +ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
5013 +ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
5014 +
5015 +/*
5016 +  mediatek probe out
5017 +*/
5018 +/************************************************************************************/
5019 +
5020 +#define SW_PRB_OUT_ADDR                (SIFSLV_IPPC+0xc0)
5021 +#define PRB_MODULE_SEL_ADDR    (SIFSLV_IPPC+0xbc)
5022 +
5023 +static inline void mtk_probe_init(const u32 byte){
5024 +       __u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
5025 +       writel(byte, ptr);
5026 +}
5027 +
5028 +static inline void mtk_probe_out(const u32 value){
5029 +       __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5030 +       writel(value, ptr);
5031 +}
5032 +
5033 +static inline u32 mtk_probe_value(void){
5034 +       __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
5035 +
5036 +       return readl(ptr);
5037 +}
5038 +
5039 +
5040 +#endif
5041 --- a/drivers/usb/host/xhci-plat.c
5042 +++ b/drivers/usb/host/xhci-plat.c
5043 @@ -33,6 +33,13 @@ static void xhci_plat_quirks(struct devi
5044          * dev struct in order to setup MSI
5045          */
5046         xhci->quirks |= XHCI_PLAT;
5047 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5048 +       /* MTK host controller gives a spurious successful event after a
5049 +        * short transfer. Ignore it.
5050 +        */
5051 +       xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5052 +       xhci->quirks |= XHCI_LPM_SUPPORT;
5053 +#endif
5054  }
5055
5056  /* called during probe() after chip reset completes */
5057 @@ -79,7 +86,11 @@ static int xhci_plat_probe(struct platfo
5058
5059         driver = &xhci_plat_hc_driver;
5060
5061 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5062 +       irq = XHC_IRQ;
5063 +#else
5064         irq = platform_get_irq(pdev, 0);
5065 +#endif
5066         if (irq < 0)
5067                 return -ENODEV;
5068
5069 --- a/drivers/usb/host/xhci-ring.c
5070 +++ b/drivers/usb/host/xhci-ring.c
5071 @@ -254,16 +254,20 @@ static void inc_enq(struct xhci_hcd *xhc
5072  static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
5073                 unsigned int num_trbs)
5074  {
5075 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5076         int num_trbs_in_deq_seg;
5077 +#endif
5078
5079         if (ring->num_trbs_free < num_trbs)
5080                 return 0;
5081
5082 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5083         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
5084                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
5085                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
5086                         return 0;
5087         }
5088 +#endif
5089
5090         return 1;
5091  }
5092 @@ -2805,6 +2809,7 @@ static int prepare_ring(struct xhci_hcd
5093                 next = ring->enqueue;
5094
5095                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
5096 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5097                         /* If we're not dealing with 0.95 hardware or isoc rings
5098                          * on AMD 0.96 host, clear the chain bit.
5099                          */
5100 @@ -2814,6 +2819,9 @@ static int prepare_ring(struct xhci_hcd
5101                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
5102                         else
5103                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
5104 +#else
5105 +                       next->link.control &= cpu_to_le32(~TRB_CHAIN);
5106 +#endif
5107
5108                         wmb();
5109                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
5110 @@ -2944,6 +2952,9 @@ static void giveback_first_trb(struct xh
5111                 start_trb->field[3] |= cpu_to_le32(start_cycle);
5112         else
5113                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
5114 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5115 +       wmb();
5116 +#endif
5117         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
5118  }
5119
5120 @@ -2999,6 +3010,29 @@ static u32 xhci_td_remainder(unsigned in
5121                 return (remainder >> 10) << 17;
5122  }
5123
5124 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5125 +static u32 mtk_xhci_td_remainder(unsigned int td_transfer_size, unsigned int td_running_total, unsigned int maxp, unsigned trb_buffer_length)
5126 +{
5127 +       u32 max = 31;
5128 +       int remainder, td_packet_count, packet_transferred;
5129 +
5130 +       //0 for the last TRB
5131 +       //FIXME: need to workaround if there is ZLP in this TD
5132 +       if (td_running_total + trb_buffer_length == td_transfer_size)
5133 +               return 0;
5134 +
5135 +       //FIXME: need to take care of high-bandwidth (MAX_ESIT)
5136 +       packet_transferred = (td_running_total /*+ trb_buffer_length*/) / maxp;
5137 +       td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
5138 +       remainder = td_packet_count - packet_transferred;
5139 +
5140 +       if (remainder > max)
5141 +               return max << 17;
5142 +       else
5143 +               return remainder << 17;
5144 +}
5145 +#endif
5146 +
5147  /*
5148   * For xHCI 1.0 host controllers, TD size is the number of max packet sized
5149   * packets remaining in the TD (*not* including this TRB).
5150 @@ -3136,6 +3170,7 @@ static int queue_bulk_sg_tx(struct xhci_
5151                 }
5152
5153                 /* Set the TRB length, TD size, and interrupter fields. */
5154 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5155                 if (xhci->hci_version < 0x100) {
5156                         remainder = xhci_td_remainder(
5157                                         urb->transfer_buffer_length -
5158 @@ -3145,6 +3180,12 @@ static int queue_bulk_sg_tx(struct xhci_
5159                                         trb_buff_len, total_packet_count, urb,
5160                                         num_trbs - 1);
5161                 }
5162 +#else
5163 +               if (num_trbs > 1)
5164 +                       remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length,
5165 +                               running_total, urb->ep->desc.wMaxPacketSize, trb_buff_len);
5166 +#endif
5167 +
5168                 length_field = TRB_LEN(trb_buff_len) |
5169                         remainder |
5170                         TRB_INTR_TARGET(0);
5171 @@ -3207,6 +3248,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5172         int running_total, trb_buff_len, ret;
5173         unsigned int total_packet_count;
5174         u64 addr;
5175 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5176 +       int max_packet;
5177 +#endif
5178
5179         if (urb->num_sgs)
5180                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
5181 @@ -3232,6 +3276,25 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5182                 running_total += TRB_MAX_BUFF_SIZE;
5183         }
5184         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
5185 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5186 +       switch(urb->dev->speed){
5187 +               case USB_SPEED_SUPER:
5188 +                       max_packet = urb->ep->desc.wMaxPacketSize;
5189 +                       break;
5190 +               case USB_SPEED_HIGH:
5191 +               case USB_SPEED_FULL:
5192 +               case USB_SPEED_LOW:
5193 +               case USB_SPEED_WIRELESS:
5194 +               case USB_SPEED_UNKNOWN:
5195 +               default:
5196 +                       max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5197 +                       break;
5198 +       }
5199 +       if((urb->transfer_flags & URB_ZERO_PACKET)
5200 +               && ((urb->transfer_buffer_length % max_packet) == 0)){
5201 +               num_trbs++;
5202 +       }
5203 +#endif
5204
5205         ret = prepare_transfer(xhci, xhci->devs[slot_id],
5206                         ep_index, urb->stream_id,
5207 @@ -3291,6 +3354,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5208                         field |= TRB_ISP;
5209
5210                 /* Set the TRB length, TD size, and interrupter fields. */
5211 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5212                 if (xhci->hci_version < 0x100) {
5213                         remainder = xhci_td_remainder(
5214                                         urb->transfer_buffer_length -
5215 @@ -3300,6 +3364,10 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
5216                                         trb_buff_len, total_packet_count, urb,
5217                                         num_trbs - 1);
5218                 }
5219 +#else
5220 +               remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5221 +#endif
5222 +
5223                 length_field = TRB_LEN(trb_buff_len) |
5224                         remainder |
5225                         TRB_INTR_TARGET(0);
5226 @@ -3389,7 +3457,11 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
5227                 field |= 0x1;
5228
5229         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
5230 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5231 +       if (1) {
5232 +#else
5233         if (xhci->hci_version == 0x100) {
5234 +#endif
5235                 if (urb->transfer_buffer_length > 0) {
5236                         if (setup->bRequestType & USB_DIR_IN)
5237                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
5238 @@ -3413,7 +3485,12 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
5239                 field = TRB_TYPE(TRB_DATA);
5240
5241         length_field = TRB_LEN(urb->transfer_buffer_length) |
5242 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5243                 xhci_td_remainder(urb->transfer_buffer_length) |
5244 +#else
5245 +               //CC: MTK style, no scatter-gather for control transfer
5246 +               0 |
5247 +#endif
5248                 TRB_INTR_TARGET(0);
5249         if (urb->transfer_buffer_length > 0) {
5250                 if (setup->bRequestType & USB_DIR_IN)
5251 @@ -3536,6 +3613,9 @@ static int xhci_queue_isoc_tx(struct xhc
5252         u64 start_addr, addr;
5253         int i, j;
5254         bool more_trbs_coming;
5255 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5256 +       int max_packet;
5257 +#endif
5258
5259         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
5260
5261 @@ -3549,6 +3629,21 @@ static int xhci_queue_isoc_tx(struct xhc
5262         start_trb = &ep_ring->enqueue->generic;
5263         start_cycle = ep_ring->cycle_state;
5264
5265 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5266 +       switch(urb->dev->speed){
5267 +               case USB_SPEED_SUPER:
5268 +                       max_packet = urb->ep->desc.wMaxPacketSize;
5269 +                       break;
5270 +               case USB_SPEED_HIGH:
5271 +               case USB_SPEED_FULL:
5272 +               case USB_SPEED_LOW:
5273 +               case USB_SPEED_WIRELESS:
5274 +               case USB_SPEED_UNKNOWN:
5275 +                       max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
5276 +                       break;
5277 +       }
5278 +#endif
5279 +
5280         urb_priv = urb->hcpriv;
5281         /* Queue the first TRB, even if it's zero-length */
5282         for (i = 0; i < num_tds; i++) {
5283 @@ -3620,9 +3715,13 @@ static int xhci_queue_isoc_tx(struct xhc
5284                         } else {
5285                                 td->last_trb = ep_ring->enqueue;
5286                                 field |= TRB_IOC;
5287 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5288 +                               if (!(xhci->quirks & XHCI_AVOID_BEI)) {
5289 +#else
5290                                 if (xhci->hci_version == 0x100 &&
5291                                                 !(xhci->quirks &
5292                                                         XHCI_AVOID_BEI)) {
5293 +#endif
5294                                         /* Set BEI bit except for the last td */
5295                                         if (i < num_tds - 1)
5296                                                 field |= TRB_BEI;
5297 @@ -3637,6 +3736,7 @@ static int xhci_queue_isoc_tx(struct xhc
5298                                 trb_buff_len = td_remain_len;
5299
5300                         /* Set the TRB length, TD size, & interrupter fields. */
5301 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5302                         if (xhci->hci_version < 0x100) {
5303                                 remainder = xhci_td_remainder(
5304                                                 td_len - running_total);
5305 @@ -3646,6 +3746,10 @@ static int xhci_queue_isoc_tx(struct xhc
5306                                                 total_packet_count, urb,
5307                                                 (trbs_per_td - j - 1));
5308                         }
5309 +#else
5310 +                       remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
5311 +#endif
5312 +
5313                         length_field = TRB_LEN(trb_buff_len) |
5314                                 remainder |
5315                                 TRB_INTR_TARGET(0);
5316 --- a/drivers/usb/host/xhci.c
5317 +++ b/drivers/usb/host/xhci.c
5318 @@ -32,6 +32,16 @@
5319  #include "xhci.h"
5320  #include "xhci-trace.h"
5321
5322 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5323 +#include <asm/uaccess.h>
5324 +#include <linux/dma-mapping.h>
5325 +#include <linux/platform_device.h>
5326 +#include "mtk-phy.h"
5327 +#include "xhci-mtk-scheduler.h"
5328 +#include "xhci-mtk-power.h"
5329 +#include "xhci-mtk.h"
5330 +#endif
5331 +
5332  #define DRIVER_AUTHOR "Sarah Sharp"
5333  #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
5334
5335 @@ -46,6 +56,18 @@ static unsigned int quirks;
5336  module_param(quirks, uint, S_IRUGO);
5337  MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
5338
5339 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5340 +long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
5341 +static struct file_operations xhci_mtk_test_fops = {
5342 +    .owner =           THIS_MODULE,
5343 +    .read =            xhci_mtk_test_read,
5344 +    .write =           xhci_mtk_test_write,
5345 +    .unlocked_ioctl =  xhci_mtk_test_unlock_ioctl,
5346 +    .open =            xhci_mtk_test_open,
5347 +    .release =         xhci_mtk_test_release,
5348 +};
5349 +#endif
5350 +
5351  /* TODO: copied from ehci-hcd.c - can this be refactored? */
5352  /*
5353   * xhci_handshake - spin reading hc until handshake completes or fails
5354 @@ -198,7 +220,7 @@ int xhci_reset(struct xhci_hcd *xhci)
5355         return ret;
5356  }
5357
5358 -#ifdef CONFIG_PCI
5359 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5360  static int xhci_free_msi(struct xhci_hcd *xhci)
5361  {
5362         int i;
5363 @@ -448,6 +470,11 @@ static void compliance_mode_recovery(uns
5364                                         "Attempting compliance mode recovery");
5365                         hcd = xhci->shared_hcd;
5366
5367 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5368 +                       temp |= (1 << 31);
5369 +                       writel(temp, xhci->usb3_ports[i]);
5370 +#endif
5371 +
5372                         if (hcd->state == HC_STATE_SUSPENDED)
5373                                 usb_hcd_resume_root_hub(hcd);
5374
5375 @@ -497,6 +524,9 @@ static bool xhci_compliance_mode_recover
5376  {
5377         const char *dmi_product_name, *dmi_sys_vendor;
5378
5379 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5380 +       return true;
5381 +#endif
5382         dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
5383         dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
5384         if (!dmi_product_name || !dmi_sys_vendor)
5385 @@ -542,6 +572,10 @@ int xhci_init(struct usb_hcd *hcd)
5386                 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
5387                                 "xHCI doesn't need link TRB QUIRK");
5388         }
5389 +
5390 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5391 +       mtk_xhci_scheduler_init();
5392 +#endif
5393         retval = xhci_mem_init(xhci, GFP_KERNEL);
5394         xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
5395
5396 @@ -626,7 +660,11 @@ int xhci_run(struct usb_hcd *hcd)
5397                         "// Set the interrupt modulation register");
5398         temp = readl(&xhci->ir_set->irq_control);
5399         temp &= ~ER_IRQ_INTERVAL_MASK;
5400 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5401 +       temp |= (u32) 16;
5402 +#else
5403         temp |= (u32) 160;
5404 +#endif
5405         writel(temp, &xhci->ir_set->irq_control);
5406
5407         /* Set the HCD state before we enable the irqs */
5408 @@ -651,6 +689,9 @@ int xhci_run(struct usb_hcd *hcd)
5409                 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
5410                                 TRB_TYPE(TRB_NEC_GET_FW));
5411         }
5412 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5413 +       enableXhciAllPortPower(xhci);
5414 +#endif
5415         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
5416                         "Finished xhci_run for USB2 roothub");
5417         return 0;
5418 @@ -1642,6 +1683,14 @@ int xhci_drop_endpoint(struct usb_hcd *h
5419         u32 drop_flag;
5420         u32 new_add_flags, new_drop_flags;
5421         int ret;
5422 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5423 +#if MTK_SCH_NEW
5424 +       struct xhci_slot_ctx *slot_ctx;
5425 +       struct sch_ep *sch_ep = NULL;
5426 +       int isTT;
5427 +       int ep_type;
5428 +#endif
5429 +#endif
5430
5431         ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5432         if (ret <= 0)
5433 @@ -1689,6 +1738,40 @@ int xhci_drop_endpoint(struct usb_hcd *h
5434
5435         xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
5436
5437 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5438 +#if MTK_SCH_NEW
5439 +       slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[udev->slot_id]->out_ctx);
5440 +       if ((slot_ctx->tt_info & 0xff) > 0) {
5441 +               isTT = 1;
5442 +       }
5443 +       else {
5444 +               isTT = 0;
5445 +       }
5446 +       if (usb_endpoint_xfer_int(&ep->desc)) {
5447 +               ep_type = USB_EP_INT;
5448 +       }
5449 +       else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5450 +               ep_type = USB_EP_ISOC;
5451 +       }
5452 +       else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5453 +               ep_type = USB_EP_BULK;
5454 +       }
5455 +       else
5456 +               ep_type = USB_EP_CONTROL;
5457 +
5458 +       sch_ep = mtk_xhci_scheduler_remove_ep(udev->speed, usb_endpoint_dir_in(&ep->desc)
5459 +               , isTT, ep_type, (mtk_u32 *)ep);
5460 +       if (sch_ep != NULL) {
5461 +               kfree(sch_ep);
5462 +       }
5463 +       else {
5464 +               xhci_dbg(xhci, "[MTK]Doesn't find ep_sch instance when removing endpoint\n");
5465 +       }
5466 +#else
5467 +       mtk_xhci_scheduler_remove_ep(xhci, udev, ep);
5468 +#endif
5469 +#endif
5470 +
5471         xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
5472                         (unsigned int) ep->desc.bEndpointAddress,
5473                         udev->slot_id,
5474 @@ -1721,6 +1804,19 @@ int xhci_add_endpoint(struct usb_hcd *hc
5475         u32 new_add_flags, new_drop_flags;
5476         struct xhci_virt_device *virt_dev;
5477         int ret = 0;
5478 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5479 +       struct xhci_ep_ctx *in_ep_ctx;
5480 +#if MTK_SCH_NEW
5481 +       struct xhci_slot_ctx *slot_ctx;
5482 +       struct sch_ep *sch_ep;
5483 +       int isTT;
5484 +       int ep_type;
5485 +       int maxp = 0;
5486 +       int burst = 0;
5487 +       int mult = 0;
5488 +       int interval;
5489 +#endif
5490 +#endif
5491
5492         ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
5493         if (ret <= 0) {
5494 @@ -1787,6 +1883,56 @@ int xhci_add_endpoint(struct usb_hcd *hc
5495                 return -ENOMEM;
5496         }
5497
5498 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5499 +       in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
5500 +#if MTK_SCH_NEW
5501 +       slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
5502 +       if ((slot_ctx->tt_info & 0xff) > 0) {
5503 +               isTT = 1;
5504 +       }
5505 +       else {
5506 +               isTT = 0;
5507 +       }
5508 +       if (usb_endpoint_xfer_int(&ep->desc)) {
5509 +               ep_type = USB_EP_INT;
5510 +       }
5511 +       else if (usb_endpoint_xfer_isoc(&ep->desc)) {
5512 +               ep_type = USB_EP_ISOC;
5513 +       }
5514 +       else if (usb_endpoint_xfer_bulk(&ep->desc)) {
5515 +               ep_type = USB_EP_BULK;
5516 +       }
5517 +       else
5518 +               ep_type = USB_EP_CONTROL;
5519 +
5520 +       if (udev->speed == USB_SPEED_FULL || udev->speed == USB_SPEED_HIGH
5521 +               || udev->speed == USB_SPEED_LOW) {
5522 +               maxp = ep->desc.wMaxPacketSize & 0x7FF;
5523 +               burst = ep->desc.wMaxPacketSize >> 11;
5524 +               mult = 0;
5525 +       }
5526 +       else if (udev->speed == USB_SPEED_SUPER) {
5527 +               maxp = ep->desc.wMaxPacketSize & 0x7FF;
5528 +               burst = ep->ss_ep_comp.bMaxBurst;
5529 +               mult = ep->ss_ep_comp.bmAttributes & 0x3;
5530 +       }
5531 +       interval = (1 << ((in_ep_ctx->ep_info >> 16) & 0xff));
5532 +       sch_ep = kmalloc(sizeof(struct sch_ep), GFP_KERNEL);
5533 +       if (mtk_xhci_scheduler_add_ep(udev->speed, usb_endpoint_dir_in(&ep->desc),
5534 +               isTT, ep_type, maxp, interval, burst, mult, (mtk_u32 *)ep
5535 +               , (mtk_u32 *)in_ep_ctx, sch_ep) != SCH_SUCCESS) {
5536 +               xhci_err(xhci, "[MTK] not enough bandwidth\n");
5537 +
5538 +               return -ENOSPC;
5539 +       }
5540 +#else
5541 +       if (mtk_xhci_scheduler_add_ep(xhci, udev, ep, in_ep_ctx) != SCH_SUCCESS) {
5542 +               xhci_err(xhci, "[MTK] not enough bandwidth\n");
5543 +
5544 +               return -ENOSPC;
5545 +       }
5546 +#endif
5547 +#endif
5548         ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
5549         new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
5550
5551 @@ -4451,8 +4597,14 @@ static u16 xhci_call_host_update_timeout
5552                 u16 *timeout)
5553  {
5554         if (state == USB3_LPM_U1)
5555 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5556 +               if (xhci->quirks & XHCI_INTEL_HOST)
5557 +#endif
5558                 return xhci_calculate_u1_timeout(xhci, udev, desc);
5559         else if (state == USB3_LPM_U2)
5560 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5561 +               if (xhci->quirks & XHCI_INTEL_HOST)
5562 +#endif
5563                 return xhci_calculate_u2_timeout(xhci, udev, desc);
5564
5565         return USB3_LPM_DISABLED;
5566 @@ -4837,7 +4989,9 @@ int xhci_gen_setup(struct usb_hcd *hcd,
5567         hcd->self.no_sg_constraint = 1;
5568
5569         /* XHCI controllers don't stop the ep queue on short packets :| */
5570 +#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5571         hcd->self.no_stop_on_short = 1;
5572 +#endif
5573
5574         if (usb_hcd_is_primary_hcd(hcd)) {
5575                 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
5576 @@ -4900,6 +5054,10 @@ int xhci_gen_setup(struct usb_hcd *hcd,
5577                 goto error;
5578         xhci_dbg(xhci, "Reset complete\n");
5579
5580 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5581 +       setInitialReg();
5582 +#endif
5583 +
5584         /* Set dma_mask and coherent_dma_mask to 64-bits,
5585          * if xHC supports 64-bit addressing */
5586         if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5587 @@ -4994,8 +5152,57 @@ MODULE_DESCRIPTION(DRIVER_DESC);
5588  MODULE_AUTHOR(DRIVER_AUTHOR);
5589  MODULE_LICENSE("GPL");
5590
5591 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5592 +static struct resource xhci_resouce[] = {
5593 +    {
5594 +        .name = "xhci-hcd",
5595 +        .start = XHC_IO_START,
5596 +        .end = XHC_IO_START + XHC_IO_LENGTH -1,
5597 +        .flags = IORESOURCE_MEM,
5598 +    }
5599 +};
5600 +
5601 +static struct platform_device xhci_platform_dev = {
5602 +       .name = "xhci-hcd",
5603 +       .id   = -1,
5604 +       .dev  = {
5605 +               .coherent_dma_mask = 0xffffffff,
5606 +        },
5607 +    .resource = xhci_resouce,
5608 +};
5609 +#endif
5610 +
5611  static int __init xhci_hcd_init(void)
5612  {
5613 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5614 +       struct platform_device *pPlatformDev;
5615 +
5616 +       register_chrdev(XHCI_MTK_TEST_MAJOR, DEVICE_NAME, &xhci_mtk_test_fops);
5617 +
5618 +       u3phy_init();
5619 +       if (u3phy_ops->u2_slew_rate_calibration) {
5620 +                u3phy_ops->u2_slew_rate_calibration(u3phy);
5621 +                u3phy_ops->u2_slew_rate_calibration(u3phy_p1);
5622 +        }
5623 +        else{
5624 +                printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
5625 +        }
5626 +        u3phy_ops->init(u3phy);
5627 +       reinitIP();
5628 +
5629 +       pPlatformDev = &xhci_platform_dev;
5630 +       memset(pPlatformDev, 0, sizeof(struct platform_device));
5631 +       pPlatformDev->name = "xhci-hcd";
5632 +       pPlatformDev->id = -1;
5633 +       pPlatformDev->dev.coherent_dma_mask = 0xffffffff;
5634 +       pPlatformDev->dev.dma_mask = &pPlatformDev->dev.coherent_dma_mask;
5635 +    pPlatformDev->resource = xhci_resouce;
5636 +    pPlatformDev->num_resources = ARRAY_SIZE(xhci_resouce);
5637 +
5638 +       platform_device_register(&xhci_platform_dev);
5639 +
5640 +#endif
5641 +
5642         /*
5643          * Check the compiler generated sizes of structures that must be laid
5644          * out in specific ways for hardware access.
5645 --- a/drivers/usb/host/xhci.h
5646 +++ b/drivers/usb/host/xhci.h
5647 @@ -33,6 +33,21 @@
5648  #include       "xhci-ext-caps.h"
5649  #include "pci-quirks.h"
5650
5651 +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5652 +#define XHC_IRQ (22 + 8)
5653 +#define XHC_IO_START 0x1E1C0000
5654 +#define XHC_IO_LENGTH 0x10000
5655 +/* mtk scheduler bitmasks */
5656 +#define BPKTS(p)       ((p) & 0x3f)
5657 +#define BCSCOUNT(p)    (((p) & 0x7) << 8)
5658 +#define BBM(p)         ((p) << 11)
5659 +#define BOFFSET(p)     ((p) & 0x3fff)
5660 +#define BREPEAT(p)     (((p) & 0x7fff) << 16)
5661 +#endif
5662 +
5663 +
5664 +
5665 +
5666  /* xHCI PCI Configuration Registers */
5667  #define XHCI_SBRN_OFFSET       (0x60)
5668
5669 @@ -1587,8 +1602,12 @@ struct xhci_hcd {
5670         /* Compliance Mode Recovery Data */
5671         struct timer_list       comp_mode_recovery_timer;
5672         u32                     port_status_u0;
5673 +#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
5674 +#define COMP_MODE_RCVRY_MSECS 5000
5675 +#else
5676  /* Compliance Mode Timer Triggered every 2 seconds */
5677  #define COMP_MODE_RCVRY_MSECS 2000
5678 +#endif
5679  };
5680
5681  /* convert between an HCD pointer and the corresponding EHCI_HCD */
5682 @@ -1736,6 +1755,26 @@ void xhci_urb_free_priv(struct xhci_hcd
5683  void xhci_free_command(struct xhci_hcd *xhci,
5684                 struct xhci_command *command);
5685
5686 +#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
5687 +/* xHCI PCI glue */
5688 +int xhci_register_pci(void);
5689 +void xhci_unregister_pci(void);
5690 +#else
5691 +static inline int xhci_register_pci(void) { return 0; }
5692 +static inline void xhci_unregister_pci(void) {}
5693 +#endif
5694 +
5695 +#if defined(CONFIG_USB_XHCI_PLATFORM) \
5696 +       || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
5697 +int xhci_register_plat(void);
5698 +void xhci_unregister_plat(void);
5699 +#else
5700 +static inline int xhci_register_plat(void)
5701 +{ return 0; }
5702 +static inline void xhci_unregister_plat(void)
5703 +{  }
5704 +#endif
5705 +
5706  /* xHCI host controller glue */
5707  typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
5708  int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,