target/linux/imx6/patches-3.18/202-net-igb-add-i210-i211-support-for-phy-read-write.patch

   1 Author: Tim Harvey <tharvey@gateworks.com>
   2 Date:   Thu May 15 00:12:26 2014 -0700
   3
   4     net: igb: add i210/i211 support for phy read/write
   5
   6     The i210/i211 uses the MDICNFG register for the phy address instead of the
   7     MDIC register.
   8
   9     Signed-off-by: Tim Harvey <tharvey@gateworks.com>
  10
  11 --- a/drivers/net/ethernet/intel/igb/e1000_phy.c
  12 +++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
  13 @@ -139,7 +139,7 @@ out:
  14  s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
  15  {
  16         struct e1000_phy_info *phy = &hw->phy;
  17 -       u32 i, mdic = 0;
  18 +       u32 i, mdicnfg, mdic = 0;
  19         s32 ret_val = 0;
  20
  21         if (offset > MAX_PHY_REG_ADDRESS) {
  22 @@ -152,11 +152,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
  23          * Control register.  The MAC will take care of interfacing with the
  24          * PHY to retrieve the desired data.
  25          */
  26 -       mdic = ((offset << E1000_MDIC_REG_SHIFT) |
  27 -               (phy->addr << E1000_MDIC_PHY_SHIFT) |
  28 -               (E1000_MDIC_OP_READ));
  29 +       switch (hw->mac.type) {
  30 +       case e1000_i210:
  31 +       case e1000_i211:
  32 +               mdicnfg = rd32(E1000_MDICNFG);
  33 +               mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
  34 +               mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
  35 +               wr32(E1000_MDICNFG, mdicnfg);
  36 +               mdic = ((offset << E1000_MDIC_REG_SHIFT) |
  37 +                       (E1000_MDIC_OP_READ));
  38 +               break;
  39 +       default:
  40 +               mdic = ((offset << E1000_MDIC_REG_SHIFT) |
  41 +                       (phy->addr << E1000_MDIC_PHY_SHIFT) |
  42 +                       (E1000_MDIC_OP_READ));
  43 +               break;
  44 +       }
  45
  46         wr32(E1000_MDIC, mdic);
  47 +       wrfl();
  48
  49         /* Poll the ready bit to see if the MDI read completed
  50          * Increasing the time out as testing showed failures with
  51 @@ -181,6 +195,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
  52         *data = (u16) mdic;
  53
  54  out:
  55 +       switch (hw->mac.type) {
  56 +               /* restore MDICNFG to have phy's addr */
  57 +               case e1000_i210:
  58 +               case e1000_i211:
  59 +                       mdicnfg = rd32(E1000_MDICNFG);
  60 +                       mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
  61 +                       mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
  62 +                       wr32(E1000_MDICNFG, mdicnfg);
  63 +                       break;
  64 +               default:
  65 +                       break;
  66 +       }
  67         return ret_val;
  68  }
  69
  70 @@ -195,7 +221,7 @@ out:
  71  s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
  72  {
  73         struct e1000_phy_info *phy = &hw->phy;
  74 -       u32 i, mdic = 0;
  75 +       u32 i, mdicnfg, mdic = 0;
  76         s32 ret_val = 0;
  77
  78         if (offset > MAX_PHY_REG_ADDRESS) {
  79 @@ -208,12 +234,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_
  80          * Control register.  The MAC will take care of interfacing with the
  81          * PHY to retrieve the desired data.
  82          */
  83 -       mdic = (((u32)data) |
  84 -               (offset << E1000_MDIC_REG_SHIFT) |
  85 -               (phy->addr << E1000_MDIC_PHY_SHIFT) |
  86 -               (E1000_MDIC_OP_WRITE));
  87 +       switch (hw->mac.type) {
  88 +               case e1000_i210:
  89 +               case e1000_i211:
  90 +                       mdicnfg = rd32(E1000_MDICNFG);
  91 +                       mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
  92 +                       mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
  93 +                       wr32(E1000_MDICNFG, mdicnfg);
  94 +                       mdic = (((u32)data) |
  95 +                               (offset << E1000_MDIC_REG_SHIFT) |
  96 +                               (E1000_MDIC_OP_WRITE));
  97 +                       break;
  98 +               default:
  99 +                       mdic = (((u32)data) |
 100 +                               (offset << E1000_MDIC_REG_SHIFT) |
 101 +                               (phy->addr << E1000_MDIC_PHY_SHIFT) |
 102 +                               (E1000_MDIC_OP_WRITE));
 103 +                       break;
 104 +       }
 105
 106         wr32(E1000_MDIC, mdic);
 107 +       wrfl();
 108
 109         /* Poll the ready bit to see if the MDI read completed
 110          * Increasing the time out as testing showed failures with
 111 @@ -237,6 +278,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_
 112         }
 113
 114  out:
 115 +       switch (hw->mac.type) {
 116 +               /* restore MDICNFG to have phy's addr */
 117 +               case e1000_i210:
 118 +               case e1000_i211:
 119 +                       mdicnfg = rd32(E1000_MDICNFG);
 120 +                       mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
 121 +                       mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
 122 +                       wr32(E1000_MDICNFG, mdicnfg);
 123 +                       break;
 124 +               default:
 125 +                       break;
 126 +       }
 127         return ret_val;
 128  }
 129