package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Arcadyan-ARV4519.patch

   1 From 9f915cf9550a6234adecaf3031c2b279835e14af Mon Sep 17 00:00:00 2001
   2 From: Luka Perkov <luka@openwrt.org>
   3 Date: Sat, 2 Mar 2013 23:34:00 +0100
   4 Subject: MIPS: add board support for Arcadyan ARV4519
   5
   6 Signed-off-by: Luka Perkov <luka@openwrt.org>
   7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
   8
   9 --- /dev/null
  10 +++ b/board/arcadyan/arv4519pw/Makefile
  11 @@ -0,0 +1,27 @@
  12 +#
  13 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
  14 +#
  15 +# SPDX-License-Identifier:     GPL-2.0+
  16 +#
  17 +
  18 +include $(TOPDIR)/config.mk
  19 +
  20 +LIB    = $(obj)lib$(BOARD).o
  21 +
  22 +COBJS  = $(BOARD).o
  23 +
  24 +SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  25 +OBJS   := $(addprefix $(obj),$(COBJS))
  26 +SOBJS  := $(addprefix $(obj),$(SOBJS))
  27 +
  28 +$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
  29 +       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
  30 +
  31 +#########################################################################
  32 +
  33 +# defines $(obj).depend target
  34 +include $(SRCTREE)/rules.mk
  35 +
  36 +sinclude $(obj).depend
  37 +
  38 +#########################################################################
  39 --- /dev/null
  40 +++ b/board/arcadyan/arv4519pw/arv4519pw.c
  41 @@ -0,0 +1,51 @@
  42 +/*
  43 + * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
  44 + *
  45 + * SPDX-License-Identifier:    GPL-2.0+
  46 + */
  47 +
  48 +#include <common.h>
  49 +#include <switch.h>
  50 +#include <asm/gpio.h>
  51 +#include <asm/lantiq/eth.h>
  52 +#include <asm/lantiq/reset.h>
  53 +#include <asm/lantiq/chipid.h>
  54 +
  55 +int board_early_init_f(void)
  56 +{
  57 +       return 0;
  58 +}
  59 +
  60 +int checkboard(void)
  61 +{
  62 +       puts("Board: " CONFIG_BOARD_NAME "\n");
  63 +       ltq_chip_print_info();
  64 +
  65 +       return 0;
  66 +}
  67 +
  68 +static const struct ltq_eth_port_config eth_port_config[] = {
  69 +       /* MAC0: Atheros ar8216 switch */
  70 +       { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE },
  71 +};
  72 +
  73 +static const struct ltq_eth_board_config eth_board_config = {
  74 +       .ports = eth_port_config,
  75 +       .num_ports = ARRAY_SIZE(eth_port_config),
  76 +};
  77 +
  78 +int board_eth_init(bd_t *bis)
  79 +{
  80 +       return ltq_eth_initialize(&eth_board_config);
  81 +}
  82 +
  83 +static struct switch_device ar8216_dev = {
  84 +       .name = "ar8216",
  85 +       .cpu_port = 0,
  86 +       .port_mask = 0xF,
  87 +};
  88 +
  89 +int board_switch_init(void)
  90 +{
  91 +       return switch_device_register(&ar8216_dev);
  92 +}
  93 --- /dev/null
  94 +++ b/board/arcadyan/arv4519pw/config.mk
  95 @@ -0,0 +1,7 @@
  96 +#
  97 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
  98 +#
  99 +# SPDX-License-Identifier:     GPL-2.0+
 100 +#
 101 +
 102 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
 103 --- /dev/null
 104 +++ b/board/arcadyan/arv4519pw/ddr_settings.h
 105 @@ -0,0 +1,55 @@
 106 +/*
 107 + * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
 108 + *
 109 + * This file has been generated with lantiq_ram_extract_magic.awk script.
 110 + *
 111 + * SPDX-License-Identifier:    GPL-2.0+
 112 + */
 113 +
 114 +#define MC_DC00_VALUE  0x1B1B
 115 +#define MC_DC01_VALUE  0x0
 116 +#define MC_DC02_VALUE  0x0
 117 +#define MC_DC03_VALUE  0x0
 118 +#define MC_DC04_VALUE  0x0
 119 +#define MC_DC05_VALUE  0x200
 120 +#define MC_DC06_VALUE  0x605
 121 +#define MC_DC07_VALUE  0x303
 122 +#define MC_DC08_VALUE  0x102
 123 +#define MC_DC09_VALUE  0x70A
 124 +#define MC_DC10_VALUE  0x203
 125 +#define MC_DC11_VALUE  0xC02
 126 +#define MC_DC12_VALUE  0x1C8
 127 +#define MC_DC13_VALUE  0x1
 128 +#define MC_DC14_VALUE  0x0
 129 +#define MC_DC15_VALUE  0x131
 130 +#define MC_DC16_VALUE  0xC800
 131 +#define MC_DC17_VALUE  0xD
 132 +#define MC_DC18_VALUE  0x301
 133 +#define MC_DC19_VALUE  0x200
 134 +#define MC_DC20_VALUE  0xA04
 135 +#define MC_DC21_VALUE  0x1700
 136 +#define MC_DC22_VALUE  0x1717
 137 +#define MC_DC23_VALUE  0x0
 138 +#define MC_DC24_VALUE  0x5A
 139 +#define MC_DC25_VALUE  0x0
 140 +#define MC_DC26_VALUE  0x0
 141 +#define MC_DC27_VALUE  0x0
 142 +#define MC_DC28_VALUE  0x510
 143 +#define MC_DC29_VALUE  0x4E20
 144 +#define MC_DC30_VALUE  0x8235
 145 +#define MC_DC31_VALUE  0x0
 146 +#define MC_DC32_VALUE  0x0
 147 +#define MC_DC33_VALUE  0x0
 148 +#define MC_DC34_VALUE  0x0
 149 +#define MC_DC35_VALUE  0x0
 150 +#define MC_DC36_VALUE  0x0
 151 +#define MC_DC37_VALUE  0x0
 152 +#define MC_DC38_VALUE  0x0
 153 +#define MC_DC39_VALUE  0x0
 154 +#define MC_DC40_VALUE  0x0
 155 +#define MC_DC41_VALUE  0x0
 156 +#define MC_DC42_VALUE  0x0
 157 +#define MC_DC43_VALUE  0x0
 158 +#define MC_DC44_VALUE  0x0
 159 +#define MC_DC45_VALUE  0x500
 160 +#define MC_DC46_VALUE  0x0
 161 --- a/boards.cfg
 162 +++ b/boards.cfg
 163 @@ -502,6 +502,9 @@ Active  mips        mips32         au1x0
 164  Active  mips        mips32         au1x00      -               dbau1x00            dbau1550                             dbau1x00:DBAU1550                                                                                                                 Thomas Lange <thomas@corelatus.se>
 165  Active  mips        mips32         au1x00      -               dbau1x00            dbau1550_el                          dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN                                                                                               Thomas Lange <thomas@corelatus.se>
 166  Active  mips        mips32         au1x00      -               pb1x00              pb1000                               pb1x00:PB1000                                                                                                                     -
 167 +Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_brn                        arv4519pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>
 168 +Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_nor                        arv4519pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>
 169 +Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_ram                        arv4519pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>
 170  Active  mips        mips32         danube      lantiq          easy50712           easy50712_nor                        easy50712:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 171  Active  mips        mips32         danube      lantiq          easy50712           easy50712_norspl                     easy50712:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 172  Active  mips        mips32         danube      lantiq          easy50712           easy50712_ram                        easy50712:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 173 --- /dev/null
 174 +++ b/include/configs/arv4519pw.h
 175 @@ -0,0 +1,67 @@
 176 +/*
 177 + * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
 178 + *
 179 + * SPDX-License-Identifier:    GPL-2.0+
 180 + */
 181 +
 182 +#ifndef __CONFIG_H
 183 +#define __CONFIG_H
 184 +
 185 +#define CONFIG_MACH_TYPE       "ARV4519PW"
 186 +#define CONFIG_IDENT_STRING    " "CONFIG_MACH_TYPE
 187 +#define CONFIG_BOARD_NAME      "Arcadyan ARV4519PW"
 188 +
 189 +/* Configure SoC */
 190 +#define CONFIG_LTQ_SUPPORT_UART                /* Enable ASC and UART */
 191 +
 192 +#define CONFIG_LTQ_SUPPORT_ETHERNET    /* Enable ethernet */
 193 +
 194 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH   /* Have a parallel NOR flash */
 195 +
 196 +/* Switch devices */
 197 +#define CONFIG_SWITCH_MULTI
 198 +#define CONFIG_SWITCH_AR8216
 199 +
 200 +/* Environment */
 201 +#if defined(CONFIG_SYS_BOOT_NOR)
 202 +#define CONFIG_ENV_IS_IN_FLASH
 203 +#define CONFIG_ENV_OVERWRITE
 204 +#define CONFIG_ENV_OFFSET              (192 * 1024)
 205 +#define CONFIG_ENV_SECT_SIZE           (64 * 1024)
 206 +#else
 207 +#define CONFIG_ENV_IS_NOWHERE
 208 +#endif
 209 +
 210 +#define CONFIG_ENV_SIZE                        (8 * 1024)
 211 +#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
 212 +
 213 +/* Brnboot loadable image */
 214 +#if defined(CONFIG_SYS_BOOT_BRN)
 215 +#define CONFIG_SYS_TEXT_BASE           0x80002000
 216 +#define CONFIG_SKIP_LOWLEVEL_INIT
 217 +#define CONFIG_SYS_DISABLE_CACHE
 218 +#define CONFIG_ENV_OVERWRITE 1
 219 +#endif
 220 +
 221 +/* Console */
 222 +#define CONFIG_LTQ_ADVANCED_CONSOLE
 223 +#define CONFIG_BAUDRATE                        115200
 224 +#define CONFIG_CONSOLE_ASC             1
 225 +#define CONFIG_CONSOLE_DEV             "ttyLTQ1"
 226 +
 227 +/* Pull in default board configs for Lantiq XWAY Danube */
 228 +#include <asm/lantiq/config.h>
 229 +#include <asm/arch/config.h>
 230 +
 231 +/* Pull in default OpenWrt configs for Lantiq SoC */
 232 +#include "openwrt-lantiq-common.h"
 233 +
 234 +#define CONFIG_ENV_UPDATE_UBOOT_NOR            \
 235 +       "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
 236 +
 237 +#define CONFIG_EXTRA_ENV_SETTINGS      \
 238 +       CONFIG_ENV_LANTIQ_DEFAULTS      \
 239 +       CONFIG_ENV_UPDATE_UBOOT_NOR     \
 240 +       "kernel_addr=0xB0040000\0"
 241 +
 242 +#endif /* __CONFIG_H */