package/boot/uboot-lantiq/patches/0017-tools-add-some-helper-tools-for-Lantiq-SoCs.patch

   1 From 1da5479d59b39d7931a2b0efabdfa314f6788b6d Mon Sep 17 00:00:00 2001
   2 From: Luka Perkov <luka@openwrt.org>
   3 Date: Sat, 2 Mar 2013 23:34:00 +0100
   4 Subject: tools: add some helper tools for Lantiq SoCs
   5
   6 Signed-off-by: Luka Perkov Luka Perkov <luka@openwrt.org>
   7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
   8
   9 --- /dev/null
  10 +++ b/tools/gct.pl
  11 @@ -0,0 +1,155 @@
  12 +#!/usr/bin/perl
  13 +
  14 +#use strict;
  15 +#use Cwd;
  16 +#use Env;
  17 +
  18 +my $aline;
  19 +my $lineid;
  20 +my $length;
  21 +my $address;
  22 +my @bytes;
  23 +my $addstr;
  24 +my $chsum=0;
  25 +my $count=0;
  26 +my $firstime=1;
  27 +my $i;
  28 +my $currentaddr;
  29 +my $tmp;
  30 +my $holder="";
  31 +my $loadaddr;
  32 +
  33 +if(@ARGV < 2){
  34 +       die("\n Syntax: perl gct.pl uart_ddr_settings.conf u-boot.srec u-boot.asc\n");
  35 +}
  36 +
  37 +open(IN_UART_DDR_SETTINGS, "<$ARGV[0]") || die("failed to open uart_ddr_settings.conf\n");
  38 +open(IN_UART_SREC, "<$ARGV[1]") || die("failed to open u-boot.srec\n");
  39 +open(OUT_UBOOT_ASC, ">$ARGV[2]") || die("failed to open u-boot.asc\n");
  40 +
  41 +$i=0;
  42 +while ($line = <IN_UART_DDR_SETTINGS>){
  43 +       if($line=~/\w/){
  44 +               if($line!~/[;#\*]/){
  45 +                       if($i eq 0){
  46 +                               printf OUT_UBOOT_ASC ("33333333");
  47 +                       }
  48 +                       chomp($line);
  49 +                       $line=~s/\t//;
  50 +                       @array=split(/ +/,$line);
  51 +                       $j=0;
  52 +                       while(@array[$j]!~/\w/){
  53 +                               $j=$j+1;
  54 +                       }
  55 +                       $addr=@array[$j];
  56 +                       $regval=@array[$j+1];
  57 +                       $addr=~s/0x//;
  58 +                       $regval=~s/0x//;
  59 +                       printf OUT_UBOOT_ASC ("%08x%08x",hex($addr),hex($regval));
  60 +                       $i=$i+1;
  61 +                       if($i eq 8){
  62 +                               $i=0;
  63 +                               printf OUT_UBOOT_ASC ("\n");
  64 +                       }
  65 +               }
  66 +       }
  67 +}
  68 +
  69 +while($i lt 8 && $i gt 0){
  70 +       printf OUT_UBOOT_ASC "00"x8;
  71 +       $i=$i+1;
  72 +}
  73 +
  74 +if($i eq 8){
  75 +       printf OUT_UBOOT_ASC ("\n");
  76 +}
  77 +
  78 +while($aline=<IN_UART_SREC>){
  79 +       $aline=uc($aline);
  80 +       chomp($aline);
  81 +       next if(($aline=~/^S0/) || ($aline=~/^S7/));
  82 +       ($lineid, $length, $address, @bytes) = unpack"A2A2A8"."A2"x300, $aline;
  83 +       $length = hex($length);
  84 +       $address = hex($address);
  85 +       $length -=5;
  86 +       $i=0;
  87 +
  88 +       while($length>0){
  89 +               if($firstime==1){
  90 +                       $addstr = sprintf("%x", $address);
  91 +                       $addstr = "0"x(8-length($addstr)).$addstr;
  92 +                       print OUT_UBOOT_ASC $addstr;
  93 +                       addchsum($addstr);
  94 +                       $firstime=0;
  95 +                       $currentaddr=$address;
  96 +                       $loadaddr = $addstr;
  97 +               }
  98 +               else{
  99 +                       if($count==64){
 100 +                               $addstr = sprintf("%x", $currentaddr);
 101 +                               $addstr = "0"x(8-length($addstr)).$addstr;
 102 +                               print OUT_UBOOT_ASC $addstr;
 103 +                               addchsum($addstr);
 104 +                               $count=0;
 105 +                       }
 106 +#printf("*** %x != %x\n", $address, $currentaddr) if $address != $currentaddr;
 107 +               }
 108 +               if($currentaddr < $address) {
 109 +                       print OUT_UBOOT_ASC "00";
 110 +                       addchsum("00");
 111 +                       $count++;
 112 +                       $currentaddr++;
 113 +               }
 114 +               else {
 115 +                       while($count<64){
 116 +                               $bytes[$i]=~tr/ABCDEF/abcdef/;
 117 +                               print OUT_UBOOT_ASC "$bytes[$i]";
 118 +                               addchsum($bytes[$i]);
 119 +                               $i++;
 120 +                               $count++;
 121 +                               $currentaddr++;
 122 +                               $length--;
 123 +                               last if($length==0);
 124 +                       }
 125 +               }
 126 +               if($count==64){
 127 +                       print OUT_UBOOT_ASC "\n";
 128 +               }
 129 +       }
 130 +}
 131 +if($count != 64){
 132 +       $tmp = "00";
 133 +       for($i=0;$i<(64-$count);$i++){
 134 +               print OUT_UBOOT_ASC "00";
 135 +               addchsum($tmp);
 136 +       }
 137 +       print OUT_UBOOT_ASC "\n";
 138 +}
 139 +
 140 +
 141 +print OUT_UBOOT_ASC "11"x4;
 142 +use integer;
 143 +$chsum=$chsum & 0xffffffff;
 144 +$chsum = sprintf("%X", $chsum);
 145 +$chsum = "0"x(8-length($chsum)).$chsum;
 146 +$chsum =~tr/ABCDEF/abcdef/;
 147 +print OUT_UBOOT_ASC $chsum;
 148 +print OUT_UBOOT_ASC "00"x60;
 149 +print OUT_UBOOT_ASC "\n";
 150 +
 151 +print OUT_UBOOT_ASC "99"x4;
 152 +print OUT_UBOOT_ASC $loadaddr;
 153 +print OUT_UBOOT_ASC "00"x60;
 154 +print OUT_UBOOT_ASC "\n";
 155 +
 156 +close OUT_UBOOT_ASC;
 157 +
 158 +sub addchsum{
 159 +       my $cc=$_[0];
 160 +       $holder=$holder.$cc;
 161 +       if(length($holder)==8){
 162 +               $holder = hex($holder);
 163 +               $chsum+=$holder;
 164 +               $holder="";
 165 +       }
 166 +}
 167 --- /dev/null
 168 +++ b/tools/lantiq_bdi_conf.awk
 169 @@ -0,0 +1,116 @@
 170 +#!/usr/bin/awk -f
 171 +#
 172 +# Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
 173 +# Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 174 +#
 175 +# Usage:
 176 +#  awk -f lantiq_bdi_conf.awk -v soc=ar9 board=<name> PATH_TO_BOARD/ddr_settings.h
 177 +#
 178 +# Additional information:
 179 +#  http://www.abatron.ch/fileadmin/user_upload/products/pdf/ManGDBR4K-3000.pdf
 180 +#
 181 +# SPDX-License-Identifier:     GPL-2.0+
 182 +#
 183 +
 184 +function print_header()
 185 +{
 186 +       print ";                                                                         "
 187 +       print "; Copyright (C) 2013 Luka Perkov <luka@openwrt.org>                       "
 188 +       print "; Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>    "
 189 +       print ";                                                                         "
 190 +       print "; This file has been generated with lantiq_bdi_conf.awk script.           "
 191 +       print ";                                                                         "
 192 +       print "; SPDX-License-Identifier:       GPL-2.0+                                 "
 193 +       print ";                                                                         "
 194 +       print ""
 195 +}
 196 +
 197 +function init_ar9_prologue()
 198 +{
 199 +       print "WM32 0xBF103010 0x80             ; CGU for CPU 333Mhz, DDR 167Mhz"
 200 +       print "WM32 0xBF103014 0x01             ; CGU update"
 201 +       print "WM32 0xBF800010 0x0              ; Clear error access log register"
 202 +       print "WM32 0xBF800020 0x0              ; Clear error access log register"
 203 +       print "WM32 0xBF800060 0xD              ; Enable FPI, DDR and SRAM module in memory controller"
 204 +       print "WM32 0xBF801030 0x0              ; Clear start bit of DDR memory controller"
 205 +}
 206 +
 207 +function init_ar9_epilogue()
 208 +{
 209 +       print "WM32 0xBE105360 0x4001D7FF       ; EBU setup"
 210 +}
 211 +
 212 +function init_ddr1_epilogue()
 213 +{
 214 +       print "WM32 0xBF801030 0x100            ; Set start bit of DDR memory controller"
 215 +}
 216 +
 217 +function ar9_target()
 218 +{
 219 +       print "CPUTYPE          M34K"
 220 +       print "ENDIAN           BIG"
 221 +       print "JTAGCLOCK        1"
 222 +       print "BDIMODE          AGENT           ; [ LOADONLY, AGENT ]"
 223 +       print "RESET            JTAG            ; [ NONE, JTAG, HARD ]"
 224 +       print "POWERUP          100"
 225 +       print "WAKEUP           100"
 226 +       print "BREAKMODE        HARD            ; [ SOFT, HARD ]"
 227 +       print  "STEPMODE        SWBP            ; [ JTAG, HWBP, SWBP ]"
 228 +       print "VECTOR           CATCH"
 229 +       print  "SCANSUCC        1 5"
 230 +}
 231 +
 232 +function flash_p2601hnfx()
 233 +{
 234 +       print "CHIPTYPE MIRRORX16"
 235 +       print "CHIPSIZE 0x1000000"
 236 +       print "BUSWIDTH 16"
 237 +}
 238 +
 239 +BEGIN {
 240 +       switch (soc) {
 241 +       case "ar9":
 242 +               reg_base = 0xbf801000
 243 +               print_header()
 244 +               print "[INIT]"
 245 +               init_ar9_prologue()
 246 +               break
 247 +       default:
 248 +               print "Invalid or no value for SoC specified!"
 249 +               exit 1
 250 +       }
 251 +}
 252 +
 253 +/^#define/ {
 254 +       /* DC03 contains MC enable bit and must not be set here */
 255 +       if (tolower($2) != "mc_dc03_value")
 256 +               printf("WM32 0x%x %s\n", reg_base, tolower($3))
 257 +
 258 +       reg_base += 0x10
 259 +}
 260 +
 261 +END {
 262 +       switch (soc) {
 263 +       case "ar9":
 264 +               init_ddr1_epilogue()
 265 +               init_ar9_epilogue()
 266 +               print ""
 267 +               print "[TARGET]"
 268 +               ar9_target()
 269 +               print ""
 270 +               print "[HOST]"
 271 +               print "PROMPT           \"ar9> \""
 272 +               print ""
 273 +               break
 274 +       default:
 275 +       }
 276 +
 277 +       switch (board) {
 278 +       case "p2601hnfx":
 279 +               print "[FLASH]"
 280 +               flash_p2601hnfx()
 281 +               print ""
 282 +               break
 283 +       default:
 284 +       }
 285 +}
 286 --- /dev/null
 287 +++ b/tools/lantiq_ram_extract_magic.awk
 288 @@ -0,0 +1,69 @@
 289 +#
 290 +# Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
 291 +#
 292 +# Usage:
 293 +# mips-openwrt-linux-objdump -EB -b binary -m mips:isa32r2 -D YOUR_IMAGE_DUMP | awk -f lantiq_ram_extract_magic.awk
 294 +#
 295 +# SPDX-License-Identifier:     GPL-2.0+
 296 +#
 297 +
 298 +BEGIN {
 299 +       print "/*                                                                            "
 300 +       print " * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>                     "
 301 +       print " *                                                                            "
 302 +       print " * This file has been generated with lantiq_ram_extract_magic.awk script.     "
 303 +       print " *                                                                            "
 304 +       print " * SPDX-License-Identifier:      GPL-2.0+                                     "
 305 +       print " */                                                                           "
 306 +       print ""
 307 +
 308 +       mc_dc_value=0
 309 +       mc_dc_number=0
 310 +       right_section=0
 311 +       mc_dc_value_print=0
 312 +       mc_dc_number_print=0
 313 +}
 314 +
 315 +/t2,[0-9]+$/ {
 316 +       if (right_section) {
 317 +               split($4, tmp, ",")
 318 +               mc_dc_value=sprintf("%X", tmp[2])
 319 +               mc_dc_value_print=1
 320 +       }
 321 +}
 322 +
 323 +/t2,0x[0-9a-f]+$/ {
 324 +       if (right_section) {
 325 +               split($4, tmp, ",0x")
 326 +               mc_dc_value=sprintf("%s", tmp[2])
 327 +               mc_dc_value=toupper(mc_dc_value)
 328 +               mc_dc_value_print=1
 329 +       }
 330 +}
 331 +
 332 +/t2,[0-9]+\(t1\)$/ {
 333 +       if (right_section) {
 334 +               split($4, tmp, ",")
 335 +               split(tmp[2], tmp, "(")
 336 +               mc_dc_number=tmp[1]/16
 337 +               mc_dc_number_print=1
 338 +       }
 339 +}
 340 +
 341 +{
 342 +       if (right_section && mc_dc_number_print && mc_dc_value_print) {
 343 +               if (mc_dc_number < 10)
 344 +                       print "#define MC_DC0" mc_dc_number "_VALUE\t0x" mc_dc_value
 345 +               else
 346 +                       print "#define MC_DC" mc_dc_number "_VALUE\t0x" mc_dc_value
 347 +               mc_dc_value_print=0
 348 +               mc_dc_number_print=0
 349 +       }
 350 +
 351 +       if ($4 == "t1,t1,0x1000")
 352 +               right_section=1
 353 +
 354 +
 355 +       if ($4 == "t2,736(t1)")
 356 +               right_section=0
 357 +}
 358 --- /dev/null
 359 +++ b/tools/lantiq_ram_init_uart.awk
 360 @@ -0,0 +1,117 @@
 361 +#!/usr/bin/awk -f
 362 +#
 363 +# Copyright (C) 2011-2012 Luka Perkov <luka@openwrt.org>
 364 +# Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 365 +#
 366 +# Usage:
 367 +# awk -f lantiq_ram_init_uart.awk -v soc=<danube|ar9|vr9> PATH_TO_BOARD/ddr_settings.h
 368 +#
 369 +# SPDX-License-Identifier:     GPL-2.0+
 370 +#
 371 +
 372 +function print_header()
 373 +{
 374 +       print ";                                                                            "
 375 +       print "; Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>                     "
 376 +       print "; Copyright (C) 2012-2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>  "
 377 +       print ";                                                                            "
 378 +       print "; This file has been generated with lantiq_ram_init_uart.awk script.         "
 379 +       print ";                                                                            "
 380 +       print "; SPDX-License-Identifier:       GPL-2.0+                                    "
 381 +       print ""
 382 +}
 383 +
 384 +function mc_danube_prologue()
 385 +{
 386 +       /* Clear access error log registers */
 387 +       print "0xbf800010", "0x0"
 388 +       print "0xbf800020", "0x0"
 389 +
 390 +       /* Enable DDR and SRAM module in memory controller */
 391 +       print "0xbf800060", "0x5"
 392 +
 393 +       /* Clear start bit of DDR memory controller */
 394 +       print "0xbf801030", "0x0"
 395 +}
 396 +
 397 +function mc_ar9_prologue()
 398 +{
 399 +       /* Clear access error log registers */
 400 +       print "0xbf800010", "0x0"
 401 +       print "0xbf800020", "0x0"
 402 +
 403 +       /* Enable FPI, DDR and SRAM module in memory controller */
 404 +       print "0xbf800060", "0xD"
 405 +
 406 +       /* Clear start bit of DDR memory controller */
 407 +       print "0xbf801030", "0x0"
 408 +}
 409 +
 410 +function mc_ddr1_epilogue()
 411 +{
 412 +       /* Set start bit of DDR memory controller */
 413 +       print "0xbf801030", "0x100"
 414 +}
 415 +
 416 +function mc_ddr2_prologue()
 417 +{
 418 +       /* Put memory controller in inactive mode */
 419 +       print "0xbf401070", "0x0"
 420 +}
 421 +
 422 +function mc_ddr2_epilogue(mc_ccr07_value)
 423 +{
 424 +       /* Put memory controller in active mode */
 425 +       mc_ccr07_value = or(mc_ccr07_value, 0x100)
 426 +       printf("0xbf401070 0x%x\n", mc_ccr07_value)
 427 +}
 428 +
 429 +BEGIN {
 430 +       switch (soc) {
 431 +       case "danube":
 432 +               reg_base = 0xbf801000
 433 +               print_header()
 434 +               mc_danube_prologue()
 435 +               break
 436 +       case "ar9":
 437 +               reg_base = 0xbf801000
 438 +               print_header()
 439 +               mc_ar9_prologue()
 440 +               break
 441 +       case "vr9":
 442 +               reg_base = 0xbf401000
 443 +               print_header()
 444 +               mc_ddr2_prologue()
 445 +               break
 446 +       default:
 447 +               print "Invalid or no value for soc specified!"
 448 +               exit 1
 449 +       }
 450 +
 451 +       mc_ccr07_value = 0
 452 +}
 453 +
 454 +/^#define/ {
 455 +       /* CCR07 contains MC enable bit and must not be set here */
 456 +       if (tolower($2) == "mc_ccr07_value")
 457 +               mc_ccr07_value = strtonum($3)
 458 +       if (tolower($2) == "mc_dc03_value")
 459 +               /* CCR07 contains MC enable bit and must not be set here */
 460 +       else
 461 +               printf("0x%x %s\n", reg_base, tolower($3))
 462 +
 463 +       reg_base += 0x10
 464 +}
 465 +
 466 +END {
 467 +       switch (soc) {
 468 +       case "danube":
 469 +       case "ar9":
 470 +               mc_ddr1_epilogue()
 471 +               break
 472 +       case "vr9":
 473 +               mc_ddr2_epilogue(mc_ccr07_value)
 474 +               break
 475 +       default:
 476 +       }
 477 +}