X-Git-Url: https://git.archive.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Framips%2Ffiles%2Fdrivers%2Fnet%2Fethernet%2Fralink%2Fsoc_mt7620.c;h=6e2fbdf645d9ed44ffda8885f81806cf4b83e3d4;hb=36403dee5c70a3ba1f0036ef53a283d9873537a8;hp=5a7ee35eb0379ae7f227eca2aa613e835e192f51;hpb=c2eb2982eb1a7811012538670077d87630d03585;p=openwrt.git

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
index 5a7ee35eb0..6e2fbdf645 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
@@ -27,7 +27,8 @@
 
 #define MT7620A_CDMA_CSG_CFG	0x400
 #define MT7620_DMA_VID		(MT7620A_CDMA_CSG_CFG | 0x30)
-#define MT7621_DMA_VID		0xa8
+#define MT7621_CDMP_IG_CTRL	(MT7620A_CDMA_CSG_CFG + 0x00)
+#define MT7621_CDMP_EG_CTRL	(MT7620A_CDMA_CSG_CFG + 0x04)
 #define MT7620A_RESET_FE	BIT(21)
 #define MT7621_RESET_FE		BIT(6)
 #define MT7620A_RESET_ESW	BIT(23)
@@ -95,7 +96,7 @@ static const u32 mt7621_reg_table[FE_REG_COUNT] = {
 	[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
 	[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
 	[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
-	[FE_REG_FE_DMA_VID_BASE] = MT7621_DMA_VID,
+	[FE_REG_FE_DMA_VID_BASE] = 0,
 	[FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
 	[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
 };
@@ -134,6 +135,14 @@ static void mt7620_txcsum_config(bool enable)
 				MT7620A_CDMA_CSG_CFG);
 }
 
+static void mt7621_rxvlan_config(bool enable)
+{
+	if (enable)
+		fe_w32(1, MT7621_CDMP_EG_CTRL);
+	else
+		fe_w32(0, MT7621_CDMP_EG_CTRL);
+}
+
 static int mt7620_fwd_config(struct fe_priv *priv)
 {
 	struct net_device *dev = priv_netdev(priv);
@@ -152,15 +161,16 @@ static int mt7621_fwd_config(struct fe_priv *priv)
 
 	fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG);
 
-	mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
+	/* mt7621 don't have txcsum config */
 	mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
+	mt7621_rxvlan_config((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
+			(priv->flags & FE_FLAG_RX_VLAN_CTAG));
 
 	return 0;
 }
 
 static void mt7620_tx_dma(struct fe_tx_dma *txd)
 {
-	txd->txd4 = 0;
 }
 
 static void mt7621_tx_dma(struct fe_tx_dma *txd)
@@ -175,10 +185,10 @@ static void mt7620_init_data(struct fe_soc_data *data,
 
 	priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
 		FE_FLAG_RX_SG_DMA;
+
 	netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 		NETIF_F_HW_VLAN_CTAG_TX;
-
-	if (mt7620_get_eco() >= 5 || IS_ENABLED(CONFIG_SOC_MT7621))
+	if (mt7620_get_eco() >= 5)
 		netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
 			NETIF_F_IPV6_CSUM;
 }
@@ -189,8 +199,11 @@ static void mt7621_init_data(struct fe_soc_data *data,
 	struct fe_priv *priv = netdev_priv(netdev);
 
 	priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
-		FE_FLAG_RX_SG_DMA;
-	netdev->hw_features = NETIF_F_HW_VLAN_CTAG_TX;
+		FE_FLAG_RX_SG_DMA | FE_FLAG_NAPI_WEIGHT;
+
+	netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
+		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_SG | NETIF_F_TSO |
+		NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
 }
 
 static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
@@ -219,7 +232,6 @@ static struct fe_soc_data mt7620_data = {
 	.rx_int = RT5350_RX_DONE_INT,
 	.tx_int = RT5350_TX_DONE_INT,
 	.checksum_bit = MT7620_L4_VALID,
-	.tx_udf_bit = MT7620_TX_DMA_UDF,
 	.has_carrier = mt7620a_has_carrier,
 	.mdio_read = mt7620_mdio_read,
 	.mdio_write = mt7620_mdio_write,
@@ -240,7 +252,6 @@ static struct fe_soc_data mt7621_data = {
 	.rx_int = RT5350_RX_DONE_INT,
 	.tx_int = RT5350_TX_DONE_INT,
 	.checksum_bit = MT7621_L4_VALID,
-	.tx_udf_bit = MT7621_TX_DMA_UDF,
 	.has_carrier = mt7620a_has_carrier,
 	.mdio_read = mt7620_mdio_read,
 	.mdio_write = mt7620_mdio_write,