X-Git-Url: https://git.archive.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Framips%2Fdts%2Frt2880.dtsi;h=47ea4c343ec72baa213016aab127eedef525f3cc;hb=504c28c7589648982595bcb93d2ec001350de448;hp=b51314856d4790a63e921379a0adda5ecb55db10;hpb=deaa1c19469b1b9917ddb58ba6c8417edfd21e94;p=openwrt.git

diff --git a/target/linux/ramips/dts/rt2880.dtsi b/target/linux/ramips/dts/rt2880.dtsi
index b51314856d..47ea4c343e 100644
--- a/target/linux/ramips/dts/rt2880.dtsi
+++ b/target/linux/ramips/dts/rt2880.dtsi
@@ -23,7 +23,7 @@
 	palmbus@300000 {
 		compatible = "palmbus";
 		reg = <0x300000 0x200000>;
-                ranges = <0x0 0x300000 0x1FFFFF>;
+		ranges = <0x0 0x300000 0x1FFFFF>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -121,15 +121,59 @@
 		};
 	};
 
+	pinctrl {
+		compatible = "ralink,rt2880-pinmux";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinctrl0 {
+			sdram {
+				ralink,group = "sdram";
+				ralink,function = "sdram";
+			};
+		};
+
+		spi_pins: spi {
+			spi {
+				ralink,group = "spi";
+				ralink,function = "spi";
+			};
+		};
+
+		uartlite_pins: uartlite {
+			uart {
+				ralink,group = "uartlite";
+				ralink,function = "uartlite";
+			};
+		};
+	};
+
+	rstctrl: rstctrl {
+		compatible = "ralink,rt2880-reset";
+		#reset-cells = <1>;
+	};
+
 	ethernet@400000 {
 		compatible = "ralink,rt2880-eth";
 		reg = <0x00400000 10000>;
 
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		resets = <&rstctrl 18>;
+		reset-names = "fe";
+
 		interrupt-parent = <&cpuintc>;
 		interrupts = <5>;
 
 		status = "disabled";
 
+		port@0 {
+			compatible = "ralink,rt2880-port", "mediatek,eth-port";
+			reg = <0>;
+		};
+
 		mdio-bus {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -146,8 +190,5 @@
 		interrupts = <6>;
 
 		ralink,eeprom = "soc_wmac.eeprom";
-
-		status = "disabled";
 	};
-
 };