X-Git-Url: https://git.archive.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Framips%2Fdts%2Fmt7621.dtsi;h=71d833d69efec1eb2f68ec63fe991a9ad44495cb;hb=41e6ca40e4f4f9e8962653358bc49b4385ce52a2;hp=06828c6bbd2a8d5d7a71dde15f57416e8d554e08;hpb=270a2afcc544ca14e79198346e7e186033472ae7;p=openwrt.git

diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index 06828c6bbd..71d833d69e 100644
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -22,6 +22,26 @@
 		compatible = "mti,cpu-interrupt-controller";
 	};
 
+	aliases {
+		serial0 = &uartlite;
+	};
+
+	cpuclock: cpuclock@0 {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+
+		/* FIXME: there should be way to detect this */
+		clock-frequency = <880000000>;
+	};
+
+	sysclock: sysclock@0 {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+
+		/* FIXME: there should be way to detect this */
+		clock-frequency = <50000000>;
+	};
+
 	palmbus@1E000000 {
 		compatible = "palmbus";
 		reg = <0x1E000000 0x100000>;
@@ -84,12 +104,11 @@
 			    reg = <0x1fbf8000 0x8000>;
  		};
 
-		uartlite@c00 {
+		uartlite: uartlite@c00 {
 			compatible = "ns16550a";
 			reg = <0xc00 0x100>;
 
-			/* FIXME: there should be way to detect this */
-			clock-frequency = <50000000>;
+			clocks = <&sysclock>;
 
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -105,8 +124,7 @@
 			compatible = "ralink,mt7621-spi";
 			reg = <0xb00 0x100>;
 
-			/* FIXME: there should be way to detect this */
-			clock-frequency = <50000000>;
+			clocks = <&sysclock>;
 
 			resets = <&rstctrl 18>;
 			reset-names = "spi";
@@ -225,7 +243,7 @@
 
 	sdhci@1E130000 {
 		compatible = "ralink,mt7620-sdhci";
-		reg = <0x1E130000 4000>;
+		reg = <0x1E130000 0x4000>;
 
 		interrupt-parent = <&gic>;
 		interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -234,8 +252,12 @@
 	xhci@1E1C0000 {
 		status = "okay";
 
-		compatible = "xhci-platform";
-		reg = <0x1E1C0000 4000>;
+		compatible = "mediatek,mt8173-xhci";
+		reg = <0x1e1c0000 0x1000
+		       0x1e1d0700 0x0100>;
+
+		clocks = <&sysclock>;
+		clock-names = "sys_ck";
 
 		interrupt-parent = <&gic>;
 		interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -253,44 +275,24 @@
 		timer {
 			compatible = "mti,gic-timer";
 			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-
-			/* FIXME: there should be way to detect this */
-			clock-frequency = <880000000>;
+			clocks = <&cpuclock>;
 		};
 	};
 
 	nand@1e003000 {
+		status = "disabled";
+
 		compatible = "mtk,mt7621-nand";
 		bank-width = <2>;
 		reg = <0x1e003000 0x800
 			0x1e003800 0x800>;
 		#address-cells = <1>;
 		#size-cells = <1>;
-
-		partition@0 {
-			label = "uboot";
-			reg = <0x00000 0x80000>; /* 64 KB */
-		};
-
-		partition@80000 {
-			label = "uboot_env";
-			reg = <0x80000 0x80000>; /* 64 KB */
-		};
-
-		partition@100000 {
-			label = "factory";
-			reg = <0x100000 0x40000>;
-		};
-
-		partition@140000 {
-			label = "rootfs";
-			reg = <0x140000 0xec0000>;
-		};
 	};
 
 	ethernet@1e100000 {
-		compatible = "ralink,mt7621-eth";
-		reg = <0x1e100000 10000>;
+		compatible = "mediatek,mt7621-eth";
+		reg = <0x1e100000 0x10000>;
 
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -301,6 +303,8 @@
 		interrupt-parent = <&gic>;
 		interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 
+		mediatek,switch = <&gsw>;
+
 		mdio-bus {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -312,9 +316,9 @@
 		};
 	};
 
-	gsw@1e110000 {
-		compatible = "ralink,mt7620a-gsw";
-		reg = <0x1e110000 8000>;
+	gsw: gsw@1e110000 {
+		compatible = "mediatek,mt7621-gsw";
+		reg = <0x1e110000 0x8000>;
 		interrupt-parent = <&gic>;
 		interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 	};