+++ /dev/null
-#
-# Copyright (C) 2007-2011 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-
-BOARD:=adm5120
-BOARDNAME:=Infineon/ADMtek ADM5120
-LINUX_VERSION:=3.8.13
-SUBTARGETS:=router_le router_be rb1xx
-INITRAMFS_EXTRA_FILES:=
-
-include $(INCLUDE_DIR)/target.mk
-
-DEFAULT_PACKAGES += admswconfig wpad-mini kmod-input-core \
- kmod-input-polldev kmod-input-gpio-keys-polled kmod-button-hotplug \
- kmod-leds-gpio kmod-ledtrig-adm5120-switch
-
-$(eval $(call BuildTarget))
+++ /dev/null
-#### VLAN configuration
-config switch
- option eth0 "0 1 2 3"
- option eth1 "4"
-
-
-#### Loopback configuration
-config interface loopback
- option ifname "lo"
- option proto static
- option ipaddr 127.0.0.1
- option netmask 255.0.0.0
-
-
-#### LAN configuration
-config interface lan
- option type bridge
- option ifname "eth0"
- option proto static
- option ipaddr 192.168.1.1
- option netmask 255.255.255.0
- option ip6assign 60
-
-
-#### WAN configuration
-config interface wan
- option ifname "eth1"
- option proto dhcp
-
-
-#### WAN6 configuration
-config interface wan6
- option ifname "@wan"
- option proto dhcpv6
-
-
-#### Network global configuration
-config globals globals
- option ula_prefix auto
+++ /dev/null
-config system
- option hostname OpenWrt
- option timezone UTC
-
-config timeserver ntp
- list server 0.openwrt.pool.ntp.org
- list server 1.openwrt.pool.ntp.org
- list server 2.openwrt.pool.ntp.org
- list server 3.openwrt.pool.ntp.org
-
-config led
- option sysfs lan1
- option trigger port_state
- option port_state link_act
-
-config led
- option sysfs lan2
- option trigger port_state
- option port_state link_act
-
-config led
- option sysfs lan3
- option trigger port_state
- option port_state link_act
-
-config led
- option sysfs lan4
- option trigger port_state
- option port_state link_act
-
-config led
- option sysfs wan
- option trigger port_state
- option port_state link_act
-
-config led
- option sysfs wlan
- option trigger netdev
- option dev wlan0
-
+++ /dev/null
-#!/bin/sh
-# Copyright (C) 2007-2013 OpenWrt.org
-
-. /lib/functions/leds.sh
-. /lib/adm5120.sh
-
-set_state() {
- case "$1" in
- preinit)
- status_led_blink_preinit
- ;;
- failsafe)
- status_led_blink_failsafe
- ;;
- done)
- status_led_on
- ;;
- esac
-}
+++ /dev/null
-::sysinit:/etc/init.d/rcS S boot
-::shutdown:/etc/init.d/rcS K shutdown
-tts/0::askfirst:/bin/ash --login
-ttyAM0::askfirst:/bin/ash --login
-tty1::askfirst:/bin/ash --login
+++ /dev/null
-#!/bin/sh
-#
-# Copyright (C) 2007 OpenWrt.org
-#
-#
-
-board_name=""
-status_led=""
-sys_mtd_part=""
-
-adm5120_detect() {
- board_name=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /machine/ {print $2}' /proc/cpuinfo)
-
- case "$board_name" in
- "Cellvision"*)
- status_led="status"
- sys_mtd_part="firmware"
- ;;
- "Compex"*)
- status_led="diag"
- case "$board_name" in
- *-WRT)
- sys_mtd_part="trx"
- ;;
- *)
- sys_mtd_part="partition1"
- ;;
- esac
- ;;
- "Edimax"*)
- status_led="power"
- sys_mtd_part="firmware"
- ;;
- "Infineon"*)
- sys_mtd_part="firmware"
- ;;
- "Mikrotik"*)
- status_led="power"
- ;;
- "ZyXEL"*)
- status_led="power"
- sys_mtd_part="trx"
- ;;
- "EB-214A"*)
- status_led="power"
- sys_mtd_part="firmware"
- ;;
- *)
- ;;
- esac
-}
-
-adm5120_detect
+++ /dev/null
-#!/bin/sh
-
-do_adm5120() {
- . /lib/adm5120.sh
-}
-
-boot_hook_add preinit_main do_adm5120
+++ /dev/null
-#!/bin/sh
-
-set_preinit_ifname() {
- ifname=eth0
-}
-
-boot_hook_add preinit_main set_preinit_ifname
-
-
+++ /dev/null
-#
-# Copyright (C) 2009-2010 OpenWrt.org
-#
-
-. /lib/adm5120.sh
-
-PART_NAME="firmware"
-RAMFS_COPY_DATA=/lib/adm5120.sh
-
-platform_check_image() {
- local magic="$(get_magic_word "$1")"
-
- [ "$#" -gt 1 ] && return 1
-
- case "$board_name" in
- "ZyXEL"*|"Compex WP54 family")
- # .trx files
- [ "$magic" != "4844" ] && {
- echo "Invalid image type."
- return 1
- }
- return 0
- ;;
- *)
- ;;
- esac
-
- echo "Sysupgrade is not yet supported on $board_name."
- return 1
-}
-
-platform_do_upgrade() {
- PART_NAME="$sys_mtd_part"
- default_do_upgrade "$ARGV"
-}
-
-disable_watchdog() {
- killall watchdog
- ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && {
- echo 'Could not disable watchdog'
- return 1
- }
-}
-append sysupgrade_pre_upgrade disable_watchdog
+++ /dev/null
-CONFIG_ADM5120=y
-CONFIG_ADM5120_ENET=y
-CONFIG_ADM5120_MACH_5GXI=y
-CONFIG_ADM5120_MACH_BR_6104K=y
-CONFIG_ADM5120_MACH_BR_6104KP=y
-CONFIG_ADM5120_MACH_BR_61X4WG=y
-CONFIG_ADM5120_MACH_CAS_771=y
-CONFIG_ADM5120_MACH_EASY5120P_ATA=y
-CONFIG_ADM5120_MACH_EASY5120_RT=y
-CONFIG_ADM5120_MACH_EASY5120_WVOIP=y
-CONFIG_ADM5120_MACH_EASY83000=y
-CONFIG_ADM5120_MACH_EB_214A=y
-CONFIG_ADM5120_MACH_NFS_101=y
-CONFIG_ADM5120_MACH_NP27G=y
-CONFIG_ADM5120_MACH_NP28G=y
-CONFIG_ADM5120_MACH_PMUGW=y
-# CONFIG_ADM5120_MACH_RB_11X is not set
-# CONFIG_ADM5120_MACH_RB_133 is not set
-# CONFIG_ADM5120_MACH_RB_133C is not set
-# CONFIG_ADM5120_MACH_RB_150 is not set
-# CONFIG_ADM5120_MACH_RB_153 is not set
-# CONFIG_ADM5120_MACH_RB_192 is not set
-CONFIG_ADM5120_MACH_WP54=y
-CONFIG_ADM5120_OEM_CELLVISION=y
-CONFIG_ADM5120_OEM_COMPEX=y
-CONFIG_ADM5120_OEM_EDIMAX=y
-CONFIG_ADM5120_OEM_GENERIC=y
-CONFIG_ADM5120_OEM_INFINEON=y
-# CONFIG_ADM5120_OEM_MIKROTIK is not set
-CONFIG_ADM5120_OEM_MOTOROLA=y
-CONFIG_ADM5120_OEM_OSBRIDGE=y
-# CONFIG_ADM5120_OEM_ZYXEL is not set
-CONFIG_ADM5120_SOC_BGA=y
-CONFIG_ADM5120_WDT=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM_AMBA=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_ATA=m
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_R4K_LIB=y
-CONFIG_CMDLINE="console=ttyAM0,115200 rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-CONFIG_CPU_MIPSR1=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_CSRC_R4K_LIB=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HID=m
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-# CONFIG_HOSTAP_FIRMWARE_NVRAM is not set
-CONFIG_HOSTAP_PCI=m
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=m
-# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_FORCED_THREADING=y
-# CONFIG_LEDS_TRIGGER_ADM5120_SWITCH is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIB80211=m
-CONFIG_LIB80211_CRYPT_CCMP=m
-CONFIG_LIB80211_CRYPT_TKIP=m
-CONFIG_LIB80211_CRYPT_WEP=m
-CONFIG_MII=m
-CONFIG_MIPS=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_MACHINE=y
-CONFIG_MIPS_MT_DISABLED=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_ADM5120=y
-CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_MYLOADER_PARTS=y
-CONFIG_MTD_TRXSPLIT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NLS=m
-CONFIG_NO_EXCEPT_FILL=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NO_HZ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_SCSI=m
-CONFIG_SCSI_MOD=m
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_AMBA_PL010=y
-CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
-CONFIG_SERIAL_AMBA_PL010_NUMPORTS=2
-# CONFIG_SERIAL_AMBA_PL011 is not set
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SOFT_WATCHDOG=m
-# CONFIG_SWAP is not set
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB=m
-CONFIG_USB_ADM5120_HCD=m
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_COMMON=m
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_OHCI_HCD_PLATFORM is not set
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-if ADM5120
-
-menu "ADM5120 Board selection"
-
-config ADM5120_MACH_CAS_771
- bool "Cellvision CAS-771/771W support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_CELLVISION
- default y
-
-config ADM5120_MACH_NFS_101
- bool "Cellvision NFS-101U/101WU support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_CELLVISION
- default y
-
-config ADM5120_MACH_NP27G
- bool "Compex NP27G support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_COMPEX
- default y
-
-config ADM5120_MACH_NP28G
- bool "Compex NP28G support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_COMPEX
- default y
-
-config ADM5120_MACH_WP54
- bool "Compex WP54 family support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_COMPEX
- default y
-
-config ADM5120_MACH_EB_214A
- bool "EB-214A support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_GENERIC
- default y
-
-config ADM5120_MACH_BR_6104K
- bool "Edimax BR-6104K support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_OEM_EDIMAX
- default y
-
-config ADM5120_MACH_BR_6104KP
- bool "Edimax BR-6104KP support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_OEM_EDIMAX
- default y
-
-config ADM5120_MACH_BR_61X4WG
- bool "Edimax BR-6104WG/6114WG support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_EDIMAX
- default y
-
-config ADM5120_MACH_EASY5120_RT
- bool "Infineon EASY 5120-RT Reference Board support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_INFINEON
- default y
-
-config ADM5120_MACH_EASY5120_WVOIP
- bool "Infineon EASY 5120-WVoIP Reference Board support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_INFINEON
- default y
-
-config ADM5120_MACH_EASY5120P_ATA
- bool "Infineon EASY 5120P-ATA Reference Board support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_OEM_INFINEON
- default y
-
-config ADM5120_MACH_EASY83000
- bool "Infineon EASY 83000 Reference Board support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_OEM_INFINEON
- default y
-
-config ADM5120_MACH_RB_11X
- bool "MikroTik RouterBOARD 111/112 support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_MIKROTIK
- default y
-
-config ADM5120_MACH_RB_133
- bool "MikroTik RouterBOARD 133 support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_MIKROTIK
- default y
-
-config ADM5120_MACH_RB_133C
- bool "MikroTik RouterBOARD 133C support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_MIKROTIK
- default y
-
-config ADM5120_MACH_RB_150
- bool "MikroTik RouterBOARD 150 support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_OEM_MIKROTIK
- default y
-
-config ADM5120_MACH_RB_153
- bool "MikroTik RouterBOARD 153 support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_MIKROTIK
- default y
-
-config ADM5120_MACH_RB_192
- bool "MikroTik RouterBOARD 192 support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_MIKROTIK
- default y
-
-config ADM5120_MACH_PMUGW
- bool "Motorola Powerline MU Gateway"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_MOTOROLA
- default y
-
-config ADM5120_MACH_5GXI
- bool "OSBRiDGE 5GXi/5XLi support"
- depends on CPU_LITTLE_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_OSBRIDGE
- default y
-
-config ADM5120_MACH_P_334WT
- bool "ZyXEL Prestige 334WT"
- depends on CPU_BIG_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_ZYXEL
- default y
-
-config ADM5120_MACH_P_335
- bool "ZyXEL Prestige 335/335WT"
- depends on CPU_BIG_ENDIAN
- select ADM5120_SOC_BGA
- select ADM5120_OEM_ZYXEL
- default y
-
-endmenu
-
-config ADM5120_SOC_BGA
- select HW_HAS_PCI
- def_bool n
-
-config ADM5120_OEM_CELLVISION
- def_bool n
-
-config ADM5120_OEM_COMPEX
- def_bool n
-
-config ADM5120_OEM_EDIMAX
- def_bool n
-
-config ADM5120_OEM_GENERIC
- def_bool n
-
-config ADM5120_OEM_INFINEON
- def_bool n
-
-config ADM5120_OEM_MIKROTIK
- def_bool n
-
-config ADM5120_OEM_MOTOROLA
- def_bool n
-
-config ADM5120_OEM_OSBRIDGE
- def_bool n
-
-config ADM5120_OEM_ZYXEL
- def_bool n
-
-config ARM_AMBA
- def_bool y
-
-endif
+++ /dev/null
-#
-# Infineon/ADMtek ADM5120
-#
-
-platform-$(CONFIG_ADM5120) += adm5120/common/
-
-platform-$(CONFIG_ADM5120_OEM_CELLVISION) += adm5120/cellvision/
-platform-$(CONFIG_ADM5120_OEM_COMPEX) += adm5120/compex/
-platform-$(CONFIG_ADM5120_OEM_EDIMAX) += adm5120/edimax/
-platform-$(CONFIG_ADM5120_OEM_GENERIC) += adm5120/generic/
-platform-$(CONFIG_ADM5120_OEM_INFINEON) += adm5120/infineon/
-platform-$(CONFIG_ADM5120_OEM_MIKROTIK) += adm5120/mikrotik/
-platform-$(CONFIG_ADM5120_OEM_MOTOROLA) += adm5120/motorola/
-platform-$(CONFIG_ADM5120_OEM_OSBRIDGE) += adm5120/osbridge/
-platform-$(CONFIG_ADM5120_OEM_ZYXEL) += adm5120/zyxel/
-
-cflags-$(CONFIG_ADM5120) += -I$(srctree)/arch/mips/include/asm/mach-adm5120
-libs-$(CONFIG_ADM5120) += arch/mips/adm5120/prom/
-load-$(CONFIG_ADM5120) += 0xffffffff80001000
+++ /dev/null
-obj-y += cellvision.o
-
-obj-$(CONFIG_ADM5120_MACH_CAS_771) += cas-771.o
-obj-$(CONFIG_ADM5120_MACH_NFS_101) += nfs-101.o
+++ /dev/null
-/*
- * Cellvision/SparkLAN CAS-771/771W support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "cellvision.h"
-
-static struct adm5120_pci_irq cas771_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
- PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI1),
- PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2)
-};
-
-static struct gpio_led cas771_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN0, "cam_flash", NULL),
- /* GPIO PIN3 is the reset */
- GPIO_LED_STD(ADM5120_GPIO_PIN6, "access", NULL),
- GPIO_LED_STD(ADM5120_GPIO_P0L1, "status", NULL),
- GPIO_LED_STD(ADM5120_GPIO_P0L2, "diag", NULL),
-};
-
-static void __init cas771_setup(void)
-{
- cas7xx_setup();
- adm5120_add_device_gpio_leds(ARRAY_SIZE(cas771_gpio_leds),
- cas771_gpio_leds);
- adm5120_pci_set_irq_map(ARRAY_SIZE(cas771_pci_irqs), cas771_pci_irqs);
-}
-
-MIPS_MACHINE(MACH_ADM5120_CAS771, "CAS-771", "Cellvision CAS-771/771W",
- cas771_setup);
+++ /dev/null
-/*
- * Cellvision/SparkLAN boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "cellvision.h"
-
-#include <prom/admboot.h>
-
-#define CELLVISION_GPIO_FLASH_A20 ADM5120_GPIO_PIN5
-#define CELLVISION_GPIO_DEV_MASK (1 << CELLVISION_GPIO_FLASH_A20)
-
-#define CELLVISION_CONFIG_OFFSET 0x8000
-#define CELLVISION_CONFIG_SIZE 0x1000
-
-static struct mtd_partition cas6xx_partitions[] = {
- {
- .name = "admboot",
- .offset = 0,
- .size = 32*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "config",
- .offset = MTDPART_OFS_APPEND,
- .size = 32*1024,
- } , {
- .name = "nvfs1",
- .offset = MTDPART_OFS_APPEND,
- .size = 64*1024,
- } , {
- .name = "nvfs2",
- .offset = MTDPART_OFS_APPEND,
- .size = 64*1024,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct mtd_partition cas7xx_partitions[] = {
- {
- .name = "admboot",
- .offset = 0,
- .size = 32*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "config",
- .offset = MTDPART_OFS_APPEND,
- .size = 32*1024,
- } , {
- .name = "nvfs",
- .offset = MTDPART_OFS_APPEND,
- .size = 128*1024,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static void switch_bank_gpio5(unsigned bank)
-{
- switch (bank) {
- case 0:
- gpio_set_value(CELLVISION_GPIO_FLASH_A20, 0);
- break;
- case 1:
- gpio_set_value(CELLVISION_GPIO_FLASH_A20, 1);
- break;
- }
-}
-
-static void __init cellvision_flash_setup(void)
-{
- /* setup flash A20 line */
- gpio_request(CELLVISION_GPIO_FLASH_A20, NULL);
- gpio_direction_output(CELLVISION_GPIO_FLASH_A20, 0);
-
- adm5120_flash0_data.switch_bank = switch_bank_gpio5;
- adm5120_add_device_flash(0);
-}
-
-void __init cellvision_mac_setup(void)
-{
- u8 mac_base[6];
- int err;
-
- err = admboot_get_mac_base(CELLVISION_CONFIG_OFFSET,
- CELLVISION_CONFIG_SIZE, mac_base);
-
- if ((err) || !is_valid_ether_addr(mac_base))
- random_ether_addr(mac_base);
-
- adm5120_setup_eth_macs(mac_base);
-}
-
-void __init cas6xx_flash_setup(void)
-{
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(cas6xx_partitions);
- adm5120_flash0_data.parts = cas6xx_partitions;
-
- cellvision_flash_setup();
-}
-
-void __init cas7xx_flash_setup(void)
-{
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(cas7xx_partitions);
- adm5120_flash0_data.parts = cas7xx_partitions;
-
- cellvision_flash_setup();
-}
-
-void __init cas6xx_setup(void)
-{
- cas6xx_flash_setup();
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
- adm5120_add_device_switch(1, NULL);
-}
-
-MIPS_MACHINE(MACH_ADM5120_CAS630, "CAS-630", "Cellvision CAS-630/630W",
- cas6xx_setup);
-MIPS_MACHINE(MACH_ADM5120_CAS670, "CAS-670", "Cellvision CAS-670/670W",
- cas6xx_setup);
-
-void __init cas7xx_setup(void)
-{
- cas7xx_flash_setup();
- cellvision_mac_setup();
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
- adm5120_add_device_switch(1, NULL);
-}
-
-MIPS_MACHINE(MACH_ADM5120_CAS700, "CAS-700", "Cellvision CAS-700/700W",
- cas7xx_setup);
-MIPS_MACHINE(MACH_ADM5120_CAS790, "CAS-790", "Cellvision CAS-790",
- cas7xx_setup);
-MIPS_MACHINE(MACH_ADM5120_CAS861, "CAS-861", "Cellvision CAS-861/861W",
- cas7xx_setup);
+++ /dev/null
-/*
- * Cellvision/SparkLAN boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/mips_machine.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-extern void cellvision_mac_setup(void) __init;
-
-extern void cas6xx_flash_setup(void) __init;
-extern void cas7xx_flash_setup(void) __init;
-extern void cas6xx_setup(void) __init;
-extern void cas7xx_setup(void) __init;
+++ /dev/null
-/*
- * Cellvision/SparkLAN NFS-101U/WU support
- *
- * Copyright (C) 2007-2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "cellvision.h"
-
-static struct adm5120_pci_irq nfs101_pci_irqs[] __initdata = {
- /* miniPCI slot */
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
-
- /* ALi USB controller */
- PCIIRQ(3, 0, 2, ADM5120_IRQ_PCI2),
- PCIIRQ(3, 3, 1, ADM5120_IRQ_PCI1),
-
- /* NEC USB controller */
- PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI1),
- PCIIRQ(3, 1, 2, ADM5120_IRQ_PCI2),
- PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2),
-};
-
-static u8 nfs101_vlans[6] __initdata = {
- /* FIXME: not tested */
- 0x5f, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static void __init nfs101_setup(void)
-{
- cas6xx_flash_setup();
- cellvision_mac_setup();
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
- adm5120_add_device_switch(1, nfs101_vlans);
-
- adm5120_pci_set_irq_map(ARRAY_SIZE(nfs101_pci_irqs),
- nfs101_pci_irqs);
-}
-
-MIPS_MACHINE(MACH_ADM5120_NFS101U, "NFS-101U", "Cellvision NFS-101U/101WU",
- nfs101_setup);
+++ /dev/null
-#
-# Makefile for the Infineon/ADMtek ADM5120 SoC specific parts of the kernel
-#
-
-obj-y := adm5120.o setup.o prom.o irq.o memory.o clock.o \
- gpio.o platform.o
-
-obj-$(CONFIG_EARLY_PRINTK) += early-printk.o
+++ /dev/null
-/*
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <asm/addrspace.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-
-unsigned int adm5120_product_code;
-unsigned int adm5120_revision;
-unsigned int adm5120_package;
-unsigned int adm5120_nand_boot;
-unsigned long adm5120_speed;
-
-/*
- * CPU settings detection
- */
-#define CODE_GET_PC(c) ((c) & CODE_PC_MASK)
-#define CODE_GET_REV(c) (((c) >> CODE_REV_SHIFT) & CODE_REV_MASK)
-#define CODE_GET_PK(c) (((c) >> CODE_PK_SHIFT) & CODE_PK_MASK)
-#define CODE_GET_CLKS(c) (((c) >> CODE_CLKS_SHIFT) & CODE_CLKS_MASK)
-#define CODE_GET_NAB(c) (((c) & CODE_NAB) != 0)
-
-void adm5120_ndelay(u32 ns)
-{
- u32 t;
-
- SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
- SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
-
- t = (ns+640) / 640;
- t &= TIMER_PERIOD_MASK;
- SW_WRITE_REG(SWITCH_REG_TIMER, t | TIMER_TE);
-
- /* wait until the timer expires */
- do {
- t = SW_READ_REG(SWITCH_REG_TIMER_INT);
- } while ((t & TIMER_INT_TOS) == 0);
-
- /* leave the timer disabled */
- SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
- SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
-}
-
-void __init adm5120_soc_init(void)
-{
- u32 code;
- u32 clks;
-
- code = SW_READ_REG(SWITCH_REG_CODE);
-
- adm5120_product_code = CODE_GET_PC(code);
- adm5120_revision = CODE_GET_REV(code);
- adm5120_package = (CODE_GET_PK(code) == CODE_PK_BGA) ?
- ADM5120_PACKAGE_BGA : ADM5120_PACKAGE_PQFP;
- adm5120_nand_boot = CODE_GET_NAB(code);
-
- clks = CODE_GET_CLKS(code);
- adm5120_speed = ADM5120_SPEED_175;
- if (clks & 1)
- adm5120_speed += 25000000;
- if (clks & 2)
- adm5120_speed += 50000000;
-}
+++ /dev/null
-/*
- * ADM5120 minimal CLK API implementation
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was based on the CLK API implementation in:
- * arch/mips/tx4938/toshiba_rbtx4938/setup.c
- * Copyright (C) 2000-2001 Toshiba Corporation
- * 2003-2005 (c) MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/device.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-
-struct clk {
- unsigned long rate;
-};
-
-static struct clk uart_clk = {
- .rate = ADM5120_UART_CLOCK
-};
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
- const char *name = dev_name(dev);
-
- if (!strcmp(name, "apb:uart0") || !strcmp(name, "apb:uart1"))
- return &uart_clk;
-
- return ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL(clk_get);
-
-int clk_enable(struct clk *clk)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
+++ /dev/null
-/*
- * ADM5120 specific early printk support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <asm/addrspace.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_uart.h>
-
-#define UART_READ(r) \
- __raw_readl((void __iomem *)(KSEG1ADDR(ADM5120_UART0_BASE)+(r)))
-#define UART_WRITE(r, v) \
- __raw_writel((v), (void __iomem *)(KSEG1ADDR(ADM5120_UART0_BASE)+(r)))
-
-void __init prom_putchar(char ch)
-{
- while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0)
- ;
- UART_WRITE(UART_REG_DATA, ch);
- while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0)
- ;
-}
+++ /dev/null
-/*
- * ADM5120 generic GPIO API support via GPIOLIB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <asm/addrspace.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-
-#define GPIO_REG(r) (void __iomem *)(KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
-
-struct gpio1_desc {
- void __iomem *reg; /* register address */
- u8 iv_shift; /* shift amount for input bit */
- u8 mode_shift; /* shift amount for mode bits */
-};
-
-#define GPIO1_DESC(p, l) { \
- .reg = GPIO_REG(SWITCH_REG_PORT0_LED + ((p) * 4)), \
- .iv_shift = LED0_IV_SHIFT + (l), \
- .mode_shift = (l) * 4 \
- }
-
-static struct gpio1_desc gpio1_table[15] = {
- GPIO1_DESC(0, 0), GPIO1_DESC(0, 1), GPIO1_DESC(0, 2),
- GPIO1_DESC(1, 0), GPIO1_DESC(1, 1), GPIO1_DESC(1, 2),
- GPIO1_DESC(2, 0), GPIO1_DESC(2, 1), GPIO1_DESC(2, 2),
- GPIO1_DESC(3, 0), GPIO1_DESC(3, 1), GPIO1_DESC(3, 2),
- GPIO1_DESC(4, 0), GPIO1_DESC(4, 1), GPIO1_DESC(4, 2)
-};
-
-static u32 gpio_conf2;
-
-int adm5120_gpio_to_irq(unsigned gpio)
-{
- int ret;
-
- switch (gpio) {
- case ADM5120_GPIO_PIN2:
- ret = ADM5120_IRQ_GPIO2;
- break;
- case ADM5120_GPIO_PIN4:
- ret = ADM5120_IRQ_GPIO4;
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-EXPORT_SYMBOL(adm5120_gpio_to_irq);
-
-int adm5120_irq_to_gpio(unsigned irq)
-{
- int ret;
-
- switch (irq) {
- case ADM5120_IRQ_GPIO2:
- ret = ADM5120_GPIO_PIN2;
- break;
- case ADM5120_IRQ_GPIO4:
- ret = ADM5120_GPIO_PIN4;
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-EXPORT_SYMBOL(adm5120_irq_to_gpio);
-
-/*
- * Helpers for GPIO lines in GPIO_CONF0 register
- */
-#define PIN_IM(p) ((1 << GPIO_CONF0_IM_SHIFT) << p)
-#define PIN_IV(p) ((1 << GPIO_CONF0_IV_SHIFT) << p)
-#define PIN_OE(p) ((1 << GPIO_CONF0_OE_SHIFT) << p)
-#define PIN_OV(p) ((1 << GPIO_CONF0_OV_SHIFT) << p)
-
-int __adm5120_gpio0_get_value(unsigned offset)
-{
- void __iomem **reg;
- u32 t;
-
- reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
-
- t = __raw_readl(reg);
- if ((t & PIN_IM(offset)) != 0)
- t &= PIN_IV(offset);
- else
- t &= PIN_OV(offset);
-
- return (t) ? 1 : 0;
-}
-EXPORT_SYMBOL(__adm5120_gpio0_get_value);
-
-void __adm5120_gpio0_set_value(unsigned offset, int value)
-{
- void __iomem **reg;
- u32 t;
-
- reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
-
- t = __raw_readl(reg);
- if (value == 0)
- t &= ~(PIN_OV(offset));
- else
- t |= PIN_OV(offset);
-
- __raw_writel(t, reg);
-}
-EXPORT_SYMBOL(__adm5120_gpio0_set_value);
-
-static int adm5120_gpio0_get_value(struct gpio_chip *chip, unsigned offset)
-{
- return __adm5120_gpio0_get_value(offset);
-}
-
-static void adm5120_gpio0_set_value(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- __adm5120_gpio0_set_value(offset, value);
-}
-
-static int adm5120_gpio0_direction_input(struct gpio_chip *chip,
- unsigned offset)
-{
- void __iomem **reg;
- u32 t;
-
- reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
-
- t = __raw_readl(reg);
- t &= ~(PIN_OE(offset));
- t |= PIN_IM(offset);
- __raw_writel(t, reg);
-
- return 0;
-}
-
-static int adm5120_gpio0_direction_output(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- void __iomem **reg;
- u32 t;
-
- reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
-
- t = __raw_readl(reg);
- t &= ~(PIN_IM(offset) | PIN_OV(offset));
- t |= PIN_OE(offset);
-
- if (value)
- t |= PIN_OV(offset);
-
- __raw_writel(t, reg);
-
- return 0;
-}
-
-static struct gpio_chip adm5120_gpio0_chip = {
- .label = "adm5120 gpio0",
- .get = adm5120_gpio0_get_value,
- .set = adm5120_gpio0_set_value,
- .direction_input = adm5120_gpio0_direction_input,
- .direction_output = adm5120_gpio0_direction_output,
- .base = ADM5120_GPIO_PIN0,
- .ngpio = ADM5120_GPIO_PIN7 - ADM5120_GPIO_PIN0 + 1,
-};
-
-int __adm5120_gpio1_get_value(unsigned offset)
-{
- void __iomem **reg;
- u32 t, m;
-
- reg = gpio1_table[offset].reg;
-
- t = __raw_readl(reg);
- m = (t >> gpio1_table[offset].mode_shift) & LED_MODE_MASK;
- if (m == LED_MODE_INPUT)
- return (t >> gpio1_table[offset].iv_shift) & 1;
-
- if (m == LED_MODE_OUT_LOW)
- return 0;
-
- return 1;
-}
-EXPORT_SYMBOL(__adm5120_gpio1_get_value);
-
-void __adm5120_gpio1_set_value(unsigned offset, int value)
-{
- void __iomem **reg;
- u32 t, s;
-
- reg = gpio1_table[offset].reg;
- s = gpio1_table[offset].mode_shift;
-
- t = __raw_readl(reg);
- t &= ~(LED_MODE_MASK << s);
-
- switch (value) {
- case ADM5120_GPIO_LOW:
- t |= (LED_MODE_OUT_LOW << s);
- break;
- case ADM5120_GPIO_FLASH:
- case ADM5120_GPIO_LINK:
- case ADM5120_GPIO_SPEED:
- case ADM5120_GPIO_DUPLEX:
- case ADM5120_GPIO_ACT:
- case ADM5120_GPIO_COLL:
- case ADM5120_GPIO_LINK_ACT:
- case ADM5120_GPIO_DUPLEX_COLL:
- case ADM5120_GPIO_10M_ACT:
- case ADM5120_GPIO_100M_ACT:
- t |= ((value & LED_MODE_MASK) << s);
- break;
- default:
- t |= (LED_MODE_OUT_HIGH << s);
- break;
- }
-
- __raw_writel(t, reg);
-}
-EXPORT_SYMBOL(__adm5120_gpio1_set_value);
-
-static int adm5120_gpio1_get_value(struct gpio_chip *chip, unsigned offset)
-{
- return __adm5120_gpio1_get_value(offset);
-}
-
-static void adm5120_gpio1_set_value(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- __adm5120_gpio1_set_value(offset, value);
-}
-
-static int adm5120_gpio1_direction_input(struct gpio_chip *chip,
- unsigned offset)
-{
- void __iomem **reg;
- u32 t;
-
- reg = gpio1_table[offset].reg;
- t = __raw_readl(reg);
- t &= ~(LED_MODE_MASK << gpio1_table[offset].mode_shift);
- __raw_writel(t, reg);
-
- return 0;
-}
-
-static int adm5120_gpio1_direction_output(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- __adm5120_gpio1_set_value(offset, value);
- return 0;
-}
-
-static struct gpio_chip adm5120_gpio1_chip = {
- .label = "adm5120 gpio1",
- .get = adm5120_gpio1_get_value,
- .set = adm5120_gpio1_set_value,
- .direction_input = adm5120_gpio1_direction_input,
- .direction_output = adm5120_gpio1_direction_output,
- .base = ADM5120_GPIO_P0L0,
- .ngpio = ADM5120_GPIO_P4L2 - ADM5120_GPIO_P0L0 + 1,
-};
-
-void __init adm5120_gpio_csx0_enable(void)
-{
- gpio_conf2 |= GPIO_CONF2_CSX0;
- SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
-
- gpio_request(ADM5120_GPIO_PIN1, "CSX0");
-}
-
-void __init adm5120_gpio_csx1_enable(void)
-{
- gpio_conf2 |= GPIO_CONF2_CSX1;
- SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
-
- gpio_request(ADM5120_GPIO_PIN3, "CSX1");
-}
-
-void __init adm5120_gpio_ew_enable(void)
-{
- gpio_conf2 |= GPIO_CONF2_EW;
- SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
-
- gpio_request(ADM5120_GPIO_PIN0, "EW");
-}
-
-void __init adm5120_gpio_init(void)
-{
- int err;
-
- SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
-
- if (adm5120_package_pqfp()) {
- gpiochip_reserve(ADM5120_GPIO_PIN4, 4);
- adm5120_gpio0_chip.ngpio = 4;
- }
-
- err = gpiochip_add(&adm5120_gpio0_chip);
- if (err)
- panic("cannot add ADM5120 GPIO0 chip, error=%d", err);
-
- err = gpiochip_add(&adm5120_gpio1_chip);
- if (err)
- panic("cannot add ADM5120 GPIO1 chip, error=%d", err);
-
-}
+++ /dev/null
-/*
- * ADM5120 specific interrupt handlers
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/version.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-#include <linux/bitops.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-
-static void adm5120_intc_irq_unmask(struct irq_data *d);
-static void adm5120_intc_irq_mask(struct irq_data *d);
-static int adm5120_intc_irq_set_type(struct irq_data *d, unsigned int flow_type);
-
-static inline void intc_write_reg(unsigned int reg, u32 val)
-{
- void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
-
- __raw_writel(val, base + reg);
-}
-
-static inline u32 intc_read_reg(unsigned int reg)
-{
- void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
-
- return __raw_readl(base + reg);
-}
-
-static struct irq_chip adm5120_intc_irq_chip = {
- .name = "INTC",
- .irq_unmask = adm5120_intc_irq_unmask,
- .irq_mask = adm5120_intc_irq_mask,
- .irq_mask_ack = adm5120_intc_irq_mask,
- .irq_set_type = adm5120_intc_irq_set_type
-};
-
-static struct irqaction adm5120_intc_irq_action = {
- .handler = no_action,
- .name = "cascade [INTC]"
-};
-
-static void adm5120_intc_irq_unmask(struct irq_data *d)
-{
- intc_write_reg(INTC_REG_IRQ_ENABLE, 1 << (d->irq - ADM5120_INTC_IRQ_BASE));
-}
-
-static void adm5120_intc_irq_mask(struct irq_data *d)
-{
- intc_write_reg(INTC_REG_IRQ_DISABLE, 1 << (d->irq - ADM5120_INTC_IRQ_BASE));
-}
-
-static int adm5120_intc_irq_set_type(struct irq_data *d, unsigned int flow_type)
-{
- unsigned int irq = d->irq;
- unsigned int sense;
- unsigned long mode;
- int err = 0;
-
- sense = flow_type & (IRQ_TYPE_SENSE_MASK);
- switch (sense) {
- case IRQ_TYPE_NONE:
- case IRQ_TYPE_LEVEL_HIGH:
- break;
- case IRQ_TYPE_LEVEL_LOW:
- switch (irq) {
- case ADM5120_IRQ_GPIO2:
- case ADM5120_IRQ_GPIO4:
- break;
- default:
- err = -EINVAL;
- break;
- }
- break;
- default:
- err = -EINVAL;
- break;
- }
-
- if (err)
- return err;
-
- switch (irq) {
- case ADM5120_IRQ_GPIO2:
- case ADM5120_IRQ_GPIO4:
- mode = intc_read_reg(INTC_REG_INT_MODE);
- if (sense == IRQ_TYPE_LEVEL_LOW)
- mode |= (1 << (irq - ADM5120_INTC_IRQ_BASE));
- else
- mode &= ~(1 << (irq - ADM5120_INTC_IRQ_BASE));
-
- intc_write_reg(INTC_REG_INT_MODE, mode);
- break;
- }
-
- return 0;
-}
-
-static void adm5120_intc_irq_dispatch(void)
-{
- unsigned long status;
- int irq;
-
- status = intc_read_reg(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
- if (status) {
- irq = ADM5120_INTC_IRQ_BASE + fls(status) - 1;
- do_IRQ(irq);
- } else
- spurious_interrupt();
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned long pending;
-
- pending = read_c0_status() & read_c0_cause() & ST0_IM;
-
- if (pending & STATUSF_IP7)
- do_IRQ(ADM5120_IRQ_COUNTER);
- else if (pending & STATUSF_IP2)
- adm5120_intc_irq_dispatch();
- else
- spurious_interrupt();
-}
-
-#define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
-static void __init adm5120_intc_irq_init(void)
-{
- int i;
-
- /* disable all interrupts */
- intc_write_reg(INTC_REG_IRQ_DISABLE, INTC_INT_ALL);
-
- /* setup all interrupts to generate IRQ instead of FIQ */
- intc_write_reg(INTC_REG_INT_MODE, 0);
-
- /* set active level for all external interrupts to HIGH */
- intc_write_reg(INTC_REG_INT_LEVEL, 0);
-
- /* disable usage of the TEST_SOURCE register */
- intc_write_reg(INTC_REG_IRQ_SOURCE_SELECT, 0);
-
- for (i = ADM5120_INTC_IRQ_BASE;
- i <= ADM5120_INTC_IRQ_BASE + INTC_IRQ_LAST;
- i++) {
- irq_set_chip_and_handler(i, &adm5120_intc_irq_chip,
- handle_level_irq);
- }
-
- setup_irq(ADM5120_IRQ_INTC, &adm5120_intc_irq_action);
-}
-
-void __init arch_init_irq(void)
-{
- mips_cpu_irq_init();
- adm5120_intc_irq_init();
-}
+++ /dev/null
-/*
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-#include <asm/mach-adm5120/adm5120_mpmc.h>
-
-#ifdef DEBUG
-# define mem_dbg(f, a...) printk(KERN_INFO "mem_detect: " f, ## a)
-#else
-# define mem_dbg(f, a...)
-#endif
-
-unsigned long adm5120_memsize;
-
-#define MEM_READL(a) __raw_readl((void __iomem *)(a))
-#define MEM_WRITEL(a, v) __raw_writel((v), (void __iomem *)(a))
-
-static int __init mem_check_pattern(u8 *addr, unsigned long offs)
-{
- u32 *p1 = (u32 *)addr;
- u32 *p2 = (u32 *)(addr+offs);
- u32 t, u, v;
-
- /* save original value */
- t = MEM_READL(p1);
-
- u = MEM_READL(p2);
- if (t != u)
- return 0;
-
- v = 0x55555555;
- if (u == v)
- v = 0xAAAAAAAA;
-
- mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1);
-
- MEM_WRITEL(p1, v);
- adm5120_ndelay(1000);
- u = MEM_READL(p2);
-
- mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u);
-
- /* restore original value */
- MEM_WRITEL(p1, t);
-
- return (v == u);
-}
-
-static void __init adm5120_detect_memsize(void)
-{
- u32 memctrl;
- u32 size, maxsize;
- u8 *p;
-
- memctrl = SW_READ_REG(SWITCH_REG_MEMCTRL);
- switch (memctrl & MEMCTRL_SDRS_MASK) {
- case MEMCTRL_SDRS_4M:
- maxsize = 4 << 20;
- break;
- case MEMCTRL_SDRS_8M:
- maxsize = 8 << 20;
- break;
- case MEMCTRL_SDRS_16M:
- maxsize = 16 << 20;
- break;
- default:
- maxsize = 64 << 20;
- break;
- }
-
- mem_dbg("checking for %uMB chip in 1st bank\n", maxsize >> 20);
-
- /* detect size of the 1st SDRAM bank */
- p = (u8 *)KSEG1ADDR(0);
- for (size = 2<<20; size <= (maxsize >> 1); size <<= 1) {
- if (mem_check_pattern(p, size)) {
- /* mirrored address */
- mem_dbg("mirrored data found at offset 0x%08X\n", size);
- break;
- }
- }
-
- mem_dbg("chip size in 1st bank is %uMB\n", size >> 20);
- adm5120_memsize = size;
-
- if (size != maxsize)
- /* 2nd bank is not supported */
- goto out;
-
- if ((memctrl & MEMCTRL_SDR1_ENABLE) == 0)
- /* 2nd bank is disabled */
- goto out;
-
- /*
- * some bootloaders enable 2nd bank, even if the 2nd SDRAM chip
- * are missing.
- */
- mem_dbg("check presence of 2nd bank\n");
-
- p = (u8 *)KSEG1ADDR(maxsize+size-4);
- if (mem_check_pattern(p, 0))
- adm5120_memsize += size;
-
- if (maxsize != size) {
- /* adjusting MECTRL register */
- memctrl &= ~(MEMCTRL_SDRS_MASK);
- switch (size>>20) {
- case 4:
- memctrl |= MEMCTRL_SDRS_4M;
- break;
- case 8:
- memctrl |= MEMCTRL_SDRS_8M;
- break;
- case 16:
- memctrl |= MEMCTRL_SDRS_16M;
- break;
- default:
- memctrl |= MEMCTRL_SDRS_64M;
- break;
- }
- SW_WRITE_REG(SWITCH_REG_MEMCTRL, memctrl);
- }
-
-out:
- mem_dbg("%dx%uMB memory found\n", (adm5120_memsize == size) ? 1 : 2 ,
- size>>20);
-}
-
-void __init adm5120_mem_init(void)
-{
- adm5120_detect_memsize();
- add_memory_region(0, adm5120_memsize, BOOT_MEM_RAM);
-}
+++ /dev/null
-/*
- * ADM5120 generic platform devices
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/slab.h>
-#include <linux/export.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-#include <asm/mach-adm5120/adm5120_nand.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-#if 1
-/*
- * TODO:remove global adm5120_eth* variables when the switch driver will be
- * converted into a real platform driver
- */
-unsigned int adm5120_eth_num_ports = 6;
-EXPORT_SYMBOL_GPL(adm5120_eth_num_ports);
-
-unsigned char adm5120_eth_macs[6][6] = {
- {'\00', 'A', 'D', 'M', '\x51', '\x20' },
- {'\00', 'A', 'D', 'M', '\x51', '\x21' },
- {'\00', 'A', 'D', 'M', '\x51', '\x22' },
- {'\00', 'A', 'D', 'M', '\x51', '\x23' },
- {'\00', 'A', 'D', 'M', '\x51', '\x24' },
- {'\00', 'A', 'D', 'M', '\x51', '\x25' }
-};
-EXPORT_SYMBOL_GPL(adm5120_eth_macs);
-
-unsigned char adm5120_eth_vlans[6] = {
- 0x41, 0x42, 0x44, 0x48, 0x50, 0x60
-};
-EXPORT_SYMBOL_GPL(adm5120_eth_vlans);
-#endif
-
-void __init adm5120_setup_eth_macs(u8 *mac_base)
-{
- u32 t;
- int i, j;
-
- t = ((u32) mac_base[3] << 16) | ((u32) mac_base[4] << 8)
- | ((u32) mac_base[5]);
-
- for (i = 0; i < ARRAY_SIZE(adm5120_eth_macs); i++) {
- for (j = 0; j < 3; j++)
- adm5120_eth_macs[i][j] = mac_base[j];
-
- adm5120_eth_macs[i][3] = (t >> 16) & 0xff;
- adm5120_eth_macs[i][4] = (t >> 8) & 0xff;
- adm5120_eth_macs[i][5] = t & 0xff;
-
- t++;
- }
-}
-
-/*
- * Built-in ethernet switch
- */
-struct resource adm5120_switch_resources[] = {
- [0] = {
- .start = ADM5120_SWITCH_BASE,
- .end = ADM5120_SWITCH_BASE+ADM5120_SWITCH_SIZE-1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = ADM5120_IRQ_SWITCH,
- .end = ADM5120_IRQ_SWITCH,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct adm5120_switch_platform_data adm5120_switch_data;
-struct platform_device adm5120_switch_device = {
- .name = "adm5120-switch",
- .id = -1,
- .num_resources = ARRAY_SIZE(adm5120_switch_resources),
- .resource = adm5120_switch_resources,
- .dev.platform_data = &adm5120_switch_data,
-};
-
-void __init adm5120_add_device_switch(unsigned num_ports, u8 *vlan_map)
-{
- if (num_ports > 0)
- adm5120_eth_num_ports = num_ports;
-
- if (vlan_map)
- memcpy(adm5120_eth_vlans, vlan_map, sizeof(adm5120_eth_vlans));
-
- platform_device_register(&adm5120_switch_device);
-}
-
-/*
- * USB Host Controller
- */
-struct resource adm5120_hcd_resources[] = {
- [0] = {
- .start = ADM5120_USBC_BASE,
- .end = ADM5120_USBC_BASE+ADM5120_USBC_SIZE-1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = ADM5120_IRQ_USBC,
- .end = ADM5120_IRQ_USBC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 adm5120_hcd_dma_mask = DMA_BIT_MASK(24);
-struct platform_device adm5120_hcd_device = {
- .name = "adm5120-hcd",
- .id = -1,
- .num_resources = ARRAY_SIZE(adm5120_hcd_resources),
- .resource = adm5120_hcd_resources,
- .dev = {
- .dma_mask = &adm5120_hcd_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(24),
- }
-};
-
-void __init adm5120_add_device_usb(void)
-{
- platform_device_register(&adm5120_hcd_device);
-}
-
-/*
- * NOR flash devices
- */
-struct adm5120_flash_platform_data adm5120_flash0_data;
-struct platform_device adm5120_flash0_device = {
- .name = "adm5120-flash",
- .id = 0,
- .dev.platform_data = &adm5120_flash0_data,
-};
-
-struct adm5120_flash_platform_data adm5120_flash1_data;
-struct platform_device adm5120_flash1_device = {
- .name = "adm5120-flash",
- .id = 1,
- .dev.platform_data = &adm5120_flash1_data,
-};
-
-void __init adm5120_add_device_flash(unsigned id)
-{
- struct platform_device *pdev;
-
- switch (id) {
- case 0:
- pdev = &adm5120_flash0_device;
- break;
- case 1:
- pdev = &adm5120_flash1_device;
- break;
- default:
- pdev = NULL;
- break;
- }
-
- if (pdev)
- platform_device_register(pdev);
-}
-
-/*
- * built-in UARTs
- */
-static void adm5120_uart_set_mctrl(struct amba_device *dev, void __iomem *base,
- unsigned int mctrl)
-{
-}
-
-struct amba_pl010_data adm5120_uart0_data = {
- .set_mctrl = adm5120_uart_set_mctrl
-};
-
-struct amba_device adm5120_uart0_device = {
- .dev = {
- .init_name = "apb:uart0",
- .platform_data = &adm5120_uart0_data,
- },
- .res = {
- .start = ADM5120_UART0_BASE,
- .end = ADM5120_UART0_BASE + ADM5120_UART_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- .irq = { ADM5120_IRQ_UART0, 0 },
- .periphid = 0x0041010,
-};
-
-struct amba_pl010_data adm5120_uart1_data = {
- .set_mctrl = adm5120_uart_set_mctrl
-};
-
-struct amba_device adm5120_uart1_device = {
- .dev = {
- .init_name = "apb:uart1",
- .platform_data = &adm5120_uart1_data,
- },
- .res = {
- .start = ADM5120_UART1_BASE,
- .end = ADM5120_UART1_BASE + ADM5120_UART_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- .irq = { ADM5120_IRQ_UART1, 0 },
- .periphid = 0x0041010,
-};
-
-void __init adm5120_add_device_uart(unsigned id)
-{
- struct amba_device *dev;
-
- switch (id) {
- case 0:
- dev = &adm5120_uart0_device;
- break;
- case 1:
- dev = &adm5120_uart1_device;
- break;
- default:
- dev = NULL;
- break;
- }
-
- if (dev)
- amba_device_register(dev, &iomem_resource);
-}
-
-/*
- * GPIO buttons
- */
-void __init adm5120_register_gpio_buttons(int id,
- unsigned poll_interval,
- unsigned nbuttons,
- struct gpio_keys_button *buttons)
-{
- struct platform_device *pdev;
- struct gpio_keys_platform_data pdata;
- struct gpio_keys_button *p;
- int err;
-
- p = kmemdup(buttons, nbuttons * sizeof(*p), GFP_KERNEL);
- if (!p)
- return;
-
- pdev = platform_device_alloc("gpio-keys-polled", id);
- if (!pdev)
- goto err_free_buttons;
-
- memset(&pdata, 0, sizeof(pdata));
- pdata.poll_interval = poll_interval;
- pdata.nbuttons = nbuttons;
- pdata.buttons = p;
-
- err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
- if (err)
- goto err_put_pdev;
-
- err = platform_device_add(pdev);
- if (err)
- goto err_put_pdev;
-
- return;
-
-err_put_pdev:
- platform_device_put(pdev);
-
-err_free_buttons:
- kfree(p);
-}
-
-/*
- * GPIO LEDS
- */
-struct gpio_led_platform_data adm5120_gpio_leds_data;
-struct platform_device adm5120_gpio_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev.platform_data = &adm5120_gpio_leds_data,
-};
-
-void __init adm5120_add_device_gpio_leds(unsigned num_leds,
- struct gpio_led *leds)
-{
- struct gpio_led *p;
-
- p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
- if (!p)
- return;
-
- memcpy(p, leds, num_leds * sizeof(*p));
- adm5120_gpio_leds_data.num_leds = num_leds;
- adm5120_gpio_leds_data.leds = p;
-
- platform_device_register(&adm5120_gpio_leds_device);
-}
-
-/*
- * NAND flash
- */
-struct resource adm5120_nand_resources[] = {
- [0] = {
- .start = ADM5120_NAND_BASE,
- .end = ADM5120_NAND_BASE + ADM5120_NAND_SIZE-1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static int adm5120_nand_ready(struct mtd_info *mtd)
-{
- return ((adm5120_nand_get_status() & ADM5120_NAND_STATUS_READY) != 0);
-}
-
-static void adm5120_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- if (ctrl & NAND_CTRL_CHANGE) {
- adm5120_nand_set_cle(ctrl & NAND_CLE);
- adm5120_nand_set_ale(ctrl & NAND_ALE);
- adm5120_nand_set_cen(ctrl & NAND_NCE);
- }
-
- if (cmd != NAND_CMD_NONE)
- NAND_WRITE_REG(NAND_REG_DATA, cmd);
-}
-
-void __init adm5120_add_device_nand(struct platform_nand_data *pdata)
-{
- struct platform_device *pdev;
- int err;
-
- pdev = platform_device_alloc("gen_nand", -1);
- if (!pdev)
- goto err_out;
-
- err = platform_device_add_resources(pdev, adm5120_nand_resources,
- ARRAY_SIZE(adm5120_nand_resources));
- if (err)
- goto err_put;
-
- err = platform_device_add_data(pdev, pdata, sizeof(*pdata));
- if (err)
- goto err_put;
-
- pdata = pdev->dev.platform_data;
- pdata->ctrl.dev_ready = adm5120_nand_ready;
- pdata->ctrl.cmd_ctrl = adm5120_nand_cmd_ctrl;
-
- err = platform_device_add(pdev);
- if (err)
- goto err_put;
-
- return;
-
-err_put:
- platform_device_put(pdev);
-err_out:
- return;
-}
+++ /dev/null
-/*
- * ADM5120 specific prom routines
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-
-#include <asm/bootinfo.h>
-#include <asm/mips_machine.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-
-#include <prom/cfe.h>
-#include <prom/generic.h>
-#include <prom/routerboot.h>
-#include <prom/myloader.h>
-#include <prom/zynos.h>
-
-unsigned int adm5120_prom_type = ADM5120_PROM_GENERIC;
-
-struct board_desc {
- unsigned long mach_type;
- char *name;
-};
-
-#define DEFBOARD(n, mt) { .mach_type = (mt), .name = (n)}
-static struct board_desc common_boards[] __initdata = {
- /* Cellvision/SparkLAN boards */
- DEFBOARD("CAS-630", MACH_ADM5120_CAS630),
- DEFBOARD("CAS-670", MACH_ADM5120_CAS670),
- DEFBOARD("CAS-700", MACH_ADM5120_CAS700),
- DEFBOARD("CAS-771", MACH_ADM5120_CAS771),
- DEFBOARD("CAS-790", MACH_ADM5120_CAS790),
- DEFBOARD("CAS-861", MACH_ADM5120_CAS861),
- DEFBOARD("NFS-101U", MACH_ADM5120_NFS101U),
- /* Compex boards */
- DEFBOARD("WP54G-WRT", MACH_ADM5120_WP54G_WRT),
- /* Edimax boards */
- DEFBOARD("BR-6104K", MACH_ADM5120_BR6104K),
- DEFBOARD("BR-6104KP", MACH_ADM5120_BR6104KP),
- DEFBOARD("BR-6104WG", MACH_ADM5120_BR61X4WG),
- DEFBOARD("BR-6114WG", MACH_ADM5120_BR61X4WG),
- /* Infineon boards */
- DEFBOARD("EASY 5120P-ATA", MACH_ADM5120_EASY5120PATA),
- DEFBOARD("EASY 5120-RT", MACH_ADM5120_EASY5120RT),
- DEFBOARD("EASY 5120-WVoIP", MACH_ADM5120_EASY5120WVOIP),
- DEFBOARD("EASY 83000", MACH_ADM5120_EASY83000),
- /* Mikrotik RouterBOARDs */
- DEFBOARD("111", MACH_ADM5120_RB_11X),
- DEFBOARD("112", MACH_ADM5120_RB_11X),
- DEFBOARD("133", MACH_ADM5120_RB_133),
- DEFBOARD("133C", MACH_ADM5120_RB_133C),
- DEFBOARD("133C3", MACH_ADM5120_RB_133C),
- DEFBOARD("150", MACH_ADM5120_RB_153), /* it's intentional */
- DEFBOARD("153", MACH_ADM5120_RB_153),
- DEFBOARD("192", MACH_ADM5120_RB_192),
- DEFBOARD("miniROUTER", MACH_ADM5120_RB_150),
- /* OSBRiDGE boards */
- DEFBOARD("OSBRiDGE 5GXi", MACH_ADM5120_5GXI),
- /* Motorola boards */
- DEFBOARD("Powerline MU Gateway", MACH_ADM5120_PMUGW),
- /* Generic EB-214A */
- DEFBOARD("ADM5120", MACH_ADM5120_EB_214A),
-};
-
-static unsigned long __init find_machtype_byname(char *name)
-{
- unsigned long ret;
- int i;
-
- ret = MACH_ADM5120_GENERIC;
- if (name == NULL)
- goto out;
-
- if (*name == '\0')
- goto out;
-
- for (i = 0; i < ARRAY_SIZE(common_boards); i++) {
- if (strcmp(common_boards[i].name, name) == 0) {
- ret = common_boards[i].mach_type;
- break;
- }
- }
-
-out:
- return ret;
-}
-
-static unsigned long __init detect_machtype_routerboot(void)
-{
- char *name;
-
- name = routerboot_get_boardname();
- return find_machtype_byname(name);
-}
-
-static unsigned long __init detect_machtype_generic(void)
-{
- char *name;
-
- name = generic_prom_getenv("board_name");
- return find_machtype_byname(name);
-}
-
-unsigned long __init detect_machtype_cfe(void)
-{
- char *name;
-
- name = cfe_getenv("BOARD_NAME");
- return find_machtype_byname(name);
-}
-
-static struct {
- unsigned long mach_type;
- u16 vendor_id;
- u16 board_id;
-} zynos_boards[] __initdata = {
-#define ZYNOS_BOARD(vi, bi, mt) \
- {.vendor_id = (vi), .board_id = (bi), .mach_type = (mt)}
-
-#define ZYXEL_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_ZYXEL, bi, mt)
-#define DLINK_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_DLINK, bi, mt)
-#define LUCENT_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_LUCENT, bi, mt)
- ZYXEL_BOARD(ZYNOS_BOARD_HS100, MACH_ADM5120_HS100),
- ZYXEL_BOARD(ZYNOS_BOARD_P334U, MACH_ADM5120_P334U),
- ZYXEL_BOARD(ZYNOS_BOARD_P334W, MACH_ADM5120_P334W),
- ZYXEL_BOARD(ZYNOS_BOARD_P334WH, MACH_ADM5120_P334WH),
- ZYXEL_BOARD(ZYNOS_BOARD_P334WHD, MACH_ADM5120_P334WHD),
- ZYXEL_BOARD(ZYNOS_BOARD_P334WT, MACH_ADM5120_P334WT),
- ZYXEL_BOARD(ZYNOS_BOARD_P334WT_ALT, MACH_ADM5120_P334WT),
- ZYXEL_BOARD(ZYNOS_BOARD_P335, MACH_ADM5120_P335),
- ZYXEL_BOARD(ZYNOS_BOARD_P335PLUS, MACH_ADM5120_P335PLUS),
- ZYXEL_BOARD(ZYNOS_BOARD_P335U, MACH_ADM5120_P335U)
-};
-
-static unsigned long __init detect_machtype_bootbase(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(zynos_boards); i++) {
- if (zynos_boards[i].vendor_id == bootbase_info.vendor_id &&
- zynos_boards[i].board_id == bootbase_info.board_id) {
- return zynos_boards[i].mach_type;
- break;
- }
- }
-
- printk(KERN_WARNING "Unknown ZyXEL model (%u)\n",
- bootbase_info.board_id);
- return MACH_ADM5120_GENERIC;
-}
-
-static struct {
- unsigned long mach_type;
- u16 vid;
- u16 did;
- u16 svid;
- u16 sdid;
-} mylo_boards[] __initdata = {
-#define MYLO_BOARD(v, d, sv, sd, mt) \
- {.vid = (v), .did = (d), .svid = (sv), .sdid = (sd), .mach_type = (mt)}
-#define COMPEX_BOARD(d, mt) \
- MYLO_BOARD(VENID_COMPEX, (d), VENID_COMPEX, (d), (mt))
-
- COMPEX_BOARD(DEVID_COMPEX_NP27G, MACH_ADM5120_NP27G),
- COMPEX_BOARD(DEVID_COMPEX_NP28G, MACH_ADM5120_NP28G),
- COMPEX_BOARD(DEVID_COMPEX_NP28GHS, MACH_ADM5120_NP28GHS),
- COMPEX_BOARD(DEVID_COMPEX_WP54G, MACH_ADM5120_WP54),
- COMPEX_BOARD(DEVID_COMPEX_WP54Gv1C, MACH_ADM5120_WP54Gv1C),
- COMPEX_BOARD(DEVID_COMPEX_WP54AG, MACH_ADM5120_WP54),
- COMPEX_BOARD(DEVID_COMPEX_WPP54G, MACH_ADM5120_WP54),
- COMPEX_BOARD(DEVID_COMPEX_WPP54AG, MACH_ADM5120_WP54),
-};
-
-static unsigned long __init detect_machtype_myloader(void)
-{
- unsigned long ret;
- int i;
-
- ret = MACH_ADM5120_GENERIC;
- for (i = 0; i < ARRAY_SIZE(mylo_boards); i++) {
- if (mylo_boards[i].vid == myloader_info.vid &&
- mylo_boards[i].did == myloader_info.did &&
- mylo_boards[i].svid == myloader_info.svid &&
- mylo_boards[i].sdid == myloader_info.sdid) {
- ret = mylo_boards[i].mach_type;
- break;
- }
- }
-
- return ret;
-}
-
-static void __init prom_detect_machtype(void)
-{
- if (bootbase_present()) {
- adm5120_prom_type = ADM5120_PROM_BOOTBASE;
- mips_machtype = detect_machtype_bootbase();
- return;
- }
-
- if (cfe_present()) {
- adm5120_prom_type = ADM5120_PROM_CFE;
- mips_machtype = detect_machtype_cfe();
- return;
- }
-
- if (myloader_present()) {
- adm5120_prom_type = ADM5120_PROM_MYLOADER;
- mips_machtype = detect_machtype_myloader();
- return;
- }
-
- if (routerboot_present()) {
- adm5120_prom_type = ADM5120_PROM_ROUTERBOOT;
- mips_machtype = detect_machtype_routerboot();
- return;
- }
-
- if (generic_prom_present()) {
- adm5120_prom_type = ADM5120_PROM_GENERIC;
- mips_machtype = detect_machtype_generic();
- return;
- }
-
- mips_machtype = MACH_ADM5120_GENERIC;
-}
-
-#ifdef CONFIG_IMAGE_CMDLINE_HACK
-extern char __image_cmdline[];
-
-static void __init prom_init_cmdline(void)
-{
- char *cmd;
-
- /* init command line, register a default kernel command line */
- cmd = __image_cmdline;
- if (strlen(cmd) > 0)
- strlcpy(arcs_cmdline, cmd, sizeof(arcs_cmdline));
-
-}
-#else
-static inline void prom_init_cmdline(void) {}
-#endif /* CONFIG_IMAGE_CMDLINE_HACK */
-
-void __init prom_init(void)
-{
- prom_detect_machtype();
- prom_init_cmdline();
-}
-
-void __init prom_free_prom_memory(void)
-{
- /* We do not have to prom memory to free */
-}
+++ /dev/null
-/*
- * ADM5120 specific setup
- *
- * Copyright (C) 2007-2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel
- * done by Jeroen Vreeken
- * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
- *
- * Jeroen's code was based on the Linux 2.4.xx source codes found in various
- * tarballs released by Edimax for it's ADM5120 based devices
- * Copyright (C) ADMtek Incorporated
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/reboot.h>
-#include <linux/time.h>
-
-#include <asm/reboot.h>
-#include <asm/time.h>
-#include <asm/bootinfo.h>
-#include <asm/mips_machine.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-#define ADM5120_SYS_TYPE_LEN 64
-
-unsigned char adm5120_sys_type[ADM5120_SYS_TYPE_LEN];
-void (*adm5120_board_reset)(void);
-
-static char *prom_names[ADM5120_PROM_LAST+1] __initdata = {
- [ADM5120_PROM_GENERIC] = "Generic",
- [ADM5120_PROM_CFE] = "CFE",
- [ADM5120_PROM_UBOOT] = "U-Boot",
- [ADM5120_PROM_MYLOADER] = "MyLoader",
- [ADM5120_PROM_ROUTERBOOT] = "RouterBOOT",
- [ADM5120_PROM_BOOTBASE] = "Bootbase"
-};
-
-static void __init adm5120_report(void)
-{
- printk(KERN_INFO "SoC : %s\n", adm5120_sys_type);
- printk(KERN_INFO "Bootdev : %s flash\n",
- adm5120_nand_boot ? "NAND" : "NOR");
- printk(KERN_INFO "Prom : %s\n", prom_names[adm5120_prom_type]);
-}
-
-const char *get_system_type(void)
-{
- return adm5120_sys_type;
-}
-
-static void adm5120_restart(char *command)
-{
- /* TODO: stop switch before reset */
-
- if (adm5120_board_reset)
- adm5120_board_reset();
-
- SW_WRITE_REG(SWITCH_REG_SOFT_RESET, 1);
-}
-
-static void adm5120_halt(void)
-{
- local_irq_disable();
-
- while (1) {
- if (cpu_wait)
- cpu_wait();
- }
-}
-
-void __init plat_time_init(void)
-{
- mips_hpt_frequency = adm5120_speed / 2;
-}
-
-void __init plat_mem_setup(void)
-{
- adm5120_soc_init();
- adm5120_mem_init();
-
- sprintf(adm5120_sys_type, "ADM%04X%s rev %u, running at %lu.%03lu MHz",
- adm5120_product_code,
- adm5120_package_bga() ? "" : "P",
- adm5120_revision,
- (adm5120_speed / 1000000), (adm5120_speed / 1000) % 1000);
-
- adm5120_report();
-
- _machine_restart = adm5120_restart;
- _machine_halt = adm5120_halt;
- pm_power_off = adm5120_halt;
-
- set_io_port_base(KSEG1);
-}
-
-static int __init adm5120_board_setup(void)
-{
- adm5120_gpio_init();
-
- mips_machine_setup();
-
- return 0;
-}
-arch_initcall(adm5120_board_setup);
-
-static void __init adm5120_generic_board_setup(void)
-{
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_add_device_flash(0);
- adm5120_add_device_switch(6, NULL);
-}
-
-MIPS_MACHINE(MACH_ADM5120_GENERIC, "Generic", "Generic ADM5120 board",
- adm5120_generic_board_setup);
+++ /dev/null
-obj-y += compex.o
-
-obj-$(CONFIG_ADM5120_MACH_NP27G) += np27g.o
-obj-$(CONFIG_ADM5120_MACH_NP28G) += np28g.o
-obj-$(CONFIG_ADM5120_MACH_WP54) += wp54.o
+++ /dev/null
-/*
- * Compex boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "compex.h"
-
-#include <asm/mach-adm5120/prom/myloader.h>
-
-static void switch_bank_gpio5(unsigned bank)
-{
- switch (bank) {
- case 0:
- gpio_set_value(ADM5120_GPIO_PIN5, 0);
- break;
- case 1:
- gpio_set_value(ADM5120_GPIO_PIN5, 1);
- break;
- }
-}
-
-void __init compex_mac_setup(void)
-{
- if (myloader_present()) {
- int i;
-
- for (i = 0; i < 6; i++) {
- if (is_valid_ether_addr(myloader_info.macs[i]))
- memcpy(adm5120_eth_macs[i],
- myloader_info.macs[i], ETH_ALEN);
- else
- random_ether_addr(adm5120_eth_macs[i]);
- }
- } else {
- u8 mac[ETH_ALEN];
-
- random_ether_addr(mac);
- adm5120_setup_eth_macs(mac);
- }
-}
-
-void __init compex_generic_setup(void)
-{
- gpio_request(ADM5120_GPIO_PIN5, NULL); /* for flash A20 line */
- gpio_direction_output(ADM5120_GPIO_PIN5, 0);
-
- adm5120_flash0_data.switch_bank = switch_bank_gpio5;
- adm5120_add_device_flash(0);
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- compex_mac_setup();
-}
+++ /dev/null
-/*
- * Compex boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/mips_machine.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-extern void compex_generic_setup(void) __init;
+++ /dev/null
-/*
- * Compex NP27G board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "compex.h"
-
-static u8 np27g_vlans[6] __initdata = {
- /* FIXME: untested */
- 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
-};
-
-static void __init np27g_setup(void)
-{
- compex_generic_setup();
- adm5120_add_device_switch(5, np27g_vlans);
- adm5120_add_device_usb();
-
- /* TODO: add PCI IRQ map */
-}
-
-MIPS_MACHINE(MACH_ADM5120_NP27G, "NP27G", "Compex NetPassage 27G", np27g_setup);
+++ /dev/null
-/*
- * Compex NP28G board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "compex.h"
-
-static struct adm5120_pci_irq np28g_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
- PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI0),
- PCIIRQ(3, 1, 2, ADM5120_IRQ_PCI1),
- PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2)
-};
-
-static struct gpio_led np28g_gpio_leds[] __initdata = {
- GPIO_LED_INV(ADM5120_GPIO_PIN2, "diag", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN3, "power", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN6, "wan_cond", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN7, "wifi", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L2, "usb1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L2, "usb2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L2, "usb3", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L2, "usb4", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL),
-};
-
-static u8 np28g_vlans[6] __initdata = {
- 0x50, 0x42, 0x44, 0x48, 0x00, 0x00
-};
-
-static void np28g_reset(void)
-{
- gpio_set_value(ADM5120_GPIO_PIN4, 0);
-}
-
-static void __init np28g_setup(void)
-{
- compex_generic_setup();
-
- /* setup reset line */
- gpio_request(ADM5120_GPIO_PIN4, NULL);
- gpio_direction_output(ADM5120_GPIO_PIN4, 1);
- adm5120_board_reset = np28g_reset;
-
- adm5120_add_device_switch(4, np28g_vlans);
- adm5120_add_device_usb();
-
- adm5120_add_device_gpio_leds(ARRAY_SIZE(np28g_gpio_leds),
- np28g_gpio_leds);
-
- adm5120_pci_set_irq_map(ARRAY_SIZE(np28g_pci_irqs), np28g_pci_irqs);
-}
-
-MIPS_MACHINE(MACH_ADM5120_NP28G, "NP28G", "Compex NetPassage 28G", np28g_setup);
+++ /dev/null
-/*
- * Compex WP54 board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "compex.h"
-
-#define WP54_KEYS_POLL_INTERVAL 20
-#define WP54_KEYS_DEBOUNCE_INTERVAL (3 * WP54_KEYS_POLL_INTERVAL)
-
-static struct mtd_partition wp54g_wrt_partitions[] = {
- {
- .name = "cfe",
- .offset = 0,
- .size = 0x050000,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "trx",
- .offset = MTDPART_OFS_APPEND,
- .size = 0x3A0000,
- } , {
- .name = "nvram",
- .offset = MTDPART_OFS_APPEND,
- .size = 0x010000,
- }
-};
-
-static struct adm5120_pci_irq wp54_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
-};
-
-static struct gpio_keys_button wp54_gpio_buttons[] __initdata = {
- {
- .desc = "reset_button",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = WP54_KEYS_DEBOUNCE_INTERVAL,
- .gpio = ADM5120_GPIO_PIN4,
- }
-};
-
-static struct gpio_led wp54_gpio_leds[] __initdata = {
- GPIO_LED_INV(ADM5120_GPIO_PIN2, "diag", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN6, "wlan", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN7, "wan", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan2", NULL),
-};
-
-static u8 wp54_vlans[6] __initdata = {
- 0x41, 0x42, 0x00, 0x00, 0x00, 0x00
-};
-
-static void wp54_reset(void)
-{
- gpio_set_value(ADM5120_GPIO_PIN3, 0);
-}
-
-static void __init wp54_setup(void)
-{
- compex_generic_setup();
-
- /* setup reset line */
- gpio_request(ADM5120_GPIO_PIN3, NULL);
- gpio_direction_output(ADM5120_GPIO_PIN3, 1);
- adm5120_board_reset = wp54_reset;
-
- adm5120_add_device_switch(2, wp54_vlans);
- adm5120_register_gpio_buttons(-1, WP54_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(wp54_gpio_buttons),
- wp54_gpio_buttons);
- adm5120_add_device_gpio_leds(ARRAY_SIZE(wp54_gpio_leds),
- wp54_gpio_leds);
-
- adm5120_pci_set_irq_map(ARRAY_SIZE(wp54_pci_irqs), wp54_pci_irqs);
-}
-
-MIPS_MACHINE(MACH_ADM5120_WP54, "WP54", "Compex WP54 family", wp54_setup);
-
-static void __init wp54_wrt_setup(void)
-{
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(wp54g_wrt_partitions);
- adm5120_flash0_data.parts = wp54g_wrt_partitions;
-
- wp54_setup();
-}
-
-MIPS_MACHINE(MACH_ADM5120_WP54G_WRT, "WP54G-WRT", "Compex WP54G-WRT",
- wp54_wrt_setup);
+++ /dev/null
-obj-y := br-61xx.o
-
-obj-$(CONFIG_ADM5120_MACH_BR_6104K) += br-6104k.o
-obj-$(CONFIG_ADM5120_MACH_BR_6104KP) += br-6104kp.o
-obj-$(CONFIG_ADM5120_MACH_BR_61X4WG) += br-61x4wg.o
+++ /dev/null
-/*
- * Edimax BR-6104K board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "br-61xx.h"
-
-static struct gpio_led br6104k_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL),
-};
-
-static void __init br6104k_setup(void)
-{
- br61xx_generic_setup();
- adm5120_add_device_gpio_leds(ARRAY_SIZE(br6104k_gpio_leds),
- br6104k_gpio_leds);
-}
-
-MIPS_MACHINE(MACH_ADM5120_BR6104K, "BR-6104K", "Edimax BR-6104K",
- br6104k_setup);
+++ /dev/null
-/*
- * Edimax BR-6104KP board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "br-61xx.h"
-
-static struct gpio_led br6104kp_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN3, "usb1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_PIN1, "usb2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL),
-};
-
-static void __init br6104kp_setup(void)
-{
- br61xx_generic_setup();
- adm5120_add_device_gpio_leds(ARRAY_SIZE(br6104kp_gpio_leds),
- br6104kp_gpio_leds);
- adm5120_add_device_usb();
-}
-
-MIPS_MACHINE(MACH_ADM5120_BR6104KP, "BR-6104KP", "Edimax BR-6104KP",
- br6104kp_setup);
+++ /dev/null
-/*
- * Edimax BR-6104Wg/6114WG board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "br-61xx.h"
-
-static struct adm5120_pci_irq br61x4wg_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
-};
-
-static struct gpio_led br61x4wg_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL),
- GPIO_LED_STD(ADM5120_GPIO_PIN5, "wlan", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL),
-};
-
-static void __init br61x4wg_setup(void)
-{
- br61xx_generic_setup();
- adm5120_add_device_gpio_leds(ARRAY_SIZE(br61x4wg_gpio_leds),
- br61x4wg_gpio_leds);
- adm5120_pci_set_irq_map(ARRAY_SIZE(br61x4wg_pci_irqs),
- br61x4wg_pci_irqs);
-}
-
-MIPS_MACHINE(MACH_ADM5120_BR61X4WG, "BR-6104WG", "Edimax BR-6104WG/6114WG",
- br61x4wg_setup);
+++ /dev/null
-/*
- * Edimax BR-61xx support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "br-61xx.h"
-
-#include <prom/admboot.h>
-
-#define BR61XX_CONFIG_OFFSET 0x8000
-#define BR61XX_CONFIG_SIZE 0x1000
-
-#define BR61XX_KEYS_POLL_INTERVAL 20
-#define BR61XX_KEYS_DEBOUNCE_INTERVAL (3 * BR61XX_KEYS_POLL_INTERVAL)
-
-static struct mtd_partition br61xx_partitions[] = {
- {
- .name = "admboot",
- .offset = 0,
- .size = 32*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "config",
- .offset = MTDPART_OFS_APPEND,
- .size = 32*1024,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct gpio_keys_button br61xx_gpio_buttons[] __initdata = {
- {
- .desc = "reset_button",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = BR61XX_KEYS_DEBOUNCE_INTERVAL,
- .gpio = ADM5120_GPIO_PIN2,
- }
-};
-
-static u8 br61xx_vlans[6] __initdata = {
- 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
-};
-
-static void __init br61xx_mac_setup(void)
-{
- u8 mac_base[6];
- int err;
-
- err = admboot_get_mac_base(BR61XX_CONFIG_OFFSET,
- BR61XX_CONFIG_SIZE, mac_base);
-
- if ((err) || !is_valid_ether_addr(mac_base))
- random_ether_addr(mac_base);
-
- adm5120_setup_eth_macs(mac_base);
-}
-
-void __init br61xx_generic_setup(void)
-{
-
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(br61xx_partitions);
- adm5120_flash0_data.parts = br61xx_partitions;
- adm5120_add_device_flash(0);
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_add_device_switch(5, br61xx_vlans);
-
- adm5120_register_gpio_buttons(-1, BR61XX_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(br61xx_gpio_buttons),
- br61xx_gpio_buttons);
-
- br61xx_mac_setup();
-}
+++ /dev/null
-/*
- * Edimax BR-61xx board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/mips_machine.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-extern void __init br61xx_generic_setup(void) __init;
+++ /dev/null
-obj-$(CONFIG_ADM5120_MACH_EB_214A) += eb-214a.o
+++ /dev/null
-/*
- * EB-214A board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2010 Cezary Jackiewicz <cezary@eko.one.pl>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/mips_machine.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-
-
-#define EB214A_CONFIG_OFFSET 0x4000
-
-#define EB214A_KEYS_POLL_INTERVAL 20
-#define EB214A_KEYS_DEBOUNCE_INTERVAL (3 * EB214A_KEYS_POLL_INTERVAL)
-
-static struct mtd_partition eb214a_partitions[] = {
- {
- .name = "bootloader",
- .offset = 0,
- .size = 32*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "config",
- .offset = MTDPART_OFS_APPEND,
- .size = 32*1024,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct adm5120_pci_irq eb214a_pci_irqs[] __initdata = {
- PCIIRQ(4, 0, 1, ADM5120_IRQ_PCI0),
- PCIIRQ(4, 1, 2, ADM5120_IRQ_PCI0),
- PCIIRQ(4, 2, 3, ADM5120_IRQ_PCI0),
-};
-
-static struct gpio_led eb214a_gpio_leds[] __initdata = {
- GPIO_LED_INV(ADM5120_GPIO_PIN7, "power", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "usb1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L1, "usb2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L2, "usb3", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "usb4", NULL),
-};
-
-static struct gpio_keys_button eb214a_gpio_buttons[] __initdata = {
- {
- .desc = "reset",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = EB214A_KEYS_DEBOUNCE_INTERVAL,
- .gpio = ADM5120_GPIO_PIN1,
- }
-};
-
-static u8 eb214a_vlans[6] __initdata = {
- 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
-};
-
-static void __init eb214a_mac_setup(void)
-{
- u8 mac_base[6];
- u8 *cfg;
- int i;
-
- cfg = (u8 *) KSEG1ADDR(ADM5120_SRAM0_BASE + EB214A_CONFIG_OFFSET);
- for (i = 0; i < 6; i++)
- mac_base[i] = cfg[i];
-
- if (!is_valid_ether_addr(mac_base))
- random_ether_addr(mac_base);
-
- adm5120_setup_eth_macs(mac_base);
-}
-
-static void __init eb214a_setup(void)
-{
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(eb214a_partitions);
- adm5120_flash0_data.parts = eb214a_partitions;
- adm5120_add_device_flash(0);
-
- adm5120_add_device_uart(0);
- /* adm5120_add_device_uart(1); */
-
- adm5120_add_device_switch(5, eb214a_vlans);
-
- eb214a_mac_setup();
-
- adm5120_register_gpio_buttons(-1, EB214A_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(eb214a_gpio_buttons),
- eb214a_gpio_buttons);
-
- adm5120_add_device_gpio_leds(ARRAY_SIZE(eb214a_gpio_leds),
- eb214a_gpio_leds);
-
- adm5120_pci_set_irq_map(ARRAY_SIZE(eb214a_pci_irqs),
- eb214a_pci_irqs);
- /* adm5120_add_device_usb(); */
-}
-
-MIPS_MACHINE(MACH_ADM5120_EB_214A, "EB-214A", "Generic EB-214A", eb214a_setup);
+++ /dev/null
-obj-y += infineon.o
-
-obj-$(CONFIG_ADM5120_MACH_EASY5120_RT) += easy5120-rt.o
-obj-$(CONFIG_ADM5120_MACH_EASY5120_WVOIP) += easy5120-wvoip.o
-obj-$(CONFIG_ADM5120_MACH_EASY5120P_ATA) += easy5120p-ata.o
-obj-$(CONFIG_ADM5120_MACH_EASY83000) += easy83000.o
+++ /dev/null
-/*
- * Infineon EASY 5120-RT Reference Board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "infineon.h"
-
-static struct gpio_led easy5120_rt_gpio_leds[] __initdata = {
- GPIO_LED_INV(ADM5120_GPIO_PIN6, "user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan0_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan0_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL),
-};
-
-static struct adm5120_pci_irq easy5120_rt_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
-};
-
-static u8 easy5120_rt_vlans[6] __initdata = {
- 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
-};
-
-static void __init easy5120_rt_setup(void)
-{
- easy_setup_bga();
-
- adm5120_add_device_switch(5, easy5120_rt_vlans);
- adm5120_add_device_usb();
- adm5120_add_device_gpio_leds(ARRAY_SIZE(easy5120_rt_gpio_leds),
- easy5120_rt_gpio_leds);
- adm5120_pci_set_irq_map(ARRAY_SIZE(easy5120_rt_pci_irqs),
- easy5120_rt_pci_irqs);
-}
-
-MIPS_MACHINE(MACH_ADM5120_EASY5120RT, "EASY5120-RT",
- "Infineon EASY 5120-RT Reference Board", easy5120_rt_setup);
+++ /dev/null
-/*
- * Infineon EASY 5120-WVoIP Reference Board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "infineon.h"
-
-static void __init easy5120wvoip_setup(void)
-{
- easy_setup_bga();
- adm5120_add_device_switch(6, NULL);
-
- /* TODO: add VINETIC2 device */
- /* TODO: setup PCI IRQ map */
-}
-
-MIPS_MACHINE(MACH_ADM5120_EASY5120WVOIP, "EASY5120WVoIP",
- "Infineon EASY 5120-WVoIP Reference Board", easy5120wvoip_setup);
+++ /dev/null
-/*
- * Infineon EASY 5120P-ATA Reference Board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "infineon.h"
-
-static void __init easy5120pata_setup(void)
-{
- easy_setup_pqfp();
-
- adm5120_add_device_switch(6, NULL);
-}
-
-MIPS_MACHINE(MACH_ADM5120_EASY5120PATA, "EASY5120P-ATA",
- "Infineon EASY 5120P-ATA Reference Board", easy5120pata_setup);
+++ /dev/null
-/*
- * Infineon EASY 83000 Reference Board support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "infineon.h"
-
-static void __init easy83000_setup(void)
-{
- easy_setup_pqfp();
- adm5120_add_device_switch(6, NULL);
-
- /* TODO: add VINAX device */
-}
-
-MIPS_MACHINE(MACH_ADM5120_EASY83000, "EASY8300",
- "Infineon EASY 83000 Reference Board", easy83000_setup);
+++ /dev/null
-/*
- * Infineon Reference Boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "infineon.h"
-
-#include <prom/admboot.h>
-
-#define EASY_CONFIG_OFFSET 0x10000
-#define EASY_CONFIG_SIZE 0x1000
-
-static struct mtd_partition easy_partitions[] = {
- {
- .name = "admboot",
- .offset = 0,
- .size = 64*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "boardcfg",
- .offset = MTDPART_OFS_APPEND,
- .size = 64*1024,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static __init void easy_setup_mac(void)
-{
- u8 mac_base[6];
- int err;
-
- err = admboot_get_mac_base(EASY_CONFIG_OFFSET,
- EASY_CONFIG_SIZE, mac_base);
-
- if ((err) || !is_valid_ether_addr(mac_base))
- random_ether_addr(mac_base);
-
- adm5120_setup_eth_macs(mac_base);
-}
-
-static void switch_bank_gpio3(unsigned bank)
-{
- switch (bank) {
- case 0:
- gpio_set_value(ADM5120_GPIO_PIN3, 0);
- break;
- case 1:
- gpio_set_value(ADM5120_GPIO_PIN3, 1);
- break;
- }
-}
-
-void __init easy_setup_pqfp(void)
-{
- /* setup flash A20 line */
- gpio_request(ADM5120_GPIO_PIN3, NULL);
- gpio_direction_output(ADM5120_GPIO_PIN3, 0);
- adm5120_flash0_data.switch_bank = switch_bank_gpio3;
-
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(easy_partitions);
- adm5120_flash0_data.parts = easy_partitions;
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_add_device_flash(0);
-
- easy_setup_mac();
-}
-
-static void switch_bank_gpio5(unsigned bank)
-{
- switch (bank) {
- case 0:
- gpio_set_value(ADM5120_GPIO_PIN5, 0);
- break;
- case 1:
- gpio_set_value(ADM5120_GPIO_PIN5, 1);
- break;
- }
-}
-
-void __init easy_setup_bga(void)
-{
- /* setup flash A20 line */
- gpio_request(ADM5120_GPIO_PIN5, NULL);
- gpio_direction_output(ADM5120_GPIO_PIN5, 0);
- adm5120_flash0_data.switch_bank = switch_bank_gpio5;
-
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(easy_partitions);
- adm5120_flash0_data.parts = easy_partitions;
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_add_device_flash(0);
-
- easy_setup_mac();
-}
+++ /dev/null
-/*
- * Infineon Reference Boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/mips_machine.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-
-extern void easy_setup_pqfp(void) __init;
-extern void easy_setup_bga(void) __init;
+++ /dev/null
-obj-y += rb-1xx.o
-
-obj-${CONFIG_ADM5120_MACH_RB_11X} += rb-11x.o
-obj-${CONFIG_ADM5120_MACH_RB_133} += rb-133.o
-obj-${CONFIG_ADM5120_MACH_RB_133C} += rb-133c.o
-obj-${CONFIG_ADM5120_MACH_RB_150} += rb-150.o
-obj-${CONFIG_ADM5120_MACH_RB_153} += rb-153.o
-obj-${CONFIG_ADM5120_MACH_RB_192} += rb-192.o
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 111/112 support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-static struct gpio_led rb11x_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN3, "user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan_lnkact", NULL),
-};
-
-static u8 rb11x_vlans[6] __initdata = {
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static void __init rb11x_setup(void)
-{
- rb1xx_generic_setup();
- rb1xx_add_device_nand();
-
- adm5120_add_device_switch(1, rb11x_vlans);
- adm5120_add_device_gpio_leds(ARRAY_SIZE(rb11x_gpio_leds),
- rb11x_gpio_leds);
-}
-
-MIPS_MACHINE(MACH_ADM5120_RB_11X, "11x", "Mikrotik RouterBOARD 111/112",
- rb11x_setup);
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 133 support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-static struct gpio_led rb133_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN6, "power", NULL),
- GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan1_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan1_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan2_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan2_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan3_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan3_lnkact", NULL),
-};
-
-static u8 rb133_vlans[6] __initdata = {
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static void __init rb133_setup(void)
-{
- rb1xx_generic_setup();
- rb1xx_add_device_nand();
-
- adm5120_add_device_switch(3, rb133_vlans);
- adm5120_add_device_gpio_leds(ARRAY_SIZE(rb133_gpio_leds),
- rb133_gpio_leds);
-}
-
-MIPS_MACHINE(MACH_ADM5120_RB_133, "133", "Mikrotik RouterBOARD 133",
- rb133_setup);
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 133C support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-static struct gpio_led rb133c_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN6, "power", NULL),
- GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan1_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan1_lnkact", NULL),
-};
-
-static u8 rb133c_vlans[6] __initdata = {
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static void __init rb133c_setup(void)
-{
- rb1xx_generic_setup();
- rb1xx_add_device_nand();
-
- adm5120_add_device_switch(1, rb133c_vlans);
- adm5120_add_device_gpio_leds(ARRAY_SIZE(rb133c_gpio_leds),
- rb133c_gpio_leds);
-}
-
-MIPS_MACHINE(MACH_ADM5120_RB_133C, "133C", "Mikrotik RouterBOARD 133C",
- rb133c_setup);
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 150 support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-#define RB150_NAND_BASE 0x1FC80000
-#define RB150_NAND_SIZE 1
-
-#define RB150_GPIO_NAND_READY ADM5120_GPIO_PIN0
-#define RB150_GPIO_NAND_NCE ADM5120_GPIO_PIN1
-#define RB150_GPIO_NAND_CLE ADM5120_GPIO_P2L2
-#define RB150_GPIO_NAND_ALE ADM5120_GPIO_P3L2
-#define RB150_GPIO_RESET_BUTTON ADM5120_GPIO_PIN1 /* FIXME */
-
-#define RB150_NAND_DELAY 100
-
-#define RB150_NAND_WRITE(v) \
- writeb((v), (void __iomem *)KSEG1ADDR(RB150_NAND_BASE))
-
-static struct resource rb150_nand_resources[] __initdata = {
- [0] = {
- .start = RB150_NAND_BASE,
- .end = RB150_NAND_BASE + RB150_NAND_SIZE-1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct gpio_led rb150_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_P0L2, "user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan1_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan5_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan5_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan4_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan4_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_led2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan2_led1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan2_led2", NULL),
-};
-
-static u8 rb150_vlans[6] __initdata = {
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static int rb150_nand_dev_ready(struct mtd_info *mtd)
-{
- return gpio_get_value(RB150_GPIO_NAND_READY);
-}
-
-static void rb150_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- if (ctrl & NAND_CTRL_CHANGE) {
- gpio_set_value(RB150_GPIO_NAND_CLE, (ctrl & NAND_CLE) ? 1 : 0);
- gpio_set_value(RB150_GPIO_NAND_ALE, (ctrl & NAND_ALE) ? 1 : 0);
- gpio_set_value(RB150_GPIO_NAND_NCE, (ctrl & NAND_NCE) ? 0 : 1);
- }
-
- udelay(RB150_NAND_DELAY);
-
- if (cmd != NAND_CMD_NONE)
- RB150_NAND_WRITE(cmd);
-}
-
-static void __init rb150_add_device_nand(void)
-{
- struct platform_device *pdev;
- int err;
-
- /* setup GPIO pins for NAND flash chip */
- gpio_request(RB150_GPIO_NAND_READY, "nand-ready");
- gpio_direction_input(RB150_GPIO_NAND_READY);
- gpio_request(RB150_GPIO_NAND_NCE, "nand-nce");
- gpio_direction_output(RB150_GPIO_NAND_NCE, 1);
- gpio_request(RB150_GPIO_NAND_CLE, "nand-cle");
- gpio_direction_output(RB150_GPIO_NAND_CLE, 0);
- gpio_request(RB150_GPIO_NAND_ALE, "nand-ale");
- gpio_direction_output(RB150_GPIO_NAND_ALE, 0);
-
- pdev = platform_device_alloc("gen_nand", -1);
- if (!pdev)
- goto err_out;
-
- err = platform_device_add_resources(pdev, rb150_nand_resources,
- ARRAY_SIZE(rb150_nand_resources));
- if (err)
- goto err_put;
-
-
- rb1xx_nand_data.ctrl.cmd_ctrl = rb150_nand_cmd_ctrl;
- rb1xx_nand_data.ctrl.dev_ready = rb150_nand_dev_ready;
-
- err = platform_device_add_data(pdev, &rb1xx_nand_data,
- sizeof(rb1xx_nand_data));
- if (err)
- goto err_put;
-
- err = platform_device_add(pdev);
- if (err)
- goto err_put;
-
- return;
-
-err_put:
- platform_device_put(pdev);
-err_out:
- return;
-}
-
-static void __init rb150_setup(void)
-{
- rb1xx_gpio_buttons[0].gpio = RB150_GPIO_RESET_BUTTON;
- rb1xx_generic_setup();
- rb150_add_device_nand();
-
- adm5120_add_device_gpio_leds(ARRAY_SIZE(rb150_gpio_leds),
- rb150_gpio_leds);
- adm5120_add_device_switch(5, rb150_vlans);
-}
-
-MIPS_MACHINE(MACH_ADM5120_RB_150, "miniROUTER", "Mikrotik RouterBOARD 150",
- rb150_setup);
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 153 support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-static struct resource rb153_cf_resources[] __initdata = {
- {
- .name = "cf_membase",
- .start = ADM5120_EXTIO1_BASE,
- .end = ADM5120_EXTIO1_BASE + ADM5120_EXTIO1_SIZE-1 ,
- .flags = IORESOURCE_MEM
- }, {
- .name = "cf_irq",
- .start = ADM5120_IRQ_GPIO4,
- .end = ADM5120_IRQ_GPIO4,
- .flags = IORESOURCE_IRQ
- }
-};
-
-static struct gpio_led rb153_gpio_leds[] __initdata = {
- GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan1_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan5_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan5_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan4_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan4_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan2_speed", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan2_lnkact", NULL),
-};
-
-static u8 rb153_vlans[6] __initdata = {
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static void __init rb153_add_device_cf(void)
-{
- /* enable CSX1:INTX1 on GPIO[3:4] for the CF slot */
- adm5120_gpio_csx1_enable();
-
- /* enable the wait state pin GPIO[0] for external I/O control */
- adm5120_gpio_ew_enable();
-
- platform_device_register_simple("pata-rb153-cf", -1,
- rb153_cf_resources, ARRAY_SIZE(rb153_cf_resources));
-}
-
-static void __init rb153_setup(void)
-{
- rb1xx_generic_setup();
- rb1xx_add_device_nand();
- rb153_add_device_cf();
-
- adm5120_add_device_gpio_leds(ARRAY_SIZE(rb153_gpio_leds),
- rb153_gpio_leds);
- adm5120_add_device_switch(5, rb153_vlans);
-}
-
-MIPS_MACHINE(MACH_ADM5120_RB_153, "150", "Mikrotik RouterBOARD 153",
- rb153_setup);
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 192 support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-static u8 rb192_vlans[6] __initdata = {
- 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static void __init rb192_setup(void)
-{
- rb1xx_generic_setup();
- rb1xx_add_device_nand();
-
- adm5120_add_device_switch(6, rb192_vlans);
-}
-
-MIPS_MACHINE(MACH_ADM5120_RB_192, "192", "Mikrotik RouterBOARD 192",
- rb192_setup);
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 1xx series support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * NAND initialization code was based on a driver for Linux 2.6.19+ which
- * was derived from the driver for Linux 2.4.xx published by Mikrotik for
- * their RouterBoard 1xx and 5xx series boards.
- * Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk>
- * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "rb-1xx.h"
-
-#define RB1XX_NAND_CHIP_DELAY 25
-
-#define RB1XX_KEYS_POLL_INTERVAL 20
-#define RB1XX_KEYS_DEBOUNCE_INTERVAL (3 * RB1XX_KEYS_POLL_INTERVAL)
-
-static struct adm5120_pci_irq rb1xx_pci_irqs[] __initdata = {
- PCIIRQ(1, 0, 1, ADM5120_IRQ_PCI0),
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI1),
- PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI2)
-};
-
-static struct mtd_partition rb1xx_nor_parts[] = {
- {
- .name = "booter",
- .offset = 0,
- .size = 64*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct mtd_partition rb1xx_nand_parts[] = {
- {
- .name = "kernel",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- } , {
- .name = "rootfs",
- .offset = MTDPART_OFS_NXTBLK,
- .size = MTDPART_SIZ_FULL
- }
-};
-
-/*
- * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
- * will not be able to find the kernel that we load. So set the oobinfo
- * when creating the partitions
- */
-static struct nand_ecclayout rb1xx_nand_ecclayout = {
- .eccbytes = 6,
- .eccpos = { 8, 9, 10, 13, 14, 15 },
- .oobavail = 9,
- .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
-};
-
-/*--------------------------------------------------------------------------*/
-
-static int rb1xx_nand_fixup(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
-
- if (mtd->writesize == 512)
- chip->ecc.layout = &rb1xx_nand_ecclayout;
-
- return 0;
-}
-
-struct platform_nand_data rb1xx_nand_data __initdata = {
- .chip = {
- .nr_chips = 1,
- .nr_partitions = ARRAY_SIZE(rb1xx_nand_parts),
- .partitions = rb1xx_nand_parts,
- .chip_delay = RB1XX_NAND_CHIP_DELAY,
- .chip_fixup = rb1xx_nand_fixup,
- },
-};
-
-struct gpio_keys_button rb1xx_gpio_buttons[] __initdata = {
- {
- .desc = "reset_button",
- .type = EV_KEY,
- .code = KEY_RESTART,
- .debounce_interval = RB1XX_KEYS_DEBOUNCE_INTERVAL,
- .gpio = ADM5120_GPIO_PIN7,
- }
-};
-
-static void __init rb1xx_mac_setup(void)
-{
- if (rb_hs.mac_base != NULL && is_valid_ether_addr(rb_hs.mac_base)) {
- adm5120_setup_eth_macs(rb_hs.mac_base);
- } else {
- u8 mac[ETH_ALEN];
-
- random_ether_addr(mac);
- adm5120_setup_eth_macs(mac);
- }
-}
-
-void __init rb1xx_add_device_flash(void)
-{
- /* setup data for flash0 device */
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(rb1xx_nor_parts);
- adm5120_flash0_data.parts = rb1xx_nor_parts;
- adm5120_flash0_data.window_size = 128*1024;
-
- adm5120_add_device_flash(0);
-}
-
-void __init rb1xx_add_device_nand(void)
-{
- /* enable NAND flash interface */
- adm5120_nand_enable();
-
- /* initialize NAND chip */
- adm5120_nand_set_spn(1);
- adm5120_nand_set_wpn(0);
-
- adm5120_add_device_nand(&rb1xx_nand_data);
-}
-
-void __init rb1xx_generic_setup(void)
-{
- if (adm5120_package_bga())
- adm5120_pci_set_irq_map(ARRAY_SIZE(rb1xx_pci_irqs),
- rb1xx_pci_irqs);
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_register_gpio_buttons(-1, RB1XX_KEYS_POLL_INTERVAL,
- ARRAY_SIZE(rb1xx_gpio_buttons),
- rb1xx_gpio_buttons);
-
- rb1xx_add_device_flash();
- rb1xx_mac_setup();
-}
+++ /dev/null
-/*
- * Mikrotik RouterBOARD 1xx series support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/mips_machine.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_nand.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-
-#include <prom/routerboot.h>
-
-extern struct platform_nand_data rb1xx_nand_data __initdata;
-extern struct gpio_keys_button rb1xx_gpio_buttons[] __initdata;
-
-extern void rb1xx_add_device_flash(void) __init;
-extern void rb1xx_add_device_nand(void) __init;
-extern void rb1xx_generic_setup(void) __init;
+++ /dev/null
-obj-$(CONFIG_ADM5120_MACH_PMUGW) += pmugw.o
+++ /dev/null
-/*
- * Motorola Powerline MU Gateway board
- *
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/mips_machine.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-
-#include <prom/admboot.h>
-
-#define PMUGW_CONFIG_OFFSET 0x10000
-#define PMUGW_CONFIG_SIZE 0x1000
-
-static struct mtd_partition pmugw_partitions[] = {
- {
- .name = "admboot",
- .offset = 0,
- .size = 64*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "boardcfg",
- .offset = MTDPART_OFS_APPEND,
- .size = 64*1024,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static u8 pmugw_vlans[6] __initdata = {
- 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
-};
-
-static __init void pmugw_setup_mac(void)
-{
- u8 mac_base[6];
- int err;
-
- err = admboot_get_mac_base(PMUGW_CONFIG_OFFSET,
- PMUGW_CONFIG_SIZE, mac_base);
-
- if ((err) || !is_valid_ether_addr(mac_base))
- random_ether_addr(mac_base);
-
- adm5120_setup_eth_macs(mac_base);
-}
-
-static void switch_bank_gpio5(unsigned bank)
-{
- switch (bank) {
- case 0:
- gpio_set_value(ADM5120_GPIO_PIN5, 0);
- break;
- case 1:
- gpio_set_value(ADM5120_GPIO_PIN5, 1);
- break;
- }
-}
-
-void __init pmugw_setup(void)
-{
- /* setup flash A20 line */
- gpio_request(ADM5120_GPIO_PIN5, NULL);
- gpio_direction_output(ADM5120_GPIO_PIN5, 0);
- adm5120_flash0_data.switch_bank = switch_bank_gpio5;
-
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(pmugw_partitions);
- adm5120_flash0_data.parts = pmugw_partitions;
-
- adm5120_add_device_uart(1); /* ttyAM0 */
- adm5120_add_device_uart(0); /* ttyAM1 */
-
- adm5120_add_device_flash(0);
-
- pmugw_setup_mac();
- adm5120_add_device_switch(5, pmugw_vlans);
-}
-
-MIPS_MACHINE(MACH_ADM5120_PMUGW, "PMUGW", "Motorola Powerline MU Gateway",
- pmugw_setup);
+++ /dev/null
-/*
- * OSBRiDGE 5GXi/5XLi board support
- *
- * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/etherdevice.h>
-
-#include <asm/mips_machine.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-
-static struct mtd_partition osbridge_5gxi_partitions[] = {
- {
- .name = "bootloader",
- .offset = 0,
- .size = 64*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "boardcfg",
- .offset = 64*1024,
- .size = 64*1024,
- } , {
- .name = "firmware",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct gpio_led osbridge_5gxi_gpio_leds[] __initdata = {
- GPIO_LED_INV(ADM5120_GPIO_PIN6, "5gxi:green:user", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "5gxi:yellow:lan", NULL),
-};
-
-static struct adm5120_pci_irq osbridge_5gxi_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
-};
-
-static u8 osbridge_5gxi_vlans[6] __initdata = {
- 0x41, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static void __init osbridge_5gxi_setup(void)
-{
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(osbridge_5gxi_partitions);
- adm5120_flash0_data.parts = osbridge_5gxi_partitions;
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_add_device_flash(0);
-
- adm5120_add_device_switch(1, osbridge_5gxi_vlans);
- adm5120_add_device_gpio_leds(ARRAY_SIZE(osbridge_5gxi_gpio_leds),
- osbridge_5gxi_gpio_leds);
- adm5120_pci_set_irq_map(ARRAY_SIZE(osbridge_5gxi_pci_irqs),
- osbridge_5gxi_pci_irqs);
-}
-
-MIPS_MACHINE(MACH_ADM5120_5GXI, "5GXi", "OSBRiDGE 5GXi/5XLi board",
- osbridge_5gxi_setup);
+++ /dev/null
-obj-$(CONFIG_ADM5120_MACH_5GXI) += 5gxi.o
+++ /dev/null
-#
-# Makefile for the ADMtek ADM5120 SoC specific parts of the kernel
-#
-
-lib-y += admboot.o
-lib-y += bootbase.o
-lib-y += cfe.o
-lib-y += generic.o
-lib-y += myloader.o
-lib-y += routerboot.o
+++ /dev/null
-/*
- * ADMBoot specific prom routines
- *
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <prom/admboot.h>
-#include "prom_read.h"
-
-#define ADMBOOT_MAGIC_MAC_BASE 0x636D676D /* 'mgmc' */
-#define ADMBOOT_MAGIC_MAC_BASE_BR6104XX 0x31305348 /* 'HS01' */
-
-int __init admboot_get_mac_base(u32 offset, u32 len, u8 *mac)
-{
- u8 *cfg;
- int i;
-
- cfg = (u8 *) KSEG1ADDR(ADM5120_SRAM0_BASE + offset);
- for (i = 0; i < len; i += 4) {
- u32 magic;
-
- magic = prom_read_le32(cfg + i);
- if (magic == ADMBOOT_MAGIC_MAC_BASE) {
- int j;
-
- for (j = 0; j < 6; j++)
- mac[j] = cfg[i + 4 + j];
-
- return 0;
- }
- if (magic == ADMBOOT_MAGIC_MAC_BASE_BR6104XX) {
- int j;
-
- for (j = 0; j < 6; j++)
- mac[j] = cfg[i + 7 + j];
-
- return 0;
- }
- }
-
- return -ENXIO;
-}
+++ /dev/null
-/*
- * ZyXEL's Bootbase specific prom routines
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <prom/zynos.h>
-#include "prom_read.h"
-
-#define ZYNOS_INFO_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x3F90)
-#define ZYNOS_HDBG_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x4000)
-#define BOOTEXT_ADDR_MIN KSEG1ADDR(ADM5120_SRAM0_BASE)
-#define BOOTEXT_ADDR_MAX (BOOTEXT_ADDR_MIN + (2*1024*1024))
-
-static int bootbase_found;
-static struct zynos_board_info *board_info;
-
-struct bootbase_info bootbase_info;
-
-static inline int bootbase_dbgarea_present(u8 *data)
-{
- u32 t;
-
- t = prom_read_be32(data+5);
- if (t != ZYNOS_MAGIC_DBGAREA1)
- return 0;
-
- t = prom_read_be32(data+9);
- if (t != ZYNOS_MAGIC_DBGAREA2)
- return 0;
-
- return 1;
-}
-
-static inline u32 bootbase_get_bootext_addr(void)
-{
- return prom_read_be32(&board_info->bootext_addr);
-}
-
-static inline void bootbase_get_mac(u8 *mac)
-{
- int i;
-
- for (i = 0; i < 6; i++)
- mac[i] = board_info->mac[i];
-}
-
-static inline u16 bootbase_get_vendor_id(void)
-{
-#define CHECK_VENDOR(n) (strnicmp(board_info->vendor, (n), strlen(n)) == 0)
- unsigned char vendor[ZYNOS_NAME_LEN];
- int i;
-
- for (i = 0; i < ZYNOS_NAME_LEN; i++)
- vendor[i] = board_info->vendor[i];
-
- if CHECK_VENDOR(ZYNOS_VENDOR_ZYXEL)
- return ZYNOS_VENDOR_ID_ZYXEL;
-
- if CHECK_VENDOR(ZYNOS_VENDOR_DLINK)
- return ZYNOS_VENDOR_ID_DLINK;
-
- if CHECK_VENDOR(ZYNOS_VENDOR_LUCENT)
- return ZYNOS_VENDOR_ID_LUCENT;
-
- if CHECK_VENDOR(ZYNOS_VENDOR_NETGEAR)
- return ZYNOS_VENDOR_ID_NETGEAR;
-
- return ZYNOS_VENDOR_ID_OTHER;
-}
-
-static inline u16 bootbase_get_board_id(void)
-{
- return prom_read_be16(&board_info->board_id);
-}
-
-int __init bootbase_present(void)
-{
- u32 t;
-
- if (bootbase_found)
- goto out;
-
- /* check presence of the dbgarea */
- if (bootbase_dbgarea_present((u8 *)ZYNOS_HDBG_ADDR) == 0)
- goto out;
-
- board_info = (struct zynos_board_info *)(ZYNOS_INFO_ADDR);
-
- /* check for a valid BootExt address */
- t = bootbase_get_bootext_addr();
- if ((t < BOOTEXT_ADDR_MIN) || (t > BOOTEXT_ADDR_MAX))
- goto out;
-
- bootbase_info.vendor_id = bootbase_get_vendor_id();
- bootbase_info.board_id = bootbase_get_board_id();
- bootbase_get_mac(bootbase_info.mac);
-
- bootbase_found = 1;
-
-out:
- return bootbase_found;
-}
-
+++ /dev/null
-/*
- * Broadcom's CFE specific prom routines
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-
-#include <prom/cfe.h>
-#include "prom_read.h"
-
-/*
- * CFE based boards
- */
-#define CFE_EPTSEAL 0x43464531 /* CFE1 is the magic number to recognize CFE
-from other bootloaders */
-
-static int cfe_found;
-
-static u32 cfe_handle;
-static u32 cfe_entry;
-static u32 cfe_seal;
-
-int __init cfe_present(void)
-{
- /*
- * This method only works, when we are booted directly from the CFE.
- */
- u32 a1 = (u32) fw_arg1;
-
- if (cfe_found)
- return 1;
-
- cfe_handle = (u32) fw_arg0;
- cfe_entry = (u32) fw_arg2;
- cfe_seal = (u32) fw_arg3;
-
- /* Check for CFE by finding the CFE magic number */
- if (cfe_seal != CFE_EPTSEAL)
- return 0;
-
- /* cfe_a1_val must be 0, because only one CPU present in the ADM5120 */
- if (a1 != 0)
- return 0;
-
- /* The cfe_handle, and the cfe_entry must be kernel mode addresses */
- if ((cfe_handle < KSEG0) || (cfe_entry < KSEG0))
- return 0;
-
- cfe_found = 1;
- return 1;
-}
-
-char *cfe_getenv(char *envname)
-{
- if (cfe_found == 0)
- return NULL;
-
- return NULL;
-}
+++ /dev/null
-/*
- * Generic PROM routines
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-
-#include <asm/bootinfo.h>
-
-#include <prom/generic.h>
-
-static int *_prom_argc;
-static char **_prom_argv;
-static char **_prom_envp;
-
-char *generic_prom_getenv(char *envname)
-{
- char **env;
- char *ret;
-
- ret = NULL;
- for (env = _prom_envp; *env != NULL; env++) {
- if (strcmp(envname, *env++) == 0) {
- ret = *env;
- break;
- }
- }
-
- return ret;
-}
-
-int generic_prom_present(void)
-{
- _prom_argc = (int *)fw_arg0;
- _prom_argv = (char **)fw_arg1;
- _prom_envp = (char **)fw_arg2;
-
- return 1;
-}
+++ /dev/null
-/*
- * Compex's MyLoader specific prom routines
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <prom/myloader.h>
-#include "prom_read.h"
-
-#define SYS_PARAMS_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x0F000)
-#define BOARD_PARAMS_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x0F800)
-#define PART_TABLE_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x10000)
-
-static int myloader_found;
-
-struct myloader_info myloader_info;
-
-int __init myloader_present(void)
-{
- struct mylo_system_params *sysp;
- struct mylo_board_params *boardp;
- struct mylo_partition_table *parts;
- int i;
-
- if (myloader_found)
- goto out;
-
- sysp = (struct mylo_system_params *)(SYS_PARAMS_ADDR);
- boardp = (struct mylo_board_params *)(BOARD_PARAMS_ADDR);
- parts = (struct mylo_partition_table *)(PART_TABLE_ADDR);
-
- /* Check for some magic numbers */
- if ((le32_to_cpu(sysp->magic) != MYLO_MAGIC_SYS_PARAMS) ||
- (le32_to_cpu(boardp->magic) != MYLO_MAGIC_BOARD_PARAMS) ||
- (le32_to_cpu(parts->magic) != MYLO_MAGIC_PARTITIONS))
- goto out;
-
- myloader_info.vid = le32_to_cpu(sysp->vid);
- myloader_info.did = le32_to_cpu(sysp->did);
- myloader_info.svid = le32_to_cpu(sysp->svid);
- myloader_info.sdid = le32_to_cpu(sysp->sdid);
-
- for (i = 0; i < MYLO_ETHADDR_COUNT; i++) {
- int j;
- for (j = 0; j < 6; j++)
- myloader_info.macs[i][j] = boardp->addr[i].mac[j];
- }
-
- myloader_found = 1;
-
-out:
- return myloader_found;
-}
+++ /dev/null
-/*
- * Generic prom definitions
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _ADM5120_PROM_H_
-#define _ADM5120_PROM_H_
-
-/*
- * Helper routines
- */
-static inline u16 prom_read_le16(void *buf)
-{
- u8 *p = buf;
-
- return ((u16)p[0] + ((u16)p[1] << 8));
-}
-
-static inline u32 prom_read_le32(void *buf)
-{
- u8 *p = buf;
-
- return ((u32)p[0] + ((u32)p[1] << 8) + ((u32)p[2] << 16) +
- ((u32)p[3] << 24));
-}
-
-static inline u16 prom_read_be16(void *buf)
-{
- u8 *p = buf;
-
- return (((u16)p[0] << 8) + (u16)p[1]);
-}
-
-static inline u32 prom_read_be32(void *buf)
-{
- u8 *p = buf;
-
- return (((u32)p[0] << 24) + ((u32)p[1] << 16) + ((u32)p[2] << 8) +
- ((u32)p[3]));
-}
-
-#endif /* _ADM5120_PROM_H_ */
-
-
+++ /dev/null
-/*
- * Mikrotik's RouterBOOT specific prom routines
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <linux/routerboot.h>
-
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <prom/routerboot.h>
-#include "prom_read.h"
-
-struct rb_hard_settings rb_hs;
-static int rb_found;
-
-static int __init routerboot_load_hs(u8 *buf, u16 buflen)
-{
- u16 id, len;
-
- memset(&rb_hs, 0, sizeof(rb_hs));
-
- if (buflen < 4)
- return -1;
-
- if (prom_read_le32(buf) != RB_MAGIC_HARD)
- return -1;
-
- /* skip magic value */
- buf += 4;
- buflen -= 4;
-
- while (buflen > 2) {
- id = prom_read_le16(buf);
- buf += 2;
- buflen -= 2;
- if (id == RB_ID_TERMINATOR || buflen < 2)
- break;
-
- len = prom_read_le16(buf);
- buf += 2;
- buflen -= 2;
-
- if (buflen < len)
- break;
-
- switch (id) {
- case RB_ID_BIOS_VERSION:
- rb_hs.bios_ver = (char *)buf;
- break;
- case RB_ID_BOARD_NAME:
- rb_hs.name = (char *)buf;
- break;
- case RB_ID_MEMORY_SIZE:
- rb_hs.mem_size = prom_read_le32(buf);
- break;
- case RB_ID_MAC_ADDRESS_COUNT:
- rb_hs.mac_count = prom_read_le32(buf);
- break;
- case RB_ID_MAC_ADDRESS_PACK:
- if ((len / RB_MAC_SIZE) > 0)
- rb_hs.mac_base = buf;
- break;
- }
-
- buf += len;
- buflen -= len;
-
- }
-
- return 0;
-}
-
-#define RB_BS_OFFS 0x14
-#define RB_OFFS_MAX (128*1024)
-
-int __init routerboot_present(void)
-{
- struct rb_bios_settings *bs;
- u8 *base;
- u32 off, len;
-
- if (rb_found)
- goto out;
-
- base = (u8 *)KSEG1ADDR(ADM5120_SRAM0_BASE);
- bs = (struct rb_bios_settings *)(base + RB_BS_OFFS);
-
- off = prom_read_le32(&bs->hs_offs);
- len = prom_read_le32(&bs->hs_size);
- if (off > RB_OFFS_MAX)
- goto out;
-
- if (routerboot_load_hs(base+off, len) != 0)
- goto out;
-
- rb_found = 1;
-
-out:
- return rb_found;
-}
-
-char *routerboot_get_boardname(void)
-{
- if (rb_found == 0)
- return NULL;
-
- return rb_hs.name;
-}
+++ /dev/null
-obj-y += p-33x.o
-
-obj-${CONFIG_ADM5120_MACH_P_334WT} += p-334wt.o
-obj-${CONFIG_ADM5120_MACH_P_335} += p-335.o
\ No newline at end of file
+++ /dev/null
-/*
- * ZyXEL Prestige P-334WT support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "p-33x.h"
-
-static struct gpio_led p334wt_gpio_leds[] __initdata = {
- GPIO_LED_INV(ADM5120_GPIO_PIN2, "power", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan1", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan3", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan4", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P4L2, "wlan", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P2L2, "otist", NULL),
- GPIO_LED_INV(ADM5120_GPIO_P1L2, "hidden", NULL),
-};
-
-static void __init p334wt_setup(void)
-{
- p33x_generic_setup();
- adm5120_add_device_gpio_leds(ARRAY_SIZE(p334wt_gpio_leds),
- p334wt_gpio_leds);
-}
-
-MIPS_MACHINE(MACH_ADM5120_P334WT, "P-334WT", "ZyXEL Prestige 334WT",
- p334wt_setup);
+++ /dev/null
-/*
- * ZyXEL Prestige P-335/335WT support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "p-33x.h"
-
-static void __init p335_setup(void)
-{
- p33x_generic_setup();
- adm5120_add_device_usb();
-}
-
-MIPS_MACHINE(MACH_ADM5120_P335, "P-335", "ZyXEL Prestige 335/335WT",
- p335_setup);
+++ /dev/null
-/*
- * ZyXEL Prestige P-33x boards support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include "p-33x.h"
-
-#include <prom/zynos.h>
-
-#define P33X_GPIO_FLASH_A20 ADM5120_GPIO_PIN5
-static struct mtd_partition p33x_partitions[] = {
- {
- .name = "bootbase",
- .offset = 0,
- .size = 16*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "rom",
- .offset = MTDPART_OFS_APPEND,
- .size = 16*1024,
- .mask_flags = MTD_WRITEABLE,
- } , {
- .name = "bootext1",
- .offset = MTDPART_OFS_APPEND,
- .size = 32*1024,
- } , {
- .name = "bootext2",
- .offset = MTDPART_OFS_APPEND,
- .size = 64*1024,
- } , {
- .name = "trx",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- } , {
- .name = "firmware",
- .offset = 32*1024,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct adm5120_pci_irq p33x_pci_irqs[] __initdata = {
- PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
-};
-
-static u8 p33x_vlans[6] __initdata = {
- /* FIXME: untested */
- 0x50, 0x48, 0x44, 0x42, 0x41, 0x00
-};
-
-static void switch_bank_gpio5(unsigned bank)
-{
- switch (bank) {
- case 0:
- gpio_set_value(P33X_GPIO_FLASH_A20, 0);
- break;
- case 1:
- gpio_set_value(P33X_GPIO_FLASH_A20, 1);
- break;
- }
-}
-
-void __init p33x_generic_setup(void)
-{
- /* setup data for flash0 device */
- gpio_request(P33X_GPIO_FLASH_A20, NULL); /* for flash A20 line */
- gpio_direction_output(P33X_GPIO_FLASH_A20, 0);
- adm5120_flash0_data.switch_bank = switch_bank_gpio5;
- adm5120_flash0_data.nr_parts = ARRAY_SIZE(p33x_partitions);
- adm5120_flash0_data.parts = p33x_partitions;
- adm5120_add_device_flash(0);
-
- adm5120_add_device_uart(0);
- adm5120_add_device_uart(1);
-
- adm5120_setup_eth_macs(bootbase_info.mac);
- adm5120_add_device_switch(6, p33x_vlans);
-
- adm5120_pci_set_irq_map(ARRAY_SIZE(p33x_pci_irqs), p33x_pci_irqs);
-}
+++ /dev/null
-/*
- * ZyXEL Prestige P-33x boards support
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-
-#include <asm/mips_machine.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-extern void p33x_generic_setup(void) __init;
+++ /dev/null
-/*
- * ADM5120 SoC definitions
- *
- * This file defines some constants specific to the ADM5120 SoC
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-#ifndef _ASM_MIPS_MACH_ADM5120_DEFS_H
-#define _ASM_MIPS_MACH_ADM5120_DEFS_H
-
-#define ADM5120_SDRAM0_BASE 0x00000000
-#define ADM5120_SDRAM1_BASE 0x01000000
-#define ADM5120_SRAM1_BASE 0x10000000
-#define ADM5120_EXTIO0_BASE 0x10C00000
-#define ADM5120_EXTIO0_SIZE 0x00200000
-#define ADM5120_EXTIO1_BASE 0x10E00000
-#define ADM5120_EXTIO1_SIZE 0x00200000
-#define ADM5120_MPMC_BASE 0x11000000
-#define ADM5120_MPMC_SIZE 0x00200000
-#define ADM5120_USBC_BASE 0x11200000
-#define ADM5120_USBC_SIZE 0x00200000
-#define ADM5120_PCIMEM_BASE 0x11400000
-#define ADM5120_PCIMEM_SIZE 0x00100000
-#define ADM5120_PCIIO_BASE 0x11500000
-#define ADM5120_PCIIO_SIZE 0x000FFFF0
-#define ADM5120_PCICFG_ADDR 0x115FFFF0
-#define ADM5120_PCICFG_DATA 0x115FFFF8
-#define ADM5120_PCICFG_SIZE 0x00000010
-#define ADM5120_SWITCH_BASE 0x12000000
-#define ADM5120_SWITCH_SIZE 0x00200000
-#define ADM5120_INTC_BASE 0x12200000
-#define ADM5120_INTC_SIZE 0x00200000
-#define ADM5120_UART0_BASE 0x12600000
-#define ADM5120_UART1_BASE 0x12800000
-#define ADM5120_UART_SIZE 0x00200000
-#define ADM5120_SRAM0_BASE 0x1FC00000
-
-#define ADM5120_NAND_BASE ADM5120_SRAM1_BASE
-#define ADM5120_NAND_SIZE 0xB
-
-#define ADM5120_CLK_175 175000000
-#define ADM5120_CLK_200 200000000
-#define ADM5120_CLK_225 225000000
-#define ADM5120_CLK_250 250000000
-
-#define ADM5120_UART_CLOCK 62500000
-
-#endif /* _ASM_MIPS_MACH_ADM5120_DEFS_H */
+++ /dev/null
-/*
- * Copyright (C) 2007-2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MACH_ADM5120_INFO_H
-#define _MACH_ADM5120_INFO_H
-
-#include <linux/types.h>
-
-extern unsigned int adm5120_prom_type;
-#define ADM5120_PROM_GENERIC 0
-#define ADM5120_PROM_CFE 1
-#define ADM5120_PROM_MYLOADER 2
-#define ADM5120_PROM_ROUTERBOOT 3
-#define ADM5120_PROM_BOOTBASE 4
-#define ADM5120_PROM_UBOOT 5
-#define ADM5120_PROM_LAST 5
-
-extern unsigned int adm5120_product_code;
-extern unsigned int adm5120_revision;
-extern unsigned int adm5120_nand_boot;
-
-extern unsigned long adm5120_speed;
-#define ADM5120_SPEED_175 175000000
-#define ADM5120_SPEED_200 200000000
-#define ADM5120_SPEED_225 225000000
-#define ADM5120_SPEED_250 250000000
-
-extern unsigned int adm5120_package;
-#define ADM5120_PACKAGE_PQFP 0
-#define ADM5120_PACKAGE_BGA 1
-
-extern unsigned long adm5120_memsize;
-
-enum {
- MACH_ADM5120_GENERIC = 0, /* Generic board */
- MACH_ADM5120_5GXI, /* OSBRiDGE 5GXi/5XLi */
- MACH_ADM5120_BR6104K, /* Edimax BR-6104K */
- MACH_ADM5120_BR6104KP, /* Edimax BR-6104KP */
- MACH_ADM5120_BR61X4WG, /* Edimax BR-6104Wg/BR-6114WG */
- MACH_ADM5120_CAS630, /* Cellvision CAS-630/630W */
- MACH_ADM5120_CAS670, /* Cellvision CAS-670/670W */
- MACH_ADM5120_CAS700, /* Cellvision CAS-700/700W */
- MACH_ADM5120_CAS771, /* Cellvision CAS-771/771W */
- MACH_ADM5120_CAS790, /* Cellvision CAS-790 */
- MACH_ADM5120_CAS861, /* Cellvision CAS-861/861W */
- MACH_ADM5120_EASY5120PATA, /* Infineon EASY 5120P-ATA */
- MACH_ADM5120_EASY5120RT, /* Infineon EASY 5120-RT */
- MACH_ADM5120_EASY5120WVOIP, /* Infineon EASY 5120-WVoIP */
- MACH_ADM5120_EASY83000, /* Infineon EASY-83000 */
- MACH_ADM5120_ES2108, /* ZyXEL Ethernet Switch 2108 */
- MACH_ADM5120_ES2108F, /* ZyXEL Ethernet Switch 2108-F */
- MACH_ADM5120_ES2108G, /* ZyXEL Ethernet Switch 2108-G */
- MACH_ADM5120_ES2108LC, /* ZyXEL Ethernet Switch 2108-LC */
- MACH_ADM5120_ES2108PWR, /* ZyXEL Ethernet Switch 2108-PWR */
- MACH_ADM5120_ES2024A, /* ZyXEL Ethernet Switch 2024A */
- MACH_ADM5120_ES2024PWR, /* ZyXEL Ethernet Switch 2024PWR */
- MACH_ADM5120_HS100, /* ZyXEL HomeSafe 100/100W */
- MACH_ADM5120_NFS101U, /* Cellvision NFS-101U/101WU */
- MACH_ADM5120_NFS202U, /* Cellvision NFS-202U/202WU */
- MACH_ADM5120_NP28G, /* Compex NP28G */
- MACH_ADM5120_NP28GHS, /* Compex NP28G HotSpot */
- MACH_ADM5120_NP27G, /* Compex NP27G */
- MACH_ADM5120_RB_11X, /* Mikrotik RouterBOARD 111/112 */
- MACH_ADM5120_RB_133, /* Mikrotik RouterBOARD 133 */
- MACH_ADM5120_RB_133C, /* Mikrotik RouterBOARD 133c */
- MACH_ADM5120_RB_150, /* Mikrotik RouterBOARD 150 */
- MACH_ADM5120_RB_153, /* Mikrotik RouterBOARD 153 */
- MACH_ADM5120_RB_192, /* Mikrotik RouterBOARD 192 */
- MACH_ADM5120_P334U, /* ZyXEL Prestige 334U */
- MACH_ADM5120_P334W, /* ZyXEL Prestige 334W */
- MACH_ADM5120_P334WH, /* ZyXEL Prestige 334WH */
- MACH_ADM5120_P334WHD, /* ZyXEL Prestige 334WHD */
- MACH_ADM5120_P334WT, /* ZyXEL Prestige 334WT */
- MACH_ADM5120_P335, /* ZyXEL Prestige 335/335WT */
- MACH_ADM5120_P335PLUS, /* ZyXEL Prestige 335Plus */
- MACH_ADM5120_P335U, /* ZyXEL Prestige 335U */
- MACH_ADM5120_PMUGW, /* Motorola Powerline MU Gateway */
- MACH_ADM5120_WP54, /* Compex WP54G/WP54AG/WPP54G/WPP54AG */
- MACH_ADM5120_WP54G_WRT, /* Compex WP54G-WRT */
- MACH_ADM5120_WP54Gv1C, /* Compex WP54G version 1C */
- MACH_ADM5120_EB_214A, /* Generic EB-214A */
-};
-
-/*
- * TODO:remove adm5120_eth* variables when the switch driver will be
- * converted into a real platform driver
- */
-extern unsigned int adm5120_eth_num_ports;
-extern unsigned char adm5120_eth_macs[6][6];
-extern unsigned char adm5120_eth_vlans[6];
-
-extern void adm5120_soc_init(void) __init;
-extern void adm5120_mem_init(void) __init;
-extern void adm5120_ndelay(u32 ns);
-
-extern void (*adm5120_board_reset)(void);
-
-extern void adm5120_gpio_init(void) __init;
-extern void adm5120_gpio_csx0_enable(void) __init;
-extern void adm5120_gpio_csx1_enable(void) __init;
-extern void adm5120_gpio_ew_enable(void) __init;
-
-static inline int adm5120_package_pqfp(void)
-{
- return (adm5120_package == ADM5120_PACKAGE_PQFP);
-}
-
-static inline int adm5120_package_bga(void)
-{
- return (adm5120_package == ADM5120_PACKAGE_BGA);
-}
-
-static inline int adm5120_has_pci(void)
-{
- return (adm5120_package == ADM5120_PACKAGE_BGA);
-}
-
-static inline int adm5120_has_gmii(void)
-{
- return (adm5120_package == ADM5120_PACKAGE_BGA);
-}
-
-#endif /* _MACH_ADM5120_INFO_H */
+++ /dev/null
-/*
- * ADM5120 interrupt controller definitions
- *
- * This header file defines the hardware registers of the ADM5120 SoC
- * built-in interrupt controller.
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MACH_ADM5120_INTC_H
-#define _MACH_ADM5120_INTC_H
-
-/*
- * INTC register offsets
- */
-#define INTC_REG_IRQ_STATUS 0x00 /* Interrupt status after masking */
-#define INTC_REG_IRQ_RAW_STATUS 0x04 /* Interrupt status before masking */
-#define INTC_REG_IRQ_ENABLE 0x08 /* Used to enable the interrupt sources */
-#define INTC_REG_IRQ_ENABLE_CLEAR 0x0C /* Used to disable the interrupt sources */
-#define INTC_REG_IRQ_DISABLE INTC_REG_IRQ_ENABLE_CLEAR
-#define INTC_REG_INT_MODE 0x14 /* The interrupt mode of the sources */
-#define INTC_REG_FIQ_STATUS 0x18 /* FIQ status */
-#define INTC_REG_IRQ_TEST_SOURCE 0x1C
-#define INTC_REG_IRQ_SOURCE_SELECT 0x20
-#define INTC_REG_INT_LEVEL 0x24
-
-/*
- * INTC IRQ numbers
- */
-#define INTC_IRQ_TIMER 0 /* built in timer */
-#define INTC_IRQ_UART0 1 /* built-in UART0 */
-#define INTC_IRQ_UART1 2 /* built-in UART1 */
-#define INTC_IRQ_USBC 3 /* USB Host Controller */
-#define INTC_IRQ_GPIO2 4 /* GPIO line 2 */
-#define INTC_IRQ_GPIO4 5 /* GPIO line 4 */
-#define INTC_IRQ_PCI0 6 /* PCI slot 2 */
-#define INTC_IRQ_PCI1 7 /* PCI slot 3 */
-#define INTC_IRQ_PCI2 8 /* PCI slot 4 */
-#define INTC_IRQ_SWITCH 9 /* built-in ethernet switch */
-#define INTC_IRQ_LAST INTC_IRQ_SWITCH
-#define INTC_IRQ_COUNT 10
-
-/*
- * INTC register bits
- */
-#define INTC_INT_TIMER (1 << INTC_IRQ_TIMER)
-#define INTC_INT_UART0 (1 << INTC_IRQ_UART0)
-#define INTC_INT_UART1 (1 << INTC_IRQ_UART1)
-#define INTC_INT_USBC (1 << INTC_IRQ_USBC)
-#define INTC_INT_INTX0 (1 << INTC_IRQ_INTX0)
-#define INTC_INT_INTX1 (1 << INTC_IRQ_INTX1)
-#define INTC_INT_PCI0 (1 << INTC_IRQ_PCI0)
-#define INTC_INT_PCI1 (1 << INTC_IRQ_PCI1)
-#define INTC_INT_PCI2 (1 << INTC_IRQ_PCI2)
-#define INTC_INT_SWITCH (1 << INTC_IRQ_SWITCH)
-#define INTC_INT_ALL ((1 << INTC_IRQ_COUNT) - 1)
-
-#endif /* _MACH_ADM5120_INTC_H */
+++ /dev/null
-/*
- * ADM5120 MPMC (Multiport Memory Controller) register definitions
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MACH_ADM5120_MPMC_H
-#define _MACH_ADM5120_MPMC_H
-
-#define MPMC_READ_REG(r) __raw_readl( \
- (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
-#define MPMC_WRITE_REG(r, v) __raw_writel((v), \
- (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
-
-#define MPMC_REG_CTRL 0x0000
-#define MPMC_REG_STATUS 0x0004
-#define MPMC_REG_CONF 0x0008
-#define MPMC_REG_DC 0x0020
-#define MPMC_REG_DR 0x0024
-#define MPMC_REG_DRP 0x0030
-
-#define MPMC_REG_DC0 0x0100
-#define MPMC_REG_DRC0 0x0104
-#define MPMC_REG_DC1 0x0120
-#define MPMC_REG_DRC1 0x0124
-#define MPMC_REG_DC2 0x0140
-#define MPMC_REG_DRC2 0x0144
-#define MPMC_REG_DC3 0x0160
-#define MPMC_REG_DRC3 0x0164
-#define MPMC_REG_SC0 0x0200 /* for F_CS1_N */
-#define MPMC_REG_SC1 0x0220 /* for F_CS0_N */
-#define MPMC_REG_SC2 0x0240
-#define MPMC_REG_WEN2 0x0244
-#define MPMC_REG_OEN2 0x0248
-#define MPMC_REG_RD2 0x024C
-#define MPMC_REG_PG2 0x0250
-#define MPMC_REG_WR2 0x0254
-#define MPMC_REG_TN2 0x0258
-#define MPMC_REG_SC3 0x0260
-
-/* Control register bits */
-#define MPMC_CTRL_AM (1 << 1) /* Address Mirror */
-#define MPMC_CTRL_LPM (1 << 2) /* Low Power Mode */
-#define MPMC_CTRL_DWB (1 << 3) /* Drain Write Buffers */
-
-/* Status register bits */
-#define MPMC_STATUS_BUSY (1 << 0) /* Busy */
-#define MPMC_STATUS_WBS (1 << 1) /* Write Buffer Status */
-#define MPMC_STATUS_SRA (1 << 2) /* Self-Refresh Acknowledge*/
-
-/* Dynamic Control register bits */
-#define MPMC_DC_CE (1 << 0)
-#define MPMC_DC_DMC (1 << 1)
-#define MPMC_DC_SRR (1 << 2)
-#define MPMC_DC_SI_SHIFT 7
-#define MPMC_DC_SI_MASK (3 << 7)
-#define MPMC_DC_SI_NORMAL (0 << 7)
-#define MPMC_DC_SI_MODE (1 << 7)
-#define MPMC_DC_SI_PALL (2 << 7)
-#define MPMC_DC_SI_NOP (3 << 7)
-
-#define SRAM_REG_CONF 0x00
-#define SRAM_REG_WWE 0x04
-#define SRAM_REG_WOE 0x08
-#define SRAM_REG_WRD 0x0C
-#define SRAM_REG_WPG 0x10
-#define SRAM_REG_WWR 0x14
-#define SRAM_REG_WTR 0x18
-
-/* Dynamic Configuration register bits */
-#define DC_BE (1 << 19) /* buffer enable */
-#define DC_RW_SHIFT 28 /* shift for number of rows */
-#define DC_RW_MASK 0x03
-#define DC_NB_SHIFT 26 /* shift for number of banks */
-#define DC_NB_MASK 0x01
-#define DC_CW_SHIFT 22 /* shift for number of columns */
-#define DC_CW_MASK 0x07
-#define DC_DW_SHIFT 7 /* shift for device width */
-#define DC_DW_MASK 0x03
-
-/* Static Configuration register bits */
-#define SC_MW_MASK 0x03 /* memory width mask */
-#define SC_MW_8 0x00 /* 8 bit memory width */
-#define SC_MW_16 0x01 /* 16 bit memory width */
-#define SC_MW_32 0x02 /* 32 bit memory width */
-
-#endif /* _MACH_ADM5120_MPMC_H */
+++ /dev/null
-/*
- * ADM5120 NAND interface definitions
- *
- * This header file defines the hardware registers of the ADM5120 SoC
- * built-in NAND interface.
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * NAND interface routines was based on a driver for Linux 2.6.19+ which
- * was derived from the driver for Linux 2.4.xx published by Mikrotik for
- * their RouterBoard 1xx and 5xx series boards.
- * Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk>
- * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MACH_ADM5120_NAND_H
-#define _MACH_ADM5120_NAND_H
-
-#include <linux/types.h>
-#include <linux/io.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-
-/* NAND control registers */
-#define NAND_REG_DATA 0x0 /* data register */
-#define NAND_REG_SET_CEn 0x1 /* CE# low */
-#define NAND_REG_CLR_CEn 0x2 /* CE# high */
-#define NAND_REG_CLR_CLE 0x3 /* CLE low */
-#define NAND_REG_SET_CLE 0x4 /* CLE high */
-#define NAND_REG_CLR_ALE 0x5 /* ALE low */
-#define NAND_REG_SET_ALE 0x6 /* ALE high */
-#define NAND_REG_SET_SPn 0x7 /* SP# low (use spare area) */
-#define NAND_REG_CLR_SPn 0x8 /* SP# high (do not use spare area) */
-#define NAND_REG_SET_WPn 0x9 /* WP# low */
-#define NAND_REG_CLR_WPn 0xA /* WP# high */
-#define NAND_REG_STATUS 0xB /* Status register */
-
-#define ADM5120_NAND_STATUS_READY 0x80
-
-#define NAND_READ_REG(r) \
- readb((void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
-#define NAND_WRITE_REG(r, v) \
- writeb((v), (void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
-
-/*-------------------------------------------------------------------------*/
-
-static inline void adm5120_nand_enable(void)
-{
- SW_WRITE_REG(SWITCH_REG_BW_CNTL1, BW_CNTL1_NAND_ENABLE);
- SW_WRITE_REG(SWITCH_REG_BOOT_DONE, 1);
-}
-
-static inline void adm5120_nand_set_wpn(unsigned int set)
-{
- NAND_WRITE_REG((set) ? NAND_REG_SET_WPn : NAND_REG_CLR_WPn, 1);
-}
-
-static inline void adm5120_nand_set_spn(unsigned int set)
-{
- NAND_WRITE_REG((set) ? NAND_REG_SET_SPn : NAND_REG_CLR_SPn, 1);
-}
-
-static inline void adm5120_nand_set_cle(unsigned int set)
-{
- NAND_WRITE_REG((set) ? NAND_REG_SET_CLE : NAND_REG_CLR_CLE, 1);
-}
-
-static inline void adm5120_nand_set_ale(unsigned int set)
-{
- NAND_WRITE_REG((set) ? NAND_REG_SET_ALE : NAND_REG_CLR_ALE, 1);
-}
-
-static inline void adm5120_nand_set_cen(unsigned int set)
-{
- NAND_WRITE_REG((set) ? NAND_REG_SET_CEn : NAND_REG_CLR_CEn, 1);
-}
-
-static inline u8 adm5120_nand_get_status(void)
-{
- return NAND_READ_REG(NAND_REG_STATUS);
-}
-
-#endif /* _MACH_ADM5120_NAND_H */
+++ /dev/null
-/*
- * ADM5120 specific platform definitions
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_MIPS_MACH_ADM5120_PLATFORM_H
-#define _ASM_MIPS_MACH_ADM5120_PLATFORM_H
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/leds.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/nand.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/serial.h>
-
-struct adm5120_flash_platform_data {
- void (*set_vpp)(struct map_info *, int);
- void (*switch_bank)(unsigned);
- u32 window_size;
- unsigned int nr_parts;
- struct mtd_partition *parts;
-};
-
-struct adm5120_switch_platform_data {
- /* TODO: not yet implemented */
-};
-
-struct adm5120_pci_irq {
- u8 slot;
- u8 func;
- u8 pin;
- unsigned irq;
-};
-
-#define PCIIRQ(s, f, p, i) {.slot = (s), .func = (f), .pin = (p), .irq = (i)}
-
-#ifdef CONFIG_PCI
-extern void adm5120_pci_set_irq_map(unsigned int nr_irqs,
- struct adm5120_pci_irq *map) __init;
-#else
-static inline void adm5120_pci_set_irq_map(unsigned int nr_irqs,
- struct adm5120_pci_irq *map)
-{
-}
-#endif
-
-extern void adm5120_setup_eth_macs(u8 *mac_base) __init;
-
-extern struct adm5120_flash_platform_data adm5120_flash0_data;
-extern struct adm5120_flash_platform_data adm5120_flash1_data;
-
-extern void adm5120_add_device_flash(unsigned id) __init;
-extern void adm5120_add_device_usb(void) __init;
-extern void adm5120_add_device_uart(unsigned id) __init;
-extern void adm5120_add_device_nand(struct platform_nand_data *pdata) __init;
-extern void adm5120_add_device_switch(unsigned num_ports, u8 *vlan_map) __init;
-extern void adm5120_register_gpio_buttons(int id,
- unsigned poll_interval,
- unsigned nbuttons,
- struct gpio_keys_button *buttons);
-
-#define GPIO_LED_DEF(g, n, t, a) { \
- .name = (n), \
- .default_trigger = (t), \
- .gpio = (g), \
- .active_low = (a) \
-}
-
-#define GPIO_LED_STD(g, n, t) GPIO_LED_DEF((g), (n), (t), 0)
-#define GPIO_LED_INV(g, n, t) GPIO_LED_DEF((g), (n), (t), 1)
-
-extern void adm5120_add_device_gpio_leds(unsigned num_leds,
- struct gpio_led *leds) __init;
-
-#endif /* _ASM_MIPS_MACH_ADM5120_PLATFORM_H */
+++ /dev/null
-/*
- * ADM5120 ethernet switch definitions
- *
- * This header file defines the hardware registers of the ADM5120 SoC
- * built-in Ethernet switch.
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MACH_ADM5120_SWITCH_H
-#define _MACH_ADM5120_SWITCH_H
-
-#ifndef BIT
-# define BIT(at) (1 << (at))
-#endif
-#define BITMASK(len) (BIT(len)-1)
-
-#define SW_READ_REG(r) __raw_readl( \
- (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
-#define SW_WRITE_REG(r, v) __raw_writel((v), \
- (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r)
-
-/* Switch register offsets */
-#define SWITCH_REG_CODE 0x0000
-#define SWITCH_REG_SOFT_RESET 0x0004 /* Soft Reset */
-#define SWITCH_REG_BOOT_DONE 0x0008 /* Boot Done */
-#define SWITCH_REG_SW_RESET 0x000C /* Switch Reset */
-#define SWITCH_REG_PHY_STATUS 0x0014 /* PHY Status */
-#define SWITCH_REG_MEMCTRL 0x001C /* Memory Control */
-#define SWITCH_REG_CPUP_CONF 0x0024 /* CPU Port Configuration */
-#define SWITCH_REG_PORT_CONF0 0x0028 /* Port Configuration 0 */
-#define SWITCH_REG_PORT_CONF1 0x002C /* Port Configuration 1 */
-#define SWITCH_REG_PORT_CONF2 0x0030 /* Port Configuration 2 */
-#define SWITCH_REG_VLAN_G1 0x0040 /* VLAN group 1 */
-#define SWITCH_REG_VLAN_G2 0x0044 /* VLAN group 2 */
-#define SWITCH_REG_SEND_TRIG 0x0048 /* Send Trigger */
-#define SWITCH_REG_MAC_WT0 0x0058 /* MAC Write Address 0 */
-#define SWITCH_REG_MAC_WT1 0x005C /* MAC Write Address 1 */
-#define SWITCH_REG_BW_CNTL0 0x0060 /* Bandwidth Control 0 */
-#define SWITCH_REG_BW_CNTL1 0x0064 /* Bandwidth Control 1 */
-#define SWITCH_REG_PHY_CNTL0 0x0068 /* PHY Control 0 */
-#define SWITCH_REG_PHY_CNTL1 0x006C /* PHY Control 1 */
-#define SWITCH_REG_PORT_TH 0x0078 /* Port Threshold */
-#define SWITCH_REG_PHY_CNTL2 0x007C /* PHY Control 2 */
-#define SWITCH_REG_PHY_CNTL3 0x0080 /* PHY Control 3 */
-#define SWITCH_REG_PRI_CNTL 0x0084 /* Priority Control */
-#define SWITCH_REG_PHY_CNTL4 0x00A0 /* PHY Control 4 */
-#define SWITCH_REG_EMPTY_CNT 0x00A4 /* Empty Count */
-#define SWITCH_REG_PORT_CNTLS 0x00A8 /* Port Control Select */
-#define SWITCH_REG_PORT_CNTL 0x00AC /* Port Control */
-#define SWITCH_REG_INT_STATUS 0x00B0 /* Interrupt Status */
-#define SWITCH_REG_INT_MASK 0x00B4 /* Interrupt Mask */
-#define SWITCH_REG_GPIO_CONF0 0x00B8 /* GPIO Configuration 0 */
-#define SWITCH_REG_GPIO_CONF2 0x00BC /* GPIO Configuration 1 */
-#define SWITCH_REG_WDOG0 0x00C0 /* Watchdog 0 */
-#define SWITCH_REG_WDOG1 0x00C4 /* Watchdog 1 */
-
-#define SWITCH_REG_SHDA 0x00D0 /* Send High Descriptors Address */
-#define SWITCH_REG_SLDA 0x00D4 /* Send Low Descriptors Address */
-#define SWITCH_REG_RHDA 0x00D8 /* Receive High Descriptor Address */
-#define SWITCH_REG_RLDA 0x00DC /* Receive Low Descriptor Address */
-#define SWITCH_REG_SHWA 0x00E0 /* Send High Working Address */
-#define SWITCH_REG_SLWA 0x00E4 /* Send Low Working Address */
-#define SWITCH_REG_RHWA 0x00E8 /* Receive High Working Address */
-#define SWITCH_REG_RLWA 0x00EC /* Receive Low Working Address */
-
-#define SWITCH_REG_TIMER_INT 0x00F0 /* Timer */
-#define SWITCH_REG_TIMER 0x00F4 /* Timer Interrupt */
-
-#define SWITCH_REG_PORT0_LED 0x0100
-#define SWITCH_REG_PORT1_LED 0x0104
-#define SWITCH_REG_PORT2_LED 0x0108
-#define SWITCH_REG_PORT3_LED 0x010C
-#define SWITCH_REG_PORT4_LED 0x0110
-
-/* CODE register bits */
-#define CODE_PC_MASK BITMASK(16) /* Product Code */
-#define CODE_REV_SHIFT 16
-#define CODE_REV_MASK BITMASK(4) /* Product Revision */
-#define CODE_CLKS_SHIFT 20
-#define CODE_CLKS_MASK BITMASK(2) /* Clock Speed */
-#define CODE_CLKS_175 0 /* 175 MHz */
-#define CODE_CLKS_200 1 /* 200 MHz */
-#define CODE_CLKS_225 2 /* 225 MHz */
-#define CODE_CLKS_250 3 /* 250 MHz */
-#define CODE_NAB BIT(24) /* NAND boot */
-#define CODE_PK_MASK BITMASK(1) /* Package type */
-#define CODE_PK_SHIFT 29
-#define CODE_PK_BGA 0 /* BGA package */
-#define CODE_PK_PQFP 1 /* PQFP package */
-
-/* MEMCTRL register bits */
-#define MEMCTRL_SDRS_MASK BITMASK(3) /* SDRAM bank size */
-#define MEMCTRL_SDRS_4M 0x01
-#define MEMCTRL_SDRS_8M 0x02
-#define MEMCTRL_SDRS_16M 0x03
-#define MEMCTRL_SDRS_64M 0x04
-#define MEMCTRL_SDRS_128M 0x05
-#define MEMCTRL_SDR1_ENABLE BIT(5) /* enable SDRAM bank 1 */
-
-#define MEMCTRL_SRS0_SHIFT 8 /* shift for SRAM0 size */
-#define MEMCTRL_SRS1_SHIFT 16 /* shift for SRAM1 size */
-#define MEMCTRL_SRS_MASK BITMASK(3) /* SRAM size mask */
-#define MEMCTRL_SRS_DISABLED 0x00 /* Disabled */
-#define MEMCTRL_SRS_512K 0x01 /* 512KB*/
-#define MEMCTRL_SRS_1M 0x02 /* 1MB */
-#define MEMCTRL_SRS_2M 0x03 /* 2MB */
-#define MEMCTRL_SRS_4M 0x04 /* 4MB */
-
-/* Port bits used in various registers */
-#define SWITCH_PORT_PHY0 BIT(0)
-#define SWITCH_PORT_PHY1 BIT(1)
-#define SWITCH_PORT_PHY2 BIT(2)
-#define SWITCH_PORT_PHY3 BIT(3)
-#define SWITCH_PORT_PHY4 BIT(4)
-#define SWITCH_PORT_MII BIT(5)
-#define SWITCH_PORT_CPU BIT(6)
-
-/* Port bit shorthands */
-#define SWITCH_PORTS_PHY 0x1F /* phy ports */
-#define SWITCH_PORTS_NOCPU 0x3F /* physical ports */
-#define SWITCH_PORTS_ALL 0x7F /* all ports */
-
-/* CPUP_CONF register bits */
-#define CPUP_CONF_DCPUP BIT(0) /* Disable CPU port */
-#define CPUP_CONF_CRCP BIT(1) /* CRC padding from CPU */
-#define CPUP_CONF_BTM BIT(2) /* Bridge Testing Mode */
-#define CPUP_CONF_DUNP_SHIFT 9 /* Disable Unknown Packets for portX */
-#define CPUP_CONF_DMCP_SHIFT 16 /* Disable Mcast Packets form portX */
-#define CPUP_CONF_DBCP_SHIFT 24 /* Disable Bcast Packets form portX */
-
-/* PORT_CONF0 register bits */
-#define PORT_CONF0_DP_SHIFT 0 /* Disable Port */
-#define PORT_CONF0_EMCP_SHIFT 8 /* Enable All MC Packets */
-#define PORT_CONF0_BP_SHIFT 16 /* Enable Back Pressure */
-
-/* PORT_CONF1 register bits */
-#define PORT_CONF1_DISL_SHIFT 0 /* Disable Learning */
-#define PORT_CONF1_BS_SHIFT 6 /* Blocking State */
-#define PORT_CONF1_BM_SHIFT 12 /* Blocking Mode */
-
-/* SEND_TRIG register bits */
-#define SEND_TRIG_STL BIT(0) /* Send Trigger Low */
-#define SEND_TRIG_STH BIT(1) /* Send Trigger High */
-
-/* MAC_WT0 register bits */
-#define MAC_WT0_MAWC BIT(0) /* MAC address write command */
-#define MAC_WT0_MWD_SHIFT 1
-#define MAC_WT0_MWD BIT(1) /* MAC write done */
-#define MAC_WT0_WFB BIT(2) /* Write Filter Bit */
-#define MAC_WT0_WVN_SHIFT 3 /* Write Vlan Number shift */
-#define MAC_WT0_WVE BIT(6) /* Write VLAN enable */
-#define MAC_WT0_WPMN_SHIFT 7
-#define MAC_WT0_WAF_SHIFT 13 /* Write Age Field shift */
-#define MAC_WT0_WAF_EMPTY 0
-#define MAC_WT0_WAF_STATIC 7 /* age: static */
-#define MAC_WT0_MAC0_SHIFT 16
-#define MAC_WT0_MAC1_SHIFT 24
-
-/* MAC_WT1 register bits */
-#define MAC_WT1_MAC2_SHIFT 0
-#define MAC_WT1_MAC3_SHIFT 8
-#define MAC_WT1_MAC4_SHIFT 16
-#define MAC_WT1_MAC5_SHIFT 24
-
-/* BW_CNTL0/BW_CNTL1 register bits */
-#define BW_CNTL_DISABLE 0x00
-#define BW_CNTL_64K 0x01
-#define BW_CNTL_128K 0x02
-#define BW_CNTL_256K 0x03
-#define BW_CNTL_512K 0x04
-#define BW_CNTL_1M 0x05
-#define BW_CNTL_4M 0x06
-#define BW_CNTL_10M 0x07
-
-#define P4TBC_SHIFT 0
-#define P4RBC_SHIFT 4
-#define P5TBC_SHIFT 8
-#define P5RBC_SHIFT 12
-
-#define BW_CNTL1_NAND_ENABLE 0x100
-
-/* PHY_CNTL0 register bits */
-#define PHY_CNTL0_PHYA_MASK BITMASK(5)
-#define PHY_CNTL0_PHYR_MASK BITMASK(5)
-#define PHY_CNTL0_PHYR_SHIFT 8
-#define PHY_CNTL0_WC BIT(13) /* Write Command */
-#define PHY_CNTL0_RC BIT(14) /* Read Command */
-#define PHY_CNTL0_WTD_MASK BIT(16) /* Read Command */
-#define PHY_CNTL0_WTD_SHIFT 16
-
-/* PHY_CNTL1 register bits */
-#define PHY_CNTL1_WOD BIT(0) /* Write Operation Done */
-#define PHY_CNTL1_ROD BIT(1) /* Read Operation Done */
-#define PHY_CNTL1_RD_MASK BITMASK(16)
-#define PHY_CNTL1_RD_SHIFT 16
-
-/* PHY_CNTL2 register bits */
-#define PHY_CNTL2_ANE_SHIFT 0 /* Auto Negotiation Enable */
-#define PHY_CNTL2_SC_SHIFT 5 /* Speed Control */
-#define PHY_CNTL2_DC_SHIFT 10 /* Duplex Control */
-#define PHY_CNTL2_FNCV_SHIFT 15 /* Recommended FC Value */
-#define PHY_CNTL2_PHYR_SHIFT 20 /* PHY reset */
-#define PHY_CNTL2_AMDIX_SHIFT 25 /* Auto MDIX enable */
-/* PHY_CNTL2_RMAE is bad in datasheet */
-#define PHY_CNTL2_RMAE BIT(31) /* Recommended MCC Average enable */
-
-/* PHY_CNTL3 register bits */
-#define PHY_CNTL3_RNT BIT(10) /* Recommend Normal Threshold */
-
-/* PORT_TH register bits */
-#define PORT_TH_PPT_MASK BITMASK(8) /* Per Port Threshold */
-#define PORT_TH_CPUT_SHIFT 8 /* CPU Port Buffer Threshold */
-#define PORT_TH_CPUT_MASK BITMASK(8)
-#define PORT_TH_CPUHT_SHIFT 16 /* CPU Hold Threshold */
-#define PORT_TH_CPUHT_MASK BITMASK(8)
-#define PORT_TH_CPURT_SHIFT 24 /* CPU Release Threshold */
-#define PORT_TH_CPURT_MASK BITMASK(8)
-
-/* EMPTY_CNT register bits */
-#define EMPTY_CNT_EBGB_MASK BITMASK(9) /* Empty Blocks in the Global Buffer */
-
-/* GPIO_CONF0 register bits */
-#define GPIO_CONF0_MASK BITMASK(8)
-#define GPIO_CONF0_IM_SHIFT 0
-#define GPIO_CONF0_IV_SHIFT 8
-#define GPIO_CONF0_OE_SHIFT 16
-#define GPIO_CONF0_OV_SHIFT 24
-#define GPIO_CONF0_IM_MASK (0xFF << GPIO_CONF0_IM_SHIFT)
-#define GPIO_CONF0_IV_MASK (0xFF << GPIO_CONF0_IV_SHIFT)
-#define GPIO_CONF0_OE_MASK (0xFF << GPIO_CONF0_OE_SHIFT)
-#define GPIO_CONF0_OV_MASK (0xFF << GPIO_CONF0_OV_SHIFT)
-
-/* GPIO_CONF2 register bits */
-#define GPIO_CONF2_CSX0 BIT(4) /* enable CSX0:INTX0 on GPIO 1:2 */
-#define GPIO_CONF2_CSX1 BIT(5) /* enable CSX1:INTX1 on GPIO 3:4 */
-#define GPIO_CONF2_EW BIT(6) /* enable wait state pin for CSX0/1 */
-
-/* INT_STATUS/INT_MASK register bits */
-#define SWITCH_INT_SHD BIT(0) /* Send High Done */
-#define SWITCH_INT_SLD BIT(1) /* Send Low Done */
-#define SWITCH_INT_RHD BIT(2) /* Receive High Done */
-#define SWITCH_INT_RLD BIT(3) /* Receive Low Done */
-#define SWITCH_INT_HDF BIT(4) /* High Descriptor Full */
-#define SWITCH_INT_LDF BIT(5) /* Low Descriptor Full */
-#define SWITCH_INT_P0QF BIT(6) /* Port0 Queue Full */
-#define SWITCH_INT_P1QF BIT(7) /* Port1 Queue Full */
-#define SWITCH_INT_P2QF BIT(8) /* Port2 Queue Full */
-#define SWITCH_INT_P3QF BIT(9) /* Port3 Queue Full */
-#define SWITCH_INT_P4QF BIT(10) /* Port4 Queue Full */
-#define SWITCH_INT_P5QF BIT(11) /* Port5 Queue Full */
-#define SWITCH_INT_CPQF BIT(13) /* CPU Queue Full */
-#define SWITCH_INT_GQF BIT(14) /* Global Queue Full */
-#define SWITCH_INT_MD BIT(15) /* Must Drop */
-#define SWITCH_INT_BCS BIT(16) /* BC Storm */
-#define SWITCH_INT_PSC BIT(18) /* Port Status Change */
-#define SWITCH_INT_ID BIT(19) /* Intruder Detected */
-#define SWITCH_INT_W0TE BIT(20) /* Watchdog 0 Timer Expired */
-#define SWITCH_INT_W1TE BIT(21) /* Watchdog 1 Timer Expired */
-#define SWITCH_INT_RDE BIT(22) /* Receive Descriptor Error */
-#define SWITCH_INT_SDE BIT(23) /* Send Descriptor Error */
-#define SWITCH_INT_CPUH BIT(24) /* CPU Hold */
-
-/* TIMER_INT register bits */
-#define TIMER_INT_TOS BIT(0) /* time-out status */
-#define TIMER_INT_TOM BIT(16) /* mask time-out interrupt */
-
-/* TIMER register bits */
-#define TIMER_PERIOD_MASK BITMASK(16) /* mask for timer period */
-#define TIMER_PERIOD_DEFAULT 0xFFFF /* default timer period */
-#define TIMER_TE BIT(16) /* timer enable bit */
-
-/* PORTx_LED register bits */
-#define LED_MODE_MASK BITMASK(4)
-#define LED_MODE_INPUT 0
-#define LED_MODE_FLASH 1
-#define LED_MODE_OUT_HIGH 2
-#define LED_MODE_OUT_LOW 3
-#define LED_MODE_LINK 4
-#define LED_MODE_SPEED 5
-#define LED_MODE_DUPLEX 6
-#define LED_MODE_ACT 7
-#define LED_MODE_COLL 8
-#define LED_MODE_LINK_ACT 9
-#define LED_MODE_DUPLEX_COLL 10
-#define LED_MODE_10M_ACT 11
-#define LED_MODE_100M_ACT 12
-#define LED0_MODE_SHIFT 0 /* LED0 mode shift */
-#define LED1_MODE_SHIFT 4 /* LED1 mode shift */
-#define LED2_MODE_SHIFT 8 /* LED2 mode shift */
-#define LED0_IV_SHIFT 12 /* LED0 input value shift */
-#define LED1_IV_SHIFT 13 /* LED1 input value shift */
-#define LED2_IV_SHIFT 14 /* LED2 input value shift */
-
-#endif /* _MACH_ADM5120_SWITCH_H */
+++ /dev/null
-/*
- * ADM5120 UART definitions
- *
- * This header file defines the hardware registers of the ADM5120 SoC
- * built-in UARTs.
- *
- * Copyright (C) 2007 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MACH_ADM5120_UART_H
-#define _MACH_ADM5120_UART_H
-
-#define UART_BAUDDIV(clk, baud) ((clk/(16 * (baud)))-1)
-
-#define UART_REG_DATA 0x00
-#define UART_REG_RSR 0x04
-#define UART_REG_ECR UART_REG_RSR
-#define UART_REG_LCRH 0x08
-#define UART_REG_LCRM 0x0C
-#define UART_REG_LCRL 0x10
-#define UART_REG_CTRL 0x14
-#define UART_REG_FLAG 0x18
-
-/* Receive Status Register bits */
-#define UART_RSR_FE (1 << 0)
-#define UART_RSR_PE (1 << 1)
-#define UART_RSR_BE (1 << 2)
-#define UART_RSR_OE (1 << 3)
-#define UART_RSR_ERR (UART_RSR_FE | UART_RSR_PE | UART_RSR_BE)
-
-#define UART_ECR_ALL 0xFF
-
-/* Line Control High register bits */
-#define UART_LCRH_BRK (1 << 0) /* send break */
-#define UART_LCRH_PEN (1 << 1) /* parity enable */
-#define UART_LCRH_EPS (1 << 2) /* even parity select */
-#define UART_LCRH_STP1 (0 << 3) /* one stop bits select */
-#define UART_LCRH_STP2 (1 << 3) /* two stop bits select */
-#define UART_LCRH_FEN (1 << 4) /* FIFO enable */
-
-#define UART_LCRH_WLEN5 (0 << 5)
-#define UART_LCRH_WLEN6 (1 << 5)
-#define UART_LCRH_WLEN7 (2 << 5)
-#define UART_LCRH_WLEN8 (3 << 5)
-
-/* Control register bits */
-#define UART_CTRL_EN (1 << 0)
-
-/* Flag register bits */
-#define UART_FLAG_CTS (1 << 0)
-#define UART_FLAG_DSR (1 << 1)
-#define UART_FLAG_DCD (1 << 2)
-#define UART_FLAG_BUSY (1 << 3)
-#define UART_FLAG_RXFE (1 << 4)
-#define UART_FLAG_TXFF (1 << 5)
-#define UART_FLAG_RXFF (1 << 6)
-#define UART_FLAG_TXFE (1 << 7)
-
-#endif /* _MACH_ADM5120_UART_H */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
-/* Size definitions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_16 0x00000010
-#define SZ_256 0x00000100
-#define SZ_512 0x00000200
-
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif
-
-/* END */
+++ /dev/null
-/*
- * ADM5120 specific CPU feature overrides
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: include/asm-mips/cpu-features.h
- * Copyright (C) 2003, 2004 Ralf Baechle
- * Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-#ifndef __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H
-
-/*
- * The ADM5120 SOC has a built-in MIPS 4Kc core.
- */
-#define cpu_has_tlb 1
-#define cpu_has_4kex 1
-#define cpu_has_3k_cache 0
-#define cpu_has_4k_cache 1
-#define cpu_has_tx39_cache 0
-#define cpu_has_sb1_cache 0
-#define cpu_has_fpu 0
-#define cpu_has_32fpr 0
-#define cpu_has_counter 1
-#define cpu_has_watch 1
-#define cpu_has_divec 1
-/* #define cpu_has_vce ? */
-/* #define cpu_has_cache_cdex_p ? */
-/* #define cpu_has_cache_cdex_s ? */
-#define cpu_has_prefetch 1
-/* #define cpu_has_mcheck ? */
-#define cpu_has_ejtag 1
-#define cpu_has_llsc 1
-
-#define cpu_has_mips16 0
-#define cpu_has_mdmx 0
-#define cpu_has_mips3d 0
-#define cpu_has_smartmips 0
-
-/* #define cpu_has_vtag_icache ? */
-/* #define cpu_has_dc_aliases ? */
-/* #define cpu_has_ic_fills_f_dc ? */
-/* #define cpu_has_pindexed_dcache ? */
-
-/* #define cpu_icache_snoops_remote_store ? */
-
-#define cpu_has_mips32r1 1
-#define cpu_has_mips32r2 0
-#define cpu_has_mips64r1 0
-#define cpu_has_mips64r2 0
-
-#define cpu_has_dsp 0
-#define cpu_has_mipsmt 0
-
-/* #define cpu_has_nofpuex ? */
-#define cpu_has_64bits 0
-#define cpu_has_64bit_zero_reg 0
-#define cpu_has_64bit_gp_regs 0
-#define cpu_has_64bit_addresses 0
-
-/* #define cpu_has_inclusive_pcaches ? */
-
-#define cpu_dcache_line_size() 16
-#define cpu_icache_line_size() 16
-
-#endif /* __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H */
+++ /dev/null
-/*
- * ADM5120 GPIO wrappers for arch-neutral GPIO calls
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_MIPS_MACH_ADM5120_GPIO_H
-#define _ASM_MIPS_MACH_ADM5120_GPIO_H
-
-#define ARCH_NR_GPIOS 64
-
-#include <asm-generic/gpio.h>
-
-#include <asm/mach-adm5120/adm5120_switch.h>
-
-#define ADM5120_GPIO_PIN0 0
-#define ADM5120_GPIO_PIN1 1
-#define ADM5120_GPIO_PIN2 2
-#define ADM5120_GPIO_PIN3 3
-#define ADM5120_GPIO_PIN4 4
-#define ADM5120_GPIO_PIN5 5
-#define ADM5120_GPIO_PIN6 6
-#define ADM5120_GPIO_PIN7 7
-#define ADM5120_GPIO_P0L0 8
-#define ADM5120_GPIO_P0L1 9
-#define ADM5120_GPIO_P0L2 10
-#define ADM5120_GPIO_P1L0 11
-#define ADM5120_GPIO_P1L1 12
-#define ADM5120_GPIO_P1L2 13
-#define ADM5120_GPIO_P2L0 14
-#define ADM5120_GPIO_P2L1 15
-#define ADM5120_GPIO_P2L2 16
-#define ADM5120_GPIO_P3L0 17
-#define ADM5120_GPIO_P3L1 18
-#define ADM5120_GPIO_P3L2 19
-#define ADM5120_GPIO_P4L0 20
-#define ADM5120_GPIO_P4L1 21
-#define ADM5120_GPIO_P4L2 22
-#define ADM5120_GPIO_MAX 22
-#define ADM5120_GPIO_COUNT ADM5120_GPIO_MAX+1
-
-#define ADM5120_GPIO_LOW 0
-#define ADM5120_GPIO_HIGH 1
-
-#define ADM5120_GPIO_SWITCH 0x10
-#define ADM5120_GPIO_FLASH (ADM5120_GPIO_SWITCH | LED_MODE_FLASH)
-#define ADM5120_GPIO_LINK (ADM5120_GPIO_SWITCH | LED_MODE_LINK)
-#define ADM5120_GPIO_SPEED (ADM5120_GPIO_SWITCH | LED_MODE_SPEED)
-#define ADM5120_GPIO_DUPLEX (ADM5120_GPIO_SWITCH | LED_MODE_DUPLEX)
-#define ADM5120_GPIO_ACT (ADM5120_GPIO_SWITCH | LED_MODE_ACT)
-#define ADM5120_GPIO_COLL (ADM5120_GPIO_SWITCH | LED_MODE_COLL)
-#define ADM5120_GPIO_LINK_ACT (ADM5120_GPIO_SWITCH | LED_MODE_LINK_ACT)
-#define ADM5120_GPIO_DUPLEX_COLL (ADM5120_GPIO_SWITCH | LED_MODE_DUPLEX_COLL)
-#define ADM5120_GPIO_10M_ACT (ADM5120_GPIO_SWITCH | LED_MODE_10M_ACT)
-#define ADM5120_GPIO_100M_ACT (ADM5120_GPIO_SWITCH | LED_MODE_100M_ACT)
-
-extern int __adm5120_gpio0_get_value(unsigned gpio);
-extern void __adm5120_gpio0_set_value(unsigned gpio, int value);
-extern int __adm5120_gpio1_get_value(unsigned gpio);
-extern void __adm5120_gpio1_set_value(unsigned gpio, int value);
-extern int adm5120_gpio_to_irq(unsigned gpio);
-extern int adm5120_irq_to_gpio(unsigned irq);
-
-static inline int gpio_get_value(unsigned gpio)
-{
- int ret;
-
- switch (gpio) {
- case ADM5120_GPIO_PIN0 ... ADM5120_GPIO_PIN7:
- ret = __adm5120_gpio0_get_value(gpio);
- break;
- case ADM5120_GPIO_P0L0 ... ADM5120_GPIO_P4L2:
- ret = __adm5120_gpio1_get_value(gpio - ADM5120_GPIO_P0L0);
- break;
- default:
- ret = __gpio_get_value(gpio);
- break;
- }
-
- return ret;
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
- switch (gpio) {
- case ADM5120_GPIO_PIN0 ... ADM5120_GPIO_PIN7:
- __adm5120_gpio0_set_value(gpio, value);
- break;
- case ADM5120_GPIO_P0L0 ... ADM5120_GPIO_P4L2:
- __adm5120_gpio1_set_value(gpio - ADM5120_GPIO_P0L0, value);
- break;
- default:
- __gpio_set_value(gpio, value);
- break;
- }
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- return adm5120_gpio_to_irq(gpio);
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return adm5120_irq_to_gpio(irq);
-}
-
-#define gpio_cansleep __gpio_cansleep
-
-#endif /* _ASM_MIPS_MACH_ADM5120_GPIO_H */
+++ /dev/null
-/*
- * ADM5120 specific IRQ numbers
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-#ifndef _ASM_MIPS_MACH_ADM5120_IRQ_H
-#define _ASM_MIPS_MACH_ADM5120_IRQ_H
-
-#define MIPS_CPU_IRQ_BASE 0
-#define NR_IRQS 24
-
-#include_next <irq.h>
-
-#include <asm/mach-adm5120/adm5120_intc.h>
-
-#define NO_IRQ (-1)
-
-#define MIPS_CPU_IRQ_COUNT 8
-#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
-
-#define ADM5120_INTC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_IRQ_COUNT)
-#define ADM5120_INTC_IRQ(x) (ADM5120_INTC_IRQ_BASE + (x))
-
-#define ADM5120_IRQ_INTC MIPS_CPU_IRQ(2)
-#define ADM5120_IRQ_COUNTER MIPS_CPU_IRQ(7)
-
-#define ADM5120_IRQ_TIMER ADM5120_INTC_IRQ(INTC_IRQ_TIMER)
-#define ADM5120_IRQ_UART0 ADM5120_INTC_IRQ(INTC_IRQ_UART0)
-#define ADM5120_IRQ_UART1 ADM5120_INTC_IRQ(INTC_IRQ_UART1)
-#define ADM5120_IRQ_USBC ADM5120_INTC_IRQ(INTC_IRQ_USBC)
-#define ADM5120_IRQ_GPIO2 ADM5120_INTC_IRQ(INTC_IRQ_GPIO2)
-#define ADM5120_IRQ_GPIO4 ADM5120_INTC_IRQ(INTC_IRQ_GPIO4)
-#define ADM5120_IRQ_PCI0 ADM5120_INTC_IRQ(INTC_IRQ_PCI0)
-#define ADM5120_IRQ_PCI1 ADM5120_INTC_IRQ(INTC_IRQ_PCI1)
-#define ADM5120_IRQ_PCI2 ADM5120_INTC_IRQ(INTC_IRQ_PCI2)
-#define ADM5120_IRQ_SWITCH ADM5120_INTC_IRQ(INTC_IRQ_SWITCH)
-
-#endif /* _ASM_MIPS_MACH_ADM5120_IRQ_H */
+++ /dev/null
-/*
- * ADMBoot specific definitions
- *
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _ADMBOOT_H
-#define _ADMBOOT_H
-
-extern int admboot_get_mac_base(u32 offset, u32 len, u8 *mac) __init;
-
-#endif /* _ADMBOOT_H */
+++ /dev/null
-/*
- * Broadcom's CFE definitions
- *
- * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _PROM_CFE_H_
-#define _PROM_CFE_H_
-
-extern int cfe_present(void) __init;
-extern char *cfe_getenv(char *);
-
-#endif /*_PROM_CFE_H_*/
+++ /dev/null
-/*
- * Generic prom definitions
- *
- * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _PROM_GENERIC_H_
-#define _PROM_GENERIC_H_
-
-extern int generic_prom_present(void) __init;
-extern char *generic_prom_getenv(char *);
-
-#endif /*_PROM_GENERIC_H_*/
+++ /dev/null
-/*
- * Compex's MyLoader specific definitions
- *
- * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _MYLOADER_H_
-#define _MYLOADER_H_
-
-/*
- * Firmware file format:
- *
- * <header>
- * [<block descriptor 0>]
- * ...
- * [<block descriptor n>]
- * <null block descriptor>
- * [<block data 0>]
- * ...
- * [<block data n>]
- *
- *
- */
-
-/* Myloader specific magic numbers */
-#define MYLO_MAGIC_FIRMWARE 0x4C594D00
-#define MYLO_MAGIC_20021103 0x20021103
-#define MYLO_MAGIC_20021107 0x20021107
-
-#define MYLO_MAGIC_SYS_PARAMS MYLO_MAGIC_20021107
-#define MYLO_MAGIC_PARTITIONS MYLO_MAGIC_20021103
-#define MYLO_MAGIC_BOARD_PARAMS MYLO_MAGIC_20021103
-
-/*
- * Addresses of the data structures provided by MyLoader
- */
-#define MYLO_MIPS_SYS_PARAMS 0x80000800 /* System Parameters */
-#define MYLO_MIPS_BOARD_PARAMS 0x80000A00 /* Board Parameters */
-#define MYLO_MIPS_PARTITIONS 0x80000C00 /* Partition Table */
-#define MYLO_MIPS_BOOT_PARAMS 0x80000E00 /* Boot Parameters */
-
-/* Vendor ID's (seems to be same as the PCI vendor ID's) */
-#define VENID_COMPEX 0x11F6
-
-/* Devices based on the ADM5120 */
-#define DEVID_COMPEX_NP27G 0x0078
-#define DEVID_COMPEX_NP28G 0x044C
-#define DEVID_COMPEX_NP28GHS 0x044E
-#define DEVID_COMPEX_WP54Gv1C 0x0514
-#define DEVID_COMPEX_WP54G 0x0515
-#define DEVID_COMPEX_WP54AG 0x0546
-#define DEVID_COMPEX_WPP54AG 0x0550
-#define DEVID_COMPEX_WPP54G 0x0555
-
-/* Devices based on the IXP422 */
-#define DEVID_COMPEX_WP18 0x047E
-#define DEVID_COMPEX_NP18A 0x0489
-
-/* Other devices */
-#define DEVID_COMPEX_NP26G8M 0x03E8
-#define DEVID_COMPEX_NP26G16M 0x03E9
-
-struct mylo_fw_header {
- uint32_t magic; /* must be MYLO_MAGIC_FIRMWARE */
- uint32_t crc; /* CRC of the whole firmware */
- uint32_t res0; /* unknown/unused */
- uint32_t res1; /* unknown/unused */
- uint16_t vid; /* vendor ID */
- uint16_t did; /* device ID */
- uint16_t svid; /* sub vendor ID */
- uint16_t sdid; /* sub device ID */
- uint32_t rev; /* device revision */
- uint32_t fwhi; /* FIXME: firmware version high? */
- uint32_t fwlo; /* FIXME: firmware version low? */
- uint32_t flags; /* firmware flags */
-};
-
-#define FW_FLAG_BOARD_PARAMS_WP 0x01 /* board parameters are write protected */
-#define FW_FLAG_BOOT_SECTOR_WE 0x02 /* enable of write boot sectors (below 64K) */
-
-struct mylo_fw_blockdesc {
- uint32_t type; /* block type */
- uint32_t addr; /* relative address to flash start */
- uint32_t dlen; /* size of block data in bytes */
- uint32_t blen; /* total size of block in bytes */
-};
-
-#define FW_DESC_TYPE_UNUSED 0
-#define FW_DESC_TYPE_USED 1
-
-struct mylo_partition {
- uint16_t flags; /* partition flags */
- uint16_t type; /* type of the partition */
- uint32_t addr; /* relative address of the partition from the
- flash start */
- uint32_t size; /* size of the partition in bytes */
- uint32_t param; /* if this is the active partition, the
- MyLoader load code to this address */
-};
-
-#define PARTITION_FLAG_ACTIVE 0x8000 /* this is the active partition,
- * MyLoader loads firmware from here */
-#define PARTITION_FLAG_ISRAM 0x2000 /* FIXME: this is a RAM partition? */
-#define PARTIIION_FLAG_RAMLOAD 0x1000 /* FIXME: load this partition into the RAM? */
-#define PARTITION_FLAG_PRELOAD 0x0800 /* the partition data preloaded to RAM
- * before decompression */
-#define PARTITION_FLAG_HAVEHDR 0x0002 /* the partition data have a header */
-
-#define PARTITION_TYPE_FREE 0
-#define PARTITION_TYPE_USED 1
-
-#define MYLO_MAX_PARTITIONS 8 /* maximum number of partitions in the
- partition table */
-
-struct mylo_partition_table {
- uint32_t magic; /* must be MYLO_MAGIC_PARTITIONS */
- uint32_t res0; /* unknown/unused */
- uint32_t res1; /* unknown/unused */
- uint32_t res2; /* unknown/unused */
- struct mylo_partition partitions[MYLO_MAX_PARTITIONS];
-};
-
-struct mylo_partition_header {
- uint32_t len; /* length of the partition data */
- uint32_t crc; /* CRC value of the partition data */
-};
-
-struct mylo_system_params {
- uint32_t magic; /* must be MYLO_MAGIC_SYS_PARAMS */
- uint32_t res0;
- uint32_t res1;
- uint32_t mylo_ver;
- uint16_t vid; /* Vendor ID */
- uint16_t did; /* Device ID */
- uint16_t svid; /* Sub Vendor ID */
- uint16_t sdid; /* Sub Device ID */
- uint32_t rev; /* device revision */
- uint32_t fwhi;
- uint32_t fwlo;
- uint32_t tftp_addr;
- uint32_t prog_start;
- uint32_t flash_size; /* Size of boot FLASH in bytes */
- uint32_t dram_size; /* Size of onboard RAM in bytes */
-};
-
-
-struct mylo_eth_addr {
- uint8_t mac[6];
- uint8_t csum[2];
-};
-
-#define MYLO_ETHADDR_COUNT 8 /* maximum number of ethernet address
- in the board parameters */
-
-struct mylo_board_params {
- uint32_t magic; /* must be MYLO_MAGIC_BOARD_PARAMS */
- uint32_t res0;
- uint32_t res1;
- uint32_t res2;
- struct mylo_eth_addr addr[MYLO_ETHADDR_COUNT];
-};
-
-struct myloader_info {
- u32 vid;
- u32 did;
- u32 svid;
- u32 sdid;
- uint8_t macs[MYLO_ETHADDR_COUNT][6];
-};
-
-extern struct myloader_info myloader_info;
-extern int myloader_present(void) __init;
-
-#endif /* _MYLOADER_H_*/
+++ /dev/null
-/*
- * Mikrotik's RouterBOOT definitions
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _PROM_ROUTERBOOT_H_
-#define _PROM_ROUTERBOOT_H_
-
-struct rb_bios_settings {
- u32 hs_offs; /* hard settings offset */
- u32 hs_size; /* hard settings size */
- u32 fw_offs; /* firmware offset */
- u32 ss_offs; /* soft settings offset */
- u32 ss_size; /* soft settings size */
-};
-
-struct rb_hard_settings {
- char *name; /* board name */
- char *bios_ver; /* BIOS version */
- u32 mem_size; /* memory size in bytes */
- u32 mac_count; /* number of mac addresses */
- u8 *mac_base; /* mac address base */
-};
-
-extern int routerboot_present(void) __init;
-extern char *routerboot_get_boardname(void);
-
-extern struct rb_hard_settings rb_hs;
-
-#endif /* _PROM_ROUTERBOOT_H_ */
+++ /dev/null
-/*
- * ZyNOS (ZyXEL's Networking OS) definitions
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#ifndef _ZYNOS_H
-#define _ZYNOS_H
-
-#define ZYNOS_NAME_LEN 32
-#define ZYNOS_FEAT_BYTES 22
-#define ZYNOS_MAC_LEN 6
-
-struct zynos_board_info {
- unsigned char vendor[ZYNOS_NAME_LEN];
- unsigned char product[ZYNOS_NAME_LEN];
- u32 bootext_addr;
- u32 res0;
- u16 board_id;
- u8 res1[6];
- u8 feat_other[ZYNOS_FEAT_BYTES];
- u8 feat_main;
- u8 res2;
- u8 mac[ZYNOS_MAC_LEN];
- u8 country;
- u8 dbgflag;
-} __attribute__ ((packed));
-
-/*
- * Vendor IDs
- */
-#define ZYNOS_VENDOR_ID_ZYXEL 0
-#define ZYNOS_VENDOR_ID_NETGEAR 1
-#define ZYNOS_VENDOR_ID_DLINK 2
-#define ZYNOS_VENDOR_ID_OTHER 3
-#define ZYNOS_VENDOR_ID_LUCENT 4
-
-/*
- * Vendor names
- */
-#define ZYNOS_VENDOR_DLINK "D-Link"
-#define ZYNOS_VENDOR_LUCENT "LUCENT"
-#define ZYNOS_VENDOR_NETGEAR "NetGear"
-#define ZYNOS_VENDOR_ZYXEL "ZyXEL"
-
-/*
- * Board IDs (big-endian)
- */
-#define ZYNOS_BOARD_ES2108 0x00F2 /* Ethernet Switch 2108 */
-#define ZYNOS_BOARD_ES2108F 0x01AF /* Ethernet Switch 2108-F */
-#define ZYNOS_BOARD_ES2108G 0x00F3 /* Ethernet Switch 2108-G */
-#define ZYNOS_BOARD_ES2108LC 0x00FC /* Ethernet Switch 2108-LC */
-#define ZYNOS_BOARD_ES2108PWR 0x00F4 /* Ethernet Switch 2108PWR */
-#define ZYNOS_BOARD_HS100 0x9FF1 /* HomeSafe 100/100W */
-#define ZYNOS_BOARD_P334 0x9FF5 /* Prestige 334 */
-#define ZYNOS_BOARD_P334U 0x9FDD /* Prestige 334U */
-#define ZYNOS_BOARD_P334W 0x9FF3 /* Prestige 334W */
-#define ZYNOS_BOARD_P334WH 0x00E0 /* Prestige 334WH */
-#define ZYNOS_BOARD_P334WHD 0x00E1 /* Prestige 334WHD */
-#define ZYNOS_BOARD_P334WT 0x9FEF /* Prestige 334WT */
-#define ZYNOS_BOARD_P334WT_ALT 0x9F02 /* Prestige 334WT alternative*/
-#define ZYNOS_BOARD_P335 0x9FED /* Prestige 335/335WT */
-#define ZYNOS_BOARD_P335PLUS 0x0025 /* Prestige 335Plus */
-#define ZYNOS_BOARD_P335U 0x9FDC /* Prestige 335U */
-
-/*
- * Some magic numbers (big-endian)
- */
-#define ZYNOS_MAGIC_DBGAREA1 0x48646267 /* "Hdbg" */
-#define ZYNOS_MAGIC_DBGAREA2 0x61726561 /* "area" */
-
-struct bootbase_info {
- u16 vendor_id;
- u16 board_id;
- u8 mac[6];
-};
-
-extern struct bootbase_info bootbase_info;
-extern int bootbase_present(void) __init;
-
-#endif /* _ZYNOS_H */
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_ADM5120_WAR_H
-#define __ASM_MIPS_MACH_ADM5120_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
-#define R4600_V1_HIT_CACHEOP_WAR 0
-#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
-#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
-#define RM9000_CDEX_SMP_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
-#define R10000_LLSC_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
-
-#endif /* __ASM_MIPS_MACH_ADM5120_WAR_H */
+++ /dev/null
-/*
- * ADM5120 PCI Host Controller driver
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel
- * done by Jeroen Vreeken
- * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
- *
- * Jeroen's code was based on the Linux 2.4.xx source codes found in various
- * tarballs released by Edimax for it's ADM5120 based devices
- * Copyright (C) ADMtek Incorporated
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-
-#include <linux/pci.h>
-#include <linux/pci_ids.h>
-#include <linux/pci_regs.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(f, a...) printk(KERN_DEBUG f, ## a)
-#else
-#define DBG(f, a...) do {} while (0)
-#endif
-
-#define PCI_ENABLE 0x80000000
-
-/* -------------------------------------------------------------------------*/
-
-static unsigned int adm5120_pci_nr_irqs __initdata;
-static struct adm5120_pci_irq *adm5120_pci_irq_map __initdata;
-
-static DEFINE_SPINLOCK(pci_lock);
-
-/* -------------------------------------------------------------------------*/
-
-static inline void write_cfgaddr(u32 addr)
-{
- __raw_writel((addr | PCI_ENABLE),
- (void __iomem *)(KSEG1ADDR(ADM5120_PCICFG_ADDR)));
-}
-
-static inline void write_cfgdata(u32 data)
-{
- __raw_writel(data, (void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
-}
-
-static inline u32 read_cfgdata(void)
-{
- return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
-}
-
-static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
-{
- return ((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
- (where & 0xFC);
-}
-
-/* -------------------------------------------------------------------------*/
-
-static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 *val)
-{
- unsigned long flags;
- u32 data;
-
- spin_lock_irqsave(&pci_lock, flags);
-
- write_cfgaddr(mkaddr(bus, devfn, where));
- data = read_cfgdata();
-
- DBG("PCI: cfg_read %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
- bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
- where, size, data);
-
- switch (size) {
- case 1:
- if (where & 1)
- data >>= 8;
- if (where & 2)
- data >>= 16;
- data &= 0xFF;
- break;
- case 2:
- if (where & 2)
- data >>= 16;
- data &= 0xFFFF;
- break;
- }
-
- *val = data;
- DBG(", 0x%08X returned\n", data);
-
- spin_unlock_irqrestore(&pci_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 val)
-{
- unsigned long flags;
- u32 data;
- int s;
-
- spin_lock_irqsave(&pci_lock, flags);
-
- write_cfgaddr(mkaddr(bus, devfn, where));
- data = read_cfgdata();
-
- DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
- bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
- where, size, data);
-
- switch (size) {
- case 1:
- s = ((where & 3) << 3);
- data &= ~(0xFF << s);
- data |= ((val & 0xFF) << s);
- break;
- case 2:
- s = ((where & 2) << 4);
- data &= ~(0xFFFF << s);
- data |= ((val & 0xFFFF) << s);
- break;
- case 4:
- data = val;
- break;
- }
-
- write_cfgdata(data);
- DBG(", 0x%08X written\n", data);
-
- spin_unlock_irqrestore(&pci_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-struct pci_ops adm5120_pci_ops = {
- .read = pci_config_read,
- .write = pci_config_write,
-};
-
-/* -------------------------------------------------------------------------*/
-
-static void adm5120_pci_fixup(struct pci_dev *dev)
-{
- if (dev->devfn != 0)
- return;
-
- /* setup COMMAND register */
- pci_write_config_word(dev, PCI_COMMAND,
- (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
-
- /* setup CACHE_LINE_SIZE register */
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
-
- /* setup BARS */
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
-}
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120,
- adm5120_pci_fixup);
-
-/* -------------------------------------------------------------------------*/
-
-void __init adm5120_pci_set_irq_map(unsigned int nr_irqs,
- struct adm5120_pci_irq *map)
-{
- adm5120_pci_nr_irqs = nr_irqs;
- adm5120_pci_irq_map = map;
-}
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq = -1;
- int i;
-
- if ((!adm5120_pci_nr_irqs) || (!adm5120_pci_irq_map)) {
- printk(KERN_ALERT "PCI: pci_irq_map is not initialized\n");
- goto out;
- }
-
- if (slot < 1 || slot > 4) {
- printk(KERN_ALERT "PCI: slot number %u is not supported\n",
- slot);
- goto out;
- }
-
- for (i = 0; i < adm5120_pci_nr_irqs; i++) {
- if ((adm5120_pci_irq_map[i].slot == slot)
- && (adm5120_pci_irq_map[i].func == PCI_FUNC(dev->devfn))
- && (adm5120_pci_irq_map[i].pin == pin)) {
- irq = adm5120_pci_irq_map[i].irq;
- break;
- }
- }
-
- if (irq < 0) {
- printk(KERN_ALERT "PCI: no irq found for %s pin:%u\n",
- pci_name((struct pci_dev *)dev), pin);
- } else {
- printk(KERN_INFO "PCI: mapping irq for %s pin:%u, irq:%d\n",
- pci_name((struct pci_dev *)dev), pin, irq);
- }
-
-out:
- return irq;
-}
-
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
-
-/* -------------------------------------------------------------------------*/
-
-static struct resource pci_io_resource = {
- .name = "ADM5120 PCI I/O",
- .start = ADM5120_PCIIO_BASE,
- .end = ADM5120_PCICFG_ADDR-1,
- .flags = IORESOURCE_IO
-};
-
-static struct resource pci_mem_resource = {
- .name = "ADM5120 PCI MEM",
- .start = ADM5120_PCIMEM_BASE,
- .end = ADM5120_PCIIO_BASE-1,
- .flags = IORESOURCE_MEM
-};
-
-static struct pci_controller adm5120_controller = {
- .pci_ops = &adm5120_pci_ops,
- .io_resource = &pci_io_resource,
- .mem_resource = &pci_mem_resource,
-};
-
-static int __init adm5120_pci_setup(void)
-{
- if (adm5120_package_pqfp()) {
- printk(KERN_INFO "PCI: not available on ADM5120P\n");
- return -1;
- }
-
- /* Avoid ISA compat ranges. */
- PCIBIOS_MIN_IO = 0x00000000;
- PCIBIOS_MIN_MEM = 0x00000000;
-
- /* Set I/O resource limits. */
- ioport_resource.end = 0x1fffffff;
- iomem_resource.end = 0xffffffff;
-
- register_pci_controller(&adm5120_controller);
- return 0;
-}
-
-arch_initcall(adm5120_pci_setup);
+++ /dev/null
-/*
- * A low-level PATA driver to handle a Compact Flash connected on the
- * Mikrotik's RouterBoard 153 board.
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was based on: drivers/ata/pata_ixp4xx_cf.c
- * Copyright (C) 2006-07 Tower Technologies
- * Author: Alessandro Zummo <a.zummo@towertech.it>
- *
- * Also was based on the driver for Linux 2.4.xx published by Mikrotik for
- * their RouterBoard 1xx and 5xx series devices. The original Mikrotik code
- * seems not to have a license.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
-#include <linux/libata.h>
-#include <scsi/scsi_host.h>
-
-#define DRV_NAME "pata-rb153-cf"
-#define DRV_VERSION "0.5.0"
-#define DRV_DESC "PATA driver for RouterBOARD 153 Compact Flash"
-
-#define RB153_CF_MAXPORTS 1
-#define RB153_CF_IO_DELAY 100
-
-#define RB153_CF_REG_CMD 0x0800
-#define RB153_CF_REG_CTRL 0x080E
-#define RB153_CF_REG_DATA 0x0C00
-
-struct rb153_cf_info {
- void __iomem *iobase;
- unsigned int gpio_line;
- int frozen;
- unsigned int irq;
-};
-
-static inline void rb153_pata_finish_io(struct ata_port *ap)
-{
- struct rb153_cf_info *info = ap->host->private_data;
-
- /* FIXME: Keep previous delay. If this is merely a fence then
- * ata_sff_sync might be sufficient. */
- ata_sff_dma_pause(ap);
- ndelay(RB153_CF_IO_DELAY);
-
- irq_set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
-}
-
-static void rb153_pata_exec_command(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- writeb(tf->command, ap->ioaddr.command_addr);
- rb153_pata_finish_io(ap);
-}
-
-static unsigned int rb153_pata_data_xfer(struct ata_device *adev,
- unsigned char *buf,
- unsigned int buflen,
- int write_data)
-{
- void __iomem *ioaddr = adev->link->ap->ioaddr.data_addr;
- unsigned int t;
-
- t = buflen;
- if (write_data) {
- for (; t > 0; t--, buf++)
- writeb(*buf, ioaddr);
- } else {
- for (; t > 0; t--, buf++)
- *buf = readb(ioaddr);
- }
-
- rb153_pata_finish_io(adev->link->ap);
- return buflen;
-}
-
-static void rb153_pata_freeze(struct ata_port *ap)
-{
- struct rb153_cf_info *info = ap->host->private_data;
-
- info->frozen = 1;
-}
-
-static void rb153_pata_thaw(struct ata_port *ap)
-{
- struct rb153_cf_info *info = ap->host->private_data;
-
- info->frozen = 0;
-}
-
-static irqreturn_t rb153_pata_irq_handler(int irq, void *dev_instance)
-{
- struct ata_host *ah = dev_instance;
- struct rb153_cf_info *info = ah->private_data;
-
- if (gpio_get_value(info->gpio_line)) {
- irq_set_irq_type(info->irq, IRQ_TYPE_LEVEL_LOW);
- if (!info->frozen)
- ata_sff_interrupt(irq, dev_instance);
- } else {
- irq_set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
- }
-
- return IRQ_HANDLED;
-}
-
-static struct ata_port_operations rb153_pata_port_ops = {
- .inherits = &ata_sff_port_ops,
- .sff_exec_command = rb153_pata_exec_command,
- .sff_data_xfer = rb153_pata_data_xfer,
- .freeze = rb153_pata_freeze,
- .thaw = rb153_pata_thaw,
-};
-
-static struct scsi_host_template rb153_pata_sht = {
- ATA_PIO_SHT(DRV_NAME),
-};
-
-static void rb153_pata_setup_port(struct ata_host *ah)
-{
- struct rb153_cf_info *info = ah->private_data;
- struct ata_port *ap;
-
- ap = ah->ports[0];
-
- ap->ops = &rb153_pata_port_ops;
- ap->pio_mask = 0x1f; /* PIO4 */
-
- ap->ioaddr.cmd_addr = info->iobase + RB153_CF_REG_CMD;
- ap->ioaddr.ctl_addr = info->iobase + RB153_CF_REG_CTRL;
- ap->ioaddr.altstatus_addr = info->iobase + RB153_CF_REG_CTRL;
-
- ata_sff_std_ports(&ap->ioaddr);
-
- ap->ioaddr.data_addr = info->iobase + RB153_CF_REG_DATA;
-}
-
-static int rb153_pata_driver_probe(struct platform_device *pdev)
-{
- unsigned int irq;
- int gpio;
- struct resource *res;
- struct ata_host *ah;
- struct rb153_cf_info *info;
- int ret;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(&pdev->dev, "no IOMEM resource found\n");
- return -EINVAL;
- }
-
- irq = platform_get_irq(pdev, 0);
- if (irq <= 0) {
- dev_err(&pdev->dev, "no IRQ resource found\n");
- return -ENOENT;
- }
-
- gpio = irq_to_gpio(irq);
- if (gpio < 0) {
- dev_err(&pdev->dev, "no GPIO found for irq%d\n", irq);
- return -ENOENT;
- }
-
- ret = gpio_request(gpio, DRV_NAME);
- if (ret) {
- dev_err(&pdev->dev, "GPIO request failed\n");
- return ret;
- }
-
- ah = ata_host_alloc(&pdev->dev, RB153_CF_MAXPORTS);
- if (!ah)
- return -ENOMEM;
-
- platform_set_drvdata(pdev, ah);
-
- info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
- if (!info)
- return -ENOMEM;
-
- ah->private_data = info;
- info->gpio_line = gpio;
- info->irq = irq;
-
- info->iobase = devm_ioremap_nocache(&pdev->dev, res->start,
- res->end - res->start + 1);
- if (!info->iobase)
- return -ENOMEM;
-
- ret = gpio_direction_input(gpio);
- if (ret) {
- dev_err(&pdev->dev, "unable to set GPIO direction, err=%d\n",
- ret);
- goto err_free_gpio;
- }
-
- rb153_pata_setup_port(ah);
-
- ret = ata_host_activate(ah, irq, rb153_pata_irq_handler,
- IRQF_TRIGGER_LOW, &rb153_pata_sht);
- if (ret)
- goto err_free_gpio;
-
- return 0;
-
-err_free_gpio:
- gpio_free(gpio);
-
- return ret;
-}
-
-static int rb153_pata_driver_remove(struct platform_device *pdev)
-{
- struct ata_host *ah = platform_get_drvdata(pdev);
- struct rb153_cf_info *info = ah->private_data;
-
- ata_host_detach(ah);
- gpio_free(info->gpio_line);
-
- return 0;
-}
-
-static struct platform_driver rb153_pata_platform_driver = {
- .probe = rb153_pata_driver_probe,
- .remove = rb153_pata_driver_remove,
- .driver = {
- .name = DRV_NAME,
- .owner = THIS_MODULE,
- },
-};
-
-/* ------------------------------------------------------------------------ */
-
-#define DRV_INFO DRV_DESC " version " DRV_VERSION
-
-static int __init rb153_pata_module_init(void)
-{
- printk(KERN_INFO DRV_INFO "\n");
-
- return platform_driver_register(&rb153_pata_platform_driver);
-}
-
-static void __exit rb153_pata_module_exit(void)
-{
- platform_driver_unregister(&rb153_pata_platform_driver);
-}
-
-MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-MODULE_DESCRIPTION(DRV_DESC);
-MODULE_VERSION(DRV_VERSION);
-MODULE_LICENSE("GPL v2");
-
-module_init(rb153_pata_module_init);
-module_exit(rb153_pata_module_exit);
+++ /dev/null
-/*
- * LED ADM5120 Switch Port State Trigger
- *
- * Copyright (C) 2007 Bernhard Held <bernhard at bernhardheld.de>
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was based on: drivers/leds/ledtrig-timer.c
- * Copyright 2005-2006 Openedhand Ltd.
- * Author: Richard Purdie
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/device.h>
-
-#include <linux/gpio.h>
-
-#include "leds.h"
-
-#define DRV_NAME "port_state"
-#define DRV_DESC "LED ADM5120 Switch Port State Trigger"
-
-struct port_state {
- char *name;
- unsigned int value;
-};
-
-#define PORT_STATE(n, v) {.name = (n), .value = (v)}
-
-static struct port_state port_states[] = {
- PORT_STATE("off", LED_OFF),
- PORT_STATE("on", LED_FULL),
- PORT_STATE("flash", ADM5120_GPIO_FLASH),
- PORT_STATE("link", ADM5120_GPIO_LINK),
- PORT_STATE("speed", ADM5120_GPIO_SPEED),
- PORT_STATE("duplex", ADM5120_GPIO_DUPLEX),
- PORT_STATE("act", ADM5120_GPIO_ACT),
- PORT_STATE("coll", ADM5120_GPIO_COLL),
- PORT_STATE("link_act", ADM5120_GPIO_LINK_ACT),
- PORT_STATE("duplex_coll", ADM5120_GPIO_DUPLEX_COLL),
- PORT_STATE("10M_act", ADM5120_GPIO_10M_ACT),
- PORT_STATE("100M_act", ADM5120_GPIO_100M_ACT),
-};
-
-static ssize_t led_port_state_show(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- struct led_classdev *led_cdev = dev_get_drvdata(dev);
- struct port_state *state = led_cdev->trigger_data;
- int len = 0;
- int i;
-
- *buf = '\0';
- for (i = 0; i < ARRAY_SIZE(port_states); i++) {
- if (&port_states[i] == state)
- len += sprintf(buf+len, "[%s] ", port_states[i].name);
- else
- len += sprintf(buf+len, "%s ", port_states[i].name);
- }
- len += sprintf(buf+len, "\n");
-
- return len;
-}
-
-static ssize_t led_port_state_store(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t size)
-{
- struct led_classdev *led_cdev = dev_get_drvdata(dev);
- size_t len;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(port_states); i++) {
- len = strlen(port_states[i].name);
- if (strncmp(port_states[i].name, buf, len) != 0)
- continue;
-
- if (buf[len] != '\0' && buf[len] != '\n')
- continue;
-
- led_cdev->trigger_data = &port_states[i];
- led_set_brightness(led_cdev, port_states[i].value);
- return size;
- }
-
- return -EINVAL;
-}
-
-static DEVICE_ATTR(port_state, 0644, led_port_state_show,
- led_port_state_store);
-
-static void adm5120_switch_trig_activate(struct led_classdev *led_cdev)
-{
- struct port_state *state = port_states;
- int rc;
-
- led_cdev->trigger_data = state;
-
- rc = device_create_file(led_cdev->dev, &dev_attr_port_state);
- if (rc)
- goto err;
-
- led_set_brightness(led_cdev, state->value);
-
- return;
-err:
- led_cdev->trigger_data = NULL;
-}
-
-static void adm5120_switch_trig_deactivate(struct led_classdev *led_cdev)
-{
- struct port_state *state = led_cdev->trigger_data;
-
- if (!state)
- return;
-
- device_remove_file(led_cdev->dev, &dev_attr_port_state);
-
-}
-
-static struct led_trigger adm5120_switch_led_trigger = {
- .name = DRV_NAME,
- .activate = adm5120_switch_trig_activate,
- .deactivate = adm5120_switch_trig_deactivate,
-};
-
-static int __init adm5120_switch_trig_init(void)
-{
- led_trigger_register(&adm5120_switch_led_trigger);
- return 0;
-}
-
-static void __exit adm5120_switch_trig_exit(void)
-{
- led_trigger_unregister(&adm5120_switch_led_trigger);
-}
-
-module_init(adm5120_switch_trig_init);
-module_exit(adm5120_switch_trig_exit);
-
-MODULE_AUTHOR("Bernhard Held <bernhard at bernhardheld.de>, "
- "Gabor Juhos <juhosg@openwrt.org>");
-MODULE_DESCRIPTION(DRV_DESC);
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * Platform driver for NOR flash devices on ADM5120 based boards
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/mtd/map/physmap.c
- * Copyright (C) 2003 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-#include <asm/mach-adm5120/adm5120_mpmc.h>
-#include <asm/mach-adm5120/adm5120_platform.h>
-
-#define DRV_NAME "adm5120-flash"
-#define DRV_DESC "ADM5120 flash MAP driver"
-#define MAX_PARSED_PARTS 8
-
-#ifdef ADM5120_FLASH_DEBUG
-#define MAP_DBG(m, f, a...) printk(KERN_INFO "%s: " f, (m->name) , ## a)
-#else
-#define MAP_DBG(m, f, a...) do {} while (0)
-#endif
-#define MAP_ERR(m, f, a...) printk(KERN_ERR "%s: " f, (m->name) , ## a)
-#define MAP_INFO(m, f, a...) printk(KERN_INFO "%s: " f, (m->name) , ## a)
-
-struct adm5120_map_info {
- struct map_info map;
- void (*switch_bank)(unsigned);
- unsigned long window_size;
-};
-
-struct adm5120_flash_info {
- struct mtd_info *mtd;
- struct resource *res;
- struct platform_device *dev;
- struct adm5120_map_info amap;
-};
-
-struct flash_desc {
- u32 phys;
- u32 srs_shift;
-};
-
-/*
- * Globals
- */
-static DEFINE_SPINLOCK(adm5120_flash_spin);
-#define FLASH_LOCK() spin_lock(&adm5120_flash_spin)
-#define FLASH_UNLOCK() spin_unlock(&adm5120_flash_spin)
-
-static u32 flash_bankwidths[4] = { 1, 2, 4, 0 };
-
-static u32 flash_sizes[8] = {
- 0, 512*1024, 1024*1024, 2*1024*1024,
- 4*1024*1024, 0, 0, 0
-};
-
-static struct flash_desc flash_descs[2] = {
- {
- .phys = ADM5120_SRAM0_BASE,
- .srs_shift = MEMCTRL_SRS0_SHIFT,
- }, {
- .phys = ADM5120_SRAM1_BASE,
- .srs_shift = MEMCTRL_SRS1_SHIFT,
- }
-};
-
-static const char const *probe_types[] = {
- "cfi_probe",
- "jedec_probe",
- "map_rom",
- NULL
-};
-
-static const char const *parse_types[] = {
- "cmdlinepart",
-#ifdef CONFIG_MTD_REDBOOT_PARTS
- "RedBoot",
-#endif
-#ifdef CONFIG_MTD_MYLOADER_PARTS
- "MyLoader",
-#endif
- NULL,
-};
-
-#define BANK_SIZE (2<<20)
-#define BANK_SIZE_MAX (4<<20)
-#define BANK_OFFS_MASK (BANK_SIZE-1)
-#define BANK_START_MASK (~BANK_OFFS_MASK)
-
-static inline struct adm5120_map_info *map_to_amap(struct map_info *map)
-{
- return (struct adm5120_map_info *)map;
-}
-
-static void adm5120_flash_switchbank(struct map_info *map,
- unsigned long ofs)
-{
- struct adm5120_map_info *amap = map_to_amap(map);
- unsigned bank;
-
- if (amap->switch_bank == NULL)
- return;
-
- bank = (ofs & BANK_START_MASK) >> 21;
- if (bank > 1)
- BUG();
-
- MAP_DBG(map, "switching to bank %u, ofs=%lX\n", bank, ofs);
- amap->switch_bank(bank);
-}
-
-static map_word adm5120_flash_read(struct map_info *map, unsigned long ofs)
-{
- struct adm5120_map_info *amap = map_to_amap(map);
- map_word ret;
-
- MAP_DBG(map, "reading from ofs %lX\n", ofs);
-
- if (ofs >= amap->window_size)
- return map_word_ff(map);
-
- FLASH_LOCK();
- adm5120_flash_switchbank(map, ofs);
- ret = inline_map_read(map, (ofs & (amap->window_size-1)));
- FLASH_UNLOCK();
-
- return ret;
-}
-
-static void adm5120_flash_write(struct map_info *map, const map_word datum,
- unsigned long ofs)
-{
- struct adm5120_map_info *amap = map_to_amap(map);
-
- MAP_DBG(map, "writing to ofs %lX\n", ofs);
-
- if (ofs > amap->window_size)
- return;
-
- FLASH_LOCK();
- adm5120_flash_switchbank(map, ofs);
- inline_map_write(map, datum, (ofs & (amap->window_size-1)));
- FLASH_UNLOCK();
-}
-
-static void adm5120_flash_copy_from(struct map_info *map, void *to,
- unsigned long from, ssize_t len)
-{
- struct adm5120_map_info *amap = map_to_amap(map);
- char *p;
- ssize_t t;
-
- MAP_DBG(map, "copy_from, to=%lX, from=%lX, len=%lX\n",
- (unsigned long)to, from, (unsigned long)len);
-
- if (from > amap->window_size)
- return;
-
- p = (char *)to;
- while (len > 0) {
- t = len;
- if ((from < BANK_SIZE) && ((from+len) > BANK_SIZE))
- t = BANK_SIZE-from;
-
- FLASH_LOCK();
- MAP_DBG(map, "copying %lu byte(s) from %lX to %lX\n",
- (unsigned long)t, (from & (amap->window_size-1)),
- (unsigned long)p);
- adm5120_flash_switchbank(map, from);
- inline_map_copy_from(map, p, (from & (amap->window_size-1)), t);
- FLASH_UNLOCK();
- p += t;
- from += t;
- len -= t;
- }
-}
-
-static int adm5120_flash_initres(struct adm5120_flash_info *info)
-{
- struct map_info *map = &info->amap.map;
- int err = 0;
-
- info->res = request_mem_region(map->phys, info->amap.window_size,
- map->name);
- if (info->res == NULL) {
- MAP_ERR(map, "could not reserve memory region\n");
- err = -ENOMEM;
- goto out;
- }
-
- map->virt = ioremap_nocache(map->phys, info->amap.window_size);
- if (map->virt == NULL) {
- MAP_ERR(map, "failed to ioremap flash region\n");
- err = -ENOMEM;
- goto out;
- }
-
-out:
- return err;
-}
-
-static int adm5120_flash_initinfo(struct adm5120_flash_info *info,
- struct platform_device *dev)
-{
- struct map_info *map = &info->amap.map;
- struct adm5120_flash_platform_data *pdata = dev->dev.platform_data;
- struct flash_desc *fdesc;
- u32 t = 0;
-
- map->name = dev_name(&dev->dev);
-
- if (dev->id > 1) {
- MAP_ERR(map, "invalid flash id\n");
- goto err_out;
- }
-
- fdesc = &flash_descs[dev->id];
-
- if (pdata)
- info->amap.window_size = pdata->window_size;
-
- if (info->amap.window_size == 0) {
- /* get memory window size */
- t = SW_READ_REG(SWITCH_REG_MEMCTRL) >> fdesc->srs_shift;
- t &= MEMCTRL_SRS_MASK;
- info->amap.window_size = flash_sizes[t];
- }
-
- if (info->amap.window_size == 0) {
- MAP_ERR(map, "unable to determine window size\n");
- goto err_out;
- }
-
- /* get flash bus width */
- switch (dev->id) {
- case 0:
- t = MPMC_READ_REG(SC1) & SC_MW_MASK;
- break;
- case 1:
- t = MPMC_READ_REG(SC0) & SC_MW_MASK;
- break;
- }
- map->bankwidth = flash_bankwidths[t];
- if (map->bankwidth == 0) {
- MAP_ERR(map, "invalid bus width detected\n");
- goto err_out;
- }
-
- map->phys = fdesc->phys;
- map->size = BANK_SIZE_MAX;
-
- simple_map_init(map);
- map->read = adm5120_flash_read;
- map->write = adm5120_flash_write;
- map->copy_from = adm5120_flash_copy_from;
-
- if (pdata) {
- map->set_vpp = pdata->set_vpp;
- info->amap.switch_bank = pdata->switch_bank;
- }
-
- info->dev = dev;
-
- MAP_INFO(map, "probing at 0x%lX, size:%ldKiB, width:%d bits\n",
- (unsigned long)map->phys,
- (unsigned long)info->amap.window_size >> 10,
- map->bankwidth*8);
-
- return 0;
-
-err_out:
- return -ENODEV;
-}
-
-static void adm5120_flash_initbanks(struct adm5120_flash_info *info)
-{
- struct map_info *map = &info->amap.map;
-
- if (info->mtd->size <= BANK_SIZE)
- /* no bank switching needed */
- return;
-
- if (info->amap.switch_bank) {
- info->amap.window_size = info->mtd->size;
- return;
- }
-
- MAP_ERR(map, "reduce visibility from %ldKiB to %ldKiB\n",
- (unsigned long)map->size >> 10,
- (unsigned long)info->mtd->size >> 10);
-
- info->mtd->size = info->amap.window_size;
-}
-
-static int adm5120_flash_remove(struct platform_device *dev)
-{
- struct adm5120_flash_info *info;
-
- info = platform_get_drvdata(dev);
- if (info == NULL)
- return 0;
-
- platform_set_drvdata(dev, NULL);
-
- if (info->mtd != NULL) {
- mtd_device_unregister(info->mtd);
- map_destroy(info->mtd);
- }
-
- if (info->amap.map.virt != NULL)
- iounmap(info->amap.map.virt);
-
- if (info->res != NULL) {
- release_resource(info->res);
- kfree(info->res);
- }
-
- return 0;
-}
-
-static int adm5120_flash_probe(struct platform_device *dev)
-{
- struct adm5120_flash_platform_data *pdata;
- struct adm5120_flash_info *info;
- struct map_info *map;
- const char **probe_type;
- int err;
-
- pdata = dev->dev.platform_data;
- if (!pdata) {
- dev_err(&dev->dev, "no platform data\n");
- return -EINVAL;
- }
-
- info = kzalloc(sizeof(*info), GFP_KERNEL);
- if (info == NULL) {
- err = -ENOMEM;
- goto err_out;
- }
-
- platform_set_drvdata(dev, info);
-
- err = adm5120_flash_initinfo(info, dev);
- if (err)
- goto err_out;
-
- err = adm5120_flash_initres(info);
- if (err)
- goto err_out;
-
- map = &info->amap.map;
- for (probe_type = probe_types; info->mtd == NULL && *probe_type != NULL;
- probe_type++)
- info->mtd = do_map_probe(*probe_type, map);
-
- if (info->mtd == NULL) {
- MAP_ERR(map, "map_probe failed\n");
- err = -ENXIO;
- goto err_out;
- }
-
- adm5120_flash_initbanks(info);
-
- if (info->mtd->size < info->amap.window_size) {
- /* readjust resources */
- iounmap(map->virt);
- release_resource(info->res);
- kfree(info->res);
-
- info->amap.window_size = info->mtd->size;
- map->size = info->mtd->size;
- MAP_INFO(map, "reducing map size to %ldKiB\n",
- (unsigned long)map->size >> 10);
- err = adm5120_flash_initres(info);
- if (err)
- goto err_out;
- }
-
- MAP_INFO(map, "found at 0x%lX, size:%ldKiB, width:%d bits\n",
- (unsigned long)map->phys, (unsigned long)info->mtd->size >> 10,
- map->bankwidth*8);
-
- info->mtd->owner = THIS_MODULE;
-
- err = mtd_device_parse_register(info->mtd, parse_types, 0,
- pdata->parts, pdata->nr_parts);
- if (err)
- goto err_out;
-
- return 0;
-
-err_out:
- adm5120_flash_remove(dev);
- return err;
-}
-
-#ifdef CONFIG_PM
-static int adm5120_flash_suspend(struct platform_device *dev,
- pm_message_t state)
-{
- struct adm5120_flash_info *info = platform_get_drvdata(dev);
- int ret = 0;
-
- if (info)
- ret = info->mtd->suspend(info->mtd);
-
- return ret;
-}
-
-static int adm5120_flash_resume(struct platform_device *dev)
-{
- struct adm5120_flash_info *info = platform_get_drvdata(dev);
-
- if (info)
- info->mtd->resume(info->mtd);
-
- return 0;
-}
-
-static void adm5120_flash_shutdown(struct platform_device *dev)
-{
- struct adm5120_flash_info *info = platform_get_drvdata(dev);
-
- if (info && info->mtd->suspend(info->mtd) == 0)
- info->mtd->resume(info->mtd);
-}
-#endif
-
-static struct platform_driver adm5120_flash_driver = {
- .probe = adm5120_flash_probe,
- .remove = adm5120_flash_remove,
-#ifdef CONFIG_PM
- .suspend = adm5120_flash_suspend,
- .resume = adm5120_flash_resume,
- .shutdown = adm5120_flash_shutdown,
-#endif
- .driver = {
- .name = DRV_NAME,
- },
-};
-
-static int __init adm5120_flash_init(void)
-{
- int err;
-
- err = platform_driver_register(&adm5120_flash_driver);
-
- return err;
-}
-
-static void __exit adm5120_flash_exit(void)
-{
- platform_driver_unregister(&adm5120_flash_driver);
-}
-
-module_init(adm5120_flash_init);
-module_exit(adm5120_flash_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-MODULE_DESCRIPTION(DRV_DESC);
+++ /dev/null
-/*
- * Copyright (C) Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-#include <linux/kmod.h>
-#include <linux/root_dev.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
-#include <linux/byteorder/generic.h>
-
-#define PFX "trxsplit: "
-
-#define TRX_MAGIC 0x30524448 /* "HDR0" */
-#define TRX_VERSION 1
-#define TRX_MAX_LEN 0x3A0000
-#define TRX_NO_HEADER 0x1 /* do not write TRX header */
-#define TRX_GZ_FILES 0x2 /* contains individual gzip files */
-#define TRX_MAX_OFFSET 3
-#define TRX_MIN_KERNEL_SIZE (256 * 1024)
-
-struct trx_header {
- u32 magic; /* "HDR0" */
- u32 len; /* Length of file including header */
- u32 crc32; /* 32-bit CRC from flag_version to end of file */
- u32 flag_version; /* 0:15 flags, 16:31 version */
- u32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions */
-};
-
-#define TRX_ALIGN 0x1000
-
-static int trx_nr_parts;
-static unsigned long trx_offset;
-static struct mtd_info *trx_mtd;
-static struct mtd_partition trx_parts[TRX_MAX_OFFSET];
-static struct trx_header trx_hdr;
-
-static int trxsplit_refresh_partitions(struct mtd_info *mtd);
-
-static int trxsplit_checktrx(struct mtd_info *mtd, unsigned long offset)
-{
- size_t retlen;
- int err;
-
- err = mtd_read(mtd, offset, sizeof(trx_hdr), &retlen, (void *)&trx_hdr);
- if (err) {
- printk(KERN_ALERT PFX "unable to read from '%s'\n", mtd->name);
- goto err_out;
- }
-
- if (retlen != sizeof(trx_hdr)) {
- printk(KERN_ALERT PFX "reading failed on '%s'\n", mtd->name);
- goto err_out;
- }
-
- trx_hdr.magic = le32_to_cpu(trx_hdr.magic);
- trx_hdr.len = le32_to_cpu(trx_hdr.len);
- trx_hdr.crc32 = le32_to_cpu(trx_hdr.crc32);
- trx_hdr.flag_version = le32_to_cpu(trx_hdr.flag_version);
- trx_hdr.offsets[0] = le32_to_cpu(trx_hdr.offsets[0]);
- trx_hdr.offsets[1] = le32_to_cpu(trx_hdr.offsets[1]);
- trx_hdr.offsets[2] = le32_to_cpu(trx_hdr.offsets[2]);
-
- /* sanity checks */
- if (trx_hdr.magic != TRX_MAGIC)
- goto err_out;
-
- if (trx_hdr.len > mtd->size - offset)
- goto err_out;
-
- /* TODO: add crc32 checking too? */
-
- return 0;
-
-err_out:
- return -1;
-}
-
-static void trxsplit_findtrx(struct mtd_info *mtd)
-{
- unsigned long offset;
- int err;
-
- printk(KERN_INFO PFX "searching TRX header in '%s'\n", mtd->name);
-
- err = 0;
- for (offset = 0; offset < mtd->size; offset += TRX_ALIGN) {
- err = trxsplit_checktrx(mtd, offset);
- if (err == 0)
- break;
- }
-
- if (err)
- return;
-
- printk(KERN_INFO PFX "TRX header found at 0x%lX\n", offset);
-
- trx_mtd = mtd;
- trx_offset = offset;
-}
-
-static void trxsplit_create_partitions(struct mtd_info *mtd)
-{
- struct mtd_partition *part = trx_parts;
- int err;
- int i;
-
- for (i = 0; i < TRX_MAX_OFFSET; i++) {
- part = &trx_parts[i];
- if (trx_hdr.offsets[i] == 0)
- continue;
- part->offset = trx_offset + trx_hdr.offsets[i];
- trx_nr_parts++;
- }
-
- for (i = 0; i < trx_nr_parts-1; i++)
- trx_parts[i].size = trx_parts[i+1].offset - trx_parts[i].offset;
-
- trx_parts[i].size = mtd->size - trx_parts[i].offset;
-
- i = 0;
- part = &trx_parts[i];
- if (part->size < TRX_MIN_KERNEL_SIZE) {
- part->name = "loader";
- i++;
- }
-
- part = &trx_parts[i];
- part->name = "kernel";
- i++;
-
- part = &trx_parts[i];
- part->name = "rootfs";
-
- err = mtd_device_register(mtd, trx_parts, trx_nr_parts);
- if (err) {
- printk(KERN_ALERT PFX "adding TRX partitions failed\n");
- return;
- }
-
- mtd->refresh_device = trxsplit_refresh_partitions;
-}
-
-static int trxsplit_refresh_partitions(struct mtd_info *mtd)
-{
- printk(KERN_INFO PFX "refreshing TRX partitions in '%s' (%d,%d)\n",
- mtd->name, MTD_BLOCK_MAJOR, mtd->index);
-
- /* remove old partitions */
- mtd_device_unregister(mtd);
-
- trxsplit_findtrx(mtd);
- if (!trx_mtd)
- goto err;
-
- trxsplit_create_partitions(trx_mtd);
- return 1;
-
-err:
- return 0;
-}
-
-static void __init trxsplit_add_mtd(struct mtd_info *mtd)
-{
- if (mtd->type != MTD_NORFLASH) {
- printk(KERN_INFO PFX "'%s' is not a NOR flash, skipped\n",
- mtd->name);
- return;
- }
-
- if (!trx_mtd)
- trxsplit_findtrx(mtd);
-}
-
-static void __init trxsplit_remove_mtd(struct mtd_info *mtd)
-{
- /* nothing to do */
-}
-
-static struct mtd_notifier trxsplit_notifier __initdata = {
- .add = trxsplit_add_mtd,
- .remove = trxsplit_remove_mtd,
-};
-
-static void __init trxsplit_scan(void)
-{
- register_mtd_user(&trxsplit_notifier);
- unregister_mtd_user(&trxsplit_notifier);
-}
-
-static int __init trxsplit_init(void)
-{
- trxsplit_scan();
-
- if (trx_mtd) {
- printk(KERN_INFO PFX "creating TRX partitions in '%s' "
- "(%d,%d)\n", trx_mtd->name, MTD_BLOCK_MAJOR,
- trx_mtd->index);
- trxsplit_create_partitions(trx_mtd);
- }
-
- return 0;
-}
-
-late_initcall(trxsplit_init);
+++ /dev/null
-/*
- * ADM5120 built-in ethernet switch driver
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This code was based on a driver for Linux 2.6.xx by Jeroen Vreeken.
- * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
- * NAPI extension for the Jeroen's driver
- * Copyright Thomas Langer (Thomas.Langer@infineon.com), 2007
- * Copyright Friedrich Beckmann (Friedrich.Beckmann@infineon.com), 2007
- * Inspiration for the Jeroen's driver came from the ADMtek 2.4 driver.
- * Copyright ADMtek Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/spinlock.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-
-#include <asm/mipsregs.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-
-#include "adm5120sw.h"
-#include <linux/dma-mapping.h>
-
-#define DRV_NAME "adm5120-switch"
-#define DRV_DESC "ADM5120 built-in ethernet switch driver"
-#define DRV_VERSION "0.1.1"
-
-#define CONFIG_ADM5120_SWITCH_NAPI 1
-#undef CONFIG_ADM5120_SWITCH_DEBUG
-
-/* ------------------------------------------------------------------------ */
-
-#ifdef CONFIG_ADM5120_SWITCH_DEBUG
-#define SW_DBG(f, a...) printk(KERN_DEBUG "%s: " f, DRV_NAME , ## a)
-#else
-#define SW_DBG(f, a...) do {} while (0)
-#endif
-#define SW_ERR(f, a...) printk(KERN_ERR "%s: " f, DRV_NAME , ## a)
-#define SW_INFO(f, a...) printk(KERN_INFO "%s: " f, DRV_NAME , ## a)
-
-#define SWITCH_NUM_PORTS 6
-#define ETH_CSUM_LEN 4
-
-#define RX_MAX_PKTLEN 1550
-#define RX_RING_SIZE 64
-
-#define TX_RING_SIZE 32
-#define TX_QUEUE_LEN 28 /* Limit ring entries actually used. */
-#define TX_TIMEOUT (HZ * 400)
-
-#define RX_DESCS_SIZE (RX_RING_SIZE * sizeof(struct dma_desc *))
-#define RX_SKBS_SIZE (RX_RING_SIZE * sizeof(struct sk_buff *))
-#define TX_DESCS_SIZE (TX_RING_SIZE * sizeof(struct dma_desc *))
-#define TX_SKBS_SIZE (TX_RING_SIZE * sizeof(struct sk_buff *))
-
-#define SKB_ALLOC_LEN (RX_MAX_PKTLEN + 32)
-#define SKB_RESERVE_LEN (NET_IP_ALIGN + NET_SKB_PAD)
-
-#define SWITCH_INTS_HIGH (SWITCH_INT_SHD | SWITCH_INT_RHD | SWITCH_INT_HDF)
-#define SWITCH_INTS_LOW (SWITCH_INT_SLD | SWITCH_INT_RLD | SWITCH_INT_LDF)
-#define SWITCH_INTS_ERR (SWITCH_INT_RDE | SWITCH_INT_SDE | SWITCH_INT_CPUH)
-#define SWITCH_INTS_Q (SWITCH_INT_P0QF | SWITCH_INT_P1QF | SWITCH_INT_P2QF | \
- SWITCH_INT_P3QF | SWITCH_INT_P4QF | SWITCH_INT_P5QF | \
- SWITCH_INT_CPQF | SWITCH_INT_GQF)
-
-#define SWITCH_INTS_ALL (SWITCH_INTS_HIGH | SWITCH_INTS_LOW | \
- SWITCH_INTS_ERR | SWITCH_INTS_Q | \
- SWITCH_INT_MD | SWITCH_INT_PSC)
-
-#define SWITCH_INTS_USED (SWITCH_INTS_LOW | SWITCH_INT_PSC)
-#define SWITCH_INTS_POLL (SWITCH_INT_RLD | SWITCH_INT_LDF | SWITCH_INT_SLD)
-
-/* ------------------------------------------------------------------------ */
-
-struct adm5120_if_priv {
- struct net_device *dev;
-
- unsigned int vlan_no;
- unsigned int port_mask;
-
-#ifdef CONFIG_ADM5120_SWITCH_NAPI
- struct napi_struct napi;
-#endif
-};
-
-struct dma_desc {
- __u32 buf1;
-#define DESC_OWN (1UL << 31) /* Owned by the switch */
-#define DESC_EOR (1UL << 28) /* End of Ring */
-#define DESC_ADDR_MASK 0x1FFFFFF
-#define DESC_ADDR(x) ((__u32)(x) & DESC_ADDR_MASK)
- __u32 buf2;
-#define DESC_BUF2_EN (1UL << 31) /* Buffer 2 enable */
- __u32 buflen;
- __u32 misc;
-/* definitions for tx/rx descriptors */
-#define DESC_PKTLEN_SHIFT 16
-#define DESC_PKTLEN_MASK 0x7FF
-/* tx descriptor specific part */
-#define DESC_CSUM (1UL << 31) /* Append checksum */
-#define DESC_DSTPORT_SHIFT 8
-#define DESC_DSTPORT_MASK 0x3F
-#define DESC_VLAN_MASK 0x3F
-/* rx descriptor specific part */
-#define DESC_SRCPORT_SHIFT 12
-#define DESC_SRCPORT_MASK 0x7
-#define DESC_DA_MASK 0x3
-#define DESC_DA_SHIFT 4
-#define DESC_IPCSUM_FAIL (1UL << 3) /* IP checksum fail */
-#define DESC_VLAN_TAG (1UL << 2) /* VLAN tag present */
-#define DESC_TYPE_MASK 0x3 /* mask for Packet type */
-#define DESC_TYPE_IP 0x0 /* IP packet */
-#define DESC_TYPE_PPPoE 0x1 /* PPPoE packet */
-} __attribute__ ((aligned(16)));
-
-/* ------------------------------------------------------------------------ */
-
-static int adm5120_nrdevs;
-
-static struct net_device *adm5120_devs[SWITCH_NUM_PORTS];
-/* Lookup table port -> device */
-static struct net_device *adm5120_port[SWITCH_NUM_PORTS];
-
-static struct dma_desc *txl_descs;
-static struct dma_desc *rxl_descs;
-
-static dma_addr_t txl_descs_dma;
-static dma_addr_t rxl_descs_dma;
-
-static struct sk_buff **txl_skbuff;
-static struct sk_buff **rxl_skbuff;
-
-static unsigned int cur_rxl, dirty_rxl; /* producer/consumer ring indices */
-static unsigned int cur_txl, dirty_txl;
-
-static unsigned int sw_used;
-
-static DEFINE_SPINLOCK(tx_lock);
-
-/* ------------------------------------------------------------------------ */
-
-static inline u32 sw_read_reg(u32 reg)
-{
- return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
-}
-
-static inline void sw_write_reg(u32 reg, u32 val)
-{
- __raw_writel(val, (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
-}
-
-static inline void sw_int_mask(u32 mask)
-{
- u32 t;
-
- t = sw_read_reg(SWITCH_REG_INT_MASK);
- t |= mask;
- sw_write_reg(SWITCH_REG_INT_MASK, t);
-}
-
-static inline void sw_int_unmask(u32 mask)
-{
- u32 t;
-
- t = sw_read_reg(SWITCH_REG_INT_MASK);
- t &= ~mask;
- sw_write_reg(SWITCH_REG_INT_MASK, t);
-}
-
-static inline void sw_int_ack(u32 mask)
-{
- sw_write_reg(SWITCH_REG_INT_STATUS, mask);
-}
-
-static inline u32 sw_int_status(void)
-{
- u32 t;
-
- t = sw_read_reg(SWITCH_REG_INT_STATUS);
- t &= ~sw_read_reg(SWITCH_REG_INT_MASK);
- return t;
-}
-
-static inline u32 desc_get_srcport(struct dma_desc *desc)
-{
- return (desc->misc >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK;
-}
-
-static inline u32 desc_get_pktlen(struct dma_desc *desc)
-{
- return (desc->misc >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK;
-}
-
-static inline int desc_ipcsum_fail(struct dma_desc *desc)
-{
- return ((desc->misc & DESC_IPCSUM_FAIL) != 0);
-}
-
-/* ------------------------------------------------------------------------ */
-
-#ifdef CONFIG_ADM5120_SWITCH_DEBUG
-static void sw_dump_desc(char *label, struct dma_desc *desc, int tx)
-{
- u32 t;
-
- SW_DBG("%s %s desc/%p\n", label, tx ? "tx" : "rx", desc);
-
- t = desc->buf1;
- SW_DBG(" buf1 %08X addr=%08X; len=%08X %s%s\n", t,
- t & DESC_ADDR_MASK,
- desc->buflen,
- (t & DESC_OWN) ? "SWITCH" : "CPU",
- (t & DESC_EOR) ? " RE" : "");
-
- t = desc->buf2;
- SW_DBG(" buf2 %08X addr=%08X%s\n", desc->buf2,
- t & DESC_ADDR_MASK,
- (t & DESC_BUF2_EN) ? " EN" : "");
-
- t = desc->misc;
- if (tx)
- SW_DBG(" misc %08X%s pktlen=%04X ports=%02X vlan=%02X\n", t,
- (t & DESC_CSUM) ? " CSUM" : "",
- (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
- (t >> DESC_DSTPORT_SHIFT) & DESC_DSTPORT_MASK,
- t & DESC_VLAN_MASK);
- else
- SW_DBG(" misc %08X pktlen=%04X port=%d DA=%d%s%s type=%d\n",
- t,
- (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
- (t >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK,
- (t >> DESC_DA_SHIFT) & DESC_DA_MASK,
- (t & DESC_IPCSUM_FAIL) ? " IPCF" : "",
- (t & DESC_VLAN_TAG) ? " VLAN" : "",
- (t & DESC_TYPE_MASK));
-}
-
-static void sw_dump_intr_mask(char *label, u32 mask)
-{
- SW_DBG("%s %08X%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
- label, mask,
- (mask & SWITCH_INT_SHD) ? " SHD" : "",
- (mask & SWITCH_INT_SLD) ? " SLD" : "",
- (mask & SWITCH_INT_RHD) ? " RHD" : "",
- (mask & SWITCH_INT_RLD) ? " RLD" : "",
- (mask & SWITCH_INT_HDF) ? " HDF" : "",
- (mask & SWITCH_INT_LDF) ? " LDF" : "",
- (mask & SWITCH_INT_P0QF) ? " P0QF" : "",
- (mask & SWITCH_INT_P1QF) ? " P1QF" : "",
- (mask & SWITCH_INT_P2QF) ? " P2QF" : "",
- (mask & SWITCH_INT_P3QF) ? " P3QF" : "",
- (mask & SWITCH_INT_P4QF) ? " P4QF" : "",
- (mask & SWITCH_INT_CPQF) ? " CPQF" : "",
- (mask & SWITCH_INT_GQF) ? " GQF" : "",
- (mask & SWITCH_INT_MD) ? " MD" : "",
- (mask & SWITCH_INT_BCS) ? " BCS" : "",
- (mask & SWITCH_INT_PSC) ? " PSC" : "",
- (mask & SWITCH_INT_ID) ? " ID" : "",
- (mask & SWITCH_INT_W0TE) ? " W0TE" : "",
- (mask & SWITCH_INT_W1TE) ? " W1TE" : "",
- (mask & SWITCH_INT_RDE) ? " RDE" : "",
- (mask & SWITCH_INT_SDE) ? " SDE" : "",
- (mask & SWITCH_INT_CPUH) ? " CPUH" : "");
-}
-
-static void sw_dump_regs(void)
-{
- u32 t;
-
- t = sw_read_reg(SWITCH_REG_PHY_STATUS);
- SW_DBG("phy_status: %08X\n", t);
-
- t = sw_read_reg(SWITCH_REG_CPUP_CONF);
- SW_DBG("cpup_conf: %08X%s%s%s\n", t,
- (t & CPUP_CONF_DCPUP) ? " DCPUP" : "",
- (t & CPUP_CONF_CRCP) ? " CRCP" : "",
- (t & CPUP_CONF_BTM) ? " BTM" : "");
-
- t = sw_read_reg(SWITCH_REG_PORT_CONF0);
- SW_DBG("port_conf0: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_PORT_CONF1);
- SW_DBG("port_conf1: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_PORT_CONF2);
- SW_DBG("port_conf2: %08X\n", t);
-
- t = sw_read_reg(SWITCH_REG_VLAN_G1);
- SW_DBG("vlan g1: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_VLAN_G2);
- SW_DBG("vlan g2: %08X\n", t);
-
- t = sw_read_reg(SWITCH_REG_BW_CNTL0);
- SW_DBG("bw_cntl0: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_BW_CNTL1);
- SW_DBG("bw_cntl1: %08X\n", t);
-
- t = sw_read_reg(SWITCH_REG_PHY_CNTL0);
- SW_DBG("phy_cntl0: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_PHY_CNTL1);
- SW_DBG("phy_cntl1: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_PHY_CNTL2);
- SW_DBG("phy_cntl2: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
- SW_DBG("phy_cntl3: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_PHY_CNTL4);
- SW_DBG("phy_cntl4: %08X\n", t);
-
- t = sw_read_reg(SWITCH_REG_INT_STATUS);
- sw_dump_intr_mask("int_status: ", t);
-
- t = sw_read_reg(SWITCH_REG_INT_MASK);
- sw_dump_intr_mask("int_mask: ", t);
-
- t = sw_read_reg(SWITCH_REG_SHDA);
- SW_DBG("shda: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_SLDA);
- SW_DBG("slda: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_RHDA);
- SW_DBG("rhda: %08X\n", t);
- t = sw_read_reg(SWITCH_REG_RLDA);
- SW_DBG("rlda: %08X\n", t);
-}
-#else
-static inline void sw_dump_desc(char *label, struct dma_desc *desc, int tx) {}
-static void sw_dump_intr_mask(char *label, u32 mask) {}
-static inline void sw_dump_regs(void) {}
-#endif /* CONFIG_ADM5120_SWITCH_DEBUG */
-
-/* ------------------------------------------------------------------------ */
-
-static inline void adm5120_rx_dma_update(struct dma_desc *desc,
- struct sk_buff *skb, int end)
-{
- desc->misc = 0;
- desc->buf2 = 0;
- desc->buflen = RX_MAX_PKTLEN;
- desc->buf1 = DESC_ADDR(skb->data) |
- DESC_OWN | (end ? DESC_EOR : 0);
-}
-
-static void adm5120_switch_rx_refill(void)
-{
- unsigned int entry;
-
- for (; cur_rxl - dirty_rxl > 0; dirty_rxl++) {
- struct dma_desc *desc;
- struct sk_buff *skb;
-
- entry = dirty_rxl % RX_RING_SIZE;
- desc = &rxl_descs[entry];
-
- skb = rxl_skbuff[entry];
- if (skb == NULL) {
- skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC);
- if (skb) {
- skb_reserve(skb, SKB_RESERVE_LEN);
- rxl_skbuff[entry] = skb;
- } else {
- SW_ERR("no memory for skb\n");
- desc->buflen = 0;
- desc->buf2 = 0;
- desc->misc = 0;
- desc->buf1 = (desc->buf1 & DESC_EOR) | DESC_OWN;
- break;
- }
- }
-
- desc->buf2 = 0;
- desc->buflen = RX_MAX_PKTLEN;
- desc->misc = 0;
- desc->buf1 = (desc->buf1 & DESC_EOR) | DESC_OWN |
- DESC_ADDR(skb->data);
- }
-}
-
-static int adm5120_switch_rx(int limit)
-{
- unsigned int done = 0;
-
- SW_DBG("rx start, limit=%d, cur_rxl=%u, dirty_rxl=%u\n",
- limit, cur_rxl, dirty_rxl);
-
- while (done < limit) {
- int entry = cur_rxl % RX_RING_SIZE;
- struct dma_desc *desc = &rxl_descs[entry];
- struct net_device *rdev;
- unsigned int port;
-
- if (desc->buf1 & DESC_OWN)
- break;
-
- if (dirty_rxl + RX_RING_SIZE == cur_rxl)
- break;
-
- port = desc_get_srcport(desc);
- rdev = adm5120_port[port];
-
- SW_DBG("rx descriptor %u, desc=%p, skb=%p\n", entry, desc,
- rxl_skbuff[entry]);
-
- if ((rdev) && netif_running(rdev)) {
- struct sk_buff *skb = rxl_skbuff[entry];
- int pktlen;
-
- pktlen = desc_get_pktlen(desc);
- pktlen -= ETH_CSUM_LEN;
-
- if ((pktlen == 0) || desc_ipcsum_fail(desc)) {
- rdev->stats.rx_errors++;
- if (pktlen == 0)
- rdev->stats.rx_length_errors++;
- if (desc_ipcsum_fail(desc))
- rdev->stats.rx_crc_errors++;
- SW_DBG("rx error, recycling skb %u\n", entry);
- } else {
- skb_put(skb, pktlen);
-
- skb->dev = rdev;
- skb->protocol = eth_type_trans(skb, rdev);
- skb->ip_summed = CHECKSUM_UNNECESSARY;
-
- dma_cache_wback_inv((unsigned long)skb->data,
- skb->len);
-
-#ifdef CONFIG_ADM5120_SWITCH_NAPI
- netif_receive_skb(skb);
-#else
- netif_rx(skb);
-#endif
-
- rdev->last_rx = jiffies;
- rdev->stats.rx_packets++;
- rdev->stats.rx_bytes += pktlen;
-
- rxl_skbuff[entry] = NULL;
- done++;
- }
- } else {
- SW_DBG("no rx device, recycling skb %u\n", entry);
- }
-
- cur_rxl++;
- if (cur_rxl - dirty_rxl > RX_RING_SIZE / 4)
- adm5120_switch_rx_refill();
- }
-
- adm5120_switch_rx_refill();
-
- SW_DBG("rx finished, cur_rxl=%u, dirty_rxl=%u, processed %d\n",
- cur_rxl, dirty_rxl, done);
-
- return done;
-}
-
-static void adm5120_switch_tx(void)
-{
- unsigned int entry;
-
- spin_lock(&tx_lock);
- entry = dirty_txl % TX_RING_SIZE;
- while (dirty_txl != cur_txl) {
- struct dma_desc *desc = &txl_descs[entry];
- struct sk_buff *skb = txl_skbuff[entry];
-
- if (desc->buf1 & DESC_OWN)
- break;
-
- if (netif_running(skb->dev)) {
- skb->dev->stats.tx_bytes += skb->len;
- skb->dev->stats.tx_packets++;
- }
-
- dev_kfree_skb_irq(skb);
- txl_skbuff[entry] = NULL;
- entry = (++dirty_txl) % TX_RING_SIZE;
- }
-
- if ((cur_txl - dirty_txl) < TX_QUEUE_LEN - 4) {
- int i;
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- if (!adm5120_devs[i])
- continue;
- netif_wake_queue(adm5120_devs[i]);
- }
- }
- spin_unlock(&tx_lock);
-}
-
-#ifdef CONFIG_ADM5120_SWITCH_NAPI
-static int adm5120_if_poll(struct napi_struct *napi, int limit)
-{
- struct adm5120_if_priv *priv = container_of(napi,
- struct adm5120_if_priv, napi);
- struct net_device *dev __maybe_unused = priv->dev;
- int done;
- u32 status;
-
- sw_int_ack(SWITCH_INTS_POLL);
-
- SW_DBG("%s: processing TX ring\n", dev->name);
- adm5120_switch_tx();
-
- SW_DBG("%s: processing RX ring\n", dev->name);
- done = adm5120_switch_rx(limit);
-
- status = sw_int_status() & SWITCH_INTS_POLL;
- if ((done < limit) && (!status)) {
- SW_DBG("disable polling mode for %s\n", dev->name);
- napi_complete(napi);
- sw_int_unmask(SWITCH_INTS_POLL);
- return 0;
- }
-
- SW_DBG("%s still in polling mode, done=%d, status=%x\n",
- dev->name, done, status);
- return 1;
-}
-#endif /* CONFIG_ADM5120_SWITCH_NAPI */
-
-
-static irqreturn_t adm5120_switch_irq(int irq, void *dev_id)
-{
- u32 status;
-
- status = sw_int_status();
- status &= SWITCH_INTS_ALL;
- if (!status)
- return IRQ_NONE;
-
-#ifdef CONFIG_ADM5120_SWITCH_NAPI
- sw_int_ack(status & ~SWITCH_INTS_POLL);
-
- if (status & SWITCH_INTS_POLL) {
- struct net_device *dev = dev_id;
- struct adm5120_if_priv *priv = netdev_priv(dev);
-
- sw_dump_intr_mask("poll ints", status);
- SW_DBG("enable polling mode for %s\n", dev->name);
- sw_int_mask(SWITCH_INTS_POLL);
- napi_schedule(&priv->napi);
- }
-#else
- sw_int_ack(status);
-
- if (status & (SWITCH_INT_RLD | SWITCH_INT_LDF))
- adm5120_switch_rx(RX_RING_SIZE);
-
- if (status & SWITCH_INT_SLD)
- adm5120_switch_tx();
-#endif
-
- return IRQ_HANDLED;
-}
-
-static void adm5120_set_bw(char *matrix)
-{
- unsigned long val;
-
- /* Port 0 to 3 are set using the bandwidth control 0 register */
- val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
- sw_write_reg(SWITCH_REG_BW_CNTL0, val);
-
- /* Port 4 and 5 are set using the bandwidth control 1 register */
- val = matrix[4];
- if (matrix[5] == 1)
- sw_write_reg(SWITCH_REG_BW_CNTL1, val | 0x80000000);
- else
- sw_write_reg(SWITCH_REG_BW_CNTL1, val & ~0x8000000);
-
- SW_DBG("D: ctl0 0x%ux, ctl1 0x%ux\n", sw_read_reg(SWITCH_REG_BW_CNTL0),
- sw_read_reg(SWITCH_REG_BW_CNTL1));
-}
-
-static void adm5120_switch_tx_ring_reset(struct dma_desc *desc,
- struct sk_buff **skbl, int num)
-{
- memset(desc, 0, num * sizeof(*desc));
- desc[num-1].buf1 |= DESC_EOR;
- memset(skbl, 0, sizeof(struct skb *) * num);
-
- cur_txl = 0;
- dirty_txl = 0;
-}
-
-static void adm5120_switch_rx_ring_reset(struct dma_desc *desc,
- struct sk_buff **skbl, int num)
-{
- int i;
-
- memset(desc, 0, num * sizeof(*desc));
- for (i = 0; i < num; i++) {
- skbl[i] = dev_alloc_skb(SKB_ALLOC_LEN);
- if (!skbl[i]) {
- i = num;
- break;
- }
- skb_reserve(skbl[i], SKB_RESERVE_LEN);
- adm5120_rx_dma_update(&desc[i], skbl[i], (num - 1 == i));
- }
-
- cur_rxl = 0;
- dirty_rxl = 0;
-}
-
-static int adm5120_switch_tx_ring_alloc(void)
-{
- int err;
-
- txl_descs = dma_alloc_coherent(NULL, TX_DESCS_SIZE, &txl_descs_dma,
- GFP_ATOMIC);
- if (!txl_descs) {
- err = -ENOMEM;
- goto err;
- }
-
- txl_skbuff = kzalloc(TX_SKBS_SIZE, GFP_KERNEL);
- if (!txl_skbuff) {
- err = -ENOMEM;
- goto err;
- }
-
- return 0;
-
-err:
- return err;
-}
-
-static void adm5120_switch_tx_ring_free(void)
-{
- int i;
-
- if (txl_skbuff) {
- for (i = 0; i < TX_RING_SIZE; i++)
- if (txl_skbuff[i])
- kfree_skb(txl_skbuff[i]);
- kfree(txl_skbuff);
- }
-
- if (txl_descs)
- dma_free_coherent(NULL, TX_DESCS_SIZE, txl_descs,
- txl_descs_dma);
-}
-
-static int adm5120_switch_rx_ring_alloc(void)
-{
- int err;
- int i;
-
- /* init RX ring */
- rxl_descs = dma_alloc_coherent(NULL, RX_DESCS_SIZE, &rxl_descs_dma,
- GFP_ATOMIC);
- if (!rxl_descs) {
- err = -ENOMEM;
- goto err;
- }
-
- rxl_skbuff = kzalloc(RX_SKBS_SIZE, GFP_KERNEL);
- if (!rxl_skbuff) {
- err = -ENOMEM;
- goto err;
- }
-
- for (i = 0; i < RX_RING_SIZE; i++) {
- struct sk_buff *skb;
- skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC);
- if (!skb) {
- err = -ENOMEM;
- goto err;
- }
- rxl_skbuff[i] = skb;
- skb_reserve(skb, SKB_RESERVE_LEN);
- }
-
- return 0;
-
-err:
- return err;
-}
-
-static void adm5120_switch_rx_ring_free(void)
-{
- int i;
-
- if (rxl_skbuff) {
- for (i = 0; i < RX_RING_SIZE; i++)
- if (rxl_skbuff[i])
- kfree_skb(rxl_skbuff[i]);
- kfree(rxl_skbuff);
- }
-
- if (rxl_descs)
- dma_free_coherent(NULL, RX_DESCS_SIZE, rxl_descs,
- rxl_descs_dma);
-}
-
-static void adm5120_write_mac(struct net_device *dev)
-{
- struct adm5120_if_priv *priv = netdev_priv(dev);
- unsigned char *mac = dev->dev_addr;
- u32 t;
-
- t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT) |
- (mac[4] << MAC_WT1_MAC4_SHIFT) | (mac[5] << MAC_WT1_MAC5_SHIFT);
- sw_write_reg(SWITCH_REG_MAC_WT1, t);
-
- t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) |
- MAC_WT0_MAWC | MAC_WT0_WVE | (priv->vlan_no<<3);
-
- sw_write_reg(SWITCH_REG_MAC_WT0, t);
-
- while (!(sw_read_reg(SWITCH_REG_MAC_WT0) & MAC_WT0_MWD))
- ;
-}
-
-static void adm5120_set_vlan(char *matrix)
-{
- unsigned long val;
- int vlan_port, port;
-
- val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
- sw_write_reg(SWITCH_REG_VLAN_G1, val);
- val = matrix[4] + (matrix[5]<<8);
- sw_write_reg(SWITCH_REG_VLAN_G2, val);
-
- /* Now set/update the port vs. device lookup table */
- for (port = 0; port < SWITCH_NUM_PORTS; port++) {
- for (vlan_port = 0; vlan_port < SWITCH_NUM_PORTS && !(matrix[vlan_port] & (0x00000001 << port)); vlan_port++)
- ;
- if (vlan_port < SWITCH_NUM_PORTS)
- adm5120_port[port] = adm5120_devs[vlan_port];
- else
- adm5120_port[port] = NULL;
- }
-}
-
-static void adm5120_switch_set_vlan_mac(unsigned int vlan, unsigned char *mac)
-{
- u32 t;
-
- t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT)
- | (mac[4] << MAC_WT1_MAC4_SHIFT)
- | (mac[5] << MAC_WT1_MAC5_SHIFT);
- sw_write_reg(SWITCH_REG_MAC_WT1, t);
-
- t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) |
- MAC_WT0_MAWC | MAC_WT0_WVE | (vlan << MAC_WT0_WVN_SHIFT) |
- (MAC_WT0_WAF_STATIC << MAC_WT0_WAF_SHIFT);
- sw_write_reg(SWITCH_REG_MAC_WT0, t);
-
- do {
- t = sw_read_reg(SWITCH_REG_MAC_WT0);
- } while ((t & MAC_WT0_MWD) == 0);
-}
-
-static void adm5120_switch_set_vlan_ports(unsigned int vlan, u32 ports)
-{
- unsigned int reg;
- u32 t;
-
- if (vlan < 4)
- reg = SWITCH_REG_VLAN_G1;
- else {
- vlan -= 4;
- reg = SWITCH_REG_VLAN_G2;
- }
-
- t = sw_read_reg(reg);
- t &= ~(0xFF << (vlan*8));
- t |= (ports << (vlan*8));
- sw_write_reg(reg, t);
-}
-
-/* ------------------------------------------------------------------------ */
-
-#ifdef CONFIG_ADM5120_SWITCH_NAPI
-static inline void adm5120_if_napi_enable(struct net_device *dev)
-{
- struct adm5120_if_priv *priv = netdev_priv(dev);
- napi_enable(&priv->napi);
-}
-
-static inline void adm5120_if_napi_disable(struct net_device *dev)
-{
- struct adm5120_if_priv *priv = netdev_priv(dev);
- napi_disable(&priv->napi);
-}
-#else
-static inline void adm5120_if_napi_enable(struct net_device *dev) {}
-static inline void adm5120_if_napi_disable(struct net_device *dev) {}
-#endif /* CONFIG_ADM5120_SWITCH_NAPI */
-
-static int adm5120_if_open(struct net_device *dev)
-{
- u32 t;
- int err;
- int i;
-
- adm5120_if_napi_enable(dev);
-
- err = request_irq(dev->irq, adm5120_switch_irq, IRQF_SHARED,
- dev->name, dev);
- if (err) {
- SW_ERR("unable to get irq for %s\n", dev->name);
- goto err;
- }
-
- if (!sw_used++)
- /* enable interrupts on first open */
- sw_int_unmask(SWITCH_INTS_USED);
-
- /* enable (additional) port */
- t = sw_read_reg(SWITCH_REG_PORT_CONF0);
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- if (dev == adm5120_devs[i])
- t &= ~adm5120_eth_vlans[i];
- }
- sw_write_reg(SWITCH_REG_PORT_CONF0, t);
-
- netif_start_queue(dev);
-
- return 0;
-
-err:
- adm5120_if_napi_disable(dev);
- return err;
-}
-
-static int adm5120_if_stop(struct net_device *dev)
-{
- u32 t;
- int i;
-
- netif_stop_queue(dev);
- adm5120_if_napi_disable(dev);
-
- /* disable port if not assigned to other devices */
- t = sw_read_reg(SWITCH_REG_PORT_CONF0);
- t |= SWITCH_PORTS_NOCPU;
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- if ((dev != adm5120_devs[i]) && netif_running(adm5120_devs[i]))
- t &= ~adm5120_eth_vlans[i];
- }
- sw_write_reg(SWITCH_REG_PORT_CONF0, t);
-
- if (!--sw_used)
- sw_int_mask(SWITCH_INTS_USED);
-
- free_irq(dev->irq, dev);
-
- return 0;
-}
-
-static int adm5120_if_hard_start_xmit(struct sk_buff *skb,
- struct net_device *dev)
-{
- struct dma_desc *desc;
- struct adm5120_if_priv *priv = netdev_priv(dev);
- unsigned int entry;
- unsigned long data;
- int i;
-
- /* lock switch irq */
- spin_lock_irq(&tx_lock);
-
- /* calculate the next TX descriptor entry. */
- entry = cur_txl % TX_RING_SIZE;
-
- desc = &txl_descs[entry];
- if (desc->buf1 & DESC_OWN) {
- /* We want to write a packet but the TX queue is still
- * occupied by the DMA. We are faster than the DMA... */
- SW_DBG("%s unable to transmit, packet dopped\n", dev->name);
- dev_kfree_skb(skb);
- dev->stats.tx_dropped++;
- return 0;
- }
-
- txl_skbuff[entry] = skb;
- data = (desc->buf1 & DESC_EOR);
- data |= DESC_ADDR(skb->data);
-
- desc->misc =
- ((skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len) << DESC_PKTLEN_SHIFT) |
- (0x1 << priv->vlan_no);
-
- desc->buflen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
-
- desc->buf1 = data | DESC_OWN;
- sw_write_reg(SWITCH_REG_SEND_TRIG, SEND_TRIG_STL);
-
- cur_txl++;
- if (cur_txl == dirty_txl + TX_QUEUE_LEN) {
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- if (!adm5120_devs[i])
- continue;
- netif_stop_queue(adm5120_devs[i]);
- }
- }
-
- dev->trans_start = jiffies;
-
- spin_unlock_irq(&tx_lock);
-
- return 0;
-}
-
-static void adm5120_if_tx_timeout(struct net_device *dev)
-{
- SW_INFO("TX timeout on %s\n", dev->name);
-}
-
-static void adm5120_if_set_rx_mode(struct net_device *dev)
-{
- struct adm5120_if_priv *priv = netdev_priv(dev);
- u32 ports;
- u32 t;
-
- ports = adm5120_eth_vlans[priv->vlan_no] & SWITCH_PORTS_NOCPU;
-
- t = sw_read_reg(SWITCH_REG_CPUP_CONF);
- if (dev->flags & IFF_PROMISC)
- /* enable unknown packets */
- t &= ~(ports << CPUP_CONF_DUNP_SHIFT);
- else
- /* disable unknown packets */
- t |= (ports << CPUP_CONF_DUNP_SHIFT);
-
- if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI ||
- netdev_mc_count(dev))
- /* enable multicast packets */
- t &= ~(ports << CPUP_CONF_DMCP_SHIFT);
- else
- /* disable multicast packets */
- t |= (ports << CPUP_CONF_DMCP_SHIFT);
-
- /* If there is any port configured to be in promiscuous mode, then the */
- /* Bridge Test Mode has to be activated. This will result in */
- /* transporting also packets learned in another VLAN to be forwarded */
- /* to the CPU. */
- /* The difficult scenario is when we want to build a bridge on the CPU.*/
- /* Assume we have port0 and the CPU port in VLAN0 and port1 and the */
- /* CPU port in VLAN1. Now we build a bridge on the CPU between */
- /* VLAN0 and VLAN1. Both ports of the VLANs are set in promisc mode. */
- /* Now assume a packet with ethernet source address 99 enters port 0 */
- /* It will be forwarded to the CPU because it is unknown. Then the */
- /* bridge in the CPU will send it to VLAN1 and it goes out at port 1. */
- /* When now a packet with ethernet destination address 99 comes in at */
- /* port 1 in VLAN1, then the switch has learned that this address is */
- /* located at port 0 in VLAN0. Therefore the switch will drop */
- /* this packet. In order to avoid this and to send the packet still */
- /* to the CPU, the Bridge Test Mode has to be activated. */
-
- /* Check if there is any vlan in promisc mode. */
- if (~t & (SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT))
- t |= CPUP_CONF_BTM; /* Enable Bridge Testing Mode */
- else
- t &= ~CPUP_CONF_BTM; /* Disable Bridge Testing Mode */
-
- sw_write_reg(SWITCH_REG_CPUP_CONF, t);
-
-}
-
-static int adm5120_if_set_mac_address(struct net_device *dev, void *p)
-{
- int ret;
-
- ret = eth_mac_addr(dev, p);
- if (ret)
- return ret;
-
- adm5120_write_mac(dev);
- return 0;
-}
-
-static int adm5120_if_do_ioctl(struct net_device *dev, struct ifreq *rq,
- int cmd)
-{
- int err;
- struct adm5120_sw_info info;
- struct adm5120_if_priv *priv = netdev_priv(dev);
-
- switch (cmd) {
- case SIOCGADMINFO:
- info.magic = 0x5120;
- info.ports = adm5120_nrdevs;
- info.vlan = priv->vlan_no;
- err = copy_to_user(rq->ifr_data, &info, sizeof(info));
- if (err)
- return -EFAULT;
- break;
- case SIOCSMATRIX:
- if (!capable(CAP_NET_ADMIN))
- return -EPERM;
- err = copy_from_user(adm5120_eth_vlans, rq->ifr_data,
- sizeof(adm5120_eth_vlans));
- if (err)
- return -EFAULT;
- adm5120_set_vlan(adm5120_eth_vlans);
- break;
- case SIOCGMATRIX:
- err = copy_to_user(rq->ifr_data, adm5120_eth_vlans,
- sizeof(adm5120_eth_vlans));
- if (err)
- return -EFAULT;
- break;
- default:
- return -EOPNOTSUPP;
- }
- return 0;
-}
-
-static const struct net_device_ops adm5120sw_netdev_ops = {
- .ndo_open = adm5120_if_open,
- .ndo_stop = adm5120_if_stop,
- .ndo_start_xmit = adm5120_if_hard_start_xmit,
- .ndo_set_rx_mode = adm5120_if_set_rx_mode,
- .ndo_do_ioctl = adm5120_if_do_ioctl,
- .ndo_tx_timeout = adm5120_if_tx_timeout,
- .ndo_validate_addr = eth_validate_addr,
- .ndo_change_mtu = eth_change_mtu,
- .ndo_set_mac_address = adm5120_if_set_mac_address,
-};
-
-static struct net_device *adm5120_if_alloc(void)
-{
- struct net_device *dev;
- struct adm5120_if_priv *priv;
-
- dev = alloc_etherdev(sizeof(*priv));
- if (!dev)
- return NULL;
-
- priv = netdev_priv(dev);
- priv->dev = dev;
-
- dev->irq = ADM5120_IRQ_SWITCH;
- dev->netdev_ops = &adm5120sw_netdev_ops;
- dev->watchdog_timeo = TX_TIMEOUT;
-
-#ifdef CONFIG_ADM5120_SWITCH_NAPI
- netif_napi_add(dev, &priv->napi, adm5120_if_poll, 64);
-#endif
-
- return dev;
-}
-
-/* ------------------------------------------------------------------------ */
-
-static void adm5120_switch_cleanup(void)
-{
- int i;
-
- /* disable interrupts */
- sw_int_mask(SWITCH_INTS_ALL);
-
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- struct net_device *dev = adm5120_devs[i];
- if (dev) {
- unregister_netdev(dev);
- free_netdev(dev);
- }
- }
-
- adm5120_switch_tx_ring_free();
- adm5120_switch_rx_ring_free();
-}
-
-static int adm5120_switch_probe(struct platform_device *pdev)
-{
- u32 t;
- int i, err;
-
- adm5120_nrdevs = adm5120_eth_num_ports;
-
- t = CPUP_CONF_DCPUP | CPUP_CONF_CRCP |
- SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT |
- SWITCH_PORTS_NOCPU << CPUP_CONF_DMCP_SHIFT ;
- sw_write_reg(SWITCH_REG_CPUP_CONF, t);
-
- t = (SWITCH_PORTS_NOCPU << PORT_CONF0_EMCP_SHIFT) |
- (SWITCH_PORTS_NOCPU << PORT_CONF0_BP_SHIFT) |
- (SWITCH_PORTS_NOCPU);
- sw_write_reg(SWITCH_REG_PORT_CONF0, t);
-
- /* setup ports to Autoneg/100M/Full duplex/Auto MDIX */
- t = SWITCH_PORTS_PHY |
- (SWITCH_PORTS_PHY << PHY_CNTL2_SC_SHIFT) |
- (SWITCH_PORTS_PHY << PHY_CNTL2_DC_SHIFT) |
- (SWITCH_PORTS_PHY << PHY_CNTL2_PHYR_SHIFT) |
- (SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) |
- PHY_CNTL2_RMAE;
- sw_write_reg(SWITCH_REG_PHY_CNTL2, t);
-
- t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
- t |= PHY_CNTL3_RNT;
- sw_write_reg(SWITCH_REG_PHY_CNTL3, t);
-
- /* Force all the packets from all ports are low priority */
- sw_write_reg(SWITCH_REG_PRI_CNTL, 0);
-
- sw_int_mask(SWITCH_INTS_ALL);
- sw_int_ack(SWITCH_INTS_ALL);
-
- err = adm5120_switch_rx_ring_alloc();
- if (err)
- goto err;
-
- err = adm5120_switch_tx_ring_alloc();
- if (err)
- goto err;
-
- adm5120_switch_tx_ring_reset(txl_descs, txl_skbuff, TX_RING_SIZE);
- adm5120_switch_rx_ring_reset(rxl_descs, rxl_skbuff, RX_RING_SIZE);
-
- sw_write_reg(SWITCH_REG_SHDA, 0);
- sw_write_reg(SWITCH_REG_SLDA, KSEG1ADDR(txl_descs));
- sw_write_reg(SWITCH_REG_RHDA, 0);
- sw_write_reg(SWITCH_REG_RLDA, KSEG1ADDR(rxl_descs));
-
- for (i = 0; i < SWITCH_NUM_PORTS; i++) {
- struct net_device *dev;
- struct adm5120_if_priv *priv;
-
- dev = adm5120_if_alloc();
- if (!dev) {
- err = -ENOMEM;
- goto err;
- }
-
- adm5120_devs[i] = dev;
- priv = netdev_priv(dev);
-
- priv->vlan_no = i;
- priv->port_mask = adm5120_eth_vlans[i];
-
- memcpy(dev->dev_addr, adm5120_eth_macs[i], 6);
- adm5120_write_mac(dev);
-
- err = register_netdev(dev);
- if (err) {
- SW_INFO("%s register failed, error=%d\n",
- dev->name, err);
- goto err;
- }
- }
-
- /* setup vlan/port mapping after devs are filled up */
- adm5120_set_vlan(adm5120_eth_vlans);
-
- /* enable CPU port */
- t = sw_read_reg(SWITCH_REG_CPUP_CONF);
- t &= ~CPUP_CONF_DCPUP;
- sw_write_reg(SWITCH_REG_CPUP_CONF, t);
-
- return 0;
-
-err:
- adm5120_switch_cleanup();
-
- SW_ERR("init failed\n");
- return err;
-}
-
-static int adm5120_switch_remove(struct platform_device *pdev)
-{
- adm5120_switch_cleanup();
- return 0;
-}
-
-static struct platform_driver adm5120_switch_driver = {
- .probe = adm5120_switch_probe,
- .remove = adm5120_switch_remove,
- .driver = {
- .name = DRV_NAME,
- },
-};
-
-/* -------------------------------------------------------------------------- */
-
-static int __init adm5120_switch_mod_init(void)
-{
- int err;
-
- pr_info(DRV_DESC " version " DRV_VERSION "\n");
- err = platform_driver_register(&adm5120_switch_driver);
-
- return err;
-}
-
-static void __exit adm5120_switch_mod_exit(void)
-{
- platform_driver_unregister(&adm5120_switch_driver);
-}
-
-module_init(adm5120_switch_mod_init);
-module_exit(adm5120_switch_mod_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-MODULE_DESCRIPTION(DRV_DESC);
-MODULE_VERSION(DRV_VERSION);
+++ /dev/null
-/*
- * Defines for ADM5120 built in ethernet switch driver
- *
- * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
- *
- * Values come from ADM5120 datasheet and original ADMtek 2.4 driver,
- * Copyright ADMtek Inc.
- */
-
-#ifndef _INCLUDE_ADM5120SW_H_
-#define _INCLUDE_ADM5120SW_H_
-
-#define SIOCSMATRIX SIOCDEVPRIVATE
-#define SIOCGMATRIX (SIOCDEVPRIVATE + 1)
-#define SIOCGADMINFO (SIOCDEVPRIVATE + 2)
-
-struct adm5120_sw_info {
- u16 magic;
- u16 ports;
- u16 vlan;
-};
-
-#endif /* _INCLUDE_ADM5120SW_H_ */
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci-dbg.c
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-/*-------------------------------------------------------------------------*/
-
-static inline char *ed_typestring(int ed_type)
-{
- switch (ed_type) {
- case PIPE_CONTROL:
- return "ctrl";
- case PIPE_BULK:
- return "bulk";
- case PIPE_INTERRUPT:
- return "intr";
- case PIPE_ISOCHRONOUS:
- return "isoc";
- }
- return "(bad ed_type)";
-}
-
-static inline char *ed_statestring(int state)
-{
- switch (state) {
- case ED_IDLE:
- return "IDLE";
- case ED_UNLINK:
- return "UNLINK";
- case ED_OPER:
- return "OPER";
- }
- return "?STATE";
-}
-
-static inline char *pipestring(int pipe)
-{
- return ed_typestring(usb_pipetype(pipe));
-}
-
-static inline char *td_pidstring(u32 info)
-{
- switch (info & TD_DP) {
- case TD_DP_SETUP:
- return "SETUP";
- case TD_DP_IN:
- return "IN";
- case TD_DP_OUT:
- return "OUT";
- }
- return "?PID";
-}
-
-static inline char *td_togglestring(u32 info)
-{
- switch (info & TD_T) {
- case TD_T_DATA0:
- return "DATA0";
- case TD_T_DATA1:
- return "DATA1";
- case TD_T_CARRY:
- return "CARRY";
- }
- return "?TOGGLE";
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-
-/* debug| print the main components of an URB
- * small: 0) header + data packets 1) just header
- */
-static void __attribute__((unused))
-urb_print(struct admhcd *ahcd, struct urb *urb, char *str, int small, int status)
-{
- unsigned int pipe = urb->pipe;
-
- if (!urb->dev || !urb->dev->bus) {
- admhc_dbg(ahcd, "%s URB: no dev", str);
- return;
- }
-
-#ifndef ADMHC_VERBOSE_DEBUG
- if (status != 0)
-#endif
- admhc_dbg(ahcd, "URB-%s %p dev=%d ep=%d%s-%s flags=%x len=%d/%d "
- "stat=%d\n",
- str,
- urb,
- usb_pipedevice(pipe),
- usb_pipeendpoint(pipe),
- usb_pipeout(pipe) ? "out" : "in",
- pipestring(pipe),
- urb->transfer_flags,
- urb->actual_length,
- urb->transfer_buffer_length,
- status);
-
-#ifdef ADMHC_VERBOSE_DEBUG
- if (!small) {
- int i, len;
-
- if (usb_pipecontrol(pipe)) {
- admhc_dbg(ahcd, "setup(8):");
- for (i = 0; i < 8 ; i++)
- printk(KERN_INFO" %02x", ((__u8 *)urb->setup_packet)[i]);
- printk(KERN_INFO "\n");
- }
- if (urb->transfer_buffer_length > 0 && urb->transfer_buffer) {
- admhc_dbg(ahcd, "data(%d/%d):",
- urb->actual_length,
- urb->transfer_buffer_length);
- len = usb_pipeout(pipe) ?
- urb->transfer_buffer_length : urb->actual_length;
- for (i = 0; i < 16 && i < len; i++)
- printk(KERN_INFO " %02x", ((__u8 *)urb->transfer_buffer)[i]);
- printk(KERN_INFO "%s stat:%d\n", i < len ? "..." : "", status);
- }
- }
-#endif /* ADMHC_VERBOSE_DEBUG */
-}
-
-#define admhc_dbg_sw(ahcd, next, size, format, arg...) \
- do { \
- if (next) { \
- unsigned s_len; \
- s_len = scnprintf(*next, *size, format, ## arg); \
- *size -= s_len; *next += s_len; \
- } else \
- admhc_dbg(ahcd, format, ## arg); \
- } while (0);
-
-
-static void admhc_dump_intr_mask(struct admhcd *ahcd, char *label, u32 mask,
- char **next, unsigned *size)
-{
- admhc_dbg_sw(ahcd, next, size, "%s 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n",
- label,
- mask,
- (mask & ADMHC_INTR_INTA) ? " INTA" : "",
- (mask & ADMHC_INTR_FATI) ? " FATI" : "",
- (mask & ADMHC_INTR_SWI) ? " SWI" : "",
- (mask & ADMHC_INTR_TDC) ? " TDC" : "",
- (mask & ADMHC_INTR_FNO) ? " FNO" : "",
- (mask & ADMHC_INTR_SO) ? " SO" : "",
- (mask & ADMHC_INTR_INSM) ? " INSM" : "",
- (mask & ADMHC_INTR_BABI) ? " BABI" : "",
- (mask & ADMHC_INTR_7) ? " !7!" : "",
- (mask & ADMHC_INTR_6) ? " !6!" : "",
- (mask & ADMHC_INTR_RESI) ? " RESI" : "",
- (mask & ADMHC_INTR_SOFI) ? " SOFI" : ""
- );
-}
-
-static void maybe_print_eds(struct admhcd *ahcd, char *label, u32 value,
- char **next, unsigned *size)
-{
- if (value)
- admhc_dbg_sw(ahcd, next, size, "%s %08x\n", label, value);
-}
-
-static char *buss2string(int state)
-{
- switch (state) {
- case ADMHC_BUSS_RESET:
- return "reset";
- case ADMHC_BUSS_RESUME:
- return "resume";
- case ADMHC_BUSS_OPER:
- return "operational";
- case ADMHC_BUSS_SUSPEND:
- return "suspend";
- }
- return "?state";
-}
-
-static void
-admhc_dump_status(struct admhcd *ahcd, char **next, unsigned *size)
-{
- struct admhcd_regs __iomem *regs = ahcd->regs;
- u32 temp;
-
- temp = admhc_readl(ahcd, ®s->gencontrol);
- admhc_dbg_sw(ahcd, next, size,
- "gencontrol 0x%08x%s%s%s%s\n",
- temp,
- (temp & ADMHC_CTRL_UHFE) ? " UHFE" : "",
- (temp & ADMHC_CTRL_SIR) ? " SIR" : "",
- (temp & ADMHC_CTRL_DMAA) ? " DMAA" : "",
- (temp & ADMHC_CTRL_SR) ? " SR" : ""
- );
-
- temp = admhc_readl(ahcd, ®s->host_control);
- admhc_dbg_sw(ahcd, next, size,
- "host_control 0x%08x BUSS=%s%s\n",
- temp,
- buss2string(temp & ADMHC_HC_BUSS),
- (temp & ADMHC_HC_DMAE) ? " DMAE" : ""
- );
-
- admhc_dump_intr_mask(ahcd, "int_status",
- admhc_readl(ahcd, ®s->int_status),
- next, size);
- admhc_dump_intr_mask(ahcd, "int_enable",
- admhc_readl(ahcd, ®s->int_enable),
- next, size);
-
- maybe_print_eds(ahcd, "hosthead",
- admhc_readl(ahcd, ®s->hosthead), next, size);
-}
-
-#define dbg_port_sw(hc, num, value, next, size) \
- admhc_dbg_sw(hc, next, size, \
- "portstatus [%d] " \
- "0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \
- num, temp, \
- (temp & ADMHC_PS_PRSC) ? " PRSC" : "", \
- (temp & ADMHC_PS_OCIC) ? " OCIC" : "", \
- (temp & ADMHC_PS_PSSC) ? " PSSC" : "", \
- (temp & ADMHC_PS_PESC) ? " PESC" : "", \
- (temp & ADMHC_PS_CSC) ? " CSC" : "", \
- \
- (temp & ADMHC_PS_LSDA) ? " LSDA" : "", \
- (temp & ADMHC_PS_PPS) ? " PPS" : "", \
- (temp & ADMHC_PS_PRS) ? " PRS" : "", \
- (temp & ADMHC_PS_POCI) ? " POCI" : "", \
- (temp & ADMHC_PS_PSS) ? " PSS" : "", \
- \
- (temp & ADMHC_PS_PES) ? " PES" : "", \
- (temp & ADMHC_PS_CCS) ? " CCS" : "" \
- );
-
-
-static void
-admhc_dump_roothub(
- struct admhcd *ahcd,
- int verbose,
- char **next,
- unsigned *size)
-{
- u32 temp, i;
-
- temp = admhc_read_rhdesc(ahcd);
- if (temp == ~(u32)0)
- return;
-
- if (verbose) {
- admhc_dbg_sw(ahcd, next, size,
- "rhdesc %08x%s%s%s%s%s%s PPCM=%02x%s%s%s%s NUMP=%d(%d)\n",
- temp,
- (temp & ADMHC_RH_CRWE) ? " CRWE" : "",
- (temp & ADMHC_RH_OCIC) ? " OCIC" : "",
- (temp & ADMHC_RH_LPSC) ? " LPSC" : "",
- (temp & ADMHC_RH_LPSC) ? " DRWE" : "",
- (temp & ADMHC_RH_LPSC) ? " OCI" : "",
- (temp & ADMHC_RH_LPSC) ? " LPS" : "",
- ((temp & ADMHC_RH_PPCM) >> 16),
- (temp & ADMHC_RH_NOCP) ? " NOCP" : "",
- (temp & ADMHC_RH_OCPM) ? " OCPM" : "",
- (temp & ADMHC_RH_NPS) ? " NPS" : "",
- (temp & ADMHC_RH_PSM) ? " PSM" : "",
- (temp & ADMHC_RH_NUMP), ahcd->num_ports
- );
- }
-
- for (i = 0; i < ahcd->num_ports; i++) {
- temp = admhc_read_portstatus(ahcd, i);
- dbg_port_sw(ahcd, i, temp, next, size);
- }
-}
-
-static void admhc_dump(struct admhcd *ahcd, int verbose)
-{
- admhc_dbg(ahcd, "ADMHC ahcd state\n");
-
- /* dumps some of the state we know about */
- admhc_dump_status(ahcd, NULL, NULL);
- admhc_dbg(ahcd, "current frame #%04x\n",
- admhc_frame_no(ahcd));
-
- admhc_dump_roothub(ahcd, verbose, NULL, NULL);
-}
-
-static const char data0[] = "DATA0";
-static const char data1[] = "DATA1";
-
-static void admhc_dump_td(const struct admhcd *ahcd, const char *label,
- const struct td *td)
-{
- u32 tmp;
-
- admhc_dbg(ahcd, "%s td %p; urb %p index %d; hwNextTD %08x\n",
- label, td,
- td->urb, td->index,
- hc32_to_cpup(ahcd, &td->hwNextTD));
-
- tmp = hc32_to_cpup(ahcd, &td->hwINFO);
- admhc_dbg(ahcd, " status %08x%s CC=%x EC=%d %s %s ISI=%x FN=%x\n",
- tmp,
- (tmp & TD_OWN) ? " OWN" : "",
- TD_CC_GET(tmp),
- TD_EC_GET(tmp),
- td_togglestring(tmp),
- td_pidstring(tmp),
- TD_ISI_GET(tmp),
- TD_FN_GET(tmp));
-
- tmp = hc32_to_cpup(ahcd, &td->hwCBL);
- admhc_dbg(ahcd, " dbp %08x; cbl %08x; LEN=%d%s\n",
- hc32_to_cpup(ahcd, &td->hwDBP),
- tmp,
- TD_BL_GET(tmp),
- (tmp & TD_IE) ? " IE" : "");
-}
-
-/* caller MUST own hcd spinlock if verbose is set! */
-static void __attribute__((unused))
-admhc_dump_ed(const struct admhcd *ahcd, const char *label,
- const struct ed *ed, int verbose)
-{
- u32 tmp = hc32_to_cpu(ahcd, ed->hwINFO);
-
- admhc_dbg(ahcd, "%s ed %p %s type %s; next ed %08x\n",
- label,
- ed, ed_statestring(ed->state), ed_typestring(ed->type),
- hc32_to_cpup(ahcd, &ed->hwNextED));
-
- admhc_dbg(ahcd, " info %08x MAX=%d%s%s%s%s EP=%d DEV=%d\n", tmp,
- ED_MPS_GET(tmp),
- (tmp & ED_ISO) ? " ISO" : "",
- (tmp & ED_SKIP) ? " SKIP" : "",
- (tmp & ED_SPEED_FULL) ? " FULL" : " LOW",
- (tmp & ED_INT) ? " INT" : "",
- ED_EN_GET(tmp),
- ED_FA_GET(tmp));
-
- tmp = hc32_to_cpup(ahcd, &ed->hwHeadP);
- admhc_dbg(ahcd, " tds: head %08x tail %08x %s%s%s\n",
- tmp & TD_MASK,
- hc32_to_cpup(ahcd, &ed->hwTailP),
- (tmp & ED_C) ? data1 : data0,
- (tmp & ED_H) ? " HALT" : "",
- verbose ? " td list follows" : " (not listing)");
-
- if (verbose) {
- struct list_head *tmp;
-
- /* use ed->td_list because HC concurrently modifies
- * hwNextTD as it accumulates ed_donelist.
- */
- list_for_each(tmp, &ed->td_list) {
- struct td *td;
- td = list_entry(tmp, struct td, td_list);
- admhc_dump_td(ahcd, " ->", td);
- }
- }
-}
-
-#else /* ifdef DEBUG */
-
-static inline void urb_print(struct admhcd *ahcd, struct urb * urb, char * str,
- int small, int status) {}
-static inline void admhc_dump_ed(const struct admhcd *ahcd, const char *label,
- const struct ed *ed, int verbose) {}
-static inline void admhc_dump_td(const struct admhcd *ahcd, const char *label,
- const struct td *td) {}
-static inline void admhc_dump(struct admhcd *ahcd, int verbose) {}
-
-#undef ADMHC_VERBOSE_DEBUG
-
-#endif /* DEBUG */
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef STUB_DEBUG_FILES
-
-static inline void create_debug_files(struct admhcd *bus) { }
-static inline void remove_debug_files(struct admhcd *bus) { }
-
-#else
-
-static int debug_async_open(struct inode *, struct file *);
-static int debug_periodic_open(struct inode *, struct file *);
-static int debug_registers_open(struct inode *, struct file *);
-static ssize_t debug_output(struct file*, char __user*, size_t, loff_t*);
-static int debug_close(struct inode *, struct file *);
-
-static const struct file_operations debug_async_fops = {
- .owner = THIS_MODULE,
- .open = debug_async_open,
- .read = debug_output,
- .release = debug_close,
- .llseek = default_llseek,
-};
-static const struct file_operations debug_periodic_fops = {
- .owner = THIS_MODULE,
- .open = debug_periodic_open,
- .read = debug_output,
- .release = debug_close,
- .llseek = default_llseek,
-};
-static const struct file_operations debug_registers_fops = {
- .owner = THIS_MODULE,
- .open = debug_registers_open,
- .read = debug_output,
- .release = debug_close,
- .llseek = default_llseek,
-};
-
-static struct dentry *admhc_debug_root;
-
-struct debug_buffer {
- ssize_t (*fill_func)(struct debug_buffer *); /* fill method */
- struct admhcd *ahcd;
- struct mutex mutex; /* protect filling of buffer */
- size_t count; /* number of characters filled into buffer */
- char *page;
-};
-
-static ssize_t
-show_list(struct admhcd *ahcd, char *buf, size_t count, struct ed *ed)
-{
- unsigned temp;
- unsigned size = count;
-
- if (!ed)
- return 0;
-
- /* dump a snapshot of the bulk or control schedule */
- while (ed) {
- u32 info = hc32_to_cpu(ahcd, ed->hwINFO);
- u32 headp = hc32_to_cpu(ahcd, ed->hwHeadP);
- u32 tailp = hc32_to_cpu(ahcd, ed->hwTailP);
- struct list_head *entry;
- struct td *td;
-
- temp = scnprintf(buf, size,
- "ed/%p %s %s %cs dev%d ep%d %s%smax %d %08x%s%s %s"
- " h:%08x t:%08x",
- ed,
- ed_statestring(ed->state),
- ed_typestring(ed->type),
- (info & ED_SPEED_FULL) ? 'f' : 'l',
- info & ED_FA_MASK,
- (info >> ED_EN_SHIFT) & ED_EN_MASK,
- (info & ED_INT) ? "INT " : "",
- (info & ED_ISO) ? "ISO " : "",
- (info >> ED_MPS_SHIFT) & ED_MPS_MASK ,
- info,
- (info & ED_SKIP) ? " S" : "",
- (headp & ED_H) ? " H" : "",
- (headp & ED_C) ? data1 : data0,
- headp & ED_MASK, tailp);
- size -= temp;
- buf += temp;
-
- list_for_each(entry, &ed->td_list) {
- u32 dbp, cbl;
-
- td = list_entry(entry, struct td, td_list);
- info = hc32_to_cpup(ahcd, &td->hwINFO);
- dbp = hc32_to_cpup(ahcd, &td->hwDBP);
- cbl = hc32_to_cpup(ahcd, &td->hwCBL);
-
- temp = scnprintf(buf, size,
- "\n\ttd/%p %s %d %s%scc=%x urb %p (%08x,%08x)",
- td,
- td_pidstring(info),
- TD_BL_GET(cbl),
- (info & TD_OWN) ? "" : "DONE ",
- (cbl & TD_IE) ? "IE " : "",
- TD_CC_GET(info), td->urb, info, cbl);
- size -= temp;
- buf += temp;
- }
-
- temp = scnprintf(buf, size, "\n");
- size -= temp;
- buf += temp;
-
- ed = ed->ed_next;
- }
-
- return count - size;
-}
-
-static ssize_t fill_async_buffer(struct debug_buffer *buf)
-{
- struct admhcd *ahcd;
- size_t temp;
- unsigned long flags;
-
- ahcd = buf->ahcd;
-
- spin_lock_irqsave(&ahcd->lock, flags);
- temp = show_list(ahcd, buf->page, PAGE_SIZE, ahcd->ed_head);
- spin_unlock_irqrestore(&ahcd->lock, flags);
-
- return temp;
-}
-
-
-#define DBG_SCHED_LIMIT 64
-
-static ssize_t fill_periodic_buffer(struct debug_buffer *buf)
-{
- struct admhcd *ahcd;
- struct ed **seen, *ed;
- unsigned long flags;
- unsigned temp, size, seen_count;
- char *next;
- unsigned i;
-
- seen = kmalloc(DBG_SCHED_LIMIT * sizeof(*seen), GFP_ATOMIC);
- if (!seen)
- return 0;
- seen_count = 0;
-
- ahcd = buf->ahcd;
- next = buf->page;
- size = PAGE_SIZE;
-
- temp = scnprintf(next, size, "size = %d\n", NUM_INTS);
- size -= temp;
- next += temp;
-
- /* dump a snapshot of the periodic schedule (and load) */
- spin_lock_irqsave(&ahcd->lock, flags);
- for (i = 0; i < NUM_INTS; i++) {
- ed = ahcd->periodic[i];
- if (!ed)
- continue;
-
- temp = scnprintf(next, size, "%2d [%3d]:", i, ahcd->load[i]);
- size -= temp;
- next += temp;
-
- do {
- temp = scnprintf(next, size, " ed%d/%p",
- ed->interval, ed);
- size -= temp;
- next += temp;
- for (temp = 0; temp < seen_count; temp++) {
- if (seen[temp] == ed)
- break;
- }
-
- /* show more info the first time around */
- if (temp == seen_count) {
- u32 info = hc32_to_cpu(ahcd, ed->hwINFO);
- struct list_head *entry;
- unsigned qlen = 0;
-
- /* qlen measured here in TDs, not urbs */
- list_for_each(entry, &ed->td_list)
- qlen++;
- temp = scnprintf(next, size,
- " (%cs dev%d ep%d%s qlen %u"
- " max %d %08x%s%s)",
- (info & ED_SPEED_FULL) ? 'f' : 'l',
- ED_FA_GET(info),
- ED_EN_GET(info),
- (info & ED_ISO) ? "iso" : "int",
- qlen,
- ED_MPS_GET(info),
- info,
- (info & ED_SKIP) ? " K" : "",
- (ed->hwHeadP &
- cpu_to_hc32(ahcd, ED_H)) ?
- " H" : "");
- size -= temp;
- next += temp;
-
- if (seen_count < DBG_SCHED_LIMIT)
- seen[seen_count++] = ed;
-
- ed = ed->ed_next;
-
- } else {
- /* we've seen it and what's after */
- temp = 0;
- ed = NULL;
- }
-
- } while (ed);
-
- temp = scnprintf(next, size, "\n");
- size -= temp;
- next += temp;
- }
- spin_unlock_irqrestore(&ahcd->lock, flags);
- kfree(seen);
-
- return PAGE_SIZE - size;
-}
-
-
-#undef DBG_SCHED_LIMIT
-
-static ssize_t fill_registers_buffer(struct debug_buffer *buf)
-{
- struct usb_hcd *hcd;
- struct admhcd *ahcd;
- struct admhcd_regs __iomem *regs;
- unsigned long flags;
- unsigned temp, size;
- char *next;
- u32 rdata;
-
- ahcd = buf->ahcd;
- hcd = admhc_to_hcd(ahcd);
- regs = ahcd->regs;
- next = buf->page;
- size = PAGE_SIZE;
-
- spin_lock_irqsave(&ahcd->lock, flags);
-
- /* dump driver info, then registers in spec order */
-
- admhc_dbg_sw(ahcd, &next, &size,
- "bus %s, device %s\n"
- "%s\n"
- "%s\n",
- hcd->self.controller->bus->name,
- dev_name(hcd->self.controller),
- hcd->product_desc,
- hcd_name);
-
- if (!HCD_HW_ACCESSIBLE(hcd)) {
- size -= scnprintf(next, size,
- "SUSPENDED (no register access)\n");
- goto done;
- }
-
- admhc_dump_status(ahcd, &next, &size);
-
- /* other registers mostly affect frame timings */
- rdata = admhc_readl(ahcd, ®s->fminterval);
- temp = scnprintf(next, size,
- "fmintvl 0x%08x %sFSLDP=0x%04x FI=0x%04x\n",
- rdata, (rdata & ADMHC_SFI_FIT) ? "FIT " : "",
- (rdata >> ADMHC_SFI_FSLDP_SHIFT) & ADMHC_SFI_FSLDP_MASK,
- rdata & ADMHC_SFI_FI_MASK);
- size -= temp;
- next += temp;
-
- rdata = admhc_readl(ahcd, ®s->fmnumber);
- temp = scnprintf(next, size, "fmnumber 0x%08x %sFR=0x%04x FN=%04x\n",
- rdata, (rdata & ADMHC_SFN_FRT) ? "FRT " : "",
- (rdata >> ADMHC_SFN_FR_SHIFT) & ADMHC_SFN_FR_MASK,
- rdata & ADMHC_SFN_FN_MASK);
- size -= temp;
- next += temp;
-
- /* TODO: use predefined bitmask */
- rdata = admhc_readl(ahcd, ®s->lsthresh);
- temp = scnprintf(next, size, "lsthresh 0x%04x\n",
- rdata & 0x3fff);
- size -= temp;
- next += temp;
-
- temp = scnprintf(next, size, "hub poll timer: %s\n",
- admhcd_to_hcd(ahcd)->poll_rh ? "ON" : "OFF");
- size -= temp;
- next += temp;
-
- /* roothub */
- admhc_dump_roothub(ahcd, 1, &next, &size);
-
-done:
- spin_unlock_irqrestore(&ahcd->lock, flags);
- return PAGE_SIZE - size;
-}
-
-
-static struct debug_buffer *alloc_buffer(struct admhcd *ahcd,
- ssize_t (*fill_func)(struct debug_buffer *))
-{
- struct debug_buffer *buf;
-
- buf = kzalloc(sizeof(struct debug_buffer), GFP_KERNEL);
-
- if (buf) {
- buf->ahcd = ahcd;
- buf->fill_func = fill_func;
- mutex_init(&buf->mutex);
- }
-
- return buf;
-}
-
-static int fill_buffer(struct debug_buffer *buf)
-{
- int ret = 0;
-
- if (!buf->page)
- buf->page = (char *)get_zeroed_page(GFP_KERNEL);
-
- if (!buf->page) {
- ret = -ENOMEM;
- goto out;
- }
-
- ret = buf->fill_func(buf);
-
- if (ret >= 0) {
- buf->count = ret;
- ret = 0;
- }
-
-out:
- return ret;
-}
-
-static ssize_t debug_output(struct file *file, char __user *user_buf,
- size_t len, loff_t *offset)
-{
- struct debug_buffer *buf = file->private_data;
- int ret = 0;
-
- mutex_lock(&buf->mutex);
- if (buf->count == 0) {
- ret = fill_buffer(buf);
- if (ret != 0) {
- mutex_unlock(&buf->mutex);
- goto out;
- }
- }
- mutex_unlock(&buf->mutex);
-
- ret = simple_read_from_buffer(user_buf, len, offset,
- buf->page, buf->count);
-
-out:
- return ret;
-}
-
-static int debug_close(struct inode *inode, struct file *file)
-{
- struct debug_buffer *buf = file->private_data;
-
- if (buf) {
- if (buf->page)
- free_page((unsigned long)buf->page);
- kfree(buf);
- }
-
- return 0;
-}
-
-static int debug_async_open(struct inode *inode, struct file *file)
-{
- file->private_data = alloc_buffer(inode->i_private, fill_async_buffer);
-
- return file->private_data ? 0 : -ENOMEM;
-}
-
-static int debug_periodic_open(struct inode *inode, struct file *file)
-{
- file->private_data = alloc_buffer(inode->i_private,
- fill_periodic_buffer);
-
- return file->private_data ? 0 : -ENOMEM;
-}
-
-static int debug_registers_open(struct inode *inode, struct file *file)
-{
- file->private_data = alloc_buffer(inode->i_private,
- fill_registers_buffer);
-
- return file->private_data ? 0 : -ENOMEM;
-}
-
-static inline void create_debug_files(struct admhcd *ahcd)
-{
- struct usb_bus *bus = &admhcd_to_hcd(ahcd)->self;
-
- ahcd->debug_dir = debugfs_create_dir(bus->bus_name, admhc_debug_root);
- if (!ahcd->debug_dir)
- goto dir_error;
-
- ahcd->debug_async = debugfs_create_file("async", S_IRUGO,
- ahcd->debug_dir, ahcd,
- &debug_async_fops);
- if (!ahcd->debug_async)
- goto async_error;
-
- ahcd->debug_periodic = debugfs_create_file("periodic", S_IRUGO,
- ahcd->debug_dir, ahcd,
- &debug_periodic_fops);
- if (!ahcd->debug_periodic)
- goto periodic_error;
-
- ahcd->debug_registers = debugfs_create_file("registers", S_IRUGO,
- ahcd->debug_dir, ahcd,
- &debug_registers_fops);
- if (!ahcd->debug_registers)
- goto registers_error;
-
- admhc_dbg(ahcd, "created debug files\n");
- return;
-
-registers_error:
- debugfs_remove(ahcd->debug_periodic);
-periodic_error:
- debugfs_remove(ahcd->debug_async);
-async_error:
- debugfs_remove(ahcd->debug_dir);
-dir_error:
- ahcd->debug_periodic = NULL;
- ahcd->debug_async = NULL;
- ahcd->debug_dir = NULL;
-}
-
-static inline void remove_debug_files(struct admhcd *ahcd)
-{
- debugfs_remove(ahcd->debug_registers);
- debugfs_remove(ahcd->debug_periodic);
- debugfs_remove(ahcd->debug_async);
- debugfs_remove(ahcd->debug_dir);
-}
-
-#endif
-
-/*-------------------------------------------------------------------------*/
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci-au1xxx.c
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
- * (C) Copyright 2002 Hewlett-Packard Company
- *
- * Written by Christopher Hoover <ch@hpl.hp.com>
- * Based on fragments of previous driver by Russell King et al.
- *
- * Modified for LH7A404 from ahcd-sa1111.c
- * by Durgesh Pattamatta <pattamattad@sharpsec.com>
- * Modified for AMD Alchemy Au1xxx
- * by Matt Porter <mporter@kernel.crashing.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/platform_device.h>
-#include <linux/signal.h>
-
-#include <asm/bootinfo.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-
-#ifdef DEBUG
-#define HCD_DBG(f, a...) printk(KERN_DEBUG "%s: " f, hcd_name, ## a)
-#else
-#define HCD_DBG(f, a...) do {} while (0)
-#endif
-#define HCD_ERR(f, a...) printk(KERN_ERR "%s: " f, hcd_name, ## a)
-#define HCD_INFO(f, a...) printk(KERN_INFO "%s: " f, hcd_name, ## a)
-
-/*-------------------------------------------------------------------------*/
-
-static int admhc_adm5120_probe(const struct hc_driver *driver,
- struct platform_device *dev)
-{
- int retval;
- struct usb_hcd *hcd;
- int irq;
- struct resource *regs;
-
- /* sanity checks */
- regs = platform_get_resource(dev, IORESOURCE_MEM, 0);
- if (!regs) {
- HCD_DBG("no IOMEM resource found\n");
- return -ENODEV;
- }
-
- irq = platform_get_irq(dev, 0);
- if (irq < 0) {
- HCD_DBG("no IRQ resource found\n");
- return -ENODEV;
- }
-
- hcd = usb_create_hcd(driver, &dev->dev, "ADM5120");
- if (!hcd)
- return -ENOMEM;
-
- hcd->rsrc_start = regs->start;
- hcd->rsrc_len = regs->end - regs->start + 1;
-
- if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
- HCD_DBG("request_mem_region failed\n");
- retval = -EBUSY;
- goto err_dev;
- }
-
- hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
- if (!hcd->regs) {
- HCD_DBG("ioremap failed\n");
- retval = -ENOMEM;
- goto err_mem;
- }
-
- admhc_hcd_init(hcd_to_admhcd(hcd));
-
- retval = usb_add_hcd(hcd, irq, 0);
- if (retval)
- goto err_io;
-
- return 0;
-
-err_io:
- iounmap(hcd->regs);
-err_mem:
- release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-err_dev:
- usb_put_hcd(hcd);
- return retval;
-}
-
-
-/* may be called without controller electrically present */
-/* may be called with controller, bus, and devices active */
-
-static void admhc_adm5120_remove(struct usb_hcd *hcd,
- struct platform_device *dev)
-{
- usb_remove_hcd(hcd);
- iounmap(hcd->regs);
- release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
- usb_put_hcd(hcd);
-}
-
-static int admhc_adm5120_start(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- int ret;
-
- ret = admhc_init(ahcd);
- if (ret < 0) {
- HCD_ERR("unable to init %s\n", hcd->self.bus_name);
- goto err;
- }
-
- ret = admhc_run(ahcd);
- if (ret < 0) {
- HCD_ERR("unable to run %s\n", hcd->self.bus_name);
- goto err_stop;
- }
-
- return 0;
-
-err_stop:
- admhc_stop(hcd);
-err:
- return ret;
-}
-
-static const struct hc_driver adm5120_hc_driver = {
- .description = hcd_name,
- .product_desc = "ADM5120 built-in USB 1.1 Host Controller",
- .hcd_priv_size = sizeof(struct admhcd),
-
- /*
- * generic hardware linkage
- */
- .irq = admhc_irq,
- .flags = HCD_USB11 | HCD_MEMORY,
-
- /*
- * basic lifecycle operations
- */
- .start = admhc_adm5120_start,
- .stop = admhc_stop,
- .shutdown = admhc_shutdown,
-
- /*
- * managing i/o requests and associated device resources
- */
- .urb_enqueue = admhc_urb_enqueue,
- .urb_dequeue = admhc_urb_dequeue,
- .endpoint_disable = admhc_endpoint_disable,
-
- /*
- * scheduling support
- */
- .get_frame_number = admhc_get_frame_number,
-
- /*
- * root hub support
- */
- .hub_status_data = admhc_hub_status_data,
- .hub_control = admhc_hub_control,
-#ifdef CONFIG_PM
- .bus_suspend = admhc_bus_suspend,
- .bus_resume = admhc_bus_resume,
-#endif
- .start_port_reset = admhc_start_port_reset,
-};
-
-static int usb_hcd_adm5120_probe(struct platform_device *pdev)
-{
- int ret;
-
- ret = admhc_adm5120_probe(&adm5120_hc_driver, pdev);
-
- return ret;
-}
-
-static int usb_hcd_adm5120_remove(struct platform_device *pdev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
-
- admhc_adm5120_remove(hcd, pdev);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-/* TODO */
-static int usb_hcd_adm5120_suspend(struct platform_device *dev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(dev);
-
- return 0;
-}
-
-static int usb_hcd_adm5120_resume(struct platform_device *dev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(dev);
-
- return 0;
-}
-#else
-#define usb_hcd_adm5120_suspend NULL
-#define usb_hcd_adm5120_resume NULL
-#endif /* CONFIG_PM */
-
-static struct platform_driver usb_hcd_adm5120_driver = {
- .probe = usb_hcd_adm5120_probe,
- .remove = usb_hcd_adm5120_remove,
- .shutdown = usb_hcd_platform_shutdown,
- .suspend = usb_hcd_adm5120_suspend,
- .resume = usb_hcd_adm5120_resume,
- .driver = {
- .name = "adm5120-hcd",
- .owner = THIS_MODULE,
- },
-};
-
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci-hcd.c
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
- *
- * [ Initialisation is based on Linus' ]
- * [ uhci code and gregs ahcd fragments ]
- * [ (C) Copyright 1999 Linus Torvalds ]
- * [ (C) Copyright 1999 Gregory P. Smith]
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/ioport.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/timer.h>
-#include <linux/list.h>
-#include <linux/usb.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/hcd.h>
-#include <linux/dma-mapping.h>
-#include <linux/dmapool.h>
-#include <linux/debugfs.h>
-#include <linux/io.h>
-
-#include <asm/irq.h>
-#include <asm/unaligned.h>
-#include <asm/byteorder.h>
-
-#define DRIVER_VERSION "0.27.0"
-#define DRIVER_AUTHOR "Gabor Juhos <juhosg@openwrt.org>"
-#define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
-
-/*-------------------------------------------------------------------------*/
-
-#undef ADMHC_VERBOSE_DEBUG /* not always helpful */
-
-/* For initializing controller (mask in an HCFS mode too) */
-#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
-
-#define ADMHC_INTR_INIT \
- (ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
- | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI)
-
-/*-------------------------------------------------------------------------*/
-
-static const char hcd_name[] = "admhc-hcd";
-
-#define STATECHANGE_DELAY msecs_to_jiffies(300)
-
-#include "adm5120.h"
-
-static void admhc_dump(struct admhcd *ahcd, int verbose);
-static int admhc_init(struct admhcd *ahcd);
-static void admhc_stop(struct usb_hcd *hcd);
-
-#include "adm5120-dbg.c"
-#include "adm5120-mem.c"
-#include "adm5120-pm.c"
-#include "adm5120-hub.c"
-#include "adm5120-q.c"
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * queue up an urb for anything except the root hub
- */
-static int admhc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
- gfp_t mem_flags)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- struct ed *ed;
- struct urb_priv *urb_priv;
- unsigned int pipe = urb->pipe;
- int td_cnt = 0;
- unsigned long flags;
- int ret = 0;
-
-#ifdef ADMHC_VERBOSE_DEBUG
- spin_lock_irqsave(&ahcd->lock, flags);
- urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe), -EINPROGRESS);
- spin_unlock_irqrestore(&ahcd->lock, flags);
-#endif
-
- /* every endpoint has an ed, locate and maybe (re)initialize it */
- ed = ed_get(ahcd, urb->ep, urb->dev, pipe, urb->interval);
- if (!ed)
- return -ENOMEM;
-
- /* for the private part of the URB we need the number of TDs */
- switch (ed->type) {
- case PIPE_CONTROL:
- if (urb->transfer_buffer_length > TD_DATALEN_MAX)
- /* td_submit_urb() doesn't yet handle these */
- return -EMSGSIZE;
-
- /* 1 TD for setup, 1 for ACK, plus ... */
- td_cnt = 2;
- /* FALLTHROUGH */
- case PIPE_BULK:
- /* one TD for every 4096 Bytes (can be up to 8K) */
- td_cnt += urb->transfer_buffer_length / TD_DATALEN_MAX;
- /* ... and for any remaining bytes ... */
- if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
- td_cnt++;
- /* ... and maybe a zero length packet to wrap it up */
- if (td_cnt == 0)
- td_cnt++;
- else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
- && (urb->transfer_buffer_length
- % usb_maxpacket(urb->dev, pipe,
- usb_pipeout(pipe))) == 0)
- td_cnt++;
- break;
- case PIPE_INTERRUPT:
- /*
- * for Interrupt IN/OUT transactions, each ED contains
- * only 1 TD.
- * TODO: check transfer_buffer_length?
- */
- td_cnt = 1;
- break;
- case PIPE_ISOCHRONOUS:
- /* number of packets from URB */
- td_cnt = urb->number_of_packets;
- break;
- }
-
- urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
- if (!urb_priv)
- return -ENOMEM;
-
- urb_priv->ed = ed;
-
- spin_lock_irqsave(&ahcd->lock, flags);
- /* don't submit to a dead HC */
- if (!HCD_HW_ACCESSIBLE(hcd)) {
- ret = -ENODEV;
- goto fail;
- }
- if (!HC_IS_RUNNING(hcd->state)) {
- ret = -ENODEV;
- goto fail;
- }
-
- ret = usb_hcd_link_urb_to_ep(hcd, urb);
- if (ret)
- goto fail;
-
- /* schedule the ed if needed */
- if (ed->state == ED_IDLE) {
- ret = ed_schedule(ahcd, ed);
- if (ret < 0) {
- usb_hcd_unlink_urb_from_ep(hcd, urb);
- goto fail;
- }
- if (ed->type == PIPE_ISOCHRONOUS) {
- u16 frame = admhc_frame_no(ahcd);
-
- /* delay a few frames before the first TD */
- frame += max_t (u16, 8, ed->interval);
- frame &= ~(ed->interval - 1);
- frame |= ed->branch;
- urb->start_frame = frame;
-
- /* yes, only URB_ISO_ASAP is supported, and
- * urb->start_frame is never used as input.
- */
- }
- } else if (ed->type == PIPE_ISOCHRONOUS)
- urb->start_frame = ed->last_iso + ed->interval;
-
- /* fill the TDs and link them to the ed; and
- * enable that part of the schedule, if needed
- * and update count of queued periodic urbs
- */
- urb->hcpriv = urb_priv;
- td_submit_urb(ahcd, urb);
-
-#ifdef ADMHC_VERBOSE_DEBUG
- admhc_dump_ed(ahcd, "admhc_urb_enqueue", urb_priv->ed, 1);
-#endif
-
-fail:
- if (ret)
- urb_priv_free(ahcd, urb_priv);
-
- spin_unlock_irqrestore(&ahcd->lock, flags);
- return ret;
-}
-
-/*
- * decouple the URB from the HC queues (TDs, urb_priv);
- * reporting is always done
- * asynchronously, and we might be dealing with an urb that's
- * partially transferred, or an ED with other urbs being unlinked.
- */
-static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
- int status)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- unsigned long flags;
- int ret;
-
- spin_lock_irqsave(&ahcd->lock, flags);
-
-#ifdef ADMHC_VERBOSE_DEBUG
- urb_print(ahcd, urb, "DEQUEUE", 1, status);
-#endif
- ret = usb_hcd_check_unlink_urb(hcd, urb, status);
- if (ret) {
- /* Do nothing */
- ;
- } else if (HC_IS_RUNNING(hcd->state)) {
- struct urb_priv *urb_priv;
-
- /* Unless an IRQ completed the unlink while it was being
- * handed to us, flag it for unlink and giveback, and force
- * some upcoming INTR_SF to call finish_unlinks()
- */
- urb_priv = urb->hcpriv;
- if (urb_priv) {
- if (urb_priv->ed->state == ED_OPER)
- start_ed_unlink(ahcd, urb_priv->ed);
- }
- } else {
- /*
- * with HC dead, we won't respect hc queue pointers
- * any more ... just clean up every urb's memory.
- */
- if (urb->hcpriv)
- finish_urb(ahcd, urb, status);
- }
- spin_unlock_irqrestore(&ahcd->lock, flags);
-
- return ret;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* frees config/altsetting state for endpoints,
- * including ED memory, dummy TD, and bulk/intr data toggle
- */
-
-static void admhc_endpoint_disable(struct usb_hcd *hcd,
- struct usb_host_endpoint *ep)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- unsigned long flags;
- struct ed *ed = ep->hcpriv;
- unsigned limit = 1000;
-
- /* ASSERT: any requests/urbs are being unlinked */
- /* ASSERT: nobody can be submitting urbs for this any more */
-
- if (!ed)
- return;
-
-#ifdef ADMHC_VERBOSE_DEBUG
- spin_lock_irqsave(&ahcd->lock, flags);
- admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
- spin_unlock_irqrestore(&ahcd->lock, flags);
-#endif
-
-rescan:
- spin_lock_irqsave(&ahcd->lock, flags);
-
- if (!HC_IS_RUNNING(hcd->state)) {
-sanitize:
- ed->state = ED_IDLE;
- finish_unlinks(ahcd, 0);
- }
-
- switch (ed->state) {
- case ED_UNLINK: /* wait for hw to finish? */
- /* major IRQ delivery trouble loses INTR_SOFI too... */
- if (limit-- == 0) {
- admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
- goto sanitize;
- }
- spin_unlock_irqrestore(&ahcd->lock, flags);
- schedule_timeout_uninterruptible(1);
- goto rescan;
- case ED_IDLE: /* fully unlinked */
- if (list_empty(&ed->td_list)) {
- td_free(ahcd, ed->dummy);
- ed_free(ahcd, ed);
- break;
- }
- /* else FALL THROUGH */
- default:
- /* caller was supposed to have unlinked any requests;
- * that's not our job. can't recover; must leak ed.
- */
- admhc_err(ahcd, "leak ed %p (#%02x) state %d%s\n",
- ed, ep->desc.bEndpointAddress, ed->state,
- list_empty(&ed->td_list) ? "" : " (has tds)");
- td_free(ahcd, ed->dummy);
- break;
- }
-
- ep->hcpriv = NULL;
-
- spin_unlock_irqrestore(&ahcd->lock, flags);
-}
-
-static int admhc_get_frame_number(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
-
- return admhc_frame_no(ahcd);
-}
-
-static void admhc_usb_reset(struct admhcd *ahcd)
-{
-#if 0
- ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
- ahcd->hc_control &= OHCI_CTRL_RWC;
- admhc_writel(ahcd, ahcd->hc_control, &ahcd->regs->control);
-#else
- /* FIXME */
- ahcd->host_control = ADMHC_BUSS_RESET;
- admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
-#endif
-}
-
-/* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
- * other cases where the next software may expect clean state from the
- * "firmware". this is bus-neutral, unlike shutdown() methods.
- */
-static void
-admhc_shutdown(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd;
-
- ahcd = hcd_to_admhcd(hcd);
- admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
- admhc_dma_disable(ahcd);
- admhc_usb_reset(ahcd);
- /* flush the writes */
- admhc_writel_flush(ahcd);
-}
-
-/*-------------------------------------------------------------------------*
- * HC functions
- *-------------------------------------------------------------------------*/
-
-static void admhc_eds_cleanup(struct admhcd *ahcd)
-{
- if (ahcd->ed_tails[PIPE_INTERRUPT]) {
- ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
- ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
- }
-
- if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
- ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
- ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
- }
-
- if (ahcd->ed_tails[PIPE_CONTROL]) {
- ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
- ahcd->ed_tails[PIPE_CONTROL] = NULL;
- }
-
- if (ahcd->ed_tails[PIPE_BULK]) {
- ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
- ahcd->ed_tails[PIPE_BULK] = NULL;
- }
-
- ahcd->ed_head = NULL;
-}
-
-#define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
-
-static int admhc_eds_init(struct admhcd *ahcd)
-{
- struct ed *ed;
-
- ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
- if (!ed)
- goto err;
-
- ahcd->ed_tails[PIPE_INTERRUPT] = ed;
-
- ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
- if (!ed)
- goto err;
-
- ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
- ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
- ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
- ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
-
- ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
- if (!ed)
- goto err;
-
- ahcd->ed_tails[PIPE_CONTROL] = ed;
- ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
- ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
- ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
-
- ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
- if (!ed)
- goto err;
-
- ahcd->ed_tails[PIPE_BULK] = ed;
- ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
- ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
- ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
-
- ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
-
-#ifdef ADMHC_VERBOSE_DEBUG
- admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
- admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
- admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
- admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
-#endif
-
- return 0;
-
-err:
- admhc_eds_cleanup(ahcd);
- return -ENOMEM;
-}
-
-/* init memory, and kick BIOS/SMM off */
-
-static int admhc_init(struct admhcd *ahcd)
-{
- struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
- int ret;
-
- admhc_disable(ahcd);
- ahcd->regs = hcd->regs;
-
- /* Disable HC interrupts */
- admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
-
- /* Read the number of ports unless overridden */
- if (ahcd->num_ports == 0)
- ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP;
-
- ret = admhc_mem_init(ahcd);
- if (ret)
- goto err;
-
- /* init dummy endpoints */
- ret = admhc_eds_init(ahcd);
- if (ret)
- goto err;
-
- create_debug_files(ahcd);
-
- return 0;
-
-err:
- admhc_stop(hcd);
- return ret;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Start an OHCI controller, set the BUS operational
- * resets USB and controller
- * enable interrupts
- */
-static int admhc_run(struct admhcd *ahcd)
-{
- u32 val;
- int first = ahcd->fminterval == 0;
- struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
-
- admhc_disable(ahcd);
-
- /* boot firmware should have set this up (5.1.1.3.1) */
- if (first) {
- val = admhc_readl(ahcd, &ahcd->regs->fminterval);
- ahcd->fminterval = val & ADMHC_SFI_FI_MASK;
- if (ahcd->fminterval != FI)
- admhc_dbg(ahcd, "fminterval delta %d\n",
- ahcd->fminterval - FI);
- ahcd->fminterval |=
- (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
- /* also: power/overcurrent flags in rhdesc */
- }
-
-#if 0 /* TODO: not applicable */
- /* Reset USB nearly "by the book". RemoteWakeupConnected has
- * to be checked in case boot firmware (BIOS/SMM/...) has set up
- * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
- * If the bus glue detected wakeup capability then it should
- * already be enabled; if so we'll just enable it again.
- */
- if ((ahcd->hc_control & OHCI_CTRL_RWC) != 0)
- device_set_wakeup_capable(hcd->self.controller, 1);
-#endif
-
- switch (ahcd->host_control & ADMHC_HC_BUSS) {
- case ADMHC_BUSS_OPER:
- val = 0;
- break;
- case ADMHC_BUSS_SUSPEND:
- /* FALLTHROUGH ? */
- case ADMHC_BUSS_RESUME:
- ahcd->host_control = ADMHC_BUSS_RESUME;
- val = 10 /* msec wait */;
- break;
- /* case ADMHC_BUSS_RESET: */
- default:
- ahcd->host_control = ADMHC_BUSS_RESET;
- val = 50 /* msec wait */;
- break;
- }
- admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
-
- /* flush the writes */
- admhc_writel_flush(ahcd);
-
- msleep(val);
- val = admhc_read_rhdesc(ahcd);
- if (!(val & ADMHC_RH_NPS)) {
- /* power down each port */
- for (val = 0; val < ahcd->num_ports; val++)
- admhc_write_portstatus(ahcd, val, ADMHC_PS_CPP);
- }
- /* flush those writes */
- admhc_writel_flush(ahcd);
-
- /* 2msec timelimit here means no irqs/preempt */
- spin_lock_irq(&ahcd->lock);
-
- admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
- val = 30; /* ... allow extra time */
- while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
- if (--val == 0) {
- spin_unlock_irq(&ahcd->lock);
- admhc_err(ahcd, "USB HC reset timed out!\n");
- return -1;
- }
- udelay(1);
- }
-
- /* enable HOST mode, before access any host specific register */
- admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
-
- /* Tell the controller where the descriptor list is */
- admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
-
- periodic_reinit(ahcd);
-
- /* use rhsc irqs after khubd is fully initialized */
- set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
- hcd->uses_new_polling = 1;
-
-#if 0
- /* wake on ConnectStatusChange, matching external hubs */
- admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
-#else
- /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
-#endif
-
- /* Choose the interrupts we care about now, others later on demand */
- admhc_intr_ack(ahcd, ~0);
- admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
-
- admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
-
- /* flush those writes */
- admhc_writel_flush(ahcd);
-
- /* start controller operations */
- ahcd->host_control = ADMHC_BUSS_OPER;
- admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
-
- val = 20;
- while ((admhc_readl(ahcd, &ahcd->regs->host_control)
- & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
- if (--val == 0) {
- spin_unlock_irq(&ahcd->lock);
- admhc_err(ahcd, "unable to setup operational mode!\n");
- return -1;
- }
- mdelay(1);
- }
-
- hcd->state = HC_STATE_RUNNING;
-
- ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
-
-#if 0
- /* FIXME: enabling DMA is always failed here for an unknown reason */
- admhc_dma_enable(ahcd);
-
- val = 200;
- while ((admhc_readl(ahcd, &ahcd->regs->host_control)
- & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) {
- if (--val == 0) {
- spin_unlock_irq(&ahcd->lock);
- admhc_err(ahcd, "unable to enable DMA!\n");
- admhc_dump(ahcd, 1);
- return -1;
- }
- mdelay(1);
- }
-
-#endif
-
- spin_unlock_irq(&ahcd->lock);
-
- mdelay(ADMHC_POTPGT);
-
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* an interrupt happens */
-
-static irqreturn_t admhc_irq(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- struct admhcd_regs __iomem *regs = ahcd->regs;
- u32 ints;
-
- ints = admhc_readl(ahcd, ®s->int_status);
- if ((ints & ADMHC_INTR_INTA) == 0) {
- /* no unmasked interrupt status is set */
- return IRQ_NONE;
- }
-
- ints &= admhc_readl(ahcd, ®s->int_enable);
-
- if (ints & ADMHC_INTR_FATI) {
- /* e.g. due to PCI Master/Target Abort */
- admhc_disable(ahcd);
- admhc_err(ahcd, "Fatal Error, controller disabled\n");
- admhc_dump(ahcd, 1);
- admhc_usb_reset(ahcd);
- }
-
- if (ints & ADMHC_INTR_BABI) {
- admhc_intr_disable(ahcd, ADMHC_INTR_BABI);
- admhc_intr_ack(ahcd, ADMHC_INTR_BABI);
- admhc_err(ahcd, "Babble Detected\n");
- }
-
- if (ints & ADMHC_INTR_INSM) {
- admhc_vdbg(ahcd, "Root Hub Status Change\n");
- ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
- admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
-
- /* NOTE: Vendors didn't always make the same implementation
- * choices for RHSC. Many followed the spec; RHSC triggers
- * on an edge, like setting and maybe clearing a port status
- * change bit. With others it's level-triggered, active
- * until khubd clears all the port status change bits. We'll
- * always disable it here and rely on polling until khubd
- * re-enables it.
- */
- admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
- usb_hcd_poll_rh_status(hcd);
- } else if (ints & ADMHC_INTR_RESI) {
- /* For connect and disconnect events, we expect the controller
- * to turn on RHSC along with RD. But for remote wakeup events
- * this might not happen.
- */
- admhc_vdbg(ahcd, "Resume Detect\n");
- admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
- set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
- if (ahcd->autostop) {
- spin_lock(&ahcd->lock);
- admhc_rh_resume(ahcd);
- spin_unlock(&ahcd->lock);
- } else
- usb_hcd_resume_root_hub(hcd);
- }
-
- if (ints & ADMHC_INTR_TDC) {
- admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
- admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
- if (HC_IS_RUNNING(hcd->state))
- admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
- spin_lock(&ahcd->lock);
- admhc_td_complete(ahcd);
- spin_unlock(&ahcd->lock);
- if (HC_IS_RUNNING(hcd->state))
- admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
- }
-
- if (ints & ADMHC_INTR_SO) {
- /* could track INTR_SO to reduce available PCI/... bandwidth */
- admhc_vdbg(ahcd, "Schedule Overrun\n");
- }
-
-#if 1
- spin_lock(&ahcd->lock);
- if (ahcd->ed_rm_list)
- finish_unlinks(ahcd, admhc_frame_no(ahcd));
-
- if ((ints & ADMHC_INTR_SOFI) != 0 && !ahcd->ed_rm_list
- && HC_IS_RUNNING(hcd->state))
- admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
- spin_unlock(&ahcd->lock);
-#else
- if (ints & ADMHC_INTR_SOFI) {
- admhc_vdbg(ahcd, "Start Of Frame\n");
- spin_lock(&ahcd->lock);
-
- /* handle any pending ED removes */
- finish_unlinks(ahcd, admhc_frameno(ahcd));
-
- /* leaving INTR_SOFI enabled when there's still unlinking
- * to be done in the (next frame).
- */
- if ((ahcd->ed_rm_list == NULL) ||
- HC_IS_RUNNING(hcd->state) == 0)
- /*
- * disable INTR_SOFI if there are no unlinking to be
- * done (in the next frame)
- */
- admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
-
- spin_unlock(&ahcd->lock);
- }
-#endif
-
- if (HC_IS_RUNNING(hcd->state)) {
- admhc_intr_ack(ahcd, ints);
- admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
- admhc_writel_flush(ahcd);
- }
-
- return IRQ_HANDLED;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static void admhc_stop(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
-
- admhc_dump(ahcd, 1);
-
- flush_scheduled_work();
-
- admhc_usb_reset(ahcd);
- admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
-
- free_irq(hcd->irq, hcd);
- hcd->irq = -1;
-
- remove_debug_files(ahcd);
- admhc_eds_cleanup(ahcd);
- admhc_mem_cleanup(ahcd);
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef CONFIG_ADM5120
-#include "adm5120-drv.c"
-#define PLATFORM_DRIVER usb_hcd_adm5120_driver
-#endif
-
-#if !defined(PLATFORM_DRIVER)
-#error "missing bus glue for admhc-hcd"
-#endif
-
-#define DRIVER_INFO DRIVER_DESC " version " DRIVER_VERSION
-
-static int __init admhc_hcd_mod_init(void)
-{
- int ret = 0;
-
- if (usb_disabled())
- return -ENODEV;
-
- pr_info("%s: " DRIVER_INFO "\n", hcd_name);
- pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
- sizeof(struct ed), sizeof(struct td));
- set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
-
-#ifdef DEBUG
- admhc_debug_root = debugfs_create_dir("admhc", usb_debug_root);
- if (!admhc_debug_root) {
- ret = -ENOENT;
- goto error_debug;
- }
-#endif
-
-#ifdef PLATFORM_DRIVER
- ret = platform_driver_register(&PLATFORM_DRIVER);
- if (ret < 0)
- goto error_platform;
-#endif
-
- return ret;
-
-#ifdef PLATFORM_DRIVER
- platform_driver_unregister(&PLATFORM_DRIVER);
-error_platform:
-#endif
-
-#ifdef DEBUG
- debugfs_remove(admhc_debug_root);
- admhc_debug_root = NULL;
-error_debug:
-#endif
- clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
- return ret;
-}
-module_init(admhc_hcd_mod_init);
-
-static void __exit admhc_hcd_mod_exit(void)
-{
- platform_driver_unregister(&PLATFORM_DRIVER);
-#ifdef DEBUG
- debugfs_remove(admhc_debug_root);
-#endif
- clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
-}
-module_exit(admhc_hcd_mod_exit);
-
-MODULE_AUTHOR(DRIVER_AUTHOR);
-MODULE_DESCRIPTION(DRIVER_INFO);
-MODULE_VERSION(DRIVER_VERSION);
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci-hub.c
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * ADM5120 Root Hub ... the nonsharable stuff
- */
-
-#define dbg_port(hc, label, num, value) \
- admhc_dbg(hc, \
- "%s port%d " \
- "= 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \
- label, num, value, \
- (value & ADMHC_PS_PRSC) ? " PRSC" : "", \
- (value & ADMHC_PS_OCIC) ? " OCIC" : "", \
- (value & ADMHC_PS_PSSC) ? " PSSC" : "", \
- (value & ADMHC_PS_PESC) ? " PESC" : "", \
- (value & ADMHC_PS_CSC) ? " CSC" : "", \
- \
- (value & ADMHC_PS_LSDA) ? " LSDA" : "", \
- (value & ADMHC_PS_PPS) ? " PPS" : "", \
- (value & ADMHC_PS_PRS) ? " PRS" : "", \
- (value & ADMHC_PS_POCI) ? " POCI" : "", \
- (value & ADMHC_PS_PSS) ? " PSS" : "", \
- \
- (value & ADMHC_PS_PES) ? " PES" : "", \
- (value & ADMHC_PS_CCS) ? " CCS" : "" \
- );
-
-#define dbg_port_write(hc, label, num, value) \
- admhc_dbg(hc, \
- "%s port%d " \
- "= 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \
- label, num, value, \
- (value & ADMHC_PS_PRSC) ? " PRSC" : "", \
- (value & ADMHC_PS_OCIC) ? " OCIC" : "", \
- (value & ADMHC_PS_PSSC) ? " PSSC" : "", \
- (value & ADMHC_PS_PESC) ? " PESC" : "", \
- (value & ADMHC_PS_CSC) ? " CSC" : "", \
- \
- (value & ADMHC_PS_CPP) ? " CPP" : "", \
- (value & ADMHC_PS_SPP) ? " SPP" : "", \
- (value & ADMHC_PS_SPR) ? " SPR" : "", \
- (value & ADMHC_PS_CPS) ? " CPS" : "", \
- (value & ADMHC_PS_SPS) ? " SPS" : "", \
- \
- (value & ADMHC_PS_SPE) ? " SPE" : "", \
- (value & ADMHC_PS_CPE) ? " CPE" : "" \
- );
-
-/*-------------------------------------------------------------------------*/
-
-/* build "status change" packet (one or two bytes) from HC registers */
-
-static int
-admhc_hub_status_data(struct usb_hcd *hcd, char *buf)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- int i, changed = 0, length = 1;
- int any_connected = 0;
- unsigned long flags;
- u32 status;
-
- spin_lock_irqsave(&ahcd->lock, flags);
- if (!HCD_HW_ACCESSIBLE(hcd))
- goto done;
-
- /* init status */
- status = admhc_read_rhdesc(ahcd);
- if (status & (ADMHC_RH_LPSC | ADMHC_RH_OCIC))
- buf[0] = changed = 1;
- else
- buf[0] = 0;
- if (ahcd->num_ports > 7) {
- buf[1] = 0;
- length++;
- }
-
- /* look at each port */
- for (i = 0; i < ahcd->num_ports; i++) {
- status = admhc_read_portstatus(ahcd, i);
-
- /* can't autostop if ports are connected */
- any_connected |= (status & ADMHC_PS_CCS);
-
- if (status & (ADMHC_PS_CSC | ADMHC_PS_PESC | ADMHC_PS_PSSC
- | ADMHC_PS_OCIC | ADMHC_PS_PRSC)) {
- changed = 1;
- if (i < 7)
- buf[0] |= 1 << (i + 1);
- else
- buf[1] |= 1 << (i - 7);
- }
- }
-
- if (admhc_root_hub_state_changes(ahcd, changed,
- any_connected))
- set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
- else
- clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
-
-done:
- spin_unlock_irqrestore(&ahcd->lock, flags);
-
- return changed ? length : 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static int admhc_get_hub_descriptor(struct admhcd *ahcd, char *buf)
-{
- struct usb_hub_descriptor *desc = (struct usb_hub_descriptor *)buf;
- u32 rh = admhc_read_rhdesc(ahcd);
- u16 temp;
-
- desc->bDescriptorType = USB_DT_HUB; /* Hub-descriptor */
- desc->bPwrOn2PwrGood = ADMHC_POTPGT/2; /* use default value */
- desc->bHubContrCurrent = 0x00; /* 0mA */
-
- desc->bNbrPorts = ahcd->num_ports;
- temp = 1 + (ahcd->num_ports / 8);
- desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
-
- /* FIXME */
- temp = 0;
- if (rh & ADMHC_RH_NPS) /* no power switching? */
- temp |= 0x0002;
- if (rh & ADMHC_RH_PSM) /* per-port power switching? */
- temp |= 0x0001;
- if (rh & ADMHC_RH_NOCP) /* no overcurrent reporting? */
- temp |= 0x0010;
- else if (rh & ADMHC_RH_OCPM) /* per-port overcurrent reporting? */
- temp |= 0x0008;
- desc->wHubCharacteristics = (__force __u16)cpu_to_hc16(ahcd, temp);
-
- /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
- desc->u.hs.DeviceRemovable[0] = 0;
- desc->u.hs.DeviceRemovable[0] = ~0;
-
- return 0;
-}
-
-static int admhc_get_hub_status(struct admhcd *ahcd, char *buf)
-{
- struct usb_hub_status *hs = (struct usb_hub_status *)buf;
- u32 t = admhc_read_rhdesc(ahcd);
- u16 status, change;
-
- status = 0;
- status |= (t & ADMHC_RH_LPS) ? HUB_STATUS_LOCAL_POWER : 0;
- status |= (t & ADMHC_RH_OCI) ? HUB_STATUS_OVERCURRENT : 0;
-
- change = 0;
- change |= (t & ADMHC_RH_LPSC) ? HUB_CHANGE_LOCAL_POWER : 0;
- change |= (t & ADMHC_RH_OCIC) ? HUB_CHANGE_OVERCURRENT : 0;
-
- hs->wHubStatus = (__force __u16)cpu_to_hc16(ahcd, status);
- hs->wHubChange = (__force __u16)cpu_to_hc16(ahcd, change);
-
- return 0;
-}
-
-static int admhc_get_port_status(struct admhcd *ahcd, unsigned port, char *buf)
-{
- struct usb_port_status *ps = (struct usb_port_status *)buf;
- u32 t = admhc_read_portstatus(ahcd, port);
- u16 status, change;
-
- status = 0;
- status |= (t & ADMHC_PS_CCS) ? USB_PORT_STAT_CONNECTION : 0;
- status |= (t & ADMHC_PS_PES) ? USB_PORT_STAT_ENABLE : 0;
- status |= (t & ADMHC_PS_PSS) ? USB_PORT_STAT_SUSPEND : 0;
- status |= (t & ADMHC_PS_POCI) ? USB_PORT_STAT_OVERCURRENT : 0;
- status |= (t & ADMHC_PS_PRS) ? USB_PORT_STAT_RESET : 0;
- status |= (t & ADMHC_PS_PPS) ? USB_PORT_STAT_POWER : 0;
- status |= (t & ADMHC_PS_LSDA) ? USB_PORT_STAT_LOW_SPEED : 0;
-
- change = 0;
- change |= (t & ADMHC_PS_CSC) ? USB_PORT_STAT_C_CONNECTION : 0;
- change |= (t & ADMHC_PS_PESC) ? USB_PORT_STAT_C_ENABLE : 0;
- change |= (t & ADMHC_PS_PSSC) ? USB_PORT_STAT_C_SUSPEND : 0;
- change |= (t & ADMHC_PS_OCIC) ? USB_PORT_STAT_C_OVERCURRENT : 0;
- change |= (t & ADMHC_PS_PRSC) ? USB_PORT_STAT_C_RESET : 0;
-
- ps->wPortStatus = (__force __u16)cpu_to_hc16(ahcd, status);
- ps->wPortChange = (__force __u16)cpu_to_hc16(ahcd, change);
-
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef CONFIG_USB_OTG
-
-static int admhc_start_port_reset(struct usb_hcd *hcd, unsigned port)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- u32 status;
-
- if (!port)
- return -EINVAL;
- port--;
-
- /* start port reset before HNP protocol times out */
- status = admhc_read_portstatus(ahcd, port);
- if (!(status & ADMHC_PS_CCS))
- return -ENODEV;
-
- /* khubd will finish the reset later */
- admhc_write_portstatus(ahcd, port, ADMHC_PS_PRS);
- return 0;
-}
-
-static void start_hnp(struct admhcd *ahcd);
-
-#else
-
-#define admhc_start_port_reset NULL
-
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-
-/* See usb 7.1.7.5: root hubs must issue at least 50 msec reset signaling,
- * not necessarily continuous ... to guard against resume signaling.
- * The short timeout is safe for non-root hubs, and is backward-compatible
- * with earlier Linux hosts.
- */
-#ifdef CONFIG_USB_SUSPEND
-#define PORT_RESET_MSEC 50
-#else
-#define PORT_RESET_MSEC 10
-#endif
-
-/* this timer value might be vendor-specific ... */
-#define PORT_RESET_HW_MSEC 10
-
-/* wrap-aware logic morphed from <linux/jiffies.h> */
-#define tick_before(t1, t2) ((s16)(((s16)(t1)) - ((s16)(t2))) < 0)
-
-/* called from some task, normally khubd */
-static inline int admhc_port_reset(struct admhcd *ahcd, unsigned port)
-{
- u32 t;
-
- admhc_vdbg(ahcd, "reset port%d\n", port);
- t = admhc_read_portstatus(ahcd, port);
- if (!(t & ADMHC_PS_CCS))
- return -ENODEV;
-
- admhc_write_portstatus(ahcd, port, ADMHC_PS_SPR);
- mdelay(10);
- admhc_write_portstatus(ahcd, port, (ADMHC_PS_SPE | ADMHC_PS_CSC));
- mdelay(100);
-
- return 0;
-}
-
-static inline int admhc_port_enable(struct admhcd *ahcd, unsigned port)
-{
- u32 t;
-
- admhc_vdbg(ahcd, "enable port%d\n", port);
- t = admhc_read_portstatus(ahcd, port);
- if (!(t & ADMHC_PS_CCS))
- return -ENODEV;
-
- admhc_write_portstatus(ahcd, port, ADMHC_PS_SPE);
-
- return 0;
-}
-
-static inline int admhc_port_disable(struct admhcd *ahcd, unsigned port)
-{
- u32 t;
-
- admhc_vdbg(ahcd, "disable port%d\n", port);
- t = admhc_read_portstatus(ahcd, port);
- if (!(t & ADMHC_PS_CCS))
- return -ENODEV;
-
- admhc_write_portstatus(ahcd, port, ADMHC_PS_CPE);
-
- return 0;
-}
-
-static inline int admhc_port_write(struct admhcd *ahcd, unsigned port,
- u32 val)
-{
-#ifdef ADMHC_VERBOSE_DEBUG
- dbg_port_write(ahcd, "write", port, val);
-#endif
- admhc_write_portstatus(ahcd, port, val);
-
- return 0;
-}
-
-static int admhc_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
- u16 wIndex, char *buf, u16 wLength)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- int ports = ahcd->num_ports;
- int ret = 0;
-
- if (unlikely(!HCD_HW_ACCESSIBLE(hcd)))
- return -ESHUTDOWN;
-
- switch (typeReq) {
- case ClearHubFeature:
- switch (wValue) {
- case C_HUB_OVER_CURRENT:
-#if 0 /* FIXME */
- admhc_writel(ahcd, ADMHC_RH_OCIC,
- &ahcd->regs->roothub.status);
-#endif
- case C_HUB_LOCAL_POWER:
- break;
- default:
- goto error;
- }
- break;
- case ClearPortFeature:
- if (!wIndex || wIndex > ports)
- goto error;
- wIndex--;
-
- switch (wValue) {
- case USB_PORT_FEAT_ENABLE:
- ret = admhc_port_disable(ahcd, wIndex);
- break;
- case USB_PORT_FEAT_SUSPEND:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CPS);
- break;
- case USB_PORT_FEAT_POWER:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CPP);
- break;
- case USB_PORT_FEAT_C_CONNECTION:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CSC);
- break;
- case USB_PORT_FEAT_C_ENABLE:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PESC);
- break;
- case USB_PORT_FEAT_C_SUSPEND:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PSSC);
- break;
- case USB_PORT_FEAT_C_OVER_CURRENT:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_OCIC);
- break;
- case USB_PORT_FEAT_C_RESET:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PRSC);
- break;
- default:
- goto error;
- }
- break;
- case GetHubDescriptor:
- ret = admhc_get_hub_descriptor(ahcd, buf);
- break;
- case GetHubStatus:
- ret = admhc_get_hub_status(ahcd, buf);
- break;
- case GetPortStatus:
- if (!wIndex || wIndex > ports)
- goto error;
- wIndex--;
-
- ret = admhc_get_port_status(ahcd, wIndex, buf);
- break;
- case SetHubFeature:
- switch (wValue) {
- case C_HUB_OVER_CURRENT:
- /* FIXME: this can be cleared, yes? */
- case C_HUB_LOCAL_POWER:
- break;
- default:
- goto error;
- }
- break;
- case SetPortFeature:
- if (!wIndex || wIndex > ports)
- goto error;
- wIndex--;
-
- switch (wValue) {
- case USB_PORT_FEAT_ENABLE:
- ret = admhc_port_enable(ahcd, wIndex);
- break;
- case USB_PORT_FEAT_RESET:
- ret = admhc_port_reset(ahcd, wIndex);
- break;
- case USB_PORT_FEAT_SUSPEND:
-#ifdef CONFIG_USB_OTG
- if (hcd->self.otg_port == (wIndex + 1)
- && hcd->self.b_hnp_enable)
- start_hnp(ahcd);
- else
-#endif
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_SPS);
- break;
- case USB_PORT_FEAT_POWER:
- ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_SPP);
- break;
- default:
- goto error;
- }
- break;
-
- default:
-error:
- /* "protocol stall" on error */
- ret = -EPIPE;
- }
-
- return ret;
-}
-
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci-mem.c
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * OHCI deals with three types of memory:
- * - data used only by the HCD ... kmalloc is fine
- * - async and periodic schedules, shared by HC and HCD ... these
- * need to use dma_pool or dma_alloc_coherent
- * - driver buffers, read/written by HC ... the hcd glue or the
- * device driver provides us with dma addresses
- *
- * There's also "register" data, which is memory mapped.
- * No memory seen by this driver (or any HCD) may be paged out.
- */
-
-/*-------------------------------------------------------------------------*/
-
-static void admhc_hcd_init(struct admhcd *ahcd)
-{
- ahcd->next_statechange = jiffies;
- spin_lock_init(&ahcd->lock);
- INIT_LIST_HEAD(&ahcd->pending);
-}
-
-/*-------------------------------------------------------------------------*/
-
-static int admhc_mem_init(struct admhcd *ahcd)
-{
- ahcd->td_cache = dma_pool_create("admhc_td",
- admhcd_to_hcd(ahcd)->self.controller,
- sizeof(struct td),
- TD_ALIGN, /* byte alignment */
- 0 /* no page-crossing issues */
- );
- if (!ahcd->td_cache)
- goto err;
-
- ahcd->ed_cache = dma_pool_create("admhc_ed",
- admhcd_to_hcd(ahcd)->self.controller,
- sizeof(struct ed),
- ED_ALIGN, /* byte alignment */
- 0 /* no page-crossing issues */
- );
- if (!ahcd->ed_cache)
- goto err_td_cache;
-
- return 0;
-
-err_td_cache:
- dma_pool_destroy(ahcd->td_cache);
- ahcd->td_cache = NULL;
-err:
- return -ENOMEM;
-}
-
-static void admhc_mem_cleanup(struct admhcd *ahcd)
-{
- if (ahcd->td_cache) {
- dma_pool_destroy(ahcd->td_cache);
- ahcd->td_cache = NULL;
- }
-
- if (ahcd->ed_cache) {
- dma_pool_destroy(ahcd->ed_cache);
- ahcd->ed_cache = NULL;
- }
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* ahcd "done list" processing needs this mapping */
-static inline struct td *dma_to_td(struct admhcd *ahcd, dma_addr_t td_dma)
-{
- struct td *td;
-
- td_dma &= TD_MASK;
- td = ahcd->td_hash[TD_HASH_FUNC(td_dma)];
- while (td && td->td_dma != td_dma)
- td = td->td_hash;
-
- return td;
-}
-
-/* TDs ... */
-static struct td *td_alloc(struct admhcd *ahcd, gfp_t mem_flags)
-{
- dma_addr_t dma;
- struct td *td;
-
- td = dma_pool_alloc(ahcd->td_cache, mem_flags, &dma);
- if (!td)
- return NULL;
-
- /* in case ahcd fetches it, make it look dead */
- memset(td, 0, sizeof *td);
- td->hwNextTD = cpu_to_hc32(ahcd, dma);
- td->td_dma = dma;
- /* hashed in td_fill */
-
- return td;
-}
-
-static void td_free(struct admhcd *ahcd, struct td *td)
-{
- struct td **prev = &ahcd->td_hash[TD_HASH_FUNC(td->td_dma)];
-
- while (*prev && *prev != td)
- prev = &(*prev)->td_hash;
- if (*prev)
- *prev = td->td_hash;
-#if 0
- /* TODO: remove */
- else if ((td->hwINFO & cpu_to_hc32(ahcd, TD_DONE)) != 0)
- admhc_dbg(ahcd, "no hash for td %p\n", td);
-#else
- else if ((td->flags & TD_FLAG_DONE) != 0)
- admhc_dbg(ahcd, "no hash for td %p\n", td);
-#endif
- dma_pool_free(ahcd->td_cache, td, td->td_dma);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* EDs ... */
-static struct ed *ed_alloc(struct admhcd *ahcd, gfp_t mem_flags)
-{
- dma_addr_t dma;
- struct ed *ed;
-
- ed = dma_pool_alloc(ahcd->ed_cache, mem_flags, &dma);
- if (!ed)
- return NULL;
-
- memset(ed, 0, sizeof(*ed));
- ed->dma = dma;
-
- INIT_LIST_HEAD(&ed->td_list);
- INIT_LIST_HEAD(&ed->urb_list);
-
- return ed;
-}
-
-static void ed_free(struct admhcd *ahcd, struct ed *ed)
-{
- dma_pool_free(ahcd->ed_cache, ed, ed->dma);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* URB priv ... */
-static void urb_priv_free(struct admhcd *ahcd, struct urb_priv *urb_priv)
-{
- int i;
-
- for (i = 0; i < urb_priv->td_cnt; i++)
- if (urb_priv->td[i])
- td_free(ahcd, urb_priv->td[i]);
-
- list_del(&urb_priv->pending);
- kfree(urb_priv);
-}
-
-static struct urb_priv *urb_priv_alloc(struct admhcd *ahcd, int num_tds,
- gfp_t mem_flags)
-{
- struct urb_priv *priv;
-
- /* allocate the private part of the URB */
- priv = kzalloc(sizeof(*priv) + sizeof(struct td) * num_tds, mem_flags);
- if (!priv)
- goto err;
-
- /* allocate the TDs (deferring hash chain updates) */
- for (priv->td_cnt = 0; priv->td_cnt < num_tds; priv->td_cnt++) {
- priv->td[priv->td_cnt] = td_alloc(ahcd, mem_flags);
- if (priv->td[priv->td_cnt] == NULL)
- goto err_free;
- }
-
- INIT_LIST_HEAD(&priv->pending);
-
- return priv;
-
-err_free:
- urb_priv_free(ahcd, priv);
-err:
- return NULL;
-}
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from fragments of the OHCI driver.
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#define OHCI_SCHED_ENABLES \
- (OHCI_CTRL_CLE|OHCI_CTRL_BLE|OHCI_CTRL_PLE|OHCI_CTRL_IE)
-
-#ifdef CONFIG_PM
-static int admhc_restart(struct admhcd *ahcd);
-
-static int admhc_rh_suspend(struct admhcd *ahcd, int autostop)
-__releases(ahcd->lock)
-__acquires(ahcd->lock)
-{
- int status = 0;
-
- ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
- switch (ahcd->hc_control & OHCI_CTRL_HCFS) {
- case OHCI_USB_RESUME:
- admhc_dbg(ahcd, "resume/suspend?\n");
- ahcd->hc_control &= ~OHCI_CTRL_HCFS;
- ahcd->hc_control |= OHCI_USB_RESET;
- admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
- (void) admhc_readl(ahcd, &ahcd->regs->control);
- /* FALL THROUGH */
- case OHCI_USB_RESET:
- status = -EBUSY;
- admhc_dbg(ahcd, "needs reinit!\n");
- goto done;
- case OHCI_USB_SUSPEND:
- if (!ahcd->autostop) {
- admhc_dbg(ahcd, "already suspended\n");
- goto done;
- }
- }
- admhc_dbg(ahcd, "%s root hub\n",
- autostop ? "auto-stop" : "suspend");
-
- /* First stop any processing */
- if (!autostop && (ahcd->hc_control & OHCI_SCHED_ENABLES)) {
- ahcd->hc_control &= ~OHCI_SCHED_ENABLES;
- admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
- ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
- admhc_writel(ahcd, OHCI_INTR_SF, &ahcd->regs->intrstatus);
-
- /* sched disables take effect on the next frame,
- * then the last WDH could take 6+ msec
- */
- admhc_dbg(ahcd, "stopping schedules ...\n");
- ahcd->autostop = 0;
- spin_unlock_irq (&ahcd->lock);
- msleep (8);
- spin_lock_irq(&ahcd->lock);
- }
- dl_done_list (ahcd);
- finish_unlinks (ahcd, admhc_frame_no(ahcd));
-
- /* maybe resume can wake root hub */
- if (device_may_wakeup(&admhcd_to_hcd(ahcd)->self.root_hub->dev) ||
- autostop)
- ahcd->hc_control |= OHCI_CTRL_RWE;
- else {
- admhc_writel(ahcd, OHCI_INTR_RHSC, &ahcd->regs->intrdisable);
- ahcd->hc_control &= ~OHCI_CTRL_RWE;
- }
-
- /* Suspend hub ... this is the "global (to this bus) suspend" mode,
- * which doesn't imply ports will first be individually suspended.
- */
- ahcd->hc_control &= ~OHCI_CTRL_HCFS;
- ahcd->hc_control |= OHCI_USB_SUSPEND;
- admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
- (void) admhc_readl(ahcd, &ahcd->regs->control);
-
- /* no resumes until devices finish suspending */
- if (!autostop) {
- ahcd->next_statechange = jiffies + msecs_to_jiffies (5);
- ahcd->autostop = 0;
- }
-
-done:
- return status;
-}
-
-static inline struct ed *find_head(struct ed *ed)
-{
- /* for bulk and control lists */
- while (ed->ed_prev)
- ed = ed->ed_prev;
- return ed;
-}
-
-/* caller has locked the root hub */
-static int admhc_rh_resume(struct admhcd *ahcd)
-__releases(ahcd->lock)
-__acquires(ahcd->lock)
-{
- struct usb_hcd *hcd = admhcd_to_hcd (ahcd);
- u32 temp, enables;
- int status = -EINPROGRESS;
- int autostopped = ahcd->autostop;
-
- ahcd->autostop = 0;
- ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
-
- if (ahcd->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
- /* this can happen after resuming a swsusp snapshot */
- if (hcd->state == HC_STATE_RESUMING) {
- admhc_dbg(ahcd, "BIOS/SMM active, control %03x\n",
- ahcd->hc_control);
- status = -EBUSY;
- /* this happens when pmcore resumes HC then root */
- } else {
- admhc_dbg(ahcd, "duplicate resume\n");
- status = 0;
- }
- } else switch (ahcd->hc_control & OHCI_CTRL_HCFS) {
- case OHCI_USB_SUSPEND:
- ahcd->hc_control &= ~(OHCI_CTRL_HCFS|OHCI_SCHED_ENABLES);
- ahcd->hc_control |= OHCI_USB_RESUME;
- admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
- (void) admhc_readl(ahcd, &ahcd->regs->control);
- admhc_dbg(ahcd, "%s root hub\n",
- autostopped ? "auto-start" : "resume");
- break;
- case OHCI_USB_RESUME:
- /* HCFS changes sometime after INTR_RD */
- admhc_dbg(ahcd, "%swakeup root hub\n",
- autostopped ? "auto-" : "");
- break;
- case OHCI_USB_OPER:
- /* this can happen after resuming a swsusp snapshot */
- admhc_dbg(ahcd, "snapshot resume? reinit\n");
- status = -EBUSY;
- break;
- default: /* RESET, we lost power */
- admhc_dbg(ahcd, "lost power\n");
- status = -EBUSY;
- }
- if (status == -EBUSY) {
- if (!autostopped) {
- spin_unlock_irq (&ahcd->lock);
- (void) ahcd_init (ahcd);
- status = admhc_restart (ahcd);
- spin_lock_irq(&ahcd->lock);
- }
- return status;
- }
- if (status != -EINPROGRESS)
- return status;
- if (autostopped)
- goto skip_resume;
- spin_unlock_irq (&ahcd->lock);
-
- /* Some controllers (lucent erratum) need extra-long delays */
- msleep (20 /* usb 11.5.1.10 */ + 12 /* 32 msec counter */ + 1);
-
- temp = admhc_readl(ahcd, &ahcd->regs->control);
- temp &= OHCI_CTRL_HCFS;
- if (temp != OHCI_USB_RESUME) {
- admhc_err (ahcd, "controller won't resume\n");
- spin_lock_irq(&ahcd->lock);
- return -EBUSY;
- }
-
- /* disable old schedule state, reinit from scratch */
- admhc_writel(ahcd, 0, &ahcd->regs->ed_controlhead);
- admhc_writel(ahcd, 0, &ahcd->regs->ed_controlcurrent);
- admhc_writel(ahcd, 0, &ahcd->regs->ed_bulkhead);
- admhc_writel(ahcd, 0, &ahcd->regs->ed_bulkcurrent);
- admhc_writel(ahcd, 0, &ahcd->regs->ed_periodcurrent);
- admhc_writel(ahcd, (u32) ahcd->hcca_dma, &ahcd->ahcd->regs->hcca);
-
- /* Sometimes PCI D3 suspend trashes frame timings ... */
- periodic_reinit(ahcd);
-
- /* the following code is executed with ahcd->lock held and
- * irqs disabled if and only if autostopped is true
- */
-
-skip_resume:
- /* interrupts might have been disabled */
- admhc_writel(ahcd, OHCI_INTR_INIT, &ahcd->regs->int_enable);
- if (ahcd->ed_rm_list)
- admhc_writel(ahcd, OHCI_INTR_SF, &ahcd->regs->int_enable);
-
- /* Then re-enable operations */
- admhc_writel(ahcd, OHCI_USB_OPER, &ahcd->regs->control);
- (void) admhc_readl(ahcd, &ahcd->regs->control);
- if (!autostopped)
- msleep (3);
-
- temp = ahcd->hc_control;
- temp &= OHCI_CTRL_RWC;
- temp |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
- ahcd->hc_control = temp;
- admhc_writel(ahcd, temp, &ahcd->regs->control);
- (void) admhc_readl(ahcd, &ahcd->regs->control);
-
- /* TRSMRCY */
- if (!autostopped) {
- msleep (10);
- spin_lock_irq(&ahcd->lock);
- }
- /* now ahcd->lock is always held and irqs are always disabled */
-
- /* keep it alive for more than ~5x suspend + resume costs */
- ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
-
- /* maybe turn schedules back on */
- enables = 0;
- temp = 0;
- if (!ahcd->ed_rm_list) {
- if (ahcd->ed_controltail) {
- admhc_writel(ahcd,
- find_head (ahcd->ed_controltail)->dma,
- &ahcd->regs->ed_controlhead);
- enables |= OHCI_CTRL_CLE;
- temp |= OHCI_CLF;
- }
- if (ahcd->ed_bulktail) {
- admhc_writel(ahcd, find_head (ahcd->ed_bulktail)->dma,
- &ahcd->regs->ed_bulkhead);
- enables |= OHCI_CTRL_BLE;
- temp |= OHCI_BLF;
- }
- }
- if (hcd->self.bandwidth_isoc_reqs || hcd->self.bandwidth_int_reqs)
- enables |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
- if (enables) {
- admhc_dbg(ahcd, "restarting schedules ... %08x\n", enables);
- ahcd->hc_control |= enables;
- admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control);
- if (temp)
- admhc_writel(ahcd, temp, &ahcd->regs->cmdstatus);
- (void) admhc_readl(ahcd, &ahcd->regs->control);
- }
-
- return 0;
-}
-
-static int admhc_bus_suspend(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- int rc;
-
- spin_lock_irq(&ahcd->lock);
-
- if (unlikely(!HCD_HW_ACCESSIBLE(hcd)))
- rc = -ESHUTDOWN;
- else
- rc = admhc_rh_suspend(ahcd, 0);
- spin_unlock_irq(&ahcd->lock);
- return rc;
-}
-
-static int admhc_bus_resume(struct usb_hcd *hcd)
-{
- struct admhcd *ahcd = hcd_to_admhcd(hcd);
- int rc;
-
- if (time_before(jiffies, ahcd->next_statechange))
- msleep(5);
-
- spin_lock_irq(&ahcd->lock);
-
- if (unlikely(!HCD_HW_ACCESSIBLE(hcd)))
- rc = -ESHUTDOWN;
- else
- rc = admhc_rh_resume(ahcd);
- spin_unlock_irq(&ahcd->lock);
-
- /* poll until we know a device is connected or we autostop */
- if (rc == 0)
- usb_hcd_poll_rh_status(hcd);
- return rc;
-}
-
-/* Carry out polling-, autostop-, and autoresume-related state changes */
-static int admhc_root_hub_state_changes(struct admhcd *ahcd, int changed,
- int any_connected)
-{
- int poll_rh = 1;
-
- switch (ahcd->hc_control & OHCI_CTRL_HCFS) {
-
- case OHCI_USB_OPER:
- /* keep on polling until we know a device is connected
- * and RHSC is enabled */
- if (!ahcd->autostop) {
- if (any_connected ||
- !device_may_wakeup(&admhcd_to_hcd(ahcd)
- ->self.root_hub->dev)) {
- if (admhc_readl(ahcd, &ahcd->regs->int_enable) &
- OHCI_INTR_RHSC)
- poll_rh = 0;
- } else {
- ahcd->autostop = 1;
- ahcd->next_statechange = jiffies + HZ;
- }
-
- /* if no devices have been attached for one second, autostop */
- } else {
- if (changed || any_connected) {
- ahcd->autostop = 0;
- ahcd->next_statechange = jiffies +
- STATECHANGE_DELAY;
- } else if (time_after_eq(jiffies,
- ahcd->next_statechange)
- && !ahcd->ed_rm_list
- && !(ahcd->hc_control &
- OHCI_SCHED_ENABLES)) {
- ahcd_rh_suspend(ahcd, 1);
- }
- }
- break;
-
- /* if there is a port change, autostart or ask to be resumed */
- case OHCI_USB_SUSPEND:
- case OHCI_USB_RESUME:
- if (changed) {
- if (ahcd->autostop)
- admhc_rh_resume(ahcd);
- else
- usb_hcd_resume_root_hub(admhcd_to_hcd(ahcd));
- } else {
- /* everything is idle, no need for polling */
- poll_rh = 0;
- }
- break;
- }
- return poll_rh;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* must not be called from interrupt context */
-static int admhc_restart(struct admhcd *ahcd)
-{
- int temp;
- int i;
- struct urb_priv *priv;
-
- /* mark any devices gone, so they do nothing till khubd disconnects.
- * recycle any "live" eds/tds (and urbs) right away.
- * later, khubd disconnect processing will recycle the other state,
- * (either as disconnect/reconnect, or maybe someday as a reset).
- */
- spin_lock_irq(&ahcd->lock);
- admhc_disable(ahcd);
- usb_root_hub_lost_power(admhcd_to_hcd(ahcd)->self.root_hub);
- if (!list_empty(&ahcd->pending))
- admhc_dbg(ahcd, "abort schedule...\n");
- list_for_each_entry(priv, &ahcd->pending, pending) {
- struct urb *urb = priv->td[0]->urb;
- struct ed *ed = priv->ed;
-
- switch (ed->state) {
- case ED_OPER:
- ed->state = ED_UNLINK;
- ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE);
- ed_deschedule (ahcd, ed);
-
- ed->ed_next = ahcd->ed_rm_list;
- ed->ed_prev = NULL;
- ahcd->ed_rm_list = ed;
- /* FALLTHROUGH */
- case ED_UNLINK:
- break;
- default:
- admhc_dbg(ahcd, "bogus ed %p state %d\n",
- ed, ed->state);
- }
-
- if (!urb->unlinked)
- urb->unlinked = -ESHUTDOWN;
- }
- finish_unlinks(ahcd, 0);
- spin_unlock_irq(&ahcd->lock);
-
- /* paranoia, in case that didn't work: */
-
- /* empty the interrupt branches */
- for (i = 0; i < NUM_INTS; i++) ahcd->load[i] = 0;
- for (i = 0; i < NUM_INTS; i++) ahcd->hcca->int_table[i] = 0;
-
- /* no EDs to remove */
- ahcd->ed_rm_list = NULL;
-
- /* empty control and bulk lists */
- ahcd->ed_controltail = NULL;
- ahcd->ed_bulktail = NULL;
-
- if ((temp = admhc_run(ahcd)) < 0) {
- admhc_err(ahcd, "can't restart, %d\n", temp);
- return temp;
- } else {
- /* here we "know" root ports should always stay powered,
- * and that if we try to turn them back on the root hub
- * will respond to CSC processing.
- */
- i = ahcd->num_ports;
- while (i--)
- admhc_writel(ahcd, RH_PS_PSS,
- &ahcd->regs->portstatus[i]);
- admhc_dbg(ahcd, "restart complete\n");
- }
- return 0;
-}
-
-#else /* CONFIG_PM */
-
-static inline int admhc_rh_resume(struct admhcd *ahcd)
-{
- return 0;
-}
-
-/* Carry out polling-related state changes.
- * autostop isn't used when CONFIG_PM is turned off.
- */
-static int admhc_root_hub_state_changes(struct admhcd *ahcd, int changed,
- int any_connected)
-{
- /* If INSM is enabled, don't poll */
- if (admhc_readl(ahcd, &ahcd->regs->int_enable) & ADMHC_INTR_INSM)
- return 0;
-
- /* If no status changes are pending, enable status-change interrupts */
- if (!changed) {
- admhc_intr_enable(ahcd, ADMHC_INTR_INSM);
- return 0;
- }
-
- return 1;
-}
-
-#endif /* CONFIG_PM */
-
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci-q.c
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-#include <linux/irq.h>
-#include <linux/slab.h>
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * URB goes back to driver, and isn't reissued.
- * It's completely gone from HC data structures.
- * PRECONDITION: ahcd lock held, irqs blocked.
- */
-static void
-finish_urb(struct admhcd *ahcd, struct urb *urb, int status)
-__releases(ahcd->lock)
-__acquires(ahcd->lock)
-{
- urb_priv_free(ahcd, urb->hcpriv);
-
- if (likely(status == -EINPROGRESS))
- status = 0;
-
- switch (usb_pipetype(urb->pipe)) {
- case PIPE_ISOCHRONOUS:
- admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs--;
- break;
- case PIPE_INTERRUPT:
- admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs--;
- break;
- }
-
-#ifdef ADMHC_VERBOSE_DEBUG
- urb_print(ahcd, urb, "RET", usb_pipeout(urb->pipe), status);
-#endif
-
- /* urb->complete() can reenter this HCD */
- usb_hcd_unlink_urb_from_ep(admhcd_to_hcd(ahcd), urb);
- spin_unlock(&ahcd->lock);
- usb_hcd_giveback_urb(admhcd_to_hcd(ahcd), urb, status);
- spin_lock(&ahcd->lock);
-}
-
-
-/*-------------------------------------------------------------------------*
- * ED handling functions
- *-------------------------------------------------------------------------*/
-
-#if 0 /* FIXME */
-/* search for the right schedule branch to use for a periodic ed.
- * does some load balancing; returns the branch, or negative errno.
- */
-static int balance(struct admhcd *ahcd, int interval, int load)
-{
- int i, branch = -ENOSPC;
-
- /* iso periods can be huge; iso tds specify frame numbers */
- if (interval > NUM_INTS)
- interval = NUM_INTS;
-
- /* search for the least loaded schedule branch of that period
- * that has enough bandwidth left unreserved.
- */
- for (i = 0; i < interval ; i++) {
- if (branch < 0 || ahcd->load[branch] > ahcd->load[i]) {
- int j;
-
- /* usb 1.1 says 90% of one frame */
- for (j = i; j < NUM_INTS; j += interval) {
- if ((ahcd->load[j] + load) > 900)
- break;
- }
- if (j < NUM_INTS)
- continue;
- branch = i;
- }
- }
- return branch;
-}
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-#if 0 /* FIXME */
-/* both iso and interrupt requests have periods; this routine puts them
- * into the schedule tree in the apppropriate place. most iso devices use
- * 1msec periods, but that's not required.
- */
-static void periodic_link(struct admhcd *ahcd, struct ed *ed)
-{
- unsigned i;
-
- admhc_vdbg(ahcd, "link %sed %p branch %d [%dus.], interval %d\n",
- (ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "",
- ed, ed->branch, ed->load, ed->interval);
-
- for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
- struct ed **prev = &ahcd->periodic[i];
- __hc32 *prev_p = &ahcd->hcca->int_table[i];
- struct ed *here = *prev;
-
- /* sorting each branch by period (slow before fast)
- * lets us share the faster parts of the tree.
- * (plus maybe: put interrupt eds before iso)
- */
- while (here && ed != here) {
- if (ed->interval > here->interval)
- break;
- prev = &here->ed_next;
- prev_p = &here->hwNextED;
- here = *prev;
- }
- if (ed != here) {
- ed->ed_next = here;
- if (here)
- ed->hwNextED = *prev_p;
- wmb();
- *prev = ed;
- *prev_p = cpu_to_hc32(ahcd, ed->dma);
- wmb();
- }
- ahcd->load[i] += ed->load;
- }
- admhcd_to_hcd(ahcd)->self.bandwidth_allocated += ed->load / ed->interval;
-}
-#endif
-
-/* link an ed into the HC chain */
-
-static int ed_schedule(struct admhcd *ahcd, struct ed *ed)
-{
- struct ed *old_tail;
-
- if (admhcd_to_hcd(ahcd)->state == HC_STATE_QUIESCING)
- return -EAGAIN;
-
- ed->state = ED_OPER;
-
- old_tail = ahcd->ed_tails[ed->type];
-
- ed->ed_next = old_tail->ed_next;
- if (ed->ed_next) {
- ed->ed_next->ed_prev = ed;
- ed->hwNextED = cpu_to_hc32(ahcd, ed->ed_next->dma);
- }
- ed->ed_prev = old_tail;
-
- old_tail->ed_next = ed;
- old_tail->hwNextED = cpu_to_hc32(ahcd, ed->dma);
-
- ahcd->ed_tails[ed->type] = ed;
-
- admhc_dma_enable(ahcd);
-
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#if 0 /* FIXME */
-/* scan the periodic table to find and unlink this ED */
-static void periodic_unlink(struct admhcd *ahcd, struct ed *ed)
-{
- int i;
-
- for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
- struct ed *temp;
- struct ed **prev = &ahcd->periodic[i];
- __hc32 *prev_p = &ahcd->hcca->int_table[i];
-
- while (*prev && (temp = *prev) != ed) {
- prev_p = &temp->hwNextED;
- prev = &temp->ed_next;
- }
- if (*prev) {
- *prev_p = ed->hwNextED;
- *prev = ed->ed_next;
- }
- ahcd->load[i] -= ed->load;
- }
-
- admhcd_to_hcd(ahcd)->self.bandwidth_allocated -= ed->load / ed->interval;
- admhc_vdbg(ahcd, "unlink %sed %p branch %d [%dus.], interval %d\n",
- (ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "",
- ed, ed->branch, ed->load, ed->interval);
-}
-#endif
-
-/* unlink an ed from the HC chain.
- * just the link to the ed is unlinked.
- * the link from the ed still points to another operational ed or 0
- * so the HC can eventually finish the processing of the unlinked ed
- * (assuming it already started that, which needn't be true).
- *
- * ED_UNLINK is a transient state: the HC may still see this ED, but soon
- * it won't. ED_SKIP means the HC will finish its current transaction,
- * but won't start anything new. The TD queue may still grow; device
- * drivers don't know about this HCD-internal state.
- *
- * When the HC can't see the ED, something changes ED_UNLINK to one of:
- *
- * - ED_OPER: when there's any request queued, the ED gets rescheduled
- * immediately. HC should be working on them.
- *
- * - ED_IDLE: when there's no TD queue. there's no reason for the HC
- * to care about this ED; safe to disable the endpoint.
- *
- * When finish_unlinks() runs later, after SOF interrupt, it will often
- * complete one or more URB unlinks before making that state change.
- */
-static void ed_deschedule(struct admhcd *ahcd, struct ed *ed)
-{
-
-#ifdef ADMHC_VERBOSE_DEBUG
- admhc_dump_ed(ahcd, "ED-DESCHED", ed, 1);
-#endif
-
- ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
- wmb();
- ed->state = ED_UNLINK;
-
- /* remove this ED from the HC list */
- ed->ed_prev->hwNextED = ed->hwNextED;
-
- /* and remove it from our list also */
- ed->ed_prev->ed_next = ed->ed_next;
-
- if (ed->ed_next)
- ed->ed_next->ed_prev = ed->ed_prev;
-
- if (ahcd->ed_tails[ed->type] == ed)
- ahcd->ed_tails[ed->type] = ed->ed_prev;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static struct ed *ed_create(struct admhcd *ahcd, unsigned int type, u32 info)
-{
- struct ed *ed;
- struct td *td;
-
- ed = ed_alloc(ahcd, GFP_ATOMIC);
- if (!ed)
- goto err;
-
- /* dummy td; end of td list for this ed */
- td = td_alloc(ahcd, GFP_ATOMIC);
- if (!td)
- goto err_free_ed;
-
- switch (type) {
- case PIPE_INTERRUPT:
- info |= ED_INT;
- break;
- case PIPE_ISOCHRONOUS:
- info |= ED_ISO;
- break;
- }
-
- ed->dummy = td;
- ed->state = ED_IDLE;
- ed->type = type;
-
- ed->hwINFO = cpu_to_hc32(ahcd, info);
- ed->hwTailP = cpu_to_hc32(ahcd, td->td_dma);
- ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
-
- return ed;
-
-err_free_ed:
- ed_free(ahcd, ed);
-err:
- return NULL;
-}
-
-/* get and maybe (re)init an endpoint. init _should_ be done only as part
- * of enumeration, usb_set_configuration() or usb_set_interface().
- */
-static struct ed *ed_get(struct admhcd *ahcd, struct usb_host_endpoint *ep,
- struct usb_device *udev, unsigned int pipe, int interval)
-{
- struct ed *ed;
- unsigned long flags;
-
- spin_lock_irqsave(&ahcd->lock, flags);
-
- ed = ep->hcpriv;
- if (!ed) {
- u32 info;
-
- /* FIXME: usbcore changes dev->devnum before SET_ADDRESS
- * succeeds ... otherwise we wouldn't need "pipe".
- */
- info = usb_pipedevice(pipe);
- info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << ED_EN_SHIFT;
- info |= le16_to_cpu(ep->desc.wMaxPacketSize) << ED_MPS_SHIFT;
- if (udev->speed == USB_SPEED_FULL)
- info |= ED_SPEED_FULL;
-
- ed = ed_create(ahcd, usb_pipetype(pipe), info);
- if (ed)
- ep->hcpriv = ed;
- }
-
- spin_unlock_irqrestore(&ahcd->lock, flags);
-
- return ed;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* request unlinking of an endpoint from an operational HC.
- * put the ep on the rm_list
- * real work is done at the next start frame (SOFI) hardware interrupt
- * caller guarantees HCD is running, so hardware access is safe,
- * and that ed->state is ED_OPER
- */
-static void start_ed_unlink(struct admhcd *ahcd, struct ed *ed)
-{
-
-#ifdef ADMHC_VERBOSE_DEBUG
- admhc_dump_ed(ahcd, "ED-UNLINK", ed, 1);
-#endif
-
- ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE);
- ed_deschedule(ahcd, ed);
-
- /* add this ED into the remove list */
- ed->ed_rm_next = ahcd->ed_rm_list;
- ahcd->ed_rm_list = ed;
-
- /* enable SOF interrupt */
- admhc_intr_ack(ahcd, ADMHC_INTR_SOFI);
- admhc_intr_enable(ahcd, ADMHC_INTR_SOFI);
- /* flush those writes */
- admhc_writel_flush(ahcd);
-
- /* SOF interrupt might get delayed; record the frame counter value that
- * indicates when the HC isn't looking at it, so concurrent unlinks
- * behave. frame_no wraps every 2^16 msec, and changes right before
- * SOF is triggered.
- */
- ed->tick = admhc_frame_no(ahcd) + 1;
-}
-
-/*-------------------------------------------------------------------------*
- * TD handling functions
- *-------------------------------------------------------------------------*/
-
-/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-
-static void
-td_fill(struct admhcd *ahcd, u32 info, dma_addr_t data, int len,
- struct urb *urb, int index)
-{
- struct td *td, *td_pt;
- struct urb_priv *urb_priv = urb->hcpriv;
- int hash;
- u32 cbl = 0;
-
-#if 1
- if (index == (urb_priv->td_cnt - 1) &&
- ((urb->transfer_flags & URB_NO_INTERRUPT) == 0))
- cbl |= TD_IE;
-#else
- if (index == (urb_priv->td_cnt - 1))
- cbl |= TD_IE;
-#endif
-
- /* use this td as the next dummy */
- td_pt = urb_priv->td[index];
-
- /* fill the old dummy TD */
- td = urb_priv->td[index] = urb_priv->ed->dummy;
- urb_priv->ed->dummy = td_pt;
-
- td->ed = urb_priv->ed;
- td->next_dl_td = NULL;
- td->index = index;
- td->urb = urb;
- td->data_dma = data;
- if (!len)
- data = 0;
-
- if (data)
- cbl |= (len & TD_BL_MASK);
-
- info |= TD_OWN;
-
- /* setup hardware specific fields */
- td->hwINFO = cpu_to_hc32(ahcd, info);
- td->hwDBP = cpu_to_hc32(ahcd, data);
- td->hwCBL = cpu_to_hc32(ahcd, cbl);
- td->hwNextTD = cpu_to_hc32(ahcd, td_pt->td_dma);
-
- /* append to queue */
- list_add_tail(&td->td_list, &td->ed->td_list);
-
- /* hash it for later reverse mapping */
- hash = TD_HASH_FUNC(td->td_dma);
- td->td_hash = ahcd->td_hash[hash];
- ahcd->td_hash[hash] = td;
-
- /* HC might read the TD (or cachelines) right away ... */
- wmb();
- td->ed->hwTailP = td->hwNextTD;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Prepare all TDs of a transfer, and queue them onto the ED.
- * Caller guarantees HC is active.
- * Usually the ED is already on the schedule, so TDs might be
- * processed as soon as they're queued.
- */
-static void td_submit_urb(struct admhcd *ahcd, struct urb *urb)
-{
- struct urb_priv *urb_priv = urb->hcpriv;
- dma_addr_t data;
- int data_len = urb->transfer_buffer_length;
- int cnt = 0;
- u32 info = 0;
- int is_out = usb_pipeout(urb->pipe);
- u32 toggle = 0;
-
- /* OHCI handles the bulk/interrupt data toggles itself. We just
- * use the device toggle bits for resetting, and rely on the fact
- * that resetting toggle is meaningless if the endpoint is active.
- */
-
- if (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), is_out)) {
- toggle = TD_T_CARRY;
- } else {
- toggle = TD_T_DATA0;
- usb_settoggle(urb->dev, usb_pipeendpoint (urb->pipe),
- is_out, 1);
- }
-
- urb_priv->td_idx = 0;
- list_add(&urb_priv->pending, &ahcd->pending);
-
- if (data_len)
- data = urb->transfer_dma;
- else
- data = 0;
-
- /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
- * using TD_CC_GET, as well as by seeing them on the done list.
- * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
- */
- switch (urb_priv->ed->type) {
- case PIPE_INTERRUPT:
- info = is_out
- ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
- : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
-
- /* setup service interval and starting frame number */
- info |= (urb->start_frame & TD_FN_MASK);
- info |= (urb->interval & TD_ISI_MASK) << TD_ISI_SHIFT;
-
- td_fill(ahcd, info, data, data_len, urb, cnt);
- cnt++;
-
- admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs++;
- break;
-
- case PIPE_BULK:
- info = is_out
- ? TD_SCC_NOTACCESSED | TD_DP_OUT
- : TD_SCC_NOTACCESSED | TD_DP_IN;
-
- /* TDs _could_ transfer up to 8K each */
- while (data_len > TD_DATALEN_MAX) {
- td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
- data, TD_DATALEN_MAX, urb, cnt);
- data += TD_DATALEN_MAX;
- data_len -= TD_DATALEN_MAX;
- cnt++;
- }
-
- td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle), data,
- data_len, urb, cnt);
- cnt++;
-
- if ((urb->transfer_flags & URB_ZERO_PACKET)
- && (cnt < urb_priv->td_cnt)) {
- td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
- 0, 0, urb, cnt);
- cnt++;
- }
- break;
-
- /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
- * any DATA phase works normally, and the STATUS ack is special.
- */
- case PIPE_CONTROL:
- /* fill a TD for the setup */
- info = TD_SCC_NOTACCESSED | TD_DP_SETUP | TD_T_DATA0;
- td_fill(ahcd, info, urb->setup_dma, 8, urb, cnt++);
-
- if (data_len > 0) {
- /* fill a TD for the data */
- info = TD_SCC_NOTACCESSED | TD_T_DATA1;
- info |= is_out ? TD_DP_OUT : TD_DP_IN;
- /* NOTE: mishandles transfers >8K, some >4K */
- td_fill(ahcd, info, data, data_len, urb, cnt++);
- }
-
- /* fill a TD for the ACK */
- info = (is_out || data_len == 0)
- ? TD_SCC_NOTACCESSED | TD_DP_IN | TD_T_DATA1
- : TD_SCC_NOTACCESSED | TD_DP_OUT | TD_T_DATA1;
- td_fill(ahcd, info, data, 0, urb, cnt++);
-
- break;
-
- /* ISO has no retransmit, so no toggle;
- * Each TD could handle multiple consecutive frames (interval 1);
- * we could often reduce the number of TDs here.
- */
- case PIPE_ISOCHRONOUS:
- info = is_out
- ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
- : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
-
- for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
- int frame = urb->start_frame;
-
- frame += cnt * urb->interval;
- frame &= TD_FN_MASK;
- td_fill(ahcd, info | frame,
- data + urb->iso_frame_desc[cnt].offset,
- urb->iso_frame_desc[cnt].length, urb, cnt);
- }
- admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs++;
- break;
- }
-
- if (urb_priv->td_cnt != cnt)
- admhc_err(ahcd, "bad number of tds created for urb %p\n", urb);
-}
-
-/*-------------------------------------------------------------------------*
- * Done List handling functions
- *-------------------------------------------------------------------------*/
-
-/* calculate transfer length/status and update the urb */
-static int td_done(struct admhcd *ahcd, struct urb *urb, struct td *td)
-{
- struct urb_priv *urb_priv = urb->hcpriv;
- u32 info;
- u32 bl;
- u32 tdDBP;
- int type = usb_pipetype(urb->pipe);
- int cc;
- int status = -EINPROGRESS;
-
- info = hc32_to_cpup(ahcd, &td->hwINFO);
- tdDBP = hc32_to_cpup(ahcd, &td->hwDBP);
- bl = TD_BL_GET(hc32_to_cpup(ahcd, &td->hwCBL));
- cc = TD_CC_GET(info);
-
- /* ISO ... drivers see per-TD length/status */
- if (type == PIPE_ISOCHRONOUS) {
- /* TODO */
- int dlen = 0;
-
- /* NOTE: assumes FC in tdINFO == 0, and that
- * only the first of 0..MAXPSW psws is used.
- */
- if (info & TD_CC) /* hc didn't touch? */
- return status;
-
- if (usb_pipeout(urb->pipe))
- dlen = urb->iso_frame_desc[td->index].length;
- else {
- /* short reads are always OK for ISO */
- if (cc == TD_CC_DATAUNDERRUN)
- cc = TD_CC_NOERROR;
- dlen = tdDBP - td->data_dma + bl;
- }
-
- urb->actual_length += dlen;
- urb->iso_frame_desc[td->index].actual_length = dlen;
- urb->iso_frame_desc[td->index].status = cc_to_error[cc];
-
- if (cc != TD_CC_NOERROR)
- admhc_vdbg(ahcd,
- "urb %p iso td %p (%d) len %d cc %d\n",
- urb, td, 1 + td->index, dlen, cc);
-
- /* BULK, INT, CONTROL ... drivers see aggregate length/status,
- * except that "setup" bytes aren't counted and "short" transfers
- * might not be reported as errors.
- */
- } else {
- /* update packet status if needed (short is normally ok) */
- if (cc == TD_CC_DATAUNDERRUN
- && !(urb->transfer_flags & URB_SHORT_NOT_OK))
- cc = TD_CC_NOERROR;
-
- if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
- status = cc_to_error[cc];
-
-
- /* count all non-empty packets except control SETUP packet */
- if ((type != PIPE_CONTROL || td->index != 0) && tdDBP != 0)
- urb->actual_length += tdDBP - td->data_dma + bl;
-
- if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
- admhc_vdbg(ahcd,
- "urb %p td %p (%d) cc %d, len=%d/%d\n",
- urb, td, td->index, cc,
- urb->actual_length,
- urb->transfer_buffer_length);
- }
-
- list_del(&td->td_list);
- urb_priv->td_idx++;
-
- return status;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static void ed_halted(struct admhcd *ahcd, struct td *td, int cc)
-{
- struct urb *urb = td->urb;
- struct urb_priv *urb_priv = urb->hcpriv;
- struct ed *ed = td->ed;
- struct list_head *tmp = td->td_list.next;
- __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
-
- admhc_dump_ed(ahcd, "ed halted", td->ed, 1);
- /* clear ed halt; this is the td that caused it, but keep it inactive
- * until its urb->complete() has a chance to clean up.
- */
- ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
- wmb();
- ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
-
- /* Get rid of all later tds from this urb. We don't have
- * to be careful: no errors and nothing was transferred.
- * Also patch the ed so it looks as if those tds completed normally.
- */
- while (tmp != &ed->td_list) {
- struct td *next;
-
- next = list_entry(tmp, struct td, td_list);
- tmp = next->td_list.next;
-
- if (next->urb != urb)
- break;
-
- /* NOTE: if multi-td control DATA segments get supported,
- * this urb had one of them, this td wasn't the last td
- * in that segment (TD_R clear), this ed halted because
- * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
- * then we need to leave the control STATUS packet queued
- * and clear ED_SKIP.
- */
- list_del(&next->td_list);
- urb_priv->td_cnt++;
- ed->hwHeadP = next->hwNextTD | toggle;
- }
-
- /* help for troubleshooting: report anything that
- * looks odd ... that doesn't include protocol stalls
- * (or maybe some other things)
- */
- switch (cc) {
- case TD_CC_DATAUNDERRUN:
- if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
- break;
- /* fallthrough */
- case TD_CC_STALL:
- if (usb_pipecontrol(urb->pipe))
- break;
- /* fallthrough */
- default:
- admhc_dbg(ahcd,
- "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
- urb, urb->dev->devpath,
- usb_pipeendpoint (urb->pipe),
- usb_pipein(urb->pipe) ? "in" : "out",
- hc32_to_cpu(ahcd, td->hwINFO),
- cc, cc_to_error[cc]);
- }
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
-static void
-finish_unlinks(struct admhcd *ahcd, u16 tick)
-{
- struct ed *ed, **last;
-
-rescan_all:
- for (last = &ahcd->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
- struct list_head *entry, *tmp;
- int completed, modified;
- __hc32 *prev;
-
- /* only take off EDs that the HC isn't using, accounting for
- * frame counter wraps and EDs with partially retired TDs
- */
- if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))) {
- if (tick_before(tick, ed->tick)) {
-skip_ed:
- last = &ed->ed_rm_next;
- continue;
- }
-#if 0
- if (!list_empty(&ed->td_list)) {
- struct td *td;
- u32 head;
-
- td = list_entry(ed->td_list.next, struct td,
- td_list);
- head = hc32_to_cpu(ahcd, ed->hwHeadP) &
- TD_MASK;
-
- /* INTR_WDH may need to clean up first */
- if (td->td_dma != head)
- goto skip_ed;
- }
-#endif
- }
-
- /* reentrancy: if we drop the schedule lock, someone might
- * have modified this list. normally it's just prepending
- * entries (which we'd ignore), but paranoia won't hurt.
- */
- *last = ed->ed_rm_next;
- ed->ed_rm_next = NULL;
- modified = 0;
-
- /* unlink urbs as requested, but rescan the list after
- * we call a completion since it might have unlinked
- * another (earlier) urb
- *
- * When we get here, the HC doesn't see this ed. But it
- * must not be rescheduled until all completed URBs have
- * been given back to the driver.
- */
-rescan_this:
- completed = 0;
- prev = &ed->hwHeadP;
- list_for_each_safe(entry, tmp, &ed->td_list) {
- struct td *td;
- struct urb *urb;
- struct urb_priv *urb_priv;
- __hc32 savebits;
- u32 tdINFO;
- int status;
-
- td = list_entry(entry, struct td, td_list);
- urb = td->urb;
- urb_priv = td->urb->hcpriv;
-
- if (!urb->unlinked) {
- prev = &td->hwNextTD;
- continue;
- }
-
- if ((urb_priv) == NULL)
- continue;
-
- /* patch pointer hc uses */
- savebits = *prev & ~cpu_to_hc32(ahcd, TD_MASK);
- *prev = td->hwNextTD | savebits;
- /* If this was unlinked, the TD may not have been
- * retired ... so manually save dhe data toggle.
- * The controller ignores the value we save for
- * control and ISO endpoints.
- */
- tdINFO = hc32_to_cpup(ahcd, &td->hwINFO);
- if ((tdINFO & TD_T) == TD_T_DATA0)
- ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_C);
- else if ((tdINFO & TD_T) == TD_T_DATA1)
- ed->hwHeadP |= cpu_to_hc32(ahcd, ED_C);
-
- /* HC may have partly processed this TD */
-#ifdef ADMHC_VERBOSE_DEBUG
- urb_print(ahcd, urb, "PARTIAL", 0);
-#endif
- status = td_done(ahcd, urb, td);
-
- /* if URB is done, clean up */
- if (urb_priv->td_idx == urb_priv->td_cnt) {
- modified = completed = 1;
- finish_urb(ahcd, urb, status);
- }
- }
- if (completed && !list_empty(&ed->td_list))
- goto rescan_this;
-
- /* ED's now officially unlinked, hc doesn't see */
- ed->state = ED_IDLE;
- ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
- ed->hwNextED = 0;
- wmb();
- ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP | ED_DEQUEUE);
-
- /* but if there's work queued, reschedule */
- if (!list_empty(&ed->td_list)) {
- if (HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))
- ed_schedule(ahcd, ed);
- }
-
- if (modified)
- goto rescan_all;
- }
-}
-
-/*-------------------------------------------------------------------------*/
-/*
- * Process normal completions (error or success) and clean the schedules.
- *
- * This is the main path for handing urbs back to drivers. The only other
- * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
- * instead of scanning the (re-reversed) donelist as this does.
- */
-
-static void ed_unhalt(struct admhcd *ahcd, struct ed *ed, struct urb *urb)
-{
- struct list_head *entry, *tmp;
- __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
-
-#ifdef ADMHC_VERBOSE_DEBUG
- admhc_dump_ed(ahcd, "UNHALT", ed, 0);
-#endif
- /* clear ed halt; this is the td that caused it, but keep it inactive
- * until its urb->complete() has a chance to clean up.
- */
- ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
- wmb();
- ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
-
- list_for_each_safe(entry, tmp, &ed->td_list) {
- struct td *td = list_entry(entry, struct td, td_list);
- __hc32 info;
-
- if (td->urb != urb)
- break;
-
- info = td->hwINFO;
- info &= ~cpu_to_hc32(ahcd, TD_CC | TD_OWN);
- td->hwINFO = info;
-
- ed->hwHeadP = td->hwNextTD | toggle;
- wmb();
- }
-
-}
-
-static void ed_intr_refill(struct admhcd *ahcd, struct ed *ed)
-{
- __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
-
- ed->hwHeadP = ed->hwTailP | toggle;
-}
-
-
-static inline int is_ed_halted(struct admhcd *ahcd, struct ed *ed)
-{
- return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) == ED_H);
-}
-
-static inline int is_td_halted(struct admhcd *ahcd, struct ed *ed,
- struct td *td)
-{
- return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & TD_MASK) ==
- (hc32_to_cpup(ahcd, &td->hwNextTD) & TD_MASK));
-}
-
-static void ed_update(struct admhcd *ahcd, struct ed *ed)
-{
- struct list_head *entry, *tmp;
-
-#ifdef ADMHC_VERBOSE_DEBUG
- admhc_dump_ed(ahcd, "UPDATE", ed, 1);
-#endif
-
- list_for_each_safe(entry, tmp, &ed->td_list) {
- struct td *td = list_entry(entry, struct td, td_list);
- struct urb *urb = td->urb;
- struct urb_priv *urb_priv = urb->hcpriv;
- int status;
-
- if (hc32_to_cpup(ahcd, &td->hwINFO) & TD_OWN)
- break;
-
- /* update URB's length and status from TD */
- status = td_done(ahcd, urb, td);
- if (is_ed_halted(ahcd, ed) && is_td_halted(ahcd, ed, td))
- ed_unhalt(ahcd, ed, urb);
-
- if (ed->type == PIPE_INTERRUPT)
- ed_intr_refill(ahcd, ed);
-
- /* If all this urb's TDs are done, call complete() */
- if (urb_priv->td_idx == urb_priv->td_cnt)
- finish_urb(ahcd, urb, status);
-
- /* clean schedule: unlink EDs that are no longer busy */
- if (list_empty(&ed->td_list)) {
- if (ed->state == ED_OPER)
- start_ed_unlink(ahcd, ed);
-
- /* ... reenabling halted EDs only after fault cleanup */
- } else if ((ed->hwINFO & cpu_to_hc32(ahcd,
- ED_SKIP | ED_DEQUEUE))
- == cpu_to_hc32(ahcd, ED_SKIP)) {
- td = list_entry(ed->td_list.next, struct td, td_list);
-#if 0
- if (!(td->hwINFO & cpu_to_hc32(ahcd, TD_DONE))) {
- ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
- /* ... hc may need waking-up */
- switch (ed->type) {
- case PIPE_CONTROL:
- admhc_writel(ahcd, OHCI_CLF,
- &ahcd->regs->cmdstatus);
- break;
- case PIPE_BULK:
- admhc_writel(ahcd, OHCI_BLF,
- &ahcd->regs->cmdstatus);
- break;
- }
- }
-#else
- if ((td->hwINFO & cpu_to_hc32(ahcd, TD_OWN)))
- ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
-#endif
- }
-
- }
-}
-
-/* there are some tds completed; called in_irq(), with HCD locked */
-static void admhc_td_complete(struct admhcd *ahcd)
-{
- struct ed *ed;
-
- for (ed = ahcd->ed_head; ed; ed = ed->ed_next) {
- if (ed->state != ED_OPER)
- continue;
-
- ed_update(ahcd, ed);
- }
-}
+++ /dev/null
-/*
- * ADM5120 HCD (Host Controller Driver) for USB
- *
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This file was derived from: drivers/usb/host/ohci.h
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- */
-
-/*
- * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
- * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
- * host controller implementation.
- */
-typedef __u32 __bitwise __hc32;
-typedef __u16 __bitwise __hc16;
-
-/*
- * OHCI Endpoint Descriptor (ED) ... holds TD queue
- * See OHCI spec, section 4.2
- *
- * This is a "Queue Head" for those transfers, which is why
- * both EHCI and UHCI call similar structures a "QH".
- */
-
-#define TD_DATALEN_MAX 4096
-
-#define ED_ALIGN 16
-#define ED_MASK ((u32)~(ED_ALIGN-1)) /* strip hw status in low addr bits */
-
-struct ed {
- /* first fields are hardware-specified */
- __hc32 hwINFO; /* endpoint config bitmap */
- /* info bits defined by hcd */
-#define ED_DEQUEUE (1 << 27)
- /* info bits defined by the hardware */
-#define ED_MPS_SHIFT 16
-#define ED_MPS_MASK ((1 << 11)-1)
-#define ED_MPS_GET(x) (((x) >> ED_MPS_SHIFT) & ED_MPS_MASK)
-#define ED_ISO (1 << 15) /* isochronous endpoint */
-#define ED_SKIP (1 << 14)
-#define ED_SPEED_FULL (1 << 13) /* fullspeed device */
-#define ED_INT (1 << 11) /* interrupt endpoint */
-#define ED_EN_SHIFT 7 /* endpoint shift */
-#define ED_EN_MASK ((1 << 4)-1) /* endpoint mask */
-#define ED_EN_GET(x) (((x) >> ED_EN_SHIFT) & ED_EN_MASK)
-#define ED_FA_MASK ((1 << 7)-1) /* function address mask */
-#define ED_FA_GET(x) ((x) & ED_FA_MASK)
- __hc32 hwTailP; /* tail of TD list */
- __hc32 hwHeadP; /* head of TD list (hc r/w) */
-#define ED_C (0x02) /* toggle carry */
-#define ED_H (0x01) /* halted */
- __hc32 hwNextED; /* next ED in list */
-
- /* rest are purely for the driver's use */
- dma_addr_t dma; /* addr of ED */
- struct td *dummy; /* next TD to activate */
-
- struct list_head urb_list; /* list of our URBs */
-
- /* host's view of schedule */
- struct ed *ed_next; /* on schedule list */
- struct ed *ed_prev; /* for non-interrupt EDs */
- struct ed *ed_rm_next; /* on rm list */
- struct list_head td_list; /* "shadow list" of our TDs */
-
- /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
- * usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
- */
- u8 state; /* ED_{IDLE,UNLINK,OPER} */
-#define ED_IDLE 0x00 /* NOT linked to HC */
-#define ED_UNLINK 0x01 /* being unlinked from hc */
-#define ED_OPER 0x02 /* IS linked to hc */
-
- u8 type; /* PIPE_{BULK,...} */
-
- /* periodic scheduling params (for intr and iso) */
- u8 branch;
- u16 interval;
- u16 load;
- u16 last_iso; /* iso only */
-
- /* HC may see EDs on rm_list until next frame (frame_no == tick) */
- u16 tick;
-} __attribute__ ((aligned(ED_ALIGN)));
-
-/*
- * OHCI Transfer Descriptor (TD) ... one per transfer segment
- * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
- * and 4.3.2 (iso)
- */
-
-#define TD_ALIGN 32
-#define TD_MASK ((u32)~(TD_ALIGN-1)) /* strip hw status in low addr bits */
-
-struct td {
- /* first fields are hardware-specified */
- __hc32 hwINFO; /* transfer info bitmask */
-
- /* hwINFO bits */
-#define TD_OWN (1 << 31) /* owner of the descriptor */
-#define TD_CC_SHIFT 27 /* condition code */
-#define TD_CC_MASK 0xf
-#define TD_CC (TD_CC_MASK << TD_CC_SHIFT)
-#define TD_CC_GET(x) (((x) >> TD_CC_SHIFT) & TD_CC_MASK)
-
-#define TD_EC_SHIFT 25 /* error count */
-#define TD_EC_MASK 0x3
-#define TD_EC (TD_EC_MASK << TD_EC_SHIFT)
-#define TD_EC_GET(x) ((x >> TD_EC_SHIFT) & TD_EC_MASK)
-#define TD_T_SHIFT 23 /* data toggle state */
-#define TD_T_MASK 0x3
-#define TD_T (TD_T_MASK << TD_T_SHIFT)
-#define TD_T_DATA0 (0x2 << TD_T_SHIFT) /* DATA0 */
-#define TD_T_DATA1 (0x3 << TD_T_SHIFT) /* DATA1 */
-#define TD_T_CARRY (0x0 << TD_T_SHIFT) /* uses ED_C */
-#define TD_T_GET(x) (((x) >> TD_T_SHIFT) & TD_T_MASK)
-#define TD_DP_SHIFT 21 /* direction/pid */
-#define TD_DP_MASK 0x3
-#define TD_DP (TD_DP_MASK << TD_DP_SHIFT)
-#define TD_DP_GET (((x) >> TD_DP_SHIFT) & TD_DP_MASK)
-#define TD_DP_SETUP (0x0 << TD_DP_SHIFT) /* SETUP pid */
-#define TD_DP_OUT (0x1 << TD_DP_SHIFT) /* OUT pid */
-#define TD_DP_IN (0x2 << TD_DP_SHIFT) /* IN pid */
-#define TD_ISI_SHIFT 8 /* Interrupt Service Interval */
-#define TD_ISI_MASK 0x3f
-#define TD_ISI_GET(x) (((x) >> TD_ISI_SHIFT) & TD_ISI_MASK)
-#define TD_FN_MASK 0x3f /* frame number */
-#define TD_FN_GET(x) ((x) & TD_FN_MASK)
-
- __hc32 hwDBP; /* Data Buffer Pointer (or 0) */
- __hc32 hwCBL; /* Controller/Buffer Length */
-
- /* hwCBL bits */
-#define TD_BL_MASK 0xffff /* buffer length */
-#define TD_BL_GET(x) ((x) & TD_BL_MASK)
-#define TD_IE (1 << 16) /* interrupt enable */
- __hc32 hwNextTD; /* Next TD Pointer */
-
- /* rest are purely for the driver's use */
- __u8 index;
- struct ed *ed;
- struct td *td_hash; /* dma-->td hashtable */
- struct td *next_dl_td;
- struct urb *urb;
-
- dma_addr_t td_dma; /* addr of this TD */
- dma_addr_t data_dma; /* addr of data it points to */
-
- struct list_head td_list; /* "shadow list", TDs on same ED */
-
- u32 flags;
-#define TD_FLAG_DONE (1 << 17) /* retired to done list */
-#define TD_FLAG_ISO (1 << 16) /* copy of ED_ISO */
-} __attribute__ ((aligned(TD_ALIGN))); /* c/b/i need 16; only iso needs 32 */
-
-/*
- * Hardware transfer status codes -- CC from td->hwINFO
- */
-#define TD_CC_NOERROR 0x00
-#define TD_CC_CRC 0x01
-#define TD_CC_BITSTUFFING 0x02
-#define TD_CC_DATATOGGLEM 0x03
-#define TD_CC_STALL 0x04
-#define TD_CC_DEVNOTRESP 0x05
-#define TD_CC_PIDCHECKFAIL 0x06
-#define TD_CC_UNEXPECTEDPID 0x07
-#define TD_CC_DATAOVERRUN 0x08
-#define TD_CC_DATAUNDERRUN 0x09
- /* 0x0A, 0x0B reserved for hardware */
-#define TD_CC_BUFFEROVERRUN 0x0C
-#define TD_CC_BUFFERUNDERRUN 0x0D
- /* 0x0E, 0x0F reserved for HCD */
-#define TD_CC_HCD0 0x0E
-#define TD_CC_NOTACCESSED 0x0F
-
-/*
- * preshifted status codes
- */
-#define TD_SCC_NOTACCESSED (TD_CC_NOTACCESSED << TD_CC_SHIFT)
-
-
-/* map OHCI TD status codes (CC) to errno values */
-static const int cc_to_error[16] = {
- /* No Error */ 0,
- /* CRC Error */ -EILSEQ,
- /* Bit Stuff */ -EPROTO,
- /* Data Togg */ -EILSEQ,
- /* Stall */ -EPIPE,
- /* DevNotResp */ -ETIME,
- /* PIDCheck */ -EPROTO,
- /* UnExpPID */ -EPROTO,
- /* DataOver */ -EOVERFLOW,
- /* DataUnder */ -EREMOTEIO,
- /* (for hw) */ -EIO,
- /* (for hw) */ -EIO,
- /* BufferOver */ -ECOMM,
- /* BuffUnder */ -ENOSR,
- /* (for HCD) */ -EALREADY,
- /* (for HCD) */ -EALREADY
-};
-
-#define NUM_INTS 32
-
-/*
- * This is the structure of the OHCI controller's memory mapped I/O region.
- * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
- * Layout is in section 7 (and appendix B) of the spec.
- */
-struct admhcd_regs {
- __hc32 gencontrol; /* General Control */
- __hc32 int_status; /* Interrupt Status */
- __hc32 int_enable; /* Interrupt Enable */
- __hc32 reserved00;
- __hc32 host_control; /* Host General Control */
- __hc32 reserved01;
- __hc32 fminterval; /* Frame Interval */
- __hc32 fmnumber; /* Frame Number */
- __hc32 reserved02;
- __hc32 reserved03;
- __hc32 reserved04;
- __hc32 reserved05;
- __hc32 reserved06;
- __hc32 reserved07;
- __hc32 reserved08;
- __hc32 reserved09;
- __hc32 reserved10;
- __hc32 reserved11;
- __hc32 reserved12;
- __hc32 reserved13;
- __hc32 reserved14;
- __hc32 reserved15;
- __hc32 reserved16;
- __hc32 reserved17;
- __hc32 reserved18;
- __hc32 reserved19;
- __hc32 reserved20;
- __hc32 reserved21;
- __hc32 lsthresh; /* Low Speed Threshold */
- __hc32 rhdesc; /* Root Hub Descriptor */
-#define MAX_ROOT_PORTS 2
- __hc32 portstatus[MAX_ROOT_PORTS]; /* Port Status */
- __hc32 hosthead; /* Host Descriptor Head */
-} __attribute__ ((aligned(32)));
-
-/*
- * General Control register bits
- */
-#define ADMHC_CTRL_UHFE (1 << 0) /* USB Host Function Enable */
-#define ADMHC_CTRL_SIR (1 << 1) /* Software Interrupt request */
-#define ADMHC_CTRL_DMAA (1 << 2) /* DMA Arbitration Control */
-#define ADMHC_CTRL_SR (1 << 3) /* Software Reset */
-
-/*
- * Host General Control register bits
- */
-#define ADMHC_HC_BUSS 0x3 /* USB bus state */
-#define ADMHC_BUSS_RESET 0x0
-#define ADMHC_BUSS_RESUME 0x1
-#define ADMHC_BUSS_OPER 0x2
-#define ADMHC_BUSS_SUSPEND 0x3
-#define ADMHC_HC_DMAE (1 << 2) /* DMA enable */
-
-/*
- * Interrupt Status/Enable register bits
- */
-#define ADMHC_INTR_SOFI (1 << 4) /* start of frame */
-#define ADMHC_INTR_RESI (1 << 5) /* resume detected */
-#define ADMHC_INTR_6 (1 << 6) /* unknown */
-#define ADMHC_INTR_7 (1 << 7) /* unknown */
-#define ADMHC_INTR_BABI (1 << 8) /* babble detected */
-#define ADMHC_INTR_INSM (1 << 9) /* root hub status change */
-#define ADMHC_INTR_SO (1 << 10) /* scheduling overrun */
-#define ADMHC_INTR_FNO (1 << 11) /* frame number overflow */
-#define ADMHC_INTR_TDC (1 << 20) /* transfer descriptor completed */
-#define ADMHC_INTR_SWI (1 << 29) /* software interrupt */
-#define ADMHC_INTR_FATI (1 << 30) /* fatal error */
-#define ADMHC_INTR_INTA (1 << 31) /* interrupt active */
-
-#define ADMHC_INTR_MIE (1 << 31) /* master interrupt enable */
-
-/*
- * SOF Frame Interval register bits
- */
-#define ADMHC_SFI_FI_MASK ((1 << 14)-1) /* Frame Interval value */
-#define ADMHC_SFI_FSLDP_SHIFT 16
-#define ADMHC_SFI_FSLDP_MASK ((1 << 15)-1)
-#define ADMHC_SFI_FIT (1 << 31) /* Frame Interval Toggle */
-
-/*
- * SOF Frame Number register bits
- */
-#define ADMHC_SFN_FN_MASK ((1 << 16)-1) /* Frame Number Mask */
-#define ADMHC_SFN_FR_SHIFT 16 /* Frame Remaining Shift */
-#define ADMHC_SFN_FR_MASK ((1 << 14)-1) /* Frame Remaining Mask */
-#define ADMHC_SFN_FRT (1 << 31) /* Frame Remaining Toggle */
-
-/*
- * Root Hub Descriptor register bits
- */
-#define ADMHC_RH_NUMP 0xff /* number of ports */
-#define ADMHC_RH_PSM (1 << 8) /* power switching mode */
-#define ADMHC_RH_NPS (1 << 9) /* no power switching */
-#define ADMHC_RH_OCPM (1 << 10) /* over current protection mode */
-#define ADMHC_RH_NOCP (1 << 11) /* no over current protection */
-#define ADMHC_RH_PPCM (0xff << 16) /* port power control */
-
-#define ADMHC_RH_LPS (1 << 24) /* local power switch */
-#define ADMHC_RH_OCI (1 << 25) /* over current indicator */
-
-/* status change bits */
-#define ADMHC_RH_LPSC (1 << 26) /* local power switch change */
-#define ADMHC_RH_OCIC (1 << 27) /* over current indicator change */
-
-#define ADMHC_RH_DRWE (1 << 28) /* device remote wakeup enable */
-#define ADMHC_RH_CRWE (1 << 29) /* clear remote wakeup enable */
-
-#define ADMHC_RH_CGP (1 << 24) /* clear global power */
-#define ADMHC_RH_SGP (1 << 26) /* set global power */
-
-/*
- * Port Status register bits
- */
-#define ADMHC_PS_CCS (1 << 0) /* current connect status */
-#define ADMHC_PS_PES (1 << 1) /* port enable status */
-#define ADMHC_PS_PSS (1 << 2) /* port suspend status */
-#define ADMHC_PS_POCI (1 << 3) /* port over current indicator */
-#define ADMHC_PS_PRS (1 << 4) /* port reset status */
-#define ADMHC_PS_PPS (1 << 8) /* port power status */
-#define ADMHC_PS_LSDA (1 << 9) /* low speed device attached */
-
-/* status change bits */
-#define ADMHC_PS_CSC (1 << 16) /* connect status change */
-#define ADMHC_PS_PESC (1 << 17) /* port enable status change */
-#define ADMHC_PS_PSSC (1 << 18) /* port suspend status change */
-#define ADMHC_PS_OCIC (1 << 19) /* over current indicator change */
-#define ADMHC_PS_PRSC (1 << 20) /* port reset status change */
-
-/* port feature bits */
-#define ADMHC_PS_CPE (1 << 0) /* clear port enable */
-#define ADMHC_PS_SPE (1 << 1) /* set port enable */
-#define ADMHC_PS_SPS (1 << 2) /* set port suspend */
-#define ADMHC_PS_CPS (1 << 3) /* clear suspend status */
-#define ADMHC_PS_SPR (1 << 4) /* set port reset */
-#define ADMHC_PS_SPP (1 << 8) /* set port power */
-#define ADMHC_PS_CPP (1 << 9) /* clear port power */
-
-/*
- * the POTPGT value is not defined in the ADMHC, so define a dummy value
- */
-#define ADMHC_POTPGT 2 /* in ms */
-
-/* hcd-private per-urb state */
-struct urb_priv {
- struct ed *ed;
- struct list_head pending; /* URBs on the same ED */
-
- u32 td_cnt; /* # tds in this request */
- u32 td_idx; /* index of the current td */
- struct td *td[0]; /* all TDs in this request */
-};
-
-#define TD_HASH_SIZE 64 /* power'o'two */
-/* sizeof (struct td) ~= 64 == 2^6 ... */
-#define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
-
-/*
- * This is the full ADMHCD controller description
- *
- * Note how the "proper" USB information is just
- * a subset of what the full implementation needs. (Linus)
- */
-
-struct admhcd {
- spinlock_t lock;
-
- /*
- * I/O memory used to communicate with the HC (dma-consistent)
- */
- struct admhcd_regs __iomem *regs;
-
- /*
- * hcd adds to schedule for a live hc any time, but removals finish
- * only at the start of the next frame.
- */
-
- struct ed *ed_head;
- struct ed *ed_tails[4];
-
- struct ed *ed_rm_list; /* to be removed */
-
- struct ed *periodic[NUM_INTS]; /* shadow int_table */
-
-#if 0 /* TODO: remove? */
- /*
- * OTG controllers and transceivers need software interaction;
- * other external transceivers should be software-transparent
- */
- struct otg_transceiver *transceiver;
- void (*start_hnp)(struct admhcd *ahcd);
-#endif
-
- /*
- * memory management for queue data structures
- */
- struct dma_pool *td_cache;
- struct dma_pool *ed_cache;
- struct td *td_hash[TD_HASH_SIZE];
- struct list_head pending;
-
- /*
- * driver state
- */
- int num_ports;
- int load[NUM_INTS];
- u32 host_control; /* copy of the host_control reg */
- unsigned long next_statechange; /* suspend/resume */
- u32 fminterval; /* saved register */
- unsigned autostop:1; /* rh auto stopping/stopped */
-
- unsigned long flags; /* for HC bugs */
-#define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */
-#define OHCI_QUIRK_SUPERIO 0x02 /* natsemi */
-#define OHCI_QUIRK_INITRESET 0x04 /* SiS, OPTi, ... */
-#define OHCI_QUIRK_BE_DESC 0x08 /* BE descriptors */
-#define OHCI_QUIRK_BE_MMIO 0x10 /* BE registers */
-#define OHCI_QUIRK_ZFMICRO 0x20 /* Compaq ZFMicro chipset*/
- /* there are also chip quirks/bugs in init logic */
-
-#ifdef DEBUG
- struct dentry *debug_dir;
- struct dentry *debug_async;
- struct dentry *debug_periodic;
- struct dentry *debug_registers;
-#endif
-};
-
-/* convert between an hcd pointer and the corresponding ahcd_hcd */
-static inline struct admhcd *hcd_to_admhcd(struct usb_hcd *hcd)
-{
- return (struct admhcd *)(hcd->hcd_priv);
-}
-static inline struct usb_hcd *admhcd_to_hcd(const struct admhcd *ahcd)
-{
- return container_of((void *)ahcd, struct usb_hcd, hcd_priv);
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifndef DEBUG
-#define STUB_DEBUG_FILES
-#endif /* DEBUG */
-
-#ifdef DEBUG
-# define admhc_dbg(ahcd, fmt, args...) \
- printk(KERN_DEBUG "adm5120-hcd: " fmt, ## args)
-#else
-# define admhc_dbg(ahcd, fmt, args...) do { } while (0)
-#endif
-
-#define admhc_err(ahcd, fmt, args...) \
- printk(KERN_ERR "adm5120-hcd: " fmt, ## args)
-#define admhc_info(ahcd, fmt, args...) \
- printk(KERN_INFO "adm5120-hcd: " fmt, ## args)
-#define admhc_warn(ahcd, fmt, args...) \
- printk(KERN_WARNING "adm5120-hcd: " fmt, ## args)
-
-#ifdef ADMHC_VERBOSE_DEBUG
-# define admhc_vdbg admhc_dbg
-#else
-# define admhc_vdbg(ahcd, fmt, args...) do { } while (0)
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * While most USB host controllers implement their registers and
- * in-memory communication descriptors in little-endian format,
- * a minority (notably the IBM STB04XXX and the Motorola MPC5200
- * processors) implement them in big endian format.
- *
- * In addition some more exotic implementations like the Toshiba
- * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
- * they have a different endianness for registers vs. in-memory
- * descriptors.
- *
- * This attempts to support either format at compile time without a
- * runtime penalty, or both formats with the additional overhead
- * of checking a flag bit.
- *
- * That leads to some tricky Kconfig rules howevber. There are
- * different defaults based on some arch/ppc platforms, though
- * the basic rules are:
- *
- * Controller type Kconfig options needed
- * --------------- ----------------------
- * little endian CONFIG_USB_ADMHC_LITTLE_ENDIAN
- *
- * fully big endian CONFIG_USB_ADMHC_BIG_ENDIAN_DESC _and_
- * CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
- *
- * mixed endian CONFIG_USB_ADMHC_LITTLE_ENDIAN _and_
- * CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC}
- *
- * (If you have a mixed endian controller, you -must- also define
- * CONFIG_USB_ADMHC_LITTLE_ENDIAN or things will not work when building
- * both your mixed endian and a fully big endian controller support in
- * the same kernel image).
- */
-
-#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_DESC
-#ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
-#define big_endian_desc(ahcd) (ahcd->flags & OHCI_QUIRK_BE_DESC)
-#else
-#define big_endian_desc(ahcd) 1 /* only big endian */
-#endif
-#else
-#define big_endian_desc(ahcd) 0 /* only little endian */
-#endif
-
-#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
-#ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
-#define big_endian_mmio(ahcd) (ahcd->flags & OHCI_QUIRK_BE_MMIO)
-#else
-#define big_endian_mmio(ahcd) 1 /* only big endian */
-#endif
-#else
-#define big_endian_mmio(ahcd) 0 /* only little endian */
-#endif
-
-/*
- * Big-endian read/write functions are arch-specific.
- * Other arches can be added if/when they're needed.
- *
- */
-static inline unsigned int admhc_readl(const struct admhcd *ahcd,
- __hc32 __iomem *regs)
-{
-#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
- return big_endian_mmio(ahcd) ?
- readl_be(regs) :
- readl(regs);
-#else
- return readl(regs);
-#endif
-}
-
-static inline void admhc_writel(const struct admhcd *ahcd,
- const unsigned int val, __hc32 __iomem *regs)
-{
-#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
- big_endian_mmio(ahcd) ?
- writel_be(val, regs) :
- writel(val, regs);
-#else
- writel(val, regs);
-#endif
-}
-
-static inline void admhc_writel_flush(const struct admhcd *ahcd)
-{
-#if 0
- /* TODO: remove? */
- (void) admhc_readl(ahcd, &ahcd->regs->gencontrol);
-#endif
-}
-
-
-/*-------------------------------------------------------------------------*/
-
-/* cpu to ahcd */
-static inline __hc16 cpu_to_hc16(const struct admhcd *ahcd, const u16 x)
-{
- return big_endian_desc(ahcd) ?
- (__force __hc16)cpu_to_be16(x) :
- (__force __hc16)cpu_to_le16(x);
-}
-
-static inline __hc16 cpu_to_hc16p(const struct admhcd *ahcd, const u16 *x)
-{
- return big_endian_desc(ahcd) ?
- cpu_to_be16p(x) :
- cpu_to_le16p(x);
-}
-
-static inline __hc32 cpu_to_hc32(const struct admhcd *ahcd, const u32 x)
-{
- return big_endian_desc(ahcd) ?
- (__force __hc32)cpu_to_be32(x) :
- (__force __hc32)cpu_to_le32(x);
-}
-
-static inline __hc32 cpu_to_hc32p(const struct admhcd *ahcd, const u32 *x)
-{
- return big_endian_desc(ahcd) ?
- cpu_to_be32p(x) :
- cpu_to_le32p(x);
-}
-
-/* ahcd to cpu */
-static inline u16 hc16_to_cpu(const struct admhcd *ahcd, const __hc16 x)
-{
- return big_endian_desc(ahcd) ?
- be16_to_cpu((__force __be16)x) :
- le16_to_cpu((__force __le16)x);
-}
-
-static inline u16 hc16_to_cpup(const struct admhcd *ahcd, const __hc16 *x)
-{
- return big_endian_desc(ahcd) ?
- be16_to_cpup((__force __be16 *)x) :
- le16_to_cpup((__force __le16 *)x);
-}
-
-static inline u32 hc32_to_cpu(const struct admhcd *ahcd, const __hc32 x)
-{
- return big_endian_desc(ahcd) ?
- be32_to_cpu((__force __be32)x) :
- le32_to_cpu((__force __le32)x);
-}
-
-static inline u32 hc32_to_cpup(const struct admhcd *ahcd, const __hc32 *x)
-{
- return big_endian_desc(ahcd) ?
- be32_to_cpup((__force __be32 *)x) :
- le32_to_cpup((__force __le32 *)x);
-}
-
-/*-------------------------------------------------------------------------*/
-
-static inline u16 admhc_frame_no(const struct admhcd *ahcd)
-{
- u32 t;
-
- t = admhc_readl(ahcd, &ahcd->regs->fmnumber) & ADMHC_SFN_FN_MASK;
- return (u16)t;
-}
-
-static inline u16 admhc_frame_remain(const struct admhcd *ahcd)
-{
- u32 t;
-
- t = admhc_readl(ahcd, &ahcd->regs->fmnumber) >> ADMHC_SFN_FR_SHIFT;
- t &= ADMHC_SFN_FR_MASK;
- return (u16)t;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static inline void admhc_disable(struct admhcd *ahcd)
-{
- admhcd_to_hcd(ahcd)->state = HC_STATE_HALT;
-}
-
-#define FI 0x2edf /* 12000 bits per frame (-1) */
-#define FSLDP(fi) (0x7fff & ((6 * ((fi) - 1200)) / 7))
-#define FIT ADMHC_SFI_FIT
-#define LSTHRESH 0x628 /* lowspeed bit threshold */
-
-static inline void periodic_reinit(struct admhcd *ahcd)
-{
-#if 0
- u32 fi = ahcd->fminterval & ADMHC_SFI_FI_MASK;
- u32 fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
-
- /* TODO: adjust FSLargestDataPacket value too? */
- admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
- &ahcd->regs->fminterval);
-#else
- u32 fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
-
- /* TODO: adjust FSLargestDataPacket value too? */
- admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
- &ahcd->regs->fminterval);
-#endif
-}
-
-static inline u32 admhc_read_rhdesc(struct admhcd *ahcd)
-{
- return admhc_readl(ahcd, &ahcd->regs->rhdesc);
-}
-
-static inline u32 admhc_read_portstatus(struct admhcd *ahcd, int port)
-{
- return admhc_readl(ahcd, &ahcd->regs->portstatus[port]);
-}
-
-static inline void admhc_write_portstatus(struct admhcd *ahcd, int port,
- u32 value)
-{
- admhc_writel(ahcd, value, &ahcd->regs->portstatus[port]);
-}
-
-static inline void roothub_write_status(struct admhcd *ahcd, u32 value)
-{
- /* FIXME: read-only bits must be masked out */
- admhc_writel(ahcd, value, &ahcd->regs->rhdesc);
-}
-
-static inline void admhc_intr_disable(struct admhcd *ahcd, u32 ints)
-{
- u32 t;
-
- t = admhc_readl(ahcd, &ahcd->regs->int_enable);
- t &= ~(ints);
- admhc_writel(ahcd, t, &ahcd->regs->int_enable);
- /* TODO: flush writes ?*/
-}
-
-static inline void admhc_intr_enable(struct admhcd *ahcd, u32 ints)
-{
- u32 t;
-
- t = admhc_readl(ahcd, &ahcd->regs->int_enable);
- t |= ints;
- admhc_writel(ahcd, t, &ahcd->regs->int_enable);
- /* TODO: flush writes ?*/
-}
-
-static inline void admhc_intr_ack(struct admhcd *ahcd, u32 ints)
-{
- admhc_writel(ahcd, ints, &ahcd->regs->int_status);
-}
-
-static inline void admhc_dma_enable(struct admhcd *ahcd)
-{
- u32 t;
-
- t = admhc_readl(ahcd, &ahcd->regs->host_control);
- if (t & ADMHC_HC_DMAE)
- return;
-
- t |= ADMHC_HC_DMAE;
- admhc_writel(ahcd, t, &ahcd->regs->host_control);
- admhc_vdbg(ahcd, "DMA enabled\n");
-}
-
-static inline void admhc_dma_disable(struct admhcd *ahcd)
-{
- u32 t;
-
- t = admhc_readl(ahcd, &ahcd->regs->host_control);
- if (!(t & ADMHC_HC_DMAE))
- return;
-
- t &= ~ADMHC_HC_DMAE;
- admhc_writel(ahcd, t, &ahcd->regs->host_control);
- admhc_vdbg(ahcd, "DMA disabled\n");
-}
+++ /dev/null
-/*
- * ADM5120_WDT 0.01: Infineon ADM5120 SoC watchdog driver
- * Copyright (c) Ondrej Zajicek <santiago@crfreenet.org>, 2007
- *
- * based on
- *
- * RC32434_WDT 0.01: IDT Interprise 79RC32434 watchdog driver
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/watchdog.h>
-#include <linux/irq.h>
-
-#include <asm/bootinfo.h>
-
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-
-#define DEFAULT_TIMEOUT 15 /* (secs) Default is 15 seconds */
-#define MAX_TIMEOUT 327
-/* Max is 327 seconds, counter is 15-bit integer, step is 10 ms */
-
-#define NAME "adm5120_wdt"
-#define VERSION "0.1"
-
-static int expect_close;
-static int access;
-static unsigned int timeout = DEFAULT_TIMEOUT;
-
-static int nowayout = WATCHDOG_NOWAYOUT;
-module_param(nowayout, int, 0);
-MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-MODULE_LICENSE("GPL");
-
-
-static inline void wdt_set_timeout(void)
-{
- u32 val = (1 << 31) | (((timeout * 100) & 0x7FFF) << 16);
- SW_WRITE_REG(SWITCH_REG_WDOG0, val);
-}
-
-/*
- It looks like WDOG0-register-write don't modify counter,
- but WDOG0-register-read resets counter.
-*/
-
-static inline void wdt_reset_counter(void)
-{
- SW_READ_REG(SWITCH_REG_WDOG0);
-}
-
-static inline void wdt_disable(void)
-{
- SW_WRITE_REG(SWITCH_REG_WDOG0, 0x7FFF0000);
-}
-
-
-
-static int wdt_open(struct inode *inode, struct file *file)
-{
- /* Allow only one person to hold it open */
- if (access)
- return -EBUSY;
-
- if (nowayout)
- __module_get(THIS_MODULE);
-
- /* Activate timer */
- wdt_reset_counter();
- wdt_set_timeout();
- printk(KERN_INFO NAME ": enabling watchdog timer\n");
- access = 1;
- return 0;
-}
-
-static int wdt_release(struct inode *inode, struct file *file)
-{
- /*
- * Shut off the timer.
- * Lock it in if it's a module and we set nowayout
- */
- if (expect_close && (nowayout == 0)) {
- wdt_disable();
- printk(KERN_INFO NAME ": disabling watchdog timer\n");
- module_put(THIS_MODULE);
- } else
- printk(KERN_CRIT NAME ": device closed unexpectedly. WDT will not stop!\n");
-
- access = 0;
- return 0;
-}
-
-static ssize_t wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos)
-{
- /* Refresh the timer. */
- if (len) {
- if (!nowayout) {
- size_t i;
-
- /* In case it was set long ago */
- expect_close = 0;
-
- for (i = 0; i != len; i++) {
- char c;
- if (get_user(c, data + i))
- return -EFAULT;
- if (c == 'V')
- expect_close = 1;
- }
- }
- wdt_reset_counter();
- return len;
- }
- return 0;
-}
-
-static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- int new_timeout;
- static struct watchdog_info ident = {
- .options = WDIOF_SETTIMEOUT |
- WDIOF_KEEPALIVEPING |
- WDIOF_MAGICCLOSE,
- .firmware_version = 0,
- .identity = "ADM5120_WDT Watchdog",
- };
- switch (cmd) {
- default:
- return -ENOTTY;
- case WDIOC_GETSUPPORT:
- if (copy_to_user((struct watchdog_info *)arg, &ident, sizeof(ident)))
- return -EFAULT;
- return 0;
- case WDIOC_GETSTATUS:
- case WDIOC_GETBOOTSTATUS:
- return put_user(0, (int *)arg);
- case WDIOC_KEEPALIVE:
- wdt_reset_counter();
- return 0;
- case WDIOC_SETTIMEOUT:
- if (get_user(new_timeout, (int *)arg))
- return -EFAULT;
- if (new_timeout < 1)
- return -EINVAL;
- if (new_timeout > MAX_TIMEOUT)
- return -EINVAL;
- timeout = new_timeout;
- wdt_set_timeout();
- /* Fall */
- case WDIOC_GETTIMEOUT:
- return put_user(timeout, (int *)arg);
- }
-}
-
-static const struct file_operations wdt_fops = {
- .owner = THIS_MODULE,
- .llseek = no_llseek,
- .write = wdt_write,
- .unlocked_ioctl = wdt_ioctl,
- .open = wdt_open,
- .release = wdt_release,
-};
-
-static struct miscdevice wdt_miscdev = {
- .minor = WATCHDOG_MINOR,
- .name = "watchdog",
- .fops = &wdt_fops,
-};
-
-static char banner[] __initdata = KERN_INFO NAME ": Watchdog Timer version " VERSION "\n";
-
-static int __init watchdog_init(void)
-{
- int ret;
-
- ret = misc_register(&wdt_miscdev);
-
- if (ret)
- return ret;
-
- wdt_disable();
- printk(banner);
-
- return 0;
-}
-
-static void __exit watchdog_exit(void)
-{
- misc_deregister(&wdt_miscdev);
-}
-
-module_init(watchdog_init);
-module_exit(watchdog_exit);
+++ /dev/null
-#
-# Copyright (C) 2006-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-LOADER_MAKE := $(NO_TRACE_MAKE) -C lzma-loader KDIR=$(KDIR)
-JFFS2BLOCK := $(KDIR)/jffs2.block
-JFFS2MARK := $(KDIR)/jffs2.mark
-
-define imgname
-$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(patsubst jffs2-%,jffs2,$(1))
-endef
-
-VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux
-fs_squash:=squashfs-only
-fs_all:=all
-fs_4k:=4k
-fs_64k:=64k
-fs_128k:=128k
-
-define Build/Clean
- $(LOADER_MAKE) clean
-endef
-
-define Image/Prepare
- cat $(KDIR)/vmlinux | $(STAGING_DIR_HOST)/bin/lzma e -si -so -eos -lc1 -lp2 -pb2 > $(KDIR)/vmlinux.lzma
- rm -f $(JFFS2BLOCK)
- touch $(JFFS2BLOCK)
- $(call prepare_generic_squashfs,$(JFFS2BLOCK))
- rm -f $(JFFS2MARK)
- touch $(JFFS2MARK)
- $(call add_jffs2_mark,$(JFFS2MARK))
-endef
-
-define Image/Build/Loader
- $(LOADER_MAKE) LOADER=loader-$(1).$(2) LOADER_DATA="" \
- LZMA_TEXT_START=$(3) LZMA_STARTUP_ORG=$(4) \
- CONFIG_PASS_KARGS=$(5) CONFIG_BOARD=$(6) \
- compile loader.$(2)
-endef
-
-define Image/Build/LZMAKernel
- $(LOADER_MAKE) TARGET_DIR=$(BIN_DIR) \
- LOADER=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-ramfs.$(2) \
- LOADER_DATA=$(KDIR)/vmlinux.lzma \
- LZMA_TEXT_START=$(3) LZMA_STARTUP_ORG=$(4) \
- CONFIG_PASS_KARGS=$(5) CONFIG_BOARD=$(6) \
- compile loader.$(2)
-endef
-
-define Image/Build/LZMAKernel/Generic
- $(call Image/Build/LZMAKernel,$(1),$(2),0x80500000,0)
-endef
-
-define Image/Build/LZMAKernel/Admboot
- $(call Image/Build/LZMAKernel,$(1),$(2),0x80500000,0x6D8,y,$(1))
-endef
-
-define Image/Build/LZMAKernel/Cellvision
- $(call Image/Build/LZMAKernel,$(1),$(3),0x80500000,0x6D8,y,$(2))
-endef
-
-define Image/Build/LZMAKernel/KArgs
- $(call Image/Build/LZMAKernel,$(1),$(2),0x80500000,0,y,$(1))
-endef
-
-define trxalign/jffs2-128k
--a 0x20000 -f $(KDIR)/root.jffs2-128k
-endef
-
-define trxalign/jffs2-64k
--a 0x10000 -f $(KDIR)/root.jffs2-64k
-endef
-
-define trxalign/squashfs
--a 1024 -f $(KDIR)/root.squashfs -a 0x10000 -A $(JFFS2BLOCK)
-endef
-
-define Image/Build/TRX
- $(STAGING_DIR_HOST)/bin/trx -o $(1) -f $(3) -f $(KDIR)/vmlinux.lzma \
- $(call trxalign/$(2))
-endef
-
-define Image/Build/TRXNoloader
- $(STAGING_DIR_HOST)/bin/trx -o $(1) -f $(KDIR)/vmlinux.lzma \
- $(call trxalign/$(2))
-endef
-
-include $(SUBTARGET).mk
-
-define Image/Build
- $(call Image/Build/Profile/$(PROFILE),$(1))
-endef
-
-define Image/Build/Initramfs
- $(call Image/Build/Profile/$(PROFILE),Initramfs)
-endef
-
-define Image/BuildKernel
- cp $(KDIR)/vmlinux.elf $(VMLINUX).elf
- cp $(KDIR)/vmlinux $(VMLINUX).bin
-ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
- cp $(KDIR)/vmlinux-initramfs.elf $(VMLINUX)-initramfs.elf
- cp $(KDIR)/vmlinux $(VMLINUX)-initramfs.bin
-endif
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-#
-# Copyright (C) 2006 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-
-LOADER := loader.bin
-LOADER_NAME := $(basename $(notdir $(LOADER)))
-LOADER_DATA :=
-TARGET_DIR :=
-
-ifeq ($(TARGET_DIR),)
-TARGET_DIR := $(KDIR)
-endif
-
-LOADER_BIN := $(TARGET_DIR)/$(LOADER_NAME).bin
-LOADER_GZ := $(TARGET_DIR)/$(LOADER_NAME).gz
-LOADER_ELF := $(TARGET_DIR)/$(LOADER_NAME).elf
-
-LZMA_STARTUP_ORG:= 0
-LZMA_TEXT_START := 0x80300000
-
-PKG_NAME := lzma-loader
-PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)
-
-.PHONY : loader-compile loader.bin loader.elf loader.gz
-
-$(PKG_BUILD_DIR)/.prepared:
- mkdir $(PKG_BUILD_DIR)
- $(CP) ./src/* $(PKG_BUILD_DIR)/
- touch $@
-
-loader-compile: $(PKG_BUILD_DIR)/.prepared
- $(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE="$(TARGET_CROSS)" \
- LZMA_STARTUP_ORG=$(LZMA_STARTUP_ORG) \
- LZMA_TEXT_START=$(LZMA_TEXT_START) \
- LOADER_DATA=$(LOADER_DATA) \
- CONFIG_BOARD=$(CONFIG_BOARD) \
- CONFIG_PASS_KARGS=$(CONFIG_PASS_KARGS) \
- clean all
-
-loader.gz: $(PKG_BUILD_DIR)/loader.bin
- gzip -nc9 $< > $(LOADER_GZ)
-
-loader.elf: $(PKG_BUILD_DIR)/loader.elf
- $(CP) $< $(LOADER_ELF)
-
-loader.bin: $(PKG_BUILD_DIR)/loader.bin
- $(CP) $< $(LOADER_BIN)
-
-download:
-prepare: $(PKG_BUILD_DIR)/.prepared
-compile: loader-compile
-
-install:
-
-clean:
- rm -rf $(PKG_BUILD_DIR)
-
+++ /dev/null
-/*
- LzmaDecode.c
- LZMA Decoder (optimized for Speed version)
-
- LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
- http://www.7-zip.org/
-
- LZMA SDK is licensed under two licenses:
- 1) GNU Lesser General Public License (GNU LGPL)
- 2) Common Public License (CPL)
- It means that you can select one of these two licenses and
- follow rules of that license.
-
- SPECIAL EXCEPTION:
- Igor Pavlov, as the author of this Code, expressly permits you to
- statically or dynamically link your Code (or bind by name) to the
- interfaces of this file without subjecting your linked Code to the
- terms of the CPL or GNU LGPL. Any modifications or additions
- to this file, however, are subject to the LGPL or CPL terms.
-*/
-
-#include "LzmaDecode.h"
-
-#define kNumTopBits 24
-#define kTopValue ((UInt32)1 << kNumTopBits)
-
-#define kNumBitModelTotalBits 11
-#define kBitModelTotal (1 << kNumBitModelTotalBits)
-#define kNumMoveBits 5
-
-#define RC_READ_BYTE (*Buffer++)
-
-#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \
- { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}
-
-#ifdef _LZMA_IN_CB
-
-#define RC_TEST { if (Buffer == BufferLim) \
- { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \
- BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}
-
-#define RC_INIT Buffer = BufferLim = 0; RC_INIT2
-
-#else
-
-#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }
-
-#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2
-
-#endif
-
-#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }
-
-#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)
-#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;
-#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;
-
-#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \
- { UpdateBit0(p); mi <<= 1; A0; } else \
- { UpdateBit1(p); mi = (mi + mi) + 1; A1; }
-
-#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)
-
-#define RangeDecoderBitTreeDecode(probs, numLevels, res) \
- { int i = numLevels; res = 1; \
- do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \
- res -= (1 << numLevels); }
-
-
-#define kNumPosBitsMax 4
-#define kNumPosStatesMax (1 << kNumPosBitsMax)
-
-#define kLenNumLowBits 3
-#define kLenNumLowSymbols (1 << kLenNumLowBits)
-#define kLenNumMidBits 3
-#define kLenNumMidSymbols (1 << kLenNumMidBits)
-#define kLenNumHighBits 8
-#define kLenNumHighSymbols (1 << kLenNumHighBits)
-
-#define LenChoice 0
-#define LenChoice2 (LenChoice + 1)
-#define LenLow (LenChoice2 + 1)
-#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
-#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
-#define kNumLenProbs (LenHigh + kLenNumHighSymbols)
-
-
-#define kNumStates 12
-#define kNumLitStates 7
-
-#define kStartPosModelIndex 4
-#define kEndPosModelIndex 14
-#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
-
-#define kNumPosSlotBits 6
-#define kNumLenToPosStates 4
-
-#define kNumAlignBits 4
-#define kAlignTableSize (1 << kNumAlignBits)
-
-#define kMatchMinLen 2
-
-#define IsMatch 0
-#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
-#define IsRepG0 (IsRep + kNumStates)
-#define IsRepG1 (IsRepG0 + kNumStates)
-#define IsRepG2 (IsRepG1 + kNumStates)
-#define IsRep0Long (IsRepG2 + kNumStates)
-#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
-#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
-#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
-#define LenCoder (Align + kAlignTableSize)
-#define RepLenCoder (LenCoder + kNumLenProbs)
-#define Literal (RepLenCoder + kNumLenProbs)
-
-#if Literal != LZMA_BASE_SIZE
-StopCompilingDueBUG
-#endif
-
-int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)
-{
- unsigned char prop0;
- if (size < LZMA_PROPERTIES_SIZE)
- return LZMA_RESULT_DATA_ERROR;
- prop0 = propsData[0];
- if (prop0 >= (9 * 5 * 5))
- return LZMA_RESULT_DATA_ERROR;
- {
- for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));
- for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);
- propsRes->lc = prop0;
- /*
- unsigned char remainder = (unsigned char)(prop0 / 9);
- propsRes->lc = prop0 % 9;
- propsRes->pb = remainder / 5;
- propsRes->lp = remainder % 5;
- */
- }
-
- #ifdef _LZMA_OUT_READ
- {
- int i;
- propsRes->DictionarySize = 0;
- for (i = 0; i < 4; i++)
- propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);
- if (propsRes->DictionarySize == 0)
- propsRes->DictionarySize = 1;
- }
- #endif
- return LZMA_RESULT_OK;
-}
-
-#define kLzmaStreamWasFinishedId (-1)
-
-int LzmaDecode(CLzmaDecoderState *vs,
- #ifdef _LZMA_IN_CB
- ILzmaInCallback *InCallback,
- #else
- const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
- #endif
- unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)
-{
- CProb *p = vs->Probs;
- SizeT nowPos = 0;
- Byte previousByte = 0;
- UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;
- UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;
- int lc = vs->Properties.lc;
-
- #ifdef _LZMA_OUT_READ
-
- UInt32 Range = vs->Range;
- UInt32 Code = vs->Code;
- #ifdef _LZMA_IN_CB
- const Byte *Buffer = vs->Buffer;
- const Byte *BufferLim = vs->BufferLim;
- #else
- const Byte *Buffer = inStream;
- const Byte *BufferLim = inStream + inSize;
- #endif
- int state = vs->State;
- UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];
- int len = vs->RemainLen;
- UInt32 globalPos = vs->GlobalPos;
- UInt32 distanceLimit = vs->DistanceLimit;
-
- Byte *dictionary = vs->Dictionary;
- UInt32 dictionarySize = vs->Properties.DictionarySize;
- UInt32 dictionaryPos = vs->DictionaryPos;
-
- Byte tempDictionary[4];
-
- #ifndef _LZMA_IN_CB
- *inSizeProcessed = 0;
- #endif
- *outSizeProcessed = 0;
- if (len == kLzmaStreamWasFinishedId)
- return LZMA_RESULT_OK;
-
- if (dictionarySize == 0)
- {
- dictionary = tempDictionary;
- dictionarySize = 1;
- tempDictionary[0] = vs->TempDictionary[0];
- }
-
- if (len == kLzmaNeedInitId)
- {
- {
- UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
- UInt32 i;
- for (i = 0; i < numProbs; i++)
- p[i] = kBitModelTotal >> 1;
- rep0 = rep1 = rep2 = rep3 = 1;
- state = 0;
- globalPos = 0;
- distanceLimit = 0;
- dictionaryPos = 0;
- dictionary[dictionarySize - 1] = 0;
- #ifdef _LZMA_IN_CB
- RC_INIT;
- #else
- RC_INIT(inStream, inSize);
- #endif
- }
- len = 0;
- }
- while(len != 0 && nowPos < outSize)
- {
- UInt32 pos = dictionaryPos - rep0;
- if (pos >= dictionarySize)
- pos += dictionarySize;
- outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];
- if (++dictionaryPos == dictionarySize)
- dictionaryPos = 0;
- len--;
- }
- if (dictionaryPos == 0)
- previousByte = dictionary[dictionarySize - 1];
- else
- previousByte = dictionary[dictionaryPos - 1];
-
- #else /* if !_LZMA_OUT_READ */
-
- int state = 0;
- UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
- int len = 0;
- const Byte *Buffer;
- const Byte *BufferLim;
- UInt32 Range;
- UInt32 Code;
-
- #ifndef _LZMA_IN_CB
- *inSizeProcessed = 0;
- #endif
- *outSizeProcessed = 0;
-
- {
- UInt32 i;
- UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
- for (i = 0; i < numProbs; i++)
- p[i] = kBitModelTotal >> 1;
- }
-
- #ifdef _LZMA_IN_CB
- RC_INIT;
- #else
- RC_INIT(inStream, inSize);
- #endif
-
- #endif /* _LZMA_OUT_READ */
-
- while(nowPos < outSize)
- {
- CProb *prob;
- UInt32 bound;
- int posState = (int)(
- (nowPos
- #ifdef _LZMA_OUT_READ
- + globalPos
- #endif
- )
- & posStateMask);
-
- prob = p + IsMatch + (state << kNumPosBitsMax) + posState;
- IfBit0(prob)
- {
- int symbol = 1;
- UpdateBit0(prob)
- prob = p + Literal + (LZMA_LIT_SIZE *
- (((
- (nowPos
- #ifdef _LZMA_OUT_READ
- + globalPos
- #endif
- )
- & literalPosMask) << lc) + (previousByte >> (8 - lc))));
-
- if (state >= kNumLitStates)
- {
- int matchByte;
- #ifdef _LZMA_OUT_READ
- UInt32 pos = dictionaryPos - rep0;
- if (pos >= dictionarySize)
- pos += dictionarySize;
- matchByte = dictionary[pos];
- #else
- matchByte = outStream[nowPos - rep0];
- #endif
- do
- {
- int bit;
- CProb *probLit;
- matchByte <<= 1;
- bit = (matchByte & 0x100);
- probLit = prob + 0x100 + bit + symbol;
- RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)
- }
- while (symbol < 0x100);
- }
- while (symbol < 0x100)
- {
- CProb *probLit = prob + symbol;
- RC_GET_BIT(probLit, symbol)
- }
- previousByte = (Byte)symbol;
-
- outStream[nowPos++] = previousByte;
- #ifdef _LZMA_OUT_READ
- if (distanceLimit < dictionarySize)
- distanceLimit++;
-
- dictionary[dictionaryPos] = previousByte;
- if (++dictionaryPos == dictionarySize)
- dictionaryPos = 0;
- #endif
- if (state < 4) state = 0;
- else if (state < 10) state -= 3;
- else state -= 6;
- }
- else
- {
- UpdateBit1(prob);
- prob = p + IsRep + state;
- IfBit0(prob)
- {
- UpdateBit0(prob);
- rep3 = rep2;
- rep2 = rep1;
- rep1 = rep0;
- state = state < kNumLitStates ? 0 : 3;
- prob = p + LenCoder;
- }
- else
- {
- UpdateBit1(prob);
- prob = p + IsRepG0 + state;
- IfBit0(prob)
- {
- UpdateBit0(prob);
- prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;
- IfBit0(prob)
- {
- #ifdef _LZMA_OUT_READ
- UInt32 pos;
- #endif
- UpdateBit0(prob);
-
- #ifdef _LZMA_OUT_READ
- if (distanceLimit == 0)
- #else
- if (nowPos == 0)
- #endif
- return LZMA_RESULT_DATA_ERROR;
-
- state = state < kNumLitStates ? 9 : 11;
- #ifdef _LZMA_OUT_READ
- pos = dictionaryPos - rep0;
- if (pos >= dictionarySize)
- pos += dictionarySize;
- previousByte = dictionary[pos];
- dictionary[dictionaryPos] = previousByte;
- if (++dictionaryPos == dictionarySize)
- dictionaryPos = 0;
- #else
- previousByte = outStream[nowPos - rep0];
- #endif
- outStream[nowPos++] = previousByte;
- #ifdef _LZMA_OUT_READ
- if (distanceLimit < dictionarySize)
- distanceLimit++;
- #endif
-
- continue;
- }
- else
- {
- UpdateBit1(prob);
- }
- }
- else
- {
- UInt32 distance;
- UpdateBit1(prob);
- prob = p + IsRepG1 + state;
- IfBit0(prob)
- {
- UpdateBit0(prob);
- distance = rep1;
- }
- else
- {
- UpdateBit1(prob);
- prob = p + IsRepG2 + state;
- IfBit0(prob)
- {
- UpdateBit0(prob);
- distance = rep2;
- }
- else
- {
- UpdateBit1(prob);
- distance = rep3;
- rep3 = rep2;
- }
- rep2 = rep1;
- }
- rep1 = rep0;
- rep0 = distance;
- }
- state = state < kNumLitStates ? 8 : 11;
- prob = p + RepLenCoder;
- }
- {
- int numBits, offset;
- CProb *probLen = prob + LenChoice;
- IfBit0(probLen)
- {
- UpdateBit0(probLen);
- probLen = prob + LenLow + (posState << kLenNumLowBits);
- offset = 0;
- numBits = kLenNumLowBits;
- }
- else
- {
- UpdateBit1(probLen);
- probLen = prob + LenChoice2;
- IfBit0(probLen)
- {
- UpdateBit0(probLen);
- probLen = prob + LenMid + (posState << kLenNumMidBits);
- offset = kLenNumLowSymbols;
- numBits = kLenNumMidBits;
- }
- else
- {
- UpdateBit1(probLen);
- probLen = prob + LenHigh;
- offset = kLenNumLowSymbols + kLenNumMidSymbols;
- numBits = kLenNumHighBits;
- }
- }
- RangeDecoderBitTreeDecode(probLen, numBits, len);
- len += offset;
- }
-
- if (state < 4)
- {
- int posSlot;
- state += kNumLitStates;
- prob = p + PosSlot +
- ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<
- kNumPosSlotBits);
- RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);
- if (posSlot >= kStartPosModelIndex)
- {
- int numDirectBits = ((posSlot >> 1) - 1);
- rep0 = (2 | ((UInt32)posSlot & 1));
- if (posSlot < kEndPosModelIndex)
- {
- rep0 <<= numDirectBits;
- prob = p + SpecPos + rep0 - posSlot - 1;
- }
- else
- {
- numDirectBits -= kNumAlignBits;
- do
- {
- RC_NORMALIZE
- Range >>= 1;
- rep0 <<= 1;
- if (Code >= Range)
- {
- Code -= Range;
- rep0 |= 1;
- }
- }
- while (--numDirectBits != 0);
- prob = p + Align;
- rep0 <<= kNumAlignBits;
- numDirectBits = kNumAlignBits;
- }
- {
- int i = 1;
- int mi = 1;
- do
- {
- CProb *prob3 = prob + mi;
- RC_GET_BIT2(prob3, mi, ; , rep0 |= i);
- i <<= 1;
- }
- while(--numDirectBits != 0);
- }
- }
- else
- rep0 = posSlot;
- if (++rep0 == (UInt32)(0))
- {
- /* it's for stream version */
- len = kLzmaStreamWasFinishedId;
- break;
- }
- }
-
- len += kMatchMinLen;
- #ifdef _LZMA_OUT_READ
- if (rep0 > distanceLimit)
- #else
- if (rep0 > nowPos)
- #endif
- return LZMA_RESULT_DATA_ERROR;
-
- #ifdef _LZMA_OUT_READ
- if (dictionarySize - distanceLimit > (UInt32)len)
- distanceLimit += len;
- else
- distanceLimit = dictionarySize;
- #endif
-
- do
- {
- #ifdef _LZMA_OUT_READ
- UInt32 pos = dictionaryPos - rep0;
- if (pos >= dictionarySize)
- pos += dictionarySize;
- previousByte = dictionary[pos];
- dictionary[dictionaryPos] = previousByte;
- if (++dictionaryPos == dictionarySize)
- dictionaryPos = 0;
- #else
- previousByte = outStream[nowPos - rep0];
- #endif
- len--;
- outStream[nowPos++] = previousByte;
- }
- while(len != 0 && nowPos < outSize);
- }
- }
- RC_NORMALIZE;
-
- #ifdef _LZMA_OUT_READ
- vs->Range = Range;
- vs->Code = Code;
- vs->DictionaryPos = dictionaryPos;
- vs->GlobalPos = globalPos + (UInt32)nowPos;
- vs->DistanceLimit = distanceLimit;
- vs->Reps[0] = rep0;
- vs->Reps[1] = rep1;
- vs->Reps[2] = rep2;
- vs->Reps[3] = rep3;
- vs->State = state;
- vs->RemainLen = len;
- vs->TempDictionary[0] = tempDictionary[0];
- #endif
-
- #ifdef _LZMA_IN_CB
- vs->Buffer = Buffer;
- vs->BufferLim = BufferLim;
- #else
- *inSizeProcessed = (SizeT)(Buffer - inStream);
- #endif
- *outSizeProcessed = nowPos;
- return LZMA_RESULT_OK;
-}
+++ /dev/null
-/*
- LzmaDecode.h
- LZMA Decoder interface
-
- LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
- http://www.7-zip.org/
-
- LZMA SDK is licensed under two licenses:
- 1) GNU Lesser General Public License (GNU LGPL)
- 2) Common Public License (CPL)
- It means that you can select one of these two licenses and
- follow rules of that license.
-
- SPECIAL EXCEPTION:
- Igor Pavlov, as the author of this code, expressly permits you to
- statically or dynamically link your code (or bind by name) to the
- interfaces of this file without subjecting your linked code to the
- terms of the CPL or GNU LGPL. Any modifications or additions
- to this file, however, are subject to the LGPL or CPL terms.
-*/
-
-#ifndef __LZMADECODE_H
-#define __LZMADECODE_H
-
-#include "LzmaTypes.h"
-
-/* #define _LZMA_IN_CB */
-/* Use callback for input data */
-
-/* #define _LZMA_OUT_READ */
-/* Use read function for output data */
-
-/* #define _LZMA_PROB32 */
-/* It can increase speed on some 32-bit CPUs,
- but memory usage will be doubled in that case */
-
-/* #define _LZMA_LOC_OPT */
-/* Enable local speed optimizations inside code */
-
-#ifdef _LZMA_PROB32
-#define CProb UInt32
-#else
-#define CProb UInt16
-#endif
-
-#define LZMA_RESULT_OK 0
-#define LZMA_RESULT_DATA_ERROR 1
-
-#ifdef _LZMA_IN_CB
-typedef struct _ILzmaInCallback
-{
- int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);
-} ILzmaInCallback;
-#endif
-
-#define LZMA_BASE_SIZE 1846
-#define LZMA_LIT_SIZE 768
-
-#define LZMA_PROPERTIES_SIZE 5
-
-typedef struct _CLzmaProperties
-{
- int lc;
- int lp;
- int pb;
- #ifdef _LZMA_OUT_READ
- UInt32 DictionarySize;
- #endif
-}CLzmaProperties;
-
-int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);
-
-#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))
-
-#define kLzmaNeedInitId (-2)
-
-typedef struct _CLzmaDecoderState
-{
- CLzmaProperties Properties;
- CProb *Probs;
-
- #ifdef _LZMA_IN_CB
- const unsigned char *Buffer;
- const unsigned char *BufferLim;
- #endif
-
- #ifdef _LZMA_OUT_READ
- unsigned char *Dictionary;
- UInt32 Range;
- UInt32 Code;
- UInt32 DictionaryPos;
- UInt32 GlobalPos;
- UInt32 DistanceLimit;
- UInt32 Reps[4];
- int State;
- int RemainLen;
- unsigned char TempDictionary[4];
- #endif
-} CLzmaDecoderState;
-
-#ifdef _LZMA_OUT_READ
-#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }
-#endif
-
-int LzmaDecode(CLzmaDecoderState *vs,
- #ifdef _LZMA_IN_CB
- ILzmaInCallback *inCallback,
- #else
- const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
- #endif
- unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);
-
-#endif
+++ /dev/null
-/*
-LzmaTypes.h
-
-Types for LZMA Decoder
-
-This file written and distributed to public domain by Igor Pavlov.
-This file is part of LZMA SDK 4.40 (2006-05-01)
-*/
-
-#ifndef __LZMATYPES_H
-#define __LZMATYPES_H
-
-#ifndef _7ZIP_BYTE_DEFINED
-#define _7ZIP_BYTE_DEFINED
-typedef unsigned char Byte;
-#endif
-
-#ifndef _7ZIP_UINT16_DEFINED
-#define _7ZIP_UINT16_DEFINED
-typedef unsigned short UInt16;
-#endif
-
-#ifndef _7ZIP_UINT32_DEFINED
-#define _7ZIP_UINT32_DEFINED
-#ifdef _LZMA_UINT32_IS_ULONG
-typedef unsigned long UInt32;
-#else
-typedef unsigned int UInt32;
-#endif
-#endif
-
-/* #define _LZMA_NO_SYSTEM_SIZE_T */
-/* You can use it, if you don't want <stddef.h> */
-
-#ifndef _7ZIP_SIZET_DEFINED
-#define _7ZIP_SIZET_DEFINED
-#ifdef _LZMA_NO_SYSTEM_SIZE_T
-typedef UInt32 SizeT;
-#else
-#include <stddef.h>
-typedef size_t SizeT;
-#endif
-#endif
-
-#endif
+++ /dev/null
-#
-# Makefile for Broadcom BCM947XX boards
-#
-# Copyright 2001-2003, Broadcom Corporation
-# All Rights Reserved.
-#
-# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-#
-# Copyright 2004 Manuel Novoa III <mjn3@codepoet.org>
-# Modified to support bzip'd kernels.
-# Of course, it would be better to integrate bunzip capability into CFE.
-#
-# Copyright 2005 Oleg I. Vdovikin <oleg@cs.msu.su>
-# Cleaned up, modified for lzma support, removed from kernel
-#
-# Copyright 2007 Gabor Juhos <juhosg at openwrt.org>
-# Modified to support user defined entry point address.
-# Added support for make targets with different names
-#
-
-LOADADDR := 0x80001000
-LZMA_TEXT_START := 0x80500000
-LZMA_STARTUP_ORG:= 0
-LOADER_DATA :=
-CONFIG_PASS_KARGS :=
-CONFIG_BOARD :=
-
-CC := $(CROSS_COMPILE)gcc
-LD := $(CROSS_COMPILE)ld
-OBJCOPY := $(CROSS_COMPILE)objcopy
-OBJDUMP := $(CROSS_COMPILE)objdump
-
-BIN_FLAGS := -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
-
-CFLAGS = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
- -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 -mno-abicalls -fno-pic \
- -ffunction-sections -pipe -mlong-calls -fno-common -ffreestanding \
- -fhonour-copts \
- -mabi=32 -march=mips32 -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap
-CFLAGS += -DLOADADDR=$(LOADADDR) -D_LZMA_PROB32
-
-ASFLAGS = $(CFLAGS) -D__ASSEMBLY__ -DLZMA_STARTUP_ORG=$(LZMA_STARTUP_ORG)
-
-LDFLAGS = -static --gc-sections -no-warn-mismatch
-LDFLAGS += -e startup -T loader.lds -Ttext $(LZMA_TEXT_START)
-
-O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
-
-OBJECTS := head.o decompress.o board.o printf.o LzmaDecode.o
-
-ifneq ($(strip $(LOADER_DATA)),)
-OBJECTS += data.o
-CFLAGS += -DLZMA_WRAPPER=1
-else
-CFLAGS += -D_LZMA_IN_CB
-endif
-
-ifneq ($(strip $(CONFIG_PASS_KARGS)),)
-CFLAGS += -DCONFIG_PASS_KARGS
-endif
-
-BOARD_DEF := $(strip $(CONFIG_BOARD))
-BOARD_DEF := $(shell echo $(BOARD_DEF) | tr a-z A-Z | tr -d -)
-ifneq ($(BOARD_DEF),)
-CFLAGS += -DCONFIG_BOARD_$(BOARD_DEF)
-endif
-
-all: loader.bin
-
-# Don't build dependencies, this may die if $(CC) isn't gcc
-dep:
-
-install:
-
-%.o : %.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-%.o : %.S
- $(CC) $(ASFLAGS) -c -o $@ $<
-
-data.o: $(LOADER_DATA)
- $(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $<
-
-loader.bin: loader.elf
- $(OBJCOPY) $(BIN_FLAGS) $< $@
-
-loader.elf: $(OBJECTS)
- $(LD) $(LDFLAGS) -o $@ $(OBJECTS)
-
-mrproper: clean
-
-clean:
- rm -f *.elf *.bin *.o
-
-
-
+++ /dev/null
-/*
- * LZMA compressed kernel decompressor for bcm947xx boards
- *
- * Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-The code is intended to decompress kernel, being compressed using lzma utility
-build using 7zip LZMA SDK. This utility is located in the LZMA_Alone directory
-
-decompressor code expects that your .trx file consist of three partitions:
-
-1) decompressor itself (this is gziped code which pmon/cfe will extract and run
-on boot-up instead of real kernel)
-2) LZMA compressed kernel (both streamed and regular modes are supported now)
-3) Root filesystem
-
-Please be sure to apply the following patch for use this new trx layout (it will
-allow using both new and old trx files for root filesystem lookup code)
-
---- linuz/arch/mips/brcm-boards/bcm947xx/setup.c 2005-01-23 19:24:27.503322896 +0300
-+++ linux/arch/mips/brcm-boards/bcm947xx/setup.c 2005-01-23 19:29:05.237100944 +0300
-@@ -221,7 +221,9 @@
- /* Try looking at TRX header for rootfs offset */
- if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
- bcm947xx_parts[1].offset = off;
-- if (le32_to_cpu(trx->offsets[1]) > off)
-+ if (le32_to_cpu(trx->offsets[2]) > off)
-+ off = le32_to_cpu(trx->offsets[2]);
-+ else if (le32_to_cpu(trx->offsets[1]) > off)
- off = le32_to_cpu(trx->offsets[1]);
- continue;
- }
-
-
-Revision history:
- 0.02 Initial release
- 0.03 Added Mineharu Takahara <mtakahar@yahoo.com> patch to pass actual
- output size to decoder (stream mode compressed input is not
- a requirement anymore)
- 0.04 Reordered functions using lds script
+++ /dev/null
-/*
- * ADM5120 specific board support for LZMA decompressor
- *
- * Copyright (C) 2007-2008 OpenWrt.org
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include "config.h"
-#include <stddef.h>
-
-#define READREG(r) *(volatile unsigned int *)(r)
-#define WRITEREG(r,v) *(volatile unsigned int *)(r) = v
-
-/*
- * INTC definitions
- */
-#define INTC_BASE 0xB2200000
-
-/* INTC registers */
-#define INTC_REG_IRQ_DISABLE 0x0C
-
-/*
- * UART definitions
- */
-#define UART0_BASE 0xB2600000
-#define UART1_BASE 0xB2800000
-/* UART registers */
-#define UART_REG_DATA 0x00 /* Data register */
-#define UART_REG_ECR 0x04 /* Error Clear register */
-#define UART_REG_LCRH 0x08 /* Line Control High register */
-#define UART_REG_LCRM 0x0C /* Line Control Middle register */
-#define UART_REG_LCRL 0x10 /* Line Control Low register */
-#define UART_REG_CTRL 0x14 /* Control register */
-#define UART_REG_FLAG 0x18 /* Flag register */
-
-/* Control register bits */
-#define UART_CTRL_EN ( 1 << 0 ) /* UART enable */
-
-/* Line Control High register bits */
-#define UART_LCRH_FEN ( 1 << 4 ) /* FIFO enable */
-
-/* Flag register bits */
-#define UART_FLAG_CTS ( 1 << 0 )
-#define UART_FLAG_DSR ( 1 << 1 )
-#define UART_FLAG_DCD ( 1 << 2 )
-#define UART_FLAG_BUSY ( 1 << 3 )
-#define UART_FLAG_RXFE ( 1 << 4 ) /* RX FIFO empty */
-#define UART_FLAG_TXFF ( 1 << 5 ) /* TX FIFO full */
-#define UART_FLAG_RXFF ( 1 << 6 ) /* RX FIFO full */
-#define UART_FLAG_TXFE ( 1 << 7 ) /* TX FIFO empty */
-
-/*
- * SWITCH definitions
- */
-#define SWITCH_BASE 0xB2000000
-
-#define SWITCH_REG_CPUP_CONF 0x0024
-#define SWITCH_REG_PORT_CONF0 0x0028
-
-#define SWITCH_REG_GPIO_CONF0 0x00B8
-#define SWITCH_REG_GPIO_CONF2 0x00BC
-
-#define SWITCH_REG_PORT0_LED 0x0100
-#define SWITCH_REG_PORT1_LED 0x0104
-#define SWITCH_REG_PORT2_LED 0x0108
-#define SWITCH_REG_PORT3_LED 0x010C
-#define SWITCH_REG_PORT4_LED 0x0110
-
-#define SWITCH_PORTS_HW 0x3F /* Hardware Ports */
-
-/* CPUP_CONF register bits */
-#define CPUP_CONF_DCPUP ( 1 << 0 ) /* Disable CPU port */
-
-/* PORT_CONF0 register bits */
-#define PORT_CONF0_DP_SHIFT 0 /* disable port shift*/
-
-
-/*
- * UART routines
- */
-
-#if defined(CONFIG_USE_UART0)
-# define UART_READ(r) READREG(UART0_BASE+(r))
-# define UART_WRITE(r,v) WRITEREG(UART0_BASE+(r),(v))
-#else
-# define UART_READ(r) READREG(UART1_BASE+(r))
-# define UART_WRITE(r,v) WRITEREG(UART1_BASE+(r),(v))
-#endif
-
-static void uart_init(void)
-{
-#if 0
- unsigned int t;
-
- /* disable uart */
- UART_WRITE(UART_REG_CTRL, 0);
-
- /* keep current baud rate */
- t = UART_READ(UART_REG_LCRM);
- UART_WRITE(UART_REG_LCRM, t);
- t = UART_READ(UART_REG_LCRL);
- UART_WRITE(UART_REG_LCRL, t);
-
- /* keep data, stop, and parity bits, but disable FIFO */
- t = UART_READ(UART_REG_LCRH);
- t &= ~(UART_LCRH_FEN);
- UART_WRITE(UART_REG_LCRH, t );
-
- /* clear error bits */
- UART_WRITE(UART_REG_ECR, 0xFF);
-
- /* enable uart, and disable interrupts */
- UART_WRITE(UART_REG_CTRL, UART_CTRL_EN);
-#endif
-}
-
-/*
- * INTC routines
- */
-
-#define INTC_READ(r) READREG(INTC_BASE+(r))
-#define INTC_WRITE(r,v) WRITEREG(INTC_BASE+(r),v)
-
-static void intc_init(void)
-{
- INTC_WRITE(INTC_REG_IRQ_DISABLE, 0xFFFFFFFF);
-}
-
-/*
- * SWITCH routines
- */
-
-#define SWITCH_READ(r) READREG(SWITCH_BASE+(r))
-#define SWITCH_WRITE(r,v) WRITEREG(SWITCH_BASE+(r),v)
-
-static void switch_init(void)
-{
- /* disable PHYS ports */
- SWITCH_WRITE(SWITCH_REG_PORT_CONF0,
- (SWITCH_PORTS_HW << PORT_CONF0_DP_SHIFT));
-
- /* disable CPU port */
- SWITCH_WRITE(SWITCH_REG_CPUP_CONF, CPUP_CONF_DCPUP);
-
- /* disable GPIO lines */
- SWITCH_WRITE(SWITCH_REG_GPIO_CONF0, 0);
- SWITCH_WRITE(SWITCH_REG_GPIO_CONF2, 0);
-
- /* disable LED lines */
- SWITCH_WRITE(SWITCH_REG_PORT0_LED, 0);
- SWITCH_WRITE(SWITCH_REG_PORT1_LED, 0);
- SWITCH_WRITE(SWITCH_REG_PORT2_LED, 0);
- SWITCH_WRITE(SWITCH_REG_PORT3_LED, 0);
- SWITCH_WRITE(SWITCH_REG_PORT4_LED, 0);
-}
-
-void board_putc(int ch)
-{
- while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0);
-
- UART_WRITE(UART_REG_DATA, ch);
-
- while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0);
-}
-
-void board_init(void)
-{
- intc_init();
- switch_init();
- uart_init();
-}
+++ /dev/null
-#ifndef _CONFIG_H_
-#define _CONFIG_H_
-
-#define FLASH_2M (2<<20)
-#define FLASH_4M (4<<20)
-
-/*
- * Cellvision/SparkLAN boards
- */
-
-#if defined(CONFIG_BOARD_CAS630)
-# define CONFIG_BOARD_NAME "CAS-630"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-#if defined(CONFIG_BOARD_CAS670)
-# define CONFIG_BOARD_NAME "CAS-670"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-#if defined(CONFIG_BOARD_CAS700)
-# define CONFIG_BOARD_NAME "CAS-700"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-#if defined(CONFIG_BOARD_CAS790)
-# define CONFIG_BOARD_NAME "CAS-790"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-#if defined(CONFIG_BOARD_CAS771)
-# define CONFIG_BOARD_NAME "CAS-771"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-#if defined(CONFIG_BOARD_CAS861)
-# define CONFIG_BOARD_NAME "CAS-861"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-#if defined(CONFIG_BOARD_NFS101U)
-# define CONFIG_BOARD_NAME "NFS-101U"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-#if defined(CONFIG_BOARD_NFS202U)
-# define CONFIG_BOARD_NAME "NFS-202U"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-/*
- * Compex boards
- */
-#if defined(CONFIG_BOARD_WP54GWRT)
-# define CONFIG_BOARD_NAME "WP54G-WRT"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-/*
- * Edimax boards
- */
-#if defined(CONFIG_BOARD_BR6104K)
-# define CONFIG_BOARD_NAME "BR-6104K"
-# define CONFIG_FLASH_SIZE FLASH_2M
-#endif
-
-#if defined(CONFIG_BOARD_BR6104KP)
-# define CONFIG_BOARD_NAME "BR-6104KP"
-# define CONFIG_FLASH_SIZE FLASH_2M
-#endif
-
-#if defined(CONFIG_BOARD_BR6104WG)
-# define CONFIG_BOARD_NAME "BR-6104WG"
-# define CONFIG_FLASH_SIZE FLASH_2M
-#endif
-
-/*
- * Infineon boards
- */
-#if defined(CONFIG_BOARD_EASY5120PATA)
-# define CONFIG_BOARD_NAME "EASY 5120P-ATA"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-#if defined(CONFIG_BOARD_EASY5120RT)
-# define CONFIG_BOARD_NAME "EASY 5120-RT"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-#if defined(CONFIG_BOARD_EASY5120WVOIP)
-# define CONFIG_BOARD_NAME "EASY 5120-WVOIP"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-#if defined(CONFIG_BOARD_EASY83000)
-# define CONFIG_BOARD_NAME "EASY 83000"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-/*
- * Motorola boards
- */
-#if defined(CONFIG_BOARD_POWERLINEMUGW)
-# define CONFIG_BOARD_NAME "Powerline MU Gateway"
-# define CONFIG_USE_UART1 1
-#endif
-
-/*
- * OSBRiDGE boards
- */
-#if defined(CONFIG_BOARD_5GXI)
-# define CONFIG_BOARD_NAME "OSBRiDGE 5GXi"
-#endif
-
-/*
- * ZyXEL boards
- */
-#if defined(CONFIG_BOARD_P334WT)
-# define CONFIG_BOARD_NAME "P-334WT"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-#if defined(CONFIG_BOARD_P335)
-# define CONFIG_BOARD_NAME "P-335"
-# define CONFIG_FLASH_SIZE FLASH_4M
-#endif
-
-/*
- * Default values
- */
-#ifndef CONFIG_BOARD_NAME
-# define CONFIG_BOARD_NAME "ADM5120"
-#endif
-
-#ifndef CONFIG_FLASH_SIZE
-# define CONFIG_FLASH_SIZE FLASH_2M
-#endif
-
-#if !defined(CONFIG_USE_UART0) && !defined(CONFIG_USE_UART1)
-# define CONFIG_USE_UART0
-#endif
-
-#endif /* _CONFIG_H_ */
+++ /dev/null
-/*
- *
- * LZMA compressed kernel decompressor for ADM5120 boards
- *
- * Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
- * Copyright (C) 2007-2008 OpenWrt.org
- * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- *
- * Please note, this was code based on the bunzip2 decompressor code
- * by Manuel Novoa III (mjn3@codepoet.org), although the only thing left
- * is an idea and part of original vendor code
- *
- *
- * 12-Mar-2005 Mineharu Takahara <mtakahar@yahoo.com>
- * pass actual output size to decoder (stream mode
- * compressed input is not a requirement anymore)
- *
- * 24-Apr-2005 Oleg I. Vdovikin
- * reordered functions using lds script, removed forward decl
- *
- * 24-Mar-2007 Gabor Juhos
- * pass original values of the a0,a1,a2,a3 registers to the kernel
- *
- * 19-May-2007 Gabor Juhos
- * endiannes related cleanups
- * add support for decompressing an embedded kernel
- *
- */
-
-#include <stddef.h>
-
-#include "config.h"
-#include "printf.h"
-#include "LzmaDecode.h"
-
-#define ADM5120_FLASH_START 0x1fc00000 /* Flash start */
-#define ADM5120_FLASH_END 0x1fe00000 /* Flash end */
-
-#define KSEG0 0x80000000
-#define KSEG1 0xa0000000
-
-#define KSEG1ADDR(a) ((((unsigned)(a)) & 0x1fffffffU) | KSEG1)
-
-#define Index_Invalidate_I 0x00
-#define Index_Writeback_Inv_D 0x01
-
-#define cache_unroll(base,op) \
- __asm__ __volatile__( \
- ".set noreorder;\n" \
- ".set mips3;\n" \
- "cache %1, (%0);\n" \
- ".set mips0;\n" \
- ".set reorder\n" \
- : \
- : "r" (base), \
- "i" (op));
-
-#ifdef LZMA_DEBUG
-# define DBG(f, a...) printf(f, ## a)
-#else
-# define DBG(f, a...) do {} while (0)
-#endif
-
-static __inline__ void blast_icache(unsigned long size, unsigned long lsize)
-{
- unsigned long start = KSEG0;
- unsigned long end = (start + size);
-
- while(start < end) {
- cache_unroll(start,Index_Invalidate_I);
- start += lsize;
- }
-}
-
-static __inline__ void blast_dcache(unsigned long size, unsigned long lsize)
-{
- unsigned long start = KSEG0;
- unsigned long end = (start + size);
-
- while(start < end) {
- cache_unroll(start,Index_Writeback_Inv_D);
- start += lsize;
- }
-}
-
-#define TRX_MAGIC 0x30524448 /* "HDR0" */
-#define TRX_ALIGN 0x1000
-
-struct trx_header {
- unsigned int magic; /* "HDR0" */
- unsigned int len; /* Length of file including header */
- unsigned int crc32; /* 32-bit CRC from flag_version to end of file */
- unsigned int flag_version; /* 0:15 flags, 16:31 version */
- unsigned int offsets[3]; /* Offsets of partitions from start of header */
-};
-
-struct env_var {
- char *name;
- char *value;
-};
-
-/* beyound the image end, size not known in advance */
-extern unsigned char workspace[];
-extern void board_init(void);
-
-static CLzmaDecoderState lzma_state;
-
-typedef void (*kernel_entry)(unsigned long reg_a0, unsigned long reg_a1,
- unsigned long reg_a2, unsigned long reg_a3);
-
-static int decompress_data(CLzmaDecoderState *vs, unsigned char *outStream,
- UInt32 outSize);
-
-#ifdef CONFIG_PASS_KARGS
-#define ENVV(n,v) {.name = (n), .value = (v)}
-struct env_var env_vars[] = {
- ENVV("board_name", CONFIG_BOARD_NAME),
- ENVV(NULL, NULL)
-};
-#endif
-
-static void halt(void)
-{
- printf("\nSystem halted!\n");
- for(;;);
-}
-
-#if (LZMA_WRAPPER)
-extern unsigned char _lzma_data_start[];
-extern unsigned char _lzma_data_end[];
-
-unsigned char *data;
-unsigned long datalen;
-
-static __inline__ unsigned char get_byte(void)
-{
- datalen--;
- return *data++;
-}
-
-static void decompress_init(void)
-{
- data = _lzma_data_start;
- datalen = _lzma_data_end - _lzma_data_start;
-}
-
-static int decompress_data(CLzmaDecoderState *vs, unsigned char *outStream,
- SizeT outSize)
-{
- SizeT ip, op;
-
- return LzmaDecode(vs, data, datalen, &ip, outStream, outSize, &op);
-}
-#endif /* LZMA_WRAPPER */
-
-#if !(LZMA_WRAPPER)
-
-#define FLASH_BANK_SIZE (2<<20)
-
-static unsigned char *flash_base = (unsigned char *) KSEG1ADDR(ADM5120_FLASH_START);
-static unsigned long flash_ofs = 0;
-static unsigned long flash_max = 0;
-static unsigned long flash_ofs_mask = (FLASH_BANK_SIZE-1);
-
-static __inline__ unsigned char get_byte(void)
-{
- return *(flash_base+flash_ofs++);
-}
-
-static int lzma_read_byte(void *object, const unsigned char **buffer,
- SizeT *bufferSize)
-{
- unsigned long len;
-
- if (flash_ofs >= flash_max)
- return LZMA_RESULT_DATA_ERROR;
-
- len = flash_max-flash_ofs;
-
-#if (CONFIG_FLASH_SIZE > FLASH_BANK_SIZE)
- if (flash_ofs < FLASH_BANK_SIZE) {
- /* switch to bank 0 */
- DBG("lzma_read_byte: switch to bank 0\n");
-
- if (len > FLASH_BANK_SIZE-flash_ofs)
- len = FLASH_BANK_SIZE-flash_ofs;
- } else {
- /* switch to bank 1 */
- DBG("lzma_read_byte: switch to bank 1\n");
- }
-#endif
- DBG("lzma_read_byte: ofs=%08X, len=%08X\n", flash_ofs, len);
-
- *buffer = flash_base+(flash_ofs & flash_ofs_mask);
- *bufferSize = len;
- flash_ofs += len;
-
- return LZMA_RESULT_OK;
-}
-
-static ILzmaInCallback lzma_callback = {
- .Read = lzma_read_byte,
-};
-
-static __inline__ unsigned int read_le32(void *buf)
-{
- unsigned char *p = buf;
-
- return ((unsigned int)p[0] + ((unsigned int)p[1] << 8) +
- ((unsigned int)p[2] << 16) +((unsigned int)p[3] << 24));
-}
-
-static void decompress_init(void)
-{
- struct trx_header *hdr = NULL;
- unsigned long kofs,klen;
-
- printf("Looking for TRX header... ");
- /* look for trx header, 32-bit data access */
- for (flash_ofs = 0; flash_ofs < FLASH_BANK_SIZE; flash_ofs += TRX_ALIGN) {
- if (read_le32(&flash_base[flash_ofs]) == TRX_MAGIC) {
- hdr = (struct trx_header *)&flash_base[flash_ofs];
- break;
- }
- }
-
- if (hdr == NULL) {
- printf("not found!\n");
- /* no compressed kernel found, halting */
- halt();
- }
-
- /* compressed kernel is in the partition 0 or 1 */
- kofs = read_le32(&hdr->offsets[1]);
- if (kofs == 0 || kofs > 65536) {
- klen = kofs-read_le32(&hdr->offsets[0]);
- kofs = read_le32(&hdr->offsets[0]);
- } else {
- klen = read_le32(&hdr->offsets[2]);
- if (klen > kofs)
- klen -= kofs;
- else
- klen = read_le32(&hdr->len)-kofs;
- }
-
- printf("found at %08X, kernel:%08X len:%08X\n", flash_ofs,
- kofs, klen);
-
- flash_ofs += kofs;
- flash_max = flash_ofs+klen;
-}
-
-static int decompress_data(CLzmaDecoderState *vs, unsigned char *outStream,
- SizeT outSize)
-{
- SizeT op;
-
-#if 0
- vs->Buffer = data;
- vs->BufferLim = datalen;
-#endif
-
- return LzmaDecode(vs, &lzma_callback, outStream, outSize, &op);
-}
-#endif /* !(LZMA_WRAPPER) */
-
-/* should be the first function */
-void decompress_entry(unsigned long reg_a0, unsigned long reg_a1,
- unsigned long reg_a2, unsigned long reg_a3,
- unsigned long icache_size, unsigned long icache_lsize,
- unsigned long dcache_size, unsigned long dcache_lsize)
-{
- unsigned char props[LZMA_PROPERTIES_SIZE];
- unsigned int i; /* temp value */
- SizeT osize; /* uncompressed size */
- int res;
-
- board_init();
-
- printf("\n\nLZMA loader for " CONFIG_BOARD_NAME
- ", Copyright (C) 2007-2008 OpenWrt.org\n\n");
-
- decompress_init();
-
- /* lzma args */
- for (i = 0; i < LZMA_PROPERTIES_SIZE; i++)
- props[i] = get_byte();
-
- /* skip rest of the LZMA coder property */
- /* read the lower half of uncompressed size in the header */
- osize = ((SizeT)get_byte()) +
- ((SizeT)get_byte() << 8) +
- ((SizeT)get_byte() << 16) +
- ((SizeT)get_byte() << 24);
-
- /* skip rest of the header (upper half of uncompressed size) */
- for (i = 0; i < 4; i++)
- get_byte();
-
- res = LzmaDecodeProperties(&lzma_state.Properties, props,
- LZMA_PROPERTIES_SIZE);
- if (res != LZMA_RESULT_OK) {
- printf("Incorrect LZMA stream properties!\n");
- halt();
- }
-
- printf("decompressing kernel... ");
-
- lzma_state.Probs = (CProb *)workspace;
- res = decompress_data(&lzma_state, (unsigned char *)LOADADDR, osize);
-
- if (res != LZMA_RESULT_OK) {
- printf("failed, ");
- switch (res) {
- case LZMA_RESULT_DATA_ERROR:
- printf("data error!\n");
- break;
- default:
- printf("unknown error %d!\n", res);
- }
- halt();
- } else
- printf("done!\n");
-
- blast_dcache(dcache_size, dcache_lsize);
- blast_icache(icache_size, icache_lsize);
-
- printf("launching kernel...\n\n");
-
-#ifdef CONFIG_PASS_KARGS
- reg_a0 = 0;
- reg_a1 = 0;
- reg_a2 = (unsigned long)env_vars;
- reg_a3 = 0;
-#endif
- /* Jump to load address */
- ((kernel_entry) LOADADDR)(reg_a0, reg_a1, reg_a2, reg_a3);
-}
+++ /dev/null
-/* Copyright 2007 Gabor Juhos <juhosg@freemail.hu> */
-/* keep original values of the a0,a1,a2,a3 registers */
-/* modifed to support user defined entry point address */
-/* Copyright 2005 Oleg I. Vdovikin (oleg@cs.msu.su) */
-/* cache manipulation adapted from Broadcom code */
-/* idea taken from original bunzip2 decompressor code */
-/* Copyright 2004 Manuel Novoa III (mjn3@codepoet.org) */
-/* Licensed under the linux kernel's version of the GPL.*/
-
-#include <asm/asm.h>
-#include <asm/regdef.h>
-
-#define KSEG0 0x80000000
-
-#define C0_STATUS $12
-#define C0_CAUSE $13
-#define C0_CONFIG $16
-#define C0_WATCHLO $18
-#define C0_WATCHHI $19
-#define C0_TAGLO $28
-#define C0_TAGHI $29
-
-#define CONF1_DA_SHIFT 7 /* D$ associativity */
-#define CONF1_DA_MASK 0x00000380
-#define CONF1_DA_BASE 1
-#define CONF1_DL_SHIFT 10 /* D$ line size */
-#define CONF1_DL_MASK 0x00001c00
-#define CONF1_DL_BASE 2
-#define CONF1_DS_SHIFT 13 /* D$ sets/way */
-#define CONF1_DS_MASK 0x0000e000
-#define CONF1_DS_BASE 64
-#define CONF1_IA_SHIFT 16 /* I$ associativity */
-#define CONF1_IA_MASK 0x00070000
-#define CONF1_IA_BASE 1
-#define CONF1_IL_SHIFT 19 /* I$ line size */
-#define CONF1_IL_MASK 0x00380000
-#define CONF1_IL_BASE 2
-#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
-#define CONF1_IS_MASK 0x01c00000
-#define CONF1_IS_BASE 64
-
-#define Index_Invalidate_I 0x00
-#define Index_Writeback_Inv_D 0x01
-
- .text
-
-#if (LZMA_STARTUP_ORG)
- .set noreorder
-
- b startup
- nop
-
- .org LZMA_STARTUP_ORG
-#endif
-
-LEAF(startup)
- .set noreorder
- .set mips32
-
- mtc0 zero, C0_WATCHLO # clear watch registers
- mtc0 zero, C0_WATCHHI
-
- mtc0 zero, C0_CAUSE # clear before writing status register
-
- mfc0 t0, C0_STATUS # get status register
- li t1, ~(0xFF01)
- and t0, t1 # mask interrupts
- mtc0 t0, C0_STATUS # set up status register
-
- move t1, ra # save return address
- la t0, __reloc_label # get linked address of label
- bal __reloc_label # branch and link to label to
- nop # get actual address
-__reloc_label:
- subu t0, ra, t0 # get reloc_delta
- move ra, t1 # restore return address
-
- beqz t0, __reloc_end # if delta is 0 we are in the right place
- nop
-
- /* Copy our code to the right place */
- la t1, _code_start # get linked address of _code_start
- la t2, _code_end # get linked address of _code_end
- addu t0, t0, t1 # calculate actual address of _code_start
-
-__reloc_copy:
- lw t3, 0(t0)
- sw t3, 0(t1)
- add t1, 4
- blt t1, t2, __reloc_copy
- add t0, 4
-
-__reloc_end:
-
- /* At this point we need to invalidate dcache and */
- /* icache before jumping to new code */
-
-1: /* Get cache sizes */
- .set mips32
- mfc0 s0,C0_CONFIG,1
- .set mips0
-
- li s1,CONF1_DL_MASK
- and s1,s0
- beq s1,zero,nodc
- nop
-
- srl s1,CONF1_DL_SHIFT
- li t0,CONF1_DL_BASE
- sll s1,t0,s1 /* s1 has D$ cache line size */
-
- li s2,CONF1_DA_MASK
- and s2,s0
- srl s2,CONF1_DA_SHIFT
- addiu s2,CONF1_DA_BASE /* s2 now has D$ associativity */
-
- li t0,CONF1_DS_MASK
- and t0,s0
- srl t0,CONF1_DS_SHIFT
- li s3,CONF1_DS_BASE
- sll s3,s3,t0 /* s3 has D$ sets per way */
-
- multu s2,s3 /* sets/way * associativity */
- mflo t0 /* total cache lines */
-
- multu s1,t0 /* D$ linesize * lines */
- mflo s2 /* s2 is now D$ size in bytes */
-
- /* Initilize the D$: */
- mtc0 zero,C0_TAGLO
- mtc0 zero,C0_TAGHI
-
- li t0,KSEG0 /* Just an address for the first $ line */
- addu t1,t0,s2 /* + size of cache == end */
-
- .set mips3
-1: cache Index_Writeback_Inv_D,0(t0)
- .set mips0
- bne t0,t1,1b
- addu t0,s1
-
-nodc:
- /* Now we get to do it all again for the I$ */
-
- move s3,zero /* just in case there is no icache */
- move s4,zero
-
- li t0,CONF1_IL_MASK
- and t0,s0
- beq t0,zero,noic
- nop
-
- srl t0,CONF1_IL_SHIFT
- li s3,CONF1_IL_BASE
- sll s3,t0 /* s3 has I$ cache line size */
-
- li t0,CONF1_IA_MASK
- and t0,s0
- srl t0,CONF1_IA_SHIFT
- addiu s4,t0,CONF1_IA_BASE /* s4 now has I$ associativity */
-
- li t0,CONF1_IS_MASK
- and t0,s0
- srl t0,CONF1_IS_SHIFT
- li s5,CONF1_IS_BASE
- sll s5,t0 /* s5 has I$ sets per way */
-
- multu s4,s5 /* sets/way * associativity */
- mflo t0 /* s4 is now total cache lines */
-
- multu s3,t0 /* I$ linesize * lines */
- mflo s4 /* s4 is cache size in bytes */
-
- /* Initilize the I$: */
- mtc0 zero,C0_TAGLO
- mtc0 zero,C0_TAGHI
-
- li t0,KSEG0 /* Just an address for the first $ line */
- addu t1,t0,s4 /* + size of cache == end */
-
- .set mips3
-1: cache Index_Invalidate_I,0(t0)
- .set mips0
- bne t0,t1,1b
- addu t0,s3
-
-noic:
- /* Setup new "C" stack */
- la sp, _stack
-
- addiu sp, -32 /* reserve stack for parameters */
-#if 0
- sw a0, 0(sp)
- sw a1, 4(sp)
- sw a2, 8(sp)
- sw a3, 12(sp)
-#endif
- sw s3, 16(sp) /* icache line size */
- sw s4, 20(sp) /* icache size */
- sw s1, 24(sp) /* dcache line size */
- sw s2, 28(sp) /* dcache size */
-
- /* jump to the decompressor routine */
- la t0, decompress_entry
- jr t0
- nop
-
- .set reorder
-END(startup)
+++ /dev/null
-OUTPUT_ARCH(mips)
-SECTIONS {
- .text : {
- _code_start = .;
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata.*)
- . = ALIGN(16);
- *(.data.lzma)
- }
-
- .data : {
- *(.data)
- *(.data.*)
- }
- _code_end = .;
-
- .bss : {
- *(.bss)
- *(.bss.*)
- }
-
- . = ALIGN(16);
- . = . + 8192;
- _stack = .;
-
- workspace = .;
-}
+++ /dev/null
-OUTPUT_ARCH(mips)
-SECTIONS {
- .data.lzma : {
- _lzma_data_start = .;
- *(.data)
- _lzma_data_end = .;
- }
-}
+++ /dev/null
-/*
- * Copyright (C) 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#include "printf.h"
-
-extern void board_putc(int ch);
-
-/* this is the maximum width for a variable */
-#define LP_MAX_BUF 256
-
-/* macros */
-#define IsDigit(x) ( ((x) >= '0') && ((x) <= '9') )
-#define Ctod(x) ( (x) - '0')
-
-/* forward declaration */
-static int PrintChar(char *, char, int, int);
-static int PrintString(char *, char *, int, int);
-static int PrintNum(char *, unsigned long, int, int, int, int, char, int);
-
-/* private variable */
-static const char theFatalMsg[] = "fatal error in lp_Print!";
-
-/* -*-
- * A low level printf() function.
- */
-static void
-lp_Print(void (*output)(void *, char *, int),
- void * arg,
- char *fmt,
- va_list ap)
-{
-
-#define OUTPUT(arg, s, l) \
- { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \
- (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \
- } else { \
- (*output)(arg, s, l); \
- } \
- }
-
- char buf[LP_MAX_BUF];
-
- char c;
- char *s;
- long int num;
-
- int longFlag;
- int negFlag;
- int width;
- int prec;
- int ladjust;
- char padc;
-
- int length;
-
- for(;;) {
- {
- /* scan for the next '%' */
- char *fmtStart = fmt;
- while ( (*fmt != '\0') && (*fmt != '%')) {
- fmt ++;
- }
-
- /* flush the string found so far */
- OUTPUT(arg, fmtStart, fmt-fmtStart);
-
- /* are we hitting the end? */
- if (*fmt == '\0') break;
- }
-
- /* we found a '%' */
- fmt ++;
-
- /* check for long */
- if (*fmt == 'l') {
- longFlag = 1;
- fmt ++;
- } else {
- longFlag = 0;
- }
-
- /* check for other prefixes */
- width = 0;
- prec = -1;
- ladjust = 0;
- padc = ' ';
-
- if (*fmt == '-') {
- ladjust = 1;
- fmt ++;
- }
-
- if (*fmt == '0') {
- padc = '0';
- fmt++;
- }
-
- if (IsDigit(*fmt)) {
- while (IsDigit(*fmt)) {
- width = 10 * width + Ctod(*fmt++);
- }
- }
-
- if (*fmt == '.') {
- fmt ++;
- if (IsDigit(*fmt)) {
- prec = 0;
- while (IsDigit(*fmt)) {
- prec = prec*10 + Ctod(*fmt++);
- }
- }
- }
-
-
- /* check format flag */
- negFlag = 0;
- switch (*fmt) {
- case 'b':
- if (longFlag) {
- num = va_arg(ap, long int);
- } else {
- num = va_arg(ap, int);
- }
- length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0);
- OUTPUT(arg, buf, length);
- break;
-
- case 'd':
- case 'D':
- if (longFlag) {
- num = va_arg(ap, long int);
- } else {
- num = va_arg(ap, int);
- }
- if (num < 0) {
- num = - num;
- negFlag = 1;
- }
- length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0);
- OUTPUT(arg, buf, length);
- break;
-
- case 'o':
- case 'O':
- if (longFlag) {
- num = va_arg(ap, long int);
- } else {
- num = va_arg(ap, int);
- }
- length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0);
- OUTPUT(arg, buf, length);
- break;
-
- case 'u':
- case 'U':
- if (longFlag) {
- num = va_arg(ap, long int);
- } else {
- num = va_arg(ap, int);
- }
- length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0);
- OUTPUT(arg, buf, length);
- break;
-
- case 'x':
- if (longFlag) {
- num = va_arg(ap, long int);
- } else {
- num = va_arg(ap, int);
- }
- length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0);
- OUTPUT(arg, buf, length);
- break;
-
- case 'X':
- if (longFlag) {
- num = va_arg(ap, long int);
- } else {
- num = va_arg(ap, int);
- }
- length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1);
- OUTPUT(arg, buf, length);
- break;
-
- case 'c':
- c = (char)va_arg(ap, int);
- length = PrintChar(buf, c, width, ladjust);
- OUTPUT(arg, buf, length);
- break;
-
- case 's':
- s = (char*)va_arg(ap, char *);
- length = PrintString(buf, s, width, ladjust);
- OUTPUT(arg, buf, length);
- break;
-
- case '\0':
- fmt --;
- break;
-
- default:
- /* output this char as it is */
- OUTPUT(arg, fmt, 1);
- } /* switch (*fmt) */
-
- fmt ++;
- } /* for(;;) */
-
- /* special termination call */
- OUTPUT(arg, "\0", 1);
-}
-
-
-/* --------------- local help functions --------------------- */
-static int
-PrintChar(char * buf, char c, int length, int ladjust)
-{
- int i;
-
- if (length < 1) length = 1;
- if (ladjust) {
- *buf = c;
- for (i=1; i< length; i++) buf[i] = ' ';
- } else {
- for (i=0; i< length-1; i++) buf[i] = ' ';
- buf[length - 1] = c;
- }
- return length;
-}
-
-static int
-PrintString(char * buf, char* s, int length, int ladjust)
-{
- int i;
- int len=0;
- char* s1 = s;
- while (*s1++) len++;
- if (length < len) length = len;
-
- if (ladjust) {
- for (i=0; i< len; i++) buf[i] = s[i];
- for (i=len; i< length; i++) buf[i] = ' ';
- } else {
- for (i=0; i< length-len; i++) buf[i] = ' ';
- for (i=length-len; i < length; i++) buf[i] = s[i-length+len];
- }
- return length;
-}
-
-static int
-PrintNum(char * buf, unsigned long u, int base, int negFlag,
- int length, int ladjust, char padc, int upcase)
-{
- /* algorithm :
- * 1. prints the number from left to right in reverse form.
- * 2. fill the remaining spaces with padc if length is longer than
- * the actual length
- * TRICKY : if left adjusted, no "0" padding.
- * if negtive, insert "0" padding between "0" and number.
- * 3. if (!ladjust) we reverse the whole string including paddings
- * 4. otherwise we only reverse the actual string representing the num.
- */
-
- int actualLength =0;
- char *p = buf;
- int i;
-
- do {
- int tmp = u %base;
- if (tmp <= 9) {
- *p++ = '0' + tmp;
- } else if (upcase) {
- *p++ = 'A' + tmp - 10;
- } else {
- *p++ = 'a' + tmp - 10;
- }
- u /= base;
- } while (u != 0);
-
- if (negFlag) {
- *p++ = '-';
- }
-
- /* figure out actual length and adjust the maximum length */
- actualLength = p - buf;
- if (length < actualLength) length = actualLength;
-
- /* add padding */
- if (ladjust) {
- padc = ' ';
- }
- if (negFlag && !ladjust && (padc == '0')) {
- for (i = actualLength-1; i< length-1; i++) buf[i] = padc;
- buf[length -1] = '-';
- } else {
- for (i = actualLength; i< length; i++) buf[i] = padc;
- }
-
-
- /* prepare to reverse the string */
- {
- int begin = 0;
- int end;
- if (ladjust) {
- end = actualLength - 1;
- } else {
- end = length -1;
- }
-
- while (end > begin) {
- char tmp = buf[begin];
- buf[begin] = buf[end];
- buf[end] = tmp;
- begin ++;
- end --;
- }
- }
-
- /* adjust the string pointer */
- return length;
-}
-
-static void printf_output(void *arg, char *s, int l)
-{
- int i;
-
- // special termination call
- if ((l==1) && (s[0] == '\0')) return;
-
- for (i=0; i< l; i++) {
- board_putc(s[i]);
- if (s[i] == '\n') board_putc('\r');
- }
-}
-
-void printf(char *fmt, ...)
-{
- va_list ap;
- va_start(ap, fmt);
- lp_Print(printf_output, 0, fmt, ap);
- va_end(ap);
-}
+++ /dev/null
-/*
- * Copyright (C) 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifndef _printf_h_
-#define _printf_h_
-
-#include <stdarg.h>
-void printf(char *fmt, ...);
-
-#endif /* _printf_h_ */
+++ /dev/null
-#
-# Copyright (C) 2007,2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-
-define Image/cmdline/yaffs2
- root=/dev/mtdblock3 rootfstype=yaffs2
-endef
-
-define Image/BuildKernel/RouterBoard
- $(CP) $(KDIR)/vmlinux-initramfs.elf $(call imgname,kernel-initramfs,rb1xx)
- $(STAGING_DIR_HOST)/bin/patch-cmdline $(call imgname,kernel-initramfs,rb1xx) \
- '$(strip $(call Image/cmdline/yaffs2))'
-endef
-
-ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),y)
- define Image/BuildKernel
- $(call Image/BuildKernel/RouterBoard)
- endef
-endif
-
+++ /dev/null
-#
-# Copyright (C) 2007,2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Image/Build/ZyXEL
- $(call Image/Build/Loader,$(2),bin,0x80500000,0,y,$(2))
- $(call Image/Build/TRXNoloader,$(call imgname,$(1),$(2)).trx,$(1))
- $(STAGING_DIR_HOST)/bin/mkzynfw -B $(2) \
- -b $(KDIR)/loader-$(2).bin \
- -r $(call imgname,$(1),$(2)).trx:0x10000 \
- -o $(call imgname,$(1),$(2))-webui.bin
-endef
-
-define Image/Build/Template/ZyXEL
- $(call Image/Build/ZyXEL,$(1),$(2))
-endef
-
-define Image/Build/Template/ZyXEL/squashfs
- $(call Image/Build/Template/ZyXEL,squashfs,$(1))
-endef
-
-define Image/Build/Template/ZyXEL/jffs2
- $(call Image/Build/Template/ZyXEL,jffs2,$(1))
-endef
-
-define Image/Build/Template/ZyXEL/Initramfs
- $(call Image/Build/LZMAKernel/KArgs,$(1),bin)
-endef
-
-#
-# Profiles
-#
-define Image/Build/Profile/P334WT
- $(call Image/Build/Template/ZyXEL/$(1),p-334wt)
-endef
-
-define Image/Build/Profile/P335WT
- $(call Image/Build/Template/ZyXEL/$(1),p-335wt)
-endef
-
-define Image/Build/Profile/Generic
- $(call Image/Build/Profile/P334WT,$(1))
- $(call Image/Build/Profile/P335WT,$(1))
-endef
-
+++ /dev/null
-#
-# Copyright (C) 2007-2009 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define trxedimax/jffs2-128k
--a 0x20000 -f $(KDIR)/root.jffs2-128k
-endef
-
-define trxedimax/jffs2-64k
--a 0x10000 -f $(KDIR)/root.jffs2-64k
-endef
-
-define trxedimax/squashfs
--a 1024 -f $(KDIR)/root.squashfs
-endef
-
-define Image/Build/TRXEdimax
- $(STAGING_DIR_HOST)/bin/trx -o $(1) -f $(KDIR)/vmlinux.lzma \
- $(call trxedimax/$(2))
-endef
-
-define Image/Build/Compex
- $(call Image/Build/Loader,$(2),gz,0x80500000,0,y,$(2))
- $(call Image/Build/TRX,$(call imgname,$(1),$(2)).trx,$(1),$(KDIR)/loader-$(2).gz)
-endef
-
-define Image/Build/Edimax
- $(call Image/Build/Loader,$(2),gz,0x80500000,0x6D8,y,$(2))
- $(call Image/Build/TRXEdimax,$(call imgname,$(1),$(2)).trx,$(1))
- $(STAGING_DIR_HOST)/bin/mkcsysimg -B $(2) -d -w \
- -r $(KDIR)/loader-$(2).gz::0x1000 \
- -x $(call imgname,$(1),$(2)).trx:0x10000 \
- -x $(JFFS2MARK):0x10000 \
- $(call imgname,$(1),$(2))-webui.bin
- $(STAGING_DIR_HOST)/bin/mkcsysimg -B $(2) -d \
- -r $(KDIR)/loader-$(2).gz::0x1000 \
- -x $(call imgname,$(1),$(2)).trx:0x10000 \
- -x $(JFFS2MARK):0x10000 \
- $(call imgname,$(1),$(2))-xmodem.bin
- rm -f $(call imgname,$(1),$(2)).trx
-endef
-
-define Image/Build/Osbridge
- $(call Image/Build/Loader,$(2),gz,0x80500000,0x6D8,y,$(2))
- $(call Image/Build/TRXEdimax,$(call imgname,$(1),$(2)).trx,$(1))
- $(STAGING_DIR_HOST)/bin/mkcsysimg -B $(2) -d \
- -r $(KDIR)/loader-$(2).gz::0x1000 \
- -x $(call imgname,$(1),$(2)).trx:0x10000 \
- -x $(JFFS2MARK):0x10000 \
- $(call imgname,$(1),$(2))-firmware.bin
- $(STAGING_DIR_HOST)/bin/osbridge-crc \
- -i $(call imgname,$(1),$(2))-firmware.bin \
- -o $(call imgname,$(1),$(2))-temp.bin
- $(STAGING_DIR_HOST)/bin/pc1crypt \
- -i $(call imgname,$(1),$(2))-temp.bin \
- -o $(call imgname,$(1),$(2))-webui.bin
- rm -f $(call imgname,$(1),$(2))-temp.bin
- rm -f $(call imgname,$(1),$(2)).trx
-endef
-
-define Image/Build/Infineon
- $(call Image/Build/Loader,$(2),gz,0x80500000,0x6D8,y,$(2))
- $(call Image/Build/TRXNoloader,$(call imgname,$(1),$(2)).trx,$(1))
- dd if=$(KDIR)/loader-$(2).gz of=$(call imgname,$(1),$(2)).img bs=64k conv=sync
- cat $(call imgname,$(1),$(2)).trx >> $(call imgname,$(1),$(2)).img
-endef
-
-define Image/Build/Cellvision
- $(call Image/Build/Loader,$(2),bin,0x80500000,0x6D8,y,$(3))
- mkdir -p $(BIN_DIR)/tmp
- cp $(KDIR)/loader-$(2).bin $(BIN_DIR)/tmp/vmlinux.bin
- gzip -9 $(BIN_DIR)/tmp/vmlinux.bin
- dd if=$(BIN_DIR)/tmp/vmlinux.bin.gz of=$(call imgname,$(1),$(2))-xmodem.bin bs=64k conv=sync
- rm -rf $(BIN_DIR)/tmp
- $(call Image/Build/TRXNoloader,$(call imgname,$(1),$(2)).trx,$(1))
- cat $(call imgname,$(1),$(2)).trx >> $(call imgname,$(1),$(2))-xmodem.bin
- $(STAGING_DIR_HOST)/bin/mkcasfw -B $(2) -d \
- -K $(call imgname,$(1),$(2))-xmodem.bin \
- $(call imgname,$(1),$(2))-webui.bin
-endef
-
-define Image/Build/Cellvision2
- # only for CAS-700/771/790/861
- $(call Image/Build/Loader,$(2),gz,0x80500000,0x6D8,y,$(3))
- $(call Image/Build/TRXNoloader,$(call imgname,$(1),$(2)).trx,$(1))
- dd if=$(KDIR)/loader-$(2).gz of=$(call imgname,$(1),$(2)).bin bs=64k conv=sync
- cat $(call imgname,$(1),$(2)).trx >> $(call imgname,$(1),$(2)).bin
- echo -ne '\x14\x07\x24\x06$(2)' | dd bs=14 count=1 conv=sync >> $(call imgname,$(1),$(2)).bin
- echo -ne 'OpenWrt\x00\x00\x00' >> $(call imgname,$(1),$(2)).bin
-endef
-
-define Image/Build/MyLoader
- $(call Image/Build/Loader,$(2),gz,0x80500000,0)
- $(call Image/Build/TRXNoloader,$(call imgname,$(1),$(2)).trx,$(1))
- $(STAGING_DIR_HOST)/bin/mkmylofw -B $(2) \
- -p0x20000:0x10000:ahp:0x80001000 \
- -p0x30000:0 \
- -b0x20000:0x10000:h:$(KDIR)/loader-$(2).gz \
- -b0x30000:0::$(call imgname,$(1),$(2)).trx \
- $(call imgname,$(1),$(2)).bin
-endef
-
-#
-# Cellvision CAS-630/630W, CAS-670/670W, NFS-101U/101WU, NFS-202U/202WU
-#
-define Image/Build/Template/Cellvision
- $(call Image/Build/Cellvision,$(1),$(2),$(3))
-endef
-
-define Image/Build/Template/Cellvision/squashfs
- $(call Image/Build/Template/Cellvision,squashfs,$(1),$(2))
-endef
-
-define Image/Build/Template/Cellvision/jffs2-64k
- $(call Image/Build/Template/Cellvision,jffs2-64k,$(1),$(2))
-endef
-
-#
-# Cellvision CAS-700/700W, CAS-771/771W, CAS-790, CAS-861/861W
-#
-define Image/Build/Template/Cellvision2
- $(call Image/Build/Cellvision2,$(1),$(2),$(3))
-endef
-
-define Image/Build/Template/Cellvision2/squashfs
- $(call Image/Build/Template/Cellvision2,squashfs,$(1),$(2))
-endef
-
-define Image/Build/Template/Cellvision2/jffs2-64k
- $(call Image/Build/Template/Cellvision2,jffs2-64k,$(1),$(2))
-endef
-
-define Image/Build/Template/Cellvision2/Initramfs
- $(call Image/Build/LZMAKernel/Cellvision,$(1),$(2),gz)
-endef
-
-#
-# Compex NP27G, NP28G, WP54G, WP54AG, WPP54G, WPP54AG
-#
-define Image/Build/Template/Compex
- $(call Image/Build/MyLoader,$(1),$(2))
-endef
-
-define Image/Build/Template/Compex/squashfs
- $(call Image/Build/Template/Compex,squashfs,$(1))
-endef
-
-define Image/Build/Template/Compex/jffs2-64k
- $(call Image/Build/Template/Compex,jffs2-64k,$(1))
-endef
-
-define Image/Build/Template/Compex/Initramfs
- $(call Image/Build/LZMAKernel/Generic,$(1),bin)
-endef
-
-#
-# Compex WP54G-WRT
-#
-define Image/Build/Template/WP54GWRT
- $(call Image/Build/Compex,$(1),wp54g-wrt)
-endef
-
-define Image/Build/Template/WP54GWRT/squashfs
- $(call Image/Build/Template/WP54GWRT,squashfs)
-endef
-
-define Image/Build/Template/WP54GWRT/jffs2-64k
- $(call Image/Build/Template/WP54GWRT,jffs2-64k)
-endef
-
-define Image/Build/Template/WP54GWRT/Initramfs
- $(call Image/Build/LZMAKernel/KArgs,wp54g-wrt,bin)
-endef
-
-#
-# Edimax BR-6104K, BR-6104KP, BR-6104Wg, BR-6114WG
-#
-define Image/Build/Template/Edimax
- $(call Image/Build/Edimax,$(1),$(2))
-endef
-
-define Image/Build/Template/Edimax/squashfs
- $(call Image/Build/Template/Edimax,squashfs,$(1))
-endef
-
-define Image/Build/Template/Edimax/Initramfs
- $(call Image/Build/LZMAKernel/Admboot,$(1),gz)
-endef
-
-#
-# Infineon EASY 5120, EASY 83000
-#
-define Image/Build/Template/Infineon
- $(call Image/Build/Infineon,$(1),$(2))
-endef
-
-define Image/Build/Template/Infineon/squashfs
- $(call Image/Build/Template/Infineon,squashfs,$(1))
-endef
-
-define Image/Build/Template/Infineon/jffs2-64k
- $(call Image/Build/Template/Infineon,jffs2-64k,$(1))
-endef
-
-define Image/Build/Template/Infineon/Initramfs
- $(call Image/Build/LZMAKernel/Admboot,$(1),gz)
-endef
-
-#
-# Generic EB-214A
-#
-define Image/Build/Template/Edimax/Initramfs
- $(call Image/Build/LZMAKernel/Admboot,eb-214a,bin)
-endef
-
-
-#
-# Mikrotik RouterBOARD 1xx
-#
-define Image/Build/Template/Mikrotik/Initramfs
- $(CP) $(KDIR)/vmlinux.elf $(call imgname,netboot,rb1xx)
-endef
-
-#
-# OSBRiDGE 5GXi/5XLi
-#
-define Image/Build/Template/Osbridge
- $(call Image/Build/Osbridge,$(1),$(2))
-endef
-
-define Image/Build/Template/Osbridge/squashfs
- $(call Image/Build/Template/Osbridge,squashfs,$(1))
-endef
-
-define Image/Build/Template/Osbridge/Initramfs
- $(call Image/Build/LZMAKernel/Admboot,$(1),gz)
-endef
-
-#
-# Profiles
-#
-define Image/Build/Profile/CAS630
- $(call Image/Build/Template/Cellvision/$(1),cas-630,cas-630)
-endef
-
-define Image/Build/Profile/CAS630W
- $(call Image/Build/Template/Cellvision/$(1),cas-630w,cas-630)
-endef
-
-define Image/Build/Profile/CAS670
- $(call Image/Build/Template/Cellvision/$(1),cas-670,cas-670)
-endef
-
-define Image/Build/Profile/CAS670W
- $(call Image/Build/Template/Cellvision/$(1),cas-670w,cas-670)
-endef
-
-define Image/Build/Profile/NFS101U
- $(call Image/Build/Template/Cellvision/$(1),nfs-101u,nfs-101u)
- $(call Image/Build/Template/Cellvision/$(1),dn-7013,nfs-101u)
- $(call Image/Build/Template/Cellvision/$(1),dns-120,nfs-101u)
- $(call Image/Build/Template/Cellvision/$(1),mu-5000fs,nfs-101u)
- $(call Image/Build/Template/Cellvision/$(1),tn-u100,nfs-101u)
- $(call Image/Build/Template/Cellvision/$(1),cg-nsadp,nfs-101u)
-endef
-
-define Image/Build/Profile/NFS101WU
- $(call Image/Build/Template/Cellvision/$(1),nfs-101wu,nfs-101u)
- $(call Image/Build/Template/Cellvision/$(1),dns-g120,nfs-101u)
-endef
-
-define Image/Build/Profile/CAS700
- $(call Image/Build/Template/Cellvision2/$(1),cas-700,cas-700)
-endef
-
-define Image/Build/Profile/CAS700W
- $(call Image/Build/Template/Cellvision2/$(1),cas-700w,cas-700)
-endef
-
-define Image/Build/Profile/CAS771
- $(call Image/Build/Template/Cellvision2/$(1),cas-771,cas-771)
-endef
-
-define Image/Build/Profile/CAS771W
- $(call Image/Build/Template/Cellvision2/$(1),cas-771w,cas-771)
-endef
-
-define Image/Build/Profile/CAS790
- $(call Image/Build/Template/Cellvision2/$(1),cas-790,cas-790)
-endef
-
-define Image/Build/Profile/CAS861
- $(call Image/Build/Template/Cellvision2/$(1),cas-861,cas-861)
-endef
-
-define Image/Build/Profile/CAS861W
- $(call Image/Build/Template/Cellvision2/$(1),cas-861w,cas-861)
-endef
-
-define Image/Build/Profile/NP27G
- $(call Image/Build/Template/Compex/$(1),np27g)
-endef
-
-define Image/Build/Profile/NP28G
- $(call Image/Build/Template/Compex/$(1),np28g)
-endef
-
-define Image/Build/Profile/WP54
- $(call Image/Build/Template/Compex/$(1),wp54g)
- $(call Image/Build/Template/Compex/$(1),wp54ag)
- $(call Image/Build/Template/Compex/$(1),wpp54g)
- $(call Image/Build/Template/Compex/$(1),wpp54ag)
- $(call Image/Build/Template/WP54GWRT/$(1))
-endef
-
-define Image/Build/Profile/BR6104K
- $(call Image/Build/Template/Edimax/$(1),br-6104k)
-endef
-
-define Image/Build/Profile/BR6104KP
- $(call Image/Build/Template/Edimax/$(1),br-6104kp)
-endef
-
-define Image/Build/Profile/BR6104WG
- $(call Image/Build/Template/Edimax/$(1),br-6104wg)
-endef
-
-define Image/Build/Profile/BR6114WG
- $(call Image/Build/Template/Edimax/$(1),br-6114wg)
-endef
-
-define Image/Build/Profile/EASY83000
- $(call Image/Build/Template/Infineon/$(1),easy-83000)
-endef
-
-define Image/Build/Profile/EASY5120RT
- $(call Image/Build/Template/Infineon/$(1),easy-5120-rt)
-endef
-
-define Image/Build/Profile/EASY5120PATA
- $(call Image/Build/Template/Infineon/$(1),easy-5120p-ata)
-endef
-
-define Image/Build/Profile/PMUGW
- $(call Image/Build/Template/Infineon/$(1),powerline-mugw)
-endef
-
-define Image/Build/Profile/5GXI
- $(call Image/Build/Template/Osbridge/$(1),5gxi)
-endef
-
-define Image/Build/Profile/RouterBoard
- $(call Image/Build/Template/Mikrotik/$(1))
-endef
-
-ifeq ($(CONFIG_BROKEN),y)
- define Image/Build/Experimental
- # Cellvison
- $(call Image/Build/Profile/CAS630,$(1))
- $(call Image/Build/Profile/CAS630W,$(1))
- $(call Image/Build/Profile/CAS670,$(1))
- $(call Image/Build/Profile/CAS670W,$(1))
- $(call Image/Build/Profile/CAS700,$(1))
- $(call Image/Build/Profile/CAS700W,$(1))
- $(call Image/Build/Profile/CAS771,$(1))
- $(call Image/Build/Profile/CAS771W,$(1))
- $(call Image/Build/Profile/CAS861,$(1))
- $(call Image/Build/Profile/CAS861W,$(1))
- # Motorola
- $(call Image/Build/Profile/PMUGW,$(1))
- # OSBRiDGE
- $(call Image/Build/Profile/5GXI,$(1))
- endef
-endif
-
-define Image/Build/Profile/Generic
- # Cellvision
- $(call Image/Build/Profile/NFS101U,$(1))
- $(call Image/Build/Profile/NFS101WU,$(1))
- # Compex
- $(call Image/Build/Profile/WP54,$(1))
- $(call Image/Build/Profile/NP27G,$(1))
- $(call Image/Build/Profile/NP28G,$(1))
- # Edimax
- $(call Image/Build/Profile/BR6104K,$(1))
- $(call Image/Build/Profile/BR6104KP,$(1))
- $(call Image/Build/Profile/BR6104WG,$(1))
- $(call Image/Build/Profile/BR6114WG,$(1))
- $(call Image/Build/Profile/EB214A,$(1))
- # Infineon
- $(call Image/Build/Profile/EASY83000,$(1))
- $(call Image/Build/Profile/EASY5120RT,$(1))
- $(call Image/Build/Profile/EASY5120PATA,$(1))
- # Mikrotik
- $(call Image/Build/Profile/RB1xx/$(1))
-
- $(call Image/Build/Experimental,$(1))
-endef
+++ /dev/null
-#
-# Copyright (C) 2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define KernelPackage/ledtrig-adm5120-switch
- SUBMENU:=$(OTHER_MENU)
- TITLE:=LED ADM5120 Switch Port Status Trigger
- DEPENDS:=@TARGET_adm5120
- KCONFIG:=CONFIG_LEDS_TRIGGER_ADM5120_SWITCH
- FILES:=$(LINUX_DIR)/drivers/leds/ledtrig-adm5120-switch.ko
- AUTOLOAD:=$(call AutoLoad,50,ledtrig-adm5120-switch)
-endef
-
-define KernelPackage/ledtrig-adm5120-switch/description
- Kernel module to allow LEDs to be controlled by the port states
- of the ADM5120 built-in ethernet switch.
-endef
-
-$(eval $(call KernelPackage,ledtrig-adm5120-switch))
-
-
-define KernelPackage/pata-rb153-cf
- SUBMENU:=$(BLOCK_MENU)
- TITLE:=RouterBOARD 153 CF Slot support
- DEPENDS:=@TARGET_adm5120_router_le
- KCONFIG:=CONFIG_PATA_RB153_CF
- FILES:=$(LINUX_DIR)/drivers/ata/pata_rb153_cf.ko
- AUTOLOAD:=$(call AutoLoad,30,pata_rb153_cf,1)
- $(call AddDepends/ata)
-endef
-
-define KernelPackage/pata-rb153-cf/description
- Kernel support for the RouterBoard 153 CF slot.
-endef
-
-$(eval $(call KernelPackage,pata-rb153-cf,1))
-
-
-define KernelPackage/usb-adm5120
- SUBMENU:=$(USB_MENU)
- TITLE:=Support for the ADM5120 HCD controller
- DEPENDS:=@TARGET_adm5120
- KCONFIG:=CONFIG_USB_ADM5120_HCD
- FILES:=$(LINUX_DIR)/drivers/usb/host/adm5120-hcd.ko
- AUTOLOAD:=$(call AutoLoad,50,adm5120-hcd,1)
- $(call AddDepends/usb)
-endef
-
-define KernelPackage/usb-adm5120/description
- Kernel support for the ADM5120 HCD USB controller
-endef
-
-$(eval $(call KernelPackage,usb-adm5120))
+++ /dev/null
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -51,6 +51,24 @@ choice
- prompt "System type"
- default SGI_IP22
-
-+config ADM5120
-+ bool "Infineon/ADMtek ADM5120 SoC based machines"
-+ select BOOT_RAW
-+ select NO_EXCEPT_FILL
-+ select CEVT_R4K
-+ select CSRC_R4K
-+ select SYS_HAS_CPU_MIPS32_R1
-+ select SYS_HAS_EARLY_PRINTK
-+ select DMA_NONCOHERENT
-+ select IRQ_CPU
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select ARCH_REQUIRE_GPIOLIB
-+ select SWAP_IO_SPACE if CPU_BIG_ENDIAN
-+ select MIPS_MACHINE
-+ select HAVE_CLK
-+
- config MIPS_ALCHEMY
- bool "Alchemy processor based machines"
- select 64BIT_PHYS_ADDR
-@@ -836,6 +854,7 @@ config NLM_XLP_BOARD
-
- endchoice
-
-+source "arch/mips/adm5120/Kconfig"
- source "arch/mips/alchemy/Kconfig"
- source "arch/mips/ath79/Kconfig"
- source "arch/mips/bcm47xx/Kconfig"
---- a/arch/mips/Kbuild.platforms
-+++ b/arch/mips/Kbuild.platforms
-@@ -1,5 +1,6 @@
- # All platforms listed in alphabetic order
-
-+platforms += adm5120
- platforms += alchemy
- platforms += ar7
- platforms += ath79
+++ /dev/null
---- a/drivers/mtd/maps/Kconfig
-+++ b/drivers/mtd/maps/Kconfig
-@@ -501,4 +501,8 @@ config MTD_LATCH_ADDR
-
- If compiled as a module, it will be called latch-addr-flash.
-
-+config MTD_ADM5120
-+ tristate "Map driver for ADM5120 based boards"
-+ depends on ADM5120
-+
- endmenu
---- a/drivers/mtd/maps/Makefile
-+++ b/drivers/mtd/maps/Makefile
-@@ -37,6 +37,7 @@ obj-$(CONFIG_MTD_SCx200_DOCFLASH)+= scx2
- obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o
- obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
- obj-$(CONFIG_MTD_PCI) += pci.o
-+obj-$(CONFIG_MTD_ADM5120) += adm5120-flash.o
- obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o
- obj-$(CONFIG_MTD_IMPA7) += impa7.o
- obj-$(CONFIG_MTD_UCLINUX) += uclinux.o
+++ /dev/null
---- a/drivers/net/Kconfig
-+++ b/drivers/net/Kconfig
-@@ -255,6 +255,10 @@ source "drivers/net/dsa/Kconfig"
-
- source "drivers/net/ethernet/Kconfig"
-
-+config ADM5120_ENET
-+ tristate "ADM5120 Ethernet switch support"
-+ depends on ADM5120
-+
- source "drivers/net/fddi/Kconfig"
-
- source "drivers/net/hippi/Kconfig"
---- a/drivers/net/Makefile
-+++ b/drivers/net/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_CAN) += can/
- obj-$(CONFIG_ETRAX_ETHERNET) += cris/
- obj-$(CONFIG_NET_DSA) += dsa/
- obj-$(CONFIG_ETHERNET) += ethernet/
-+obj-$(CONFIG_ADM5120_ENET) += adm5120sw.o
- obj-$(CONFIG_FDDI) += fddi/
- obj-$(CONFIG_HIPPI) += hippi/
- obj-$(CONFIG_HAMRADIO) += hamradio/
+++ /dev/null
---- a/drivers/usb/Makefile
-+++ b/drivers/usb/Makefile
-@@ -13,6 +13,7 @@ obj-$(CONFIG_USB_DWC3) += dwc3/
- obj-$(CONFIG_USB_MON) += mon/
-
- obj-$(CONFIG_PCI) += host/
-+obj-$(CONFIG_USB_ADM5120_HCD) += host/
- obj-$(CONFIG_USB_EHCI_HCD) += host/
- obj-$(CONFIG_USB_ISP116X_HCD) += host/
- obj-$(CONFIG_USB_OHCI_HCD) += host/
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -4,6 +4,10 @@
- comment "USB Host Controller Drivers"
- depends on USB
-
-+config USB_ADM5120_HCD
-+ tristate "ADM5120 HCD support (EXPERIMENTAL)"
-+ depends on USB && ADM5120 && EXPERIMENTAL
-+
- config USB_C67X00_HCD
- tristate "Cypress C67x00 HCD support"
- depends on USB
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -23,6 +23,7 @@ obj-$(CONFIG_USB_WHCI_HCD) += whci/
-
- obj-$(CONFIG_PCI) += pci-quirks.o
-
-+obj-$(CONFIG_USB_ADM5120_HCD) += adm5120-hcd.o
- obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
- obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
- obj-$(CONFIG_USB_EHCI_HCD_PLATFORM) += ehci-platform.o
+++ /dev/null
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -18,6 +18,7 @@ obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
- obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
- obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
- ops-bcm63xx.o
-+obj-$(CONFIG_ADM5120) += pci-adm5120.o
- obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
- obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
- obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
---- a/include/linux/pci_ids.h
-+++ b/include/linux/pci_ids.h
-@@ -1807,6 +1807,9 @@
- #define PCI_VENDOR_ID_ESDGMBH 0x12fe
- #define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
-
-+#define PCI_VENDOR_ID_ADMTEK 0x1317
-+#define PCI_DEVICE_ID_ADMTEK_ADM5120 0x5120
-+
- #define PCI_VENDOR_ID_SIIG 0x131f
- #define PCI_SUBVENDOR_ID_SIIG 0x131f
- #define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000
+++ /dev/null
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -579,4 +579,12 @@ config LEDS_TRIGGER_USBDEV
- This allows LEDs to be controlled by the presence/activity of
- an USB device. If unsure, say N.
-
-+config LEDS_TRIGGER_ADM5120_SWITCH
-+ tristate "LED ADM5120 Switch Port Status Trigger"
-+ depends on LEDS_TRIGGERS && ADM5120
-+ help
-+ This allows LEDs to be controlled by the port states of
-+ the ADM5120 built-in Ethernet Switch
-+ If unsure, say N.
-+
- endif # NEW_LEDS
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -68,3 +68,4 @@ obj-$(CONFIG_LEDS_TRIGGER_TRANSIENT) +=
- obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o
- obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o
- obj-$(CONFIG_LEDS_TRIGGER_USBDEV) += ledtrig-usbdev.o
-+obj-$(CONFIG_LEDS_TRIGGER_ADM5120_SWITCH) += ledtrig-adm5120-switch.o
+++ /dev/null
---- a/drivers/mtd/chips/cfi_cmdset_0002.c
-+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
-@@ -48,6 +48,12 @@
- #define SST49LF008A 0x005a
- #define AT49BV6416 0x00d6
-
-+/* Macronix */
-+#define MX29LV160B 0x2249 /* MX29LV160 Bottom-boot chip */
-+#define MX29LV160T 0x22C4 /* MX29LV160 Top-boot chip */
-+#define MX29LV320B 0x22A8 /* MX29LV320 Bottom-boot chip */
-+#define MX29LV320T 0x22A7 /* MX29LV320 Top-boot chip */
-+
- static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
- static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
- static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
-@@ -358,6 +364,41 @@ static struct cfi_fixup cfi_nopri_fixup_
- { 0, 0, NULL }
- };
-
-+#ifdef CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC
-+/*
-+ * Some Macronix chips has no/bad bootblock information in the CFI table
-+ */
-+static void fixup_macronix_bootloc(struct mtd_info *mtd)
-+{
-+ struct map_info *map = mtd->priv;
-+ struct cfi_private *cfi = map->fldrv_priv;
-+ struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
-+ __u8 t;
-+
-+ switch (cfi->id) {
-+ /* TODO: put affected chip ids here */
-+ case MX29LV160B:
-+ case MX29LV320B:
-+ t = 2; /* Bottom boot */
-+ break;
-+ case MX29LV160T:
-+ case MX29LV320T:
-+ t = 3; /* Top boot */
-+ break;
-+ default:
-+ return;
-+ }
-+
-+ if (extp->TopBottom == t)
-+ /* boot location detected by the CFI layer is correct */
-+ return;
-+
-+ extp->TopBottom = t;
-+ printk("%s: Macronix chip detected, id:0x%04X, boot location forced "
-+ "to %s\n", map->name, cfi->id, (t == 2) ? "bottom" : "top");
-+}
-+#endif /* CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC */
-+
- static struct cfi_fixup cfi_fixup_table[] = {
- { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
- #ifdef AMD_BOOTLOC_BUG
-@@ -400,6 +441,9 @@ static struct cfi_fixup fixup_table[] =
- */
- { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
- { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
-+#ifdef CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC
-+ { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_macronix_bootloc },
-+#endif
- { 0, 0, NULL }
- };
-
---- a/drivers/mtd/chips/Kconfig
-+++ b/drivers/mtd/chips/Kconfig
-@@ -189,6 +189,14 @@ config MTD_CFI_AMDSTD
- provides support for one of those command sets, used on chips
- including the AMD Am29LV320.
-
-+config MTD_CFI_FIXUP_MACRONIX_BOOTLOC
-+ bool "Fix boot-block location for Macronix flash chips"
-+ depends on MTD_CFI_AMDSTD
-+ help
-+ Some Macronix flash chips have no/wrong boot-block location in the
-+ CFI table, and the driver may detect the type incorrectly. Select
-+ this if your board has such chip.
-+
- config MTD_CFI_STAA
- tristate "Support for ST (Advanced Architecture) flash chips"
- depends on MTD_GEN_PROBE
+++ /dev/null
---- a/drivers/mtd/chips/jedec_probe.c
-+++ b/drivers/mtd/chips/jedec_probe.c
-@@ -115,6 +115,10 @@
- #define UPD29F064115 0x221C
-
- /* PMC */
-+#define PM39LV512 0x001B
-+#define PM39LV010 0x001C
-+#define PM39LV020 0x003D
-+#define PM39LV040 0x003E
- #define PM49FL002 0x006D
- #define PM49FL004 0x006E
- #define PM49FL008 0x006A
-@@ -1259,6 +1263,54 @@ static const struct amd_flash_info jedec
- ERASEINFO(0x02000,2),
- ERASEINFO(0x04000,1),
- }
-+ }, {
-+ .mfr_id = CFI_MFR_PMC,
-+ .dev_id = PM39LV512,
-+ .name = "PMC Pm39LV512",
-+ .devtypes = CFI_DEVICETYPE_X8,
-+ .uaddr = MTD_UADDR_0x0555_0x02AA,
-+ .dev_size = SIZE_64KiB,
-+ .cmd_set = P_ID_AMD_STD,
-+ .nr_regions = 1,
-+ .regions = {
-+ ERASEINFO(0x01000,16),
-+ }
-+ }, {
-+ .mfr_id = CFI_MFR_PMC,
-+ .dev_id = PM39LV010,
-+ .name = "PMC Pm39LV010",
-+ .devtypes = CFI_DEVICETYPE_X8,
-+ .uaddr = MTD_UADDR_0x0555_0x02AA,
-+ .dev_size = SIZE_128KiB,
-+ .cmd_set = P_ID_AMD_STD,
-+ .nr_regions = 1,
-+ .regions = {
-+ ERASEINFO(0x01000,32),
-+ }
-+ }, {
-+ .mfr_id = CFI_MFR_PMC,
-+ .dev_id = PM39LV020,
-+ .name = "PMC Pm39LV020",
-+ .devtypes = CFI_DEVICETYPE_X8,
-+ .uaddr = MTD_UADDR_0x0555_0x02AA,
-+ .dev_size = SIZE_256KiB,
-+ .cmd_set = P_ID_AMD_STD,
-+ .nr_regions = 1,
-+ .regions = {
-+ ERASEINFO(0x01000,64),
-+ }
-+ }, {
-+ .mfr_id = CFI_MFR_PMC,
-+ .dev_id = PM39LV040,
-+ .name = "PMC Pm39LV040",
-+ .devtypes = CFI_DEVICETYPE_X8,
-+ .uaddr = MTD_UADDR_0x0555_0x02AA,
-+ .dev_size = SIZE_512KiB,
-+ .cmd_set = P_ID_AMD_STD,
-+ .nr_regions = 1,
-+ .regions = {
-+ ERASEINFO(0x01000,128),
-+ }
- }, {
- .mfr_id = CFI_MFR_PMC,
- .dev_id = PM49FL002,
+++ /dev/null
---- a/drivers/mtd/Kconfig
-+++ b/drivers/mtd/Kconfig
-@@ -31,6 +31,10 @@ config MTD_ROOTFS_SPLIT
- bool "Automatically split 'rootfs' partition for squashfs"
- default y
-
-+config MTD_TRXSPLIT
-+ bool "Automatically find and split TRX partitions"
-+ default n
-+
- config MTD_REDBOOT_PARTS
- tristate "RedBoot partition table parsing"
- ---help---
---- a/drivers/mtd/Makefile
-+++ b/drivers/mtd/Makefile
-@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
- obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o
- obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o
- obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
-+obj-$(CONFIG_MTD_TRXSPLIT) += trxsplit.o
-
- # 'Users' - code which presents functionality to userspace.
- obj-$(CONFIG_MTD_CHAR) += mtdchar.o
+++ /dev/null
---- a/drivers/ata/Makefile
-+++ b/drivers/ata/Makefile
-@@ -90,6 +90,7 @@ obj-$(CONFIG_PATA_PCMCIA) += pata_pcmcia
- obj-$(CONFIG_PATA_PALMLD) += pata_palmld.o
- obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
- obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
-+obj-$(CONFIG_PATA_RB153_CF) += pata_rb153_cf.o
- obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
- obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
- obj-$(CONFIG_PATA_SAMSUNG_CF) += pata_samsung_cf.o
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -852,6 +852,15 @@ config PATA_QDI
- help
- Support for QDI 6500 and 6580 PATA controllers on VESA local bus.
-
-+config PATA_RB153_CF
-+ tristate "RouterBOARD 153 Compact Flash support"
-+ depends on ADM5120_MACH_RB_153
-+ help
-+ This option enables support for a Compact Flash connected on
-+ the RouterBOARD 153.
-+
-+ If unsure, say N.
-+
- config PATA_RB532
- tristate "RouterBoard 532 PATA CompactFlash support"
- depends on MIKROTIK_RB532
+++ /dev/null
---- a/drivers/tty/serial/amba-pl010.c
-+++ b/drivers/tty/serial/amba-pl010.c
-@@ -49,11 +49,9 @@
-
- #include <asm/io.h>
-
--#define UART_NR 8
--
- #define SERIAL_AMBA_MAJOR 204
- #define SERIAL_AMBA_MINOR 16
--#define SERIAL_AMBA_NR UART_NR
-+#define SERIAL_AMBA_NR CONFIG_SERIAL_AMBA_PL010_NUMPORTS
-
- #define AMBA_ISR_PASS_LIMIT 256
-
-@@ -79,9 +77,9 @@ static void pl010_stop_tx(struct uart_po
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int cr;
-
-- cr = readb(uap->port.membase + UART010_CR);
-+ cr = __raw_readl(uap->port.membase + UART010_CR);
- cr &= ~UART010_CR_TIE;
-- writel(cr, uap->port.membase + UART010_CR);
-+ __raw_writel(cr, uap->port.membase + UART010_CR);
- }
-
- static void pl010_start_tx(struct uart_port *port)
-@@ -89,9 +87,9 @@ static void pl010_start_tx(struct uart_p
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int cr;
-
-- cr = readb(uap->port.membase + UART010_CR);
-+ cr = __raw_readl(uap->port.membase + UART010_CR);
- cr |= UART010_CR_TIE;
-- writel(cr, uap->port.membase + UART010_CR);
-+ __raw_writel(cr, uap->port.membase + UART010_CR);
- }
-
- static void pl010_stop_rx(struct uart_port *port)
-@@ -99,9 +97,9 @@ static void pl010_stop_rx(struct uart_po
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int cr;
-
-- cr = readb(uap->port.membase + UART010_CR);
-+ cr = __raw_readl(uap->port.membase + UART010_CR);
- cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
-- writel(cr, uap->port.membase + UART010_CR);
-+ __raw_writel(cr, uap->port.membase + UART010_CR);
- }
-
- static void pl010_enable_ms(struct uart_port *port)
-@@ -109,9 +107,9 @@ static void pl010_enable_ms(struct uart_
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int cr;
-
-- cr = readb(uap->port.membase + UART010_CR);
-+ cr = __raw_readl(uap->port.membase + UART010_CR);
- cr |= UART010_CR_MSIE;
-- writel(cr, uap->port.membase + UART010_CR);
-+ __raw_writel(cr, uap->port.membase + UART010_CR);
- }
-
- static void pl010_rx_chars(struct uart_amba_port *uap)
-@@ -119,9 +117,9 @@ static void pl010_rx_chars(struct uart_a
- struct tty_struct *tty = uap->port.state->port.tty;
- unsigned int status, ch, flag, rsr, max_count = 256;
-
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- while (UART_RX_DATA(status) && max_count--) {
-- ch = readb(uap->port.membase + UART01x_DR);
-+ ch = __raw_readl(uap->port.membase + UART01x_DR);
- flag = TTY_NORMAL;
-
- uap->port.icount.rx++;
-@@ -130,9 +128,9 @@ static void pl010_rx_chars(struct uart_a
- * Note that the error handling code is
- * out of the main execution path
- */
-- rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
-+ rsr = __raw_readl(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
- if (unlikely(rsr & UART01x_RSR_ANY)) {
-- writel(0, uap->port.membase + UART01x_ECR);
-+ __raw_writel(0, uap->port.membase + UART01x_ECR);
-
- if (rsr & UART01x_RSR_BE) {
- rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
-@@ -162,7 +160,7 @@ static void pl010_rx_chars(struct uart_a
- uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
-
- ignore_char:
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- }
- spin_unlock(&uap->port.lock);
- tty_flip_buffer_push(tty);
-@@ -175,7 +173,7 @@ static void pl010_tx_chars(struct uart_a
- int count;
-
- if (uap->port.x_char) {
-- writel(uap->port.x_char, uap->port.membase + UART01x_DR);
-+ __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR);
- uap->port.icount.tx++;
- uap->port.x_char = 0;
- return;
-@@ -187,7 +185,7 @@ static void pl010_tx_chars(struct uart_a
-
- count = uap->port.fifosize >> 1;
- do {
-- writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
-+ __raw_writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
- xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
- uap->port.icount.tx++;
- if (uart_circ_empty(xmit))
-@@ -205,9 +203,9 @@ static void pl010_modem_status(struct ua
- {
- unsigned int status, delta;
-
-- writel(0, uap->port.membase + UART010_ICR);
-+ __raw_writel(0, uap->port.membase + UART010_ICR);
-
-- status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
-+ status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
-
- delta = status ^ uap->old_status;
- uap->old_status = status;
-@@ -235,7 +233,7 @@ static irqreturn_t pl010_int(int irq, vo
-
- spin_lock(&uap->port.lock);
-
-- status = readb(uap->port.membase + UART010_IIR);
-+ status = __raw_readl(uap->port.membase + UART010_IIR);
- if (status) {
- do {
- if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
-@@ -248,7 +246,7 @@ static irqreturn_t pl010_int(int irq, vo
- if (pass_counter-- == 0)
- break;
-
-- status = readb(uap->port.membase + UART010_IIR);
-+ status = __raw_readl(uap->port.membase + UART010_IIR);
- } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
- UART010_IIR_TIS));
- handled = 1;
-@@ -262,7 +260,7 @@ static irqreturn_t pl010_int(int irq, vo
- static unsigned int pl010_tx_empty(struct uart_port *port)
- {
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
-- unsigned int status = readb(uap->port.membase + UART01x_FR);
-+ unsigned int status = __raw_readl(uap->port.membase + UART01x_FR);
- return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
- }
-
-@@ -272,7 +270,7 @@ static unsigned int pl010_get_mctrl(stru
- unsigned int result = 0;
- unsigned int status;
-
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- if (status & UART01x_FR_DCD)
- result |= TIOCM_CAR;
- if (status & UART01x_FR_DSR)
-@@ -298,12 +296,12 @@ static void pl010_break_ctl(struct uart_
- unsigned int lcr_h;
-
- spin_lock_irqsave(&uap->port.lock, flags);
-- lcr_h = readb(uap->port.membase + UART010_LCRH);
-+ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
- if (break_state == -1)
- lcr_h |= UART01x_LCRH_BRK;
- else
- lcr_h &= ~UART01x_LCRH_BRK;
-- writel(lcr_h, uap->port.membase + UART010_LCRH);
-+ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
- spin_unlock_irqrestore(&uap->port.lock, flags);
- }
-
-@@ -331,12 +329,12 @@ static int pl010_startup(struct uart_por
- /*
- * initialise the old status of the modem signals
- */
-- uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
-+ uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
-
- /*
- * Finally, enable interrupts
- */
-- writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
-+ __raw_writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
- uap->port.membase + UART010_CR);
-
- return 0;
-@@ -359,10 +357,10 @@ static void pl010_shutdown(struct uart_p
- /*
- * disable all interrupts, disable the port
- */
-- writel(0, uap->port.membase + UART010_CR);
-+ __raw_writel(0, uap->port.membase + UART010_CR);
-
- /* disable break condition and fifos */
-- writel(readb(uap->port.membase + UART010_LCRH) &
-+ __raw_writel(__raw_readl(uap->port.membase + UART010_LCRH) &
- ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
- uap->port.membase + UART010_LCRH);
-
-@@ -384,7 +382,7 @@ pl010_set_termios(struct uart_port *port
- /*
- * Ask the core to calculate the divisor for us.
- */
-- baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
-+ baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
- quot = uart_get_divisor(port, baud);
-
- switch (termios->c_cflag & CSIZE) {
-@@ -447,25 +445,25 @@ pl010_set_termios(struct uart_port *port
- uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
-
- /* first, disable everything */
-- old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
-+ old_cr = __raw_readl(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
-
- if (UART_ENABLE_MS(port, termios->c_cflag))
- old_cr |= UART010_CR_MSIE;
-
-- writel(0, uap->port.membase + UART010_CR);
-+ __raw_writel(0, uap->port.membase + UART010_CR);
-
- /* Set baud rate */
- quot -= 1;
-- writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
-- writel(quot & 0xff, uap->port.membase + UART010_LCRL);
-+ __raw_writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
-+ __raw_writel(quot & 0xff, uap->port.membase + UART010_LCRL);
-
- /*
- * ----------v----------v----------v----------v-----
- * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
- * ----------^----------^----------^----------^-----
- */
-- writel(lcr_h, uap->port.membase + UART010_LCRH);
-- writel(old_cr, uap->port.membase + UART010_CR);
-+ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
-+ __raw_writel(old_cr, uap->port.membase + UART010_CR);
-
- spin_unlock_irqrestore(&uap->port.lock, flags);
- }
-@@ -547,7 +545,7 @@ static struct uart_ops amba_pl010_pops =
- .verify_port = pl010_verify_port,
- };
-
--static struct uart_amba_port *amba_ports[UART_NR];
-+static struct uart_amba_port *amba_ports[SERIAL_AMBA_NR];
-
- #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
-
-@@ -557,10 +555,10 @@ static void pl010_console_putchar(struct
- unsigned int status;
-
- do {
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- barrier();
- } while (!UART_TX_READY(status));
-- writel(ch, uap->port.membase + UART01x_DR);
-+ __raw_writel(ch, uap->port.membase + UART01x_DR);
- }
-
- static void
-@@ -574,8 +572,8 @@ pl010_console_write(struct console *co,
- /*
- * First save the CR then disable the interrupts
- */
-- old_cr = readb(uap->port.membase + UART010_CR);
-- writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
-+ old_cr = __raw_readl(uap->port.membase + UART010_CR);
-+ __raw_writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
-
- uart_console_write(&uap->port, s, count, pl010_console_putchar);
-
-@@ -584,10 +582,10 @@ pl010_console_write(struct console *co,
- * and restore the TCR
- */
- do {
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- barrier();
- } while (status & UART01x_FR_BUSY);
-- writel(old_cr, uap->port.membase + UART010_CR);
-+ __raw_writel(old_cr, uap->port.membase + UART010_CR);
-
- clk_disable(uap->clk);
- }
-@@ -596,9 +594,9 @@ static void __init
- pl010_console_get_options(struct uart_amba_port *uap, int *baud,
- int *parity, int *bits)
- {
-- if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
-+ if (__raw_readl(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
- unsigned int lcr_h, quot;
-- lcr_h = readb(uap->port.membase + UART010_LCRH);
-+ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
-
- *parity = 'n';
- if (lcr_h & UART01x_LCRH_PEN) {
-@@ -613,8 +611,8 @@ pl010_console_get_options(struct uart_am
- else
- *bits = 8;
-
-- quot = readb(uap->port.membase + UART010_LCRL) |
-- readb(uap->port.membase + UART010_LCRM) << 8;
-+ quot = __raw_readl(uap->port.membase + UART010_LCRL) |
-+ __raw_readl(uap->port.membase + UART010_LCRM) << 8;
- *baud = uap->port.uartclk / (16 * (quot + 1));
- }
- }
-@@ -633,7 +631,7 @@ static int __init pl010_console_setup(st
- * if so, search for the first available port that does have
- * console support.
- */
-- if (co->index >= UART_NR)
-+ if (co->index >= SERIAL_AMBA_NR)
- co->index = 0;
- uap = amba_ports[co->index];
- if (!uap)
-@@ -675,7 +673,7 @@ static struct uart_driver amba_reg = {
- .dev_name = "ttyAM",
- .major = SERIAL_AMBA_MAJOR,
- .minor = SERIAL_AMBA_MINOR,
-- .nr = UART_NR,
-+ .nr = SERIAL_AMBA_NR,
- .cons = AMBA_CONSOLE,
- };
-
---- a/drivers/tty/serial/Kconfig
-+++ b/drivers/tty/serial/Kconfig
-@@ -16,10 +16,18 @@ config SERIAL_AMBA_PL010
- help
- This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
- an Integrator/AP or Integrator/PP2 platform, or if you have a
-- Cirrus Logic EP93xx CPU, say Y or M here.
-+ Cirrus Logic EP93xx CPU or an Infineon ADM5120 SOC, say Y or M here.
-
- If unsure, say N.
-
-+config SERIAL_AMBA_PL010_NUMPORTS
-+ int "Maximum number of AMBA PL010 serial ports"
-+ depends on SERIAL_AMBA_PL010
-+ default "8"
-+ ---help---
-+ Set this to the number of serial ports you want the AMBA PL010 driver
-+ to support.
-+
- config SERIAL_AMBA_PL010_CONSOLE
- bool "Support for console on AMBA serial port"
- depends on SERIAL_AMBA_PL010=y
+++ /dev/null
---- a/drivers/leds/leds-gpio.c
-+++ b/drivers/leds/leds-gpio.c
-@@ -56,13 +56,17 @@ static void gpio_led_set(struct led_clas
- container_of(led_cdev, struct gpio_led_data, cdev);
- int level;
-
-- if (value == LED_OFF)
-- level = 0;
-- else
-- level = 1;
--
-- if (led_dat->active_low)
-- level = !level;
-+ switch (value) {
-+ case LED_OFF:
-+ level = led_dat->active_low ? 1 : 0;
-+ break;
-+ case LED_FULL:
-+ level = led_dat->active_low ? 0 : 1;
-+ break;
-+ default:
-+ level = value;
-+ break;
-+ }
-
- /* Setting GPIOs with I2C/etc requires a task context, and we don't
- * seem to have a reliable way to know if we're already in one; so
+++ /dev/null
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -985,6 +985,18 @@ config RC32434_WDT
- To compile this driver as a module, choose M here: the
- module will be called rc32434_wdt.
-
-+config ADM5120_WDT
-+ tristate "Infineon ADM5120 SoC hardware watchdog"
-+ depends on WATCHDOG && ADM5120
-+ help
-+ This is a driver for hardware watchdog integrated in Infineon
-+ ADM5120 SoC. This watchdog simply watches your kernel to make sure
-+ it doesn't freeze, and if it does, it reboots your computer after a
-+ certain amount of time.
-+
-+ To compile this driver as a module, choose M here: the module will be
-+ called adm5120_wdt.
-+
- config INDYDOG
- tristate "Indy/I2 Hardware Watchdog"
- depends on SGI_HAS_INDYDOG
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -122,6 +122,7 @@ obj-$(CONFIG_ATH79_WDT) += ath79_wdt.o
- obj-$(CONFIG_BCM47XX_WDT) += bcm47xx_wdt.o
- obj-$(CONFIG_BCM63XX_WDT) += bcm63xx_wdt.o
- obj-$(CONFIG_RC32434_WDT) += rc32434_wdt.o
-+obj-$(CONFIG_ADM5120_WDT) += adm5120_wdt.o
- obj-$(CONFIG_INDYDOG) += indydog.o
- obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o
- obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
+++ /dev/null
-#!/bin/sh
-# wget2nand
-# This script can be used to download a TGZ file from your build system which
-# contains the files to be installed on the NAND flash on your RB1xx card.
-# The one parameter is the URL of the TGZ file to be downloaded.
-# Licence GPL V2
-# Author david.goodenough@linkchoose.co.uk
-# Based on cf2nand from RB532 support
-. /lib/functions.sh
-
-[ -d /tmp/wget2nand-rootfs ] && {
- echo "/tmp/wget2nand-rootfs already exists"
- exit 1
-}
-
-[ -d /tmp/wget2nand-kernel ] && {
- echo "/tmp/wget2nand-kernel already exists"
- exit 1
-}
-
-# need to find the wget server from the command line
-url=$1
-[ -z "$url" ] && {
- echo "No URL specified for image TGZ"
- echo "Usage : $0 URL"
- exit 1
-}
-
-# first get an address for br-lan using udhcpc
-killall udhcpc
-/sbin/udhcpc -i br-lan
-
-mtd_kernel="$(find_mtd_part 'kernel')"
-mtd_rootfs="$(find_mtd_part 'rootfs')"
-[ -z "$mtd_kernel" -o -z "$mtd_rootfs" ] && {
- echo "Cannot find NAND Flash partitions"
- exit 1
-}
-
-echo "Erasing filesystem..."
-mtd erase kernel 2>/dev/null >/dev/null
-mtd erase rootfs 2>/dev/null >/dev/null
-
-echo "Mounting $mtd_rootfs as new root and $mtd_kernel as kernel partition"
-
-mkdir /tmp/wget2nand-rootfs
-mkdir /tmp/wget2nand-kernel
-mount -t yaffs2 "$mtd_rootfs" /tmp/wget2nand-rootfs
-mount -t yaffs2 "$mtd_kernel" /tmp/wget2nand-kernel
-
-echo "Erasing existing files..."
-rm -rf /tmp/wget2nand-rootfs/*
-
-echo "Copying filesystem..."
-( wget -O - $url/openwrt-adm5120-rb1xx-rootfs.tar.gz) | ( cd /tmp/wget2nand-rootfs/; tar xvz )
-# RouterBOOT is looking for a kernel named "kernel"
-wget -O /tmp/wget2nand-kernel/kernel $url/openwrt-adm5120-rb1xx-vmlinux.elf
-
-chmod +x /tmp/wget2nand-kernel/kernel
-
-# make sure everything is written before we unmount the partitions
-echo "chmod ugo+x /" > /tmp/wget2nand-rootfs/etc/uci-defaults/set_root_permission
-sync
-ls /tmp/wget2nand-kernel/
-ls /tmp/wget2nand-rootfs/
-# use kexec if present
-[ -x /usr/sbin/kexec ] && {
- kexec -l /tmp/wget2nand-kernel/kernel --command-line="$(cat /proc/cmdline) rootfstype=yaffs2 root=$mtd_kernel"
- kexec -e
-}
-# unmount the partitions and remove the directories into which they were mounted
-umount /tmp/wget2nand-kernel
-umount /tmp/wget2nand-rootfs
-rmdir /tmp/wget2nand-kernel
-rmdir /tmp/wget2nand-rootfs
-
-# all done
-echo "Image written, you can now reboot. Remember to change the boot source to Boot from Nand"
+++ /dev/null
-# CONFIG_ADM5120_MACH_5GXI is not set
-# CONFIG_ADM5120_MACH_BR_6104K is not set
-# CONFIG_ADM5120_MACH_BR_6104KP is not set
-# CONFIG_ADM5120_MACH_BR_61X4WG is not set
-# CONFIG_ADM5120_MACH_CAS_771 is not set
-# CONFIG_ADM5120_MACH_EASY5120P_ATA is not set
-# CONFIG_ADM5120_MACH_EASY5120_RT is not set
-# CONFIG_ADM5120_MACH_EASY5120_WVOIP is not set
-# CONFIG_ADM5120_MACH_EASY83000 is not set
-# CONFIG_ADM5120_MACH_EB_214A is not set
-# CONFIG_ADM5120_MACH_NFS_101 is not set
-# CONFIG_ADM5120_MACH_NP27G is not set
-# CONFIG_ADM5120_MACH_NP28G is not set
-# CONFIG_ADM5120_MACH_PMUGW is not set
-CONFIG_ADM5120_MACH_RB_11X=y
-CONFIG_ADM5120_MACH_RB_133=y
-CONFIG_ADM5120_MACH_RB_133C=y
-CONFIG_ADM5120_MACH_RB_150=y
-CONFIG_ADM5120_MACH_RB_153=y
-CONFIG_ADM5120_MACH_RB_192=y
-# CONFIG_ADM5120_MACH_WP54 is not set
-# CONFIG_ADM5120_OEM_CELLVISION is not set
-# CONFIG_ADM5120_OEM_COMPEX is not set
-# CONFIG_ADM5120_OEM_EDIMAX is not set
-# CONFIG_ADM5120_OEM_GENERIC is not set
-# CONFIG_ADM5120_OEM_INFINEON is not set
-CONFIG_ADM5120_OEM_MIKROTIK=y
-# CONFIG_ADM5120_OEM_MOTOROLA is not set
-# CONFIG_ADM5120_OEM_OSBRIDGE is not set
-CONFIG_CMDLINE="console=ttyAM0,115200 rootfstype=yaffs2"
-# CONFIG_JFFS2_FS is not set
-# CONFIG_MTD_MYLOADER_PARTS is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_PLATFORM=y
-# CONFIG_MTD_ROOTFS_SPLIT is not set
-# CONFIG_MTD_SM_COMMON is not set
-# CONFIG_MTD_TRXSPLIT is not set
-# CONFIG_OVERLAYFS_FS is not set
-# CONFIG_PATA_RB153_CF is not set
-# CONFIG_SQUASHFS is not set
-CONFIG_YAFFS_9BYTE_TAGS=y
-# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
-CONFIG_YAFFS_AUTO_YAFFS2=y
-# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
-# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
-CONFIG_YAFFS_DISABLE_TAGS_ECC=y
-# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
-CONFIG_YAFFS_FS=y
-CONFIG_YAFFS_XATTR=y
-CONFIG_YAFFS_YAFFS1=y
-CONFIG_YAFFS_YAFFS2=y
+++ /dev/null
-#
-# Copyright (C) 2007 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/RouterBoard
- NAME:=Mikrotik RouterBoard 1xx family
- PACKAGES:=kmod-ath5k kmod-pata-rb153-cf
-endef
-
-define Profile/RouterBoard/Description
- Package set compatible with the RouterBoard RB1xx devices. Contains RouterOS to OpenWrt\\\
- installation scripts.
-endef
-
-$(eval $(call Profile,RouterBoard))
+++ /dev/null
-ARCH:=mipsel
-ARCH_PACKAGES:=adm5120_mipsel
-SUBTARGET:=rb1xx
-BOARDNAME:=MikroTik RB-1xx boards
-FEATURES:=tgz
-
-define Target/Description
- Build firmware images for Mikrotik RB-1xx series.
-endef
+++ /dev/null
-CONFIG_ADM5120_MACH_P_334WT=y
-CONFIG_ADM5120_MACH_P_335=y
-# CONFIG_ADM5120_OEM_CELLVISION is not set
-# CONFIG_ADM5120_OEM_COMPEX is not set
-# CONFIG_ADM5120_OEM_EDIMAX is not set
-# CONFIG_ADM5120_OEM_GENERIC is not set
-# CONFIG_ADM5120_OEM_INFINEON is not set
-# CONFIG_ADM5120_OEM_MOTOROLA is not set
-# CONFIG_ADM5120_OEM_OSBRIDGE is not set
-CONFIG_ADM5120_OEM_ZYXEL=y
-CONFIG_CPU_BIG_ENDIAN=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-CONFIG_SWAP_IO_SPACE=y
+++ /dev/null
-#
-# Copyright (C) 2007 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Generic
- NAME:=Generic (default)
- PACKAGES:=
-endef
-
-define Profile/Generic/Description
- Generic package set compatible with most boards.
-endef
-$(eval $(call Profile,Generic))
-
+++ /dev/null
-#
-# Copyright (C) 2007 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/P334WT
- NAME:=ZyXEL Prestige 334WT
- PACKAGES:=kmod-acx-mac80211
-endef
-
-define Profile/P334WT/Description
- Package set optimized for the ZyXEL Prestige 334WT board.
-endef
-
-define Profile/P335WT
- NAME:=ZyXEL Prestige 335WT
- PACKAGES:=kmod-acx-mac80211 kmod-usb-core kmod-usb-adm5120
-endef
-
-define Profile/P335WT/Description
- Package set optimized for the ZyXEL Prestige 335WT board.
-endef
-
-$(eval $(call Profile,P334WT))
-$(eval $(call Profile,P335WT))
+++ /dev/null
-ARCH:=mips
-ARCH_PACKAGES:=adm5120_mips
-SUBTARGET:=router_be
-BOARDNAME:=Big Endian
-FEATURES:=squashfs
-
-define Target/Description
- Build firmware images for Infineon/ADMTek ADM5120 based boards
- running in big-endian mode (e.g : ZyXEL Prestige 335WT ...)
-endef
-
+++ /dev/null
-#
-# Copyright (C) 2007 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Generic
- NAME:=Generic (default)
- PACKAGES:=
-endef
-
-define Profile/Generic/Description
- Generic package set compatible with most boards.
-endef
-
-define Profile/EB-214A
- NAME:=Generic EB-214A
- PACKAGES:=-wpad-mini -admswconfig -kmod-usb-adm5120 -kmod-ledtrig-adm5120-switch -dnsmasq kmod-usb-uhci kmod-usb2
-endef
-
-define Profile/EB-214A/Description
- Package set optimized for generic EB-214A boards.
-endef
-
-$(eval $(call Profile,Generic))
-$(eval $(call Profile,EB-214A))
-
+++ /dev/null
-#
-# Copyright (C) 2007-2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/CAS630
- NAME:=Cellvision CAS-630 IP camera (Experimental)
- # TODO: add default packages
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/CAS630/Description
- Package set optimized for the Cellvision CAS-630 device.
-endef
-
-define Profile/CAS630W
- NAME:=Cellvision CAS-630W IP camera (Experimental)
- # TODO: add default packages
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/CAS630W/Description
- Package set optimized for the Cellvision CAS-630W device.
-endef
-
-define Profile/CAS670
- NAME:=Cellvision CAS-670 IP camera (Experimental)
- # TODO: add default packages
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/CAS670/Description
- Package set optimized for the Cellvision CAS-670 device.
-endef
-
-define Profile/CAS670W
- NAME:=Cellvision CAS-670W IP camera (Experimental)
- # TODO: add default packages
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/CAS670W/Description
- Package set optimized for the Cellvision CAS-670 device.
-endef
-
-define Profile/CAS700
- NAME:=Cellvision CAS-700 IP camera (Experimental)
- # TODO: add default packages
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/CAS700/Description
- Package set optimized for the Cellvision CAS-700 device.
-endef
-
-define Profile/CAS700W
- NAME:=Cellvision CAS-700W IP camera (Experimental)
- # TODO: add default packages
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/CAS700W/Description
- Package set optimized for the Cellvision CAS-700W device.
-endef
-
-define Profile/CAS771
- NAME:=Cellvision CAS-771 IP camera (Experimental)
- PACKAGES:=-wpad-mini kmod-video-cpia2 kmod-usb-ohci kmod-usb2 kmod-usb-audio
-endef
-
-define Profile/CAS771/Description
- Package set optimized for the Cellvision CAS-771 device.
-endef
-
-define Profile/CAS771W
- NAME:=Cellvision CAS-771W IP camera (Experimental)
- PACKAGES:=-wpad-mini kmod-video-cpia2 kmod-usb-ohci kmod-usb2 kmod-usb-audio kmod-rt2500-pci
-endef
-
-define Profile/CAS771W/Description
- Package set optimized for the Cellvision CAS-771W device.
-endef
-
-define Profile/CAS790
- NAME:=Cellvision CAS-790 IP camera (Experimental)
- # TODO: add default packages
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/CAS790/Description
- Package set optimized for the Cellvision CAS-790 device.
-endef
-
-define Profile/CAS861
- NAME:=Cellvision CAS-861 IP camera (Experimental)
- # TODO: add default packages
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/CAS861/Description
- Package set optimized for the Cellvision CAS-861 device.
-endef
-
-define Profile/CAS861W
- NAME:=Cellvision CAS-861W IP camera (Experimental)
- PACKAGES:=kmod-rt2500-pci
-endef
-
-define Profile/CAS861W/Description
- Package set optimized for the Cellvision CAS-861W device.
-endef
-
-define Profile/NFS101U
- NAME:=Cellvision NFS-101U Network File Server (Experimental)
- PACKAGES:=-wpad-mini kmod-usb-ohci kmod-usb2
-endef
-
-define Profile/NFS101U/Description
- Package set optimized for the Cellvision NFS-101U device.
-endef
-
-define Profile/NFS101WU
- NAME:=Cellvision NFS-101WU Network File Server (Experimental)
- PACKAGES:=-wpad-mini kmod-usb-ohci kmod-usb2
-endef
-
-define Profile/NFS101WU/Description
- Package set optimized for the Cellvision NFS-101WU device.
-endef
-
-$(eval $(call Profile,CAS630))
-$(eval $(call Profile,CAS630W))
-$(eval $(call Profile,CAS670))
-$(eval $(call Profile,CAS670W))
-$(eval $(call Profile,CAS700))
-$(eval $(call Profile,CAS700W))
-$(eval $(call Profile,CAS771))
-$(eval $(call Profile,CAS771W))
-$(eval $(call Profile,CAS790))
-$(eval $(call Profile,CAS861))
-$(eval $(call Profile,CAS861W))
-$(eval $(call Profile,NFS101U))
-$(eval $(call Profile,NFS101WU))
-
+++ /dev/null
-#
-# Copyright (C) 2007 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/NP27G
- NAME:=Compex NP27G
- PACKAGES:=kmod-ath5k kmod-usb-core kmod-usb-adm5120
-endef
-
-define Profile/NP27G/Description
- Package set optimized for the Compex NP27G.
-endef
-
-define Profile/NP28G
- NAME:=Compex NP28G
- PACKAGES:=kmod-ath5k kmod-usb-core kmod-usb-uhci kmod-usb2
-endef
-
-define Profile/NP28G/Description
- Package set optimized for the Compex NP28G.
-endef
-
-define Profile/WP54
- NAME:=Compex WP54 family
- PACKAGES:=kmod-ath5k
-endef
-
-define Profile/WP54/Description
- Package set optimized for the Compex WP54 family.
-endef
-
-$(eval $(call Profile,NP27G))
-$(eval $(call Profile,NP28G))
-$(eval $(call Profile,WP54))
+++ /dev/null
-#
-# Copyright (C) 2007,2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/BR6104K
- NAME:=Edimax BR-6104K (Unofficial)
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/BR6104K/Description
- Package set optimized for the Edimax BR-6104K
-endef
-
-define Profile/BR6104KP
- NAME:=Edimax BR-6104KP (Unofficial)
- PACKAGES:=-wpad-mini kmod-usb-core kmod-usb-adm5120
-endef
-
-define Profile/BR6104KP/Description
- Package set optimized for the Edimax BR-6104KP
-endef
-
-define Profile/BR6104WG
- NAME:=Edimax BR-6104Wg (Unofficial, No WiFi)
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/BR6104WG/Description
- Package set optimized for the Edimax BR-6104Wg
-endef
-
-define Profile/BR6114WG
- NAME:=Edimax BR-6114WG (Unofficial, No WiFi)
- PACKAGES:=-wpad-mini
-endef
-
-define Profile/BR6114WG/Description
- Package set optimized for the Edimax BR-6114WG
-endef
-
-$(eval $(call Profile,BR6104K))
-$(eval $(call Profile,BR6104KP))
-$(eval $(call Profile,BR6104WG))
-$(eval $(call Profile,BR6114WG))
+++ /dev/null
-#
-# Copyright (C) 2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/EASY5120RT
- NAME:=Infineon EASY 5120-RT Reference Board
- PACKAGES:=kmod-usb-core kmod-usb-adm5120
-endef
-
-define Profile/EASY5120RT/Description
- Package set optimized for the Infineon EASY 5120-RT Reference Board
-endef
-
-$(eval $(call Profile,EASY5120RT))
-
-define Profile/EASY5120PATA
- NAME:=Infineon EASY 5120P-ATA Reference Board
-endef
-
-define Profile/EASY5120RT/Description
- Package set optimized for the Infineon EASY 5120P-ATA Reference Board
-endef
-
-$(eval $(call Profile,EASY5120PATA))
+++ /dev/null
-#
-# Copyright (C) 2008 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/PMUGW
- NAME:=Motorola Powerline MU Gateway (EXPERIMENTAL)
-endef
-
-define Profile/PMUGW/Description
- Package set optimized for the Motorola Powerline MU Gateway board
-endef
-
-$(eval $(call Profile,PMUGW))
+++ /dev/null
-#
-# Copyright (C) 2007-2009 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/5GXI
- NAME:=Osbridge 5GXi/5XLi (Unofficial)
-endef
-
-define Profile/5GXI/Description
- Package set optimized for the OSBRiDGE 5GXi/5XLi boards.
-endef
-
-$(eval $(call Profile,5GXI))
+++ /dev/null
-ARCH:=mipsel
-ARCH_PACKAGES:=adm5120_mipsel
-SUBTARGET:=router_le
-BOARDNAME:=Little Endian
-FEATURES:=squashfs tgz
-
-define Target/Description
- Build firmware images for Infineon/ADMtek ADM5120 based boards
- running in little-endian mode (e.g: RouterBoard RB1xx, Compex WP54x ...)
-endef
-
+++ /dev/null
-#
-# Copyright (C) 2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=mipsel
-BOARD:=adm8668
-BOARDNAME:=Infineon WildPass ADM8668
-FEATURES:=squashfs usb pci
-MAINTAINER:=Florian Fainelli <florian@openwrt.org>
-
-LINUX_VERSION:=3.3.8
-
-include $(INCLUDE_DIR)/target.mk
-
-define Target/Description
- Build firmware images for Infineon WildPass (ADM8668) based routers
- (e.g. T-Mobile branded Linksys WRTU54G-TM)
-endef
-
-$(eval $(call BuildTarget))
+++ /dev/null
-#define Package/base-files/install-target
-# rm -f $(1)/etc/config/network
-#endef
+++ /dev/null
-config interface loopback
- option ifname lo
- option proto static
- option ipaddr 127.0.0.1
- option netmask 255.0.0.0
-
-config interface lan
- option ifname eth0
- option type bridge
- option proto static
- option ipaddr 192.168.1.1
- option netmask 255.255.255.0
- option ip6assign 60
-
-config interface wan
- option ifname eth1
- option proto dhcp
-
-config interface wan6
- option ifname @wan
- option proto dhcpv6
-
-config globals globals
- option ula_prefix auto
+++ /dev/null
-#!/bin/sh
-# Copyright (C) 2010 OpenWrt.org
-
-set_led() {
- local state="$1"
- [ -f "/proc/adm8668/sesled" ] && echo "$state" > "/proc/adm8668/sesled"
-}
-
-set_state() {
- case "$1" in
- preinit)
- set_led 1
- ;;
- failsafe)
- set_led 2
- ;;
- done)
- set_led 0
- ;;
- esac
-}
+++ /dev/null
-#!/bin/sh
-
-init_hotplug_failsafe() {
- echo '/sbin/hotplug.failsafe' > /proc/sys/kernel/hotplug
-}
-
-boot_hook_add preinit_main init_hotplug_failsafe
-
-
+++ /dev/null
-#!/bin/sh
-
-set_preinit_ifname() {
- ifname=eth0
-}
-
-boot_hook_add preinit_main set_preinit_ifname
-
-
+++ /dev/null
-PART_NAME=linux
-platform_check_image() {
- [ "$#" -gt 1 ] && return 1
-
- case "$(get_magic_word "$1")" in
- # u-boot
- 2705) return 0;;
- *)
- echo "Invalid image type. Please use only u-boot files"
- return 1
- ;;
- esac
-}
-
-# use default for platform_do_upgrade()
+++ /dev/null
-#!/bin/sh
-case "$1" in
- button) kill -USR1 1;;
-esac
+++ /dev/null
-CONFIG_ADM8668=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM_AMBA=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_R4K_LIB=y
-CONFIG_CMDLINE="console=ttyS0 earlyprintk"
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-CONFIG_CPU_MIPSR1=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_CSRC_R4K_LIB=y
-# CONFIG_DE2104X is not set
-# CONFIG_DE4X5 is not set
-CONFIG_DECOMPRESS_LZMA=y
-# CONFIG_DM9102 is not set
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EEPROM_93CX6=m
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_MIPS=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-CONFIG_MTD_ADM8668_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_TULIP=y
-CONFIG_NO_EXCEPT_FILL=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_AMBA_PL010=y
-CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
-CONFIG_SERIAL_AMBA_PL010_NUMPORTS=2
-CONFIG_SERIAL_AMBA_PL010_PORTNAME="ttyS"
-# CONFIG_SERIAL_AMBA_PL011 is not set
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TULIP=y
-CONFIG_TULIP_NAPI=y
-# CONFIG_TULIP_NAPI_HW_MITIGATION is not set
-# CONFIG_TULIP_PCI is not set
-CONFIG_TULIP_PLATFORM=y
-# CONFIG_ULI526X is not set
-CONFIG_USB_ARCH_HAS_XHCI=y
-# CONFIG_USB_HCD_BCMA is not set
-# CONFIG_USB_HCD_SSB is not set
-CONFIG_USB_SUPPORT=y
-# CONFIG_WINBOND_840 is not set
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-config ARM_AMBA
- def_bool y
+++ /dev/null
-#
-# something witty --neutronscott
-#
-
-obj-y := irq.o prom.o platform.o gpio.o \
- setup.o clock.o time.o early_printk.o \
+++ /dev/null
-#
-# Infineon ADM8668 WildPass
-#
-platform-$(CONFIG_ADM8668) += adm8668/
-cflags-$(CONFIG_ADM8668) += -I$(srctree)/arch/mips/include/asm/mach-adm8668
-load-$(CONFIG_ADM8668) += 0xffffffff80002000
+++ /dev/null
-/*
- * ADM8668 minimal clock support
- *
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * Licensed under the terms of the GPLv2
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-
-#include <adm8668.h>
-
-struct clk {
- unsigned long rate;
-};
-
-static struct clk uart_clk = {
- .rate = 62500000,
-};
-
-static struct clk sys_clk;
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
- const char *lookup = id;
-
- if (dev)
- lookup = dev_name(dev);
-
- if (!strcmp(lookup, "apb:uart0"))
- return &uart_clk;
- if (!strcmp(lookup, "sys"))
- return &sys_clk;
-
- return ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL(clk_get);
-
-int clk_enable(struct clk *clk)
-{
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
-void __init adm8668_init_clocks(void)
-{
- u32 adj;
-
- /* adjustable clock selection
- * CR3 bit 14~11, 0000 -> 175MHz, 0001 -> 180MHz, etc...
- */
- adj = (ADM8668_CONFIG_REG(ADM8668_CR3) >> 11) & 0xf;
- sys_clk.rate = 175000000 + (adj * 5000000);
-
- pr_info("ADM8668 CPU clock: %lu MHz\n", sys_clk.rate / 1000000);
-}
+++ /dev/null
-#include <linux/io.h>
-#include <linux/amba/serial.h>
-#include <adm8668.h>
-
-#define UART_READ(r) \
- __raw_readl((void __iomem *)(KSEG1ADDR(ADM8668_UART0_BASE) + (r)))
-
-#define UART_WRITE(v, r) \
- __raw_writel((v), (void __iomem *)(KSEG1ADDR(ADM8668_UART0_BASE) + (r)))
-
-void prom_putchar(char c)
-{
- UART_WRITE(c, UART01x_DR);
- while ((UART_READ(UART01x_FR) & UART01x_FR_TXFF) != 0)
- ;
-}
+++ /dev/null
-/*
- * Infineon/ADMTek ADM8668 WildPass GPIO support
- *
- * Copyright (C) 2012 Florian Fainelli <florian@openwrt.org>
- *
- * Licensed under the terms of GPLv2.
- *
- */
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-
-#include <adm8668.h>
-
-#define GPIO_MASK 0x3f
-
-#define GPIO_IN_OFS 0
-#define GPIO_OUT_OFS 6
-#define GPIO_OE_OFS 12
-
-struct adm8668_gpio_chip {
- void __iomem *base;
- struct gpio_chip chip;
-};
-
-static int adm8668_gpio_dir_out(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- struct adm8668_gpio_chip *c =
- container_of(chip, struct adm8668_gpio_chip, chip);
- u32 mask;
-
- /* clear input, set output enable and output value */
- mask = __raw_readl(c->base);
- mask &= ~(1 << offset);
- mask |= (1 << (offset + GPIO_OE_OFS));
- if (value)
- mask |= (1 << (offset + GPIO_OUT_OFS));
- else
- mask &= ~(1 << (offset + GPIO_OUT_OFS));
- __raw_writel(mask, c->base);
-
- return 0;
-}
-
-static int adm8668_gpio_dir_in(struct gpio_chip *chip,
- unsigned offset)
-{
- struct adm8668_gpio_chip *c =
- container_of(chip, struct adm8668_gpio_chip, chip);
- u32 mask;
-
- mask = __raw_readl(c->base);
- mask &= ~(((1 << (offset + GPIO_OE_OFS)) | (1 << (offset + GPIO_OUT_OFS))));
- mask |= (1 << offset);
- __raw_writel(mask, c->base);
-
- return 0;
-}
-
-static void adm8668_gpio_set(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- struct adm8668_gpio_chip *c =
- container_of(chip, struct adm8668_gpio_chip, chip);
- u32 mask;
-
- mask = __raw_readl(c->base);
- if (value)
- mask |= (1 << (offset + GPIO_OUT_OFS));
- else
- mask &= ~(1 << (offset + GPIO_OUT_OFS));
- __raw_writel(mask, c->base);
-}
-
-static int adm8668_gpio_get(struct gpio_chip *chip,
- unsigned offset)
-{
- struct adm8668_gpio_chip *c =
- container_of(chip, struct adm8668_gpio_chip, chip);
- u32 value;
-
- value = __raw_readl(c->base) & GPIO_MASK;
-
- return value & (1 << offset);
-}
-
-static struct adm8668_gpio_chip adm8668_gpio_cpu = {
- .base = (void __iomem *)KSEG1ADDR(ADM8668_CONFIG_BASE + CRGPIO_REG),
- .chip = {
- .label = "adm8668-cpu-gpio",
- .direction_output = adm8668_gpio_dir_out,
- .direction_input = adm8668_gpio_dir_in,
- .set = adm8668_gpio_set,
- .get = adm8668_gpio_get,
- .ngpio = 6,
- },
-};
-
-static struct adm8668_gpio_chip adm8668_gpio_wlan = {
- .base = (void __iomem *)KSEG1ADDR(ADM8668_WLAN_BASE + GPIO_REG),
- .chip = {
- .label = "adm8668-wlan-gpio",
- .direction_output = adm8668_gpio_dir_out,
- .direction_input = adm8668_gpio_dir_in,
- .set = adm8668_gpio_set,
- .get = adm8668_gpio_get,
- .ngpio = 6,
- .base = 6,
- },
-};
-
-static int __init adm8668_gpio_init(void)
-{
- int ret;
-
- ret = gpiochip_add(&adm8668_gpio_cpu.chip);
- if (ret)
- return ret;
-
- return gpiochip_add(&adm8668_gpio_wlan.chip);
-}
-arch_initcall(adm8668_gpio_init);
+++ /dev/null
-/*
- * Copyright (C) 2010 Scott Nicholas <neutronscott@scottn.us>
- * Copyright (C) 2012 Florian Fainelli <florian@openwrt.org>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/pm.h>
-#include <linux/irq.h>
-#include <asm/mipsregs.h>
-#include <asm/irq_cpu.h>
-#include <asm/irq.h>
-#include <adm8668.h>
-
-/* interrupt controller */
-#define IRQ_STATUS_REG 0x00 /* Read */
-#define IRQ_ENABLE_REG 0x08 /* Read/Write */
-#define IRQ_DISABLE_REG 0x0C /* Write */
-
-#define IRQ_MASK 0xffff
-
-static inline void intc_write_reg(u32 val, unsigned int reg)
-{
- void __iomem *base = (void __iomem *)KSEG1ADDR(ADM8668_INTC_BASE);
-
- __raw_writel(val, base + reg);
-}
-
-static inline u32 intc_read_reg(unsigned int reg)
-{
- void __iomem *base = (void __iomem *)KSEG1ADDR(ADM8668_INTC_BASE);
-
- return __raw_readl(base + reg);
-}
-
-static void adm8668_irq_cascade(void)
-{
- int irq;
- u32 intsrc;
-
- intsrc = intc_read_reg(IRQ_STATUS_REG) & IRQ_MASK;
- if (intsrc) {
- irq = fls(intsrc) - 1;
- do_IRQ(irq);
- } else
- spurious_interrupt();
-}
-
-/*
- * System irq dispatch
- */
-void plat_irq_dispatch(void)
-{
- unsigned int pending;
-
- pending = read_c0_cause() & read_c0_status() & ST0_IM;
-
- /* timer interrupt, that we renumbered */
- if (pending & STATUSF_IP7)
- do_IRQ(MIPS_CPU_IRQ_BASE + 7);
- else if (pending & STATUSF_IP2)
- adm8668_irq_cascade();
- else
- spurious_interrupt();
-}
-
-/*
- * enable 8668 irq
- */
-static void enable_adm8668_irq(struct irq_data *d)
-{
- intc_write_reg((1 << d->irq), IRQ_ENABLE_REG);
-}
-
-
-static void ack_adm8668_irq(struct irq_data *d)
-{
- intc_write_reg((1 << d->irq), IRQ_DISABLE_REG);
-}
-
-/*
- * system irq type
- */
-
-static struct irq_chip adm8668_irq_type = {
- .name = "adm8668",
- .irq_ack = ack_adm8668_irq,
- .irq_mask = ack_adm8668_irq,
- .irq_unmask = enable_adm8668_irq
-};
-
-/*
- * irq init
- */
-static void __init init_adm8668_irqs(void)
-{
- int i;
-
- /* disable all interrupts for the moment */
- intc_write_reg(IRQ_MASK, IRQ_DISABLE_REG);
-
- for (i = 0; i <= ADM8668_IRQ_MAX; i++)
- irq_set_chip_and_handler(i, &adm8668_irq_type,
- handle_level_irq);
-
- /* hw0 is where our interrupts are uh.. interrupted at. */
- set_c0_status(IE_IRQ0);
-}
-
-/*
- * system init
- */
-void __init arch_init_irq(void)
-{
- mips_cpu_irq_init();
- init_adm8668_irqs();
-}
+++ /dev/null
-/*
- * Infineon/ADMTek 8668 (WildPass) platform devices support
- *
- * Copyright (C) 2010 Scott Nicholas <neutronscott@scottn.us>
- * Copyright (C) 2012 Florian Fainelli <florian@openwrt.org>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/tulip.h>
-#include <linux/usb/ehci_pdriver.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-#include <linux/ioport.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/serial.h>
-
-#include <asm/reboot.h>
-#include <asm/time.h>
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <adm8668.h>
-
-#define ADM8868_UBOOT_ENV 0x20000
-#define ADM8868_UBOOT_WAN_MAC 0x5ac
-#define ADM8868_UBOOT_LAN_MAC 0x404
-
-static void adm8668_uart_set_mctrl(struct amba_device *dev,
- void __iomem *base,
- unsigned int mcrtl)
-{
-}
-
-static struct amba_pl010_data adm8668_uart0_data = {
- .set_mctrl = adm8668_uart_set_mctrl,
-};
-
-static struct amba_device adm8668_uart0_device = {
- .dev = {
- .init_name = "apb:uart0",
- .platform_data = &adm8668_uart0_data,
- },
- .res = {
- .start = ADM8668_UART0_BASE,
- .end = ADM8668_UART0_BASE + 0xF,
- .flags = IORESOURCE_MEM,
- },
- .irq = {
- ADM8668_UART0_IRQ,
- -1
- },
- .periphid = 0x0041010,
-};
-
-static struct resource eth0_resources[] = {
- {
- .start = ADM8668_LAN_BASE,
- .end = ADM8668_LAN_BASE + 256,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = ADM8668_LAN_IRQ,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct tulip_platform_data eth0_pdata = {
- .chip_id = ADM8668,
-};
-
-static struct platform_device adm8668_eth0_device = {
- .name = "tulip",
- .id = 0,
- .resource = eth0_resources,
- .num_resources = ARRAY_SIZE(eth0_resources),
- .dev.platform_data = ð0_pdata,
-};
-
-static struct resource eth1_resources[] = {
- {
- .start = ADM8668_WAN_BASE,
- .end = ADM8668_WAN_BASE + 256,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = ADM8668_WAN_IRQ,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct tulip_platform_data eth1_pdata = {
- .chip_id = ADM8668,
-};
-
-static struct platform_device adm8668_eth1_device = {
- .name = "tulip",
- .id = 1,
- .resource = eth1_resources,
- .num_resources = ARRAY_SIZE(eth1_resources),
- .dev.platform_data = ð1_pdata,
-};
-
-static const char *nor_probe_types[] = { "adm8668part", NULL };
-
-static struct physmap_flash_data nor_flash_data = {
- .width = 2,
- .part_probe_types = nor_probe_types,
-};
-
-static struct resource nor_resources[] = {
- {
- .start = ADM8668_SMEM1_BASE,
- .end = ADM8668_SMEM1_BASE + 0x800000 - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device adm8668_nor_device = {
- .name = "physmap-flash",
- .id = -1,
- .resource = nor_resources,
- .num_resources = ARRAY_SIZE(nor_resources),
- .dev.platform_data = &nor_flash_data,
-};
-
-static struct resource usb_resources[] = {
- {
- .start = ADM8668_USB_BASE,
- .end = ADM8668_USB_BASE + 0x1FFFFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = ADM8668_USB_IRQ,
- .end = ADM8668_USB_IRQ,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct usb_ehci_pdata usb_pdata = {
- .caps_offset = 0x100,
- .has_tt = 1,
- .port_power_off = 1,
-};
-
-static struct platform_device adm8668_usb_device = {
- .name = "ehci-platform",
- .id = -1,
- .resource = usb_resources,
- .num_resources = ARRAY_SIZE(usb_resources),
- .dev.platform_data = &usb_pdata,
-};
-
-static struct platform_device *adm8668_devs[] = {
- &adm8668_eth0_device,
- &adm8668_eth1_device,
- &adm8668_nor_device,
- &adm8668_usb_device,
-};
-
-static void adm8668_fetch_mac(int unit)
-{
- u8 *mac;
- u32 offset;
- struct tulip_platform_data *pdata;
-
- switch (unit) {
- case -1:
- case 0:
- offset = ADM8868_UBOOT_LAN_MAC;
- pdata = ð0_pdata;
- break;
- case 1:
- offset = ADM8868_UBOOT_WAN_MAC;
- pdata = ð1_pdata;
- break;
- default:
- pr_err("unsupported ethernet unit: %d\n", unit);
- return;
- }
-
- mac = (u8 *)(KSEG1ADDR(ADM8668_SMEM1_BASE) + ADM8868_UBOOT_ENV + offset);
-
- memcpy(pdata->mac, mac, sizeof(pdata->mac));
-}
-
-static void adm8668_ehci_workaround(void)
-{
- u32 chipid;
-
- chipid = ADM8668_CONFIG_REG(ADM8668_CR0);
- ADM8668_CONFIG_REG(ADM8668_CR66) = 0x0C1600D9;
-
- if (chipid == 0x86880001)
- return;
-
- ADM8668_CONFIG_REG(ADM8668_CR66) &= ~(3 << 20);
- ADM8668_CONFIG_REG(ADM8668_CR66) |= (1 << 20);
- pr_info("ADM8668: applied USB workaround\n");
-}
-
-
-int __devinit adm8668_devs_register(void)
-{
- int ret;
-
- ret = amba_device_register(&adm8668_uart0_device, &iomem_resource);
- if (ret)
- panic("failed to register AMBA UART");
-
- adm8668_fetch_mac(0);
- adm8668_fetch_mac(1);
- adm8668_ehci_workaround();
-
- return platform_add_devices(adm8668_devs, ARRAY_SIZE(adm8668_devs));
-}
-arch_initcall(adm8668_devs_register);
+++ /dev/null
-/*
- * Copyright (C) 2010 Scott Nicholas <neutronscott@scottn.us>
- *
- * based on work of rb532 prom.c
- * Copyright (C) 2003, Peter Sadik <peter.sadik@idt.com>
- * Copyright (C) 2005-2006, P.Christeas <p_christ@hol.gr>
- * Copyright (C) 2007, Gabor Juhos <juhosg@openwrt.org>
- * Felix Fietkau <nbd@openwrt.org>
- * Florian Fainelli <florian@openwrt.org>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/console.h>
-#include <linux/string.h>
-#include <linux/serial_core.h>
-#include <asm/bootinfo.h>
-#include <adm8668.h>
-#include "u-boot.h"
-
-register volatile struct global_data *gd asm ("k0");
-
-void __init prom_free_prom_memory(void)
-{
- /* No prom memory to free */
-}
-
-static inline int match_tag(char *arg, const char *tag)
-{
- return strncmp(arg, tag, strlen(tag)) == 0;
-}
-
-static inline unsigned long tag2ul(char *arg, const char *tag)
-{
- char *num;
-
- num = arg + strlen(tag);
- return simple_strtoul(num, 0, 10);
-}
-
-void __init prom_setup_cmdline(void)
-{
- char *cp;
- int prom_argc;
- char **prom_argv;
- int i;
-
- prom_argc = fw_arg0;
- prom_argv = (char **)KSEG0ADDR(fw_arg1);
-
- cp = &(arcs_cmdline[0]);
- for (i = 1; i < prom_argc; i++) {
- prom_argv[i] = (char *)KSEG0ADDR(prom_argv[i]);
-
- /* default bootargs has "console=/dev/ttyS0" yet console won't
- * show up at all if you include the '/dev/' nowadays ... */
- if (match_tag(prom_argv[i], "console=/dev/")) {
- char *ptr = prom_argv[i] + strlen("console=/dev/");
-
- strcpy(cp, "console=");
- cp += strlen("console=");
- strcpy(cp, ptr);
- cp += strlen(ptr);
- *cp++ = ' ';
- continue;
- }
- strcpy(cp, prom_argv[i]);
- cp += strlen(prom_argv[i]);
- *cp++ = ' ';
- }
- if (prom_argc > 1)
- --cp; /* trailing space */
-
- *cp = '\0';
-}
-
-void __init prom_init(void)
-{
- bd_t *bd = gd->bd;
- int memsize;
-
- memsize = bd->bi_memsize;
- printk("Board info:\n");
- printk(" RAM size: %d MB\n", (int)memsize/(1024*1024));
- printk(" NOR start: %#lx\n", bd->bi_flashstart);
- printk(" NOR size: %#lx\n", bd->bi_flashsize);
-
- prom_setup_cmdline();
- add_memory_region(0, memsize, BOOT_MEM_RAM);
-}
+++ /dev/null
-#include <linux/init.h>
-#include <linux/reboot.h>
-
-#include <asm/reboot.h>
-#include <adm8668.h>
-
-static void adm8668_restart(char *cmd)
-{
- int i;
-
- /* the real deal */
- for (i = 0; i < 1000; i++)
- ;
- ADM8668_CONFIG_REG(ADM8668_CR1) = 1;
-}
-
-void __init plat_mem_setup(void)
-{
- _machine_restart = adm8668_restart;
-}
-
-const char *get_system_type(void)
-{
- unsigned long chipid = ADM8668_CONFIG_REG(ADM8668_CR0);
- int product, revision;
- static char ret[32];
-
- product = chipid >> 16;
- revision = chipid & 0xffff;
-
- /* i getting fancy :\ */
- snprintf(ret, sizeof(ret), "ADM%xr%x", product, revision);
-
- return ret;
-}
-
+++ /dev/null
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/clk.h>
-
-#include <asm/time.h>
-#include <adm8668.h>
-
-void __init plat_time_init(void)
-{
- struct clk *sys_clk;
-
- adm8668_init_clocks();
-
- sys_clk = clk_get(NULL, "sys");
- if (IS_ERR(sys_clk))
- panic("unable to get system clock\n");
-
- mips_hpt_frequency = clk_get_rate(sys_clk) / 2;
-}
-
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _U_BOOT_H_
-#define _U_BOOT_H_ 1
-
-typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
- unsigned long bi_ip_addr; /* IP Address */
- unsigned char bi_enetaddr[6]; /* Ethernet adress */
- unsigned long bi_arch_number; /* unique id for this board */
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned long bi_memstart; /* start of DRAM memory */
- unsigned long bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
-} bd_t;
-
-struct global_data {
- bd_t *bd; /* board data... */
- unsigned long flags;
- unsigned long baudrate;
- unsigned long have_console; /* serial_init() was called */
- unsigned long ram_size; /* RAM size */
- unsigned long reloc_off; /* Relocation Offset */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
- void **jt; /* jump table */
-};
-
-#endif /* _U_BOOT_H_ */
+++ /dev/null
-/************************************************************************
- *
- * Copyright (c) 2005
- * Infineon Technologies AG
- * St. Martin Strasse 53; 81669 Muenchen; Germany
- *
- ************************************************************************/
-
-#ifndef __ADM8668_H__
-#define __ADM8668_H__
-
-/*======================= Physical Memory Map ============================*/
-#define ADM8668_SDRAM_BASE 0
-#define ADM8668_SMEM1_BASE 0x10000000
-#define ADM8668_MPMC_BASE 0x11000000
-#define ADM8668_USB_BASE 0x11200000
-#define ADM8668_CONFIG_BASE 0x11400000
-#define ADM8668_WAN_BASE 0x11600000
-#define ADM8668_WLAN_BASE 0x11800000
-#define ADM8668_LAN_BASE 0x11A00000
-#define ADM8668_INTC_BASE 0x1E000000
-#define ADM8668_TMR_BASE 0x1E200000
-#define ADM8668_UART0_BASE 0x1E400000
-#define ADM8668_SMEM0_BASE 0x1FC00000
-#define ADM8668_NAND_BASE 0x1FFFFF00
-
-#define ADM8668_PCICFG_BASE 0x12200000
-#define ADM8668_PCIDAT_BASE 0x12400000
-
-/* interrupt levels */
-#define ADM8668_SWI_IRQ 1
-#define ADM8668_COMMS_RX_IRQ 2
-#define ADM8668_COMMS_TX_IRQ 3
-#define ADM8668_TIMER0_IRQ 4
-#define ADM8668_TIMER1_IRQ 5
-#define ADM8668_UART0_IRQ 6
-#define ADM8668_LAN_IRQ 7
-#define ADM8668_WAN_IRQ 8
-#define ADM8668_WLAN_IRQ 9
-#define ADM8668_GPIO_IRQ 10
-#define ADM8668_IDE_IRQ 11
-#define ADM8668_PCI2_IRQ 12
-#define ADM8668_PCI1_IRQ 13
-#define ADM8668_PCI0_IRQ 14
-#define ADM8668_USB_IRQ 15
-#define ADM8668_IRQ_MAX ADM8668_USB_IRQ
-
-/* register access macros */
-#define ADM8668_CONFIG_REG(_reg) \
- (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_CONFIG_BASE + (_reg)))))
-
-/* lan registers */
-#define NETCSR6 0x30
-#define NETCSR7 0x38
-#define NETCSR37 0xF8
-
-/* known/used CPU configuration registers */
-#define ADM8668_CR0 0x00
-#define ADM8668_CR1 0x04
-#define ADM8668_CR3 0x0C
-#define ADM8668_CR66 0x108
-
-/** For GPIO control **/
-#define GPIO_REG 0x5C /* on WLAN */
-#define CRGPIO_REG 0x20 /* on CPU */
-
-void adm8668_init_clocks(void);
-
-#endif /* __ADM8668_H__ */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
-/* Size definitions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_16 0x00000010
-#define SZ_256 0x00000100
-#define SZ_512 0x00000200
-
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif
-
-/* END */
+++ /dev/null
-#ifndef __ADM8668_GPIO_H__
-#define __ADM8668_GPIO_H__
-
-#define gpio_to_irq(gpio) -1
-
-#define gpio_get_value __gpio_get_value
-#define gpio_set_value __gpio_set_value
-
-#define gpio_cansleep __gpio_cansleep
-
-#include <asm-generic/gpio.h>
-
-#endif
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 by Ralf Baechle
- */
-#ifndef __ASM_MACH_ADM8668_IRQ_H
-#define __ASM_MACH_ADM8668_IRQ_H
-
-#define NR_IRQS 32
-#define MIPS_CPU_IRQ_BASE 16
-
-#endif /* __ASM_MACH_ADM8668_IRQ_H */
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_ADM8668_WAR_H
-#define __ASM_MIPS_MACH_ADM8668_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
-#define R4600_V1_HIT_CACHEOP_WAR 0
-#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
-#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
-#define RM9000_CDEX_SMP_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
-#define R10000_LLSC_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
-
-#endif /* __ASM_MIPS_MACH_ADM8668_WAR_H */
+++ /dev/null
-/*
- * Copyright (C) 2010 Scott Nicholas <neutronscott@scottn.us>
- * Copyright (C) 2012 Florian Fainelli <florian@openwrt.org>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Note that this controller is identical to the ADM5120 one
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/types.h>
-#include <linux/spinlock.h>
-
-#include <asm/byteorder.h>
-#include <asm/pci.h>
-#include <adm8668.h>
-
-static DEFINE_SPINLOCK(pci_lock);
-
-#define PCI_ENABLE 0x80000000
-#define ADMPCI_IO_BASE 0x12600000
-#define ADMPCI_IO_SIZE 0x1fffff
-#define ADMPCI_MEM_BASE 0x16000000
-#define ADMPCI_MEM_SIZE 0x7ffffff
-
-static inline void write_cfgaddr(u32 addr)
-{
- __raw_writel((addr | PCI_ENABLE),
- (void __iomem *)KSEG1ADDR(ADM8668_PCICFG_BASE));
-}
-
-static inline void write_cfgdata(u32 data)
-{
- __raw_writel(data, (void __iomem *)KSEG1ADDR(ADM8668_PCIDAT_BASE));
-}
-
-static inline u32 read_cfgdata(void)
-{
- return __raw_readl((void __iomem *)KSEG1ADDR(ADM8668_PCIDAT_BASE));
-}
-
-static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
-{
- return ((bus->number & 0xff) << 16) | ((devfn & 0xff) << 8) |
- (where & 0xfc);
-}
-
-static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *val)
-{
- unsigned long flags;
- u32 data;
-
- spin_lock_irqsave(&pci_lock, flags);
- write_cfgaddr(mkaddr(bus, devfn, where));
- data = read_cfgdata();
-
- switch (size) {
- case 1:
- if (where & 1)
- data >>= 8;
- if (where & 2)
- data >>= 16;
- data &= 0xff;
- break;
- case 2:
- if (where & 2)
- data >>= 16;
- data &= 0xffff;
- break;
- }
-
- *val = data;
-
- spin_unlock_irqrestore(&pci_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
-{
- unsigned long flags;
- u32 data;
- int s;
-
- spin_lock_irqsave(&pci_lock, flags);
-
- write_cfgaddr(mkaddr(bus, devfn, where));
- data = read_cfgdata();
-
- switch (size) {
- case 1:
- s = ((where & 3) << 3);
- data &= ~(0xff << s);
- data |= ((val & 0xff) << s);
- break;
- case 2:
- s = ((where & 2) << 4);
- data &= ~(0xffff << s);
- data |= ((val & 0xffff) << s);
- break;
- case 4:
- data = val;
- break;
- }
-
- write_cfgdata(data);
-
- spin_unlock_irqrestore(&pci_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-struct pci_ops adm8668_pci_ops = {
- .read = pci_read_config,
- .write = pci_write_config
-};
-
-
-struct resource pciioport_resource = {
- .name = "adm8668_pci",
- .start = ADMPCI_IO_BASE,
- .end = ADMPCI_IO_BASE + ADMPCI_IO_SIZE,
- .flags = IORESOURCE_IO
-};
-
-struct resource pciiomem_resource = {
- .name = "adm8668_pci",
- .start = ADMPCI_MEM_BASE,
- .end = ADMPCI_MEM_BASE + ADMPCI_MEM_SIZE,
- .flags = IORESOURCE_MEM
-};
-
-struct pci_controller adm8668_pci_controller = {
- .pci_ops = &adm8668_pci_ops,
- .io_resource = &pciioport_resource,
- .mem_resource = &pciiomem_resource,
-};
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- switch (slot) {
- case 1:
- return 14;
- case 2:
- return 13;
- case 3:
- return 12;
- default:
- return dev->irq;
- }
-}
-
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
-
-static void adm8668_pci_fixup(struct pci_dev *dev)
-{
- if (dev->devfn != 0)
- return;
-
- pr_info("PCI: fixing up ADM8668 controller\n");
-
- /* setup COMMAND register */
- pci_write_config_word(dev, PCI_COMMAND,
- (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
-
- /* setup CACHE_LINE_SIZE register */
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
-
- /* setup BARS */
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
-}
-DECLARE_PCI_FIXUP_HEADER(0x1317, 0x8688, adm8668_pci_fixup);
-
-static int __init adm8668_pci_init(void)
-{
- void __iomem *io_map_base;
-
- ioport_resource.start = ADMPCI_IO_BASE;
- ioport_resource.end = ADMPCI_IO_BASE + ADMPCI_IO_SIZE;
-
- io_map_base = ioremap(ADMPCI_IO_BASE, ADMPCI_IO_SIZE);
- if (!io_map_base)
- printk("io_map_base didn't work.\n");
-
- adm8668_pci_controller.io_map_base = (unsigned long)io_map_base;
- register_pci_controller(&adm8668_pci_controller);
-
- return 0;
-}
-arch_initcall(adm8668_pci_init);
+++ /dev/null
-/*
- * Infineon/ADMTek ADM8668 (WildPass) partition parser support
- *
- * Copyright (C) 2010 Scott Nicholas <neutronscott@scottn.us>
- * Copyright (C) 2012 Florian Fainelli <florian@openwrt.org>
- *
- * original functions for finding root filesystem from Mike Baker
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- * Copyright 2004, Broadcom Corporation
- * All Rights Reserved.
- *
- * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
- * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
- * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/wait.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/vmalloc.h>
-#include <linux/slab.h>
-#include <linux/crc32.h>
-#include <linux/magic.h>
-
-#define PFX "adm8668-part: "
-
-/* first a little bit about the headers i need.. */
-
-/* just interested in part of the full struct */
-struct squashfs_super_block {
- __le32 s_magic;
- __le32 pad0[9]; /* it's not really padding */
- __le64 bytes_used;
-};
-
-#define IH_MAGIC 0x56190527 /* Image Magic Number */
-struct uboot_header {
- uint32_t ih_magic; /* Image Header Magic Number */
- uint32_t ih_hcrc; /* Image Header CRC Checksum */
- uint32_t ih_time; /* Image Creation Timestamp */
- uint32_t ih_size; /* Image Data Size */
- uint32_t ih_load; /* Data Load Address */
- uint32_t ih_ep; /* Entry Point Address */
- uint32_t ih_dcrc; /* Image Data CRC Checksum */
- uint8_t ih_os; /* Operating System */
- uint8_t ih_arch; /* CPU architecture */
- uint8_t ih_type; /* Image Type */
- uint8_t ih_comp; /* Compression Type */
- char ih_name[32]; /* image name */
-};
-
-/* in case i wanna change stuff later, and to clarify the math section... */
-#define PART_LINUX 0
-#define PART_ROOTFS 1
-#define PART_UBOOT_ENV 2
-#define NR_PARTS 3
-
-static int adm8668_parse_partitions(struct mtd_info *master,
- struct mtd_partition **pparts,
- struct mtd_part_parser_data *data)
-{
- int ret;
- struct uboot_header uhdr;
- int off, blocksize;
- size_t len, linux_len;
- struct squashfs_super_block shdr;
- struct erase_info erase_info;
- struct mtd_partition *adm8668_parts;
-
- memset(&erase_info, 0, sizeof(erase_info));
-
- blocksize = master->erasesize;
-
- if (blocksize < 0x10000)
- blocksize = 0x10000;
-
- adm8668_parts = kzalloc(sizeof(*adm8668_parts) * NR_PARTS, GFP_KERNEL);
- if (!adm8668_parts)
- return -ENOMEM;
-
- adm8668_parts[PART_LINUX].name = kstrdup("linux", GFP_KERNEL);
- adm8668_parts[PART_LINUX].offset = 0x40000;
- adm8668_parts[PART_LINUX].size = master->size - 0x40000;
- adm8668_parts[PART_ROOTFS].name = kstrdup("rootfs", GFP_KERNEL);
- adm8668_parts[PART_ROOTFS].offset = 0xe0000;
- adm8668_parts[PART_ROOTFS].size = 0x140000;
- adm8668_parts[PART_UBOOT_ENV].name = kstrdup("uboot_env", GFP_KERNEL);
- adm8668_parts[PART_UBOOT_ENV].offset = 0x20000;
- adm8668_parts[PART_UBOOT_ENV].size = 0x20000;
-
- /* now find squashfs */
- memset(&shdr, 0xe5, sizeof(shdr));
-
- for (off = 0x40000; off < master->size; off += blocksize) {
- /*
- * Read into buffer
- */
- if (mtd_read(master, off, sizeof(shdr), &len, (char *)&shdr) ||
- len != sizeof(shdr))
- continue;
-
- if (shdr.s_magic == SQUASHFS_MAGIC) {
- uint32_t fs_size = (uint32_t)shdr.bytes_used;
-
- pr_info(PFX "filesystem type: squashfs, size=%dkB\n",
- fs_size >> 10);
-
- /*
- * Update rootfs based on the superblock info, and
- * stretch to end of MTD. rootfs_split will split it
- */
- adm8668_parts[PART_ROOTFS].offset = off;
- adm8668_parts[PART_ROOTFS].size = master->size -
- adm8668_parts[PART_ROOTFS].offset;
-
- /*
- * kernel ends where rootfs starts
- * but we'll keep it full-length for upgrades
- */
- linux_len = adm8668_parts[PART_LINUX + 1].offset -
- adm8668_parts[PART_LINUX].offset;
-
- adm8668_parts[PART_LINUX].size = master->size -
- adm8668_parts[PART_LINUX].offset;
- goto found;
- }
- }
-
- pr_err(PFX "could't find root filesystem\n");
- return NR_PARTS;
-
-found:
- if (mtd_read(master, adm8668_parts[PART_LINUX].offset, sizeof(uhdr), &len, (char *)&uhdr) ||
- len != sizeof(uhdr)) {
- pr_err(PFX "failed to read u-boot header\n");
- return NR_PARTS;
- }
-
- if (uhdr.ih_magic != IH_MAGIC) {
- pr_info(PFX "invalid u-boot magic detected?!?!\n");
- return NR_PARTS;
- }
-
- if (be32_to_cpu(uhdr.ih_size) != (linux_len - sizeof(uhdr))) {
- u32 data;
- size_t data_len = 0;
- unsigned char *block;
- unsigned int offset;
-
- offset = adm8668_parts[PART_LINUX].offset +
- sizeof(struct uboot_header);
-
- pr_info(PFX "Updating U-boot image:\n");
- pr_info(PFX " old: [size: %8d crc32: 0x%08x]\n",
- be32_to_cpu(uhdr.ih_size), be32_to_cpu(uhdr.ih_dcrc));
-
- if (mtd_read(master, offset, sizeof(data), &data_len, (char *)&data)) {
- pr_err(PFX "failed to read data\n");
- goto out;
- }
-
- /* Update the data length & crc32 */
- uhdr.ih_size = cpu_to_be32(linux_len - sizeof(uhdr));
- uhdr.ih_dcrc = crc32_le(~0, (char *)&data, linux_len - sizeof(uhdr)) ^ (~0);
- uhdr.ih_dcrc = cpu_to_be32(uhdr.ih_dcrc);
-
- pr_info(PFX " new: [size: %8d crc32: 0x%08x]\n",
- be32_to_cpu(uhdr.ih_size), be32_to_cpu(uhdr.ih_dcrc));
-
- /* update header's crc... */
- uhdr.ih_hcrc = 0;
- uhdr.ih_hcrc = crc32_le(~0, (unsigned char *)&uhdr,
- sizeof(uhdr)) ^ (~0);
- uhdr.ih_hcrc = cpu_to_be32(uhdr.ih_hcrc);
-
- /* read first eraseblock from the image */
- block = vmalloc(master->erasesize);
- if (!block)
- return -ENOMEM;
-
- if (mtd_read(master, adm8668_parts[PART_LINUX].offset, master->erasesize, &len, block)
- || len != master->erasesize) {
- pr_err(PFX "error copying first eraseblock\n");
- return 0;
- }
-
- /* Write updated header to the flash */
- memcpy(block, &uhdr, sizeof(uhdr));
- if (master->unlock)
- master->unlock(master, off, master->erasesize);
-
- erase_info.mtd = master;
- erase_info.addr = (uint64_t)adm8668_parts[PART_LINUX].offset;
- erase_info.len = master->erasesize;
- ret = mtd_erase(master, &erase_info);
- if (!ret) {
- if (mtd_write(master, adm8668_parts[PART_LINUX].offset, master->erasesize,
- &len, block))
- pr_err(PFX "write failed");
- } else
- pr_err(PFX "erase failed");
-
- mtd_sync(master);
-out:
- if (block)
- vfree(block);
- pr_info(PFX "done\n");
- }
-
- *pparts = adm8668_parts;
-
- return NR_PARTS;
-}
-
-static struct mtd_part_parser adm8668_parser = {
- .owner = THIS_MODULE,
- .parse_fn = adm8668_parse_partitions,
- .name = "adm8668part",
-};
-
-static int __init adm8668_parser_init(void)
-{
- register_mtd_parser(&adm8668_parser);
-
- return 0;
-}
-
-static void __exit adm8668_parser_exit(void)
-{
- deregister_mtd_parser(&adm8668_parser);
-}
-
-module_init(adm8668_parser_init);
-module_exit(adm8668_parser_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Scott Nicholas <neutronscott@scottn.us>");
-MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
-MODULE_DESCRIPTION("MTD partition parser for ADM8668");
+++ /dev/null
-#
-# Copyright (C) 2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux
-UIMAGE:=$(IMG_PREFIX)-uImage
-
-define kernel_entry
--a 0x80002000 -e 0x80002000
-endef
-
-
-define CompressGzip
- gzip -9 -c $(1) > $(2)
-endef
-
-define MkImage
- mkimage -A mips -O linux -T kernel $(call kernel_entry) -C $(1) $(2) \
- -n "ADM8668 Linux Kernel(2.4.31)" \
- -d $(3) $(4)
-endef
-
-define Build/Clean
- $(MAKE) -C lzma-loader clean
-endef
-
-define Image/Prepare
- cat $(KDIR)/vmlinux | $(STAGING_DIR_HOST)/bin/lzma e -si -so -eos -lc1 -lp2 -pb2 > $(KDIR)/vmlinux.lzma
- $(MAKE) -C lzma-loader \
- KDIR="$(KDIR)" \
- clean compile
- rm -f $(KDIR)/fs_mark
- touch $(KDIR)/fs_mark
- $(call prepare_generic_squashfs,$(KDIR)/fs_mark)
-endef
-
-define Image/Build
- ./my-mkimage $(KDIR)/loader.bin $(KDIR)/root.squashfs \
- $(KDIR)/fs_mark $(BIN_DIR)/$(IMG_PREFIX)-$(1).bin
-endef
-
-define Image/BuildKernel
- cp $(KDIR)/vmlinux.elf $(VMLINUX).elf
- cp $(KDIR)/vmlinux $(VMLINUX).bin
- $(call CompressGzip,$(KDIR)/vmlinux,$(KDIR)/vmlinux.bin.gz)
- $(call MkImage,gzip,,$(KDIR)/vmlinux.bin.gz,$(BIN_DIR)/$(UIMAGE)-gzip.bin)
-ifeq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),y)
- cp $(KDIR)/vmlinux-initramfs.elf $(VMLINUX)-initramfs.elf
- cp $(KDIR)/vmlinux $(VMLINUX)-initramfs.bin
- $(call CompressGzip,$(KDIR)/vmlinux-initramfs,$(KDIR)/vmlinux-initramfs.bin.gz)
- $(call MkImage,gzip,,$(KDIR)/vmlinux-initramfs.bin.gz,$(BIN_DIR)/$(UIMAGE)-initramfs-gzip.bin)
-endif
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-#
-# Copyright (C) 2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-
-PKG_NAME := loader
-PKG_VERSION := 0.05
-
-PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)-$(PKG_VERSION)$(LOADER_TYPE)
-
-$(PKG_BUILD_DIR)/.prepared:
- mkdir $(PKG_BUILD_DIR)
- $(CP) ./src/* $(PKG_BUILD_DIR)/
- touch $@
-
-$(PKG_BUILD_DIR)/lzma.elf: $(PKG_BUILD_DIR)/.prepared $(PKG_BUILD_DIR)/vmlinux.lzma
- PATH="$(TARGET_PATH)" $(MAKE) -C $(PKG_BUILD_DIR) \
- CC="$(TARGET_CC)" CROSS_COMPILE="$(TARGET_CROSS)"
-
-$(PKG_BUILD_DIR)/vmlinux.lzma: $(KDIR)/vmlinux.lzma
- $(CP) $< $@
-
-$(KDIR)/loader$(LOADER_TYPE).elf: $(PKG_BUILD_DIR)/lzma.elf
- $(CP) $< $@
-
-$(KDIR)/loader$(LOADER_TYPE).bin: $(PKG_BUILD_DIR)/lzma.bin
- $(CP) $< $@
-
-download:
-prepare: $(PKG_BUILD_DIR)/.prepared
-compile: $(KDIR)/loader$(LOADER_TYPE).elf $(KDIR)/loader$(LOADER_TYPE).bin
-install:
-
-clean:
- rm -rf $(PKG_BUILD_DIR)
- rm -f $(KDIR)/loader.elf
- rm -f $(KDIR)/loader.bin
+++ /dev/null
-/*
- LzmaDecode.c
- LZMA Decoder (optimized for Speed version)
-
- LZMA SDK 4.22 Copyright (c) 1999-2005 Igor Pavlov (2005-06-10)
- http://www.7-zip.org/
-
- LZMA SDK is licensed under two licenses:
- 1) GNU Lesser General Public License (GNU LGPL)
- 2) Common Public License (CPL)
- It means that you can select one of these two licenses and
- follow rules of that license.
-
- SPECIAL EXCEPTION:
- Igor Pavlov, as the author of this Code, expressly permits you to
- statically or dynamically link your Code (or bind by name) to the
- interfaces of this file without subjecting your linked Code to the
- terms of the CPL or GNU LGPL. Any modifications or additions
- to this file, however, are subject to the LGPL or CPL terms.
-*/
-
-#include "LzmaDecode.h"
-
-#ifndef Byte
-#define Byte unsigned char
-#endif
-
-#define kNumTopBits 24
-#define kTopValue ((UInt32)1 << kNumTopBits)
-
-#define kNumBitModelTotalBits 11
-#define kBitModelTotal (1 << kNumBitModelTotalBits)
-#define kNumMoveBits 5
-
-#define RC_READ_BYTE (*Buffer++)
-
-#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \
- { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}
-
-#ifdef _LZMA_IN_CB
-
-#define RC_TEST { if (Buffer == BufferLim) \
- { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \
- BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}
-
-#define RC_INIT Buffer = BufferLim = 0; RC_INIT2
-
-#else
-
-#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }
-
-#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2
-
-#endif
-
-#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }
-
-#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)
-#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;
-#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;
-
-#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \
- { UpdateBit0(p); mi <<= 1; A0; } else \
- { UpdateBit1(p); mi = (mi + mi) + 1; A1; }
-
-#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)
-
-#define RangeDecoderBitTreeDecode(probs, numLevels, res) \
- { int i = numLevels; res = 1; \
- do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \
- res -= (1 << numLevels); }
-
-
-#define kNumPosBitsMax 4
-#define kNumPosStatesMax (1 << kNumPosBitsMax)
-
-#define kLenNumLowBits 3
-#define kLenNumLowSymbols (1 << kLenNumLowBits)
-#define kLenNumMidBits 3
-#define kLenNumMidSymbols (1 << kLenNumMidBits)
-#define kLenNumHighBits 8
-#define kLenNumHighSymbols (1 << kLenNumHighBits)
-
-#define LenChoice 0
-#define LenChoice2 (LenChoice + 1)
-#define LenLow (LenChoice2 + 1)
-#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
-#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
-#define kNumLenProbs (LenHigh + kLenNumHighSymbols)
-
-
-#define kNumStates 12
-#define kNumLitStates 7
-
-#define kStartPosModelIndex 4
-#define kEndPosModelIndex 14
-#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
-
-#define kNumPosSlotBits 6
-#define kNumLenToPosStates 4
-
-#define kNumAlignBits 4
-#define kAlignTableSize (1 << kNumAlignBits)
-
-#define kMatchMinLen 2
-
-#define IsMatch 0
-#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
-#define IsRepG0 (IsRep + kNumStates)
-#define IsRepG1 (IsRepG0 + kNumStates)
-#define IsRepG2 (IsRepG1 + kNumStates)
-#define IsRep0Long (IsRepG2 + kNumStates)
-#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
-#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
-#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
-#define LenCoder (Align + kAlignTableSize)
-#define RepLenCoder (LenCoder + kNumLenProbs)
-#define Literal (RepLenCoder + kNumLenProbs)
-
-#if Literal != LZMA_BASE_SIZE
-StopCompilingDueBUG
-#endif
-
-#if 0
-int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)
-{
- unsigned char prop0;
- if (size < LZMA_PROPERTIES_SIZE)
- return LZMA_RESULT_DATA_ERROR;
- prop0 = propsData[0];
- if (prop0 >= (9 * 5 * 5))
- return LZMA_RESULT_DATA_ERROR;
- {
- for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));
- for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);
- propsRes->lc = prop0;
- /*
- unsigned char remainder = (unsigned char)(prop0 / 9);
- propsRes->lc = prop0 % 9;
- propsRes->pb = remainder / 5;
- propsRes->lp = remainder % 5;
- */
- }
-
- #ifdef _LZMA_OUT_READ
- {
- int i;
- propsRes->DictionarySize = 0;
- for (i = 0; i < 4; i++)
- propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);
- if (propsRes->DictionarySize == 0)
- propsRes->DictionarySize = 1;
- }
- #endif
- return LZMA_RESULT_OK;
-}
-#endif
-
-#define kLzmaStreamWasFinishedId (-1)
-
-int LzmaDecode(CLzmaDecoderState *vs,
- #ifdef _LZMA_IN_CB
- ILzmaInCallback *InCallback,
- #else
- const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
- #endif
- unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)
-{
- CProb *p = vs->Probs;
- SizeT nowPos = 0;
- Byte previousByte = 0;
- UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;
- UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;
- int lc = vs->Properties.lc;
-
- #ifdef _LZMA_OUT_READ
-
- UInt32 Range = vs->Range;
- UInt32 Code = vs->Code;
- #ifdef _LZMA_IN_CB
- const Byte *Buffer = vs->Buffer;
- const Byte *BufferLim = vs->BufferLim;
- #else
- const Byte *Buffer = inStream;
- const Byte *BufferLim = inStream + inSize;
- #endif
- int state = vs->State;
- UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];
- int len = vs->RemainLen;
- UInt32 globalPos = vs->GlobalPos;
- UInt32 distanceLimit = vs->DistanceLimit;
-
- Byte *dictionary = vs->Dictionary;
- UInt32 dictionarySize = vs->Properties.DictionarySize;
- UInt32 dictionaryPos = vs->DictionaryPos;
-
- Byte tempDictionary[4];
-
- #ifndef _LZMA_IN_CB
- *inSizeProcessed = 0;
- #endif
- *outSizeProcessed = 0;
- if (len == kLzmaStreamWasFinishedId)
- return LZMA_RESULT_OK;
-
- if (dictionarySize == 0)
- {
- dictionary = tempDictionary;
- dictionarySize = 1;
- tempDictionary[0] = vs->TempDictionary[0];
- }
-
- if (len == kLzmaNeedInitId)
- {
- {
- UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
- UInt32 i;
- for (i = 0; i < numProbs; i++)
- p[i] = kBitModelTotal >> 1;
- rep0 = rep1 = rep2 = rep3 = 1;
- state = 0;
- globalPos = 0;
- distanceLimit = 0;
- dictionaryPos = 0;
- dictionary[dictionarySize - 1] = 0;
- #ifdef _LZMA_IN_CB
- RC_INIT;
- #else
- RC_INIT(inStream, inSize);
- #endif
- }
- len = 0;
- }
- while(len != 0 && nowPos < outSize)
- {
- UInt32 pos = dictionaryPos - rep0;
- if (pos >= dictionarySize)
- pos += dictionarySize;
- outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];
- if (++dictionaryPos == dictionarySize)
- dictionaryPos = 0;
- len--;
- }
- if (dictionaryPos == 0)
- previousByte = dictionary[dictionarySize - 1];
- else
- previousByte = dictionary[dictionaryPos - 1];
-
- #else /* if !_LZMA_OUT_READ */
-
- int state = 0;
- UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
- int len = 0;
- const Byte *Buffer;
- const Byte *BufferLim;
- UInt32 Range;
- UInt32 Code;
-
- #ifndef _LZMA_IN_CB
- *inSizeProcessed = 0;
- #endif
- *outSizeProcessed = 0;
-
- {
- UInt32 i;
- UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
- for (i = 0; i < numProbs; i++)
- p[i] = kBitModelTotal >> 1;
- }
-
- #ifdef _LZMA_IN_CB
- RC_INIT;
- #else
- RC_INIT(inStream, inSize);
- #endif
-
- #endif /* _LZMA_OUT_READ */
-
- while(nowPos < outSize)
- {
- CProb *prob;
- UInt32 bound;
- int posState = (int)(
- (nowPos
- #ifdef _LZMA_OUT_READ
- + globalPos
- #endif
- )
- & posStateMask);
-
- prob = p + IsMatch + (state << kNumPosBitsMax) + posState;
- IfBit0(prob)
- {
- int symbol = 1;
- UpdateBit0(prob)
- prob = p + Literal + (LZMA_LIT_SIZE *
- (((
- (nowPos
- #ifdef _LZMA_OUT_READ
- + globalPos
- #endif
- )
- & literalPosMask) << lc) + (previousByte >> (8 - lc))));
-
- if (state >= kNumLitStates)
- {
- int matchByte;
- #ifdef _LZMA_OUT_READ
- UInt32 pos = dictionaryPos - rep0;
- if (pos >= dictionarySize)
- pos += dictionarySize;
- matchByte = dictionary[pos];
- #else
- matchByte = outStream[nowPos - rep0];
- #endif
- do
- {
- int bit;
- CProb *probLit;
- matchByte <<= 1;
- bit = (matchByte & 0x100);
- probLit = prob + 0x100 + bit + symbol;
- RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)
- }
- while (symbol < 0x100);
- }
- while (symbol < 0x100)
- {
- CProb *probLit = prob + symbol;
- RC_GET_BIT(probLit, symbol)
- }
- previousByte = (Byte)symbol;
-
- outStream[nowPos++] = previousByte;
- #ifdef _LZMA_OUT_READ
- if (distanceLimit < dictionarySize)
- distanceLimit++;
-
- dictionary[dictionaryPos] = previousByte;
- if (++dictionaryPos == dictionarySize)
- dictionaryPos = 0;
- #endif
- if (state < 4) state = 0;
- else if (state < 10) state -= 3;
- else state -= 6;
- }
- else
- {
- UpdateBit1(prob);
- prob = p + IsRep + state;
- IfBit0(prob)
- {
- UpdateBit0(prob);
- rep3 = rep2;
- rep2 = rep1;
- rep1 = rep0;
- state = state < kNumLitStates ? 0 : 3;
- prob = p + LenCoder;
- }
- else
- {
- UpdateBit1(prob);
- prob = p + IsRepG0 + state;
- IfBit0(prob)
- {
- UpdateBit0(prob);
- prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;
- IfBit0(prob)
- {
- #ifdef _LZMA_OUT_READ
- UInt32 pos;
- #endif
- UpdateBit0(prob);
-
- #ifdef _LZMA_OUT_READ
- if (distanceLimit == 0)
- #else
- if (nowPos == 0)
- #endif
- return LZMA_RESULT_DATA_ERROR;
-
- state = state < kNumLitStates ? 9 : 11;
- #ifdef _LZMA_OUT_READ
- pos = dictionaryPos - rep0;
- if (pos >= dictionarySize)
- pos += dictionarySize;
- previousByte = dictionary[pos];
- dictionary[dictionaryPos] = previousByte;
- if (++dictionaryPos == dictionarySize)
- dictionaryPos = 0;
- #else
- previousByte = outStream[nowPos - rep0];
- #endif
- outStream[nowPos++] = previousByte;
- #ifdef _LZMA_OUT_READ
- if (distanceLimit < dictionarySize)
- distanceLimit++;
- #endif
-
- continue;
- }
- else
- {
- UpdateBit1(prob);
- }
- }
- else
- {
- UInt32 distance;
- UpdateBit1(prob);
- prob = p + IsRepG1 + state;
- IfBit0(prob)
- {
- UpdateBit0(prob);
- distance = rep1;
- }
- else
- {
- UpdateBit1(prob);
- prob = p + IsRepG2 + state;
- IfBit0(prob)
- {
- UpdateBit0(prob);
- distance = rep2;
- }
- else
- {
- UpdateBit1(prob);
- distance = rep3;
- rep3 = rep2;
- }
- rep2 = rep1;
- }
- rep1 = rep0;
- rep0 = distance;
- }
- state = state < kNumLitStates ? 8 : 11;
- prob = p + RepLenCoder;
- }
- {
- int numBits, offset;
- CProb *probLen = prob + LenChoice;
- IfBit0(probLen)
- {
- UpdateBit0(probLen);
- probLen = prob + LenLow + (posState << kLenNumLowBits);
- offset = 0;
- numBits = kLenNumLowBits;
- }
- else
- {
- UpdateBit1(probLen);
- probLen = prob + LenChoice2;
- IfBit0(probLen)
- {
- UpdateBit0(probLen);
- probLen = prob + LenMid + (posState << kLenNumMidBits);
- offset = kLenNumLowSymbols;
- numBits = kLenNumMidBits;
- }
- else
- {
- UpdateBit1(probLen);
- probLen = prob + LenHigh;
- offset = kLenNumLowSymbols + kLenNumMidSymbols;
- numBits = kLenNumHighBits;
- }
- }
- RangeDecoderBitTreeDecode(probLen, numBits, len);
- len += offset;
- }
-
- if (state < 4)
- {
- int posSlot;
- state += kNumLitStates;
- prob = p + PosSlot +
- ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<
- kNumPosSlotBits);
- RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);
- if (posSlot >= kStartPosModelIndex)
- {
- int numDirectBits = ((posSlot >> 1) - 1);
- rep0 = (2 | ((UInt32)posSlot & 1));
- if (posSlot < kEndPosModelIndex)
- {
- rep0 <<= numDirectBits;
- prob = p + SpecPos + rep0 - posSlot - 1;
- }
- else
- {
- numDirectBits -= kNumAlignBits;
- do
- {
- RC_NORMALIZE
- Range >>= 1;
- rep0 <<= 1;
- if (Code >= Range)
- {
- Code -= Range;
- rep0 |= 1;
- }
- }
- while (--numDirectBits != 0);
- prob = p + Align;
- rep0 <<= kNumAlignBits;
- numDirectBits = kNumAlignBits;
- }
- {
- int i = 1;
- int mi = 1;
- do
- {
- CProb *prob3 = prob + mi;
- RC_GET_BIT2(prob3, mi, ; , rep0 |= i);
- i <<= 1;
- }
- while(--numDirectBits != 0);
- }
- }
- else
- rep0 = posSlot;
- if (++rep0 == (UInt32)(0))
- {
- /* it's for stream version */
- len = kLzmaStreamWasFinishedId;
- break;
- }
- }
-
- len += kMatchMinLen;
- #ifdef _LZMA_OUT_READ
- if (rep0 > distanceLimit)
- #else
- if (rep0 > nowPos)
- #endif
- return LZMA_RESULT_DATA_ERROR;
-
- #ifdef _LZMA_OUT_READ
- if (dictionarySize - distanceLimit > (UInt32)len)
- distanceLimit += len;
- else
- distanceLimit = dictionarySize;
- #endif
-
- do
- {
- #ifdef _LZMA_OUT_READ
- UInt32 pos = dictionaryPos - rep0;
- if (pos >= dictionarySize)
- pos += dictionarySize;
- previousByte = dictionary[pos];
- dictionary[dictionaryPos] = previousByte;
- if (++dictionaryPos == dictionarySize)
- dictionaryPos = 0;
- #else
- previousByte = outStream[nowPos - rep0];
- #endif
- len--;
- outStream[nowPos++] = previousByte;
- }
- while(len != 0 && nowPos < outSize);
- }
- }
- RC_NORMALIZE;
-
- #ifdef _LZMA_OUT_READ
- vs->Range = Range;
- vs->Code = Code;
- vs->DictionaryPos = dictionaryPos;
- vs->GlobalPos = globalPos + (UInt32)nowPos;
- vs->DistanceLimit = distanceLimit;
- vs->Reps[0] = rep0;
- vs->Reps[1] = rep1;
- vs->Reps[2] = rep2;
- vs->Reps[3] = rep3;
- vs->State = state;
- vs->RemainLen = len;
- vs->TempDictionary[0] = tempDictionary[0];
- #endif
-
- #ifdef _LZMA_IN_CB
- vs->Buffer = Buffer;
- vs->BufferLim = BufferLim;
- #else
- *inSizeProcessed = (SizeT)(Buffer - inStream);
- #endif
- *outSizeProcessed = nowPos;
- return LZMA_RESULT_OK;
-}
+++ /dev/null
-/*
- LzmaDecode.h
- LZMA Decoder interface
-
- LZMA SDK 4.21 Copyright (c) 1999-2005 Igor Pavlov (2005-06-08)
- http://www.7-zip.org/
-
- LZMA SDK is licensed under two licenses:
- 1) GNU Lesser General Public License (GNU LGPL)
- 2) Common Public License (CPL)
- It means that you can select one of these two licenses and
- follow rules of that license.
-
- SPECIAL EXCEPTION:
- Igor Pavlov, as the author of this code, expressly permits you to
- statically or dynamically link your code (or bind by name) to the
- interfaces of this file without subjecting your linked code to the
- terms of the CPL or GNU LGPL. Any modifications or additions
- to this file, however, are subject to the LGPL or CPL terms.
-*/
-
-#ifndef __LZMADECODE_H
-#define __LZMADECODE_H
-
-/* #define _LZMA_IN_CB */
-/* Use callback for input data */
-
-/* #define _LZMA_OUT_READ */
-/* Use read function for output data */
-
-/* #define _LZMA_PROB32 */
-/* It can increase speed on some 32-bit CPUs,
- but memory usage will be doubled in that case */
-
-/* #define _LZMA_LOC_OPT */
-/* Enable local speed optimizations inside code */
-
-/* #define _LZMA_SYSTEM_SIZE_T */
-/* Use system's size_t. You can use it to enable 64-bit sizes supporting*/
-
-#ifndef UInt32
-#ifdef _LZMA_UINT32_IS_ULONG
-#define UInt32 unsigned long
-#else
-#define UInt32 unsigned int
-#endif
-#endif
-
-#ifndef SizeT
-#ifdef _LZMA_SYSTEM_SIZE_T
-#include <stddef.h>
-#define SizeT size_t
-#else
-#define SizeT UInt32
-#endif
-#endif
-
-#ifdef _LZMA_PROB32
-#define CProb UInt32
-#else
-#define CProb unsigned short
-#endif
-
-#define LZMA_RESULT_OK 0
-#define LZMA_RESULT_DATA_ERROR 1
-
-#ifdef _LZMA_IN_CB
-typedef struct _ILzmaInCallback
-{
- int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);
-} ILzmaInCallback;
-#endif
-
-#define LZMA_BASE_SIZE 1846
-#define LZMA_LIT_SIZE 768
-
-#define LZMA_PROPERTIES_SIZE 5
-
-typedef struct _CLzmaProperties
-{
- int lc;
- int lp;
- int pb;
- #ifdef _LZMA_OUT_READ
- UInt32 DictionarySize;
- #endif
-}CLzmaProperties;
-
-int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);
-
-#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))
-
-#define kLzmaNeedInitId (-2)
-
-typedef struct _CLzmaDecoderState
-{
- CLzmaProperties Properties;
- CProb *Probs;
-
- #ifdef _LZMA_IN_CB
- const unsigned char *Buffer;
- const unsigned char *BufferLim;
- #endif
-
- #ifdef _LZMA_OUT_READ
- unsigned char *Dictionary;
- UInt32 Range;
- UInt32 Code;
- UInt32 DictionaryPos;
- UInt32 GlobalPos;
- UInt32 DistanceLimit;
- UInt32 Reps[4];
- int State;
- int RemainLen;
- unsigned char TempDictionary[4];
- #endif
-} CLzmaDecoderState;
-
-#ifdef _LZMA_OUT_READ
-#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }
-#endif
-
-int LzmaDecode(CLzmaDecoderState *vs,
- #ifdef _LZMA_IN_CB
- ILzmaInCallback *inCallback,
- #else
- const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
- #endif
- unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);
-
-#endif
+++ /dev/null
-#
-# Copyright (C) 2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-RAMSTART = 0x80000000
-RAMSIZE = 0x00800000 # 8MB
-LOADADDR = 0x80400000 # RAM start + 4M
-KERNEL_ENTRY = 0x80002000
-
-CROSS_COMPILE = mipsel-openwrt-linux-
-
-OBJCOPY:= $(CROSS_COMPILE)objcopy -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
-CFLAGS := -I./include -fno-builtin -Os -G 0 -ffunction-sections -mno-abicalls -fno-pic -mabi=32 -march=mips32 -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap -Wall -DRAMSTART=${RAMSTART} -DRAMSIZE=${RAMSIZE} -DKERNEL_ENTRY=${KERNEL_ENTRY}
-
-.c.o:
- $(CC) $(CFLAGS) -c $< -o $*.o
-
-CC = $(CROSS_COMPILE)gcc
-LD = $(CROSS_COMPILE)ld
-OBJDUMP = $(CROSS_COMPILE)objdump
-
-O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
-
-# Drop some uninteresting sections in the kernel.
-# This is only relevant for ELF kernels but doesn't hurt a.out
-drop-sections = .reginfo .mdebug .comment
-strip-flags = $(addprefix --remove-section=,$(drop-sections))
-
-all : lzma.elf lzma.bin
-
-lzma.lds: lzma.lds.in
- sed -e 's,@LOADADDR@,$(LOADADDR),g' $< >$@
-
-kernel.o: vmlinux.lzma lzma.lds
- $(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $<
-
-lzma.bin: lzma.elf
- $(OBJCOPY) $< $@
-
-lzma.elf: decompress.o stubs.o LzmaDecode.o kernel.o lzma.lds
- $(LD) -T lzma.lds -o $@ $^
-#-s ^
-
-clean:
- rm -f *.o lzma.elf lzma.bin *.tmp *.lds
+++ /dev/null
-/*
- * LZMA compressed kernel decompressor for bcm947xx boards
- *
- * Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- *
- * Please note, this was code based on the bunzip2 decompressor code
- * by Manuel Novoa III (mjn3@codepoet.org), although the only thing left
- * is an idea and part of original vendor code
- *
- *
- * 12-Mar-2005 Mineharu Takahara <mtakahar@yahoo.com>
- * pass actual output size to decoder (stream mode
- * compressed input is not a requirement anymore)
- *
- * 24-Apr-2005 Oleg I. Vdovikin
- * reordered functions using lds script, removed forward decl
- *
- * ??-Nov-2005 Mike Baker
- * reorder the script as an lzma wrapper; do not depend on flash access
- */
-
-#include "LzmaDecode.h"
-#include <exports.h>
-
-#define KSEG0ADDR(addr) (0x80000000|addr)
-
-register volatile gd_t *gd asm ("k0");
-unsigned char *data;
-
-static __inline__ unsigned char get_byte()
-{
- unsigned char *buffer;
-
- buffer = data;
- data++;
-
- return *buffer;
-}
-
-/* This puts lzma workspace 128k below RAM end.
- * That should be enough for both lzma and stack
- */
-static char *buffer = (char *)(RAMSTART + RAMSIZE - 0x00020000);
-extern char _binary_vmlinux_lzma_start[];
-extern char _binary_vmlinux_lzma_end[];
-extern char lzma_start[];
-extern char lzma_end[];
-
-/* should be the first function */
-void entry(unsigned int arg0, unsigned int arg1,
- unsigned int arg2, unsigned int arg3)
-{
- unsigned int i; /* temp value */
- unsigned int isize; /* compressed size */
- unsigned int osize; /* uncompressed size */
- int argc = arg0;
- char **argv = (char **)arg1;
- char **envp = (char **)arg2;
-
- CLzmaDecoderState vs;
-
- data = (unsigned char *)_binary_vmlinux_lzma_start;
- isize = _binary_vmlinux_lzma_end - _binary_vmlinux_lzma_start + 1;
-
- puts("\nLZMA kernel loader\n");
-
- printf("lzma data @ %#x - %#x\n", _binary_vmlinux_lzma_start, _binary_vmlinux_lzma_end);
- printf("load addr @ %#x\n\n", KERNEL_ENTRY);
- printf("jump table @ %#x\n", gd->jt[3]);
-
- /* lzma args */
- i = get_byte();
- vs.Properties.lc = i % 9, i = i / 9;
- vs.Properties.lp = i % 5, vs.Properties.pb = i / 5;
-
- vs.Probs = (CProb *)buffer;
-
- /* skip rest of the LZMA coder property */
- data += 4;
-
- /* read the lower half of uncompressed size in the header */
- osize = ((unsigned int)get_byte()) +
- ((unsigned int)get_byte() << 8) +
- ((unsigned int)get_byte() << 16) +
- ((unsigned int)get_byte() << 24);
-
- /* skip rest of the header (upper half of uncompressed size) */
- data += 4;
-
- /* decompress kernel */
- puts("\nDecompressing kernel...");
- if ((i = LzmaDecode(&vs,
- (unsigned char*)data, isize, &isize,
- (unsigned char*)KERNEL_ENTRY, osize, &osize)) == LZMA_RESULT_OK)
- {
- puts("success!\n");
-
- /* Jump to load address */
-// ((void (*)(int a0, int a1, int a2, int a3))KERNEL_ENTRY)(0,0,0,0);
- ((void (*)(int a0, int a1, int a2, int a3))KERNEL_ENTRY)(arg0, arg1, arg2, arg3);
- }
- puts("failure!\n");
-}
+++ /dev/null
-EXPORT_FUNC(get_version)
-EXPORT_FUNC(getc)
-EXPORT_FUNC(tstc)
-EXPORT_FUNC(putc)
-EXPORT_FUNC(puts)
-EXPORT_FUNC(printf)
-EXPORT_FUNC(install_hdlr)
-EXPORT_FUNC(free_hdlr)
-EXPORT_FUNC(malloc)
-EXPORT_FUNC(free)
-EXPORT_FUNC(udelay)
-EXPORT_FUNC(get_timer)
-EXPORT_FUNC(vprintf)
-EXPORT_FUNC(do_reset)
-#if (CONFIG_COMMANDS & CFG_CMD_I2C)
-EXPORT_FUNC(i2c_write)
-EXPORT_FUNC(i2c_read)
-#endif /* CFG_CMD_I2C */
+++ /dev/null
-/*
- * (C) Copyright 2002-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-
-#include <asm/regdef.h>
-
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- *
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
- */
-
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
- unsigned long baudrate;
- unsigned long have_console; /* serial_init() was called */
- unsigned long ram_size; /* RAM size */
- unsigned long reloc_off; /* Relocation Offset */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
- void **jt; /* jump table */
-} gd_t;
-
-/*
- * Global Data Flags
- */
-#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
-#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
-#define GD_FLG_SILENT 0x00004 /* Silent mode */
-
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0")
-
-#endif /* __ASM_GBL_DATA_H */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _U_BOOT_H_
-#define _U_BOOT_H_ 1
-
-typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
- unsigned long bi_ip_addr; /* IP Address */
- unsigned char bi_enetaddr[6]; /* Ethernet adress */
- unsigned long bi_arch_number; /* unique id for this board */
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned long bi_memstart; /* start of DRAM memory */
- unsigned long bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
-} bd_t;
-#define bi_env_data bi_env->data
-#define bi_env_crc bi_env->crc
-
-#endif /* _U_BOOT_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __COMMON_H_
-#define __COMMON_H_ 1
-
-#undef _LINUX_CONFIG_H
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
-typedef unsigned char uchar;
-typedef volatile unsigned long vu_long;
-typedef volatile unsigned short vu_short;
-typedef volatile unsigned char vu_char;
-
-#include <inttypes.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <asm/ptrace.h>
-#include <stdarg.h>
-#include <image.h>
-
-typedef void (interrupt_handler_t)(void *);
-
-#include <asm/u-boot.h> /* boot information for Linux kernel */
-#include <asm/global_data.h> /* global data used for startup functions */
-
-
-#endif /* __COMMON_H_ */
+++ /dev/null
-#ifndef __EXPORTS_H__
-#define __EXPORTS_H__
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-#ifndef __ASSEMBLY__
-
-#include <common.h>
-
-/* These are declarations of exported functions available in C code */
-unsigned long get_version(void);
-int getc(void);
-int tstc(void);
-void putc(const char);
-void puts(const char*);
-void printf(const char* fmt, ...);
-void install_hdlr(int, interrupt_handler_t*, void*);
-void free_hdlr(int);
-void *malloc(size_t);
-void free(void*);
-void udelay(unsigned long);
-unsigned long get_timer(unsigned long);
-void vprintf(const char *, va_list);
-void do_reset (void);
-
-void app_startup(char **);
-
-#endif /* ifndef __ASSEMBLY__ */
-
-enum {
-#define EXPORT_FUNC(x) XF_ ## x ,
-#include <_exports.h>
-#undef EXPORT_FUNC
-
- XF_MAX
-};
-
-#define XF_VERSION 2
-
-#endif /* __EXPORTS_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __IMAGE_H__
-#define __IMAGE_H__
-
-/*
- * Operating System Codes
- */
-#define IH_OS_INVALID 0 /* Invalid OS */
-#define IH_OS_OPENBSD 1 /* OpenBSD */
-#define IH_OS_NETBSD 2 /* NetBSD */
-#define IH_OS_FREEBSD 3 /* FreeBSD */
-#define IH_OS_4_4BSD 4 /* 4.4BSD */
-#define IH_OS_LINUX 5 /* Linux */
-#define IH_OS_SVR4 6 /* SVR4 */
-#define IH_OS_ESIX 7 /* Esix */
-#define IH_OS_SOLARIS 8 /* Solaris */
-#define IH_OS_IRIX 9 /* Irix */
-#define IH_OS_SCO 10 /* SCO */
-#define IH_OS_DELL 11 /* Dell */
-#define IH_OS_NCR 12 /* NCR */
-#define IH_OS_LYNXOS 13 /* LynxOS */
-#define IH_OS_VXWORKS 14 /* VxWorks */
-#define IH_OS_PSOS 15 /* pSOS */
-#define IH_OS_QNX 16 /* QNX */
-#define IH_OS_U_BOOT 17 /* Firmware */
-#define IH_OS_RTEMS 18 /* RTEMS */
-#define IH_OS_ARTOS 19 /* ARTOS */
-#define IH_OS_UNITY 20 /* Unity OS */
-
-/*
- * CPU Architecture Codes (supported by Linux)
- */
-#define IH_CPU_INVALID 0 /* Invalid CPU */
-#define IH_CPU_ALPHA 1 /* Alpha */
-#define IH_CPU_ARM 2 /* ARM */
-#define IH_CPU_I386 3 /* Intel x86 */
-#define IH_CPU_IA64 4 /* IA64 */
-#define IH_CPU_MIPS 5 /* MIPS */
-#define IH_CPU_MIPS64 6 /* MIPS 64 Bit */
-#define IH_CPU_PPC 7 /* PowerPC */
-#define IH_CPU_S390 8 /* IBM S390 */
-#define IH_CPU_SH 9 /* SuperH */
-#define IH_CPU_SPARC 10 /* Sparc */
-#define IH_CPU_SPARC64 11 /* Sparc 64 Bit */
-#define IH_CPU_M68K 12 /* M68K */
-#define IH_CPU_NIOS 13 /* Nios-32 */
-#define IH_CPU_MICROBLAZE 14 /* MicroBlaze */
-#define IH_CPU_NIOS2 15 /* Nios-II */
-
-/*
- * Image Types
- *
- * "Standalone Programs" are directly runnable in the environment
- * provided by U-Boot; it is expected that (if they behave
- * well) you can continue to work in U-Boot after return from
- * the Standalone Program.
- * "OS Kernel Images" are usually images of some Embedded OS which
- * will take over control completely. Usually these programs
- * will install their own set of exception handlers, device
- * drivers, set up the MMU, etc. - this means, that you cannot
- * expect to re-enter U-Boot except by resetting the CPU.
- * "RAMDisk Images" are more or less just data blocks, and their
- * parameters (address, size) are passed to an OS kernel that is
- * being started.
- * "Multi-File Images" contain several images, typically an OS
- * (Linux) kernel image and one or more data images like
- * RAMDisks. This construct is useful for instance when you want
- * to boot over the network using BOOTP etc., where the boot
- * server provides just a single image file, but you want to get
- * for instance an OS kernel and a RAMDisk image.
- *
- * "Multi-File Images" start with a list of image sizes, each
- * image size (in bytes) specified by an "uint32_t" in network
- * byte order. This list is terminated by an "(uint32_t)0".
- * Immediately after the terminating 0 follow the images, one by
- * one, all aligned on "uint32_t" boundaries (size rounded up to
- * a multiple of 4 bytes - except for the last file).
- *
- * "Firmware Images" are binary images containing firmware (like
- * U-Boot or FPGA images) which usually will be programmed to
- * flash memory.
- *
- * "Script files" are command sequences that will be executed by
- * U-Boot's command interpreter; this feature is especially
- * useful when you configure U-Boot to use a real shell (hush)
- * as command interpreter (=> Shell Scripts).
- */
-
-#define IH_TYPE_INVALID 0 /* Invalid Image */
-#define IH_TYPE_STANDALONE 1 /* Standalone Program */
-#define IH_TYPE_KERNEL 2 /* OS Kernel Image */
-#define IH_TYPE_RAMDISK 3 /* RAMDisk Image */
-#define IH_TYPE_MULTI 4 /* Multi-File Image */
-#define IH_TYPE_FIRMWARE 5 /* Firmware Image */
-#define IH_TYPE_SCRIPT 6 /* Script file */
-#define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */
-
-/*
- * Compression Types
- */
-#define IH_COMP_NONE 0 /* No Compression Used */
-#define IH_COMP_GZIP 1 /* gzip Compression Used */
-#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */
-
-#define IH_MAGIC 0x27051956 /* Image Magic Number */
-#define IH_NMLEN 32 /* Image Name Length */
-
-#define IH_NAMEMAGIC 0x86680001 /* Name Magic Number */
-#define IH_SIZEMAX 5800000 /* Max image size */
-/*
- * all data in network byte order (aka natural aka bigendian)
- */
-
-typedef struct image_header {
- uint32_t ih_magic; /* Image Header Magic Number */
- uint32_t ih_hcrc; /* Image Header CRC Checksum */
- uint32_t ih_time; /* Image Creation Timestamp */
- uint32_t ih_size; /* Image Data Size */
- uint32_t ih_load; /* Data Load Address */
- uint32_t ih_ep; /* Entry Point Address */
- uint32_t ih_dcrc; /* Image Data CRC Checksum */
- uint8_t ih_os; /* Operating System */
- uint8_t ih_arch; /* CPU architecture */
- uint8_t ih_type; /* Image Type */
- uint8_t ih_comp; /* Compression Type */
-#ifdef NEW_IMAGE_HEADER
- uint32_t ih_namemagic; /* image name CRC */
- uint8_t ih_name[IH_NMLEN-4]; /* image name */
-#else
- uint8_t ih_name[IH_NMLEN]; /* Image Name */
-#endif
-} image_header_t;
-
-
-#endif /* __IMAGE_H__ */
+++ /dev/null
-OUTPUT_ARCH(mips)
-ENTRY(entry)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = @LOADADDR@;
- .text :
- {
- _ftext = . ;
- *(.text.entry)
- *(.text)
- lzma_start = .;
- kernel.o
- lzma_end = .;
- *(.rodata)
- } =0
-
- .reginfo : { *(.reginfo) }
-
- .bss :
- {
- *(.bss)
- }
-}
+++ /dev/null
-#include <exports.h>
-
-#ifndef GCC_VERSION
-#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__)
-#endif /* GCC_VERSION */
-
-/*
- * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-
- * clobbered register that is also used to set gp ($26). Note that the
- * jr instruction also executes the instruction immediately following
- * it; however, GCC/mips generates an additional `nop' after each asm
- * statement
- */
-#define EXPORT_FUNC(x) \
- asm volatile ( \
-" .globl " #x "\n" \
-#x ":\n" \
-" lw $25, %0($26)\n" \
-" lw $25, %1($25)\n" \
-" jr $25\n" \
- : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "t9");
-
-/* This function is necessary to prevent the compiler from
- * generating prologue/epilogue, preparing stack frame etc.
- * The stub functions are special, they do not use the stack
- * frame passed to them, but pass it intact to the actual
- * implementation. On the other hand, asm() statements with
- * arguments can be used only inside the functions (gcc limitation)
- */
-#if GCC_VERSION < 3004
-static
-#endif /* GCC_VERSION */
-void __attribute__((unused)) dummy(void)
-{
-#include <_exports.h>
-}
-
-#if 0
-extern unsigned long __bss_start, _end;
-
-void app_startup(char **argv)
-{
- unsigned long * cp = &__bss_start;
-
- /* Zero out BSS */
- while (cp < &_end) {
- *cp++ = 0;
- }
-}
-#endif
-
-#undef EXPORT_FUNC
+++ /dev/null
-#!/bin/sh
-# my-mkimage
-# This will pad given files to 64k boundaries to make a single u-boot image.
-# we have to be fancy because u-boot mkimage is going to add 64 byte header, ...
-# and i only know basic arithmetic.. ;)
-#
-# Copyright (C) 2010 Scott Nicholas <neutronscott@scottn.us>
-[ $# -lt 2 ] && {
- echo usage: $0 loader.bin [rootfs.squashfs [fs_mark [...]]] output.bin
-}
-
-OLDSIZE=$(stat -c%s $1)
-NEWSIZE=$(((OLDSIZE / 65536 + 1) * 65536 - 64))
-
-dd if=$1 of=vmlinuz.tmp bs=$NEWSIZE conv=sync >/dev/null 2>&1
-shift
-appends=$(($# - 1))
-echo
-while [ $appends -gt 0 ]; do
- dd if=$1 of=temp bs=64k conv=sync >/dev/null 2>&1
- printf "### '%s' starts at 0x%x\n" "`basename $1`" "$((NEWSIZE+64))"
- cat temp >>vmlinuz.tmp
- shift
- appends=$((appends-1))
- NEWSIZE=$(stat -c%s vmlinuz.tmp)
-done
-echo
-../../../../staging_dir/host/bin/mkimage -A mips -O linux -T kernel \
--C none -a 0x80400000 -e 0x80400000 -n "ADM8668 Linux Kernel(2.4.31)" \
--d vmlinuz.tmp $1
-
-rm temp vmlinuz.tmp
+++ /dev/null
---- a/arch/mips/Kbuild.platforms
-+++ b/arch/mips/Kbuild.platforms
-@@ -30,6 +30,7 @@ platforms += sni
- platforms += txx9
- platforms += vr41xx
- platforms += wrppmc
-+platforms += adm8668
-
- # include the platform specific files
- include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -105,6 +105,26 @@ config BCM47XX
- help
- Support for BCM47XX based boards
-
-+config ADM8668
-+ bool "WildPass ADM8668"
-+ select SYS_HAS_CPU_MIPS32_R1
-+ select BOOT_RAW
-+ select NO_EXCEPT_FILL
-+ select IRQ_CPU
-+ select CEVT_R4K
-+ select CSRC_R4K
-+ select HW_HAS_PCI
-+ select PCI
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select DMA_NONCOHERENT
-+ select SWAP_IO_SPACE
-+ select SYS_HAS_EARLY_PRINTK
-+ select ARCH_REQUIRE_GPIOLIB
-+ help
-+ ADM8668 board support by neutronscott
-+ Scott Nicholas <neutronscott@scottn.us>
-+
- config BCM63XX
- bool "Broadcom BCM63XX based boards"
- select CEVT_R4K
-@@ -813,6 +833,7 @@ config NLM_XLP_BOARD
-
- endchoice
-
-+source "arch/mips/adm8668/Kconfig"
- source "arch/mips/alchemy/Kconfig"
- source "arch/mips/ath79/Kconfig"
- source "arch/mips/bcm47xx/Kconfig"
+++ /dev/null
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -57,6 +57,7 @@ obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
- obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
- obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
- obj-$(CONFIG_CPU_XLR) += pci-xlr.o
-+obj-$(CONFIG_ADM8668) += pci-adm8668.o
-
- ifdef CONFIG_PCI_MSI
- obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
---- a/include/linux/pci_ids.h
-+++ b/include/linux/pci_ids.h
-@@ -1803,6 +1803,9 @@
- #define PCI_VENDOR_ID_ESDGMBH 0x12fe
- #define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
-
-+#define PCI_VENDOR_ADMTEK 0x1317
-+#define PCI_DEVICE_ID_ADM8668 0x8688
-+
- #define PCI_VENDOR_ID_SIIG 0x131f
- #define PCI_SUBVENDOR_ID_SIIG 0x131f
- #define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000
+++ /dev/null
---- a/drivers/mtd/maps/Kconfig
-+++ b/drivers/mtd/maps/Kconfig
-@@ -96,6 +96,12 @@ config MSP_FLASH_MAP_LIMIT
- default "0x02000000"
- depends on MSP_FLASH_MAP_LIMIT_32M
-
-+config MTD_ADM8668_PARTS
-+ tristate "ADM8668 partition parser"
-+ depends on ADM8668
-+ help
-+ Partition parser for the Infineon/ADMTek ADM8668 (WildPass).
-+
- config MTD_SUN_UFLASH
- tristate "Sun Microsystems userflash support"
- depends on SPARC && MTD_CFI && PCI
---- a/drivers/mtd/maps/Makefile
-+++ b/drivers/mtd/maps/Makefile
-@@ -7,6 +7,7 @@ obj-$(CONFIG_MTD) += map_funcs.o
- endif
-
- # Chip mappings
-+obj-$(CONFIG_MTD_ADM8668_PARTS) += adm8668.o
- obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
- obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
- obj-$(CONFIG_MTD_DC21285) += dc21285.o
+++ /dev/null
---- a/drivers/net/ethernet/dec/tulip/tulip_core.c
-+++ b/drivers/net/ethernet/dec/tulip/tulip_core.c
-@@ -206,7 +206,7 @@ struct tulip_chip_table tulip_tbl[] = {
-
- };
-
--
-+#ifdef CONFIG_TULIP_PCI
- static DEFINE_PCI_DEVICE_TABLE(tulip_pci_tbl) = {
- { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
- { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
-@@ -250,7 +250,7 @@ static DEFINE_PCI_DEVICE_TABLE(tulip_pci
- { } /* terminate list */
- };
- MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
--
-+#endif
-
- /* A full-duplex map for media types. */
- const char tulip_media_cap[32] =
-@@ -268,11 +268,14 @@ static void tulip_down(struct net_device
- static struct net_device_stats *tulip_get_stats(struct net_device *dev);
- static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
- static void set_rx_mode(struct net_device *dev);
-+#ifdef CONFIG_TULIP_PCI
- static void tulip_set_wolopts(struct pci_dev *pdev, u32 wolopts);
-+#endif
- #ifdef CONFIG_NET_POLL_CONTROLLER
- static void poll_tulip(struct net_device *dev);
- #endif
-
-+#ifdef CONFIG_TULIP_PCI
- static void tulip_set_power_state (struct tulip_private *tp,
- int sleep, int snooze)
- {
-@@ -289,7 +292,7 @@ static void tulip_set_power_state (struc
- }
-
- }
--
-+#endif
-
- static void tulip_up(struct net_device *dev)
- {
-@@ -303,6 +306,7 @@ static void tulip_up(struct net_device *
- napi_enable(&tp->napi);
- #endif
-
-+#ifdef CONFIG_TULIP_PCI
- /* Wake the chip from sleep/snooze mode. */
- tulip_set_power_state (tp, 0, 0);
-
-@@ -310,6 +314,7 @@ static void tulip_up(struct net_device *
- pci_enable_wake(tp->pdev, PCI_D3hot, 0);
- pci_enable_wake(tp->pdev, PCI_D3cold, 0);
- tulip_set_wolopts(tp->pdev, 0);
-+#endif
-
- /* On some chip revs we must set the MII/SYM port before the reset!? */
- if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
-@@ -317,14 +322,18 @@ static void tulip_up(struct net_device *
-
- /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
- iowrite32(0x00000001, ioaddr + CSR0);
-+#ifdef CONFIG_TULIP_PCI
- pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */
-+#endif
- udelay(100);
-
- /* Deassert reset.
- Wait the specified 50 PCI cycles after a reset by initializing
- Tx and Rx queues and the address filter list. */
- iowrite32(tp->csr0, ioaddr + CSR0);
-+#ifdef CONFIG_TULIP_PCI
- pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */
-+#endif
- udelay(100);
-
- if (tulip_debug > 1)
-@@ -362,9 +371,11 @@ static void tulip_up(struct net_device *
- *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
- *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
-
-+#ifdef CONFIG_TULIP_PCI
- mapping = pci_map_single(tp->pdev, tp->setup_frame,
- sizeof(tp->setup_frame),
- PCI_DMA_TODEVICE);
-+#endif
- tp->tx_buffers[tp->cur_tx].skb = NULL;
- tp->tx_buffers[tp->cur_tx].mapping = mapping;
-
-@@ -642,8 +653,10 @@ static void tulip_init_ring(struct net_d
- tp->rx_buffers[i].skb = skb;
- if (skb == NULL)
- break;
-+#ifdef CONFIG_TULIP_PCI
- mapping = pci_map_single(tp->pdev, skb->data,
- PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
-+#endif
- tp->rx_buffers[i].mapping = mapping;
- skb->dev = dev; /* Mark as being used by this device. */
- tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
-@@ -677,8 +690,10 @@ tulip_start_xmit(struct sk_buff *skb, st
- entry = tp->cur_tx % TX_RING_SIZE;
-
- tp->tx_buffers[entry].skb = skb;
-+#ifdef CONFIG_TULIP_PCI
- mapping = pci_map_single(tp->pdev, skb->data,
- skb->len, PCI_DMA_TODEVICE);
-+#endif
- tp->tx_buffers[entry].mapping = mapping;
- tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
-
-@@ -729,16 +744,19 @@ static void tulip_clean_tx_ring(struct t
- if (tp->tx_buffers[entry].skb == NULL) {
- /* test because dummy frames not mapped */
- if (tp->tx_buffers[entry].mapping)
-+#ifdef CONFIG_TULIP_PCI
- pci_unmap_single(tp->pdev,
- tp->tx_buffers[entry].mapping,
- sizeof(tp->setup_frame),
- PCI_DMA_TODEVICE);
-+#endif
- continue;
- }
--
-+#ifdef CONFIG_TULIP_PCI
- pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
- tp->tx_buffers[entry].skb->len,
- PCI_DMA_TODEVICE);
-+#endif
-
- /* Free the original skb. */
- dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
-@@ -789,7 +807,9 @@ static void tulip_down (struct net_devic
- dev->if_port = tp->saved_if_port;
-
- /* Leave the driver in snooze, not sleep, mode. */
-+#ifdef CONFIG_TULIP_PCI
- tulip_set_power_state (tp, 0, 1);
-+#endif
- }
-
- static void tulip_free_ring (struct net_device *dev)
-@@ -810,8 +830,10 @@ static void tulip_free_ring (struct net_
- /* An invalid address. */
- tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
- if (skb) {
-+#ifdef CONFIG_TULIP_PCI
- pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
- PCI_DMA_FROMDEVICE);
-+#endif
- dev_kfree_skb (skb);
- }
- }
-@@ -820,8 +842,10 @@ static void tulip_free_ring (struct net_
- struct sk_buff *skb = tp->tx_buffers[i].skb;
-
- if (skb != NULL) {
-+#ifdef CONFIG_TULIP_PCI
- pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
- skb->len, PCI_DMA_TODEVICE);
-+#endif
- dev_kfree_skb (skb);
- }
- tp->tx_buffers[i].skb = NULL;
-@@ -873,7 +897,9 @@ static void tulip_get_drvinfo(struct net
- struct tulip_private *np = netdev_priv(dev);
- strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
- strlcpy(info->version, DRV_VERSION, sizeof(info->version));
-+#ifdef CONFIG_TULIP_PCI
- strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
-+#endif
- }
-
-
-@@ -886,7 +912,9 @@ static int tulip_ethtool_set_wol(struct
- return -EOPNOTSUPP;
-
- tp->wolinfo.wolopts = wolinfo->wolopts;
-+#ifdef CONFIG_TULIP_PCI
- device_set_wakeup_enable(&tp->pdev->dev, tp->wolinfo.wolopts);
-+#endif
- return 0;
- }
-
-@@ -1167,9 +1195,11 @@ static void set_rx_mode(struct net_devic
-
- tp->tx_buffers[entry].skb = NULL;
- tp->tx_buffers[entry].mapping =
-+#ifdef CONFIG_TULIP_PCI
- pci_map_single(tp->pdev, tp->setup_frame,
- sizeof(tp->setup_frame),
- PCI_DMA_TODEVICE);
-+#endif
- /* Put the setup frame on the Tx list. */
- if (entry == TX_RING_SIZE-1)
- tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
-@@ -1267,19 +1297,22 @@ out:
- netdev_dbg(dev, "MWI config cacheline=%d, csr0=%08x\n",
- cache, csr0);
- }
--#endif
-
- /*
- * Chips that have the MRM/reserved bit quirk and the burst quirk. That
- * is the DM910X and the on chip ULi devices
- */
-+#endif
-
-+#ifdef CONFIG_TULIP_PCI
- static int tulip_uli_dm_quirk(struct pci_dev *pdev)
- {
- if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
- return 1;
- return 0;
- }
-+#endif
-+
-
- static const struct net_device_ops tulip_netdev_ops = {
- .ndo_open = tulip_open,
-@@ -1297,6 +1330,7 @@ static const struct net_device_ops tulip
- #endif
- };
-
-+#ifdef CONFIG_TULIP_PCI
- DEFINE_PCI_DEVICE_TABLE(early_486_chipsets) = {
- { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
- { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
-@@ -1814,6 +1848,7 @@ err_out_free_netdev:
- }
-
-
-+#ifdef CONFIG_TULIP_PCI
- /* set the registers according to the given wolopts */
- static void tulip_set_wolopts (struct pci_dev *pdev, u32 wolopts)
- {
-@@ -1842,6 +1877,7 @@ static void tulip_set_wolopts (struct pc
- iowrite32(tmp, ioaddr + CSR13);
- }
- }
-+#endif
-
- #ifdef CONFIG_PM
-
-@@ -1953,6 +1989,7 @@ static void __devexit tulip_remove_one (
-
- /* pci_power_off (pdev, -1); */
- }
-+#endif /* CONFIG_TULIP_PCI */
-
- #ifdef CONFIG_NET_POLL_CONTROLLER
- /*
-@@ -1971,7 +2008,8 @@ static void poll_tulip (struct net_devic
- }
- #endif
-
--static struct pci_driver tulip_driver = {
-+#ifdef CONFIG_TULIP_PCI
-+static struct pci_driver tulip_pci_driver = {
- .name = DRV_NAME,
- .id_table = tulip_pci_tbl,
- .probe = tulip_init_one,
-@@ -1981,10 +2019,12 @@ static struct pci_driver tulip_driver =
- .resume = tulip_resume,
- #endif /* CONFIG_PM */
- };
-+#endif
-
-
- static int __init tulip_init (void)
- {
-+ int ret = 0;
- #ifdef MODULE
- pr_info("%s", version);
- #endif
-@@ -1994,13 +2034,18 @@ static int __init tulip_init (void)
- tulip_max_interrupt_work = max_interrupt_work;
-
- /* probe for and init boards */
-- return pci_register_driver(&tulip_driver);
-+#ifdef CONFIG_TULIP_PCI
-+ ret = pci_register_driver(&tulip_pci_driver);
-+#endif
-+ return ret;
- }
-
-
- static void __exit tulip_cleanup (void)
- {
-- pci_unregister_driver (&tulip_driver);
-+#ifdef CONFIG_TULIP_PCI
-+ pci_unregister_driver (&tulip_pci_driver);
-+#endif
- }
-
-
---- a/drivers/net/ethernet/dec/tulip/interrupt.c
-+++ b/drivers/net/ethernet/dec/tulip/interrupt.c
-@@ -72,9 +72,10 @@ int tulip_refill_rx(struct net_device *d
- skb = tp->rx_buffers[entry].skb = dev_alloc_skb(PKT_BUF_SZ);
- if (skb == NULL)
- break;
--
-+#ifdef CONFIG_TULIP_PCI
- mapping = pci_map_single(tp->pdev, skb->data, PKT_BUF_SZ,
- PCI_DMA_FROMDEVICE);
-+#endif
- tp->rx_buffers[entry].mapping = mapping;
-
- skb->dev = dev; /* Mark as being used by this device. */
-@@ -204,9 +205,11 @@ int tulip_poll(struct napi_struct *napi,
- if (pkt_len < tulip_rx_copybreak &&
- (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
- skb_reserve(skb, 2); /* 16 byte align the IP header */
-+#ifdef CONFIG_TULIP_PCI
- pci_dma_sync_single_for_cpu(tp->pdev,
- tp->rx_buffers[entry].mapping,
- pkt_len, PCI_DMA_FROMDEVICE);
-+#endif
- #if ! defined(__alpha__)
- skb_copy_to_linear_data(skb, tp->rx_buffers[entry].skb->data,
- pkt_len);
-@@ -216,9 +219,11 @@ int tulip_poll(struct napi_struct *napi,
- tp->rx_buffers[entry].skb->data,
- pkt_len);
- #endif
-+#ifdef CONFIG_TULIP_PCI
- pci_dma_sync_single_for_device(tp->pdev,
- tp->rx_buffers[entry].mapping,
- pkt_len, PCI_DMA_FROMDEVICE);
-+#endif
- } else { /* Pass up the skb already on the Rx ring. */
- char *temp = skb_put(skb = tp->rx_buffers[entry].skb,
- pkt_len);
-@@ -233,9 +238,10 @@ int tulip_poll(struct napi_struct *napi,
- skb->head, temp);
- }
- #endif
--
-+#ifdef CONFIG_TULIP_PCI
- pci_unmap_single(tp->pdev, tp->rx_buffers[entry].mapping,
- PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
-+#endif
-
- tp->rx_buffers[entry].skb = NULL;
- tp->rx_buffers[entry].mapping = 0;
-@@ -591,10 +597,12 @@ irqreturn_t tulip_interrupt(int irq, voi
- if (tp->tx_buffers[entry].skb == NULL) {
- /* test because dummy frames not mapped */
- if (tp->tx_buffers[entry].mapping)
-+#ifdef CONFIG_TULIP_PCI
- pci_unmap_single(tp->pdev,
- tp->tx_buffers[entry].mapping,
- sizeof(tp->setup_frame),
- PCI_DMA_TODEVICE);
-+#endif
- continue;
- }
-
-@@ -622,10 +630,11 @@ irqreturn_t tulip_interrupt(int irq, voi
- dev->stats.collisions += (status >> 3) & 15;
- dev->stats.tx_packets++;
- }
--
-+#ifdef CONFIG_TULIP_PCI
- pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
- tp->tx_buffers[entry].skb->len,
- PCI_DMA_TODEVICE);
-+#endif
-
- /* Free the original skb. */
- dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
---- a/drivers/net/ethernet/dec/tulip/Kconfig
-+++ b/drivers/net/ethernet/dec/tulip/Kconfig
-@@ -40,8 +40,12 @@ config DE2104X_DSL
- Default is 0, and range is 0 to 31.
-
- config TULIP
-+ tristate
-+
-+config TULIP_PCI
- tristate "DECchip Tulip (dc2114x) PCI support"
- depends on PCI
-+ select TULIP
- select CRC32
- ---help---
- This driver is developed for the SMC EtherPower series Ethernet
-@@ -58,7 +62,7 @@ config TULIP
-
- config TULIP_MWI
- bool "New bus configuration (EXPERIMENTAL)"
-- depends on TULIP && EXPERIMENTAL
-+ depends on TULIP_PCI && EXPERIMENTAL
- ---help---
- This configures your Tulip card specifically for the card and
- system cache line size type you are using.
-@@ -69,7 +73,7 @@ config TULIP_MWI
-
- config TULIP_MMIO
- bool "Use PCI shared mem for NIC registers"
-- depends on TULIP
-+ depends on TULIP_PCI
- ---help---
- Use PCI shared memory for the NIC registers, rather than going through
- the Tulip's PIO (programmed I/O ports). Faster, but could produce
+++ /dev/null
---- a/drivers/net/ethernet/dec/tulip/Kconfig
-+++ b/drivers/net/ethernet/dec/tulip/Kconfig
-@@ -60,6 +60,14 @@ config TULIP_PCI
- To compile this driver as a module, choose M here. The module will
- be called tulip.
-
-+config TULIP_PLATFORM
-+ tristate "DECchip Tulip (dc2114x) Platform support"
-+ depends on HAS_IOMEM
-+ select TULIP
-+ select CRC32
-+ ---help---
-+ This driver is for the platform variant.
-+
- config TULIP_MWI
- bool "New bus configuration (EXPERIMENTAL)"
- depends on TULIP_PCI && EXPERIMENTAL
---- a/drivers/net/ethernet/dec/tulip/tulip_core.c
-+++ b/drivers/net/ethernet/dec/tulip/tulip_core.c
-@@ -27,6 +27,8 @@
- #include <linux/init.h>
- #include <linux/interrupt.h>
- #include <linux/etherdevice.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/tulip.h>
- #include <linux/delay.h>
- #include <linux/mii.h>
- #include <linux/crc32.h>
-@@ -204,6 +206,9 @@ struct tulip_chip_table tulip_tbl[] = {
- { "Conexant LANfinity", 256, 0x0001ebef,
- HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
-
-+ { "Infineon ADM8668", 256, 0x0001a451,
-+ MC_HASH_ONLY | COMET_MAC_ADDR, tulip_timer, tulip_media_task, },
-+
- };
-
- #ifdef CONFIG_TULIP_PCI
-@@ -395,6 +400,7 @@ static void tulip_up(struct net_device *
- i = 0;
- if (tp->mtable == NULL)
- goto media_picked;
-+
- if (dev->if_port) {
- int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
- (dev->if_port == 12 ? 0 : dev->if_port);
-@@ -488,6 +494,10 @@ media_picked:
- iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
- dev->if_port = tp->mii_cnt ? 11 : 0;
- tp->csr6 = 0x00040000;
-+ } else if (tp->chip_id == ADM8668) {
-+ /* Enable automatic Tx underrun recovery. */
-+ iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
-+ tp->csr6 = 0x00040000;
- } else if (tp->chip_id == AX88140) {
- tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
- } else
-@@ -657,6 +667,10 @@ static void tulip_init_ring(struct net_d
- mapping = pci_map_single(tp->pdev, skb->data,
- PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
- #endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ mapping = dma_map_single(&tp->pldev->dev, skb->data,
-+ PKT_BUF_SZ, DMA_FROM_DEVICE);
-+#endif
- tp->rx_buffers[i].mapping = mapping;
- skb->dev = dev; /* Mark as being used by this device. */
- tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
-@@ -694,6 +708,11 @@ tulip_start_xmit(struct sk_buff *skb, st
- mapping = pci_map_single(tp->pdev, skb->data,
- skb->len, PCI_DMA_TODEVICE);
- #endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ mapping = dma_map_single(&tp->pldev->dev, skb->data,
-+ skb->len,
-+ DMA_TO_DEVICE);
-+#endif
- tp->tx_buffers[entry].mapping = mapping;
- tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
-
-@@ -757,6 +776,11 @@ static void tulip_clean_tx_ring(struct t
- tp->tx_buffers[entry].skb->len,
- PCI_DMA_TODEVICE);
- #endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ dma_unmap_single(&tp->pldev->dev, tp->tx_buffers[entry].mapping,
-+ tp->tx_buffers[entry].skb->len,
-+ DMA_TO_DEVICE);
-+#endif
-
- /* Free the original skb. */
- dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
-@@ -834,6 +858,10 @@ static void tulip_free_ring (struct net_
- pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
- PCI_DMA_FROMDEVICE);
- #endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ dma_unmap_single(&tp->pldev->dev, mapping, PKT_BUF_SZ,
-+ DMA_FROM_DEVICE);
-+#endif
- dev_kfree_skb (skb);
- }
- }
-@@ -846,6 +874,10 @@ static void tulip_free_ring (struct net_
- pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
- skb->len, PCI_DMA_TODEVICE);
- #endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ dma_unmap_single(&tp->pldev->dev, tp->tx_buffers[i].mapping,
-+ skb->len, DMA_TO_DEVICE);
-+#endif
- dev_kfree_skb (skb);
- }
- tp->tx_buffers[i].skb = NULL;
-@@ -900,6 +932,9 @@ static void tulip_get_drvinfo(struct net
- #ifdef CONFIG_TULIP_PCI
- strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
- #endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
-+#endif
- }
-
-
-@@ -915,6 +950,9 @@ static int tulip_ethtool_set_wol(struct
- #ifdef CONFIG_TULIP_PCI
- device_set_wakeup_enable(&tp->pdev->dev, tp->wolinfo.wolopts);
- #endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ device_set_wakeup_enable(&tp->pldev->dev, tp->wolinfo.wolopts);
-+#endif
- return 0;
- }
-
-@@ -1193,9 +1231,9 @@ static void set_rx_mode(struct net_devic
-
- }
-
-+#ifdef CONFIG_TULIP_PCI
- tp->tx_buffers[entry].skb = NULL;
- tp->tx_buffers[entry].mapping =
--#ifdef CONFIG_TULIP_PCI
- pci_map_single(tp->pdev, tp->setup_frame,
- sizeof(tp->setup_frame),
- PCI_DMA_TODEVICE);
-@@ -1219,6 +1257,9 @@ static void set_rx_mode(struct net_devic
- spin_unlock_irqrestore(&tp->lock, flags);
- }
-
-+ if (tp->chip_id == ADM8668)
-+ csr6 |= (1 << 9); /* force 100Mbps full duplex */
-+
- iowrite32(csr6, ioaddr + CSR6);
- }
-
-@@ -1991,6 +2032,124 @@ static void __devexit tulip_remove_one (
- }
- #endif /* CONFIG_TULIP_PCI */
-
-+#ifdef CONFIG_TULIP_PLATFORM
-+static int __devinit tulip_probe(struct platform_device *pdev)
-+{
-+ struct tulip_private *tp;
-+ struct tulip_platform_data *pdata;
-+ struct net_device *dev;
-+ struct resource *res;
-+ void __iomem *ioaddr;
-+ int irq;
-+
-+ if (pdev->id < 0 || pdev->id >= MAX_UNITS)
-+ return -EINVAL;
-+
-+ if (!(res = platform_get_resource(pdev, IORESOURCE_IRQ, 0)))
-+ return -ENODEV;
-+ irq = res->start;
-+ if (!(res = platform_get_resource(pdev, IORESOURCE_MEM, 0)))
-+ return -ENODEV;
-+ if (!(ioaddr = ioremap(res->start, res->end - res->start)))
-+ return -ENODEV;
-+
-+ pdata = pdev->dev.platform_data;
-+ if (!pdata)
-+ return -ENODEV;
-+
-+ if (!(dev = alloc_etherdev(sizeof (*tp))))
-+ return -ENOMEM;
-+
-+ /* setup net dev */
-+ dev->base_addr = (unsigned long)res->start;
-+ dev->irq = irq;
-+ SET_NETDEV_DEV(dev, &pdev->dev);
-+
-+ /* tulip private struct */
-+ tp = netdev_priv(dev);
-+ tp->dev = dev;
-+ tp->base_addr = ioaddr;
-+ tp->csr0 = 0;
-+ tp->pldev = pdev;
-+ tp->rx_ring = dma_alloc_coherent(&pdev->dev,
-+ sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
-+ sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
-+ &tp->rx_ring_dma, GFP_KERNEL);
-+ if (!tp->rx_ring)
-+ return -ENODEV;
-+ tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
-+ tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
-+
-+ tp->chip_id = pdata->chip_id;
-+ tp->flags = tulip_tbl[tp->chip_id].flags;
-+
-+ spin_lock_init(&tp->lock);
-+ spin_lock_init(&tp->mii_lock);
-+
-+ init_timer(&tp->timer);
-+ tp->timer.data = (unsigned long)dev;
-+ tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
-+
-+ INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
-+
-+ /* Stop the chip's Tx and Rx processes. */
-+ tulip_stop_rxtx(tp);
-+
-+ /* Clear the missed-packet counter. */
-+ ioread32(ioaddr + CSR8);
-+
-+ if (!is_valid_ether_addr(pdata->mac)) {
-+ dev_info(&pdev->dev, "generating random ethernet MAC\n");
-+ random_ether_addr(dev->dev_addr);
-+ } else
-+ memcpy(dev->dev_addr, pdata->mac, ETH_ALEN);
-+
-+ /* The Tulip-specific entries in the device structure. */
-+ dev->netdev_ops = &tulip_netdev_ops;
-+ dev->watchdog_timeo = TX_TIMEOUT;
-+ netif_napi_add(dev, &tp->napi, tulip_poll, 16);
-+ SET_ETHTOOL_OPS(dev, &ops);
-+
-+ if (register_netdev(dev))
-+ goto err_out_free_ring;
-+
-+ dev_info(&dev->dev,
-+ "tulip_platform (%s) at MMIO %#lx %pM, IRQ %d\n",
-+ tulip_tbl[tp->chip_id].chip_name,
-+ (unsigned long)dev->base_addr, dev->dev_addr, irq);
-+
-+ platform_set_drvdata(pdev, dev);
-+ return 0;
-+
-+err_out_free_ring:
-+ dma_free_coherent(&pdev->dev,
-+ sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
-+ sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
-+ tp->rx_ring, tp->rx_ring_dma);
-+ return -ENODEV;
-+}
-+
-+static int __devexit tulip_remove(struct platform_device *pdev)
-+{
-+ struct net_device *dev = platform_get_drvdata (pdev);
-+ struct tulip_private *tp;
-+
-+ if (!dev)
-+ return -ENODEV;
-+
-+ tp = netdev_priv(dev);
-+ unregister_netdev(dev);
-+ dma_free_coherent(&pdev->dev,
-+ sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
-+ sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
-+ tp->rx_ring, tp->rx_ring_dma);
-+ iounmap(tp->base_addr);
-+ free_netdev(dev);
-+ platform_set_drvdata(pdev, NULL);
-+ return 0;
-+}
-+#endif
-+
- #ifdef CONFIG_NET_POLL_CONTROLLER
- /*
- * Polling 'interrupt' - used by things like netconsole to send skbs
-@@ -2021,6 +2180,17 @@ static struct pci_driver tulip_pci_drive
- };
- #endif
-
-+#ifdef CONFIG_TULIP_PLATFORM
-+static struct platform_driver tulip_platform_driver = {
-+ .probe = tulip_probe,
-+ .remove = __devexit_p(tulip_remove),
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = DRV_NAME,
-+ },
-+};
-+#endif
-+
-
- static int __init tulip_init (void)
- {
-@@ -2037,6 +2207,9 @@ static int __init tulip_init (void)
- #ifdef CONFIG_TULIP_PCI
- ret = pci_register_driver(&tulip_pci_driver);
- #endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ ret = platform_driver_register(&tulip_platform_driver);
-+#endif
- return ret;
- }
-
-@@ -2046,6 +2219,9 @@ static void __exit tulip_cleanup (void)
- #ifdef CONFIG_TULIP_PCI
- pci_unregister_driver (&tulip_pci_driver);
- #endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ platform_driver_unregister (&tulip_platform_driver);
-+#endif
- }
-
-
---- a/drivers/net/ethernet/dec/tulip/tulip.h
-+++ b/drivers/net/ethernet/dec/tulip/tulip.h
-@@ -21,6 +21,8 @@
- #include <linux/timer.h>
- #include <linux/delay.h>
- #include <linux/pci.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/tulip.h>
- #include <asm/io.h>
- #include <asm/irq.h>
- #include <asm/unaligned.h>
-@@ -69,28 +71,6 @@ enum tbl_flag {
- };
-
-
--/* chip types. careful! order is VERY IMPORTANT here, as these
-- * are used throughout the driver as indices into arrays */
--/* Note 21142 == 21143. */
--enum chips {
-- DC21040 = 0,
-- DC21041 = 1,
-- DC21140 = 2,
-- DC21142 = 3, DC21143 = 3,
-- LC82C168,
-- MX98713,
-- MX98715,
-- MX98725,
-- AX88140,
-- PNIC2,
-- COMET,
-- COMPEX9881,
-- I21145,
-- DM910X,
-- CONEXANT,
--};
--
--
- enum MediaIs {
- MediaIsFD = 1,
- MediaAlwaysFD = 2,
-@@ -446,7 +426,12 @@ struct tulip_private {
- struct mediatable *mtable;
- int cur_index; /* Current media index. */
- int saved_if_port;
-+#ifdef CONFIG_TULIP_PCI
- struct pci_dev *pdev;
-+#endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ struct platform_device *pldev;
-+#endif
- int ttimer;
- int susp_rx;
- unsigned long nir;
---- a/drivers/net/ethernet/dec/tulip/interrupt.c
-+++ b/drivers/net/ethernet/dec/tulip/interrupt.c
-@@ -76,6 +76,10 @@ int tulip_refill_rx(struct net_device *d
- mapping = pci_map_single(tp->pdev, skb->data, PKT_BUF_SZ,
- PCI_DMA_FROMDEVICE);
- #endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ mapping = dma_map_single(&tp->pldev->dev, skb->data, PKT_BUF_SZ,
-+ DMA_FROM_DEVICE);
-+#endif
- tp->rx_buffers[entry].mapping = mapping;
-
- skb->dev = dev; /* Mark as being used by this device. */
-@@ -198,8 +202,7 @@ int tulip_poll(struct napi_struct *napi,
- dev->stats.rx_fifo_errors++;
- }
- } else {
-- struct sk_buff *skb;
--
-+ struct sk_buff *skb;
- /* Check if the packet is long enough to accept without copying
- to a minimally-sized skbuff. */
- if (pkt_len < tulip_rx_copybreak &&
-@@ -242,6 +245,10 @@ int tulip_poll(struct napi_struct *napi,
- pci_unmap_single(tp->pdev, tp->rx_buffers[entry].mapping,
- PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
- #endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ dma_unmap_single(&tp->pldev->dev, tp->rx_buffers[entry].mapping,
-+ PKT_BUF_SZ, DMA_FROM_DEVICE);
-+#endif
-
- tp->rx_buffers[entry].skb = NULL;
- tp->rx_buffers[entry].mapping = 0;
-@@ -635,6 +642,11 @@ irqreturn_t tulip_interrupt(int irq, voi
- tp->tx_buffers[entry].skb->len,
- PCI_DMA_TODEVICE);
- #endif
-+#ifdef CONFIG_TULIP_PLATFORM
-+ dma_unmap_single(&tp->pldev->dev, tp->tx_buffers[entry].mapping,
-+ tp->tx_buffers[entry].skb->len,
-+ DMA_TO_DEVICE);
-+#endif
-
- /* Free the original skb. */
- dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
---- /dev/null
-+++ b/include/linux/platform_data/tulip.h
-@@ -0,0 +1,31 @@
-+#ifndef _LINUX_TULIP_PDATA_H
-+#define _LINUX_TULIP_PDATA_H
-+
-+/* chip types. careful! order is VERY IMPORTANT here, as these
-+ * are used throughout the driver as indices into arrays */
-+/* Note 21142 == 21143. */
-+enum chips {
-+ DC21040 = 0,
-+ DC21041 = 1,
-+ DC21140 = 2,
-+ DC21142 = 3, DC21143 = 3,
-+ LC82C168,
-+ MX98713,
-+ MX98715,
-+ MX98725,
-+ AX88140,
-+ PNIC2,
-+ COMET,
-+ COMPEX9881,
-+ I21145,
-+ DM910X,
-+ CONEXANT,
-+ ADM8668,
-+};
-+
-+struct tulip_platform_data {
-+ u8 mac[6];
-+ enum chips chip_id;
-+};
-+
-+#endif
+++ /dev/null
---- a/drivers/tty/serial/amba-pl010.c
-+++ b/drivers/tty/serial/amba-pl010.c
-@@ -49,11 +49,10 @@
-
- #include <asm/io.h>
-
--#define UART_NR 8
--
- #define SERIAL_AMBA_MAJOR 204
- #define SERIAL_AMBA_MINOR 16
--#define SERIAL_AMBA_NR UART_NR
-+#define SERIAL_AMBA_NR CONFIG_SERIAL_AMBA_PL010_NUMPORTS
-+#define SERIAL_AMBA_NAME CONFIG_SERIAL_AMBA_PL010_PORTNAME
-
- #define AMBA_ISR_PASS_LIMIT 256
-
-@@ -79,9 +78,9 @@ static void pl010_stop_tx(struct uart_po
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int cr;
-
-- cr = readb(uap->port.membase + UART010_CR);
-+ cr = __raw_readl(uap->port.membase + UART010_CR);
- cr &= ~UART010_CR_TIE;
-- writel(cr, uap->port.membase + UART010_CR);
-+ __raw_writel(cr, uap->port.membase + UART010_CR);
- }
-
- static void pl010_start_tx(struct uart_port *port)
-@@ -89,9 +88,9 @@ static void pl010_start_tx(struct uart_p
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int cr;
-
-- cr = readb(uap->port.membase + UART010_CR);
-+ cr = __raw_readl(uap->port.membase + UART010_CR);
- cr |= UART010_CR_TIE;
-- writel(cr, uap->port.membase + UART010_CR);
-+ __raw_writel(cr, uap->port.membase + UART010_CR);
- }
-
- static void pl010_stop_rx(struct uart_port *port)
-@@ -99,9 +98,9 @@ static void pl010_stop_rx(struct uart_po
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int cr;
-
-- cr = readb(uap->port.membase + UART010_CR);
-+ cr = __raw_readl(uap->port.membase + UART010_CR);
- cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
-- writel(cr, uap->port.membase + UART010_CR);
-+ __raw_writel(cr, uap->port.membase + UART010_CR);
- }
-
- static void pl010_enable_ms(struct uart_port *port)
-@@ -109,9 +108,9 @@ static void pl010_enable_ms(struct uart_
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
- unsigned int cr;
-
-- cr = readb(uap->port.membase + UART010_CR);
-+ cr = __raw_readl(uap->port.membase + UART010_CR);
- cr |= UART010_CR_MSIE;
-- writel(cr, uap->port.membase + UART010_CR);
-+ __raw_writel(cr, uap->port.membase + UART010_CR);
- }
-
- static void pl010_rx_chars(struct uart_amba_port *uap)
-@@ -119,9 +118,9 @@ static void pl010_rx_chars(struct uart_a
- struct tty_struct *tty = uap->port.state->port.tty;
- unsigned int status, ch, flag, rsr, max_count = 256;
-
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- while (UART_RX_DATA(status) && max_count--) {
-- ch = readb(uap->port.membase + UART01x_DR);
-+ ch = __raw_readl(uap->port.membase + UART01x_DR);
- flag = TTY_NORMAL;
-
- uap->port.icount.rx++;
-@@ -130,9 +129,9 @@ static void pl010_rx_chars(struct uart_a
- * Note that the error handling code is
- * out of the main execution path
- */
-- rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
-+ rsr = __raw_readl(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
- if (unlikely(rsr & UART01x_RSR_ANY)) {
-- writel(0, uap->port.membase + UART01x_ECR);
-+ __raw_writel(0, uap->port.membase + UART01x_ECR);
-
- if (rsr & UART01x_RSR_BE) {
- rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
-@@ -162,7 +161,7 @@ static void pl010_rx_chars(struct uart_a
- uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
-
- ignore_char:
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- }
- spin_unlock(&uap->port.lock);
- tty_flip_buffer_push(tty);
-@@ -175,7 +174,7 @@ static void pl010_tx_chars(struct uart_a
- int count;
-
- if (uap->port.x_char) {
-- writel(uap->port.x_char, uap->port.membase + UART01x_DR);
-+ __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR);
- uap->port.icount.tx++;
- uap->port.x_char = 0;
- return;
-@@ -187,7 +186,7 @@ static void pl010_tx_chars(struct uart_a
-
- count = uap->port.fifosize >> 1;
- do {
-- writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
-+ __raw_writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
- xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
- uap->port.icount.tx++;
- if (uart_circ_empty(xmit))
-@@ -205,9 +204,9 @@ static void pl010_modem_status(struct ua
- {
- unsigned int status, delta;
-
-- writel(0, uap->port.membase + UART010_ICR);
-+ __raw_writel(0, uap->port.membase + UART010_ICR);
-
-- status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
-+ status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
-
- delta = status ^ uap->old_status;
- uap->old_status = status;
-@@ -235,7 +234,7 @@ static irqreturn_t pl010_int(int irq, vo
-
- spin_lock(&uap->port.lock);
-
-- status = readb(uap->port.membase + UART010_IIR);
-+ status = __raw_readl(uap->port.membase + UART010_IIR);
- if (status) {
- do {
- if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
-@@ -248,7 +247,7 @@ static irqreturn_t pl010_int(int irq, vo
- if (pass_counter-- == 0)
- break;
-
-- status = readb(uap->port.membase + UART010_IIR);
-+ status = __raw_readl(uap->port.membase + UART010_IIR);
- } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
- UART010_IIR_TIS));
- handled = 1;
-@@ -262,7 +261,7 @@ static irqreturn_t pl010_int(int irq, vo
- static unsigned int pl010_tx_empty(struct uart_port *port)
- {
- struct uart_amba_port *uap = (struct uart_amba_port *)port;
-- unsigned int status = readb(uap->port.membase + UART01x_FR);
-+ unsigned int status = __raw_readl(uap->port.membase + UART01x_FR);
- return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
- }
-
-@@ -272,7 +271,7 @@ static unsigned int pl010_get_mctrl(stru
- unsigned int result = 0;
- unsigned int status;
-
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- if (status & UART01x_FR_DCD)
- result |= TIOCM_CAR;
- if (status & UART01x_FR_DSR)
-@@ -298,12 +297,12 @@ static void pl010_break_ctl(struct uart_
- unsigned int lcr_h;
-
- spin_lock_irqsave(&uap->port.lock, flags);
-- lcr_h = readb(uap->port.membase + UART010_LCRH);
-+ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
- if (break_state == -1)
- lcr_h |= UART01x_LCRH_BRK;
- else
- lcr_h &= ~UART01x_LCRH_BRK;
-- writel(lcr_h, uap->port.membase + UART010_LCRH);
-+ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
- spin_unlock_irqrestore(&uap->port.lock, flags);
- }
-
-@@ -335,12 +334,12 @@ static int pl010_startup(struct uart_por
- /*
- * initialise the old status of the modem signals
- */
-- uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
-+ uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
-
- /*
- * Finally, enable interrupts
- */
-- writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
-+ __raw_writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
- uap->port.membase + UART010_CR);
-
- return 0;
-@@ -365,10 +364,10 @@ static void pl010_shutdown(struct uart_p
- /*
- * disable all interrupts, disable the port
- */
-- writel(0, uap->port.membase + UART010_CR);
-+ __raw_writel(0, uap->port.membase + UART010_CR);
-
- /* disable break condition and fifos */
-- writel(readb(uap->port.membase + UART010_LCRH) &
-+ __raw_writel(__raw_readl(uap->port.membase + UART010_LCRH) &
- ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
- uap->port.membase + UART010_LCRH);
-
-@@ -391,7 +390,7 @@ pl010_set_termios(struct uart_port *port
- /*
- * Ask the core to calculate the divisor for us.
- */
-- baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
-+ baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
- quot = uart_get_divisor(port, baud);
-
- switch (termios->c_cflag & CSIZE) {
-@@ -454,25 +453,25 @@ pl010_set_termios(struct uart_port *port
- uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
-
- /* first, disable everything */
-- old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
-+ old_cr = __raw_readl(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
-
- if (UART_ENABLE_MS(port, termios->c_cflag))
- old_cr |= UART010_CR_MSIE;
-
-- writel(0, uap->port.membase + UART010_CR);
-+ __raw_writel(0, uap->port.membase + UART010_CR);
-
- /* Set baud rate */
- quot -= 1;
-- writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
-- writel(quot & 0xff, uap->port.membase + UART010_LCRL);
-+ __raw_writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
-+ __raw_writel(quot & 0xff, uap->port.membase + UART010_LCRL);
-
- /*
- * ----------v----------v----------v----------v-----
- * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
- * ----------^----------^----------^----------^-----
- */
-- writel(lcr_h, uap->port.membase + UART010_LCRH);
-- writel(old_cr, uap->port.membase + UART010_CR);
-+ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
-+ __raw_writel(old_cr, uap->port.membase + UART010_CR);
-
- spin_unlock_irqrestore(&uap->port.lock, flags);
- }
-@@ -554,7 +553,7 @@ static struct uart_ops amba_pl010_pops =
- .verify_port = pl010_verify_port,
- };
-
--static struct uart_amba_port *amba_ports[UART_NR];
-+static struct uart_amba_port *amba_ports[SERIAL_AMBA_NR];
-
- #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
-
-@@ -564,10 +563,10 @@ static void pl010_console_putchar(struct
- unsigned int status;
-
- do {
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- barrier();
- } while (!UART_TX_READY(status));
-- writel(ch, uap->port.membase + UART01x_DR);
-+ __raw_writel(ch, uap->port.membase + UART01x_DR);
- }
-
- static void
-@@ -581,8 +580,8 @@ pl010_console_write(struct console *co,
- /*
- * First save the CR then disable the interrupts
- */
-- old_cr = readb(uap->port.membase + UART010_CR);
-- writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
-+ old_cr = __raw_readl(uap->port.membase + UART010_CR);
-+ __raw_writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
-
- uart_console_write(&uap->port, s, count, pl010_console_putchar);
-
-@@ -591,10 +590,10 @@ pl010_console_write(struct console *co,
- * and restore the TCR
- */
- do {
-- status = readb(uap->port.membase + UART01x_FR);
-+ status = __raw_readl(uap->port.membase + UART01x_FR);
- barrier();
- } while (status & UART01x_FR_BUSY);
-- writel(old_cr, uap->port.membase + UART010_CR);
-+ __raw_writel(old_cr, uap->port.membase + UART010_CR);
-
- clk_disable(uap->clk);
- }
-@@ -603,9 +602,9 @@ static void __init
- pl010_console_get_options(struct uart_amba_port *uap, int *baud,
- int *parity, int *bits)
- {
-- if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
-+ if (__raw_readl(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
- unsigned int lcr_h, quot;
-- lcr_h = readb(uap->port.membase + UART010_LCRH);
-+ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
-
- *parity = 'n';
- if (lcr_h & UART01x_LCRH_PEN) {
-@@ -620,8 +619,8 @@ pl010_console_get_options(struct uart_am
- else
- *bits = 8;
-
-- quot = readb(uap->port.membase + UART010_LCRL) |
-- readb(uap->port.membase + UART010_LCRM) << 8;
-+ quot = __raw_readl(uap->port.membase + UART010_LCRL) |
-+ __raw_readl(uap->port.membase + UART010_LCRM) << 8;
- *baud = uap->port.uartclk / (16 * (quot + 1));
- }
- }
-@@ -640,7 +639,7 @@ static int __init pl010_console_setup(st
- * if so, search for the first available port that does have
- * console support.
- */
-- if (co->index >= UART_NR)
-+ if (co->index >= SERIAL_AMBA_NR)
- co->index = 0;
- uap = amba_ports[co->index];
- if (!uap)
-@@ -662,7 +661,7 @@ static int __init pl010_console_setup(st
-
- static struct uart_driver amba_reg;
- static struct console amba_console = {
-- .name = "ttyAM",
-+ .name = SERIAL_AMBA_NAME,
- .write = pl010_console_write,
- .device = uart_console_device,
- .setup = pl010_console_setup,
-@@ -678,11 +677,11 @@ static struct console amba_console = {
-
- static struct uart_driver amba_reg = {
- .owner = THIS_MODULE,
-- .driver_name = "ttyAM",
-- .dev_name = "ttyAM",
-+ .driver_name = SERIAL_AMBA_NAME,
-+ .dev_name = SERIAL_AMBA_NAME,
- .major = SERIAL_AMBA_MAJOR,
- .minor = SERIAL_AMBA_MINOR,
-- .nr = UART_NR,
-+ .nr = SERIAL_AMBA_NR,
- .cons = AMBA_CONSOLE,
- };
-
---- a/drivers/tty/serial/Kconfig
-+++ b/drivers/tty/serial/Kconfig
-@@ -16,10 +16,25 @@ config SERIAL_AMBA_PL010
- help
- This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
- an Integrator/AP or Integrator/PP2 platform, or if you have a
-- Cirrus Logic EP93xx CPU, say Y or M here.
-+ Cirrus Logic EP93xx CPU or an Infineon ADM5120 SOC, say Y or M here.
-
- If unsure, say N.
-
-+config SERIAL_AMBA_PL010_NUMPORTS
-+ int "Maximum number of AMBA PL010 serial ports"
-+ depends on SERIAL_AMBA_PL010
-+ default "8"
-+ ---help---
-+ Set this to the number of serial ports you want the AMBA PL010 driver
-+ to support.
-+
-+config SERIAL_AMBA_PL010_PORTNAME
-+ string "Name of the AMBA PL010 serial ports"
-+ depends on SERIAL_AMBA_PL010
-+ default "ttyAM"
-+ ---help---
-+ ::: To be written :::
-+
- config SERIAL_AMBA_PL010_CONSOLE
- bool "Support for console on AMBA serial port"
- depends on SERIAL_AMBA_PL010=y
+++ /dev/null
---- a/drivers/amba/bus.c
-+++ b/drivers/amba/bus.c
-@@ -20,6 +20,10 @@
- #include <asm/irq.h>
- #include <asm/sizes.h>
-
-+#ifndef NO_IRQ
-+#define NO_IRQ (-1)
-+#endif
-+
- #define to_amba_driver(d) container_of(d, struct amba_driver, drv)
-
- static const struct amba_id *
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/WRTU54G-TM
- NAME:=Linksys WRTU54G T-Mobile (Default)
- PACKAGES:=kmod-rt61-pci kmod-usb2 wpad-mini
-endef
-
-define Profile/WRTU54G-TM/Description
- Package set compatible with the Linksys WRTU54G T-Mobile
-endef
-$(eval $(call Profile,WRTU54G-TM))
-
+++ /dev/null
-#
-# Copyright (C) 2006 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=mips
-BOARD:=amazon
-BOARDNAME:=Infineon Amazon
-FEATURES:=squashfs broken
-LINUX_VERSION:=3.3.8
-
-include $(INCLUDE_DIR)/target.mk
-
-define Target/Description
- Build firmware images for Infineon Amazon boards
-endef
-
-define Kernel/Prepare
- $(call Kernel/Prepare/Default)
- mkdir -p $(LINUX_DIR)/arch/mips/include/asm/amazon
- $(CP) $(LINUX_DIR)/include/asm-mips/amazon/*.h $(LINUX_DIR)/arch/mips/include/asm/amazon
-endef
-
-$(eval $(call BuildTarget))
+++ /dev/null
-# Copyright (C) 2006 OpenWrt.org
-
-config interface loopback
- option ifname lo
- option proto static
- option ipaddr 127.0.0.1
- option netmask 255.0.0.0
-
-config interface lan
- option ifname eth1
- option type bridge
- option proto static
- option ipaddr 192.168.1.1
- option netmask 255.255.255.0
- option ip6assign 60
-
-config globals globals
- option ula_prefix auto
+++ /dev/null
-CONFIG_ADM6996_SUPPORT=y
-CONFIG_AMAZON=y
-CONFIG_AMAZON_ASC_UART=y
-CONFIG_AMAZON_MTD=y
-CONFIG_AMAZON_NET_SW=y
-CONFIG_AMAZON_PCI=y
-CONFIG_AMAZON_WDT=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_R4K_LIB=y
-CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/bin/sh"
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_CSRC_R4K_LIB=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_STD_PC_SERIAL_PORT=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_KALLSYMS=y
-CONFIG_MIPS=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-CONFIG_MTD_AMAZON_BUS_WIDTH_16=y
-# CONFIG_MTD_AMAZON_BUS_WIDTH_32 is not set
-# CONFIG_MTD_AMAZON_BUS_WIDTH_8 is not set
-# CONFIG_MTD_AMAZON_FLASH_SIZE_16 is not set
-# CONFIG_MTD_AMAZON_FLASH_SIZE_2 is not set
-CONFIG_MTD_AMAZON_FLASH_SIZE_4=y
-# CONFIG_MTD_AMAZON_FLASH_SIZE_8 is not set
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_SUPPORT=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-# copyright 2007 john crispin <blogic@openwrt.org>
-
-menu "Amazon built-in"
-
-config AMAZON_ASC_UART
- bool "Amazon asc uart"
- select SERIAL_CORE
- select SERIAL_CORE_CONSOLE
- default y
-
-config AMAZON_PCI
- bool "Amazon PCI support"
- default y
- select HW_HAS_PCI
- select PCI
-
-config AMAZON_NET_SW
- bool "Amazon network"
- default y
-
-config AMAZON_WDT
- bool "Amazon watchdog timer"
- default y
-
-config AMAZON_MTD
- bool "Amazon MTD map"
- default y
-
-config ADM6996_SUPPORT
- bool "Amazon ADM6996 Switch driver"
- default y
-
-choice
- prompt "Flash Size"
- depends on AMAZON_MTD
-
-config MTD_AMAZON_FLASH_SIZE_2
- bool "2MB"
-
-config MTD_AMAZON_FLASH_SIZE_4
- bool "4MB"
-
-config MTD_AMAZON_FLASH_SIZE_8
- bool "8MB"
-
-config MTD_AMAZON_FLASH_SIZE_16
- bool "16MB"
-
-endchoice
-
-choice
- prompt "Bus Width"
- depends on AMAZON_MTD
-
-config MTD_AMAZON_BUS_WIDTH_8
- bool "8-bit"
-
-config MTD_AMAZON_BUS_WIDTH_16
- bool "16-bit"
-
-config MTD_AMAZON_BUS_WIDTH_32
- bool "32-bit"
-
-endchoice
-
-
-endmenu
+++ /dev/null
-#
-# Copyright 2007 openwrt.org
-# John Crispin <blogic@openwrt.org>
-#
-# Makefile for Infineon Amazon
-#
-obj-y := dma-core.o interrupt.o prom.o setup.o board.o
-obj-$(CONFIG_PCI) += pci.o
-
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) 2009 Hauke Mehrtens <hauke@hauke-m.de>
- */
-
-
-#include <linux/platform_device.h>
-#include <asm/amazon/irq.h>
-
-#define AMAZON_FLASH_START 0x13000000
-#define AMAZON_FLASH_MAX 0x1000000
-
-static struct platform_device amazon_mii = {
- .id = 0,
- .name = "amazon_mii0",
-// .dev = {
-// .platform_data = amazon_ethaddr,
-// }
-};
-
-static struct platform_device amazon_wdt = {
- .id = 0,
- .name = "amazon_wdt",
-};
-
-static struct platform_device amazon_asc = {
- .id = 0,
- .name = "amazon_asc",
-};
-
-static struct resource amazon_mtd_resource = {
- .start = AMAZON_FLASH_START,
- .end = AMAZON_FLASH_START + AMAZON_FLASH_MAX - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device amazon_mtd = {
- .id = 0,
- .name = "amazon_mtd",
- .num_resources = 1,
- .resource = &amazon_mtd_resource,
-};
-
-
-struct platform_device *amazon_devs[] = {
- &amazon_mii, &amazon_mtd, &amazon_wdt, &amazon_asc
-};
-
-
-int __init amazon_init_devices(void)
-{
- printk(KERN_INFO "");
- return platform_add_devices(amazon_devs, 4);
-}
-
-arch_initcall(amazon_init_devices);
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- */
-//-----------------------------------------------------------------------
-/*
- * Description:
- * Driver for Infineon Amazon DMA
- */
-//-----------------------------------------------------------------------
-/* Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com]
- * Created: 7-April-2004
- */
-//-----------------------------------------------------------------------
-/* History
- * Last changed on: 4-May-2004
- * Last changed by: <peng.liu@infineon.com>
- * Reason: debug
- */
-//-----------------------------------------------------------------------
-/* Last changed on: 03-Dec-2004
- * Last changed by: peng.liu@infineon.com
- * Reason: recover from TPE bug
- */
-
-//000004:fchang 2005/6/2 Modified by Linpeng as described below
-//-----------------------------------------------------------------------
-/* Last changed on: 28-Jan-2004
- * Last changed by: peng.liu@infineon.com
- * Reason:
- * - handle "out of memory" bug
- */
-//000003:tc.chen 2005/06/16 fix memory leak when Tx buffer full (heaving traffic).
-//507261:tc.chen 2005/07/26 re-organize code address map to improve performance.
-
-#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS)
-#define MODVERSIONS
-#endif
-
-#if defined(MODVERSIONS) && !defined(__GENKSYMS__)
-#include <linux/modversions.h>
-#endif
-
-#ifndef EXPORT_SYMTAB
-#define EXPORT_SYMTAB /* need this one 'cause we export symbols */
-#endif
-
-#undef DMA_NO_POLLING
-
-/* no TX interrupt handling */
-#define NO_TX_INT
-/* need for DMA workaround */
-#undef AMAZON_DMA_TPE_AAL5_RECOVERY
-
-#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY
-#define MAX_SYNC_FAILS 1000000 // 000004:fchang
-unsigned int dma_sync_fails = 0;
-unsigned int total_dma_tpe_reset = 0;
-int (*tpe_reset) (void);
-int (*tpe_start) (void);
-int (*tpe_inject) (void);
-#endif // AMAZON_DMA_TPE_AAL5_RECOVERY
-
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/timer.h>
-#include <linux/fs.h>
-#include <linux/errno.h>
-#include <linux/proc_fs.h>
-#include <linux/stat.h>
-#include <linux/mm.h>
-#include <linux/tty.h>
-#include <linux/selection.h>
-#include <linux/kmod.h>
-#include <linux/vmalloc.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <asm/uaccess.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-
-#include <asm/amazon/amazon.h>
-#include <asm/amazon/irq.h>
-#include <asm/amazon/amazon_dma.h>
-#include "dma-core.h"
-
-#define AMAZON_DMA_EMSG(fmt, args...) printk( KERN_ERR "%s: " fmt,__FUNCTION__, ## args)
-
-static irqreturn_t dma_interrupt(int irq, void *dev_id);
-extern void mask_and_ack_amazon_irq(unsigned int irq_nr);
-
-/***************************************** global data *******************************************/
-u64 *g_desc_list;
-dev_list *g_current_dev = NULL;
-dev_list *g_head_dev = NULL;
-dev_list *g_tail_dev = NULL;
-channel_info g_log_chan[CHAN_TOTAL_NUM + 1];
-struct proc_dir_entry *g_amazon_dma_dir;
-static u8 rx_chan_list_len = 0;
-static u8 tx_chan_list_len = 0;
-static int rx_chan_list[RX_CHAN_NUM + 1];
-static int tx_chan_list[TX_CHAN_NUM + 1];
-static u32 comb_isr_mask[CHAN_TOTAL_NUM];
-
-static inline int is_rx_chan(int chan_no)
-/*judge if this is an rx channel*/
-{
- int result = 0;
- if (chan_no < RX_CHAN_NUM)
- result = 1;
- return result;
-}
-
-/* Ugly, Channel ON register is badly mapped to channel no. */
-static u8 ch_on_mapping[CHAN_TOTAL_NUM] =
- { 0, 1, 2, 3, 6, 7, 10, 4, 5, 8, 9, 11 };
-
-/* Brief: check wether the chan_no is legal
- * Parameter: chan_no: logical channel number
- * Return: 0 if is not valid
- * 1 if is valid
- */
-static inline int is_valid_dma_ch(int chan_no)
-{
- return ((chan_no >= 0) && (chan_no < CHAN_TOTAL_NUM));
-}
-
-/* Brief: check whether a channel is open through Channel ON register
- * Parameter: chan_no: logical channel number
- * Return: 1 channel is open
- * 0 not yet
- * EINVAL: invalid parameter
- */
-static inline int is_channel_open(int chan_no)
-{
- return (AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) &
- (1 << ch_on_mapping[chan_no]));
-}
-
-/* Brief: add a list entry
- * Description:
- * always add to the tail and no redundancy allowed. (i.e. entries are unique)
- * 0 : entry deleted
- * <0 : not deleted (due to not unique)
- */
-static inline int _add_list_entry(int *list, int size_of_list, int entry)
-{
- int i;
- for (i = 0; i < size_of_list; i++) {
- if (list[i] == entry)
- break;
- if (list[i] < 0) {
- list[i] = entry;
- return 0;
- }
- }
- return -1;
-}
-
-/* Brief: delete a list entry
- * Description:
- * find the entry and remove it. shift all entries behind it one step forward if necessary\
- * Return:
- * 0 : entry deleted
- * <0 : not deleted (due to not found?)
- */
-static inline int _delete_list_entry(int *list, int size_of_list,
- int entry)
-{
- int i, j;
- for (i = 0; i < size_of_list; i++) {
- if (list[i] == entry) {
- for (j = i; j < size_of_list; j++) {
- list[j] = list[j + 1];
- if (list[j + 1] < 0) {
- break;
- }
- }
- return 0;
- }
- }
- return -1;
-}
-
-/* Brief: enable a channel through Channel ON register
- * Parameter: chan_no: logical channel number
- * Description:
- * Please don't open a channel without a valid descriptor (hardware pitfall)
- */
-static inline void open_channel(int chan_no)
-{
- AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) |= (1 << ch_on_mapping[chan_no]);
- if (is_rx_chan(chan_no)) {
- if (_add_list_entry(rx_chan_list, RX_CHAN_NUM, chan_no) == 0) {
- rx_chan_list_len++;
- } else {
- AMAZON_DMA_DMSG("cannot add chan %d to open list\n", chan_no);
- }
- } else {
- if (_add_list_entry(tx_chan_list, TX_CHAN_NUM, chan_no) == 0) {
- tx_chan_list_len++;
- } else {
- AMAZON_DMA_DMSG("cannot add chan %d to open list\n", chan_no);
- }
- }
-}
-
-/* Brief: disable a channel through Channel ON register
- * Parameter: chan_no: logical channel number
- */
-
-static inline void close_channel(int chan_no)
-{
- AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) &= ~(1 << ch_on_mapping[chan_no]);
- if (is_rx_chan(chan_no)) {
- if (_delete_list_entry(rx_chan_list, RX_CHAN_NUM, chan_no) == 0) {
- rx_chan_list_len--;
- } else {
- AMAZON_DMA_DMSG("cannot remove chan %d from open list \n",
- chan_no);
- }
- } else {
- if (_delete_list_entry(tx_chan_list, TX_CHAN_NUM, chan_no) == 0) {
- tx_chan_list_len--;
- } else {
- AMAZON_DMA_DMSG("cannot remove chan %d from open list \n",
- chan_no);
- }
- }
-}
-
-/* Brief: clear RX interrupt
- */
-inline void rx_chan_clear_isr(int chan_no)
-{
-#ifdef DMA_NO_POLLING
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + chan_no * AMAZON_DMA_CH_STEP) =
- (AMAZON_DMA_REG32
- (AMAZON_DMA_CH0_ISR +
- chan_no *
- AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP | DMA_ISR_CMDCPT
- | DMA_ISR_DURR));
-#else
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + chan_no * AMAZON_DMA_CH_STEP) =
- (AMAZON_DMA_REG32
- (AMAZON_DMA_CH0_ISR +
- chan_no *
- AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP |
- DMA_ISR_CMDCPT));
-#endif
-}
-
-#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY
-/* Brief: hacking function, this will reset all descriptors back to DMA
- */
-static void dma_reset_all_descriptors(int chan_no)
-{
- volatile struct rx_desc *rx_desc_p = NULL;
- int i;
- rx_desc_p =
- (struct rx_desc *) g_desc_list +
- g_log_chan[chan_no].offset_from_base;
- for (i = 0; i < g_log_chan[chan_no].desc_len; i++) {
- rx_desc_p->status.word &=
- (~(DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | DMA_DESC_CPT_SET));
- rx_desc_p->status.word |=
- (DMA_DESC_OWN_DMA | g_log_chan[chan_no].packet_size);
- rx_desc_p++;
- }
-}
-
-/* Brief: Reset DMA descriptors
- */
-static void amazon_dma_reset_tpe_rx(int chan_no)
-{
- struct tx_desc *tx_desc_p = NULL;
- int j, i = 0;
-
- // wait until all TX channels stop transmitting
- for (j = 9; j <= 10; j++) {
- tx_desc_p =
- (struct tx_desc *) g_desc_list +
- g_log_chan[j].offset_from_base;
- for (i = 0; i < g_log_chan[j].desc_len; i++) {
- while ((tx_desc_p->status.field.OWN != CPU_OWN)) {
- AMAZON_DMA_DMSG("DMA TX in progress\n"); // 000004:fchang
- udelay(100);
- }
- tx_desc_p++;
- }
- }
-
- if (tpe_reset) {
- total_dma_tpe_reset++;
- AMAZON_DMA_DMSG
- ("\n===============resetting TPE========================== \n");
- if ((*tpe_reset) ()) {
- panic("cannot reset TPE engien\n"); // 000004:fchang
- }
- } else {
- panic("no tpe_reset function\n"); // 000004:fchang
- return;
- }
- dma_reset_all_descriptors(chan_no);
- rx_chan_clear_isr(chan_no);
- mb();
-
- // send EoP
- if (tpe_inject) {
- if ((*tpe_inject) ()) {
- panic("cannot inject a cell\n"); // 000004:fchang
- }
- } else {
- AMAZON_DMA_EMSG("no tpe_inject function\n");
- return;
- }
- mb();
- while (1) {
- if (AMAZON_DMA_REG32
- (AMAZON_DMA_CH0_ISR +
- chan_no * AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT)) {
- rx_chan_clear_isr(chan_no);
- mb();
- dma_reset_all_descriptors(chan_no);
- if (g_log_chan[chan_no].current_desc ==
- (g_log_chan[chan_no].desc_len - 1)) {
- g_log_chan[chan_no].current_desc = 0;
- } else {
- g_log_chan[chan_no].current_desc++;
- }
- break;
- }
- mdelay(1);
- }
- mb();
-#if 0
- AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) &= ~(1 << ch_on_mapping[chan_no]);
- while (AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) &
- (1 << ch_on_mapping[chan_no])) {
- printk("TPE channel still on\n");
- mdelay(1);
- }
-
- // AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = (1<<chan_no);
- mb();
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + chan_no * AMAZON_DMA_CH_STEP) =
- 0x32;
- mb();
- rx_chan_clear_isr(chan_no);
- dma_reset_all_descriptors(chan_no);
- mb();
- AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) |= (1 << ch_on_mapping[chan_no]);
- // g_log_chan[chan_no].current_desc=0;
- mb();
- mdelay(1);
-#endif
- if (tpe_start) {
- (*tpe_start) ();
- } else {
- AMAZON_DMA_EMSG("cannot restart TPE engien\n");
- }
-}
-#endif // AMAZON_DMA_TPE_AAL5_RECOVERY
-
-
-/* Brief: RX channel interrupt handler
- * Parameter: RX channel no
- * Description: the interrupt handler for each RX channel
- * 1. check descriptor, clear ISR if no incoming packet
- * 2. inform upper layer to receive packet (and update descriptors)
- */
-inline void rx_chan_intr_handler(int chan_no)
-{
- volatile struct rx_desc *rx_desc_p = NULL;
-
- /* fetch the current descriptor */
- rx_desc_p =
- (struct rx_desc *) g_desc_list +
- g_log_chan[chan_no].offset_from_base +
- g_log_chan[chan_no].current_desc;
-
- g_log_chan[chan_no].dma_dev->current_rx_chan =
- chan_no - g_log_chan[chan_no].dma_dev->logic_rx_chan_base;
-
- // workaround for DMA pitfall: complete bit set happends before the
- // other two bits (own,eop) are ready
- if ((rx_desc_p->status.field.EoP != 1)
- || (rx_desc_p->status.field.OWN != CPU_OWN)
- || (rx_desc_p->status.field.data_length ==
- g_log_chan[chan_no].packet_size)) {
-#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY
- if (chan_no == 4 || chan_no == 5) {
- dma_sync_fails++;
- if (dma_sync_fails > MAX_SYNC_FAILS) {
- // detect bug
- rx_desc_p0 =
- (struct rx_desc *) g_desc_list +
- g_log_chan[chan_no].offset_from_base;
- rx_desc_p1 =
- (struct rx_desc *) g_desc_list +
- g_log_chan[chan_no].offset_from_base + 1;
- if ((rx_desc_p0->status.field.OWN == CPU_OWN
- && rx_desc_p0->status.field.EoP != 1)
- && (rx_desc_p1->status.field.OWN == CPU_OWN
- && rx_desc_p1->status.field.EoP != 1)) {
- amazon_dma_reset_tpe_rx(chan_no);
- dma_sync_fails = 0;
- return;
- }
- dma_sync_fails = 0;
- AMAZON_DMA_DMSG("too many times ch:%d\n", chan_no); // 000004:fchang
- return;
- }
- udelay(10); // 000004:fchang
- }
-#endif // //AMAZON_DMA_TPE_AAL5_RECOVERY
- return;
- }
-
- /* inform the upper layer to receive the packet */
- g_log_chan[chan_no].intr_handler(g_log_chan[chan_no].dma_dev, RCV_INT);
- /* check the next descriptor, if still contains the incoming packet,
- then do not clear the interrupt status */
- rx_desc_p =
- (struct rx_desc *) g_desc_list +
- g_log_chan[chan_no].offset_from_base +
- g_log_chan[chan_no].current_desc;
- if (!
- ((rx_desc_p->status.field.OWN == CPU_OWN)
- && (rx_desc_p->status.field.C == 1))) {
- rx_chan_clear_isr(chan_no);
- }
-}
-
-
-/* Brief: TX channel interrupt handler
- * Parameter: TX channel no
- * Description: the interrupt handler for each TX channel
- * 1. check all the descripters,if any of them had transmitted a packet, then free buffer
- * because we cannot garantee the which one has already transmitted out, we have to go through all the descriptors here
- * 2. clear the interrupt status bit
- */
-inline void tx_chan_intr_handler(int chan_no)
-{
- struct tx_desc *tx_desc_p = NULL;
- int i = 0;
-
- tx_desc_p =
- (struct tx_desc *) g_desc_list +
- g_log_chan[chan_no].offset_from_base;
-
- for (i = 0; i < g_log_chan[chan_no].desc_len; i++) {
- if ((tx_desc_p->status.field.OWN == CPU_OWN)
- && (tx_desc_p->status.field.C == 1)) {
- /* if already transmitted, then free the buffer */
- g_log_chan[chan_no].
- buffer_free((u8 *) __va(tx_desc_p->Data_Pointer),
- g_log_chan[chan_no].opt[i]);
- tx_desc_p->status.field.C = 0;
- /* inform the upper layer about the completion of the
- transmitted packet, the upper layer may want to free the
- packet */
- g_log_chan[chan_no].intr_handler(g_log_chan[chan_no].dma_dev,
- TRANSMIT_CPT_INT);
- }
- tx_desc_p++;
- }
-
- /* after all these operations, clear the interrupt status bit */
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + chan_no * AMAZON_DMA_CH_STEP) =
- (AMAZON_DMA_REG32
- (AMAZON_DMA_CH0_ISR +
- chan_no *
- AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP |
- DMA_ISR_CMDCPT));
-}
-
-/* Brief: DMA interrupt handler
- */
-static irqreturn_t dma_interrupt(int irq, void *dev_id)
-{
- int i = 0;
- int chan_no;
- u32 isr = 0;
-#ifdef NO_TX_INT // 000004:fchang
- static int cnt = 0; // 000004:fchang
-#endif // 000004:fchang
- while ((isr =
- AMAZON_DMA_REG32(AMAZON_DMA_COMB_ISR)) & (COMB_ISR_RX_MASK |
- COMB_ISR_TX_MASK)) {
- if (isr & COMB_ISR_RX_MASK) {
- // RX Channels: start WFQ algorithm
- chan_no = CHAN_TOTAL_NUM;
- for (i = 0; i < RX_CHAN_NUM; i++) {
- if ((isr & (comb_isr_mask[i]))
- && (g_log_chan[i].weight > 0)) {
- if (g_log_chan[chan_no].weight < g_log_chan[i].weight) {
- chan_no = i;
- }
- }
- }
- if (chan_no < CHAN_TOTAL_NUM) {
- rx_chan_intr_handler(chan_no);
- } else {
- for (i = 0; i < RX_CHAN_NUM; i++) {
- g_log_chan[i].weight = g_log_chan[i].default_weight;
- }
- }
- }
-#ifdef NO_TX_INT
- cnt++;
- if (cnt == 10) {
- cnt = 0;
- for (i = 0; i < tx_chan_list_len; i++) {
- if (AMAZON_DMA_REG32
- (AMAZON_DMA_CH0_ISR +
- tx_chan_list[i] *
- AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP)) {
- tx_chan_intr_handler(tx_chan_list[i]);
- }
- }
- }
-#else
- if (isr & COMB_ISR_TX_MASK) {
- // TX channels: RR
- for (i = 0; i < tx_chan_list_len; i++) {
- if (isr & (comb_isr_mask[tx_chan_list[i]])) {
- tx_chan_intr_handler(tx_chan_list[i]);
- }
- }
- }
-#endif
- } // while
- return IRQ_HANDLED;
-}
-
-
-/* Brief: read a packet from DMA RX channel
- * Parameter:
- * Return: packet length
- * Description:
- * This is called back in a context of DMA interrupt
- * 1. prepare new descriptor
- * 2. read data
- * 3. update WFQ weight
- */
-//507261:tc.chen int dma_device_read(struct dma_device_info* dma_dev, u8** dataptr, void** opt)
-int asmlinkage dma_device_read(struct dma_device_info *dma_dev,
- u8 ** dataptr, void **opt)
-{
- u8 *buf;
- int len;
- int chan_no = 0;
- int byte_offset = 0;
-
- struct rx_desc *rx_desc_p;
- void *p = NULL;
- int current_desc;
-
- chan_no = dma_dev->logic_rx_chan_base + dma_dev->current_rx_chan;
- current_desc = g_log_chan[chan_no].current_desc;
- rx_desc_p =
- (struct rx_desc *) (g_desc_list +
- g_log_chan[chan_no].offset_from_base +
- current_desc);
- buf = (u8 *) __va(rx_desc_p->Data_Pointer); /* extract the virtual
- address of the data
- pointer */
- len = rx_desc_p->status.field.data_length; /* extract the data length */
-#ifndef CONFIG_MIPS_UNCACHED
- dma_cache_inv((unsigned long) buf, len);
-#endif // CONFIG_MIPS_UNCACHED
- *(u32 *) dataptr = (u32) buf;
- if (opt) {
- *(int *) opt = (int) g_log_chan[chan_no].opt[current_desc]; /* read
- out
- the
- opt
- information */
- }
-
- buf =
- (u8 *) g_log_chan[chan_no].buffer_alloc(g_log_chan[chan_no].
- packet_size, &byte_offset,
- &p);
- // should check null!!!!
- if (buf == NULL || p == NULL) {
- *(u32 *) dataptr = 0;
- *(int *) opt = 0;
- len = 0;
- } else {
- g_log_chan[chan_no].opt[current_desc] = p;
- /* reduce the weight for WFQ algorithm */
- g_log_chan[chan_no].weight -= len;
- rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf);
- }
- if (current_desc == g_log_chan[chan_no].desc_len - 1) {
- current_desc = 0;
- } else {
- current_desc++;
- }
- g_log_chan[chan_no].current_desc = current_desc;
-
- rx_desc_p->status.word = DMA_DESC_OWN_DMA
- | (byte_offset << DMA_DESC_BYTEOFF_SHIFT)
- | g_log_chan[chan_no].packet_size;
- return len;
-}
-
-/* Brief: write a packet through DMA RX channel to peripheral
- * Parameter:
- * Return: packet length
- * Description:
- *
- */
-u64 dma_tx_drop = 0;
-//507261:tc.chen int dma_device_write(struct dma_device_info* dma_dev, u8* dataptr, int len,void* opt)
-int asmlinkage dma_device_write(struct dma_device_info *dma_dev,
- u8 * dataptr, int len, void *opt)
-{
- int chan_no = 0;
- struct tx_desc *tx_desc_p;
-
- int byte_offset = 0;
- int current_desc;
- static int cnt = 0; // 000004:fchang
-
- unsigned long flag;
- local_irq_save(flag);
-
- chan_no = dma_dev->logic_tx_chan_base + dma_dev->current_tx_chan;
- current_desc = g_log_chan[chan_no].current_desc;
- tx_desc_p =
- (struct tx_desc *) (g_desc_list +
- g_log_chan[chan_no].offset_from_base +
- current_desc);
- // 000003:tc.chen if(tx_desc_p->status.field.OWN==DMA_OWN){
- if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C == 1) { // 000003:tc.chen
- AMAZON_DMA_DMSG("no TX desc for CPU, drop packet\n");
- dma_tx_drop++;
- g_log_chan[chan_no].intr_handler(dma_dev, TX_BUF_FULL_INT);
- local_irq_restore(flag);
- return 0;
- }
- g_log_chan[chan_no].opt[current_desc] = opt;
-
- /* byte offset----to adjust the starting address of the data buffer,
- should be multiple of the burst length. */
- byte_offset =
- ((u32) CPHYSADDR((u32) dataptr)) % (g_log_chan[chan_no].burst_len *
- 4);
-#ifndef CONFIG_MIPS_UNCACHED
- dma_cache_wback((unsigned long) dataptr, len);
- wmb();
-#endif // CONFIG_MIPS_UNCACHED
-
- tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset;
- wmb();
- tx_desc_p->status.word = DMA_DESC_OWN_DMA
- | DMA_DESC_SOP_SET
- | DMA_DESC_EOP_SET | (byte_offset << DMA_DESC_BYTEOFF_SHIFT)
- | len;
- wmb();
- if (is_channel_open(chan_no) == 0) {
- // turn on if necessary
- open_channel(chan_no);
- }
-#ifdef DMA_NO_POLLING
- if ((AMAZON_DMA_REG32
- (AMAZON_DMA_CH0_ISR +
- chan_no * AMAZON_DMA_CH_STEP) & (DMA_ISR_DURR | DMA_ISR_CPT)) ==
- (DMA_ISR_DURR)) {
- // clear DURR if (CPT is AND set and DURR is set)
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR +
- chan_no * AMAZON_DMA_CH_STEP) = DMA_ISR_DURR;
- }
-#endif
-
- if (current_desc == (g_log_chan[chan_no].desc_len - 1)) {
- current_desc = 0;
- } else {
- current_desc++;
- }
-
-
- g_log_chan[chan_no].current_desc = current_desc;
- tx_desc_p =
- (struct tx_desc *) (g_desc_list +
- g_log_chan[chan_no].offset_from_base +
- current_desc);
- // 000003:tc.chen if(tx_desc_p->status.field.OWN==DMA_OWN){
- if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C == 1) { // 000003:tc.chen
- g_log_chan[chan_no].intr_handler(dma_dev, TX_BUF_FULL_INT);
- }
-#ifdef NO_TX_INT
-//000004:fchang Start
- cnt++;
- if (cnt == 5) {
- cnt = 0;
- tx_chan_intr_handler(chan_no);
- }
-//000004:fchang End
-#endif
- local_irq_restore(flag); // 000004:fchang
- return len;
-}
-
-
-
-int desc_list_proc_read(char *buf, char **start, off_t offset,
- int count, int *eof, void *data)
-{
- int i;
- u32 *p = (u32 *) g_desc_list;
- int len = 0;
- len += sprintf(buf + len, "descriptor list:\n");
- for (i = 0; i < 120; i++) {
- len += sprintf(buf + len, "%d\n", i);
- len += sprintf(buf + len, "%08x\n", *(p + i * 2 + 1));
- len += sprintf(buf + len, "%08x\n", *(p + i * 2));
-
- }
-
- return len;
-
-}
-
-int channel_weight_proc_read(char *buf, char **start, off_t offset,
- int count, int *eof, void *data)
-{
-
- // int i=0;
- int len = 0;
- len += sprintf(buf + len, "Qos dma channel weight list\n");
- len +=
- sprintf(buf + len,
- "channel_num default_weight current_weight device Tx/Rx\n");
- len +=
- sprintf(buf + len,
- " 0 %08x %08x Switch Rx0\n",
- g_log_chan[0].default_weight, g_log_chan[0].weight);
- len +=
- sprintf(buf + len,
- " 1 %08x %08x Switch Rx1\n",
- g_log_chan[1].default_weight, g_log_chan[1].weight);
- len +=
- sprintf(buf + len,
- " 2 %08x %08x Switch Rx2\n",
- g_log_chan[2].default_weight, g_log_chan[2].weight);
- len +=
- sprintf(buf + len,
- " 3 %08x %08x Switch Rx3\n",
- g_log_chan[3].default_weight, g_log_chan[3].weight);
- len +=
- sprintf(buf + len,
- " 4 %08x %08x Switch Tx0\n",
- g_log_chan[4].default_weight, g_log_chan[4].weight);
- len +=
- sprintf(buf + len,
- " 5 %08x %08x Switch Tx1\n",
- g_log_chan[5].default_weight, g_log_chan[5].weight);
- /*
- len+=sprintf(buf+len," 6 %08x %08x TPE
- Rx0\n",g_log_chan[6].default_weight, g_log_chan[6].weight);
- len+=sprintf(buf+len," 7 %08x %08x TPE
- Rx0\n",g_log_chan[7].default_weight, g_log_chan[7].weight);
- len+=sprintf(buf+len," 8 %08x %08x TPE
- Tx0\n",g_log_chan[8].default_weight, g_log_chan[8].weight);
- len+=sprintf(buf+len," 9 %08x %08x TPE
- Rx0\n",g_log_chan[9].default_weight, g_log_chan[9].weight);
- len+=sprintf(buf+len," 10 %08x %08x DPLUS
- Rx0\n",g_log_chan[10].default_weight, g_log_chan[10].weight);
- len+=sprintf(buf+len," 11 %08x %08x DPLUS
- Rx0\n",g_log_chan[11].default_weight, g_log_chan[11].weight); */
- return len;
-}
-
-int dma_register_proc_read(char *buf, char **start, off_t offset,
- int count, int *eof, void *data)
-{
- dev_list *temp_dev;
- int len = 0;;
-
- len += sprintf(buf + len, "amazon dma driver\n");
- len += sprintf(buf + len, "version 1.0\n");
- len += sprintf(buf + len, "devices registered:\n");
- for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) {
- len += sprintf(buf + len, "%s ", temp_dev->dev->device_name);
- }
- len += sprintf(buf + len, "\n");
- len += sprintf(buf + len, "CH_ON=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH_ON));
- len += sprintf(buf + len, "CH_RST=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH_RST));
- len += sprintf(buf + len, "CH0_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR));
- len += sprintf(buf + len, "CH1_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH1_ISR));
- len += sprintf(buf + len, "CH2_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH2_ISR));
- len += sprintf(buf + len, "CH3_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH3_ISR));
- len += sprintf(buf + len, "CH4_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH4_ISR));
- len += sprintf(buf + len, "CH5_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH5_ISR));
- len += sprintf(buf + len, "CH6_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH6_ISR));
- len += sprintf(buf + len, "CH7_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH7_ISR));
- len += sprintf(buf + len, "CH8_ISR=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH8_ISR));
- len +=
- sprintf(buf + len, "CH9_ISR=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH9_ISR));
- len +=
- sprintf(buf + len, "CH10_ISR=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH10_ISR));
- len +=
- sprintf(buf + len, "CH11_ISR=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH11_ISR));
- len +=
- sprintf(buf + len, "LCH0_MSK=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK));
- len +=
- sprintf(buf + len, "LCH1_MSK=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH1_MSK));
- len +=
- sprintf(buf + len, "LCH2_MSK=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH2_MSK));
- len +=
- sprintf(buf + len, "LCH3_MSK=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH3_MSK));
- len +=
- sprintf(buf + len, "LCH4_MSK=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH4_MSK));
- len +=
- sprintf(buf + len, "LCH5_MSK=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH5_MSK));
- len +=
- sprintf(buf + len, "LCH6_MSK=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH6_MSK));
- len +=
- sprintf(buf + len, "LCH7_MSK=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH7_MSK));
- len +=
- sprintf(buf + len, "LCH8_MSK=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH8_MSK));
- len +=
- sprintf(buf + len, "LCH9_MSK=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH9_MSK));
- len +=
- sprintf(buf + len, "LCH10_MSK=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH10_MSK));
- len +=
- sprintf(buf + len, "LCH11_MSK=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH11_MSK));
- len +=
- sprintf(buf + len, "Desc_BA=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_Desc_BA));
- len +=
- sprintf(buf + len, "LCH0_DES_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_DES_LEN));
- len +=
- sprintf(buf + len, "LCH1_DES_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH1_DES_LEN));
- len +=
- sprintf(buf + len, "LCH2_DES_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH2_DES_LEN));
- len +=
- sprintf(buf + len, "LCH3_DES_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH3_DES_LEN));
- len +=
- sprintf(buf + len, "LCH4_DES_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH4_DES_LEN));
- len +=
- sprintf(buf + len, "LCH5_DES_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH5_DES_LEN));
- len +=
- sprintf(buf + len, "LCH6_DES_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH6_DES_LEN));
- len +=
- sprintf(buf + len, "LCH7_DES_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH7_DES_LEN));
- len +=
- sprintf(buf + len, "LCH8_DES_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH8_DES_LEN));
- len +=
- sprintf(buf + len, "LCH9_DES_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH9_DES_LEN));
- len +=
- sprintf(buf + len, "LCH10_DES_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH10_DES_LEN));
- len +=
- sprintf(buf + len, "LCH11_DES_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH11_DES_LEN));
- len +=
- sprintf(buf + len, "LCH1_DES_OFST=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH1_DES_OFST));
- len +=
- sprintf(buf + len, "LCH2_DES_OFST=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH2_DES_OFST));
- len +=
- sprintf(buf + len, "LCH3_DES_OFST=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH3_DES_OFST));
- len +=
- sprintf(buf + len, "LCH4_DES_OFST=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH4_DES_OFST));
- len +=
- sprintf(buf + len, "LCH5_DES_OFST=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH5_DES_OFST));
- len +=
- sprintf(buf + len, "LCH6_DES_OFST=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH6_DES_OFST));
- len +=
- sprintf(buf + len, "LCH7_DES_OFST=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH7_DES_OFST));
- len +=
- sprintf(buf + len, "LCH8_DES_OFST=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH8_DES_OFST));
- len +=
- sprintf(buf + len, "LCH9_DES_OFST=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH9_DES_OFST));
- len +=
- sprintf(buf + len, "LCH10_DES_OFST=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH10_DES_OFST));
- len +=
- sprintf(buf + len, "LCH11_DES_OFST=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH11_DES_OFST));
- len +=
- sprintf(buf + len, "AMAZON_DMA_SW_BL=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_SW_BL));
- len +=
- sprintf(buf + len, "AMAZON_DMA_TPE_BL=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_TPE_BL));
- len +=
- sprintf(buf + len, "DPlus2FPI_BL=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_DPlus2FPI_BL));
- len +=
- sprintf(buf + len, "GRX_BUF_LEN=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_GRX_BUF_LEN));
- len +=
- sprintf(buf + len, "DMA_ECON_REG=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_DMA_ECON_REG));
- len +=
- sprintf(buf + len, "POLLING_REG=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_POLLING_REG));
- len +=
- sprintf(buf + len, "CH_WGT=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_CH_WGT));
- len +=
- sprintf(buf + len, "TX_WGT=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_TX_WGT));
- len +=
- sprintf(buf + len, "DPlus2FPI_CLASS=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_DPLus2FPI_CLASS));
- len +=
- sprintf(buf + len, "COMB_ISR=%08x\n",
- AMAZON_DMA_REG32(AMAZON_DMA_COMB_ISR));
-#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY
- len += sprintf(buf + len, "TPE fails:%u\n", total_dma_tpe_reset); // 000004:fchang
-#endif
- return len;
-}
-
-/* Brief: initialize DMA registers
- * Description:
- */
-static void dma_chip_init(void)
-{
- int i;
- for (i = 0; i < CHAN_TOTAL_NUM; i++) {
- AMAZON_DMA_REG32(AMAZON_DMA_CH1_DES_OFST +
- i * AMAZON_DMA_CH_STEP) = DEFAULT_OFFSET;
- }
-#ifdef DMA_NO_POLLING
- AMAZON_DMA_REG32(AMAZON_DMA_POLLING_REG) = 0;
-#else
- // enable poll mode and set polling counter
- AMAZON_DMA_REG32(AMAZON_DMA_POLLING_REG) = DMA_POLLING_CNT | DMA_POLLING_ENABLE;
-#endif
- // to enable DMA drop
- AMAZON_DMA_REG32(AMAZON_DMA_GRX_BUF_LEN) = 0x10000;
-}
-
-int insert_dev_list(dev_list * dev)
-{
- dev_list *temp_dev;
- if (g_head_dev == NULL) {
- g_head_dev = dev;
- g_tail_dev = dev;
- dev->prev = NULL;
- dev->next = NULL;
- } else {
- for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) {
- if (temp_dev->weight < dev->weight) {
- if (temp_dev->prev)
- temp_dev->prev->next = dev;
-
- dev->prev = temp_dev->prev;
- dev->next = temp_dev;
- temp_dev->prev = dev;
- if (temp_dev == g_head_dev)
- g_head_dev = dev;
- break;
- }
- }
-
- if (!temp_dev) {
- g_tail_dev->next = dev;
- dev->prev = g_tail_dev;
- dev->next = NULL;
- g_tail_dev = dev;
- }
-
- }
-
- return 1;
-}
-
-u8 *common_buffer_alloc(int len, int *byte_offset, void **opt)
-{
- u8 *buffer = (u8 *) kmalloc(len * sizeof(u8), GFP_KERNEL);
- *byte_offset = 0;
- return buffer;
-
-}
-
-int common_buffer_free(u8 * dataptr, void *opt)
-{
- if (dataptr)
- kfree(dataptr);
- return 0;
-}
-
-
-int register_dev(struct dma_device_info *dma_dev)
-{
- int i, j, temp;
- int burst_reg = 0;
- u8 *buffer;
- void *p = NULL;
- int byte_offset = 0;
-
- struct rx_desc *rx_desc_p;
- struct tx_desc *tx_desc_p;
- if (strcmp(dma_dev->device_name, "switch1") == 0) {
- AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = SWITCH1_RST_MASK; // resest
- // channel
- // 1st
- AMAZON_DMA_REG32(AMAZON_DMA_DMA_ECON_REG) |= 0x3; // endian
- // conversion
- // for Switch
- burst_reg = AMAZON_DMA_SW_BL;
- dma_dev->logic_rx_chan_base = switch_rx_chan_base;
- dma_dev->logic_tx_chan_base = switch_tx_chan_base;
- }
-
- else if (strcmp(dma_dev->device_name, "switch2") == 0) {
- AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = SWITCH2_RST_MASK; // resest
- // channel
- // 1st
- AMAZON_DMA_REG32(AMAZON_DMA_DMA_ECON_REG) |= 0x3; // endian
- // conversion
- // for Switch
- burst_reg = AMAZON_DMA_SW_BL;
- dma_dev->logic_rx_chan_base = switch2_rx_chan_base;
- dma_dev->logic_tx_chan_base = switch2_tx_chan_base;
-
- } else if (strcmp(dma_dev->device_name, "TPE") == 0) {
- AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = TPE_RST_MASK; // resest
- // channel 1st
- //
- burst_reg = AMAZON_DMA_TPE_BL;
- dma_dev->logic_rx_chan_base = TPE_rx_chan_base;
- dma_dev->logic_tx_chan_base = TPE_tx_chan_base;
- }
-
- else if (strcmp(dma_dev->device_name, "DPlus") == 0) {
- AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = DPlus2FPI_RST_MASK; // resest
- // channel
- // 1st
- dma_dev->logic_rx_chan_base = DPLus2FPI_rx_chan_base;
- dma_dev->logic_tx_chan_base = DPLus2FPI_tx_chan_base;
-
- }
-
- i = 0;
- for (temp = dma_dev->tx_burst_len; temp > 2; temp /= 2) {
- i += 1;
- }
-
-
- AMAZON_DMA_REG32(burst_reg) = i << 1;
- i = 0;
- for (temp = dma_dev->rx_burst_len; temp > 2; temp /= 2) {
- i += 1;
- }
- AMAZON_DMA_REG32(burst_reg) += i;
-
- for (i = 0; i < dma_dev->num_rx_chan; i++) {
-
- temp = dma_dev->logic_rx_chan_base + i;
- g_log_chan[temp].dma_dev = dma_dev;
- g_log_chan[temp].weight = dma_dev->rx_chan[i].weight;
- g_log_chan[temp].default_weight = dma_dev->rx_chan[i].weight;
- g_log_chan[temp].current_desc = 0;
- g_log_chan[temp].desc_ofst = DEFAULT_OFFSET;
- g_log_chan[temp].desc_len = dma_dev->rx_chan[i].desc_num;
- g_log_chan[temp].offset_from_base = temp * DEFAULT_OFFSET;
- g_log_chan[temp].packet_size = dma_dev->rx_chan[i].packet_size;
-
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_DES_LEN + temp * AMAZON_DMA_CH_STEP) = dma_dev->rx_chan[i].desc_num;
- // enable interrupt mask
- if (temp == 4 || temp == 5) {
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x32;
- } else {
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x36;
- }
- strcpy(g_log_chan[temp].device_name, dma_dev->device_name);
- g_log_chan[temp].burst_len = dma_dev->rx_burst_len;
- g_log_chan[temp].control = dma_dev->rx_chan[i].control;
-
-
- /* specify the buffer allocation and free method */
- if (dma_dev->buffer_alloc)
- g_log_chan[temp].buffer_alloc = dma_dev->buffer_alloc;
- else
- g_log_chan[temp].buffer_alloc = common_buffer_alloc;
-
- if (dma_dev->buffer_free)
- g_log_chan[temp].buffer_free = dma_dev->buffer_free;
- else
- g_log_chan[temp].buffer_free = common_buffer_free;
-
- if (dma_dev->intr_handler)
- g_log_chan[temp].intr_handler = dma_dev->intr_handler;
- else
- g_log_chan[temp].intr_handler = NULL;
-
- for (j = 0; j < g_log_chan[temp].desc_len; j++) {
- rx_desc_p = (struct rx_desc *) (g_desc_list + g_log_chan[temp].offset_from_base + j);
- rx_desc_p->status.word = 0;
- rx_desc_p->status.field.data_length = g_log_chan[temp].packet_size;
- buffer = (u8 *) g_log_chan[temp].buffer_alloc(g_log_chan[temp].packet_size, &byte_offset, &p);
- rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buffer);
- rx_desc_p->status.field.byte_offset = byte_offset;
- /* fix me, should check if the addresss comply with the burst
- lenght requirment */
- g_log_chan[temp].opt[j] = p;
- rx_desc_p->status.field.OWN = DMA_OWN;
-
- }
- /* open or close the channel */
- if (g_log_chan[temp].control)
- open_channel(temp);
- else
- close_channel(temp);
- }
-
- for (i = 0; i < dma_dev->num_tx_chan; i++) {
- temp = dma_dev->logic_tx_chan_base + i;
- g_log_chan[temp].dma_dev = dma_dev;
- g_log_chan[temp].weight = dma_dev->tx_chan[i].weight;
- g_log_chan[temp].default_weight = dma_dev->tx_chan[i].weight;
- g_log_chan[temp].current_desc = 0;
- g_log_chan[temp].desc_ofst = DEFAULT_OFFSET;
- g_log_chan[temp].desc_len = dma_dev->tx_chan[i].desc_num;
- g_log_chan[temp].offset_from_base = temp * DEFAULT_OFFSET;
- g_log_chan[temp].packet_size = dma_dev->tx_chan[i].packet_size;
-
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_DES_LEN + temp * AMAZON_DMA_CH_STEP) = dma_dev->tx_chan[i].desc_num;
- // enable interrupt mask
-#ifdef NO_TX_INT
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x3e;
-#else
- AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x36;
-#endif
-
- strcpy(g_log_chan[temp].device_name, dma_dev->device_name);
- g_log_chan[temp].burst_len = dma_dev->tx_burst_len;
- g_log_chan[temp].control = dma_dev->tx_chan[i].control;
-
- if (dma_dev->buffer_alloc)
- g_log_chan[temp].buffer_alloc = dma_dev->buffer_alloc;
- else
- g_log_chan[temp].buffer_alloc = common_buffer_alloc;
-
- if (dma_dev->buffer_free)
- g_log_chan[temp].buffer_free = dma_dev->buffer_free;
- else
- g_log_chan[temp].buffer_free = common_buffer_free;
-
- if (dma_dev->intr_handler)
- g_log_chan[temp].intr_handler = dma_dev->intr_handler;
- else
- g_log_chan[temp].intr_handler = NULL;
-
- for (j = 0; j < g_log_chan[temp].desc_len; j++) {
-
- tx_desc_p =
- (struct tx_desc *) (g_desc_list +
- g_log_chan[temp].offset_from_base + j);
- tx_desc_p->status.word = 0;
- tx_desc_p->status.field.data_length =
- g_log_chan[temp].packet_size;
- tx_desc_p->status.field.OWN = CPU_OWN;
-
- }
- /* workaround DMA pitfall, we never turn on channel if we don't
- have proper descriptors */
- if (!g_log_chan[temp].control) {
- close_channel(temp);
- }
-
- }
-
- return 0;
-}
-
-int dma_device_register(struct dma_device_info *dma_dev)
-{
- dev_list *temp_dev;
- temp_dev = (dev_list *) kmalloc(sizeof(dev_list), GFP_KERNEL);
- temp_dev->dev = dma_dev;
- temp_dev->weight = dma_dev->weight;
- insert_dev_list(temp_dev);
- /* check whether this is a known device */
- if ((strcmp(dma_dev->device_name, "switch1") == 0)
- || (strcmp(dma_dev->device_name, "TPE") == 0)
- || (strcmp(dma_dev->device_name, "switch2") == 0)
- || (strcmp(dma_dev->device_name, "DPlus") == 0)) {
- register_dev(dma_dev);
- }
-
- return 0;
-}
-
-
-int unregister_dev(struct dma_device_info *dma_dev)
-{
- int i, j, temp;
- u8 *buffer;
- struct rx_desc *rx_desc_p;
-
- for (i = 0; i < dma_dev->num_rx_chan; i++) {
- temp = dma_dev->logic_rx_chan_base + i;
- close_channel(temp);
- for (j = 0; j < g_log_chan[temp].desc_len; j++) {
- rx_desc_p =
- (struct rx_desc *) (g_desc_list +
- g_log_chan[temp].offset_from_base + j);
- buffer = (u8 *) __va(rx_desc_p->Data_Pointer);
- g_log_chan[temp].buffer_free(buffer, g_log_chan[temp].opt[j]);
- }
- }
- for (i = 0; i < dma_dev->num_tx_chan; i++) {
- temp = dma_dev->logic_tx_chan_base + i;
- close_channel(temp);
- }
- return 0;
-}
-
-int dma_device_unregister(struct dma_device_info *dev)
-{
- dev_list *temp_dev;
- for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) {
- if (strcmp(dev->device_name, temp_dev->dev->device_name) == 0) {
- if ((strcmp(dev->device_name, "switch1") == 0)
- || (strcmp(dev->device_name, "TPE") == 0)
- || (strcmp(dev->device_name, "switch2") == 0)
- || (strcmp(dev->device_name, "DPlus") == 0))
- unregister_dev(dev);
- if (temp_dev == g_head_dev) {
- g_head_dev = temp_dev->next;
- kfree(temp_dev);
- } else {
- if (temp_dev == g_tail_dev)
- g_tail_dev = temp_dev->prev;
- if (temp_dev->prev)
- temp_dev->prev->next = temp_dev->next;
- if (temp_dev->next)
- temp_dev->next->prev = temp_dev->prev;
- kfree(temp_dev);
- }
- break;
- }
-
- }
- return 0;
-}
-
-void dma_device_update_rx(struct dma_device_info *dma_dev)
-{
- int i, temp;
- for (i = 0; i < dma_dev->num_rx_chan; i++) {
- temp = dma_dev->logic_rx_chan_base + i;
- g_log_chan[temp].control = dma_dev->rx_chan[i].control;
-
- if (g_log_chan[temp].control)
- open_channel(temp);
- else
- close_channel(temp);
- }
-
-}
-
-void dma_device_update_tx(struct dma_device_info *dma_dev)
-{
- int i, temp;
- for (i = 0; i < dma_dev->num_tx_chan; i++) {
- temp = dma_dev->logic_tx_chan_base + i;
- g_log_chan[temp].control = dma_dev->tx_chan[i].control;
- if (g_log_chan[temp].control) {
- /* we turn on channel when send out the very first packet */
- // open_channel(temp);
- } else
- close_channel(temp);
- }
-}
-
-int dma_device_update(struct dma_device_info *dma_dev)
-{
- dma_device_update_rx(dma_dev);
- dma_device_update_tx(dma_dev);
- return 0;
-}
-
-static int dma_open(struct inode *inode, struct file *file)
-{
- return 0;
-}
-
-static int dma_release(struct inode *inode, struct file *file)
-{
- /* release the resources */
- return 0;
-}
-
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))
-static long dma_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-#else
-static int dma_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
-#endif
-{
- int value = 0;
- int chan_no = 0;
-
- switch (cmd) {
- case 0: /* get register value */
- break;
- case 1: /* return channel weight */
- chan_no = *((int *) arg);
- *((int *) arg + 1) = g_log_chan[chan_no].default_weight;
- break;
- case 2: /* set channel weight */
- chan_no = *((int *) arg);
- value = *((int *) arg + 1);
- printk("new weight=%08x\n", value);
- g_log_chan[chan_no].default_weight = value;
- break;
- default:
- break;
- }
- return 0;
-}
-
-
-static struct file_operations dma_fops = {
- owner:THIS_MODULE,
- open:dma_open,
- release:dma_release,
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))
- unlocked_ioctl:dma_ioctl,
-#else
- ioctl:dma_ioctl,
-#endif
-};
-
-static int dma_init(void)
-{
- int result = 0;
- int i;
- printk("initialising dma core\n");
- result = register_chrdev(DMA_MAJOR, "dma-core", &dma_fops);
- if (result) {
- AMAZON_DMA_EMSG("cannot register device dma-core!\n");
- return result;
- }
- result = request_irq(AMAZON_DMA_INT, dma_interrupt, IRQF_DISABLED, "dma-core", (void *) &dma_interrupt);
- if (result) {
- AMAZON_DMA_EMSG("error, cannot get dma_irq!\n");
- free_irq(AMAZON_DMA_INT, (void *) &dma_interrupt);
- return -EFAULT;
- }
-
- g_desc_list = (u64 *) KSEG1ADDR(__get_free_page(GFP_DMA));
-
- if (g_desc_list == NULL) {
- AMAZON_DMA_EMSG("no memory for desriptor\n");
- return -ENOMEM;
- }
- memset(g_desc_list, 0, PAGE_SIZE);
- AMAZON_DMA_REG32(AMAZON_DMA_Desc_BA) = (u32) CPHYSADDR((u32) g_desc_list);
- g_amazon_dma_dir = proc_mkdir("amazon_dma", NULL);
- create_proc_read_entry("dma_register", 0, g_amazon_dma_dir, dma_register_proc_read, NULL);
- create_proc_read_entry("g_desc_list", 0, g_amazon_dma_dir, desc_list_proc_read, NULL);
- create_proc_read_entry("channel_weight", 0, g_amazon_dma_dir, channel_weight_proc_read, NULL);
-
- dma_chip_init();
- for (i = 0; i < (RX_CHAN_NUM + 1); i++) {
- rx_chan_list[i] = -1;
- }
- for (i = 0; i < (TX_CHAN_NUM + 1); i++) {
- tx_chan_list[i] = -1;
- }
-
- for (i = 0; i < CHAN_TOTAL_NUM; i++) {
- comb_isr_mask[i] = 0x80000000 >> (i);
- }
-
- g_log_chan[CHAN_TOTAL_NUM].weight = 0;
- printk("initialising dma core ... done\n");
-
- return 0;
-}
-
-arch_initcall(dma_init);
-
-
-void dma_cleanup(void)
-{
- dev_list *temp_dev;
-
- unregister_chrdev(DMA_MAJOR, "dma-core");
- for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) {
- kfree(temp_dev);
- }
- free_page(KSEG0ADDR((unsigned long) g_desc_list));
- remove_proc_entry("channel_weight", g_amazon_dma_dir);
- remove_proc_entry("dma_list", g_amazon_dma_dir);
- remove_proc_entry("dma_register", g_amazon_dma_dir);
- remove_proc_entry("amazon_dma", NULL);
- /* release the resources */
- free_irq(AMAZON_DMA_INT, (void *) &dma_interrupt);
-}
-
-EXPORT_SYMBOL(dma_device_register);
-EXPORT_SYMBOL(dma_device_unregister);
-EXPORT_SYMBOL(dma_device_read);
-EXPORT_SYMBOL(dma_device_write);
-EXPORT_SYMBOL(dma_device_update);
-EXPORT_SYMBOL(dma_device_update_rx);
-
-MODULE_LICENSE("GPL");
+++ /dev/null
-#ifndef DMA_CORE_H
-#define DMA_CORE_H
-
-#define AMAZON_DMA_REG32(reg_num) *((volatile u32*)(reg_num))
-#define AMAZON_DMA_CH_STEP 4
-
-#define COMB_ISR_RX_MASK 0xfe000000
-#define COMB_ISR_TX_MASK 0x01f00000
-
-
-#define DMA_OWN 1
-#define CPU_OWN 0
-#define DMA_MAJOR 250
-
-//Descriptors
-#define DMA_DESC_OWN_CPU 0x0
-#define DMA_DESC_OWN_DMA 0x80000000
-#define DMA_DESC_CPT_SET 0x40000000
-#define DMA_DESC_SOP_SET 0x20000000
-#define DMA_DESC_EOP_SET 0x10000000
-
-#define switch_rx_chan_base 0
-#define switch_tx_chan_base 7
-#define switch2_rx_chan_base 2
-#define switch2_tx_chan_base 8
-#define TPE_rx_chan_base 4
-#define TPE_tx_chan_base 9
-#define DPLus2FPI_rx_chan_base 6
-#define DPLus2FPI_tx_chan_base 11
-
-#define RX_CHAN_NUM 7
-#define TX_CHAN_NUM 5
-#define CHAN_TOTAL_NUM (RX_CHAN_NUM+TX_CHAN_NUM)
-#define DEFAULT_OFFSET 20
-#define DESCRIPTOR_SIZE 8
-
-typedef struct dev_list{
- struct dma_device_info* dev;
- int weight;
- struct dev_list* prev;
- struct dev_list* next;
-}dev_list;
-
-typedef struct channel_info{
- char device_name[16];
- int occupied;
- enum attr_t attr;
- int current_desc;
- int weight;
- int default_weight;
- int desc_num;
- int burst_len;
- int desc_len;
- int desc_ofst;
- int packet_size;
- int offset_from_base;
- int control;
- void* opt[DEFAULT_OFFSET];
- u8* (*buffer_alloc)(int len,int* offset, void** opt);
- int (*buffer_free)(u8* dataptr,void* opt);
- int (*intr_handler)(struct dma_device_info* info,int status);
-
- struct dma_device_info* dma_dev;
-}channel_info;
-
-
-
-#endif
-
+++ /dev/null
-/*
- * Gary Jennejohn (C) 2003 <gj@denx.de>
- * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Routines for generic manipulation of the interrupts found on the
- * AMAZON boards.
- */
-
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-
-#include <asm/amazon/amazon.h>
-#include <asm/amazon/irq.h>
-#include <asm/bootinfo.h>
-#include <asm/irq_cpu.h>
-#include <asm/irq.h>
-#include <asm/time.h>
-
-static void amazon_disable_irq(struct irq_data *d)
-{
- int i;
- u32 amazon_ier = AMAZON_ICU_IM0_IER;
- unsigned int irq_nr = d->irq;
-
- if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
- amazon_writel(amazon_readl(amazon_ier) & (~(AMAZON_DMA_H_MASK)), amazon_ier);
- else {
- irq_nr -= INT_NUM_IRQ0;
- for (i = 0; i <= 4; i++)
- {
- if (irq_nr <= 31)
- amazon_writel(amazon_readl(amazon_ier) & ~(1 << irq_nr ), amazon_ier);
- amazon_ier += 0x10;
- irq_nr -= 32;
- }
- }
-}
-
-static void amazon_mask_and_ack_irq(struct irq_data *d)
-{
- int i;
- u32 amazon_ier = AMAZON_ICU_IM0_IER;
- u32 amazon_isr = AMAZON_ICU_IM0_ISR;
- unsigned int irq_nr = d->irq;
-
- if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0){
- amazon_writel(amazon_readl(amazon_ier) & (~(AMAZON_DMA_H_MASK)), amazon_ier);
- amazon_writel(AMAZON_DMA_H_MASK, amazon_isr);
- } else {
- irq_nr -= INT_NUM_IRQ0;
- for (i = 0; i <= 4; i++)
- {
- if (irq_nr <= 31){
- amazon_writel(amazon_readl(amazon_ier) & ~(1 << irq_nr ), amazon_ier);
- amazon_writel((1 << irq_nr ), amazon_isr);
- }
- amazon_ier += 0x10;
- amazon_isr += 0x10;
- irq_nr -= 32;
- }
- }
-}
-
-static void amazon_enable_irq(struct irq_data *d)
-{
- int i;
- u32 amazon_ier = AMAZON_ICU_IM0_IER;
- unsigned int irq_nr = d->irq;
-
- if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
- amazon_writel(amazon_readl(amazon_ier) | AMAZON_DMA_H_MASK, amazon_ier);
- else {
- irq_nr -= INT_NUM_IRQ0;
- for (i = 0; i <= 4; i++)
- {
- if (irq_nr <= 31)
- amazon_writel(amazon_readl(amazon_ier) | (1 << irq_nr ), amazon_ier);
- amazon_ier += 0x10;
- irq_nr -= 32;
- }
- }
-}
-
-static unsigned int amazon_startup_irq(struct irq_data *d)
-{
- amazon_enable_irq(d);
- return 0;
-}
-
-static struct irq_chip amazon_irq_type = {
- .name = "AMAZON",
- .irq_startup = amazon_startup_irq,
- .irq_enable = amazon_enable_irq,
- .irq_disable = amazon_disable_irq,
- .irq_unmask = amazon_enable_irq,
- .irq_ack = amazon_mask_and_ack_irq,
- .irq_mask = amazon_disable_irq,
- .irq_mask_ack = amazon_mask_and_ack_irq,
-};
-
-/* Cascaded interrupts from IM0-4 */
-static inline void amazon_hw_irqdispatch(u8 line)
-{
- u32 irq;
-
- irq = (amazon_readl(AMAZON_ICU_IM_VEC) >> (line * 5)) & AMAZON_ICU_IM0_VEC_MASK;
- if (line == 0 && irq <= 11 && irq >= 0) {
- //DMA fixed to IM0_IRL0
- irq = 0;
- }
- do_IRQ(irq + INT_NUM_IRQ0 + (line * 32));
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
- if (pending & CAUSEF_IP7){
- do_IRQ(MIPS_CPU_TIMER_IRQ);
- goto out;
- } else {
- unsigned int i;
- for (i = 0; i <= 4; i++)
- {
- if(pending & (CAUSEF_IP2 << i)){
- amazon_hw_irqdispatch(i);
- goto out;
- }
- }
- }
- printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
-out:
- return;
-}
-
-static struct irqaction cascade = {
- .handler = no_action,
- .flags = IRQF_DISABLED,
- .name = "cascade",
-};
-
-void __init arch_init_irq(void)
-{
- int i;
-
- /* mask all interrupt sources */
- for(i = 0; i <= 4; i++){
- amazon_writel(0, AMAZON_ICU_IM0_IER + (i * 0x10));
- }
-
- mips_cpu_irq_init();
-
- /* set up irq cascade */
- for (i = 2; i <= 6; i++) {
- setup_irq(i, &cascade);
- }
-
- for (i = INT_NUM_IRQ0; i <= INT_NUM_IM4_IRL31; i++)
- irq_set_chip_and_handler(i, &amazon_irq_type,
- handle_level_irq);
-
- set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
-}
-
-void __cpuinit arch_fixup_c0_irqs(void)
-{
- /* FIXME: check for CPUID and only do fix for specific chips/versions */
- cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
- cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
-}
+++ /dev/null
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
- * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-
-/* FIXME: convert nasty volatile register derefs to readl/writel calls */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <asm/io.h>
-#include <asm/paccess.h>
-#include <asm/amazon/irq.h>
-#include <asm/amazon/amazon.h>
-
-#define AMAZON_PCI_REG32( addr ) (*(volatile u32 *)(addr))
-#ifndef AMAZON_PCI_MEM_BASE
-#define AMAZON_PCI_MEM_BASE 0xb2000000
-#endif
-#define AMAZON_PCI_MEM_SIZE 0x00400000
-#define AMAZON_PCI_IO_BASE 0xb2400000
-#define AMAZON_PCI_IO_SIZE 0x00200000
-
-#define AMAZON_PCI_CFG_BUSNUM_SHF 16
-#define AMAZON_PCI_CFG_DEVNUM_SHF 11
-#define AMAZON_PCI_CFG_FUNNUM_SHF 8
-
-#define PCI_ACCESS_READ 0
-#define PCI_ACCESS_WRITE 1
-
-static struct resource pci_io_resource = {
- .name = "io pci IO space",
-#if 1
- .start = AMAZON_PCI_IO_BASE,
- .end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1,
-#else
- .start = 0,
- .end = 0x00002000 - 1,
-#endif
- .flags = IORESOURCE_IO
-};
-
-static struct resource pci_mem_resource = {
- .name = "ext pci memory space",
- .start = AMAZON_PCI_MEM_BASE,
- .end = AMAZON_PCI_MEM_BASE + AMAZON_PCI_MEM_SIZE - 1,
- .flags = IORESOURCE_MEM
-};
-
-static int amazon_pci_config_access(unsigned char access_type,
- struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
-{
- unsigned long flags;
- u32 pci_addr;
- u32 val;
- int ret;
-
- /* Amazon support slot from 0 to 15 */
- /* devfn 0 & 0x20 is itself */
- if ((bus->number != 0) || (devfn > 0x7f) || (devfn == 0) || (devfn == 0x20))
- return 1;
-
- local_irq_save(flags);
-
- pci_addr = AMAZON_PCI_CFG_BASE |
- bus->number << AMAZON_PCI_CFG_BUSNUM_SHF |
- devfn << AMAZON_PCI_CFG_FUNNUM_SHF |
- (where & ~0x3);
-
- if (access_type == PCI_ACCESS_WRITE)
- {
-#ifdef CONFIG_SWAP_IO_SPACE
- val = swab32(*data);
-#endif
- ret = put_dbe(val, (u32 *)pci_addr);
- } else {
- ret = get_dbe(val, (u32 *)pci_addr);
-#ifdef CONFIG_SWAP_IO_SPACE
- *data = swab32(val);
-#else
- *data = val;
-#endif
- }
-
- amazon_writel(amazon_readl(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
- amazon_writel(amazon_readl(STATUS_COMMAND_ADDR), STATUS_COMMAND_ADDR);
- amazon_writel(amazon_readl(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
- mb();
- local_irq_restore(flags);
-
- if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
- return 1;
-
- return ret;
-}
-
-
-static int amazon_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
-{
- u32 data = 0;
-
- if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- if (size == 1)
- *val = (data >> ((where & 3) << 3)) & 0xff;
- else if (size == 2)
- *val = (data >> ((where & 3) << 3)) & 0xffff;
- else
- *val = data;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int amazon_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
-{
- u32 data = 0;
-
- if (size == 4)
- {
- data = val;
- } else {
- if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- if (size == 1)
- data = (data & ~(0xff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
- else if (size == 2)
- data = (data & ~(0xffff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
- }
-
- if (amazon_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops amazon_pci_ops = {
- amazon_pci_read,
- amazon_pci_write
-};
-
-static struct pci_controller amazon_pci_controller = {
- .pci_ops = &amazon_pci_ops,
- .mem_resource = &pci_mem_resource,
- .mem_offset = 0x00000000UL,
- .io_resource = &pci_io_resource,
- .io_offset = 0x00000000UL,
-};
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- switch (slot) {
- case 13:
- /* IDSEL = AD29 --> USB Host Controller */
- return INT_NUM_IM2_IRL15;
- case 14:
- /* IDSEL = AD30 --> mini PCI connector */
- return INT_NUM_IM2_IRL14;
- default:
- printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
- return 0;
- }
-}
-
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- switch(dev->irq) {
- case INT_NUM_IM2_IRL15:
- /*
- * IDSEL = AD29 --> USB Host Controller
- * PCI_INTA/B/C--GPIO Port0.2--EXIN3
- * IN/ALT0:1 ALT1:0
- * PULL UP
- */
- (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffb;
- (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 4;
- (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffb;
- (*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 4;
- (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 4;
- //External Interrupt Node
- (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x6000; /* Low Level triggered */
- (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x8;
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
- break;
- case INT_NUM_IM2_IRL14:
- /*
- * IDSEL = AD30 --> mini PCI connector
- * PCI_INTA--GPIO Port0.1--EXIN2
- * IN/ALT0:1 ALT1:0
- * PULL UP
- */
- (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffd;
- (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 2;
- (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffd;
- (*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 2;
- (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 2;
- //External Interrupt Node
- (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x600;
- (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x4;
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
- break;
- default:
- return 1;
- }
- return 0;
-}
-
-int __init amazon_pci_init(void)
-{
- u32 temp_buffer;
-
-#ifdef CONFIG_SWAP_IO_SPACE
- AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28);
- wmb();
-#endif
-
- AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1<<ARB_CTRL_bit);
- amazon_writel(amazon_readl(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
-
- AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) = AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) | (1<<BUS_MASTER_ENABLE_BIT) |(1<<MEM_SPACE_ENABLE_BIT);
-
- temp_buffer = AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR);
- temp_buffer = temp_buffer | (1<< INTERNAL_ARB_ENABLE_BIT);
- temp_buffer = temp_buffer & ~(3<< PCI_MASTER0_REQ_MASK_2BITS);
- temp_buffer = temp_buffer & ~(3<< PCI_MASTER0_GNT_MASK_2BITS);
-
- /* flash */
- temp_buffer = temp_buffer & ~(3<< PCI_MASTER1_REQ_MASK_2BITS);
- temp_buffer = temp_buffer & ~(3<< PCI_MASTER1_GNT_MASK_2BITS);
-
- /* external master */
- temp_buffer = temp_buffer & ~(3<< PCI_MASTER2_REQ_MASK_2BITS);
- temp_buffer = temp_buffer & ~(3<< PCI_MASTER2_GNT_MASK_2BITS);
-
- AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR) = temp_buffer;
- wmb();
-
- AMAZON_PCI_REG32(FPI_ADDRESS_MAP_0) = 0xb2000000;
- AMAZON_PCI_REG32(FPI_ADDRESS_MAP_1) = 0xb2100000;
- AMAZON_PCI_REG32(FPI_ADDRESS_MAP_2) = 0xb2200000;
- AMAZON_PCI_REG32(FPI_ADDRESS_MAP_3) = 0xb2300000;
- AMAZON_PCI_REG32(FPI_ADDRESS_MAP_4) = 0xb2400000;
- AMAZON_PCI_REG32(FPI_ADDRESS_MAP_5) = 0xb2500000;
- AMAZON_PCI_REG32(FPI_ADDRESS_MAP_6) = 0xb2600000;
- AMAZON_PCI_REG32(FPI_ADDRESS_MAP_7) = 0xb2700000;
-
- AMAZON_PCI_REG32(BAR11_MASK) = 0x0c000008;
- AMAZON_PCI_REG32(PCI_ADDRESS_MAP_11) = 0x0;
- AMAZON_PCI_REG32(BAR1_ADDR) = 0x0;
- amazon_writel(amazon_readl(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
- //use 8 dw burse length
- AMAZON_PCI_REG32(FPI_BURST_LENGTH) = 0x303;
-
- amazon_pci_controller.io_map_base = (unsigned long)ioremap(AMAZON_PCI_IO_BASE, AMAZON_PCI_IO_SIZE - 1);
- register_pci_controller(&amazon_pci_controller);
- return 0;
-}
-arch_initcall(amazon_pci_init);
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright 2007 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/init.h>
-#include <linux/string.h>
-#include <linux/ctype.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <linux/ioport.h>
-#include <asm/bootinfo.h>
-#include <asm/amazon/amazon.h>
-#include <asm/amazon/irq.h>
-#include <asm/amazon/model.h>
-#include <asm/cpu.h>
-
-void prom_putchar(char c)
-{
- /* Wait for FIFO to empty */
- while ((amazon_readl(AMAZON_ASC_FSTAT) >> 8) != 0x00) ;
- /* Crude cr/nl handling is better than none */
- if(c == '\n')
- amazon_writel('\r', AMAZON_ASC_TBUF);
- amazon_writel(c, AMAZON_ASC_TBUF);
-}
-
-void __init prom_init(void)
-{
- char **envp = (char **) fw_arg2;
-
- int memsize = 16; /* assume 16M as default */
-
- envp = (char **)KSEG1ADDR((unsigned long)envp);
- while (*envp) {
- char *e = (char *)KSEG1ADDR(*envp);
-
- if (!strncmp(e, "memsize=", 8)) {
- e += 8;
- memsize = simple_strtoul(e, NULL, 10);
- }
- envp++;
- }
- memsize *= 1024 * 1024;
-
- strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2");
-
- add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
-}
-
-void prom_free_prom_memory(void)
-{
-}
-
-const char *get_system_type(void)
-{
- return BOARD_SYSTEM_TYPE;
-}
+++ /dev/null
-/*
- * Copyright (C) 2004 Peng Liu <peng.liu@infineon.com>
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- */
-
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-
-#include <asm/reboot.h>
-#include <asm/system.h>
-#include <asm/time.h>
-#include <asm/cpu.h>
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-#include <asm/mipsregs.h>
-#include <asm/amazon/amazon.h>
-#include <asm/amazon/irq.h>
-#include <asm/amazon/model.h>
-
-static unsigned int r4k_offset;
-static unsigned int r4k_cur;
-
-/* required in arch/mips/kernel/kspd.c */
-unsigned long cpu_khz;
-
-static void amazon_reboot_setup(void);
-
-/* the CPU clock rate - lifted from u-boot */
-unsigned int amazon_get_cpu_hz(void)
-{
- /*-----------------------------------*/
- /**CGU CPU Clock Reduction Register***/
- /*-----------------------------------*/
- switch(amazon_readl(AMAZON_CGU_CPUCRD) & 0x3){
- case 0:
- /*divider ration 1/1, 235 MHz clock */
- return 235000000;
- case 1:
- /*divider ration 2/3, 235 MHz clock, clock not accurate, here */
- return 150000000;
- case 2:
- /*divider ration 1/2, 235 MHz clock */
- return 117500000;
- default:
- /*divider ration 1/4, 235 MHz clock */
- return 58750000;
- }
-}
-
-/* the FPI clock rate - lifted from u-boot */
-unsigned int amazon_get_fpi_hz(void)
-{
- unsigned int clkCPU;
- clkCPU = amazon_get_cpu_hz();
-
- /*-------------------------------------*/
- /***CGU Clock Divider Select Register***/
- /*-------------------------------------*/
- switch (amazon_readl(AMAZON_CGU_DIV) & 0x3)
- {
- case 1:
- return clkCPU >> 1;
- case 2:
- return clkCPU >> 2;
- default:
- return clkCPU;
- /* '11' is reserved */
- }
-}
-EXPORT_SYMBOL(amazon_get_fpi_hz);
-
-/* this doesn't really belong here, but it's a convenient location */
-unsigned int amazon_get_cpu_ver(void)
-{
- static unsigned int cpu_ver = 0;
- if (cpu_ver == 0)
- cpu_ver = amazon_readl(AMAZON_MCD_CHIPID) & 0xFFFFF000;
- return cpu_ver;
-}
-
-static inline u32 amazon_get_counter_resolution(void)
-{
- u32 res;
- __asm__ __volatile__(
- ".set push\n"
- ".set mips32r2\n"
- ".set noreorder\n"
- "rdhwr %0, $3\n"
- "ehb\n"
- ".set pop\n"
- : "=&r" (res)
- : /* no input */
- : "memory");
- instruction_hazard();
- return res;
-}
-
-void __init plat_time_init(void)
-{
- mips_hpt_frequency = amazon_get_cpu_hz() / amazon_get_counter_resolution();
- r4k_offset = mips_hpt_frequency / HZ;
- printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);
- printk("r4k_offset: %08x(%d)\n", r4k_offset, r4k_offset);
-
- r4k_cur = (read_c0_count() + r4k_offset);
- write_c0_compare(r4k_cur);
-
- /* enable the timer in the PMU */
- amazon_writel(amazon_readl(AMAZON_PMU_PWDCR)| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI, AMAZON_PMU_PWDCR);
-
- /* setup the GPTU for timer tick f_fpi == f_gptu*/
- amazon_writel(0x0100, AMAZON_GPTU_CLC);
- amazon_writel(0xffff, AMAZON_GPTU_CAPREL);
- amazon_writel(0x80C0, AMAZON_GPTU_T6CON);
-}
-
-void __init plat_mem_setup(void)
-{
- u32 chipid = 0;
- u32 part_no = 0;
-
- chipid = amazon_readl(AMAZON_MCD_CHIPID);
- part_no = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid);
-
- if(part_no == AMAZON_CHIPID_YANGTSE){
- printk("Yangtse Version\n");
- } else if (part_no == AMAZON_CHIPID_STANDARD) {
- printk(SYSTEM_MODEL_NAME "\n");
- } else {
- printk("unknown version %8x\n",part_no);
- }
-
- amazon_reboot_setup();
-
- //stop reset TPE and DFE
- amazon_writel(0, AMAZON_RST_REQ);
- //clock
- amazon_writel(0x3fff, AMAZON_PMU_PWDCR);
- //reenable trace capability
- part_no = readl(AMAZON_BCU_ECON);
-
- ioport_resource.start = IOPORT_RESOURCE_START;
- ioport_resource.end = IOPORT_RESOURCE_END;
- iomem_resource.start = IOMEM_RESOURCE_START;
- iomem_resource.end = IOMEM_RESOURCE_END;
-}
-
-static void amazon_machine_restart(char *command)
-{
- local_irq_disable();
- amazon_writel(AMAZON_RST_ALL, AMAZON_RST_REQ);
- for (;;) ;
-}
-
-static void amazon_machine_halt(void)
-{
- printk(KERN_NOTICE "System halted.\n");
- local_irq_disable();
- for (;;) ;
-}
-
-static void amazon_machine_power_off(void)
-{
- printk(KERN_NOTICE "Please turn off the power now.\n");
- local_irq_disable();
- for (;;) ;
-}
-
-static void amazon_reboot_setup(void)
-{
- _machine_restart = amazon_machine_restart;
- _machine_halt = amazon_machine_halt;
- pm_power_off = amazon_machine_power_off;
-}
+++ /dev/null
-#ifndef __AMAZON_IRQ_H
-#define __AMAZON_IRQ_H
-
-#define NR_IRQS 256
-#include_next <irq.h>
-
-#endif
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 2004 Ralf Baechle
- */
-#ifndef __ASM_MACH_AMAZON_MANGLE_PORT_H
-#define __ASM_MACH_AMAZON_MANGLE_PORT_H
-
-#define __swizzle_addr_b(port) (port)
-#define __swizzle_addr_w(port) ((port) ^ 2)
-#define __swizzle_addr_l(port) (port)
-#define __swizzle_addr_q(port) (port)
-
-/*
- * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
- * less sane hardware forces software to fiddle with this...
- *
- * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
- * you can't have the numerical value of data and byte addresses within
- * multibyte quantities both preserved at the same time. Hence two
- * variations of functions: non-prefixed ones that preserve the value
- * and prefixed ones that preserve byte addresses. The latters are
- * typically used for moving raw data between a peripheral and memory (cf.
- * string I/O functions), hence the "__mem_" prefix.
- */
-#if defined(CONFIG_SWAP_IO_SPACE)
-
-# define ioswabb(a, x) (x)
-# define __mem_ioswabb(a, x) (x)
-# define ioswabw(a, x) le16_to_cpu(x)
-# define __mem_ioswabw(a, x) (x)
-# define ioswabl(a, x) le32_to_cpu(x)
-# define __mem_ioswabl(a, x) (x)
-# define ioswabq(a, x) le64_to_cpu(x)
-# define __mem_ioswabq(a, x) (x)
-
-#else
-
-# define ioswabb(a, x) (x)
-# define __mem_ioswabb(a, x) (x)
-# define ioswabw(a, x) (x)
-# define __mem_ioswabw(a, x) cpu_to_le16(x)
-# define ioswabl(a, x) (x)
-# define __mem_ioswabl(a, x) cpu_to_le32(x)
-# define ioswabq(a, x) (x)
-# define __mem_ioswabq(a, x) cpu_to_le32(x)
-
-#endif
-
-#endif /* __ASM_MACH_AMAZON_MANGLE_PORT_H */
+++ /dev/null
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- */
-#ifndef __ASM_MIPS_MACH_AMAZON_WAR_H
-#define __ASM_MIPS_MACH_AMAZON_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
-#define R4600_V1_HIT_CACHEOP_WAR 0
-#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
-#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
-#define RM9000_CDEX_SMP_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
-#define R10000_LLSC_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
-
-#endif
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- */
-//-----------------------------------------------------------------------
-/*
- * Description:
- * Driver for Infineon Amazon TPE
- */
-//-----------------------------------------------------------------------
-/* Author: peng.liu@infineon.com
- * Created: 12-April-2004
- */
-//-----------------------------------------------------------------------
-/* History
- * Last changed on: 13 Oct. 2004
- * Last changed by: peng.liu@infineon.com
- * Last changed on: 28 Jan. 2004
- * Last changed by: peng.liu@infineon.com
- * Last changed Reason:
- * - AAL5R may send more bytes than expected in MFL (so far, confirmed as 64 bytes)
- */
-// 507261:tc.chen 2005/07/26 re-organize code address map to improve performance.
-// 507281:tc.chen 2005/07/28 fix f4 segment isssue
-/* 511045:linmars 2005/11/04 from Liu.Peng: change NRT_VBR bandwidth calculation based on scr instead of pcr */
-
-#ifndef __KERNEL__
-#define __KERNEL__
-#endif
-#ifndef EXPORT_SYMTAB
-#define EXPORT_SYMTAB
-#endif
-
-/*TPE level loopback, bypass AWARE DFE */
-#undef TPE_LOOPBACK
-
-/* enable debug options */
-#undef AMAZON_ATM_DEBUG
-
-/* enable rx error packet analysis */
-#undef AMAZON_ATM_DEBUG_RX
-
-/* test AAL5 Interrupt */
-#undef AMAZON_TPE_TEST_AAL5_INT
-
-/* dump packet */
-#undef AMAZON_TPE_DUMP
-
-/* read ARC register*/
-/* this register is located in side DFE module*/
-#undef AMAZON_TPE_READ_ARC
-
-/* software controlled reassembly */
-#undef AMAZON_TPE_SCR
-
-/* recovery from AAL5 bug */
-#undef AMAZON_TPE_AAL5_RECOVERY
-
-#if defined(AMAZON_TPE_READ_ARC) || defined(AMAZON_TPE_AAL5_RECOVERY)
-#define ALPHAEUS_BASE_ADDR 0x31c00
-#define A_CFG_ADDR (ALPHAEUS_BASE_ADDR+0x04)
-#define AR_CB0_STATUS_ADDR (ALPHAEUS_BASE_ADDR+0x2c)
-#define AR_CB1_STATUS_ADDR (ALPHAEUS_BASE_ADDR+0x30)
-#define AT_CELL0_ADDR (ALPHAEUS_BASE_ADDR+0x90)
-#define AR_CELL0_ADDR (ALPHAEUS_BASE_ADDR+0x1a0)
-#define AR_CD_CNT0_ADDR (ALPHAEUS_BASE_ADDR+0x1c8)
-#endif
-
-#include <linux/module.h>
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/fs.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/time.h>
-#include <linux/atm.h>
-#include <linux/atmdev.h>
-#include <linux/netdevice.h>
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/uaccess.h>
-#include <asm/system.h>
-#include <asm/atomic.h>
-#include <asm/bitops.h>
-#include <asm/system.h>
-
-#include <asm/amazon/amazon.h>
-#include <asm/amazon/irq.h>
-
-#include <linux/in.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/ip.h>
-#include <linux/tcp.h>
-#include <linux/skbuff.h>
-#include <linux/in6.h>
-#include <linux/delay.h>
-#include <asm/amazon/atm_defines.h>
-#include <asm/amazon/amazon_dma.h>
-#include <asm/amazon/amazon_tpe.h>
-
-#if defined(AMAZON_TPE_READ_ARC) || defined(AMAZON_TPE_AAL5_RECOVERY)
-#include <asm/amazon/amazon_mei.h>
-#include <asm/amazon/amazon_mei_app.h>
-#endif
-
-#define AMAZON_TPE_EMSG(fmt, args...) printk( KERN_ERR "%s: " fmt,__FUNCTION__, ## args)
-
-/***************************************** External Functions *******************************************/
-extern unsigned int amazon_get_fpi_hz(void);
-extern void mask_and_ack_amazon_irq(unsigned int irq_nr);
-extern void amz_push_oam(unsigned char *);
-
-//amazon_mei.c
-#if defined(AMAZON_TPE_READ_ARC) || defined(AMAZON_TPE_AAL5_RECOVERY)
-extern MEI_ERROR meiDebugRead(u32 srcaddr, u32 *databuff, u32 databuffsize);
-extern MEI_ERROR meiDebugWrite(u32 destaddr, u32 *databuff, u32 databuffsize);
-#endif
-
-/***************************************** Internal Functions *******************************************/
-int amazon_atm_read_procmem(char *buf, char **start, off_t offset,int count, int *eof, void *data);
-/***************************************** Global Data *******************************************/
-amazon_atm_dev_t g_atm_dev; //device data
-static struct tq_struct swex_start_task; //BH task
-static struct tq_struct swex_complete_task; //BH task
-#ifdef AMAZON_TPE_SCR
-static struct tq_struct a5r_task; //BH task
-#endif
-static struct dma_device_info g_dma_dev; //for DMA
-static struct atm_dev * amazon_atm_devs[AMAZON_ATM_PORT_NUM];
-static struct oam_last_activity g_oam_time_stamp[AMAZON_ATM_MAX_VCC_NUM];
-static u8 g_oam_cell[AMAZON_AAL0_SDU+4]; //for OAM cells
-#ifdef AMAZON_CHECK_LINK
-static int adsl_link_status; //ADSL link status, 0:down, 1:up
-#endif //AMAZON_CHECK_LINK
-/***************************************** Module Parameters *************************************/
-// Parameter Definition for module
-static int port_enable0 = 1; // Variable for parameter port_enable0
-static int port_enable1 = 0; // Variable for parameter port_enable1
-static int port_max_conn0 = 15; // Variable for parameter port_max_conn0
-static int port_max_conn1 = 0; // Variable for parameter port_max_conn1
-static int port_cell_rate_up0 = 7500; // Variable for parameter port_cell_rate_up0
-static int port_cell_rate_up1 = 7500; // Variable for parameter port_cell_rate_up1
-
-
-static int qsb_tau = 1; // Variable for parameter qsb_tau
-static int qsb_srvm = 0xf; // Variable for parameter qsb_srvm
-static int qsb_tstep = 4 ; // Variable for parameter qsb_tstep
-
-static int cbm_nrt = 3900; // Variable for parameter cbm_nrt
-static int cbm_clp0 =3500; // Variable for parameter cbm_clp0
-static int cbm_clp1 =3200; // Variable for parameter cbm_clp1
-static int cbm_free_cell_no = AMAZON_ATM_FREE_CELLS; // Variable for parameter cbm_free_cell_no
-
-static int a5_fill_pattern = 0x7e; // Variable for parameter a5_fill_pattern '~'
-static int a5s_mtu = 0x700; // mtu for tx
-static int a5r_mtu = 0x700; // mtu for rx
-
-static int oam_q_threshold = 64; // oam queue threshold, minium value 64
-static int rx_q_threshold = 1000; // rx queue threshold, minium value 64
-static int tx_q_threshold = 800; // tx queue threshold, minium value 64
-
-MODULE_PARM(port_max_conn0, "i");
-MODULE_PARM_DESC(port_max_conn0, "Maximum atm connection for port #0");
-MODULE_PARM(port_max_conn1, "i");
-MODULE_PARM_DESC(port_max_conn1, "Maximum atm connection for port #1");
-MODULE_PARM(port_enable0, "i");
-MODULE_PARM_DESC(port_enable0, "0 -> port disabled, 1->port enabled");
-MODULE_PARM(port_enable1, "i");
-MODULE_PARM_DESC(port_enable1, "0 -> port disabled, 1->port enabled");
-MODULE_PARM(port_cell_rate_up0, "i");
-MODULE_PARM_DESC(port_cell_rate_up0, "ATM port upstream rate in cells/s");
-MODULE_PARM(port_cell_rate_up1, "i");
-MODULE_PARM_DESC(port_cell_rate_up1, "ATM port upstream rate in cells/s");
-
-MODULE_PARM(qsb_tau,"i");
-MODULE_PARM_DESC(qsb_tau, "Cell delay variation. value must be > 0");
-MODULE_PARM(qsb_srvm, "i");
-MODULE_PARM_DESC(qsb_srvm, "Maximum burst size");
-MODULE_PARM(qsb_tstep, "i");
-MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4");
-
-MODULE_PARM(cbm_nrt, "i");
-MODULE_PARM_DESC(cbm_nrt, "Non real time threshold for cell buffer");
-MODULE_PARM(cbm_clp0, "i");
-MODULE_PARM_DESC(cbm_clp0, "Threshold for cells with cell loss priority 0");
-MODULE_PARM(cbm_clp1, "i");
-MODULE_PARM_DESC(cbm_clp1, "Threshold for cells with cell loss priority 1");
-MODULE_PARM(cbm_free_cell_no, "i");
-MODULE_PARM_DESC(cbm_free_cell_no, "Number of cells in the cell buffer manager");
-
-MODULE_PARM(a5_fill_pattern, "i");
-MODULE_PARM_DESC(a5_fill_pattern, "filling pattern (PAD) for aal5 frames");
-MODULE_PARM(a5s_mtu, "i");
-MODULE_PARM_DESC(a5s_mtu, "max. SDU for upstream");
-MODULE_PARM(a5r_mtu, "i");
-MODULE_PARM_DESC(a5r_mtu, "max. SDU for downstream");
-
-MODULE_PARM(oam_q_threshold, "i");
-MODULE_PARM_DESC(oam_q_threshold, "oam queue threshold");
-
-MODULE_PARM(rx_q_threshold, "i");
-MODULE_PARM_DESC(rx_q_threshold, "downstream/rx queue threshold");
-
-MODULE_PARM(tx_q_threshold, "i");
-MODULE_PARM_DESC(tx_q_threshold, "upstream/tx queue threshold");
-
-/***************************************** local functions *************************************/
-/* Brief: valid QID
- * Return: 1 if valid
- * 0 if not
- */
-static inline int valid_qid(int qid)
-{
- return ( (qid>0) && (qid<AMAZON_ATM_MAX_QUEUE_NUM));
-}
-
-/*
- * Brief: align to 16 bytes boundary
- * Parameter:
- * skb
- * Description:
- * use skb_reserve to adjust the data pointer
- * don't change head pointer
- * pls allocate extrac 16 bytes before call this function
- */
-static void inline alloc_align_16(struct sk_buff * skb)
-{
- if ( ( ((u32) (skb->data)) & 15) != 0){
- AMAZON_TPE_DMSG("need to adjust the alignment manually\n");
- skb_reserve(skb, 16 - (((u32) (skb->data)) & 15) );
- }
-
-}
-
-/*
- * Brief: initialize the device according to the module paramters
- * Return: not NULL - ok
- * NULL - fails
- * Description: arrange load parameters and call the hardware initialization routines
- */
-static void atm_init_parameters(amazon_atm_dev_t *dev)
-{
- //port setting
- dev->ports[0].enable = port_enable0;
- dev->ports[0].max_conn = port_max_conn0;
- dev->ports[0].tx_max_cr = port_cell_rate_up0;
- if (port_enable1){
- dev->ports[1].enable = port_enable1;
- dev->ports[1].max_conn = port_max_conn1;
- dev->ports[1].tx_max_cr = port_cell_rate_up1;
- }
-
- //aal5
- dev->aal5.padding_byte = a5_fill_pattern;
- dev->aal5.tx_max_sdu = a5s_mtu;
- dev->aal5.rx_max_sdu = a5r_mtu;
-
- //cbm
- dev->cbm.nrt_thr = cbm_nrt;
- dev->cbm.clp0_thr = cbm_clp0;
- dev->cbm.clp1_thr = cbm_clp1;
- dev->cbm.free_cell_cnt = cbm_free_cell_no;
-
- //qsb
- dev->qsb.tau = qsb_tau;
- dev->qsb.tstepc =qsb_tstep;
- dev->qsb.sbl = qsb_srvm;
-
- //allocate on the fly
- dev->cbm.mem_addr = NULL;
- dev->cbm.qd_addr = NULL;
-}
-
-
-/* Brief: Find QID for VCC
- * Parameters: vcc - VCC data structure
- * Return Value: -EINVAL - VCC not found
- * qid - QID for this VCC
- * Description:
- * This function returns the QID of a given VCC
- */
-static int amazon_atm_get_queue(struct atm_vcc* vcc)
-{
- int i;
- for (i=0;i<AMAZON_ATM_MAX_QUEUE_NUM;i++) {
- if (g_atm_dev.queues[i].vcc == vcc) return i;
- }
- return -EINVAL;
-}
-
-
-/*
- * Brief: Find QID for VPI/VCI
- * Parameters: vpi - VPI to found
- * vci - VCI to found
- *
- * Return Value: -EINVAL - VPI/VCI not found
- * qid - QID for this VPI/VCI
- *
- * Description:
- * This function returns the QID for a given VPI/VCI. itf doesn't matter
- */
-static int amazon_atm_find_vpivci(u8 vpi, u16 vci)
-{
- int i;
- struct atm_vcc * vcc;
- for (i=0;i<AMAZON_ATM_MAX_QUEUE_NUM;i++) {
- if ( (vcc = g_atm_dev.queues[i].vcc)!= NULL) {
- if ((vcc->vpi == vpi) && (vcc->vci == vci)) return i;
- }
- }
- return -EINVAL;
-}
-
-/* Brief: Find QID for VPI
- * Parameters: vpi - VPI to found
- * Return Value: -EINVAL - VPI not found
- * qid - QID for this VPI
- *
- * Description:
- * This function returns the QID for a given VPI. itf and VCI don't matter
- */
-static int amazon_atm_find_vpi(u8 vpi)
-{
- int i;
- for (i=0;i<AMAZON_ATM_MAX_QUEUE_NUM;i++) {
- if ( g_atm_dev.queues[i].vcc!= NULL) {
- if (g_atm_dev.queues[i].vcc->vpi == vpi) return i;
- }
- }
- return -EINVAL;
-}
-
-/*
- * Brief: Clears QID entries for VCC
- *
- * Parameters: vcc - VCC to found
- *
- * Description:
- * This function searches for the given VCC and sets it to NULL if found.
- */
-static inline void amazon_atm_clear_vcc(int i)
-{
- g_atm_dev.queues[i].vcc = NULL;
- g_atm_dev.queues[i].free = 1;
-}
-
-
-/*
- * Brief: dump skb data
- */
-static inline void dump_skb(u32 len, char * data)
-{
-#ifdef AMAZON_TPE_DUMP
- int i;
- for(i=0;i<len;i++){
- printk("%2.2x ",(u8)(data[i]));
- if (i % 16 == 15)
- printk("\n");
- }
- printk("\n");
-#endif
-}
-
-/*
- * Brief: dump queue descriptor
- */
-static inline void dump_qd(int qid)
-{
-#ifdef AMAZON_TPE_DUMP
- u8 * qd_addr;
- if (valid_qid(qid) != 1) return;
- qd_addr = (u8 *) KSEG1ADDR((unsigned long)g_atm_dev.cbm.qd_addr);
- AMAZON_TPE_EMSG("qid: %u [%8x][%8x][%8x][%8x]\n", qid
- ,readl(qd_addr+qid*CBM_QD_SIZE+0x0)
- ,readl(qd_addr+qid*CBM_QD_SIZE+0x4)
- ,readl(qd_addr+qid*CBM_QD_SIZE+0x8)
- ,readl(qd_addr+qid*CBM_QD_SIZE+0xc));
-#endif
-}
-
-/*
- * Brief: release TX skbuff
- */
-static inline void amazon_atm_free_tx_skb_vcc(struct atm_vcc *vcc, struct sk_buff *skb)
-{
- if ( vcc->pop != NULL) {
- vcc->pop(vcc, skb);
- } else {
- dev_kfree_skb_any(skb);
- }
-}
-/*
- * Brief: release TX skbuff
- */
-static inline void amazon_atm_free_tx_skb(struct sk_buff *skb)
-{
- struct atm_vcc* vcc = ATM_SKB(skb)->vcc;
- if (vcc!=NULL){
- amazon_atm_free_tx_skb_vcc(vcc,skb);
- } else {
- dev_kfree_skb_any(skb);//fchang:Added
- }
-}
-
-/* Brief: divide by 64 and round up
- */
-static inline u32 divide_by_64_round_up(int input)
-{
- u32 tmp1;
- tmp1 = (u32) input;
- tmp1 = (tmp1%64)?(tmp1/64 + 1): (tmp1/64);
- if (tmp1 == 0) tmp1 = 1;
- return tmp1;
-}
-
-/*
- * Brief: statistics
- */
-#ifdef AMAZON_ATM_DEBUG
-static inline void queue_statics(int qid, qs_t idx)
-{
- if (valid_qid(qid)){
- g_atm_dev.queues[qid].qs[idx]++;
- }
-}
-#else //not AMAZON_ATM_DEBUG
-static inline void queue_statics(int qid, qs_t idx){}
-#endif //AMAZON_ATM_DEBUG
-
-
-/* Brief: set dma tx full, i.e. there is no available descriptors
- */
-static void inline atm_dma_full(void)
-{
- AMAZON_TPE_DMSG("ch0 is full\n");
- atomic_set(&g_atm_dev.dma_tx_free_0,0);
-}
-
-/*
- * Brief set dma tx free (at least one descript is available)
- */
-inline static void atm_dma_free(void)
-{
- AMAZON_TPE_DMSG("ch0 is free\n");
- atomic_set(&g_atm_dev.dma_tx_free_0,1);
-}
-
-
-/* Brief: return the status of DMA TX descriptors
- * Parameters: TX channel (DMA_TX_CH0, TX_CH1)
- * Return:
- * 1: there are availabel TX descriptors
- * 0: no available
- * Description:
- *
- */
-inline int dma_may_send(int ch)
-{
- if (atomic_read(&g_atm_dev.dma_tx_free_0)){
- return 1;
- }
- return 0;
-}
-
-/******************************* global functions *********************************/
-/*
- * Brief: SWIE Cell Extraction Start Routine
- * and task routine for swex_complete_task
- * Parameters: irq_stat - interrupt status
- *
- * Description:
- * This is the routine for extracting cell. It will schedule itself if the hardware is busy.
- * This routine runs in interrupt context
- */
-void amazon_atm_swex(void * irq_stat)
-{
- u32 ex_stat=0;
- u32 addr;
- // Read extraction status register
- ex_stat = readl(CBM_HWEXSTAT0_ADDR);
-
- // Check if extraction/insertion is in progress
- if ( (ex_stat & CBM_EXSTAT_SCB) || (ex_stat & CBM_EXSTAT_FB) || (test_and_set_bit(SWIE_LOCK, &(g_atm_dev.swie.lock))!=0)) {
- AMAZON_TPE_DMSG(" extraction in progress. Will wait\n");
- swex_start_task.data = irq_stat;
- queue_task(&swex_start_task, &tq_immediate);
- mark_bh(IMMEDIATE_BH);
- }else {
- // Extract QID
- g_atm_dev.swie.qid = (((u32)irq_stat) >> 24);
- AMAZON_TPE_DMSG("extracting from qid=%u\n",g_atm_dev.swie.qid);
- //read status word
- addr = KSEG1ADDR((unsigned long)g_atm_dev.cbm.qd_addr);
- addr = readl((addr + g_atm_dev.swie.qid * 0x10 + 4) & 0xFFFFFFC0);
- addr = KSEG1ADDR(addr);
- g_atm_dev.swie.sw = readl(addr+52)&SWIE_ADDITION_DATA_MASK;
- AMAZON_TPE_DMSG("cell addition word: %8x \n", g_atm_dev.swie.sw);
-
- // Start extraction
- AMAZON_WRITE_REGISTER_L(g_atm_dev.swie.qid | SWIE_CBM_PID_SUBADDR, CBM_HWEXPAR0_ADDR);
- AMAZON_WRITE_REGISTER_L(SWIE_CBM_SCE0, CBM_HWEXCMD_ADDR);
- }
-}
-#ifdef AMAZON_TPE_SCR
-u32 g_a5r_wait=0;
-/*
- * Brief: AAL5 Packet Extraction Routine and task routine for a5r_task
- * Parameters: irq_stat - interrupt status
- *
- * Description:
- * This is the routine for extracting frame. It will schedule itself if the hardware is busy.
- * This routine runs in interrupt context
- */
-void amazon_atm_a5r(void* qid)
-{
- volatile u32 ex_stat=0;
- u32 addr;
- u32 a5r_wait=0;
-
- ex_stat = readl(CBM_HWEXSTAT0_ADDR);
-#if 0
- // Check if extraction/insertion is in progress
- if ( (ex_stat & CBM_EXSTAT_SCB) || (ex_stat & CBM_EXSTAT_FB) ) {
- AMAZON_TPE_DMSG(" extraction in progress. Will wait\n");
- a5r_task.data = qid;
- queue_task(&a5r_task, &tq_immediate);
- mark_bh(IMMEDIATE_BH);
- }else {
- AMAZON_TPE_DMSG("extracting from qid=%u\n",(u8)qid);
- // Start extraction
- AMAZON_WRITE_REGISTER_L(((u8)qid) | CBM_HWEXPAR_PN_A5, CBM_HWEXPAR0_ADDR);
- AMAZON_WRITE_REGISTER_L(CBM_HWEXCMD_FE0, CBM_HWEXCMD_ADDR);
- }
-#else
- //while ( (ex_stat & CBM_EXSTAT_SCB) || (ex_stat & CBM_EXSTAT_FB) ) {
- while ( ex_stat != 0x80){
- a5r_wait++;
- ex_stat = readl(CBM_HWEXSTAT0_ADDR);
-#if 0
- if (a5r_wait >= 0xffffff){
- a5r_wait=0;
- printk(".");
- }
-#endif
- }
- if (a5r_wait > g_a5r_wait){
- g_a5r_wait = a5r_wait;
- }
- AMAZON_WRITE_REGISTER_L(((u8)qid) | CBM_HWEXPAR_PN_A5, CBM_HWEXPAR0_ADDR);
- AMAZON_WRITE_REGISTER_L(CBM_HWEXCMD_FE0, CBM_HWEXCMD_ADDR);
-#endif
-}
-
-#endif //AMAZON_TPE_SCR
-
-/* Brief: Handle F4/F5 OAM cell
- * Return:
- * 0 ok
- * <0 fails
- */
-static int inline amazon_handle_oam_cell(void *data, u8 vpi, u16 vci,u32 status)
-{
- struct atm_vcc* vcc=NULL;
- int qid;
- if (!status&SWIE_EOAM_MASK){
- AMAZON_TPE_EMSG("unknown cell received, discarded\n");
- goto amazon_handle_oam_cell_err_exit;
- }else if (status&SWIE_ECRC10ERROR_MASK){
- AMAZON_TPE_EMSG("CRC-10 Error Status:%8x, discarded\n", status);
- goto amazon_handle_oam_cell_err_exit;
- }else{
- if(status & (SWIE_EVCI3_MASK |SWIE_EVCI4_MASK)){
- //F4 level (VPI) OAM, Assume duplex
- qid = amazon_atm_find_vpi(vpi)+CBM_RX_OFFSET;
- }else if (status & (SWIE_EPTI4_MASK|SWIE_EPTI5_MASK)){
- //F5 level (VCI) OAM, Assume duplex
- qid = amazon_atm_find_vpivci(vpi,vci)+CBM_RX_OFFSET;
- }else{
- qid = -1;
- AMAZON_TPE_EMSG("non-F4/F5 OAM cells?, discarded\n");
- goto amazon_handle_oam_cell_err_exit;
- }
- }
- if (valid_qid(qid) && ((vcc = g_atm_dev.queues[qid].vcc)!=NULL)){
- //TODO, should we do this for ALL OAM types? (Actually only User and CC)
- g_atm_dev.queues[qid].access_time=xtime;
- if (vcc->push_oam){
- (*vcc->push_oam)(vcc,data);
- }else{
- amz_push_oam(data);
- }
- }else{
- AMAZON_TPE_EMSG("no VCC yet\n");
- goto amazon_handle_oam_cell_err_exit;
- }
- return 0;
-amazon_handle_oam_cell_err_exit:
- dump_skb(AMAZON_AAL0_SDU,(char *)data);
- return -1;
-}
-
-/* Brief: SWIE Cell Extraction Finish Routine
- * and task routine for swex_complete_task
- * Description:
- * 1.Allocate a buffer of type struct sk_buff
- * 2.Copy the data from the temporary memory to this buffer
- * 3.Push the data to upper layer
- * 4.Update the statistical data if necessary
- * 5.Release the temporary data
-
- */
-void amazon_atm_swex_push(void * data)
-{
- struct atm_vcc* vcc=NULL;
- struct sk_buff* skb=NULL;
- struct amazon_atm_cell_header * cell_header;
- u32 status;
- int qid;
- if (!data){
- AMAZON_TPE_EMSG("data is NULL\n");
- return;
- }
- qid = ((u8*)data)[AMAZON_AAL0_SDU];
- status = ((u32*)data)[ATM_AAL0_SDU/4];
- cell_header = (struct amazon_atm_cell_header *) data;
- if (valid_qid(qid) != 1){
- AMAZON_TPE_EMSG("error qid: %u\n",qid);
- AMAZON_TPE_EMSG("unknown cells recieved\n");
- }else if (qid == AMAZON_ATM_OAM_Q_ID){
- //OAM or RM or OTHER cell
- //Find real connection
-
-#ifdef IKOS_MINI_BOOT
- //for OAM loop back test
- dump_skb(56,(char *)data);
- //kfree(data); using g_oam_cell
- return;
-#endif //IKOS_MINI_BOOT
-#ifdef TPE_LOOPBACK
- amz_push_oam(data);
- return;
-#endif//TPE_LOOPBACK
- int ret = 0;
- ret = amazon_handle_oam_cell(data,cell_header->bit.vpi,cell_header->bit.vci,status);
- if (ret == 0)
- return;
- }else{
- //should be normal AAL0 cells
- // Get VCC
- vcc = g_atm_dev.queues[qid].vcc;
- if (vcc != NULL) {
- AMAZON_TPE_DMSG("push to upper layer\n");
- skb = dev_alloc_skb(AMAZON_AAL0_SDU);
- if (skb != NULL) {
- //skb->dev=vcc->dev;
- memcpy(skb_put(skb, AMAZON_AAL0_SDU), data, AMAZON_AAL0_SDU);
- skb->stamp = xtime;
- ATM_SKB(skb)->vcc = vcc;
- (*g_atm_dev.queues[qid].push)(vcc,skb,0);
- }else{
- AMAZON_TPE_EMSG(" No memory left for incoming AAL0 cell! Cell discarded!\n");
- //inform the upper layer
- (*g_atm_dev.queues[qid].push)(vcc,skb,-ENOMEM);
- atomic_inc(&vcc->stats->rx_drop);
- }
- }else{
- AMAZON_TPE_EMSG("invalid qid %u\n",qid);
- }
- }
- //kfree(data); using g_oam_cell
-}
-
-/*
- * Brief: Interrupt handler for software cell extraction (done)
- * Parameters: irq - CPPN for this interrupt
- * data - Device ID for this interrupt
- * regs - Register file
- *
- * Description:
- * When a software extraction is finished this interrupt is issued.
- * It reads the cell data and sends it to the ATM stack.
- */
-void amazon_atm_swex_isr(int irq, void *data, struct pt_regs *regs)
-{
- u32 * cell = NULL;
- int i;
- //ATM_AAL0 SDU + QID
- AMAZON_TPE_DMSG("SWIE extraction done\n");
- cell = (u32 *) g_oam_cell;
- if (cell != NULL){
- //convert to host byte order from big endian
- for(i=0;i<ATM_AAL0_SDU;i+=4){
- cell[i/4]=readl(SWIE_ECELL_ADDR+i);
- }
- cell[ATM_AAL0_SDU/4]= g_atm_dev.swie.sw;
- ((u8*)cell)[AMAZON_AAL0_SDU] = g_atm_dev.swie.qid;
-#ifdef IKOS_MINI_BOOT
- for(i=0;i<ATM_AAL0_SDU;i+=4){
- AMAZON_TPE_DMSG("[%2x][%2x][%2x][%2x]\n",
- ((char*)cell)[i],
- ((char*)cell)[i+1],
- ((char*)cell)[i+2],
- ((char*)cell)[i+3]
- );
- }
- AMAZON_TPE_DMSG("qid: %u\n", ((u8*)cell)[AMAZON_AAL0_SDU]);
- amazon_atm_swex_push((void *) cell);
-#else //not IKOS_MINI_BOOT
- swex_complete_task.data = cell;
- queue_task(&swex_complete_task,&tq_immediate);
- mark_bh(IMMEDIATE_BH);
-#endif //not IKOS_MINI_BOOT
- }else{
- AMAZON_TPE_EMSG("no memory for receiving AAL0 cell\n");
- }
-
- /* release the lock and check */
- if (test_and_clear_bit(SWIE_LOCK,&(g_atm_dev.swie.lock)) == 0){
- AMAZON_TPE_EMSG("swie lock is already released\n");
- }
- wake_up(&g_atm_dev.swie.sleep);
-}
-/* Brief: Interrupt handler for software cell insertion
- *
- * Parameters: irq - CPPN for this interrupt
- * data - Device ID for this interrupt
- * regs - Register file
- *
- * Description:
- * When a software insertion is finished this interrupt is issued.
- * The only purpose is to release the semaphore and read the status register.
- */
-void amazon_atm_swin_isr(int irq, void *data, struct pt_regs *regs)
-{
- AMAZON_TPE_DMSG("SWIE insertion done\n");
- /* release the lock and check */
- if (test_and_clear_bit(SWIE_LOCK,&(g_atm_dev.swie.lock)) == 0){
- AMAZON_TPE_EMSG("swie lock is already released");
- }
- // Release semaphore
- up(&g_atm_dev.swie.in_sem);
-
-}
-/* Brief: Interrupt handler for software cell insertion & extraction
- * Parameters: irq - CPPN for this interrupt
- * data - Device ID for this interrupt
- * regs - Register file
- * Description:
- * When a software insertion or extractionis finished this interrupt is issued.
- */
-void amazon_atm_swie_isr(int irq, void *data, struct pt_regs *regs)
-{
- u32 status=0;
- // Read status register
- status = readl(SWIE_ISTAT_ADDR);
- AMAZON_TPE_DMSG("insertion status: %8x\n", status);
- if (status & SWIE_ISTAT_DONE){
- //clear interrupt in peripheral and ICU
- AMAZON_WRITE_REGISTER_L(SRC_TOS_MIPS | SRC_CLRR|SRC_SRE_ENABLE | AMAZON_SWIE_INT, SWIE_ISRC_ADDR);
- mask_and_ack_amazon_irq(AMAZON_SWIE_INT);
-
- amazon_atm_swin_isr(irq,data,regs);
- }
- status = readl(SWIE_ESTAT_ADDR);
- AMAZON_TPE_DMSG("extraction status: %8x\n", status);
- if (status & SWIE_ESTAT_DONE){
- //clear interrupt
- AMAZON_WRITE_REGISTER_L(SRC_TOS_MIPS | SRC_CLRR|SRC_SRE_ENABLE | AMAZON_SWIE_INT, SWIE_ESRC_ADDR);
- mask_and_ack_amazon_irq(AMAZON_SWIE_INT);
-
- amazon_atm_swex_isr(irq,data,regs);
- }
- //clear interrupt in ICU
-}
-
-/*
- * Brief: Insert ATM cell into CBM
- * Parameters: queue - Target queue
- * cell - Pointer to cell data
- * Return Value: EBUSY - CBM is busy
- * 0 - OK, cell inserted
- * Description:
- * This function inserts a cell into the CBM using the software insertion
- * method. The format of the cell should be
- * Little Endian (address starting from 0)
- * H3, H2, H1, H0, P3, P2, P1, P0, P7, P6, P5, P4, ..., P47, P46, P45, P44
- * Big Endian (address starting from 0)
- * H0, H1, H2, H3, P0, P1, P2, P3, P4, P5, P6, P7, ..., P44, P45, P46, P47
- * This function does not free memory!!!
- */
-int amazon_atm_swin(u8 queue, void* cell)
-{
- u32 status=0;
- int i;
- // Read status register
- status = readl(SWIE_ISTAT_ADDR);
- AMAZON_TPE_DMSG(" SWIE status=0x%08x\n",status);
-
- AMAZON_TPE_DMSG(" Inserting cell qid=%u\n",queue);
-
-#ifdef AMAZON_CHECK_LINK
- if (adsl_link_status == 0){
- return -EFAULT;
- }
-#endif //AMAZON_CHECK_LINK
-
- // Get semaphore (if possible)
- if (down_interruptible(&g_atm_dev.swie.in_sem)) {
- return -ERESTARTSYS;
- }
- /* try to set lock */
- wait_event_interruptible(g_atm_dev.swie.sleep,(test_and_set_bit(SWIE_LOCK,&(g_atm_dev.swie.lock)) == 0));
- if (signal_pending(current)){
- return -ERESTARTSYS;
- }
-
- // Store cell in CBM memory
- for(i=0;i<ATM_AAL0_SDU;i+=4){
- AMAZON_WRITE_REGISTER_L(((u32*)cell)[i/4],SWIE_ICELL_ADDR+i);
- }
- //Store queue id
- AMAZON_WRITE_REGISTER_L((u32) queue,SWIE_IQID_ADDR);
-
- //Start SWIE
- AMAZON_WRITE_REGISTER_L(SWIE_ICMD_START,SWIE_ICMD_ADDR);
-
- return 0;
-}
-
-#ifdef AMAZON_ATM_DEBUG
-/*
- * Brief: Interrupt handler for HTU
- *
- * Parameters: irq - CPPN for this interrupt
- * data - Device ID for this interrupt
- * regs - Register file
- *
- */
-void amazon_atm_htu_isr(int irq, void *data, struct pt_regs *regs)
-{
- u32 irq_stat=0;
-
- // Read interrupt status register
- irq_stat = readl(HTU_ISR0_ADDR);
- AMAZON_TPE_DMSG("HTU status: %8x\n",irq_stat);
- //Clear interrupt in CBM and ICU
- AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS | SRC_SRE_ENABLE | AMAZON_HTU_INT, HTU_SRC0_ADDR);
- mask_and_ack_amazon_irq(AMAZON_HTU_INT);
- // Check if Any Cell Arrived
- if (irq_stat & (HTU_ISR_NE | HTU_ISR_PNE) ) {
- AMAZON_TPE_EMSG("INFNOENTRY %8x\n", readl(HTU_INFNOENTRY_ADDR));
- }else if (irq_stat & (HTU_ISR_TORD|HTU_ISR_PT)){
- AMAZON_TPE_EMSG("Time Out %8x\n", readl(HTU_INFTIMEOUT_ADDR));
- }else if (irq_stat & HTU_ISR_IT){
- AMAZON_TPE_EMSG("Interrupt Test\n");
- }else if (irq_stat & HTU_ISR_OTOC){
- AMAZON_TPE_EMSG("Overflow of Time Out Counter\n");
- }else if (irq_stat & HTU_ISR_ONEC){
- AMAZON_TPE_EMSG("Overflow of No Entry Counter\n");
- }else{
- AMAZON_TPE_EMSG("unknown HTU interrupt occurs %8x\n", irq_stat);
- }
-
-}
-#endif //AMAZON_ATM_DEBUG
-
-#ifdef AMAZON_TPE_TEST_AAL5_INT
-/*
- * Brief: Interrupt handler for AAL5
- *
- * Parameters: irq - CPPN for this interrupt
- * data - Device ID for this interrupt
- * regs - Register file
- *
- */
-void amazon_atm_aal5_isr(int irq, void *data, struct pt_regs *regs)
-{
- volatile u32 irq_stat=0;
-
- // Read interrupt status register
- irq_stat = readl(AAL5_SISR0_ADDR);
- if (irq_stat){
- AMAZON_TPE_EMSG("A5S status: %8x\n",irq_stat);
- //Clear interrupt in CBM and ICU
- AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS | SRC_SRE_ENABLE | AMAZON_AAL5_INT, AAL5_SSRC0_ADDR);
- mask_and_ack_amazon_irq(AMAZON_AAL5_INT);
- }
- irq_stat = readl(AAL5_RISR0_ADDR);
- if (irq_stat){
- AMAZON_TPE_EMSG("A5R status: %8x\n",irq_stat);
- //Clear interrupt in CBM and ICU
- AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS | SRC_SRE_ENABLE | AMAZON_AAL5_INT, AAL5_RSRC0_ADDR);
- mask_and_ack_amazon_irq(AMAZON_AAL5_INT);
- }
-}
-#endif //AMAZON_TPE_TEST_AAL5_INT
-
-/*
- * Brief: Interrupt handler for CBM
- *
- * Parameters: irq - CPPN for this interrupt
- * data - Device ID for this interrupt
- * regs - Register file
- *
- * Description:
- * This is the MIPS interrupt handler for the CBM. It processes incoming cells
- * for SWIE queues.
- */
-void amazon_atm_cbm_isr(int irq, void *data, struct pt_regs *regs)
-{
- u32 irq_stat=0;
- u8 qid=0;
-
- // Read interrupt status register
- while ( (irq_stat = readl(CBM_INTINF0_ADDR))){
- AMAZON_TPE_DMSG("CBM INT status: %8x\n",irq_stat);
- //Clear interrupt in CBM and ICU
- AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS | SRC_SRE_ENABLE | AMAZON_CBM_INT, CBM_SRC0_ADDR);
- qid = (u8) ((irq_stat & CBM_INTINF0_QID_MASK)>>CBM_INTINF0_QID_SHIFT);
-#ifdef AMAZON_TPE_SCR
- if (irq_stat & CBM_INTINF0_EF){
- amazon_atm_a5r((void*)qid);
- }
-#endif
- // Check if Any Cell Arrived
- if (irq_stat & CBM_INTINF0_ACA) {
- amazon_atm_swex((void *)irq_stat);
- }
- //TX AAL5 PDU discard
- if (irq_stat & CBM_INTINF0_OPF){
- if ( (qid) < CBM_RX_OFFSET ){
- g_atm_dev.mib_counter.tx_drop++;
- }
- queue_statics(qid, QS_HW_DROP);
- }
- if (irq_stat & (CBM_INTINF0_ERR|CBM_INTINF0_Q0E|CBM_INTINF0_Q0I|CBM_INTINF0_RDE)){
- AMAZON_TPE_EMSG("CBM INT status: %8x\n",irq_stat);
- if (irq_stat & CBM_INTINF0_ERR){
- AMAZON_TPE_EMSG("CBM Error: FPI Bus Error\n");
- }
- if (irq_stat & CBM_INTINF0_Q0E){
- AMAZON_TPE_EMSG("CBM Error: Queue 0 Extract\n");
- }
- if (irq_stat & CBM_INTINF0_Q0I){
- AMAZON_TPE_EMSG("CBM Error: Queue 0 Extract\n");
- }
- if (irq_stat & CBM_INTINF0_RDE){
- AMAZON_TPE_EMSG("CBM Error: Read Empty Queue %u\n",qid);
- dump_qd(qid);
- }
- }
- }
- mask_and_ack_amazon_irq(AMAZON_CBM_INT);
-}
-
-/* Brief: check the status word after AAL SDU after reassembly
- */
-static inline void check_aal5_error(u8 stw0, u8 stw1, int qid)
-{
- if (stw0 & AAL5_STW0_MFL){
- AMAZON_TPE_DMSG("Maximum Frame Length\n");
- g_atm_dev.queues[qid].aal5VccOverSizedSDUs++;
- }
- if (stw0 & AAL5_STW0_CRC){
- AMAZON_TPE_DMSG("CRC\n");
- g_atm_dev.queues[qid].aal5VccCrcErrors++;
- }
-#ifdef AMAZON_ATM_DEBUG_RX
- AMAZON_TPE_EMSG("qid:%u stw0:%8x stw1:%8x\n",qid,stw0,stw1);
-#endif
-}
-
-/* Brief: Process DMA rx data
- * Parameters:
- dma_dev: pointer to the dma_device_info, provided by us when register the dma device
- * Return: no
- * Description: DMA interrupt handerl with OoS support. It is called when there is some data in rx direction.
- *
- */
-//507261:tc.chen void atm_process_dma_rx(struct dma_device_info* dma_dev)
-void __system atm_process_dma_rx(struct dma_device_info* dma_dev)
-{
- u8 * head=NULL;
- u32 length=0;
- u8 stw0=0;
- u8 stw1=0;
-
- struct sk_buff * skb=NULL;
- struct atm_vcc * vcc=NULL;
- int qid=0;
-#ifdef AMAZON_ATM_DEBUG_RX
- static int dma_rx_dump=0;
- static u32 seq=0;
-
- seq++;
- if (dma_rx_dump>0){
- printk("\n=========================[%u]=========================\n",seq);
- }
-#endif
- length=dma_device_read(dma_dev,&head,(void**)&skb);
- AMAZON_TPE_DMSG("receive %8p[%u] from DMA\n", head,length);
- if (head == NULL||length<=0) {
- AMAZON_TPE_DMSG("dma_read null \n");
- goto error_exit;
- }
-
- if (length > (g_atm_dev.aal5.rx_max_sdu+64)){
- AMAZON_TPE_EMSG("received packet too large (%u)\n",length);
- goto error_exit;
- }
- //check AAL5R trail for error and qid
- //last byte is qid
- length--;
- qid = (int) head[length];
- AMAZON_TPE_DMSG("head[%u] qid %u\n",length, qid);
- //STW0 is always 4 bytes before qid
- length -= 4;
- stw0 = head[length]&0xff;
- AMAZON_TPE_DMSG("head[%u] stw0 %8x\n",length, stw0);
- //position of STW1 depends on the BE bits
- length = length-4 + (stw0&AAL5_STW0_BE);
- stw1 = head[length]&0xff;
- AMAZON_TPE_DMSG("head[%u] stw1 %8x\n",length, stw1);
- if ( (stw0 & AAL5_STW0_MASK) || (stw1 & AAL5_STW1_MASK) ){
- //AAL5 Error
- check_aal5_error(stw0, stw1,qid);
- goto error_exit;
- }
- //make data pointers consistent
- //UU + CPI
- length -= 2;
- AMAZON_TPE_DMSG("packet length %u\n", length);
-
- //error: cannot restore the qid
- if (valid_qid(qid) != 1){
- AMAZON_TPE_EMSG("received frame in invalid qid %u!\n", qid);
- goto error_exit;
- }
- vcc = g_atm_dev.queues[qid].vcc;
- if (vcc == NULL){
- AMAZON_TPE_EMSG("received frame in invalid vcc, qid=%u!\n",qid);
- goto error_exit;
- }
- if (skb == NULL){
- AMAZON_TPE_EMSG("cannot restore skb pointer!\n");
- goto error_exit;
- }
- skb_put(skb,length);
- skb->stamp = xtime;
- g_atm_dev.queues[qid].access_time=xtime;
- if ((*g_atm_dev.queues[qid].push)(vcc,skb,0)){
- g_atm_dev.mib_counter.rx_drop++;
- queue_statics(qid, QS_SW_DROP);
- }else{
- g_atm_dev.mib_counter.rx++;
- adsl_led_flash();//joelin adsl led
- queue_statics(qid, QS_PKT);
- AMAZON_TPE_DMSG("push successful!\n");
- }
-#ifdef AMAZON_ATM_DEBUG_RX
- if (dma_rx_dump>0){
- printk("\nOK packet [dump=%u] length=%u\n",dma_rx_dump,length);
- dump_skb(length+7, head);
- }
- if (dma_rx_dump >0) dma_rx_dump--;
-#endif
- return ;
-error_exit:
-#ifdef AMAZON_ATM_DEBUG_RX
- if ( (head!=NULL) && (length >0)){
- AMAZON_TPE_EMSG("length=%u\n",length);
- dump_skb(length+5, head);
- }
- dma_rx_dump++;
-#endif
- g_atm_dev.mib_counter.rx_err++;
- queue_statics(qid, QS_ERR);
- /*
- if (vcc){
- (*g_atm_dev.queues[qid].push)(vcc,skb,1);
- }
- */
- if (skb != NULL) {
- dev_kfree_skb_any(skb);
- }
- return;
-}
-
-/*Brief: ISR for DMA pseudo interrupt
- *Parameter:
- dma_dev: pointer to the dma_device_info, provided by us when register the dma device
- intr_status:
- RCV_INT: rx data available
- TX_BUF_FULL_INT: tx descriptor run out of
- TRANSMIT_CPT_INT: tx descriptor available again
- *Return:
- 0 for success???
- */
-//507261:tc.chen int amazon_atm_dma_handler(struct dma_device_info* dma_dev, int intr_status)
-int __system amazon_atm_dma_handler(struct dma_device_info* dma_dev, int intr_status)
-{
- AMAZON_TPE_DMSG("status:%u\n",intr_status);
- switch (intr_status) {
- case RCV_INT:
- atm_process_dma_rx(dma_dev);
- break;
- case TX_BUF_FULL_INT:
- //TX full: no descriptors
- atm_dma_full();
- break;
- case TRANSMIT_CPT_INT:
- //TX free: at least one descriptor
- atm_dma_free();
- break;
- default:
- AMAZON_TPE_EMSG("unknown status!\n");
- }
- return 0;
-}
-
-/*Brief: free buffer for DMA tx
- *Parameter:
- dataptr: pointers to data buffer
- opt: optional parameter, used to convey struct skb pointer, passwd in dma_device_write
- *Return:
- 0 for success???
- *Description:
- called by DMA module to release data buffer after DMA tx transaction
- *Error:
- cannot restore skb pointer
- */
-int amazon_atm_free_tx(u8*dataptr, void* opt)
-{
- struct sk_buff *skb;
- if (opt){
- AMAZON_TPE_DMSG("free skb%8p\n",opt);
- skb = (struct sk_buff *)opt;
- amazon_atm_free_tx_skb(skb);
- }else{
- AMAZON_TPE_EMSG("BUG: cannot restore skb pointer!\n");
- }
- return 0;
-}
-
-/*Brief: allocate buffer & do alignment
- */
-inline struct sk_buff * amazon_atm_alloc_buffer(int len)
-{
- struct sk_buff *skb;
- skb = dev_alloc_skb(len+16);
- if (skb){
- //alignment requriements (4x32 bits (16 bytes) boundary)
- alloc_align_16(skb);
- }
- return skb;
-}
-
-/*Brief: allocate buffer for DMA rx
- *Parameter:
- len: length
- opt: optional data to convey the skb pointer, which will be returned to me in interrupt handler,
- *Return:
- pointer to buffer, NULL means error?
- *Description:
- must make sure byte alignment
- */
-
-u8* amazon_atm_alloc_rx(int len, int* offset, void **opt)
-{
- struct sk_buff *skb;
- *offset = 0;
- skb = amazon_atm_alloc_buffer(len);
- if (skb){
- AMAZON_TPE_DMSG("alloc skb->data:%8p len:%u\n",skb->data,len);
- *(struct sk_buff**)opt = skb;
- }else{
- AMAZON_TPE_DMSG("no memory for receiving atm frame!\n");
- return NULL;
- }
- return skb->data;
-}
-
-
-
-
-/* Brief: Allocate kernel memory for sending a datagram.
- * Parameters
- * vcc virtual connection
- * size data buffer size
- * Return:
- * NULL fail
- * sk_buff a pointer to a sk_buff
- * Description:
- * This function can allocate our own additional memory for AAL5S inbound
- * header (8bytes). We have to replace the protocol default one (alloc_tx in /net/atm/common.c)
- * when we open the device.
- * byte alignment is done is DMA driver.
- */
-struct sk_buff *amazon_atm_alloc_tx(struct atm_vcc *vcc,unsigned int size)
-{
- struct sk_buff *skb;
-
- if (!dma_may_send(DMA_TX_CH0)){
- AMAZON_TPE_EMSG("no DMA descriptor available!\n");
- return NULL;
- }
- //AAL5 inbound header space + alignment extra buffer
- size+=8+AAL5S_INBOUND_HEADER;
-
- if (atomic_read(&vcc->tx_inuse) && !atm_may_send(vcc,size)) {
- AMAZON_TPE_EMSG("Sorry tx_inuse = %u, size = %u, sndbuf = %u\n",
- atomic_read(&vcc->tx_inuse),size,vcc->sk->sndbuf);
- return NULL;
- }
-
- skb = amazon_atm_alloc_buffer(size);
- if (skb == NULL){
- AMAZON_TPE_EMSG("no memory\n");
- return NULL;
- }
- AMAZON_TPE_DMSG("dev_alloc_skb(%u) = %x\n", skb->len, (u32)skb);
- AMAZON_TPE_DMSG("tx_inuse %u += %u\n",atomic_read(&vcc->tx_inuse),skb->truesize);
- atomic_add(skb->truesize+ATM_PDU_OVHD,&vcc->tx_inuse);
-
- //reserve for AAL5 inbound header
- skb_reserve(skb,AAL5S_INBOUND_HEADER);
- return skb;
-}
-
-
-/* Brief: change per queue QSB setting according to vcc qos parameters
- * Paramters:
- * vcc: atm_vcc pointer
- * qid: CBM queue id (1~15)
- * Return:
- */
-static inline void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, int qid)
-{
- qsb_qptl_t qptl;
- qsb_qvpt_t qvpt;
- u32 tmp=0;
- unsigned int qsb_clk;
-
- qsb_clk = amazon_get_fpi_hz()>>1;
-
- AMAZON_TPE_EMSG("Class=%u MAX_PCR=%u PCR=%u MIN_PCR=%u SCR=%u MBS=%u CDV=%u\n"
- ,qos->txtp.traffic_class
- ,qos->txtp.max_pcr
- ,qos->txtp.pcr
- ,qos->txtp.min_pcr
- ,qos->txtp.scr
- ,qos->txtp.mbs
- ,qos->txtp.cdv
- );
-
- // PCR limiter
- if (qos->txtp.max_pcr == 0){
- qptl.bit.tprs = 0; /* 0 disables the PCR limiter */
- }else {
- // peak cell rate will be slightly lower than requested (maximum rate / pcr)= (qsbclock/2^3 * timestep/4)/pcr
- tmp = (( (qsb_clk * g_atm_dev.qsb.tstepc)>>5)/ qos->txtp.max_pcr ) + 1;
- // check if an overfow occured
- if (tmp > QSB_TP_TS_MAX) {
- AMAZON_TPE_EMSG("max_pcr is too small, max_pcr:%u tprs:%u\n",qos->txtp.max_pcr, tmp);
- qptl.bit.tprs = QSB_TP_TS_MAX;
- }else{
- qptl.bit.tprs = tmp;
- }
- }
- //WFQ
- if (qos->txtp.traffic_class == ATM_CBR || qos->txtp.traffic_class ==ATM_VBR_RT){
- // real time queue gets weighted fair queueing bypass
- qptl.bit.twfq = 0;
- }else if (qos->txtp.traffic_class ==ATM_VBR_NRT ||qos->txtp.traffic_class ==ATM_UBR_PLUS ){
- // wfq calculation here are based on virtual cell rates, to reduce granularity for large rates
- // wfq factor is maximum cell rate / garenteed cell rate.
- //qptl.bit.twfq = g_atm_dev.qsb.min_cr * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
- if (qos->txtp.min_pcr == 0) {
- AMAZON_TPE_EMSG("<warning> MIN_PCR should not be zero\n");
- qptl.bit.twfq = QSB_WFQ_NONUBR_MAX;
- }else{
- tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
- if (tmp == 0 ){
- qptl.bit.twfq = 1;
- }else if (tmp > QSB_WFQ_NONUBR_MAX){
- AMAZON_TPE_EMSG("min_pcr is too small, min_pcr:%u twfq:%u\n",qos->txtp.min_pcr, tmp);
- qptl.bit.twfq = QSB_WFQ_NONUBR_MAX;
- }else{
- qptl.bit.twfq = tmp;
- }
- }
- }else if (qos->txtp.traffic_class == ATM_UBR){
- // ubr bypass, twfq set to maximum value
- qptl.bit.twfq = QSB_WFQ_UBR_BYPASS;
- }else{
- //tx is diabled, treated as UBR
- AMAZON_TPE_EMSG("<warning> unsupported traffic class %u \n", qos->txtp.traffic_class);
- qos->txtp.traffic_class = ATM_UBR;
- qptl.bit.twfq = QSB_WFQ_UBR_BYPASS;
- }
-
- //SCR Leaky Bucket Shaper VBR.0/VBR.1
- if (qos->txtp.traffic_class ==ATM_VBR_RT || qos->txtp.traffic_class ==ATM_VBR_NRT){
- if (qos->txtp.scr == 0){
- //SCR == 0 disable the shaper
- qvpt.bit.ts = 0;
- qvpt.bit.taus = 0;
- }else{
- //CLP
- if (vcc->atm_options&ATM_ATMOPT_CLP){
- //CLP1
- qptl.bit.vbr = 1;
- }else{
- //CLP0
- qptl.bit.vbr = 0;
- }
- //TS and TauS
- tmp = (( (qsb_clk * g_atm_dev.qsb.tstepc)>>5)/ qos->txtp.scr ) + 1;
- if (tmp > QSB_TP_TS_MAX) {
- AMAZON_TPE_EMSG("scr is too small, scr:%u ts:%u\n",qos->txtp.scr, tmp);
- qvpt.bit.ts = QSB_TP_TS_MAX;
- }else{
- qvpt.bit.ts = tmp;
- }
- tmp = (qos->txtp.mbs - 1)*(qvpt.bit.ts - qptl.bit.tprs)/64;
- if (tmp > QSB_TAUS_MAX){
- AMAZON_TPE_EMSG("mbs is too large, mbr:%u taus:%u\n",qos->txtp.mbs, tmp);
- qvpt.bit.taus = QSB_TAUS_MAX;
- }else if (tmp == 0){
- qvpt.bit.taus = 1;
- }else{
- qvpt.bit.taus = tmp;
- }
- }
- }else{
- qvpt.w0 = 0;
- }
- //write the QSB Queue Parameter Table (QPT)
- AMAZON_WRITE_REGISTER_L(QSB_QPT_SET_MASK,QSB_RTM_ADDR);
- AMAZON_WRITE_REGISTER_L(qptl.w0, QSB_RTD_ADDR);
- AMAZON_WRITE_REGISTER_L((QSB_TABLESEL_QPT<<QSB_TABLESEL_SHIFT)
- | QSB_RAMAC_REG_LOW
- | QSB_WRITE
- | qid
- ,QSB_RAMAC_ADDR);
- //write the QSB Queue VBR Parameter Table (QVPT)
- AMAZON_WRITE_REGISTER_L(QSB_QVPT_SET_MASK,QSB_RTM_ADDR);
- AMAZON_WRITE_REGISTER_L(qvpt.w0, QSB_RTD_ADDR);
- AMAZON_WRITE_REGISTER_L((QSB_TABLESEL_QVPT<<QSB_TABLESEL_SHIFT)
- | QSB_RAMAC_REG_LOW
- | QSB_WRITE
- | qid
- ,QSB_RAMAC_ADDR);
- AMAZON_TPE_EMSG("tprs:%u twfq:%u ts:%u taus:%u\n",qptl.bit.tprs,qptl.bit.twfq,qvpt.bit.ts,qvpt.bit.taus);
-}
-
-/*
- * Brief: create/change CBM queue descriptor
- * Parameter:
- * vcc: atm_vcc pointer
- * qid: CBM queue id (1~15)
- */
-static inline void set_qd(struct atm_vcc *vcc, u32 qid)
-{
- u32 tx_config=0,rx_config=0;
- u32 itf = (u32) vcc->itf;
- u32 dma_qos=0;
- u8 * qd_addr=NULL;
-
- tx_config|=CBM_QD_W3_WM_EN|CBM_QD_W3_CLPt;
- //RT: check if the connection is a real time connection
- if (vcc->qos.txtp.traffic_class == ATM_CBR || vcc->qos.txtp.traffic_class == ATM_VBR_RT){
- tx_config|= CBM_QD_W3_RT;
- }else{
- tx_config|= CBM_QD_W3_AAL5; //don't set the AAL5 flag if it is a RT service
- }
- rx_config = tx_config;
-
- if(vcc->qos.aal == ATM_AAL5){
- //QoS: DMA QoS according to the traffic class
- switch (vcc->qos.txtp.traffic_class){
- case ATM_CBR: dma_qos = CBR_DMA_QOS;break;
- case ATM_VBR_RT: dma_qos = VBR_RT_DMA_QOS;break;
- case ATM_VBR_NRT: dma_qos = VBR_NRT_DMA_QOS;break;
- case ATM_UBR_PLUS: dma_qos = UBR_PLUS_DMA_QOS;break;
- case ATM_UBR: dma_qos = UBR_DMA_QOS;break;
- }
-
- //TX: upstream, AAL5(EPD or PPD), NOINT, SBid
- tx_config |= CBM_QD_W3_DIR_UP|CBM_QD_W3_INT_NOINT|(itf&CBM_QD_W3_SBID_MASK);
- //RX: DMA QoS, downstream, no interrupt, AAL5(EPD, PPD), NO INT, HCR
-#ifdef AMAZON_TPE_SCR
- rx_config |= dma_qos|CBM_QD_W3_DIR_DOWN|CBM_QD_W3_INT_EOF;
-#else
- rx_config |= dma_qos|CBM_QD_W3_DIR_DOWN|CBM_QD_W3_INT_NOINT|CBM_QD_W3_HCR;
-#endif
- }else {
- //should be AAL0
- //upstream, NOINT, SBid
- tx_config |= CBM_QD_W3_DIR_UP|CBM_QD_W3_INT_NOINT|(itf&CBM_QD_W3_SBID_MASK);
- //RX: downstream, ACA interrupt,
- rx_config |= CBM_QD_W3_DIR_DOWN|CBM_QD_W3_INT_ACA;
- }
-
- //Threshold: maximum threshold for tx/rx queue, which is adjustable in steps of 64 cells
- tx_config |= ( (divide_by_64_round_up(tx_q_threshold)&0xffff)<<CBM_QD_W3_THRESHOLD_SHIFT) & CBM_QD_W3_THRESHOLD_MASK;
- rx_config |= ( (divide_by_64_round_up(rx_q_threshold)&0xffff)<<CBM_QD_W3_THRESHOLD_SHIFT) & CBM_QD_W3_THRESHOLD_MASK;
-
- qd_addr = (u8*) KSEG1ADDR((unsigned long)g_atm_dev.cbm.qd_addr);
- //TX
- AMAZON_WRITE_REGISTER_L(tx_config, (qd_addr+qid*CBM_QD_SIZE + 0xc));
- AMAZON_WRITE_REGISTER_L(0, (qd_addr+qid*CBM_QD_SIZE + 0x8));
- //RX
- AMAZON_WRITE_REGISTER_L(rx_config, (qd_addr+(qid+CBM_RX_OFFSET)*CBM_QD_SIZE + 0xc));
- AMAZON_WRITE_REGISTER_L(0, (qd_addr+(qid+CBM_RX_OFFSET)*CBM_QD_SIZE + 0x8));
-}
-/*
- * Brief: add HTU table entry
- * Parameter:
- * vpi.vci:
- * qid: CBM queue id (DEST is qid + CBM_RX_OFFSET)
- * idx: entry id (starting from zero to 14)
- * Return:
- * 0: sucessful
- * EIO: HTU table entry cannot be written
- */
-
-inline int set_htu_entry(u8 vpi, u16 vci, u8 qid, u8 idx)
-{
- int i = 0;
- u32 tmp1=0;
- while ((tmp1 = readl(HTU_RAMSTAT_ADDR))!=0 && i < 1024) i++;
- if (i > 1024)
- {
- AMAZON_TPE_EMSG("timeout\n");
- return -EIO;
- }
- // write address register,
- AMAZON_WRITE_REGISTER_L(idx, HTU_RAMADDR_ADDR);
- // configure transmit queue
- tmp1 = vpi<<24|vci<<8;
- tmp1|= HTU_RAMDAT1_VCON // valid connection the entry is not validated here !!!!!!!!!!!!!!!!
- |HTU_RAMDAT1_VCI3 // vci3 -> oam queue
- |HTU_RAMDAT1_VCI4 // vci4 -> oam queue
- |HTU_RAMDAT1_VCI6 // vci6 -> rm queue
- |HTU_RAMDAT1_PTI4 // pti4 -> oam queue
- |HTU_RAMDAT1_PTI5; // pti5 -> oam queue
-
- // ramdat 1 (in params & oam handling)
- AMAZON_WRITE_REGISTER_L( tmp1, HTU_RAMDAT1_ADDR);
- // ramdat 2 (out params & oam handling)
- tmp1 = ((qid+CBM_RX_OFFSET)&HTU_RAMDAT2_QID_MASK)
- |HTU_RAMDAT2_PTI6
- |HTU_RAMDAT2_PTI7
- |HTU_RAMDAT2_F4U
- |HTU_RAMDAT2_F5U
- ;
- AMAZON_WRITE_REGISTER_L( tmp1, HTU_RAMDAT2_ADDR);
- wmb();
- // write HTU entry
- AMAZON_WRITE_REGISTER_L(HTU_RAMCMD_WR, HTU_RAMCMD_ADDR);
- return 0;
-}
-/*
- * Brief: add HTU table entry
- * Parameter:
- * vcc: atm_vcc pointer
- * qid: CBM queue id
- * Return:
- * 0: sucessful
- * EIO: HTU table entry cannot be written
- */
-inline static int set_htu(struct atm_vcc *vcc, u32 qid)
-{
- return set_htu_entry(vcc->vpi, vcc->vci, qid, (qid - CBM_DEFAULT_Q_OFFSET));
-}
-
-/*
- * Brief: allocate a queue
- * Return:
- * <=0 no available queues
- * >0 qid
- */
-static int atm_allocate_q(short itf)
-{
- int i;
- u32 tmp1=0;
- int qid=0;
- amazon_atm_port_t * dev;
- dev = &g_atm_dev.ports[itf];
- //find start queue id for this interface
- for (i=0; i< itf; i++)
- {
- qid+= g_atm_dev.ports[i].max_conn;
- }
- // apply default queue offset ( oam, free cell queue, others, rm )
- qid += CBM_DEFAULT_Q_OFFSET;
- tmp1 = qid;
- // search for a free queue
- while ( (qid<tmp1+dev->max_conn)
- && ( g_atm_dev.queues[qid].free != 1)) {
- qid++;;
- }
- // if none was found, send failure message and return
- if ( tmp1+dev->max_conn == qid)
- {
- return -EFAULT;
- }
- return qid;
-
-}
-/* Brief: open a aal5 or aal0 connection
- */
-static int atm_open(struct atm_vcc *vcc, push_back_t push)
-{
- int err=0;
- int qid=0;
- amazon_atm_port_t * port = & g_atm_dev.ports[vcc->itf];
- unsigned long flags;
- /***************** check bandwidth ******************/
- /* 511045:linmars change ATM_VBR_NRT to use scr instead of pcr */
- if ((vcc->qos.txtp.traffic_class==ATM_CBR&&vcc->qos.txtp.max_pcr>port->tx_rem_cr)
- ||(vcc->qos.txtp.traffic_class==ATM_VBR_RT&&vcc->qos.txtp.max_pcr>port->tx_rem_cr)
- ||(vcc->qos.txtp.traffic_class==ATM_VBR_NRT&&vcc->qos.txtp.scr>port->tx_rem_cr)
- ||(vcc->qos.txtp.traffic_class==ATM_UBR_PLUS&&vcc->qos.txtp.min_pcr>port->tx_rem_cr)
- ) {
- AMAZON_TPE_EMSG("not enough bandwidth left (%u) cells per seconds \n",port->tx_rem_cr);
- return -EINVAL;
- }
- if ( (qid = amazon_atm_find_vpivci(vcc->vpi, vcc->vci)) >0 ){
- AMAZON_TPE_EMSG("vpi:%u vci:%u is alreay open on queue:%u\n", vcc->vpi, vcc->vci, qid);
- return -EADDRINUSE;
- }
-
- /***************** allocate entry queueID for this port *****************/
- if ( (qid=atm_allocate_q(vcc->itf)) <= 0){
- AMAZON_TPE_EMSG("port: %u max:%u qid: %u\n", vcc->itf, port->max_conn, qid);
- AMAZON_TPE_EMSG("no availabel connections for this port:%u\n",vcc->itf);
- return -EINVAL;
- }
- /**************QSB parameters and CBM descriptors*************/
- set_qsb(vcc, &vcc->qos, qid);
- set_qd(vcc, qid);
- mb();
- err=set_htu(vcc,qid);
- if (err){
- AMAZON_TPE_EMSG("set htu entry fails %u\n",err);
- return err;
- }
- /************set internal mapping*************/
- local_irq_save(flags);
- g_atm_dev.queues[qid].free = 0;
- g_atm_dev.queues[qid].vcc = vcc;
- g_atm_dev.queues[qid].push = push;
- g_atm_dev.queues[qid+CBM_RX_OFFSET].free = 0;
- g_atm_dev.queues[qid+CBM_RX_OFFSET].vcc = vcc;
- g_atm_dev.queues[qid+CBM_RX_OFFSET].push = push;
- /******************reserve bandwidth**********************/
- if (vcc->qos.txtp.traffic_class == ATM_CBR){
- //CBR, real time connection, reserve PCR
- port->tx_cur_cr += vcc->qos.txtp.max_pcr;
- port->tx_rem_cr -= vcc->qos.txtp.max_pcr;
- }else if (vcc->qos.txtp.traffic_class == ATM_VBR_RT){
- //VBR_RT, real time connection, reserve PCR
- port->tx_cur_cr += vcc->qos.txtp.max_pcr;
- port->tx_rem_cr -= vcc->qos.txtp.max_pcr;
- }else if (vcc->qos.txtp.traffic_class == ATM_VBR_NRT){
- //VBR_NRT, reserve SCR
- port->tx_cur_cr += vcc->qos.txtp.pcr;
- port->tx_rem_cr -= vcc->qos.txtp.pcr;
- }else if (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS){
- //UBR_PLUS, reserve MCR
- port->tx_cur_cr += vcc->qos.txtp.min_pcr;
- port->tx_rem_cr -= vcc->qos.txtp.min_pcr;
- }
- local_irq_restore(flags);
- return err;
-}
-/* Brief: Open ATM connection
- * Parameters: atm_vcc - Pointer to VCC data structure
- * vpi - VPI value for new connection
- * vci - VCI value for new connection
- *
- * Return: 0 - sucessful
- * -ENOMEM - No memory available
- * -EINVAL - No bandwidth/queue/ or unsupported AAL type
- * Description:
- * This function opens an ATM connection on a specific device/interface
- *
- */
-int amazon_atm_open(struct atm_vcc *vcc,push_back_t push)
-{
- int err=0;
-
- AMAZON_TPE_DMSG("vpi %u vci %u itf %u aal %u\n"
- ,vcc->vpi
- ,vcc->vci
- ,vcc->itf
- ,vcc->qos.aal
- );
-
- AMAZON_TPE_DMSG("tx cl %u bw %u mtu %u\n"
- ,vcc->qos.txtp.traffic_class
- ,vcc->qos.txtp.max_pcr
- ,vcc->qos.txtp.max_sdu
- );
- AMAZON_TPE_DMSG("rx cl %u bw %u mtu %u\n"
- ,vcc->qos.rxtp.traffic_class
- ,vcc->qos.rxtp.max_pcr
- ,vcc->qos.rxtp.max_sdu
- );
- if (vcc->qos.aal == ATM_AAL5 || vcc->qos.aal == ATM_AAL0){
- err = atm_open(vcc,push);
- }else{
- AMAZON_TPE_EMSG("unsupported aal type %u\n", vcc->qos.aal);
- err = -EPROTONOSUPPORT;
- };
- if (err == 0 ){
- //replace the default memory allocation function with our own
- vcc->alloc_tx = amazon_atm_alloc_tx;
- set_bit(ATM_VF_READY,&vcc->flags);
- }
- return err;
-}
-
-/* Brief: Send ATM OAM cell
- * Parameters: atm_vcc - Pointer to VCC data structure
- * skb - Pointer to sk_buff structure, that contains the data
- * Return: 0 - sucessful
- * -ENOMEM - No memory available
- * -EINVAL - Not supported
- * Description:
- * This function sends a cell over and ATM connection
- * We always release the skb
- * TODO: flags handling (ATM_OF_IMMED, ATM_OF_INRATE)
- */
-int amazon_atm_send_oam(struct atm_vcc *vcc, void * cell, int flags)
-{
- int err=0;
- int qid=0;
- struct amazon_atm_cell_header * cell_header;
- // Get cell header
- cell_header = (struct amazon_atm_cell_header*) cell;
- if ((cell_header->bit.pti == ATM_PTI_SEGF5) || (cell_header->bit.pti == ATM_PTI_E2EF5)) {
- qid = amazon_atm_find_vpivci( cell_header->bit.vpi, cell_header->bit.vci);
- }else if (cell_header->bit.vci == 0x3 || cell_header->bit.vci == 0x4) {
- //507281:tc.chen qid = amazon_atm_find_vpi((int) cell_header->bit.vpi);
- // 507281:tc.chen start
- u8 f4_vpi;
- f4_vpi = cell_header->bit.vpi;
- qid = amazon_atm_find_vpi(f4_vpi );
- // 507281:tc.chen end
- }else{
- //non-OAM cells, always invalid
- qid = -EINVAL;
- }
- if (qid == -EINVAL) {
- err = -EINVAL;
- AMAZON_TPE_EMSG("not valid AAL0 packet\n");
- }else{
- //send the cell using swie
-#ifdef TPE_LOOPBACK
- err = amazon_atm_swin(AMAZON_ATM_OAM_Q_ID, cell);
-#else
- err = amazon_atm_swin(qid, cell);
-#endif
- }
- //kfree(cell);
- return err;
-}
-
-/* Brief: Send AAL5 frame through DMA
- * Parameters: vpi - virtual path id
- * vci - virtual circuit id
- * clp - cell loss priority
- * qid - CBM queue to be sent to
- * skb - packet to be sent
- * Return: 0 - sucessful
- * -ENOMEM - No memory available
- * -EINVAL - Not supported
- * Description:
- * This function sends a AAL5 frame over and ATM connection
- * 1. make sure that the data is aligned to 4x32-bit boundary
- * 2. provide the inbound data (CPCS-UU and CPI, not used here)
- * 3. set CLPn
- * 4. send the frame by DMA
- * 5. release the buffer ???
- ** use our own allocation alloc_tx
- ** we make sure the alignment and additional memory
- *** we always release the skb
-
- */
-int amazon_atm_dma_tx(u8 vpi, u16 vci, u8 clp, u8 qid, struct sk_buff *skb)
-{
- int err=0,need_pop=1;
- u32 * data=NULL;
- int nwrite=0;
- struct sk_buff *skb_tmp;
- u32 len=skb->len;
-
- //AAL5S inbound header 8 bytes
- if (skb->len > g_atm_dev.aal5.tx_max_sdu - AAL5S_INBOUND_HEADER) {
- AMAZON_TPE_DMSG("tx_max_sdu:%u\n",g_atm_dev.aal5.tx_max_sdu);
- AMAZON_TPE_DMSG("skb too large [%u]!\n",skb->len);
- err = -EMSGSIZE;
- goto atm_dma_tx_error_exit;
- }
-
- //Check the byte alignment requirement and header space
- if ( ( ((u32)(skb->data)%16) !=AAL5S_INBOUND_HEADER)|| (skb_headroom(skb)<AAL5S_INBOUND_HEADER)){
- //not aligned or no space for header, fall back to memcpy
- skb_tmp = dev_alloc_skb(skb->len+16);
- if (skb_tmp==NULL){
- err = - ENOMEM;
- goto atm_dma_tx_error_exit;
- }
- alloc_align_16(skb_tmp);
- g_atm_dev.aal5.cnt_cpy++;
- skb_reserve(skb_tmp,AAL5S_INBOUND_HEADER);
- memcpy(skb_put(skb_tmp,skb->len), skb->data, skb->len);
- amazon_atm_free_tx_skb(skb);
- need_pop=0;
- skb = skb_tmp;
- }
- //Provide AAL5S inbound header
- data = (u32 *)skb_push(skb,8);
- data[0] = __be32_to_cpu(vpi<<20|vci<<4|clp);
- data[1] = __be32_to_cpu(g_atm_dev.aal5.padding_byte<<8|qid);
-
- len = skb->len;
-
- //send through DMA
- AMAZON_TPE_DMSG("AAL5S header 0 %8x\n", data[0]);
- AMAZON_TPE_DMSG("AAL5S header 0 %8x\n", data[1]);
- AMAZON_TPE_DMSG("about to call dma_write len: %u\n", len);
- nwrite=dma_device_write( &g_dma_dev,skb->data,len,skb);
- if (nwrite != len) {
- //DMA descriptors full
-// AMAZON_TPE_EMSG("AAL5 packet drop due to DMA nwrite:%u skb->len:%u\n", nwrite,len);
- AMAZON_TPE_DMSG("AAL5 packet drop due to DMA nwrite:%u skb->len:%u\n", nwrite,len);
- err = -EAGAIN;
- goto atm_dma_tx_drop_exit;
- }
- AMAZON_TPE_DMSG("just finish call dma_write\n");
- //release in the "dma done" call-back
- return 0;
-atm_dma_tx_error_exit:
- g_atm_dev.mib_counter.tx_err++;
- queue_statics(qid, QS_ERR);
- goto atm_dma_tx_exit;
-
-atm_dma_tx_drop_exit:
- g_atm_dev.mib_counter.tx_drop++;
- queue_statics(qid, QS_SW_DROP);
-atm_dma_tx_exit:
- if (need_pop){
- amazon_atm_free_tx_skb(skb);
- }else{
- dev_kfree_skb_any(skb);
- }
- return err;
-}
-
-/* Brief: Send AAL0/AAL5 packet
- * Parameters: atm_vcc - Pointer to VCC data structure
- * skb - Pointer to sk_buff structure, that contains the data
- * Return: 0 - sucessful
- * -ENOMEM - No memory available
- * -EINVAL - Not supported
- * Description:
- * See amazon_atm_dma_tx
- */
-int amazon_atm_send(struct atm_vcc *vcc,struct sk_buff *skb)
-{
- int qid=0;
- u8 clp=0;
- int err=0;
- u32 wm=0;
-
- if (vcc == NULL || skb == NULL){
- AMAZON_TPE_EMSG("invalid parameter\n");
- return -EINVAL;
- }
- ATM_SKB(skb)->vcc = vcc;
- qid = amazon_atm_get_queue(vcc);
- if (valid_qid(qid) != 1) {
- AMAZON_TPE_EMSG("invalid vcc!\n");
- err = -EINVAL;
- goto atm_send_err_exit;
- }
-
- //Send AAL0 using SWIN
- if (vcc->qos.aal == ATM_AAL0){
-#ifdef TPE_LOOPBACK
- err=amazon_atm_swin((qid+CBM_RX_OFFSET), skb->data);
-#else
- err=amazon_atm_swin(qid, skb->data);
-#endif
- if (err){
- goto atm_send_err_exit;
- }
- goto atm_send_exit;
- }
-
- //Should be AAl5
- //MIB counter
- g_atm_dev.mib_counter.tx++;
- adsl_led_flash();//joelin adsl led
- queue_statics(qid, QS_PKT);
-
-#ifdef AMAZON_CHECK_LINK
- //check adsl link
- if (adsl_link_status == 0){
- //link down
- AMAZON_TPE_DMSG("ADSL link down, discarded!\n");
- err=-EFAULT;
- goto atm_send_drop_exit;
- }
-#endif
- clp = (vcc->atm_options&ATM_ATMOPT_CLP)?1:0;
- //check watermark first
- wm = readl(CBM_WMSTAT0_ADDR);
- if ( (wm & (1<<qid))
- ||( (vcc->qos.txtp.traffic_class != ATM_CBR
- &&vcc->qos.txtp.traffic_class != ATM_VBR_RT)
- &(wm & (CBM_WM_NRT_MASK | (clp&CBM_WM_CLP1_MASK)) ))){
- //wm hit: discard
- AMAZON_TPE_DMSG("watermark hit, discarded!\n");
- err=-EFAULT;
- goto atm_send_drop_exit;
- }
-#ifdef TPE_LOOPBACK
- return amazon_atm_dma_tx(vcc->vpi, vcc->vci,clp, (qid+CBM_RX_OFFSET),skb);
-#else
- return amazon_atm_dma_tx(vcc->vpi, vcc->vci,clp, qid,skb);
-#endif
-
-atm_send_exit:
- amazon_atm_free_tx_skb_vcc(vcc,skb);
- return 0;
-
-atm_send_drop_exit:
- g_atm_dev.mib_counter.tx_drop++;
- queue_statics(qid,QS_SW_DROP);
-atm_send_err_exit:
- amazon_atm_free_tx_skb_vcc(vcc,skb);
- return err;
-}
-
-/* Brief: Return ATM port related MIB
- * Parameter: interface number
- atm_cell_ifEntry_t
- */
-int amazon_atm_cell_mib(atm_cell_ifEntry_t* to,u32 itf)
-{
- g_atm_dev.mib_counter.htu_unp += readl(HTU_MIBCIUP);
- to->ifInUnknownProtos = g_atm_dev.mib_counter.htu_unp;
-#ifdef AMAZON_TPE_READ_ARC
- u32 reg_val=0;
- meiDebugRead((AR_CELL0_ADDR+itf*4),®_val,1);
- g_atm_dev.mib_counter.rx_cells += reg_val;
- reg_val=0;
- meiDebugWrite((AR_CELL0_ADDR+itf*4),®_val,1);
- to->ifHCInOctets_h = (g_atm_dev.mib_counter.rx_cells * 53)>>32;
- to->ifHCInOctets_l = (g_atm_dev.mib_counter.rx_cells * 53) & 0xffff;
-
- meiDebugRead((AT_CELL0_ADDR+itf*4),®_val,1);
- g_atm_dev.mib_counter.tx_cells += reg_val;
- reg_val=0;
- meiDebugWrite((AT_CELL0_ADDR+itf*4),®_val,1);
- to->ifHCOutOctets_h = (g_atm_dev.mib_counter.tx_cells * 53)>>32;
- to->ifHCOutOctets_l = (g_atm_dev.mib_counter.rx_cells * 53) & 0xffff;
-
- meiDebugRead((AR_CD_CNT0_ADDR+itf*4),®_val,1);
- g_atm_dev.mib_counter.rx_err_cells += reg_val;
- reg_val=0;
- meiDebugWrite((AR_CD_CNT0_ADDR+itf*4),®_val,1);
- to->ifInErrors = g_atm_dev.mib_counter.rx_err_cells;
-
- to->ifOutErrors = 0;
-#else
- to->ifHCInOctets_h = 0;
- to->ifHCInOctets_l = 0;
- to->ifHCOutOctets_h = 0;
- to->ifHCOutOctets_l = 0;
- to->ifInErrors = 0;
- to->ifOutErrors = 0;
-#endif
- return 0;
-}
-
-/* Brief: Return ATM AAL5 related MIB
- * Parameter:
- atm_aal5_ifEntry_t
- */
-int amazon_atm_aal5_mib(atm_aal5_ifEntry_t* to)
-{
- u32 reg_l,reg_h;
- //AAL5R received Octets from ATM
- reg_l = readl(AAL5_RIOL_ADDR);
- reg_h = readl(AAL5_RIOM_ADDR);
- g_atm_dev.mib_counter.rx_cnt_h +=reg_h;
- if (reg_l + g_atm_dev.mib_counter.rx_cnt_l < reg_l){
- g_atm_dev.mib_counter.rx_cnt_h++;
- }
-
- g_atm_dev.mib_counter.rx_cnt_l+= reg_l;
- //AAL5S sent Octets to ATM
- reg_l = readl(AAL5_SOOL_ADDR);
- reg_h = readl(AAL5_SOOM_ADDR);
- g_atm_dev.mib_counter.tx_cnt_h +=reg_h;
- if (reg_l + g_atm_dev.mib_counter.tx_cnt_l < reg_l){
- g_atm_dev.mib_counter.tx_cnt_h++;
- }
- g_atm_dev.mib_counter.tx_cnt_l+= reg_l;
-
-
- g_atm_dev.mib_counter.tx_ppd += readl(CBM_AAL5ODIS_ADDR);
- g_atm_dev.mib_counter.rx_drop += readl(CBM_AAL5IDIS_ADDR);
-
- //store
- to->ifHCInOctets_h = g_atm_dev.mib_counter.rx_cnt_h;
- to->ifHCInOctets_l = g_atm_dev.mib_counter.rx_cnt_l;
- to->ifHCOutOctets_h = g_atm_dev.mib_counter.tx_cnt_h;
- to->ifHCOutOctets_l = g_atm_dev.mib_counter.tx_cnt_l;
- to->ifOutDiscards = g_atm_dev.mib_counter.tx_drop;
- to->ifInDiscards = g_atm_dev.mib_counter.rx_drop;
-
- //Software provided counters
- //packets passed to higher layer
- to->ifInUcastPkts = g_atm_dev.mib_counter.rx;
- //packets passed from higher layer
- to->ifOutUcastPkts = g_atm_dev.mib_counter.tx;
- //number of wrong downstream packets
- to->ifInErrors = g_atm_dev.mib_counter.rx_err;
- //number of wrong upstream packets
- to->ifOutErros = g_atm_dev.mib_counter.tx_err;
-
- return 0;
-}
-/* Brief: Return ATM AAL5 VCC related MIB from internale use
- * Parameter:
- * qid
- * atm_aal5_vcc_t
- */
-static int __amazon_atm_vcc_mib(int qid, atm_aal5_vcc_t* to)
-{
- //aal5VccCrcErrors
- to->aal5VccCrcErrors = g_atm_dev.queues[qid].aal5VccCrcErrors;
- to->aal5VccOverSizedSDUs =g_atm_dev.queues[qid].aal5VccOverSizedSDUs;
- to->aal5VccSarTimeOuts = 0; //not supported yet
- return 0;
-}
-/* Brief: Return ATM AAL5 VCC related MIB from vpi/vci
- * Parameter: atm_vcc
- * atm_aal5_vcc_t
- */
-int amazon_atm_vcc_mib_x(int vpi, int vci,atm_aal5_vcc_t* to)
-{
- int qid=0;
- int err=0;
- qid = amazon_atm_find_vpivci(vpi, vci);
- if (qid >0 ){
- err = __amazon_atm_vcc_mib(qid,to);
- }else{
- return -EINVAL;
- }
- return err;
-}
-
-
-/* Brief: Return ATM AAL5 VCC related MIB
- * Parameter: atm_vcc
- * atm_aal5_vcc_t
- */
-int amazon_atm_vcc_mib(struct atm_vcc *vcc,atm_aal5_vcc_t* to)
-{
- int qid=0;
- int err=0;
- qid = amazon_atm_get_queue(vcc);
- if (qid >0 ){
- err = __amazon_atm_vcc_mib(qid,to);
- }else{
- return -EINVAL;
- }
- return err;
-}
-
-/* Brief: Close ATM connection
- * Parameters: atm_vcc - Pointer to VCC data structure
- * Return: no
- * Description:
- * This function closes the given ATM connection
- */
-void amazon_atm_close(struct atm_vcc *vcc){
- int i;
- int qid=0;
- u32 tmp1;
- u8 * qd_addr;
- unsigned long flags;
- if (vcc == NULL){
- AMAZON_TPE_EMSG("invalid parameter. vcc is null\n");
- return;
- }
- u32 itf = (u32) vcc->itf;
- //release bandwidth
- if (vcc->qos.txtp.traffic_class == ATM_CBR){
- g_atm_dev.ports[itf].tx_rem_cr += vcc->qos.txtp.max_pcr;
- g_atm_dev.ports[itf].tx_cur_cr -= vcc->qos.txtp.max_pcr;
- }else if (vcc->qos.txtp.traffic_class == ATM_VBR_RT){
- g_atm_dev.ports[itf].tx_rem_cr += vcc->qos.txtp.max_pcr;
- g_atm_dev.ports[itf].tx_cur_cr -= vcc->qos.txtp.max_pcr;
- }else if (vcc->qos.txtp.traffic_class == ATM_VBR_NRT){
- g_atm_dev.ports[itf].tx_rem_cr += vcc->qos.txtp.pcr;
- g_atm_dev.ports[itf].tx_cur_cr -= vcc->qos.txtp.pcr;
- }else if (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS){
- g_atm_dev.ports[itf].tx_rem_cr += vcc->qos.txtp.min_pcr;
- g_atm_dev.ports[itf].tx_cur_cr -= vcc->qos.txtp.min_pcr;
- }
-
- qid = amazon_atm_get_queue(vcc);
- if (qid == -EINVAL){
- AMAZON_TPE_EMSG("unknown vcc %u.%u.%u\n", vcc->itf, vcc->vpi, vcc->vci);
- return;
- }
- local_irq_save(flags);
- //Disable HTU entry
- i=0;
- while ((tmp1 = readl(HTU_RAMSTAT_ADDR))!=0 && i < HTU_RAM_ACCESS_MAX) i++;
- if (i == HTU_RAM_ACCESS_MAX){
- AMAZON_TPE_EMSG("HTU RAM ACCESS out of time\n");
- }
-
- // write address register
- AMAZON_WRITE_REGISTER_L(qid - CBM_DEFAULT_Q_OFFSET, HTU_RAMADDR_ADDR);
- // invalidate the connection
- AMAZON_WRITE_REGISTER_L(0, HTU_RAMDAT1_ADDR);
- // write command
- AMAZON_WRITE_REGISTER_L(HTU_RAMCMD_WR,HTU_RAMCMD_ADDR);
-
- qd_addr = (u8 *) KSEG1ADDR((unsigned long)g_atm_dev.cbm.qd_addr);
-#ifdef AMAZON_ATM_DEBUG
- tmp1 = readl(qd_addr+qid*CBM_QD_SIZE+0x8) & 0xffff;
- AMAZON_TPE_DMSG("TX queue has %u cells \n", tmp1);
- tmp1 = readl( qd_addr+(qid+CBM_RX_OFFSET)*CBM_QD_SIZE+0x08)&0xffff;
- AMAZON_TPE_DMSG("RX queue has %u cells \n", tmp1);
-#endif
- // set threshold of txqueue to 0
- tmp1 = readl(qd_addr+qid*CBM_QD_SIZE+0x0c);
- tmp1&= (~ CBM_QD_W3_THRESHOLD_MASK);
- AMAZON_WRITE_REGISTER_L(tmp1, (qd_addr+qid*CBM_QD_SIZE+0x0c));
- // set threshold of rxqueue to 0
- tmp1 = readl( qd_addr+(qid+CBM_RX_OFFSET)*CBM_QD_SIZE+0x0c);
- tmp1&= (~ CBM_QD_W3_THRESHOLD_MASK);
- AMAZON_WRITE_REGISTER_L(tmp1,(qd_addr+(qid+CBM_RX_OFFSET)*CBM_QD_SIZE+0x0c));
-
- //clear internal mapping
- amazon_atm_clear_vcc(qid);
- amazon_atm_clear_vcc(qid+CBM_RX_OFFSET);
-
- local_irq_restore(flags);
-}
-
-
-/* Brief: initialize internal data structure
- */
-static void atm_constructor(amazon_atm_dev_t * dev)
-{
- int i;
- memset(dev,0,sizeof(amazon_atm_dev_t));
- atm_init_parameters(dev);
- //internal: queue "free" flag
- for(i=1;i<AMAZON_ATM_MAX_QUEUE_NUM;i++) {
- //dev->queues[i].vcc=NULL;
- dev->queues[i].free = 1;
- }
- for(i=0;i<AMAZON_ATM_PORT_NUM;i++){
- dev->ports[i].tx_rem_cr = dev->ports[i].tx_max_cr;
- }
- //MIB
- atomic_set(&dev->dma_tx_free_0,1); //initially there should be free descriptors
-}
-
-/* Brief: return round up base-2 logarithm
- */
-static inline int get_log_2(u32 value)
-{
- int i=0,j=1;
- while (i<11){
- if (j>=value) break;
- j=j<<1;
- i++;
- }
- AMAZON_TPE_DMSG("round up base-2 logarithm of %u is %u\n", value, i);
- return i;
-}
-
-/* Brief: TPE hardware initialization
- * Parameter: specifiy the configurations of the hardware
- */
-static inline int atm_init_hard(amazon_atm_dev_t * dev)
-{
- int i;
- u32 tmp1, tmp2, tmp3;
- u8 * mem_addr=NULL;
- u8 * qd_addr=NULL;
- //PMU power on the module 1st
- *(AMAZON_PMU_PWDCR) = (*AMAZON_PMU_PWDCR) | (AMAZON_PMU_PWDCR_TPE);
- //Reset the module
- *(AMAZON_RST_REQ) = (* AMAZON_RST_REQ) | (AMAZON_RST_REQ_TPE);
- mb();
- mdelay(100);
- *(AMAZON_RST_REQ) = (* AMAZON_RST_REQ) & (~(AMAZON_RST_REQ_TPE));
- mb();
-
- unsigned long qsb_clk = amazon_get_fpi_hz()>>1;
- /*********allocate & arrange memory for CBM *********/
- if (dev->cbm.mem_addr == NULL){
- dev->cbm.allocated = 1;
- mem_addr = (u8 *)__get_free_pages(GFP_KERNEL, get_log_2(((CBM_CELL_SIZE * dev->cbm.free_cell_cnt) >>PAGE_SHIFT) + 1));
- if (mem_addr != NULL){
- dev->cbm.mem_addr = mem_addr;
- } else {
- goto init_no_mem;
- }
- }
- if (dev->cbm.qd_addr == NULL){
-#ifdef CONFIG_USE_VENUS
- //to work around a bug, bit15 of QDOFF address should be 1,Aug4, 2004
- //thus, we allocate 64k memory
- qd_addr = (u8 *)__get_free_pages(GFP_KERNEL, 4);
- if (qd_addr != NULL) {
- dev->cbm.qd_addr_free = (u8*) (((unsigned long) qd_addr));
- dev->cbm.qd_addr = (u8*) (((unsigned long) qd_addr) | 0x8000);
- }else{
- goto init_no_mem;
- }
-#else //CONFIG_USE_VENUS
- qd_addr = (u8 *)kmalloc( CBM_QD_SIZE * AMAZON_ATM_MAX_QUEUE_NUM, GFP_KERNEL);
- if (qd_addr != NULL) {
- dev->cbm.qd_addr = qd_addr;
- }else {
- goto init_no_mem;
- }
-#endif //CONFIG_USE_VENUS
- }
-//#ifndef CONFIG_MIPS_UNCACHED
- mem_addr = (u8 *)KSEG1ADDR((unsigned long)dev->cbm.mem_addr);
- qd_addr = (u8 *)KSEG1ADDR((unsigned long)dev->cbm.qd_addr);
-//#endif
- //CBM reset cell queue memory, 64 bytes / cell
- memset_io(mem_addr, 0, CBM_CELL_SIZE * dev->cbm.free_cell_cnt);
- //make a link list, last 4 bytes is pointer
- for(i=1;i<dev->cbm.free_cell_cnt;i++){
- AMAZON_WRITE_REGISTER_L(CPHYSADDR((mem_addr + CBM_CELL_SIZE * i)),(mem_addr + CBM_CELL_SIZE * (i-1) + 0x3c));
- }
- //reset queue descriptor
- memset_io(qd_addr, 0, CBM_QD_SIZE * AMAZON_ATM_MAX_QUEUE_NUM);
- //init word 0-2 of q0 (free cell list)
- //address of last cell
- AMAZON_WRITE_REGISTER_L(CPHYSADDR((mem_addr + CBM_CELL_SIZE * (dev->cbm.free_cell_cnt-1))), qd_addr);
- //address of first cell
- AMAZON_WRITE_REGISTER_L(CPHYSADDR((mem_addr)), (qd_addr + 4));
- //no. of free cells
- AMAZON_WRITE_REGISTER_L(dev->cbm.free_cell_cnt,(qd_addr + 8));
- //init q descriptor for OAM receiving
- AMAZON_WRITE_REGISTER_L((CBM_QD_W3_INT_ACA | (divide_by_64_round_up(oam_q_threshold)&0xff)<< CBM_QD_W3_THRESHOLD_SHIFT), (qd_addr + AMAZON_ATM_OAM_Q_ID * CBM_QD_SIZE + 0x0c));
-// AMAZON_WRITE_REGISTER_L((CBM_QD_W3_INT_ACA | (u32)oam_q_threshold<< CBM_QD_W3_THRESHOLD_SHIFT), (qd_addr + AMAZON_ATM_OAM_Q_ID * CBM_QD_SIZE + 0x0c));
- //config CBM
- //set offset address and threshold
- AMAZON_WRITE_REGISTER_L(CPHYSADDR(qd_addr), CBM_QDOFF_ADDR);
- AMAZON_WRITE_REGISTER_L(((dev->cbm.nrt_thr&CBM_THR_MASK)|CBM_WM_3_1), CBM_NRTTHR_ADDR);
- AMAZON_WRITE_REGISTER_L(((dev->cbm.clp0_thr&CBM_THR_MASK)|CBM_WM_3_1), CBM_CLP0THR_ADDR);
- AMAZON_WRITE_REGISTER_L(((dev->cbm.clp1_thr&CBM_THR_MASK)|CBM_WM_3_1), CBM_CLP1THR_ADDR);
- //config interrupts
- AMAZON_WRITE_REGISTER_L( CBM_IMR_MASK & (~(CBM_IMR_ACA|CBM_IMR_Q0E|CBM_IMR_Q0I|CBM_IMR_RDE|CBM_IMR_OPF|CBM_IMR_ERR
-#ifdef AMAZON_ATM_DEBUG
- |CBM_IMR_DISC|CBM_IMR_QFD|CBM_IMR_NFCA|CBM_IMR_CLP1TR|CBM_IMR_CLP0TR|CBM_IMR_NRTTR|CBM_IMR_QTR
-#endif
-#ifdef AMAZON_TPE_SCR
- |CBM_IMR_EF
-#endif
- )), CBM_IMR0_ADDR);
- AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS | SRC_SRE_ENABLE | AMAZON_CBM_INT, CBM_SRC0_ADDR);
-
- //HTU
- //RAM entry for number of possible connections per interface
- tmp1 = dev->ports[0].max_conn?dev->ports[0].max_conn-1:0;
- AMAZON_WRITE_REGISTER_L(tmp1, HTU_RX0_ADDR);
- for(i=1;i<AMAZON_ATM_PORT_NUM;i++){
- tmp1+=dev->ports[i].max_conn;
- AMAZON_WRITE_REGISTER_L(tmp1, HTU_RX0_ADDR + 4 * i);
- }
- dev->cbm.max_q_off = tmp1+1;
- //Queue ID for OAM/RM/Other cells
- AMAZON_WRITE_REGISTER_L (AMAZON_ATM_OAM_Q_ID, HTU_DESTOAM_ADDR);
- AMAZON_WRITE_REGISTER_L( AMAZON_ATM_RM_Q_ID, HTU_DESTRM_ADDR);
- AMAZON_WRITE_REGISTER_L( AMAZON_ATM_OTHER_Q_ID, HTU_DESTOTHER_ADDR);
- //Timeout
- AMAZON_WRITE_REGISTER_L((u32) HTUTIMEOUT, HTU_TIMEOUT_ADDR);
-#ifdef AMAZON_ATM_DEBUG
- AMAZON_WRITE_REGISTER_L((u32) HTU_ISR_MASK
- &(~(HTU_ISR_NE|HTU_ISR_TORD|HTU_ISR_OTOC|HTU_ISR_ONEC|HTU_ISR_PNE|HTU_ISR_PT)), HTU_IMR0_ADDR);
- AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS|SRC_SRE_ENABLE|AMAZON_HTU_INT,HTU_SRC0_ADDR);
-#endif
- //QSB
- //global setting, TstepC, SBL, Tau
- //Tau
- AMAZON_WRITE_REGISTER_L(dev->qsb.tau, QSB_TAU_ADDR);
- //SBL
- AMAZON_WRITE_REGISTER_L(dev->qsb.sbl, QSB_SBL_ADDR);
- //tstep
- AMAZON_WRITE_REGISTER_L(dev->qsb.tstepc>>1, QSB_CONFIG_ADDR);
-
- //port settting
- for(i=0;i<AMAZON_ATM_PORT_NUM;i++){
- if ( (dev->ports[i].enable) && (dev->ports[i].tx_max_cr!=0) ){
- tmp1 = ((qsb_clk * dev->qsb.tstepc) >>1) / dev->ports[i].tx_max_cr;
- tmp2 = tmp1 / 64; //integer value of Tsb
- tmp3 = tmp1%64 + 1; //fractional part of Tsb
- //carry over to integer part (?)
- if (tmp3 == 64) {
- tmp3 = 0;
- tmp2++;
- }
- if (tmp2 == 0){
- tmp2 = 1;
- tmp3 = 1;
- }
- //1. set mask 2. write value to data transfer register 3. start the transfer
- //SCT(FracRate)
- AMAZON_WRITE_REGISTER_L(QSB_SET_SCT_MASK, QSB_RTM_ADDR);
- AMAZON_WRITE_REGISTER_L(tmp3,QSB_RTD_ADDR);
- AMAZON_WRITE_REGISTER_L(((QSB_TABLESEL_SCT<<QSB_TABLESEL_SHIFT)|QSB_RAMAC_REG_LOW|QSB_WRITE|i),QSB_RAMAC_ADDR);
- //SPT(SBV + PN + IntRage)
- AMAZON_WRITE_REGISTER_L(QSB_SET_SPT_MASK, QSB_RTM_ADDR);
- AMAZON_WRITE_REGISTER_L(QSB_SPT_SBVALID|tmp2|(i<<16),QSB_RTD_ADDR);
- AMAZON_WRITE_REGISTER_L(((QSB_TABLESEL_SPT<<QSB_TABLESEL_SHIFT)|QSB_RAMAC_REG_LOW|QSB_WRITE|i),QSB_RAMAC_ADDR);
-
-
- }
- }
-
- //SWIE: Setup Service Request Control Registers to enable interrupts
- AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS | SRC_SRE_ENABLE | AMAZON_SWIE_INT, SWIE_ISRC_ADDR);
- AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS | SRC_SRE_ENABLE | AMAZON_SWIE_INT, SWIE_ESRC_ADDR);
-
- wmb();
-#ifdef AMAZON_TPE_TEST_AAL5_INT
- AMAZON_WRITE_REGISTER_L(AAL5R_ISR_FE,AAL5_RIMR0_ADDR);
- AMAZON_WRITE_REGISTER_L(0, AAL5_SIMR0_ADDR);
- AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS | SRC_SRE_ENABLE | AMAZON_AAL5_INT,AAL5_SSRC0_ADDR);
- AMAZON_WRITE_REGISTER_L(SRC_CLRR|SRC_TOS_MIPS | SRC_SRE_ENABLE | AMAZON_AAL5_INT,AAL5_RSRC0_ADDR);
-#endif //AMAZON_TPE_TEST_AAL5_INT
-
- AMAZON_WRITE_REGISTER_L(dev->aal5.tx_max_sdu,AAL5_SMFL_ADDR);
- AMAZON_WRITE_REGISTER_L(dev->aal5.rx_max_sdu,AAL5_RMFL_ADDR);
- AMAZON_WRITE_REGISTER_L(AAL5_SCMD_MODE_POLL // enable polling mode
- |AAL5_SCMD_SS
- |AAL5_SCMD_AR
- ,AAL5_SCMD_ADDR);
- //start CBM
- AMAZON_WRITE_REGISTER_L(CBM_CFG_START,CBM_CFG_ADDR);
- wmb();
- return 0;
-init_no_mem:
- if (mem_addr != NULL) free_pages((unsigned long)mem_addr,get_log_2(((CBM_CELL_SIZE * dev->cbm.free_cell_cnt) >>PAGE_SHIFT) + 1));
-
-#ifdef CONFIG_USE_VENUS
- //to work around a bug, bit15 of QDOFF address should be 1
- if (qd_addr != NULL) free_pages((unsigned long)qd_addr,4);
-#else //CONFIG_USE_VENUS
- if (qd_addr != NULL) kfree(qd_addr);
-#endif //CONFIG_USE_VENUS
- return -ENOMEM;
-}
-
-/*
- * Brief: Create entry in /proc for status information
- */
-void atm_create_proc(void)
-{
- create_proc_read_entry("amazon_atm", 0,NULL, amazon_atm_read_procmem,(void*)PROC_ATM);
- create_proc_read_entry("amazon_atm_mib", 0,NULL, amazon_atm_read_procmem,(void*)PROC_MIB);
- create_proc_read_entry("amazon_atm_vcc", 0,NULL, amazon_atm_read_procmem,(void*)PROC_VCC);
-#if 0
- create_proc_read_entry("amazon_atm_aal5", 0,NULL, amazon_atm_read_procmem,(void*)PROC_AAL5);
- create_proc_read_entry("amazon_atm_cbm", 0,NULL, amazon_atm_read_procmem,(void*)PROC_CBM);
- create_proc_read_entry("amazon_atm_htu", 0,NULL, amazon_atm_read_procmem,(void*)PROC_HTU);
- create_proc_read_entry("amazon_atm_qsb", 0,NULL, amazon_atm_read_procmem,(void*)PROC_QSB);
- create_proc_read_entry("amazon_atm_swie", 0,NULL, amazon_atm_read_procmem,(void*)PROC_SWIE);
-#endif
-}
-
-/*
- * Brief: Delete entry in /proc for status information
- */
-void atm_delete_proc(void)
-{
- remove_proc_entry("amazon_atm", NULL);
- remove_proc_entry("amazon_atm_mib", NULL);
- remove_proc_entry("amazon_atm_vcc", NULL);
-#if 0
- remove_proc_entry("amazon_atm_aal5", NULL);
- remove_proc_entry("amazon_atm_cbm", NULL);
- remove_proc_entry("amazon_atm_htu", NULL);
- remove_proc_entry("amazon_atm_qsb", NULL);
- remove_proc_entry("amazon_atm_swie", NULL);
-#endif
-}
-/* Brief: Initialize ATM module
- * Parameters: no
- * Return: &g_atm_dev - sucessful
- * NULL - fails:
- * 1. invalid parameter
- * 2. No memory available
- * Description:
- * This function configure the TPE components according to the input info,
- * -CBM
- * -HTU
- * -QSB
- * -AAL5
- *
- */
-amazon_atm_dev_t * amazon_atm_create(void)
-{
- int i;
- AMAZON_TPE_DMSG("atm_init\n");
- /************initialize global data structure****************/
- atm_constructor(&g_atm_dev);
- /***********allocate kernel resources****************/
- //bottom halfs for SWEX
- swex_start_task.routine = amazon_atm_swex;
- swex_start_task.data = NULL;
- swex_complete_task.routine = amazon_atm_swex_push;
- swex_complete_task.data = NULL;
-#ifdef AMAZON_TPE_SCR
- a5r_task.routine = amazon_atm_a5r;
- a5r_task.data = NULL;
-#endif //AMAZON_TPE_SCR
- //SWIN semaphore
- sema_init(&(g_atm_dev.swie.in_sem), 1);
- //SWIE lock
- clear_bit(SWIE_LOCK, &(g_atm_dev.swie.lock));
- //SWIE wait queue
- init_waitqueue_head(&(g_atm_dev.swie.sleep));
- atm_create_proc();
-
- //register DMA
- memset(&g_dma_dev,0,sizeof(struct dma_device_info));
- strcpy(g_dma_dev.device_name,"TPE");
- g_dma_dev.weight=1;
- g_dma_dev.num_tx_chan=2;
- g_dma_dev.num_rx_chan=2;
- g_dma_dev.ack=1;
- g_dma_dev.tx_burst_len=4;
- g_dma_dev.rx_burst_len=4;
- //DMA TX
-
- for(i=0;i<1;i++){
- g_dma_dev.tx_chan[i].weight=QOS_DEFAULT_WGT;
- g_dma_dev.tx_chan[i].desc_num=10;
- g_dma_dev.tx_chan[i].packet_size=g_atm_dev.aal5.tx_max_sdu + AAL5S_INBOUND_HEADER;
- g_dma_dev.tx_chan[i].control=1;
- }
- //DMA RX
- for(i=0;i<2;i++){
- g_dma_dev.rx_chan[i].weight=QOS_DEFAULT_WGT;
- /* BingTao's suggestion, change from 5->10 will prevent packet loss in NO_TX_INT mode */
- g_dma_dev.rx_chan[i].desc_num=10;
- g_dma_dev.rx_chan[i].packet_size=(g_atm_dev.aal5.rx_max_sdu + AAL5R_TRAILER_LEN+0x10f)&(~0xf);
- g_dma_dev.rx_chan[i].control=1;
- }
- g_dma_dev.intr_handler=amazon_atm_dma_handler;
- g_dma_dev.buffer_alloc=amazon_atm_alloc_rx;
- g_dma_dev.buffer_free=amazon_atm_free_tx;
- dma_device_register(&g_dma_dev);
-/***********intialize the atm hardware ****************/
- if ( atm_init_hard(&g_atm_dev) != 0){
- return NULL;
- }
- //start CBM
- AMAZON_WRITE_REGISTER_L(CBM_CFG_START,CBM_CFG_ADDR);
- wmb();
-
- //Start HTU
- AMAZON_WRITE_REGISTER_L(HTU_CFG_START ,HTU_CFG_ADDR);
- wmb();
-
-
- // Register interrupts for insertion and extraction
- request_irq(AMAZON_SWIE_INT, amazon_atm_swie_isr, IRQF_DISABLED, "tpe_swie", NULL);
- request_irq(AMAZON_CBM_INT, amazon_atm_cbm_isr, IRQF_DISABLED, "tpe_cbm", NULL);
-#ifdef AMAZON_ATM_DEBUG
- request_irq(AMAZON_HTU_INT , amazon_atm_htu_isr, IRQF_DISABLED, "tpe_htu", NULL);
-#endif
-#ifdef AMAZON_TPE_TEST_AAL5_INT
- request_irq(AMAZON_AAL5_INT, amazon_atm_aal5_isr, IRQF_DISABLED, "tpe_aal5", NULL);
-#endif
- return &g_atm_dev;
-}
-
-/* Brief: clean up atm
- * Parameters: no
- * Return: no
- * Description:
- * Disable the device.
- */
-void amazon_atm_cleanup(void){
- int i;
- clear_bit(SWIE_LOCK, &(g_atm_dev.swie.lock));
- wake_up(&g_atm_dev.swie.sleep);
- up(&g_atm_dev.swie.in_sem);
- // diable SWIE interrupts
- AMAZON_WRITE_REGISTER_L(0, SWIE_ISRC_ADDR);
- AMAZON_WRITE_REGISTER_L(0, SWIE_ESRC_ADDR);
- wmb();
-
- // Disable schedulers ( including interrupts )-----------------------
- for (i = 0; i < AMAZON_ATM_PORT_NUM; i++);
- {
- AMAZON_WRITE_REGISTER_L(QSB_SET_SPT_SBVALID_MASK, QSB_RTM_ADDR);
- AMAZON_WRITE_REGISTER_L( 0 ,QSB_RTD_ADDR);
- AMAZON_WRITE_REGISTER_L( (QSB_TABLESEL_SPT<<QSB_TABLESEL_SHIFT)
- | QSB_RAMAC_REG_LOW
- | QSB_WRITE
- | i,
- QSB_RAMAC_ADDR);
- }
- // disable QSB_Interrupts
- AMAZON_WRITE_REGISTER_L( 0, QSB_IMR_ADDR);
- AMAZON_WRITE_REGISTER_L( 0, QSB_SRC_ADDR);
- // disable CBM interrupts
- AMAZON_WRITE_REGISTER_L( 0 , CBM_IMR0_ADDR);
- AMAZON_WRITE_REGISTER_L( 0 , CBM_SRC0_ADDR);
- // set CBM start bit to 0
- AMAZON_WRITE_REGISTER_L(0,CBM_CFG_ADDR);
- // request hardware extraction of queue 0, wich should force the CBM
- // to recognize that the start bit is not set
- AMAZON_WRITE_REGISTER_L(CBM_HWEXPAR_PN_A5, CBM_HWEXPAR0_ADDR);
- // write frame extraction command into the hw extract command register
- AMAZON_WRITE_REGISTER_L(CBM_HWEXCMD_FE0, CBM_HWEXCMD_ADDR);
- // disable htu
- // disable all HTU interrupts
- AMAZON_WRITE_REGISTER_L(0 ,HTU_IMR0_ADDR);
- AMAZON_WRITE_REGISTER_L(0 ,HTU_SRC0_ADDR);
-
- if (g_atm_dev.cbm.allocated){
- free_pages((unsigned long)g_atm_dev.cbm.mem_addr, get_log_2(((CBM_CELL_SIZE * g_atm_dev.cbm.free_cell_cnt) >>PAGE_SHIFT)+1));
-#ifdef CONFIG_USE_VENUS
- //to work around a bug, bit15 of QDOFF address should be 1
- free_pages((unsigned long)g_atm_dev.cbm.qd_addr_free,4);
-#else //CONFIG_USE_VENUS
- kfree(g_atm_dev.cbm.qd_addr);
-#endif //CONFIG_USE_VENUS
- }
- atm_delete_proc();
- // free interrupts for insertion and extraction
- dma_device_unregister(&g_dma_dev);
- free_irq(AMAZON_SWIE_INT, NULL);
- free_irq(AMAZON_CBM_INT, NULL);
-#ifdef AMAZON_ATM_DEBUG
- free_irq(AMAZON_HTU_INT, NULL);
-#endif
-#ifdef AMAZON_TPE_TEST_AAL5_INT
- free_irq(AMAZON_AAL5_INT, NULL);
-#endif
-
-}
-
-/************************ ATM network interface ***********************************************/
-/* Brief: getsockopt
- */
-int amazon_atm_getsockopt(struct atm_vcc *vcc, int level, int optname, char *optval, int optlen)
-{
- int err=0;
- atm_aal5_vcc_t mib_vcc;
- AMAZON_TPE_DMSG("1\n");
- switch (optname){
- case SO_AMAZON_ATM_MIB_VCC:
- AMAZON_TPE_DMSG("2\n");
- err = amazon_atm_vcc_mib(vcc, &mib_vcc);
- AMAZON_TPE_DMSG("%u\n",mib_vcc.aal5VccCrcErrors);
- err = copy_to_user((void *)optval,&mib_vcc, sizeof(mib_vcc));
- AMAZON_TPE_DMSG("err %u\n",err);
- break;
- default:
- return -EFAULT;
- }
- return err;
-}
-
-/* Brief: IOCTL
- */
-
-int amazon_atm_ioctl(struct atm_dev *dev,unsigned int cmd,void *arg)
-{
- int err=0;
- //MIB
- atm_cell_ifEntry_t mib_cell;
- atm_aal5_ifEntry_t mib_aal5;
- atm_aal5_vcc_x_t mib_vcc;
- if (_IOC_TYPE(cmd) != AMAZON_ATM_IOC_MAGIC) return -ENOTTY;
- if (_IOC_NR(cmd) > AMAZON_ATM_IOC_MAXNR) return -ENOTTY;
-
- if (_IOC_DIR(cmd) & _IOC_READ)
- err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
- else if (_IOC_DIR(cmd) & _IOC_WRITE)
- err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
- if (err) {
- AMAZON_TPE_EMSG("acess verification fails \n");
- return -EFAULT;
- }
- switch(cmd) {
- case AMAZON_ATM_MIB_CELL:
- err = amazon_atm_cell_mib(&mib_cell,(u32)arg);
- if (err==0){
- err = __copy_to_user((void *)arg,&mib_cell,sizeof(mib_cell));
- }else{
- AMAZON_TPE_EMSG("cannot get MIB ATM_CELL\n");
- }
- break;
- case AMAZON_ATM_MIB_AAL5:
- err = amazon_atm_aal5_mib(&mib_aal5);
- if (err==0){
- err=__copy_to_user(arg, &mib_aal5, sizeof(mib_aal5));
- }else{
- AMAZON_TPE_EMSG("cannot get MIB ATM_AAL5\n");
- }
- break;
- case AMAZON_ATM_MIB_VCC:
- err=__copy_from_user(&mib_vcc,arg, sizeof(mib_vcc));
- AMAZON_TPE_DMSG("return of copy_from_user %x\n",err);
- err = amazon_atm_vcc_mib_x(mib_vcc.vpi, mib_vcc.vci, &(mib_vcc.mib_vcc));
- if (err==0){
- err=__copy_to_user(arg, &mib_vcc, sizeof(mib_vcc));
- }else{
- AMAZON_TPE_EMSG("cannot get MIB ATM_VCC\n");
- }
-
- default:
- return -ENOTTY;
- }
- return err;
-}
-/* Brief: return a link list of OAM related time stamp info
- * Parameter: none
- * Return:
- a link list of "struct oam_last_activity" data
- * Description:
- Each time, a F4/F5 cell or AAL5 packet is received, the time stamp is updated.
- Through this call, u get a list of this time stamp for all active connection.
- Please note that u have read-only access.
- */
-const struct oam_last_activity* get_oam_time_stamp()
-{
- int i,j;
- for(i=CBM_DEFAULT_Q_OFFSET+CBM_RX_OFFSET,j=0;i<CBM_RX_OFFSET+CBM_DEFAULT_Q_OFFSET+AMAZON_ATM_MAX_VCC_NUM;i++){
- if (g_atm_dev.queues[i].free != 1 && g_atm_dev.queues[i].vcc != NULL){
- //active connection
- if (j !=0 ){
- g_oam_time_stamp[j-1].next = &g_oam_time_stamp[j];
- }
- g_oam_time_stamp[j].vpi = g_atm_dev.queues[i].vcc->vpi;
- g_oam_time_stamp[j].vci = g_atm_dev.queues[i].vcc->vci;
- g_oam_time_stamp[j].stamp = g_atm_dev.queues[i].access_time;
- g_oam_time_stamp[j].next = NULL;
- j++;
- }
- }
- if (j==0) {
- return NULL;
- }else{
- return g_oam_time_stamp;
- }
-}
-
-
-/* Brief: call back routine for rx
- * Parameter:
- * vcc atm_vcc pointer
- * skb data if no error
- err error flag, 0: no error, 1:error
- * Return:
- * 0
- * <>0 cannot push up
- * Description:
- * release the packet if cannot push up
- */
-static int amazon_atm_net_push(struct atm_vcc *vcc,struct sk_buff *skb, int err)
-{
- if (err){
- if (vcc && vcc->stats) {
- atomic_inc(&vcc->stats->rx_err);
- }
- }else{
- ATM_SKB(skb)->vcc = vcc;
-
- if (!atm_charge(vcc, skb->truesize)){
- //no space this vcc
- AMAZON_TPE_EMSG("no space for this vcc\n");
- dev_kfree_skb_any(skb);
- return -ENOMEM;
- }
- atomic_inc(&vcc->stats->rx);
- AMAZON_TPE_DMSG("push to vcc\n");
- vcc->push(vcc,skb);
- }
- return 0;
-}
-int amazon_atm_net_send_oam(struct atm_vcc*vcc, void *cell, int flags)
-{
- return amazon_atm_send_oam(vcc,cell,flags);
-}
-
-int amazon_atm_net_send(struct atm_vcc *vcc,struct sk_buff *skb)
-{
- int err=0;
- if (vcc->qos.aal == ATM_AAL0 || vcc->qos.aal == ATM_AAL5) {
- err=amazon_atm_send(vcc,skb);
- }else{
- //not supported
- err = -EPROTONOSUPPORT;
- }
- if (err){
- atomic_inc(&vcc->stats->tx_err);
- }else{
- atomic_inc(&vcc->stats->tx);
- }
- AMAZON_TPE_DMSG("sent, tx_inuse:%u\n", atomic_read(&vcc->tx_inuse));
- return err;
-}
-
-int amazon_atm_net_open(struct atm_vcc *vcc,short vpi, int vci)
-{
- vcc->itf = (int) vcc->dev->dev_data;
- vcc->vpi = vpi;
- vcc->vci = vci;
- return(amazon_atm_open(vcc,amazon_atm_net_push));
-}
-
-static int amazon_atm_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flgs)
-{
- int qid;
-
- if (vcc == NULL || qos == NULL){
- AMAZON_TPE_EMSG("invalid parameters\n");
- return -EINVAL;
- }
- qid = amazon_atm_get_queue(vcc);
- if (valid_qid(qid) != 1) {
- AMAZON_TPE_EMSG("no vcc connection opened\n");
- return -EINVAL;
- }
- set_qsb(vcc,qos,qid);
- return 0;
-}
-
-static struct atmdev_ops amazon_atm_ops = {
- open: amazon_atm_net_open,
- close: amazon_atm_close,
- ioctl: amazon_atm_ioctl,
- send: amazon_atm_net_send,
- send_oam: amazon_atm_net_send_oam,
-// getsockopt: amazon_atm_getsockopt,
- change_qos: amazon_atm_change_qos,
-// proc_read: amazon_atm_proc_read,
- owner: THIS_MODULE,
-}; // ATM device callback functions
-
-/*
- * brief "/proc" function
- */
-int amazon_atm_read_procmem(char *buf, char **start, off_t offset,int count, int *eof, void *data)
-{
- int buf_off=0; /* for buf */
- int i=0,j=0;
- int type= (u32)data;//which module
- atm_aal5_ifEntry_t mib_aal5;
- atm_cell_ifEntry_t mib_cell;
- atm_aal5_vcc_t mib_vcc;
- switch(type){
- case PROC_MIB:
- //MIB counter
- amazon_atm_aal5_mib(&mib_aal5);
- //TX:
- buf_off+=sprintf(buf+buf_off,"\n============= AAL5 Upstream =========\n");
- buf_off+=sprintf(buf+buf_off,"received %u (pkts) from upper layer\n", mib_aal5.ifOutUcastPkts);
- buf_off+=sprintf(buf+buf_off,"errors: %u (pkts)\n",mib_aal5.ifOutErros);
- buf_off+=sprintf(buf+buf_off,"discards: %u (ptks)\n", mib_aal5.ifOutDiscards);
- buf_off+=sprintf(buf+buf_off,"transmitted: %x-%x (bytes) \n",
- mib_aal5.ifHCOutOctets_h, mib_aal5.ifHCOutOctets_l);
- //RX:
- buf_off+=sprintf(buf+buf_off,"\n============= AAL5 Downstream =========\n");
- buf_off+=sprintf(buf+buf_off,"received %x-%x (bytes)\n",
- mib_aal5.ifHCInOctets_h,mib_aal5.ifHCInOctets_l);
- buf_off+=sprintf(buf+buf_off,"discards: %u (ptks)\n",mib_aal5.ifInDiscards);
- buf_off+=sprintf(buf+buf_off,"errors: %u (ptks)\n",mib_aal5.ifInErrors);
- buf_off+=sprintf(buf+buf_off,"passed %u (ptks) to upper layer\n",mib_aal5.ifInUcastPkts);
-
- //Cell level
- buf_off+=sprintf(buf+buf_off,"\n============= ATM Cell =========\n");
- amazon_atm_cell_mib(&mib_cell,0);
-#ifdef AMAZON_TPE_READ_ARC
- buf_off+=sprintf(buf+buf_off,"Port 0: downstream received: %x-%x (bytes)\n",mib_cell.ifHCInOctets_h,mib_cell.ifHCInOctets_l);
- buf_off+=sprintf(buf+buf_off,"Port 0: upstream transmitted: %x-%x (bytes)\n",mib_cell.ifHCOutOctets_h,mib_cell.ifHCOutOctets_l);
- buf_off+=sprintf(buf+buf_off,"Port 0: downstream errors: %u (cells)\n",mib_cell.ifInErrors);
- amazon_atm_cell_mib(&mib_cell,1);
- buf_off+=sprintf(buf+buf_off,"Port 1: downstream received: %x-%x (bytes)\n",mib_cell.ifHCInOctets_h,mib_cell.ifHCInOctets_l);
- buf_off+=sprintf(buf+buf_off,"Port 1: upstream transmitted: %x-%x (bytes)\n",mib_cell.ifHCOutOctets_h,mib_cell.ifHCOutOctets_l);
- buf_off+=sprintf(buf+buf_off,"Port 1: downstream errors: %u (cells)\n",mib_cell.ifInErrors);
-#endif
- buf_off+=sprintf(buf+buf_off,"HTU discards: %u (cells)\n",mib_cell.ifInUnknownProtos);
-
- buf_off+=sprintf(buf+buf_off,"\n====== Specials =====\n");
- buf_off+=sprintf(buf+buf_off,"AAL5S PPD: %u (cells)\n",g_atm_dev.mib_counter.tx_ppd);
-#ifdef AMAZON_TPE_SCR
- buf_off+=sprintf(buf+buf_off,"Reassembly wait: %u \n",g_a5r_wait);
-#endif
- break;
- case PROC_ATM:
- //Interface (Port)
- buf_off+=sprintf(buf+buf_off,"[Interfaces]\n");
- for(i=0;i<AMAZON_ATM_PORT_NUM;i++){
- if (g_atm_dev.ports[i].enable==0){
- buf_off+=sprintf(buf+buf_off,"\tport[%u] not in use\n",i);
- }else{
- buf_off+=sprintf(buf+buf_off,"\tport[%u]\n\t\tmax_conn=%u\n"
- ,i
- ,g_atm_dev.ports[i].max_conn
- );
- buf_off+=sprintf(buf+buf_off,"\t\ttx_max=%u\n\t\trem=%u\n\t\tcur=%u\n"
- ,g_atm_dev.ports[i].tx_max_cr
- ,g_atm_dev.ports[i].tx_rem_cr
- ,g_atm_dev.ports[i].tx_cur_cr
- );
- }
-
- }
- //Units Info
- //AAL5
- buf_off+=sprintf(buf+buf_off,"[AAL5]\n\tpad=%c(%x)\n\trx_mtu=%u\n\ttx_mtu=%u\n"
- ,g_atm_dev.aal5.padding_byte
- ,g_atm_dev.aal5.padding_byte
- ,g_atm_dev.aal5.rx_max_sdu
- ,g_atm_dev.aal5.tx_max_sdu
- );
- //CBM
- buf_off+=sprintf(buf+buf_off,
- "[CBM]\n\tnrt_thr=%u\n\tclp0_thr=%u\n\tclp1_thr=%u\n\ttx_q_threshold=%u\n\trx_q_threshold=%u\n\toam_q_threshold=%u\n\tfree_cell_cnt=%u\n"
- ,g_atm_dev.cbm.nrt_thr
- ,g_atm_dev.cbm.clp0_thr
- ,g_atm_dev.cbm.clp1_thr
- ,tx_q_threshold
- ,rx_q_threshold
- ,oam_q_threshold
- ,g_atm_dev.cbm.free_cell_cnt
- );
- //QSB
- buf_off+=sprintf(buf+buf_off,"[QSB]\n\ttau=%u\n\ttstepc=%u\n\tsbl=%u\n"
- ,g_atm_dev.qsb.tau
- ,g_atm_dev.qsb.tstepc
- ,g_atm_dev.qsb.sbl
- );
- buf_off+=sprintf(buf+buf_off,"[Debugging]\n\taal5_need_copy=%u\n",g_atm_dev.aal5.cnt_cpy);
- break;
- case PROC_VCC:
- for(i=CBM_DEFAULT_Q_OFFSET,j=0;i<g_atm_dev.cbm.max_q_off+CBM_DEFAULT_Q_OFFSET;i++){
- if (g_atm_dev.queues[i].free!=1){
- buf_off+=sprintf(buf+buf_off,"vcc[%u]\n\tvpi=%u vci=%u itf=%u qid=%u access_time=%u.%u\n"
- ,j++
- ,g_atm_dev.queues[i].vcc->vpi
- ,g_atm_dev.queues[i].vcc->vci
- ,g_atm_dev.queues[i].vcc->itf
- ,i
- ,(u32)g_atm_dev.queues[i+CBM_RX_OFFSET].access_time.tv_sec
- ,(u32)g_atm_dev.queues[i+CBM_RX_OFFSET].access_time.tv_usec
- );
- buf_off+=sprintf(buf+buf_off,"\tqos_tx class=%u max_pcr=%u pcr=%u min_pcr=%u scr=%u mbs=%u cdv=%u\n"
- ,g_atm_dev.queues[i].vcc->qos.txtp.traffic_class
- ,g_atm_dev.queues[i].vcc->qos.txtp.max_pcr
- ,g_atm_dev.queues[i].vcc->qos.txtp.pcr
- ,g_atm_dev.queues[i].vcc->qos.txtp.min_pcr
- ,g_atm_dev.queues[i].vcc->qos.txtp.scr
- ,g_atm_dev.queues[i].vcc->qos.txtp.mbs
- ,g_atm_dev.queues[i].vcc->qos.txtp.cdv
- );
- buf_off+=sprintf(buf+buf_off,"\tqos_rx class=%u max_pcr=%u pcr=%u min_pcr=%u scr=%u mbs=%u cdv=%u\n"
- ,g_atm_dev.queues[i].vcc->qos.rxtp.traffic_class
- ,g_atm_dev.queues[i].vcc->qos.rxtp.max_pcr
- ,g_atm_dev.queues[i].vcc->qos.rxtp.pcr
- ,g_atm_dev.queues[i].vcc->qos.rxtp.min_pcr
- ,g_atm_dev.queues[i].vcc->qos.rxtp.scr
- ,g_atm_dev.queues[i].vcc->qos.rxtp.mbs
- ,g_atm_dev.queues[i].vcc->qos.rxtp.cdv
- );
- __amazon_atm_vcc_mib((i+CBM_RX_OFFSET),&mib_vcc);
- buf_off+=sprintf(buf+buf_off,"\tCRC error=%u\n", mib_vcc.aal5VccCrcErrors);
- buf_off+=sprintf(buf+buf_off,"\toversized packet=%u\n", mib_vcc.aal5VccOverSizedSDUs);
-#ifdef AMAZON_ATM_DEBUG
- if ( valid_qid(i+CBM_RX_OFFSET)){
- buf_off+=sprintf(buf+buf_off,"\tdownstream statics\n" );
- buf_off+=sprintf(buf+buf_off,"\t\tpackets=%u\n",g_atm_dev.queues[i+CBM_RX_OFFSET].qs[QS_PKT]);
- buf_off+=sprintf(buf+buf_off,"\t\terr_packets=%u\n",g_atm_dev.queues[i+CBM_RX_OFFSET].qs[QS_ERR] );
- buf_off+=sprintf(buf+buf_off,"\t\tsw_dropped=%u\n",g_atm_dev.queues[i+CBM_RX_OFFSET].qs[QS_SW_DROP] );
- }
-
- buf_off+=sprintf(buf+buf_off,"\tupstream statics\n" );
- buf_off+=sprintf(buf+buf_off,"\t\tpackets=%u\n",g_atm_dev.queues[i].qs[QS_PKT]);
- buf_off+=sprintf(buf+buf_off,"\t\terr_packets=%u\n",g_atm_dev.queues[i].qs[QS_ERR] );
- buf_off+=sprintf(buf+buf_off,"\t\thw_dropped=%u\n",g_atm_dev.queues[i].qs[QS_HW_DROP] );
- buf_off+=sprintf(buf+buf_off,"\t\tsw_dropped=%u\n",g_atm_dev.queues[i].qs[QS_SW_DROP] );
-
-#endif
-
- }
-
- }
- break;
- default:
- break;
- }
- if(buf_off>0) *eof = 1;
- return buf_off;
-}
-
-#ifdef AMAZON_TPE_AAL5_RECOVERY
-extern int (*tpe_reset)(void);
-extern int (*tpe_start)(void);
-extern int (*tpe_inject)(void);
-/* Brief: Reset TPE hardware
- * Description
- * This is a wordaround for AAL5 bug. It tries to reset TPE.
- * take care of software
- * setup all previous connection
- */
-int amazon_tpe_reset(void)
-{
- struct atm_vcc * vcc;
- int err=0;
- int i;
- u8 * qd_addr;
- u32 reg_l, reg_h;
- unsigned int a_cfg_value=0;
- unsigned int a_cfg_old_value=0;
- atm_aal5_ifEntry_t mib_aal5;
- atm_cell_ifEntry_t mib_cell;
-
- //make sure all cells transmitting out first
- //Segmentation done
- amazon_atm_aal5_mib(&mib_aal5);
- reg_l = g_atm_dev.mib_counter.tx_cnt_l;
- reg_h = g_atm_dev.mib_counter.tx_cnt_h;
- while(1){
- mdelay(10);
- amazon_atm_aal5_mib(&mib_aal5);
- if( (reg_l == g_atm_dev.mib_counter.tx_cnt_l) && (reg_h == g_atm_dev.mib_counter.tx_cnt_h) ){
- break;
- }
- AMAZON_TPE_DMSG("AAL5 Segmentation still in progress!\n");
- reg_l = g_atm_dev.mib_counter.tx_cnt_l;
- reg_h = g_atm_dev.mib_counter.tx_cnt_h;
- }
- //QSB done
- qd_addr = (u8 *) KSEG1ADDR((unsigned long)g_atm_dev.cbm.qd_addr);
- for (i=1;i<15;i++){
- while ( (err=readl(qd_addr+i*CBM_QD_SIZE+0x8)&0xffff) !=0 ){
- mdelay(20);
- AMAZON_TPE_DMSG("queue %u not empty (%u)\n",i,err);
- }
- }
- //insurance for interfaces between Aware and CARB
- mdelay(100);
- amazon_atm_cell_mib(&mib_cell,0);
- amazon_atm_cell_mib(&mib_cell,1);
- amazon_atm_aal5_mib(&mib_aal5);
-
- mb();
- while ( (AMAZON_READ_REGISTER_L(AR_CELLRDY_BC0) != 0 ) || (AMAZON_READ_REGISTER_L(AR_CELLRDY_BC0) != 0 ) ){
- AMAZON_TPE_EMSG("\nwaiting for AWARE");
- AMAZON_TPE_EMSG(" BC0 %u ", AMAZON_READ_REGISTER_L(AR_CELLRDY_BC0));
- AMAZON_TPE_EMSG(" BC1 %u ", AMAZON_READ_REGISTER_L(AR_CELLRDY_BC1));
- AMAZON_TPE_EMSG("\n");
- mdelay(1);
- }
- // disable AAI module
- meiDebugRead(A_CFG_ADDR,&a_cfg_value,1);
- a_cfg_old_value=a_cfg_value;
- a_cfg_value &= (~(0x2800));
- meiDebugWrite(A_CFG_ADDR,&a_cfg_value,1);
- //clear buffer
- a_cfg_value = 0x1;
- meiDebugWrite(AR_CB0_STATUS_ADDR,&a_cfg_value,1);
- meiDebugWrite(AR_CB1_STATUS_ADDR,&a_cfg_value,1);
-
- if ( atm_init_hard(&g_atm_dev) != 0){
- return -EIO;
- }
- sema_init(&(g_atm_dev.swie.in_sem), 1);
- //SWIE lock
- clear_bit(SWIE_LOCK, &(g_atm_dev.swie.lock));
- //SWIE wait queue
- init_waitqueue_head(&(g_atm_dev.swie.sleep));
-
- for (i=CBM_DEFAULT_Q_OFFSET;i<AMAZON_ATM_MAX_QUEUE_NUM/2;i++) {
- vcc = g_atm_dev.queues[i].vcc;
- if (vcc != NULL){
- set_qsb(vcc, &vcc->qos, i);
- set_qd(vcc, i);
- mb();
- err=set_htu(vcc,i);
- if (err){
- AMAZON_TPE_EMSG("set htu entry fails %u\n",err);
- }
- }
- }
- meiDebugWrite(A_CFG_ADDR,&a_cfg_old_value,1);
-#if 0
- //reset DFE
- *(AMAZON_RST_REQ) = (* AMAZON_RST_REQ) | (AMAZON_RST_REQ_DFE);
- mb();
- *(AMAZON_RST_REQ) = (* AMAZON_RST_REQ) & (~AMAZON_RST_REQ_DFE);
- mb();
-#endif
-
- return 0;
-}
-
-/* Brief: Send a ATM EoP packet to save DMA channel
- */
-int amazon_tpe_inject_debug_cell(void)
-{
- //Send a ATM cell to save DMA channel
- u8 qid;
- unsigned char atm_cell[48];
- qid = 0x11;
- AMAZON_TPE_DMSG("qid = %d\n",qid);
- memset(atm_cell,0,48);
- atm_cell[3] = 0x2;
- if ( amazon_atm_swin(qid,atm_cell)) {
- AMAZON_TPE_EMSG("cannot insert EoP cell\n");
- return -1;
- }
- return 0;
-}
-
-/* Brief: start HTU (TPE)
- */
-
-int amazon_tpe_start(void)
-{
- AMAZON_WRITE_REGISTER_L(HTU_CFG_START ,HTU_CFG_ADDR);
- wmb();
- return 0;
-}
-#endif //AMAZON_TPE_AAL5_RECOVERY
-
-#ifdef AMAZON_CHECK_LINK
-extern int (*adsl_link_notify)(int);
-/* Brief: notify link status of ADSL link
- * Parameters: 0 link down
- * 1 link up
- * Returns: 0 OK
- * Details: called by MEI driver
- * should update status and inform upper layer
- */
-int amazon_tpe_link_notify(int status)
-{
- adsl_link_status = status;
- AMAZON_TPE_DMSG("link status %s\n",(status==1)?"Up":"Down");
- if (status == 0){
- //wait until no cells in upstream queues
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(2*HZ);
- }
- return 0;
-}
-#endif //ifdef AMAZON_CHECK_LINK
-
-/*
- * Brief: Initialize ATM module
- *
- * Return Value: ENOMEM - No memory available
- * EBUSY - Cannot register atm device
- * ERESTARTSYS - Process interrupted by other signal
- * 0 - OK, module initialized
- *
- * Description:
- * This function registers an atm device for all UTOPIA devices.
- * It also allocates memory for the private device data structures
- */
-int __init amazon_atm_net_init(void)
-{
- int i;
- int err=0;
- amazon_atm_dev_t *dev = NULL;
-
- if ((dev=amazon_atm_create()) != NULL){
- for(i=0;i<AMAZON_ATM_PORT_NUM;i++){
- if (!dev->ports[i].enable){
- amazon_atm_devs[i] = NULL;
- continue;
- }
- amazon_atm_devs[i] =atm_dev_register("amazon_atm",&amazon_atm_ops,-1,0UL);
- if (amazon_atm_devs[i] == NULL){
- AMAZON_TPE_EMSG("atm_dev_register fails\n");
- err = -EIO;
- goto amazon_atm_net_init_exit;
- }else{
- AMAZON_TPE_DMSG("registering device %u\n",i);
- amazon_atm_devs[i]->ci_range.vpi_bits = 8;
- amazon_atm_devs[i]->ci_range.vci_bits = 16;
- amazon_atm_devs[i]->link_rate = dev->ports[i].tx_max_cr;
- amazon_atm_devs[i]->dev_data = (void *) i;
- }
- }
-
- }else{
- err = -ENOMEM;
- AMAZON_TPE_EMSG("cannot init atm device\n");
- goto amazon_atm_net_init_exit;
- }
-#ifdef AMAZON_TPE_AAL5_RECOVERY
- tpe_reset = & amazon_tpe_reset;
- tpe_start = & amazon_tpe_start;
- tpe_inject = & amazon_tpe_inject_debug_cell;
-#endif //AMAZON_TPE_AAL5_RECOVERY
-#ifdef AMAZON_CHECK_LINK
- adsl_link_notify=amazon_tpe_link_notify;
-#endif //AMAZON_CHECK_LINK
-amazon_atm_net_init_exit:
- return err;
-}
-
-void __exit amazon_atm_net_cleanup(void)
-{
- int i;
- amazon_atm_cleanup();
- for(i=0;i<AMAZON_ATM_PORT_NUM;i++){
- if (amazon_atm_devs[i] != NULL){
- AMAZON_TPE_DMSG("unregister dev %u\n",i);
- atm_dev_deregister(amazon_atm_devs[i]);
- }
- }
- return;
-}
-EXPORT_SYMBOL(get_oam_time_stamp);
-
-MODULE_LICENSE ("GPL");
-MODULE_AUTHOR("Infineon IFAP DC COM peng.liu@infineon.com");
-MODULE_DESCRIPTION("AMAZON ATM driver");
-
-module_init(amazon_atm_net_init);
-module_exit(amazon_atm_net_cleanup);
-
-
-
-
-
+++ /dev/null
-/* ============================================================================
- * Copyright (C) 2004 -Infineon Technologies AG.
- *
- * All rights reserved.
- * ============================================================================
- *
- *============================================================================
- * Licensed under GNU GPL v2
- * ============================================================================
- */
-
-
-/* ===========================================================================
- *
- * File Name: amazon_mei.c
- * Author : Ou Ke
- *
- * ===========================================================================
- *
- * Project: Amazon
- *
- * ===========================================================================
- * Contents:This file implements the MEI driver for Amazon ADSL/ADSL2+
- * controller.
- *
- * ===========================================================================
- * References:
- *
- */
-
-
-/* ===========================================================================
- * Revision History:
- * 12/1/2005 : Ritesh Banerjee
- * - Create a kernel thread kmibpoll to poll for periodic RFC 2662
- * and RFC 3440 counters. Removes the need for user space
- * adsl_mibpoll_daemon and saves atleast 30KB of RAM.
- *
- * $Log$
- * ===========================================================================
- */
-
-/*
- * ===========================================================================
- * INCLUDE FILES
- * ===========================================================================
- */
-//000002:fchang 2005/6/2 joelin 04/27/2005 for pcm clock
-//000003:fchang 2005/6/2 Henry added for Amazon-E support
-//165001:henryhsu 2005/9/6 Modify for adsl firmware version 1.2.1.2.0.1 DATA_LED can't flash.
-// 509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC
-// 603221:tc.chen 2006/03/21 added APIs to support the WEB related parameters for ADSL Statistics
-
-#ifndef EXPORT_SYMTAB
-#define EXPORT_SYMTAB
-#endif
-#define AMAZON_MEI_MIB_RFC3440
-
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <asm/irq.h>
-#include <asm/segment.h>
-#include <asm/semaphore.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <asm/uaccess.h>
-#include <linux/proc_fs.h>
-#include <asm/io.h>
-#include <linux/vmalloc.h>
-#include <linux/delay.h>
-#include <linux/poll.h>
-#include <linux/list.h>
-#include <linux/time.h>
-
-#include <asm/amazon/amazon.h>
-#include <asm/irq.h>
-#include <asm/amazon/irq.h>
-#include <asm/amazon/amazon_mei.h>
-#include <asm/amazon/amazon_mei_app.h>
-#include <asm/amazon/amazon_mei_ioctl.h>
-#include <asm/amazon/amazon_mei_app_ioctl.h>
-
-#define SET_BIT(reg, mask) reg |= (mask)
-#define CLEAR_BIT(reg, mask) reg &= (~mask)
-#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
-#define SET_BITS(reg, mask) SET_BIT(reg, mask)
-#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
-
-extern void mask_and_ack_amazon_irq(unsigned int irq_nr);
-
-#ifdef AMAZON_CHECK_LINK
-//amazon_tpe.c
-extern int (*adsl_link_notify)(int);
-#endif //AMAZON_CHECK_LINK
-
-// for ARC memory access
-#define WHILE_DELAY 20000
-#define AMAZON_DMA_DEBUG_MUTEX
-
-
-//TODO
-#undef DFE_LOOPBACK
-#define ARC_READY_ACK
-
-static amazon_mei_mib * current_intvl;
-static struct list_head interval_list;
-static amazon_mei_mib * mei_mib;
-
-static int reboot_firsttime=1;//000002:fchang
-
- //PCM
-#define PCM_CHANNEL_NUM 2 //1 rx, 1 tx
-static pcm_data_struct pcm_data[PCM_CHANNEL_NUM]__attribute__ ((aligned(4))); //0=tx0, 1=rx0, 2=tx1, 3=rx1
-static u32 pcm_start_addr;
-//#define PCM_HRT_TIME_HZ 4000 //?us
-#define PCM_ACCESS_DEBUG
-static int irqtimes=0;
-#undef DATA_LED_ON_MODE
-#define ADSL_LED_SUPPORT //joelin for adsl led
-#ifdef ADSL_LED_SUPPORT
-static int firmware_support_led=0; //joelin version check for adsl led
-static int stop_led_module=0; //wakeup and clean led module
-static int led_support_check=0; //1.1.2.7.1.1
-#endif //ADSL_LED_SUPPORT
-#define IFX_DYING_GASP
-#ifdef IFX_DYING_GASP
-static wait_queue_head_t wait_queue_dying_gasp; //dying gasp
-//struct tq_struct dying_gasp_task; //dying gasp
-static wait_queue_head_t wait_queue_uas_poll; //joelin 04/16/2005
-static u16 unavailable_seconds=0; //joelin 04/16/2005
-static meidebug lop_debugwr; //dying gasp
-#endif //IFX_DYING_GASP
-static int dbg_int=0;
-//#define DEBUG_ACCESS_DELAY for(dbg_int=0;dbg_int<100;dbg_int++){;}
-#define DEBUG_ACCESS_DELAY
-static u8 sampledata[512];
-static int firsttime[PCM_CHANNEL_NUM]={0,1};
-static int num_cmp[PCM_CHANNEL_NUM]={0,0};
-static int pcm_start_loc[PCM_CHANNEL_NUM]={0,0};
-
- // for clearEoC
-//#define MEI_CLREOC_BUFF_SIZE 512 //double the receive fifo size, bytes
-//static u8 clreoc[MEI_CLREOC_BUFF_SIZE]__attribute__ ((aligned(4))); //buffer to hold clearEoC data in bytes
-#undef AMAZON_CLEAR_EOC
-#ifdef AMAZON_CLEAR_EOC
-extern void ifx_push_eoc(struct sk_buff * pkt);
-#endif
-static int meiResetArc(void);
-#define IFX_POP_EOC_DONE 0
-#define IFX_POP_EOC_FAIL -1
-static struct list_head clreoc_list;
-static amazon_clreoc_pkt * clreoc_pkt;
-#define CLREOC_BUFF_SIZE 12 //number of clreoc commands being buffered
-//static int clreoc_wr=0;
-//static int clreoc_rd=0; //used to control clreoc circular buffer
-static wait_queue_head_t wait_queue_clreoc;
-#ifdef ADSL_LED_SUPPORT
-static wait_queue_head_t wait_queue_led; //adsl led
-static wait_queue_head_t wait_queue_led_polling;// adsl led
-struct tq_struct led_task; // adsl led
-static DECLARE_TASK_QUEUE(tq_ifx_led); // task
-int adsl_led_flash_task(void *ptr); // adsl led
-#endif //ADSL_LED_SUPPORT
-static void * clreoc_command_pkt=NULL;
-static int clreoc_max_tx_len=0;
-
-// 603221:tc.chen start
-#define ME_HDLC_IDLE 0
-#define ME_HDLC_INVALID_MSG 1
-#define ME_HDLC_MSG_QUEUED 2
-#define ME_HDLC_MSG_SENT 3
-#define ME_HDLC_RESP_RCVD 4
-#define ME_HDLC_RESP_TIMEOUT 5
-#define ME_HDLC_RX_BUF_OVERFLOW 6
-#define ME_HDLC_UNRESOLVED 1
-#define ME_HDLC_RESOLVED 2
-// 603221:tc.chen end
-
-#ifdef LOCK_RETRY
-static int reboot_lock=0;
-#endif
-
-static mib_previous_read mib_pread={0,0,0,0,0,0,0,0,0,0,0,0};
-static mib_flags_pretime mib_pflagtime;// initialized when module loaded
-
- static u32 ATUC_PERF_LOFS=0;
- static u32 ATUC_PERF_LOSS=0;
- static u32 ATUC_PERF_ESS=0;
- static u32 ATUC_PERF_INITS=0;
- static u32 ATUR_PERF_LOFS=0;
- static u32 ATUR_PERF_LOSS=0;
- static u32 ATUR_PERF_LPR=0;
- static u32 ATUR_PERF_ESS=0;
- static u32 ATUR_CHAN_RECV_BLK=0;
- static u32 ATUR_CHAN_TX_BLK=0;
- static u32 ATUR_CHAN_CORR_BLK=0;
- static u32 ATUR_CHAN_UNCORR_BLK=0;
- //RFC-3440
- static u32 ATUC_PERF_STAT_FASTR=0;
- static u32 ATUC_PERF_STAT_FAILED_FASTR=0;
- static u32 ATUC_PERF_STAT_SESL=0;
- static u32 ATUC_PERF_STAT_UASL=0;
- static u32 ATUR_PERF_STAT_SESL=0;
- static u32 ATUR_PERF_STAT_UASL=0;
-
- static adslChanPrevTxRate PrevTxRate={0,0};
- static adslPhysCurrStatus CurrStatus={0,0};
- static ChanType chantype={0,0};
- static adslLineAlarmConfProfileEntry AlarmConfProfile={"No Name\0",0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1};
-// 603221:tc.chen start
- static adslFarEndPerfStats FarendStatsData;
- struct timeval FarendData_acquire_time={0};
- static u32 adsl_mode,adsl_mode_extend; // adsl mode : adsl/ 2/ 2+
- static adslInitStats AdslInitStatsData;
-//603221:tc.chen end
-static u32 loop_diagnostics_mode=0;
-static wait_queue_head_t wait_queue_loop_diagnostic;
-#ifdef AMAZON_MEI_MIB_RFC3440
- static adslLineAlarmConfProfileExtEntry AlarmConfProfileExt={"No Name\0",0,0,0,0,0,0};
-#endif
-
-static int showtime=0;
-static int loop_diagnostics_completed=0;
-//////////////////////////////////////////////////////////////////////////////////
-static int phy_mei_net_init(struct net_device * dev);
-static int interleave_mei_net_init(struct net_device * dev);
-static int fast_mei_net_init(struct net_device * dev);
-static struct net_device_stats * phy_mei_net_get_stats(struct net_device * dev);
-static struct net_device_stats * interleave_mei_net_get_stats(struct net_device * dev);
-static struct net_device_stats * fast_mei_net_get_stats(struct net_device * dev);
-
-typedef struct mei_priv{
- struct net_device_stats stats;
-}mei_priv;
-
-static struct net_device phy_mei_net = { init: phy_mei_net_init, name: "MEI_PHY"};
-static struct net_device interleave_mei_net = { init: interleave_mei_net_init, name: "MEI_INTL"};
-static struct net_device fast_mei_net = { init: fast_mei_net_init, name: "MEI_FAST"};
-///////////////////////////////////////////////////////////////////////////////////
-
-static int major=AMAZON_MEI_MAJOR;
-
-static struct semaphore mei_sema;
-
-// Mei to ARC CMV count, reply count, ARC Indicator count
-static int indicator_count=0;
-static int cmv_count=0;
-static int reply_count=0;
-static u16 Recent_indicator[MSG_LENGTH];
-
-// Used in interrupt handler as flags
-static int arcmsgav=0;
-static int cmv_reply=0;
-static int cmv_waiting=0;
-
-#define PROC_ITEMS 8
-
-long mei_debug_mode = 0; //509221:tc.chen for adsl firmware debug
-
-// to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
-static wait_queue_head_t wait_queue_arcmsgav;
-static wait_queue_head_t wait_queue_codeswap;
-static wait_queue_head_t wait_queue_mibdaemon;
-static wait_queue_head_t wait_queue_reboot;
-static u32 * image_buffer=NULL; // holding adsl firmware image
-static u16 RxMessage[MSG_LENGTH]__attribute__ ((aligned(4)));
-static u16 TxMessage[MSG_LENGTH]__attribute__ ((aligned(4)));
-static u32 * mei_arc_swap_buff=NULL; // holding swap pages
-static ARC_IMG_HDR * img_hdr;
-static int reboot_flag;
-
-#ifdef DFE_LOOPBACK
-#include "arc_pm.h"
-#endif
-
-
-///////////////// net device ///////////////////////////////////////////////////
-static int phy_mei_net_init(struct net_device * dev)
-{
- //ether_setup(dev);
- dev->get_stats = phy_mei_net_get_stats;
- dev->ip_ptr = NULL;
- dev->type = 94;
-
-// dev->mtu=12345;
- dev->flags=IFF_UP;
-
- dev->priv = kmalloc(sizeof(struct mei_priv), GFP_KERNEL);
- if(dev->priv == NULL)
- return -ENOMEM;
- memset(dev->priv, 0, sizeof(struct mei_priv));
- return 0;
-}
-
-static int interleave_mei_net_init(struct net_device * dev)
-{
- //ether_setup(dev);
- dev->get_stats = interleave_mei_net_get_stats;
- dev->ip_ptr = NULL;
- dev->type = 124;
- dev->flags=IFF_UP;
- dev->priv = kmalloc(sizeof(struct mei_priv), GFP_KERNEL);
- if(dev->priv == NULL)
- return -ENOMEM;
- memset(dev->priv, 0, sizeof(struct mei_priv));
- return 0;
-}
-
-static int fast_mei_net_init(struct net_device * dev)
-{
- //ether_setup(dev);
- dev->get_stats = fast_mei_net_get_stats;
- dev->ip_ptr = NULL;
- dev->type = 125;
- dev->flags=IFF_UP;
- dev->priv = kmalloc(sizeof(struct mei_priv), GFP_KERNEL);
- if(dev->priv == NULL)
- return -ENOMEM;
- memset(dev->priv, 0, sizeof(struct mei_priv));
- return 0;
-}
-
-static struct net_device_stats * phy_mei_net_get_stats(struct net_device * dev)
-{
- struct mei_priv * priv;
- priv = (struct mei_priv *)dev->priv;
- // update statistics
- (priv->stats).rx_packets = ATUR_CHAN_RECV_BLK;
- (priv->stats).tx_packets = ATUR_CHAN_TX_BLK;
- (priv->stats).rx_errors = ATUR_CHAN_CORR_BLK + ATUR_CHAN_UNCORR_BLK;
- (priv->stats).rx_dropped = ATUR_CHAN_UNCORR_BLK;
-
- return &(priv->stats);
-}
-
-static struct net_device_stats * interleave_mei_net_get_stats(struct net_device * dev)
-{
- struct mei_priv * priv;
- priv = (struct mei_priv *)dev->priv;
- // update statistics
- (priv->stats).rx_packets = ATUR_CHAN_RECV_BLK;
- (priv->stats).tx_packets = ATUR_CHAN_TX_BLK;
- (priv->stats).rx_errors = ATUR_CHAN_CORR_BLK + ATUR_CHAN_UNCORR_BLK;
- (priv->stats).rx_dropped = ATUR_CHAN_UNCORR_BLK;
-
- return &(priv->stats);
-}
-
-static struct net_device_stats * fast_mei_net_get_stats(struct net_device * dev)
-{
- struct mei_priv * priv;
- priv = (struct mei_priv *)dev->priv;
- // update statistics
- (priv->stats).rx_packets = ATUR_CHAN_RECV_BLK;
- (priv->stats).tx_packets = ATUR_CHAN_TX_BLK;
- (priv->stats).rx_errors = ATUR_CHAN_CORR_BLK + ATUR_CHAN_UNCORR_BLK;
- (priv->stats).rx_dropped = ATUR_CHAN_UNCORR_BLK;
-
- return &(priv->stats);
-}
-///////////////// mei access Rd/Wr methods ///////////////////////////////////////////////////
-void meiLongwordWrite(u32 ul_address, u32 ul_data)
-{
- *((volatile u32 *)ul_address) = ul_data;
- asm("SYNC");
- return;
-} // end of "meiLongwordWrite(..."
-
-void meiLongwordRead(u32 ul_address, u32 *pul_data)
-{
- *pul_data = *((volatile u32 *)ul_address);
- asm("SYNC");
- return;
-} // end of "meiLongwordRead(..."
-
-MEI_ERROR meiDMAWrite(u32 destaddr, u32 *databuff, u32 databuffsize)
-{
- u32 *p = databuff;
- u32 temp;
- u32 flags;
-
- if( destaddr & 3)
- return MEI_FAILURE;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- save_flags(flags);
- cli();
-#endif
-
-
- // Set the write transfer address
- meiLongwordWrite(MEI_XFR_ADDR, destaddr);
-
- // Write the data pushed across DMA
- while (databuffsize--)
- {
- temp = *p;
- if(databuff==(u32 *)TxMessage) // swap half word
- temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16);
- meiLongwordWrite(MEI_DATA_XFR, temp);
- p++;
- } // end of "while(..."
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- restore_flags(flags);
-#endif
-
- return MEI_SUCCESS;
-
-} // end of "meiDMAWrite(..."
-
-MEI_ERROR meiDMAWrite_16(u32 destaddr, u32 *databuff, u32 databuffsize)
-{
- u32 *p = databuff;
- u32 temp;
- u32 flags;
-
- if( destaddr & 3)
- return MEI_FAILURE;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- save_flags(flags);
- cli();
-#endif
-
-
- // Set the write transfer address
- meiLongwordWrite(MEI_XFR_ADDR, destaddr);
-
- // Write the data pushed across DMA
- while (databuffsize--)
- {
- temp = *p;
- temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16);//swap half word
- meiLongwordWrite(MEI_DATA_XFR, temp);
- p++;
- } // end of "while(..."
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- restore_flags(flags);
-#endif
-
- return MEI_SUCCESS;
-
-} // end of "meiDMAWrite_16(..."
-
-MEI_ERROR meiDMAWrite_8(u32 destaddr, u32 *databuff, u32 databuffsize)
-{
- u32 *p = databuff;
- u32 temp;
- u32 flags;
-
- if( destaddr & 3)
- return MEI_FAILURE;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- save_flags(flags);
- cli();
-#endif
-
-
- // Set the write transfer address
- meiLongwordWrite(MEI_XFR_ADDR, destaddr);
-
- // Write the data pushed across DMA
- while (databuffsize--)
- {
- temp = *p;
- temp = ((temp & 0xff)<<24) + ((temp & 0xff00)<<8)+ ((temp & 0xff0000)>>8)+ ((temp & 0xff000000)>>24);//swap byte
- meiLongwordWrite(MEI_DATA_XFR, temp);
- p++;
- } // end of "while(..."
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- restore_flags(flags);
-#endif
-
- return MEI_SUCCESS;
-
-} // end of "meiDMAWrite_8(..."
-
-MEI_ERROR meiDMARead(u32 srcaddr, u32 *databuff, u32 databuffsize)
-{
- u32 *p = databuff;
- u32 temp;
- u32 flags;
-
- if( srcaddr & 3)
- return MEI_FAILURE;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- save_flags(flags);
- cli();
-#endif
-
-
- // Set the read transfer address
- meiLongwordWrite(MEI_XFR_ADDR, srcaddr);
-
- // Read the data popped across DMA
- while (databuffsize--)
- {
- meiLongwordRead(MEI_DATA_XFR, &temp);
- if(databuff==(u32 *)RxMessage) // swap half word
- temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16);
- *p=temp;
- p++;
- } // end of "while(..."
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- restore_flags(flags);
-#endif
-
- return MEI_SUCCESS;
-
-} // end of "meiDMARead(..."
-
-MEI_ERROR meiDMARead_16(u32 srcaddr, u32 *databuff, u32 databuffsize)
-{
- u32 *p = databuff;
- u32 temp;
- u32 flags;
-
- if( srcaddr & 3)
- return MEI_FAILURE;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- save_flags(flags);
- cli();
-#endif
-
-
- // Set the read transfer address
- meiLongwordWrite(MEI_XFR_ADDR, srcaddr);
-
- // Read the data popped across DMA
- while (databuffsize--)
- {
- meiLongwordRead(MEI_DATA_XFR, &temp);
- temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16);
- *p=temp;
- p++;
- } // end of "while(..."
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- restore_flags(flags);
-#endif
-
- return MEI_SUCCESS;
-
-} // end of "meiDMARead_16(..."
-
-MEI_ERROR meiDMARead_8(u32 srcaddr, u32 *databuff, u32 databuffsize)
-{
- u32 *p = databuff;
- u32 temp;
- u32 flags;
-
- if( srcaddr & 3)
- return MEI_FAILURE;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- save_flags(flags);
- cli();
-#endif
-
-
- // Set the read transfer address
- meiLongwordWrite(MEI_XFR_ADDR, srcaddr);
-
- // Read the data popped across DMA
- while (databuffsize--)
- {
- meiLongwordRead(MEI_DATA_XFR, &temp);
- temp = ((temp & 0xff)<<24) + ((temp & 0xff00)<<8)+ ((temp & 0xff0000)>>8)+ ((temp & 0xff000000)>>24);//swap byte
- *p=temp;
- p++;
- } // end of "while(..."
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- restore_flags(flags);
-#endif
-
- return MEI_SUCCESS;
-
-} // end of "meiDMARead_8(..."
-
-void meiPollForDbgDone(void)
-{
- u32 query = 0;
- int i=0;
- while (i<WHILE_DELAY)
- {
- meiLongwordRead(ARC_TO_MEI_INT, &query);
- query &= (ARC_TO_MEI_DBG_DONE);
- if(query)
- break;
- i++;
- if(i==WHILE_DELAY){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n PollforDbg fail");
-#endif
- }
- DEBUG_ACCESS_DELAY;
- }
- meiLongwordWrite(ARC_TO_MEI_INT, ARC_TO_MEI_DBG_DONE); // to clear this interrupt
-} // end of "meiPollForDbgDone(..."
-
-MEI_ERROR meiDebugWrite_8(u32 destaddr, u32 *databuff, u32 databuffsize)
-{
- u32 i;
- u32 temp = 0x0;
- u32 address = 0x0;
- u32 *buffer = 0x0;
- u32 flags;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- save_flags(flags);
- cli();
-#endif
-
-
- // Open the debug port before DMP memory write
- meiLongwordRead(MEI_CONTROL, &temp);
- DEBUG_ACCESS_DELAY;
- temp |= (HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, temp);
- DEBUG_ACCESS_DELAY;
- meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK);
- DEBUG_ACCESS_DELAY;
-
- // For the requested length, write the address and write the data
- address = destaddr;
- buffer = databuff;
- for (i=0; i < databuffsize; i++)
- {
- meiLongwordWrite(MEI_DEBUG_WAD, address);
- DEBUG_ACCESS_DELAY;
- temp=*buffer;
- temp = ((temp & 0xff)<<24) + ((temp & 0xff00)<<8)+ ((temp & 0xff0000)>>8)+ ((temp & 0xff000000)>>24);//swap byte
- meiLongwordWrite(MEI_DEBUG_DATA, temp);
- DEBUG_ACCESS_DELAY;
- meiPollForDbgDone();
- address += 4;
- buffer++;
- } // end of "for(..."
-
- // Close the debug port after DMP memory write
- meiLongwordRead(MEI_CONTROL, &temp);
- DEBUG_ACCESS_DELAY;
- temp &= ~(HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, temp);
- DEBUG_ACCESS_DELAY;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- restore_flags(flags);
-#endif
-
- // Return
- return MEI_SUCCESS;
-
-} // end of "meiDebugWrite_8(..."
-
-MEI_ERROR meiDebugRead_8(u32 srcaddr, u32 *databuff, u32 databuffsize)
-{
- u32 i;
- u32 temp = 0x0;
- u32 address = 0x0;
- u32 *buffer = 0x0;
- u32 flags;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- save_flags(flags);
- cli();
-#endif
-
-
- // Open the debug port before DMP memory read
- meiLongwordRead(MEI_CONTROL, &temp);
- DEBUG_ACCESS_DELAY;
- temp |= (HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, temp);
- DEBUG_ACCESS_DELAY;
- meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP2_MASK);
- DEBUG_ACCESS_DELAY;
-
- // For the requested length, write the address and read the data
- address = srcaddr;
- buffer = databuff;
- for (i=0; i<databuffsize; i++)
- {
- meiLongwordWrite(MEI_DEBUG_RAD, address);
- DEBUG_ACCESS_DELAY;
- meiPollForDbgDone();
- meiLongwordRead(MEI_DEBUG_DATA, &temp);
- DEBUG_ACCESS_DELAY;
- temp = ((temp & 0xff)<<24) + ((temp & 0xff00)<<8)+ ((temp & 0xff0000)>>8)+ ((temp & 0xff000000)>>24);//swap byte
- *buffer=temp;
- address += 4;
- buffer++;
- } // end of "for(..."
-
- // Close the debug port after DMP memory read
- meiLongwordRead(MEI_CONTROL, &temp);
- DEBUG_ACCESS_DELAY;
- temp &= ~(HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, temp);
- DEBUG_ACCESS_DELAY;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- restore_flags(flags);
-#endif
-
- // Return
- return MEI_SUCCESS;
-
-} // end of "meiDebugRead_8(..."
-
-MEI_ERROR meiDebugWrite_16(u32 destaddr, u32 *databuff, u32 databuffsize)
-{
- u32 i;
- u32 temp = 0x0;
- u32 address = 0x0;
- u32 *buffer = 0x0;
- u32 flags;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- save_flags(flags);
- cli();
-#endif
-
-
- // Open the debug port before DMP memory write
- meiLongwordRead(MEI_CONTROL, &temp);
- DEBUG_ACCESS_DELAY;
- temp |= (HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, temp);
- DEBUG_ACCESS_DELAY;
- meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK);
- DEBUG_ACCESS_DELAY;
-
- // For the requested length, write the address and write the data
- address = destaddr;
- buffer = databuff;
- for (i=0; i < databuffsize; i++)
- {
- meiLongwordWrite(MEI_DEBUG_WAD, address);
- DEBUG_ACCESS_DELAY;
- temp=*buffer;
- temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16);//swap half word
- meiLongwordWrite(MEI_DEBUG_DATA, temp);
- DEBUG_ACCESS_DELAY;
- meiPollForDbgDone();
- address += 4;
- buffer++;
- } // end of "for(..."
-
- // Close the debug port after DMP memory write
- meiLongwordRead(MEI_CONTROL, &temp);
- DEBUG_ACCESS_DELAY;
- temp &= ~(HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, temp);
- DEBUG_ACCESS_DELAY;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- restore_flags(flags);
-#endif
-
- // Return
- return MEI_SUCCESS;
-
-} // end of "meiDebugWrite_16(..."
-
-MEI_ERROR meiDebugRead_16(u32 srcaddr, u32 *databuff, u32 databuffsize)
-{
- u32 i;
- u32 temp = 0x0;
- u32 address = 0x0;
- u32 *buffer = 0x0;
- u32 flags;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- save_flags(flags);
- cli();
-#endif
-
-
- // Open the debug port before DMP memory read
- meiLongwordRead(MEI_CONTROL, &temp);
- DEBUG_ACCESS_DELAY;
- temp |= (HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, temp);
- DEBUG_ACCESS_DELAY;
- meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP2_MASK);
- DEBUG_ACCESS_DELAY;
-
- // For the requested length, write the address and read the data
- address = srcaddr;
- buffer = databuff;
- for (i=0; i<databuffsize; i++)
- {
- meiLongwordWrite(MEI_DEBUG_RAD, address);
- DEBUG_ACCESS_DELAY;
- meiPollForDbgDone();
- meiLongwordRead(MEI_DEBUG_DATA, &temp);
- DEBUG_ACCESS_DELAY;
- temp = ((temp & 0xffff)<<16) + ((temp & 0xffff0000)>>16);//swap half word
- *buffer=temp;
- address += 4;
- buffer++;
- } // end of "for(..."
-
- // Close the debug port after DMP memory read
- meiLongwordRead(MEI_CONTROL, &temp);
- DEBUG_ACCESS_DELAY;
- temp &= ~(HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, temp);
- DEBUG_ACCESS_DELAY;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- restore_flags(flags);
-#endif
-
- // Return
- return MEI_SUCCESS;
-
-} // end of "meiDebugRead_16(..."
-
-MEI_ERROR meiDebugWrite(u32 destaddr, u32 *databuff, u32 databuffsize)
-{
- u32 i;
- u32 temp = 0x0;
- u32 address = 0x0;
- u32 *buffer = 0x0;
- u32 flags;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- save_flags(flags);
- cli();
-#endif
-
-
- // Open the debug port before DMP memory write
- meiLongwordRead(MEI_CONTROL, &temp);
- DEBUG_ACCESS_DELAY;
- temp |= (HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, temp);
- DEBUG_ACCESS_DELAY;
- meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK);
- DEBUG_ACCESS_DELAY;
-
- // For the requested length, write the address and write the data
- address = destaddr;
- buffer = databuff;
- for (i=0; i < databuffsize; i++)
- {
- meiLongwordWrite(MEI_DEBUG_WAD, address);
- DEBUG_ACCESS_DELAY;
- temp=*buffer;
- meiLongwordWrite(MEI_DEBUG_DATA, temp);
- DEBUG_ACCESS_DELAY;
- meiPollForDbgDone();
- address += 4;
- buffer++;
- } // end of "for(..."
-
- // Close the debug port after DMP memory write
- meiLongwordRead(MEI_CONTROL, &temp);
- DEBUG_ACCESS_DELAY;
- temp &= ~(HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, temp);
- DEBUG_ACCESS_DELAY;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- restore_flags(flags);
-#endif
-
- // Return
- return MEI_SUCCESS;
-
-} // end of "meiDebugWrite(..."
-
-MEI_ERROR meiDebugRead(u32 srcaddr, u32 *databuff, u32 databuffsize)
-{
- u32 i;
- u32 temp = 0x0;
- u32 address = 0x0;
- u32 *buffer = 0x0;
- u32 flags;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- save_flags(flags);
- cli();
-#endif
-
-
- // Open the debug port before DMP memory read
- meiLongwordRead(MEI_CONTROL, &temp);
- DEBUG_ACCESS_DELAY;
- temp |= (HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, temp);
- DEBUG_ACCESS_DELAY;
- meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP2_MASK);
- DEBUG_ACCESS_DELAY;
-
- // For the requested length, write the address and read the data
- address = srcaddr;
- buffer = databuff;
- for (i=0; i<databuffsize; i++)
- {
- meiLongwordWrite(MEI_DEBUG_RAD, address);
- DEBUG_ACCESS_DELAY;
- meiPollForDbgDone();
- meiLongwordRead(MEI_DEBUG_DATA, &temp);
- DEBUG_ACCESS_DELAY;
- *buffer=temp;
- address += 4;
- buffer++;
- } // end of "for(..."
-
- // Close the debug port after DMP memory read
- meiLongwordRead(MEI_CONTROL, &temp);
- DEBUG_ACCESS_DELAY;
- temp &= ~(HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, temp);
- DEBUG_ACCESS_DELAY;
-
-#ifdef AMAZON_DMA_DEBUG_MUTEX
- restore_flags(flags);
-#endif
-
- // Return
- return MEI_SUCCESS;
-
-} // end of "meiDebugRead(..."
-EXPORT_SYMBOL(meiDebugRead);
-
-void meiMailboxInterruptsDisable(void)
-{
- meiLongwordWrite(ARC_TO_MEI_INT_MASK, 0x0);
-} // end of "meiMailboxInterruptsDisable(..."
-
-void meiMailboxInterruptsEnable(void)
-{
- meiLongwordWrite(ARC_TO_MEI_INT_MASK, MSGAV_EN);
-} // end of "meiMailboxInterruptsEnable(..."
-
-MEI_ERROR meiMailboxWrite(u16 *msgsrcbuffer, u16 msgsize)
-{
- int i;
- u32 arc_mailbox_status = 0x0;
- u32 temp=0;
- MEI_ERROR meiMailboxError = MEI_SUCCESS;
-
- // Check arc if mailbox write can be initiated
-/* meiLongwordRead(MEI_TO_ARC_INT, &arc_mailbox_status);
- if ((arc_mailbox_status & MEI_TO_ARC_MSGAV))
- {
- return MEI_MAILBOX_FULL;
- }
-*/
- // Write to mailbox
- meiMailboxError = meiDMAWrite(MEI_TO_ARC_MAILBOX, (u32*)msgsrcbuffer, msgsize/2);
- meiMailboxError = meiDMAWrite(MEI_TO_ARC_MAILBOXR, (u32 *)(&temp), 1);
-
- // Notify arc that mailbox write completed
- cmv_waiting=1;
- meiLongwordWrite(MEI_TO_ARC_INT, MEI_TO_ARC_MSGAV);
-
- i=0;
- while(i<WHILE_DELAY){ // wait for ARC to clear the bit
- meiLongwordRead(MEI_TO_ARC_INT, &arc_mailbox_status);
- if((arc_mailbox_status & MEI_TO_ARC_MSGAV) != MEI_TO_ARC_MSGAV)
- break;
- i++;
- if(i==WHILE_DELAY){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n MEI_TO_ARC_MSGAV not cleared by ARC");
-#endif
- meiMailboxError = MEI_FAILURE;
-#if 0
- for(i=0;i<msgsize;i++)
- printk("\n %8x", (*(msgsrcbuffer+i)));
-#endif
- }
- }
-
- // Return
- return meiMailboxError;
-
-} // end of "meiMailboxWrite(..."
-
-MEI_ERROR meiMailboxRead(u16 *msgdestbuffer, u16 msgsize)
-{
- //u32 arc_mailbox_status = 0x0;
- //u32 *mei_arc_msgbuff = 0x0;
- MEI_ERROR meiMailboxError = MEI_SUCCESS;
-
- /*
- // Check arc if mailbox read can be initiated
- meiLongwordRead(ARC_TO_MEI_INT, &arc_mailbox_status);
- if ((arc_mailbox_status & ARC_TO_MEI_MSGAV) == 0)
- {
- return MEI_MAILBOX_EMPTY;
- } // end of "if(..."
- */
-
- // Read from mailbox
- meiMailboxError = meiDMARead(ARC_TO_MEI_MAILBOX, (u32*)msgdestbuffer, msgsize/2);
-
- // Notify arc that mailbox read completed
- meiLongwordWrite(ARC_TO_MEI_INT, ARC_TO_MEI_MSGAV);
-
- // Return
- return meiMailboxError;
-
-} // end of "meiMailboxRead(..."
-
-MEI_ERROR meiHaltArc(void)
-{
- u32 arc_control_mode = 0x0;
- u32 arc_debug_addr = 0x5;
- u32 arc_debug_data = 0x0;
-
- // Switch arc control from JTAG mode to MEI mode- write '1' to bit0
- meiLongwordRead(MEI_CONTROL, &arc_control_mode);
- arc_control_mode |= (HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, arc_control_mode);
-
- // Write arc aux reg access mask (0x0) into debug addr decode reg
- meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_AUX_MASK);
-
- // Write arc debug reg addr (0x5) into debug read addr reg
- meiLongwordWrite(MEI_DEBUG_RAD, arc_debug_addr);
- meiPollForDbgDone();
-
- // Read debug data reg and save content
- meiLongwordRead(MEI_DEBUG_DATA, &arc_debug_data);
-
- // Write arc debug reg addr (0x5) into debug write addr reg
- meiLongwordWrite(MEI_DEBUG_WAD, arc_debug_addr);
-
- // Write debug data reg with content ORd with 0x2 (halt bit set)
- arc_debug_data |= (BIT1);
- meiLongwordWrite(MEI_DEBUG_DATA, arc_debug_data);
- meiPollForDbgDone();
-
- // Switch arc control from MEI mode to JTAG mode- write '0' to bit0
- meiLongwordRead(MEI_CONTROL, &arc_control_mode);
- arc_control_mode &= ~(HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, arc_control_mode);
-
- // Return
- return MEI_SUCCESS;
-
-} // end of "meiHalt(..."
-
-MEI_ERROR meiDownloadBootCode(void)
-{
- u32 arc_control_mode;
- u32 boot_loop;
- u32 page_size;
- u32 dest_addr;
-
- u32 arc_debug_addr = 0x31F00;
- u32 arc_debug_data = 0x10;
- u32 temp;
-// int i;
-
- //MEI_ERROR meiDMAError = MEI_SUCCESS;
-
- // Disable mask for arc codeswap interrupts
- meiMailboxInterruptsDisable();
-
- // Switch arc control from JTAG mode to MEI mode- write '1' to bit0
- meiLongwordRead(MEI_CONTROL, &arc_control_mode);
- arc_control_mode |= (HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, arc_control_mode);
-
- // Write (0x10) to CRI_CCR0(0x31F00) to enable ac_clk signal
- meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK);
- meiLongwordWrite(MEI_DEBUG_RAD, arc_debug_addr);
- meiPollForDbgDone();
- meiLongwordRead(MEI_DEBUG_DATA, &temp);
- temp |=arc_debug_data;
-
- meiLongwordWrite(MEI_DEBUG_WAD, arc_debug_addr);
- meiLongwordWrite(MEI_DEBUG_DATA, temp);
- meiPollForDbgDone();
- //meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_AUX_MASK);
-
- // Switch arc control from MEI mode to JTAG mode- write '0' to bit0
- meiLongwordRead(MEI_CONTROL, &arc_control_mode);
- arc_control_mode &= ~(HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, arc_control_mode);
-
-#ifdef AMAZON_MEI_DEBUG_ON //to test ac_clk setting correctness
- meiLongwordRead(MEI_CONTROL, &arc_control_mode);
- arc_control_mode |= (HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, arc_control_mode);
-
- meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK);
- meiLongwordWrite(MEI_DEBUG_RAD, arc_debug_addr);
- meiPollForDbgDone();
- meiLongwordRead(MEI_DEBUG_DATA, &arc_debug_data);
-
- meiLongwordRead(MEI_CONTROL, &arc_control_mode);
- arc_control_mode &= ~(HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, arc_control_mode);
-
-// printk("\n\n ac_clk is %8x\n", arc_debug_data);
-#endif
-
- /*
- ** DMA the boot code page(s)
- */
-#ifdef AMAZON_MEI_DEBUG_ON
-// printk("\n\n start download pages");
-#endif
- for( boot_loop = 0; boot_loop < img_hdr->count; boot_loop++)
- {
- if( img_hdr->page[boot_loop].p_size & BOOT_FLAG)
- {
- page_size = meiGetPage( boot_loop, GET_PROG, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr);
- if( page_size > 0)
- {
- meiDMAWrite(dest_addr, mei_arc_swap_buff, page_size);
- }
- }
- if( img_hdr->page[boot_loop].d_size & BOOT_FLAG)
- {
- page_size = meiGetPage( boot_loop, GET_DATA, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr);
- if( page_size > 0)
- {
- meiDMAWrite( dest_addr, mei_arc_swap_buff, page_size);
- }
- }
- }
-#ifdef AMAZON_MEI_DEBUG_ON
-// printk("\n\n pages downloaded");
-#endif
- return MEI_SUCCESS;
-
-} // end of "meiDownloadBootCode(..."
-
-MEI_ERROR meiRunArc(void)
-{
- u32 arc_control_mode = 0x0;
- u32 arc_debug_addr = 0x0;
- u32 arc_debug_data = 0x0;
-
- // Switch arc control from JTAG mode to MEI mode- write '1' to bit0
- meiLongwordRead(MEI_CONTROL, &arc_control_mode);
- arc_control_mode |= (HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, arc_control_mode);
-
- // Write arc aux reg access mask (0x0) into debug addr decode reg
- meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_AUX_MASK);
-
- // Write arc status aux reg addr (0x0) into debug read addr reg
- meiLongwordWrite(MEI_DEBUG_RAD, arc_debug_addr);
- meiPollForDbgDone();
-
- // Read debug data reg and save content
- meiLongwordRead(MEI_DEBUG_DATA, &arc_debug_data);
-
- // Write arc status aux reg addr (0x0) into debug write addr reg
- meiLongwordWrite(MEI_DEBUG_WAD, arc_debug_addr);
-
- // Write debug data reg with content ANDd with 0xFDFFFFFF (halt bit cleared)
- arc_debug_data &= ~(BIT25);
- meiLongwordWrite(MEI_DEBUG_DATA, arc_debug_data);
- meiPollForDbgDone();
-
- // Switch arc control from MEI mode to JTAG mode- write '0' to bit0
- meiLongwordRead(MEI_CONTROL, &arc_control_mode);
- arc_control_mode &= ~(HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, arc_control_mode);
-
- // Enable mask for arc codeswap interrupts
- meiMailboxInterruptsEnable();
-
- // Return
- return MEI_SUCCESS;
-
-} // end of "meiActivate(..."
-
-int meiGetPage( u32 Page, u32 data, u32 MaxSize, u32 *Buffer, u32 *Dest)
-{
- u32 size;
- u32 i;
- u32 *p;
-
- if( Page > img_hdr->count)
- return -2;
-
- /*
- ** Get program or data size, depending on "data" flag
- */
- size = (data == GET_DATA) ? img_hdr->page[ Page].d_size : img_hdr->page[ Page].p_size;
-
- size &= BOOT_FLAG_MASK; // Clear boot bit!
- if( size > MaxSize)
- return -1;
-
- if( size == 0)
- return 0;
- /*
- ** Get program or data offset, depending on "data" flag
- */
- i = data ? img_hdr->page[ Page].d_offset : img_hdr->page[ Page].p_offset;
-
- /*
- ** Copy data/program to buffer
- */
-
- i /= 4; // Adjust offset for byte-to-UINT for array operation
-
- p = (u32 *)img_hdr + i;
- for(i = 0; i < size; i++)
- Buffer[i] = *p++;
- /*
- ** Pass back data/program destination address
- */
- *Dest = data ? img_hdr->page[Page].d_dest : img_hdr->page[Page].p_dest;
-
- return size;
-}
-
-MEI_ERROR meiCMV(u16 * request, int reply) // write cmv to arc, if reply needed, wait for reply
-{
- MEI_ERROR meierror;
- wait_queue_t wait;
-
- cmv_reply=reply;
-
- meierror = meiMailboxWrite(request, MSG_LENGTH);
-
- if(meierror != MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n MailboxWrite Fail.");
-#endif
- return meierror;
- }
- else{
- cmv_count++;
- }
-
- if(cmv_reply == NO_REPLY)
- return MEI_SUCCESS;
-
- init_waitqueue_entry(&wait, current);
- add_wait_queue(&wait_queue_arcmsgav, &wait);
- set_current_state(TASK_INTERRUPTIBLE);
-// cmv_waiting=1;
-
- if(arcmsgav==1){
- set_current_state(TASK_RUNNING);
- remove_wait_queue(&wait_queue_arcmsgav, &wait);
- }
- else{
- schedule_timeout(CMV_TIMEOUT);
- remove_wait_queue(&wait_queue_arcmsgav, &wait);
- }
- if(arcmsgav==0){//CMV_timeout
- cmv_waiting=0;
- arcmsgav=0;
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\nmeiCMV: MEI_MAILBOX_TIMEOUT\n");
-#endif
- return MEI_MAILBOX_TIMEOUT;
- }
- else{
- arcmsgav=0;
- reply_count++;
- return MEI_SUCCESS;
- }
-}
-
-//TODO, for loopback test
-#ifdef DFE_LOOPBACK
-#define mte_reg_base (0x4800*4+0x20000)
-
-/* Iridia Registers Address Constants */
-#define MTE_Reg(r) (int)(mte_reg_base + (r*4))
-
-#define IT_AMODE MTE_Reg(0x0004)
-
-
-#define OMBOX_BASE 0x15F80
-#define IMBOX_BASE 0x15FC0
-
-#define TIMER_DELAY (1024)
-#define BC0_BYTES (32)
-#define BC1_BYTES (30)
-#define NUM_MB (12)
-#define TIMEOUT_VALUE 2000
-
-void BFMWait (u32 cycle) {
- u32 i;
- for (i = 0 ; i< cycle ; i++);
-}
-
-void WriteRegLong(u32 addr, u32 data){
- //printk("[%8x] <= %8x \n\n", addr, data);
- *((volatile u32 *)(addr)) = data;
-}
-
-u32 ReadRegLong (u32 addr) {
- u32 rd_val;
-
- rd_val = *((volatile u32 *)(addr));
- //printk("[%8x] => %8x \n\n", addr, rd_val);
- return rd_val;
-
-}
-
-/* This routine writes the mailbox with the data in an input array */
-void WriteMbox(u32 *mboxarray,u32 size) {
- u32 i;
-
- WriteRegLong(MEI_XFR_ADDR,IMBOX_BASE);
- for (i=0;i<size;i++) {
- WriteRegLong(MEI_DATA_XFR,*(mboxarray+i));
- }
-}
-
-/* This routine reads the output mailbox and places the results into an array */
-void ReadMbox(u32 *mboxarray,u32 size) {
- u32 i;
-
- WriteRegLong(MEI_XFR_ADDR,OMBOX_BASE);
- for (i=0;i<size;i++) {
- mboxarray[i] = ReadRegLong(MEI_DATA_XFR);
- }
-}
-
-void MEIWriteARCValue(u32 address, u32 value)
-{
- u32 i,check = 0;
- /* Write address register */
- *((volatile u32 *)MEI_DEBUG_WAD) = address;
-
- /* Write data register */
- *((volatile u32 *)MEI_DEBUG_DATA) = value;
-
- /* wait until complete - timeout at 40*/
- for (i=0;i<40;i++) {
- check = *((volatile u32 *)ARC_TO_MEI_INT);
- if ((check & 0x20)) break;
- //printk("MEIWriteARCValue: check:%8x\n\n", check);
- }
-
- /* clear the flag */
- *((volatile u32 *)ARC_TO_MEI_INT) = 0x20;
-
-}
-
-
-void post_mei_init(void)
-{
-u32 mailbox[NUM_MB];
-
- mailbox[0] = TIMER_DELAY;
-
- /* set bytes per bearer channel */
- mailbox[1] = BC0_BYTES;
- mailbox[2] = BC1_BYTES;
- WriteMbox(mailbox, 3);
-
- WriteRegLong(AAI_ACCESS, 0x00000001);
-
- /* enable ADSL block clock, ac_clk */
- WriteRegLong(MEI_CONTROL, 0x01);
- WriteRegLong(MEI_DEBUG_DEC, 0x00000001); // select ld/st space
- MEIWriteARCValue(0x31F00, 0x00000010); // write CRI_CCR0 to enable ac_clk
-
- /* set the MTE to register start */
- MEIWriteARCValue(IT_AMODE, 0xF);
- BFMWait(10);
-}
-
-
-int wait_sync(void)
-{
-u32 mailbox[NUM_MB];
- /* wait for ATM sync to be achieved on both BC0 and BC1 */
- u32 timeout=0;
- ReadMbox(mailbox, 1);
- u32 readval = mailbox[0];
- while( ((readval & 0xFFFFFFFF) == 0) && (timeout < TIMEOUT_VALUE) ) {
- BFMWait(1);
- //printk("wait_sync\n\n");
- ReadMbox(mailbox, 1);
- readval = mailbox[0];
- timeout++;
- }
- if(timeout == TIMEOUT_VALUE)return 0;
- else return 1;
-}
-#endif //DFE_LOOPBACK
-//end of TODO, for loopback test
-
-MEI_ERROR meiForceRebootAdslModem(void)
-{
-#if 0
-//#ifdef ARC_READY_ACK
- if(down_interruptible(&mei_sema)) //disable CMV access until ARC ready
- {
- return -ERESTARTSYS;
- }
-#endif
- if(reboot_firsttime==1){//000002:fchang Start
- // reset ARC
- *((volatile u32 *)0xB0100910) = 0x80; //reset DFE
- asm("SYNC");
- *((volatile u32 *)0xB0100910) = 0x0;
- asm("SYNC");
- if((*((volatile u32 *)0xB0100910))!=0x0)
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n reset DFE fail");
-#endif
-
- // reset ARC
- meiLongwordWrite(MEI_CONTROL, SOFT_RESET);
- asm("SYNC");
- meiLongwordWrite(MEI_CONTROL, 0);
- asm("SYNC");
-
- } //000002:fchang End
-#ifdef DFE_LOOPBACK
- img_hdr=(ARC_IMG_HDR *)lp_image;
-#else
- img_hdr=(ARC_IMG_HDR *)image_buffer;
-#endif
-// printk("\n\n enter haltarc");
- meiHaltArc();
-// printk("\n\n haltarc done");
-//000002:fchang Start
- if(reboot_firsttime==0){
- printk("\n\n new reboot");
- meiResetArc();
- meiResetCore();
- }
- if(reboot_firsttime==1)
- meiDownloadBootCode();
- else
- mei_ioctl((struct inode *)NULL, (struct file *)NULL, AMAZON_MEI_DOWNLOAD, (unsigned long)NULL);
-
-//000002:fchang End
-#ifdef AMAZON_MEI_DEBUG_ON
-// printk("\n\n Download Done");
-#endif
-
-#ifdef DFE_LOOPBACK
- post_mei_init();
-#endif
-
-// sema_init(&mei_sema, 1);
- //up(&mei_sema);
-
-// enable_irq(AMAZON_MEI_INT);
-
- meiRunArc();
-//000002:fchang Start
- if(reboot_firsttime==0){
- meiEnalbeMailboxInt();
- }
-//000002:fchang End
-
-#ifdef AMAZON_MEI_DEBUG_ON
-// printk("\n\n ARC Running");
-#endif
-
-#ifdef AMAZON_MEI_DEBUG_ON //to test ac_clk setting correctness
- {
- u32 arc_control_mode;
- u32 arc_debug_addr = 0x31F00;
- u32 arc_debug_data = 0x10;
- meiLongwordRead(MEI_CONTROL, &arc_control_mode);
- arc_control_mode |= (HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, arc_control_mode);
-
- meiLongwordWrite(MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK);
- meiLongwordWrite(MEI_DEBUG_RAD, arc_debug_addr);
- meiPollForDbgDone();
- meiLongwordRead(MEI_DEBUG_DATA, &arc_debug_data);
-
- meiLongwordRead(MEI_CONTROL, &arc_control_mode);
- arc_control_mode &= ~(HOST_MSTR);
- meiLongwordWrite(MEI_CONTROL, arc_control_mode);
-
-// printk("\n\n ac_clk is %8x\n", arc_debug_data);
- }
-#endif
-
-
-#ifdef DFE_LOOPBACK
- if (wait_sync() == 0){
- printk("ARC fails to run: time out\n\n");
- }else{
-// printk("ARC is ready\n\n");
- }
-#endif
- if(reboot_firsttime==1) //000002:fchang
- reboot_firsttime=0; //000002:fchang
-
- return MEI_SUCCESS;
-}
-
-//////////////////// procfs debug ////////////////////////////////////////////////////////
-#define MEI_DIRNAME "mei"
-static struct proc_dir_entry *meidir;
-
-static ssize_t proc_write(struct file *, const char *, size_t, loff_t *);
-static ssize_t proc_read(struct file *, char *, size_t, loff_t *);
-
-static struct file_operations proc_operations = {
- read: proc_read,
- write: proc_write,
-};
-
-typedef struct reg_entry {
- int * flag;
- char name[30]; // big enough to hold names
- char description[100]; // big enough to hold description
- unsigned short low_ino;
-} reg_entry_t;
-
-static reg_entry_t regs[PROC_ITEMS]; // total items to be monitored by /proc/mei
-
-#define NUM_OF_REG_ENTRY (sizeof(regs)/sizeof(reg_entry_t))
-
-static int proc_read(struct file * file, char * buf, size_t nbytes, loff_t *ppos)
-{
- int i_ino = (file->f_dentry->d_inode)->i_ino;
- char outputbuf[64];
- int count=0;
- int i;
- u32 version=0;
- reg_entry_t* current_reg=NULL;
-
- for (i=0;i<NUM_OF_REG_ENTRY;i++) {
- if (regs[i].low_ino==i_ino) {
- current_reg = ®s[i];
- break;
- }
- }
- if (current_reg==NULL)
- return -EINVAL;
-
- if (current_reg->flag == (int *) 8){
- ///proc/mei/version
- //format:
- //Firmware version: major.minor.sub_version.int_version.rel_state.spl_appl
- //Firmware Date Time Code: date/month min:hour
- if (*ppos>0) /* Assume reading completed in previous read*/
- return 0; // indicates end of file
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- //if (indicator_count != 1){
- if (indicator_count < 1){
- up(&mei_sema);
- return -EAGAIN;
- }
- //major:bits 0-7
- //minor:bits 8-15
- makeCMV(H2D_CMV_READ, INFO, 54, 0, 1, NULL);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#if 0
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n WINHOST CMV fail");
-#endif
-#endif
- up(&mei_sema);
- return -EIO;
- }
- version = RxMessage[4];
- count = sprintf(outputbuf, "%d.%d.",(version)&0xff,(version>>8)&0xff);
-
- //sub_version:bits 4-7
- //int_version:bits 0-3
- //spl_appl:bits 8-13
- //rel_state:bits 14-15
- makeCMV(H2D_CMV_READ, INFO, 54, 1, 1, NULL);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#if 0
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n WINHOST CMV fail");
-#endif
-#endif
- up(&mei_sema);
- return -EFAULT;
- }
- version =RxMessage[4];
- count += sprintf(outputbuf+count, "%d.%d.%d.%d",
- (version>>4)&0xf,
- version&0xf,
- (version>>14)&0x3,
- (version>>8)&0x3f);
-#ifdef ADSL_LED_SUPPORT
-// version check -start for adsl led
- if ((((version>>4)&0xf)==2)&&((version&0xf)>=3)&&((version&0xf)<7)) firmware_support_led=1;
- else if ((((version>>4)&0xf)==2)&&((version&0xf)>=7)) firmware_support_led=2;
- else if (((version>>4)&0xf)>2) firmware_support_led=2;
-
-//165001:henryhsu:20050906:Modify for adsl firmware version 1.2.1.2.0.1 DATA_LED can't flash.
- //else firmware_support_led=0;
- else firmware_support_led=2;
-//165001
-
-
-// version check -end
-#endif
- //Date:bits 0-7
- //Month:bits 8-15
- makeCMV(H2D_CMV_READ, INFO, 55, 0, 1, NULL);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#if 0
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n WINHOST CMV fail");
-#endif
-#endif
- up(&mei_sema);
- return -EIO;
- }
- version = RxMessage[4];
-
- //Hour:bits 0-7
- //Minute:bits 8-15
- makeCMV(H2D_CMV_READ, INFO, 55, 1, 1, NULL);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#if 0
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n WINHOST CMV fail");
-#endif
-#endif
- up(&mei_sema);
- return -EFAULT;
- }
- version += (RxMessage[4]<<16);
- count += sprintf(outputbuf+count, " %d/%d %d:%d\n"
- ,version&0xff
- ,(version>>8)&0xff
- ,(version>>25)&0xff
- ,(version>>16)&0xff);
-
- up(&mei_sema);
-
- *ppos+=count;
- }else if(current_reg->flag != (int *)Recent_indicator){
- if (*ppos>0) /* Assume reading completed in previous read*/
- return 0; // indicates end of file
- count = sprintf(outputbuf, "0x%08X\n\n", *(current_reg->flag));
- *ppos+=count;
- if (count>nbytes) /* Assume output can be read at one time */
- return -EINVAL;
- }else{
- if((int)(*ppos)/((int)7)==16)
- return 0; // indicate end of the message
- count = sprintf(outputbuf, "0x%04X\n\n", *(((u16 *)(current_reg->flag))+ (int)(*ppos)/((int)7)));
- *ppos+=count;
- }
- if (copy_to_user(buf, outputbuf, count))
- return -EFAULT;
- return count;
-}
-
-static ssize_t proc_write(struct file * file, const char * buffer, size_t count, loff_t *ppos)
-{
- int i_ino = (file->f_dentry->d_inode)->i_ino;
- reg_entry_t* current_reg=NULL;
- int i;
- unsigned long newRegValue;
- char *endp;
-
- for (i=0;i<NUM_OF_REG_ENTRY;i++) {
- if (regs[i].low_ino==i_ino) {
- current_reg = ®s[i];
- break;
- }
- }
- if ((current_reg==NULL) || (current_reg->flag == (int *)Recent_indicator))
- return -EINVAL;
-
- newRegValue = simple_strtoul(buffer,&endp,0);
- *(current_reg->flag)=(int)newRegValue;
- return (count+endp-buffer);
-}
-////////////////makeCMV(Opcode, Group, Address, Index, Size, Data), CMV in u16 TxMessage[MSG_LENGTH]///////////////////////////
-void makeCMV(u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data)
-{
- memset(TxMessage, 0, MSG_LENGTH*2);
- TxMessage[0]= (opcode<<4) + (size&0xf);
- TxMessage[1]= (((index==0)?0:1)<<7) + (group&0x7f);
- TxMessage[2]= address;
- TxMessage[3]= index;
- if(opcode == H2D_CMV_WRITE)
- memcpy(TxMessage+4, data, size*2);
- return;
-}
-
-////////////////makeCMV(Opcode, Group, Address, Index, Size, Data), CMV in u16 TxMessage[MSG_LENGTH]///////////////////////////
-void makeCMV_local(u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data,u16 *CMVMSG)
-{
- memset(CMVMSG, 0, MSG_LENGTH*2);
- CMVMSG[0]= (opcode<<4) + (size&0xf);
- CMVMSG[1]= (((index==0)?0:1)<<7) + (group&0x7f);
- CMVMSG[2]= address;
- CMVMSG[3]= index;
- if(opcode == H2D_CMV_WRITE)
- memcpy(CMVMSG+4, data, size*2);
- return;
-}
-
-//////////////// Driver Structure /////////////////////////////////////////////////////////////////////////////
-static ssize_t mei_write(struct file *, const char *, size_t, loff_t *);
-static int mei_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
-
-static struct file_operations mei_operations = {
- write: mei_write,
- ioctl: mei_ioctl,
-};
-
-
-static ssize_t mei_write(struct file * filp, const char * buf, size_t size, loff_t * loff)
-{
-// printk("\n\n mei_write entered");
-// image_buffer = (u32 *)kmalloc(size, GFP_KERNEL);
- image_buffer = (u32 *)vmalloc(size);
-// printk("\n\n image_buffer kmalloc done");
- if(image_buffer == NULL){
-#ifdef AMAZON_MEI_DEBUG_ON
-// printk("\n\n kmalloc for firmware image fail");
- printk("\n\n vmalloc for firmware image fail");
-#endif
- return -1;
- }
- copy_from_user((char *)image_buffer, buf, size);
-// printk("\n\n copy_from_user done");
- return size;
-}
-
- ////////// ISR GPTU Timer 6 for high resolution timer /////////////
-void amazon_timer6_interrupt_MEI(int irq, void *dev_id, struct pt_regs *regs)
-{
- int i,j;
- u32 temp;
- u16 temp16;
- u16 rdindex, wrindex;
- u16 num_rd=0; //num of byte can be read
- u16 bytes_to_wr=0;
-
-// printk("\n\nenter timer\n\n");
- irqtimes++;
-// printk("\n%d\n",irqtimes);
-
-
-/*
-#ifdef PCM_ACCESS_DEBUG
- meiDebugRead_8(0x30f20, &temp, 1);
-#else
- meiDMARead_8(0x30f20, &temp, 1);
-#endif
- if((temp&0x4000)!=0){
- printk("\nER_ERR");
-#ifdef PCM_ACCESS_DEBUG
- meiDebugWrite_8(0x30f20, &temp, 1);
-#else
- meiDMAWrite_8(0x30f20, &temp, 1);
-#endif
-#ifdef PCM_ACCESS_DEBUG
- meiDebugRead_8(0x30f20, &temp, 1);
-#else
- meiDMARead_8(0x30f20, &temp, 1);
-#endif
- if((temp&0x4000)!=0)
- printk("\nER_ERR not cleared");
- }
-*/
-
- for(i=PCM_CHANNEL_NUM-1;i>=0;i--){// start from last channel, which is rx
-#ifdef PCM_ACCESS_DEBUG
- meiDebugRead_16(pcm_start_addr+i*16+12, &temp, 1);
-#else
- meiDMARead_16(pcm_start_addr+i*16+12, &temp, 1);
-#endif
- wrindex = (u16)((temp & 0xffff0000)>>16);
-// printk(" %d",wrindex);
-#ifdef PCM_ACCESS_DEBUG
- meiDebugRead_16(pcm_start_addr+i*16+8, &temp, 1);
-#else
- meiDMARead_16(pcm_start_addr+i*16+8, &temp, 1);
-#endif
- rdindex = (u16)(temp & 0xffff);
-// printk(" %d",rdindex);
- if(rdindex<=wrindex)
- num_rd=((wrindex-rdindex)/4)*4; //read multiply of 4 bytes
- else
- num_rd=((pcm_data[i].len-(rdindex-wrindex))/4)*4; //read multiply of 4 bytes
-
- if(i%2!=0){//rx channel
- pcm_data[i].point=0;
- for(j=0;j<num_rd/4;j++){
- if(pcm_data[i].finish!=1){
- if((rdindex+j*4)>=pcm_data[i].len)
- temp16=(rdindex+j*4) - pcm_data[i].len;
- else
- temp16=rdindex+j*4;
-#ifdef PCM_ACCESS_DEBUG
- meiDebugRead_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16, (u32*)(pcm_data[i].buff+pcm_data[i].point), 1);
-#else
- meiDMARead_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16, (u32*)(pcm_data[i].buff+pcm_data[i].point), 1);
-#endif
- // printk(" %8x", *((u32*)(pcm_data[i].buff+pcm_data[i].point)));
- /* if(pcm_data[i].point==0){
- if(pcm_data[i].buff[0]==0xA5){// start of loopback data
- pcm_data[i].point+=4;
- printk("\nstart receive data");
- }
- }
- else*/
- pcm_data[i].point+=4;
- /* if(pcm_data[i].point==PCM_BUFF_SIZE){ //finish rx
- pcm_data[i].finish=1;
- printk("\nchannel[%d] finished", i);
- } */
- }
- }
- if(firsttime[i]==1){
- for(j=0;j<num_rd;j++){
- if(pcm_data[i].buff[j]==0x1){
- num_cmp[i]=num_rd-j;
- firsttime[i]=0;
- break;
- }
- }
- if(memcmp(sampledata+1, pcm_data[i].buff+j, num_cmp[i])!=0)
- printk("\n\ndata wrong,1st\n\n");
- else
- pcm_start_loc[i] = num_cmp[i]+1;
- }
- else{
- if(memcmp(sampledata+pcm_start_loc[i], pcm_data[i].buff, num_rd)!=0)
- printk("\n\ndata wrong\n\n");
- else{
- pcm_start_loc[i]+=num_rd;
- if(pcm_start_loc[i]>=256)
- pcm_start_loc[i]=pcm_start_loc[i]-256;
- }
- }
-
- rdindex +=num_rd;
- if(rdindex>=pcm_data[i].len)
- rdindex=rdindex-pcm_data[i].len;
-#ifdef PCM_ACCESS_DEBUG
- meiDebugRead_16(pcm_start_addr+i*16+8, &temp, 1);
-#else
- meiDMARead_16(pcm_start_addr+i*16+8, &temp, 1);
-#endif
- temp= (temp & 0xffff0000) + rdindex;
-#ifdef PCM_ACCESS_DEBUG
- meiDebugWrite_16(pcm_start_addr+i*16+8, &temp, 1); // update rdindex
-#else
- meiDMAWrite_16(pcm_start_addr+i*16+8, &temp, 1); // update rdindex
-#endif
-
- bytes_to_wr = num_rd;
-
- // if(bytes_to_wr>0){
- // printk(" %d", num_rd);
- // printk(" %d", rdindex);
-// printk("\n\nrdindex = %d", rdindex);
- //}
- }
- else{ //tx channel
- // if((bytes_to_wr + num_rd) < pcm_data[i].len){
- for(j=0;j<bytes_to_wr/4;j++){
- if(pcm_data[i].finish!=1){
- if((wrindex+j*4)>=pcm_data[i].len)
- temp16=(wrindex+j*4) - pcm_data[i].len;
- else
- temp16=wrindex + j*4;
-/*
-#ifdef PCM_ACCESS_DEBUG
- meiDebugWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i+1].buff+j*4), 1);
-#else
- meiDMAWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i+1].buff+j*4), 1);
-#endif*/
-
-#ifdef PCM_ACCESS_DEBUG
- meiDebugWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i].buff+pcm_data[i].point), 1);
- // meiDebugWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i].buff), 1);
-#else
- meiDMAWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16))+temp16,(u32*)(pcm_data[i].buff+pcm_data[i].point), 1);
-#endif
- pcm_data[i].point+=4;
- if(pcm_data[i].point==PCM_BUFF_SIZE){
- // pcm_data[i].finish=1;
- // printk("\nchannel[%d] finished", i);
- pcm_data[i].point=0;
- }
- }
- }
- wrindex+=bytes_to_wr;
- if(wrindex>=pcm_data[i].len)
- wrindex=wrindex-pcm_data[i].len;
-#ifdef PCM_ACCESS_DEBUG
- meiDebugRead_16(pcm_start_addr+i*16+12, &temp, 1);
-#else
- meiDMARead_16(pcm_start_addr+i*16+12, &temp, 1);
-#endif
- temp=(temp&0xffff) + (wrindex<<16);
-#ifdef PCM_ACCESS_DEBUG
- meiDebugWrite_16(pcm_start_addr+i*16+12, &temp, 1); // update wrindex
-#else
- meiDMAWrite_16(pcm_start_addr+i*16+12, &temp, 1); // update wrindex
-#endif
-
- //if(bytes_to_wr>0){
- // printk(" %d", bytes_to_wr);
- // printk(" %d", wrindex);
-// printk("\n\nwrindex = %d", wrindex);
- //}
- // }
- }
- }
- return;
-}
-//000002:fchang Start
-static int meiResetArc(void)
-{
- u32 auxreg0;
- u32 auxreg5;
- int flshcnt=0;
- int flshcnt1=0;
- int flshcnt2=0;
-
- meiLongwordWrite(MEI_CONTROL, 1);
- meiLongwordWrite(MEI_DEBUG_DEC, 3);
- meiLongwordWrite(MEI_DEBUG_WAD, 0x3c);
- meiLongwordWrite(MEI_DEBUG_DATA, 0x10);
- meiPollForDbgDone();
- meiLongwordWrite(MEI_DEBUG_DEC, 0x0);
- meiLongwordWrite(MEI_DEBUG_WAD, 0x2);
- meiLongwordWrite(MEI_DEBUG_DATA, 0x0);
- meiPollForDbgDone();
- meiLongwordWrite(MEI_DEBUG_WAD, 0x3);
- meiLongwordWrite(MEI_DEBUG_DATA, 0x0);
- meiPollForDbgDone();
- meiLongwordWrite(MEI_DEBUG_DEC, 0x0);
- meiLongwordWrite(MEI_DEBUG_RAD, 0x0);
- meiPollForDbgDone();
- meiLongwordRead(MEI_DEBUG_DATA, &auxreg0);
- auxreg0 = auxreg0 & 0x03ffffff;
- meiLongwordWrite(MEI_DEBUG_WAD, 0x0);
- meiLongwordWrite(MEI_DEBUG_DATA, auxreg0);
- meiPollForDbgDone();
- meiLongwordWrite(MEI_DEBUG_WAD, 0x10a);
- meiLongwordWrite(MEI_DEBUG_DATA, 0x0);
- meiPollForDbgDone();
- meiLongwordWrite(MEI_DEBUG_DEC, 0x2);
- meiLongwordWrite(MEI_DEBUG_WAD, 0xfffc);
- meiLongwordWrite(MEI_DEBUG_DATA, 0x1fffffff);
- meiPollForDbgDone();
- while(flshcnt<3){
- meiLongwordWrite(MEI_DEBUG_DEC, 0x0);
- meiLongwordWrite(MEI_DEBUG_RAD, 0x0);
- meiPollForDbgDone();
- meiLongwordRead(MEI_DEBUG_DATA, &auxreg0);
- auxreg0 = auxreg0 & 0xff000000;
- auxreg0 = auxreg0 | 0x3fff;
- meiLongwordWrite(MEI_DEBUG_WAD, 0x0);
- meiLongwordWrite(MEI_DEBUG_DATA, auxreg0);
- meiPollForDbgDone();
-
- meiLongwordWrite(MEI_DEBUG_DEC, 0x0);
- meiLongwordWrite(MEI_DEBUG_RAD, 0x5);
- meiPollForDbgDone();
- meiLongwordRead(MEI_DEBUG_DATA, &auxreg5);
- auxreg5 = auxreg5 | 0x801;
- meiLongwordWrite(MEI_DEBUG_WAD, 0x5);
- meiLongwordWrite(MEI_DEBUG_DATA, auxreg5);
- meiPollForDbgDone();
- meiLongwordWrite(MEI_DEBUG_RAD, 0x0);
- meiPollForDbgDone();
- meiLongwordRead(MEI_DEBUG_DATA, &auxreg0);
- auxreg0 = auxreg0 & 0x00ffffff;
- if(auxreg0 == 0x4000)
- flshcnt = flshcnt+1;
- else{
- if(flshcnt == 0)
- flshcnt1 = flshcnt1 +1;
- else
- flshcnt2 = flshcnt2 +1;
- }
- }
-
- return 1;
-}
-
-static int meiResetCore(void)
-{
- meiLongwordWrite(MEI_CONTROL, 0x1);
- meiLongwordWrite(MEI_DEBUG_DEC, 0x2);
- meiLongwordWrite(MEI_DEBUG_WAD, 0x31f10);
- meiLongwordWrite(MEI_DEBUG_DATA, 0xf);
- meiPollForDbgDone();
- meiLongwordWrite(MEI_DEBUG_WAD, 0x31f10);
- meiLongwordWrite(MEI_DEBUG_DATA, 0x0);
- meiPollForDbgDone();
- meiLongwordWrite(MEI_DEBUG_WAD, 0x31f00);
- meiLongwordWrite(MEI_DEBUG_DATA, 0x55);
- meiPollForDbgDone();
- return 1;
-}
-
-static int meiEnalbeMailboxInt(void)
-{
- u32 arc2meiintmsk;
- meiLongwordRead(ARC_TO_MEI_INT_MASK, &arc2meiintmsk);
- arc2meiintmsk = arc2meiintmsk | 0x1;
- meiLongwordWrite(ARC_TO_MEI_INT_MASK, arc2meiintmsk);
- meiLongwordWrite(MEI_CONTROL, 0x0);
- return 1;
-}
-
-
-
-//000002:fchang End
-
-static int mei_ioctl(struct inode * ino, struct file * fil, unsigned int command, unsigned long lon)
-{
- int i,k;
- u32 boot_loop;
- u32 page_size;
- u32 dest_addr;
- u32 j;
- u32 temp;
- u32 temp2;
- u16 trapsflag=0;
- amazon_clreoc_pkt * current_clreoc;
- struct timeval time_now;
- struct timeval time_fini;
- struct list_head * ptr;
- amazon_mei_mib * mib_ptr;
-// u16 buff[MSG_LENGTH]__attribute__ ((aligned(4)));
- structpts pts;
- int meierr=MEI_SUCCESS;
- u16 data[12]; //used in makeCMV, to pass in payload when CMV set, ignored when CMV read.
- meireg regrdwr;
- meidebug debugrdwr;
- amazon_mei_mib * temp_intvl;
- struct sk_buff * eoc_skb;
-// 603221:tc.chen start
- u16 hdlc_cmd[2];
- u16 hdlc_rx_buffer[32];
- int hdlc_rx_len=0;
-// 603221:tc.chen end
-
- int from_kernel = 0;//joelin
- if (ino == (struct inode *)0) from_kernel = 1;//joelin
-
-// printk("\n switch.command = %i\n", command);
- switch(command){
- case GET_ADSL_LINE_CODE:
- pts.adslLineTableEntry_pt = (adslLineTableEntry *)kmalloc(sizeof(adslLineTableEntry), GFP_KERNEL);
- copy_from_user((char *)pts.adslLineTableEntry_pt, (char *)lon, sizeof(adslLineTableEntry));
- if(IS_FLAG_SET((&(pts.adslLineTableEntry_pt->flags)), LINE_CODE_FLAG)){
- pts.adslLineTableEntry_pt->adslLineCode = 2;
- }
- copy_to_user((char *)lon, (char *)pts.adslLineTableEntry_pt, sizeof(adslLineTableEntry));
- kfree(pts.adslLineTableEntry_pt);
- break;
-#ifdef AMAZON_MEI_MIB_RFC3440
- case GET_ADSL_ATUC_LINE_EXT:
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
- pts.adslLineExtTableEntry_pt = (adslLineExtTableEntry *)kmalloc(sizeof(adslLineExtTableEntry), GFP_KERNEL);
- copy_from_user((char *)pts.adslLineExtTableEntry_pt, (char *)lon, sizeof(adslLineExtTableEntry));
- if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CAP_FLAG)){
- ATUC_LINE_TRANS_CAP_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 67 Index 0");
-#endif
- CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CAP_FLAG);
- }
- else{
- memcpy((&(pts.adslLineExtTableEntry_pt->adslLineTransAtucCap)), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CONFIG_FLAG)){
- ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 67 Index 0");
-#endif
- CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CONFIG_FLAG);
- }
- else{
- memcpy((&(pts.adslLineExtTableEntry_pt->adslLineTransAtucConfig)), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_ACTUAL_FLAG)){
- ATUC_LINE_TRANS_ACTUAL_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 2 Address 1 Index 0");
-#endif
- CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_ACTUAL_FLAG);
- }
- else{
- memcpy((&(pts.adslLineExtTableEntry_pt->adslLineTransAtucActual)), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), LINE_GLITE_POWER_STATE_FLAG)){ // not supported currently
-/*
- LINE_GLITE_POWER_STATE_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 2 Address 0 Index 0");
-#endif
- CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), LINE_GLITE_POWER_STATE_FLAG);
- }
- else{
- memcpy((&(pts.adslLineExtTableEntry_pt->adslLineGlitePowerState)), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
-*/
- CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), LINE_GLITE_POWER_STATE_FLAG);
- }
- copy_to_user((char *)lon, (char *)pts.adslLineExtTableEntry_pt, sizeof(adslLineExtTableEntry));
- kfree(pts.adslLineTableEntry_pt);
- up(&mei_sema);
- break;
-#endif
-
-#ifdef AMAZON_MEI_MIB_RFC3440
- case SET_ADSL_ATUC_LINE_EXT:
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
- pts.adslLineExtTableEntry_pt = (adslLineExtTableEntry *)kmalloc(sizeof(adslLineExtTableEntry), GFP_KERNEL);
- copy_from_user((char *)pts.adslLineExtTableEntry_pt, (char *)lon, sizeof(adslLineExtTableEntry));
-
- //only adslLineTransAtucConfig can be set.
- CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CAP_FLAG);
- if(IS_FLAG_SET((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CONFIG_FLAG)){
- memcpy(data,(&(pts.adslLineExtTableEntry_pt->adslLineTransAtucConfig)), 2);
- ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV_WR;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 67 Index 0");
-#endif
- CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_CONFIG_FLAG);
- }
- }
- CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), ATUC_LINE_TRANS_ACTUAL_FLAG);
- CLR_FLAG((&(pts.adslLineExtTableEntry_pt->flags)), LINE_GLITE_POWER_STATE_FLAG);
-
- copy_to_user((char *)lon, (char *)pts.adslLineExtTableEntry_pt, sizeof(adslLineExtTableEntry));
- kfree(pts.adslLineTableEntry_pt);
- up(&mei_sema);
- break;
-#endif
-
- case GET_ADSL_ATUC_PHY:
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- pts.adslAtucPhysEntry_pt = (adslAtucPhysEntry *)kmalloc(sizeof(adslAtucPhysEntry), GFP_KERNEL);
- copy_from_user((char *)pts.adslAtucPhysEntry_pt, (char *)lon, sizeof(adslAtucPhysEntry));
- if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_SER_NUM_FLAG)){
- ATUC_PHY_SER_NUM_FLAG_MAKECMV1;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 57 Index 0");
-#endif
- CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_SER_NUM_FLAG);
- }
- else{
- memcpy(pts.adslAtucPhysEntry_pt->serial_no, RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- ATUC_PHY_SER_NUM_FLAG_MAKECMV2;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 57 Index 12");
-#endif
- CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_SER_NUM_FLAG);
- }
- else{
- memcpy((pts.adslAtucPhysEntry_pt->serial_no+24), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_VENDOR_ID_FLAG)){
- ATUC_PHY_VENDOR_ID_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 64 Index 0");
-#endif
- CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_VENDOR_ID_FLAG);
- }
- else{
- memcpy(pts.adslAtucPhysEntry_pt->vendor_id.vendor_id, RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_VER_NUM_FLAG)){
- ATUC_PHY_VER_NUM_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 58 Index 0");
-#endif
- CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_PHY_VER_NUM_FLAG);
- }
- else{
- memcpy(pts.adslAtucPhysEntry_pt->version_no, RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_STAT_FLAG)){
- pts.adslAtucPhysEntry_pt->status = CurrStatus.adslAtucCurrStatus;
- }
- if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_OUT_PWR_FLAG)){
- ATUC_CURR_OUT_PWR_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 68 Index 5");
-#endif
- CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_OUT_PWR_FLAG);
- }
- else{
- memcpy((&(pts.adslAtucPhysEntry_pt->outputPwr)), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_ATTR_FLAG)){
- ATUC_CURR_ATTR_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 69 Index 0");
-#endif
- CLR_FLAG((&(pts.adslAtucPhysEntry_pt->flags)), ATUC_CURR_ATTR_FLAG);
- }
- else{
- memcpy((&(pts.adslAtucPhysEntry_pt->attainableRate)), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- copy_to_user((char *)lon, (char *)pts.adslAtucPhysEntry_pt, sizeof(adslAtucPhysEntry));
- kfree(pts.adslAtucPhysEntry_pt);
-
- up(&mei_sema);
- break;
- case GET_ADSL_ATUR_PHY:
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- pts.adslAturPhysEntry_pt = (adslAturPhysEntry *)kmalloc(sizeof(adslAturPhysEntry), GFP_KERNEL);
- copy_from_user((char *)pts.adslAturPhysEntry_pt, (char *)lon, sizeof(adslAturPhysEntry));
- if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_SER_NUM_FLAG)){
- ATUR_PHY_SER_NUM_FLAG_MAKECMV1;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 62 Index 0");
-#endif
- CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_SER_NUM_FLAG);
- }
- else{
- memcpy(pts.adslAturPhysEntry_pt->serial_no, RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- ATUR_PHY_SER_NUM_FLAG_MAKECMV2;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 62 Index 12");
-#endif
- CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_SER_NUM_FLAG);
- }
- else{
- memcpy((pts.adslAturPhysEntry_pt->serial_no+24), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_VENDOR_ID_FLAG)){
- ATUR_PHY_VENDOR_ID_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 65 Index 0");
-#endif
- CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_VENDOR_ID_FLAG);
- }
- else{
- memcpy(pts.adslAturPhysEntry_pt->vendor_id.vendor_id, RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_VER_NUM_FLAG)){
- ATUR_PHY_VER_NUM_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 61 Index 0");
-#endif
- CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_PHY_VER_NUM_FLAG);
- }
- else{
- memcpy(pts.adslAturPhysEntry_pt->version_no, RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_SNRMGN_FLAG)){
- ATUR_SNRMGN_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 68 Index 4");
-#endif
- CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_SNRMGN_FLAG);
- }
- else{
- memcpy((&(pts.adslAturPhysEntry_pt->SnrMgn)), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_ATTN_FLAG)){
- ATUR_ATTN_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 68 Index 2");
-#endif
- CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_ATTN_FLAG);
- }
- else{
- memcpy((&(pts.adslAturPhysEntry_pt->Attn)), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_STAT_FLAG)){
- pts.adslAturPhysEntry_pt->status = CurrStatus.adslAturCurrStatus;
- }
- if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_OUT_PWR_FLAG)){
- ATUR_CURR_OUT_PWR_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 69 Index 5");
-#endif
- CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_OUT_PWR_FLAG);
- }
- else{
- memcpy((&(pts.adslAturPhysEntry_pt->outputPwr)), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- if(IS_FLAG_SET((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_ATTR_FLAG)){
- ATUR_CURR_ATTR_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 68 Index 0");
-#endif
- CLR_FLAG((&(pts.adslAturPhysEntry_pt->flags)), ATUR_CURR_ATTR_FLAG);
- }
- else{
- memcpy((&(pts.adslAturPhysEntry_pt->attainableRate)), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- copy_to_user((char *)lon, (char *)pts.adslAturPhysEntry_pt, sizeof(adslAturPhysEntry));
- kfree(pts.adslAturPhysEntry_pt);
-
- up(&mei_sema);
- break;
- case GET_ADSL_ATUC_CHAN_INFO:
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- pts.adslAtucChanInfo_pt = (adslAtucChanInfo *)kmalloc(sizeof(adslAtucChanInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslAtucChanInfo_pt, (char *)lon, sizeof(adslAtucChanInfo));
- if(IS_FLAG_SET((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_INTLV_DELAY_FLAG)){
- if((chantype.interleave!=1) || (chantype.fast==1)){
- CLR_FLAG((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_INTLV_DELAY_FLAG);
- }
- else{
- ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 6 Address 3 Index 1");
-#endif
- CLR_FLAG((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_INTLV_DELAY_FLAG);
- }
- else{
- memcpy((&(pts.adslAtucChanInfo_pt->interleaveDelay)), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- }
- if(IS_FLAG_SET((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_CURR_TX_RATE_FLAG)){
- ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 6 Address 1 Index 0");
-#endif
- CLR_FLAG((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_CURR_TX_RATE_FLAG);
- }
- else{
- pts.adslAtucChanInfo_pt->currTxRate = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- }
- }
- if(IS_FLAG_SET((&(pts.adslAtucChanInfo_pt->flags)), ATUC_CHAN_PREV_TX_RATE_FLAG)){
- pts.adslAtucChanInfo_pt->prevTxRate = PrevTxRate.adslAtucChanPrevTxRate;
- }
- copy_to_user((char *)lon, (char *)pts.adslAtucChanInfo_pt, sizeof(adslAtucChanInfo));
- kfree(pts.adslAtucChanInfo_pt);
-
- up(&mei_sema);
- break;
- case GET_ADSL_ATUR_CHAN_INFO:
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- pts.adslAturChanInfo_pt = (adslAturChanInfo *)kmalloc(sizeof(adslAturChanInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslAturChanInfo_pt, (char *)lon, sizeof(adslAturChanInfo));
- if(IS_FLAG_SET((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_INTLV_DELAY_FLAG)){
- if((chantype.interleave!=1) || (chantype.fast==1)){
- CLR_FLAG((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_INTLV_DELAY_FLAG);
- }
- else{
- ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 6 Address 2 Index 1");
-#endif
- CLR_FLAG((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_INTLV_DELAY_FLAG);
- }
- else{
- memcpy((&(pts.adslAturChanInfo_pt->interleaveDelay)), RxMessage+4, ((RxMessage[0]&0xf)*2));
- }
- }
- }
- if(IS_FLAG_SET((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_CURR_TX_RATE_FLAG)){
- ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 6 Address 0 Index 0");
-#endif
- CLR_FLAG((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_CURR_TX_RATE_FLAG);
- }
- else{
- pts.adslAturChanInfo_pt->currTxRate = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- }
- }
- if(IS_FLAG_SET((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_PREV_TX_RATE_FLAG)){
- pts.adslAturChanInfo_pt->prevTxRate = PrevTxRate.adslAturChanPrevTxRate;
- }
- if(IS_FLAG_SET((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_CRC_BLK_LEN_FLAG)){
- // ? no CMV to update this
- CLR_FLAG((&(pts.adslAturChanInfo_pt->flags)), ATUR_CHAN_CRC_BLK_LEN_FLAG);
- }
- copy_to_user((char *)lon, (char *)pts.adslAturChanInfo_pt, sizeof(adslAturChanInfo));
- kfree(pts.adslAturChanInfo_pt);
-
- up(&mei_sema);
- break;
- case GET_ADSL_ATUC_PERF_DATA:
- pts.atucPerfDataEntry_pt = (atucPerfDataEntry *)kmalloc(sizeof(atucPerfDataEntry), GFP_KERNEL);
- copy_from_user((char *)pts.atucPerfDataEntry_pt, (char *)lon, sizeof(atucPerfDataEntry));
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_LOFS_FLAG)){
- pts.atucPerfDataEntry_pt->adslAtucPerfLofs=ATUC_PERF_LOFS;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_LOSS_FLAG)){
- pts.atucPerfDataEntry_pt->adslAtucPerfLoss=ATUC_PERF_LOSS;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_ESS_FLAG)){
- pts.atucPerfDataEntry_pt->adslAtucPerfESs=ATUC_PERF_ESS;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_INITS_FLAG)){
- pts.atucPerfDataEntry_pt->adslAtucPerfInits=ATUC_PERF_INITS;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_VALID_INTVLS_FLAG)){
- i=0;
- for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){
- i++;
- if(i==96)
- break;
- }
- pts.atucPerfDataEntry_pt->adslAtucPerfValidIntervals=i;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_INVALID_INTVLS_FLAG)){
- pts.atucPerfDataEntry_pt->adslAtucPerfInvalidIntervals=0;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_TIME_ELAPSED_FLAG)){
- do_gettimeofday(&time_now);
- pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinTimeElapsed=time_now.tv_sec - (current_intvl->start_time).tv_sec;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_LOFS_FLAG)){
- pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinLofs=current_intvl->AtucPerfLof;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_LOSS_FLAG)){
- pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinLoss=current_intvl->AtucPerfLos;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_ESS_FLAG)){
- pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinESs=current_intvl->AtucPerfEs;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_15MIN_INIT_FLAG)){
- pts.atucPerfDataEntry_pt->adslAtucPerfCurr15MinInits=current_intvl->AtucPerfInit;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_TIME_ELAPSED_FLAG)){
- i=0;
- for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){
- i+=900;
- }
- do_gettimeofday(&time_now);
- i+=time_now.tv_sec - (current_intvl->start_time).tv_sec;
- if(i>=86400)
- pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayTimeElapsed=i-86400;
- else
- pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayTimeElapsed=i;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_LOFS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfLof;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AtucPerfLof;
- pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayLofs=j;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_LOSS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfLos;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AtucPerfLos;
- pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayLoss=j;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_ESS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfEs;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AtucPerfEs;
- pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayESs=j;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_CURR_1DAY_INIT_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfInit;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AtucPerfInit;
- pts.atucPerfDataEntry_pt->adslAtucPerfCurr1DayInits=j;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_MON_SEC_FLAG)){
- i=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- i++;
- }
- if(i>=96)
- pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayMoniSecs=86400;
- else
- pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayMoniSecs=0;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_LOFS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfLof;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayLofs=j;
- else
- pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayLofs=0;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_LOSS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfLos;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayLoss=j;
- else
- pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayLoss=0;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_ESS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfEs;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayESs=j;
- else
- pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayESs=0;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataEntry_pt->flags)), ATUC_PERF_PREV_1DAY_INITS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfInit;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayInits=j;
- else
- pts.atucPerfDataEntry_pt->adslAtucPerfPrev1DayInits=0;
- }
-
- copy_to_user((char *)lon, (char *)pts.atucPerfDataEntry_pt, sizeof(atucPerfDataEntry));
- kfree(pts.atucPerfDataEntry_pt);
- break;
-#ifdef AMAZON_MEI_MIB_RFC3440
- case GET_ADSL_ATUC_PERF_DATA_EXT: //??? CMV mapping not available
- pts.atucPerfDataExtEntry_pt = (atucPerfDataExtEntry *)kmalloc(sizeof(atucPerfDataExtEntry), GFP_KERNEL);
- copy_from_user((char *)pts.atucPerfDataExtEntry_pt, (char *)lon, sizeof(atucPerfDataExtEntry));
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_STAT_FASTR_FLAG)){
- pts.atucPerfDataExtEntry_pt->adslAtucPerfStatFastR=ATUC_PERF_STAT_FASTR;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_STAT_FAILED_FASTR_FLAG)){
- pts.atucPerfDataExtEntry_pt->adslAtucPerfStatFailedFastR=ATUC_PERF_STAT_FAILED_FASTR;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_STAT_SESL_FLAG)){
- pts.atucPerfDataExtEntry_pt->adslAtucPerfStatSesL=ATUC_PERF_STAT_SESL;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_STAT_UASL_FLAG)){
- pts.atucPerfDataExtEntry_pt->adslAtucPerfStatUasL=ATUC_PERF_STAT_UASL;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_15MIN_FASTR_FLAG)){
- pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr15MinFastR=current_intvl->AtucPerfStatFastR;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_15MIN_FAILED_FASTR_FLAG)){
- pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr15MinFailedFastR=current_intvl->AtucPerfStatFailedFastR;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_15MIN_SESL_FLAG)){
- pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr15MinSesL=current_intvl->AtucPerfStatSesL;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_15MIN_UASL_FLAG)){
- pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr15MinUasL=current_intvl->AtucPerfStatUasL;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_1DAY_FASTR_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfStatFastR;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AtucPerfStatFastR;
- pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr1DayFastR=j;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_1DAY_FAILED_FASTR_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfStatFailedFastR;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AtucPerfStatFailedFastR;
- pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr1DayFailedFastR=j;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_1DAY_SESL_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfStatSesL;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AtucPerfStatSesL;
- pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr1DaySesL=j;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_CURR_1DAY_UASL_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfStatUasL;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AtucPerfStatUasL;
- pts.atucPerfDataExtEntry_pt->adslAtucPerfCurr1DayUasL=j;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_PREV_1DAY_FASTR_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfStatFastR;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayFastR=j;
- else
- pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayFastR=0;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_PREV_1DAY_FAILED_FASTR_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfStatFailedFastR;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayFailedFastR=j;
- else
- pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayFailedFastR=0;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_PREV_1DAY_SESL_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfStatSesL;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DaySesL=j;
- else
- pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DaySesL=0;
- }
- if(IS_FLAG_SET((&(pts.atucPerfDataExtEntry_pt->flags)), ATUC_PERF_PREV_1DAY_UASL_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AtucPerfStatUasL;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayUasL=j;
- else
- pts.atucPerfDataExtEntry_pt->adslAtucPerfPrev1DayUasL=0;
- }
- copy_to_user((char *)lon, (char *)pts.atucPerfDataExtEntry_pt, sizeof(atucPerfDataExtEntry));
- kfree(pts.atucPerfDataExtEntry_pt);
- break;
-#endif
- case GET_ADSL_ATUR_PERF_DATA:
- pts.aturPerfDataEntry_pt = (aturPerfDataEntry *)kmalloc(sizeof(aturPerfDataEntry), GFP_KERNEL);
- copy_from_user((char *)pts.aturPerfDataEntry_pt, (char *)lon, sizeof(aturPerfDataEntry));
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_LOFS_FLAG)){
- pts.aturPerfDataEntry_pt->adslAturPerfLofs=ATUR_PERF_LOFS;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_LOSS_FLAG)){
- pts.aturPerfDataEntry_pt->adslAturPerfLoss=ATUR_PERF_LOSS;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_LPR_FLAG)){
- pts.aturPerfDataEntry_pt->adslAturPerfLprs=ATUR_PERF_LPR;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_ESS_FLAG)){
- pts.aturPerfDataEntry_pt->adslAturPerfESs=ATUR_PERF_ESS;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_VALID_INTVLS_FLAG)){
- i=0;
- for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){
- i++;
- if(i==96)
- break;
- }
- pts.aturPerfDataEntry_pt->adslAturPerfValidIntervals=i;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_INVALID_INTVLS_FLAG)){
- pts.aturPerfDataEntry_pt->adslAturPerfInvalidIntervals=0;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_TIME_ELAPSED_FLAG)){
- do_gettimeofday(&time_now);
- pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinTimeElapsed=time_now.tv_sec - (current_intvl->start_time).tv_sec;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_LOFS_FLAG)){
- pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinLofs=current_intvl->AturPerfLof;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_LOSS_FLAG)){
- pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinLoss=current_intvl->AturPerfLos;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_LPR_FLAG)){
- pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinLprs=current_intvl->AturPerfLpr;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_15MIN_ESS_FLAG)){
- pts.aturPerfDataEntry_pt->adslAturPerfCurr15MinESs=current_intvl->AturPerfEs;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_TIME_ELAPSED_FLAG)){
- i=0;
- for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){
- i+=900;
- }
- do_gettimeofday(&time_now);
- i+=time_now.tv_sec - (current_intvl->start_time).tv_sec;
- if(i>=86400)
- pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayTimeElapsed=i-86400;
- else
- pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayTimeElapsed=i;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_LOFS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturPerfLof;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AturPerfLof;
- pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayLofs=j;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_LOSS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturPerfLos;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AturPerfLos;
- pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayLoss=j;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_LPR_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturPerfLpr;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AturPerfLpr;
- pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayLprs=j;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_CURR_1DAY_ESS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturPerfEs;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AturPerfEs;
- pts.aturPerfDataEntry_pt->adslAturPerfCurr1DayESs=j;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_MON_SEC_FLAG)){
- i=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- i++;
- }
- if(i>=96)
- pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayMoniSecs=86400;
- else
- pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayMoniSecs=0;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_LOFS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturPerfLof;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLofs=j;
- else
- pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLofs=0;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_LOSS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturPerfLos;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLoss=j;
- else
- pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLoss=0;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_LPR_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturPerfLpr;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLprs=j;
- else
- pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayLprs=0;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataEntry_pt->flags)), ATUR_PERF_PREV_1DAY_ESS_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturPerfEs;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayESs=j;
- else
- pts.aturPerfDataEntry_pt->adslAturPerfPrev1DayESs=0;
- }
-
- copy_to_user((char *)lon, (char *)pts.aturPerfDataEntry_pt, sizeof(aturPerfDataEntry));
- kfree(pts.aturPerfDataEntry_pt);
- break;
-#ifdef AMAZON_MEI_MIB_RFC3440
- case GET_ADSL_ATUR_PERF_DATA_EXT:
- pts.aturPerfDataExtEntry_pt = (aturPerfDataExtEntry *)kmalloc(sizeof(aturPerfDataExtEntry), GFP_KERNEL);
- copy_from_user((char *)pts.aturPerfDataExtEntry_pt, (char *)lon, sizeof(aturPerfDataExtEntry));
- if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_STAT_SESL_FLAG)){
- pts.aturPerfDataExtEntry_pt->adslAturPerfStatSesL=ATUR_PERF_STAT_SESL;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_STAT_UASL_FLAG)){
- pts.aturPerfDataExtEntry_pt->adslAturPerfStatUasL=ATUR_PERF_STAT_UASL;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_CURR_15MIN_SESL_FLAG)){
- pts.aturPerfDataExtEntry_pt->adslAturPerfCurr15MinSesL=current_intvl->AturPerfStatSesL;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_CURR_15MIN_UASL_FLAG)){
- pts.aturPerfDataExtEntry_pt->adslAturPerfCurr15MinUasL=current_intvl->AturPerfStatUasL;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_CURR_1DAY_SESL_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturPerfStatSesL;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AturPerfStatSesL;
- pts.aturPerfDataExtEntry_pt->adslAturPerfCurr1DaySesL=j;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_CURR_1DAY_UASL_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturPerfStatUasL;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AturPerfStatUasL;
- pts.aturPerfDataExtEntry_pt->adslAturPerfCurr1DayUasL=j;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_PREV_1DAY_SESL_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturPerfStatSesL;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.aturPerfDataExtEntry_pt->adslAturPerfPrev1DaySesL=j;
- else
- pts.aturPerfDataExtEntry_pt->adslAturPerfPrev1DaySesL=0;
- }
- if(IS_FLAG_SET((&(pts.aturPerfDataExtEntry_pt->flags)), ATUR_PERF_PREV_1DAY_UASL_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturPerfStatUasL;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.aturPerfDataExtEntry_pt->adslAturPerfPrev1DayUasL=j;
- else
- pts.aturPerfDataExtEntry_pt->adslAturPerfPrev1DayUasL=0;
- }
- copy_to_user((char *)lon, (char *)pts.aturPerfDataExtEntry_pt, sizeof(aturPerfDataExtEntry));
- kfree(pts.aturPerfDataExtEntry_pt);
- break;
-#endif
- case GET_ADSL_ATUC_INTVL_INFO:
- pts.adslAtucIntvlInfo_pt = (adslAtucIntvlInfo *)kmalloc(sizeof(adslAtucIntvlInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslAtucIntvlInfo_pt, (char *)lon, sizeof(adslAtucIntvlInfo));
-
- if(pts.adslAtucIntvlInfo_pt->IntervalNumber <1){
- pts.adslAtucIntvlInfo_pt->intervalLOF = ATUC_PERF_LOFS;
- pts.adslAtucIntvlInfo_pt->intervalLOS = ATUC_PERF_LOSS;
- pts.adslAtucIntvlInfo_pt->intervalES = ATUC_PERF_ESS;
- pts.adslAtucIntvlInfo_pt->intervalInits = ATUC_PERF_INITS;
- pts.adslAtucIntvlInfo_pt->intervalValidData = 1;
- }
- else{
- i=0;
- for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){
- i++;
- if(i==pts.adslAtucIntvlInfo_pt->IntervalNumber){
- temp_intvl = list_entry(ptr, amazon_mei_mib, list);
- pts.adslAtucIntvlInfo_pt->intervalLOF = temp_intvl->AtucPerfLof;
- pts.adslAtucIntvlInfo_pt->intervalLOS = temp_intvl->AtucPerfLos;
- pts.adslAtucIntvlInfo_pt->intervalES = temp_intvl->AtucPerfEs;
- pts.adslAtucIntvlInfo_pt->intervalInits = temp_intvl->AtucPerfInit;
- pts.adslAtucIntvlInfo_pt->intervalValidData = 1;
- break;
- }
- }
- if(ptr==&interval_list){
- pts.adslAtucIntvlInfo_pt->intervalValidData = 0;
- pts.adslAtucIntvlInfo_pt->flags = 0;
- pts.adslAtucIntvlInfo_pt->intervalLOF = 0;
- pts.adslAtucIntvlInfo_pt->intervalLOS = 0;
- pts.adslAtucIntvlInfo_pt->intervalES = 0;
- pts.adslAtucIntvlInfo_pt->intervalInits = 0;
- }
- }
-
- copy_to_user((char *)lon, (char *)pts.adslAtucIntvlInfo_pt, sizeof(adslAtucIntvlInfo));
- kfree(pts.adslAtucIntvlInfo_pt);
- break;
-#ifdef AMAZON_MEI_MIB_RFC3440
- case GET_ADSL_ATUC_INTVL_EXT_INFO:
- pts.adslAtucInvtlExtInfo_pt = (adslAtucInvtlExtInfo *)kmalloc(sizeof(adslAtucInvtlExtInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslAtucInvtlExtInfo_pt, (char *)lon, sizeof(adslAtucInvtlExtInfo));
- if(pts.adslAtucInvtlExtInfo_pt->IntervalNumber <1){
- pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFastR = ATUC_PERF_STAT_FASTR;
- pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFailedFastR = ATUC_PERF_STAT_FAILED_FASTR;
- pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalSesL = ATUC_PERF_STAT_SESL;
- pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalUasL = ATUC_PERF_STAT_UASL;
-// pts.adslAtucInvtlExtInfo_pt->intervalValidData = 1;
- }
- else{
- i=0;
- for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){
- i++;
- if(i==pts.adslAtucInvtlExtInfo_pt->IntervalNumber){
- temp_intvl = list_entry(ptr, amazon_mei_mib, list);
- pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFastR = temp_intvl->AtucPerfStatFastR;
- pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFailedFastR = temp_intvl->AtucPerfStatFailedFastR;
- pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalSesL = temp_intvl->AtucPerfStatSesL;
- pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalUasL = temp_intvl->AtucPerfStatUasL;
-// pts.adslAtucInvtlExtInfo_pt->intervalValidData = 1;
- break;
- }
- }
- if(ptr==&interval_list){
-// pts.adslAtucInvtlExtInfo_pt->intervalValidData = 0;
- pts.adslAtucInvtlExtInfo_pt->flags = 0;
- pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFastR = 0;
- pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalFailedFastR = 0;
- pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalSesL = 0;
- pts.adslAtucInvtlExtInfo_pt->adslAtucIntervalUasL = 0;
- }
- }
- copy_to_user((char *)lon, (char *)pts.adslAtucInvtlExtInfo_pt, sizeof(adslAtucInvtlExtInfo));
- kfree(pts.adslAtucInvtlExtInfo_pt);
- break;
-#endif
- case GET_ADSL_ATUR_INTVL_INFO:
- pts.adslAturIntvlInfo_pt = (adslAturIntvlInfo *)kmalloc(sizeof(adslAturIntvlInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslAturIntvlInfo_pt, (char *)lon, sizeof(adslAturIntvlInfo));
-
- if(pts.adslAturIntvlInfo_pt->IntervalNumber <1){
- pts.adslAturIntvlInfo_pt->intervalLOF = ATUR_PERF_LOFS;
- pts.adslAturIntvlInfo_pt->intervalLOS = ATUR_PERF_LOSS;
- pts.adslAturIntvlInfo_pt->intervalES = ATUR_PERF_ESS;
- pts.adslAturIntvlInfo_pt->intervalLPR = ATUR_PERF_LPR;
- pts.adslAturIntvlInfo_pt->intervalValidData = 1;
- }
- else{
- i=0;
- for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){
- i++;
- if(i==pts.adslAturIntvlInfo_pt->IntervalNumber){
- temp_intvl = list_entry(ptr, amazon_mei_mib, list);
- pts.adslAturIntvlInfo_pt->intervalLOF = temp_intvl->AturPerfLof;
- pts.adslAturIntvlInfo_pt->intervalLOS = temp_intvl->AturPerfLos;
- pts.adslAturIntvlInfo_pt->intervalES = temp_intvl->AturPerfEs;
- pts.adslAturIntvlInfo_pt->intervalLPR = temp_intvl->AturPerfLpr;
- pts.adslAturIntvlInfo_pt->intervalValidData = 1;
- break;
- }
- }
- if(ptr==&interval_list){
- pts.adslAturIntvlInfo_pt->intervalValidData = 0;
- pts.adslAturIntvlInfo_pt->flags = 0;
- pts.adslAturIntvlInfo_pt->intervalLOF = 0;
- pts.adslAturIntvlInfo_pt->intervalLOS = 0;
- pts.adslAturIntvlInfo_pt->intervalES = 0;
- pts.adslAturIntvlInfo_pt->intervalLPR = 0;
- }
- }
-
- copy_to_user((char *)lon, (char *)pts.adslAturIntvlInfo_pt, sizeof(adslAturIntvlInfo));
- kfree(pts.adslAturIntvlInfo_pt);
- break;
-#ifdef AMAZON_MEI_MIB_RFC3440
- case GET_ADSL_ATUR_INTVL_EXT_INFO:
- pts.adslAturInvtlExtInfo_pt = (adslAturInvtlExtInfo *)kmalloc(sizeof(adslAturInvtlExtInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslAturInvtlExtInfo_pt, (char *)lon, sizeof(adslAturInvtlExtInfo));
-
- if(pts.adslAturInvtlExtInfo_pt->IntervalNumber <1){
- pts.adslAturInvtlExtInfo_pt->adslAturIntervalSesL = ATUR_PERF_STAT_SESL;
- pts.adslAturInvtlExtInfo_pt->adslAturIntervalUasL = ATUR_PERF_STAT_UASL;
-// pts.adslAturInvtlExtInfo_pt->intervalValidData = 1;
- }
- else{
- i=0;
- for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){
- i++;
- if(i==pts.adslAturInvtlExtInfo_pt->IntervalNumber){
- temp_intvl = list_entry(ptr, amazon_mei_mib, list);
- pts.adslAturInvtlExtInfo_pt->adslAturIntervalSesL = temp_intvl->AturPerfStatSesL;
- pts.adslAturInvtlExtInfo_pt->adslAturIntervalUasL = temp_intvl->AturPerfStatUasL;
-// pts.adslAturInvtlExtInfo_pt->intervalValidData = 1;
- break;
- }
- }
- if(ptr==&interval_list){
-// pts.adslAturInvtlExtInfo_pt->intervalValidData = 0;
- pts.adslAturInvtlExtInfo_pt->flags = 0;
- pts.adslAturInvtlExtInfo_pt->adslAturIntervalSesL = 0;
- pts.adslAturInvtlExtInfo_pt->adslAturIntervalUasL = 0;
- }
- }
-
- copy_to_user((char *)lon, (char *)pts.adslAturInvtlExtInfo_pt, sizeof(adslAturInvtlExtInfo));
- kfree(pts.adslAturInvtlExtInfo_pt);
- break;
-#endif
- case GET_ADSL_ATUC_CHAN_PERF_DATA:
- pts.atucChannelPerfDataEntry_pt = (atucChannelPerfDataEntry *)kmalloc(sizeof(atucChannelPerfDataEntry), GFP_KERNEL);
- copy_from_user((char *)pts.atucChannelPerfDataEntry_pt, (char *)lon, sizeof(atucChannelPerfDataEntry));
-
- pts.atucChannelPerfDataEntry_pt->flags = 0;
-
- copy_to_user((char *)lon, (char *)pts.atucChannelPerfDataEntry_pt, sizeof(atucChannelPerfDataEntry));
- kfree(pts.atucChannelPerfDataEntry_pt);
- break;
- case GET_ADSL_ATUR_CHAN_PERF_DATA:
- pts.aturChannelPerfDataEntry_pt = (aturChannelPerfDataEntry *)kmalloc(sizeof(aturChannelPerfDataEntry), GFP_KERNEL);
- copy_from_user((char *)pts.aturChannelPerfDataEntry_pt, (char *)lon, sizeof(aturChannelPerfDataEntry));
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_RECV_BLK_FLAG)){
- pts.aturChannelPerfDataEntry_pt->adslAturChanReceivedBlks=ATUR_CHAN_RECV_BLK;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_TX_BLK_FLAG)){
- pts.aturChannelPerfDataEntry_pt->adslAturChanTransmittedBlks=ATUR_CHAN_TX_BLK;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_CORR_BLK_FLAG)){
- pts.aturChannelPerfDataEntry_pt->adslAturChanCorrectedBlks=ATUR_CHAN_CORR_BLK;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_UNCORR_BLK_FLAG)){
- pts.aturChannelPerfDataEntry_pt->adslAturChanUncorrectBlks=ATUR_CHAN_UNCORR_BLK;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_VALID_INTVL_FLAG)){
- i=0;
- for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){
- i++;
- if(i==96)
- break;
- }
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfValidIntervals=i;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_INVALID_INTVL_FLAG)){
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfInvalidIntervals=0;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG)){
- do_gettimeofday(&time_now);
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinTimeElapsed=time_now.tv_sec - (current_intvl->start_time).tv_sec;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG)){
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinReceivedBlks=current_intvl->AturChanPerfRxBlk;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG)){
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinTransmittedBlks=current_intvl->AturChanPerfTxBlk;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG)){
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinCorrectedBlks=current_intvl->AturChanPerfCorrBlk;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG)){
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr15MinUncorrectBlks=current_intvl->AturChanPerfUncorrBlk;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG)){
- i=0;
- for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){
- i+=900;
- }
- do_gettimeofday(&time_now);
- i+=time_now.tv_sec - (current_intvl->start_time).tv_sec;
- if(i>=86400)
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayTimeElapsed=i-86400;
- else
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayTimeElapsed=i;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturChanPerfRxBlk;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AturChanPerfRxBlk;
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayReceivedBlks=j;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturChanPerfTxBlk;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AturChanPerfTxBlk;
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayTransmittedBlks=j;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturChanPerfCorrBlk;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AturChanPerfCorrBlk;
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayCorrectedBlks=j;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturChanPerfUncorrBlk;
- i++;
- if(i==96)
- j=0;
- }
- j+=current_intvl->AturChanPerfUncorrBlk;
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfCurr1DayUncorrectBlks=j;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG)){
- i=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- i++;
- }
- if(i>=96)
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayMoniSecs=86400;
- else
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayMoniSecs=0;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturChanPerfRxBlk;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayReceivedBlks=j;
- else
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayReceivedBlks=0;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_TRANS_BLK_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturChanPerfTxBlk;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayTransmittedBlks=j;
- else
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayTransmittedBlks=0;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturChanPerfCorrBlk;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayCorrectedBlks=j;
- else
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayCorrectedBlks=0;
- }
- if(IS_FLAG_SET((&(pts.aturChannelPerfDataEntry_pt->flags)), ATUR_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG)){
- i=0;
- j=0;
- for(ptr=interval_list.next; ptr!=&(current_intvl->list); ptr=ptr->next){
- mib_ptr = list_entry(ptr, amazon_mei_mib, list);
- j+=mib_ptr->AturChanPerfUncorrBlk;
- i++;
- if(i==96)
- break;
- }
- if(i==96)
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayUncorrectBlks=j;
- else
- pts.aturChannelPerfDataEntry_pt->adslAturChanPerfPrev1DayUncorrectBlks=0;
- }
-
- copy_to_user((char *)lon, (char *)pts.aturChannelPerfDataEntry_pt, sizeof(aturChannelPerfDataEntry));
- kfree(pts.aturChannelPerfDataEntry_pt);
- break;
- case GET_ADSL_ATUC_CHAN_INTVL_INFO:
- pts.adslAtucChanIntvlInfo_pt = (adslAtucChanIntvlInfo *)kmalloc(sizeof(adslAtucChanIntvlInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslAtucChanIntvlInfo_pt, (char *)lon, sizeof(adslAtucChanIntvlInfo));
-
- pts.adslAtucChanIntvlInfo_pt->flags = 0;
-
- copy_to_user((char *)lon, (char *)pts.adslAtucChanIntvlInfo_pt, sizeof(adslAtucChanIntvlInfo));
- kfree(pts.adslAtucChanIntvlInfo_pt);
- break;
- case GET_ADSL_ATUR_CHAN_INTVL_INFO:
- pts.adslAturChanIntvlInfo_pt = (adslAturChanIntvlInfo *)kmalloc(sizeof(adslAturChanIntvlInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslAturChanIntvlInfo_pt, (char *)lon, sizeof(adslAturChanIntvlInfo));
-
- if(pts.adslAturChanIntvlInfo_pt->IntervalNumber <1){
- pts.adslAturChanIntvlInfo_pt->chanIntervalRecvdBlks = ATUR_CHAN_RECV_BLK;
- pts.adslAturChanIntvlInfo_pt->chanIntervalXmitBlks = ATUR_CHAN_TX_BLK;
- pts.adslAturChanIntvlInfo_pt->chanIntervalCorrectedBlks = ATUR_CHAN_CORR_BLK;
- pts.adslAturChanIntvlInfo_pt->chanIntervalUncorrectBlks = ATUR_CHAN_UNCORR_BLK;
- pts.adslAturChanIntvlInfo_pt->intervalValidData = 1;
- }
- else{
- i=0;
- for(ptr=(current_intvl->list).prev; ptr!=&interval_list; ptr=ptr->prev){
- i++;
- if(i==pts.adslAturChanIntvlInfo_pt->IntervalNumber){
- temp_intvl = list_entry(ptr, amazon_mei_mib, list);
- pts.adslAturChanIntvlInfo_pt->chanIntervalRecvdBlks = temp_intvl->AturChanPerfRxBlk;
- pts.adslAturChanIntvlInfo_pt->chanIntervalXmitBlks = temp_intvl->AturChanPerfTxBlk;
- pts.adslAturChanIntvlInfo_pt->chanIntervalCorrectedBlks = temp_intvl->AturChanPerfCorrBlk;
- pts.adslAturChanIntvlInfo_pt->chanIntervalUncorrectBlks = temp_intvl->AturChanPerfUncorrBlk;
- pts.adslAturChanIntvlInfo_pt->intervalValidData = 1;
- break;
- }
- }
- if(ptr==&interval_list){
- pts.adslAturChanIntvlInfo_pt->intervalValidData = 0;
- pts.adslAturChanIntvlInfo_pt->flags = 0;
- }
- }
-
- copy_to_user((char *)lon, (char *)pts.adslAturChanIntvlInfo_pt, sizeof(adslAturChanIntvlInfo));
- kfree(pts.adslAturChanIntvlInfo_pt);
- break;
- case GET_ADSL_ALRM_CONF_PROF:
- pts.adslLineAlarmConfProfileEntry_pt = (adslLineAlarmConfProfileEntry *)kmalloc(sizeof(adslLineAlarmConfProfileEntry), GFP_KERNEL);
- copy_from_user((char *)pts.adslLineAlarmConfProfileEntry_pt, (char *)lon, sizeof(adslLineAlarmConfProfileEntry));
-
- strncpy(pts.adslLineAlarmConfProfileEntry_pt->adslLineAlarmConfProfileName, AlarmConfProfile.adslLineAlarmConfProfileName, 32);
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_LOFS_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinLofs=AlarmConfProfile.adslAtucThresh15MinLofs;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_LOSS_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinLoss=AlarmConfProfile.adslAtucThresh15MinLoss;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_ESS_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinESs=AlarmConfProfile.adslAtucThresh15MinESs;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_FAST_RATEUP_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshFastRateUp=AlarmConfProfile.adslAtucThreshFastRateUp;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_INTERLEAVE_RATEUP_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshInterleaveRateUp=AlarmConfProfile.adslAtucThreshInterleaveRateUp;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_FAST_RATEDOWN_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshFastRateDown=AlarmConfProfile.adslAtucThreshFastRateDown;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshInterleaveRateDown=AlarmConfProfile.adslAtucThreshInterleaveRateDown;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAtucInitFailureTrapEnable=AlarmConfProfile.adslAtucInitFailureTrapEnable;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LOFS_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLofs=AlarmConfProfile.adslAturThresh15MinLofs;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LOSS_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLoss=AlarmConfProfile.adslAturThresh15MinLoss;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LPRS_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLprs=AlarmConfProfile.adslAturThresh15MinLprs;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_ESS_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinESs=AlarmConfProfile.adslAturThresh15MinESs;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_FAST_RATEUP_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshFastRateUp=AlarmConfProfile.adslAturThreshFastRateUp;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_INTERLEAVE_RATEUP_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshInterleaveRateUp=AlarmConfProfile.adslAturThreshInterleaveRateUp;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_FAST_RATEDOWN_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshFastRateDown=AlarmConfProfile.adslAturThreshFastRateDown;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshInterleaveRateDown=AlarmConfProfile.adslAturThreshInterleaveRateDown;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG)){
- pts.adslLineAlarmConfProfileEntry_pt->adslLineAlarmConfProfileRowStatus=AlarmConfProfile.adslLineAlarmConfProfileRowStatus;
- }
- copy_to_user((char *)lon, (char *)pts.adslLineAlarmConfProfileEntry_pt, sizeof(adslLineAlarmConfProfileEntry));
- kfree(pts.adslLineAlarmConfProfileEntry_pt);
- break;
-#ifdef AMAZON_MEI_MIB_RFC3440
- case GET_ADSL_ALRM_CONF_PROF_EXT:
- pts.adslLineAlarmConfProfileExtEntry_pt = (adslLineAlarmConfProfileExtEntry *)kmalloc(sizeof(adslLineAlarmConfProfileExtEntry), GFP_KERNEL);
- copy_from_user((char *)pts.adslLineAlarmConfProfileExtEntry_pt, (char *)lon, sizeof(adslLineAlarmConfProfileExtEntry));
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_FAILED_FASTR_FLAG)){
- pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinFailedFastR=AlarmConfProfileExt.adslAtucThreshold15MinFailedFastR;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_SESL_FLAG)){
- pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinSesL=AlarmConfProfileExt.adslAtucThreshold15MinSesL;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_UASL_FLAG)){
- pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinUasL=AlarmConfProfileExt.adslAtucThreshold15MinUasL;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUR_THRESH_15MIN_SESL_FLAG)){
- pts.adslLineAlarmConfProfileExtEntry_pt->adslAturThreshold15MinSesL=AlarmConfProfileExt.adslAturThreshold15MinSesL;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUR_THRESH_15MIN_UASL_FLAG)){
- pts.adslLineAlarmConfProfileExtEntry_pt->adslAturThreshold15MinUasL=AlarmConfProfileExt.adslAturThreshold15MinUasL;
- }
- copy_to_user((char *)lon, (char *)pts.adslLineAlarmConfProfileExtEntry_pt, sizeof(adslLineAlarmConfProfileExtEntry));
- kfree(pts.adslLineAlarmConfProfileExtEntry_pt);
- break;
-#endif
- case SET_ADSL_ALRM_CONF_PROF:
- pts.adslLineAlarmConfProfileEntry_pt = (adslLineAlarmConfProfileEntry *)kmalloc(sizeof(adslLineAlarmConfProfileEntry), GFP_KERNEL);
- copy_from_user((char *)pts.adslLineAlarmConfProfileEntry_pt, (char *)lon, sizeof(adslLineAlarmConfProfileEntry));
-
- strncpy(AlarmConfProfile.adslLineAlarmConfProfileName, pts.adslLineAlarmConfProfileEntry_pt->adslLineAlarmConfProfileName, 32);
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_LOFS_FLAG)){
- AlarmConfProfile.adslAtucThresh15MinLofs=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinLofs;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_LOSS_FLAG)){
- AlarmConfProfile.adslAtucThresh15MinLoss=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinLoss;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_15MIN_ESS_FLAG)){
- AlarmConfProfile.adslAtucThresh15MinESs=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThresh15MinESs;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_FAST_RATEUP_FLAG)){
- AlarmConfProfile.adslAtucThreshFastRateUp=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshFastRateUp;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_INTERLEAVE_RATEUP_FLAG)){
- AlarmConfProfile.adslAtucThreshInterleaveRateUp=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshInterleaveRateUp;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_FAST_RATEDOWN_FLAG)){
- AlarmConfProfile.adslAtucThreshFastRateDown=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshFastRateDown;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG)){
- AlarmConfProfile.adslAtucThreshInterleaveRateDown=pts.adslLineAlarmConfProfileEntry_pt->adslAtucThreshInterleaveRateDown;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG)){
- AlarmConfProfile.adslAtucInitFailureTrapEnable=pts.adslLineAlarmConfProfileEntry_pt->adslAtucInitFailureTrapEnable;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LOFS_FLAG)){
- AlarmConfProfile.adslAturThresh15MinLofs=pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLofs;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LOSS_FLAG)){
- AlarmConfProfile.adslAturThresh15MinLoss=pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLoss;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_LPRS_FLAG)){
- AlarmConfProfile.adslAturThresh15MinLprs=pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinLprs;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_15MIN_ESS_FLAG)){
- AlarmConfProfile.adslAturThresh15MinESs=pts.adslLineAlarmConfProfileEntry_pt->adslAturThresh15MinESs;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_FAST_RATEUP_FLAG)){
- AlarmConfProfile.adslAturThreshFastRateUp=pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshFastRateUp;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_INTERLEAVE_RATEUP_FLAG)){
- AlarmConfProfile.adslAturThreshInterleaveRateUp=pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshInterleaveRateUp;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_FAST_RATEDOWN_FLAG)){
- AlarmConfProfile.adslAturThreshFastRateDown=pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshFastRateDown;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG)){
- AlarmConfProfile.adslAturThreshInterleaveRateDown=pts.adslLineAlarmConfProfileEntry_pt->adslAturThreshInterleaveRateDown;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileEntry_pt->flags)), LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG)){
- AlarmConfProfile.adslLineAlarmConfProfileRowStatus=pts.adslLineAlarmConfProfileEntry_pt->adslLineAlarmConfProfileRowStatus;
- }
- copy_to_user((char *)lon, (char *)pts.adslLineAlarmConfProfileEntry_pt, sizeof(adslLineAlarmConfProfileEntry));
- kfree(pts.adslLineAlarmConfProfileEntry_pt);
- break;
-
-#ifdef AMAZON_MEI_MIB_RFC3440
- case SET_ADSL_ALRM_CONF_PROF_EXT:
- pts.adslLineAlarmConfProfileExtEntry_pt = (adslLineAlarmConfProfileExtEntry *)kmalloc(sizeof(adslLineAlarmConfProfileExtEntry), GFP_KERNEL);
- copy_from_user((char *)pts.adslLineAlarmConfProfileExtEntry_pt, (char *)lon, sizeof(adslLineAlarmConfProfileExtEntry));
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_FAILED_FASTR_FLAG)){
- AlarmConfProfileExt.adslAtucThreshold15MinFailedFastR=pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinFailedFastR;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_SESL_FLAG)){
- AlarmConfProfileExt.adslAtucThreshold15MinSesL=pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinSesL;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUC_THRESH_15MIN_UASL_FLAG)){
- AlarmConfProfileExt.adslAtucThreshold15MinUasL=pts.adslLineAlarmConfProfileExtEntry_pt->adslAtucThreshold15MinUasL;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUR_THRESH_15MIN_SESL_FLAG)){
- AlarmConfProfileExt.adslAturThreshold15MinSesL=pts.adslLineAlarmConfProfileExtEntry_pt->adslAturThreshold15MinSesL;
- }
- if(IS_FLAG_SET((&(pts.adslLineAlarmConfProfileExtEntry_pt->flags)), ATUR_THRESH_15MIN_UASL_FLAG)){
- AlarmConfProfileExt.adslAturThreshold15MinUasL=pts.adslLineAlarmConfProfileExtEntry_pt->adslAturThreshold15MinUasL;
- }
- copy_to_user((char *)lon, (char *)pts.adslLineAlarmConfProfileExtEntry_pt, sizeof(adslLineAlarmConfProfileExtEntry));
- kfree(pts.adslLineAlarmConfProfileExtEntry_pt);
- break;
-#endif
-
- case ADSL_ATUR_TRAPS:
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- trapsflag=0;
- if(AlarmConfProfile.adslAtucThresh15MinLofs!=0 && current_intvl->AtucPerfLof>=AlarmConfProfile.adslAtucThresh15MinLofs)
- trapsflag|=ATUC_PERF_LOFS_THRESH_FLAG;
- if(AlarmConfProfile.adslAtucThresh15MinLoss!=0 && current_intvl->AtucPerfLos>=AlarmConfProfile.adslAtucThresh15MinLoss)
- trapsflag|=ATUC_PERF_LOSS_THRESH_FLAG;
- if(AlarmConfProfile.adslAtucThresh15MinESs!=0 && current_intvl->AtucPerfEs>=AlarmConfProfile.adslAtucThresh15MinESs)
- trapsflag|=ATUC_PERF_ESS_THRESH_FLAG;
- if(chantype.fast==1){
- if(AlarmConfProfile.adslAtucThreshFastRateUp!=0 || AlarmConfProfile.adslAtucThreshFastRateDown!=0){
- ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 6 Address 1 Index 0");
-#endif
- }
- else{
- temp = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- if((AlarmConfProfile.adslAtucThreshFastRateUp!=0) && (temp>=PrevTxRate.adslAtucChanPrevTxRate+AlarmConfProfile.adslAtucThreshFastRateUp)){
- trapsflag|=ATUC_RATE_CHANGE_FLAG;
- PrevTxRate.adslAtucChanPrevTxRate = temp;
- }
- if((AlarmConfProfile.adslAtucThreshFastRateDown!=0) && (temp<=PrevTxRate.adslAtucChanPrevTxRate-AlarmConfProfile.adslAtucThreshFastRateDown)){
- trapsflag|=ATUC_RATE_CHANGE_FLAG;
- PrevTxRate.adslAtucChanPrevTxRate = temp;
- }
- }
- }
- }
- if(chantype.interleave==1){
- if(AlarmConfProfile.adslAtucThreshInterleaveRateUp!=0 || AlarmConfProfile.adslAtucThreshInterleaveRateDown!=0){
- ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 6 Address 1 Index 0");
-#endif
- }
- else{
- temp = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- if((AlarmConfProfile.adslAtucThreshInterleaveRateUp!=0) && (temp>=PrevTxRate.adslAtucChanPrevTxRate+AlarmConfProfile.adslAtucThreshInterleaveRateUp)){
- trapsflag|=ATUC_RATE_CHANGE_FLAG;
- PrevTxRate.adslAtucChanPrevTxRate = temp;
- }
- if((AlarmConfProfile.adslAtucThreshInterleaveRateDown!=0) && (temp<=PrevTxRate.adslAtucChanPrevTxRate-AlarmConfProfile.adslAtucThreshInterleaveRateDown)){
- trapsflag|=ATUC_RATE_CHANGE_FLAG;
- PrevTxRate.adslAtucChanPrevTxRate = temp;
- }
- }
- }
- }
- if(AlarmConfProfile.adslAturThresh15MinLofs!=0 && current_intvl->AturPerfLof>=AlarmConfProfile.adslAturThresh15MinLofs)
- trapsflag|=ATUR_PERF_LOFS_THRESH_FLAG;
- if(AlarmConfProfile.adslAturThresh15MinLoss!=0 && current_intvl->AturPerfLos>=AlarmConfProfile.adslAturThresh15MinLoss)
- trapsflag|=ATUR_PERF_LOSS_THRESH_FLAG;
- if(AlarmConfProfile.adslAturThresh15MinLprs!=0 && current_intvl->AturPerfLpr>=AlarmConfProfile.adslAturThresh15MinLprs)
- trapsflag|=ATUR_PERF_LPRS_THRESH_FLAG;
- if(AlarmConfProfile.adslAturThresh15MinESs!=0 && current_intvl->AturPerfEs>=AlarmConfProfile.adslAturThresh15MinESs)
- trapsflag|=ATUR_PERF_ESS_THRESH_FLAG;
- if(chantype.fast==1){
- if(AlarmConfProfile.adslAturThreshFastRateUp!=0 || AlarmConfProfile.adslAturThreshFastRateDown!=0){
- ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 6 Address 0 Index 0");
-#endif
- }
- else{
- temp = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- if((AlarmConfProfile.adslAturThreshFastRateUp!=0) && (temp>=PrevTxRate.adslAturChanPrevTxRate+AlarmConfProfile.adslAturThreshFastRateUp)){
- trapsflag|=ATUR_RATE_CHANGE_FLAG;
- PrevTxRate.adslAturChanPrevTxRate = temp;
- }
- if((AlarmConfProfile.adslAturThreshFastRateDown!=0) && (temp<=PrevTxRate.adslAturChanPrevTxRate-AlarmConfProfile.adslAturThreshFastRateDown)){
- trapsflag|=ATUR_RATE_CHANGE_FLAG;
- PrevTxRate.adslAturChanPrevTxRate = temp;
- }
- }
- }
- }
- if(chantype.interleave==1){
- if(AlarmConfProfile.adslAturThreshInterleaveRateUp!=0 || AlarmConfProfile.adslAturThreshInterleaveRateDown!=0){
- ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 6 Address 0 Index 0");
-#endif
- }
- else{
- temp = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- if((AlarmConfProfile.adslAturThreshInterleaveRateUp!=0) && (temp>=PrevTxRate.adslAturChanPrevTxRate+AlarmConfProfile.adslAturThreshInterleaveRateUp)){
- trapsflag|=ATUR_RATE_CHANGE_FLAG;
- PrevTxRate.adslAturChanPrevTxRate = temp;
- }
- if((AlarmConfProfile.adslAturThreshInterleaveRateDown!=0) && (temp<=PrevTxRate.adslAturChanPrevTxRate-AlarmConfProfile.adslAturThreshInterleaveRateDown)){
- trapsflag|=ATUR_RATE_CHANGE_FLAG;
- PrevTxRate.adslAturChanPrevTxRate = temp;
- }
- }
- }
- }
- copy_to_user((char *)lon, (char *)(&trapsflag), 2);
-
- up(&mei_sema);
- break;
-
-#ifdef AMAZON_MEI_MIB_RFC3440
- case ADSL_ATUR_EXT_TRAPS:
- trapsflag=0;
- if(AlarmConfProfileExt.adslAtucThreshold15MinFailedFastR!=0 && current_intvl->AtucPerfStatFailedFastR>=AlarmConfProfileExt.adslAtucThreshold15MinFailedFastR)
- trapsflag|=ATUC_15MIN_FAILED_FASTR_TRAP_FLAG;
- if(AlarmConfProfileExt.adslAtucThreshold15MinSesL!=0 && current_intvl->AtucPerfStatSesL>=AlarmConfProfileExt.adslAtucThreshold15MinSesL)
- trapsflag|=ATUC_15MIN_SESL_TRAP_FLAG;
- if(AlarmConfProfileExt.adslAtucThreshold15MinUasL!=0 && current_intvl->AtucPerfStatUasL>=AlarmConfProfileExt.adslAtucThreshold15MinUasL)
- trapsflag|=ATUC_15MIN_UASL_TRAP_FLAG;
- if(AlarmConfProfileExt.adslAturThreshold15MinSesL!=0 && current_intvl->AturPerfStatSesL>=AlarmConfProfileExt.adslAturThreshold15MinSesL)
- trapsflag|=ATUR_15MIN_SESL_TRAP_FLAG;
- if(AlarmConfProfileExt.adslAturThreshold15MinUasL!=0 && current_intvl->AturPerfStatUasL>=AlarmConfProfileExt.adslAturThreshold15MinUasL)
- trapsflag|=ATUR_15MIN_UASL_TRAP_FLAG;
- copy_to_user((char *)lon, (char *)(&trapsflag), 2);
- break;
-#endif
-
-// 603221:tc.chen start
- case GET_ADSL_LINE_STATUS:
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- pts.adslLineStatusInfo_pt = (adslLineStatusInfo *)kmalloc(sizeof(adslLineStatusInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslLineStatusInfo_pt, (char *)lon, sizeof(adslLineStatusInfo));
-
- if(IS_FLAG_SET((&(pts.adslLineStatusInfo_pt->flags)), LINE_STAT_MODEM_STATUS_FLAG)){
- LINE_STAT_MODEM_STATUS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group STAT Address 0 Index 0");
-#endif
- pts.adslLineStatusInfo_pt->adslModemStatus = 0;
- }
- else{
- pts.adslLineStatusInfo_pt->adslModemStatus = RxMessage[4];
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineStatusInfo_pt->flags)), LINE_STAT_MODE_SEL_FLAG)){
- LINE_STAT_MODE_SEL_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group STAT Address 1 Index 0");
-#endif
- pts.adslLineStatusInfo_pt->adslModeSelected = 0;
- }
- else{
- pts.adslLineStatusInfo_pt->adslModeSelected = RxMessage[4];
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineStatusInfo_pt->flags)), LINE_STAT_TRELLCOD_ENABLE_FLAG)){
- LINE_STAT_TRELLCOD_ENABLE_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group OPTN Address 2 Index 0");
-#endif
- pts.adslLineStatusInfo_pt->adslTrellisCodeEnable = 0;
- }
- else{
-
- pts.adslLineStatusInfo_pt->adslTrellisCodeEnable = (RxMessage[4]>>13)&0x1==0x1?0:1;
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineStatusInfo_pt->flags)), LINE_STAT_LATENCY_FLAG)){
- LINE_STAT_LATENCY_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group STAT Address 12 Index 0");
-#endif
- pts.adslLineStatusInfo_pt->adslLatency = 0;
- }
- else{
- pts.adslLineStatusInfo_pt->adslLatency = RxMessage[4];
- }
- }
-
- copy_to_user((char *)lon, (char *)pts.adslLineStatusInfo_pt, sizeof(adslLineStatusInfo));
- kfree(pts.adslLineStatusInfo_pt);
-
- up(&mei_sema);
- break;
-
-
- case GET_ADSL_LINE_RATE:
- if (showtime!=1)
- return -ERESTARTSYS;
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- pts.adslLineRateInfo_pt = (adslLineRateInfo *)kmalloc(sizeof(adslLineRateInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslLineRateInfo_pt, (char *)lon, sizeof(adslLineRateInfo));
-
- if(IS_FLAG_SET((&(pts.adslLineRateInfo_pt->flags)), LINE_RATE_DATA_RATEDS_FLAG)){
- if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode
- {
- if (chantype.interleave)
- LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP0_MAKECMV;
- else
- LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP1_MAKECMV;
-
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group RATE Address 1 Index 0");
-#endif
- pts.adslLineRateInfo_pt->adslDataRateds = 0;
- }
- else{
- pts.adslLineRateInfo_pt->adslDataRateds = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- }
- }else // adsl 2/2+
- {
- unsigned long Mp,Lp,Tp,Rp,Kp,Bpn,DataRate,DataRate_remain;
- Mp=Lp=Tp=Rp=Kp=Bpn=DataRate=DataRate_remain=0;
- //// up stream data rate
-
- if (chantype.interleave)
- {
- LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP0_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 25 Index 0");
-#endif
- Lp = 0;
- }else
- Lp=RxMessage[4];
-
- LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP0_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 23 Index 0");
-#endif
- Rp = 0;
- }else
- Rp=RxMessage[4];
-
- LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP0_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 24 Index 0");
-#endif
- Mp = 0;
- }else
- Mp=RxMessage[4];
-
- LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP0_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 26 Index 0");
-#endif
- Tp = 0;
- }else
- Tp=RxMessage[4];
-
- LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP0_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 28 Index 0");
-#endif
- Kp = 0;
- }else
- {
- Kp=RxMessage[4]+ RxMessage[5]+1;
- Bpn=RxMessage[4]+ RxMessage[5];
- }
- }else
- {
- LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP1_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 25 Index 1");
-#endif
- Lp = 0;
- }else
- Lp=RxMessage[4];
-
- LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP1_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 23 Index 1");
-#endif
- Rp = 0;
- }else
- Rp=RxMessage[4];
-
- LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP1_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 24 Index 1");
-#endif
- Mp = 0;
- }else
- Mp=RxMessage[4];
-
- LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP1_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 26 Index 1");
-#endif
- Tp = 0;
- }else
- Tp=RxMessage[4];
-
- LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP1_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 28 Index 2");
-#endif
- Kp = 0;
- }else
- {
- Kp=RxMessage[4]+ RxMessage[5]+1;
- Bpn=RxMessage[4]+ RxMessage[5];
- }
- }
- DataRate=((Tp*(Bpn+1)-1)*Mp*Lp*4)/(Tp*(Kp*Mp+Rp));
- //DataRate_remain=((((Tp*(Bpn+1)-1)*Mp*Lp*4)%(Tp*(Kp*Mp+Rp)))*1000)/(Tp*(Kp*Mp+Rp));
- //pts.adslLineRateInfo_pt->adslDataRateds = DataRate * 1000 + DataRate_remain;
- pts.adslLineRateInfo_pt->adslDataRateds = DataRate;
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineRateInfo_pt->flags)), LINE_RATE_DATA_RATEUS_FLAG)){
- if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode
- {
- if (chantype.interleave)
- LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP0_MAKECMV;
- else
- LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP1_MAKECMV;
-
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
- #ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group RATE Address 0 Index 0");
- #endif
- pts.adslLineRateInfo_pt->adslDataRateus = 0;
- }
- else{
- pts.adslLineRateInfo_pt->adslDataRateus = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- }
- }else // adsl 2/2+
- {
- unsigned long Mp,Lp,Tp,Rp,Kp,Bpn,DataRate,DataRate_remain;
- Mp=Lp=Tp=Rp=Kp=Bpn=DataRate=DataRate_remain=0;
- //// down stream data rate
-
- if (chantype.interleave)
- {
- LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP0_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 14 Index 0");
-#endif
- Lp = 0;
- }else
- Lp=RxMessage[4];
-
- LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP0_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 12 Index 0");
-#endif
- Rp = 0;
- }else
- Rp=RxMessage[4];
-
- LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP0_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 13 Index 0");
-#endif
- Mp = 0;
- }else
- Mp=RxMessage[4];
-
- LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP0_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 15 Index 0");
-#endif
- Tp = 0;
- }else
- Tp=RxMessage[4];
-
- LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP0_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 17 Index 0");
-#endif
- Kp = 0;
- }else
- {
- Kp=RxMessage[4]+ RxMessage[5]+1;
- Bpn=RxMessage[4]+ RxMessage[5];
- }
- }else
- {
- LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP1_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 14 Index 1");
-#endif
- Lp = 0;
- }else
- Lp=RxMessage[4];
-
- LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP1_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 12 Index 1");
-#endif
- Rp = 0;
- }else
- Rp=RxMessage[4];
-
- LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP1_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 13 Index 1");
-#endif
- Mp = 0;
- }else
- Mp=RxMessage[4];
-
- LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP1_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 15 Index 1");
-#endif
- Tp = 0;
- }else
- Tp=RxMessage[4];
-
- LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP1_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 17 Index 2");
-#endif
- Kp = 0;
- }else
- {
- Kp=RxMessage[4]+ RxMessage[5]+1;
- Bpn=RxMessage[4]+ RxMessage[5];
- }
- }
- DataRate=((Tp*(Bpn+1)-1)*Mp*Lp*4)/(Tp*(Kp*Mp+Rp));
- //DataRate_remain=((((Tp*(Bpn+1)-1)*Mp*Lp*4)%(Tp*(Kp*Mp+Rp)))*1000)/(Tp*(Kp*Mp+Rp));
- //pts.adslLineRateInfo_pt->adslDataRateus = DataRate * 1000 + DataRate_remain;
- pts.adslLineRateInfo_pt->adslDataRateus = DataRate;
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineRateInfo_pt->flags)), LINE_RATE_ATTNDRDS_FLAG)){
- LINE_RATE_ATTNDRDS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 68 Index 4");
-#endif
- pts.adslLineRateInfo_pt->adslATTNDRds = 0;
- }
- else{
- pts.adslLineRateInfo_pt->adslATTNDRds = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineRateInfo_pt->flags)), LINE_RATE_ATTNDRUS_FLAG)){
- if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode
- {
- LINE_RATE_ATTNDRUS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
- #ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 69 Index 4");
- #endif
- pts.adslLineRateInfo_pt->adslATTNDRus = 0;
- }
- else{
- pts.adslLineRateInfo_pt->adslATTNDRus = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- }
- }else
- {
- hdlc_cmd[0]=0x0181;
- hdlc_cmd[1]=0x24;
- up(&mei_sema);
- if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY)
- {
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(1);
- hdlc_rx_len=0;
- hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2);
- if (hdlc_rx_len <=0)
- {
- meierr = -ERESTARTSYS;
- goto GET_ADSL_LINE_RATE_END;
- }
- pts.adslLineRateInfo_pt->adslATTNDRus = (u32)le16_to_cpu(hdlc_rx_buffer[1])<<16 | (u32)le16_to_cpu(hdlc_rx_buffer[2]);
- }
- if(down_interruptible(&mei_sema))
- {
- meierr = -ERESTARTSYS;
- goto GET_ADSL_LINE_RATE_END;
- }
- }
- }
- copy_to_user((char *)lon, (char *)pts.adslLineRateInfo_pt, sizeof(adslLineRateInfo));
- up(&mei_sema);
-
-GET_ADSL_LINE_RATE_END:
- kfree(pts.adslLineRateInfo_pt);
- break;
-
- case GET_ADSL_LINE_INFO:
- if (showtime!=1)
- return -ERESTARTSYS;
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- pts.adslLineInfo_pt = (adslLineInfo *)kmalloc(sizeof(adslLineInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslLineInfo_pt, (char *)lon, sizeof(adslLineInfo));
-
- if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_INTLV_DEPTHDS_FLAG)){
- if (chantype.interleave)
- LINE_INFO_INTLV_DEPTHDS_FLAG_LP0_MAKECMV;
- else
- LINE_INFO_INTLV_DEPTHDS_FLAG_LP1_MAKECMV;
-
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 27 Index 0");
-#endif
- pts.adslLineInfo_pt->adslInterleaveDepthds = 0;
- }
- else{
- pts.adslLineInfo_pt->adslInterleaveDepthds = RxMessage[4];
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_INTLV_DEPTHUS_FLAG)){
- if (chantype.interleave)
- LINE_INFO_INTLV_DEPTHUS_FLAG_LP0_MAKECMV;
- else
- LINE_INFO_INTLV_DEPTHUS_FLAG_LP1_MAKECMV;
-
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group CNFG Address 16 Index 0");
-#endif
- pts.adslLineInfo_pt->adslInterleaveDepthus = 0;
- }
- else{
- pts.adslLineInfo_pt->adslInterleaveDepthus = RxMessage[4];
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_LATNDS_FLAG)){
- LINE_INFO_LATNDS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 68 Index 1");
-#endif
- pts.adslLineInfo_pt->adslLATNds = 0;
- }
- else{
- pts.adslLineInfo_pt->adslLATNds = RxMessage[4];
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_LATNUS_FLAG)){
- if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode
- {
- LINE_INFO_LATNUS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 69 Index 1");
-#endif
- pts.adslLineInfo_pt->adslLATNus = 0;
- }
- else{
- pts.adslLineInfo_pt->adslLATNus = RxMessage[4];
- }
- }else
- {
- hdlc_cmd[0]=0x0181;
- hdlc_cmd[1]=0x21;
- up(&mei_sema);
- if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY)
- {
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(1);
- hdlc_rx_len=0;
- hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2);
- if (hdlc_rx_len <=0)
- {
- meierr = -ERESTARTSYS;
- goto GET_ADSL_LINE_INFO_END;
- }
- pts.adslLineInfo_pt->adslLATNus = le16_to_cpu(hdlc_rx_buffer[1]);
- }
- if(down_interruptible(&mei_sema))
- {
- meierr = -ERESTARTSYS;
- goto GET_ADSL_LINE_INFO_END;
- }
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_SATNDS_FLAG)){
- LINE_INFO_SATNDS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 68 Index 2");
-#endif
- pts.adslLineInfo_pt->adslSATNds = 0;
- }
- else{
- pts.adslLineInfo_pt->adslSATNds = RxMessage[4];
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_SATNUS_FLAG)){
- if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode
- {
- LINE_INFO_SATNUS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 69 Index 2");
-#endif
- pts.adslLineInfo_pt->adslSATNus = 0;
- }
- else{
- pts.adslLineInfo_pt->adslSATNus = RxMessage[4];
- }
- }else
- {
- hdlc_cmd[0]=0x0181;
- hdlc_cmd[1]=0x22;
- up(&mei_sema);
- if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY)
- {
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(1);
- hdlc_rx_len=0;
- hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2);
- if (hdlc_rx_len <=0)
- {
- meierr = -ERESTARTSYS;
- goto GET_ADSL_LINE_INFO_END;
- }
- pts.adslLineInfo_pt->adslSATNus = le16_to_cpu(hdlc_rx_buffer[1]);
- }
- if(down_interruptible(&mei_sema))
- {
- meierr = -ERESTARTSYS;
- goto GET_ADSL_LINE_INFO_END;
- }
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_SNRMNDS_FLAG)){
- if (adsl_mode <=8 && adsl_mode_extend==0) // adsl mode
- {
- LINE_INFO_SNRMNDS_FLAG_ADSL1_MAKECMV;
- }
- else if ((adsl_mode == 0x4000) || (adsl_mode == 0x8000) || adsl_mode_extend > 0)
- {
- LINE_INFO_SNRMNDS_FLAG_ADSL2PLUS_MAKECMV;
- }
- else
- {
- LINE_INFO_SNRMNDS_FLAG_ADSL2_MAKECMV;
- }
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 68 Index 3");
-#endif
- pts.adslLineInfo_pt->adslSNRMds = 0;
- }
- else{
- if (adsl_mode>8 || adsl_mode_extend>0)
- {
- int SNRMds,SNRMds_remain;
- SNRMds=RxMessage[4];
- SNRMds_remain=((SNRMds&0xff)*1000)/256;
- SNRMds=(SNRMds>>8)&0xff;
- if ((SNRMds_remain%100)>=50) SNRMds_remain=(SNRMds_remain/100)+1;
- else SNRMds_remain=(SNRMds_remain/100);
- pts.adslLineInfo_pt->adslSNRMds = SNRMds*10 + SNRMds_remain;
- }else
- {
- pts.adslLineInfo_pt->adslSNRMds = RxMessage[4];
- }
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_SNRMNUS_FLAG)){
- if (adsl_mode <=8 && adsl_mode_extend == 0)
- {
- LINE_INFO_SNRMNUS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 69 Index 3");
-#endif
- pts.adslLineInfo_pt->adslSNRMus = 0;
- }
- else{
- pts.adslLineInfo_pt->adslSNRMus = RxMessage[4];
- }
- }else
- {
- hdlc_cmd[0]=0x0181;
- hdlc_cmd[1]=0x23;
- up(&mei_sema);
- if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY)
- {
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(1);
- hdlc_rx_len=0;
- hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2);
- if (hdlc_rx_len <=0)
- {
- meierr = -ERESTARTSYS;
- goto GET_ADSL_LINE_INFO_END;
- }
- pts.adslLineInfo_pt->adslSNRMus = le16_to_cpu(hdlc_rx_buffer[1]);
- }
- if(down_interruptible(&mei_sema))
- {
- meierr = -ERESTARTSYS;
- goto GET_ADSL_LINE_INFO_END;
- }
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_ACATPDS_FLAG)){
- if (adsl_mode <=8 && adsl_mode_extend == 0)
- {
- LINE_INFO_ACATPDS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
- #ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 68 Index 6");
- #endif
- pts.adslLineInfo_pt->adslACATPds = 0;
- }
- else{
- pts.adslLineInfo_pt->adslACATPds = RxMessage[4];
- }
- }else
- {
- hdlc_cmd[0]=0x0181;
- hdlc_cmd[1]=0x25;
- up(&mei_sema);
- if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY)
- {
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(1);
- hdlc_rx_len=0;
- hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2);
- if (hdlc_rx_len <=0)
- {
- meierr = -ERESTARTSYS;
- goto GET_ADSL_LINE_INFO_END;
- }
- pts.adslLineInfo_pt->adslACATPds = le16_to_cpu(hdlc_rx_buffer[1]);
- }
- if(down_interruptible(&mei_sema))
- {
- meierr = -ERESTARTSYS;
- goto GET_ADSL_LINE_INFO_END;
- }
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslLineInfo_pt->flags)), LINE_INFO_ACATPUS_FLAG)){
- if (adsl_mode <=8 && adsl_mode_extend == 0)
- {
- LINE_INFO_ACATPUS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 69 Index 6");
-#endif
- pts.adslLineInfo_pt->adslACATPus = 0;
- }
- else{
- pts.adslLineInfo_pt->adslACATPus = RxMessage[4];
- }
- }else
- {
- hdlc_cmd[0]=0x0181;
- hdlc_cmd[1]=0x26;
- up(&mei_sema);
- if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],4)!= -EBUSY)
- {
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(1);
- hdlc_rx_len=0;
- hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2);
- if (hdlc_rx_len <=0)
- {
- meierr = -ERESTARTSYS;
- goto GET_ADSL_LINE_INFO_END;
- }
- pts.adslLineInfo_pt->adslACATPus = le16_to_cpu(hdlc_rx_buffer[1]);
- }
- if(down_interruptible(&mei_sema))
- {
- meierr = -ERESTARTSYS;
- goto GET_ADSL_LINE_INFO_END;
- }
- }
- }
-
- copy_to_user((char *)lon, (char *)pts.adslLineInfo_pt, sizeof(adslLineInfo));
- up(&mei_sema);
-
-GET_ADSL_LINE_INFO_END:
- kfree(pts.adslLineInfo_pt);
- break;
-
- case GET_ADSL_NEAREND_STATS:
- if (showtime!=1)
- return -ERESTARTSYS;
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- pts.adslNearEndPerfStats_pt = (adslNearEndPerfStats *)kmalloc(sizeof(adslNearEndPerfStats), GFP_KERNEL);
- copy_from_user((char *)pts.adslNearEndPerfStats_pt, (char *)lon, sizeof(adslNearEndPerfStats));
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_SUPERFRAME_FLAG)){
- NEAREND_PERF_SUPERFRAME_FLAG_LSW_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 20 Index 0");
-#endif
- pts.adslNearEndPerfStats_pt->adslSuperFrames = 0;
- }
- else{
- pts.adslNearEndPerfStats_pt->adslSuperFrames = (u32)(RxMessage[4]);
- }
- NEAREND_PERF_SUPERFRAME_FLAG_MSW_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 21 Index 0");
-#endif
- pts.adslNearEndPerfStats_pt->adslSuperFrames = 0;
- }
- else{
- pts.adslNearEndPerfStats_pt->adslSuperFrames += (((u32)(RxMessage[4]))<<16);
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOS_FLAG) ||
- IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOF_FLAG) ||
- IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LPR_FLAG) ||
- IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_NCD_FLAG) ||
- IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LCD_FLAG) ){
- NEAREND_PERF_LOS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 0 Index 0");
-#endif
- RxMessage[4] = 0;
- }
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOS_FLAG)){
- if( (RxMessage[4]&0x1) == 0x1)
- pts.adslNearEndPerfStats_pt->adslneLOS = 1;
- else
- pts.adslNearEndPerfStats_pt->adslneLOS = 0;
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOF_FLAG)){
- if( (RxMessage[4]&0x2) == 0x2)
- pts.adslNearEndPerfStats_pt->adslneLOF = 1;
- else
- pts.adslNearEndPerfStats_pt->adslneLOF = 0;
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LPR_FLAG)){
- if( (RxMessage[4]&0x4) == 0x4)
- pts.adslNearEndPerfStats_pt->adslneLPR = 1;
- else
- pts.adslNearEndPerfStats_pt->adslneLPR = 0;
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_NCD_FLAG)){
- pts.adslNearEndPerfStats_pt->adslneNCD = (RxMessage[4]>>4)&0x3;
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LCD_FLAG)){
- pts.adslNearEndPerfStats_pt->adslneLCD = (RxMessage[4]>>6)&0x3;
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_CRC_FLAG)){
- if (chantype.interleave)
- NEAREND_PERF_CRC_FLAG_LP0_MAKECMV;
- else
- NEAREND_PERF_CRC_FLAG_LP1_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 2 Index 0");
-#endif
- pts.adslNearEndPerfStats_pt->adslneCRC = 0;
- }
- else{
- pts.adslNearEndPerfStats_pt->adslneCRC = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_RSCORR_FLAG)){
- if (chantype.interleave)
- NEAREND_PERF_RSCORR_FLAG_LP0_MAKECMV;
- else
- NEAREND_PERF_RSCORR_FLAG_LP1_MAKECMV;
-
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 3 Index 0");
-#endif
- pts.adslNearEndPerfStats_pt->adslneRSCorr = 0;
- }
- else{
- pts.adslNearEndPerfStats_pt->adslneRSCorr = RxMessage[4];
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_FECS_FLAG)){
- NEAREND_PERF_FECS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 6 Index 0");
-#endif
- pts.adslNearEndPerfStats_pt->adslneFECS = 0;
- }
- else{
- pts.adslNearEndPerfStats_pt->adslneFECS = RxMessage[4];
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_ES_FLAG)){
- NEAREND_PERF_ES_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 7 Index 0");
-#endif
- pts.adslNearEndPerfStats_pt->adslneES = 0;
- }
- else{
- pts.adslNearEndPerfStats_pt->adslneES = RxMessage[4];
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_SES_FLAG)){
- NEAREND_PERF_SES_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 8 Index 0");
-#endif
- pts.adslNearEndPerfStats_pt->adslneSES = 0;
- }
- else{
- pts.adslNearEndPerfStats_pt->adslneSES = RxMessage[4];
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_LOSS_FLAG)){
- NEAREND_PERF_LOSS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 9 Index 0");
-#endif
- pts.adslNearEndPerfStats_pt->adslneLOSS = 0;
- }
- else{
- pts.adslNearEndPerfStats_pt->adslneLOSS = RxMessage[4];
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_UAS_FLAG)){
- NEAREND_PERF_UAS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 10 Index 0");
-#endif
- pts.adslNearEndPerfStats_pt->adslneUAS = 0;
- }
- else{
- pts.adslNearEndPerfStats_pt->adslneUAS = RxMessage[4];
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslNearEndPerfStats_pt->flags)), NEAREND_PERF_HECERR_FLAG)){
- if (chantype.bearchannel0)
- {
- NEAREND_PERF_HECERR_FLAG_BC0_MAKECMV;
- }else if (chantype.bearchannel1)
- {
- NEAREND_PERF_HECERR_FLAG_BC1_MAKECMV;
- }
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 11 Index 0");
-#endif
- pts.adslNearEndPerfStats_pt->adslneHECErrors = 0;
- }
- else{
- pts.adslNearEndPerfStats_pt->adslneHECErrors = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- }
- }
-
- copy_to_user((char *)lon, (char *)pts.adslNearEndPerfStats_pt, sizeof(adslNearEndPerfStats));
- kfree(pts.adslNearEndPerfStats_pt);
-
- up(&mei_sema);
- break;
-
- case GET_ADSL_FAREND_STATS:
-
- if (showtime!=1)
- return -ERESTARTSYS;
-
- if (adsl_mode>8 || adsl_mode_extend > 0)
- {
- do_gettimeofday(&time_now);
- if( FarendData_acquire_time.tv_sec==0 || time_now.tv_sec - FarendData_acquire_time.tv_sec>=1)
- {
- hdlc_cmd[0]=0x105;
-
- if (ifx_me_hdlc_send((unsigned char *)&hdlc_cmd[0],2)!= -EBUSY)
- {
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(1);
- hdlc_rx_len=0;
- hdlc_rx_len = ifx_mei_hdlc_read(&hdlc_rx_buffer,32*2);
- if (hdlc_rx_len <=0)
- {
- return -ERESTARTSYS;
- }
- FarendStatsData.adslfeRSCorr = ((u32)le16_to_cpu(hdlc_rx_buffer[1]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[2]);
- FarendStatsData.adslfeCRC = ((u32)le16_to_cpu(hdlc_rx_buffer[3]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[4]);
- FarendStatsData.adslfeFECS = ((u32)le16_to_cpu(hdlc_rx_buffer[5]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[6]);
- FarendStatsData.adslfeES = ((u32)le16_to_cpu(hdlc_rx_buffer[7]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[8]);
- FarendStatsData.adslfeSES = ((u32)le16_to_cpu(hdlc_rx_buffer[9]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[10]);
- FarendStatsData.adslfeLOSS = ((u32)le16_to_cpu(hdlc_rx_buffer[11]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[12]);
- FarendStatsData.adslfeUAS = ((u32)le16_to_cpu(hdlc_rx_buffer[13]) << 16) + (u32)le16_to_cpu(hdlc_rx_buffer[14]);
- do_gettimeofday(&FarendData_acquire_time);
- }
-
- }
- }
-
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
- pts.adslFarEndPerfStats_pt = (adslFarEndPerfStats *)kmalloc(sizeof(adslFarEndPerfStats), GFP_KERNEL);
- copy_from_user((char *)pts.adslFarEndPerfStats_pt, (char *)lon, sizeof(adslFarEndPerfStats));
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOS_FLAG) ||
- IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOF_FLAG) ||
- IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LPR_FLAG) ||
- IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_NCD_FLAG) ||
- IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LCD_FLAG) ){
- FAREND_PERF_LOS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 1 Index 0");
-#endif
- RxMessage[4] = 0;
- }
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOS_FLAG)){
- if((RxMessage[4]&0x1) == 0x1)
- pts.adslFarEndPerfStats_pt->adslfeLOS = 1;
- else
- pts.adslFarEndPerfStats_pt->adslfeLOS = 0;
- }
-
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOF_FLAG)){
- if((RxMessage[4]&0x2) == 0x2)
- pts.adslFarEndPerfStats_pt->adslfeLOF = 1;
- else
- pts.adslFarEndPerfStats_pt->adslfeLOF = 0;
- }
-
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LPR_FLAG)){
- if((RxMessage[4]&0x4) == 0x4)
- pts.adslFarEndPerfStats_pt->adslfeLPR = 1;
- else
- pts.adslFarEndPerfStats_pt->adslfeLPR = 0;
- }
-
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_NCD_FLAG)){
- pts.adslFarEndPerfStats_pt->adslfeNCD = (RxMessage[4]>>4)&0x3;
- }
-
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LCD_FLAG)){
- pts.adslFarEndPerfStats_pt->adslfeLCD = (RxMessage[4]>>6)&0x3;
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_CRC_FLAG)){
- if (adsl_mode<=8 && adsl_mode_extend == 0)
- {
- if (chantype.interleave)
- {
- FAREND_PERF_CRC_FLAG_LP0_MAKECMV;
- }
- else
- {
- FAREND_PERF_CRC_FLAG_LP1_MAKECMV;
- }
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 24 Index 0");
-#endif
- pts.adslFarEndPerfStats_pt->adslfeCRC = 0;
- }
- else{
- pts.adslFarEndPerfStats_pt->adslfeCRC = RxMessage[4];
- }
- }else
- {
- pts.adslFarEndPerfStats_pt->adslfeCRC = FarendStatsData.adslfeCRC;
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_RSCORR_FLAG)){
- if (adsl_mode<=8 && adsl_mode_extend == 0)
- {
- if (chantype.interleave)
- FAREND_PERF_RSCORR_FLAG_LP0_MAKECMV;
- else
- FAREND_PERF_RSCORR_FLAG_LP1_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 28 Index 0");
-#endif
- pts.adslFarEndPerfStats_pt->adslfeRSCorr = 0;
- }
- else{
- pts.adslFarEndPerfStats_pt->adslfeRSCorr = RxMessage[4];
-
- }
- }
- else
- {
- pts.adslFarEndPerfStats_pt->adslfeRSCorr = FarendStatsData.adslfeRSCorr;
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_FECS_FLAG)){
- if (adsl_mode<=8 && adsl_mode_extend == 0)
- {
- FAREND_PERF_FECS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 32 Index 0");
-#endif
- pts.adslFarEndPerfStats_pt->adslfeFECS = 0;
- }
- else{
- pts.adslFarEndPerfStats_pt->adslfeFECS = RxMessage[4];
- }
- }else {
- pts.adslFarEndPerfStats_pt->adslfeFECS = FarendStatsData.adslfeFECS;
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_ES_FLAG)){
- if (adsl_mode<=8 && adsl_mode_extend == 0)
- {
- FAREND_PERF_ES_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 33 Index 0");
-#endif
- pts.adslFarEndPerfStats_pt->adslfeES = 0;
- }
- else{
- pts.adslFarEndPerfStats_pt->adslfeES = RxMessage[4];
- }
- }else
- {
- pts.adslFarEndPerfStats_pt->adslfeES = FarendStatsData.adslfeES;
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_SES_FLAG)){
- if (adsl_mode<=8 && adsl_mode_extend == 0)
- {
- FAREND_PERF_SES_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 34 Index 0");
-#endif
- pts.adslFarEndPerfStats_pt->adslfeSES = 0;
- }
- else{
- pts.adslFarEndPerfStats_pt->adslfeSES = RxMessage[4];
-
- }
- }else
- {
- pts.adslFarEndPerfStats_pt->adslfeSES = FarendStatsData.adslfeSES;
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_LOSS_FLAG)){
- if (adsl_mode<=8 && adsl_mode_extend == 0)
- {
- FAREND_PERF_LOSS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- pts.adslFarEndPerfStats_pt->adslfeLOSS = 0;
- }
- else{
- pts.adslFarEndPerfStats_pt->adslfeLOSS = RxMessage[4];
-
- }
- }else
- {
- pts.adslFarEndPerfStats_pt->adslfeLOSS = FarendStatsData.adslfeLOSS;
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_UAS_FLAG)){
- if (adsl_mode<=8 && adsl_mode_extend == 0)
- {
- FAREND_PERF_UAS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 36 Index 0");
-#endif
- pts.adslFarEndPerfStats_pt->adslfeUAS = 0;
- }
- else{
- pts.adslFarEndPerfStats_pt->adslfeUAS = RxMessage[4];
-
- }
- }else
- {
- pts.adslFarEndPerfStats_pt->adslfeUAS = FarendStatsData.adslfeUAS;
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslFarEndPerfStats_pt->flags)), FAREND_PERF_HECERR_FLAG)){
- if (chantype.bearchannel0)
- {
- FAREND_PERF_HECERR_FLAG_BC0_MAKECMV;
- }else if (chantype.bearchannel1)
- {
- FAREND_PERF_HECERR_FLAG_BC1_MAKECMV;
- }
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 37 Index 0");
-#endif
- pts.adslFarEndPerfStats_pt->adslfeHECErrors = 0;
- }
- else{
- pts.adslFarEndPerfStats_pt->adslfeHECErrors = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- }
- }
-
- copy_to_user((char *)lon, (char *)pts.adslFarEndPerfStats_pt, sizeof(adslFarEndPerfStats));
- kfree(pts.adslFarEndPerfStats_pt);
-
- up(&mei_sema);
-
- break;
-// 603221:tc.chen end
- case GET_ADSL_LOOP_DIAGNOSTICS_MODE:
- //lon = loop_diagnostics_mode;
- copy_to_user((char *)lon, (char *)&loop_diagnostics_mode, sizeof(int));
- break;
-//>> SHC
- case IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE:
- copy_to_user((char *)lon, (char *)&loop_diagnostics_completed, sizeof(int));
- break;
-
-//<< end SHC
- case LOOP_DIAGNOSTIC_MODE_COMPLETE:
- loop_diagnostics_completed = 1;
- // read adsl mode
- makeCMV(H2D_CMV_READ, STAT, 1, 0, 1, data);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group STAT Address 1 Index 0");
-#endif
- }
- adsl_mode = RxMessage[4];
-
- makeCMV(H2D_CMV_READ, STAT, 17, 0, 1, data);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group STAT Address 1 Index 0");
-#endif
- }
- adsl_mode_extend = RxMessage[4];
- wake_up_interruptible(&wait_queue_loop_diagnostic);
- break;
- case SET_ADSL_LOOP_DIAGNOSTICS_MODE:
- if (lon != loop_diagnostics_mode)
- {
- loop_diagnostics_completed = 0;
- loop_diagnostics_mode = lon;
-
- mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_REBOOT, NULL);
-
- }
- break;
- case GET_ADSL_ATUR_SUBCARRIER_STATS:
- if (loop_diagnostics_completed == 0)
- {
- interruptible_sleep_on_timeout(&wait_queue_loop_diagnostic,300*HZ);
- if (loop_diagnostics_completed==0)
- {
- return -ERESTARTSYS;
- }
- }
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- pts.adslATURSubcarrierInfo_pt = (adslATURSubcarrierInfo *)kmalloc(sizeof(adslATURSubcarrierInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslATURSubcarrierInfo_pt, (char *)lon, sizeof(adslATURSubcarrierInfo));
-
- if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_HLINSC)){
- FAREND_HLINSC_MAKECMV(H2D_CMV_READ);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- pts.adslATURSubcarrierInfo_pt->HLINSCds = 0;
- }
- else{
- pts.adslATURSubcarrierInfo_pt->HLINSCds = RxMessage[4];
-
- }
- }
- if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_HLINPS)){
- int index=0,size=12;
- //printk("FAREND_HLINPS\n");
- for (index=0;index<1024;index+=size)
- {
- if (index+size>=1024)
- size = 1024-index;
- FAREND_HLINPS_MAKECMV(H2D_CMV_READ,index,size);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- }
- else{
- memcpy(&pts.adslATURSubcarrierInfo_pt->HLINpsds[index],&RxMessage[4],size*2);
-#if 0
- int msg_idx;
- for(msg_idx=0;msg_idx<size;msg_idx++)
- printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]);
-#endif
- }
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_HLOGMT)){
- FAREND_HLOGMT_MAKECMV(H2D_CMV_READ);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- pts.adslATURSubcarrierInfo_pt->HLOGMTds = 0;
- }
- else{
- pts.adslATURSubcarrierInfo_pt->HLOGMTds = RxMessage[4];
-
- }
- }
-
- /////////////////////////////////////////////////////////////////////////
- if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_HLOGPS)){
- //printk("FAREND_HLOGPS\n");
- int index=0,size=12;
- for (index=0;index<256;index+=size)
- {
- if (index+size>=256)
- size = 256-index;
-
- FAREND_HLOGPS_MAKECMV(H2D_CMV_READ,index,size);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- }
- else{
- if (adsl_mode < 0x4000 && adsl_mode_extend==0)//adsl2 mode
- {
- memcpy(&pts.adslATURSubcarrierInfo_pt->HLOGpsds[index],&RxMessage[4],size*2);
- }else
- {
- int msg_idx=0;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
- pts.adslATURSubcarrierInfo_pt->HLOGpsds[(index+msg_idx)*2+1] = RxMessage[4+msg_idx];
- //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]);
- }
- }
- }
- }
- if (adsl_mode >= 0x4000 || adsl_mode_extend >0)//adsl2+ mode
- {
- pts.adslATURSubcarrierInfo_pt->HLOGpsds[0] = pts.adslATURSubcarrierInfo_pt->HLOGpsds[1];
- for (index=1;index<256;index++)
- {
- pts.adslATURSubcarrierInfo_pt->HLOGpsds[index*2] = (pts.adslATURSubcarrierInfo_pt->HLOGpsds[(index)*2-1] + pts.adslATURSubcarrierInfo_pt->HLOGpsds[(index)*2+1] +1) >>1;
- }
- }
- }
- if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_QLNMT)){
- FAREND_QLNMT_MAKECMV(H2D_CMV_READ);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- pts.adslATURSubcarrierInfo_pt->QLNMTds = 0;
- }
- else{
- pts.adslATURSubcarrierInfo_pt->QLNMTds = RxMessage[4];
- }
- }
-
- /////////////////////////////////////////////////////////////////////////
- if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_QLNPS)){
- int index=0,size=12;
- //printk("FAREND_QLNPS\n");
- for (index=0;index<128;index+=size)
- {
- if (index+size>=128)
- size = 128-index;
- FAREND_QLNPS_MAKECMV(H2D_CMV_READ,index,size);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- }
- else{
- int msg_idx=0;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
- //memcpy(&pts.adslATURSubcarrierInfo_pt->QLNpsds[index],&RxMessage[4],size*2);
- if (adsl_mode < 0x4000 && adsl_mode_extend==0)//adsl2 mode
- {
- pts.adslATURSubcarrierInfo_pt->QLNpsds[(index+msg_idx)*2] = (u16)(RxMessage[4+msg_idx]&0xFF);
- pts.adslATURSubcarrierInfo_pt->QLNpsds[(index+msg_idx)*2+1] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF);
- }else
- {
- pts.adslATURSubcarrierInfo_pt->QLNpsds[(index+msg_idx)*4+1] = (u16)(RxMessage[4+msg_idx]&0xFF);
- pts.adslATURSubcarrierInfo_pt->QLNpsds[(index+msg_idx)*4+3] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF);
- //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]);
- }
- }
-
-
- }
- }
- if (adsl_mode >= 0x4000 || adsl_mode_extend >0)//adsl2+ mode
- {
- pts.adslATURSubcarrierInfo_pt->QLNpsds[0] = pts.adslATURSubcarrierInfo_pt->QLNpsds[1];
- for (index=1;index<256;index++)
- {
- pts.adslATURSubcarrierInfo_pt->QLNpsds[index*2] = (pts.adslATURSubcarrierInfo_pt->QLNpsds[(index)*2-1] + pts.adslATURSubcarrierInfo_pt->QLNpsds[(index)*2+1]) >>1;
- }
- }
- }
- if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_SNRMT)){
- FAREND_SNRMT_MAKECMV(H2D_CMV_READ);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- pts.adslATURSubcarrierInfo_pt->SNRMTds = 0;
- }
- else{
- pts.adslATURSubcarrierInfo_pt->SNRMTds = RxMessage[4];
- }
- }
- if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_SNRPS)){
- int index=0,size=12;
- //printk("FAREND_SNRPS\n");
- for (index=0;index<512;index+=size)
- {
- if (index+size>=512)
- size = 512-index;
- FAREND_SNRPS_MAKECMV(H2D_CMV_READ,index,size);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- }
- else{
- //memcpy(&pts.adslATURSubcarrierInfo_pt->SNRpsds[index],&RxMessage[4],size*2);
- int msg_idx=0;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
- pts.adslATURSubcarrierInfo_pt->SNRpsds[index+msg_idx] = (u16)(RxMessage[4+msg_idx]&0xFF);
- //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]);
- }
-
- }
- }
- }
- if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_BITPS)){
- int index=0,size=12;
- //printk("FAREND_BITPS\n");
- for (index=0;index<256;index+=size)
- {
- if (index+size>=256)
- size = 256-index;
- FAREND_BITPS_MAKECMV(H2D_CMV_READ,index,size);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- }
- else{
- int msg_idx=0;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
- pts.adslATURSubcarrierInfo_pt->BITpsds[(index+msg_idx)*2] = (u16)(RxMessage[4+msg_idx]&0xFF);
- pts.adslATURSubcarrierInfo_pt->BITpsds[(index+msg_idx)*2+1] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF);
- //printk("index:%d ,cmv_result: %04X, %d\n",index+msg_idx,RxMessage[4+msg_idx],RxMessage[4+msg_idx]);
-
- }
-
- }
- }
- }
- if(IS_FLAG_SET((&(pts.adslATURSubcarrierInfo_pt->flags)), FAREND_GAINPS)){
- int index=0,size=12;
- //printk("FAREND_GAINPS\n");
- for (index=0;index<512;index+=size)
- {
- FAREND_GAINPS_MAKECMV(H2D_CMV_READ,index,size);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- }
- else{
- /*
- int msg_idx=0;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
- pts.adslATURSubcarrierInfo_pt->GAINpsds[(index+msg_idx)*2] = RxMessage[4+msg_idx]&0xFF;
- pts.adslATURSubcarrierInfo_pt->GAINpsds[(index+msg_idx)*2+1] = (RxMessage[4+msg_idx]>>8)&0xFF;
-
- }
- */
- memcpy(&pts.adslATURSubcarrierInfo_pt->GAINpsds[index],&RxMessage[4],size*2);
-#if 0
- int msg_idx=0;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
- printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]);
-
- }
-#endif
- }
- }
- }
- copy_to_user((char *)lon, (char *)pts.adslATURSubcarrierInfo_pt, sizeof(adslATURSubcarrierInfo));
- kfree(pts.adslATURSubcarrierInfo_pt);
-
- up(&mei_sema);
- break;
- case GET_ADSL_ATUC_SUBCARRIER_STATS:
- if (loop_diagnostics_completed == 0)
- {
- interruptible_sleep_on_timeout(&wait_queue_loop_diagnostic,300*HZ);
- if (loop_diagnostics_completed==0)
- {
- return -ERESTARTSYS;
- }
- }
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
- pts.adslATUCSubcarrierInfo_pt = (adslATUCSubcarrierInfo *)kmalloc(sizeof(adslATUCSubcarrierInfo), GFP_KERNEL);
- copy_from_user((char *)pts.adslATUCSubcarrierInfo_pt, (char *)lon, sizeof(adslATUCSubcarrierInfo));
-
-
- if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_HLINSC)){
- NEAREND_HLINSC_MAKECMV(H2D_CMV_READ);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 71 Index 2");
-#endif
- pts.adslATUCSubcarrierInfo_pt->HLINSCus = 0;
- }
- else{
- pts.adslATUCSubcarrierInfo_pt->HLINSCus = RxMessage[4];
-
- }
- }
- if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_HLINPS)){
- int index=0,size=12;
- //printk("NEAREND_HLINPS\n");
- for (index=0;index<128;index+=size)
- {
- if (index+size>=128)
- size = 128-index;
- NEAREND_HLINPS_MAKECMV(H2D_CMV_READ,index,size);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 73 Index 0");
-#endif
- }
- else{
- memcpy(&pts.adslATUCSubcarrierInfo_pt->HLINpsus[index],&RxMessage[4],size*2);
-#if 0
- int msg_idx;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
- printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]);
- }
-#endif
- }
- }
- }
-
- if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_HLOGMT)){
- NEAREND_HLOGMT_MAKECMV(H2D_CMV_READ);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 80 Index 0");
-#endif
- pts.adslATUCSubcarrierInfo_pt->HLOGMTus = 0;
- }
- else{
- pts.adslATUCSubcarrierInfo_pt->HLOGMTus = RxMessage[4];
-
- }
- }
-
- /////////////////////////////////////////////////////////////////////////
- if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_HLOGPS)){
- int index=0,size=12;
- //printk("NEAREND_HLOGPS\n");
- for (index=0;index<64;index+=size)
- {
- if (index+size>=64)
- size = 64-index;
- NEAREND_HLOGPS_MAKECMV(H2D_CMV_READ,index,size);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 75 Index 0");
-#endif
- }
- else{
-#if 0
- if (adsl_mode <0x4000)//adsl /adsl2 mode
- {
-#endif
- memcpy(&pts.adslATUCSubcarrierInfo_pt->HLOGpsus[index],&RxMessage[4],size*2);
-#if 0
- }else
- {
- int msg_idx=0;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
- //pts.adslATUCSubcarrierInfo_pt->HLOGpsus[(index+msg_idx)*2+1] = RxMessage[4+msg_idx];
- pts.adslATUCSubcarrierInfo_pt->HLOGpsus[(index+msg_idx)] = RxMessage[4+msg_idx];
- }
- }
-#endif
- }
- }
-#if 0
- if (adsl_mode >= 0x4000)//adsl2 mode
- {
- pts.adslATUCSubcarrierInfo_pt->HLOGpsus[0] = pts.adslATUCSubcarrierInfo_pt->HLOGpsus[1];
- for (index=1;index<64;index++)
- {
- pts.adslATUCSubcarrierInfo_pt->HLOGpsus[index*2] = (pts.adslATUCSubcarrierInfo_pt->HLOGpsus[(index)*2-1] + pts.adslATUCSubcarrierInfo_pt->HLOGpsus[(index)*2+1]) >>1;
- }
- }
-#endif
- }
- if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_QLNMT)){
- NEAREND_QLNMT_MAKECMV(H2D_CMV_READ);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 80 Index 1");
-#endif
- pts.adslATUCSubcarrierInfo_pt->QLNMTus = 0;
- }
- else{
- pts.adslATUCSubcarrierInfo_pt->QLNMTus = RxMessage[4];
- }
- }
-
- /////////////////////////////////////////////////////////////////////////
- if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_QLNPS)){
- int index=0,size=12;
- //printk("NEAREND_QLNPS\n");
- for (index=0;index<32;index+=size)
- {
- if (index+size>=32)
- size = 32-index;
- NEAREND_QLNPS_MAKECMV(H2D_CMV_READ,index,size);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 77 Index 0");
-#endif
- }
- else{
- int msg_idx=0;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
-
-#if 0
- //memcpy(&pts.adslATUCSubcarrierInfo_pt->QLNpsds[index],&RxMessage[4],size*2);
- if (adsl_mode == 0x200 || adsl_mode == 0x800 || adsl_mode ==0x2000 || adsl_mode ==0x4000 || (adsl_mode == 0 && (adsl_mode_extend == 0x4 || adsl_mode_extend == 0x2))//ADSL 2 Annex B(0x200)/J(0x800)/M(0x2000) //ADSL 2+ B,J,M
- if (adsl_mode < 0x4000 && adsl_mode_extend==0)//adsl2 mode
- {
- pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index+msg_idx)*4+1] = (u16)(RxMessage[4+msg_idx]&0xFF);
- pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index+msg_idx)*4+3] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF);
- }else
-#endif
- {
- pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index+msg_idx)*2] = (u16)(RxMessage[4+msg_idx]&0xFF);
- pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index+msg_idx)*2+1] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF);
- //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]);
- }
- }
-
-
- }
- }
-#if 0
- //if (adsl_mode <0x4000)//Annex I/J/L/M
- if (adsl_mode == 0x200 || adsl_mode == 0x800 || adsl_mode ==0x2000 || adsl_mode ==0x4000 || (adsl_mode == 0 && (adsl_mode_extend == 0x4 || adsl_mode_extend == 0x2))//ADSL 2 Annex B(0x200)/J(0x800)/M(0x2000) //ADSL 2+ B,J,M
- {
- pts.adslATUCSubcarrierInfo_pt->QLNpsus[0] = pts.adslATUCSubcarrierInfo_pt->QLNpsus[1];
- for (index=1;index<64;index++)
- {
- pts.adslATUCSubcarrierInfo_pt->QLNpsus[index*2] = (pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index)*2-1] + pts.adslATUCSubcarrierInfo_pt->QLNpsus[(index)*2+1]) >>1;
- }
- }
-#endif
- }
- if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_SNRMT)){
- NEAREND_SNRMT_MAKECMV(H2D_CMV_READ);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 80 Index 2");
-#endif
- pts.adslATUCSubcarrierInfo_pt->SNRMTus = 0;
- }
- else{
- pts.adslATUCSubcarrierInfo_pt->SNRMTus = RxMessage[4];
- }
- }
- if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_SNRPS)){
- int index=0,size=12;
- //printk("NEAREND_SNRPS\n");
- for (index=0;index<64;index+=size)
- {
- if (index+size>=64)
- size = 64-index;
- NEAREND_SNRPS_MAKECMV(H2D_CMV_READ,index,size);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 78 Index 0");
-#endif
- }
- else{
- //memcpy(&pts.adslATUCSubcarrierInfo_pt->SNRpsus[index],&RxMessage[4],size*2);
- int msg_idx=0;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
- pts.adslATUCSubcarrierInfo_pt->SNRpsus[index+msg_idx] = (u16)(RxMessage[4+msg_idx]&0xFF);
- //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]);
- }
-
- }
- }
- }
- if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_BITPS)){
- int index=0,size=12;
- //printk("NEAREND_BITPS\n");
- for (index=0;index<32;index+=size)
- {
- if (index+size>=32)
- size = 32-index;
- NEAREND_BITPS_MAKECMV(H2D_CMV_READ,index,size);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 22 Index 0");
-#endif
- }
- else{
- int msg_idx=0;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
- pts.adslATUCSubcarrierInfo_pt->BITpsus[(index+msg_idx)*2] = (u16)(RxMessage[4+msg_idx]&0xFF);
- pts.adslATUCSubcarrierInfo_pt->BITpsus[(index+msg_idx)*2+1] = (u16)((RxMessage[4+msg_idx]>>8)&0xFF);
- //printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]);
- }
-
- }
- }
- }
- if(IS_FLAG_SET((&(pts.adslATUCSubcarrierInfo_pt->flags)), NEAREND_GAINPS)){
- int index=0,size=12;
- //printk("NEAREND_GAINPS\n");
- for (index=0;index<64;index+=size)
- {
- if (index+size>=64)
- size = 64-index;
- NEAREND_GAINPS_MAKECMV(H2D_CMV_READ,index,size);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group INFO Address 24 Index 0");
-#endif
- }
- else{
- /*
- int msg_idx=0;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
- pts.adslATUCSubcarrierInfo_pt->GAINpsds[(index+msg_idx)*2] = RxMessage[4+msg_idx]&0xFF;
- pts.adslATUCSubcarrierInfo_pt->GAINpsds[(index+msg_idx)*2+1] = (RxMessage[4+msg_idx]>>8)&0xFF;
-
- }
- */
- memcpy(&pts.adslATUCSubcarrierInfo_pt->GAINpsus[index],&RxMessage[4],size*2);
-#if 0
- int msg_idx;
- for (msg_idx=0;msg_idx<size;msg_idx++)
- {
- printk("index:%d ,cmv_result: %04X\n",index+msg_idx,RxMessage[4+msg_idx]);
- }
-#endif
- }
- }
- }
- copy_to_user((char *)lon, (char *)pts.adslATUCSubcarrierInfo_pt, sizeof(adslATUCSubcarrierInfo));
- kfree(pts.adslATUCSubcarrierInfo_pt);
- up(&mei_sema);
- break;
- case GET_ADSL_LINE_INIT_STATS:
- copy_to_user((char *)lon, (char *)&AdslInitStatsData, sizeof(AdslInitStatsData));
- break;
-
- case GET_ADSL_POWER_SPECTRAL_DENSITY:
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
- i=0;
- pts.adslPowerSpectralDensity_pt = (adslPowerSpectralDensity *)kmalloc(sizeof(adslPowerSpectralDensity), GFP_KERNEL);
- memset((char *)pts.adslPowerSpectralDensity_pt, 0, sizeof(adslPowerSpectralDensity));
-
- //US
- NOMPSD_US_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- i=-1;
- }
- else{
- j=RxMessage[4];
- }
- PCB_US_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- i=-1;
- }
- else{
- temp=RxMessage[4];
- }
- RMSGI_US_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- i=-1;
- }
- else{
- k=(int16_t)RxMessage[4];
- }
- if (i==0)
- {
- pts.adslPowerSpectralDensity_pt->ACTPSDus = ((int )(j*256 - temp*10*256 + k*10)) /256;
- }
- // DS
- i=0;
- j=temp=temp2=0;
- NOMPSD_DS_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- i=-1;
- }
- else{
- j=RxMessage[4];
- }
- PCB_DS_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- i=-1;
- }
- else{
- temp=RxMessage[4];
- }
- RMSGI_DS_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group PLAM Address 35 Index 0");
-#endif
- i=-1;
- }
- else{
- //temp2=RxMessage[4];
- k=(int16_t)RxMessage[4];
- }
- if (i==0)
- {
- pts.adslPowerSpectralDensity_pt->ACTPSDds = ((int )(j*256 - temp*10*256 + k*10)) /256;
- }
- copy_to_user((char *)lon, (char *)pts.adslPowerSpectralDensity_pt, sizeof(adslPowerSpectralDensity));
- kfree(pts.adslPowerSpectralDensity_pt);
- up(&mei_sema);
- break;
- case AMAZON_MEI_START:
- showtime=0;
- loop_diagnostics_completed = 0;
-#ifdef ARC_READY_ACK
-#ifdef LOCK_RETRY
- i=0;
-lock_retry:
- if(down_trylock(&mei_sema)!=0)
- {
- reboot_lock = 1;
- printk("lock fail\n");
- i++;
- if (i <=5)
- {
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(10);
- goto lock_retry;
- }else
- {
- printk("Force to Reboot ADSL!\n");
- up(&mei_sema);
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(1000);
- sema_init(&mei_sema, 1); // semaphore initialization, mutex
- }
- }else
- {
- reboot_lock = 1;
- }
-#else
- if(down_interruptible(&mei_sema)) //disable CMV access until ARC ready
- {
- return -ERESTARTSYS;
- }
-#endif
-#endif
- //CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO ON
- if(chantype.interleave==1){
- kfree(interleave_mei_net.priv);
- unregister_netdev(&interleave_mei_net);
- }
- else if(chantype.fast==1){
- kfree(fast_mei_net.priv);
- unregister_netdev(&fast_mei_net);
- }
- chantype.interleave=0;
- chantype.fast=0;
- meiMailboxInterruptsDisable(); //disable all MEI interrupts
- if(mei_arc_swap_buff == NULL){
- mei_arc_swap_buff = (u32 *)kmalloc(MAXSWAPSIZE*4, GFP_KERNEL);
- if(mei_arc_swap_buff==NULL){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n malloc fail for codeswap buff");
-#endif
- meierr=MEI_FAILURE;
- }
- }
- if(meiForceRebootAdslModem() != MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n meiForceRebootAdslModem() error...");
-#endif
- meierr=MEI_FAILURE;
- }
- interruptible_sleep_on(&wait_queue_codeswap);
- // reset is called
- break;
- case AMAZON_MEI_MIB_DAEMON:
-#ifdef IFX_SMALL_FOOTPRINT /* [ */
- return -1;
-#else /* ][ !IFX_SMALL_FOOTPRINT */
- i=0;
- while(1){
- if(i<MIB_INTERVAL)
- interruptible_sleep_on_timeout(&wait_queue_mibdaemon, ((MIB_INTERVAL-i)/(1000/HZ)));
- i=0;
- if(showtime==1){
-// printk("\n\n update mib");
-
- do_gettimeofday(&time_now);
- if(time_now.tv_sec - current_intvl->start_time.tv_sec>=900){
- if(current_intvl->list.next!=&interval_list){
- current_intvl = list_entry(current_intvl->list.next, amazon_mei_mib, list);
- do_gettimeofday(&(current_intvl->start_time));
- }
- else{
- mib_ptr = list_entry(interval_list.next, amazon_mei_mib, list);
- list_del(interval_list.next);
- memset(mib_ptr, 0, sizeof(amazon_mei_mib));
- list_add_tail(&(mib_ptr->list), &interval_list);
- if(current_intvl->list.next==&interval_list)
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nlink list error");
-#endif
- current_intvl = list_entry(current_intvl->list.next, amazon_mei_mib, list);
- do_gettimeofday(&(current_intvl->start_time));
- }
- }
-
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-/*
- ATUC_PERF_LO_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 0 Index 0");
-#endif
- }
- else{
- if(RxMessage[4]&PLAM_LOS_FailureBit){
- current_intvl->AtucPerfLos++;
- ATUC_PERF_LOSS++;
- CurrStatus.adslAtucCurrStatus = 2;
- }
- if(RxMessage[4]&PLAM_LOF_FailureBit){
- current_intvl->AtucPerfLof++;
- ATUC_PERF_LOFS++;
- CurrStatus.adslAtucCurrStatus = 1;
- }
- if(!(RxMessage[4]&(PLAM_LOS_FailureBit|PLAM_LOF_FailureBit)))
- CurrStatus.adslAtucCurrStatus = 0;
- }
-*/
- ATUC_PERF_ESS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 7 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4]-mib_pread.ATUC_PERF_ESS;
- if(temp>=0){
- current_intvl->AtucPerfEs+=temp;
- ATUC_PERF_ESS+=temp;
- mib_pread.ATUC_PERF_ESS = RxMessage[4];
- }
- else{
- current_intvl->AtucPerfEs+=0xffff-mib_pread.ATUC_PERF_ESS+RxMessage[4];
- ATUC_PERF_ESS+=0xffff-mib_pread.ATUC_PERF_ESS+RxMessage[4];
- mib_pread.ATUC_PERF_ESS = RxMessage[4];
- }
- }
-/*
- ATUR_PERF_LO_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 1 Index 0");
-#endif
- }
- else{
- if(RxMessage[4]&PLAM_LOS_FailureBit){
- current_intvl->AturPerfLos++;
- ATUR_PERF_LOSS++;
- CurrStatus.adslAturCurrStatus = 2;
- }
- if(RxMessage[4]&PLAM_LOF_FailureBit){
- current_intvl->AturPerfLof++;
- ATUR_PERF_LOFS++;
- CurrStatus.adslAturCurrStatus = 1;
- }
- if(RxMessage[4]&PLAM_LPR_FailureBit){
- current_intvl->AturPerfLpr++;
- ATUR_PERF_LPR++;
- CurrStatus.adslAturCurrStatus = 3;
- }
- if(!(RxMessage[4]&(PLAM_LOS_FailureBit|PLAM_LOF_FailureBit|PLAM_LPR_FailureBit)))
- CurrStatus.adslAturCurrStatus = 0;
- }
-*/
- ATUR_PERF_ESS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 33 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4]-mib_pread.ATUR_PERF_ESS;
- if(temp>=0){
- current_intvl->AturPerfEs+=temp;
- ATUR_PERF_ESS+=temp;
- mib_pread.ATUR_PERF_ESS = RxMessage[4];
- }
- else{
- current_intvl->AturPerfEs+=0xffff-mib_pread.ATUR_PERF_ESS+RxMessage[4];
- ATUR_PERF_ESS+= 0xffff-mib_pread.ATUR_PERF_ESS+RxMessage[4];
- mib_pread.ATUR_PERF_ESS=RxMessage[4];
- }
- }
- // to update rx/tx blocks
- ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 20 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4];
- }
- ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 21 Index 0");
-#endif
- }
- else{
- temp2 = RxMessage[4];
- }
- if((temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK)>=0){
- current_intvl->AturChanPerfRxBlk+=temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK;
- ATUR_CHAN_RECV_BLK+=temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK;
- mib_pread.ATUR_CHAN_RECV_BLK = temp + (temp2<<16);
- }
- else{
- current_intvl->AturChanPerfRxBlk+=0xffffffff - mib_pread.ATUR_CHAN_RECV_BLK +(temp + (temp2<<16));
- ATUR_CHAN_RECV_BLK+=0xffffffff - mib_pread.ATUR_CHAN_RECV_BLK +(temp + (temp2<<16));
- mib_pread.ATUR_CHAN_RECV_BLK = temp + (temp2<<16);
- }
- current_intvl->AturChanPerfTxBlk = current_intvl->AturChanPerfRxBlk;
- ATUR_CHAN_TX_BLK = ATUR_CHAN_RECV_BLK;
-/*
- ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS)
- printk("\n\nCMV fail, Group 7 Address 20 Index 0");
- else{
- if(RxMessage[4]){
- current_intvl->AturChanPerfTxBlk+=RxMessage[4];
- ATUR_CHAN_TX_BLK+=RxMessage[4];
- }
- }
- ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS)
- printk("\n\nCMV fail, Group 7 Address 21 Index 0");
- else{
- if(RxMessage[4]){
- current_intvl->AturChanPerfTxBlk+=(int)((RxMessage[4])<<16);
- ATUR_CHAN_TX_BLK+=(int)((RxMessage[4])<<16);
- }
- }
-*/
- if(chantype.interleave == 1){
- ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 3 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUR_CHAN_CORR_BLK_INTL;
- if(temp>=0){
- current_intvl->AturChanPerfCorrBlk+=temp;
- ATUR_CHAN_CORR_BLK+=temp;
- mib_pread.ATUR_CHAN_CORR_BLK_INTL = RxMessage[4];
- }
- else{
- current_intvl->AturChanPerfCorrBlk+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_INTL +RxMessage[4];
- ATUR_CHAN_CORR_BLK+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_INTL +RxMessage[4];
- mib_pread.ATUR_CHAN_CORR_BLK_INTL = RxMessage[4];
- }
- }
- }
- else if(chantype.fast == 1){
- ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 3 Index 1");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUR_CHAN_CORR_BLK_FAST;
- if(temp>=0){
- current_intvl->AturChanPerfCorrBlk+=temp;
- ATUR_CHAN_CORR_BLK+=temp;
- mib_pread.ATUR_CHAN_CORR_BLK_FAST = RxMessage[4];
- }
- else{
- current_intvl->AturChanPerfCorrBlk+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_FAST + RxMessage[4];
- ATUR_CHAN_CORR_BLK+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_FAST + RxMessage[4];
- mib_pread.ATUR_CHAN_CORR_BLK_FAST = RxMessage[4];
- }
- }
- }
-
- if(chantype.interleave == 1){
- ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 2 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL;
- if(temp>=0){
- current_intvl->AturChanPerfUncorrBlk+=temp;
- ATUR_CHAN_UNCORR_BLK+=temp;
- mib_pread.ATUR_CHAN_UNCORR_BLK_INTL = RxMessage[4];
- }
- else{
- current_intvl->AturChanPerfUncorrBlk+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL + RxMessage[4];
- ATUR_CHAN_UNCORR_BLK+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL + RxMessage[4];
- mib_pread.ATUR_CHAN_UNCORR_BLK_INTL = RxMessage[4];
- }
- }
- }
- else if(chantype.fast == 1){
- ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 2 Index 1");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST;
- if(temp>=0){
- current_intvl->AturChanPerfUncorrBlk+=temp;
- ATUR_CHAN_UNCORR_BLK+=temp;
- mib_pread.ATUR_CHAN_UNCORR_BLK_FAST = RxMessage[4];
- }
- else{
- current_intvl->AturChanPerfUncorrBlk+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST + RxMessage[4];
- ATUR_CHAN_UNCORR_BLK+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST + RxMessage[4];
- mib_pread.ATUR_CHAN_UNCORR_BLK_FAST = RxMessage[4];
- }
- }
- }
-
- //RFC-3440
-
-#ifdef AMAZON_MEI_MIB_RFC3440
- ATUC_PERF_STAT_FASTR_FLAG_MAKECMV; //???
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 0 Address 0 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_FASTR;
- if(temp>=0){
- current_intvl->AtucPerfStatFastR+=temp;
- ATUC_PERF_STAT_FASTR+=temp;
- mib_pread.ATUC_PERF_STAT_FASTR = RxMessage[4];
- }
- else{
- current_intvl->AtucPerfStatFastR+=0xffff - mib_pread.ATUC_PERF_STAT_FASTR + RxMessage[4];
- ATUC_PERF_STAT_FASTR+=0xffff - mib_pread.ATUC_PERF_STAT_FASTR + RxMessage[4];
- mib_pread.ATUC_PERF_STAT_FASTR = RxMessage[4];
- }
- }
- ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV; //???
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 0 Address 0 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_FAILED_FASTR;
- if(temp>=0){
- current_intvl->AtucPerfStatFailedFastR+=temp;
- ATUC_PERF_STAT_FAILED_FASTR+=temp;
- mib_pread.ATUC_PERF_STAT_FAILED_FASTR = RxMessage[4];
- }
- else{
- current_intvl->AtucPerfStatFailedFastR+=0xffff - mib_pread.ATUC_PERF_STAT_FAILED_FASTR + RxMessage[4];
- ATUC_PERF_STAT_FAILED_FASTR+=0xffff - mib_pread.ATUC_PERF_STAT_FAILED_FASTR + RxMessage[4];
- mib_pread.ATUC_PERF_STAT_FAILED_FASTR = RxMessage[4];
- }
- }
- ATUC_PERF_STAT_SESL_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 8 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_SESL;
- if(temp>=0){
- current_intvl->AtucPerfStatSesL+=temp;
- ATUC_PERF_STAT_SESL+=temp;
- mib_pread.ATUC_PERF_STAT_SESL = RxMessage[4];
- }
- else{
- current_intvl->AtucPerfStatSesL+=0xffff - mib_pread.ATUC_PERF_STAT_SESL + RxMessage[4];
- ATUC_PERF_STAT_SESL+=0xffff - mib_pread.ATUC_PERF_STAT_SESL + RxMessage[4];
- mib_pread.ATUC_PERF_STAT_SESL = RxMessage[4];
- }
- }
- ATUC_PERF_STAT_UASL_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 10 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_UASL;
- if(temp>=0){
- current_intvl->AtucPerfStatUasL+=temp;
- ATUC_PERF_STAT_UASL+=temp;
- mib_pread.ATUC_PERF_STAT_UASL = RxMessage[4];
- }
- else{
- current_intvl->AtucPerfStatUasL+=0xffff - mib_pread.ATUC_PERF_STAT_UASL + RxMessage[4];
- ATUC_PERF_STAT_UASL+=0xffff - mib_pread.ATUC_PERF_STAT_UASL + RxMessage[4];
- mib_pread.ATUC_PERF_STAT_UASL = RxMessage[4];
- }
- }
- ATUR_PERF_STAT_SESL_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 34 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUR_PERF_STAT_SESL;
- if(temp>=0){
- current_intvl->AtucPerfStatUasL+=temp;
- ATUC_PERF_STAT_UASL+=temp;
- mib_pread.ATUR_PERF_STAT_SESL = RxMessage[4];
- }
- else{
- current_intvl->AtucPerfStatUasL+=0xffff - mib_pread.ATUR_PERF_STAT_SESL + RxMessage[4];
- ATUC_PERF_STAT_UASL+=0xffff - mib_pread.ATUR_PERF_STAT_SESL + RxMessage[4];
- mib_pread.ATUR_PERF_STAT_SESL = RxMessage[4];
- }
- }
-
-#endif
- up(&mei_sema);
-
- do_gettimeofday(&time_fini);
- i = ((int)((time_fini.tv_sec-time_now.tv_sec)*1000)) + ((int)((time_fini.tv_usec-time_now.tv_usec)/1000)) ; //msec
- }//showtime==1
- }
- break;
-#endif /* ] !IFX_SMALL_FOOTPRINT */
- case AMAZON_MEI_RESET:
- case AMAZON_MEI_REBOOT:
- case AMAZON_MEI_SHOWTIME:
-/* if(mei_arc_swap_buff !=NULL){
- kfree(mei_arc_swap_buff);
- mei_arc_swap_buff=NULL;
- }
- if(image_buffer !=NULL){
-// kfree(image_buffer);
- vfree(image_buffer);
- image_buffer =NULL;
- }
-*/
- if(clreoc_command_pkt !=NULL){
- kfree(clreoc_command_pkt);
- clreoc_command_pkt =NULL;
- }
- for(i=0;i<CLREOC_BUFF_SIZE;i++)
- clreoc_pkt[i].len=0; //flush all remaining clreoc commands in buffer
-/*
- memset(mei_mib, 0, (sizeof(amazon_mei_mib)*INTERVAL_NUM));
- INIT_LIST_HEAD(&interval_list);
- for(i=0;i<INTERVAL_NUM;i++)
- list_add_tail(&(mei_mib[i].list), &interval_list);
- current_intvl = list_entry(interval_list.next, amazon_mei_mib, list);
- do_gettimeofday(&(current_intvl->start_time));
- ATUC_PERF_LOFS=0;
- ATUC_PERF_LOSS=0;
- ATUC_PERF_ESS=0;
- ATUC_PERF_INITS=0;
- ATUR_PERF_LOFS=0;
- ATUR_PERF_LOSS=0;
- ATUR_PERF_LPR=0;
- ATUR_PERF_ESS=0;
- ATUR_CHAN_RECV_BLK=0;
- ATUR_CHAN_TX_BLK=0;
- ATUR_CHAN_CORR_BLK=0;
- ATUR_CHAN_UNCORR_BLK=0;
- memset((((u8 *)&AlarmConfProfile)+32), 0, 16*4);
- AlarmConfProfile.adslLineAlarmConfProfileRowStatus=1;
-*/
- PrevTxRate.adslAtucChanPrevTxRate=0;
- PrevTxRate.adslAturChanPrevTxRate=0;
- CurrStatus.adslAtucCurrStatus=0;
- CurrStatus.adslAturCurrStatus=0;
-
- if((command==AMAZON_MEI_RESET) || (command==AMAZON_MEI_REBOOT)){
-#ifdef AMAZON_CHECK_LINK
- if (adsl_link_notify){
- (*adsl_link_notify)(0);
- }
-#endif
- showtime=0;
- //CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO ON
- // disconnect net_dev
- if(chantype.interleave==1){
- kfree(interleave_mei_net.priv);
- unregister_netdev(&interleave_mei_net);
-// if(unregister_netdev(&interleave_mei_net)!=0)
-// printk("\n unregister interleave fail");
- }
- else if(chantype.fast==1){
- kfree(fast_mei_net.priv);
- unregister_netdev(&fast_mei_net);
-// if(unregister_netdev(&fast_mei_net)!=0)
-// printk("\n unregister fast fail");
- }
- chantype.interleave=0;
- chantype.fast=0;
-// 603221:tc.chen start
- chantype.bearchannel0 = 0;
- chantype.bearchannel1 = 0;
- adsl_mode = 0;
-// 603221:tc.chen end
-
- while(1){
-
- makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, NULL); //maximum allowed tx message length, in bytes
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
- //printk("AdslInitStatsData.FullInitializationCount++\n");
- AdslInitStatsData.FullInitializationCount++;
- //printk("AdslInitStatsData.FailedFullInitializationCount++\n");
- AdslInitStatsData.FailedFullInitializationCount++;
- //printk("AdslInitStatsData.LINIT_Errors++\n");
- AdslInitStatsData.LINIT_Errors++;
- }else
- {
- //printk("RxMessage=%X\n",RxMessage[4]);
- if ( RxMessage[4]!=0x1)
- {
- //printk("AdslInitStatsData.FullInitializationCount++\n");
- AdslInitStatsData.FullInitializationCount++;
- if ( RxMessage[4] != 0x7)
- {
- //printk("AdslInitStatsData.LINIT_Errors++\n");
- AdslInitStatsData.LINIT_Errors++;
- //printk("AdslInitStatsData.FailedFullInitializationCount++\n");
- AdslInitStatsData.FailedFullInitializationCount++;
-
- }
- }
- }
-
- reboot_flag=0;
- wake_up_interruptible(&wait_queue_codeswap); //wake up codeswap daemon
-
- interruptible_sleep_on_timeout(&wait_queue_reboot, 1*HZ); // sleep until arc ready
-#ifdef ARC_READY_ACK
- if(reboot_flag!=0)
- break;
- else
- {
- up(&mei_sema);
- printk("\n reboot retry");
- }
-#else
- break;
-#endif
- }
- }
- else{ //AMAZON_MEI_SHOWTIME
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- // clreoc stuff
- makeCMV(H2D_CMV_READ, INFO, 83, 0, 1, data); //maximum allowed tx message length, in bytes
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 83 Index 0");
-#endif
- }
- else{
- clreoc_max_tx_len = (int)RxMessage[4];
- clreoc_command_pkt = kmalloc((clreoc_max_tx_len*CLREOC_BUFF_SIZE), GFP_KERNEL);
- if(clreoc_command_pkt == NULL){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("kmalloc error for clreoc_command_pkt\n\n");
-#endif
- up(&mei_sema);
- return -1;
- }
- for(i=0;i<CLREOC_BUFF_SIZE;i++){
- clreoc_pkt[i].command = (u8 *)(((u8 *)clreoc_command_pkt) + (clreoc_max_tx_len*i));
- clreoc_pkt[i].len=0;
- }
- }
-
- // decide what channel, then register
- makeCMV(H2D_CMV_READ, STAT, 12, 0, 1, data);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 2 Address 12 Index 0");
-#endif
- }
- else{
- if((RxMessage[4]&0x1)==1){
- if(register_netdev(&interleave_mei_net)!=0){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n Register interleave Device Failed.");
-#endif
- }
- else{
- chantype.interleave = 1;
- chantype.fast= 0;
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n channel is interleave");
-#endif
- }
- }
- else if((RxMessage[4]&0x2)==2){
- if(register_netdev(&fast_mei_net)!=0){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n Register fast Device Failed.");
-#endif
- }
- else{
- chantype.fast = 1;
- chantype.interleave = 0;
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n channel is fast");
-#endif
- }
- }
- else{
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\nunknown channel type, 0x%8x", RxMessage[4]);
-#endif
- }
-// 603221:tc.chen start
- if ( (RxMessage[4]&0x100) == 0x100)
- {
- chantype.bearchannel0 = 1;
- }else if ( (RxMessage[4]&0x100) == 0x200)
- {
- chantype.bearchannel1 = 1;
- }
-// 603221:tc.chen end
- }
-// 603221:tc.chen start
- // read adsl mode
- makeCMV(H2D_CMV_READ, STAT, 1, 0, 1, data);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group STAT Address 1 Index 0");
-#endif
- }
- adsl_mode = RxMessage[4];
-// 603221:tc.chen end
- makeCMV(H2D_CMV_READ, STAT, 17, 0, 1, data);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group STAT Address 1 Index 0");
-#endif
- }
- adsl_mode_extend = RxMessage[4];
-
- // update previous channel tx rate
- ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 6 Address 1 Index 0");
-#endif
- PrevTxRate.adslAtucChanPrevTxRate = 0;
- }
- else{
- PrevTxRate.adslAtucChanPrevTxRate = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- }
- ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 6 Address 0 Index 0");
-#endif
- PrevTxRate.adslAturChanPrevTxRate = 0;
- }
- else{
- PrevTxRate.adslAturChanPrevTxRate = (u32)(RxMessage[4]) + (((u32)(RxMessage[5]))<<16);
- }
-
-// up(&mei_sema);
-
-// showtime=1;
- //SET_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO OFF
-//dying gasp -start
-#ifdef IFX_DYING_GASP
- lop_debugwr.buffer[0]=0xffffffff; //dying gasp
- lop_debugwr.iCount=1; //dying gasp
- makeCMV(H2D_CMV_READ, INFO, 66, 4, 1, NULL);
- //mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &RxMessage);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 66 Index 4");
- }
-#endif
- lop_debugwr.iAddress=(u32)RxMessage[4];
- makeCMV(H2D_CMV_READ, INFO, 66, 5, 1, NULL);
- //mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &RxMessage);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 3 Address 66 Index 5");
- }
-#endif
- lop_debugwr.iAddress+=((u32)RxMessage[4])<<16;
-
-//dying gasp -end
-#endif // IFX_DYING_GASP
-
-//joelin 04/16/2005-start
- makeCMV(H2D_CMV_WRITE, PLAM, 10, 0, 1, &unavailable_seconds);
- //mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &RxMessage);
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 10 Index 0");
-
-#endif
- }
-
-
-//joelin 04/16/2005-end
- showtime=1;
- up(&mei_sema);
-#ifdef AMAZON_CHECK_LINK
- if (adsl_link_notify){
- (*adsl_link_notify)(1);
- }
-#endif
-
-
- }
- break;
-/*
- case AMAZON_MEI_REPLY:
- copy_from_user((char *)buff, (char *)lon, MSG_LENGTH * 2);
- if(meiCMV(buff, YES_REPLY) != MEI_SUCCESS){
- printk("\n\n meiCMV no reply back");
- meierr=MEI_FAILURE;
- }
- else
- copy_to_user((char *)lon, (char *)RxMessage, MSG_LENGTH * 2);
- break;
- case AMAZON_MEI_NOREPLY:
- copy_from_user((char *)buff, (char *)lon, MSG_LENGTH * 2);
- if(meiCMV(buff, NO_REPLY) != MEI_SUCCESS){
- printk("\n\n meiCMV Host to DSP failed");
- meierr=MEI_FAILURE;
- }
- break;
-*/
-
- case AMAZON_MEI_HALT:
- meiHaltArc();
- break;
- case AMAZON_MEI_CMV_WINHOST:
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-
- if (!from_kernel )
- copy_from_user((char *)TxMessage, (char *)lon, MSG_LENGTH*2);//joelin
- else
- memcpy(TxMessage,(char *)lon,MSG_LENGTH*2);
-
-#if 0
-// if((TxMessage[0]&0xff0)==0x0a0){
- for(i=0;i<16;i++){
- printk("\nTxMessage[%i]=%8x", i, TxMessage[i]);
- }
-// }
-#endif
-
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
-// printk("\n\n WINHOST CMV fail ");
- printk("\n\nWINHOST CMV fail :TxMessage:%X %X %X %X, RxMessage:%X %X %X %X %X\n",TxMessage[0],TxMessage[1],TxMessage[2],TxMessage[3],RxMessage[0],RxMessage[1],RxMessage[2],RxMessage[3],RxMessage[4]);
-#endif
- meierr = MEI_FAILURE;
- }
- else
- {
- if (!from_kernel ) //joelin
- copy_to_user((char *)lon, (char *)RxMessage, MSG_LENGTH*2);
- else
- memcpy((char *)lon,(char *)RxMessage,MSG_LENGTH*2);
- }
-
- up(&mei_sema);
- break;
-#ifdef AMAZON_MEI_CMV_EXTRA
- case AMAZON_MEI_CMV_READ:
- copy_from_user((char *)(®rdwr), (char *)lon, sizeof(meireg));
- meiLongwordRead(regrdwr.iAddress, &(regrdwr.iData));
- {
-// printk("\n\n iAddress = %8x",regrdwr.iAddress);
- }
- copy_to_user((char *)lon, (char *)(®rdwr), sizeof(meireg));
- {
-// printk("\n\n iData readback = %8x", regrdwr.iData);
- }
- break;
-#endif
-
-#ifdef AMAZON_MEI_CMV_EXTRA
- case AMAZON_MEI_CMV_WRITE:
- copy_from_user((char *)(®rdwr), (char *)lon, sizeof(meireg));
- {
-// printk("\n\n iAddress = %8x",regrdwr.iAddress);
-// printk("\n\n iData = %8x",regrdwr.iData);
- }
- meiLongwordWrite(regrdwr.iAddress, regrdwr.iData);
- break;
-#endif
-
-#ifdef AMAZON_MEI_CMV_EXTRA
- case AMAZON_MEI_REMOTE:
- copy_from_user((char *)(&i), (char *)lon, sizeof(int));
- if(i==0){
- meiMailboxInterruptsEnable();
-
- up(&mei_sema);
- }
- else if(i==1){
- meiMailboxInterruptsDisable();
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
- }
- else{
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n AMAZON_MEI_REMOTE argument error");
-#endif
- meierr=MEI_FAILURE;
- }
- break;
-#endif
-
-#ifdef AMAZON_MEI_CMV_EXTRA
- case AMAZON_MEI_READDEBUG:
- case AMAZON_MEI_WRITEDEBUG:
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-#ifdef IFX_DYING_GASP
- if (!from_kernel) copy_from_user((char *)(&debugrdwr), (char *)lon, sizeof(debugrdwr));//dying gasp
- else memcpy((char *)(&debugrdwr), (char *)lon, sizeof(debugrdwr));
-#else //IFX_DYING_GASP
- copy_from_user((char *)(&debugrdwr), (char *)lon, sizeof(debugrdwr));
-
-#endif //IFX_DYING_GASP
-#if 0
- printk("\nIN iAddress: %8x, iCount:%8x\n", debugrdwr.iAddress, debugrdwr.iCount);
-#endif
-
- if(command==AMAZON_MEI_READDEBUG)
- meiDebugRead(debugrdwr.iAddress, debugrdwr.buffer, debugrdwr.iCount);
- else
- meiDebugWrite(debugrdwr.iAddress, debugrdwr.buffer, debugrdwr.iCount);
-
-#ifdef IFX_DYING_GASP
- if (!from_kernel) copy_to_user((char *)lon, (char*)(&debugrdwr), sizeof(debugrdwr));//dying gasp
-#else //IFX_DYING_GASP
- copy_to_user((char *)lon, (char*)(&debugrdwr), sizeof(debugrdwr));
-#endif //IFX_DYING_GASP
- up(&mei_sema);
-
-#if 0
- printk("\nOUT iAddress: %8x, iCount:%8x\n", debugrdwr.iAddress, debugrdwr.iCount);
- for(i=0;i<debugrdwr.iCount;i++)
- printk("\n %8x",debugrdwr.buffer[i]);
-#endif
- break;
-#endif
-
- case AMAZON_MEI_LOP:
- //GPIO31 :dying gasp event indication
- // (1) logic high: dying gasp event is false (default)
- // (2) logic low: dying gasp event is true
-#ifdef IFX_DYING_GASP
- break;
-#else
- CLEAR_BIT((*((volatile u32 *)0xB0100B48)), 0x8000);
- CLEAR_BIT((*((volatile u32 *)0xB0100B4C)), 0x8000);
- CLEAR_BIT((*((volatile u32 *)0xB0100B50)), 0x8000);
- SET_BIT((*((volatile u32 *)0xB0100B54)), 0x8000);
- asm("SYNC");
- if(((*((volatile u32 *)0xB0100B44))&0x8000)==0x0)
- meierr=MEI_FAILURE; //return - to indicate loss of power
- break;
-#endif //#ifdef IFX_DYING_GASP
-
- //for PCM
- case AMAZON_MEI_PCM_SETUP:
- //gpio
-
- *AMAZON_GPIO_P0_DIR |=1<<15;
- *AMAZON_GPIO_P0_ALTSEL0 |=1<<15;
- *AMAZON_GPIO_P0_ALTSEL1 &=~(1<<15);
- *AMAZON_GPIO_P0_OD |=1<<15;
-
- /*GPIO 16 TDM_DI*/
- *AMAZON_GPIO_P1_DIR &=~1;
- *AMAZON_GPIO_P1_ALTSEL0 |=1;
- *AMAZON_GPIO_P1_ALTSEL1 &=~1;
-
- /*GPIO 17 TDM_DCL */
- *AMAZON_GPIO_P1_DIR|=0x02;
- *AMAZON_GPIO_P1_ALTSEL0|=0x02;
- *AMAZON_GPIO_P1_ALTSEL1 &=(u32)~0x02;
- *AMAZON_GPIO_P1_OD|=0x02;
-
- /*GPIO 18 TDM FSC*/
- *AMAZON_GPIO_P1_DIR|=0x04;
- *AMAZON_GPIO_P1_ALTSEL0|=0x04;
- *AMAZON_GPIO_P1_ALTSEL1 &=(u32)~0x04;
- *AMAZON_GPIO_P1_OD|=0x04;
-
- for(i=0;i<2;i++){
- for(j=0;j<256;j++)
- sampledata[i*256+j]=j;
- }
-
- pcm_start_addr = lon;
-
- printk("\n\n pcm_start_addr is %8x", lon);
-
- for(i=0;i<PCM_CHANNEL_NUM;i++){
-#ifdef PCM_ACCESS_DEBUG
- meiDebugRead_16((pcm_start_addr+i*16), (u32*)(pcm_data+i), 4);
-#else
- meiDMARead_16((pcm_start_addr+i*16), (u32*)(pcm_data+i), 4);
-#endif
- if((pcm_data[i].S!=8)||(pcm_data[i].len<1)||(pcm_data[i].rdindex!=0)||(pcm_data[i].wrindex!=0)||(pcm_data[i].flow!=0))
- printk("\n\n pcm_data fill in wrongly\n\n");
- printk("\npcm_data %d",i);
- printk("\n S = %d", pcm_data[i].S);
- printk("\n LSW = %4x", pcm_data[i].LSW);
- printk("\n MSW = %4x", pcm_data[i].MSW);
- printk("\n len = %d", pcm_data[i].len);
- printk("\n rdindex = %d", pcm_data[i].rdindex);
- printk("\n wrindex = %d", pcm_data[i].wrindex);
- printk("\n flow = %d", pcm_data[i].flow);
- pcm_data[i].finish=0;
- if(i%2==0){//tx channel
- for(j=0;j<PCM_BUFF_SIZE/256;j++){
- for(k=0;k<256;k++){
- pcm_data[i].buff[j*256+k]=k;
- /* if(k%2==0)
- pcm_data[i].buff[j*256+k]=0xaa;
- else
- pcm_data[i].buff[j*256+k]=0x55;*/
- }
- }
-#ifdef PCM_ACCESS_DEBUG
- meiDebugWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16)), (u32*)(pcm_data[i].buff),((pcm_data[i].len/4)/2));//fill half first
-// meiDebugWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16)), (u32*)(pcm_data[i].buff),2);//fill half first
-#else
- meiDMAWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16)), (u32*)(pcm_data[i].buff),((pcm_data[i].len/4)/2));//fill half first
-// meiDMAWrite_8((((u32)(pcm_data[i].LSW))+(((u32)(pcm_data[i].MSW))<<16)), (u32*)(pcm_data[i].buff),2);//fill half first
-#endif
- pcm_data[i].point=(pcm_data[i].len)/2;
-// pcm_data[i].point=8;
-#ifdef PCM_ACCESS_DEBUG
- meiDebugRead_16(pcm_start_addr+i*16+12, &temp, 1);
-#else
- meiDMARead_16(pcm_start_addr+i*16+12, &temp, 1);
-#endif
- temp = (temp &0xffff) + (((u32)(pcm_data[i].point))<<16);
-#ifdef PCM_ACCESS_DEBUG
- meiDebugWrite_16(pcm_start_addr+i*16+12,&temp, 1);//update wrindex
-#else
- meiDMAWrite_16(pcm_start_addr+i*16+12,&temp, 1);//update wrindex
-#endif
- }
- else{// rx channel
- pcm_data[i].point=0;
- }
- }
- break;
- case AMAZON_MEI_PCM_START_TIMER:
- /* GPTU timer 6 */
- /* enable the timer in the PMU */
- *(AMAZON_PMU_PWDCR) = (*(AMAZON_PMU_PWDCR))| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI;
- /* setup the GPTU for timer tick f_fpi == f_gptu*/
- *(AMAZON_GPTU_CLC) = 0x100;
- //reload value = fpi/(HZ * P), timer mode, Prescaler = 4 ( T6I = 000, T6BPS2 = 0)
- *(AMAZON_GPTU_CAPREL) = (int)(117500000/(lon*4));
- *(AMAZON_GPTU_T6CON) = 0x80C0;
-
- if (request_irq(AMAZON_TIMER6_INT, amazon_timer6_interrupt_MEI,0, "hrt", NULL)!=0){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n unable to register irq for hrt!!!");
-#endif
- return -1;
- }
- enable_irq(AMAZON_TIMER6_INT);
- break;
- case AMAZON_MEI_PCM_STOP_TIMER:
- disable_irq(AMAZON_TIMER6_INT);
- free_irq(AMAZON_TIMER6_INT, NULL);
- break;
- case AMAZON_MEI_PCM_CHECK:
- for(i=0;i<PCM_CHANNEL_NUM;i++){
- if(pcm_data[i].finish!=1)
- return 0;
- }
- for(i=0;i<PCM_CHANNEL_NUM/2;i++){
- j=0;
- while(1){
- if((pcm_data[i*2+1].buff[j]==0x0) && (pcm_data[i*2+1].buff[j+1]==0x1)&& (pcm_data[i*2+1].buff[j+2]==0x2))
- break;
- else
- j++;
- }
- printk("\n j=%d", j);
- temp=0;
- for(k=0;k<((PCM_BUFF_SIZE-j)/4);k++){
- if(memcmp(pcm_data[i*2].buff+k*4, pcm_data[i*2+1].buff+j+k*4, 4)!=0){
- temp++;
- printk("\n\n%2x %2x %2x %2x %2x %2x %2x %2x\n\n", *((u8*)(pcm_data[i*2].buff+k*4)), *((u8*)(pcm_data[i*2].buff+k*4+1)),*((u8*)(pcm_data[i*2].buff+k*4+2)),*((u8*)(pcm_data[i*2].buff+k*4+3)),*((u8*)(pcm_data[i*2+1].buff+j+k*4)),*((u8*)(pcm_data[i*2+1].buff+j+k*4+1)),*((u8*)(pcm_data[i*2+1].buff+j+k*4+2)),*((u8*)(pcm_data[i*2+1].buff+j+k*4+3)));
- break;
- }
- }
- if(temp!=0)
- printk("\n\n Channel pair %d not match: err32 %d\n\n", i, temp);
- else
- printk("\n\n Channel pair %d match\n\n", i);
- }
- for(i=0;i<PCM_CHANNEL_NUM;i++){
- if(i%2==1){//rx channel
-#ifdef PCM_ACCESS_DEBUG
- meiDebugRead_16(pcm_start_addr+i*16+12, &temp, 1);
-#else
- meiDMARead_16(pcm_start_addr+i*16+12, &temp, 1);
-#endif
- printk("\n\nRx channel %d: Overflow Bytes %d", i, (temp&0xffff));
- }
- else{//tx channel
-#ifdef PCM_ACCESS_DEBUG
- meiDebugRead_16(pcm_start_addr+i*16, &temp, 1);
-#else
- meiDMARead_16(pcm_start_addr+i*16, &temp, 1);
-#endif
- printk("\n\nElectra Err: %d",(temp&0xffff));
- }
- }
- //check electra overflow
-
- meierr=1;
- break;
- case AMAZON_MEI_PCM_GETDATA:
- copy_to_user(lon, pcm_data[1].buff, PCM_BUFF_SIZE);
- break;
- case AMAZON_MEI_PCM_GPIO:
- //gpio
-
- *AMAZON_GPIO_P0_DIR |=1<<15;
- *AMAZON_GPIO_P0_ALTSEL0 |=1<<15;
- *AMAZON_GPIO_P0_ALTSEL1 &=~(1<<15);
- *AMAZON_GPIO_P0_OD |=1<<15;
-
- /*GPIO 16 TDM_DI*/
- *AMAZON_GPIO_P1_DIR &=~1;
- *AMAZON_GPIO_P1_ALTSEL0 |=1;
- *AMAZON_GPIO_P1_ALTSEL1 &=~1;
-
- /*GPIO 17 TDM_DCL */
- *AMAZON_GPIO_P1_DIR|=0x02;
- *AMAZON_GPIO_P1_ALTSEL0|=0x02;
- *AMAZON_GPIO_P1_ALTSEL1 &=(u32)~0x02;
- *AMAZON_GPIO_P1_OD|=0x02;
-
- /*GPIO 18 TDM FSC*/
- *AMAZON_GPIO_P1_DIR|=0x04;
- *AMAZON_GPIO_P1_ALTSEL0|=0x04;
- *AMAZON_GPIO_P1_ALTSEL1 &=(u32)~0x04;
- *AMAZON_GPIO_P1_OD|=0x04;
- break;
-
-
-
- //for clearEoC
-#ifdef AMAZON_CLEAR_EOC
- case AMAZON_MEI_GET_EOC_LEN:
- while(1){
- current_clreoc = list_entry(clreoc_list.next, amazon_clreoc_pkt, list);
- if((current_clreoc->len)>0){
- copy_to_user((char *)lon, (char*)(&(current_clreoc->len)), 4);
- break;
- }
- else//wait for eoc data from higher layer
- interruptible_sleep_on(&wait_queue_clreoc);
- }
- break;
- case AMAZON_MEI_GET_EOC_DATA:
- current_clreoc = list_entry(clreoc_list.next, amazon_clreoc_pkt, list);
- if((current_clreoc->len)>0){
- copy_to_user((char*)lon, (char*)(current_clreoc->command), current_clreoc->len);
- meierr=1;
- list_del(clreoc_list.next); //remove and add to end of list
- current_clreoc->len = 0;
- list_add_tail(&(current_clreoc->list), &clreoc_list);
- }
- else
- meierr=-1;
- break;
- case AMAZON_MEI_EOC_SEND:
- copy_from_user((char *)(&debugrdwr), (char *)lon, sizeof(debugrdwr));
- eoc_skb = dev_alloc_skb(debugrdwr.iCount*4);
- if(eoc_skb==NULL){
- printk("\n\nskb alloc fail");
- break;
- }
-
- eoc_skb->len=debugrdwr.iCount*4;
- memcpy(skb_put(eoc_skb, debugrdwr.iCount*4), (char *)debugrdwr.buffer, debugrdwr.iCount*4);
-
- ifx_push_eoc(eoc_skb); //pass data to higher layer
- break;
-#endif //#ifdef AMAZON_CLEAR_EOC
- case AMAZON_MIB_LO_ATUC:
- do_gettimeofday(&time_now);
- if(lon&0x1){
- if((time_now.tv_sec-(mib_pflagtime.ATUC_PERF_LOSS_PTIME).tv_sec)>2){
- current_intvl->AtucPerfLos++;
- ATUC_PERF_LOSS++;
- CurrStatus.adslAtucCurrStatus = 2;
- }
- (mib_pflagtime.ATUC_PERF_LOSS_PTIME).tv_sec = time_now.tv_sec;
- }
- if(lon&0x2){
- if((time_now.tv_sec-(mib_pflagtime.ATUC_PERF_LOFS_PTIME).tv_sec)>2){
- current_intvl->AtucPerfLof++;
- ATUC_PERF_LOFS++;
- CurrStatus.adslAtucCurrStatus = 1;
- }
- (mib_pflagtime.ATUC_PERF_LOFS_PTIME).tv_sec = time_now.tv_sec;
- }
- if(!(lon&0x3))
- CurrStatus.adslAtucCurrStatus = 0;
- break;
- case AMAZON_MIB_LO_ATUR:
- do_gettimeofday(&time_now);
- if(lon&0x1){
- if((time_now.tv_sec-(mib_pflagtime.ATUR_PERF_LOSS_PTIME).tv_sec)>2){
- current_intvl->AturPerfLos++;
- ATUR_PERF_LOSS++;
- CurrStatus.adslAturCurrStatus = 2;
- }
- (mib_pflagtime.ATUR_PERF_LOSS_PTIME).tv_sec = time_now.tv_sec;
- }
- if(lon&0x2){
- if((time_now.tv_sec-(mib_pflagtime.ATUR_PERF_LOFS_PTIME).tv_sec)>2){
- current_intvl->AturPerfLof++;
- ATUR_PERF_LOFS++;
- CurrStatus.adslAturCurrStatus = 1;
- }
- (mib_pflagtime.ATUR_PERF_LOFS_PTIME).tv_sec = time_now.tv_sec;
- }
- if(lon&0x4){
- if((time_now.tv_sec-(mib_pflagtime.ATUR_PERF_LPR_PTIME).tv_sec)>2){
- current_intvl->AturPerfLpr++;
- ATUR_PERF_LPR++;
- CurrStatus.adslAturCurrStatus = 3;
- }
- (mib_pflagtime.ATUR_PERF_LPR_PTIME).tv_sec = time_now.tv_sec;
- }
- if(!(lon&0x7))
- CurrStatus.adslAturCurrStatus = 0;
- break;
- case AMAZON_MEI_DOWNLOAD:
- // DMA the boot code page(s)
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n start download pages");
-#endif
- for( boot_loop = 0; boot_loop < img_hdr->count; boot_loop++){
- if( img_hdr->page[boot_loop].p_size & BOOT_FLAG){
- page_size = meiGetPage( boot_loop, GET_PROG, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr);
- if( page_size > 0){
- meiDMAWrite(dest_addr, mei_arc_swap_buff, page_size);
- }
- }
- if( img_hdr->page[boot_loop].d_size & BOOT_FLAG){
- page_size = meiGetPage( boot_loop, GET_DATA, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr);
- if( page_size > 0){
- meiDMAWrite( dest_addr, mei_arc_swap_buff, page_size);
- }
- }
- }
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n pages downloaded");
-#endif
- break;
- //509221:tc.chen start
- case AMAZON_MEI_DEBUG_MODE:
- mei_debug_mode = lon;
- break;
- //509221:tc.chen end
- }
- return meierr;
-}
-
-
-////////////////////// Interrupt handler /////////////////////////////////////////////////////
-static void mei_interrupt_arcmsgav(int,void *,struct pt_regs *);
-static void mei_interrupt_arcmsgav(int int1, void * void0, struct pt_regs * regs)
-{
- u32 scratch;
- u32 fetchpage;
- u32 size;
- u32 dest_addr;
- u32 temp;
- int i;
-
- meiDebugRead(ARC_MEI_MAILBOXR, &scratch, 1);
- if(scratch & OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK)
- {
- if(showtime==1){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n Code Swap Request After ShowTime !!!");
-#endif
- }
- else{
-#ifdef AMAZON_MEI_DEBUG_ON
-// printk("\n\n Code Swap Request");
-#endif
- fetchpage = scratch & ~OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK;
- size = meiGetPage( fetchpage, GET_PROG, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr);
- if( size > 0)
- {
-#ifdef AMAZON_MEI_DEBUG_ON
-// printk(" : prom page num %d",fetchpage);
-#endif
- meiDMAWrite( dest_addr, mei_arc_swap_buff, size);
- }
-
- size = meiGetPage( fetchpage, GET_DATA, MAXSWAPSIZE, mei_arc_swap_buff, &dest_addr);
- if( size > 0)
- {
-#ifdef AMAZON_MEI_DEBUG_ON
-// printk(" : data page num %d",fetchpage);
-#endif
- meiDMAWrite( dest_addr, mei_arc_swap_buff, size);
- }
- }
- // Notify arc that mailbox read complete
- meiLongwordWrite(ARC_TO_MEI_INT, ARC_TO_MEI_MSGAV);
-
- // Tell ARC Codeswap is done
- meiLongwordWrite(MEI_TO_ARC_INT, MEI_TO_ARC_CS_DONE);
- asm("SYNC");
- i=0;
- while(i<WHILE_DELAY){
- meiLongwordRead(MEI_TO_ARC_INT, &temp);
- if((temp & MEI_TO_ARC_CS_DONE) ==0){
-#ifdef AMAZON_MEI_DEBUG_ON
-// printk("\n\n Code Swap Done");
-#endif
- break;
- }
- i++;
- if(i==WHILE_DELAY){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n MEI_TO_ARC_CS_DONE not cleared by ARC");
- //509221:tc.chen start
- if (!mei_debug_mode)
- {
- //printk("Reset Arc!\n");
- //printk("AdslInitStatsData.FullInitializationCount++\n");
- AdslInitStatsData.FullInitializationCount++;
- if (!showtime)
- {
- //printk("AdslInitStatsData.FailedFullInitializationCount++\n");
- AdslInitStatsData.FailedFullInitializationCount++;
- //printk("AdslInitStatsData.LINIT_Errors++\n");
- AdslInitStatsData.LINIT_Errors++;
- }
-
- wake_up_interruptible(&wait_queue_codeswap); // wait up ioctl reboot
- }
- //509221:tc.chen end
-#endif
- }
- }
- }
- else{ // normal message
-// printk("\n\n interrupt");
- meiMailboxRead(RxMessage, MSG_LENGTH);
- if(cmv_waiting==1){
- arcmsgav=1;
- cmv_waiting=0;
- wake_up_interruptible(&wait_queue_arcmsgav);
- }
- else{
- indicator_count++;
- memcpy((char *)Recent_indicator, (char *)RxMessage, MSG_LENGTH *2);
-#ifdef ARC_READY_ACK
- if(((RxMessage[0]&0xff0)>>4)==D2H_AUTONOMOUS_MODEM_READY_MSG){ //check ARC ready message
-
-#ifdef LOCK_RETRY
- if (reboot_lock)
- {
- reboot_lock = 0;
- up(&mei_sema); // allow cmv access
- }
-#else
- up(&mei_sema); // allow cmv access
-#endif
- reboot_flag=1;
-//#ifdef ADSL_LED_SUPPORT
-#if 0
- led_support_check=1;//adsl led for 1.1.2.7.1.1
- adsl_led_flash();//adsl led for 1.1.2.7.1.1
-#endif
- wake_up_interruptible(&wait_queue_reboot); // wait up ioctl reboot
- }
-#endif
- }
- }
-// meiLongwordWrite(ARC_TO_MEI_INT, ARC_TO_MEI_MSGAV);
- mask_and_ack_amazon_irq(AMAZON_MEI_INT);
- return;
-}
-
-// 603221:tc.chen start
-////////////////////////hdlc ////////////////
-
-// get hdlc status
-static unsigned int ifx_me_hdlc_status(void)
-{
- u16 CMVMSG[MSG_LENGTH];
- int ret;
-
- if (showtime!=1)
- return -ENETRESET;
-
- makeCMV_local(H2D_CMV_READ, STAT, 14, 0, 1, NULL,CMVMSG); //Get HDLC status
- ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG);
- if (ret != 0)
- {
- return -EIO;
- }
- return CMVMSG[4]&0x0F;
-}
-
-int ifx_me_is_resloved(int status)
-{
- u16 CMVMSG[MSG_LENGTH];
- int ret;
-
- if (status == ME_HDLC_MSG_QUEUED || status == ME_HDLC_MSG_SENT)
- return ME_HDLC_UNRESOLVED;
- if (status == ME_HDLC_IDLE)
- {
- makeCMV_local(H2D_CMV_READ, CNTL, 2, 0, 1, NULL,CMVMSG); //Get ME-HDLC Control
- ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG);
- if (ret != 0)
- {
- return IFX_POP_EOC_FAIL;
- }
- if (CMVMSG[4]&(1<<0))
- {
- return ME_HDLC_UNRESOLVED;
- }
-
- }
- return ME_HDLC_RESOLVED;
-}
-
-int _ifx_me_hdlc_send(unsigned char *hdlc_pkt,int len,int max_length)
-{
- int ret;
- u16 CMVMSG[MSG_LENGTH];
- u16 data=0;
- u16 pkt_len=len;
- if (pkt_len > max_length)
- {
- printk("Exceed maximum eoc message length\n");
- return -ENOBUFS;
- }
- //while(pkt_len > 0)
- {
- makeCMV_local(H2D_CMV_WRITE, INFO, 81, 0, (pkt_len+1)/2,(u16 *)hdlc_pkt,CMVMSG); //Write clear eoc message to ARC
- ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG);
- if (ret != 0)
- {
- return -EIO;
- }
-
- makeCMV_local(H2D_CMV_WRITE, INFO, 83, 2, 1,&pkt_len,CMVMSG); //Update tx message length
- ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG);
- if (ret != 0)
- {
- return -EIO;
- }
-
- data = (1<<0);
- makeCMV_local(H2D_CMV_WRITE, CNTL, 2, 0, 1,&data,CMVMSG); //Start to send
- ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG);
- if (ret != 0)
- {
- return -EIO;
- }
- return 0;
- }
-}
-
-static int ifx_me_hdlc_send(unsigned char *hdlc_pkt,int hdlc_pkt_len)
-{
- int hdlc_status=0;
- u16 CMVMSG[MSG_LENGTH];
- int max_hdlc_tx_length=0,ret=0,retry=0;
-
- while(retry<10)
- {
- hdlc_status = ifx_me_hdlc_status();
- if (ifx_me_is_resloved(hdlc_status)==ME_HDLC_RESOLVED) // arc ready to send HDLC message
- {
- makeCMV_local(H2D_CMV_READ, INFO, 83, 0, 1, NULL,CMVMSG); //Get Maximum Allowed HDLC Tx Message Length
- ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG);
- if (ret != 0)
- {
- return -EIO;
- }
- max_hdlc_tx_length = CMVMSG[4];
- ret = _ifx_me_hdlc_send(hdlc_pkt,hdlc_pkt_len,max_hdlc_tx_length);
- return ret;
- }
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(10);
- }
- return -EBUSY;
-}
-
-int ifx_mei_hdlc_read(char *hdlc_pkt,int max_hdlc_pkt_len)
-{
- u16 CMVMSG[MSG_LENGTH];
- int msg_read_len,ret=0,pkt_len=0,retry = 0;
-
- while(retry<10)
- {
- ret = ifx_me_hdlc_status();
- if (ret == ME_HDLC_RESP_RCVD)
- {
- int current_size=0;
- makeCMV_local(H2D_CMV_READ, INFO, 83, 3, 1, NULL,CMVMSG); //Get EoC packet length
- ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG);
- if (ret != 0)
- {
- return -EIO;
- }
-
- pkt_len = CMVMSG[4];
- if (pkt_len > max_hdlc_pkt_len)
- {
- ret = -ENOMEM;
- goto error;
- }
- while( current_size < pkt_len)
- {
- if (pkt_len - current_size >(MSG_LENGTH*2-8))
- msg_read_len = (MSG_LENGTH*2-8);
- else
- msg_read_len = pkt_len - (current_size);
- makeCMV_local(H2D_CMV_READ, INFO, 82, 0 + (current_size/2), (msg_read_len+1)/2, NULL,CMVMSG); //Get hdlc packet
- ret = mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG);
- if (ret != 0)
- {
- goto error;
- }
- memcpy(hdlc_pkt+current_size,&CMVMSG[4],msg_read_len);
- current_size +=msg_read_len;
- }
- ret = current_size;
- break;
- }else
- {
- ret = -ENODATA;
- }
-
- retry++;
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(10);
-
- }
- return ret;
-error:
-
- return ret;
-}
-
-////////////////////////hdlc ////////////////
-// 603221:tc.chen end
-
-/////////////////////// clearEoC, int ifx_pop_eoc(sk_buff * pkt) //////////
-int ifx_pop_eoc(struct sk_buff * pkt);
-int ifx_pop_eoc(struct sk_buff * pkt)
-{
- amazon_clreoc_pkt * current;
- if(showtime!=1){
- dev_kfree_skb(pkt);
- return IFX_POP_EOC_FAIL;
- }
- if((pkt->len)>clreoc_max_tx_len){
- dev_kfree_skb(pkt);
- return IFX_POP_EOC_FAIL;
- }
- current = list_entry(clreoc_list.next, amazon_clreoc_pkt, list);
- while(1){
- if(current->len==0){
- memcpy(current->command, pkt->data, pkt->len);
- current->len=pkt->len;
- break;
- }
- else{
- if((current->list).next==&clreoc_list){
- dev_kfree_skb(pkt);
- return IFX_POP_EOC_FAIL; //buffer full
- }
- current = list_entry((current->list).next,amazon_clreoc_pkt, list);
- }
- }
- wake_up_interruptible(&wait_queue_clreoc);
-
- dev_kfree_skb(pkt);
- return IFX_POP_EOC_DONE;
-}
-/* this is used in circular fifo mode */
-/*
-int ifx_pop_eoc(sk_buff * pkt);
-int ifx_pop_eoc(sk_buff * pkt)
-{
- int buff_space,i;
- if(showtime!=1)
- return IFX_POP_EOC_FAIL;
-
- if(clreoc_wr>=clreoc_rd)
- buff_space = (MEI_CLREOC_BUFF_SIZE-1)-(clreoc_wr - clreoc_rd);
- else
- buff_space = clreoc_rd - clreoc_wr - 1;
- if((pkt->len)>buff_space)
- return IFX_POP_EOC_FAIL;
-
- if((clreoc_wr+pkt->len)>MEI_CLREOC_BUFF_SIZE){
- memcpy((clreoc+clreoc_wr), pkt->data, ((clreoc_wr+pkt->len)-MEI_CLREOC_BUFF_SIZE+1));
- memcpy(clreoc, (pkt->data)+((clreoc_wr+pkt->len)-MEI_CLREOC_BUFF_SIZE+1), (pkt->len)-((clreoc_wr+pkt->len)-MEI_CLREOC_BUFF_SIZE+1));
- clreoc_wr=(clreoc_wr+pkt->len)-MEI_CLREOC_BUFF_SIZE;
- }
- else{
- memcpy((clreoc+clreoc_wr), pkt->data, pkt->len);
- if((clreoc_wr+pkt->len)=MEI_CLREOC_BUFF_SIZE)
- clreoc_wr=0;
- else
- clreoc_wr+=pkt->len;
- }
- wake_up_interruptible(&wait_queue_clreoc);
- return IFX_POP_EOC_DONE;
-}
-*/
-
-
-////////////////////////////////////////////////////////////////////////////
-//int amazon_mei_init_module (void);
-//void amazon_mei_cleanup_module (void);
-//int __init init_module (void);
-//void __exit cleanup_module (void);
-
-int __init amazon_mei_init_module(void)
-//int __init init_module(void)
-{
- struct proc_dir_entry *entry;
- int i;
-
-//dying gasp-start
-#ifdef IFX_DYING_GASP
-
-//000003:fchang Start
-#ifdef CONFIG_CPU_AMAZON_E
- //GPIO31 :dying gasp event indication
- // (1) logic high: dying gasp event is false (default)
- // (2) logic low: dying gasp event is true
- CLEAR_BIT((*((volatile u32 *)0xB0100B18)), 0x4);
- CLEAR_BIT((*((volatile u32 *)0xB0100B1c)), 0x4);
- CLEAR_BIT((*((volatile u32 *)0xB0100B20)), 0x4);
- SET_BIT((*((volatile u32 *)0xB0100B24)), 0x4);
- asm("SYNC");
-#else //000003:fchang End
-
- //GPIO31 :dying gasp event indication
- // (1) logic high: dying gasp event is false (default)
- // (2) logic low: dying gasp event is true
- CLEAR_BIT((*((volatile u32 *)0xB0100B48)), 0x8000);
- CLEAR_BIT((*((volatile u32 *)0xB0100B4C)), 0x8000);
- CLEAR_BIT((*((volatile u32 *)0xB0100B50)), 0x8000);
- SET_BIT((*((volatile u32 *)0xB0100B54)), 0x8000);
-#if 0
-//warning-led-start
-//GPIO 22
- SET_BIT ((*((volatile u32 *)0xB0100B48)), 0x40);
- CLEAR_BIT((*((volatile u32 *)0xB0100B4C)), 0x40);
- CLEAR_BIT((*((volatile u32 *)0xB0100B50)), 0x40);
- SET_BIT((*((volatile u32 *)0xB0100B54)), 0x40);
- CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //GPIO ON
- printk("LED ON ON ON ON ON ON.....");
-//warning-led-end
-#endif
- asm("SYNC");
-#endif //000003:fchang
-
-#endif //IFX_DYING_GASP
-//dying gasp -end
-
-
- reg_entry_t regs_temp[PROC_ITEMS] = // Items being debugged
- {
- /* { flag, name, description } */
- { &arcmsgav, "arcmsgav", "arc to mei message ", 0 },
- { &cmv_reply, "cmv_reply", "cmv needs reply", 0},
- { &cmv_waiting, "cmv_waiting", "waiting for cmv reply from arc", 0},
- { &indicator_count, "indicator_count", "ARC to MEI indicator count", 0},
- { &cmv_count, "cmv_count", "MEI to ARC CMVs", 0},
- { &reply_count, "reply_count", "ARC to MEI Reply", 0},
- { (int *)Recent_indicator, "Recent_indicator", "most recent indicator", 0},
- { (int *)8, "version", "version of firmware", 0},
- };
- memcpy((char *)regs, (char *)regs_temp, sizeof(regs_temp));
-
-
- //sema_init(&mei_sema, 0); // semaphore initialization, mutex
- sema_init(&mei_sema, 1); // semaphore initialization, mutex
-
- init_waitqueue_head(&wait_queue_arcmsgav); // for ARCMSGAV
- init_waitqueue_head(&wait_queue_codeswap); // for codeswap daemon
- init_waitqueue_head(&wait_queue_mibdaemon); // for mib daemon
- init_waitqueue_head(&wait_queue_reboot); // for ioctl reboot
- init_waitqueue_head(&wait_queue_clreoc); // for clreoc_wr function
- init_waitqueue_head(&wait_queue_loop_diagnostic); // for loop diagnostic function
-#ifdef ADSL_LED_SUPPORT
- init_waitqueue_head(&wait_queue_led); // adsl led for led function
- init_waitqueue_head(&wait_queue_led_polling); // adsl led for led function
- led_task.routine = adsl_led_flash_task; // adsl led for led function
- led_poll_init(); // adsl led for led function
-#endif //ADSL_LED_SUPPORT
-#ifdef IFX_DYING_GASP
- init_waitqueue_head(&wait_queue_dying_gasp); // IFX_DYING_GASP
- lop_poll_init(); // IFX_DYING_GASP
-#endif //IFX_DYING_GASP
-
- init_waitqueue_head(&wait_queue_uas_poll);//joelin 04/16/2005
- unavailable_seconds_poll_init();//joelin 04/16/2005
- memset(&mib_pflagtime, 0, (sizeof(mib_flags_pretime)));
-
- // initialize link list for intervals
- mei_mib = (amazon_mei_mib *)kmalloc((sizeof(amazon_mei_mib)*INTERVAL_NUM), GFP_KERNEL);
- if(mei_mib == NULL){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("kmalloc error for amazon_mei_mib\n\n");
-#endif
- return -1;
- }
- memset(mei_mib, 0, (sizeof(amazon_mei_mib)*INTERVAL_NUM));
- INIT_LIST_HEAD(&interval_list);
- for(i=0;i<INTERVAL_NUM;i++)
- list_add_tail(&(mei_mib[i].list), &interval_list);
- current_intvl = list_entry(interval_list.next, amazon_mei_mib, list);
- do_gettimeofday(&(current_intvl->start_time));
- // initialize clreoc list
- clreoc_pkt = (amazon_clreoc_pkt *)kmalloc((sizeof(amazon_clreoc_pkt)*CLREOC_BUFF_SIZE), GFP_KERNEL);
- if(clreoc_pkt == NULL){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("kmalloc error for clreoc_pkt\n\n");
-#endif
- return -1;
- }
- memset(clreoc_pkt, 0, (sizeof(amazon_clreoc_pkt)*CLREOC_BUFF_SIZE));
- INIT_LIST_HEAD(&clreoc_list);
- for(i=0;i<CLREOC_BUFF_SIZE;i++)
- list_add_tail(&(clreoc_pkt[i].list), &clreoc_list);
-
- memset(&AdslInitStatsData, 0, sizeof(AdslInitStatsData));
- if (register_chrdev(major, "amazon_mei", &mei_operations)!=0) {
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n unable to register major for amazon_mei!!!");
-#endif
- return -1;
- }
- if (request_irq(AMAZON_MEI_INT, mei_interrupt_arcmsgav,0, "amazon_mei_arcmsgav", NULL)!=0){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n unable to register irq for amazon_mei!!!");
-#endif
- return -1;
- }
-// disable_irq(AMAZON_MEI_INT);
- enable_irq(AMAZON_MEI_INT);
- // procfs
- meidir=proc_mkdir(MEI_DIRNAME, &proc_root);
- if ( meidir == NULL) {
-#ifdef AMAZON_MEI_DEBUG_ON
- printk(KERN_ERR ": can't create /proc/" MEI_DIRNAME "\n\n");
-#endif
- return(-ENOMEM);
- }
-
- for(i=0;i<NUM_OF_REG_ENTRY;i++) {
- entry = create_proc_entry(regs[i].name,
- S_IWUSR |S_IRUSR | S_IRGRP | S_IROTH,
- meidir);
- if(entry) {
- regs[i].low_ino = entry->low_ino;
- entry->proc_fops = &proc_operations;
- } else {
-#ifdef AMAZON_MEI_DEBUG_ON
- printk( KERN_ERR
- ": can't create /proc/" MEI_DIRNAME
- "/%s\n\n", regs[i].name);
-#endif
- return(-ENOMEM);
- }
- }
- ///////////////////////////////// register net device ////////////////////////////
- if(register_netdev(&phy_mei_net)!=0){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\n Register phy Device Failed.");
-#endif
- return -1;
- }
-/*
- if(register_netdev(&interleave_mei_net)!=0){
- printk("\n\n Register interleave Device Failed.");
- return -1;
- }
- if(register_netdev(&fast_mei_net)!=0){
- printk("\n\n Register fast Device Failed.");
- return -1;
- }
-*/
-#ifdef DFE_LOOPBACK
- mei_arc_swap_buff = (u32 *)kmalloc(MAXSWAPSIZE*4, GFP_KERNEL);
- if (mei_arc_swap_buff){
-#ifdef ARC_READY_ACK
- if(down_interruptible(&mei_sema)) //disable CMV access until ARC ready
- {
- return -ERESTARTSYS;
- }
-#ifdef LOCK_RETRY
- reboot_lock = 1;
-#endif
-#endif
- meiForceRebootAdslModem();
- kfree(mei_arc_swap_buff);
- }else{
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("cannot load image: no memory\n\n");
-#endif
- }
-#endif
-#ifdef IFX_SMALL_FOOTPRINT
- mib_poll_init();
-#endif
- return 0;
-}
-
-void __exit amazon_mei_cleanup_module(void)
-//void __exit cleanup_module(void)
-{
- int i;
-#ifdef ADSL_LED_SUPPORT
- stop_led_module=1; //wake up and clean led module
- led_support_check=0;//joelin , clear task
- showtime=0;//joelin,clear task
- //CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO ON
- firmware_support_led=0;//joelin ,clear task
- wake_up_interruptible(&wait_queue_led); //wake up and clean led module
- wake_up_interruptible(&wait_queue_led_polling); //wake up and clean led module
-#endif
- for(i=0;i<NUM_OF_REG_ENTRY;i++)
- remove_proc_entry(regs[i].name, meidir);
- remove_proc_entry(MEI_DIRNAME, &proc_root);
-
- disable_irq(AMAZON_MEI_INT);
- free_irq(AMAZON_MEI_INT, NULL);
- unregister_chrdev(major, "amazon_mei");
-
- kfree(mei_mib);
- kfree(clreoc_pkt);
-
- kfree(phy_mei_net.priv);
- unregister_netdev(&phy_mei_net);
-
- return;
-}
-#ifdef IFX_SMALL_FOOTPRINT
-
-
-int adsl_mib_poll(void *unused)
-{
- struct task_struct *tsk = current;
- int i=0;
- struct timeval time_now;
- struct timeval time_fini;
- u32 temp,temp2;
-
- amazon_mei_mib * mib_ptr;
-// u16 buff[MSG_LENGTH]__attribute__ ((aligned(4)));
- u16 * data=NULL; //used in makeCMV, to pass in payload when CMV set, ignored when CMV read.
-
- daemonize();
- strcpy(tsk->comm, "kmibpoll");
- sigfillset(&tsk->blocked);
-
- printk("Inside mib poll loop ...\n");
- i=0;
- while(1){
- if(i<MIB_INTERVAL)
- interruptible_sleep_on_timeout(&wait_queue_mibdaemon, ((MIB_INTERVAL-i)/(1000/HZ)));
- i=0;
- if(showtime==1){
-// printk("\n\n update mib");
-
- do_gettimeofday(&time_now);
- if(time_now.tv_sec - current_intvl->start_time.tv_sec>=900){
- if(current_intvl->list.next!=&interval_list){
- current_intvl = list_entry(current_intvl->list.next, amazon_mei_mib, list);
- do_gettimeofday(&(current_intvl->start_time));
- }
- else{
- mib_ptr = list_entry(interval_list.next, amazon_mei_mib, list);
- list_del(interval_list.next);
- memset(mib_ptr, 0, sizeof(amazon_mei_mib));
- list_add_tail(&(mib_ptr->list), &interval_list);
- if(current_intvl->list.next==&interval_list)
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nlink list error");
-#endif
- current_intvl = list_entry(current_intvl->list.next, amazon_mei_mib, list);
- do_gettimeofday(&(current_intvl->start_time));
- }
- }
-
- if(down_interruptible(&mei_sema))
- return -ERESTARTSYS;
-/*
- ATUC_PERF_LO_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 0 Index 0");
-#endif
- }
- else{
- if(RxMessage[4]&PLAM_LOS_FailureBit){
- current_intvl->AtucPerfLos++;
- ATUC_PERF_LOSS++;
- CurrStatus.adslAtucCurrStatus = 2;
- }
- if(RxMessage[4]&PLAM_LOF_FailureBit){
- current_intvl->AtucPerfLof++;
- ATUC_PERF_LOFS++;
- CurrStatus.adslAtucCurrStatus = 1;
- }
- if(!(RxMessage[4]&(PLAM_LOS_FailureBit|PLAM_LOF_FailureBit)))
- CurrStatus.adslAtucCurrStatus = 0;
- }
-*/
-
- if(showtime!=1)
- goto mib_poll_end;
- ATUC_PERF_ESS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 7 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4]-mib_pread.ATUC_PERF_ESS;
- if(temp>=0){
- current_intvl->AtucPerfEs+=temp;
- ATUC_PERF_ESS+=temp;
- mib_pread.ATUC_PERF_ESS = RxMessage[4];
- }
- else{
- current_intvl->AtucPerfEs+=0xffff-mib_pread.ATUC_PERF_ESS+RxMessage[4];
- ATUC_PERF_ESS+=0xffff-mib_pread.ATUC_PERF_ESS+RxMessage[4];
- mib_pread.ATUC_PERF_ESS = RxMessage[4];
- }
- }
-/*
- ATUR_PERF_LO_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 1 Index 0");
-#endif
- }
- else{
- if(RxMessage[4]&PLAM_LOS_FailureBit){
- current_intvl->AturPerfLos++;
- ATUR_PERF_LOSS++;
- CurrStatus.adslAturCurrStatus = 2;
- }
- if(RxMessage[4]&PLAM_LOF_FailureBit){
- current_intvl->AturPerfLof++;
- ATUR_PERF_LOFS++;
- CurrStatus.adslAturCurrStatus = 1;
- }
- if(RxMessage[4]&PLAM_LPR_FailureBit){
- current_intvl->AturPerfLpr++;
- ATUR_PERF_LPR++;
- CurrStatus.adslAturCurrStatus = 3;
- }
- if(!(RxMessage[4]&(PLAM_LOS_FailureBit|PLAM_LOF_FailureBit|PLAM_LPR_FailureBit)))
- CurrStatus.adslAturCurrStatus = 0;
- }
-*/
- if(showtime!=1)
- goto mib_poll_end;
- ATUR_PERF_ESS_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 33 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4]-mib_pread.ATUR_PERF_ESS;
- if(temp>=0){
- current_intvl->AturPerfEs+=temp;
- ATUR_PERF_ESS+=temp;
- mib_pread.ATUR_PERF_ESS = RxMessage[4];
- }
- else{
- current_intvl->AturPerfEs+=0xffff-mib_pread.ATUR_PERF_ESS+RxMessage[4];
- ATUR_PERF_ESS+= 0xffff-mib_pread.ATUR_PERF_ESS+RxMessage[4];
- mib_pread.ATUR_PERF_ESS=RxMessage[4];
- }
- }
- if(showtime!=1)
- goto mib_poll_end;
- // to update rx/tx blocks
- ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 20 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4];
- }
- if(showtime!=1)
- goto mib_poll_end;
- ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 21 Index 0");
-#endif
- }
- else{
- temp2 = RxMessage[4];
- }
- if((temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK)>=0){
- current_intvl->AturChanPerfRxBlk+=temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK;
- ATUR_CHAN_RECV_BLK+=temp + (temp2<<16) - mib_pread.ATUR_CHAN_RECV_BLK;
- mib_pread.ATUR_CHAN_RECV_BLK = temp + (temp2<<16);
- }
- else{
- current_intvl->AturChanPerfRxBlk+=0xffffffff - mib_pread.ATUR_CHAN_RECV_BLK +(temp + (temp2<<16));
- ATUR_CHAN_RECV_BLK+=0xffffffff - mib_pread.ATUR_CHAN_RECV_BLK +(temp + (temp2<<16));
- mib_pread.ATUR_CHAN_RECV_BLK = temp + (temp2<<16);
- }
- current_intvl->AturChanPerfTxBlk = current_intvl->AturChanPerfRxBlk;
- ATUR_CHAN_TX_BLK = ATUR_CHAN_RECV_BLK;
-/*
- ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS)
- printk("\n\nCMV fail, Group 7 Address 20 Index 0");
- else{
- if(RxMessage[4]){
- current_intvl->AturChanPerfTxBlk+=RxMessage[4];
- ATUR_CHAN_TX_BLK+=RxMessage[4];
- }
- }
- ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS)
- printk("\n\nCMV fail, Group 7 Address 21 Index 0");
- else{
- if(RxMessage[4]){
- current_intvl->AturChanPerfTxBlk+=(int)((RxMessage[4])<<16);
- ATUR_CHAN_TX_BLK+=(int)((RxMessage[4])<<16);
- }
- }
-*/
- if(chantype.interleave == 1){
- if(showtime!=1)
- goto mib_poll_end;
- ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 3 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUR_CHAN_CORR_BLK_INTL;
- if(temp>=0){
- current_intvl->AturChanPerfCorrBlk+=temp;
- ATUR_CHAN_CORR_BLK+=temp;
- mib_pread.ATUR_CHAN_CORR_BLK_INTL = RxMessage[4];
- }
- else{
- current_intvl->AturChanPerfCorrBlk+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_INTL +RxMessage[4];
- ATUR_CHAN_CORR_BLK+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_INTL +RxMessage[4];
- mib_pread.ATUR_CHAN_CORR_BLK_INTL = RxMessage[4];
- }
- }
- }
- else if(chantype.fast == 1){
- if(showtime!=1)
- goto mib_poll_end;
- ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 3 Index 1");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUR_CHAN_CORR_BLK_FAST;
- if(temp>=0){
- current_intvl->AturChanPerfCorrBlk+=temp;
- ATUR_CHAN_CORR_BLK+=temp;
- mib_pread.ATUR_CHAN_CORR_BLK_FAST = RxMessage[4];
- }
- else{
- current_intvl->AturChanPerfCorrBlk+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_FAST + RxMessage[4];
- ATUR_CHAN_CORR_BLK+=0xffff - mib_pread.ATUR_CHAN_CORR_BLK_FAST + RxMessage[4];
- mib_pread.ATUR_CHAN_CORR_BLK_FAST = RxMessage[4];
- }
- }
- }
-
- if(chantype.interleave == 1){
- if(showtime!=1)
- goto mib_poll_end;
- ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 2 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL;
- if(temp>=0){
- current_intvl->AturChanPerfUncorrBlk+=temp;
- ATUR_CHAN_UNCORR_BLK+=temp;
- mib_pread.ATUR_CHAN_UNCORR_BLK_INTL = RxMessage[4];
- }
- else{
- current_intvl->AturChanPerfUncorrBlk+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL + RxMessage[4];
- ATUR_CHAN_UNCORR_BLK+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_INTL + RxMessage[4];
- mib_pread.ATUR_CHAN_UNCORR_BLK_INTL = RxMessage[4];
- }
- }
- }
- else if(chantype.fast == 1){
- if(showtime!=1)
- goto mib_poll_end;
- ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 2 Index 1");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST;
- if(temp>=0){
- current_intvl->AturChanPerfUncorrBlk+=temp;
- ATUR_CHAN_UNCORR_BLK+=temp;
- mib_pread.ATUR_CHAN_UNCORR_BLK_FAST = RxMessage[4];
- }
- else{
- current_intvl->AturChanPerfUncorrBlk+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST + RxMessage[4];
- ATUR_CHAN_UNCORR_BLK+=0xffff - mib_pread.ATUR_CHAN_UNCORR_BLK_FAST + RxMessage[4];
- mib_pread.ATUR_CHAN_UNCORR_BLK_FAST = RxMessage[4];
- }
- }
- }
-
- //RFC-3440
-
-#ifdef AMAZON_MEI_MIB_RFC3440
- if(showtime!=1)
- goto mib_poll_end;
- ATUC_PERF_STAT_FASTR_FLAG_MAKECMV; //???
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 0 Address 0 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_FASTR;
- if(temp>=0){
- current_intvl->AtucPerfStatFastR+=temp;
- ATUC_PERF_STAT_FASTR+=temp;
- mib_pread.ATUC_PERF_STAT_FASTR = RxMessage[4];
- }
- else{
- current_intvl->AtucPerfStatFastR+=0xffff - mib_pread.ATUC_PERF_STAT_FASTR + RxMessage[4];
- ATUC_PERF_STAT_FASTR+=0xffff - mib_pread.ATUC_PERF_STAT_FASTR + RxMessage[4];
- mib_pread.ATUC_PERF_STAT_FASTR = RxMessage[4];
- }
- }
- if(showtime!=1)
- goto mib_poll_end;
- ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV; //???
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 0 Address 0 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_FAILED_FASTR;
- if(temp>=0){
- current_intvl->AtucPerfStatFailedFastR+=temp;
- ATUC_PERF_STAT_FAILED_FASTR+=temp;
- mib_pread.ATUC_PERF_STAT_FAILED_FASTR = RxMessage[4];
- }
- else{
- current_intvl->AtucPerfStatFailedFastR+=0xffff - mib_pread.ATUC_PERF_STAT_FAILED_FASTR + RxMessage[4];
- ATUC_PERF_STAT_FAILED_FASTR+=0xffff - mib_pread.ATUC_PERF_STAT_FAILED_FASTR + RxMessage[4];
- mib_pread.ATUC_PERF_STAT_FAILED_FASTR = RxMessage[4];
- }
- }
- if(showtime!=1)
- goto mib_poll_end;
- ATUC_PERF_STAT_SESL_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 8 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_SESL;
- if(temp>=0){
- current_intvl->AtucPerfStatSesL+=temp;
- ATUC_PERF_STAT_SESL+=temp;
- mib_pread.ATUC_PERF_STAT_SESL = RxMessage[4];
- }
- else{
- current_intvl->AtucPerfStatSesL+=0xffff - mib_pread.ATUC_PERF_STAT_SESL + RxMessage[4];
- ATUC_PERF_STAT_SESL+=0xffff - mib_pread.ATUC_PERF_STAT_SESL + RxMessage[4];
- mib_pread.ATUC_PERF_STAT_SESL = RxMessage[4];
- }
- }
- if(showtime!=1)
- goto mib_poll_end;
- ATUC_PERF_STAT_UASL_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 10 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUC_PERF_STAT_UASL;
- if(temp>=0){
- current_intvl->AtucPerfStatUasL+=temp;
- ATUC_PERF_STAT_UASL+=temp;
- mib_pread.ATUC_PERF_STAT_UASL = RxMessage[4];
- }
- else{
- current_intvl->AtucPerfStatUasL+=0xffff - mib_pread.ATUC_PERF_STAT_UASL + RxMessage[4];
- ATUC_PERF_STAT_UASL+=0xffff - mib_pread.ATUC_PERF_STAT_UASL + RxMessage[4];
- mib_pread.ATUC_PERF_STAT_UASL = RxMessage[4];
- }
- }
- if(showtime!=1)
- goto mib_poll_end;
- ATUR_PERF_STAT_SESL_FLAG_MAKECMV;
- if(meiCMV(TxMessage, YES_REPLY)!=MEI_SUCCESS){
-#ifdef AMAZON_MEI_DEBUG_ON
- printk("\n\nCMV fail, Group 7 Address 34 Index 0");
-#endif
- }
- else{
- temp = RxMessage[4] - mib_pread.ATUR_PERF_STAT_SESL;
- if(temp>=0){
- current_intvl->AtucPerfStatUasL+=temp;
- ATUC_PERF_STAT_UASL+=temp;
- mib_pread.ATUR_PERF_STAT_SESL = RxMessage[4];
- }
- else{
- current_intvl->AtucPerfStatUasL+=0xffff - mib_pread.ATUR_PERF_STAT_SESL + RxMessage[4];
- ATUC_PERF_STAT_UASL+=0xffff - mib_pread.ATUR_PERF_STAT_SESL + RxMessage[4];
- mib_pread.ATUR_PERF_STAT_SESL = RxMessage[4];
- }
- }
-
-#endif
-mib_poll_end:
- up(&mei_sema);
-
- do_gettimeofday(&time_fini);
- i = ((int)((time_fini.tv_sec-time_now.tv_sec)*1000)) + ((int)((time_fini.tv_usec-time_now.tv_usec)/1000)) ; //msec
- }//showtime==1
- }
-
-}
-int mib_poll_init(void)
-{
- printk("Starting mib_poll...\n");
-
- kernel_thread(adsl_mib_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGNAL);
- return 0;
-}
-#endif //IFX_SMALL_FOOTPRINT
-//EXPORT_NO_SYMBOLS;
-
-#ifdef ADSL_LED_SUPPORT
-// adsl led -start
-int led_status_on=0,led_need_to_flash=0;
-int led_current_flashing=0;
-unsigned long led_delay=0;
-static int led_poll(void *unused)
-{
- stop_led_module=0; //begin polling ...
- while(!stop_led_module){
- if ((!led_status_on)&&(!led_need_to_flash)) interruptible_sleep_on_timeout (&wait_queue_led_polling,1000); //10 seconds timeout for waiting wakeup
-// else printk("direct running task, no waiting");
- run_task_queue(&tq_ifx_led);//joelin task
-// printk("led and LOP polling...\n");
- }
- return 0;
-}
-static int led_poll_init(void)
-{
-// printk("Starting adsl led polling...\n");
-
-//warning-led-start
-// CLEAR_BIT((*((volatile u32 *)0xB0100B40)), 0x40); //Warning LED GPIO ON
-//warning-led-end
-
- kernel_thread(led_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGNAL);
- return 0;
-}
-
-int adsl_led_flash(void)
-{
- int i;
- if (!firmware_support_led) return 0; //joelin version check
-
- if (led_status_on == 0 && led_need_to_flash == 0)
- {
- queue_task(&led_task, &tq_ifx_led);//joelin task
- wake_up_interruptible(&wait_queue_led_polling); //wake up and clean led module
-// printk("queue Task 1...\n"); //joelin test
- }
- led_need_to_flash=1;//asking to flash led
-
- return 0;
-}
-
-int adsl_led_flash_task(void *ptr)
-{
-
- u16 one=1;
- u16 zero=0;
- u16 data=0x0600;
- int kernel_use=1;
- u16 CMVMSG[MSG_LENGTH];
-//adsl-led-start for >v1.1.2.7.1.1
-// printk("Task Running...\n"); //joelin test
- if ((firmware_support_led==2)&&(led_support_check))
- {
- led_support_check=0;
- data=0x0600;
- makeCMV_local(H2D_CMV_WRITE, INFO, 91, 0, 1, &data,CMVMSG); //configure GPIO9 GPIO10 as outputs
- mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG);
-
- makeCMV_local(H2D_CMV_WRITE, INFO, 91, 2, 1, &data,CMVMSG); //enable writing to bit 9 and bit10
- mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG);
-
- data=0x0a01;
- makeCMV_local(H2D_CMV_WRITE, INFO, 91, 4, 1, &data,CMVMSG); //use GPIO10 for TR68 .Enable and don't invert.
- mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG);
-
-#ifdef DATA_LED_ON_MODE
- data=0x0903;//tecom //use GPIO9 for TR68 data led .turn on.
-#else
- data=0x0900;
-#endif
- makeCMV_local(H2D_CMV_WRITE, INFO, 91, 5, 1, &data,CMVMSG); //use GPIO9 for TR68 data led .turn off.
- mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, CMVMSG);
-
- }
- if (!showtime) {led_need_to_flash=0; return 0;}
-//adsl-led-end for >v1.1.2.7.1.1
-
- if (led_status_on == 0 || led_need_to_flash == 1)
- {
-
- if (led_current_flashing==0)
- {
- if (firmware_support_led==1){//>1.1.2.3.1.1
- makeCMV_local(H2D_CMV_WRITE, INFO, 91, 0, 1, &one,CMVMSG); //flash
- mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &CMVMSG);
- }
- else if (firmware_support_led==2){//>1.1.2.7.1.1
- data=0x0901;//flash
- makeCMV_local(H2D_CMV_WRITE, INFO, 91, 5, 1, &data,CMVMSG); //use GPIO9 for TR68 data led .flash.
- mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &CMVMSG);
-
- }//(firmware_support_led==2)
- led_current_flashing = 1;//turn on led
- }
- led_status_on=1;
-
- do{//do nothing , waiting untill no data traffic
- led_need_to_flash=0;
- interruptible_sleep_on_timeout(&wait_queue_led, 25); //the time for LED Off , if no data traffic
- }while(led_need_to_flash==1);
-
- }else if (led_status_on == 1 && led_need_to_flash==0)
- {
- if (led_current_flashing==1)
- {//turn off led
- if (firmware_support_led==1){//>1.1.2.3.1.1
- makeCMV_local(H2D_CMV_WRITE, INFO, 91, 0, 1, &zero,CMVMSG);//off
- mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &CMVMSG);
- } //>1.1.2.3.1.1
- else if (firmware_support_led==2){//>1.1.2.7.1.1
-#ifdef DATA_LED_ON_MODE
- data=0x0903;//tecom //use GPIO9 for TR68 data led .turn on.
-#else
- data=0x0900;//off
-#endif
- makeCMV_local(H2D_CMV_WRITE, INFO, 91, 5, 1, &data,CMVMSG); //use GPIO9 for TR68 data led .off.
- mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_CMV_WINHOST, &CMVMSG);
-
- }//(firmware_support_led==2)
- led_status_on=0;
- led_current_flashing = 0;
- }
- }
-
- if (led_status_on == 1 || led_need_to_flash)
- {//led flash job on going or led need to flash
- queue_task(&led_task, &tq_ifx_led); //joelin task
-// printk("queue Task 2...\n"); //joelin test
- }
- return 0;
-}
-//joelin adsl led-end
-#else
-int adsl_led_flash(void)
-{
- return 0;
-}
-#endif //ADSL_LED_SUPPORT
-#ifdef IFX_DYING_GASP
-static int lop_poll(void *unused)
-{
-
- while(1)
- {
- interruptible_sleep_on_timeout(&wait_queue_dying_gasp, 1);
-#ifdef CONFIG_CPU_AMAZON_E //000003:fchang
- if(showtime&&((*((volatile u32 *)0xB0100B14))&0x4)==0x0) {//000003:fchang
-#else //000003:fchang
- if(showtime&&((*((volatile u32 *)0xB0100B44))&0x8000)==0x0) {
-#endif //CONFIG_CPU_AMAZON_E
- mei_ioctl((struct inode *)0,NULL, AMAZON_MEI_WRITEDEBUG, &lop_debugwr);
- printk("send dying gasp..\n");}
-
- }
- return 0;
- }
-static int lop_poll_init(void)
-{
-// printk("Starting LOP polling...\n");
- kernel_thread(lop_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGNAL);
- return 0;
-}
-
-#endif //IFX_DYING_GASP
-
-//joelin 04/16/2005-satrt
-static int unavailable_seconds_poll(void *unused)
-{
- while(1){
- interruptible_sleep_on_timeout (&wait_queue_uas_poll,100); //1 second timeout for waiting wakeup
- if (!showtime) unavailable_seconds++;
- }
- return 0;
-}
-static int unavailable_seconds_poll_init(void)
-{
-
- kernel_thread(unavailable_seconds_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGNAL);
- return 0;
-}
-
-
-//joelin 04/16/2005-end
-EXPORT_SYMBOL(meiDebugWrite);
-EXPORT_SYMBOL(ifx_pop_eoc);
-
-MODULE_LICENSE("GPL");
-
-module_init(amazon_mei_init_module);
-module_exit(amazon_mei_cleanup_module);
-
+++ /dev/null
-/**************************************************
- *
- * drivers/ifx/serial/ifx_ssc.c
- *
- * Driver for IFX_SSC serial ports
- *
- * Copyright (C) 2004 Infineon Technologies AG
- * Author Michael Schoenenborn (IFX COM TI BT)
- *
- */
-#define IFX_SSC_DRV_VERSION "0.2.1"
-/*
- **************************************************
- *
- * This driver was originally based on the INCA-IP driver, but due to
- * fundamental conceptual drawbacks there has been changed a lot.
- *
- * Based on INCA-IP driver Copyright (c) 2003 Gary Jennejohn <gj@denx.de>
- * Based on the VxWorks drivers Copyright (c) 2002, Infineon Technologies.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-// ### TO DO: general issues:
-// - power management
-// - interrupt handling (direct/indirect)
-// - pin/mux-handling (just overall concept due to project dependency)
-// - multiple instances capability
-// - slave functionality
-
-/*
- * Include section
- */
-#ifndef EXPORT_SYMTAB
-#define EXPORT_SYMTAB
-#endif
-
-#include <linux/config.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/timer.h>
-#include <linux/interrupt.h>
-#include <linux/major.h>
-#include <linux/string.h>
-#include <linux/fs.h>
-#include <linux/proc_fs.h>
-#include <linux/fcntl.h>
-#include <linux/ptrace.h>
-#include <linux/mm.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/slab.h>
-//#include <linux/poll.h>
-
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <asm/bitops.h>
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/version.h>
-
-#include <asm/amazon/amazon.h>
-#include <asm/amazon/irq.h>
-#include <asm/amazon/ifx_ssc_defines.h>
-#include <asm/amazon/ifx_ssc.h>
-
-#ifdef SSC_FRAME_INT_ENABLE
-#undef SSC_FRAME_INT_ENABLE
-#endif
-
-#define not_yet
-
-#define SPI_VINETIC
-
-/*
- * Deal with CONFIG_MODVERSIONS
- */
-#if CONFIG_MODVERSIONS==1
-# include <linux/modversions.h>
-#endif
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Michael Schoenenborn");
-MODULE_DESCRIPTION("IFX SSC driver");
-MODULE_SUPPORTED_DEVICE("ifx_ssc");
-MODULE_PARM(maj, "i");
-MODULE_PARM_DESC(maj, "Major device number");
-
-/* allow the user to set the major device number */
-static int maj = 0;
-
-
-/*
- * This is the per-channel data structure containing pointers, flags
- * and variables for the port. This driver supports a maximum of PORT_CNT.
- * isp is allocated in ifx_ssc_init() based on the chip version.
- */
-static struct ifx_ssc_port *isp;
-
-/* prototypes for fops */
-static ssize_t ifx_ssc_read(struct file *, char *, size_t, loff_t *);
-static ssize_t ifx_ssc_write(struct file *, const char *, size_t, loff_t *);
-//static unsigned int ifx_ssc_poll(struct file *, struct poll_table_struct *);
-int ifx_ssc_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
-int ifx_ssc_open(struct inode *, struct file *);
-int ifx_ssc_close(struct inode *, struct file *);
-
-/* other forward declarations */
-static unsigned int ifx_ssc_get_kernel_clk(struct ifx_ssc_port *info);
-static void ifx_ssc_rx_int(int, void *, struct pt_regs *);
-static void ifx_ssc_tx_int(int, void *, struct pt_regs *);
-static void ifx_ssc_err_int(int, void *, struct pt_regs *);
-#ifdef SSC_FRAME_INT_ENABLE
-static void ifx_ssc_frm_int(int, void *, struct pt_regs *);
-#endif
-static void tx_int(struct ifx_ssc_port *);
-static int ifx_ssc1_read_proc(char *, char **, off_t, int, int *, void *);
-static void ifx_gpio_init(void);
-/************************************************************************
- * Function declaration
- ************************************************************************/
-//interrupt.c
-extern unsigned int amazon_get_fpi_hz(void);
-extern void disable_amazon_irq(unsigned int irq_nr);
-extern void enable_amazon_irq(unsigned int irq_nr);
-extern void mask_and_ack_amazon_irq(unsigned int irq_nr);
-
-
-/*****************************************************************/
-typedef struct {
- int (*request)(unsigned int irq,
- void (*handler)(int, void *, struct pt_regs *),
- unsigned long irqflags,
- const char * devname,
- void *dev_id);
- void (*free)(unsigned int irq, void *dev_id);
- void (*enable)(unsigned int irq);
- void (*disable)(unsigned int irq);
- void (*clear)(unsigned int irq);
-} ifx_int_wrapper_t;
-
-static ifx_int_wrapper_t ifx_int_wrapper = {
- request: request_irq, // IM action: enable int
- free: free_irq, // IM action: disable int
- enable: enable_amazon_irq,
- disable: disable_amazon_irq,
- clear: mask_and_ack_amazon_irq,
- //end:
-};
-
-/* Fops-struct */
-static struct file_operations ifx_ssc_fops = {
- owner: THIS_MODULE,
- read: ifx_ssc_read, /* read */
- write: ifx_ssc_write, /* write */
-// poll: ifx_ssc_poll, /* poll */
- ioctl: ifx_ssc_ioctl, /* ioctl */
- open: ifx_ssc_open, /* open */
- release: ifx_ssc_close, /* release */
-};
-
-
-static inline unsigned int ifx_ssc_get_kernel_clk(struct ifx_ssc_port *info)
-{ // ATTENTION: This function assumes that the CLC register is set with the
- // appropriate value for RMC.
- unsigned int rmc;
-
- rmc = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_CLC) &
- IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
- if (rmc == 0){
- printk("ifx_ssc_get_kernel_clk rmc==0 \n");
- return (0);
- }
- return (amazon_get_fpi_hz() / rmc);
-}
-
-#ifndef not_yet
-#ifdef IFX_SSC_INT_USE_BH
-/*
- * This routine is used by the interrupt handler to schedule
- * processing in the software interrupt portion of the driver
- * (also known as the "bottom half"). This can be called any
- * number of times for any channel without harm.
- */
-static inline void
-ifx_ssc_sched_event(struct ifx_ssc_port *info, int event)
-{
- info->event |= 1 << event; /* remember what kind of event and who */
- queue_task(&info->tqueue, &tq_cyclades); /* it belongs to */
- mark_bh(CYCLADES_BH); /* then trigger event */
-} /* ifx_ssc_sched_event */
-
-
-/*
- * This routine is used to handle the "bottom half" processing for the
- * serial driver, known also the "software interrupt" processing.
- * This processing is done at the kernel interrupt level, after the
- * cy#/_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
- * is where time-consuming activities which can not be done in the
- * interrupt driver proper are done; the interrupt driver schedules
- * them using ifx_ssc_sched_event(), and they get done here.
- *
- * This is done through one level of indirection--the task queue.
- * When a hardware interrupt service routine wants service by the
- * driver's bottom half, it enqueues the appropriate tq_struct (one
- * per port) to the tq_cyclades work queue and sets a request flag
- * via mark_bh for processing that queue. When the time is right,
- * do_ifx_ssc_bh is called (because of the mark_bh) and it requests
- * that the work queue be processed.
- *
- * Although this may seem unwieldy, it gives the system a way to
- * pass an argument (in this case the pointer to the ifx_ssc_port
- * structure) to the bottom half of the driver. Previous kernels
- * had to poll every port to see if that port needed servicing.
- */
-static void
-do_ifx_ssc_bh(void)
-{
- run_task_queue(&tq_cyclades);
-} /* do_ifx_ssc_bh */
-
-static void
-do_softint(void *private_)
-{
- struct ifx_ssc_port *info = (struct ifx_ssc_port *) private_;
-
- if (test_and_clear_bit(Cy_EVENT_HANGUP, &info->event)) {
- wake_up_interruptible(&info->open_wait);
- info->flags &= ~(ASYNC_NORMAL_ACTIVE|
- ASYNC_CALLOUT_ACTIVE);
- }
- if (test_and_clear_bit(Cy_EVENT_OPEN_WAKEUP, &info->event)) {
- wake_up_interruptible(&info->open_wait);
- }
- if (test_and_clear_bit(Cy_EVENT_DELTA_WAKEUP, &info->event)) {
- wake_up_interruptible(&info->delta_msr_wait);
- }
- if (test_and_clear_bit(Cy_EVENT_WRITE_WAKEUP, &info->event)) {
- wake_up_interruptible(&tty->write_wait);
- }
-#ifdef Z_WAKE
- if (test_and_clear_bit(Cy_EVENT_SHUTDOWN_WAKEUP, &info->event)) {
- wake_up_interruptible(&info->shutdown_wait);
- }
-#endif
-} /* do_softint */
-#endif /* IFX_SSC_INT_USE_BH */
-#endif // not_yet
-
-inline static void
-rx_int(struct ifx_ssc_port *info)
-{
- int fifo_fill_lev, bytes_in_buf, i;
- unsigned long tmp_val;
- unsigned long *tmp_ptr;
- unsigned int rx_valid_cnt;
- /* number of words waiting in the RX FIFO */
- fifo_fill_lev = (READ_PERIPHERAL_REGISTER(info->mapbase +
- IFX_SSC_FSTAT) &
- IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >>
- IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
- // Note: There are always 32 bits in a fifo-entry except for the last
- // word of a contigous transfer block and except for not in rx-only
- // mode and CON.ENBV set. But for this case it should be a convention
- // in software which helps:
- // In tx or rx/tx mode all transfers from the buffer to the FIFO are
- // 32-bit wide, except for the last three bytes, which could be a
- // combination of 16- and 8-bit access.
- // => The whole block is received as 32-bit words as a contigous stream,
- // even if there was a gap in tx which has the fifo run out of data!
- // Just the last fifo entry *may* be partially filled (0, 1, 2 or 3 bytes)!
-
- /* free space in the RX buffer */
- bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
- // transfer with 32 bits per entry
- while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
- tmp_ptr = (unsigned long *)info->rxbuf_ptr;
- *tmp_ptr = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RB);
- info->rxbuf_ptr += 4;
- info->stats.rxBytes += 4;
- fifo_fill_lev --;
- bytes_in_buf -= 4;
- } // while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0))
- // now do the rest as mentioned in STATE.RXBV
- while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
- rx_valid_cnt = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) &
- IFX_SSC_STATE_RX_BYTE_VALID_MASK) >>
- IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
- if (rx_valid_cnt == 0) break;
- if (rx_valid_cnt > bytes_in_buf) {
- // ### TO DO: warning message: not block aligned data, other data
- // in this entry will be lost
- rx_valid_cnt = bytes_in_buf;
- }
- tmp_val = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RB);
-
- for (i=0; i<rx_valid_cnt; i++) {
- *info->rxbuf_ptr = (tmp_val >> ( 8 * (rx_valid_cnt - i-1))) & 0xff;
-/*
- *info->rxbuf_ptr = tmp_val & 0xff;
- tmp_val >>= 8;
-*/
- bytes_in_buf--;
-
-
- info->rxbuf_ptr++;
- }
- info->stats.rxBytes += rx_valid_cnt;
- } // while ((bytes_in_buf > 0) && (fifo_fill_lev > 0))
-
- // check if transfer is complete
- if (info->rxbuf_ptr >= info->rxbuf_end) {
- ifx_int_wrapper.disable(info->rxirq);
- /* wakeup any processes waiting in read() */
- wake_up_interruptible(&info->rwait);
- /* and in poll() */
- //wake_up_interruptible(&info->pwait);
- } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) &&
- (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RXCNT) == 0)) {
- // if buffer not filled completely and rx request done initiate new transfer
-/*
- if (info->rxbuf_end - info->rxbuf_ptr < 65536)
-*/
- if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
- WRITE_PERIPHERAL_REGISTER((info->rxbuf_end - info->rxbuf_ptr) <<
- IFX_SSC_RXREQ_RXCOUNT_OFFSET,
- info->mapbase + IFX_SSC_RXREQ);
- else
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET,
- info->mapbase + IFX_SSC_RXREQ);
- }
-} // rx_int
-
-inline static void
-tx_int(struct ifx_ssc_port *info)
-{
-
- int fifo_space, fill, i;
- fifo_space = ((READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_ID) &
- IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET) -
- ((READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_FSTAT) &
- IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >>
- IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
-
- if (fifo_space == 0)
- return;
-
- fill = info->txbuf_end - info->txbuf_ptr;
-
- if (fill > fifo_space * 4)
- fill = fifo_space * 4;
-
- for (i = 0; i < fill / 4; i++) {
- // at first 32 bit access
- WRITE_PERIPHERAL_REGISTER(*(UINT32 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
- info->txbuf_ptr += 4;
- }
-
- fifo_space -= fill / 4;
- info->stats.txBytes += fill & ~0x3;
- fill &= 0x3;
- if ((fifo_space > 0) & (fill > 1)) {
- // trailing 16 bit access
- WRITE_PERIPHERAL_REGISTER_16(*(UINT16 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
- info->txbuf_ptr += 2;
- info->stats.txBytes += 2;
- fifo_space --;
-/* added by bingtao */
- fill -=2;
- }
- if ((fifo_space > 0) & (fill > 0)) {
- // trailing 8 bit access
- WRITE_PERIPHERAL_REGISTER_8(*(UINT8 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
- info->txbuf_ptr ++;
- info->stats.txBytes ++;
-/*
- fifo_space --;
-*/
- }
-
- // check if transmission complete
- if (info->txbuf_ptr >= info->txbuf_end) {
- ifx_int_wrapper.disable(info->txirq);
- kfree(info->txbuf);
- info->txbuf = NULL;
- /* wake up any process waiting in poll() */
- //wake_up_interruptible(&info->pwait);
- }
-
-} // tx_int
-
-static void
-ifx_ssc_rx_int(int irq, void *dev_id, struct pt_regs *regs)
-{
- struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id;
- //WRITE_PERIPHERAL_REGISTER(IFX_SSC_R_BIT, info->mapbase + IFX_SSC_IRN_CR);
- rx_int(info);
-}
-
-static void
-ifx_ssc_tx_int(int irq, void *dev_id, struct pt_regs *regs)
-{
- struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id;
- //WRITE_PERIPHERAL_REGISTER(IFX_SSC_T_BIT, info->mapbase + IFX_SSC_IRN_CR);
- tx_int(info);
-}
-
-static void
-ifx_ssc_err_int(int irq, void *dev_id, struct pt_regs *regs)
-{
- struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id;
- unsigned int state;
- unsigned int write_back = 0;
- unsigned long flags;
-
-
- local_irq_save(flags);
- state = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE);
-
- if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
- info->stats.rxUnErr++;
- write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR;
- }
- if ((state & IFX_SSC_STATE_RX_OFL) != 0) {
- info->stats.rxOvErr++;
- write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR;
- }
- if ((state & IFX_SSC_STATE_TX_OFL) != 0) {
- info->stats.txOvErr++;
- write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR;
- }
- if ((state & IFX_SSC_STATE_TX_UFL) != 0) {
- info->stats.txUnErr++;
- write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR;
- }
-// if ((state & IFX_SSC_STATE_ABORT_ERR) != 0) {
-// info->stats.abortErr++;
-// write_back |= IFX_SSC_WHBSTATE_CLR_ABORT_ERROR;
-// }
- if ((state & IFX_SSC_STATE_MODE_ERR) != 0) {
- info->stats.modeErr++;
- write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR;
- }
-
- if (write_back)
- WRITE_PERIPHERAL_REGISTER(write_back,
- info->mapbase + IFX_SSC_WHBSTATE);
-
- local_irq_restore(flags);
-}
-
-#ifdef SSC_FRAME_INT_ENABLE
-static void
-ifx_ssc_frm_int(int irq, void *dev_id, struct pt_regs *regs)
-{
- // ### TO DO: wake up framing wait-queue in conjunction with batch execution
-}
-#endif
-
-static void
-ifx_ssc_abort(struct ifx_ssc_port *info)
-{
- unsigned long flags;
- bool enabled;
-
- local_irq_save(flags);
-
- // disable all int's
- ifx_int_wrapper.disable(info->rxirq);
- ifx_int_wrapper.disable(info->txirq);
- ifx_int_wrapper.disable(info->errirq);
-/*
- ifx_int_wrapper.disable(info->frmirq);
-*/
- local_irq_restore(flags);
-
- // disable SSC (also aborts a receive request!)
- // ### TO DO: Perhaps it's better to abort after the receiption of a
- // complete word. The disable cuts the transmission immediatly and
- // releases the chip selects. This could result in unpredictable
- // behavior of connected external devices!
- enabled = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE)
- & IFX_SSC_STATE_IS_ENABLED) != 0;
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE,
- info->mapbase + IFX_SSC_WHBSTATE);
-
-
- // flush fifos
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_XFCON_FIFO_FLUSH,
- info->mapbase + IFX_SSC_TXFCON);
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_XFCON_FIFO_FLUSH,
- info->mapbase + IFX_SSC_RXFCON);
-
- // free txbuf
- if (info->txbuf != NULL) {
- kfree(info->txbuf);
- info->txbuf = NULL;
- }
-
- // wakeup read process
- if (info->rxbuf != NULL)
- wake_up_interruptible(&info->rwait);
-
- // clear pending int's
- ifx_int_wrapper.clear(info->rxirq);
- ifx_int_wrapper.clear(info->txirq);
- ifx_int_wrapper.clear(info->errirq);
-/*
- ifx_int_wrapper.clear(info->frmirq);
-*/
-
- // clear error flags
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ALL_ERROR,
- info->mapbase + IFX_SSC_WHBSTATE);
-
- //printk("IFX SSC%d: Transmission aborted\n", info->port_nr);
- // enable SSC
- if (enabled)
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_ENABLE,
- info->mapbase + IFX_SSC_WHBSTATE);
-
-} // ifx_ssc_abort
-
-
-/*
- * This routine is called whenever a port is opened. It enforces
- * exclusive opening of a port and enables interrupts, etc.
- */
-int
-ifx_ssc_open(struct inode *inode, struct file * filp)
-{
- struct ifx_ssc_port *info;
- int line;
- int from_kernel = 0;
-
- if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) {
- from_kernel = 1;
- line = (int)inode;
- }
- else {
- line = MINOR(filp->f_dentry->d_inode->i_rdev);
- filp->f_op = &ifx_ssc_fops;
- }
-
- /* don't open more minor devices than we can support */
- if (line < 0 || line >= PORT_CNT)
- return -ENXIO;
-
- info = &isp[line];
-
- /* exclusive open */
- if (info->port_is_open != 0)
- return -EBUSY;
- info->port_is_open++;
-
- ifx_int_wrapper.disable(info->rxirq);
- ifx_int_wrapper.disable(info->txirq);
- ifx_int_wrapper.disable(info->errirq);
-/*
- ifx_int_wrapper.disable(info->frmirq);
-*/
-
- /* Flush and enable TX/RX FIFO */
- WRITE_PERIPHERAL_REGISTER((IFX_SSC_DEF_TXFIFO_FL <<
- IFX_SSC_XFCON_ITL_OFFSET) |
- IFX_SSC_XFCON_FIFO_FLUSH |
- IFX_SSC_XFCON_FIFO_ENABLE,
- info->mapbase + IFX_SSC_TXFCON);
- WRITE_PERIPHERAL_REGISTER((IFX_SSC_DEF_RXFIFO_FL <<
- IFX_SSC_XFCON_ITL_OFFSET) |
- IFX_SSC_XFCON_FIFO_FLUSH |
- IFX_SSC_XFCON_FIFO_ENABLE,
- info->mapbase + IFX_SSC_RXFCON);
-
-
- /* logically flush the software FIFOs */
- info->rxbuf_ptr = 0;
- info->txbuf_ptr = 0;
-
- /* clear all error bits */
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ALL_ERROR,
- info->mapbase + IFX_SSC_WHBSTATE);
-
- // clear pending interrupts
- ifx_int_wrapper.clear(info->rxirq);
- ifx_int_wrapper.clear(info->txirq);
- ifx_int_wrapper.clear(info->errirq);
-/*
- ifx_int_wrapper.clear(info->frmirq);
-*/
-
- // enable SSC
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_ENABLE,
- info->mapbase + IFX_SSC_WHBSTATE);
-
- MOD_INC_USE_COUNT;
-
- return 0;
-} /* ifx_ssc_open */
-EXPORT_SYMBOL(ifx_ssc_open);
-
-/*
- * This routine is called when a particular device is closed.
- */
-int
-ifx_ssc_close(struct inode *inode, struct file *filp)
-{
- struct ifx_ssc_port *info;
- int idx;
-
- if ((inode == (struct inode *)0) || (inode == (struct inode *)1))
- idx = (int)inode;
- else
- idx = MINOR(filp->f_dentry->d_inode->i_rdev);
-
- if (idx < 0 || idx >= PORT_CNT)
- return -ENXIO;
-
- info = &isp[idx];
- if (!info)
- return -ENXIO;
-
- // disable SSC
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE,
- info->mapbase + IFX_SSC_WHBSTATE);
-
- // call abort function to disable int's, flush fifos...
- ifx_ssc_abort(info);
-
- info->port_is_open --;
- MOD_DEC_USE_COUNT;
-
- return 0;
-} /* ifx_ssc_close */
-EXPORT_SYMBOL(ifx_ssc_close);
-
-/* added by bingtao */
-/* helper routine to handle reads from the kernel or user-space */
-/* info->rxbuf : never kfree and contains valid data */
-/* should be points to NULL after copying data !!! */
-static ssize_t
-ifx_ssc_read_helper_poll(struct ifx_ssc_port *info, char *buf, size_t len,
- int from_kernel)
-{
- ssize_t ret_val;
- unsigned long flags;
-
- if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
- return -EFAULT;
- local_irq_save(flags);
- info->rxbuf_ptr = info->rxbuf;
- info->rxbuf_end = info->rxbuf + len;
- local_irq_restore(flags);
-/* Vinetic driver always works in IFX_SSC_MODE_RXTX */
-/* TXRX in poll mode */
- while (info->rxbuf_ptr < info->rxbuf_end){
-/* This is the key point, if you don't check this condition
- kfree (NULL) will happen
- because tx only need write into FIFO, it's much fast than rx
- So when rx still waiting , tx already finish and release buf
-*/
- if (info->txbuf_ptr < info->txbuf_end) {
- tx_int(info);
- }
-
- rx_int(info);
- };
-
- ret_val = info->rxbuf_ptr - info->rxbuf;
- return (ret_val);
-} // ifx_ssc_read_helper_poll
-
-/* helper routine to handle reads from the kernel or user-space */
-/* info->rx_buf : never kfree and contains valid data */
-/* should be points to NULL after copying data !!! */
-static ssize_t
-ifx_ssc_read_helper(struct ifx_ssc_port *info, char *buf, size_t len,
- int from_kernel)
-{
- ssize_t ret_val;
- unsigned long flags;
- DECLARE_WAITQUEUE(wait, current);
-
- if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
- return -EFAULT;
- local_irq_save(flags);
- info->rxbuf_ptr = info->rxbuf;
- info->rxbuf_end = info->rxbuf + len;
- if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) {
- if ((info->txbuf == NULL) ||
- (info->txbuf != info->txbuf_ptr) ||
- (info->txbuf_end != len + info->txbuf)) {
- local_irq_restore(flags);
- printk("IFX SSC - %s: write must be called before calling "
- "read in combined RX/TX!\n", __FUNCTION__);
- return -EFAULT;
- }
- local_irq_restore(flags);
- /* should enable tx, right?*/
- tx_int(info);
- if (info->txbuf_ptr < info->txbuf_end){
- ifx_int_wrapper.enable(info->txirq);
- }
-
- ifx_int_wrapper.enable(info->rxirq);
- } else { // rx mode
- local_irq_restore(flags);
- if (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RXCNT) &
- IFX_SSC_RXCNT_TODO_MASK)
- return -EBUSY;
- ifx_int_wrapper.enable(info->rxirq);
- // rx request limited to ' bytes
-/*
- if (len < 65536)
-*/
- if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
- WRITE_PERIPHERAL_REGISTER(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET,
- info->mapbase + IFX_SSC_RXREQ);
- else
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET,
- info->mapbase + IFX_SSC_RXREQ);
- }
-
- __add_wait_queue(&info->rwait, &wait);
- set_current_state(TASK_INTERRUPTIBLE);
- // wakeup done in rx_int
-
- do {
- local_irq_save(flags);
- if (info->rxbuf_ptr >= info->rxbuf_end)
- break;
- local_irq_restore(flags);
-
-// if (filp->f_flags & O_NONBLOCK)
-// {
-// N = -EAGAIN;
-// goto out;
-// }
- if (signal_pending(current)) {
- ret_val = -ERESTARTSYS;
- goto out;
- }
- schedule();
- } while (1);
-
- ret_val = info->rxbuf_ptr - info->rxbuf; // should be equal to len
- local_irq_restore(flags);
-
- out:
- current->state = TASK_RUNNING;
- __remove_wait_queue(&info->rwait, &wait);
- return (ret_val);
-} // ifx_ssc_read_helper
-
-
-#if 0
-/* helper routine to handle reads from the kernel or user-space */
-/* appropriate in interrupt context */
-static ssize_t
-ifx_ssc_read_helper(struct ifx_ssc_port *info, char *buf, size_t len,
- int from_kernel)
-{
- ssize_t ret_val;
- unsigned long flags;
- DECLARE_WAITQUEUE(wait, current);
-
- if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
- return -EFAULT;
- local_irq_save(flags);
- info->rxbuf_ptr = info->rxbuf;
- info->rxbuf_end = info->rxbuf + len;
- if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) {
- if ((info->txbuf == NULL) ||
- (info->txbuf != info->txbuf_ptr) ||
- (info->txbuf_end != len + info->txbuf)) {
- local_irq_restore(flags);
- printk("IFX SSC - %s: write must be called before calling "
- "read in combined RX/TX!\n", __FUNCTION__);
- return -EFAULT;
- }
- local_irq_restore(flags);
- /* should enable tx, right?*/
- tx_int(info);
- if (!in_irq()){
- if (info->txbuf_ptr < info->txbuf_end){
- ifx_int_wrapper.enable(info->txirq);
- }
- ifx_int_wrapper.enable(info->rxirq);
- }
- } else { // rx mode
- local_irq_restore(flags);
- if (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RXCNT) &
- IFX_SSC_RXCNT_TODO_MASK)
- return -EBUSY;
- if (!in_irq()){
- ifx_int_wrapper.enable(info->rxirq);
- }
-
- if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
- WRITE_PERIPHERAL_REGISTER(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET,
- info->mapbase + IFX_SSC_RXREQ);
- else
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET,
- info->mapbase + IFX_SSC_RXREQ);
- }
- if (in_irq()){
- do {
- rx_int(info);
- if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) {
- tx_int(info);
- }
-
- if (info->rxbuf_ptr >= info->rxbuf_end)
- break;
- } while (1);
- ret_val = info->rxbuf_ptr - info->rxbuf;
- }else{
- __add_wait_queue(&info->rwait, &wait);
- set_current_state(TASK_INTERRUPTIBLE);
- // wakeup done in rx_int
-
- do {
- local_irq_save(flags);
- if (info->rxbuf_ptr >= info->rxbuf_end)
- break;
- local_irq_restore(flags);
-
- if (signal_pending(current)) {
- ret_val = -ERESTARTSYS;
- goto out;
- }
- schedule();
- } while (1);
-
- ret_val = info->rxbuf_ptr - info->rxbuf; // should be equal to len
- local_irq_restore(flags);
-
- out:
- current->state = TASK_RUNNING;
- __remove_wait_queue(&info->rwait, &wait);
- }
- return (ret_val);
-} // ifx_ssc_read_helper
-#endif
-
-/* helper routine to handle writes to the kernel or user-space */
-/* info->txbuf has two cases:
- * 1) return value < 0 (-EFAULT), not touched at all
- * 2) kfree and points to NULL in interrupt routine (but maybe later )
- */
-static ssize_t
-ifx_ssc_write_helper(struct ifx_ssc_port *info, const char *buf,
- size_t len, int from_kernel)
-{
- // check if in tx or tx/rx mode
- if (info->opts.modeRxTx == IFX_SSC_MODE_RX)
- return -EFAULT;
-
- info->txbuf_ptr = info->txbuf;
- info->txbuf_end = len + info->txbuf;
- /* start the transmission (not in rx/tx, see read helper) */
- if (info->opts.modeRxTx == IFX_SSC_MODE_TX) {
- tx_int(info);
- if (info->txbuf_ptr < info->txbuf_end){
- ifx_int_wrapper.enable(info->txirq);
- }
- }
- //local_irq_restore(flags);
- return len;
-}
-
-/*
- * kernel interfaces for read and write.
- * The caller must set port to: n for SSC<m> with n=m-1 (e.g. n=0 for SSC1)
- */
-ssize_t
-ifx_ssc_kread(int port, char *kbuf, size_t len)
-{
- struct ifx_ssc_port *info;
- ssize_t ret_val;
-
- if (port < 0 || port >= PORT_CNT)
- return -ENXIO;
-
- if (len == 0)
- return 0;
-
- info = &isp[port];
-
- // check if reception in progress
- if (info->rxbuf != NULL){
- printk("SSC device busy\n");
- return -EBUSY;
- }
-
- info->rxbuf = kbuf;
- if (info->rxbuf == NULL){
- printk("SSC device error\n");
- return -EINVAL;
- }
-
-/* changed by bingtao */
- /* change by TaiCheng */
- //if (!in_irq()){
- if (0){
- ret_val = ifx_ssc_read_helper(info, kbuf, len, 1);
- }else{
- ret_val = ifx_ssc_read_helper_poll(info, kbuf, len, 1);
- };
- info->rxbuf = NULL;
-
- // ### TO DO: perhaps warn if ret_val != len
- ifx_int_wrapper.disable(info->rxirq);
-
- return (ret_val);
-} // ifx_ssc_kread
-EXPORT_SYMBOL(ifx_ssc_kread);
-
-ssize_t
-ifx_ssc_kwrite(int port, const char *kbuf, size_t len)
-{
- struct ifx_ssc_port *info;
- ssize_t ret_val;
-
- if (port < 0 || port >= PORT_CNT)
- return -ENXIO;
-
- if (len == 0)
- return 0;
-
- info = &isp[port];
-
- // check if transmission in progress
- if (info->txbuf != NULL)
- return -EBUSY;
- info->txbuf = (char *)kbuf;
-
- ret_val = ifx_ssc_write_helper(info, info->txbuf, len, 1);
- if (ret_val < 0){
- info->txbuf = NULL;
- }
- return ret_val;
-}
-EXPORT_SYMBOL(ifx_ssc_kwrite);
-
-
-/*
- * user interfaces to read and write
- */
-static ssize_t
-ifx_ssc_read(struct file *filp, char *ubuf, size_t len, loff_t *off)
-{
- ssize_t ret_val;
- int idx;
- struct ifx_ssc_port *info;
-
-/*
- if (len == 0)
- return (0);
-*/
- idx = MINOR(filp->f_dentry->d_inode->i_rdev);
- info = &isp[idx];
-
- // check if reception in progress
- if (info->rxbuf != NULL)
- return -EBUSY;
-
- info->rxbuf = kmalloc(len+ 3, GFP_KERNEL);
- if (info->rxbuf == NULL)
- return -ENOMEM;
-
- ret_val = ifx_ssc_read_helper(info, info->rxbuf, len, 0);
- // ### TO DO: perhaps warn if ret_val != len
- if (copy_to_user((void*)ubuf, info->rxbuf, ret_val) != 0)
- ret_val = -EFAULT;
-
- ifx_int_wrapper.disable(info->rxirq);
-
- kfree(info->rxbuf);
- info->rxbuf = NULL;
- return (ret_val);
-} // ifx_ssc_read
-
-/*
- * As many bytes as we have free space for are copied from the user
- * into txbuf and the actual byte count is returned. The transmission is
- * always kicked off by calling the appropriate TX routine.
- */
-static ssize_t
-ifx_ssc_write(struct file *filp, const char *ubuf, size_t len, loff_t *off)
-{
- int idx;
- struct ifx_ssc_port *info;
- int ret_val;
-
- if (len == 0)
- return (0);
-
- idx = MINOR(filp->f_dentry->d_inode->i_rdev);
- info = &isp[idx];
-
- // check if transmission in progress
- if (info->txbuf != NULL)
- return -EBUSY;
-
- info->txbuf = kmalloc(len+ 3, GFP_KERNEL);
- if (info->txbuf == NULL)
- return -ENOMEM;
-
- ret_val = copy_from_user(info->txbuf, ubuf, len);
- if (ret_val == 0)
- ret_val = ifx_ssc_write_helper(info, info->txbuf, len, 0);
- else
- ret_val = -EFAULT;
- if (ret_val < 0) {
- kfree(info->txbuf); // otherwise will be done in ISR
- info->txbuf = NULL;
- }
- return (ret_val);
-} /* ifx_ssc_write */
-
-
-/*
- * ------------------------------------------------------------
- * ifx_ssc_ioctl() and friends
- * ------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- FUNC-NAME : ifx_ssc_frm_status_get
- LONG-NAME : framing status get
- PURPOSE : Get the actual status of the framing.
-
- PARAMETER : *info pointer to the port-specific structure ifx_ssc_port.
-
- RESULT : pointer to a structure ifx_ssc_frm_status which holds busy and
- count values.
-
- REMARKS : Returns a register value independent of framing is enabled or
- not! Changes structure inside of info, so the return value isn't
- needed at all, but could be used for simple access.
------------------------------------------------------------------------------*/
-static struct ifx_ssc_frm_status *
-ifx_ssc_frm_status_get(struct ifx_ssc_port *info)
-{
- unsigned long tmp;
-
- tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_SFSTAT);
- info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
- info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
- info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK)
- >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
- info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK)
- >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
- tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_SFCON);
- info->frm_status.EnIntAfterData =
- (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
- info->frm_status.EnIntAfterPause =
- (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
- return (&info->frm_status);
-} // ifx_ssc_frm_status_get
-
-
-/*-----------------------------------------------------------------------------
- FUNC-NAME : ifx_ssc_frm_control_get
- LONG-NAME : framing control get
- PURPOSE : Get the actual control values of the framing.
-
- PARAMETER : *info pointer to the port-specific structure ifx_ssc_port.
-
- RESULT : pointer to a structure ifx_ssc_frm_opts which holds control bits
- and count reload values.
-
- REMARKS : Changes structure inside of info, so the return value isn't
- needed at all, but could be used for simple access.
------------------------------------------------------------------------------*/
-static struct ifx_ssc_frm_opts *
-ifx_ssc_frm_control_get(struct ifx_ssc_port *info)
-{
- unsigned long tmp;
-
- tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_SFCON);
- info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
- info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK)
- >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
- info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK)
- >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
- info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK)
- >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
- info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK)
- >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
- info->frm_opts.StopAfterPause =
- (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0;
- return (&info->frm_opts);
-} // ifx_ssc_frm_control_get
-
-
-/*-----------------------------------------------------------------------------
- FUNC-NAME : ifx_ssc_frm_control_set
- LONG-NAME : framing control set
- PURPOSE : Set the actual control values of the framing.
-
- PARAMETER : *info pointer to the port-specific structure ifx_ssc_port.
-
- RESULT : pointer to a structure ifx_ssc_frm_opts which holds control bits
- and count reload values.
-
- REMARKS :
------------------------------------------------------------------------------*/
-static int
-ifx_ssc_frm_control_set(struct ifx_ssc_port *info)
-{
- unsigned long tmp;
-
- // check parameters
- if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX) ||
- (info->frm_opts.DataLength < 1) ||
- (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX) ||
- (info->frm_opts.PauseLength < 1) ||
- ((info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >>
- IFX_SSC_SFCON_PAUSE_DATA_OFFSET)) != 0 ) ||
- ((info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >>
- IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET)) != 0 ))
- return -EINVAL;
-
- // read interrupt bits (they're not changed here)
- tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_SFCON) &
- (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE |
- IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
-
- // set all values with respect to it's bit position (for data and pause
- // length set N-1)
- tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
- tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
- tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
- tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
- tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
- tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
-
- WRITE_PERIPHERAL_REGISTER(tmp, info->mapbase + IFX_SSC_SFCON);
-
- return 0;
-} // ifx_ssc_frm_control_set
-
-
-/*-----------------------------------------------------------------------------
- FUNC-NAME : ifx_ssc_rxtx_mode_set
- LONG-NAME : rxtx mode set
- PURPOSE : Set the transmission mode.
-
- PARAMETER : *info pointer to the port-specific structure ifx_ssc_port.
-
- RESULT : Returns error code
-
- REMARKS : Assumes that SSC not used (SSC disabled, device not opened yet
- or just closed)
------------------------------------------------------------------------------*/
-static int
-ifx_ssc_rxtx_mode_set(struct ifx_ssc_port *info, unsigned int val)
-{
- unsigned long tmp;
-
- // check parameters
- if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
- return -EINVAL;
- /*check BUSY and RXCNT*/
- if ( READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) & IFX_SSC_STATE_BUSY
- ||READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
- return -EBUSY;
- // modify
- tmp = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_CON) &
- ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
- WRITE_PERIPHERAL_REGISTER(tmp, info->mapbase + IFX_SSC_CON);
- info->opts.modeRxTx = val;
-/*
- printk(KERN_DEBUG "IFX SSC%d: Setting mode to %s%s\n",
- info->port_nr,
- ((val & IFX_SSC_CON_RX_OFF) == 0) ? "rx ":"",
- ((val & IFX_SSC_CON_TX_OFF) == 0) ? "tx":"");
-*/
- return 0;
-} // ifx_ssc_rxtx_mode_set
-
-void ifx_gpio_init(void)
-{
- u32 temp;
-/* set gpio pin p0.10(SPI_DIN) p0.11(SPI_DOUT) p0.12(SPI_CLK) p0.13(SPI_CS2) direction */
- temp = *(AMAZON_GPIO_P0_DIR) ;
- temp &= 0xFFFFFBFF;
- temp |= 0x3800;
- *(AMAZON_GPIO_P0_DIR) = temp;
-/* set port 0 alternate select register 0 */
- temp = *(AMAZON_GPIO_P0_ALTSEL0) ;
- temp &= 0xFFFFC3FF;
- temp |= 0x00001c00;
- *(AMAZON_GPIO_P0_ALTSEL0) = temp;
-
-/* set port 0 alternate select register 1 */
- temp = *(AMAZON_GPIO_P0_ALTSEL1) ;
- temp &= 0xFFFFC3FF;
- temp |= 0x00002000;
- *(AMAZON_GPIO_P0_ALTSEL1) = temp;
-
-/* set port 0 open drain mode register */
- temp = *(AMAZON_GPIO_P0_OD);
- temp |= 0x00003800; /* set output pin normal mode */
- *(AMAZON_GPIO_P0_OD)= temp;
-}
-
-/*
- * This routine intializes the SSC appropriately depending
- * on slave/master and full-/half-duplex mode.
- * It assumes that the SSC is disabled and the fifo's and buffers
- * are flushes later on.
- */
-static int
-ifx_ssc_sethwopts(struct ifx_ssc_port *info)
-{
- unsigned long flags, bits;
- struct ifx_ssc_hwopts *opts = &info->opts;
-
- /* sanity checks */
- if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH) ||
- (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH)) {
- printk("%s: sanity check failed\n", __FUNCTION__);
- return -EINVAL;
- }
- bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET;
- bits |= IFX_SSC_CON_ENABLE_BYTE_VALID;
-// if (opts->abortErrDetect)
-// bits |= IFX_SSC_CON_ABORT_ERR_CHECK;
- if (opts->rxOvErrDetect)
- bits |= IFX_SSC_CON_RX_OFL_CHECK;
- if (opts->rxUndErrDetect)
- bits |= IFX_SSC_CON_RX_UFL_CHECK;
- if (opts->txOvErrDetect)
- bits |= IFX_SSC_CON_TX_OFL_CHECK;
- if (opts->txUndErrDetect)
- bits |= IFX_SSC_CON_TX_UFL_CHECK;
- if (opts->loopBack)
- bits |= IFX_SSC_CON_LOOPBACK_MODE;
- if (opts->echoMode)
- bits |= IFX_SSC_CON_ECHO_MODE_ON;
- if (opts->headingControl)
- bits |= IFX_SSC_CON_MSB_FIRST;
- if (opts->clockPhase)
- bits |= IFX_SSC_CON_LATCH_THEN_SHIFT;
- if (opts->clockPolarity)
- bits |= IFX_SSC_CON_CLOCK_FALL;
- switch (opts->modeRxTx) {
- case IFX_SSC_MODE_TX:
- bits |= IFX_SSC_CON_RX_OFF;
- break;
- case IFX_SSC_MODE_RX:
- bits |= IFX_SSC_CON_TX_OFF;
- break;
- } // switch (opts->modeRxT)
- local_irq_save(flags);
- WRITE_PERIPHERAL_REGISTER(bits, info->mapbase + IFX_SSC_CON);
- WRITE_PERIPHERAL_REGISTER((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
- (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS),
- info->mapbase + IFX_SSC_GPOCON);
- //master mode
- if (opts->masterSelect){
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_MASTER_SELECT,info->mapbase + IFX_SSC_WHBSTATE);
- }else{
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT,info->mapbase + IFX_SSC_WHBSTATE);
- }
- // init serial framing
- WRITE_PERIPHERAL_REGISTER(0, info->mapbase + IFX_SSC_SFCON);
- /* set up the port pins */
- //check for general requirements to switch (external) pad/pin characteristics
- ifx_gpio_init();
- local_irq_restore(flags);
-
- return 0;
-} // ifx_ssc_sethwopts
-
-static int
-ifx_ssc_set_baud(struct ifx_ssc_port *info, unsigned int baud)
-{
- unsigned int ifx_ssc_clock;
- unsigned int br;
- unsigned long flags;
- bool enabled;
-
- ifx_ssc_clock = ifx_ssc_get_kernel_clk(info);
- if (ifx_ssc_clock ==0)
- return -EINVAL;
-
- local_irq_save(flags);
- /* have to disable the SSC to set the baudrate */
- enabled = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE)
- & IFX_SSC_STATE_IS_ENABLED) != 0;
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE,
- info->mapbase + IFX_SSC_WHBSTATE);
-
- // compute divider
- br = ((ifx_ssc_clock >> 1)/baud) - 1;
- asm("SYNC");
- if (br > 0xffff ||
- ((br == 0) &&
- ((READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE) &
- IFX_SSC_STATE_IS_MASTER) == 0))){
- local_irq_restore(flags);
- printk("%s: illegal baudrate %u\n", __FUNCTION__, baud);
- return -EINVAL;
- }
- WRITE_PERIPHERAL_REGISTER(br, info->mapbase + IFX_SSC_BR);
- if (enabled)
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_ENABLE,
- info->mapbase + IFX_SSC_WHBSTATE);
-
- local_irq_restore(flags);
- return 0;
-} // ifx_ssc_set_baud
-
-static int
-ifx_ssc_hwinit(struct ifx_ssc_port *info)
-{
- unsigned long flags;
- bool enabled;
-
- /* have to disable the SSC */
- enabled = (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE)
- & IFX_SSC_STATE_IS_ENABLED) != 0;
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE,
- info->mapbase + IFX_SSC_WHBSTATE);
-
- if (ifx_ssc_sethwopts(info) < 0)
- {
- printk("%s: setting the hardware options failed\n",
- __FUNCTION__);
- return -EINVAL;
- }
-
- if (ifx_ssc_set_baud(info, info->baud) < 0) {
- printk("%s: setting the baud rate failed\n", __FUNCTION__);
- return -EINVAL;
- }
- local_irq_save(flags);
- /* TX FIFO */
- WRITE_PERIPHERAL_REGISTER((IFX_SSC_DEF_TXFIFO_FL <<
- IFX_SSC_XFCON_ITL_OFFSET) |
- IFX_SSC_XFCON_FIFO_ENABLE,
- info->mapbase + IFX_SSC_TXFCON);
- /* RX FIFO */
- WRITE_PERIPHERAL_REGISTER((IFX_SSC_DEF_RXFIFO_FL <<
- IFX_SSC_XFCON_ITL_OFFSET) |
- IFX_SSC_XFCON_FIFO_ENABLE,
- info->mapbase + IFX_SSC_RXFCON);
- local_irq_restore(flags);
- if (enabled)
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_SET_ENABLE,
- info->mapbase + IFX_SSC_WHBSTATE);
- return 0;
-} // ifx_ssc_hwinit
-
-/*-----------------------------------------------------------------------------
- FUNC-NAME : ifx_ssc_batch_exec
- LONG-NAME :
- PURPOSE :
-
- PARAMETER : *info pointer to the port-specific structure ifx_ssc_port.
-
- RESULT : Returns error code
-
- REMARKS :
------------------------------------------------------------------------------*/
-static int
-ifx_ssc_batch_exec(struct ifx_ssc_port *info, struct ifx_ssc_batch_list *batch_anchor)
-{
- // ### TO DO: implement user space batch execution
- // first, copy the whole linked list from user to kernel space
- // save some hardware options
- // execute list
- // restore hardware options if selected
- return -EFAULT;
-} // ifx_ssc_batch_exec
-
-
-/*
- * This routine allows the driver to implement device-
- * specific ioctl's. If the ioctl number passed in cmd is
- * not recognized by the driver, it should return ENOIOCTLCMD.
- */
-int
-ifx_ssc_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
- unsigned long data)
-{
- struct ifx_ssc_port *info;
- int line, ret_val = 0;
- unsigned long flags;
- unsigned long tmp;
- int from_kernel = 0;
-
- if ((inode == (struct inode *)0) || (inode == (struct inode *)1))
- {
- from_kernel = 1;
- line = (int)inode;
- }
- else
- line = MINOR(filp->f_dentry->d_inode->i_rdev);
-
- /* don't use more minor devices than we can support */
- if (line < 0 || line >= PORT_CNT)
- return -ENXIO;
-
- info = &isp[line];
-
- switch (cmd) {
- case IFX_SSC_STATS_READ:
- /* data must be a pointer to a struct ifx_ssc_statistics */
- if (from_kernel)
- memcpy((void *)data, (void *)&info->stats,
- sizeof(struct ifx_ssc_statistics));
- else
- if (copy_to_user((void *)data,
- (void *)&info->stats,
- sizeof(struct ifx_ssc_statistics)))
- ret_val = -EFAULT;
- break;
- case IFX_SSC_STATS_RESET:
- /* just resets the statistics counters */
- memset((void *)&info->stats, 0, sizeof(struct ifx_ssc_statistics));
- break;
- case IFX_SSC_BAUD_SET:
- /* if the buffers are not empty then the port is */
- /* busy and we shouldn't change things on-the-fly! */
- if (!info->txbuf || !info->rxbuf ||
- (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE)
- & IFX_SSC_STATE_BUSY)) {
- ret_val = -EBUSY;
- break;
- }
- /* misuse flags */
- if (from_kernel)
- flags = *((unsigned long *)data);
- else
- if (copy_from_user((void *)&flags,
- (void *)data, sizeof(flags)))
- {
- ret_val = -EFAULT;
- break;
- }
- if (flags == 0)
- {
- ret_val = -EINVAL;
- break;
- }
- if (ifx_ssc_set_baud(info, flags) < 0)
- {
- ret_val = -EINVAL;
- break;
- }
- info->baud = flags;
- break;
- case IFX_SSC_BAUD_GET:
- if (from_kernel)
- *((unsigned int *)data) = info->baud;
- else
- if (copy_to_user((void *)data,
- (void *)&info->baud,
- sizeof(unsigned long)))
- ret_val = -EFAULT;
- break;
- case IFX_SSC_RXTX_MODE_SET:
- if (from_kernel)
- tmp = *((unsigned long *)data);
- else
- if (copy_from_user((void *)&tmp,
- (void *)data, sizeof(tmp))) {
- ret_val = -EFAULT;
- break;
- }
- ret_val = ifx_ssc_rxtx_mode_set(info, tmp);
- break;
- case IFX_SSC_RXTX_MODE_GET:
- tmp = READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_CON) &
- (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
- if (from_kernel)
- *((unsigned int *)data) = tmp;
- else
- if (copy_to_user((void *)data,
- (void *)&tmp,
- sizeof(tmp)))
- ret_val = -EFAULT;
- break;
-
- case IFX_SSC_ABORT:
- ifx_ssc_abort(info);
- break;
-
- case IFX_SSC_GPO_OUT_SET:
- if (from_kernel)
- tmp = *((unsigned long *)data);
- else
- if (copy_from_user((void *)&tmp,
- (void *)data, sizeof(tmp))) {
- ret_val = -EFAULT;
- break;
- }
- if (tmp > IFX_SSC_MAX_GPO_OUT)
- ret_val = -EINVAL;
- else
- WRITE_PERIPHERAL_REGISTER
- (1<<(tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
- info->mapbase + IFX_SSC_WHBGPOSTAT);
- break;
- case IFX_SSC_GPO_OUT_CLR:
- if (from_kernel)
- tmp = *((unsigned long *)data);
- else
- if (copy_from_user((void *)&tmp,
- (void *)data, sizeof(tmp))) {
- ret_val = -EFAULT;
- break;
- }
- if (tmp > IFX_SSC_MAX_GPO_OUT)
- ret_val = -EINVAL;
- else {
- WRITE_PERIPHERAL_REGISTER
- (1<<(tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
- info->mapbase + IFX_SSC_WHBGPOSTAT);
- }
- break;
- case IFX_SSC_GPO_OUT_GET:
- tmp = READ_PERIPHERAL_REGISTER
- (info->mapbase + IFX_SSC_GPOSTAT);
- if (from_kernel)
- *((unsigned int *)data) = tmp;
- else
- if (copy_to_user((void *)data,
- (void *)&tmp,
- sizeof(tmp)))
- ret_val = -EFAULT;
- break;
- case IFX_SSC_FRM_STATUS_GET:
- ifx_ssc_frm_status_get(info);
- if (from_kernel)
- memcpy((void *)data, (void *)&info->frm_status,
- sizeof(struct ifx_ssc_frm_status));
- else
- if (copy_to_user((void *)data,
- (void *)&info->frm_status,
- sizeof(struct ifx_ssc_frm_status)))
- ret_val = -EFAULT;
- break;
- case IFX_SSC_FRM_CONTROL_GET:
- ifx_ssc_frm_control_get(info);
- if (from_kernel)
- memcpy((void *)data, (void *)&info->frm_opts,
- sizeof(struct ifx_ssc_frm_opts));
- else
- if (copy_to_user((void *)data,
- (void *)&info->frm_opts,
- sizeof(struct ifx_ssc_frm_opts)))
- ret_val = -EFAULT;
- break;
- case IFX_SSC_FRM_CONTROL_SET:
- if (from_kernel)
- memcpy((void *)&info->frm_opts, (void *)data,
- sizeof(struct ifx_ssc_frm_opts));
- else
- if (copy_to_user((void *)&info->frm_opts,
- (void *)data,
- sizeof(struct ifx_ssc_frm_opts))){
- ret_val = -EFAULT;
- break;
- }
- ret_val = ifx_ssc_frm_control_set(info);
- break;
- case IFX_SSC_HWOPTS_SET:
- /* data must be a pointer to a struct ifx_ssc_hwopts */
- /* if the buffers are not empty then the port is */
- /* busy and we shouldn't change things on-the-fly! */
- if (!info->txbuf || !info->rxbuf ||
- (READ_PERIPHERAL_REGISTER(info->mapbase + IFX_SSC_STATE)
- & IFX_SSC_STATE_BUSY)) {
- ret_val = -EBUSY;
- break;
- }
- if (from_kernel)
- memcpy((void *)&info->opts, (void *)data,
- sizeof(struct ifx_ssc_hwopts));
- else
- if (copy_from_user((void *)&info->opts,
- (void *)data,
- sizeof(struct ifx_ssc_hwopts)))
- {
- ret_val = -EFAULT;
- break;
- }
- if (ifx_ssc_hwinit(info) < 0)
- {
- ret_val = -EIO;
- }
- break;
- case IFX_SSC_HWOPTS_GET:
- /* data must be a pointer to a struct ifx_ssc_hwopts */
- if (from_kernel)
- memcpy((void *)data, (void *)&info->opts,
- sizeof(struct ifx_ssc_hwopts));
- else
- if (copy_to_user((void *)data,
- (void *)&info->opts,
- sizeof(struct ifx_ssc_hwopts)))
- ret_val = -EFAULT;
- break;
- default:
- ret_val = -ENOIOCTLCMD;
- }
-
- return ret_val;
-} /* ifx_ssc_ioctl */
-EXPORT_SYMBOL(ifx_ssc_ioctl);
-
-///* the poll routine */
-//static unsigned int
-//ifx_ssc_poll(struct file *filp, struct poll_table_struct *pts)
-//{
-// int unit = MINOR(filp->f_dentry->d_inode->i_rdev);
-// struct ifx_ssc_port *info;
-// unsigned int mask = 0;
-// int spc;
-//
-// info = &isp[unit];
-//
-// /* add event to the wait queues */
-// /* DO NOT FORGET TO DO A WAKEUP ON THESE !!!! */
-// poll_wait(filp, &info->pwait, pts);
-//
-// /* are there bytes in the RX SW-FIFO? */
-// if (info->rxrp != info->rxwp)
-// mask |= POLLIN | POLLRDNORM;
-//
-// /* free space in the TX SW-FIFO */
-// spc = info->txrp - info->txwp - 1;
-// if (spc < 0)
-// spc += TX_BUFSIZE;
-//#ifdef IFX_SSC_USEDMA
-// /* writing always works, except in the DMA case when all descriptors */
-// /* are used up */
-// if (unit == 1 && info->dma_freecnt == 0)
-// spc = 0;
-//#endif
-// if (spc > 0)
-// mask |= POLLOUT | POLLWRNORM;
-//
-// return (mask);
-//}
-
-static int
-ifx_ssc1_read_proc(char *page, char **start, off_t offset, int count, int *eof, void *data)
-{
- int off = 0;
- unsigned long flags;
-
- /* don't want any interrupts here */
- save_flags(flags);
- cli();
-
-
- /* print statistics */
- off += sprintf(page+off, "Statistics for Infineon Synchronous Serial Controller SSC1\n");
- off += sprintf(page+off, "RX overflow errors %d\n", isp[0].stats.rxOvErr);
- off += sprintf(page+off, "RX underflow errors %d\n", isp[0].stats.rxUnErr);
- off += sprintf(page+off, "TX overflow errors %d\n", isp[0].stats.txOvErr);
- off += sprintf(page+off, "TX underflow errors %d\n", isp[0].stats.txUnErr);
- off += sprintf(page+off, "Abort errors %d\n", isp[0].stats.abortErr);
- off += sprintf(page+off, "Mode errors %d\n", isp[0].stats.modeErr);
- off += sprintf(page+off, "RX Bytes %d\n", isp[0].stats.rxBytes);
- off += sprintf(page+off, "TX Bytes %d\n", isp[0].stats.txBytes);
-
- restore_flags (flags); /* XXXXX */
- *eof = 1;
- return (off);
-}
-
-
-/*
- * This routine prints out the appropriate serial driver version number
- */
-static inline void
-show_version(void)
-{
-#if 0
- printk("Infineon Technologies Synchronous Serial Controller (SSC) driver\n"
- " version %s - built %s %s\n", IFX_SSC_DRV_VERSION, __DATE__, __TIME__);
-#endif
-} /* show_version */
-
-
-/*
- * Due to the fact that a port can be dynamically switched between slave
- * and master mode using an IOCTL the hardware is not initialized here,
- * but in ifx_ssc_hwinit() as a result of an IOCTL.
- */
-int __init
-ifx_ssc_init(void)
-{
- struct ifx_ssc_port *info;
- int i, nbytes;
- unsigned long flags;
- int ret_val;
-
- // ### TO DO: dynamic port count evaluation due to pin multiplexing
-
- ret_val = -ENOMEM;
- nbytes = PORT_CNT * sizeof(struct ifx_ssc_port);
- isp = (struct ifx_ssc_port *)kmalloc(nbytes, GFP_KERNEL);
- if (isp == NULL)
- {
- printk("%s: no memory for isp\n", __FUNCTION__);
- return (ret_val);
- }
- memset(isp, 0, nbytes);
-
- show_version();
-
- /* register the device */
- ret_val = -ENXIO;
-/*
- i = maj;
-*/
- if ((i = register_chrdev(maj, "ssc", &ifx_ssc_fops)) < 0)
- {
- printk("Unable to register major %d for the Infineon SSC\n", maj);
- if (maj == 0){
- goto errout;
- }
- else{
- maj = 0;
- if ((i = register_chrdev(maj, "ssc", &ifx_ssc_fops)) < 0)
- {
- printk("Unable to register major %d for the Infineon SSC\n", maj);
- goto errout;
- }
- }
- }
- if (maj == 0) maj = i;
- //printk("registered major %d for Infineon SSC\n", maj);
-
- /* set default values in ifx_ssc_port */
- for (i = 0; i < PORT_CNT; i++) {
- info = &isp[i];
- info->port_nr = i;
- /* default values for the HwOpts */
- info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT;
- info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT;
- info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT;
- info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT;
- info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT;
- info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK;
- info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE;
- info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA;
- info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY;
- info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE;
- info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL;
- info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH;
- info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX;
- info->opts.gpoCs = IFX_SSC_DEF_GPO_CS;
- info->opts.gpoInv = IFX_SSC_DEF_GPO_INV;
- info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE;
- info->baud = IFX_SSC_DEF_BAUDRATE;
- info->rxbuf = NULL;
- info->txbuf = NULL;
- /* values specific to SSC1 */
- if (i == 0) {
- info->mapbase = AMAZON_SSC_BASE_ADD_0;
- // ### TO DO: power management
-
- // setting interrupt vectors
- info->txirq = IFX_SSC_TIR;
- info->rxirq = IFX_SSC_RIR;
- info->errirq = IFX_SSC_EIR;
-/*
- info->frmirq = IFX_SSC_FIR;
-*/
- }
- /* activate SSC */
- /* CLC.DISS = 0 */
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, info->mapbase + IFX_SSC_CLC);
-
-// ### TO DO: multiple instances
-
- init_waitqueue_head(&info->rwait);
- //init_waitqueue_head(&info->pwait);
-
- local_irq_save(flags);
-
- // init serial framing register
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_DEF_SFCON, info->mapbase + IFX_SSC_SFCON);
-
- /* try to get the interrupts */
- // ### TO DO: interrupt handling with multiple instances
- ret_val = ifx_int_wrapper.request(info->txirq, ifx_ssc_tx_int,
- 0, "ifx_ssc_tx", info);
- if (ret_val){
- printk("%s: unable to get irq %d\n", __FUNCTION__,
- info->txirq);
- local_irq_restore(flags);
- goto errout;
- }
- ret_val = ifx_int_wrapper.request(info->rxirq, ifx_ssc_rx_int,
- 0, "ifx_ssc_rx", info);
- if (ret_val){
- printk("%s: unable to get irq %d\n", __FUNCTION__,
- info->rxirq);
- local_irq_restore(flags);
- goto irqerr;
- }
- ret_val = ifx_int_wrapper.request(info->errirq, ifx_ssc_err_int,
- 0, "ifx_ssc_err", info);
- if (ret_val){
- printk("%s: unable to get irq %d\n", __FUNCTION__,
- info->errirq);
- local_irq_restore(flags);
- goto irqerr;
- }
-/*
- ret_val = ifx_int_wrapper.request(info->frmirq, ifx_ssc_frm_int,
- 0, "ifx_ssc_frm", info);
- if (ret_val){
- printk("%s: unable to get irq %d\n", __FUNCTION__,
- info->frmirq);
- local_irq_restore(flags);
- goto irqerr;
- }
-
-*/
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_DEF_IRNEN, info->mapbase + IFX_SSC_IRN_EN);
-
- local_irq_restore(flags);
- } // for (i = 0; i < PORT_CNT; i++)
-
- /* init the SSCs with default values */
- for (i = 0; i < PORT_CNT; i++)
- {
- info = &isp[i];
- if (ifx_ssc_hwinit(info) < 0)
- {
- printk("%s: hardware init failed for port %d\n",
- __FUNCTION__, i);
- goto irqerr;
- }
- }
-
- /* register /proc read handler */
- // ### TO DO: multiple instances
- /* for SSC1, which is always present */
- create_proc_read_entry("driver/ssc1", 0, NULL, ifx_ssc1_read_proc, NULL);
- return 0;
-
-irqerr:
- // ### TO DO: multiple instances
- ifx_int_wrapper.free(isp[0].txirq,&isp[0]);
- ifx_int_wrapper.free(isp[0].rxirq,&isp[0]);
- ifx_int_wrapper.free(isp[0].errirq,&isp[0]);
-/*
- ifx_int_wrapper.free(isp[0].frmirq, &isp[0]);
-*/
-errout:
- /* free up any allocated memory in the error case */
- kfree(isp);
- return (ret_val);
-} /* ifx_ssc_init */
-
-
-void
-ifx_ssc_cleanup_module(void)
-{
- int i;
-
- /* free up any allocated memory */
- for (i = 0; i < PORT_CNT; i++)
- {
- /* disable the SSC */
- WRITE_PERIPHERAL_REGISTER(IFX_SSC_WHBSTATE_CLR_ENABLE,isp[i].mapbase + IFX_SSC_WHBSTATE);
- /* free the interrupts */
- ifx_int_wrapper.free(isp[i].txirq, &isp[i]);
- ifx_int_wrapper.free(isp[i].rxirq, &isp[i]);
- ifx_int_wrapper.free(isp[i].errirq, &isp[i]);
-/*
- ifx_int_wrapper.free(isp[i].frmirq, &isp[i]);
-
- if (isp[i].rxbuf != NULL)
- kfree(isp[i].rxbuf);
- if (isp[i].txbuf != NULL)
- kfree(isp[i].txbuf);
-*/
- }
- kfree(isp);
- /* unregister the device */
- if (unregister_chrdev(maj, "ssc"))
- {
- printk("Unable to unregister major %d for the SSC\n", maj);
- }
- /* delete /proc read handler */
- remove_proc_entry("driver/ssc1", NULL);
- remove_proc_entry("driver/ssc2", NULL);
-} /* ifx_ssc_cleanup_module */
-
-module_exit(ifx_ssc_cleanup_module);
-
-/* Module entry-points */
-module_init(ifx_ssc_init);
-
-#ifndef MODULE
-static int __init
-ifx_ssc_set_maj(char *str)
-{
- maj = simple_strtol(str, NULL, 0);
- return 1;
-}
-__setup("ssc_maj=", ifx_ssc_set_maj);
-#endif /* !MODULE */
-
-#define AMAZON_SSC_EMSG(fmt,arg...) printk("%s: "fmt,__FUNCTION__, ##arg)
-/* Brief: chip select enable
- */
-inline int amazon_ssc_cs_low(u32 pin)
-{
- int ret=0;
- if ((ret=ifx_ssc_ioctl((struct inode *)0, NULL,IFX_SSC_GPO_OUT_CLR, (unsigned long)&pin))){
- AMAZON_SSC_EMSG("clear CS %d fails\n",pin);
- }
- wmb();
- return ret;
-}
-EXPORT_SYMBOL(amazon_ssc_cs_low);
-/* Brief: chip select disable
- */
-inline int amazon_ssc_cs_high(u32 pin)
-{
- int ret=0;
- if ((ret=ifx_ssc_ioctl((struct inode *)0, NULL,IFX_SSC_GPO_OUT_SET, (unsigned long)&pin))){
- AMAZON_SSC_EMSG("set CS %d fails\n", pin);
- }
- wmb();
- return ret;
-}
-EXPORT_SYMBOL(amazon_ssc_cs_high);
-/* Brief: one SSC session
- * Parameter:
- * tx_buf
- * tx_len
- * rx_buf
- * rx_len
- * session_mode: IFX_SSC_MODE_RXTX or IFX_SSC_MODE_TX
- * Return: >=0 number of bytes received (if rx_buf != 0) or transmitted
- * <0 error code
- * Description:
- * 0. copy data to internal buffer
- * 1. Write command
- * 2a. If SSC_SESSION_MODE_TXONLY, read tx_len data
- * 2b. If not Read back (tx_len + rx_len) data
- * 3. copy internal buffer to rx buf if necessary
- */
-static int ssc_session(char * tx_buf, u32 tx_len, char * rx_buf, u32 rx_len)
-{
- int ret=0;
-
- char * ssc_tx_buf=NULL;
- char * ssc_rx_buf=NULL;
-
-// volatile char ssc_tx_buf[128]={0};
-// volatile char ssc_rx_buf[128]={0};
-
- int eff_size=0;
- u8 mode=0;
-
- if (tx_buf == NULL && tx_len ==0 && rx_buf == NULL && rx_len == 0){
- AMAZON_SSC_EMSG("invalid parameters\n");
- ret=-EINVAL;
- goto ssc_session_exit;
- }else if (tx_buf == NULL || tx_len == 0){
- if (rx_buf != NULL && rx_len != 0){
- mode = IFX_SSC_MODE_RX;
- }else{
- AMAZON_SSC_EMSG("invalid parameters\n");
- ret=-EINVAL;
- goto ssc_session_exit;
- }
- }else if (rx_buf == NULL || rx_len ==0){
- if (tx_buf != NULL && tx_len != 0){
- mode = IFX_SSC_MODE_TX;
- }else{
- AMAZON_SSC_EMSG("invalid parameters\n");
- ret=-EINVAL;
- goto ssc_session_exit;
- }
- }else{
- mode = IFX_SSC_MODE_RXTX;
- }
-
- if (mode == IFX_SSC_MODE_RXTX){
- eff_size = tx_len + rx_len;
- }else if (mode == IFX_SSC_MODE_RX){
- eff_size = rx_len;
- }else{
- eff_size = tx_len;
- }
-
- //4 bytes alignment, required by driver
- /* change by TaiCheng */
- //if (in_irq()){
- if (1){
- ssc_tx_buf = (char*) kmalloc(sizeof(char) * ((eff_size + 3) & (~3)), GFP_ATOMIC);
- ssc_rx_buf = (char*) kmalloc(sizeof(char) * ((eff_size + 3) & (~3)), GFP_ATOMIC);
- }else{
- ssc_tx_buf = (char*) kmalloc(sizeof(char) * ((eff_size + 3) & (~3)), GFP_KERNEL);
- ssc_rx_buf = (char*) kmalloc(sizeof(char) * ((eff_size + 3) & (~3)), GFP_KERNEL);
- }
- if (ssc_tx_buf == NULL || ssc_rx_buf == NULL){
- AMAZON_SSC_EMSG("no memory for size of %d\n", eff_size);
- ret = -ENOMEM;
- goto ssc_session_exit;
- }
- memset((void*)ssc_tx_buf, 0, eff_size);
- memset((void*)ssc_rx_buf, 0, eff_size);
-
- if (tx_len>0){
- memcpy(ssc_tx_buf, tx_buf, tx_len);
- }
-
- ret=ifx_ssc_kwrite(0, ssc_tx_buf, eff_size);
-
- if (ret > 0) {
- ssc_tx_buf = NULL; //should be freed by ifx_ssc_kwrite
- }
-
- if ( ret != eff_size ){
- AMAZON_SSC_EMSG("ifx_ssc_write return %d\n",ret);
- goto ssc_session_exit;
- }
- ret=ifx_ssc_kread(0, ssc_rx_buf,eff_size);
- if ( ret != eff_size ){
- AMAZON_SSC_EMSG("ifx_ssc_read return %d\n",ret);
- goto ssc_session_exit;
- }
-
- memcpy(rx_buf, ssc_rx_buf+tx_len, rx_len);
-
- if (mode == IFX_SSC_MODE_TX) {
- ret = tx_len;
- }else{
- ret = rx_len;
- }
-ssc_session_exit:
-
- if (ssc_tx_buf != NULL) kfree(ssc_tx_buf);
- if (ssc_rx_buf != NULL) kfree(ssc_rx_buf);
-
- if (ret<0) {
- printk("ssc session fails\n");
- }
- return ret;
-}
-/* Brief: TX-RX session
- * Parameter:
- * tx_buf
- * tx_len
- * rx_buf
- * rx_len
- * Return: >=0 number of bytes received
- * <0 error code
- * Description:
- * 1. TX session
- * 2. RX session
- */
-int amazon_ssc_txrx(char * tx_buf, u32 tx_len, char * rx_buf, u32 rx_len)
-{
- return ssc_session(tx_buf,tx_len,rx_buf,rx_len);
-}
-EXPORT_SYMBOL(amazon_ssc_txrx);
-/* Brief: TX only session
- * Parameter:
- * tx_buf
- * tx_len
- * Return: >=0 number of bytes transmitted
- * <0 error code
- */
-int amazon_ssc_tx(char * tx_buf, u32 tx_len)
-{
- return ssc_session(tx_buf,tx_len,NULL,0);
-}
-EXPORT_SYMBOL(amazon_ssc_tx);
-/* Brief: RX only session
- * Parameter:
- * rx_buf
- * rx_len
- * Return: >=0 number of bytes received
- * <0 error code
- */
-int amazon_ssc_rx(char * rx_buf, u32 rx_len)
-{
- return ssc_session(NULL,0,rx_buf,rx_len);
-}
-EXPORT_SYMBOL(amazon_ssc_rx);
-
+++ /dev/null
-/*
- * Handle mapping of the flash memory access routines
- * on Amazon based devices.
- *
- * Copyright(C) 2004 peng.liu@infineon.com
- *
- * This code is GPLed
- *
- */
-// 000005:fchang 2005/6/2 Modified by Bingtao to double check if the EBU is enabled/disabled
-// 506231:tc.chen 2005/06/23 increase firmware partition size form 192KB to 256KB
-// 050701:linmars 2005/07/01 fix flash size wrong alignment after increase firmware partition
-// 165001:henryhsu 2005/8/18 Remove the support for Intel flash because of 2.1 not enough rootfs partition size
-// 165001:henryhsu 2005/9/7 Rolback to support INtel flash
-// 509071:tc.chen 2005/09/07 Reduced flash writing time
-// 511046:linmars 2005/11/04 change bootloader size from 128 into 64
-// 511241:linmars 2005/11/24 merge TaiChen's IRM patch
-
-// copyright 2005 infineon
-
-// copyright 2007 john crispin <blogic@openwrt.org>
-// copyright 2007 felix fietkau <nbd@openwrt.org>
-// copyright 2009 hauke mehrtens <hauke@hauke-m.de>
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <asm/io.h>
-
-#include <linux/init.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/cfi.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-#include <asm/amazon/amazon.h>
-
-#define AMAZON_PCI_ARB_CTL_ALT 0xb100205c
-#define AMAZON_MTD_REG32( addr ) (*(volatile u32 *)(addr))
-
-
-static struct map_info amazon_map = {
- .name = "AMAZON_FLASH",
- .bankwidth = 2,
-};
-
-static map_word amazon_read16(struct map_info * map, unsigned long ofs)
-{
- map_word temp;
- ofs ^= 2;
- temp.x[0] = *((__u16 *) (map->virt + ofs));
- return temp;
-}
-
-static void amazon_write16(struct map_info *map, map_word d, unsigned long adr)
-{
- adr ^= 2;
- *((__u16 *) (map->virt + adr)) = d.x[0];
-}
-
-void amazon_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
-{
- u8 *p;
- u8 *to_8;
- from = (unsigned long) (from + map->virt);
- p = (u8 *) from;
- to_8 = (u8 *) to;
- while(len--){
- *to_8++ = *p++;
- }
-}
-
-void amazon_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
-{
- u8 *p = (u8*) from;
- u8 *to_8;
- to += (unsigned long) map->virt;
- to_8 = (u8*)to;
- while(len--){
- *p++ = *to_8++;
- }
-}
-
-#define UBOOT_SIZE 0x40000
-
-static struct mtd_partition amazon_partitions[3] = {
- {
- name:"U-Boot", /* U-Boot firmware */
- offset:0x00000000,
- size:UBOOT_SIZE , /* 128k */
- },
- {
- name:"kernel", /* firmware */
- offset:UBOOT_SIZE,
- size:0x00100000, /* 192K */
- },
- {
- name:"rootfs", /* default partition */
- offset:0x00200000,
- size:0x00200000,
- },
-};
-
-unsigned long uImage_size = 0x10000d;
-
-int find_uImage_size(unsigned long start_offset)
-{
- unsigned long magic;
- unsigned long temp;
- amazon_copy_from(&amazon_map, &magic, start_offset, 4);
- if (!(ntohl(magic) == 0x27051956)) {
- printk(KERN_INFO "amazon_mtd: invalid magic (0x%08X) of kernel at 0x%08lx \n", ntohl(magic), start_offset);
- return 0;
- }
- amazon_copy_from(&amazon_map, &temp, start_offset + 12, 4);
- printk(KERN_INFO "amazon_mtd: kernel size is %ld \n", temp + 0x40);
- return temp + 0x40;
-}
-
-static int amazon_mtd_probe(struct platform_device *dev)
-{
- unsigned long uimage_size;
- struct mtd_info *mymtd = NULL;
- struct mtd_partition *parts = NULL;
-
- *AMAZON_EBU_BUSCON0 = 0x1d7ff;
-
- amazon_map.read = amazon_read16;
- amazon_map.write = amazon_write16;
- amazon_map.copy_from = amazon_copy_from;
- amazon_map.copy_to = amazon_copy_to;
-
- amazon_map.phys = dev->resource->start;
- amazon_map.size = dev->resource->end - amazon_map.phys + 1;
- amazon_map.virt = ioremap_nocache(amazon_map.phys, amazon_map.size);
-
- if (!amazon_map.virt) {
- printk(KERN_WARNING "amazon_mtd: Failed to ioremap!\n");
- return -EIO;
- }
-
- mymtd = (struct mtd_info *) do_map_probe("cfi_probe", &amazon_map);
- if (!mymtd) {
- iounmap(amazon_map.virt);
- printk(KERN_WARNING "amazon_mtd: probing failed\n");
- return -ENXIO;
- }
-
- mymtd->owner = THIS_MODULE;
- parts = &amazon_partitions[0];
-
- /* Some Samsung devices are containing a 16 MB flash chip with a bigger U-Boot partition. */
- if(mymtd->size == 0x01000000 && mymtd->erasesize == 0x00020000) {
- printk(KERN_INFO "amazon_mtd: Found big flash chip!\n");
- amazon_partitions[0].size = 0x60000;
- amazon_partitions[1].offset = 0x60000;
- uimage_size = find_uImage_size(amazon_partitions[1].offset);
- amazon_partitions[1].size = uimage_size;
- amazon_partitions[2].offset = 0x60000 + uimage_size;
- amazon_partitions[2].size = mymtd->size - amazon_partitions[2].offset - mymtd->erasesize;
- } else {
- printk(KERN_INFO "amazon_mtd: Found small flash chip!\n");
- uimage_size = find_uImage_size(amazon_partitions[1].offset);
- amazon_partitions[1].size = uimage_size;
- amazon_partitions[2].offset = UBOOT_SIZE + uimage_size;
- amazon_partitions[2].size = mymtd->size - amazon_partitions[2].offset - (2 * mymtd->erasesize);
- }
-
- mtd_device_register(mymtd, parts, 3);
-
- printk(KERN_INFO "amazon_mtd: added %s flash with %dMB\n",
- amazon_map.name, ((int)mymtd->size) >> 20);
- return 0;
-}
-
-static struct platform_driver amazon_mtd_driver = {
- .probe = amazon_mtd_probe,
- .driver = {
- .name = "amazon_mtd",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init amazon_mtd_init(void)
-{
- int ret = platform_driver_register(&amazon_mtd_driver);
- if (ret)
- printk(KERN_WARNING "amazon_mtd: error registering platfom driver!\n");
- return ret;
-}
-
-static void __exit amazon_mtd_cleanup(void)
-{
- platform_driver_unregister(&amazon_mtd_driver);
-}
-
-module_init(amazon_mtd_init);
-module_exit(amazon_mtd_cleanup);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("john crispin blogic@openwrt.org");
-MODULE_DESCRIPTION("MTD map driver for AMAZON boards");
-
+++ /dev/null
-/******************************************************************************
- Copyright (c) 2004, Infineon Technologies. All rights reserved.
-
- No Warranty
- Because the program is licensed free of charge, there is no warranty for
- the program, to the extent permitted by applicable law. Except when
- otherwise stated in writing the copyright holders and/or other parties
- provide the program "as is" without warranty of any kind, either
- expressed or implied, including, but not limited to, the implied
- warranties of merchantability and fitness for a particular purpose. The
- entire risk as to the quality and performance of the program is with
- you. should the program prove defective, you assume the cost of all
- necessary servicing, repair or correction.
-
- In no event unless required by applicable law or agreed to in writing
- will any copyright holder, or any other party who may modify and/or
- redistribute the program as permitted above, be liable to you for
- damages, including any general, special, incidental or consequential
- damages arising out of the use or inability to use the program
- (including but not limited to loss of data or data being rendered
- inaccurate or losses sustained by you or third parties or a failure of
- the program to operate with any other programs), even if such holder or
- other party has been advised of the possibility of such damages.
- ******************************************************************************
- Module : admmod.c
- Date : 2004-09-01
- Description : JoeLin
- Remarks:
-
- Revision:
- MarsLin, add to support VLAN
-
- *****************************************************************************/
-//000001.joelin 2005/06/02 add"ADM6996_MDC_MDIO_MODE" define,
-// if define ADM6996_MDC_MDIO_MODE==> ADM6996LC and ADM6996I will be in MDIO/MDC(SMI)(16 bit) mode,
-// amazon should contrl ADM6996 by MDC/MDIO pin
-// if undef ADM6996_MDC_MDIO_MODE==> ADM6996 will be in EEProm(32 bit) mode,
-// amazon should contrl ADM6996 by GPIO15,16,17,18 pin
-/* 507281:linmars 2005/07/28 support MDIO/EEPROM config mode */
-/* 509201:linmars remove driver testing codes */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/proc_fs.h>
-#include <linux/delay.h>
-#include <asm/uaccess.h>
-#include <linux/init.h>
-#include <linux/ioctl.h>
-#include <asm/atomic.h>
-#include <asm-mips/amazon/amazon.h>
-#include <asm-mips/amazon/adm6996.h>
-//#include <linux/amazon/adm6996.h>
-
-
-unsigned int ifx_sw_conf[ADM_SW_MAX_PORT_NUM+1] = \
- {ADM_SW_PORT0_CONF, ADM_SW_PORT1_CONF, ADM_SW_PORT2_CONF, \
- ADM_SW_PORT3_CONF, ADM_SW_PORT4_CONF, ADM_SW_PORT5_CONF};
-unsigned int ifx_sw_bits[8] = \
- {0x1, 0x3, 0x7, 0xf, 0x1f, 0x3f, 0x7f, 0xff};
-unsigned int ifx_sw_vlan_port[6] = {0, 2, 4, 6, 7, 8};
-//050613:fchang
-/* 507281:linmars start */
-#ifdef CONFIG_SWITCH_ADM6996_MDIO
-#define ADM6996_MDC_MDIO_MODE 1 //000001.joelin
-#else
-#undef ADM6996_MDC_MDIO_MODE
-#endif
-/* 507281:linmars end */
-#define adm6996i 0
-#define adm6996lc 1
-#define adm6996l 2
-unsigned int adm6996_mode=adm6996i;
-/*
- initialize GPIO pins.
- output mode, low
-*/
-void ifx_gpio_init(void)
-{
- //GPIO16,17,18 direction:output
- //GPIO16,17,18 output 0
-
- AMAZON_SW_REG(AMAZON_GPIO_P1_DIR) |= (GPIO_MDIO|GPIO_MDCS|GPIO_MDC);
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT) =AMAZON_SW_REG(AMAZON_GPIO_P1_IN)& ~(GPIO_MDIO|GPIO_MDCS|GPIO_MDC);
-
-}
-
-/* read one bit from mdio port */
-int ifx_sw_mdio_readbit(void)
-{
- //int val;
-
- //val = (AMAZON_SW_REG(GPIO_conf0_REG) & GPIO0_INPUT_MASK) >> 8;
- //return val;
- //GPIO16
- return AMAZON_SW_REG(AMAZON_GPIO_P1_IN)&1;
-}
-
-/*
- MDIO mode selection
- 1 -> output
- 0 -> input
-
- switch input/output mode of GPIO 0
-*/
-void ifx_mdio_mode(int mode)
-{
-// AMAZON_SW_REG(GPIO_conf0_REG) = mode ? GPIO_ENABLEBITS :
-// ((GPIO_ENABLEBITS | MDIO_INPUT) & ~MDIO_OUTPUT_EN);
- mode?(AMAZON_SW_REG(AMAZON_GPIO_P1_DIR)|=GPIO_MDIO):
- (AMAZON_SW_REG(AMAZON_GPIO_P1_DIR)&=~GPIO_MDIO);
- /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_DIR);
- mode?(r|=GPIO_MDIO):(r&=~GPIO_MDIO);
- AMAZON_SW_REG(AMAZON_GPIO_P1_DIR)=r;*/
-}
-
-void ifx_mdc_hi(void)
-{
- //GPIO_SET_HI(GPIO_MDC);
- //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)|=GPIO_MDC;
- /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT);
- r|=GPIO_MDC;
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/
-
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)|GPIO_MDC;
-}
-
-void ifx_mdio_hi(void)
-{
- //GPIO_SET_HI(GPIO_MDIO);
- //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)|=GPIO_MDIO;
- /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT);
- r|=GPIO_MDIO;
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/
-
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)|GPIO_MDIO;
-}
-
-void ifx_mdcs_hi(void)
-{
- //GPIO_SET_HI(GPIO_MDCS);
- //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)|=GPIO_MDCS;
- /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT);
- r|=GPIO_MDCS;
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/
-
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)|GPIO_MDCS;
-}
-
-void ifx_mdc_lo(void)
-{
- //GPIO_SET_LOW(GPIO_MDC);
- //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)&=~GPIO_MDC;
- /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT);
- r&=~GPIO_MDC;
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/
-
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)&(~GPIO_MDC);
-}
-
-void ifx_mdio_lo(void)
-{
- //GPIO_SET_LOW(GPIO_MDIO);
- //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)&=~GPIO_MDIO;
- /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT);
- r&=~GPIO_MDIO;
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/
-
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)&(~GPIO_MDIO);
-}
-
-void ifx_mdcs_lo(void)
-{
- //GPIO_SET_LOW(GPIO_MDCS);
- //AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)&=~GPIO_MDCS;
- /*int r=AMAZON_SW_REG(AMAZON_GPIO_P1_OUT);
- r&=~GPIO_MDCS;
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=r;*/
-
- AMAZON_SW_REG(AMAZON_GPIO_P1_OUT)=AMAZON_SW_REG(AMAZON_GPIO_P1_IN)&(~GPIO_MDCS);
-}
-
-/*
- mdc pulse
- 0 -> 1 -> 0
-*/
-static void ifx_sw_mdc_pulse(void)
-{
- ifx_mdc_lo();
- udelay(ADM_SW_MDC_DOWN_DELAY);
- ifx_mdc_hi();
- udelay(ADM_SW_MDC_UP_DELAY);
- ifx_mdc_lo();
-}
-
-/*
- mdc toggle
- 1 -> 0
-*/
-static void ifx_sw_mdc_toggle(void)
-{
- ifx_mdc_hi();
- udelay(ADM_SW_MDC_UP_DELAY);
- ifx_mdc_lo();
- udelay(ADM_SW_MDC_DOWN_DELAY);
-}
-
-/*
- enable eeprom write
- For ATC 93C66 type EEPROM; accessing ADM6996 internal EEPROM type registers
-*/
-static void ifx_sw_eeprom_write_enable(void)
-{
- unsigned int op;
-
- ifx_mdcs_lo();
- ifx_mdc_lo();
- ifx_mdio_hi();
- udelay(ADM_SW_CS_DELAY);
- /* enable chip select */
- ifx_mdcs_hi();
- udelay(ADM_SW_CS_DELAY);
- /* start bit */
- ifx_mdio_hi();
- ifx_sw_mdc_pulse();
-
- /* eeprom write enable */
- op = ADM_SW_BIT_MASK_4;
- while (op)
- {
- if (op & ADM_SW_EEPROM_WRITE_ENABLE)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 3);
- while (op)
- {
- ifx_mdio_lo();
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
- /* disable chip select */
- ifx_mdcs_lo();
- udelay(ADM_SW_CS_DELAY);
- ifx_sw_mdc_pulse();
-}
-
-/*
- disable eeprom write
-*/
-static void ifx_sw_eeprom_write_disable(void)
-{
- unsigned int op;
-
- ifx_mdcs_lo();
- ifx_mdc_lo();
- ifx_mdio_hi();
- udelay(ADM_SW_CS_DELAY);
- /* enable chip select */
- ifx_mdcs_hi();
- udelay(ADM_SW_CS_DELAY);
-
- /* start bit */
- ifx_mdio_hi();
- ifx_sw_mdc_pulse();
- /* eeprom write disable */
- op = ADM_SW_BIT_MASK_4;
- while (op)
- {
- if (op & ADM_SW_EEPROM_WRITE_DISABLE)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 3);
- while (op)
- {
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
- /* disable chip select */
- ifx_mdcs_lo();
- udelay(ADM_SW_CS_DELAY);
- ifx_sw_mdc_pulse();
-}
-
-/*
- read registers from ADM6996
- serial registers start at 0x200 (addr bit 9 = 1b)
- EEPROM registers -> 16bits; Serial registers -> 32bits
-*/
-#ifdef ADM6996_MDC_MDIO_MODE //smi mode//000001.joelin
-static int ifx_sw_read_adm6996i_smi(unsigned int addr, unsigned int *dat)
-{
- addr=(addr<<16)&0x3ff0000;
- AMAZON_SW_REG(AMAZON_SW_MDIO_ACC) =(0xC0000000|addr);
- while ((AMAZON_SW_REG(AMAZON_SW_MDIO_ACC))&0x80000000){};
- *dat=((AMAZON_SW_REG(AMAZON_SW_MDIO_ACC))&0x0FFFF);
- return 0;
-}
-#endif
-
-static int ifx_sw_read_adm6996i(unsigned int addr, unsigned int *dat)
-{
- unsigned int op;
-
- ifx_gpio_init();
-
- ifx_mdcs_hi();
- udelay(ADM_SW_CS_DELAY);
-
- ifx_mdcs_lo();
- ifx_mdc_lo();
- ifx_mdio_lo();
-
- udelay(ADM_SW_CS_DELAY);
-
- /* preamble, 32 bit 1 */
- ifx_mdio_hi();
- op = ADM_SW_BIT_MASK_32;
- while (op)
- {
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* command start (01b) */
- op = ADM_SW_BIT_MASK_2;
- while (op)
- {
- if (op & ADM_SW_SMI_START)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* read command (10b) */
- op = ADM_SW_BIT_MASK_2;
- while (op)
- {
- if (op & ADM_SW_SMI_READ)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* send address A9 ~ A0 */
- op = ADM_SW_BIT_MASK_10;
- while (op)
- {
- if (op & addr)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* turnaround bits */
- op = ADM_SW_BIT_MASK_2;
- ifx_mdio_hi();
- while (op)
- {
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- udelay(ADM_SW_MDC_DOWN_DELAY);
-
- /* set MDIO pin to input mode */
- ifx_mdio_mode(ADM_SW_MDIO_INPUT);
-
- /* start read data */
- *dat = 0;
-//adm6996i op = ADM_SW_BIT_MASK_32;
- op = ADM_SW_BIT_MASK_16;//adm6996i
- while (op)
- {
- *dat <<= 1;
- if (ifx_sw_mdio_readbit()) *dat |= 1;
- ifx_sw_mdc_toggle();
-
- op >>= 1;
- }
-
- /* set MDIO to output mode */
- ifx_mdio_mode(ADM_SW_MDIO_OUTPUT);
-
- /* dummy clock */
- op = ADM_SW_BIT_MASK_4;
- ifx_mdio_lo();
- while(op)
- {
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- ifx_mdc_lo();
- ifx_mdio_lo();
- ifx_mdcs_hi();
-
- /* EEPROM registers */
-//adm6996i if (!(addr & 0x200))
-//adm6996i {
-//adm6996i if (addr % 2)
-//adm6996i *dat >>= 16;
-//adm6996i else
-//adm6996i *dat &= 0xffff;
-//adm6996i }
-
- return 0;
-}
-//adm6996
-static int ifx_sw_read_adm6996l(unsigned int addr, unsigned int *dat)
-{
- unsigned int op;
-
- ifx_gpio_init();
-
- ifx_mdcs_hi();
- udelay(ADM_SW_CS_DELAY);
-
- ifx_mdcs_lo();
- ifx_mdc_lo();
- ifx_mdio_lo();
-
- udelay(ADM_SW_CS_DELAY);
-
- /* preamble, 32 bit 1 */
- ifx_mdio_hi();
- op = ADM_SW_BIT_MASK_32;
- while (op)
- {
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* command start (01b) */
- op = ADM_SW_BIT_MASK_2;
- while (op)
- {
- if (op & ADM_SW_SMI_START)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* read command (10b) */
- op = ADM_SW_BIT_MASK_2;
- while (op)
- {
- if (op & ADM_SW_SMI_READ)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* send address A9 ~ A0 */
- op = ADM_SW_BIT_MASK_10;
- while (op)
- {
- if (op & addr)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* turnaround bits */
- op = ADM_SW_BIT_MASK_2;
- ifx_mdio_hi();
- while (op)
- {
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- udelay(ADM_SW_MDC_DOWN_DELAY);
-
- /* set MDIO pin to input mode */
- ifx_mdio_mode(ADM_SW_MDIO_INPUT);
-
- /* start read data */
- *dat = 0;
- op = ADM_SW_BIT_MASK_32;
- while (op)
- {
- *dat <<= 1;
- if (ifx_sw_mdio_readbit()) *dat |= 1;
- ifx_sw_mdc_toggle();
-
- op >>= 1;
- }
-
- /* set MDIO to output mode */
- ifx_mdio_mode(ADM_SW_MDIO_OUTPUT);
-
- /* dummy clock */
- op = ADM_SW_BIT_MASK_4;
- ifx_mdio_lo();
- while(op)
- {
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- ifx_mdc_lo();
- ifx_mdio_lo();
- ifx_mdcs_hi();
-
- /* EEPROM registers */
- if (!(addr & 0x200))
- {
- if (addr % 2)
- *dat >>= 16;
- else
- *dat &= 0xffff;
- }
-
- return 0;
-}
-
-static int ifx_sw_read(unsigned int addr, unsigned int *dat)
-{
-#ifdef ADM6996_MDC_MDIO_MODE //smi mode ////000001.joelin
- ifx_sw_read_adm6996i_smi(addr,dat);
-#else
- if (adm6996_mode==adm6996i) ifx_sw_read_adm6996i(addr,dat);
- else ifx_sw_read_adm6996l(addr,dat);
-#endif
- return 0;
-
-}
-
-/*
- write register to ADM6996 eeprom registers
-*/
-//for adm6996i -start
-#ifdef ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin
-static int ifx_sw_write_adm6996i_smi(unsigned int addr, unsigned int dat)
-{
-
- AMAZON_SW_REG(AMAZON_SW_MDIO_ACC) = ((addr<<16)&0x3ff0000)|dat|0x80000000;
- while ((AMAZON_SW_REG(AMAZON_SW_MDIO_ACC))&0x80000000){};
-
- return 0;
-
-}
-#endif //ADM6996_MDC_MDIO_MODE //000001.joelin
-
-static int ifx_sw_write_adm6996i(unsigned int addr, unsigned int dat)
-{
- unsigned int op;
-
- ifx_gpio_init();
-
- ifx_mdcs_hi();
- udelay(ADM_SW_CS_DELAY);
-
- ifx_mdcs_lo();
- ifx_mdc_lo();
- ifx_mdio_lo();
-
- udelay(ADM_SW_CS_DELAY);
-
- /* preamble, 32 bit 1 */
- ifx_mdio_hi();
- op = ADM_SW_BIT_MASK_32;
- while (op)
- {
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* command start (01b) */
- op = ADM_SW_BIT_MASK_2;
- while (op)
- {
- if (op & ADM_SW_SMI_START)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* write command (01b) */
- op = ADM_SW_BIT_MASK_2;
- while (op)
- {
- if (op & ADM_SW_SMI_WRITE)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* send address A9 ~ A0 */
- op = ADM_SW_BIT_MASK_10;
- while (op)
- {
- if (op & addr)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* turnaround bits */
- op = ADM_SW_BIT_MASK_2;
- ifx_mdio_hi();
- while (op)
- {
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- udelay(ADM_SW_MDC_DOWN_DELAY);
-
- /* set MDIO pin to output mode */
- ifx_mdio_mode(ADM_SW_MDIO_OUTPUT);
-
-
- /* start write data */
- op = ADM_SW_BIT_MASK_16;
- while (op)
- {
- if (op & dat)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_toggle();
- op >>= 1;
- }
-
- // /* set MDIO to output mode */
- // ifx_mdio_mode(ADM_SW_MDIO_OUTPUT);
-
- /* dummy clock */
- op = ADM_SW_BIT_MASK_4;
- ifx_mdio_lo();
- while(op)
- {
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- ifx_mdc_lo();
- ifx_mdio_lo();
- ifx_mdcs_hi();
-
- /* EEPROM registers */
-//adm6996i if (!(addr & 0x200))
-//adm6996i {
-//adm6996i if (addr % 2)
-//adm6996i *dat >>= 16;
-//adm6996i else
-//adm6996i *dat &= 0xffff;
-//adm6996i }
-
- return 0;
-}
-//for adm6996i-end
-static int ifx_sw_write_adm6996l(unsigned int addr, unsigned int dat)
-{
- unsigned int op;
-
- ifx_gpio_init();
-
- /* enable write */
- ifx_sw_eeprom_write_enable();
-
- /* chip select */
- ifx_mdcs_hi();
- udelay(ADM_SW_CS_DELAY);
-
- /* issue write command */
- /* start bit */
- ifx_mdio_hi();
- ifx_sw_mdc_pulse();
-
- /* EEPROM write command */
- op = ADM_SW_BIT_MASK_2;
- while (op)
- {
- if (op & ADM_SW_EEPROM_WRITE)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_pulse();
- op >>= 1;
- }
-
- /* send address A7 ~ A0 */
- op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 1);
-
- while (op)
- {
- if (op & addr)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_toggle();
- op >>= 1;
- }
-
- /* start write data */
- op = ADM_SW_BIT_MASK_16;
- while (op)
- {
- if (op & dat)
- ifx_mdio_hi();
- else
- ifx_mdio_lo();
-
- ifx_sw_mdc_toggle();
- op >>= 1;
- }
-
- /* disable cs & wait 1 clock */
- ifx_mdcs_lo();
- udelay(ADM_SW_CS_DELAY);
- ifx_sw_mdc_toggle();
-
- ifx_sw_eeprom_write_disable();
-
- return 0;
-}
-
-static int ifx_sw_write(unsigned int addr, unsigned int dat)
-{
-#ifdef ADM6996_MDC_MDIO_MODE //smi mode ////000001.joelin
- ifx_sw_write_adm6996i_smi(addr,dat);
-#else //000001.joelin
- if (adm6996_mode==adm6996i) ifx_sw_write_adm6996i(addr,dat);
- else ifx_sw_write_adm6996l(addr,dat);
-#endif //000001.joelin
- return 0;
-}
-
-/*
- do switch PHY reset
-*/
-int ifx_sw_reset(void)
-{
- /* reset PHY */
- ifx_sw_write(ADM_SW_PHY_RESET, 0);
-
- return 0;
-}
-
-/* 509201:linmars start */
-#if 0
-/*
- check port status
-*/
-int ifx_check_port_status(int port)
-{
- unsigned int val;
-
- if ((port < 0) || (port > ADM_SW_MAX_PORT_NUM))
- {
- ifx_printf(("error on port number (%d)!!\n", port));
- return -1;
- }
-
- ifx_sw_read(ifx_sw_conf[port], &val);
- if (ifx_sw_conf[port]%2) val >>= 16;
- /* only 16bits are effective */
- val &= 0xFFFF;
-
- ifx_printf(("Port %d status (%.8x): \n", port, val));
-
- if (val & ADM_SW_PORT_FLOWCTL)
- ifx_printf(("\t802.3x flow control supported!\n"));
- else
- ifx_printf(("\t802.3x flow control not supported!\n"));
-
- if (val & ADM_SW_PORT_AN)
- ifx_printf(("\tAuto negotiation ON!\n"));
- else
- ifx_printf(("\tAuto negotiation OFF!\n"));
-
- if (val & ADM_SW_PORT_100M)
- ifx_printf(("\tLink at 100M!\n"));
- else
- ifx_printf(("\tLink at 10M!\n"));
-
- if (val & ADM_SW_PORT_FULL)
- ifx_printf(("\tFull duplex!\n"));
- else
- ifx_printf(("\tHalf duplex!\n"));
-
- if (val & ADM_SW_PORT_DISABLE)
- ifx_printf(("\tPort disabled!\n"));
- else
- ifx_printf(("\tPort enabled!\n"));
-
- if (val & ADM_SW_PORT_TOS)
- ifx_printf(("\tTOS enabled!\n"));
- else
- ifx_printf(("\tTOS disabled!\n"));
-
- if (val & ADM_SW_PORT_PPRI)
- ifx_printf(("\tPort priority first!\n"));
- else
- ifx_printf(("\tVLAN or TOS priority first!\n"));
-
- if (val & ADM_SW_PORT_MDIX)
- ifx_printf(("\tAuto MDIX!\n"));
- else
- ifx_printf(("\tNo auto MDIX\n"));
-
- ifx_printf(("\tPVID: %d\n", \
- ((val >> ADM_SW_PORT_PVID_SHIFT)&ifx_sw_bits[ADM_SW_PORT_PVID_BITS])));
-
- return 0;
-}
-/*
- initialize a VLAN
- clear all VLAN bits
-*/
-int ifx_sw_vlan_init(int vlanid)
-{
- ifx_sw_write(ADM_SW_VLAN0_CONF + vlanid, 0);
-
- return 0;
-}
-
-/*
- add a port to certain vlan
-*/
-int ifx_sw_vlan_add(int port, int vlanid)
-{
- int reg = 0;
-
- if ((port < 0) || (port > ADM_SW_MAX_PORT_NUM) || (vlanid < 0) ||
- (vlanid > ADM_SW_MAX_VLAN_NUM))
- {
- ifx_printf(("Port number or VLAN number ERROR!!\n"));
- return -1;
- }
- ifx_sw_read(ADM_SW_VLAN0_CONF + vlanid, ®);
- reg |= (1 << ifx_sw_vlan_port[port]);
- ifx_sw_write(ADM_SW_VLAN0_CONF + vlanid, reg);
-
- return 0;
-}
-
-/*
- delete a given port from certain vlan
-*/
-int ifx_sw_vlan_del(int port, int vlanid)
-{
- unsigned int reg = 0;
-
- if ((port < 0) || (port > ADM_SW_MAX_PORT_NUM) || (vlanid < 0) || (vlanid > ADM_SW_MAX_VLAN_NUM))
- {
- ifx_printf(("Port number or VLAN number ERROR!!\n"));
- return -1;
- }
- ifx_sw_read(ADM_SW_VLAN0_CONF + vlanid, ®);
- reg &= ~(1 << ifx_sw_vlan_port[port]);
- ifx_sw_write(ADM_SW_VLAN0_CONF + vlanid, reg);
-
- return 0;
-}
-
-/*
- default VLAN setting
-
- port 0~3 as untag port and PVID = 1
- VLAN1: port 0~3 and port 5 (MII)
-*/
-static int ifx_sw_init(void)
-{
- ifx_printf(("Setting default ADM6996 registers... \n"));
-
- /* MAC clone, 802.1q based VLAN */
- ifx_sw_write(ADM_SW_VLAN_MODE, 0xff30);
- /* auto MDIX, PVID=1, untag */
- ifx_sw_write(ADM_SW_PORT0_CONF, 0x840f);
- ifx_sw_write(ADM_SW_PORT1_CONF, 0x840f);
- ifx_sw_write(ADM_SW_PORT2_CONF, 0x840f);
- ifx_sw_write(ADM_SW_PORT3_CONF, 0x840f);
- /* auto MDIX, PVID=2, untag */
- ifx_sw_write(ADM_SW_PORT5_CONF, 0x880f);
- /* port 0~3 & 5 as VLAN1 */
- ifx_sw_write(ADM_SW_VLAN0_CONF+1, 0x0155);
-
- return 0;
-}
-#endif
-/* 509201:linmars end */
-
-int adm_open(struct inode *node, struct file *filp)
-{
- return 0;
-}
-
-ssize_t adm_read(struct file *filep, char *buf, size_t count, loff_t *ppos)
-{
- return count;
-}
-
-ssize_t adm_write(struct file *filep, const char *buf, size_t count, loff_t *ppos)
-{
- return count;
-}
-
-/* close */
-int adm_release(struct inode *inode, struct file *filp)
-{
- return 0;
-}
-
-/* IOCTL function */
-
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))
-static long adm_ioctl(struct file *filp, unsigned int cmd, unsigned long args)
-#else
-static int adm_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long args)
-#endif
-{
- PREGRW uREGRW;
- unsigned int rtval;
- unsigned int val; //6996i
- unsigned int control[6] ; //6996i
- unsigned int status[6] ; //6996i
-
- PMACENTRY mMACENTRY;//adm6996i
- PPROTOCOLFILTER uPROTOCOLFILTER ;///adm6996i
-
- if (_IOC_TYPE(cmd) != ADM_MAGIC)
- {
- printk("adm_ioctl: IOC_TYPE(%x) != ADM_MAGIC(%x)! \n", _IOC_TYPE(cmd), ADM_MAGIC);
- return (-EINVAL);
- }
-
- if(_IOC_NR(cmd) >= KEY_IOCTL_MAX_KEY)
- {
- printk(KERN_WARNING "adm_ioctl: IOC_NR(%x) invalid! \n", _IOC_NR(cmd));
- return (-EINVAL);
- }
-
- switch (cmd)
- {
- case ADM_IOCTL_REGRW:
- {
- uREGRW = (PREGRW)kmalloc(sizeof(REGRW), GFP_KERNEL);
- rtval = copy_from_user(uREGRW, (PREGRW)args, sizeof(REGRW));
- if (rtval != 0)
- {
- printk("ADM_IOCTL_REGRW: copy from user FAILED!! \n");
- return (-EFAULT);
- }
-
- switch(uREGRW->mode)
- {
- case REG_READ:
- uREGRW->value = 0x12345678;//inl(uREGRW->addr);
- copy_to_user((PREGRW)args, uREGRW, sizeof(REGRW));
- break;
- case REG_WRITE:
- //outl(uREGRW->value, uREGRW->addr);
- break;
-
- default:
- printk("No such Register Read/Write function!! \n");
- return (-EFAULT);
- }
- kfree(uREGRW);
- break;
- }
-
- case ADM_SW_IOCTL_REGRW:
- {
- unsigned int val = 0xff;
-
- uREGRW = (PREGRW)kmalloc(sizeof(REGRW), GFP_KERNEL);
- rtval = copy_from_user(uREGRW, (PREGRW)args, sizeof(REGRW));
- if (rtval != 0)
- {
- printk("ADM_IOCTL_REGRW: copy from user FAILED!! \n");
- return (-EFAULT);
- }
-
- switch(uREGRW->mode)
- {
- case REG_READ:
- ifx_sw_read(uREGRW->addr, &val);
- uREGRW->value = val;
- copy_to_user((PREGRW)args, uREGRW, sizeof(REGRW));
- break;
-
- case REG_WRITE:
- ifx_sw_write(uREGRW->addr, uREGRW->value);
- break;
- default:
- printk("No such Register Read/Write function!! \n");
- return (-EFAULT);
- }
- kfree(uREGRW);
- break;
- }
-/* 509201:linmars start */
-#if 0
- case ADM_SW_IOCTL_PORTSTS:
- for (rtval = 0; rtval < ADM_SW_MAX_PORT_NUM+1; rtval++)
- ifx_check_port_status(rtval);
- break;
- case ADM_SW_IOCTL_INIT:
- ifx_sw_init();
- break;
-#endif
-/* 509201:linmars end */
-//adm6996i
- case ADM_SW_IOCTL_MACENTRY_ADD:
- case ADM_SW_IOCTL_MACENTRY_DEL:
- case ADM_SW_IOCTL_MACENTRY_GET_INIT:
- case ADM_SW_IOCTL_MACENTRY_GET_MORE:
-
-
- mMACENTRY = (PMACENTRY)kmalloc(sizeof(MACENTRY), GFP_KERNEL);
- rtval = copy_from_user(mMACENTRY, (PMACENTRY)args, sizeof(MACENTRY));
- if (rtval != 0)
- {
- printk("ADM_SW_IOCTL_MACENTRY: copy from user FAILED!! \n");
- return (-EFAULT);
- }
- control[0]=(mMACENTRY->mac_addr[1]<<8)+mMACENTRY->mac_addr[0] ;
- control[1]=(mMACENTRY->mac_addr[3]<<8)+mMACENTRY->mac_addr[2] ;
- control[2]=(mMACENTRY->mac_addr[5]<<8)+mMACENTRY->mac_addr[4] ;
- control[3]=(mMACENTRY->fid&0xf)+((mMACENTRY->portmap&0x3f)<<4);
- if (((mMACENTRY->info_type)&0x01)) control[4]=(mMACENTRY->ctrl.info_ctrl)+0x1000; //static ,info control
- else control[4]=((mMACENTRY->ctrl.age_timer)&0xff);//not static ,agetimer
- if (cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT) {
- //initial the pointer to the first address
- val=0x8000;//busy ,status5[15]
- while(val&0x8000){ //check busy ?
- ifx_sw_read(0x125, &val);
- }
- control[5]=0x030;//initial the first address
- ifx_sw_write(0x11f,control[5]);
-
-
- val=0x8000;//busy ,status5[15]
- while(val&0x8000){ //check busy ?
- ifx_sw_read(0x125, &val);
- }
-
- } //if (cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)
- if (cmd==ADM_SW_IOCTL_MACENTRY_ADD) control[5]=0x07;//create a new address
- else if (cmd==ADM_SW_IOCTL_MACENTRY_DEL) control[5]=0x01f;//erased an existed address
- else if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE))
- control[5]=0x02c;//search by the mac address field
-
- val=0x8000;//busy ,status5[15]
- while(val&0x8000){ //check busy ?
- ifx_sw_read(0x125, &val);
- }
- ifx_sw_write(0x11a,control[0]);
- ifx_sw_write(0x11b,control[1]);
- ifx_sw_write(0x11c,control[2]);
- ifx_sw_write(0x11d,control[3]);
- ifx_sw_write(0x11e,control[4]);
- ifx_sw_write(0x11f,control[5]);
- val=0x8000;//busy ,status5[15]
- while(val&0x8000){ //check busy ?
- ifx_sw_read(0x125, &val);
- }
- val=((val&0x7000)>>12);//result ,status5[14:12]
- mMACENTRY->result=val;
-
- if (!val) {
- printk(" Command OK!! \n");
- if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) {
- ifx_sw_read(0x120,&(status[0]));
- ifx_sw_read(0x121,&(status[1]));
- ifx_sw_read(0x122,&(status[2]));
- ifx_sw_read(0x123,&(status[3]));
- ifx_sw_read(0x124,&(status[4]));
- ifx_sw_read(0x125,&(status[5]));
-
-
- mMACENTRY->mac_addr[0]=(status[0]&0x00ff) ;
- mMACENTRY->mac_addr[1]=(status[0]&0xff00)>>8 ;
- mMACENTRY->mac_addr[2]=(status[1]&0x00ff) ;
- mMACENTRY->mac_addr[3]=(status[1]&0xff00)>>8 ;
- mMACENTRY->mac_addr[4]=(status[2]&0x00ff) ;
- mMACENTRY->mac_addr[5]=(status[2]&0xff00)>>8 ;
- mMACENTRY->fid=(status[3]&0xf);
- mMACENTRY->portmap=((status[3]>>4)&0x3f);
- if (status[5]&0x2) {//static info_ctrl //status5[1]????
- mMACENTRY->ctrl.info_ctrl=(status[4]&0x00ff);
- mMACENTRY->info_type=1;
- }
- else {//not static age_timer
- mMACENTRY->ctrl.age_timer=(status[4]&0x00ff);
- mMACENTRY->info_type=0;
- }
-//status5[13]???? mMACENTRY->occupy=(status[5]&0x02)>>1;//status5[1]
- mMACENTRY->occupy=(status[5]&0x02000)>>13;//status5[13] ???
- mMACENTRY->bad=(status[5]&0x04)>>2;//status5[2]
- }//if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE))
-
- }
- else if (val==0x001)
- printk(" All Entry Used!! \n");
- else if (val==0x002)
- printk(" Entry Not Found!! \n");
- else if (val==0x003)
- printk(" Try Next Entry!! \n");
- else if (val==0x005)
- printk(" Command Error!! \n");
- else
- printk(" UnKnown Error!! \n");
-
- copy_to_user((PMACENTRY)args, mMACENTRY,sizeof(MACENTRY));
-
- break;
-
- case ADM_SW_IOCTL_FILTER_ADD:
- case ADM_SW_IOCTL_FILTER_DEL:
- case ADM_SW_IOCTL_FILTER_GET:
-
- uPROTOCOLFILTER = (PPROTOCOLFILTER)kmalloc(sizeof(PROTOCOLFILTER), GFP_KERNEL);
- rtval = copy_from_user(uPROTOCOLFILTER, (PPROTOCOLFILTER)args, sizeof(PROTOCOLFILTER));
- if (rtval != 0)
- {
- printk("ADM_SW_IOCTL_FILTER_ADD: copy from user FAILED!! \n");
- return (-EFAULT);
- }
-
- if(cmd==ADM_SW_IOCTL_FILTER_DEL) { //delete filter
- uPROTOCOLFILTER->ip_p=00; //delet filter
- uPROTOCOLFILTER->action=00; //delete filter
- } //delete filter
-
- ifx_sw_read(((uPROTOCOLFILTER->protocol_filter_num/2)+0x68), &val);//rx68~rx6b,protocol filter0~7
-
- if (((uPROTOCOLFILTER->protocol_filter_num)%2)==00){
- if(cmd==ADM_SW_IOCTL_FILTER_GET) uPROTOCOLFILTER->ip_p= val&0x00ff;//get filter ip_p
- else val=(val&0xff00)|(uPROTOCOLFILTER->ip_p);//set filter ip_p
- }
- else {
- if(cmd==ADM_SW_IOCTL_FILTER_GET) uPROTOCOLFILTER->ip_p= (val>>8);//get filter ip_p
- else val=(val&0x00ff)|((uPROTOCOLFILTER->ip_p)<<8);//set filter ip_p
- }
- if(cmd!=ADM_SW_IOCTL_FILTER_GET) ifx_sw_write(((uPROTOCOLFILTER->protocol_filter_num/2)+0x68), val);//write rx68~rx6b,protocol filter0~7
-
- ifx_sw_read(0x95, &val); //protocol filter action
- if(cmd==ADM_SW_IOCTL_FILTER_GET) {
- uPROTOCOLFILTER->action= ((val>>(uPROTOCOLFILTER->protocol_filter_num*2))&0x3);//get filter action
- copy_to_user((PPROTOCOLFILTER)args, uPROTOCOLFILTER, sizeof(PROTOCOLFILTER));
-
- }
- else {
- val=(val&(~(0x03<<(uPROTOCOLFILTER->protocol_filter_num*2))))|(((uPROTOCOLFILTER->action)&0x03)<<(uPROTOCOLFILTER->protocol_filter_num*2));
- // printk("%d----\n",val);
- ifx_sw_write(0x95, val); //write protocol filter action
- }
-
- break;
-//adm6996i
-
- /* others */
- default:
- return -EFAULT;
- }
- /* end of switch */
- return 0;
-}
-
-/* Santosh: handle IGMP protocol filter ADD/DEL/GET */
-int adm_process_protocol_filter_request (unsigned int cmd, PPROTOCOLFILTER uPROTOCOLFILTER)
-{
- unsigned int val; //6996i
-
- if(cmd==ADM_SW_IOCTL_FILTER_DEL) { //delete filter
- uPROTOCOLFILTER->ip_p=00; //delet filter
- uPROTOCOLFILTER->action=00; //delete filter
- } //delete filter
-
- ifx_sw_read(((uPROTOCOLFILTER->protocol_filter_num/2)+0x68), &val);//rx68~rx6b,protocol filter0~7
-
- if (((uPROTOCOLFILTER->protocol_filter_num)%2)==00){
- if(cmd==ADM_SW_IOCTL_FILTER_GET) uPROTOCOLFILTER->ip_p= val&0x00ff;//get filter ip_p
- else val=(val&0xff00)|(uPROTOCOLFILTER->ip_p);//set filter ip_p
- }
- else {
- if(cmd==ADM_SW_IOCTL_FILTER_GET) uPROTOCOLFILTER->ip_p= (val>>8);//get filter ip_p
- else val=(val&0x00ff)|((uPROTOCOLFILTER->ip_p)<<8);//set filter ip_p
- }
- if(cmd!=ADM_SW_IOCTL_FILTER_GET) ifx_sw_write(((uPROTOCOLFILTER->protocol_filter_num/2)+0x68), val);//write rx68~rx6b,protocol filter0~7
-
- ifx_sw_read(0x95, &val); //protocol filter action
- if(cmd==ADM_SW_IOCTL_FILTER_GET) {
- uPROTOCOLFILTER->action= ((val>>(uPROTOCOLFILTER->protocol_filter_num*2))&0x3);//get filter action
- }
- else {
- val=(val&(~(0x03<<(uPROTOCOLFILTER->protocol_filter_num*2))))|(((uPROTOCOLFILTER->action)&0x03)<<(uPROTOCOLFILTER->protocol_filter_num*2));
- ifx_sw_write(0x95, val); //write protocol filter action
- }
-
- return 0;
-}
-
-
-/* Santosh: function for MAC ENTRY ADD/DEL/GET */
-
-int adm_process_mac_table_request (unsigned int cmd, PMACENTRY mMACENTRY)
-{
- unsigned int val; //6996i
- unsigned int control[6] ; //6996i
- unsigned int status[6] ; //6996i
-
- // printk ("adm_process_mac_table_request: enter\n");
-
- control[0]=(mMACENTRY->mac_addr[1]<<8)+mMACENTRY->mac_addr[0] ;
- control[1]=(mMACENTRY->mac_addr[3]<<8)+mMACENTRY->mac_addr[2] ;
- control[2]=(mMACENTRY->mac_addr[5]<<8)+mMACENTRY->mac_addr[4] ;
- control[3]=(mMACENTRY->fid&0xf)+((mMACENTRY->portmap&0x3f)<<4);
-
- if (((mMACENTRY->info_type)&0x01)) control[4]=(mMACENTRY->ctrl.info_ctrl)+0x1000; //static ,info control
- else control[4]=((mMACENTRY->ctrl.age_timer)&0xff);//not static ,agetimer
- if (cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT) {
- //initial the pointer to the first address
- val=0x8000;//busy ,status5[15]
- while(val&0x8000){ //check busy ?
- ifx_sw_read(0x125, &val);
- }
- control[5]=0x030;//initial the first address
- ifx_sw_write(0x11f,control[5]);
-
-
- val=0x8000;//busy ,status5[15]
- while(val&0x8000){ //check busy ?
- ifx_sw_read(0x125, &val);
- }
-
- } //if (cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)
- if (cmd==ADM_SW_IOCTL_MACENTRY_ADD) control[5]=0x07;//create a new address
- else if (cmd==ADM_SW_IOCTL_MACENTRY_DEL) control[5]=0x01f;//erased an existed address
- else if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE))
- control[5]=0x02c;//search by the mac address field
-
- val=0x8000;//busy ,status5[15]
- while(val&0x8000){ //check busy ?
- ifx_sw_read(0x125, &val);
- }
- ifx_sw_write(0x11a,control[0]);
- ifx_sw_write(0x11b,control[1]);
- ifx_sw_write(0x11c,control[2]);
- ifx_sw_write(0x11d,control[3]);
- ifx_sw_write(0x11e,control[4]);
- ifx_sw_write(0x11f,control[5]);
- val=0x8000;//busy ,status5[15]
- while(val&0x8000){ //check busy ?
- ifx_sw_read(0x125, &val);
- }
- val=((val&0x7000)>>12);//result ,status5[14:12]
- mMACENTRY->result=val;
-
- if (!val) {
- printk(" Command OK!! \n");
- if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE)) {
- ifx_sw_read(0x120,&(status[0]));
- ifx_sw_read(0x121,&(status[1]));
- ifx_sw_read(0x122,&(status[2]));
- ifx_sw_read(0x123,&(status[3]));
- ifx_sw_read(0x124,&(status[4]));
- ifx_sw_read(0x125,&(status[5]));
-
-
- mMACENTRY->mac_addr[0]=(status[0]&0x00ff) ;
- mMACENTRY->mac_addr[1]=(status[0]&0xff00)>>8 ;
- mMACENTRY->mac_addr[2]=(status[1]&0x00ff) ;
- mMACENTRY->mac_addr[3]=(status[1]&0xff00)>>8 ;
- mMACENTRY->mac_addr[4]=(status[2]&0x00ff) ;
- mMACENTRY->mac_addr[5]=(status[2]&0xff00)>>8 ;
- mMACENTRY->fid=(status[3]&0xf);
- mMACENTRY->portmap=((status[3]>>4)&0x3f);
- if (status[5]&0x2) {//static info_ctrl //status5[1]????
- mMACENTRY->ctrl.info_ctrl=(status[4]&0x00ff);
- mMACENTRY->info_type=1;
- }
- else {//not static age_timer
- mMACENTRY->ctrl.age_timer=(status[4]&0x00ff);
- mMACENTRY->info_type=0;
- }
-//status5[13]???? mMACENTRY->occupy=(status[5]&0x02)>>1;//status5[1]
- mMACENTRY->occupy=(status[5]&0x02000)>>13;//status5[13] ???
- mMACENTRY->bad=(status[5]&0x04)>>2;//status5[2]
- }//if ((cmd==ADM_SW_IOCTL_MACENTRY_GET_INIT)||(cmd==ADM_SW_IOCTL_MACENTRY_GET_MORE))
-
- }
- else if (val==0x001)
- printk(" All Entry Used!! \n");
- else if (val==0x002)
- printk(" Entry Not Found!! \n");
- else if (val==0x003)
- printk(" Try Next Entry!! \n");
- else if (val==0x005)
- printk(" Command Error!! \n");
- else
- printk(" UnKnown Error!! \n");
-
- // printk ("adm_process_mac_table_request: Exit\n");
- return 0;
-}
-
-/* Santosh: End of function for MAC ENTRY ADD/DEL*/
-struct file_operations adm_ops =
-{
- read: adm_read,
- write: adm_write,
- open: adm_open,
- release: adm_release,
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))
- unlocked_ioctl: adm_ioctl
-#else
- ioctl: adm_ioctl
-#endif
-};
-
-int adm_proc(char *buf, char **start, off_t offset, int count, int *eof, void *data)
-{
- int len = 0;
-
- len += sprintf(buf+len, " ************ Registers ************ \n");
- *eof = 1;
- return len;
-}
-
-int __init init_adm6996_module(void)
-{
- unsigned int val = 000;
- unsigned int val1 = 000;
-
- printk("Loading ADM6996 driver... \n");
-
- /* if running on adm5120 */
- /* set GPIO 0~2 as adm6996 control pins */
- //outl(0x003f3f00, 0x12000028);
- /* enable switch port 5 (MII) as RMII mode (5120MAC <-> 6996MAC) */
- //outl(0x18a, 0x12000030);
- /* group adm5120 port 1 ~ 5 as VLAN0, port 5 & 6(CPU) as VLAN1 */
- //outl(0x417e, 0x12000040);
- /* end adm5120 fixup */
-#ifdef ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin
- register_chrdev(69, "adm6996", &adm_ops);
- AMAZON_SW_REG(AMAZON_SW_MDIO_CFG) = 0x27be;
- AMAZON_SW_REG(AMAZON_SW_EPHY) = 0xfc;
- adm6996_mode=adm6996i;
- ifx_sw_read(0xa0, &val);
- ifx_sw_read(0xa1, &val1);
- val=((val1&0x0f)<<16)|val;
- printk ("\nADM6996 SMI Mode-");
- printk ("Chip ID:%5x \n ", val);
-#else //000001.joelin
-
- AMAZON_SW_REG(AMAZON_SW_MDIO_CFG) = 0x2c50;
- AMAZON_SW_REG(AMAZON_SW_EPHY) = 0xff;
-
- AMAZON_SW_REG(AMAZON_GPIO_P1_ALTSEL0) &= ~(GPIO_MDIO|GPIO_MDCS|GPIO_MDC);
- AMAZON_SW_REG(AMAZON_GPIO_P1_ALTSEL1) &= ~(GPIO_MDIO|GPIO_MDCS|GPIO_MDC);
- AMAZON_SW_REG(AMAZON_GPIO_P1_OD) |= (GPIO_MDIO|GPIO_MDCS|GPIO_MDC);
-
- ifx_gpio_init();
- register_chrdev(69, "adm6996", &adm_ops);
- mdelay(100);
-
- /* create proc entries */
- // create_proc_read_entry("admide", 0, NULL, admide_proc, NULL);
-
-//joelin adm6996i support start
- adm6996_mode=adm6996i;
- ifx_sw_read(0xa0, &val);
- adm6996_mode=adm6996l;
- ifx_sw_read(0x200, &val1);
-// printk ("\n %0x \n",val1);
- if ((val&0xfff0)==0x1020) {
- printk ("\n ADM6996I .. \n");
- adm6996_mode=adm6996i;
- }
- else if ((val1&0xffffff00)==0x71000) {//71010 or 71020
- printk ("\n ADM6996LC .. \n");
- adm6996_mode=adm6996lc;
- }
- else {
- printk ("\n ADM6996L .. \n");
- adm6996_mode=adm6996l;
- }
-#endif //ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin
-
- if ((adm6996_mode==adm6996lc)||(adm6996_mode==adm6996i)){
-#if 0 /* removed by MarsLin */
- ifx_sw_write(0x29,0xc000);
- ifx_sw_write(0x30,0x0985);
-#else
- ifx_sw_read(0xa0, &val);
- if (val == 0x1021) // for both 6996LC and 6996I, only AB version need the patch
- ifx_sw_write(0x29, 0x9000);
- ifx_sw_write(0x30,0x0985);
-#endif
- }
-//joelin adm6996i support end
- return 0;
-}
-
-void __exit cleanup_adm6996_module(void)
-{
- printk("Free ADM device driver... \n");
-
- unregister_chrdev(69, "adm6996");
-
- /* remove proc entries */
- // remove_proc_entry("admide", NULL);
-}
-
-/* MarsLin, add start */
-#if defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT) || defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT_MODULE)
- #define SET_BIT(reg, mask) reg |= (mask)
- #define CLEAR_BIT(reg, mask) reg &= (~mask)
- static int ifx_hw_reset(void)
- {
- CLEAR_BIT((*AMAZON_GPIO_P0_ALTSEL0),0x2000);
- CLEAR_BIT((*AMAZON_GPIO_P0_ALTSEL1),0x2000);
- SET_BIT((*AMAZON_GPIO_P0_OD),0x2000);
- SET_BIT((*AMAZON_GPIO_P0_DIR), 0x2000);
- CLEAR_BIT((*AMAZON_GPIO_P0_OUT), 0x2000);
- mdelay(500);
- SET_BIT((*AMAZON_GPIO_P0_OUT), 0x2000);
- cleanup_adm6996_module();
- return init_adm6996_module();
- }
- int (*adm6996_hw_reset)(void) = ifx_hw_reset;
- EXPORT_SYMBOL(adm6996_hw_reset);
- EXPORT_SYMBOL(adm6996_mode);
- int (*adm6996_sw_read)(unsigned int addr, unsigned int *data) = ifx_sw_read;
- EXPORT_SYMBOL(adm6996_sw_read);
- int (*adm6996_sw_write)(unsigned int addr, unsigned int data) = ifx_sw_write;
- EXPORT_SYMBOL(adm6996_sw_write);
-#endif
-/* MarsLin, add end */
-
-/* Santosh: for IGMP proxy/snooping, Begin */
-EXPORT_SYMBOL (adm_process_mac_table_request);
-EXPORT_SYMBOL (adm_process_protocol_filter_request);
-/* Santosh: for IGMP proxy/snooping, End */
-
-MODULE_DESCRIPTION("ADMtek 6996 Driver");
-MODULE_AUTHOR("Joe Lin <joe.lin@infineon.com>");
-MODULE_LICENSE("GPL");
-
-module_init(init_adm6996_module);
-module_exit(cleanup_adm6996_module);
-
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- */
-//-----------------------------------------------------------------------
-/*
- * Description:
- * Driver for Infineon Amazon 3 port switch
- */
-//-----------------------------------------------------------------------
-/* Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com]
- * Created: 7-April-2004
- */
-//-----------------------------------------------------------------------
-/* History
- * Changed on: Jun 28, 2004
- * Changed by: peng.liu@infineon.com
- * Reason: add hardware flow control (HFC) (CONFIG_NET_HW_FLOWCONTROL)
- *
- * Changed on: Apr 6, 2005
- * Changed by: mars.lin@infineon.com
- * Reason : supoort port identification
- */
-
-
-// copyright 2004-2005 infineon.com
-
-// copyright 2007 john crispin <blogic@openwrt.org>
-// copyright 2007 felix fietkau <nbd@openwrt.org>
-// copyright 2009 hauke mehrtens <hauke@hauke-m.de>
-
-
-// TODO
-// port vlan code from bcrm target... the tawainese code was scrapped due to crappyness
-// check all the mmi reg settings and possibly document them better
-// verify the ethtool code
-// remove the while(1) stuff
-// further clean up and rework ... but it works for now
-// check the mode[]=bridge stuff
-// verify that the ethaddr can be set from u-boot
-
-
-#ifndef __KERNEL__
-#define __KERNEL__
-#endif
-
-
-#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS)
-#define MODVERSIONS
-#endif
-
-#if defined(MODVERSIONS) && !defined(__GENKSYMS__)
-#include <linux/modversions.h>
-#endif
-
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/errno.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/mii.h>
-#include <asm/uaccess.h>
-#include <linux/in.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/ip.h>
-#include <linux/tcp.h>
-#include <linux/skbuff.h>
-#include <linux/in6.h>
-#include <linux/proc_fs.h>
-#include <linux/mm.h>
-#include <linux/ethtool.h>
-#include <asm/checksum.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/amazon/amazon.h>
-#include <asm/amazon/amazon_dma.h>
-#include <asm/amazon/amazon_sw.h>
-
-// how many mii ports are there ?
-#define AMAZON_SW_INT_NO 2
-
-#define ETHERNET_PACKET_DMA_BUFFER_SIZE 1536
-
-/***************************************** Module Parameters *************************************/
-static char mode[] = "bridge";
-module_param_array(mode, charp, NULL, 0);
-
-static int timeout = 1 * HZ;
-module_param(timeout, int, 0);
-
-int switch_init(struct net_device *dev);
-void switch_tx_timeout(struct net_device *dev);
-
-static struct net_device *switch_devs[2];
-
-int add_mac_table_entry(u64 entry_value)
-{
- int i;
- u32 data1, data2;
-
- AMAZON_SW_REG32(AMAZON_SW_ARL_CTL) = ~7;
-
- for (i = 0; i < 32; i++) {
- AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0x80000000 | 0x20 | i;
- while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {};
- data1 = AMAZON_SW_REG32(AMAZON_SW_DATA1);
- data2 = AMAZON_SW_REG32(AMAZON_SW_DATA2);
- if ((data1 & (0x00700000)) != 0x00700000)
- continue;
- AMAZON_SW_REG32(AMAZON_SW_DATA1) = (u32) (entry_value >> 32);
- AMAZON_SW_REG32(AMAZON_SW_DATA2) = (u32) entry_value & 0xffffffff;
- AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0xc0000020 | i;
- while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {};
- break;
- }
- AMAZON_SW_REG32(AMAZON_SW_ARL_CTL) |= 7;
- if (i >= 32)
- return -1;
- return OK;
-}
-
-u64 read_mac_table_entry(int index)
-{
- u32 data1, data2;
- u64 value;
- AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0x80000000 | 0x20 | index;
- while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {};
- data1 = AMAZON_SW_REG32(AMAZON_SW_DATA1) & 0xffffff;
- data2 = AMAZON_SW_REG32(AMAZON_SW_DATA2);
- value = (u64) data1 << 32 | (u64) data2;
- return value;
-}
-
-int write_mac_table_entry(int index, u64 value)
-{
- u32 data1, data2;
- data1 = (u32) (value >> 32);
- data2 = (u32) value & 0xffffffff;
- AMAZON_SW_REG32(AMAZON_SW_DATA1) = data1;
- AMAZON_SW_REG32(AMAZON_SW_DATA2) = data2;
- AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) = 0xc0000020 | index;
- while (AMAZON_SW_REG32(AMAZON_SW_CPU_ACTL) & (0x80000000)) {};
- return OK;
-}
-
-u32 get_mdio_reg(int phy_addr, int reg_num)
-{
- u32 value;
- AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) = (3 << 30) | ((phy_addr & 0x1f) << 21) | ((reg_num & 0x1f) << 16);
- while (AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) & (1 << 31)) {};
- value = AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) & 0xffff;
- return value;
-}
-
-int set_mdio_reg(int phy_addr, int reg_num, u32 value)
-{
- AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) = (2 << 30) | ((phy_addr & 0x1f) << 21) | ((reg_num & 0x1f) << 16) | (value & 0xffff);
- while (AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) & (1 << 31)) {};
- return OK;
-}
-
-int auto_negotiate(int phy_addr)
-{
- u32 value = 0;
- value = get_mdio_reg(phy_addr, MDIO_BASE_CONTROL_REG);
- set_mdio_reg(phy_addr, MDIO_BASE_CONTROL_REG, (value | RESTART_AUTO_NEGOTIATION | AUTO_NEGOTIATION_ENABLE | PHY_RESET));
- return OK;
-}
-
-/*
- In this version of switch driver, we split the dma channels for the switch.
- 2 for port0 and 2 for port1. So that we can do internal bridging if necessary.
- In switch mode, packets coming in from port0 or port1 is able to do Destination
- address lookup. Packets coming from port0 with destination address of port1 should
- not go to pmac again. The switch hardware should be able to do the switch in the hard
- ware level. Packets coming from the pmac should not do the DA look up in that the
- desination is already known for the kernel. It only needs to go to the correct NIC to
- find its way out.
- */
-int amazon_sw_chip_init(void)
-{
- u32 tmp1;
- int i = 0;
-
- /* Aging tick select: 5mins */
- tmp1 = 0xa0;
- if (strcmp(mode, "bridge") == 0) {
- // bridge mode, set militarised mode to 1, no learning!
- tmp1 |= 0xC00;
- } else {
- // enable learning for P0 and P1,
- tmp1 |= 3;
- }
-
- /* unknown broadcast/multicast/unicast to all ports */
- AMAZON_SW_REG32(AMAZON_SW_UN_DEST) = 0x1ff;
-
- AMAZON_SW_REG32(AMAZON_SW_ARL_CTL) = tmp1;
-
- /* OCS:1 set OCS bit, split the two NIC in rx direction EDL:1 (enable DA lookup) */
-#if defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT) || defined(CONFIG_IFX_NFEXT_AMAZON_SWITCH_PHYPORT_MODULE)
- AMAZON_SW_REG32(AMAZON_SW_P2_PCTL) = 0x700;
-#else
- AMAZON_SW_REG32(AMAZON_SW_P2_PCTL) = 0x401;
-#endif
-
- /* EPC: 1 split the two NIC in tx direction CRC is generated */
- AMAZON_SW_REG32(AMAZON_SW_P2_CTL) = 0x6;
-
- // for bi-directional
- AMAZON_SW_REG32(AMAZON_SW_P0_WM) = 0x14141412;
- AMAZON_SW_REG32(AMAZON_SW_P1_WM) = 0x14141412;
- AMAZON_SW_REG32(AMAZON_SW_P2_WM) = 0x28282826;
- AMAZON_SW_REG32(AMAZON_SW_GBL_WM) = 0x0;
-
- AMAZON_SW_REG32(AMAZON_CGU_PLL0SR) = (AMAZON_SW_REG32(AMAZON_CGU_PLL0SR)) | 0x58000000;
- // clock for PHY
- AMAZON_SW_REG32(AMAZON_CGU_IFCCR) = (AMAZON_SW_REG32(AMAZON_CGU_IFCCR)) | 0x80000004;
- // enable power for PHY
- AMAZON_SW_REG32(AMAZON_PMU_PWDCR) = (AMAZON_SW_REG32(AMAZON_PMU_PWDCR)) | AMAZON_PMU_PWDCR_EPHY;
- // set reverse MII, enable MDIO statemachine
- AMAZON_SW_REG32(AMAZON_SW_MDIO_CFG) = 0x800027bf;
- while (1)
- if (((AMAZON_SW_REG32(AMAZON_SW_MDIO_CFG)) & 0x80000000) == 0)
- break;
- AMAZON_SW_REG32(AMAZON_SW_EPHY) = 0xff;
-
- // auto negotiation
- AMAZON_SW_REG32(AMAZON_SW_MDIO_ACC) = 0x83e08000;
- auto_negotiate(0x1f);
-
- /* enable all ports */
- AMAZON_SW_REG32(AMAZON_SW_PS_CTL) = 0x7;
- for (i = 0; i < 32; i++)
- write_mac_table_entry(i, 1 << 50);
- return 0;
-}
-
-static unsigned char my_ethaddr[MAX_ADDR_LEN];
-/* need to get the ether addr from u-boot */
-static int __init ethaddr_setup(char *line)
-{
- char *ep;
- int i;
-
- memset(my_ethaddr, 0, MAX_ADDR_LEN);
- for (i = 0; i < 6; i++) {
- my_ethaddr[i] = line ? simple_strtoul(line, &ep, 16) : 0;
- if (line)
- line = (*ep) ? ep + 1 : ep;
- }
- printk(KERN_INFO "amazon_mii0: mac address %2x-%2x-%2x-%2x-%2x-%2x \n", my_ethaddr[0], my_ethaddr[1], my_ethaddr[2], my_ethaddr[3], my_ethaddr[4], my_ethaddr[5]);
- return 0;
-}
-
-__setup("ethaddr=", ethaddr_setup);
-
-static void open_rx_dma(struct net_device *dev)
-{
- struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev);
- struct dma_device_info *dma_dev = priv->dma_device;
- int i;
-
- for (i = 0; i < dma_dev->num_rx_chan; i++)
- dma_dev->rx_chan[i].control = 1;
- dma_device_update_rx(dma_dev);
-}
-
-#ifdef CONFIG_NET_HW_FLOWCONTROL
-static void close_rx_dma(struct net_device *dev)
-{
- struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev);
- struct dma_device_info *dma_dev = priv->dma_device;
- int i;
-
- for (i = 0; i < dma_dev->num_rx_chan; i++)
- dma_dev->rx_chan[i].control = 0;
- dma_device_update_rx(dma_dev);
-}
-
-void amazon_xon(struct net_device *dev)
-{
- unsigned long flag;
- local_irq_save(flag);
- open_rx_dma(dev);
- local_irq_restore(flag);
-}
-#endif
-
-int switch_open(struct net_device *dev)
-{
- struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev);
- if (!strcmp(dev->name, "eth1")) {
- priv->mdio_phy_addr = PHY0_ADDR;
- }
- open_rx_dma(dev);
-
-#ifdef CONFIG_NET_HW_FLOWCONTROL
- if ((priv->fc_bit = netdev_register_fc(dev, amazon_xon)) == 0) {
- printk(KERN_WARNING "amazon_mii0: Hardware Flow Control register fails\n");
- }
-#endif
-
- netif_start_queue(dev);
- return OK;
-}
-
-int switch_release(struct net_device *dev)
-{
- int i;
- struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev);
- struct dma_device_info *dma_dev = priv->dma_device;
-
- for (i = 0; i < dma_dev->num_tx_chan; i++)
- dma_dev->tx_chan[i].control = 0;
- for (i = 0; i < dma_dev->num_rx_chan; i++)
- dma_dev->rx_chan[i].control = 0;
-
- dma_device_update(dma_dev);
-
-#ifdef CONFIG_NET_HW_FLOWCONTROL
- if (priv->fc_bit) {
- netdev_unregister_fc(priv->fc_bit);
- }
-#endif
- netif_stop_queue(dev);
-
- return OK;
-}
-
-
-void switch_rx(struct net_device *dev, int len, struct sk_buff *skb)
-{
- struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev);
-#ifdef CONFIG_NET_HW_FLOWCONTROL
- int mit_sel = 0;
-#endif
- skb->dev = dev;
- skb->protocol = eth_type_trans(skb, dev);
-
-#ifdef CONFIG_NET_HW_FLOWCONTROL
- mit_sel = netif_rx(skb);
- switch (mit_sel) {
- case NET_RX_SUCCESS:
- case NET_RX_CN_LOW:
- case NET_RX_CN_MOD:
- break;
- case NET_RX_CN_HIGH:
- break;
- case NET_RX_DROP:
- if ((priv->fc_bit)
- && (!test_and_set_bit(priv->fc_bit, &netdev_fc_xoff))) {
- close_rx_dma(dev);
- }
- break;
- }
-#else
- netif_rx(skb);
-#endif
- priv->stats.rx_packets++;
- priv->stats.rx_bytes += len;
- return;
-}
-
-int asmlinkage switch_hw_tx(char *buf, int len, struct net_device *dev)
-{
- struct switch_priv *priv = netdev_priv(dev);
- struct dma_device_info *dma_dev = priv->dma_device;
-
- dma_dev->current_tx_chan = 0;
- return dma_device_write(dma_dev, buf, len, priv->skb);
-}
-
-int asmlinkage switch_tx(struct sk_buff *skb, struct net_device *dev)
-{
- int len;
- char *data;
- struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev);
-
- len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
- data = skb->data;
- priv->skb = skb;
- dev->trans_start = jiffies;
-
- if (switch_hw_tx(data, len, dev) != len) {
- dev_kfree_skb_any(skb);
- return OK;
- }
-
- priv->stats.tx_packets++;
- priv->stats.tx_bytes += len;
- return OK;
-}
-
-void switch_tx_timeout(struct net_device *dev)
-{
- struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev);
- priv->stats.tx_errors++;
- netif_wake_queue(dev);
- return;
-}
-
-void negotiate(struct net_device *dev)
-{
- struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev);
- unsigned short data = get_mdio_reg(priv->mdio_phy_addr, MDIO_ADVERTISMENT_REG);
-
- data &= ~(MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD | MDIO_ADVERT_10_HD);
-
- switch (priv->current_speed_selection) {
- case 10:
- if (priv->current_duplex == full)
- data |= MDIO_ADVERT_10_FD;
- else if (priv->current_duplex == half)
- data |= MDIO_ADVERT_10_HD;
- else
- data |= MDIO_ADVERT_10_HD | MDIO_ADVERT_10_FD;
- break;
-
- case 100:
- if (priv->current_duplex == full)
- data |= MDIO_ADVERT_100_FD;
- else if (priv->current_duplex == half)
- data |= MDIO_ADVERT_100_HD;
- else
- data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD;
- break;
-
- case 0: /* Auto */
- if (priv->current_duplex == full)
- data |= MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD;
- else if (priv->current_duplex == half)
- data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_10_HD;
- else
- data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD | MDIO_ADVERT_10_HD;
- break;
-
- default: /* assume autoneg speed and duplex */
- data |= MDIO_ADVERT_100_HD | MDIO_ADVERT_100_FD | MDIO_ADVERT_10_FD | MDIO_ADVERT_10_HD;
- }
-
- set_mdio_reg(priv->mdio_phy_addr, MDIO_ADVERTISMENT_REG, data);
-
- /* Renegotiate with link partner */
-
- data = get_mdio_reg(priv->mdio_phy_addr, MDIO_BASE_CONTROL_REG);
- data |= MDIO_BC_NEGOTIATE;
-
- set_mdio_reg(priv->mdio_phy_addr, MDIO_BASE_CONTROL_REG, data);
-
-}
-
-
-void set_duplex(struct net_device *dev, enum duplex new_duplex)
-{
- struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev);
- if (new_duplex != priv->current_duplex) {
- priv->current_duplex = new_duplex;
- negotiate(dev);
- }
-}
-
-void set_speed(struct net_device *dev, unsigned long speed)
-{
- struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev);
- priv->current_speed_selection = speed;
- negotiate(dev);
-}
-
-static int switch_ethtool_ioctl(struct net_device *dev, struct ifreq *ifr)
-{
- struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev);
- struct ethtool_cmd ecmd;
-
- if (copy_from_user(&ecmd, ifr->ifr_data, sizeof(ecmd)))
- return -EFAULT;
-
- switch (ecmd.cmd) {
- case ETHTOOL_GSET:
- memset((void *) &ecmd, 0, sizeof(ecmd));
- ecmd.supported = SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
- SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
- ecmd.port = PORT_TP;
- ecmd.transceiver = XCVR_EXTERNAL;
- ecmd.phy_address = priv->mdio_phy_addr;
-
- ecmd.speed = priv->current_speed;
-
- ecmd.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
-
- ecmd.advertising = ADVERTISED_TP;
- if (priv->current_duplex == autoneg && priv->current_speed_selection == 0)
- ecmd.advertising |= ADVERTISED_Autoneg;
- else {
- ecmd.advertising |= ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
- ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
- if (priv->current_speed_selection == 10)
- ecmd.advertising &= ~(ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full);
- else if (priv->current_speed_selection == 100)
- ecmd.advertising &= ~(ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full);
- if (priv->current_duplex == half)
- ecmd.advertising &= ~(ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Full);
- else if (priv->current_duplex == full)
- ecmd.advertising &= ~(ADVERTISED_10baseT_Half | ADVERTISED_100baseT_Half);
- }
- ecmd.autoneg = AUTONEG_ENABLE;
- if (copy_to_user(ifr->ifr_data, &ecmd, sizeof(ecmd)))
- return -EFAULT;
- break;
-
- case ETHTOOL_SSET:
- if (!capable(CAP_NET_ADMIN)) {
- return -EPERM;
- }
- if (ecmd.autoneg == AUTONEG_ENABLE) {
- set_duplex(dev, autoneg);
- set_speed(dev, 0);
- } else {
- set_duplex(dev, ecmd.duplex == DUPLEX_HALF ? half : full);
- set_speed(dev, ecmd.speed == SPEED_10 ? 10 : 100);
- }
- break;
-
- case ETHTOOL_GDRVINFO:
- {
- struct ethtool_drvinfo info;
- memset((void *) &info, 0, sizeof(info));
- strncpy(info.driver, "AMAZONE", sizeof(info.driver) - 1);
- strncpy(info.fw_version, "N/A", sizeof(info.fw_version) - 1);
- strncpy(info.bus_info, "N/A", sizeof(info.bus_info) - 1);
- info.regdump_len = 0;
- info.eedump_len = 0;
- info.testinfo_len = 0;
- if (copy_to_user(ifr->ifr_data, &info, sizeof(info)))
- return -EFAULT;
- }
- break;
- case ETHTOOL_NWAY_RST:
- if (priv->current_duplex == autoneg && priv->current_speed_selection == 0)
- negotiate(dev);
- break;
- default:
- return -EOPNOTSUPP;
- break;
- }
- return 0;
-}
-
-
-
-int mac_table_tools_ioctl(struct net_device *dev, struct mac_table_req *req)
-{
- int cmd;
- int i;
- cmd = req->cmd;
- switch (cmd) {
- case RESET_MAC_TABLE:
- for (i = 0; i < 32; i++) {
- write_mac_table_entry(i, 0);
- }
- break;
- case READ_MAC_ENTRY:
- req->entry_value = read_mac_table_entry(req->index);
- break;
- case WRITE_MAC_ENTRY:
- write_mac_table_entry(req->index, req->entry_value);
- break;
- case ADD_MAC_ENTRY:
- add_mac_table_entry(req->entry_value);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-
-/*
- the ioctl for the switch driver is developed in the conventional way
- the control type falls into some basic categories, among them, the
- SIOCETHTOOL is the traditional eth interface. VLAN_TOOLS and
- MAC_TABLE_TOOLS are designed specifically for amazon chip. User
- should be aware of the data structures used in these interfaces.
-*/
-int switch_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
-{
- struct data_req *switch_data_req = (struct data_req *) ifr->ifr_data;
- struct mac_table_req *switch_mac_table_req;
- switch (cmd) {
- case SIOCETHTOOL:
- switch_ethtool_ioctl(dev, ifr);
- break;
- case SIOCGMIIPHY: /* Get PHY address */
- break;
- case SIOCGMIIREG: /* Read MII register */
- break;
- case SIOCSMIIREG: /* Write MII register */
- break;
- case SET_ETH_SPEED_10: /* 10 Mbps */
- break;
- case SET_ETH_SPEED_100: /* 100 Mbps */
- break;
- case SET_ETH_SPEED_AUTO: /* Auto negotiate speed */
- break;
- case SET_ETH_DUPLEX_HALF: /* Half duplex. */
- break;
- case SET_ETH_DUPLEX_FULL: /* Full duplex. */
- break;
- case SET_ETH_DUPLEX_AUTO: /* Autonegotiate duplex */
- break;
- case SET_ETH_REG:
- AMAZON_SW_REG32(switch_data_req->index) = switch_data_req->value;
- break;
- case MAC_TABLE_TOOLS:
- switch_mac_table_req = (struct mac_table_req *) ifr->ifr_data;
- mac_table_tools_ioctl(dev, switch_mac_table_req);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-struct net_device_stats *switch_stats(struct net_device *dev)
-{
- struct switch_priv *priv = (struct switch_priv *) netdev_priv(dev);
- return &priv->stats;
-}
-
-int switch_change_mtu(struct net_device *dev, int new_mtu)
-{
- if (new_mtu >= 1516)
- new_mtu = 1516;
- dev->mtu = new_mtu;
- return 0;
-}
-
-int switch_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev)
-{
- u8 *buf = NULL;
- int len = 0;
- struct sk_buff *skb = NULL;
-
- len = dma_device_read(dma_dev, &buf, (void **) &skb);
-
- if (len >= 0x600) {
- printk(KERN_WARNING "amazon_mii0: packet too large %d\n", len);
- goto switch_hw_receive_err_exit;
- }
-
- /* remove CRC */
- len -= 4;
- if (skb == NULL) {
- printk(KERN_WARNING "amazon_mii0: cannot restore pointer\n");
- goto switch_hw_receive_err_exit;
- }
- if (len > (skb->end - skb->tail)) {
- printk(KERN_WARNING "amazon_mii0: BUG, len:%d end:%p tail:%p\n", (len + 4), skb->end, skb->tail);
- goto switch_hw_receive_err_exit;
- }
- skb_put(skb, len);
- skb->dev = dev;
- switch_rx(dev, len, skb);
- return OK;
-
- switch_hw_receive_err_exit:
- if (skb)
- dev_kfree_skb_any(skb);
- return -EIO;
-}
-
-int dma_intr_handler(struct dma_device_info *dma_dev, int status)
-{
- struct net_device *dev;
-
- dev = dma_dev->priv;
- switch (status) {
- case RCV_INT:
- switch_hw_receive(dev, dma_dev);
- break;
- case TX_BUF_FULL_INT:
- netif_stop_queue(dev);
- break;
- case TRANSMIT_CPT_INT:
- netif_wake_queue(dev);
- break;
- }
- return OK;
-}
-
-/* reserve 2 bytes in front of data pointer*/
-u8 *dma_buffer_alloc(int len, int *byte_offset, void **opt)
-{
- u8 *buffer = NULL;
- struct sk_buff *skb = NULL;
- skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
- if (skb == NULL) {
- return NULL;
- }
- buffer = (u8 *) (skb->data);
- skb_reserve(skb, 2);
- *(int *) opt = (int) skb;
- *byte_offset = 2;
- return buffer;
-}
-
-int dma_buffer_free(u8 * dataptr, void *opt)
-{
- struct sk_buff *skb = NULL;
- if (opt == NULL) {
- kfree(dataptr);
- } else {
- skb = (struct sk_buff *) opt;
- dev_kfree_skb_any(skb);
- }
- return OK;
-}
-
-int init_dma_device(_dma_device_info * dma_dev, struct net_device *dev)
-{
- int i;
- int num_tx_chan, num_rx_chan;
- if (strcmp(dma_dev->device_name, "switch1") == 0) {
- num_tx_chan = 1;
- num_rx_chan = 2;
- } else {
- num_tx_chan = 1;
- num_rx_chan = 2;
- }
- dma_dev->priv = dev;
-
- dma_dev->weight = 1;
- dma_dev->num_tx_chan = num_tx_chan;
- dma_dev->num_rx_chan = num_rx_chan;
- dma_dev->ack = 1;
- dma_dev->tx_burst_len = 4;
- dma_dev->rx_burst_len = 4;
- for (i = 0; i < dma_dev->num_tx_chan; i++) {
- dma_dev->tx_chan[i].weight = QOS_DEFAULT_WGT;
- dma_dev->tx_chan[i].desc_num = 10;
- dma_dev->tx_chan[i].packet_size = 0;
- dma_dev->tx_chan[i].control = 0;
- }
- for (i = 0; i < num_rx_chan; i++) {
- dma_dev->rx_chan[i].weight = QOS_DEFAULT_WGT;
- dma_dev->rx_chan[i].desc_num = 10;
- dma_dev->rx_chan[i].packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
- dma_dev->rx_chan[i].control = 0;
- }
- dma_dev->intr_handler = dma_intr_handler;
- dma_dev->buffer_alloc = dma_buffer_alloc;
- dma_dev->buffer_free = dma_buffer_free;
- return 0;
-}
-
-int switch_set_mac_address(struct net_device *dev, void *p)
-{
- struct sockaddr *addr = p;
- memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
- return OK;
-}
-
-static const struct net_device_ops amazon_mii_ops = {
- .ndo_init = switch_init,
- .ndo_open = switch_open,
- .ndo_stop = switch_release,
- .ndo_start_xmit = switch_tx,
- .ndo_do_ioctl = switch_ioctl,
- .ndo_get_stats = switch_stats,
- .ndo_change_mtu = switch_change_mtu,
- .ndo_set_mac_address = switch_set_mac_address,
- .ndo_tx_timeout = switch_tx_timeout,
-};
-
-int switch_init(struct net_device *dev)
-{
- u64 retval = 0;
- int i;
- int result;
- struct switch_priv *priv;
- ether_setup(dev); /* assign some of the fields */
- printk(KERN_INFO "amazon_mii0: %s up using ", dev->name);
- dev->watchdog_timeo = timeout;
-
- priv = netdev_priv(dev);
- priv->dma_device = (struct dma_device_info *) kmalloc(sizeof(struct dma_device_info), GFP_KERNEL);
- if (priv->num == 0) {
- sprintf(priv->dma_device->device_name, "switch1");
- } else if (priv->num == 1) {
- sprintf(priv->dma_device->device_name, "switch2");
- }
- printk("\"%s\"\n", priv->dma_device->device_name);
- init_dma_device(priv->dma_device, dev);
- result = dma_device_register(priv->dma_device);
-
- /* read the mac address from the mac table and put them into the mac table. */
- for (i = 0; i < 6; i++) {
- retval += my_ethaddr[i];
- }
- /* ethaddr not set in u-boot ? */
- if (retval == 0) {
- dev->dev_addr[0] = 0x00;
- dev->dev_addr[1] = 0x20;
- dev->dev_addr[2] = 0xda;
- dev->dev_addr[3] = 0x86;
- dev->dev_addr[4] = 0x23;
- dev->dev_addr[5] = 0x74 + (unsigned char) priv->num;
- } else {
- for (i = 0; i < 6; i++) {
- dev->dev_addr[i] = my_ethaddr[i];
- }
- dev->dev_addr[5] += +(unsigned char) priv->num;
- }
- return OK;
-}
-
-static int amazon_mii_probe(struct platform_device *dev)
-{
- int i = 0, result, device_present = 0;
- struct switch_priv *priv;
-
- for (i = 0; i < AMAZON_SW_INT_NO; i++) {
- switch_devs[i] = alloc_etherdev(sizeof(struct switch_priv));
- switch_devs[i]->netdev_ops = &amazon_mii_ops;
- strcpy(switch_devs[i]->name, "eth%d");
- priv = (struct switch_priv *) netdev_priv(switch_devs[i]);
- priv->num = i;
- if ((result = register_netdev(switch_devs[i])))
- printk(KERN_WARNING "amazon_mii0: error %i registering device \"%s\"\n", result, switch_devs[i]->name);
- else
- device_present++;
- }
- amazon_sw_chip_init();
- return device_present ? 0 : -ENODEV;
-}
-
-static int amazon_mii_remove(struct platform_device *dev)
-{
- int i;
- struct switch_priv *priv;
- for (i = 0; i < AMAZON_SW_INT_NO; i++) {
- priv = netdev_priv(switch_devs[i]);
- if (priv->dma_device) {
- dma_device_unregister(priv->dma_device);
- kfree(priv->dma_device);
- }
- kfree(netdev_priv(switch_devs[i]));
- unregister_netdev(switch_devs[i]);
- }
- return 0;
-}
-
-static struct platform_driver amazon_mii_driver = {
- .probe = amazon_mii_probe,
- .remove = amazon_mii_remove,
- .driver = {
- .name = "amazon_mii0",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init amazon_mii_init(void)
-{
- int ret = platform_driver_register(&amazon_mii_driver);
- if (ret)
- printk(KERN_WARNING "amazon_mii0: Error registering platfom driver!\n");
- return ret;
-}
-
-static void __exit amazon_mii_cleanup(void)
-{
- platform_driver_unregister(&amazon_mii_driver);
-}
-
-module_init(amazon_mii_init);
-module_exit(amazon_mii_cleanup);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Wu Qi Ming");
-MODULE_DESCRIPTION("ethernet driver for AMAZON boards");
-
+++ /dev/null
-/*
- * Driver for AMAZONASC serial ports
- *
- * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
- * Based on drivers/serial/serial_s3c2400.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Copyright (C) 2004 Infineon IFAP DC COM CPE
- * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/tty.h>
-#include <linux/tty_flip.h>
-#include <linux/major.h>
-#include <linux/string.h>
-#include <linux/fcntl.h>
-#include <linux/ptrace.h>
-#include <linux/ioport.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/circ_buf.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/console.h>
-#include <linux/sysrq.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/uaccess.h>
-#include <asm/bitops.h>
-#include <asm/amazon/amazon.h>
-#include <asm/amazon/irq.h>
-#include <asm/amazon/serial.h>
-
-#define PORT_AMAZONASC 111
-
-#include <linux/serial_core.h>
-
-#define UART_NR 1
-
-#define UART_DUMMY_UER_RX 1
-
-#define SERIAL_AMAZONASC_MAJOR TTY_MAJOR
-#define CALLOUT_AMAZONASC_MAJOR TTYAUX_MAJOR
-#define SERIAL_AMAZONASC_MINOR 64
-#define SERIAL_AMAZONASC_NR UART_NR
-
-static void amazonasc_tx_chars(struct uart_port *port);
-static struct uart_port amazonasc_ports[UART_NR];
-static struct uart_driver amazonasc_reg;
-static unsigned int uartclk = 0;
-
-static void amazonasc_stop_tx(struct uart_port *port)
-{
- /* fifo underrun shuts up after firing once */
- return;
-}
-
-static void amazonasc_start_tx(struct uart_port *port)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- amazonasc_tx_chars(port);
- local_irq_restore(flags);
-
- return;
-}
-
-static void amazonasc_stop_rx(struct uart_port *port)
-{
- /* clear the RX enable bit */
- amazon_writel(ASCWHBCON_CLRREN, AMAZON_ASC_WHBCON);
-}
-
-static void amazonasc_enable_ms(struct uart_port *port)
-{
- /* no modem signals */
- return;
-}
-
-#include <linux/version.h>
-
-static void
-amazonasc_rx_chars(struct uart_port *port)
-{
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31))
- struct tty_struct *tty = port->state->port.tty;
-#else
- struct tty_struct *tty = port->info->port.tty;
-#endif
- unsigned int ch = 0, rsr = 0, fifocnt;
-
- fifocnt = amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
- while (fifocnt--)
- {
- u8 flag = TTY_NORMAL;
- ch = amazon_readl(AMAZON_ASC_RBUF);
- rsr = (amazon_readl(AMAZON_ASC_CON) & ASCCON_ANY) | UART_DUMMY_UER_RX;
- tty_flip_buffer_push(tty);
- port->icount.rx++;
-
- /*
- * Note that the error handling code is
- * out of the main execution path
- */
- if (rsr & ASCCON_ANY) {
- if (rsr & ASCCON_PE) {
- port->icount.parity++;
- amazon_writel_masked(AMAZON_ASC_WHBCON, ASCWHBCON_CLRPE, ASCWHBCON_CLRPE);
- } else if (rsr & ASCCON_FE) {
- port->icount.frame++;
- amazon_writel_masked(AMAZON_ASC_WHBCON, ASCWHBCON_CLRFE, ASCWHBCON_CLRFE);
- }
- if (rsr & ASCCON_OE) {
- port->icount.overrun++;
- amazon_writel_masked(AMAZON_ASC_WHBCON, ASCWHBCON_CLROE, ASCWHBCON_CLROE);
- }
-
- rsr &= port->read_status_mask;
-
- if (rsr & ASCCON_PE)
- flag = TTY_PARITY;
- else if (rsr & ASCCON_FE)
- flag = TTY_FRAME;
- }
-
- if ((rsr & port->ignore_status_mask) == 0)
- tty_insert_flip_char(tty, ch, flag);
-
- if (rsr & ASCCON_OE)
- /*
- * Overrun is special, since it's reported
- * immediately, and doesn't affect the current
- * character
- */
- tty_insert_flip_char(tty, 0, TTY_OVERRUN);
- }
- if (ch != 0)
- tty_flip_buffer_push(tty);
-
- return;
-}
-
-
-static void amazonasc_tx_chars(struct uart_port *port)
-{
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31))
- struct circ_buf *xmit = &port->state->xmit;
-#else
- struct circ_buf *xmit = &port->info->xmit;
-#endif
-
- if (uart_tx_stopped(port)) {
- amazonasc_stop_tx(port);
- return;
- }
-
- while (((amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
- >> ASCFSTAT_TXFFLOFF) != AMAZONASC_TXFIFO_FULL)
- {
- if (port->x_char) {
- amazon_writel(port->x_char, AMAZON_ASC_TBUF);
- port->icount.tx++;
- port->x_char = 0;
- continue;
- }
-
- if (uart_circ_empty(xmit))
- break;
-
- amazon_writel(xmit->buf[xmit->tail], AMAZON_ASC_TBUF);
- xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
- port->icount.tx++;
- }
-
- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
- uart_write_wakeup(port);
-}
-
-static irqreturn_t amazonasc_tx_int(int irq, void *port)
-{
- amazon_writel(ASC_IRNCR_TIR, AMAZON_ASC_IRNCR1);
- amazonasc_start_tx(port);
-
- /* clear any pending interrupts */
- amazon_writel_masked(AMAZON_ASC_WHBCON,
- (ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE),
- (ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE));
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t amazonasc_er_int(int irq, void *port)
-{
- /* clear any pending interrupts */
- amazon_writel_masked(AMAZON_ASC_WHBCON,
- (ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE),
- (ASCWHBCON_CLRPE | ASCWHBCON_CLRFE | ASCWHBCON_CLROE));
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t amazonasc_rx_int(int irq, void *port)
-{
- amazon_writel(ASC_IRNCR_RIR, AMAZON_ASC_IRNCR1);
- amazonasc_rx_chars((struct uart_port *) port);
- return IRQ_HANDLED;
-}
-
-static u_int amazonasc_tx_empty(struct uart_port *port)
-{
- int status;
-
- /*
- * FSTAT tells exactly how many bytes are in the FIFO.
- * The question is whether we really need to wait for all
- * 16 bytes to be transmitted before reporting that the
- * transmitter is empty.
- */
- status = amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
- return status ? 0 : TIOCSER_TEMT;
-}
-
-static u_int amazonasc_get_mctrl(struct uart_port *port)
-{
- /* no modem control signals - the readme says to pretend all are set */
- return TIOCM_CTS|TIOCM_CAR|TIOCM_DSR;
-}
-
-static void amazonasc_set_mctrl(struct uart_port *port, u_int mctrl)
-{
- /* no modem control - just return */
- return;
-}
-
-static void amazonasc_break_ctl(struct uart_port *port, int break_state)
-{
- /* no way to send a break */
- return;
-}
-
-static int amazonasc_startup(struct uart_port *port)
-{
- unsigned int con = 0;
- unsigned long flags;
- int retval;
-
- /* this assumes: CON.BRS = CON.FDE = 0 */
- if (uartclk == 0)
- uartclk = amazon_get_fpi_hz();
-
- amazonasc_ports[0].uartclk = uartclk;
-
- local_irq_save(flags);
-
- /* this setup was probably already done in u-boot */
- /* ASC and GPIO Port 1 bits 3 and 4 share the same pins
- * P1.3 (RX) in, Alternate 10
- * P1.4 (TX) in, Alternate 10
- */
- amazon_writel_masked(AMAZON_GPIO_P1_DIR, 0x18, 0x10); //P1.4 output, P1.3 input
- amazon_writel_masked(AMAZON_GPIO_P1_ALTSEL0, 0x18, 0x18); //ALTSETL0 11
- amazon_writel_masked(AMAZON_GPIO_P1_ALTSEL1, 0x18, 0); //ALTSETL1 00
- amazon_writel_masked(AMAZON_GPIO_P1_OD, 0x18, 0x10);
-
- /* set up the CLC */
- amazon_writel_masked(AMAZON_ASC_CLC, AMAZON_ASC_CLC_DISS, 0);
- amazon_writel_masked(AMAZON_ASC_CLC, ASCCLC_RMCMASK, 1 << ASCCLC_RMCOFFSET);
-
- /* asynchronous mode */
- con = ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_OEN | ASCCON_PEN;
-
- /* choose the line - there's only one */
- amazon_writel(0, AMAZON_ASC_PISEL);
- amazon_writel(((AMAZONASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
- AMAZON_ASC_TXFCON);
- amazon_writel(((AMAZONASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
- AMAZON_ASC_RXFCON);
- wmb();
-
- amazon_writel_masked(AMAZON_ASC_CON, con, con);
-
- retval = request_irq(AMAZONASC_RIR, amazonasc_rx_int, 0, "asc_rx", port);
- if (retval){
- printk("failed to request amazonasc_rx_int\n");
- return retval;
- }
- retval = request_irq(AMAZONASC_TIR, amazonasc_tx_int, 0, "asc_tx", port);
- if (retval){
- printk("failed to request amazonasc_tx_int\n");
- goto err1;
- }
-
- retval = request_irq(AMAZONASC_EIR, amazonasc_er_int, 0, "asc_er", port);
- if (retval){
- printk("failed to request amazonasc_er_int\n");
- goto err2;
- }
-
- local_irq_restore(flags);
- return 0;
-
-err2:
- free_irq(AMAZONASC_TIR, port);
-
-err1:
- free_irq(AMAZONASC_RIR, port);
- local_irq_restore(flags);
- return retval;
-}
-
-static void amazonasc_shutdown(struct uart_port *port)
-{
- free_irq(AMAZONASC_RIR, port);
- free_irq(AMAZONASC_TIR, port);
- free_irq(AMAZONASC_EIR, port);
- /*
- * disable the baudrate generator to disable the ASC
- */
- amazon_writel(0, AMAZON_ASC_CON);
-
- /* flush and then disable the fifos */
- amazon_writel_masked(AMAZON_ASC_RXFCON, ASCRXFCON_RXFFLU, ASCRXFCON_RXFFLU);
- amazon_writel_masked(AMAZON_ASC_RXFCON, ASCRXFCON_RXFEN, 0);
- amazon_writel_masked(AMAZON_ASC_TXFCON, ASCTXFCON_TXFFLU, ASCTXFCON_TXFFLU);
- amazon_writel_masked(AMAZON_ASC_TXFCON, ASCTXFCON_TXFEN, 0);
-}
-
-static void amazonasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
-{
- unsigned int cflag;
- unsigned int iflag;
- unsigned int baud, quot;
- unsigned int con = 0;
- unsigned long flags;
-
- cflag = new->c_cflag;
- iflag = new->c_iflag;
-
- /* byte size and parity */
- switch (cflag & CSIZE) {
- /* 7 bits are always with parity */
- case CS7: con = ASCCON_M_7ASYNCPAR; break;
- /* the ASC only suports 7 and 8 bits */
- case CS5:
- case CS6:
- default:
- if (cflag & PARENB)
- con = ASCCON_M_8ASYNCPAR;
- else
- con = ASCCON_M_8ASYNC;
- break;
- }
- if (cflag & CSTOPB)
- con |= ASCCON_STP;
- if (cflag & PARENB) {
- if (!(cflag & PARODD))
- con &= ~ASCCON_ODD;
- else
- con |= ASCCON_ODD;
- }
-
- port->read_status_mask = ASCCON_OE;
- if (iflag & INPCK)
- port->read_status_mask |= ASCCON_FE | ASCCON_PE;
-
- port->ignore_status_mask = 0;
- if (iflag & IGNPAR)
- port->ignore_status_mask |= ASCCON_FE | ASCCON_PE;
-
- if (iflag & IGNBRK) {
- /*
- * If we're ignoring parity and break indicators,
- * ignore overruns too (for real raw support).
- */
- if (iflag & IGNPAR)
- port->ignore_status_mask |= ASCCON_OE;
- }
-
- /*
- * Ignore all characters if CREAD is not set.
- */
- if ((cflag & CREAD) == 0)
- port->ignore_status_mask |= UART_DUMMY_UER_RX;
-
- /* set error signals - framing, parity and overrun */
- con |= ASCCON_FEN;
- con |= ASCCON_OEN;
- con |= ASCCON_PEN;
- /* enable the receiver */
- con |= ASCCON_REN;
-
- /* block the IRQs */
- local_irq_save(flags);
-
- /* set up CON */
- amazon_writel(con, AMAZON_ASC_CON);
-
- /* Set baud rate - take a divider of 2 into account */
- baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
- quot = uart_get_divisor(port, baud);
- quot = quot/2 - 1;
-
- /* the next 3 probably already happened when we set CON above */
- /* disable the baudrate generator */
- amazon_writel_masked(AMAZON_ASC_CON, ASCCON_R, 0);
- /* make sure the fractional divider is off */
- amazon_writel_masked(AMAZON_ASC_CON, ASCCON_FDE, 0);
- /* set up to use divisor of 2 */
- amazon_writel_masked(AMAZON_ASC_CON, ASCCON_BRS, 0);
- /* now we can write the new baudrate into the register */
- amazon_writel(quot, AMAZON_ASC_BTR);
- /* turn the baudrate generator back on */
- amazon_writel_masked(AMAZON_ASC_CON, ASCCON_R, ASCCON_R);
-
- local_irq_restore(flags);
-}
-
-static const char *amazonasc_type(struct uart_port *port)
-{
- return port->type == PORT_AMAZONASC ? "AMAZONASC" : NULL;
-}
-
-/*
- * Release the memory region(s) being used by 'port'
- */
-static void amazonasc_release_port(struct uart_port *port)
-{
- return;
-}
-
-/*
- * Request the memory region(s) being used by 'port'
- */
-static int amazonasc_request_port(struct uart_port *port)
-{
- return 0;
-}
-
-/*
- * Configure/autoconfigure the port.
- */
-static void amazonasc_config_port(struct uart_port *port, int flags)
-{
- if (flags & UART_CONFIG_TYPE) {
- port->type = PORT_AMAZONASC;
- amazonasc_request_port(port);
- }
-}
-
-/*
- * verify the new serial_struct (for TIOCSSERIAL).
- */
-static int amazonasc_verify_port(struct uart_port *port, struct serial_struct *ser)
-{
- int ret = 0;
- if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMAZONASC)
- ret = -EINVAL;
- if (ser->irq < 0 || ser->irq >= NR_IRQS)
- ret = -EINVAL;
- if (ser->baud_base < 9600)
- ret = -EINVAL;
- return ret;
-}
-
-static struct uart_ops amazonasc_pops = {
- .tx_empty = amazonasc_tx_empty,
- .set_mctrl = amazonasc_set_mctrl,
- .get_mctrl = amazonasc_get_mctrl,
- .stop_tx = amazonasc_stop_tx,
- .start_tx = amazonasc_start_tx,
- .stop_rx = amazonasc_stop_rx,
- .enable_ms = amazonasc_enable_ms,
- .break_ctl = amazonasc_break_ctl,
- .startup = amazonasc_startup,
- .shutdown = amazonasc_shutdown,
- .set_termios = amazonasc_set_termios,
- .type = amazonasc_type,
- .release_port = amazonasc_release_port,
- .request_port = amazonasc_request_port,
- .config_port = amazonasc_config_port,
- .verify_port = amazonasc_verify_port,
-};
-
-static struct uart_port amazonasc_ports[UART_NR] = {
- {
- membase: (void *)AMAZON_ASC,
- mapbase: AMAZON_ASC,
- iotype: SERIAL_IO_MEM,
- irq: AMAZONASC_RIR, /* RIR */
- uartclk: 0, /* filled in dynamically */
- fifosize: 16,
- unused: { AMAZONASC_TIR, AMAZONASC_EIR}, /* xmit/error/xmit-buffer-empty IRQ */
- type: PORT_AMAZONASC,
- ops: &amazonasc_pops,
- flags: ASYNC_BOOT_AUTOCONF,
- },
-};
-
-static void amazonasc_console_write(struct console *co, const char *s, u_int count)
-{
- int i, fifocnt;
- unsigned long flags;
- local_irq_save(flags);
- for (i = 0; i < count;)
- {
- /* wait until the FIFO is not full */
- do
- {
- fifocnt = (amazon_readl(AMAZON_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
- >> ASCFSTAT_TXFFLOFF;
- } while (fifocnt == AMAZONASC_TXFIFO_FULL);
- if (s[i] == '\0')
- {
- break;
- }
- if (s[i] == '\n')
- {
- amazon_writel('\r', AMAZON_ASC_TBUF);
- do
- {
- fifocnt = (amazon_readl(AMAZON_ASC_FSTAT) &
- ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF;
- } while (fifocnt == AMAZONASC_TXFIFO_FULL);
- }
- amazon_writel(s[i], AMAZON_ASC_TBUF);
- i++;
- }
-
- local_irq_restore(flags);
-}
-
-static void __init
-amazonasc_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
-{
- u_int lcr_h;
-
- lcr_h = amazon_readl(AMAZON_ASC_CON);
- /* do this only if the ASC is turned on */
- if (lcr_h & ASCCON_R) {
- u_int quot, div, fdiv, frac;
-
- *parity = 'n';
- if ((lcr_h & ASCCON_MODEMASK) == ASCCON_M_7ASYNCPAR ||
- (lcr_h & ASCCON_MODEMASK) == ASCCON_M_8ASYNCPAR) {
- if (lcr_h & ASCCON_ODD)
- *parity = 'o';
- else
- *parity = 'e';
- }
-
- if ((lcr_h & ASCCON_MODEMASK) == ASCCON_M_7ASYNCPAR)
- *bits = 7;
- else
- *bits = 8;
-
- quot = amazon_readl(AMAZON_ASC_BTR) + 1;
-
- /* this gets hairy if the fractional divider is used */
- if (lcr_h & ASCCON_FDE)
- {
- div = 1;
- fdiv = amazon_readl(AMAZON_ASC_FDV);
- if (fdiv == 0)
- fdiv = 512;
- frac = 512;
- }
- else
- {
- div = lcr_h & ASCCON_BRS ? 3 : 2;
- fdiv = frac = 1;
- }
- /*
- * This doesn't work exactly because we use integer
- * math to calculate baud which results in rounding
- * errors when we try to go from quot -> baud !!
- * Try to make this work for both the fractional divider
- * and the simple divider. Also try to avoid rounding
- * errors using integer math.
- */
-
- *baud = frac * (port->uartclk / (div * 512 * 16 * quot));
- if (*baud > 1100 && *baud < 2400)
- *baud = 1200;
- if (*baud > 2300 && *baud < 4800)
- *baud = 2400;
- if (*baud > 4700 && *baud < 9600)
- *baud = 4800;
- if (*baud > 9500 && *baud < 19200)
- *baud = 9600;
- if (*baud > 19000 && *baud < 38400)
- *baud = 19200;
- if (*baud > 38400 && *baud < 57600)
- *baud = 38400;
- if (*baud > 57600 && *baud < 115200)
- *baud = 57600;
- if (*baud > 115200 && *baud < 230400)
- *baud = 115200;
- }
-}
-
-static int __init amazonasc_console_setup(struct console *co, char *options)
-{
- struct uart_port *port;
- int baud = 115200;
- int bits = 8;
- int parity = 'n';
- int flow = 'n';
-
- /* this assumes: CON.BRS = CON.FDE = 0 */
- if (uartclk == 0)
- uartclk = amazon_get_fpi_hz();
- co->index = 0;
- port = &amazonasc_ports[0];
- amazonasc_ports[0].uartclk = uartclk;
- amazonasc_ports[0].type = PORT_AMAZONASC;
-
- if (options){
- uart_parse_options(options, &baud, &parity, &bits, &flow);
- }
-
- return uart_set_options(port, co, baud, parity, bits, flow);
-}
-
-static struct uart_driver amazonasc_reg;
-static struct console amazonasc_console = {
- name: "ttyS",
- write: amazonasc_console_write,
- device: uart_console_device,
- setup: amazonasc_console_setup,
- flags: CON_PRINTBUFFER,
- index: -1,
- data: &amazonasc_reg,
-};
-
-static struct uart_driver amazonasc_reg = {
- .owner = THIS_MODULE,
- .driver_name = "serial",
- .dev_name = "ttyS",
- .major = TTY_MAJOR,
- .minor = 64,
- .nr = UART_NR,
- .cons = &amazonasc_console,
-};
-
-static int amazon_asc_probe(struct platform_device *dev)
-{
- unsigned char res;
- uart_register_driver(&amazonasc_reg);
- res = uart_add_one_port(&amazonasc_reg, &amazonasc_ports[0]);
- return res;
-}
-
-static int amazon_asc_remove(struct platform_device *dev)
-{
- uart_unregister_driver(&amazonasc_reg);
- return 0;
-}
-
-static struct platform_driver amazon_asc_driver = {
- .probe = amazon_asc_probe,
- .remove = amazon_asc_remove,
- .driver = {
- .name = "amazon_asc",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init amazon_asc_init(void)
-{
- int ret = platform_driver_register(&amazon_asc_driver);
- if (ret)
- printk(KERN_WARNING "amazon_asc: error registering platfom driver!\n");
- return ret;
-}
-
-static void __exit amazon_asc_cleanup(void)
-{
- platform_driver_unregister(&amazon_asc_driver);
-}
-
-module_init(amazon_asc_init);
-module_exit(amazon_asc_cleanup);
-
-MODULE_AUTHOR("Gary Jennejohn, Felix Fietkau, John Crispin");
-MODULE_DESCRIPTION("MIPS AMAZONASC serial port driver");
-MODULE_LICENSE("GPL");
-
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Copyright 2004 Wu Qi Ming <gokimi@msn.com>
- * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/version.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/timer.h>
-#include <linux/fs.h>
-#include <linux/errno.h>
-#include <linux/proc_fs.h>
-#include <linux/stat.h>
-#include <linux/tty.h>
-#include <linux/selection.h>
-#include <linux/kmod.h>
-#include <linux/vmalloc.h>
-#include <linux/kdev_t.h>
-#include <linux/ioctl.h>
-#include <asm/uaccess.h>
-#include <asm/system.h>
-#include <linux/platform_device.h>
-#include <asm/amazon/amazon.h>
-#include <asm/amazon/amazon_wdt.h>
-
-#define DRV_NAME "AMAZON WDT:"
-
-#undef AMAZON_WDT_DEBUG
-
-static int amazon_wdt_isopen = 0;
-
-#ifdef AMAZON_WDT_DEBUG
-static struct proc_dir_entry* amazon_wdt_dir;
-#endif
-
-int wdt_enable(int timeout)
-{
- u32 hard_psw, ffpi;
- int reload_value, divider = 1;
-
- ffpi = amazon_get_fpi_hz();
-
- reload_value = 65536 - timeout * ffpi / 256;
-
- if (reload_value < 0) {
- divider = 0;
- reload_value = 65536 - timeout * ffpi / 16384;
- }
-
- if (reload_value < 0){
- printk(KERN_INFO DRV_NAME "timeout too large %d\n", timeout);
- return -EINVAL;
- }
-
- printk(KERN_INFO DRV_NAME "timeout:%d reload_value: %8x\n", timeout, reload_value);
-
- hard_psw = (amazon_readl(AMAZON_WDT_CON0) & 0xffffff01) +
- (amazon_readl(AMAZON_WDT_CON1) & 0xc) + 0xf0;
- amazon_writel(hard_psw, AMAZON_WDT_CON0);
- wmb();
-
- amazon_writel((hard_psw & 0xff00) + (reload_value << 16) + 0xf2, AMAZON_WDT_CON0);
- wmb();
-
- amazon_writel(divider << 2, AMAZON_WDT_CON1);
- wmb();
-
- hard_psw = (amazon_readl(AMAZON_WDT_CON0) & 0xffffff01) +
- (amazon_readl(AMAZON_WDT_CON1) & 0xc) + 0xf0;
- amazon_writel(hard_psw, AMAZON_WDT_CON0);
- wmb();
-
- amazon_writel_masked(AMAZON_WDT_CON0, 0xff, 0xf3);
- wmb();
- return 0;
-}
-
-void wdt_disable(void)
-{
- u32 hard_psw = 0;
-
- hard_psw = (amazon_readl(AMAZON_WDT_CON0) & 0xffffff01) +
- (amazon_readl(AMAZON_WDT_CON1) & 0xc) + 0xf0;
- amazon_writel(hard_psw, AMAZON_WDT_CON0);
- wmb();
-
- amazon_writel_masked(AMAZON_WDT_CON0, 0xff, 0xf2);
- wmb();
-
- amazon_writel_masked(AMAZON_WDT_CON1, 0x8, 0x8);
- wmb();
-
- hard_psw=(amazon_readl(AMAZON_WDT_CON0) & 0xffffff01) +
- (amazon_readl(AMAZON_WDT_CON1) & 0xc) + 0xf0;
- amazon_writel(hard_psw, AMAZON_WDT_CON0);
- wmb();
-
- amazon_writel_masked(AMAZON_WDT_CON0, 0xff, 0xf3);
- wmb();
-
- return;
-}
-
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))
-static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-#else
-static int wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
-#endif
-{
- int result=0;
- static int timeout=-1;
-
- switch(cmd){
- case AMAZON_WDT_IOC_START:
- printk(KERN_INFO DRV_NAME "enable watch dog timer!\n");
- if (copy_from_user((void*)&timeout, (void*)arg, sizeof (int))) {
- printk(KERN_INFO DRV_NAME "invalid argument\n");
- result=-EINVAL;
- } else if ((result = wdt_enable(timeout)) < 0) {
- timeout = -1;
- }
- break;
-
- case AMAZON_WDT_IOC_STOP:
- printk(KERN_INFO DRV_NAME "disable watch dog timer\n");
- timeout = -1;
- wdt_disable();
- break;
-
- case AMAZON_WDT_IOC_PING:
- if (timeout < 0) {
- result = -EIO;
- } else {
- result = wdt_enable(timeout);
- }
- break;
-
- default:
- result=-EINVAL;
- break;
- }
- return result;
-}
-
-static ssize_t wdt_read(struct file *file, char *buf, size_t count, loff_t *offset)
-{
- return 0;
-}
-
-static ssize_t wdt_write(struct file *file, const char *buf, size_t count, loff_t *offset)
-{
- return count;
-}
-
-static int wdt_open(struct inode *inode, struct file *file)
-{
- if (amazon_wdt_isopen == 1)
- return -EBUSY;
-
- amazon_wdt_isopen = 1;
- printk(KERN_INFO DRV_NAME "opened\n");
- return 0;
-}
-
-static int wdt_release(struct inode *inode, struct file *file)
-{
- amazon_wdt_isopen = 0;
- printk(KERN_INFO DRV_NAME "closed\n");
- return 0;
-}
-
-#ifdef AMAZON_WDT_DEBUG
-int wdt_register_proc_read(char *buf, char **start, off_t offset,
- int count, int *eof, void *data)
-{
- int len=0;
- len+=sprintf(buf+len,"NMISR: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_NMISR));
- len+=sprintf(buf+len,"RST_REQ: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_RST_REQ));
- len+=sprintf(buf+len,"RST_SR: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_RST_SR));
- len+=sprintf(buf+len,"WDT_CON0: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_CON0));
- len+=sprintf(buf+len,"WDT_CON1: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_CON1));
- len+=sprintf(buf+len,"WDT_SR: 0x%08x\n",AMAZON_WDT_REG32(AMAZON_WDT_SR));
- *eof = 1;
- return len;
-}
-#endif
-
-static struct file_operations wdt_fops = {
- read: wdt_read,
- write: wdt_write,
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))
- unlocked_ioctl: wdt_ioctl,
-#else
- ioctl: wdt_ioctl,
-#endif
- open: wdt_open,
- release: wdt_release,
-};
-
-static int amazon_wdt_probe(struct platform_device *dev)
-{
- int result = result = register_chrdev(0, "watchdog", &wdt_fops);
-
- if (result < 0) {
- printk(KERN_INFO DRV_NAME "cannot register device\n");
- return result;
- }
-
-#ifdef AMAZON_WDT_DEBUG
- amazon_wdt_dir=proc_mkdir("amazon_wdt",NULL);
- create_proc_read_entry("wdt_register", 0, amazon_wdt_dir,
- wdt_register_proc_read, NULL);
-#endif
-
- amazon_wdt_isopen=0;
- printk(KERN_INFO DRV_NAME "driver loaded but inactive\n");
- return 0;
-}
-
-static int amazon_wdt_remove(struct platform_device *dev)
-{
- unregister_chrdev(0, "watchdog");
-#ifdef AMAZON_WDT_DEBUG
- remove_proc_entry("wdt_register", amazon_wdt_dir);
- remove_proc_entry("amazon_wdt", NULL);
-#endif
- printk(KERN_INFO DRV_NAME "unregistered\n");
- return 0;
-}
-
-static struct platform_driver amazon_wdt_driver = {
- .probe = amazon_wdt_probe,
- .remove = amazon_wdt_remove,
- .driver = {
- .name = "amazon_wdt",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init amazon_wdt_init(void)
-{
- int ret = platform_driver_register(&amazon_wdt_driver);
- if (ret)
- printk(KERN_WARNING "amazon_wdt: error registering platfom driver!\n");
- return ret;
-}
-
-static void __exit amazon_wdt_exit(void)
-{
- platform_driver_unregister(&amazon_wdt_driver);
-}
-
-module_init(amazon_wdt_init);
-module_exit(amazon_wdt_exit);
-
-MODULE_LICENSE ("GPL");
-MODULE_AUTHOR("Infineon / John Crispin <blogic@openwrt.org>");
-MODULE_DESCRIPTION("AMAZON WDT driver");
-
+++ /dev/null
-/******************************************************************************
- Copyright (c) 2004, Infineon Technologies. All rights reserved.
-
- No Warranty
- Because the program is licensed free of charge, there is no warranty for
- the program, to the extent permitted by applicable law. Except when
- otherwise stated in writing the copyright holders and/or other parties
- provide the program "as is" without warranty of any kind, either
- expressed or implied, including, but not limited to, the implied
- warranties of merchantability and fitness for a particular purpose. The
- entire risk as to the quality and performance of the program is with
- you. should the program prove defective, you assume the cost of all
- necessary servicing, repair or correction.
-
- In no event unless required by applicable law or agreed to in writing
- will any copyright holder, or any other party who may modify and/or
- redistribute the program as permitted above, be liable to you for
- damages, including any general, special, incidental or consequential
- damages arising out of the use or inability to use the program
- (including but not limited to loss of data or data being rendered
- inaccurate or losses sustained by you or third parties or a failure of
- the program to operate with any other programs), even if such holder or
- other party has been advised of the possibility of such damages.
- ******************************************************************************
- Module : ifx_swdrv.h
- Date : 2004-09-01
- Description : JoeLin
- Remarks:
-
- *****************************************************************************/
-
-#ifndef _ADM_6996_MODULE_H_
-#define _ADM_6996_MODULE_H_
-
-#include <asm/amazon/amazon.h>
-
-#define ifx_printf(x) printk x
-
-/* command codes */
-#define ADM_SW_SMI_READ 0x02
-#define ADM_SW_SMI_WRITE 0x01
-#define ADM_SW_SMI_START 0x01
-
-#define ADM_SW_EEPROM_WRITE 0x01
-#define ADM_SW_EEPROM_WRITE_ENABLE 0x03
-#define ADM_SW_EEPROM_WRITE_DISABLE 0x00
-#define EEPROM_TYPE 8 /* for 93C66 */
-
-/* bit masks */
-#define ADM_SW_BIT_MASK_1 0x00000001
-#define ADM_SW_BIT_MASK_2 0x00000002
-#define ADM_SW_BIT_MASK_4 0x00000008
-#define ADM_SW_BIT_MASK_10 0x00000200
-#define ADM_SW_BIT_MASK_16 0x00008000
-#define ADM_SW_BIT_MASK_32 0x80000000
-
-/* delay timers */
-#define ADM_SW_MDC_DOWN_DELAY 5
-#define ADM_SW_MDC_UP_DELAY 5
-#define ADM_SW_CS_DELAY 5
-
-/* MDIO modes */
-#define ADM_SW_MDIO_OUTPUT 1
-#define ADM_SW_MDIO_INPUT 0
-
-#define ADM_SW_MAX_PORT_NUM 5
-#define ADM_SW_MAX_VLAN_NUM 15
-
-/* registers */
-#define ADM_SW_PORT0_CONF 0x1
-#define ADM_SW_PORT1_CONF 0x3
-#define ADM_SW_PORT2_CONF 0x5
-#define ADM_SW_PORT3_CONF 0x7
-#define ADM_SW_PORT4_CONF 0x8
-#define ADM_SW_PORT5_CONF 0x9
-#define ADM_SW_VLAN_MODE 0x11
-#define ADM_SW_MAC_LOCK 0x12
-#define ADM_SW_VLAN0_CONF 0x13
-#define ADM_SW_PORT0_PVID 0x28
-#define ADM_SW_PORT1_PVID 0x29
-#define ADM_SW_PORT2_PVID 0x2a
-#define ADM_SW_PORT34_PVID 0x2b
-#define ADM_SW_PORT5_PVID 0x2c
-#define ADM_SW_PHY_RESET 0x2f
-#define ADM_SW_MISC_CONF 0x30
-#define ADM_SW_BNDWDH_CTL0 0x31
-#define ADM_SW_BNDWDH_CTL1 0x32
-#define ADM_SW_BNDWDH_CTL_ENA 0x33
-
-/* port modes */
-#define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */
-#define ADM_SW_PORT_AN 0x2 /* auto negotiation */
-#define ADM_SW_PORT_100M 0x4 /* 100M */
-#define ADM_SW_PORT_FULL 0x8 /* full duplex */
-#define ADM_SW_PORT_TAG 0x10 /* output tag on */
-#define ADM_SW_PORT_DISABLE 0x20 /* disable port */
-#define ADM_SW_PORT_TOS 0x40 /* TOS first */
-#define ADM_SW_PORT_PPRI 0x80 /* port based priority first */
-#define ADM_SW_PORT_MDIX 0x8000 /* auto MDIX on */
-#define ADM_SW_PORT_PVID_SHIFT 10
-#define ADM_SW_PORT_PVID_BITS 4
-
-/* VLAN */
-#define ADM_SW_VLAN_PORT0 0x1
-#define ADM_SW_VLAN_PORT1 0x2
-#define ADM_SW_VLAN_PORT2 0x10
-#define ADM_SW_VLAN_PORT3 0x40
-#define ADM_SW_VLAN_PORT4 0x80
-#define ADM_SW_VLAN_PORT5 0x100
-
-
-/* GPIO 012 enabled, output mode */
-#define GPIO_ENABLEBITS 0x000700f8
-
-/*
- define AMAZON GPIO port to ADM6996 EEPROM interface
- MDIO -> EEDI GPIO 16, AMAZON GPIO P1.0, bi-direction
- MDC -> EESK GPIO 17, AMAZON GPIO P1.1, output only
- MDCS -> EECS GPIO 18, AMAZON GPIO P1.2, output only
- EEDO GPIO 15, AMAZON GPIO P0.15, do not need this one! */
-
-#define GPIO_MDIO 1 //P1.0
-#define GPIO_MDC 2 //P1.1
-#define GPIO_MDCS 4 //P1.2
-
-//joelin #define GPIO_MDIO 0
-//joelin #define GPIO_MDC 5 /* PORT 0 GPIO5 */
-//joelin #define GPIO_MDCS 6 /* PORT 0 GPIO6 */
-
-
-#define MDIO_INPUT 0x00000001
-#define MDIO_OUTPUT_EN 0x00010000
-
-
-/* type definitions */
-typedef unsigned char U8;
-typedef unsigned short U16;
-typedef unsigned int U32;
-
-typedef struct _REGRW_
-{
- unsigned int addr;
- unsigned int value;
- unsigned int mode;
-}REGRW, *PREGRW;
-
-//joelin adm6996i
-typedef struct _MACENTRY_
-{
- unsigned char mac_addr[6];
- unsigned long fid:4;
- unsigned long portmap:6;
- union {
- unsigned long age_timer:9;
- unsigned long info_ctrl:9;
- } ctrl;
- unsigned long occupy:1;
- unsigned long info_type:1;
- unsigned long bad:1;
- unsigned long result:3;//000:command ok ,001:all entry used,010:Entry Not found ,011:try next entry ,101:command error
-
- }MACENTRY, *PMACENTRY;
-typedef struct _PROTOCOLFILTER_
-{
- int protocol_filter_num;//[0~7]
- int ip_p; //Value Compared with Protocol in IP Heade[7:0]
- char action:2;//Action for protocol Filter .
-//00 = Protocol Portmap is Default Output Ports.
-//01 = Protocol Portmap is 6'b0.
-//10 = Protocol Portmap is the CPU port if the incoming port
-//is not the CPU port. But if the incoming port is the CPU port, then Type Portmap contains Default Output Ports, excluding the CPU port.
- }PROTOCOLFILTER, *PPROTOCOLFILTER;
-
-//joelin adm6996i
-
-/* Santosh: for IGMP proxy/snooping */
-
-//050614:fchang int adm_process_mac_table_request (unsigned int cmd, struct _MACENTRY_ *mac);
-//050614:fchang int adm_process_protocol_filter_request (unsigned int cmd, struct _PROTOCOLFILTER_ *filter);
-
-
-/* IOCTL keys */
-#define KEY_IOCTL_ADM_REGRW 0x01
-#define KEY_IOCTL_ADM_SW_REGRW 0x02
-#define KEY_IOCTL_ADM_SW_PORTSTS 0x03
-#define KEY_IOCTL_ADM_SW_INIT 0x04
-//for adm6996i-start
-#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD 0x05
-#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL 0x06
-#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT 0x07
-#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE 0x08
-#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD 0x09
-#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL 0x0a
-#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET 0x0b
-
-//adm6996i #define KEY_IOCTL_MAX_KEY 0x05
-#define KEY_IOCTL_MAX_KEY 0x0c
-//for adm6996i-end
-/* IOCTL MAGIC */
-#define ADM_MAGIC ('a'|'d'|'m'|'t'|'e'|'k')
-
-/* IOCTL parameters */
-#define ADM_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_REGRW, REGRW)
-#define ADM_SW_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_REGRW, REGRW)
-#define ADM_SW_IOCTL_PORTSTS _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS, NULL)
-#define ADM_SW_IOCTL_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT, NULL)
-
-
-//6996i-stat
-#define ADM_SW_IOCTL_MACENTRY_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD,MACENTRY)
-#define ADM_SW_IOCTL_MACENTRY_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL,MACENTRY)
-#define ADM_SW_IOCTL_MACENTRY_GET_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT,MACENTRY)
-#define ADM_SW_IOCTL_MACENTRY_GET_MORE _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE,MACENTRY)
-#define ADM_SW_IOCTL_FILTER_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD,PROTOCOLFILTER)
-#define ADM_SW_IOCTL_FILTER_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL,PROTOCOLFILTER)
-#define ADM_SW_IOCTL_FILTER_GET _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET,PROTOCOLFILTER)
-
-//6996i-end
-
-
-#define REG_READ 0x0
-#define REG_WRITE 0x1
-
-/* undefine symbol */
-#define AMAZON_SW_REG(reg) *((volatile U32*)(reg))
-//#define GPIO0_INPUT_MASK 0
-//#define GPIO_conf0_REG 0x12345678
-//#define GPIO_SET_HI
-//#define GPIO_SET_LOW
-
-#endif
-/* _ADM_6996_MODULE_H_ */
+++ /dev/null
-#ifndef AMAZON_H
-#define AMAZON_H
-/******************************************************************************
- Copyright (c) 2002, Infineon Technologies. All rights reserved.
-
- No Warranty
- Because the program is licensed free of charge, there is no warranty for
- the program, to the extent permitted by applicable law. Except when
- otherwise stated in writing the copyright holders and/or other parties
- provide the program "as is" without warranty of any kind, either
- expressed or implied, including, but not limited to, the implied
- warranties of merchantability and fitness for a particular purpose. The
- entire risk as to the quality and performance of the program is with
- you. should the program prove defective, you assume the cost of all
- necessary servicing, repair or correction.
-
- In no event unless required by applicable law or agreed to in writing
- will any copyright holder, or any other party who may modify and/or
- redistribute the program as permitted above, be liable to you for
- damages, including any general, special, incidental or consequential
- damages arising out of the use or inability to use the program
- (including but not limited to loss of data or data being rendered
- inaccurate or losses sustained by you or third parties or a failure of
- the program to operate with any other programs), even if such holder or
- other party has been advised of the possibility of such damages.
-******************************************************************************/
-
-#define amazon_readl(a) __raw_readl(((u32*)(a)))
-#define amazon_writel(a,b) __raw_writel(a, ((u32*)(b)))
-#define amazon_writel_masked(a,b,c) __raw_writel((__raw_readl(((u32*)(a))) & ~b) | (c & b), ((u32*)(a)))
-
-unsigned int amazon_get_fpi_hz(void);
-
-#define IOPORT_RESOURCE_START 0x10000000
-#define IOPORT_RESOURCE_END 0xffffffff
-#define IOMEM_RESOURCE_START 0x10000000
-#define IOMEM_RESOURCE_END 0xffffffff
-
-/* check ADSL link status */
-#define AMAZON_CHECK_LINK
-
-/***********************************************************************/
-/* Module : WDT register address and bits */
-/***********************************************************************/
-
-#define AMAZON_WDT (KSEG1+0x10100900)
-/***********************************************************************/
-
-/***Reset Request Register***/
-#define AMAZON_RST_REQ ((volatile u32*)(AMAZON_WDT+ 0x0010))
-#define AMAZON_RST_REQ_PLL (1 << 31)
-#define AMAZON_RST_REQ_PCI_CORE (1 << 13)
-#define AMAZON_RST_REQ_TPE (1 << 12)
-#define AMAZON_RST_REQ_AFE (1 << 11)
-#define AMAZON_RST_REQ_DMA (1 << 9)
-#define AMAZON_RST_REQ_SWITCH (1 << 8)
-#define AMAZON_RST_REQ_DFE (1 << 7)
-#define AMAZON_RST_REQ_PHY (1 << 5)
-#define AMAZON_RST_REQ_PCI (1 << 4)
-#define AMAZON_RST_REQ_FPI (1 << 2)
-#define AMAZON_RST_REQ_CPU (1 << 1)
-#define AMAZON_RST_REQ_HRST (1 << 0)
-#define AMAZON_RST_ALL (AMAZON_RST_REQ_PLL \
- |AMAZON_RST_REQ_PCI_CORE \
- |AMAZON_RST_REQ_TPE \
- |AMAZON_RST_REQ_AFE \
- |AMAZON_RST_REQ_DMA \
- |AMAZON_RST_REQ_SWITCH \
- |AMAZON_RST_REQ_DFE \
- |AMAZON_RST_REQ_PHY \
- |AMAZON_RST_REQ_PCI \
- |AMAZON_RST_REQ_FPI \
- |AMAZON_RST_REQ_CPU \
- |AMAZON_RST_REQ_HRST)
-
-/***Reset Status Register Power On***/
-#define AMAZON_RST_SR ((volatile u32*)(AMAZON_WDT+ 0x0014))
-
-/***Watchdog Timer Control Register 0***/
-#define AMAZON_WDT_CON0 ((volatile u32*)(AMAZON_WDT+ 0x0020))
-
-/***Watchdog Timer Control Register 1***/
-#define AMAZON_WDT_CON1 ((volatile u32*)(AMAZON_WDT+ 0x0024))
-#define AMAZON_WDT_CON1_WDTDR (1 << 3)
-#define AMAZON_WDT_CON1_WDTIR (1 << 2)
-
-/***Watchdog Timer Status Register***/
-#define AMAZON_WDT_SR ((volatile u32*)(AMAZON_WDT+ 0x0028))
-#define AMAZON_WDT_SR_WDTTIM(value) (((( 1 << 16) - 1) & (value)) << 16)
-#define AMAZON_WDT_SR_WDTPR (1 << 5)
-#define AMAZON_WDT_SR_WDTTO (1 << 4)
-#define AMAZON_WDT_SR_WDTDS (1 << 3)
-#define AMAZON_WDT_SR_WDTIS (1 << 2)
-#define AMAZON_WDT_SR_WDTOE (1 << 1)
-#define AMAZON_WDT_SR_WDTAE (1 << 0)
-
-/***NMI Status Register***/
-#define AMAZON_WDT_NMISR ((volatile u32*)(AMAZON_WDT+ 0x002C))
-#define AMAZON_WDT_NMISR_NMIWDT (1 << 2)
-#define AMAZON_WDT_NMISR_NMIPLL (1 << 1)
-#define AMAZON_WDT_NMISR_NMIEXT (1 << 0)
-
-#define AMAZON_WDT_RST_MON ((volatile u32*)(AMAZON_WDT+ 0x0030))
-
-/***********************************************************************/
-/* Module : MCD register address and bits */
-/***********************************************************************/
-#define AMAZON_MCD (KSEG1+0x1F106000)
-
-/***Manufacturer Identification Register***/
-#define AMAZON_MCD_MANID ((volatile u32*)(AMAZON_MCD+ 0x0024))
-#define AMAZON_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5)
-
-/***Chip Identification Register***/
-#define AMAZON_MCD_CHIPID ((volatile u32*)(AMAZON_MCD+ 0x0028))
-#define AMAZON_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
-#define AMAZON_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
-#define AMAZON_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1))
-#define AMAZON_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
-#define AMAZON_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1))
-#define AMAZON_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1)
-
-#define AMAZON_CHIPID_STANDARD 0x00EB
-#define AMAZON_CHIPID_YANGTSE 0x00ED
-
-/***Redesign Tracing Identification Register***/
-#define AMAZON_MCD_RTID ((volatile u32*)(AMAZON_MCD+ 0x002C))
-#define AMAZON_MCD_RTID_LC (1 << 15)
-#define AMAZON_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0)
-
-
-/***********************************************************************/
-/* Module : CGU register address and bits */
-/***********************************************************************/
-
-#define AMAZON_CGU (KSEG1+0x1F103000)
-/***********************************************************************/
-
-/***CGU Clock Divider Select Register***/
-#define AMAZON_CGU_DIV (AMAZON_CGU + 0x0000)
-/***CGU PLL0 Status Register***/
-#define AMAZON_CGU_PLL0SR (AMAZON_CGU + 0x0004)
-/***CGU PLL1 Status Register***/
-#define AMAZON_CGU_PLL1SR (AMAZON_CGU + 0x0008)
-/***CGU Interface Clock Control Register***/
-#define AMAZON_CGU_IFCCR (AMAZON_CGU + 0x000c)
-/***CGU Oscillator Control Register***/
-#define AMAZON_CGU_OSCCR (AMAZON_CGU + 0x0010)
-/***CGU Memory Clock Delay Register***/
-#define AMAZON_CGU_MCDEL (AMAZON_CGU + 0x0014)
-/***CGU CPU Clock Reduction Register***/
-#define AMAZON_CGU_CPUCRD (AMAZON_CGU + 0x0018)
-/***CGU Test Register**/
-#define AMAZON_CGU_TST (AMAZON_CGU + 0x003c)
-
-/***********************************************************************/
-/* Module : PMU register address and bits */
-/***********************************************************************/
-
-#define AMAZON_PMU AMAZON_CGU
-/***********************************************************************/
-
-
-/***PMU Power Down Control Register***/
-#define AMAZON_PMU_PWDCR ((volatile u32*)(AMAZON_PMU+ 0x001c))
-#define AMAZON_PMU_PWDCR_TPE (1 << 13)
-#define AMAZON_PMU_PWDCR_PLL (1 << 12)
-#define AMAZON_PMU_PWDCR_XTAL (1 << 11)
-#define AMAZON_PMU_PWDCR_EBU (1 << 10)
-#define AMAZON_PMU_PWDCR_DFE (1 << 9)
-#define AMAZON_PMU_PWDCR_SPI (1 << 8)
-#define AMAZON_PMU_PWDCR_UART (1 << 7)
-#define AMAZON_PMU_PWDCR_GPT (1 << 6)
-#define AMAZON_PMU_PWDCR_DMA (1 << 5)
-#define AMAZON_PMU_PWDCR_PCI (1 << 4)
-#define AMAZON_PMU_PWDCR_SW (1 << 3)
-#define AMAZON_PMU_PWDCR_IOR (1 << 2)
-#define AMAZON_PMU_PWDCR_FPI (1 << 1)
-#define AMAZON_PMU_PWDCR_EPHY (1 << 0)
-
-/***PMU Status Register***/
-#define AMAZON_PMU_SR ((volatile u32*)(AMAZON_PMU+ 0x0020))
-#define AMAZON_PMU_SR_TPE (1 << 13)
-#define AMAZON_PMU_SR_PLL (1 << 12)
-#define AMAZON_PMU_SR_XTAL (1 << 11)
-#define AMAZON_PMU_SR_EBU (1 << 10)
-#define AMAZON_PMU_SR_DFE (1 << 9)
-#define AMAZON_PMU_SR_SPI (1 << 8)
-#define AMAZON_PMU_SR_UART (1 << 7)
-#define AMAZON_PMU_SR_GPT (1 << 6)
-#define AMAZON_PMU_SR_DMA (1 << 5)
-#define AMAZON_PMU_SR_PCI (1 << 4)
-#define AMAZON_PMU_SR_SW (1 << 3)
-#define AMAZON_PMU_SR_IOR (1 << 2)
-#define AMAZON_PMU_SR_FPI (1 << 1)
-#define AMAZON_PMU_SR_EPHY (1 << 0)
-
-/***********************************************************************/
-/* Module : BCU register address and bits */
-/***********************************************************************/
-
-#define AMAZON_BCU (KSEG1+0x10100000)
-/***********************************************************************/
-
-
-/***BCU Control Register (0010H)***/
-#define AMAZON_BCU_CON ((volatile u32*)(AMAZON_BCU+ 0x0010))
-#define AMAZON_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24)
-#define AMAZON_BCU_CON_SPE (1 << 19)
-#define AMAZON_BCU_CON_PSE (1 << 18)
-#define AMAZON_BCU_CON_DBG (1 << 16)
-#define AMAZON_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***BCU Error Control Capture Register (0020H)***/
-#define AMAZON_BCU_ECON ((volatile u32*)(AMAZON_BCU+ 0x0020))
-#define AMAZON_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24)
-#define AMAZON_BCU_ECON_RDN (1 << 23)
-#define AMAZON_BCU_ECON_WRN (1 << 22)
-#define AMAZON_BCU_ECON_SVM (1 << 21)
-#define AMAZON_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19)
-#define AMAZON_BCU_ECON_ABT (1 << 18)
-#define AMAZON_BCU_ECON_RDY (1 << 17)
-#define AMAZON_BCU_ECON_TOUT (1 << 16)
-#define AMAZON_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0)
-#define AMAZON_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28)
-
-/***BCU Error Address Capture Register (0024 H)***/
-#define AMAZON_BCU_EADD ((volatile u32*)(AMAZON_BCU+ 0x0024))
-#define AMAZON_BCU_EADD_FPIADR
-
-/***BCU Error Data Capture Register (0028H)***/
-#define AMAZON_BCU_EDAT ((volatile u32*)(AMAZON_BCU+ 0x0028))
-#define AMAZON_BCU_EDAT_FPIDAT
-
-/***********************************************************************/
-/* Module : Switch register address and bits */
-/***********************************************************************/
-
-#define AMAZON_SWITCH (KSEG1+0x10106000)
-/***********************************************************************/
-#define AMAZON_SW_UN_DEST AMAZON_SWITCH+0x00 /*Unknown destination register*/
-#define AMAZON_SW_VLAN_CTRL AMAZON_SWITCH+0x04 /*VLAN control register*/
-#define AMAZON_SW_PS_CTL AMAZON_SWITCH+0x08 /*port status control register*/
-#define AMAZON_SW_COS_CTL AMAZON_SWITCH+0x0c /*Cos control register*/
-#define AMAZON_SW_VLAN_COS AMAZON_SWITCH+0x10 /*VLAN priority cos mapping register*/
-#define AMAZON_SW_DSCP_COS3 AMAZON_SWITCH+0x14 /*DSCP cos mapping register3*/
-#define AMAZON_SW_DSCP_COS2 AMAZON_SWITCH+0x18 /*DSCP cos mapping register2*/
-#define AMAZON_SW_DSCP_COS1 AMAZON_SWITCH+0x1c /*DSCP cos mapping register1*/
-#define AMAZON_SW_DSCP_COS0 AMAZON_SWITCH+0x20 /*DSCP cos mapping register*/
-#define AMAZON_SW_ARL_CTL AMAZON_SWITCH+0x24 /*ARL control register*/
-#define AMAZON_SW_PKT_LEN AMAZON_SWITCH+0x28 /*packet length register*/
-#define AMAZON_SW_CPU_ACTL AMAZON_SWITCH+0x2c /*CPU control register1*/
-#define AMAZON_SW_DATA1 AMAZON_SWITCH+0x30 /*CPU access control register1*/
-#define AMAZON_SW_DATA2 AMAZON_SWITCH+0x34 /*CPU access control register2*/
-#define AMAZON_SW_P2_PCTL AMAZON_SWITCH+0x38 /*Port2 control register*/
-#define AMAZON_SW_P0_TX_CTL AMAZON_SWITCH+0x3c /*port0 TX control register*/
-#define AMAZON_SW_P1_TX_CTL AMAZON_SWITCH+0x40 /*port 1 TX control register*/
-#define AMAZON_SW_P0_WM AMAZON_SWITCH+0x44 /*port 0 watermark control register*/
-#define AMAZON_SW_P1_WM AMAZON_SWITCH+0x48 /*port 1 watermark control register*/
-#define AMAZON_SW_P2_WM AMAZON_SWITCH+0x4c /*port 2 watermark control register*/
-#define AMAZON_SW_GBL_WM AMAZON_SWITCH+0x50 /*Global watermark register*/
-#define AMAZON_SW_PM_CTL AMAZON_SWITCH+0x54 /*PM control register*/
-#define AMAZON_SW_P2_CTL AMAZON_SWITCH+0x58 /*PMAC control register*/
-#define AMAZON_SW_P2_TX_IPG AMAZON_SWITCH+0x5c /*port2 TX IPG control register*/
-#define AMAZON_SW_P2_RX_IPG AMAZON_SWITCH+0x60 /*prot2 RX IPG control register*/
-#define AMAZON_SW_MDIO_ACC AMAZON_SWITCH+0x64 /*MDIO access register*/
-#define AMAZON_SW_EPHY AMAZON_SWITCH+0x68 /*Ethernet PHY register*/
-#define AMAZON_SW_MDIO_CFG AMAZON_SWITCH+0x6c /*MDIO configuration register*/
-#define AMAZON_SW_P0_RCV_DROP_CNT AMAZON_SWITCH+0x70 /*port0 receive drop counter */
-#define AMAZON_SW_P0_RCV_FRAME_ERR_CNT AMAZON_SWITCH+0x74 /*port0 receive frame error conter*/
-#define AMAZON_SW_P0_TX_COLL_CNT AMAZON_SWITCH+0x78 /*port0 transmit collision counter*/
-#define AMAZON_SW_P0_TX_DROP_CNT AMAZON_SWITCH+0x7c /*port1 transmit drop counter*/
-#define AMAZON_SW_P1_RCV_DROP_CNT AMAZON_SWITCH+0x80 /*port1 receive drop counter*/
-#define AMAZON_SW_P1_RCV_FRAME_ERR_CNT AMAZON_SWITCH+0x84 /*port1 receive error counter*/
-#define AMAZON_SW_P1_TX_COLL_CNT AMAZON_SWITCH+0x88 /*port1 transmit collision counter*/
-#define AMAZON_SW_P1_TX_DROP_CNT AMAZON_SWITCH+0x8c /*port1 transmit drop counter*/
-
-
-
-/***********************************************************************/
-/* Module : SSC register address and bits */
-/***********************************************************************/
-#define AMAZON_SSC_BASE_ADD_0 (KSEG1+0x10100800)
-
-/*165001:henryhsu:20050603:Source add by Bing Tao*/
-
-/*configuration/Status Registers in Bus Clock Domain*/
-#define AMAZON_SSC_CLC ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0000))
-#define AMAZON_SSC_ID ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0008))
-#define AMAZON_SSC_CON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0010))
-#define AMAZON_SSC_STATE ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0014))
-#define AMAZON_SSC_WHBSTATE ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0018))
-#define AMAZON_SSC_TB ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0020))
-#define AMAZON_SSC_RB ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0024))
-#define AMAZON_SSC_FSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0038))
-
-/*Configuration/Status Registers in Kernel Clock Domain*/
-#define AMAZON_SSC_PISEL ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0004))
-#define AMAZON_SSC_RXFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0030))
-#define AMAZON_SSC_TXFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0034))
-#define AMAZON_SSC_BR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0040))
-#define AMAZON_SSC_BRSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0044))
-#define AMAZON_SSC_SFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0060))
-#define AMAZON_SSC_SFSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0064))
-#define AMAZON_SSC_GPOCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0070))
-#define AMAZON_SSC_GPOSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0074))
-#define AMAZON_SSC_WHBGPOSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0078))
-#define AMAZON_SSC_RXREQ ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0080))
-#define AMAZON_SSC_RXCNT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0084))
-
-/*DMA Registers in Bus Clock Domain*/
-#define AMAZON_SSC_DMA_CON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00ec))
-
-/*interrupt Node Registers in Bus Clock Domain*/
-#define AMAZON_SSC_IRNEN ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00F4))
-#define AMAZON_SSC_IRNICR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00FC))
-#define AMAZON_SSC_IRNCR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00F8))
-
-/*165001*/
-
-/***********************************************************************/
-
-
-
-/***********************************************************************/
-/* Module : EBU register address and bits */
-/***********************************************************************/
-
-#define AMAZON_EBU (KSEG1+0x10105300)
-/***********************************************************************/
-
-
-/***EBU Clock Control Register***/
-#define AMAZON_EBU_CLC ((volatile u32*)(AMAZON_EBU+ 0x0000))
-#define AMAZON_EBU_CLC_DISS (1 << 1)
-#define AMAZON_EBU_CLC_DISR (1 << 0)
-
-/***EBU Global Control Register***/
-#define AMAZON_EBU_CON ((volatile u32*)(AMAZON_EBU+ 0x0010))
-#define AMAZON_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20)
-#define AMAZON_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16)
-#define AMAZON_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8)
-#define AMAZON_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6)
-#define AMAZON_EBU_CON_ARBSYNC (1 << 5)
-#define AMAZON_EBU_CON_1 (1 << 3)
-
-/***EBU Address Select Register 0***/
-#define AMAZON_EBU_ADDSEL0 ((volatile u32*)(AMAZON_EBU+ 0x0020))
-#define AMAZON_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12)
-#define AMAZON_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4)
-#define AMAZON_EBU_ADDSEL0_MIRRORE (1 << 1)
-#define AMAZON_EBU_ADDSEL0_REGEN (1 << 0)
-
-/***EBU Address Select Register 1***/
-#define AMAZON_EBU_ADDSEL1 ((volatile u32*)(AMAZON_EBU+ 0x0024))
-#define AMAZON_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12)
-#define AMAZON_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4)
-#define AMAZON_EBU_ADDSEL1_MIRRORE (1 << 1)
-#define AMAZON_EBU_ADDSEL1_REGEN (1 << 0)
-
-/***EBU Address Select Register 2***/
-#define AMAZON_EBU_ADDSEL2 ((volatile u32*)(AMAZON_EBU+ 0x0028))
-#define AMAZON_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12)
-#define AMAZON_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4)
-#define AMAZON_EBU_ADDSEL2_MIRRORE (1 << 1)
-#define AMAZON_EBU_ADDSEL2_REGEN (1 << 0)
-
-/***EBU Bus Configuration Register 0***/
-#define AMAZON_EBU_BUSCON0 ((volatile u32*)(AMAZON_EBU+ 0x0060))
-#define AMAZON_EBU_BUSCON0_WRDIS (1 << 31)
-#define AMAZON_EBU_BUSCON0_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29)
-#define AMAZON_EBU_BUSCON0_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27)
-#define AMAZON_EBU_BUSCON0_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24)
-#define AMAZON_EBU_BUSCON0_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22)
-#define AMAZON_EBU_BUSCON0_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20)
-#define AMAZON_EBU_BUSCON0_WAITINV (1 << 19)
-#define AMAZON_EBU_BUSCON0_SETUP (1 << 18)
-#define AMAZON_EBU_BUSCON0_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16)
-#define AMAZON_EBU_BUSCON0_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9)
-#define AMAZON_EBU_BUSCON0_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6)
-#define AMAZON_EBU_BUSCON0_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4)
-#define AMAZON_EBU_BUSCON0_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2)
-#define AMAZON_EBU_BUSCON0_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***EBU Bus Configuration Register 1***/
-#define AMAZON_EBU_BUSCON1 ((volatile u32*)(AMAZON_EBU+ 0x0064))
-#define AMAZON_EBU_BUSCON1_WRDIS (1 << 31)
-#define AMAZON_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29)
-#define AMAZON_EBU_BUSCON1_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27)
-#define AMAZON_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24)
-#define AMAZON_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22)
-#define AMAZON_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20)
-#define AMAZON_EBU_BUSCON1_WAITINV (1 << 19)
-#define AMAZON_EBU_BUSCON1_SETUP (1 << 18)
-#define AMAZON_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16)
-#define AMAZON_EBU_BUSCON1_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9)
-#define AMAZON_EBU_BUSCON1_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6)
-#define AMAZON_EBU_BUSCON1_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4)
-#define AMAZON_EBU_BUSCON1_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2)
-#define AMAZON_EBU_BUSCON1_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***EBU Bus Configuration Register 2***/
-#define AMAZON_EBU_BUSCON2 ((volatile u32*)(AMAZON_EBU+ 0x0068))
-#define AMAZON_EBU_BUSCON2_WRDIS (1 << 31)
-#define AMAZON_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29)
-#define AMAZON_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27)
-#define AMAZON_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24)
-#define AMAZON_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22)
-#define AMAZON_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20)
-#define AMAZON_EBU_BUSCON2_WAITINV (1 << 19)
-#define AMAZON_EBU_BUSCON2_SETUP (1 << 18)
-#define AMAZON_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16)
-#define AMAZON_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9)
-#define AMAZON_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6)
-#define AMAZON_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4)
-#define AMAZON_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2)
-#define AMAZON_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : SDRAM register address and bits */
-/***********************************************************************/
-
-#define AMAZON_SDRAM (KSEG1+0x1F800000)
-/***********************************************************************/
-
-
-/***MC Access Error Cause Register***/
-#define AMAZON_SDRAM_MC_ERRCAUSE ((volatile u32*)(AMAZON_SDRAM+ 0x0010))
-#define AMAZON_SDRAM_MC_ERRCAUSE_ERR (1 << 31)
-#define AMAZON_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16)
-#define AMAZON_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0)
-#define AMAZON_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN)
-
-/***MC Access Error Address Register***/
-#define AMAZON_SDRAM_MC_ERRADDR ((volatile u32*)(AMAZON_SDRAM+ 0x0020))
-#define AMAZON_SDRAM_MC_ERRADDR_ADDR
-
-/***MC I/O General Purpose Register***/
-#define AMAZON_SDRAM_MC_IOGP ((volatile u32*)(AMAZON_SDRAM+ 0x0100))
-#define AMAZON_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28)
-#define AMAZON_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24)
-#define AMAZON_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20)
-#define AMAZON_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16)
-#define AMAZON_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12)
-#define AMAZON_SDRAM_MC_IOGP_CPS (1 << 11)
-#define AMAZON_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8)
-#define AMAZON_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4)
-#define AMAZON_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***MC Self Refresh Register***/
-#define AMAZON_SDRAM_MC_SELFRFSH ((volatile u32*)(AMAZON_SDRAM+ 0x01A0))
-#define AMAZON_SDRAM_MC_SELFRFSH_PWDS (1 << 1)
-#define AMAZON_SDRAM_MC_SELFRFSH_PWD (1 << 0)
-#define AMAZON_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2)
-
-/***MC Enable Register***/
-#define AMAZON_SDRAM_MC_CTRLENA ((volatile u32*)(AMAZON_SDRAM+ 0x0110))
-#define AMAZON_SDRAM_MC_CTRLENA_ENA (1 << 0)
-#define AMAZON_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1)
-
-/***MC Mode Register Setup Code***/
-#define AMAZON_SDRAM_MC_MRSCODE ((volatile u32*)(AMAZON_SDRAM+ 0x0120))
-#define AMAZON_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7)
-#define AMAZON_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4)
-#define AMAZON_SDRAM_MC_MRSCODE_WT (1 << 3)
-#define AMAZON_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***MC Configuration Data-word Width Register***/
-#define AMAZON_SDRAM_MC_CFGDW ((volatile u32*)(AMAZON_SDRAM+ 0x0130))
-#define AMAZON_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0)
-#define AMAZON_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4)
-
-/***MC Configuration Physical Bank 0 Register***/
-#define AMAZON_SDRAM_MC_CFGPB0 ((volatile u32*)(AMAZON_SDRAM+ 0x140))
-#define AMAZON_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12)
-#define AMAZON_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8)
-#define AMAZON_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4)
-#define AMAZON_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0)
-#define AMAZON_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16)
-
-/***MC Latency Register***/
-#define AMAZON_SDRAM_MC_LATENCY ((volatile u32*)(AMAZON_SDRAM+ 0x0180))
-#define AMAZON_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16)
-#define AMAZON_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12)
-#define AMAZON_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8)
-#define AMAZON_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4)
-#define AMAZON_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0)
-#define AMAZON_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20)
-
-/***MC Refresh Cycle Time Register***/
-#define AMAZON_SDRAM_MC_TREFRESH ((volatile u32*)(AMAZON_SDRAM+ 0x0190))
-#define AMAZON_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0)
-#define AMAZON_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13)
-
-/***********************************************************************/
-/* Module : GPTU register address and bits */
-/***********************************************************************/
-
-#define AMAZON_GPTU (KSEG1+0x10100A00)
-/***********************************************************************/
-
-
-/***GPT Clock Control Register***/
-#define AMAZON_GPTU_CLC ((volatile u32*)(AMAZON_GPTU+ 0x0000))
-#define AMAZON_GPTU_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8)
-#define AMAZON_GPTU_CLC_DISS (1 << 1)
-#define AMAZON_GPTU_CLC_DISR (1 << 0)
-
-/***GPT Timer 3 Control Register***/
-#define AMAZON_GPTU_T3CON ((volatile u32*)(AMAZON_GPTU+ 0x0014))
-#define AMAZON_GPTU_T3CON_T3RDIR (1 << 15)
-#define AMAZON_GPTU_T3CON_T3CHDIR (1 << 14)
-#define AMAZON_GPTU_T3CON_T3EDGE (1 << 13)
-#define AMAZON_GPTU_T3CON_BPS1(value) (((( 1 << 2) - 1) & (value)) << 11)
-#define AMAZON_GPTU_T3CON_T3OTL (1 << 10)
-#define AMAZON_GPTU_T3CON_T3UD (1 << 7)
-#define AMAZON_GPTU_T3CON_T3R (1 << 6)
-#define AMAZON_GPTU_T3CON_T3M(value) (((( 1 << 3) - 1) & (value)) << 3)
-#define AMAZON_GPTU_T3CON_T3I(value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write Hardware Modified Timer 3 Control Register
-If set and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define AMAZON_GPTU_WHBT3CON ((volatile u32*)(AMAZON_GPTU+ 0x004C))
-#define AMAZON_GPTU_WHBT3CON_SETT3CHDIR (1 << 15)
-#define AMAZON_GPTU_WHBT3CON_CLRT3CHDIR (1 << 14)
-#define AMAZON_GPTU_WHBT3CON_SETT3EDGE (1 << 13)
-#define AMAZON_GPTU_WHBT3CON_CLRT3EDGE (1 << 12)
-#define AMAZON_GPTU_WHBT3CON_SETT3OTL (1 << 11)
-#define AMAZON_GPTU_WHBT3CON_CLRT3OTL (1 << 10)
-
-/***GPT Timer 2 Control Register***/
-#define AMAZON_GPTU_T2CON ((volatile u32*)(AMAZON_GPTU+ 0x0010))
-#define AMAZON_GPTU_T2CON_TxRDIR (1 << 15)
-#define AMAZON_GPTU_T2CON_TxCHDIR (1 << 14)
-#define AMAZON_GPTU_T2CON_TxEDGE (1 << 13)
-#define AMAZON_GPTU_T2CON_TxIRDIS (1 << 12)
-#define AMAZON_GPTU_T2CON_TxRC (1 << 9)
-#define AMAZON_GPTU_T2CON_TxUD (1 << 7)
-#define AMAZON_GPTU_T2CON_TxR (1 << 6)
-#define AMAZON_GPTU_T2CON_TxM(value) (((( 1 << 3) - 1) & (value)) << 3)
-#define AMAZON_GPTU_T2CON_TxI(value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Timer 4 Control Register***/
-#define AMAZON_GPTU_T4CON ((volatile u32*)(AMAZON_GPTU+ 0x0018))
-#define AMAZON_GPTU_T4CON_TxRDIR (1 << 15)
-#define AMAZON_GPTU_T4CON_TxCHDIR (1 << 14)
-#define AMAZON_GPTU_T4CON_TxEDGE (1 << 13)
-#define AMAZON_GPTU_T4CON_TxIRDIS (1 << 12)
-#define AMAZON_GPTU_T4CON_TxRC (1 << 9)
-#define AMAZON_GPTU_T4CON_TxUD (1 << 7)
-#define AMAZON_GPTU_T4CON_TxR (1 << 6)
-#define AMAZON_GPTU_T4CON_TxM(value) (((( 1 << 3) - 1) & (value)) << 3)
-#define AMAZON_GPTU_T4CON_TxI(value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write HW Modified Timer 2 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define AMAZON_GPTU_WHBT2CON ((volatile u32*)(AMAZON_GPTU+ 0x0048))
-#define AMAZON_GPTU_WHBT2CON_SETTxCHDIR (1 << 15)
-#define AMAZON_GPTU_WHBT2CON_CLRTxCHDIR (1 << 14)
-#define AMAZON_GPTU_WHBT2CON_SETTxEDGE (1 << 13)
-#define AMAZON_GPTU_WHBT2CON_CLRTxEDGE (1 << 12)
-
-/***GPT Write HW Modified Timer 4 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define AMAZON_GPTU_WHBT4CON ((volatile u32*)(AMAZON_GPTU+ 0x0050))
-#define AMAZON_GPTU_WHBT4CON_SETTxCHDIR (1 << 15)
-#define AMAZON_GPTU_WHBT4CON_CLRTxCHDIR (1 << 14)
-#define AMAZON_GPTU_WHBT4CON_SETTxEDGE (1 << 13)
-#define AMAZON_GPTU_WHBT4CON_CLRTxEDGE (1 << 12)
-
-/***GPT Capture Reload Register***/
-#define AMAZON_GPTU_CAPREL ((volatile u32*)(AMAZON_GPTU+ 0x0030))
-#define AMAZON_GPTU_CAPREL_CAPREL(value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 2 Register***/
-#define AMAZON_GPTU_T2 ((volatile u32*)(AMAZON_GPTU+ 0x0034))
-#define AMAZON_GPTU_T2_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 3 Register***/
-#define AMAZON_GPTU_T3 ((volatile u32*)(AMAZON_GPTU+ 0x0038))
-#define AMAZON_GPTU_T3_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 4 Register***/
-#define AMAZON_GPTU_T4 ((volatile u32*)(AMAZON_GPTU+ 0x003C))
-#define AMAZON_GPTU_T4_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 5 Register***/
-#define AMAZON_GPTU_T5 ((volatile u32*)(AMAZON_GPTU+ 0x0040))
-#define AMAZON_GPTU_T5_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 6 Register***/
-#define AMAZON_GPTU_T6 ((volatile u32*)(AMAZON_GPTU+ 0x0044))
-#define AMAZON_GPTU_T6_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 6 Control Register***/
-#define AMAZON_GPTU_T6CON ((volatile u32*)(AMAZON_GPTU+ 0x0020))
-#define AMAZON_GPTU_T6CON_T6SR (1 << 15)
-#define AMAZON_GPTU_T6CON_T6CLR (1 << 14)
-#define AMAZON_GPTU_T6CON_BPS2(value) (((( 1 << 2) - 1) & (value)) << 11)
-#define AMAZON_GPTU_T6CON_T6OTL (1 << 10)
-#define AMAZON_GPTU_T6CON_T6UD (1 << 7)
-#define AMAZON_GPTU_T6CON_T6R (1 << 6)
-#define AMAZON_GPTU_T6CON_T6M(value) (((( 1 << 3) - 1) & (value)) << 3)
-#define AMAZON_GPTU_T6CON_T6I(value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write HW Modified Timer 6 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define AMAZON_GPTU_WHBT6CON ((volatile u32*)(AMAZON_GPTU+ 0x0054))
-#define AMAZON_GPTU_WHBT6CON_SETT6OTL (1 << 11)
-#define AMAZON_GPTU_WHBT6CON_CLRT6OTL (1 << 10)
-
-/***GPT Timer 5 Control Register***/
-#define AMAZON_GPTU_T5CON ((volatile u32*)(AMAZON_GPTU+ 0x001C))
-#define AMAZON_GPTU_T5CON_T5SC (1 << 15)
-#define AMAZON_GPTU_T5CON_T5CLR (1 << 14)
-#define AMAZON_GPTU_T5CON_CI(value) (((( 1 << 2) - 1) & (value)) << 12)
-#define AMAZON_GPTU_T5CON_T5CC (1 << 11)
-#define AMAZON_GPTU_T5CON_CT3 (1 << 10)
-#define AMAZON_GPTU_T5CON_T5RC (1 << 9)
-#define AMAZON_GPTU_T5CON_T5UDE (1 << 8)
-#define AMAZON_GPTU_T5CON_T5UD (1 << 7)
-#define AMAZON_GPTU_T5CON_T5R (1 << 6)
-#define AMAZON_GPTU_T5CON_T5M(value) (((( 1 << 3) - 1) & (value)) << 3)
-#define AMAZON_GPTU_T5CON_T5I(value) (((( 1 << 3) - 1) & (value)) << 0)
-
-
-/***********************************************************************/
-/* Module : ASC register address and bits */
-/***********************************************************************/
-
-#define AMAZON_ASC (KSEG1+0x10100400)
-/***********************************************************************/
-
-
-/***ASC Port Input Select Register***/
-#define AMAZON_ASC_PISEL (AMAZON_ASC+ 0x0004)
-#define AMAZON_ASC_PISEL_RIS (1 << 0)
-
-/***ASC Control Register***/
-#define AMAZON_ASC_CON (AMAZON_ASC+ 0x0010)
-#define AMAZON_ASC_CON_R (1 << 15)
-#define AMAZON_ASC_CON_LB (1 << 14)
-#define AMAZON_ASC_CON_BRS (1 << 13)
-#define AMAZON_ASC_CON_ODD (1 << 12)
-#define AMAZON_ASC_CON_FDE (1 << 11)
-#define AMAZON_ASC_CON_OE (1 << 10)
-#define AMAZON_ASC_CON_FE (1 << 9)
-#define AMAZON_ASC_CON_PE (1 << 8)
-#define AMAZON_ASC_CON_OEN (1 << 7)
-#define AMAZON_ASC_CON_FEN (1 << 6)
-#define AMAZON_ASC_CON_PENRXDI (1 << 5)
-#define AMAZON_ASC_CON_REN (1 << 4)
-#define AMAZON_ASC_CON_STP (1 << 3)
-#define AMAZON_ASC_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***ASC Write Hardware Modified Control Register***/
-#define AMAZON_ASC_WHBCON (AMAZON_ASC+ 0x0050)
-#define AMAZON_ASC_WHBCON_SETOE (1 << 13)
-#define AMAZON_ASC_WHBCON_SETFE (1 << 12)
-#define AMAZON_ASC_WHBCON_SETPE (1 << 11)
-#define AMAZON_ASC_WHBCON_CLROE (1 << 10)
-#define AMAZON_ASC_WHBCON_CLRFE (1 << 9)
-#define AMAZON_ASC_WHBCON_CLRPE (1 << 8)
-#define AMAZON_ASC_WHBCON_SETREN (1 << 5)
-#define AMAZON_ASC_WHBCON_CLRREN (1 << 4)
-
-/***ASC Baudrate Timer/Reload Register***/
-#define AMAZON_ASC_BTR (AMAZON_ASC+ 0x0014)
-#define AMAZON_ASC_BTR_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0)
-
-/***ASC Fractional Divider Register***/
-#define AMAZON_ASC_FDV (AMAZON_ASC+ 0x0018)
-#define AMAZON_ASC_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC IrDA Pulse Mode/Width Register***/
-#define AMAZON_ASC_PMW (AMAZON_ASC+ 0x001C)
-#define AMAZON_ASC_PMW_IRPW (1 << 8)
-#define AMAZON_ASC_PMW_PW_VALUE(value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***ASC Transmit Buffer Register***/
-#define AMAZON_ASC_TBUF (AMAZON_ASC+ 0x0020)
-#define AMAZON_ASC_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC Receive Buffer Register***/
-#define AMAZON_ASC_RBUF (AMAZON_ASC+ 0x0024)
-#define AMAZON_ASC_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC Autobaud Control Register***/
-#define AMAZON_ASC_ABCON (AMAZON_ASC+ 0x0030)
-#define AMAZON_ASC_ABCON_RXINV (1 << 11)
-#define AMAZON_ASC_ABCON_TXINV (1 << 10)
-#define AMAZON_ASC_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8)
-#define AMAZON_ASC_ABCON_FCDETEN (1 << 4)
-#define AMAZON_ASC_ABCON_ABDETEN (1 << 3)
-#define AMAZON_ASC_ABCON_ABSTEN (1 << 2)
-#define AMAZON_ASC_ABCON_AUREN (1 << 1)
-#define AMAZON_ASC_ABCON_ABEN (1 << 0)
-
-/***Receive FIFO Control Register***/
-#define AMAZON_ASC_RXFCON (AMAZON_ASC+ 0x0040)
-#define AMAZON_ASC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
-#define AMAZON_ASC_RXFCON_RXTMEN (1 << 2)
-#define AMAZON_ASC_RXFCON_RXFFLU (1 << 1)
-#define AMAZON_ASC_RXFCON_RXFEN (1 << 0)
-
-/***Transmit FIFO Control Register***/
-#define AMAZON_ASC_TXFCON (AMAZON_ASC+ 0x0044)
-#define AMAZON_ASC_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
-#define AMAZON_ASC_TXFCON_TXTMEN (1 << 2)
-#define AMAZON_ASC_TXFCON_TXFFLU (1 << 1)
-#define AMAZON_ASC_TXFCON_TXFEN (1 << 0)
-
-/***FIFO Status Register***/
-#define AMAZON_ASC_FSTAT (AMAZON_ASC+ 0x0048)
-#define AMAZON_ASC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8)
-#define AMAZON_ASC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0)
-
-/***ASC Write HW Modified Autobaud Control Register***/
-#define AMAZON_ASC_WHBABCON (AMAZON_ASC+ 0x0054)
-#define AMAZON_ASC_WHBABCON_SETABEN (1 << 1)
-#define AMAZON_ASC_WHBABCON_CLRABEN (1 << 0)
-
-/***ASC Autobaud Status Register***/
-#define AMAZON_ASC_ABSTAT (AMAZON_ASC+ 0x0034)
-#define AMAZON_ASC_ABSTAT_DETWAIT (1 << 4)
-#define AMAZON_ASC_ABSTAT_SCCDET (1 << 3)
-#define AMAZON_ASC_ABSTAT_SCSDET (1 << 2)
-#define AMAZON_ASC_ABSTAT_FCCDET (1 << 1)
-#define AMAZON_ASC_ABSTAT_FCSDET (1 << 0)
-
-/***ASC Write HW Modified Autobaud Status Register***/
-#define AMAZON_ASC_WHBABSTAT (AMAZON_ASC+ 0x0058)
-#define AMAZON_ASC_WHBABSTAT_SETDETWAIT (1 << 9)
-#define AMAZON_ASC_WHBABSTAT_CLRDETWAIT (1 << 8)
-#define AMAZON_ASC_WHBABSTAT_SETSCCDET (1 << 7)
-#define AMAZON_ASC_WHBABSTAT_CLRSCCDET (1 << 6)
-#define AMAZON_ASC_WHBABSTAT_SETSCSDET (1 << 5)
-#define AMAZON_ASC_WHBABSTAT_CLRSCSDET (1 << 4)
-#define AMAZON_ASC_WHBABSTAT_SETFCCDET (1 << 3)
-#define AMAZON_ASC_WHBABSTAT_CLRFCCDET (1 << 2)
-#define AMAZON_ASC_WHBABSTAT_SETFCSDET (1 << 1)
-#define AMAZON_ASC_WHBABSTAT_CLRFCSDET (1 << 0)
-
-/***ASC Clock Control Register***/
-#define AMAZON_ASC_CLC (AMAZON_ASC+ 0x0000)
-#define AMAZON_ASC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8)
-#define AMAZON_ASC_CLC_DISS (1 << 1)
-#define AMAZON_ASC_CLC_DISR (1 << 0)
-
-/***ASC IRNCR0 **/
-#define AMAZON_ASC_IRNCR0 (AMAZON_ASC+ 0x00FC)
-/***ASC IRNCR1 **/
-#define AMAZON_ASC_IRNCR1 (AMAZON_ASC+ 0x00F8)
-#define ASC_IRNCR_TIR 0x1
-#define ASC_IRNCR_RIR 0x2
-#define ASC_IRNCR_EIR 0x4
-/***********************************************************************/
-/* Module : DMA register address and bits */
-/***********************************************************************/
-
-#define AMAZON_DMA (KSEG1+0x10103000)
-/***********************************************************************/
-#define AMAZON_DMA_CH_ON AMAZON_DMA+0x28
-#define AMAZON_DMA_CH_RST AMAZON_DMA+0x2c
-#define AMAZON_DMA_CH0_ISR AMAZON_DMA+0x30
-#define AMAZON_DMA_CH1_ISR AMAZON_DMA+0x34
-#define AMAZON_DMA_CH2_ISR AMAZON_DMA+0x38
-#define AMAZON_DMA_CH3_ISR AMAZON_DMA+0x3c
-#define AMAZON_DMA_CH4_ISR AMAZON_DMA+0x40
-#define AMAZON_DMA_CH5_ISR AMAZON_DMA+0x44
-#define AMAZON_DMA_CH6_ISR AMAZON_DMA+0x48
-#define AMAZON_DMA_CH7_ISR AMAZON_DMA+0x4c
-#define AMAZON_DMA_CH8_ISR AMAZON_DMA+0x50
-#define AMAZON_DMA_CH9_ISR AMAZON_DMA+0x54
-#define AMAZON_DMA_CH10_ISR AMAZON_DMA+0x58
-#define AMAZON_DMA_CH11_ISR AMAZON_DMA+0x5c
-#define AMAZON_DMA_CH0_MSK AMAZON_DMA+0x60
-#define AMAZON_DMA_CH1_MSK AMAZON_DMA+0x64
-#define AMAZON_DMA_CH2_MSK AMAZON_DMA+0x68
-#define AMAZON_DMA_CH3_MSK AMAZON_DMA+0x6c
-#define AMAZON_DMA_CH4_MSK AMAZON_DMA+0x70
-#define AMAZON_DMA_CH5_MSK AMAZON_DMA+0x74
-#define AMAZON_DMA_CH6_MSK AMAZON_DMA+0x78
-#define AMAZON_DMA_CH7_MSK AMAZON_DMA+0x7c
-#define AMAZON_DMA_CH8_MSK AMAZON_DMA+0x80
-#define AMAZON_DMA_CH9_MSK AMAZON_DMA+0x84
-#define AMAZON_DMA_CH10_MSK AMAZON_DMA+0x88
-#define AMAZON_DMA_CH11_MSK AMAZON_DMA+0x8c
-#define AMAZON_DMA_Desc_BA AMAZON_DMA+0x90
-#define AMAZON_DMA_CH0_DES_LEN AMAZON_DMA+0x94
-#define AMAZON_DMA_CH1_DES_LEN AMAZON_DMA+0x98
-#define AMAZON_DMA_CH2_DES_LEN AMAZON_DMA+0x9c
-#define AMAZON_DMA_CH3_DES_LEN AMAZON_DMA+0xa0
-#define AMAZON_DMA_CH4_DES_LEN AMAZON_DMA+0xa4
-#define AMAZON_DMA_CH5_DES_LEN AMAZON_DMA+0xa8
-#define AMAZON_DMA_CH6_DES_LEN AMAZON_DMA+0xac
-#define AMAZON_DMA_CH7_DES_LEN AMAZON_DMA+0xb0
-#define AMAZON_DMA_CH8_DES_LEN AMAZON_DMA+0xb4
-#define AMAZON_DMA_CH9_DES_LEN AMAZON_DMA+0xb8
-#define AMAZON_DMA_CH10_DES_LEN AMAZON_DMA+0xbc
-#define AMAZON_DMA_CH11_DES_LEN AMAZON_DMA+0xc0
-#define AMAZON_DMA_CH1_DES_OFST AMAZON_DMA+0xc4
-#define AMAZON_DMA_CH2_DES_OFST AMAZON_DMA+0xc8
-#define AMAZON_DMA_CH3_DES_OFST AMAZON_DMA+0xcc
-#define AMAZON_DMA_CH4_DES_OFST AMAZON_DMA+0xd0
-#define AMAZON_DMA_CH5_DES_OFST AMAZON_DMA+0xd4
-#define AMAZON_DMA_CH6_DES_OFST AMAZON_DMA+0xd8
-#define AMAZON_DMA_CH7_DES_OFST AMAZON_DMA+0xdc
-#define AMAZON_DMA_CH8_DES_OFST AMAZON_DMA+0xe0
-#define AMAZON_DMA_CH9_DES_OFST AMAZON_DMA+0xe4
-#define AMAZON_DMA_CH10_DES_OFST AMAZON_DMA+0xe8
-#define AMAZON_DMA_CH11_DES_OFST AMAZON_DMA+0xec
-#define AMAZON_DMA_SW_BL AMAZON_DMA+0xf0
-#define AMAZON_DMA_TPE_BL AMAZON_DMA+0xf4
-#define AMAZON_DMA_DPlus2FPI_BL AMAZON_DMA+0xf8
-#define AMAZON_DMA_GRX_BUF_LEN AMAZON_DMA+0xfc
-#define AMAZON_DMA_DMA_ECON_REG AMAZON_DMA+0x100
-#define AMAZON_DMA_POLLING_REG AMAZON_DMA+0x104
-#define AMAZON_DMA_CH_WGT AMAZON_DMA+0x108
-#define AMAZON_DMA_TX_WGT AMAZON_DMA+0x10c
-#define AMAZON_DMA_DPLus2FPI_CLASS AMAZON_DMA+0x110
-#define AMAZON_DMA_COMB_ISR AMAZON_DMA+0x114
-
-//channel reset
-#define SWITCH1_RST_MASK 0x83 /* Switch1 channel mask */
-#define SWITCH2_RST_MASK 0x10C /* Switch1 channel mask */
-#define TPE_RST_MASK 0x630 /* TPE channel mask */
-#define DPlus2FPI_RST_MASK 0x840 /* DPlusFPI channel mask */
-
-//ISR
-#define DMA_ISR_RDERR 0x20
-#define DMA_ISR_CMDCPT 0x10
-#define DMA_ISR_CPT 0x8
-#define DMA_ISR_DURR 0x4
-#define DMA_ISR_EOP 0x2
-#define DMA_DESC_BYTEOFF_SHIFT 23
-
-#define DMA_POLLING_ENABLE 0x80000000
-#define DMA_POLLING_CNT 0x50 /*minimum 0x10, max 0xfff0*/
-
-/***********************************************************************/
-/* Module : Debug register address and bits */
-/***********************************************************************/
-
-#define AMAZON_DEBUG (KSEG1+0x1F106000)
-/***********************************************************************/
-
-
-/***MCD Break System Control Register***/
-#define AMAZON_DEBUG_MCD_BSCR ((volatile u32*)(AMAZON_DEBUG+ 0x0000))
-
-/***PMC Performance Counter Control Register0***/
-#define AMAZON_DEBUG_PMC_PCCR0 ((volatile u32*)(AMAZON_DEBUG+ 0x0010))
-
-/***PMC Performance Counter Control Register1***/
-#define AMAZON_DEBUG_PMC_PCCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x0014))
-
-/***PMC Performance Counter Register0***/
-#define AMAZON_DEBUG_PMC_PCR0 ((volatile u32*)(AMAZON_DEBUG+ 0x0018))
-
-/*165001:henryhsu:20050603:Source modified by Bing Tao*/
-
-/***PMC Performance Counter Register1***/
-//#define AMAZON_DEBUG_PMC_PCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x0020))
-#define AMAZON_DEBUG_PMC_PCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x001c))
-
-/*165001*/
-
-
-
-/***MCD Suspend Mode Control Register***/
-#define AMAZON_DEBUG_MCD_SMCR ((volatile u32*)(AMAZON_DEBUG+ 0x0024))
-
-/***********************************************************************/
-/* Module : GPIO register address and bits */
-/***********************************************************************/
-
-#define AMAZON_GPIO (KSEG1+0x10100B00)
-/***********************************************************************/
-
-
-/***Port 0 Data Output Register (0010H)***/
-#define AMAZON_GPIO_P0_OUT ((volatile u32*)(AMAZON_GPIO+ 0x0010))
-
-/***Port 1 Data Output Register (0040H)***/
-#define AMAZON_GPIO_P1_OUT ((volatile u32*)(AMAZON_GPIO+ 0x0040))
-
-/***Port 0 Data Input Register (0014H)***/
-#define AMAZON_GPIO_P0_IN ((volatile u32*)(AMAZON_GPIO+ 0x0014))
-
-/***Port 1 Data Input Register (0044H)***/
-#define AMAZON_GPIO_P1_IN ((volatile u32*)(AMAZON_GPIO+ 0x0044))
-
-/***Port 0 Direction Register (0018H)***/
-#define AMAZON_GPIO_P0_DIR ((volatile u32*)(AMAZON_GPIO+ 0x0018))
-
-/***Port 1 Direction Register (0048H)***/
-#define AMAZON_GPIO_P1_DIR ((volatile u32*)(AMAZON_GPIO+ 0x0048))
-
-/***Port 0 Alternate Function Select Register 0 (001C H) ***/
-#define AMAZON_GPIO_P0_ALTSEL0 ((volatile u32*)(AMAZON_GPIO+ 0x001C))
-
-/***Port 1 Alternate Function Select Register 0 (004C H) ***/
-#define AMAZON_GPIO_P1_ALTSEL0 ((volatile u32*)(AMAZON_GPIO+ 0x004C))
-
-/***Port 0 Alternate Function Select Register 1 (0020 H) ***/
-#define AMAZON_GPIO_P0_ALTSEL1 ((volatile u32*)(AMAZON_GPIO+ 0x0020))
-
-/***Port 1 Alternate Function Select Register 0 (0050 H) ***/
-#define AMAZON_GPIO_P1_ALTSEL1 ((volatile u32*)(AMAZON_GPIO+ 0x0050))
-
-/***Port 0 Open Drain Control Register (0024H)***/
-#define AMAZON_GPIO_P0_OD ((volatile u32*)(AMAZON_GPIO+ 0x0024))
-
-/***Port 1 Open Drain Control Register (0054H)***/
-#define AMAZON_GPIO_P1_OD ((volatile u32*)(AMAZON_GPIO+ 0x0054))
-
-/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/
-#define AMAZON_GPIO_P0_STOFF ((volatile u32*)(AMAZON_GPIO+ 0x0028))
-
-/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/
-#define AMAZON_GPIO_P1_STOFF ((volatile u32*)(AMAZON_GPIO+ 0x0058))
-
-/***Port 0 Pull Up/Pull Down Select Register (002C H)***/
-#define AMAZON_GPIO_P0_PUDSEL ((volatile u32*)(AMAZON_GPIO+ 0x002C))
-
-/***Port 1 Pull Up/Pull Down Select Register (005C H)***/
-#define AMAZON_GPIO_P1_PUDSEL ((volatile u32*)(AMAZON_GPIO+ 0x005C))
-
-/***Port 0 Pull Up Device Enable Register (0030 H)***/
-#define AMAZON_GPIO_P0_PUDEN ((volatile u32*)(AMAZON_GPIO+ 0x0030))
-
-/***Port 1 Pull Up Device Enable Register (0060 H)***/
-#define AMAZON_GPIO_P1_PUDEN ((volatile u32*)(AMAZON_GPIO+ 0x0060))
-
-/***********************************************************************/
-/* Module : BIU register address and bits */
-/***********************************************************************/
-
-#define AMAZON_BIU (KSEG1+0x1FA80000)
-/***********************************************************************/
-
-
-/***BIU Identification Register***/
-#define AMAZON_BIU_ID ((volatile u32*)(AMAZON_BIU+ 0x0000))
-#define AMAZON_BIU_ID_ARCH (1 << 16)
-#define AMAZON_BIU_ID_ID(value) (((( 1 << 8) - 1) & (value)) << 8)
-#define AMAZON_BIU_ID_REV(value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***BIU Access Error Cause Register***/
-#define AMAZON_BIU_ERRCAUSE ((volatile u32*)(AMAZON_BIU+ 0x0100))
-#define AMAZON_BIU_ERRCAUSE_ERR (1 << 31)
-#define AMAZON_BIU_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16)
-#define AMAZON_BIU_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***BIU Access Error Address Register***/
-#define AMAZON_BIU_ERRADDR ((volatile u32*)(AMAZON_BIU+ 0x0108))
-#define AMAZON_BIU_ERRADDR_ADDR
-
-/***********************************************************************/
-/* Module : ICU register address and bits */
-/***********************************************************************/
-
-#define AMAZON_ICU (KSEG1+0x1F101000)
-/***********************************************************************/
-
-/***IM0 Interrupt Status Register***/
-#define AMAZON_ICU_IM0_ISR (AMAZON_ICU + 0x0010)
-#define AMAZON_ICU_IM1_ISR (AMAZON_ICU + 0x0020)
-#define AMAZON_ICU_IM2_ISR (AMAZON_ICU + 0x0030)
-#define AMAZON_ICU_IM3_ISR (AMAZON_ICU + 0x0040)
-#define AMAZON_ICU_IM4_ISR (AMAZON_ICU + 0x0050)
-
-/***IM0 Interrupt Enable Register***/
-#define AMAZON_ICU_IM0_IER (AMAZON_ICU + 0x0014)
-#define AMAZON_ICU_IM1_IER (AMAZON_ICU + 0x0024)
-#define AMAZON_ICU_IM2_IER (AMAZON_ICU + 0x0034)
-#define AMAZON_ICU_IM3_IER (AMAZON_ICU + 0x0044)
-#define AMAZON_ICU_IM4_IER (AMAZON_ICU + 0x0054)
-
-/***IM0 Interrupt Output Status Register***/
-#define AMAZON_ICU_IM0_IOSR (AMAZON_ICU + 0x0018)
-#define AMAZON_ICU_IM1_IOSR (AMAZON_ICU + 0x0028)
-#define AMAZON_ICU_IM2_IOSR (AMAZON_ICU + 0x0038)
-#define AMAZON_ICU_IM3_IOSR (AMAZON_ICU + 0x0048)
-#define AMAZON_ICU_IM4_IOSR (AMAZON_ICU + 0x0058)
-
-/***IM0 Interrupt Request Set Register***/
-#define AMAZON_ICU_IM0_IRSR (AMAZON_ICU + 0x001c)
-#define AMAZON_ICU_IM1_IRSR (AMAZON_ICU + 0x002c)
-#define AMAZON_ICU_IM2_IRSR (AMAZON_ICU + 0x003c)
-#define AMAZON_ICU_IM3_IRSR (AMAZON_ICU + 0x004c)
-#define AMAZON_ICU_IM4_IRSR (AMAZON_ICU + 0x005c)
-
-/***Interrupt Vector Value Register***/
-#define AMAZON_ICU_IM_VEC (AMAZON_ICU + 0x0060)
-
-/***Interrupt Vector Value Mask***/
-#define AMAZON_ICU_IM0_VEC_MASK 0x0000001f
-#define AMAZON_ICU_IM1_VEC_MASK 0x000003e0
-#define AMAZON_ICU_IM2_VEC_MASK 0x00007c00
-#define AMAZON_ICU_IM3_VEC_MASK 0x000f8000
-#define AMAZON_ICU_IM4_VEC_MASK 0x01f00000
-
-/***DMA Interrupt Mask Value***/
-#define AMAZON_DMA_H_MASK 0x00000fff
-
-/***External Interrupt Control Register***/
-#define AMAZON_ICU_EXTINTCR ((volatile u32*)(AMAZON_ICU + 0x0000))
-#define AMAZON_ICU_IRNICR ((volatile u32*)(AMAZON_ICU + 0x0004))
-#define AMAZON_ICU_IRNCR ((volatile u32*)(AMAZON_ICU + 0x0008))
-#define AMAZON_ICU_IRNEN ((volatile u32*)(AMAZON_ICU + 0x000c))
-
-/***********************************************************************/
-/* Module : PCI/Card-BUS/PC-Card register address and bits */
-/***********************************************************************/
-
-#define AMAZON_PCI (KSEG1+0x10105400)
-#define AMAZON_PCI_CFG_BASE (KSEG1+0x11000000)
-#define AMAZON_PCI_MEM_BASE (KSEG1+0x12000000)
-
-#define CLOCK_CONTROL AMAZON_PCI + 0x00000000
-#define ARB_CTRL_bit 1
-#define IDENTIFICATION AMAZON_PCI + 0x00000004
-#define SOFTRESET AMAZON_PCI + 0x00000010
-#define PCI_FPI_ERROR_ADDRESS AMAZON_PCI + 0x00000014
-#define FPI_PCI_ERROR_ADDRESS AMAZON_PCI + 0x00000018
-#define FPI_ERROR_TAG AMAZON_PCI + 0x0000001c
-#define IRR AMAZON_PCI + 0x00000020
-#define IRA_IR AMAZON_PCI + 0x00000024
-#define IRM AMAZON_PCI + 0x00000028
-#define DMA_COMPLETE_BIT 0
-#define PCI_POWER_CHANGE_BIT 16
-#define PCI_MASTER0_BROKEN_INT_BIT 24
-#define PCI_MASTER1_BROKEN_INT_BIT 25
-#define PCI_MASTER2_BROKEN_INT_BIT 26
-#define EOI AMAZON_PCI + 0x0000002c
-#define PCI_MODE AMAZON_PCI + 0x00000030
-#define PCI_MODE_cfgok_bit 24
-#define DEVICE_VENDOR_ID AMAZON_PCI + 0x00000034
-#define SUBSYSTEM_VENDOR_ID AMAZON_PCI + 0x00000038
-#define POWER_MANAGEMENT AMAZON_PCI + 0x0000003c
-#define CLASS_CODE1 AMAZON_PCI + 0x00000040
-#define BAR11_MASK AMAZON_PCI + 0x00000044
-#define BAR12_MASK AMAZON_PCI + 0x00000048
-#define BAR13_MASK AMAZON_PCI + 0x0000004c
-#define BAR14_MASK AMAZON_PCI + 0x00000050
-#define BAR15_MASK AMAZON_PCI + 0x00000054
-#define BAR16_MASK AMAZON_PCI + 0x00000058
-#define CARDBUS_CIS_POINTER1 AMAZON_PCI + 0x0000005c
-#define SUBSYSTEM_ID1 AMAZON_PCI + 0x00000060
-#define PCI_ADDRESS_MAP_11 AMAZON_PCI + 0x00000064
-#define PCI_ADDRESS_MAP_12 AMAZON_PCI + 0x00000068
-#define PCI_ADDRESS_MAP_13 AMAZON_PCI + 0x0000006c
-#define PCI_ADDRESS_MAP_14 AMAZON_PCI + 0x00000070
-#define PCI_ADDRESS_MAP_15 AMAZON_PCI + 0x00000074
-#define PCI_ADDRESS_MAP_16 AMAZON_PCI + 0x00000078
-#define FPI_SEGMENT_ENABLE AMAZON_PCI + 0x0000007c
-#define CLASS_CODE2 AMAZON_PCI + 0x00000080
-#define BAR21_MASK AMAZON_PCI + 0x00000084
-#define BAR22_MASK AMAZON_PCI + 0x00000088
-#define BAR23_MASK AMAZON_PCI + 0x0000008c
-#define BAR24_MASK AMAZON_PCI + 0x00000090
-#define BAR25_MASK AMAZON_PCI + 0x00000094
-#define BAR26_MASK AMAZON_PCI + 0x00000098
-#define CARDBUS_CIS_POINTER2 AMAZON_PCI + 0x0000009c
-#define SUBSYSTEM_ID2 AMAZON_PCI + 0x000000a0
-#define PCI_ADDRESS_MAP_21 AMAZON_PCI + 0x000000a4
-#define PCI_ADDRESS_MAP_22 AMAZON_PCI + 0x000000a8
-#define PCI_ADDRESS_MAP_23 AMAZON_PCI + 0x000000ac
-#define PCI_ADDRESS_MAP_24 AMAZON_PCI + 0x000000b0
-#define PCI_ADDRESS_MAP_25 AMAZON_PCI + 0x000000b4
-#define PCI_ADDRESS_MAP_26 AMAZON_PCI + 0x000000b8
-#define FPI_ADDRESS_MASK11LOW AMAZON_PCI + 0x000000bc
-#define FPI_ADDRESS_MAP_0 AMAZON_PCI + 0x000000c0
-#define FPI_ADDRESS_MAP_1 AMAZON_PCI + 0x000000c4
-#define FPI_ADDRESS_MAP_2 AMAZON_PCI + 0x000000c8
-#define FPI_ADDRESS_MAP_3 AMAZON_PCI + 0x000000cc
-#define FPI_ADDRESS_MAP_4 AMAZON_PCI + 0x000000d0
-#define FPI_ADDRESS_MAP_5 AMAZON_PCI + 0x000000d4
-#define FPI_ADDRESS_MAP_6 AMAZON_PCI + 0x000000d8
-#define FPI_ADDRESS_MAP_7 AMAZON_PCI + 0x000000dc
-#define FPI_ADDRESS_MAP_11LOW AMAZON_PCI + 0x000000e0
-#define FPI_ADDRESS_MAP_11HIGH AMAZON_PCI + 0x000000e4
-#define FPI_BURST_LENGTH AMAZON_PCI + 0x000000e8
-#define SET_PCI_SERR AMAZON_PCI + 0x000000ec
-#define DMA_FPI_START_ADDR AMAZON_PCI + 0x000000f0
-#define DMA_PCI_START_ADDR AMAZON_PCI + 0x000000f4
-#define DMA_TRANSFER_COUNT AMAZON_PCI + 0x000000f8
-#define DMA_CONTROL_STATUS AMAZON_PCI + 0x000000fc
-
-#define EXT_PCI1_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x0800
-#define EXT_PCI2_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x1000
-#define EXT_PCI3_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x1800
-#define EXT_PCI4_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x2000
-#define EXT_PCI5_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x2800
-#define EXT_PCI6_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x3000
-#define EXT_PCI7_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x3800
-#define EXT_PCI8_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x4000
-#define EXT_PCI9_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x4800
-#define EXT_PCI10_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x5000
-#define EXT_PCI11_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x5800
-#define EXT_PCI12_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x6000
-#define EXT_PCI13_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x6800
-#define EXT_PCI14_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x7000
-#define EXT_PCI15_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x7800
-#define EXT_CARDBUS_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0XF000
-#define EXT_PCI_BAR1_ADDR 0x10
-#define EXT_PCI_BAR2_ADDR 0x14
-#define EXT_PCI_BAR3_ADDR 0x18
-#define EXT_PCI_BAR4_ADDR 0x1C
-#define EXT_PCI_BAR5_ADDR 0x20
-#define EXT_PCI_BAR6_ADDR 0x24
-
-#define DEVICE_ID_VECDOR_ID_ADDR AMAZON_PCI_CFG_BASE + 0x0
-#define STATUS_COMMAND_ADDR AMAZON_PCI_CFG_BASE + 0x4
-#define BUS_MASTER_ENABLE_BIT 2
-#define MEM_SPACE_ENABLE_BIT 1
-#define CLASS_CODE_REVISION_ADDR AMAZON_PCI_CFG_BASE + 0x8
-#define BIST_HEADER_TYPE_LATENCY_CAHCE_ADDR AMAZON_PCI_CFG_BASE + 0xC
-#define BAR1_ADDR AMAZON_PCI_CFG_BASE + 0x10
-#define BAR2_ADDR AMAZON_PCI_CFG_BASE + 0x14
-#define BAR3_ADDR AMAZON_PCI_CFG_BASE + 0x18
-#define BAR4_ADDR AMAZON_PCI_CFG_BASE + 0x1C
-#define BAR3_ADDR AMAZON_PCI_CFG_BASE + 0x18
-#define BAR4_ADDR AMAZON_PCI_CFG_BASE + 0x1C
-#define BAR5_ADDR AMAZON_PCI_CFG_BASE + 0x20
-#define BAR6_ADDR AMAZON_PCI_CFG_BASE + 0x24
-#define CARDBUS_CIS_POINTER_ADDR AMAZON_PCI_CFG_BASE + 0x28
-#define SUBSYSTEM_ID_VENDOR_ID_ADDR AMAZON_PCI_CFG_BASE + 0x2C
-#define EXPANSION_ROM_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x30
-#define CAPABILITIES_POINTER_ADDR AMAZON_PCI_CFG_BASE + 0x34
-#define RESERVED_0x38 AMAZON_PCI_CFG_BASE + 0x38
-#define MAX_LAT_MIN_GNT_INT_PIN_LINE_ADDR AMAZON_PCI_CFG_BASE + 0x3C
-#define POWER_MNGT_NEXT_POINTER_CAP_ID_ADDR AMAZON_PCI_CFG_BASE + 0x40
-#define POWER_MANAGEMENT_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x44
-#define RESERVED_0x48 AMAZON_PCI_CFG_BASE + 0x48
-#define RESERVED_0x4C AMAZON_PCI_CFG_BASE + 0x4C
-#define ERROR_ADDR_PCI_FPI_ADDR AMAZON_PCI_CFG_BASE + 0x50
-#define ERROR_ADdR_FPI_PCI_ADDR AMAZON_PCI_CFG_BASE + 0x54
-#define ERROR_TAG_FPI_PCI_ADDR AMAZON_PCI_CFG_BASE + 0x58
-#define PCI_ARB_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x5C
-#define INTERNAL_ARB_ENABLE_BIT 0
-#define ARB_SCHEME_BIT 1
-#define PCI_MASTER0_PRIOR_2BITS 2
-#define PCI_MASTER1_PRIOR_2BITS 4
-#define PCI_MASTER2_PRIOR_2BITS 6
-#define PCI_MASTER0_REQ_MASK_2BITS 8
-#define PCI_MASTER1_REQ_MASK_2BITS 10
-#define PCI_MASTER2_REQ_MASK_2BITS 12
-#define PCI_MASTER0_GNT_MASK_2BITS 14
-#define PCI_MASTER1_GNT_MASK_2BITS 16
-#define PCI_MASTER2_GNT_MASK_2BITS 18
-#define FPI_PCI_INT_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x60
-#define FPI_PCI_INT_ACK_ADDR AMAZON_PCI_CFG_BASE + 0x64
-#define FPI_PCI_INT_MASK_ADDR AMAZON_PCI_CFG_BASE + 0x68
-#define CARDBUS_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x6C
-#define CARDBUS_CFRAME_ENABLE 0
-
-#define CLOCK_CONTROL_default 0x00000000
-#define CLOCK_CONTROL_mask 0x00000003
-
-#define IDENTIFICATION_default 0x0011C002
-#define IDENTIFICATION_mask 0x00000000
-
-#define SOFTRESET_default 0x00000000
-// SOFTRESET bit 0 is writable but will be reset to 0 after software reset is over
-#define SOFTRESET_mask 0x00000000
-
-#define PCI_FPI_ERROR_ADDRESS_default 0xFFFFFFFF
-#define PCI_FPI_ERROR_ADDRESS_mask 0x00000000
-
-#define FPI_PCI_ERROR_ADDRESS_default 0xFFFFFFFF
-#define FPI_PCI_ERROR_ADDRESS_mask 0x00000000
-
-#define FPI_ERROR_TAG_default 0x0000000F
-#define FPI_ERROR_TAG_mask 0x00000000
-
-#define IRR_default 0x00000000
-#define IRR_mask 0x07013b2F
-
-#define IRA_IR_default 0x00000000
-#define IRA_IR_mask 0x07013b2F
-
-#define IRM_default 0x00000000
-#define IRM_mask 0xFFFFFFFF
-
-#define EOI_default 0x00000000
-#define EOI_mask 0x00000000
-
-#define PCI_MODE_default 0x01000103
-#define PCI_MODE_mask 0x1107070F
-
-#define DEVICE_VENDOR_ID_default 0x000C15D1
-#define DEVICE_VENDOR_ID_mask 0xFFFFFFFF
-
-#define SUBSYSTEM_VENDOR_ID_default 0x000015D1
-#define SUBSYSTEM_VENDOR_ID_mask 0x0000FFFF
-
-#define POWER_MANAGEMENT_default 0x0000001B
-#define POWER_MANAGEMENT_mask 0x0000001F
-
-#define CLASS_CODE1_default 0x00028000
-#define CLASS_CODE1_mask 0x00FFFFFF
-
-#define BAR11_MASK_default 0x0FF00008
-#define BAR11_MASK_mask 0x8FF00008
-
-#define BAR12_MASK_default 0x80001800
-#define BAR12_MASK_mask 0x80001F08
-
-#define BAR13_MASK_default 0x8FF00008
-#define BAR13_MASK_mask 0x8FF00008
-
-#define BAR14_MASK_default 0x8F000000
-#define BAR14_MASK_mask 0x8FFFFF08
-
-#define BAR15_MASK_default 0x80000000
-#define BAR15_MASK_mask 0x8FFFFF08
-
-#define BAR16_MASK_default 0x80000001
-// bit 0 and bit 3 is mutually exclusive
-#define BAR16_MASK_mask 0x8FFFFFF9
-
-#define CARDBUS_CIS_POINTER1_default 0x00000000
-#define CARDBUS_CIS_POINTER1_mask 0x03FFFFFF
-
-#define SUBSYSTEM_ID1_default 0x0000000C
-#define SUBSYSTEM_ID1_mask 0x0000FFFF
-
-#define PCI_ADDRESS_MAP_11_default 0x18000000
-#define PCI_ADDRESS_MAP_11_mask 0x7FFFFFF1
-
-#define PCI_ADDRESS_MAP_12_default 0x18100000
-#define PCI_ADDRESS_MAP_12_mask 0x7FFFFF01
-
-#define PCI_ADDRESS_MAP_13_default 0x18200000
-#define PCI_ADDRESS_MAP_13_mask 0x7FF00001
-
-#define PCI_ADDRESS_MAP_14_default 0x70000000
-#define PCI_ADDRESS_MAP_14_mask 0x7FFFFF01
-
-#define PCI_ADDRESS_MAP_15_default 0x00000001
-#define PCI_ADDRESS_MAP_15_mask 0x7FFFFF01
-
-#define PCI_ADDRESS_MAP_16_default 0x60000000
-#define PCI_ADDRESS_MAP_16_mask 0x7FF00001
-
-#define FPI_SEGMENT_ENABLE_default 0x000003FF
-#define FPI_SEGMENT_ENABLE_mask 0x000003FF
-
-#define CLASS_CODE2_default 0x00FF0000
-#define CLASS_CODE2_mask 0x00FFFFFF
-
-#define BAR21_MASK_default 0x80000008
-#define BAR21_MASK_mask 0x8FFFFFF8
-
-#define BAR22_MASK_default 0x80000008
-#define BAR22_MASK_mask 0x80001F08
-
-#define BAR23_MASK_default 0x80000008
-#define BAR23_MASK_mask 0x8FF00008
-
-#define BAR24_MASK_default 0x8FE00000
-#define BAR24_MASK_mask 0x8FFFFF08
-
-#define BAR25_MASK_default 0x8FFFF000
-#define BAR25_MASK_mask 0x8FFFFF08
-
-#define BAR26_MASK_default 0x8FFFFFE1
-#define BAR26_MASK_mask 0x8FFFFFF1
-
-#define CARDBUS_CIS_POINTER2_default 0x00000000
-#define CARDBUS_CIS_POINTER2_mask 0x03FFFFFF
-
-#define SUBSYSTEM_ID2_default 0x0000000C
-#define SUBSYSTEM_ID2_mask 0x0000FFFF
-
-#define PCI_ADDRESS_MAP_21_default 0x3FE00000
-#define PCI_ADDRESS_MAP_21_mask 0x7FFFFFF1
-
-#define PCI_ADDRESS_MAP_22_default 0x68000000
-#define PCI_ADDRESS_MAP_22_mask 0x7FFFFF01
-
-#define PCI_ADDRESS_MAP_23_default 0x20000000
-#define PCI_ADDRESS_MAP_23_mask 0x7FF00001
-
-#define PCI_ADDRESS_MAP_24_default 0x70000001
-#define PCI_ADDRESS_MAP_24_mask 0x7FFFFF01
-
-#define PCI_ADDRESS_MAP_25_default 0x78000001
-#define PCI_ADDRESS_MAP_25_mask 0x7FFFFF01
-
-#define PCI_ADDRESS_MAP_26_default 0x20000000
-#define PCI_ADDRESS_MAP_26_mask 0x7FF00001
-
-#define FPI_ADDRESS_MASK11LOW_default 0x00000000
-#define FPI_ADDRESS_MASK11LOW_mask 0x00070000
-
-#define FPI_ADDRESS_MAP_0_default 0x00000000
-#define FPI_ADDRESS_MAP_0_mask 0xFFF00000
-
-#define FPI_ADDRESS_MAP_1_default 0x10000000
-#define FPI_ADDRESS_MAP_1_mask 0xFFF00000
-
-#define FPI_ADDRESS_MAP_2_default 0x20000000
-#define FPI_ADDRESS_MAP_2_mask 0xFFF00000
-
-#define FPI_ADDRESS_MAP_3_default 0x30000000
-#define FPI_ADDRESS_MAP_3_mask 0xFFF00000
-
-#define FPI_ADDRESS_MAP_4_default 0x40000000
-#define FPI_ADDRESS_MAP_4_mask 0xFFF00000
-
-#define FPI_ADDRESS_MAP_5_default 0x50000000
-#define FPI_ADDRESS_MAP_5_mask 0xFFF00000
-
-#define FPI_ADDRESS_MAP_6_default 0x60000000
-#define FPI_ADDRESS_MAP_6_mask 0xFFF00000
-
-#define FPI_ADDRESS_MAP_7_default 0x70000000
-#define FPI_ADDRESS_MAP_7_mask 0xFFF00000
-
-#define FPI_ADDRESS_MAP_11LOW_default 0xB0000000
-#define FPI_ADDRESS_MAP_11LOW_mask 0xFFFF0000
-
-#define FPI_ADDRESS_MAP_11HIGH_default 0xB8000000
-#define FPI_ADDRESS_MAP_11HIGH_mask 0xFFF80000
-
-#define FPI_BURST_LENGTH_default 0x00000000
-#define FPI_BURST_LENGTH_mask 0x00000303
-
-#define SET_PCI_SERR_default 0x00000000
-#define SET_PCI_SERR_mask 0x00000000
-
-#define DMA_FPI_START_ADDRESS_default 0x00000000
-#define DMA_FPI_START_ADDRESS_mask 0xFFFFFFFF
-
-#define DMA_PCI_START_ADDRESS_default 0x00000000
-#define DMA_PCI_START_ADDRESS_mask 0xFFFFFFFF
-
-#define DMA_TRANSFER_COUNT_default 0x00000000
-#define DMA_TRANSFER_COUNT_mask 0x0000FFFF
-
-#define DMA_CONTROL_STATUS_default 0x00000000
-#define DMA_CONTROL_STATUS_mask 0x00000000 // bit 0,1 is writable
-
-/***********************************************************************/
-#undef IKOS_MINI_BOOT //don't run a full booting
-#ifdef CONFIG_USE_IKOS
-#define CONFIG_USE_VENUS //Faster, 10M CPU and 192k baudrate
-#ifdef CONFIG_USE_VENUS
-#define IKOS_CPU_SPEED 10000000
-#else
-#define IKOS_CPU_SPEED 180000 //IKOS is slow
-#endif
-#endif //CONFIG_USE_IKOS
-
-/* 165001:henryhsu:20050603:Source Modify form Bing Tao */
-
-#if defined(CONFIG_NET_WIRELESS_SPURS) || defined(CONFIG_NET_WIRELESS_SPURS_MODULE)
-#define EBU_PCI_SOFTWARE_ARBITOR
-#endif
-
-#define AMAZON_B11
-#ifdef AMAZON_B11
-#define SWITCH_BUF_FPI_ADDR (0x10110000)
-#define SWITCH_BUF_ADDR (KSEG1+SWITCH_BUF_FPI_ADDR)
-#define SWITCH_BUF_SIZE (0x2800)
-#define AMAZON_B11_CBM_QD_ADDR (SWITCH_BUF_ADDR+0x0)
-#define AMAZON_B11_BOND_CELL_ADDR (SWITCH_BUF_ADDR+0x000)
-#endif
-#define AMAZON_REFERENCE_BOARD
-//for AMAZON ATM bonding application
-#ifdef AMAZON_REFERENCE_BOARD
-#define GPIO_DETECT_LOW
-#else
-#undef GPIO_DETECT_LOW
-#endif
-
-/* 165001 */
-
-#undef AMAZON_IKOS_DEBUG_MSG
-#undef AMAZON_INT_DEBUG_MSG
-#undef AMAZON_ATM_DEBUG_MSG
-#undef AMAZON_DMA_DEBUG_MSG
-#undef AMAZON_SW_DEBUG_MSG
-#undef AMAZON_WDT_DEBUG_MSG
-#undef AMAZON_MTD_DEBUG_MSG
-#undef AMAZON_SSC_DEBUG_MSG
-#undef AMAZON_MEI_DEBUG_MSG
-
-#ifdef AMAZON_IKOS_DEBUG_MSG
-#define AMAZON_IKOS_DMSG(fmt,args...) printk("%s:" fmt, __FUNCTION__, ##args)
-#else
-#define AMAZON_IKOS_DMSG(fmt,args...)
-#endif
-
-#ifdef AMAZON_WDT_DEBUG_MSG
-#define AMAZON_WDT_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args)
-#else
-#define AMAZON_WDT_DMSG(fm,args...)
-#endif
-
-#ifdef AMAZON_SSC_DEBUG_MSG
-#define AMAZON_SSC_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args)
-#else
-#define AMAZON_SSC_DMSG(fm,args...)
-#endif
-
-#ifdef AMAZON_DMA_DEBUG_MSG
-#define AMAZON_DMA_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args)
-#else
-#define AMAZON_DMA_DMSG(fm,args...)
-#endif
-
-#ifdef AMAZON_ATM_DEBUG_MSG
-#define AMAZON_TPE_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args)
-#else //not AMAZON_ATM_DEBUG
-#define AMAZON_TPE_DMSG(fmt, args...)
-#endif //AMAZON_ATM_DEBUG
-
-#ifdef AMAZON_SW_DEBUG_MSG
-#define AMAZON_SW_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args)
-#else
-#define AMAZON_SW_DMSG(fmt,args...)
-#endif
-
-#ifdef AMAZON_MTD_DEBUG_MSG
-#define AMAZON_MTD_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args)
-#else
-#define AMAZON_MTD_DMSG(fmt,args...)
-#endif
-
-#ifdef AMAZON_INT_DEBUG_MSG
-#define AMAZON_INT_DMSG(x...) printk(x)
-#else
-#define AMAZON_INT_DMSG(x...)
-#endif
-
-#ifdef AMAZON_MEI_DEBUG_MSG
-#define AMAZON_MEI_DMSG(fmt,args...) printk("%s:" fmt, __FUNCTION__, ##args)
-#else
-#define AMAZON_MEI_DMSG(fmt,args...)
-#endif
-
-#endif //AMAZON_H
+++ /dev/null
-#ifndef AMAZON_DMA_H
-#define AMAZON_DMA_H
-
-#define RCV_INT 1
-#define TX_BUF_FULL_INT 2
-#define TRANSMIT_CPT_INT 4
-
-#define QOS_DEFAULT_WGT 0x7fffffffUL;
-
-
-enum attr_t{
- TX=0,
- RX=1,
- RESERVED=2,
- DEFAULT=3,
-
-};
-
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-typedef struct rx_desc{
- u32 data_length:16;
- volatile u32 reserved:7;
- volatile u32 byte_offset:2;
- volatile u32 Burst_length_offset:3;
- volatile u32 EoP:1;
- volatile u32 Res:1;
- volatile u32 C:1;
- volatile u32 OWN:1;
- volatile u32 Data_Pointer;
- /*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/
-}_rx_desc;
-
-
-typedef struct tx_desc{
- volatile u32 data_length:16;
- volatile u32 reserved1:7;
- volatile u32 byte_offset:5;
- volatile u32 EoP:1;
- volatile u32 SoP:1;
- volatile u32 C:1;
- volatile u32 OWN:1;
- volatile u32 Data_Pointer;//fix me:should be 28 bits here
-}_tx_desc;
-#else //BIG
-typedef struct rx_desc{
- union
- {
- struct
- {
- volatile u32 OWN :1;
- volatile u32 C :1;
- volatile u32 SoP :1;
- volatile u32 EoP :1;
- volatile u32 Burst_length_offset :3;
- volatile u32 byte_offset :2;
- volatile u32 reserve :7;
- volatile u32 data_length :16;
- }field;
-
- volatile u32 word;
- }status;
-
- volatile u32 Data_Pointer;
-}_rx_desc;
-
-
-typedef struct tx_desc{
- union
- {
- struct
- {
- volatile u32 OWN :1;
- volatile u32 C :1;
- volatile u32 SoP :1;
- volatile u32 EoP :1;
- volatile u32 byte_offset :5;
- volatile u32 reserved :7;
- volatile u32 data_length :16;
- }field;
-
- volatile u32 word;
- }status;
-
- volatile u32 Data_Pointer;
-}_tx_desc;
-
-#endif //ENDIAN
-
-struct dma_channel_info{
- /*filled by driver, optional*/
- enum attr_t attr;/*TX or RX*/
- int weight;
- int desc_num;
- int packet_size;
- int control;/*on or off*/
-
- int desc_base;
- int status;
-};
-
-typedef struct dma_channel_info _dma_channel_info;
-
-struct dma_device_info{
- /*variables*/
- /*filled by driver, compulsary*/
- char device_name[15];
- enum attr_t attr;/*default or else*/
- int tx_burst_len;
- int rx_burst_len;
-
- int logic_rx_chan_base;
- int logic_tx_chan_base;
- u8 on_ch_bit;
- /*filled by driver, optional*/
- int weight;
- int current_tx_chan;
- int current_rx_chan;
- int num_tx_chan;
- int num_rx_chan;
- struct dma_channel_info tx_chan[2];
- struct dma_channel_info rx_chan[4];
-
- /*functions, optional*/
- u8* (*buffer_alloc)(int len,int* offset, void** opt);
- int (*buffer_free)(u8* dataptr, void* opt);
- int (*intr_handler)(struct dma_device_info* info, int status);
- /*set by device, clear by dma*/
- int ack;
- void * priv; /* used by peripheral driver only */
-};
-typedef struct dma_device_info _dma_device_info;
-
-int dma_device_register(struct dma_device_info* info);
-
-int dma_device_unregister(struct dma_device_info* info);
-
-int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt);
-
-int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt);
-
-int dma_device_update(struct dma_device_info* info);
-
-void dma_device_update_rx(struct dma_device_info* dma_dev);
-
-void dma_device_update_tx(struct dma_device_info* dma_dev);
-
-void register_handler_sim(int (*handler)(int));
-#endif /* AMAZON_DMA_H */
+++ /dev/null
-#ifndef _AMAZON_MEI_H
-#define _AMAZON_MEI_H
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#include "amazon_mei_app.h"
-
-#define AMAZON_MEI_DEBUG_ON
-#define AMAZON_MEI_CMV_EXTRA
-
-#define AMAZON_MEI_MAJOR 106
-
-/*
-** Define where in ME Processor's memory map the Stratify chip lives
-*/
-#define MEI_SPACE_ACCESS 0xB0100C00
-
-#define MAXSWAPSIZE 8 * 1024 //8k *(32bits)
-//#define AMAZON_ADSL_IMAGESIZE 16*1024 // 16k * (32bits)
-
-
-// Mailboxes
-#define MSG_LENGTH 16 // x16 bits
-#define YES_REPLY 1
-#define NO_REPLY 0
-
-#define CMV_TIMEOUT 100 //jiffies
-#define MIB_INTERVAL 10000 //msec
-
-/*** Bit definitions ***/
-
-#define FALSE 0
-#define TRUE 1
-#define BIT0 1<<0
-#define BIT1 1<<1
-#define BIT2 1<<2
-#define BIT3 1<<3
-#define BIT4 1<<4
-#define BIT5 1<<5
-#define BIT6 1<<6
-#define BIT7 1<<7
-#define BIT8 1<<8
-#define BIT9 1<<9
-#define BIT10 1<<10
-#define BIT11 1<<11
-#define BIT12 1<<12
-#define BIT13 1<<13
-#define BIT14 1<<14
-#define BIT15 1<<15
-#define BIT16 1<<16
-#define BIT17 1<<17
-#define BIT18 1<<18
-#define BIT19 1<<19
-#define BIT20 1<<20
-#define BIT21 1<<21
-#define BIT22 1<<22
-#define BIT23 1<<23
-#define BIT24 1<<24
-#define BIT25 1<<25
-#define BIT26 1<<26
-#define BIT27 1<<27
-#define BIT28 1<<28
-#define BIT29 1<<29
-#define BIT30 1<<30
-#define BIT31 1<<31
-
-
-/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
-#define MEI_DATA_XFR (0x0000 + MEI_SPACE_ACCESS)
-#define MEI_VERSION (0x0200 + MEI_SPACE_ACCESS)
-#define ARC_GP_STAT (0x0204 + MEI_SPACE_ACCESS)
-#define MEI_XFR_ADDR (0x020C + MEI_SPACE_ACCESS)
-#define MEI_TO_ARC_INT (0x021C + MEI_SPACE_ACCESS)
-#define ARC_TO_MEI_INT (0x0220 + MEI_SPACE_ACCESS)
-#define ARC_TO_MEI_INT_MASK (0x0224 + MEI_SPACE_ACCESS)
-#define MEI_DEBUG_WAD (0x0228 + MEI_SPACE_ACCESS)
-#define MEI_DEBUG_RAD (0x022C + MEI_SPACE_ACCESS)
-#define MEI_DEBUG_DATA (0x0230 + MEI_SPACE_ACCESS)
-#define MEI_DEBUG_DEC (0x0234 + MEI_SPACE_ACCESS)
-#define MEI_CONTROL (0x0238 + MEI_SPACE_ACCESS)
-#define AT_CELLRDY_BC0 (0x023C + MEI_SPACE_ACCESS)
-#define AT_CELLRDY_BC1 (0x0240 + MEI_SPACE_ACCESS)
-#define AR_CELLRDY_BC0 (0x0244 + MEI_SPACE_ACCESS)
-#define AR_CELLRDY_BC1 (0x0248 + MEI_SPACE_ACCESS)
-#define AAI_ACCESS (0x024C + MEI_SPACE_ACCESS)
-#define AAITXCB0 (0x0300 + MEI_SPACE_ACCESS)
-#define AAITXCB1 (0x0304 + MEI_SPACE_ACCESS)
-#define AAIRXCB0 (0x0308 + MEI_SPACE_ACCESS)
-#define AAIRXCB1 (0x030C + MEI_SPACE_ACCESS)
-
-
-// MEI_TO_ARC_INTERRUPT Register definitions
-#define MEI_TO_ARC_INT1 BIT3
-#define MEI_TO_ARC_INT0 BIT2
-#define MEI_TO_ARC_CS_DONE BIT1
-#define MEI_TO_ARC_MSGAV BIT0
-
-// ARC_TO_MEI_INTERRUPT Register definitions
-#define ARC_TO_MEI_INT1 BIT8
-#define ARC_TO_MEI_INT0 BIT7
-#define ARC_TO_MEI_CS_REQ BIT6
-#define ARC_TO_MEI_DBG_DONE BIT5
-#define ARC_TO_MEI_MSGACK BIT4
-#define ARC_TO_MEI_NO_ACCESS BIT3
-#define ARC_TO_MEI_CHECK_AAITX BIT2
-#define ARC_TO_MEI_CHECK_AAIRX BIT1
-#define ARC_TO_MEI_MSGAV BIT0
-
-// ARC_TO_MEI_INTERRUPT_MASK Register definitions
-#define GP_INT1_EN BIT8
-#define GP_INT0_EN BIT7
-#define CS_REQ_EN BIT6
-#define DBG_DONE_EN BIT5
-#define MSGACK_EN BIT4
-#define NO_ACC_EN BIT3
-#define AAITX_EN BIT2
-#define AAIRX_EN BIT1
-#define MSGAV_EN BIT0
-
-// MEI_CONTROL Register definitions
-#define INT_LEVEL BIT2
-#define SOFT_RESET BIT1
-#define HOST_MSTR BIT0
-
-// MEI_DEBUG_DECODE Register definitions
-#define MEI_DEBUG_DEC_MASK (0x3)
-#define MEI_DEBUG_DEC_AUX_MASK (0x0)
-#define MEI_DEBUG_DEC_DMP1_MASK (0x1)
-#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
-#define MEI_DEBUG_DEC_CORE_MASK (0x3)
-
-
-// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
-// page swap requests.
-#define MEI_TO_ARC_MAILBOX (0x15FC0)
-#define MEI_TO_ARC_MAILBOXR (0x15FEC)
-#define ARC_TO_MEI_MAILBOX (0x15F90)
-#define ARC_MEI_MAILBOXR (0x15FBC)
-
-// Codeswap request messages are indicated by setting BIT31
-#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
-
-/*
-** Swap page header
-*/
-// Page must be loaded at boot time if size field has BIT31 set
-#define BOOT_FLAG (BIT31)
-#define BOOT_FLAG_MASK ~BOOT_FLAG
-
-// Swap page header describes size in 32-bit words, load location, and image offset
-// for program and/or data segments
-typedef struct _arc_swp_page_hdr
-{
- u32 p_offset; // Offset bytes of progseg from beginning of image
- u32 p_dest; // Destination addr of progseg on processor
- u32 p_size; // Size in 32-bitwords of program segment
- u32 d_offset; // Offset bytes of dataseg from beginning of image
- u32 d_dest; // Destination addr of dataseg on processor
- u32 d_size; // Size in 32-bitwords of data segment
-}ARC_SWP_PAGE_HDR;
-
-
-/*
-** Swap image header
-*/
-#define GET_PROG 0 // Flag used for program mem segment
-#define GET_DATA 1 // Flag used for data mem segment
-
-// Image header contains size of image, checksum for image, and count of
-// page headers. Following that are 'count' page headers followed by
-// the code and/or data segments to be loaded
-typedef struct _arc_img_hdr
-{
- u32 size; // Size of binary image in bytes
- u32 checksum; // Checksum for image
- u32 count; // Count of swp pages in image
- ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
-}ARC_IMG_HDR;
-
-
-
-/*
-** Native size for the Stratiphy interface is 32-bits. All reads and writes
-** MUST be aligned on 32-bit boundaries. Trickery must be invoked to read word and/or
-** byte data. Read routines are provided. Write routines are probably a bad idea, as the
-** Arc has unrestrained, unseen access to the same memory, so a read-modify-write cycle
-** could very well have unintended results.
-*/
-MEI_ERROR meiCMV(u16 *, int); // first arg is CMV to ARC, second to indicate whether need reply
-
-void meiLongwordWrite(u32 ul_address, u32 ul_data);
-void meiLongwordRead(u32 ul_address, u32 *pul_data);
-
-
-MEI_ERROR meiDMAWrite(u32 destaddr, u32 *databuff, u32 databuffsize);
-MEI_ERROR meiDebugWrite(u32 destaddr, u32 *databuff, u32 databuffsize);
-
-MEI_ERROR meiDMARead(u32 srcaddr, u32 *databuff, u32 databuffsize);
-MEI_ERROR meiDebugRead(u32 srcaddr, u32 *databuff, u32 databuffsize);
-
-void meiPollForDbgDone(void);
-
-void meiMailboxInterruptsDisable(void);
-void meiMailboxInterruptsEnable(void);
-
-MEI_ERROR meiMailboxWrite(u16 *msgsrcbuffer, u16 msgsize);
-MEI_ERROR meiMailboxRead(u16 *msgdestbuffer, u16 msgsize);
-
-int meiGetPage( u32 Page, u32 data, u32 MaxSize, u32 *Buffer, u32 *Dest);
-
-MEI_ERROR meiHaltArc(void);
-MEI_ERROR meiRunArc(void);
-
-MEI_ERROR meiDownloadBootCode(void);
-
-MEI_ERROR meiForceRebootAdslModem(void);
-
-void makeCMV(u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data);
-
-#endif
-
+++ /dev/null
-//509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC and Added AMAZON_MEI_DEBUG_MODE ioctl
-
-#ifndef _AMAZON_MEI_APP_H
-#define _AMAZON_MEI_APP_H
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-
- // ioctl control
-#define AMAZON_MEI_START 300
-#define AMAZON_MEI_REPLY 301
-#define AMAZON_MEI_NOREPLY 302
-
-#define AMAZON_MEI_RESET 303
-#define AMAZON_MEI_REBOOT 304
-#define AMAZON_MEI_HALT 305
-#define AMAZON_MEI_CMV_WINHOST 306
-#define AMAZON_MEI_CMV_READ 307
-#define AMAZON_MEI_CMV_WRITE 308
-#define AMAZON_MEI_MIB_DAEMON 309
-#define AMAZON_MEI_SHOWTIME 310
-#define AMAZON_MEI_REMOTE 311
-#define AMAZON_MEI_READDEBUG 312
-#define AMAZON_MEI_WRITEDEBUG 313
-#define AMAZON_MEI_LOP 314
-
-#define AMAZON_MEI_PCM_SETUP 315
-#define AMAZON_MEI_PCM_START_TIMER 316
-#define AMAZON_MEI_PCM_STOP_TIMER 317
-#define AMAZON_MEI_PCM_CHECK 318
-#define AMAZON_MEI_GET_EOC_LEN 319
-#define AMAZON_MEI_GET_EOC_DATA 320
-#define AMAZON_MEI_PCM_GETDATA 321
-#define AMAZON_MEI_PCM_GPIO 322
-#define AMAZON_MEI_EOC_SEND 323
-//MIB
-#define AMAZON_MIB_LO_ATUC 324
-#define AMAZON_MIB_LO_ATUR 325
-#define AMAZON_MEI_DOWNLOAD 326
-
-#define AMAZON_MEI_DEBUG_MODE 327 //509221:tc.chen
-#define LOOP_DIAGNOSTIC_MODE_COMPLETE 328
-
-
-/*** Enums ***/
-typedef enum mei_error
-{
- MEI_SUCCESS = 0,
- MEI_FAILURE = -1,
- MEI_MAILBOX_FULL = -2,
- MEI_MAILBOX_EMPTY = -3,
- MEI_MAILBOX_TIMEOUT = -4,
-}MEI_ERROR;
-
-#endif
+++ /dev/null
-// 603221:tc.chen 2006/03/21 added APIs to support the WEB related parameters for ADSL Statistics
-
-#ifndef __AMAZON_MEI_APP_IOCTL_H
-#define __AMAZON_MEI_APP_IOCTL_H
-
-#ifdef __KERNEL__
-#include "amazon_mei_ioctl.h"
-#endif
-
-/* Interface Name */
-//#define INTERFACE_NAME <define the interface>
-
-/* adslLineTable constants */
-#define GET_ADSL_LINE_CODE 1
-
-/* adslAtucPhysTable constants */
-#define GET_ADSL_ATUC_PHY 4
-
-/* adslAturPhysTable constants */
-#define GET_ADSL_ATUR_PHY 10
-
-/* adslAtucChanTable constants */
-#define GET_ADSL_ATUC_CHAN_INFO 15
-
-/* adslAturChanTable constants */
-#define GET_ADSL_ATUR_CHAN_INFO 18
-
-/* adslAtucPerfDataTable constants */
-#define GET_ADSL_ATUC_PERF_DATA 21
-
-/* adslAturPerfDataTable constants */
-#define GET_ADSL_ATUR_PERF_DATA 40
-
-/* adslAtucIntervalTable constants */
-#define GET_ADSL_ATUC_INTVL_INFO 60
-
-/* adslAturIntervalTable constants */
-#define GET_ADSL_ATUR_INTVL_INFO 65
-
-/* adslAtucChanPerfDataTable constants */
-#define GET_ADSL_ATUC_CHAN_PERF_DATA 70
-
-/* adslAturChanPerfDataTable constants */
-#define GET_ADSL_ATUR_CHAN_PERF_DATA 90
-
-/* adslAtucChanIntervalTable constants */
-#define GET_ADSL_ATUC_CHAN_INTVL_INFO 110
-
-/* adslAturChanIntervalTable constants */
-#define GET_ADSL_ATUR_CHAN_INTVL_INFO 115
-
-/* adslLineAlarmConfProfileTable constants */
-#define GET_ADSL_ALRM_CONF_PROF 120
-#define SET_ADSL_ALRM_CONF_PROF 121
-
-/* adslAturTrap constants */
-#define ADSL_ATUR_TRAPS 135
-
-////////////////// RFC-3440 //////////////
-
-#ifdef AMAZON_MEI_MIB_RFC3440
-/* adslLineExtTable */
-#define GET_ADSL_ATUC_LINE_EXT 201
-#define SET_ADSL_ATUC_LINE_EXT 203
-
-/* adslAtucPerfDateExtTable */
-#define GET_ADSL_ATUC_PERF_DATA_EXT 205
-
-/* adslAtucIntervalExtTable */
-#define GET_ADSL_ATUC_INTVL_EXT_INFO 221
-
-/* adslAturPerfDataExtTable */
-#define GET_ADSL_ATUR_PERF_DATA_EXT 225
-
-/* adslAturIntervalExtTable */
-#define GET_ADSL_ATUR_INTVL_EXT_INFO 233
-
-/* adslAlarmConfProfileExtTable */
-#define GET_ADSL_ALRM_CONF_PROF_EXT 235
-#define SET_ADSL_ALRM_CONF_PROF_EXT 236
-
-/* adslAturExtTrap */
-#define ADSL_ATUR_EXT_TRAPS 240
-
-#endif
-
-// 603221:tc.chen start
-/* The following constants are added to support the WEB related ADSL Statistics */
-
-/* adslLineStatus constants */
-#define GET_ADSL_LINE_STATUS 245
-
-/* adslLineRate constants */
-#define GET_ADSL_LINE_RATE 250
-
-/* adslLineInformation constants */
-#define GET_ADSL_LINE_INFO 255
-
-/* adslNearEndPerformanceStats constants */
-#define GET_ADSL_NEAREND_STATS 270
-
-/* adslFarEndPerformanceStats constants */
-#define GET_ADSL_FAREND_STATS 290
-
-// 603221:tc.chen end
-
-/* Loop diagnostics mode of the ADSL line related constants */
-#define GET_ADSL_LOOP_DIAGNOSTICS_MODE 295
-#define SET_ADSL_LOOP_DIAGNOSTICS_MODE 296
-#define IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE 299
-
-/* Sub-carrier related parameters */
-#define GET_ADSL_ATUC_SUBCARRIER_STATS 297
-#define GET_ADSL_ATUR_SUBCARRIER_STATS 298
-#define GET_ADSL_LINE_INIT_STATS 150
-#define GET_ADSL_POWER_SPECTRAL_DENSITY 151
-
-
-///////////////////////////////////////////////////////////
-// makeCMV(Opcode, Group, Address, Index, Size, Data)
-
-/* adslLineCode Flags */
-#define LINE_CODE_FLAG 0x1 /* BIT 0th position */
-
-/* adslAtucPhysTable Flags */
-#define ATUC_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */
-#define ATUC_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 57, 0, 12, data)
-#define ATUC_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 57, 12, 4, data)
-
-#define ATUC_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */
-#define ATUC_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 64, 0, 4, data)
-
-#define ATUC_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */
-#define ATUC_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 58, 0, 8, data)
-
-#define ATUC_CURR_STAT_FLAG 0x8 /* BIT 3 */
-
-#define ATUC_CURR_OUT_PWR_FLAG 0x10 /* BIT 4 */
-#define ATUC_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 5, 1, data)
-
-#define ATUC_CURR_ATTR_FLAG 0x20 /* BIT 5 */
-#define ATUC_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 0, 2, data)
-
-
-/* adslAturPhysTable Flags */
-#define ATUR_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */
-#define ATUR_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 62, 0, 12, data)
-#define ATUR_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 62, 12, 4, data)
-
-#define ATUR_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */
-#define ATUR_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 65, 0, 4, data)
-
-#define ATUR_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */
-#define ATUR_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 61, 0, 8, data)
-
-#define ATUR_SNRMGN_FLAG 0x8
-#define ATUR_SNRMGN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 1, data)
-
-#define ATUR_ATTN_FLAG 0x10
-#define ATUR_ATTN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data)
-
-#define ATUR_CURR_STAT_FLAG 0x20 /* BIT 3 */
-
-#define ATUR_CURR_OUT_PWR_FLAG 0x40 /* BIT 4 */
-#define ATUR_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 5, 1, data)
-
-#define ATUR_CURR_ATTR_FLAG 0x80 /* BIT 5 */
-#define ATUR_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 0, 2, data)
-
-/* adslAtucChanTable Flags */
-#define ATUC_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */
-#define ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 1, 1, data)
-
-#define ATUC_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */
-#define ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data)
-
-#define ATUC_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */
-
-/* adslAturChanTable Flags */
-#define ATUR_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */
-#define ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 2, 1, 1, data)
-
-#define ATUR_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */
-#define ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data)
-
-#define ATUR_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */
-
-#define ATUR_CHAN_CRC_BLK_LEN_FLAG 0x8 /* BIT 3 */
-
-/* adslAtucPerfDataTable Flags */
-#define ATUC_PERF_LOFS_FLAG 0x1 /* BIT 0th position */
-#define ATUC_PERF_LOSS_FLAG 0x2 /* BIT 1 */
-#define ATUC_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data)
-#define ATUC_PERF_ESS_FLAG 0x4 /* BIT 2 */
-#define ATUC_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data)
-#define ATUC_PERF_INITS_FLAG 0x8 /* BIT 3 */
-#define ATUC_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */
-#define ATUC_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */
-#define ATUC_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */
-#define ATUC_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */
-#define ATUC_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */
-#define ATUC_PERF_CURR_15MIN_ESS_FLAG 0x200 /* BIT 9 */
-#define ATUC_PERF_CURR_15MIN_INIT_FLAG 0x400 /* BIT 10 */
-#define ATUC_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */
-#define ATUC_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */
-#define ATUC_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */
-#define ATUC_PERF_CURR_1DAY_ESS_FLAG 0x4000 /* BIT 14 */
-#define ATUC_PERF_CURR_1DAY_INIT_FLAG 0x8000 /* BIT 15 */
-#define ATUC_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */
-#define ATUC_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */
-#define ATUC_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */
-#define ATUC_PERF_PREV_1DAY_ESS_FLAG 0x80000 /* BIT 19 */
-#define ATUC_PERF_PREV_1DAY_INITS_FLAG 0x100000 /* BIT 20 */
-
-/* adslAturPerfDataTable Flags */
-#define ATUR_PERF_LOFS_FLAG 0x1 /* BIT 0th position */
-#define ATUR_PERF_LOSS_FLAG 0x2 /* BIT 1 */
-#define ATUR_PERF_LPR_FLAG 0x4 /* BIT 2 */
-#define ATUR_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data)
-#define ATUR_PERF_ESS_FLAG 0x8 /* BIT 3 */
-#define ATUR_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data)
-#define ATUR_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */
-#define ATUR_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */
-#define ATUR_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */
-#define ATUR_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */
-#define ATUR_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */
-#define ATUR_PERF_CURR_15MIN_LPR_FLAG 0x200 /* BIT 9 */
-#define ATUR_PERF_CURR_15MIN_ESS_FLAG 0x400 /* BIT 10 */
-#define ATUR_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */
-#define ATUR_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */
-#define ATUR_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */
-#define ATUR_PERF_CURR_1DAY_LPR_FLAG 0x4000 /* BIT 14 */
-#define ATUR_PERF_CURR_1DAY_ESS_FLAG 0x8000 /* BIT 15 */
-#define ATUR_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */
-#define ATUR_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */
-#define ATUR_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */
-#define ATUR_PERF_PREV_1DAY_LPR_FLAG 0x80000 /* BIT 19 */
-#define ATUR_PERF_PREV_1DAY_ESS_FLAG 0x100000 /* BIT 20 */
-
-/* adslAtucIntervalTable Flags */
-#define ATUC_INTVL_LOF_FLAG 0x1 /* BIT 0th position */
-#define ATUC_INTVL_LOS_FLAG 0x2 /* BIT 1 */
-#define ATUC_INTVL_ESS_FLAG 0x4 /* BIT 2 */
-#define ATUC_INTVL_INIT_FLAG 0x8 /* BIT 3 */
-#define ATUC_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */
-
-/* adslAturIntervalTable Flags */
-#define ATUR_INTVL_LOF_FLAG 0x1 /* BIT 0th position */
-#define ATUR_INTVL_LOS_FLAG 0x2 /* BIT 1 */
-#define ATUR_INTVL_LPR_FLAG 0x4 /* BIT 2 */
-#define ATUR_INTVL_ESS_FLAG 0x8 /* BIT 3 */
-#define ATUR_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */
-
-/* adslAtucChanPerfDataTable Flags */
-#define ATUC_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */
-#define ATUC_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */
-#define ATUC_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */
-#define ATUC_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */
-#define ATUC_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */
-#define ATUC_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */
-#define ATUC_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */
-#define ATUC_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */
-#define ATUC_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */
-#define ATUC_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */
-#define ATUC_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */
-#define ATUC_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11*/
-#define ATUC_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */
-#define ATUC_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */
-#define ATUC_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */
-#define ATUC_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */
-#define ATUC_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */
-#define ATUC_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */
-#define ATUC_CHAN_PERF_PREV_1DAY_TX_BLK_FLAG 0x40000 /* BIT 18 */
-#define ATUC_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */
-#define ATUC_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */
-
-
-/* adslAturChanPerfDataTable Flags */
-#define ATUR_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */
-#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data)
-#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data)
-#define ATUR_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */
-#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data)
-#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data)
-#define ATUR_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */
-#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data)
-#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data)
-#define ATUR_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */
-#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data)
-#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data)
-#define ATUR_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */
-#define ATUR_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */
-#define ATUR_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */
-#define ATUR_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */
-#define ATUR_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */
-#define ATUR_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */
-#define ATUR_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */
-#define ATUR_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */
-#define ATUR_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */
-#define ATUR_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */
-#define ATUR_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */
-#define ATUR_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */
-#define ATUR_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */
-#define ATUR_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */
-#define ATUR_CHAN_PERF_PREV_1DAY_TRANS_BLK_FLAG 0x40000 /* BIT 18 */
-#define ATUR_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */
-#define ATUR_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */
-
-/* adslAtucChanIntervalTable Flags */
-#define ATUC_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th position */
-#define ATUC_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */
-#define ATUC_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */
-#define ATUC_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */
-#define ATUC_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */
-#define ATUC_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */
-
-/* adslAturChanIntervalTable Flags */
-#define ATUR_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th Position */
-#define ATUR_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */
-#define ATUR_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */
-#define ATUR_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */
-#define ATUR_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */
-#define ATUR_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */
-
-/* adslLineAlarmConfProfileTable Flags */
-#define ATUC_THRESH_15MIN_LOFS_FLAG 0x01 /* BIT 0th position */
-#define ATUC_THRESH_15MIN_LOSS_FLAG 0x02 /* BIT 1 */
-#define ATUC_THRESH_15MIN_ESS_FLAG 0x04 /* BIT 2 */
-#define ATUC_THRESH_FAST_RATEUP_FLAG 0x08 /* BIT 3 */
-#define ATUC_THRESH_INTERLEAVE_RATEUP_FLAG 0x10 /* BIT 4 */
-#define ATUC_THRESH_FAST_RATEDOWN_FLAG 0x20 /* BIT 5 */
-#define ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x40 /* BIT 6 */
-#define ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG 0x80 /* BIT 7 */
-#define ATUR_THRESH_15MIN_LOFS_FLAG 0x100 /* BIT 8 */
-#define ATUR_THRESH_15MIN_LOSS_FLAG 0x200 /* BIT 9 */
-#define ATUR_THRESH_15MIN_LPRS_FLAG 0x400 /* BIT 10 */
-#define ATUR_THRESH_15MIN_ESS_FLAG 0x800 /* BIT 11 */
-#define ATUR_THRESH_FAST_RATEUP_FLAG 0x1000 /* BIT 12 */
-#define ATUR_THRESH_INTERLEAVE_RATEUP_FLAG 0x2000 /* BIT 13 */
-#define ATUR_THRESH_FAST_RATEDOWN_FLAG 0x4000 /* BIT 14 */
-#define ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x8000 /* BIT 15 */
-#define LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG 0x10000 /* BIT 16 */
-
-
-/* adslAturTraps Flags */
-#define ATUC_PERF_LOFS_THRESH_FLAG 0x1 /* BIT 0th position */
-#define ATUC_PERF_LOSS_THRESH_FLAG 0x2 /* BIT 1 */
-#define ATUC_PERF_ESS_THRESH_FLAG 0x4 /* BIT 2 */
-#define ATUC_RATE_CHANGE_FLAG 0x8 /* BIT 3 */
-#define ATUR_PERF_LOFS_THRESH_FLAG 0x10 /* BIT 4 */
-#define ATUR_PERF_LOSS_THRESH_FLAG 0x20 /* BIT 5 */
-#define ATUR_PERF_LPRS_THRESH_FLAG 0x40 /* BIT 6 */
-#define ATUR_PERF_ESS_THRESH_FLAG 0x80 /* BIT 7 */
-#define ATUR_RATE_CHANGE_FLAG 0x100 /* BIT 8 */
-
-//RFC- 3440 FLAG DEFINITIONS
-
-#ifdef AMAZON_MEI_MIB_RFC3440
-/* adslLineExtTable flags */
-#define ATUC_LINE_TRANS_CAP_FLAG 0x1 /* BIT 0th position */
-#define ATUC_LINE_TRANS_CAP_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data)
-#define ATUC_LINE_TRANS_CONFIG_FLAG 0x2 /* BIT 1 */
-#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data)
-#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV_WR makeCMV(H2D_CMV_WRITE,INFO, 67, 0, 1, data)
-#define ATUC_LINE_TRANS_ACTUAL_FLAG 0x4 /* BIT 2 */
-#define ATUC_LINE_TRANS_ACTUAL_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 1, 0, 1, data)
-#define LINE_GLITE_POWER_STATE_FLAG 0x8 /* BIT 3 */
-#define LINE_GLITE_POWER_STATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 0, 0, 1, data)
-
-/* adslAtucPerfDataExtTable flags */
-#define ATUC_PERF_STAT_FASTR_FLAG 0x1 /* BIT 0th position */
-#define ATUC_PERF_STAT_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data)
-#define ATUC_PERF_STAT_FAILED_FASTR_FLAG 0x2 /* BIT 1 */
-#define ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data)
-#define ATUC_PERF_STAT_SESL_FLAG 0X4 /* BIT 2 */
-#define ATUC_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data)
-#define ATUC_PERF_STAT_UASL_FLAG 0X8 /* BIT 3 */
-#define ATUC_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data)
-#define ATUC_PERF_CURR_15MIN_FASTR_FLAG 0X10 /* BIT 4 */
-#define ATUC_PERF_CURR_15MIN_FAILED_FASTR_FLAG 0X20 /* BIT 5 */
-#define ATUC_PERF_CURR_15MIN_SESL_FLAG 0X40 /* BIT 6 */
-#define ATUC_PERF_CURR_15MIN_UASL_FLAG 0X80 /* BIT 7 */
-#define ATUC_PERF_CURR_1DAY_FASTR_FLAG 0X100 /* BIT 8 */
-#define ATUC_PERF_CURR_1DAY_FAILED_FASTR_FLAG 0X200 /* BIT 9 */
-#define ATUC_PERF_CURR_1DAY_SESL_FLAG 0X400 /* BIT 10 */
-#define ATUC_PERF_CURR_1DAY_UASL_FLAG 0X800 /* BIT 11 */
-#define ATUC_PERF_PREV_1DAY_FASTR_FLAG 0X1000 /* BIT 12 */
-#define ATUC_PERF_PREV_1DAY_FAILED_FASTR_FLAG 0X2000 /* BIT 13 */
-#define ATUC_PERF_PREV_1DAY_SESL_FLAG 0X4000 /* BIT 14 */
-#define ATUC_PERF_PREV_1DAY_UASL_FLAG 0X8000 /* BIT 15 */
-
-/* adslAturPerfDataExtTable */
-#define ATUR_PERF_STAT_SESL_FLAG 0X1 /* BIT 0th position */
-#define ATUR_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data)
-#define ATUR_PERF_STAT_UASL_FLAG 0X2 /* BIT 1 */
-#define ATUR_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data)
-#define ATUR_PERF_CURR_15MIN_SESL_FLAG 0X4 /* BIT 2 */
-#define ATUR_PERF_CURR_15MIN_UASL_FLAG 0X8 /* BIT 3 */
-#define ATUR_PERF_CURR_1DAY_SESL_FLAG 0X10 /* BIT 4 */
-#define ATUR_PERF_CURR_1DAY_UASL_FLAG 0X20 /* BIT 5 */
-#define ATUR_PERF_PREV_1DAY_SESL_FLAG 0X40 /* BIT 6 */
-#define ATUR_PERF_PREV_1DAY_UASL_FLAG 0X80 /* BIT 7 */
-
-/* adslAutcIntervalExtTable flags */
-#define ATUC_INTERVAL_FASTR_FLAG 0x1 /* Bit 0 */
-#define ATUC_INTERVAL_FAILED_FASTR_FLAG 0x2 /* Bit 1 */
-#define ATUC_INTERVAL_SESL_FLAG 0x4 /* Bit 2 */
-#define ATUC_INTERVAL_UASL_FLAG 0x8 /* Bit 3 */
-
-/* adslAturIntervalExtTable */
-#define ATUR_INTERVAL_SESL_FLAG 0X1 /* BIT 0th position */
-#define ATUR_INTERVAL_UASL_FLAG 0X2 /* BIT 1 */
-
-/* adslAlarmConfProfileExtTable */
-#define ATUC_THRESH_15MIN_FAILED_FASTR_FLAG 0X1/* BIT 0th position */
-#define ATUC_THRESH_15MIN_SESL_FLAG 0X2 /* BIT 1 */
-#define ATUC_THRESH_15MIN_UASL_FLAG 0X4 /* BIT 2 */
-#define ATUR_THRESH_15MIN_SESL_FLAG 0X8 /* BIT 3 */
-#define ATUR_THRESH_15MIN_UASL_FLAG 0X10 /* BIT 4 */
-
-/* adslAturExtTraps */
-#define ATUC_15MIN_FAILED_FASTR_TRAP_FLAG 0X1 /* BIT 0th position */
-#define ATUC_15MIN_SESL_TRAP_FLAG 0X2 /* BIT 1 */
-#define ATUC_15MIN_UASL_TRAP_FLAG 0X4 /* BIT 2 */
-#define ATUR_15MIN_SESL_TRAP_FLAG 0X8 /* BIT 3 */
-#define ATUR_15MIN_UASL_TRAP_FLAG 0X10 /* BIT 4 */
-
-// 603221:tc.chen start
-/* adslLineStatus Flags */
-#define LINE_STAT_MODEM_STATUS_FLAG 0x1 /* BIT 0th position */
-#define LINE_STAT_MODEM_STATUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data)
-#define LINE_STAT_MODE_SEL_FLAG 0x2 /* BIT 1 */
-#define LINE_STAT_MODE_SEL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 1, 0, 1, data)
-#define LINE_STAT_TRELLCOD_ENABLE_FLAG 0x4 /* BIT 2 */
-#define LINE_STAT_TRELLCOD_ENABLE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, OPTN, 2, 0, 1, data)
-#define LINE_STAT_LATENCY_FLAG 0x8 /* BIT 3 */
-#define LINE_STAT_LATENCY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 12, 0, 1, data)
-
-/* adslLineRate Flags */
-#define LINE_RATE_DATA_RATEDS_FLAG 0x1 /* BIT 0th position */
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 2, 2, data)
-
-
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 0, 1, data)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 0, 1, data)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 0, 1, data)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 0, 1, data)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 0, 2, data)
-
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 1, 1, data)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 1, 1, data)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 1, 1, data)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 1, 1, data)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 2, 2, data)
-
-#define LINE_RATE_DATA_RATEUS_FLAG 0x2 /* BIT 1 */
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 2, 2, data)
-
-
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 0, 1, data)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 0, 1, data)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 0, 1, data)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 0, 1, data)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 0, 2, data)
-
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 1, 1, data)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 1, 1, data)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 1, 1, data)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 1, 1, data)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 2, 2, data)
-
-#define LINE_RATE_ATTNDRDS_FLAG 0x4 /* BIT 2 */
-#define LINE_RATE_ATTNDRDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 2, data)
-
-#define LINE_RATE_ATTNDRUS_FLAG 0x8 /* BIT 3 */
-#define LINE_RATE_ATTNDRUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 4, 2, data)
-
-/* adslLineInformation Flags */
-#define LINE_INFO_INTLV_DEPTHDS_FLAG 0x1 /* BIT 0th position */
-#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 0, 1, data)
-#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 1, 1, data)
-#define LINE_INFO_INTLV_DEPTHUS_FLAG 0x2 /* BIT 1 */
-#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 0, 1, data)
-#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 1, 1, data)
-#define LINE_INFO_LATNDS_FLAG 0x4 /* BIT 2 */
-#define LINE_INFO_LATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 1, 1, data)
-#define LINE_INFO_LATNUS_FLAG 0x8 /* BIT 3 */
-#define LINE_INFO_LATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 1, 1, data)
-#define LINE_INFO_SATNDS_FLAG 0x10 /* BIT 4 */
-#define LINE_INFO_SATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data)
-#define LINE_INFO_SATNUS_FLAG 0x20 /* BIT 5 */
-#define LINE_INFO_SATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 2, 1, data)
-#define LINE_INFO_SNRMNDS_FLAG 0x40 /* BIT 6 */
-#define LINE_INFO_SNRMNDS_FLAG_ADSL1_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 3, 1, data)
-#define LINE_INFO_SNRMNDS_FLAG_ADSL2_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 0, 1, data)
-#define LINE_INFO_SNRMNDS_FLAG_ADSL2PLUS_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 46, 0, 1, data)
-#define LINE_INFO_SNRMNUS_FLAG 0x80 /* BIT 7 */
-#define LINE_INFO_SNRMNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 3, 1, data)
-#define LINE_INFO_ACATPDS_FLAG 0x100 /* BIT 8 */
-#define LINE_INFO_ACATPDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 6, 1, data)
-#define LINE_INFO_ACATPUS_FLAG 0x200 /* BIT 9 */
-#define LINE_INFO_ACATPUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 6, 1, data)
-
-/* adslNearEndPerformanceStats Flags */
-#define NEAREND_PERF_SUPERFRAME_FLAG_LSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data)
-#define NEAREND_PERF_SUPERFRAME_FLAG_MSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data)
-#define NEAREND_PERF_SUPERFRAME_FLAG 0x1 /* BIT 0th position */
-#define NEAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data)
-#define NEAREND_PERF_LOS_FLAG 0x2 /* BIT 1 */
-#define NEAREND_PERF_LOF_FLAG 0x4 /* BIT 2 */
-#define NEAREND_PERF_LPR_FLAG 0x8 /* BIT 3 */
-#define NEAREND_PERF_NCD_FLAG 0x10 /* BIT 4 */
-#define NEAREND_PERF_LCD_FLAG 0x20 /* BIT 5 */
-#define NEAREND_PERF_CRC_FLAG 0x40 /* BIT 6 */
-#define NEAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data)
-#define NEAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data)
-#define NEAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data)
-#define NEAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data)
-#define NEAREND_PERF_RSCORR_FLAG 0x80 /* BIT 7 */
-#define NEAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 6, 0, 1, data)
-#define NEAREND_PERF_FECS_FLAG 0x100 /* BIT 8 */
-#define NEAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data)
-#define NEAREND_PERF_ES_FLAG 0x200 /* BIT 9 */
-#define NEAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data)
-#define NEAREND_PERF_SES_FLAG 0x400 /* BIT 10 */
-#define NEAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 9, 0, 1, data)
-#define NEAREND_PERF_LOSS_FLAG 0x800 /* BIT 11 */
-#define NEAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data)
-#define NEAREND_PERF_UAS_FLAG 0x1000 /* BIT 12 */
-#define NEAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 0, 2, data)
-#define NEAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 2, 2, data)
-#define NEAREND_PERF_HECERR_FLAG 0x2000 /* BIT 13 */
-
-/* adslFarEndPerformanceStats Flags */
-#define FAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data)
-#define FAREND_PERF_LOS_FLAG 0x1 /* BIT 0th position */
-#define FAREND_PERF_LOF_FLAG 0x2 /* BIT 1 */
-#define FAREND_PERF_LPR_FLAG 0x4 /* BIT 2 */
-#define FAREND_PERF_NCD_FLAG 0x8 /* BIT 3 */
-#define FAREND_PERF_LCD_FLAG 0x10 /* BIT 4 */
-#define FAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 0, 1, data)
-#define FAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 1, 1, data)
-#define FAREND_PERF_CRC_FLAG 0x20 /* BIT 5 */
-#define FAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 0, 1, data)
-#define FAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 1, 1, data)
-#define FAREND_PERF_RSCORR_FLAG 0x40 /* BIT 6 */
-#define FAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 32, 0, 1, data)
-#define FAREND_PERF_FECS_FLAG 0x80 /* BIT 7 */
-#define FAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data)
-#define FAREND_PERF_ES_FLAG 0x100 /* BIT 8 */
-#define FAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data)
-#define FAREND_PERF_SES_FLAG 0x200 /* BIT 9 */
-#define FAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 35, 0, 1, data)
-#define FAREND_PERF_LOSS_FLAG 0x400 /* BIT 10 */
-#define FAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data)
-#define FAREND_PERF_UAS_FLAG 0x800 /* BIT 11 */
-#define FAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 0, 2, data)
-#define FAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 2, 2, data)
-#define FAREND_PERF_HECERR_FLAG 0x1000 /* BIT 12 */
-// 603221:tc.chen end
-/* TR-69 related additional parameters - defines */
-/* Defines for struct adslATURSubcarrierInfo */
-#define NEAREND_HLINSC 0x1
-#define NEAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 71, 2, 1, data)
-#define NEAREND_HLINPS 0x2
-#define NEAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 73, idx, size, data)
-#define NEAREND_HLOGMT 0x4
-#define NEAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 0, 1, data)
-#define NEAREND_HLOGPS 0x8
-#define NEAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 75, idx, size, data)
-#define NEAREND_QLNMT 0x10
-#define NEAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 1, 1, data)
-#define NEAREND_QLNPS 0x20
-#define NEAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 77, idx, size, data)
-#define NEAREND_SNRMT 0x40
-#define NEAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 2, 1, data)
-#define NEAREND_SNRPS 0x80
-#define NEAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 78, idx, size, data)
-#define NEAREND_BITPS 0x100
-#define NEAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 22, idx, size, data)
-#define NEAREND_GAINPS 0x200
-#define NEAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 24, idx, size, data)
-
-/* Defines for struct adslATUCSubcarrierInfo */
-#define FAREND_HLINSC 0x1
-#define FAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 70, 0, 1, data)
-#define FAREND_HLINPS 0x2
-#define FAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 72, idx, size, data)
-#define FAREND_HLOGMT 0x4
-#define FAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 0, 1, data)
-#define FAREND_HLOGPS 0x8
-#define FAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 74, idx, size, data)
-#define FAREND_QLNMT 0x10
-#define FAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 1, 1, data)
-#define FAREND_QLNPS 0x20
-#define FAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 76, idx, size, data)
-#define FAREND_SNRMT 0x40
-#define FAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 2, 1, data)
-#define FAREND_SNRPS 0x80
-#define FAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 10, idx, size, data)
-#define FAREND_BITPS 0x100
-#define FAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 23, idx, size, data)
-#define FAREND_GAINPS 0x200
-#define FAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 25, idx, size, data)
-
-
-// GET_ADSL_POWER_SPECTRAL_DENSITY
-#define NOMPSD_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 0, 1, data)
-#define NOMPSD_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 1, 1, data)
-#define PCB_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 6, 1, data)
-#define PCB_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 7, 1, data)
-#define RMSGI_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 10, 1, data)
-#define RMSGI_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 11, 1, data)
-
-
-#endif
-/////////////////////////////////////////////////Macro Definitions ? FLAG Setting & Testing
-
-#define SET_FLAG(flags, flag_val) ((*flags) = ((*flags) | flag_val))
-// -- This macro sets the flags with the flag_val. Here flags is passed as a pointer
-
-#define IS_FLAG_SET(flags, test_flag) (((*flags) & (test_flag)) == (test_flag)? test_flag:0)
-// -- This macro verifies whether test_flag has been set in flags. Here flags is passed as a pointer
-
-
-#define CLR_FLAG(flags, flag_bit) ((*flags) = (*flags) & (~flag_bit))
-// -- This macro resets the specified flag_bit in the flags. Here flags is passed as a pointer
-
-
-////////////////////////////////////////////////DATA STRUCTURES ORGANIZATION
-
-//Here are the data structures used for accessing mib parameters. The ioctl call includes the third parameter as a void pointer. This parameter has to be type-casted in the driver code to the corresponding structure depending upon the command type. For Ex: consider the ioctl used to get the adslLineCode type, ioctl(fd,GET_ADSL_LINE_CODE,void *struct_adslLineTableEntry). In the driver code we check on the type of the command, i.e GET_ADSL_LINE_CODE and type-cast the void pointer to struct adslLineTableEntry type.
- //
-#define u32 unsigned int
-#define u16 unsigned short
-#define s16 short
-#define u8 unsigned char
-
-
-typedef u32 AdslPerfTimeElapsed;
-typedef u32 AdslPerfPrevDayCount;
-typedef u32 PerfCurrentCount;
-typedef u32 PerfIntervalCount;
-typedef u32 AdslPerfCurrDayCount;
-
-
-//ioctl(int fd, GET_ADSL_LINE_CODE, void *struct_adslLineTableEntry)
-
-typedef struct adslLineTableEntry {
- int ifIndex;
- int adslLineCode;
- u8 flags;
-} adslLineTableEntry;
-
-#ifdef AMAZON_MEI_MIB_RFC3440
-typedef struct adslLineExtTableEntry {
- int ifIndex;
- u16 adslLineTransAtucCap;
- u16 adslLineTransAtucConfig;
- u16 adslLineTransAtucActual;
- int adslLineGlitePowerState;
- u32 flags;
-}adslLineExtTableEntry;
-#endif
-//ioctl(int fd, GET_ADSL_ATUC_PHY, void *struct_adslAtucPhysEntry)
-
-typedef struct adslVendorId {
- u16 country_code;
- u_char provider_id[4]; /* Ascii characters */
- u_char revision_info[2];
-}adslVendorId;
-
-
-typedef struct adslAtucPhysEntry {
- int ifIndex;
- char serial_no[32];
- union {
- char vendor_id[16];
- adslVendorId vendor_info;
- } vendor_id;
-
- char version_no[16];
- u32 status;
- int outputPwr;
- u32 attainableRate;
- u8 flags;
-} adslAtucPhysEntry;
-
-
-//ioctl(int fd, GET_ADSL_ATUR_PHY, void *struct_adslAturPhysEntry)
-
-typedef struct adslAturPhysEntry {
- int ifIndex;
- char serial_no[32];
- union {
- char vendor_id[16];
- adslVendorId vendor_info;
- } vendor_id;
- char version_no[16];
- int SnrMgn;
- u32 Attn;
- u32 status;
- int outputPwr;
- u32 attainableRate;
- u8 flags;
-} adslAturPhysEntry;
-
-
-//ioctl(int fd, GET_ADSL_ATUC_CHAN_INFO, void *struct_adslAtucChanInfo)
-
-typedef struct adslAtucChanInfo {
- int ifIndex;
- u32 interleaveDelay;
- u32 currTxRate;
- u32 prevTxRate;
- u8 flags;
-} adslAtucChanInfo;
-
-
-//ioctl(int fd, GET_ADSL_ATUR_CHAN_INFO, void *struct_adslAturChanInfo)
-
-typedef struct adslAturChanInfo {
- int ifIndex;
- u32 interleaveDelay;
- u32 currTxRate;
- u32 prevTxRate;
- u32 crcBlkLen;
- u8 flags;
-} adslAturChanInfo;
-
-
-//ioctl(int fd, GET_ADSL_ATUC_PERF_DATA, void *struct_atucPerfDataEntry)
-
-typedef struct atucPerfDataEntry
-{
- int ifIndex;
- u32 adslAtucPerfLofs;
- u32 adslAtucPerfLoss;
- u32 adslAtucPerfESs;
- u32 adslAtucPerfInits;
- int adslAtucPerfValidIntervals;
- int adslAtucPerfInvalidIntervals;
- AdslPerfTimeElapsed adslAtucPerfCurr15MinTimeElapsed;
- PerfCurrentCount adslAtucPerfCurr15MinLofs;
- PerfCurrentCount adslAtucPerfCurr15MinLoss;
- PerfCurrentCount adslAtucPerfCurr15MinESs;
- PerfCurrentCount adslAtucPerfCurr15MinInits;
- AdslPerfTimeElapsed adslAtucPerfCurr1DayTimeElapsed;
- AdslPerfCurrDayCount adslAtucPerfCurr1DayLofs;
- AdslPerfCurrDayCount adslAtucPerfCurr1DayLoss;
- AdslPerfCurrDayCount adslAtucPerfCurr1DayESs;
- AdslPerfCurrDayCount adslAtucPerfCurr1DayInits;
- int adslAtucPerfPrev1DayMoniSecs;
- AdslPerfPrevDayCount adslAtucPerfPrev1DayLofs;
- AdslPerfPrevDayCount adslAtucPerfPrev1DayLoss;
- AdslPerfPrevDayCount adslAtucPerfPrev1DayESs;
- AdslPerfPrevDayCount adslAtucPerfPrev1DayInits;
- u32 flags;
-} atucPerfDataEntry;
-
-#ifdef AMAZON_MEI_MIB_RFC3440
-typedef struct atucPerfDataExtEntry
- {
- int ifIndex;
- u32 adslAtucPerfStatFastR;
- u32 adslAtucPerfStatFailedFastR;
- u32 adslAtucPerfStatSesL;
- u32 adslAtucPerfStatUasL;
- u32 adslAtucPerfCurr15MinFastR;
- u32 adslAtucPerfCurr15MinFailedFastR;
- u32 adslAtucPerfCurr15MinSesL;
- u32 adslAtucPerfCurr15MinUasL;
- u32 adslAtucPerfCurr1DayFastR;
- u32 adslAtucPerfCurr1DayFailedFastR;
- u32 adslAtucPerfCurr1DaySesL;
- u32 adslAtucPerfCurr1DayUasL;
- u32 adslAtucPerfPrev1DayFastR;
- u32 adslAtucPerfPrev1DayFailedFastR;
- u32 adslAtucPerfPrev1DaySesL;
- u32 adslAtucPerfPrev1DayUasL;
- u32 flags;
-} atucPerfDataExtEntry;
-
-#endif
-//ioctl(int fd, GET_ADSL_ATUR_PERF_DATA, void *struct_aturPerfDataEntry)
-
-typedef struct aturPerfDataEntry
-{
- int ifIndex;
- u32 adslAturPerfLofs;
- u32 adslAturPerfLoss;
- u32 adslAturPerfLprs;
- u32 adslAturPerfESs;
- int adslAturPerfValidIntervals;
- int adslAturPerfInvalidIntervals;
- AdslPerfTimeElapsed adslAturPerfCurr15MinTimeElapsed;
- PerfCurrentCount adslAturPerfCurr15MinLofs;
- PerfCurrentCount adslAturPerfCurr15MinLoss;
- PerfCurrentCount adslAturPerfCurr15MinLprs;
- PerfCurrentCount adslAturPerfCurr15MinESs;
- AdslPerfTimeElapsed adslAturPerfCurr1DayTimeElapsed;
- AdslPerfCurrDayCount adslAturPerfCurr1DayLofs;
- AdslPerfCurrDayCount adslAturPerfCurr1DayLoss;
- AdslPerfCurrDayCount adslAturPerfCurr1DayLprs;
- AdslPerfCurrDayCount adslAturPerfCurr1DayESs;
- int adslAturPerfPrev1DayMoniSecs;
- AdslPerfPrevDayCount adslAturPerfPrev1DayLofs;
- AdslPerfPrevDayCount adslAturPerfPrev1DayLoss;
- AdslPerfPrevDayCount adslAturPerfPrev1DayLprs;
- AdslPerfPrevDayCount adslAturPerfPrev1DayESs;
- u32 flags;
-} aturPerfDataEntry;
-
-#ifdef AMAZON_MEI_MIB_RFC3440
-typedef struct aturPerfDataExtEntry
- {
- int ifIndex;
- u32 adslAturPerfStatSesL;
- u32 adslAturPerfStatUasL;
- u32 adslAturPerfCurr15MinSesL;
- u32 adslAturPerfCurr15MinUasL;
- u32 adslAturPerfCurr1DaySesL;
- u32 adslAturPerfCurr1DayUasL;
- u32 adslAturPerfPrev1DaySesL;
- u32 adslAturPerfPrev1DayUasL;
- u32 flags;
-} aturPerfDataExtEntry;
-#endif
-//ioctl(int fd, GET_ADSL_ATUC_INTVL_INFO, void *struct_adslAtucInvtInfo)
-
-typedef struct adslAtucIntvlInfo {
- int ifIndex;
- int IntervalNumber;
- PerfIntervalCount intervalLOF;
- PerfIntervalCount intervalLOS;
- PerfIntervalCount intervalES;
- PerfIntervalCount intervalInits;
- int intervalValidData;
- u8 flags;
-} adslAtucIntvlInfo;
-
-#ifdef AMAZON_MEI_MIB_RFC3440
-typedef struct adslAtucInvtlExtInfo
- {
- int ifIndex;
- int IntervalNumber;
- u32 adslAtucIntervalFastR;
- u32 adslAtucIntervalFailedFastR;
- u32 adslAtucIntervalSesL;
- u32 adslAtucIntervalUasL;
- u32 flags;
-} adslAtucInvtlExtInfo;
-#endif
-//ioctl(int fd, GET_ADSL_ATUR_INTVL_INFO, void *struct_adslAturInvtlInfo)
-
-typedef struct adslAturIntvlInfo {
- int ifIndex;
- int IntervalNumber;
- PerfIntervalCount intervalLOF;
- PerfIntervalCount intervalLOS;
- PerfIntervalCount intervalLPR;
- PerfIntervalCount intervalES;
- int intervalValidData;
- u8 flags;
-} adslAturIntvlInfo;
-
-#ifdef AMAZON_MEI_MIB_RFC3440
-typedef struct adslAturInvtlExtInfo
- {
- int ifIndex;
- int IntervalNumber;
- u32 adslAturIntervalSesL;
- u32 adslAturIntervalUasL;
- u32 flags;
-} adslAturInvtlExtInfo;
-#endif
-//ioctl(int fd, GET_ADSL_ATUC_CHAN_PERF_DATA, void *struct_atucChannelPerfDataEntry)
-
-typedef struct atucChannelPerfDataEntry
-{
- int ifIndex;
- u32 adslAtucChanReceivedBlks;
- u32 adslAtucChanTransmittedBlks;
- u32 adslAtucChanCorrectedBlks;
- u32 adslAtucChanUncorrectBlks;
- int adslAtucChanPerfValidIntervals;
- int adslAtucChanPerfInvalidIntervals;
- AdslPerfTimeElapsed adslAtucChanPerfCurr15MinTimeElapsed;
- PerfCurrentCount adslAtucChanPerfCurr15MinReceivedBlks;
- PerfCurrentCount adslAtucChanPerfCurr15MinTransmittedBlks;
- PerfCurrentCount adslAtucChanPerfCurr15MinCorrectedBlks;
- PerfCurrentCount adslAtucChanPerfCurr15MinUncorrectBlks;
- AdslPerfTimeElapsed adslAtucChanPerfCurr1DayTimeElapsed;
- AdslPerfCurrDayCount adslAtucChanPerfCurr1DayReceivedBlks;
- AdslPerfCurrDayCount adslAtucChanPerfCurr1DayTransmittedBlks;
- AdslPerfCurrDayCount adslAtucChanPerfCurr1DayCorrectedBlks;
- AdslPerfCurrDayCount adslAtucChanPerfCurr1DayUncorrectBlks;
- int adslAtucChanPerfPrev1DayMoniSecs;
- AdslPerfPrevDayCount adslAtucChanPerfPrev1DayReceivedBlks;
- AdslPerfPrevDayCount adslAtucChanPerfPrev1DayTransmittedBlks;
- AdslPerfPrevDayCount adslAtucChanPerfPrev1DayCorrectedBlks;
- AdslPerfPrevDayCount adslAtucChanPerfPrev1DayUncorrectBlks;
- u32 flags;
-}atucChannelPerfDataEntry;
-
-
-//ioctl(int fd, GET_ADSL_ATUR_CHAN_PERF_DATA, void *struct_aturChannelPerfDataEntry)
-
-typedef struct aturChannelPerfDataEntry
-{
- int ifIndex;
- u32 adslAturChanReceivedBlks;
- u32 adslAturChanTransmittedBlks;
- u32 adslAturChanCorrectedBlks;
- u32 adslAturChanUncorrectBlks;
- int adslAturChanPerfValidIntervals;
- int adslAturChanPerfInvalidIntervals;
- AdslPerfTimeElapsed adslAturChanPerfCurr15MinTimeElapsed;
- PerfCurrentCount adslAturChanPerfCurr15MinReceivedBlks;
- PerfCurrentCount adslAturChanPerfCurr15MinTransmittedBlks;
- PerfCurrentCount adslAturChanPerfCurr15MinCorrectedBlks;
- PerfCurrentCount adslAturChanPerfCurr15MinUncorrectBlks;
- AdslPerfTimeElapsed adslAturChanPerfCurr1DayTimeElapsed;
- AdslPerfCurrDayCount adslAturChanPerfCurr1DayReceivedBlks;
- AdslPerfCurrDayCount adslAturChanPerfCurr1DayTransmittedBlks;
- AdslPerfCurrDayCount adslAturChanPerfCurr1DayCorrectedBlks;
- AdslPerfCurrDayCount adslAturChanPerfCurr1DayUncorrectBlks;
- int adslAturChanPerfPrev1DayMoniSecs;
- AdslPerfPrevDayCount adslAturChanPerfPrev1DayReceivedBlks;
- AdslPerfPrevDayCount adslAturChanPerfPrev1DayTransmittedBlks;
- AdslPerfPrevDayCount adslAturChanPerfPrev1DayCorrectedBlks;
- AdslPerfPrevDayCount adslAturChanPerfPrev1DayUncorrectBlks;
- u32 flags;
-} aturChannelPerfDataEntry;
-
-
-//ioctl(int fd, GET_ADSL_ATUC_CHAN_INTVL_INFO, void *struct_adslAtucChanIntvlInfo)
-
-typedef struct adslAtucChanIntvlInfo {
- int ifIndex;
- int IntervalNumber;
- PerfIntervalCount chanIntervalRecvdBlks;
- PerfIntervalCount chanIntervalXmitBlks;
- PerfIntervalCount chanIntervalCorrectedBlks;
- PerfIntervalCount chanIntervalUncorrectBlks;
- int intervalValidData;
- u8 flags;
-} adslAtucChanIntvlInfo;
-
-
-//ioctl(int fd, GET_ADSL_ATUR_CHAN_INTVL_INFO, void *struct_adslAturChanIntvlInfo)
-
-typedef struct adslAturChanIntvlInfo {
- int ifIndex;
- int IntervalNumber;
- PerfIntervalCount chanIntervalRecvdBlks;
- PerfIntervalCount chanIntervalXmitBlks;
- PerfIntervalCount chanIntervalCorrectedBlks;
- PerfIntervalCount chanIntervalUncorrectBlks;
- int intervalValidData;
- u8 flags;
-} adslAturChanIntvlInfo;
-
-
-//ioctl(int fd, GET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry)
-//ioctl(int fd, SET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry)
-
-typedef struct adslLineAlarmConfProfileEntry
- {
- unsigned char adslLineAlarmConfProfileName[32];
- int adslAtucThresh15MinLofs;
- int adslAtucThresh15MinLoss;
- int adslAtucThresh15MinESs;
- u32 adslAtucThreshFastRateUp;
- u32 adslAtucThreshInterleaveRateUp;
- u32 adslAtucThreshFastRateDown;
- u32 adslAtucThreshInterleaveRateDown;
- int adslAtucInitFailureTrapEnable;
- int adslAturThresh15MinLofs;
- int adslAturThresh15MinLoss;
- int adslAturThresh15MinLprs;
- int adslAturThresh15MinESs;
- u32 adslAturThreshFastRateUp;
- u32 adslAturThreshInterleaveRateUp;
- u32 adslAturThreshFastRateDown;
- u32 adslAturThreshInterleaveRateDown;
- int adslLineAlarmConfProfileRowStatus;
- u32 flags;
-} adslLineAlarmConfProfileEntry;
-
-#ifdef AMAZON_MEI_MIB_RFC3440
-typedef struct adslLineAlarmConfProfileExtEntry
- {
- u8 adslLineAlarmConfProfileExtName[32];
- u32 adslAtucThreshold15MinFailedFastR;
- u32 adslAtucThreshold15MinSesL;
- u32 adslAtucThreshold15MinUasL;
- u32 adslAturThreshold15MinSesL;
- u32 adslAturThreshold15MinUasL;
- u32 flags;
-} adslLineAlarmConfProfileExtEntry;
-#endif
-//TRAPS
-
-// 603221:tc.chen start
-/* The following Data Sturctures are added to support the WEB related parameters for ADSL Statistics */
-typedef struct adslLineStatus
- {
- int adslModemStatus;
- u32 adslModeSelected;
- int adslAtucThresh15MinESs;
- int adslTrellisCodeEnable;
- int adslLatency;
- u8 flags;
- } adslLineStatusInfo;
-
-typedef struct adslLineRate
- {
- u32 adslDataRateds;
- u32 adslDataRateus;
- u32 adslATTNDRds;
- u32 adslATTNDRus;
- u8 flags;
- } adslLineRateInfo;
-
-typedef struct adslLineInfo
- {
- u32 adslInterleaveDepthds;
- u32 adslInterleaveDepthus;
- u32 adslLATNds;
- u32 adslLATNus;
- u32 adslSATNds;
- u32 adslSATNus;
- int adslSNRMds;
- int adslSNRMus;
- int adslACATPds;
- int adslACATPus;
- u32 flags;
- } adslLineInfo;
-
-typedef struct adslNearEndPerfStats
- {
- u32 adslSuperFrames;
- u32 adslneLOS;
- u32 adslneLOF;
- u32 adslneLPR;
- u32 adslneNCD;
- u32 adslneLCD;
- u32 adslneCRC;
- u32 adslneRSCorr;
- u32 adslneFECS;
- u32 adslneES;
- u32 adslneSES;
- u32 adslneLOSS;
- u32 adslneUAS;
- u32 adslneHECErrors;
- u32 flags;
- } adslNearEndPerfStats;
-
-typedef struct adslFarEndPerfStats
- {
- u32 adslfeLOS;
- u32 adslfeLOF;
- u32 adslfeLPR;
- u32 adslfeNCD;
- u32 adslfeLCD;
- u32 adslfeCRC;
- u32 adslfeRSCorr;
- u32 adslfeFECS;
- u32 adslfeES;
- u32 adslfeSES;
- u32 adslfeLOSS;
- u32 adslfeUAS;
- u32 adslfeHECErrors;
- u32 flags;
- } adslFarEndPerfStats;
-// 603221:tc.chen end
-
-/* The number of tones (and hence indexes) is dependent on the ADSL mode - G.992.1, G.992.2, G.992.3, * G.992.4 and G.992.5 */
-typedef struct adslATURSubcarrierInfo {
- int ifindex;
- u16 HLINSCds;
- u16 HLINpsds[1024];/* Even index = real part; Odd Index
- = imaginary part for each tone */
- u16 HLOGMTds;
- u16 HLOGpsds[512];
- u16 QLNMTds;
- u16 QLNpsds[512];
- u16 SNRMTds;
- u16 SNRpsds[512];
- u16 BITpsds[512];
- u16 GAINpsds[512];
- u16 flags;
-}adslATURSubcarrierInfo;
-
-typedef struct adslATUCSubcarrierInfo {
- int ifindex;
- u16 HLINSCus;
- u16 HLINpsus[128];/* Even index = real part; Odd Index
- = imaginary part for each tone */
- u16 HLOGMTus;
- u16 HLOGpsus[64];
- u16 QLNMTus;
- u16 QLNpsus[64];
- u16 SNRMTus;
- u16 SNRpsus[64];
- u16 BITpsus[64];
- u16 GAINpsus[64];
- u16 flags;
-}adslATUCSubcarrierInfo;
-
-#ifndef u_int16
-#define u_int16 u16
-#endif
-
-typedef struct adslInitStats {
- u_int16 FullInitializationCount;
- u_int16 FailedFullInitializationCount;
- u_int16 LINIT_Errors;
- u_int16 Init_Timeouts;
-}adslInitStats;
-
-typedef struct adslPowerSpectralDensity {
- int ACTPSDds;
- int ACTPSDus;
-}adslPowerSpectralDensity;
-
-
-//ioctl(int fd, ADSL_ATUR_TRAPS, void *uint16_flags)
-typedef union structpts {
- adslLineTableEntry * adslLineTableEntry_pt;
- adslAtucPhysEntry * adslAtucPhysEntry_pt;
- adslAturPhysEntry * adslAturPhysEntry_pt;
- adslAtucChanInfo * adslAtucChanInfo_pt;
- adslAturChanInfo * adslAturChanInfo_pt;
- atucPerfDataEntry * atucPerfDataEntry_pt;
- aturPerfDataEntry * aturPerfDataEntry_pt;
- adslAtucIntvlInfo * adslAtucIntvlInfo_pt;
- adslAturIntvlInfo * adslAturIntvlInfo_pt;
- atucChannelPerfDataEntry * atucChannelPerfDataEntry_pt;
- aturChannelPerfDataEntry * aturChannelPerfDataEntry_pt;
- adslAtucChanIntvlInfo * adslAtucChanIntvlInfo_pt;
- adslAturChanIntvlInfo * adslAturChanIntvlInfo_pt;
- adslLineAlarmConfProfileEntry * adslLineAlarmConfProfileEntry_pt;
- // RFC 3440
-
- #ifdef AMAZON_MEI_MIB_RFC3440
- adslLineExtTableEntry * adslLineExtTableEntry_pt;
- atucPerfDataExtEntry * atucPerfDataExtEntry_pt;
- adslAtucInvtlExtInfo * adslAtucInvtlExtInfo_pt;
- aturPerfDataExtEntry * aturPerfDataExtEntry_pt;
- adslAturInvtlExtInfo * adslAturInvtlExtInfo_pt;
- adslLineAlarmConfProfileExtEntry * adslLineAlarmConfProfileExtEntry_pt;
- #endif
-// 603221:tc.chen start
- adslLineStatusInfo * adslLineStatusInfo_pt;
- adslLineRateInfo * adslLineRateInfo_pt;
- adslLineInfo * adslLineInfo_pt;
- adslNearEndPerfStats * adslNearEndPerfStats_pt;
- adslFarEndPerfStats * adslFarEndPerfStats_pt;
-// 603221:tc.chen end
- adslATUCSubcarrierInfo * adslATUCSubcarrierInfo_pt;
- adslATURSubcarrierInfo * adslATURSubcarrierInfo_pt;
- adslPowerSpectralDensity * adslPowerSpectralDensity_pt;
-}structpts;
-
-#endif /* ] __AMAZON_MEI_APP_IOCTL_H */
+++ /dev/null
-//509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC and Added AMAZON_MEI_DEBUG_MODE ioctl
-#ifndef _AMAZON_MEI_IOCTL_H
-#define _AMAZON_MEI_IOCTL_H
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-#define PCM_BUFF_SIZE 1024 //bytes
-// interrupt numbers
-
-#ifndef _AMAZON_ADSL_APP
-
-typedef struct pcm_data_struct{
- u16 S;
- u16 temp;
- u16 LSW;
- u16 MSW;
- u16 len;
- u16 rdindex;
- u16 wrindex;
- u16 flow;
-
- int finish;
- u8 buff[PCM_BUFF_SIZE];
- int point;
-}pcm_data_struct;
-
-typedef struct amazon_clreoc_pkt{
- struct list_head list;
- u8 * command; //point to clreoc command data
- int len; //command length
-}amazon_clreoc_pkt;
-
-// Number of intervals
-#define INTERVAL_NUM 192 //two days
-typedef struct amazon_mei_mib{
- struct list_head list;
- struct timeval start_time; //start of current interval
-
- int AtucPerfLof;
- int AtucPerfLos;
- int AtucPerfEs;
- int AtucPerfInit;
-
- int AturPerfLof;
- int AturPerfLos;
- int AturPerfLpr;
- int AturPerfEs;
-
- int AturChanPerfRxBlk;
- int AturChanPerfTxBlk;
- int AturChanPerfCorrBlk;
- int AturChanPerfUncorrBlk;
-
- //RFC-3440
- int AtucPerfStatFastR;
- int AtucPerfStatFailedFastR;
- int AtucPerfStatSesL;
- int AtucPerfStatUasL;
- int AturPerfStatSesL;
- int AturPerfStatUasL;
-}amazon_mei_mib;
-
-typedef struct adslChanPrevTxRate{
- u32 adslAtucChanPrevTxRate;
- u32 adslAturChanPrevTxRate;
-}adslChanPrevTxRate;
-
-typedef struct adslPhysCurrStatus{
- u32 adslAtucCurrStatus;
- u32 adslAturCurrStatus;
-}adslPhysCurrStatus;
-
-typedef struct ChanType{
- int interleave;
- int fast;
-// 603221:tc.chen start
- int bearchannel0;
- int bearchannel1;
-// 603221:tc.chen end
-}ChanType;
-
-typedef struct mib_previous_read{
- u16 ATUC_PERF_ESS;
- u16 ATUR_PERF_ESS;
- u32 ATUR_CHAN_RECV_BLK;
- u16 ATUR_CHAN_CORR_BLK_INTL;
- u16 ATUR_CHAN_CORR_BLK_FAST;
- u16 ATUR_CHAN_UNCORR_BLK_INTL;
- u16 ATUR_CHAN_UNCORR_BLK_FAST;
- u16 ATUC_PERF_STAT_FASTR;
- u16 ATUC_PERF_STAT_FAILED_FASTR;
- u16 ATUC_PERF_STAT_SESL;
- u16 ATUC_PERF_STAT_UASL;
- u16 ATUR_PERF_STAT_SESL;
-}mib_previous_read;
-
-typedef struct mib_flags_pretime{
- struct timeval ATUC_PERF_LOSS_PTIME;
- struct timeval ATUC_PERF_LOFS_PTIME;
- struct timeval ATUR_PERF_LOSS_PTIME;
- struct timeval ATUR_PERF_LOFS_PTIME;
- struct timeval ATUR_PERF_LPR_PTIME;
-}mib_flags_pretime;
-
- // cmv message structures
-#define MP_PAYLOAD_SIZE 12
-typedef struct mpmessage{
- u16 iFunction;
- u16 iGroup;
- u16 iAddress;
- u16 iIndex;
- u16 iPayload[MP_PAYLOAD_SIZE];
-}MPMessage;
-#endif
-
-
-typedef struct meireg{
- u32 iAddress;
- u32 iData;
-}meireg;
-
-#define MEIDEBUG_BUFFER_SIZES 50
-typedef struct meidebug{
- u32 iAddress;
- u32 iCount;
- u32 buffer[MEIDEBUG_BUFFER_SIZES];
-}meidebug;
-
-//==============================================================================
-// Group definitions
-//==============================================================================
-#define OPTN 5
-#define CNFG 8
-#define CNTL 1
-#define STAT 2
-#define RATE 6
-#define PLAM 7
-#define INFO 3
-#define TEST 4
-//==============================================================================
-// Opcode definitions
-//==============================================================================
-#define H2D_CMV_READ 0x00
-#define H2D_CMV_WRITE 0x04
-#define H2D_CMV_INDICATE_REPLY 0x10
-#define H2D_ERROR_OPCODE_UNKNOWN 0x20
-#define H2D_ERROR_CMV_UNKNOWN 0x30
-
-#define D2H_CMV_READ_REPLY 0x01
-#define D2H_CMV_WRITE_REPLY 0x05
-#define D2H_CMV_INDICATE 0x11
-#define D2H_ERROR_OPCODE_UNKNOWN 0x21
-#define D2H_ERROR_CMV_UNKNOWN 0x31
-#define D2H_ERROR_CMV_READ_NOT_AVAILABLE 0x41
-#define D2H_ERROR_CMV_WRITE_ONLY 0x51
-#define D2H_ERROR_CMV_READ_ONLY 0x61
-
-#define H2D_DEBUG_READ_DM 0x02
-#define H2D_DEBUG_READ_PM 0x06
-#define H2D_DEBUG_WRITE_DM 0x0a
-#define H2D_DEBUG_WRITE_PM 0x0e
-
-#define D2H_DEBUG_READ_DM_REPLY 0x03
-#define D2H_DEBUG_READ_FM_REPLY 0x07
-#define D2H_DEBUG_WRITE_DM_REPLY 0x0b
-#define D2H_DEBUG_WRITE_FM_REPLY 0x0f
-#define D2H_ERROR_ADDR_UNKNOWN 0x33
-
-#define D2H_AUTONOMOUS_MODEM_READY_MSG 0xf1
-//==============================================================================
-// INFO register address field definitions
-//==============================================================================
-
-#define INFO_TxState 0
-#define INFO_RxState 1
-#define INFO_TxNextState 2
-#define INFO_RxNextState 3
-#define INFO_TxStateJumpFrom 4
-#define INFO_RxStateJumpFrom 5
-
-#define INFO_ReverbSnrBuf 8
-#define INFO_ReverbEchoSnrBuf 9
-#define INFO_MedleySnrBuf 10
-#define INFO_RxShowtimeSnrBuf 11
-#define INFO_DECdelay 12
-#define INFO_DECExponent 13
-#define INFO_DECTaps 14
-#define INFO_AECdelay 15
-#define INFO_AECExponent 16
-#define INFO_AECTaps 17
-#define INFO_TDQExponent 18
-#define INFO_TDQTaps 19
-#define INFO_FDQExponent 20
-#define INFO_FDQTaps 21
-#define INFO_USBat 22
-#define INFO_DSBat 23
-#define INFO_USFineGains 24
-#define INFO_DSFineGains 25
-#define INFO_BitloadFirstChannel 26
-#define INFO_BitloadLastChannel 27
-#define INFO_PollEOCData 28 // CO specific
-#define INFO_CSNRMargin 29 // CO specific
-#define INFO_RCMsgs1 30
-#define INFO_RMsgs1 31
-#define INFO_RMsgRA 32
-#define INFO_RCMsgRA 33
-#define INFO_RMsg2 34
-#define INFO_RCMsg2 35
-#define INFO_BitLoadOK 36
-#define INFO_RCRates1 37
-#define INFO_RRates1Tab 38
-#define INFO_RMsgs1Tab 39
-#define INFO_RMsgRATab 40
-#define INFO_RRatesRA 41
-#define INFO_RCRatesRA 42
-#define INFO_RRates2 43
-#define INFO_RCRates2 44
-#define INFO_PackedRMsg2 45
-#define INFO_RxBitSwapFlag 46
-#define INFO_TxBitSwapFlag 47
-#define INFO_ShowtimeSNRUpdateCount 48
-#define INFO_ShowtimeFDQUpdateCount 49
-#define INFO_ShowtimeDECUpdateCount 50
-#define INFO_CopyRxBuffer 51
-#define INFO_RxToneBuf 52
-#define INFO_TxToneBuf 53
-#define INFO_Version 54
-#define INFO_TimeStamp 55
-#define INFO_feVendorID 56
-#define INFO_feSerialNum 57
-#define INFO_feVersionNum 58
-#define INFO_BulkMemory 59 //Points to start of bulk memory
-#define INFO_neVendorID 60
-#define INFO_neVersionNum 61
-#define INFO_neSerialNum 62
-
-//==============================================================================
-// RATE register address field definitions
-//==============================================================================
-
-
-#define RATE_UsRate 0
-#define RATE_DsRate 1
-
-
-//==============================================================================
-// PLAM (Physical Layer Management) register address field definitions
-// (See G997.1 for reference)
-//==============================================================================
-
-
- // ///
- // Failure Flags ///
- // ///
-
-#define PLAM_NearEndFailureFlags 0
-#define PLAM_FarEndFailureFlags 1
-
- // ///
- // Near End Failure Flags Bit Definitions ///
- // ///
-
-// ADSL Failures ///
-#define PLAM_LOS_FailureBit 0x0001
-#define PLAM_LOF_FailureBit 0x0002
-#define PLAM_LPR_FailureBit 0x0004
-#define PLAM_RFI_FailureBit 0x0008
-
-// ATM Failures ///
-#define PLAM_NCD_LP0_FailureBit 0x0010
-#define PLAM_NCD_LP1_FailureBit 0x0020
-#define PLAM_LCD_LP0_FailureBit 0x0040
-#define PLAM_LCD_LP1_FailureBit 0x0080
-
-#define PLAM_NCD_BC0_FailureBit 0x0100
-#define PLAM_NCD_BC1_FailureBit 0x0200
-#define PLAM_LCD_BC0_FailureBit 0x0400
-#define PLAM_LCD_BC1_FailureBit 0x0800
- // ///
- // Performance Counts ///
- // ///
-
-#define PLAM_NearEndCrcCnt 2
-#define PLAM_CorrectedRSErrors 3
-
-#define PLAM_NearEndECSCnt 6
-#define PLAM_NearEndESCnt 7
-#define PLAM_NearEndSESCnt 8
-#define PLAM_NearEndLOSSCnt 9
-#define PLAM_NearEndUASLCnt 10
-
-#define PLAM_NearEndHECErrCnt 11
-
-#define PLAM_NearEndHECTotCnt 16
-#define PLAM_NearEndCellTotCnt 18
-#define PLAM_NearEndSfCntLSW 20
-#define PLAM_NearEndSfCntMSW 21
-
-#define PLAM_FarEndFebeCnt 24
-
-#define PLAM_FarEndFecCnt 28
-
-#define PLAM_FarEndFECSCnt 32
-#define PLAM_FarEndESCnt 33
-#define PLAM_FarEndSESCnt 34
-#define PLAM_FarEndLOSSCnt 35
-#define PLAM_FarEndUASLCnt 36
-
-#define PLAM_FarEndHECErrCnt 37
-
-#define PLAM_FarEndHECTotCnt 41
-
-#define PLAM_FarEndCellTotCnt 43
-
-#define PLAM_LineAttn 45
-#define PLAM_SNRMargin 46
-
-
-//==============================================================================
-// CNTL register address and bit field definitions
-//==============================================================================
-
-
-#define CNTL_ModemControl 0
-
-#define CNTL_ModemReset 0x0
-#define CNTL_ModemStart 0x2
-
-
-//==============================================================================
-// STAT register address and bit field definitions
-//==============================================================================
-
-#define STAT_MacroState 0
-#define STAT_Mode 1
-#define STAT_DMTFramingMode 2
-#define STAT_SleepState 3
-#define STAT_Misc 4
-#define STAT_FailureState 5
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- // STAT_OLRStatus provides status of OLR
- //16-bit STAT_OLRStatus_DS
- // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
- // [3:2]: Reserved
- // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA)
- // [7:6]: Reserved
- // [10:8]: >0=Request. 0=not. For DS, # of request transmissions/retransmissions (3 bits).
- // [11]: 1=Receive Response, 0=not
- // [15:12]: Reserved
- //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- ///
-#define STAT_OLRStatus_DS 6
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- // STAT_OLRStatus provides status of OLR
- // 16-bit STAT_OLRStatus_US CMV
- // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
- // [3:2]: Reserved
- // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA)
- // [7:6]: Reserved
- // [8]: 1=Request Received. 0=not.
- // [10:9]: Reserved
- // [11]: 1=Response Sent, 0=not
- // [15:12]: Reserved
- //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-///
-#define STAT_OLRStatus_US 7
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- // STAT_PMStatus provides status of PM
- // 16-bit STAT_PMStatus CMV
- // [1:0] : PM Status 00=IDLE, 01=PM_IN_PROGRESS, 10=PM_Completed, 11=PM_Aborted
- // [2] : 0=ATU_R initiated PM; 1 = ATU_C initiated PM
- // [3]: Reserved
- // [5:4]: PM_Type (1:Simple Request; 2: L2 request; 3: L2 trim)
- // [7:6]: Reserved
- // [10:8]: >0=Request. 0=not. # of request transmissions/retransmissions (3 bits).
- // [11]: 1=Response, 0=not
- // [15:12]: Reserved
- //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- ///
-#define STAT_PMStatus 8
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- // 16-bit STAT_OLRError_DS, STAT_OLRError_US, STAT_PMError
- // [3:0]: OLR/PM response reason code
- // [7:4]: OLR/PM Internal error code
- // [15:8]: OLR/PM Reserved for future
- //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- ///
-#define STAT_OLRError_DS 9
-#define STAT_OLRError_US 10
-#define STAT_PMError 11
-
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// STAT_MacroState
-// MacroState reflects the high level state of the modem
-
-#define STAT_InitState 0x0000
-#define STAT_ReadyState 0x0001
-#define STAT_FailState 0x0002
-#define STAT_IdleState 0x0003
-#define STAT_QuietState 0x0004
-#define STAT_GhsState 0x0005
-#define STAT_FullInitState 0x0006
-#define STAT_ShowTimeState 0x0007
-#define STAT_FastRetrainState 0x0008
-#define STAT_LoopDiagMode 0x0009
-#define STAT_ShortInit 0x000A // Bis short initialization ///
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// STAT_Mode
-// ConfigurationMode indicates the mode of the current ADSL Link. In general, a modem may use
-// G.Hs or some other mechanism to negotiate the specific mode of operation.
-// The OPTN_modeControl CMV is used to select a set of desired modes.
-// The STAT_Mode CMV indicates which mode was actually selected.
-
-#define STAT_ConfigMode_T1413 0x0001
-#define STAT_ConfigMode_G992_2_AB 0x0002
-#define STAT_ConfigMode_G992_1_A 0x0004
-#define STAT_ConfigMode_G992_1_B 0x0008
-#define STAT_ConfigMode_G992_1_C 0x0010
-#define STAT_ConfigMode_G992_2_C 0x0020
-
-#define STAT_ConfigMode_G992_3_A 0x0100
-#define STAT_ConfigMode_G992_3_B 0x0200
-#define STAT_ConfigMode_G992_3_I 0x0400
-#define STAT_ConfigMode_G992_3_J 0x0800
-#define STAT_ConfigMode_G992_3_L 0x1000
-
-#define STAT_ConfigMode_G992_4_A 0x2000
-#define STAT_ConfigMode_G992_4_I 0x4000
-
-#define STAT_ConfigMode_G992_5 0x8000
-
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// STAT_DMTFramingMode
-// FramingMode indicates the DMT framing mde negotiated during initialization. The framing mode
-// status is not applicable in BIS mode and its value is undefined
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define STAT_FramingModeMask 0x0003
-
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// STAT_Misc
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define STAT_OverlappedSpectrum 0x0008
-#define STAT_TCM 0x0010
-#define STAT_TDQ_at_1104 0x0020
-#define STAT_T1413_Signal_Detected 0x0040
-#define STAT_AnnexL_US_Mask1_PSD 0x1000 //indicate we actually selected G992.3 AnnexL US PSD mask1
-#define STAT_AnnexL_US_Mask2_PSD 0x2000 //indicate we actually selected G992.3 AnnexL US PSD mask2
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// STAT_FailureState
-// when the MacroSTate indicates the fail state, FailureState provides a failure code
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-#define E_CODE_NO_ERROR 0
-#define E_CODE_BAT_TX 1 // TX BAT table is incorrect */
-#define E_CODE_BAT_RX 2 // RX BAT table is incorrect */
-#define E_CODE_PROFILE 3 // profile is not selected in fast retrain */
-#define E_CODE_TX_AOC_FIFO_OVERFLOW 4
-#define E_CODE_TRUNCATE_FR 5 //Fast Retrain truncated due to no stored profiles*/
-#define E_CODE_BITLOAD 6 // bit loading fails */
-#define E_CODE_ST_ERROR 7 // showtime CRC error */
-#define E_CODE_RESERVED 8 // using parameters reserved by the ITU-T */
-#define E_CODE_C_TONES 9 // detected C_TONES */
-#define E_CODE_CODESWAP_ERR 10 // codeswap not finished in time */
-#define E_CODE_FIFO_OVERFLOW 11 // we have run out of fifo space */
-#define E_CODE_C_BG_DECODE_ERR 12 // error in decoding C-BG message */
-#define E_CODE_C_RATES2_DECODE_ERR 13 // error in decoding C-MSGS2 and C-RATES2 */
-#define E_CODE_RCMedleyRx_C_SEGUE2_Failure 14 // Timeout after RCMedleyRx waiting for C_SEGUE2 */
-#define E_CODE_RReverbRATx_C_SEGUE2_Failure 15 // Timeout after RReverbRATx waiting for C_SEGUE2 */
-#define E_CODE_RReverb3Tx_C_SEGUE1_Failure 16 // Timeout after RReverb3Tx waiting for C_SEGUE1 */
-#define E_CODE_RCCRC2Rx_C_RATES1_DECOD_ERR 17 // Received CRC not equal to computed CRC */
-#define E_CODE_RCCRC1Rx_C_RATES1_DECOD_ERR 18 // Received CRC not equal to computed CRC */
-#define E_CODE_RReverb5Tx_C_SEGUE2_Failure 19 // Timeout after RReverb5Tx waiting for C_SEGUE2 */
-#define E_CODE_RReverb6Tx_C_SEGUE3_Failure 20 // Timeout after RReverb6Tx waiting for C_SEGUE3 */
-#define E_CODE_RSegue5Tx_C_SEGUE3_Failure 21 // Timeout after RSegue5Tx waiting for C_SEGUE3 */
-#define E_CODE_RCReverb5Rx_C_SEGUE_Failure 22 // Timeout after RCReverb5Rx waiting for C_SEGUE */
-#define E_CODE_RCReverbRARx_C_SEGUE2_Failure 23 // Timeout after RCReverbRARx waiting for C_SEGUE2 */
-#define E_CODE_RCCRC4Rx_CMSGS2_DECOD_ERR 24 // Received CRC not equal to computed CRC */
-#define E_CODE_RCCRC5Rx_C_BG_DECOD_ERR 25 // Received CRC not equal to computed CRC */
-#define E_CODE_RCCRC3Rx_DECOD_ERR 26 // Received CRC not equal to computed CRC */
-#define E_CODE_RCPilot3_DEC_PATH_DEL_TIMEOUT 27 // DEC Path Delay timeout */
-#define E_CODE_RCPilot3_DEC_TRAINING_TIMEOUT 28 // DEC Training timeout */
-#define E_CODE_RCReverb3Rx_C_SEGUE1_Failure 29 // Timeout after RCReverb3Rx waiting for C_SEGUE1 */
-#define E_CODE_RCReverb2Rx_SignalEnd_Failure 30 // Timeout waiting for the end of RCReverb2Rx signal */
-#define E_CODE_RQuiet2_SignalEnd_Failure 31 // Timeout waiting for the end of RQuiet2 signal */
-#define E_CODE_RCReverbFR1Rx_Failure 32 // Timeout waiting for the end of RCReverbFR1Rx signal */
-#define E_CODE_RCPilotFR1Rx_SignalEnd_Failure 33 // Timeout waiting for the end of RCPilotFR1Rx signal */
-#define E_CODE_RCReverbFR2Rx_C_Segue_Failure 34 // Timeout after RCReverbFR2Rx waiting for C_SEGUE */
-#define E_CODE_RCReverbFR5Rx_SignalEnd_TIMEOUT 35 // Timeout waiting for the end of RCReverbFR5Rx signal */
-#define E_CODE_RCReverbFR6Rx_C_SEGUE_Failure 36 // Timeout after RCReverbFR6Rx waiting for C_SEGUE */
-#define E_CODE_RCReverbFR8Rx_C_SEGUE_FR4_Failure 37 // Timeout after RCReverbFR8Rx waiting for C_SEGUE_FR4 */
-#define E_CODE_RCReverbFR8Rx_No_PROFILE 38 // Timeout since no profile was selected */
-#define E_CODE_RCReverbFR8Rx_SignalEnd_TIMEOUT 39 // Timeout waiting for the end of RCReverbFR8Rx signal */
-#define E_CODE_RCCRCFR1_DECOD_ERR 40 // Received CRC not equal to computed CRC */
-#define E_CODE_RCRecovRx_SingnalEnd_TIMEOUT 41 // Timeout waiting for the end of RCRecovRx signal */
-#define E_CODE_RSegueFR5Tx_TX_Not_Ready_TIMEOUT 42 // Timeout after RSegueFR5Tx waiting for C_SEGUE2 */
-#define E_CODE_RRecovTx_SignalEnd_TIMEOUT 43 // Timeout waiting for the end of RRecovTx signal */
-#define E_CODE_RCMedleyFRRx_C_SEGUE2_Failure 44 // Timeout after RCMedleyFRRx waiting for C_SEGUE2 */
-#define E_CODE_CONFIGURATION_PARAMETERS_ERROR 45 // one of the configuration parameters do not meet the standard */
-#define E_CODE_BAD_MEM_ACCESS 46
-#define E_CODE_BAD_INSTRUCTION_ACCESS 47
-#define E_CODE_TX_EOC_FIFO_OVERFLOW 48
-#define E_CODE_RX_EOC_FIFO_OVERFLOW 49
-#define E_CODE_GHS_CD_FLAG_TIME_OUT 50 // Timeout when transmitting Flag in handshake cleardown */
-
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//STAT_OLRStatus:
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define STAT_OLRPM_IDLE 0x0000
-#define STAT_OLRPM_IN_PROGRESS 0x0001
-#define STAT_OLRPM_COMPLETE 0x0002
-#define STAT_OLRPM_ABORTED 0x0003
-#define STAT_OLRPM_RESPONSE 0x0800
-
-#define STAT_OLR_BITSWAP 0x0010
-#define STAT_OLR_DRR 0x0020
-#define STAT_OLR_SRA 0x0030
-
-//STAT_PMStatus_US:
-#define STAT_PM_CO_REQ 0x0004
-#define STAT_PM_SIMPLE_REQ 0x0010
-#define STAT_PM_L2_REQ 0x0020
-#define STAT_PM_L2_TRIM_REQ 0x0030
-
-// STAT_OLRError_DS, STAT_OLRError_US
-//4 bit response reason code:
-#define RESP_BUSY 0x01
-#define RESP_INVALID_PARAMETERS 0x02
-#define RESP_NOT_ENABLED 0x03
-#define RESP_NOT_SUPPORTED 0x04
-
-//4 bit internal error code (common for OLR and PM)
-#define REQ_INVALID_BiGi 0x10
-#define REQ_INVALID_Lp 0x20
-#define REQ_INVALID_Bpn 0x30
-#define REQ_INVALID_FRAMING_CONSTRAINT 0x40
-#define REQ_NOT_IN_L0_STATE 0x50
-#define REQ_NOT_IN_L2_STATE 0x60
-#define REQ_INVALID_PCB 0x70
-#define REQ_VIOLATES_MARGIN 0x80
-
-//STAT_PMError
-//4 bit response reason code:
-#define RESP_STATE_NOT_DESIRED 0x03
-#define RESP_INFEASIBLE_PARAMETERS 0x04
-
-
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// OPTN register address and bit field definitions
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define OPTN_ModeControl 0
-#define OPTN_DMTLnkCtl 1
-// Reserved 2
-#define OPTN_GhsControl 3
-// Reserved 4
-#define OPTN_PwrManControl 5
-#define OPTN_AnnexControl 6
-#define OPTN_ModeControl1 7
-// Reserved 8
-#define OPTN_StateMachineCtrl 9
-// Reserved 10
-// Reserved 11
-#define OPTN_BisLinkControl 12
-#define OPTN_ATMAddrConfig 13
-#define OPTN_ATMNumCellConfig 14
-
-// Mode control defines the allowable operating modes of an ADSL link. In general, a modem may ///
-// use G.Hs or some other mechanism to negotiate the specific mode of operation. ///
-// The OPTN_ModeControl CMV is used to select a set of desired modes ///
-// The STAT_ModeControl CMV indicates which mode was actually selected ///
-
-// OPTN_ModeControl
-#define OPTN_ConfigMode_T1413 0x0001
-#define OPTN_ConfigMode_G992_2_AB 0x0002
-#define OPTN_ConfigMode_G992_1_A 0x0004
-#define OPTN_ConfigMode_G992_1_B 0x0008
-#define OPTN_ConfigMode_G992_1_C 0x0010
-#define OPTN_ConfigMode_G992_2_C 0x0020
-
-#define OPTN_ConfigMode_G992_3_A 0x0100
-#define OPTN_ConfigMode_G992_3_B 0x0200
-#define OPTN_ConfigMode_G992_3_I 0x0400
-#define OPTN_ConfigMode_G992_3_J 0x0800
-#define OPTN_ConfigMode_G992_3_L 0x1000
-
-#define OPTN_ConfigMode_G992_4_A 0x2000
-#define OPTN_ConfigMode_G992_4_I 0x4000
-
-#define OPTN_ConfigMode_G992_5 0x8000
-
-// OPTN_PwrManControl
-#define OPTN_PwrManWakeUpGhs 0x1
-#define OPTN_PwrManWakeUpFR 0x2
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// OPTN_DMT Link Control
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define OPTN_DMT_DualLatency_Dis 0x200
-#define OPTN_DMT_S_Dis 0x100
-#define OPTN_DMT_FRAMINGMODE 0x1
-#define OPTN_DMT_FRAMINGMODE_MASK 0x7
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// OPTN_BIS Link Control
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define OPTN_BisLinkContrl_LineProbeDis 0x1
-#define OPTN_BisLinkContrl_DSBlackBitsEn 0x2
-#define OPTN_BisLinkContrl_DiagnosticModeEn 0x4
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// OPTN_GhsControl
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//
-// for OPTN_GhsControl, we will assign 16bit word as follows
-// bit 0~3: set the control over which start(initial) message CPE will send:
-//
-// BIT: 2 1 0
-// 0 0 1 CLR
-// 0 1 0 MR
-// 0 1 1 MS
-// 1 0 0 MP
-//
-// // bit 4~6: set the control over which message will be sent when we get at lease one CL/CLR exchange
-// BIT: 5 4
-// 0 1 MS
-// 1 0 MR
-// 1 1 MP
-//
-// // bit 15: RT initiated G.hs sample sessions one through eight. Session one is default.
-// BIT: 15
-// 1 means session one
-//
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define OPTN_GHS_ST_GHS 0x8000
-#define OPTN_GHS_INIT_MASK 0x000F
-#define OPTN_GHS_RESP_MASK 0x00F0
-
-#define OPTN_RTInitTxMsg_CLR 0x0001
-#define OPTN_RTInitTxMsg_MR 0x0002
-#define OPTN_RTInitTxMsg_MS 0x0003
-#define OPTN_RTInitTxMsg_MP 0x0004
-
-#define OPTN_RTRespTxMsg_MS 0x0010
-#define OPTN_RTRespTxMsg_MR 0x0020
-#define OPTN_RTRespTxMsg_MP 0x0030
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// OPTN_AnnexControl
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-// G.992.3 Annex A/L1/L2 US PSD Mask preferred
-
-#define OPTN_G992_3_AnnexA_PreferredModeMask 0x3000
-#define OPTN_G992_3_AnnexA_PreferredModeA 0x0000 // default AnnexA PSD mask ///
-#define OPTN_G992_3_AnnexA_PreferredModeL1 0x1000 // AnnexL wide spectrum upstream PSD mask ///
-#define OPTN_G992_3_AnnexA_PreferredModeL2 0x2000 // AnnexL narrow spectrum upstream PSD mask ///
-
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//OPTN_ATMAddrConfig
-// Bits 4:0 are Utopia address for BC1
-// Bits 9:5 are Utopia address for BC0
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define OPTN_UTPADDR_BC1 0x001F
-#define OPTN_UTPADDR_BC0 0x03E0
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//OPTN_ATMNumCellConfig
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define OPTN_BC1_NUM_CELL_PAGES 0x000F // Bits 0:3 ///
-#define OPTN_BC0_NUM_CELL_PAGES 0x00F0 // Bits 4:7 ///
-
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// CNFG register address field ///
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-///////////////////////////////////////////
-// these cmvs are used by bis handshake ///
-///////////////////////////////////////////
-
-// Each of the CNFG_TPS entries points to a structure of type (TPS_TC_BearerChannel_t)
-#define CNFG_TPS_TC_DS0 0
-#define CNFG_TPS_TC_DS1 1
-#define CNFG_TPS_TC_US0 2
-#define CNFG_TPS_TC_US1 3
-
-#define CNFG_HDLC_Overhead_Requirements 4
-
-// Each of the CNFG_PMS entries points to a structure of type (PMS_TC_LatencyPath_t)
-#define CNFG_PMS_TC_DS0 5
-#define CNFG_PMS_TC_DS1 6
-#define CNFG_PMS_TC_US0 7
-#define CNFG_PMS_TC_US1 8
-
-// CNFG_PMD_PARAMETERS points to a structure of type (PMD_params_t)
-#define CNFG_PMD_PARAMETERS 9
-
-////////////////////////////////////////////////////////////
-// these cmvs are used by bis training and showtime code ///
-////////////////////////////////////////////////////////////
-
-////////////////
-// Tx Config ///
-////////////////
-#define CNFG_tx_Cnfg_Nbc 10
-#define CNFG_tx_Cnfg_Nlp 11
-#define CNFG_tx_Cnfg_Rp 12
-#define CNFG_tx_Cnfg_Mp 13
-#define CNFG_tx_Cnfg_Lp 14
-#define CNFG_tx_Cnfg_Tp 15
-#define CNFG_tx_Cnfg_Dp 16
-#define CNFG_tx_Cnfg_Bpn 17
-#define CNFG_tx_Cnfg_FramingMode 18
-#define CNFG_tx_Cnfg_MSGLp 19
-#define CNFG_tx_Cnfg_MSGc 20
-
-
-////////////////
-// Rx Config ///
-////////////////
-#define CNFG_rx_Cnfg_Nbc 21
-#define CNFG_rx_Cnfg_Nlp 22
-#define CNFG_rx_Cnfg_Rp 23
-#define CNFG_rx_Cnfg_Mp 24
-#define CNFG_rx_Cnfg_Lp 25
-#define CNFG_rx_Cnfg_Tp 26
-#define CNFG_rx_Cnfg_Dp 27
-#define CNFG_rx_Cnfg_Bpn 28
-#define CNFG_rx_Cnfg_FramingMode 29
-#define CNFG_rx_Cnfg_MSGLp 30
-#define CNFG_rx_Cnfg_MSGc 31
-
-#define CNFG_tx_Cnfg_BCnToLPp 32
-#define CNFG_rx_Cnfg_BCnToLPp 33
-
-
-
-#endif
-
+++ /dev/null
-#ifndef AMAZON_SW_H
-#define AMAZON_SW_H
-#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE
-#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1
-#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2
-#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3
-#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4
-#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5
-#define SET_ETH_REG SIOCDEVPRIVATE+6
-#define VLAN_TOOLS SIOCDEVPRIVATE+7
-#define MAC_TABLE_TOOLS SIOCDEVPRIVATE+8
-
-
-/*===mac table commands==*/
-#define RESET_MAC_TABLE 0
-#define READ_MAC_ENTRY 1
-#define WRITE_MAC_ENTRY 2
-#define ADD_MAC_ENTRY 3
-
-/*====vlan commands===*/
-
-#define CHANGE_VLAN_CTRL 0
-#define READ_VLAN_ENTRY 1
-#define UPDATE_VLAN_ENTRY 2
-#define CLEAR_VLAN_ENTRY 3
-#define RESET_VLAN_TABLE 4
-#define ADD_VLAN_ENTRY 5
-
-/*
-** MDIO constants.
-*/
-
-#define MDIO_BASE_STATUS_REG 0x1
-#define MDIO_BASE_CONTROL_REG 0x0
-#define MDIO_PHY_ID_HIGH_REG 0x2
-#define MDIO_PHY_ID_LOW_REG 0x3
-#define MDIO_BC_NEGOTIATE 0x0200
-#define MDIO_BC_FULL_DUPLEX_MASK 0x0100
-#define MDIO_BC_AUTO_NEG_MASK 0x1000
-#define MDIO_BC_SPEED_SELECT_MASK 0x2000
-#define MDIO_STATUS_100_FD 0x4000
-#define MDIO_STATUS_100_HD 0x2000
-#define MDIO_STATUS_10_FD 0x1000
-#define MDIO_STATUS_10_HD 0x0800
-#define MDIO_STATUS_SPEED_DUPLEX_MASK 0x7800
-#define MDIO_ADVERTISMENT_REG 0x4
-#define MDIO_ADVERT_100_FD 0x100
-#define MDIO_ADVERT_100_HD 0x080
-#define MDIO_ADVERT_10_FD 0x040
-#define MDIO_ADVERT_10_HD 0x020
-#define MDIO_LINK_UP_MASK 0x4
-#define MDIO_START 0x1
-#define MDIO_READ 0x2
-#define MDIO_WRITE 0x1
-#define MDIO_PREAMBLE 0xfffffffful
-
-#define PHY_RESET 0x8000
-#define AUTO_NEGOTIATION_ENABLE 0X1000
-#define AUTO_NEGOTIATION_COMPLETE 0x20
-#define RESTART_AUTO_NEGOTIATION 0X200
-
-
-#define PHY0_ADDR 0
-#define PHY1_ADDR 1
-#define P1M 0
-
-#define AMAZON_SW_REG32(reg_num) *((volatile u32*)(reg_num))
-
-#define OK 0;
-
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-typedef struct mac_table_entry{
- u64 mac_address:48;
- u64 p0:1;
- u64 p1:1;
- u64 p2:1;
- u64 cr:1;
- u64 ma_st:3;
- u64 res:9;
-}_mac_table_entry;
-
-typedef struct IFX_Switch_VLanTableEntry{
- u32 vlan_id:12;
- u32 mp0:1;
- u32 mp1:1;
- u32 mp2:1;
- u32 v:1;
- u32 res:16;
-}_IFX_Switch_VLanTableEntry;
-
-typedef struct mac_table_req{
- int cmd;
- int index;
- u32 data;
- u64 entry_value;
-}_mac_table_req;
-
-#else //not CONFIG_CPU_LITTLE_ENDIAN
-typedef struct mac_table_entry{
- u64 mac_address:48;
- u64 p0:1;
- u64 p1:1;
- u64 p2:1;
- u64 cr:1;
- u64 ma_st:3;
- u64 res:9;
-}_mac_table_entry;
-
-typedef struct IFX_Switch_VLanTableEntry{
- u32 vlan_id:12;
- u32 mp0:1;
- u32 mp1:1;
- u32 mp2:1;
- u32 v:1;
- u32 res:16;
-}_IFX_Switch_VLanTableEntry;
-
-
-typedef struct mac_table_req{
- int cmd;
- int index;
- u32 data;
- u64 entry_value;
-}_mac_table_req;
-
-#endif //CONFIG_CPU_LITTLE_ENDIAN
-
-
-
-typedef struct vlan_req{
- int cmd;
- int index;
- u32 data;
- u32 entry_value;
-}_vlan_req;
-
-typedef struct data_req{
- int index;
- u32 value;
-}_data_req;
-
-enum duplex
-{
- half,
- full,
- autoneg
-};
-
-struct switch_priv {
- struct net_device_stats stats;
- int rx_packetlen;
- u8 *rx_packetdata;
- int rx_status;
- int tx_packetlen;
-#ifdef CONFIG_NET_HW_FLOWCONTROL
- int fc_bit;
-#endif //CONFIG_NET_HW_FLOWCONTROL
- u8 *tx_packetdata;
- int tx_status;
- struct dma_device_info *dma_device;
- struct sk_buff *skb;
- spinlock_t lock;
- int mdio_phy_addr;
- int current_speed;
- int current_speed_selection;
- int rx_queue_len;
- int full_duplex;
- enum duplex current_duplex;
- int num;
-};
-
-#endif //AMAZON_SW_H
-
-
-
-
-
+++ /dev/null
-#ifndef AMAZON_TPE_H
-#define AMAZON_TPE_H
-#include <linux/atm.h>
-#include <linux/atmdev.h>
-#include <linux/netdevice.h>
-#include <linux/ioctl.h>
-
-#ifdef CONFIG_IFX_ATM_MIB
-/* For ATM-MIB lists */
-#include <linux/list.h>
-#endif
-#include <asm/amazon/atm_mib.h>
-
-/* CBM Queue arranagement
- * Q0: free cells pool
- * Q1~ Q15: upstream queues
- * Q16: QAM downstream
- * Q17~Q31: downstream queues
- */
-#define AMAZON_ATM_MAX_QUEUE_NUM 32
-#define AMAZON_ATM_PORT_NUM 2
-#define AMAZON_ATM_FREE_CELLS 4000
-#define AMAZON_ATM_MAX_VCC_NUM (AMAZON_ATM_MAX_QUEUE_NUM/2 - 1)
-#define AMAZON_AAL0_SDU (ATM_AAL0_SDU+4) //one more word for status
-#define CBM_RX_OFFSET 16 //offset from the same q for tx
-#define AMAZON_ATM_OAM_Q_ID 16
-#define AMAZON_ATM_RM_Q_ID 16
-#define AMAZON_ATM_OTHER_Q_ID 16
-#define CBM_DEFAULT_Q_OFFSET 1
-#define HTUTIMEOUT 0xffff//timeoutofhtutocbm
-#define QSB_WFQ_NONUBR_MAX 0x3f00
-#define QSB_WFQ_UBR_BYPASS 0x3fff
-#define QSB_TP_TS_MAX 65472
-#define QSB_TAUS_MAX 64512
-#define QSB_GCR_MIN 18
-#define HTU_RAM_ACCESS_MAX 1024//maxium time for HTU RAM access
-
-#define SWIE_LOCK 1
-#define PROC_ATM 1
-#define PROC_MIB 2
-#define PROC_VCC 3
-#define PROC_AAL5 4
-#define PROC_CBM 5
-#define PROC_HTU 6
-#define PROC_QSB 7
-#define PROC_SWIE 8
-
-/***************** internal data structure ********************/
-typedef int (*push_back_t)(struct atm_vcc *vcc,struct sk_buff *skb,int err) ;
-/* Device private data */
-typedef struct{
- u8 padding_byte;
- u32 tx_max_sdu;
- u32 rx_max_sdu;
- u32 cnt_cpy; //no. of packets that need a copy due to alignment
-}amazon_aal5_dev_t;
-
-typedef struct{
- u32 max_q_off; //maxium queues used in real scenario
- u32 nrt_thr;
- u32 clp0_thr;
- u32 clp1_thr;
- u32 free_cell_cnt;
-#ifdef CONFIG_USE_VENUS
- u8 * qd_addr_free; //to work around a bug, bit15 of QDOFF address should be 1
-#endif
- u8 * qd_addr;
- u8 * mem_addr;
- u8 allocated;
-}amazon_cbm_dev_t;
-
-typedef struct{
-
-}amazon_htu_dev_t;
-
-typedef struct{
- u32 tau; //cell delay variation due to concurrency(?)
- u32 tstepc; //time step, all legal values are 1,2,4
- u32 sbl; //scheduler burse length (for PHY)
-}amazon_qsb_dev_t;
-
-typedef struct{
- u32 qid; //QID of the current extraction queue
- struct semaphore in_sem; // Software-Insertion semaphore
- volatile long lock; //lock that avoids race contions between SWIN and SWEX
- wait_queue_head_t sleep; //wait queue for SWIE and SWEX
- u32 sw; //status word
-}amazon_swie_dev_t;
-
-//AAL5 MIB Counter
-typedef struct{
- u32 tx,rx; //number AAL5 CPCS PDU from/to higher-layer
- u32 tx_err,rx_err; //ifInErrors and ifOutErros
- u32 tx_drop,rx_drop; //discarded received packets due to mm shortage
- u32 htu_unp; //number of unknown received cells
- u32 rx_cnt_h; //number of octets received, high 32 bits
- u32 rx_cnt_l; //number of octets received, low 32 bits
- u32 tx_cnt_h; //number of octets transmitted, high 32 bits
- u32 tx_cnt_l; //number of octets transmitted, low 32 bits
- u32 tx_ppd; //number of cells for AAL5 upstream PPD discards
- u64 rx_cells; //number of cells for downstream
- u64 tx_cells; //number of cells for upstream
- u32 rx_err_cells; //number of cells dropped due to uncorrectable HEC errors
-}amazon_mib_counter_t;
-
-
-
-typedef enum {QS_PKT,QS_LEN,QS_ERR,QS_HW_DROP,QS_SW_DROP,QS_MAX} qs_t;
-//queue statics no. of packet received / sent
-//queue statics no. of bytes received / sent
-//queue statics no. of packets with error
-//queue statics no. of packets dropped by hw
-//queue statics no. of packets dropped by sw
-
-typedef struct{
- push_back_t push; //call back function
- struct atm_vcc * vcc; //opened vcc
- struct timeval access_time; //time when last F4/F5 user cells arrive
- int free; //whether this queue is occupied, 0: occupied, 1: free
- u32 aal5VccCrcErrors; //MIB counter
- u32 aal5VccOverSizedSDUs; //MIB counter
-
-#if defined(AMAZON_ATM_DEBUG) || defined (CONFIG_IFX_ATM_MIB)
- u32 qs[QS_MAX];
-#endif
-}amazon_atm_queue_t;
-
-
-typedef struct{
- int enable; //enable / disable
- u32 max_conn; //maximum number of connections per port
- u32 tx_max_cr; //Remaining cellrate for this device for tx direction
- u32 tx_rem_cr; //Remaining cellrate for this device for tx direction
- u32 tx_cur_cr; //Current cellrate for this device for tx direction
-}amazon_atm_port_t;
-
-typedef struct{
- amazon_aal5_dev_t aal5;
- amazon_cbm_dev_t cbm;
- amazon_htu_dev_t htu;
- amazon_qsb_dev_t qsb;
- amazon_swie_dev_t swie;
- amazon_mib_counter_t mib_counter;
- amazon_atm_queue_t queues[AMAZON_ATM_MAX_QUEUE_NUM];
- amazon_atm_port_t ports[AMAZON_ATM_PORT_NUM];
- atomic_t dma_tx_free_0;//TX_CH0 has availabe descriptors
-} amazon_atm_dev_t;
-
-struct oam_last_activity{
- u8 vpi; //vpi for this connection
- u16 vci; //vci for t his connection
- struct timeval stamp; //time when last F4/F5 user cells arrive
- struct oam_last_activity * next;//for link list purpose
-};
-
-typedef union{
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
- struct{
- u32 tprs :16;
- u32 twfq :14;
- u32 vbr :1;
- u32 reserved :1;
- }bit;
- u32 w0;
-#else
- struct{
- u32 reserved :1;
- u32 vbr :1;
- u32 twfq :14;
- u32 tprs :16;
- }bit;
- u32 w0;
-#endif
-
-}qsb_qptl_t;
-
-typedef union{
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
- struct{
- u32 ts :16;
- u32 taus :16;
- }bit;
- u32 w0;
-#else
- struct{
- u32 taus :16;
- u32 ts :16;
- }bit;
- u32 w0;
-#endif
-}qsb_qvpt_t;
-
-
-
-struct amazon_atm_cell_header {
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
- struct{
- u32 clp :1; // Cell Loss Priority
- u32 pti :3; // Payload Type Identifier
- u32 vci :16; // Virtual Channel Identifier
- u32 vpi :8; // Vitual Path Identifier
- u32 gfc :4; // Generic Flow Control
- }bit;
-#else
- struct{
- u32 gfc :4; // Generic Flow Control
- u32 vpi :8; // Vitual Path Identifier
- u32 vci :16; // Virtual Channel Identifier
- u32 pti :3; // Payload Type Identifier
- u32 clp :1; // Cell Loss Priority
- }bit;
-#endif
-};
-
-
-/************************ Function Declarations **************************/
-amazon_atm_dev_t * amazon_atm_create(void);
-int amazon_atm_open(struct atm_vcc *vcc,push_back_t);
-int amazon_atm_send(struct atm_vcc *vcc,struct sk_buff *skb);
-int amazon_atm_send_oam(struct atm_vcc *vcc,void *cell, int flags);
-void amazon_atm_close(struct atm_vcc *vcc);
-void amazon_atm_cleanup(void);
-const struct oam_last_activity* get_oam_time_stamp(void);
-
-//mib-related
-int amazon_atm_cell_mib(atm_cell_ifEntry_t * to,u32 itf);
-int amazon_atm_aal5_mib(atm_aal5_ifEntry_t * to);
-int amazon_atm_vcc_mib(struct atm_vcc *vcc,atm_aal5_vcc_t * to);
-int amazon_atm_vcc_mib_x(int vpi, int vci,atm_aal5_vcc_t* to);
-
-#define AMAZON_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data); wmb();} while (0)
-#define AMAZON_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
-/******************************* ioctl stuff****************************************/
-#define NUM(dev) (MINOR(dev) & 0xf)
-/*
- * Ioctl definitions
- */
-/* Use 'o' as magic number */
-#define AMAZON_ATM_IOC_MAGIC 'o'
-/* MIB_CELL: get atm cell level mib counter
- * MIB_AAL5: get aal5 mib counter
- * MIB_VCC: get vcc mib counter
- */
-typedef struct{
- int vpi;
- int vci;
- atm_aal5_vcc_t mib_vcc;
-}atm_aal5_vcc_x_t;
-#define AMAZON_ATM_MIB_CELL _IOWR(AMAZON_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
-#define AMAZON_ATM_MIB_AAL5 _IOWR(AMAZON_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
-#define AMAZON_ATM_MIB_VCC _IOWR(AMAZON_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
-#define AMAZON_ATM_IOC_MAXNR 3
-
-//sockopt
-#define SO_AMAZON_ATM_MIB_VCC __SO_ENCODE(SOL_ATM,5,atm_aal5_vcc_t)
-
-#endif // AMAZON_TPE_H
-
+++ /dev/null
-#ifndef AMAZON_WDT_H
-#define AMAZON_WDT_H
-#ifdef __KERNEL__
-typedef struct wdt_dev{
- char name[16];
- int major;
- int minor;
-
- int full;
- char buff[10];
-}wdt_dev;
-#define AMAZON_WDT_REG32(addr) (*((volatile u32*)(addr)))
-#endif //__KERNEL__
-
-//AMAZON_WDT_IOC_START: start the WDT timer (must provide a initial timeout value)
-//AMAZON_WDT_IOC_STOP: stop the WDT
-//AMAZON_WDT_IOC_PING: reload the timer to initial value (must happend after a AMAZON_WDT_IOC_START)
-#define AMAZON_WDT_IOC_MAGIC 0xc0
-#define AMAZON_WDT_IOC_START _IOW( AMAZON_WDT_IOC_MAGIC,0, int)
-#define AMAZON_WDT_IOC_STOP _IO( AMAZON_WDT_IOC_MAGIC,1)
-#define AMAZON_WDT_IOC_PING _IO( AMAZON_WDT_IOC_MAGIC,2)
-
-#endif //AMAZON_WDT_H
+++ /dev/null
-#ifndef ATM_DEFINES_H
-#define ATM_DEFINES_H
-
-//Registers Base Address
-#define IO_BASE_ADDR 0xA0000000
-#define AAL5_BASE_ADDRESS 0x10104400+IO_BASE_ADDR
-#define CBM_BASE_ADDRESS 0x10104000+IO_BASE_ADDR
-#define HTU_BASE_ADDRESS 0x10105100+IO_BASE_ADDR
-#define QSB_BASE_ADDRESS 0x10105000+IO_BASE_ADDR
-#define SWIE_BASE_ADDRESS 0x10105200+IO_BASE_ADDR
-
-//AAL5 Registers
-#define AAL5_SISR0_ADDR AAL5_BASE_ADDRESS+0x20
-#define AAL5_SIMR0_ADDR AAL5_BASE_ADDRESS+0x24
-#define AAL5_SISR1_ADDR AAL5_BASE_ADDRESS+0x28
-#define AAL5_SIMR1_ADDR AAL5_BASE_ADDRESS+0x2C
-#define AAL5_SMFL_ADDR AAL5_BASE_ADDRESS+0x30
-#define AAL5_SATMHD_ADDR AAL5_BASE_ADDRESS+0x34
-#define AAL5_SCON_ADDR AAL5_BASE_ADDRESS+0x38
-#define AAL5_SCMD_ADDR AAL5_BASE_ADDRESS+0x3C
-#define AAL5_RISR0_ADDR AAL5_BASE_ADDRESS+0x40
-#define AAL5_RIMR0_ADDR AAL5_BASE_ADDRESS+0x44
-#define AAL5_RISR1_ADDR AAL5_BASE_ADDRESS+0x48
-#define AAL5_RIMR1_ADDR AAL5_BASE_ADDRESS+0x4C
-#define AAL5_RMFL_ADDR AAL5_BASE_ADDRESS+0x50
-#define AAL5_RINTINF0_ADDR AAL5_BASE_ADDRESS+0x54
-#define AAL5_RINTINF1_ADDR AAL5_BASE_ADDRESS+0x58
-#define AAL5_RES5C_ADDR AAL5_BASE_ADDRESS+0x5C
-#define AAL5_RIOL_ADDR AAL5_BASE_ADDRESS+0x60
-#define AAL5_RIOM_ADDR AAL5_BASE_ADDRESS+0x64
-#define AAL5_SOOL_ADDR AAL5_BASE_ADDRESS+0x68
-#define AAL5_SOOM_ADDR AAL5_BASE_ADDRESS+0x6C
-#define AAL5_RES70_ADDR AAL5_BASE_ADDRESS+0x70
-#define AAL5_RES74_ADDR AAL5_BASE_ADDRESS+0x74
-#define AAL5_RES78_ADDR AAL5_BASE_ADDRESS+0x78
-#define AAL5_RES7C_ADDR AAL5_BASE_ADDRESS+0x7C
-#define AAL5_RES80_ADDR AAL5_BASE_ADDRESS+0x80
-#define AAL5_RES84_ADDR AAL5_BASE_ADDRESS+0x84
-#define AAL5_RES88_ADDR AAL5_BASE_ADDRESS+0x88
-#define AAL5_RES8C_ADDR AAL5_BASE_ADDRESS+0x8C
-#define AAL5_RES90_ADDR AAL5_BASE_ADDRESS+0x90
-#define AAL5_RES94_ADDR AAL5_BASE_ADDRESS+0x94
-#define AAL5_RES98_ADDR AAL5_BASE_ADDRESS+0x98
-#define AAL5_RES9C_ADDR AAL5_BASE_ADDRESS+0x9C
-#define AAL5_RESA0_ADDR AAL5_BASE_ADDRESS+0xA0
-#define AAL5_RESA4_ADDR AAL5_BASE_ADDRESS+0xA4
-#define AAL5_RESA8_ADDR AAL5_BASE_ADDRESS+0xA8
-#define AAL5_RESAC_ADDR AAL5_BASE_ADDRESS+0xAC
-#define AAL5_RESB0_ADDR AAL5_BASE_ADDRESS+0xB0
-#define AAL5_RESB4_ADDR AAL5_BASE_ADDRESS+0xB4
-#define AAL5_RESB8_ADDR AAL5_BASE_ADDRESS+0xB8
-#define AAL5_RESBC_ADDR AAL5_BASE_ADDRESS+0xBC
-#define AAL5_RESC0_ADDR AAL5_BASE_ADDRESS+0xC0
-#define AAL5_RESC4_ADDR AAL5_BASE_ADDRESS+0xC4
-#define AAL5_RESC8_ADDR AAL5_BASE_ADDRESS+0xC8
-#define AAL5_RESCC_ADDR AAL5_BASE_ADDRESS+0xCC
-#define AAL5_RESD0_ADDR AAL5_BASE_ADDRESS+0xD0
-#define AAL5_RESD4_ADDR AAL5_BASE_ADDRESS+0xD4
-#define AAL5_RESD8_ADDR AAL5_BASE_ADDRESS+0xD8
-#define AAL5_RESDC_ADDR AAL5_BASE_ADDRESS+0xDC
-#define AAL5_RESE0_ADDR AAL5_BASE_ADDRESS+0xE0
-#define AAL5_RESE4_ADDR AAL5_BASE_ADDRESS+0xE4
-#define AAL5_RESE8_ADDR AAL5_BASE_ADDRESS+0xE8
-#define AAL5_RESEC_ADDR AAL5_BASE_ADDRESS+0xEC
-#define AAL5_SSRC0_ADDR AAL5_BASE_ADDRESS+0xF0
-#define AAL5_SSRC1_ADDR AAL5_BASE_ADDRESS+0xF4
-#define AAL5_RSRC0_ADDR AAL5_BASE_ADDRESS+0xF8
-#define AAL5_RSRC1_ADDR AAL5_BASE_ADDRESS+0xFC
-
-#define AAL5S_ISR_QID_MASK 0xFF000000
-#define AAL5S_ISR_SAB 0x00000100
-#define AAL5S_ISR_SE 0x00000080
-#define AAL5S_ISR_MFLE 0x00000040
-#define AAL5S_ISR_SBE0 0x00000020
-#define AAL5S_ISR_SEG0 0x00000010
-#define AAL5S_ISR_TAB 0x00000004
-
-#define AAL5_SIMR_MASK 0x000001c7
-#define AAL5_SIMR_SAB 0x00000100
-#define AAL5_SIMR_SE 0x00000080
-#define AAL5_SIMR_MFLE 0x00000040
-#define AAL5_SIMR_TAB 0x00000004
-#define AAL5_SIMR_SBE0 0x00000002
-#define AAL5_SIMR_SEG0 0x00000001
-
-#define AAL5_SCMD_SEQCOUNT_MASK 0x0000ff00
-#define AAL5_SCMD_MODE_POLL 0x00000008
-#define AAL5_SCMD_MODE_COUNT 0x00000000
-#define AAL5_SCMD_AS 0x00000004
-#define AAL5_SCMD_SS 0x00000002
-#define AAL5_SCMD_AR 0x00000001
-
-#define AAL5R_ISR_CID_MASK 0xFF000000//ConnectionID
-#define AAL5R_ISR_DBC_MASK 0x00FF0000//DiscardedByteCounter
-#define AAL5R_ISR_END 0x00002000//End
-#define AAL5R_ISR_ICID 0x00001000//InvalidConnectionID
-#define AAL5R_ISR_CLP 0x00000800//CellLossPriority
-#define AAL5R_ISR_CGST 0x00000400//Congestion
-#define AAL5R_ISR_UUE 0x00000200//CPCSUUError
-#define AAL5R_ISR_CPIE 0x00000100//CPIError
-#define AAL5R_ISR_FE 0x00000080//FrameEnd
-#define AAL5R_ISR_MFLE 0x00000040//MaximumFrameLengthExceeded
-#define AAL5R_ISR_DBCE 0x00000020//DiscardedByteCounterExceeded
-#define AAL5R_ISR_CRC 0x00000010//CRCError
-#define AAL5R_ISR_ILEN 0x00000008//InvalidLength
-#define AAL5R_ISR_RAB 0x00000004//ReceiveAbort
-
-#define AAL5_RIMR1_MASK 0x00003ffc
-#define AAL5_RIMR1_END 0x00002000//End
-#define AAL5_RIMR1_ICID 0x00001000//InvalidConnectionID
-#define AAL5_RIMR1_CLP 0x00000800//CellLossPriority
-#define AAL5_RIMR1_CGST 0x00000400//Congestion
-#define AAL5_RIMR1_UUE 0x00000200//CPCSUUError
-#define AAL5_RIMR1_CPIE 0x00000100//CPIError
-#define AAL5_RIMR1_FE 0x00000080//FrameEnd
-#define AAL5_RIMR1_MFLE 0x00000040//MaximumFrameLengthExceeded
-#define AAL5_RIMR1_DBCE 0x00000020//DiscardedByteCounterExceeded
-#define AAL5_RIMR1_CRC 0x00000010//CRCError
-#define AAL5_RIMR1_ILEN 0x00000008//InvalidLength
-#define AAL5_RIMR1_RAB 0x00000004//ReceiveAbort
-
-//AAL5 Reassambly Errors
-#define AAL5_STW1_MASK 0x33//Error mask
-#define AAL5_STW0_MASK 0x5c//Error mask
-#define AAL5_STW0_BE 0x3//padding bytes mask
-#define AAL5_STW1_CBM 0x20//Transfer from CBM to A5R abnormally ended
-#define AAL5_STW1_CH 0x10//Invalid Channel number error
-#define AAL5_STW1_CLP 0x8//CLP value of cells in packet is 1
-#define AAL5_STW1_CG 0x4//Cell in packet expired congestion
-#define AAL5_STW1_UU 0x2//CPCS-UU value error
-#define AAL5_STW1_CPI 0x1//CPI value error
-#define AAL5_STW0_FE 0x80//Frame end
-#define AAL5_STW0_MFL 0x40//Maximum frame length error
-#define AAL5_STW0_CRC 0x10//CRC error
-#define AAL5_STW0_IL 0x8//Invalid length
-#define AAL5_STW0_RA 0x4//Received abort
-
-
-
-//CBM Registers
-#define CBM_NRTTHR_ADDR CBM_BASE_ADDRESS+0x10//NonRealTimeThreshold
-#define CBM_CLP0THR_ADDR CBM_BASE_ADDRESS+0x14//CLP0Threshold
-#define CBM_CLP1THR_ADDR CBM_BASE_ADDRESS+0x18//CLP1Threshold
-#define CBM_QDOFF_ADDR CBM_BASE_ADDRESS+0x1C//QueueDescriptorOffset
-#define CBM_CFG_ADDR CBM_BASE_ADDRESS+0x20//Configuration
-#define CBM_HWEXPAR0_ADDR CBM_BASE_ADDRESS+0x24//HWExtractParameter0
-#define CBM_RES28_ADDR CBM_BASE_ADDRESS+0x28
-#define CBM_WMSTAT0_ADDR CBM_BASE_ADDRESS+0x2C
-#define CBM_HWEXCMD_ADDR CBM_BASE_ADDRESS+0x30//HWExtractCommand0
-#define CBM_RES34_ADDR CBM_BASE_ADDRESS+0x34
-#define CBM_HWEXSTAT0_ADDR CBM_BASE_ADDRESS+0x38//HWExtractStatus0
-#define CBM_RES3C_ADDR CBM_BASE_ADDRESS+0x3C
-#define CBM_RES40_ADDR CBM_BASE_ADDRESS+0x40
-#define CBM_CNT_ADDR CBM_BASE_ADDRESS+0x44//CellCount
-#define CBM_RES48_ADDR CBM_BASE_ADDRESS+0x48
-#define CBM_LFR_ADDR CBM_BASE_ADDRESS+0x4C//PointertolastCellinfreeCellQueue
-#define CBM_FFR_ADDR CBM_BASE_ADDRESS+0x50//PointertofirstCellinfreeCellQueue
-#define CBM_RES54_ADDR CBM_BASE_ADDRESS+0x54
-#define CBM_RES58_ADDR CBM_BASE_ADDRESS+0x58
-#define CBM_RES5C_ADDR CBM_BASE_ADDRESS+0x5C
-#define CBM_RES60_ADDR CBM_BASE_ADDRESS+0x60
-#define CBM_RES64_ADDR CBM_BASE_ADDRESS+0x64
-#define CBM_RES68_ADDR CBM_BASE_ADDRESS+0x68
-#define CBM_RES6C_ADDR CBM_BASE_ADDRESS+0x6C
-#define CBM_RES70_ADDR CBM_BASE_ADDRESS+0x70
-#define CBM_RES74_ADDR CBM_BASE_ADDRESS+0x74
-#define CBM_RES78_ADDR CBM_BASE_ADDRESS+0x78
-#define CBM_RES7C_ADDR CBM_BASE_ADDRESS+0x7C
-#define CBM_RES80_ADDR CBM_BASE_ADDRESS+0x80
-#define CBM_RES84_ADDR CBM_BASE_ADDRESS+0x84
-#define CBM_RES88_ADDR CBM_BASE_ADDRESS+0x88
-#define CBM_RES8C_ADDR CBM_BASE_ADDRESS+0x8C
-#define CBM_RES90_ADDR CBM_BASE_ADDRESS+0x90
-#define CBM_RES94_ADDR CBM_BASE_ADDRESS+0x94
-#define CBM_RES98_ADDR CBM_BASE_ADDRESS+0x98
-#define CBM_RES9C_ADDR CBM_BASE_ADDRESS+0x9C
-#define CBM_RESA0_ADDR CBM_BASE_ADDRESS+0xA0
-#define CBM_RESA4_ADDR CBM_BASE_ADDRESS+0xA4
-#define CBM_RESA8_ADDR CBM_BASE_ADDRESS+0xA8
-#define CBM_RESAC_ADDR CBM_BASE_ADDRESS+0xAC
-#define CBM_RESB0_ADDR CBM_BASE_ADDRESS+0xB0
-#define CBM_RESB4_ADDR CBM_BASE_ADDRESS+0xB4
-#define CBM_RESB8_ADDR CBM_BASE_ADDRESS+0xB8
-#define CBM_RESBC_ADDR CBM_BASE_ADDRESS+0xBC
-#define CBM_INTINF0_ADDR CBM_BASE_ADDRESS+0xC0//InterruptInfo0
-#define CBM_INTCMD_ADDR CBM_BASE_ADDRESS+0xC4//InterruptCommand0
-#define CBM_IMR0_ADDR CBM_BASE_ADDRESS+0xC8//InterruptMask
-#define CBM_SRC0_ADDR CBM_BASE_ADDRESS+0xCC//ServiceRequestControl
-#define CBM_RESD0_ADDR CBM_BASE_ADDRESS+0xD0
-#define CBM_RESD4_ADDR CBM_BASE_ADDRESS+0xD4
-#define CBM_RESD8_ADDR CBM_BASE_ADDRESS+0xD8
-#define CBM_RESDC_ADDR CBM_BASE_ADDRESS+0xDC
-#define CBM_RESE0_ADDR CBM_BASE_ADDRESS+0xE0
-#define CBM_AAL5IDIS_ADDR CBM_BASE_ADDRESS+0xE4//MIB-No.EPDdiscardedpacketsupstream
-#define CBM_AAL5ODIS_ADDR CBM_BASE_ADDRESS+0xE8//MIB-No.PPDdiscardedpacketsupstream
-#define CBM_RESEC_ADDR CBM_BASE_ADDRESS+0xEC
-#define CBM_RESF0_ADDR CBM_BASE_ADDRESS+0xF0
-#define CBM_RESF4_ADDR CBM_BASE_ADDRESS+0xF4
-#define CBM_RESF8_ADDR CBM_BASE_ADDRESS+0xF8
-#define CBM_RESFC_ADDR CBM_BASE_ADDRESS+0xFC
-
-//CBMCFG
-#define CBM_CFG_INTLCK0EN 0x00000008
-#define CBM_CFG_INT0HLT 0x00000004
-#define CBM_CFG_START 0x00000001
-
-#define CBM_HWEXPAR_PN_A5 0x00002000
-#define CBM_HWEXPAR_PN_CM 0x00000000
-#define CBM_HWEXPAR_SUBADD_PORTMASK 0x00000070
-#define CBM_HWEXPAR_SUBADD_ADU 0x00000000
-#define CBM_HWEXPAR_SUBADD_AAL2 0x00000080
-#define CBM_HWEXPAR_SUBADD_SWIE 0x00000100
-
-#define CBM_HWEXCMD_SFE2 0x00000100
-#define CBM_HWEXCMD_FE2 0x00000080
-#define CBM_HWEXCMD_SCE2 0x00000040
-#define CBM_HWEXCMD_SFE1 0x00000020
-#define CBM_HWEXCMD_FE1 0x00000010
-#define CBM_HWEXCMD_SCE1 0x00000008
-#define CBM_HWEXCMD_SFE0 0x00000004
-#define CBM_HWEXCMD_FE0 0x00000002
-#define CBM_HWEXCMD_SCE0 0x00000001
-
-#define CBM_INTINF0_QID_MASK 0xFF000000
-#define CBM_INTINF0_ORIGIN_MASK 0x00F00000
-#define CBM_INTINF0_EF 0x00004000
-#define CBM_INTINF0_ACA 0x00002000
-#define CBM_INTINF0_ERR 0x00001000
-#define CBM_INTINF0_DISC 0x00000800
-#define CBM_INTINF0_QSBV 0x00000400
-#define CBM_INTINF0_Q0E 0x00000200
-#define CBM_INTINF0_Q0I 0x00000100
-#define CBM_INTINF0_RDE 0x00000080
-#define CBM_INTINF0_OPF 0x00000040
-#define CBM_INTINF0_NFCA 0x00000020
-#define CBM_INTINF0_CLP1TR 0x00000010
-#define CBM_INTINF0_CLP0TR 0x00000008
-#define CBM_INTINF0_NRTTR 0x00000004
-#define CBM_INTINF0_QFD 0x00000002
-#define CBM_INTINF0_QTR 0x00000001
-#define CBM_INTINF0_QID_SHIFT 24
-//CBM QD Word 3
-#define CBM_QD_W3_QOS_0 0x00000000
-#define CBM_QD_W3_QOS_1 0x40000000
-#define CBM_QD_W3_QOS_2 0x80000000
-#define CBM_QD_W3_QOS_3 0xc0000000
-
-#define CBM_QD_W3_DIR_UP 0x20000000
-#define CBM_QD_W3_DIR_DOWN 0x00000000
-
-#define CBM_QD_W3_CLPt 0x10000000
-#define CBM_QD_W3_RT 0x08000000
-#define CBM_QD_W3_AAL5 0x04000000
-
-#define CBM_QD_W3_INT_NOINT 0x00000000
-#define CBM_QD_W3_INT_ACA 0x01000000
-#define CBM_QD_W3_INT_EOF 0x02000000
-#define CBM_QD_W3_INT_BOTH 0x03000000
-
-#define CBM_QD_W3_THRESHOLD_MASK 0x00ff0000
-#define CBM_QD_W3_WM_EN 0x00000010
-#define CBM_QD_W3_HCR 0x00000008
-#define CBM_QD_W3_SBID_MASK 0x00000001
-
-#define CBM_QD_W3_THRESHOLD_SHIFT 16
-
-//WATER MARK STATUS
-#define CBM_WM_NRT_MASK 0x00040000
-#define CBM_WM_CLP0_MASK 0x00020000
-#define CBM_WM_CLP1_MASK 0x00010000
-
-//CBMNRTTHR, CBMCLP0THR, CBMCLP0THR
-#define CBM_NRT_WM_NONE 0x00000000//no water mark
-#define CBM_WM_3_1 0x00010000//3/4 to set, 1/4 to release
-#define CBM_WM_3_2 0x00020000//3/4 to set, 2/4 to release
-#define CBM_WM_2_1 0x00030000//2/4 to set, 1/4 to release
-#define CBM_THR_MASK 0x0000FFFF
-
-#define CBM_IMR_MASK 0x0000fbff
-#define CBM_IMR_reserved 0xFFFF0400
-#define CBM_IMR_RFULL 0x00008000//EndofFrame
-#define CBM_IMR_EF 0x00004000//EndofFrame
-#define CBM_IMR_ACA 0x00002000//AnyCellArrived
-#define CBM_IMR_ERR 0x00001000//FPI Error
-#define CBM_IMR_DISC 0x00000800//Discard
-#define CBM_IMR_reserved1 0x00000400//reserved
-#define CBM_IMR_Q0E 0x00000200//Queue0Extract
-#define CBM_IMR_Q0I 0x00000100//Queue0Insert
-#define CBM_IMR_RDE 0x00000080//ReadEmptyQueue
-#define CBM_IMR_OPF 0x00000040//OncePerFrame
-#define CBM_IMR_NFCA 0x00000020//NoFreeCellAvailable
-#define CBM_IMR_CLP1TR 0x00000010//CLP1ThresholdReached
-#define CBM_IMR_CLP0TR 0x00000008//CLP0ThresholdReached
-#define CBM_IMR_NRTTR 0x00000004//NonRealTimeThresholdReached
-#define CBM_IMR_QFD 0x00000002//QueueFrameDiscard
-#define CBM_IMR_QTR 0x00000001//QueueThresholdReached
-
-#define CBM_EXSTAT_FB 0x00000010
-#define CBM_EXSTAT_SCB 0x00000008
-#define CBM_EXSTAT_Q0 0x00000004
-#define CBM_EXSTAT_RDE 0x00000002
-#define CBM_EXSTAT_QV 0x00000001
-
-//HTU Registers
-#define HTU_RX0_ADDR HTU_BASE_ADDRESS+0x10
-#define HTU_RX1_ADDR HTU_BASE_ADDRESS+0x14
-#define HTU_RES18_ADDR HTU_BASE_ADDRESS+0x18
-#define HTU_RES1C_ADDR HTU_BASE_ADDRESS+0x1C
-#define HTU_RES20_ADDR HTU_BASE_ADDRESS+0x20
-#define HTU_RES24_ADDR HTU_BASE_ADDRESS+0x24
-#define HTU_RES28_ADDR HTU_BASE_ADDRESS+0x28
-#define HTU_RES2C_ADDR HTU_BASE_ADDRESS+0x2C
-#define HTU_PCF0PAT_ADDR HTU_BASE_ADDRESS+0x30
-#define HTU_PCF1PAT_ADDR HTU_BASE_ADDRESS+0x34
-#define HTU_RES38_ADDR HTU_BASE_ADDRESS+0x38
-#define HTU_RES3C_ADDR HTU_BASE_ADDRESS+0x3C
-#define HTU_RES40_ADDR HTU_BASE_ADDRESS+0x40
-#define HTU_RES44_ADDR HTU_BASE_ADDRESS+0x44
-#define HTU_RES48_ADDR HTU_BASE_ADDRESS+0x48
-#define HTU_RES4C_ADDR HTU_BASE_ADDRESS+0x4C
-#define HTU_PCF0MASK_ADDR HTU_BASE_ADDRESS+0x50
-#define HTU_PCF1MASK_ADDR HTU_BASE_ADDRESS+0x54
-#define HTU_RES58_ADDR HTU_BASE_ADDRESS+0x58
-#define HTU_RES5C_ADDR HTU_BASE_ADDRESS+0x5C
-#define HTU_RES60_ADDR HTU_BASE_ADDRESS+0x60
-#define HTU_RES64_ADDR HTU_BASE_ADDRESS+0x64
-#define HTU_RES68_ADDR HTU_BASE_ADDRESS+0x68
-#define HTU_RES6C_ADDR HTU_BASE_ADDRESS+0x6C
-#define HTU_TIMEOUT_ADDR HTU_BASE_ADDRESS+0x70
-#define HTU_DESTOAM_ADDR HTU_BASE_ADDRESS+0x74
-#define HTU_DESTRM_ADDR HTU_BASE_ADDRESS+0x78
-#define HTU_DESTOTHER_ADDR HTU_BASE_ADDRESS+0x7C
-#define HTU_CFG_ADDR HTU_BASE_ADDRESS+0x80
-#define HTU_RES84_ADDR HTU_BASE_ADDRESS+0x84
-#define HTU_RES88_ADDR HTU_BASE_ADDRESS+0x88
-#define HTU_RES8C_ADDR HTU_BASE_ADDRESS+0x8C
-#define HTU_INFNOENTRY_ADDR HTU_BASE_ADDRESS+0x90
-#define HTU_INFTIMEOUT_ADDR HTU_BASE_ADDRESS+0x94
-#define HTU_RES98_STAT HTU_BASE_ADDRESS+0x98
-#define HTU_RES9C_ADDR HTU_BASE_ADDRESS+0x9C
-#define HTU_MIBCIUP HTU_BASE_ADDRESS+0xA0//MIB Counter In Unknown Protoc Register
-#define HTU_CNTTIMEOUT_ADDR HTU_BASE_ADDRESS+0xA4
-#define HTU_RESA8_ADDR HTU_BASE_ADDRESS+0xA8
-#define HTU_RESAC_ADDR HTU_BASE_ADDRESS+0xAC
-#define HTU_RAMADDR_ADDR HTU_BASE_ADDRESS+0xB0
-#define HTU_RAMCMD_ADDR HTU_BASE_ADDRESS+0xB4
-#define HTU_RAMSTAT_ADDR HTU_BASE_ADDRESS+0xB8
-#define HTU_RESBC_ADDR HTU_BASE_ADDRESS+0xBC
-#define HTU_RAMDAT1_ADDR HTU_BASE_ADDRESS+0xC0
-#define HTU_RAMDAT2_ADDR HTU_BASE_ADDRESS+0xC4
-#define HTU_RESCC_ADDR HTU_BASE_ADDRESS+0xCC
-#define HTU_RESD0_ADDR HTU_BASE_ADDRESS+0xD0
-#define HTU_RESD4_ADDR HTU_BASE_ADDRESS+0xD4
-#define HTU_RESD8_ADDR HTU_BASE_ADDRESS+0xD8
-#define HTU_RESDC_ADDR HTU_BASE_ADDRESS+0xDC
-#define HTU_RESE0_ADDR HTU_BASE_ADDRESS+0xE0
-#define HTU_RESE4_ADDR HTU_BASE_ADDRESS+0xE4
-#define HTU_IMR0_ADDR HTU_BASE_ADDRESS+0xE8
-#define HTU_RESEC_ADDR HTU_BASE_ADDRESS+0xEC
-#define HTU_ISR0_ADDR HTU_BASE_ADDRESS+0xF0
-#define HTU_RESF4_ADDR HTU_BASE_ADDRESS+0xF4
-#define HTU_SRC0_ADDR HTU_BASE_ADDRESS+0xF8
-#define HTU_RESFC_ADDR HTU_BASE_ADDRESS+0xFC
-
-//HTU_CFG
-#define HTU_CFG_START 0x00000001
-
-#define HTU_RAMCMD_RMW 0x00000004
-#define HTU_RAMCMD_RD 0x00000002
-#define HTU_RAMCMD_WR 0x00000001
-
-#define HTU_RAMDAT1_VCON 0x00000080//validconnection
-#define HTU_RAMDAT1_VCT 0x00000040//vcivalueistransparent
-#define HTU_RAMDAT1_QIDS 0x00000020//qid selects a cell in cbm
-#define HTU_RAMDAT1_VCI3 0x00000010//vci3->oamqueue
-#define HTU_RAMDAT1_VCI4 0x00000008//vci4->oamqueue
-#define HTU_RAMDAT1_VCI6 0x00000004//vci6->rmqueue
-#define HTU_RAMDAT1_PTI4 0x00000002//pti4->oamqueue
-#define HTU_RAMDAT1_PTI5 0x00000001//pti5->oamqueue
-
-#define HTU_RAMDAT2_PTI6 0x00000800
-#define HTU_RAMDAT2_PTI7 0x00000400
-#define HTU_RAMDAT2_F4U 0x00000200
-#define HTU_RAMDAT2_F5U 0x00000100
-#define HTU_RAMDAT2_QID_MASK 0x000000ff
-
-#define HTU_ISR_NE 0x00000001
-#define HTU_ISR_TORD 0x00000002
-#define HTU_ISR_IT 0x00000008
-#define HTU_ISR_OTOC 0x00000010
-#define HTU_ISR_ONEC 0x00000020
-#define HTU_ISR_PNE 0x00000040
-#define HTU_ISR_PT 0x00000080
-#define HTU_ISR_MASK 0x000000ff
-
-
-//QSB Registers
-#define QSB_BIP0_ADDR QSB_BASE_ADDRESS+0x00
-#define QSB_BIP1_ADDR QSB_BASE_ADDRESS+0x04
-#define QSB_BIP2_ADDR QSB_BASE_ADDRESS+0x08
-#define QSB_BIP3_ADDR QSB_BASE_ADDRESS+0x0C
-#define QSB_RSVP_ADDR QSB_BASE_ADDRESS+0x10
-#define QSB_TNOW_ADDR QSB_BASE_ADDRESS+0x14
-#define QSB_TNOWCYC_ADDR QSB_BASE_ADDRESS+0x18
-#define QSB_TAU_ADDR QSB_BASE_ADDRESS+0x1C
-#define QSB_L1BRS_ADDR QSB_BASE_ADDRESS+0x20
-#define QSB_SBL_ADDR QSB_BASE_ADDRESS+0x24
-#define QSB_CONFIG_ADDR QSB_BASE_ADDRESS+0x28
-#define QSB_RTM_ADDR QSB_BASE_ADDRESS+0x2C
-#define QSB_RTD_ADDR QSB_BASE_ADDRESS+0x30
-#define QSB_RAMAC_ADDR QSB_BASE_ADDRESS+0x34
-#define QSB_ISR_ADDR QSB_BASE_ADDRESS+0x38
-#define QSB_IMR_ADDR QSB_BASE_ADDRESS+0x3C
-#define QSB_SRC_ADDR QSB_BASE_ADDRESS+0x40
-
-#define QSB_TABLESEL_QVPT 8
-#define QSB_TABLESEL_QPT 1
-#define QSB_TABLESEL_SCT 2
-#define QSB_TABLESEL_SPT 3
-#define QSB_TABLESEL_CALENDARWFQ 4/*notusedbyFW*/
-#define QSB_TABLESEL_L2WFQ 5/*notusedbyFW*/
-#define QSB_TABLESEL_CALENDARRS 6/*notusedbyFW*/
-#define QSB_TABLESEL_L2BITMAPRS 7/*notusedbyFW*/
-#define QSB_TABLESEL_SHIFT 24
-#define QSB_TWFQ_MASK 0x3FFF0000
-#define QSB_TPRS_MASK 0x0000FFFF
-#define QSB_SBID_MASK 0xF
-#define QSB_TWFQ_SHIFT 16
-#define QSB_SCDRATE_MASK 0x00007FFF
-#define QSB_SBVALID_MASK 0x80000000
-
-#define QSB_ISR_WFQLE 0x00000001
-#define QSB_ISR_WFQBE 0x00000002
-#define QSB_ISR_RSLE 0x00000004
-#define QSB_ISR_RSBE 0x00000008
-#define QSB_ISR_MUXOV 0x00000010
-#define QSB_ISR_CDVOV 0x00000020
-#define QSB_ISR_PARAMI 0x00000040
-#define QSB_ISR_SLOSS 0x00000080
-#define QSB_ISR_IIPS 0x00000100
-
-#define QSB_IMR_WFQLE 0x00000001
-#define QSB_IMR_WFQBE 0x00000002
-#define QSB_IMR_RSLE 0x00000004
-#define QSB_IMR_RSBE 0x00000008
-#define QSB_IMR_MUXOV 0x00000010
-#define QSB_IMR_CDVOV 0x00000020
-#define QSB_IMR_PARAMI 0x00000040
-#define QSB_IMR_SLOSS 0x00000080
-#define QSB_IMR_IIPS 0x00000100
-
-#define QSB_READ 0x0
-#define QSB_WRITE 0x80000000
-#define QSB_READ_ALL 0xFFFFFFFF
-
-#if 1 //some bug with QSB access mask
-#define QSB_QPT_SET_MASK 0x0
-#define QSB_QVPT_SET_MASK 0x0
-#define QSB_SET_SCT_MASK 0x0
-#define QSB_SET_SPT_MASK 0x0
-#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF
-#else //some bug with QSB access mask
-#define QSB_QPT_SET_MASK 0x80000000
-#define QSB_QVPT_SET_MASK 0x0
-#define QSB_SET_SCT_MASK 0xFFFFFFE0
-#define QSB_SET_SPT_MASK 0x7FF8C000
-#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF
-#endif //some bug with QSB access mask
-
-#define QSB_SPT_SBVALID 0x80000000
-
-#define QSB_RAMAC_REG_LOW 0x0
-#define QSB_RAMAC_REG_HIGH 0x00010000
-
-#define SRC_SRE_ENABLE 0x1000
-#define SRC_CLRR 0x4000 //request clear bit
-
-
-
-//SWIE Registers
-#define SWIE_IQID_ADDR SWIE_BASE_ADDRESS+0x0c//SWIEInsertQueueDescriptor
-#define SWIE_ICMD_ADDR SWIE_BASE_ADDRESS+0x10//SWIEInsertCommand
-#define SWIE_ISTAT_ADDR SWIE_BASE_ADDRESS+0x14//SWIEInsertStatus
-#define SWIE_ESTAT_ADDR SWIE_BASE_ADDRESS+0x18//SWIEExtractStatus
-#define SWIE_ISRC_ADDR SWIE_BASE_ADDRESS+0x74//SWIEInsertServiceRequestControl
-#define SWIE_ESRC_ADDR SWIE_BASE_ADDRESS+0x78//SWIEExtractServiceRequestControl
-#define SWIE_ICELL_ADDR SWIE_BASE_ADDRESS+0x80//SWIEInsertCell(0x80-0xb4)
-#define SWIE_ECELL_ADDR SWIE_BASE_ADDRESS+0xc0//SWIEExtractCell(0xc0-0xf4)
-
-#define SWIE_ISTAT_DONE 0x1
-#define SWIE_ESTAT_DONE 0x1
-#define SWIE_ICMD_START 0x00000001//Startcommandforinsertion
-#define SWIE_CBM_SCE0 CBM_HWEXCMD_SCE0//CBMcommandforSingle-Cell-Extract
-#define SWIE_CBM_PID_SUBADDR 0x00001000//CBMPortIDandSubAddressforUTOPIA
-
-//Extracted cell format
-//52bytes AAL0 PDU + "Input cell additional data"(14bits)
-#define SWIE_ADDITION_DATA_MASK 0x7fff
-#define SWIE_EPORT_MASK 0x7000//Source ID (000 AUB0, 001 AUB1)
-#define SWIE_EF4USER_MASK 0x800
-#define SWIE_EF5USER_MASK 0x400
-#define SWIE_EOAM_MASK 0x200
-#define SWIE_EAUU_MASK 0x100
-#define SWIE_EVCI3_MASK 0x80
-#define SWIE_EVCI4_MASK 0x40
-#define SWIE_EVCI6_MASK 0x20
-#define SWIE_EPTI4_MASK 0x10
-#define SWIE_EPTI5_MASK 0x8
-#define SWIE_EPTI6_MASK 0x4
-#define SWIE_EPTI7_MASK 0x2
-#define SWIE_ECRC10ERROR_MASK 0x1
-
-#define CBM_CELL_SIZE 0x40
-#define CBM_QD_SIZE 0x10
-#define AAL5R_TRAILER_LEN 12
-#define AAL5S_INBOUND_HEADER 8
-
-//constants
-//TODO: to be finalized by system guys
-//DMA QOS defined by ATM QoS Service type
-#define DMA_RX_CH0 0
-#define DMA_RX_CH1 1
-#define DMA_TX_CH0 0
-#define DMA_TX_CH1 1
-#define CBR_DMA_QOS CBM_QD_W3_QOS_0
-#define VBR_RT_DMA_QOS CBM_QD_W3_QOS_0
-#define VBR_NRT_DMA_QOS CBM_QD_W3_QOS_0
-#define UBR_PLUS_DMA_QOS CBM_QD_W3_QOS_0
-#define UBR_DMA_QOS CBM_QD_W3_QOS_0
-
-#define SRC_TOS_MIPS 0
-#define AAL5R_SRPN 0x00000006//a5rneedshigherprioritythanDR
-#define AAL5S_SRPN 0x00000005
-#define CBM_MIPS_SRPN 0x00000004
-#define QSB_SRPN 0x00000023
-#define HTU_SRPN1 0x00000022
-#define HTU_SRPN0 0x00000021
-
-#endif //ATM_DEFINES_H
-
+++ /dev/null
-#ifndef AMAZON_ATM_MIB_H
-#define AMAZON_ATM_MIB_H
-
-#ifdef CONFIG_IFX_ATM_MIB
-#include <asm/types.h>
-#ifdef __KERNEL__
-#include <linux/list.h>
-#endif
-#endif /* CONFIG_IFX_ATM_MIB */
-
-#ifndef __KERNEL__
-#include <atmMIB/local_list.h>
-typedef unsigned int __u32;
-#endif
-
-typedef struct{
- __u32 ifHCInOctets_h;
- __u32 ifHCInOctets_l;
- __u32 ifHCOutOctets_h;
- __u32 ifHCOutOctets_l;
- __u32 ifInErrors;
- __u32 ifInUnknownProtos;
- __u32 ifOutErrors;
-}atm_cell_ifEntry_t;
-
-typedef struct{
- __u32 ifHCInOctets_h;
- __u32 ifHCInOctets_l;
- __u32 ifHCOutOctets_h;
- __u32 ifHCOutOctets_l;
- __u32 ifInUcastPkts;
- __u32 ifOutUcastPkts;
- __u32 ifInErrors;
- __u32 ifInDiscards;
- __u32 ifOutErros;
- __u32 ifOutDiscards;
-}atm_aal5_ifEntry_t;
-
-typedef struct{
- __u32 aal5VccCrcErrors;
- __u32 aal5VccSarTimeOuts;//no timer support yet
- __u32 aal5VccOverSizedSDUs;
-}atm_aal5_vcc_t;
-
-#if defined(CONFIG_IFX_ATM_MIB) || defined(IFX_CONFIG_SNMP_ATM_MIB)
-/* ATM-MIB data structures */
-typedef struct atmIfConfEntry {
- int ifIndex;
- int atmInterfaceMaxVpcs;
- int atmInterfaceMaxVccs;
- int atmInterfaceConfVpcs;
- int atmInterfaceConfVccs;
- int atmInterfaceMaxActiveVpiBits;
- int atmInterfaceMaxActiveVciBits;
- int atmInterfaceIlmiVpi;
- int atmInterfaceIlmiVci;
- int atmInterfaceAddressType;
- char atmInterfaceAdminAddress[40];
- unsigned long atmInterfaceMyNeighborIpAddress;
- char atmInterfaceMyNeighborIfName[20];
- int atmInterfaceCurrentMaxVpiBits;
- int atmInterfaceCurrentMaxVciBits;
- char atmInterfaceSubscrAddress[40];
- int flags;
-}atmIfConfEntry;
-
-typedef struct atmTrafficDescParamEntry {
- /* Following three parameters are used to update VCC QoS values */
- int ifIndex;
- short atmVclvpi;
- int atmVclvci;
-
- unsigned int atmTrafficParamIndex;
- unsigned char traffic_class;
- int max_pcr;
- /* Subramani: Added min_pcr */
- int min_pcr;
- int cdv;
- int scr;
- int mbs;
- int atmTrafficRowStatus;
- int atmTrafficFrameDiscard;
- struct list_head vpivci_head;
- struct list_head list;
-}atmTrafficDescParamEntry;
-
-
-typedef struct atmVclEntry {
- int ifIndex;
- short atmVclvpi;
- int atmVclvci;
- char vpivci[20];
- int atmVclAdminStatus;
- int atmVclOperStatus;
- unsigned long atmVclLastChange;
- struct atmTrafficDescParamEntry *atmVclRxTrafficPtr;
- struct atmTrafficDescParamEntry *atmVclTxTrafficPtr;
- unsigned char atmVccAalType;
- unsigned int atmVccAal5TxSduSize;
- unsigned int atmVccAal5RxSduSize;
- int atmVccAal5Encap;
- int atmVclRowStatus;
- int atmVclCastType;
- int atmVclConnKind;
- struct list_head list;
- int flags;
-}atmVclEntry;
-
-
-typedef union union_atmptrs {
- struct atmIfConfEntry *atmIfConfEntry_ptr;
- struct atmTrafficDescParamEntry *atmTrafficDescParamEntry_ptr;
- struct atmVclEntry *atmVclEntry_ptr;
-}union_atmptrs;
-
-/* ATM Character device major number */
-#define ATM_MEI_MAJOR 107
-
-/* Protocol Constants */
-#define IFX_PROTO_RAW 0
-#define IFX_PROTO_BR2684 1
-#define IFX_PROTO_PPPOATM 2
-#define IFX_PROTO_CLIP 3
-
-/* IOCTL Command Set for ATM-MIB */
-#define GET_ATM_IF_CONF_DATA 0x0AB0
-#define SET_ATM_IF_CONF_DATA 0x0AB1
-
-#define SET_ATM_QOS_DATA 0x0BC0
-
-#define GET_ATM_VCL_DATA 0x0CD0
-#define SET_ATM_VCL_DATA 0x0CD1
-
-#define FIND_VCC_IN_KERNEL 0x0DE0
-
-/* User defined flags for VCL Table */
-#define ATMVCCAAL5CPCSTRANSMITSDUSIZE 9
-#define ATMVCCAAL5CPCSRECEIVESDUSIZE 10
-
-#endif /* CONFIG_IFX_ATM_MIB || IFX_CONFIG_SNMP_ATM_MIB */
-
-#endif //AMAZON_ATM_MIB_H
+++ /dev/null
-//*************************************************************************
-//* Summary of definitions which are used in each peripheral *
-//*************************************************************************
-
-#ifndef peripheral_definitions_h
-#define peripheral_definitions_h
-
-typedef unsigned char UINT8;
-typedef signed char INT8;
-typedef unsigned short UINT16;
-typedef signed short INT16;
-typedef unsigned int UINT32;
-typedef signed int INT32;
-typedef unsigned long long UINT64;
-typedef signed long long INT64;
-
-#define REG8( addr ) (*(volatile UINT8 *) (addr))
-#define REG16( addr ) (*(volatile UINT16 *)(addr))
-#define REG32( addr ) (*(volatile UINT32 *)(addr))
-#define REG64( addr ) (*(volatile UINT64 *)(addr))
-
-/* define routine to set FPI access in Supervisor Mode */
-#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01
-/* Supervisor mode ends, following functions will be done in User mode */
-#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00
-/* Supervisor mode ends, following functions will be done in User mode */
-#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG)
-/* Supervisor mode ends, following functions will be done in User mode */
-#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm
-/* enable all Interrupts in IIU */
-//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask
-///* get all high priority interrupt bits in IIU */
-//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED)
-///* signal ends of interrupt to IIU */
-//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit
-///* force IIU interrupt register */
-//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data
-///* get all bits of interrupt register */
-//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR)
-/* insert a NOP instruction */
-#define NOP _nop()
-/* CPU goes to power down mode until interrupt occurs */
-#define IFX_CPU_SLEEP _sleep()
-/* enable all interrupts to CPU */
-#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int()
-/* get all low priority interrupt bits in peripheral */
-#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg)
-/* clear low priority interrupt bit in peripheral */
-#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit
-/* write FPI bus */
-#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data
-#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data
-#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data
-/* read FPI bus */
-#define READ_FPI_BYTE(addr) REG8(addr)
-#define READ_FPI_16BIT(addr) REG16(addr)
-#define READ_FPI_32BIT(addr) REG32(addr)
-/* write peripheral register */
-#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data
-
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data
-#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data
-#else //not CONFIG_CPU_LITTLE_ENDIAN
-#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data
-#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data
-#endif //CONFIG_CPU_LITTLE_ENDIAN
-
-/* read peripheral register */
-#define READ_PERIPHERAL_REGISTER(addr) REG32(addr)
-
-/* read/modify(or)/write peripheral register */
-#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data
-/* read/modify(and)/write peripheral register */
-#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data
-
-/* CPU-independent mnemonic constants */
-/* CLC register bits */
-#define IFX_CLC_ENABLE 0x00000000
-#define IFX_CLC_DISABLE 0x00000001
-#define IFX_CLC_DISABLE_STATUS 0x00000002
-#define IFX_CLC_SUSPEND_ENABLE 0x00000004
-#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008
-#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010
-#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020
-#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00
-#define IFX_CLC_RUN_DIVIDER_OFFSET 8
-#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000
-#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16
-#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000
-#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24
-
-/* number of cycles to wait for interrupt service routine to be called */
-#define WAIT_CYCLES 50
-
-#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */
+++ /dev/null
-/*
- * ifx_ssc.h defines some data sructures used in ifx_ssc.c
- *
- * Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT)
- *
- *
- */
-
-#ifndef __IFX_SSC_H
-#define __IFX_SSC_H
-#ifdef __KERNEL__
-#include <asm/amazon/ifx_ssc_defines.h>
-#endif //__KERNEL__
-
-#define PORT_CNT 1 // assume default value
-
-/* symbolic constants to be used in SSC routines */
-
-// ### TO DO: bad performance
-#define IFX_SSC_TXFIFO_ITL 1
-#define IFX_SSC_RXFIFO_ITL 1
-
-
-
-struct ifx_ssc_statistics{
- unsigned int abortErr; /* abort error */
- unsigned int modeErr; /* master/slave mode error */
- unsigned int txOvErr; /* TX Overflow error */
- unsigned int txUnErr; /* TX Underrun error */
- unsigned int rxOvErr; /* RX Overflow error */
- unsigned int rxUnErr; /* RX Underrun error */
- unsigned int rxBytes;
- unsigned int txBytes;
-};
-
-
-struct ifx_ssc_hwopts {
- unsigned int AbortErrDetect :1; /* Abort Error detection (in slave mode) */
- unsigned int rxOvErrDetect :1; /* Receive Overflow Error detection */
- unsigned int rxUndErrDetect :1; /* Receive Underflow Error detection */
- unsigned int txOvErrDetect :1; /* Transmit Overflow Error detection */
- unsigned int txUndErrDetect :1; /* Transmit Underflow Error detection */
- unsigned int echoMode :1; /* Echo mode */
- unsigned int loopBack :1; /* Loopback mode */
- unsigned int idleValue :1; /* Idle value */
- unsigned int clockPolarity :1; /* Idle clock is high or low */
- unsigned int clockPhase :1; /* Tx on trailing or leading edge*/
- unsigned int headingControl :1; /* LSB first or MSB first */
- unsigned int dataWidth :6; /* from 2 up to 32 bits */
- unsigned int masterSelect :1; /* Master or Slave mode */
- unsigned int modeRxTx :2; /* rx/tx mode */
- unsigned int gpoCs :8; /* choose outputs to use for chip select */
- unsigned int gpoInv :8; /* invert GPO outputs */
-};
-
-
-struct ifx_ssc_frm_opts {
- bool FrameEnable; // SFCON.SFEN
- unsigned int DataLength; // SFCON.DLEN
- unsigned int PauseLength; // SFCON.PLEN
- unsigned int IdleData; // SFCON.IDAT
- unsigned int IdleClock; // SFCON.ICLK
- bool StopAfterPause; // SFCON.STOP
-};
-
-struct ifx_ssc_frm_status {
- bool DataBusy; // SFSTAT.DBSY
- bool PauseBusy; // SFSTAT.PBSY
- unsigned int DataCount; // SFSTAT.DCNT
- unsigned int PauseCount; // SFSTAT.PCNT
- bool EnIntAfterData; // SFCON.IBEN
- bool EnIntAfterPause;// SFCON.IAEN
-};
-
-typedef struct {
- char *buf;
- size_t len;
-} ifx_ssc_buf_item_t;
-
-
-// data structures for batch execution
-typedef union {
- struct {
- bool save_options;
- } init;
- ifx_ssc_buf_item_t read;
- ifx_ssc_buf_item_t write;
- ifx_ssc_buf_item_t rd_wr;
- unsigned int set_baudrate;
- struct ifx_ssc_frm_opts set_frm;
- unsigned int set_gpo;
- struct ifx_ssc_hwopts set_hwopts;
-}ifx_ssc_batch_cmd_param;
-
-struct ifx_ssc_batch_list {
- unsigned int cmd;
- ifx_ssc_batch_cmd_param cmd_param;
- struct ifx_ssc_batch_list *next;
-};
-
-#ifdef __KERNEL__
-#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE)
-
-
-struct ifx_ssc_port{
- unsigned long mapbase;
- struct ifx_ssc_hwopts opts;
- struct ifx_ssc_statistics stats;
- struct ifx_ssc_frm_status frm_status;
- struct ifx_ssc_frm_opts frm_opts;
- /* wait queue for ifx_ssc_read() */
- wait_queue_head_t rwait, pwait;
- int port_nr;
- char port_is_open; /* exclusive open - boolean */
-// int no_of_bits; /* number of _valid_ bits */
-// int elem_size; /* shift for element (no of bytes)*/
- /* buffer and pointers to the read/write position */
- char *rxbuf; /* buffer for RX */
- char *rxbuf_end; /* buffer end pointer for RX */
- volatile char *rxbuf_ptr; /* buffer write pointer for RX */
- char *txbuf; /* buffer for TX */
- char *txbuf_end; /* buffer end pointer for TX */
- volatile char *txbuf_ptr; /* buffer read pointer for TX */
- unsigned int baud;
- /* each channel has its own interrupts */
- /* (transmit/receive/error/frame) */
- unsigned int txirq, rxirq, errirq, frmirq;
-};
-/* default values for SSC configuration */
-// values of CON
-#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */
-#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */
-#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */
-#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */
-#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */
-#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */
-#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */
-#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */
-#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */
-#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */
-#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */
-#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */
-#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST
-#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX
-// other values
-#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */
-#define IFX_SSC_DEF_BAUDRATE 1000000
-#define IFX_SSC_DEF_RMC 0x10
-
-#define IFX_SSC_DEF_TXFIFO_FL 8
-#define IFX_SSC_DEF_RXFIFO_FL 1
-
-#if 1 //TODO
-#define IFX_SSC_DEF_GPO_CS 2 /* no chip select */
-#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */
-#else
-#error "what is ur Chip Select???"
-#endif
-#define IFX_SSC_DEF_SFCON 0 /* no serial framing */
-#if 0
-#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
- IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT
-#endif
-#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
- IFX_SSC_R_BIT | IFX_SSC_E_BIT
-#endif /* __KERNEL__ */
-
-// batch execution commands
-#define IFX_SSC_BATCH_CMD_INIT 1
-#define IFX_SSC_BATCH_CMD_READ 2
-#define IFX_SSC_BATCH_CMD_WRITE 3
-#define IFX_SSC_BATCH_CMD_RD_WR 4
-#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5
-#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6
-#define IFX_SSC_BATCH_CMD_SET_FRM 7
-#define IFX_SSC_BATCH_CMD_SET_GPO 8
-#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9
-//#define IFX_SSC_BATCH_CMD_
-//#define IFX_SSC_BATCH_CMD_
-#define IFX_SSC_BATCH_CMD_END_EXEC 0
-
-/* Macros to configure SSC hardware */
-/* headingControl: */
-#define IFX_SSC_LSB_FIRST 0
-#define IFX_SSC_MSB_FIRST 1
-/* dataWidth: */
-#define IFX_SSC_MIN_DATA_WIDTH 2
-#define IFX_SSC_MAX_DATA_WIDTH 32
-/* master/slave mode select */
-#define IFX_SSC_MASTER_MODE 1
-#define IFX_SSC_SLAVE_MODE 0
-/* rx/tx mode */
-// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h
-#define IFX_SSC_MODE_RXTX 0
-#define IFX_SSC_MODE_RX 1
-#define IFX_SSC_MODE_TX 2
-#define IFX_SSC_MODE_OFF 3
-#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX
-
-/* GPO values */
-#define IFX_SSC_MAX_GPO_OUT 7
-
-#define IFX_SSC_RXREQ_BLOCK_SIZE 32768
-
-/***********************/
-/* defines for ioctl's */
-/***********************/
-#define IFX_SSC_IOCTL_MAGIC 'S'
-/* read out the statistics */
-#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics)
-/* clear the statistics */
-#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2)
-/* set the baudrate */
-#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int)
-/* get the current baudrate */
-#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int)
-/* set hardware options */
-#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts)
-/* get the current hardware options */
-#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts)
-/* set transmission mode */
-#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int)
-/* get the current transmission mode */
-#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int)
-/* abort transmission */
-#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9)
-#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9)
-
-/* set general purpose outputs */
-#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int)
-/* clear general purpose outputs */
-#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int)
-/* get general purpose outputs */
-#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int)
-
-/*** serial framing ***/
-/* get status of serial framing */
-#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status)
-/* get counter reload values and control bits */
-#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts)
-/* set counter reload values and control bits */
-#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts)
-
-
-/*** batch execution ***/
-/* do batch execution */
-#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list)
-
-
-#ifdef __KERNEL__
-// routines from ifx_ssc.c
-// ### TO DO
-/* kernel interface for read and write */
-ssize_t ifx_ssc_kread(int, char *, size_t);
-ssize_t ifx_ssc_kwrite(int, const char *, size_t);
-
-#ifdef CONFIG_IFX_VP_KERNEL_TEST
-void ifx_ssc_tc(void);
-#endif // CONFIG_IFX_VP_KERNEL_TEST
-
-#endif //__KERNEL__
-#endif // __IFX_SSC_H
-
+++ /dev/null
-#ifndef IFX_SSC_DEFINES_H
-#define IFX_SSC_DEFINES_H
-
-#include "ifx_peripheral_definitions.h"
-
-/* maximum SSC FIFO size */
-#define IFX_SSC_MAX_FIFO_SIZE 32
-
-/* register map of SSC */
-
-/* address of the Clock Control Register of the SSC */
-#define IFX_SSC_CLC 0x00000000
-/* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0
- bit 1 is hardware modified*/
-#define IFX_SSC_CLC_readmask 0x00FFFFEF
-#define IFX_SSC_CLC_writemask 0x00FFFF3D
-#define IFX_SSC_CLC_hwmask 0x00000002
-#define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask)
-
-/* address of Port Input Select Register of the SSC */
-#define IFX_SSC_PISEL 0x00000004
-/* IFX_SSC_PISEL register is significant in lowest three bits only */
-#define IFX_SSC_PISEL_readmask 0x00000007
-#define IFX_SSC_PISEL_writemask 0x00000007
-#define IFX_SSC_PISEL_hwmask 0x00000000
-#define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask)
-
-/* address of Identification Register of the SSC */
-#define IFX_SSC_ID 0x00000008
-/* IFX_SSC_ID register is significant in no bit */
-#define IFX_SSC_ID_readmask 0x0000FF3F
-#define IFX_SSC_ID_writemask 0x00000000
-#define IFX_SSC_ID_hwmask 0x00000000
-#define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask)
-
-/* address of the Control Register of the SSC */
-#define IFX_SSC_CON 0x00000010
-/* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */
-#define IFX_SSC_CON_readmask 0x01DF1FFF
-#define IFX_SSC_CON_writemask 0x01DF1FFF
-#define IFX_SSC_CON_hwmask 0x00000000
-#define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask)
-
-
-/* address of the Status Register of the SSC */
-#define IFX_SSC_STATE 0x00000014
-/* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0
- all bits except 1:0 are hardware modified */
-#define IFX_SSC_STATE_readmask 0x771F3F87
-#define IFX_SSC_STATE_writemask 0x00000000
-#define IFX_SSC_STATE_hwmask 0x771F3F84
-#define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask)
-
-/* address of the Write Hardware Modified Control Register Bits of the SSC */
-#define IFX_SSC_WHBSTATE 0x00000018
-/* IFX_SSC_WHBSTATE register is write only */
-#define IFX_SSC_WHBSTATE_readmask 0x00000000
-#define IFX_SSC_WHBSTATE_writemask 0x0000FFFF
-#define IFX_SSC_WHBSTATE_hwmask 0x00000000
-#define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask)
-
-/* address of the Baudrate Timer Reload Register of the SSC */
-#define IFX_SSC_BR 0x00000040
-/* IFX_SSC_BR register is significant in bit 15 downto 0*/
-#define IFX_SSC_BR_readmask 0x0000FFFF
-#define IFX_SSC_BR_writemask 0x0000FFFF
-#define IFX_SSC_BR_hwmask 0x00000000
-#define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask)
-
-/* address of the Baudrate Timer Status Register of the SSC */
-#define IFX_SSC_BRSTAT 0x00000044
-/* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/
-#define IFX_SSC_BRSTAT_readmask 0x0000FFFF
-#define IFX_SSC_BRSTAT_writemask 0x00000000
-#define IFX_SSC_BRSTAT_hwmask 0x0000FFFF
-#define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask)
-
-/* address of the Transmitter Buffer Register of the SSC */
-#define IFX_SSC_TB 0x00000020
-/* IFX_SSC_TB register is significant in bit 31 downto 0*/
-#define IFX_SSC_TB_readmask 0xFFFFFFFF
-#define IFX_SSC_TB_writemask 0xFFFFFFFF
-#define IFX_SSC_TB_hwmask 0x00000000
-#define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask)
-
-/* address of the Reciver Buffer Register of the SSC */
-#define IFX_SSC_RB 0x00000024
-/* IFX_SSC_RB register is significant in no bits*/
-#define IFX_SSC_RB_readmask 0xFFFFFFFF
-#define IFX_SSC_RB_writemask 0x00000000
-#define IFX_SSC_RB_hwmask 0xFFFFFFFF
-#define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask)
-
-/* address of the Receive FIFO Control Register of the SSC */
-#define IFX_SSC_RXFCON 0x00000030
-/* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
-#define IFX_SSC_RXFCON_readmask 0x00003F03
-#define IFX_SSC_RXFCON_writemask 0x00003F03
-#define IFX_SSC_RXFCON_hwmask 0x00000000
-#define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask)
-
-/* address of the Transmit FIFO Control Register of the SSC */
-#define IFX_SSC_TXFCON 0x00000034
-/* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
-#define IFX_SSC_TXFCON_readmask 0x00003F03
-#define IFX_SSC_TXFCON_writemask 0x00003F03
-#define IFX_SSC_TXFCON_hwmask 0x00000000
-#define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask)
-
-/* address of the FIFO Status Register of the SSC */
-#define IFX_SSC_FSTAT 0x00000038
-/* IFX_SSC_FSTAT register is significant in no bit*/
-#define IFX_SSC_FSTAT_readmask 0x00003F3F
-#define IFX_SSC_FSTAT_writemask 0x00000000
-#define IFX_SSC_FSTAT_hwmask 0x00003F3F
-#define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask)
-
-/* address of the Data Frame Control register of the SSC */
-#define IFX_SSC_SFCON 0x00000060
-#define IFX_SSC_SFCON_readmask 0xFFDFFFFD
-#define IFX_SSC_SFCON_writemask 0xFFDFFFFD
-#define IFX_SSC_SFCON_hwmask 0x00000000
-#define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask)
-
-/* address of the Data Frame Status register of the SSC */
-#define IFX_SSC_SFSTAT 0x00000064
-#define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3
-#define IFX_SSC_SFSTAT_writemask 0x00000000
-#define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3
-#define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask)
-
-/* address of the General Purpose Output Control register of the SSC */
-#define IFX_SSC_GPOCON 0x00000070
-#define IFX_SSC_GPOCON_readmask 0x0000FFFF
-#define IFX_SSC_GPOCON_writemask 0x0000FFFF
-#define IFX_SSC_GPOCON_hwmask 0x00000000
-#define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask)
-
-/* address of the General Purpose Output Status register of the SSC */
-#define IFX_SSC_GPOSTAT 0x00000074
-#define IFX_SSC_GPOSTAT_readmask 0x000000FF
-#define IFX_SSC_GPOSTAT_writemask 0x00000000
-#define IFX_SSC_GPOSTAT_hwmask 0x00000000
-#define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask)
-
-/* address of the Force GPO Status register of the SSC */
-#define IFX_SSC_WHBGPOSTAT 0x00000078
-#define IFX_SSC_WHBGPOSTAT_readmask 0x00000000
-#define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF
-#define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000
-#define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask)
-
-/* address of the Receive Request Register of the SSC */
-#define IFX_SSC_RXREQ 0x00000080
-#define IFX_SSC_RXREQ_readmask 0x0000FFFF
-#define IFX_SSC_RXREQ_writemask 0x0000FFFF
-#define IFX_SSC_RXREQ_hwmask 0x00000000
-#define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask)
-
-/* address of the Receive Count Register of the SSC */
-#define IFX_SSC_RXCNT 0x00000084
-#define IFX_SSC_RXCNT_readmask 0x0000FFFF
-#define IFX_SSC_RXCNT_writemask 0x00000000
-#define IFX_SSC_RXCNT_hwmask 0x0000FFFF
-#define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask)
-
-/* address of the DMA Configuration Register of the SSC */
-#define IFX_SSC_DMACON 0x000000EC
-#define IFX_SSC_DMACON_readmask 0x0000FFFF
-#define IFX_SSC_DMACON_writemask 0x00000000
-#define IFX_SSC_DMACON_hwmask 0x0000FFFF
-#define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask)
-
-//------------------------------------------------------
-// interrupt register for enabling interrupts, mask register of irq_reg
-#define IFX_SSC_IRN_EN 0xF4
-// read/write
-#define IFX_SSC_IRN_EN_readmask 0x0000000F
-#define IFX_SSC_IRN_EN_writemask 0x0000000F
-#define IFX_SSC_IRN_EN_hwmask 0x00000000
-#define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask)
-
-// interrupt register for accessing interrupts
-#define IFX_SSC_IRN_CR 0xF8
-// read/write
-#define IFX_SSC_IRN_CR_readmask 0x0000000F
-#define IFX_SSC_IRN_CR_writemask 0x0000000F
-#define IFX_SSC_IRN_CR_hwmask 0x0000000F
-#define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask)
-
-// interrupt register for stimulating interrupts
-#define IFX_SSC_IRN_ICR 0xFC
-// read/write
-#define IFX_SSC_IRN_ICR_readmask 0x0000000F
-#define IFX_SSC_IRN_ICR_writemask 0x0000000F
-#define IFX_SSC_IRN_ICR_hwmask 0x00000000
-#define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask)
-
-//---------------------------------------------------------------------
-// Number of IRQs and bitposition of IRQ
-#define IFX_SSC_NUM_IRQ 4
-#define IFX_SSC_T_BIT 0x00000001
-#define IFX_SSC_R_BIT 0x00000002
-#define IFX_SSC_E_BIT 0x00000004
-#define IFX_SSC_F_BIT 0x00000008
-
-/* bit masks for SSC registers */
-
-/* ID register */
-#define IFX_SSC_PERID_REV_MASK 0x0000001F
-#define IFX_SSC_PERID_CFG_MASK 0x00000020
-#define IFX_SSC_PERID_ID_MASK 0x0000FF00
-#define IFX_SSC_PERID_REV_OFFSET 0
-#define IFX_SSC_PERID_CFG_OFFSET 5
-#define IFX_SSC_PERID_ID_OFFSET 8
-#define IFX_SSC_PERID_ID 0x45
-#define IFX_SSC_PERID_DMA_ON 0x00000020
-#define IFX_SSC_PERID_RXFS_MASK 0x003F0000
-#define IFX_SSC_PERID_RXFS_OFFSET 16
-#define IFX_SSC_PERID_TXFS_MASK 0x3F000000
-#define IFX_SSC_PERID_TXFS_OFFSET 24
-
-/* PISEL register */
-#define IFX_SSC_PISEL_MASTER_IN_A 0x0000
-#define IFX_SSC_PISEL_MASTER_IN_B 0x0001
-#define IFX_SSC_PISEL_SLAVE_IN_A 0x0000
-#define IFX_SSC_PISEL_SLAVE_IN_B 0x0002
-#define IFX_SSC_PISEL_CLOCK_IN_A 0x0000
-#define IFX_SSC_PISEL_CLOCK_IN_B 0x0004
-
-
-/* IFX_SSC_CON register */
-#define IFX_SSC_CON_ECHO_MODE_ON 0x01000000
-#define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000
-#define IFX_SSC_CON_IDLE_HIGH 0x00800000
-#define IFX_SSC_CON_IDLE_LOW 0x00000000
-#define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000
-#define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000
-#define IFX_SSC_CON_DATA_WIDTH_OFFSET 16
-#define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000
-#define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK)
-
-#define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000
-#define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000
-
-#define IFX_SSC_CON_RX_UFL_CHECK 0x00001000
-#define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000
-#define IFX_SSC_CON_TX_UFL_CHECK 0x00000800
-#define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000
-#define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400
-#define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000
-#define IFX_SSC_CON_RX_OFL_CHECK 0x00000200
-#define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000
-#define IFX_SSC_CON_TX_OFL_CHECK 0x00000100
-#define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000
-#define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00
-#define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000
-
-#define IFX_SSC_CON_LOOPBACK_MODE 0x00000080
-#define IFX_SSC_CON_NO_LOOPBACK 0x00000000
-#define IFX_SSC_CON_HALF_DUPLEX 0x00000080
-#define IFX_SSC_CON_FULL_DUPLEX 0x00000000
-#define IFX_SSC_CON_CLOCK_FALL 0x00000040
-#define IFX_SSC_CON_CLOCK_RISE 0x00000000
-#define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000
-#define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020
-#define IFX_SSC_CON_MSB_FIRST 0x00000010
-#define IFX_SSC_CON_LSB_FIRST 0x00000000
-#define IFX_SSC_CON_ENABLE_CSB 0x00000008
-#define IFX_SSC_CON_DISABLE_CSB 0x00000000
-#define IFX_SSC_CON_INVERT_CSB 0x00000004
-#define IFX_SSC_CON_TRUE_CSB 0x00000000
-#define IFX_SSC_CON_RX_OFF 0x00000002
-#define IFX_SSC_CON_RX_ON 0x00000000
-#define IFX_SSC_CON_TX_OFF 0x00000001
-#define IFX_SSC_CON_TX_ON 0x00000000
-
-
-/* IFX_SSC_STATE register */
-#define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28
-#define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000
-#define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET)
-#define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24
-#define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000
-#define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET)
-#define IFX_SSC_STATE_BIT_COUNT_OFFSET 16
-#define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000
-#define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1)
-#define IFX_SSC_STATE_BUSY 0x00002000
-#define IFX_SSC_STATE_RX_UFL 0x00001000
-#define IFX_SSC_STATE_TX_UFL 0x00000800
-#define IFX_SSC_STATE_ABORT_ERR 0x00000400
-#define IFX_SSC_STATE_RX_OFL 0x00000200
-#define IFX_SSC_STATE_TX_OFL 0x00000100
-#define IFX_SSC_STATE_MODE_ERR 0x00000080
-#define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004
-#define IFX_SSC_STATE_IS_MASTER 0x00000002
-#define IFX_SSC_STATE_IS_ENABLED 0x00000001
-
-/* WHBSTATE register */
-#define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001
-#define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001
-#define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001
-
-#define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002
-#define IFX_SSC_WHBSTATE_RUN_MODE 0x0002
-#define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002
-
-#define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004
-#define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004
-
-#define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008
-#define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008
-
-#define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010
-#define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020
-
-#define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040
-#define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080
-
-#define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100
-#define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200
-#define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400
-#define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800
-#define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000
-#define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000
-#define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000
-#define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000
-#define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50
-#define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0
-
-/* BR register */
-#define IFX_SSC_BR_BAUDRATE_OFFSET 0
-#define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF
-
-/* BR_STAT register */
-#define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0
-#define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF
-
-/* TB register */
-#define IFX_SSC_TB_DATA_OFFSET 0
-#define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF
-
-/* RB register */
-#define IFX_SSC_RB_DATA_OFFSET 0
-#define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF
-
-
-/* RXFCON and TXFCON registers */
-#define IFX_SSC_XFCON_FIFO_DISABLE 0x0000
-#define IFX_SSC_XFCON_FIFO_ENABLE 0x0001
-#define IFX_SSC_XFCON_FIFO_FLUSH 0x0002
-#define IFX_SSC_XFCON_ITL_MASK 0x00003F00
-#define IFX_SSC_XFCON_ITL_OFFSET 8
-
-/* FSTAT register */
-#define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0
-#define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F
-#define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8
-#define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00
-
-/* GPOCON register */
-#define IFX_SSC_GPOCON_INVOUT0_POS 0
-#define IFX_SSC_GPOCON_INV_OUT0 0x00000001
-#define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000
-#define IFX_SSC_GPOCON_INVOUT1_POS 1
-#define IFX_SSC_GPOCON_INV_OUT1 0x00000002
-#define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000
-#define IFX_SSC_GPOCON_INVOUT2_POS 2
-#define IFX_SSC_GPOCON_INV_OUT2 0x00000003
-#define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000
-#define IFX_SSC_GPOCON_INVOUT3_POS 3
-#define IFX_SSC_GPOCON_INV_OUT3 0x00000008
-#define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000
-#define IFX_SSC_GPOCON_INVOUT4_POS 4
-#define IFX_SSC_GPOCON_INV_OUT4 0x00000010
-#define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000
-#define IFX_SSC_GPOCON_INVOUT5_POS 5
-#define IFX_SSC_GPOCON_INV_OUT5 0x00000020
-#define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000
-#define IFX_SSC_GPOCON_INVOUT6_POS 6
-#define IFX_SSC_GPOCON_INV_OUT6 0x00000040
-#define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000
-#define IFX_SSC_GPOCON_INVOUT7_POS 7
-#define IFX_SSC_GPOCON_INV_OUT7 0x00000080
-#define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000
-#define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF
-#define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000
-
-#define IFX_SSC_GPOCON_ISCSB0_POS 8
-#define IFX_SSC_GPOCON_IS_CSB0 0x00000100
-#define IFX_SSC_GPOCON_IS_GPO0 0x00000000
-#define IFX_SSC_GPOCON_ISCSB1_POS 9
-#define IFX_SSC_GPOCON_IS_CSB1 0x00000200
-#define IFX_SSC_GPOCON_IS_GPO1 0x00000000
-#define IFX_SSC_GPOCON_ISCSB2_POS 10
-#define IFX_SSC_GPOCON_IS_CSB2 0x00000400
-#define IFX_SSC_GPOCON_IS_GPO2 0x00000000
-#define IFX_SSC_GPOCON_ISCSB3_POS 11
-#define IFX_SSC_GPOCON_IS_CSB3 0x00000800
-#define IFX_SSC_GPOCON_IS_GPO3 0x00000000
-#define IFX_SSC_GPOCON_ISCSB4_POS 12
-#define IFX_SSC_GPOCON_IS_CSB4 0x00001000
-#define IFX_SSC_GPOCON_IS_GPO4 0x00000000
-#define IFX_SSC_GPOCON_ISCSB5_POS 13
-#define IFX_SSC_GPOCON_IS_CSB5 0x00002000
-#define IFX_SSC_GPOCON_IS_GPO5 0x00000000
-#define IFX_SSC_GPOCON_ISCSB6_POS 14
-#define IFX_SSC_GPOCON_IS_CSB6 0x00004000
-#define IFX_SSC_GPOCON_IS_GPO6 0x00000000
-#define IFX_SSC_GPOCON_ISCSB7_POS 15
-#define IFX_SSC_GPOCON_IS_CSB7 0x00008000
-#define IFX_SSC_GPOCON_IS_GPO7 0x00000000
-#define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00
-#define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000
-
-/* GPOSTAT register */
-#define IFX_SSC_GPOSTAT_OUT0 0x00000001
-#define IFX_SSC_GPOSTAT_OUT1 0x00000002
-#define IFX_SSC_GPOSTAT_OUT2 0x00000004
-#define IFX_SSC_GPOSTAT_OUT3 0x00000008
-#define IFX_SSC_GPOSTAT_OUT4 0x00000010
-#define IFX_SSC_GPOSTAT_OUT5 0x00000020
-#define IFX_SSC_GPOSTAT_OUT6 0x00000040
-#define IFX_SSC_GPOSTAT_OUT7 0x00000080
-#define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF
-
-/* WHBGPOSTAT register */
-#define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001
-#define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002
-#define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004
-#define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008
-#define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010
-#define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020
-#define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040
-#define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF
-
-#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0
-#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1
-#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2
-#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3
-#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4
-#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5
-#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6
-#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7
-
-
-#define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8
-#define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100
-#define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9
-#define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200
-#define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10
-#define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400
-#define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11
-#define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800
-#define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12
-#define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000
-#define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13
-#define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000
-#define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14
-#define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000
-#define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15
-#define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000
-#define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00
-
-/* SFCON register */
-#define IFX_SSC_SFCON_SF_ENABLE 0x00000001
-#define IFX_SSC_SFCON_SF_DISABLE 0x00000000
-#define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004
-#define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000
-#define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008
-#define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000
-#define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0
-#define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4
-#define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000
-#define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16
-#define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000
-#define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000
-#define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000
-#define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000
-#define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18
-#define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000
-#define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000
-#define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000
-#define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000
-#define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000
-#define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000
-#define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000
-#define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22
-#define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096
-#define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024
-
-#define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET)
-#define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET)
-#define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK)
-#define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK)
-
-/* SFSTAT register */
-#define IFX_SSC_SFSTAT_IN_DATA 0x00000001
-#define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002
-#define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0
-#define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4
-#define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000
-#define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20
-
-#define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET)
-#define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET)
-
-/* RXREQ register */
-#define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF
-#define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0
-
-/* RXCNT register */
-#define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF
-#define IFX_SSC_RXCNT_TODO_OFFSET 0
-
-/* DMACON register */
-#define IFX_SSC_DMACON_RXON 0x00000001
-#define IFX_SSC_DMACON_RXOFF 0x00000000
-#define IFX_SSC_DMACON_TXON 0x00000002
-#define IFX_SSC_DMACON_TXOFF 0x00000000
-#define IFX_SSC_DMACON_DMAON 0x00000003
-#define IFX_SSC_DMACON_DMAOFF 0x00000000
-#define IFX_SSC_DMACON_CLASS_MASK 0x0000000C
-#define IFX_SSC_DMACON_CLASS_OFFSET 2
-
-/* register access macros */
-#define ifx_ssc_fstat_received_words(status) (status & 0x003F)
-#define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8)
-
-#define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE))
-#define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON))
-#define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON))
-#define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE))
-#define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB))
-#define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB))
-#define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT))
-#define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR))
-
-#define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET)
-#define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
-
-#endif
+++ /dev/null
-/* irq.h - AMAZON interrupts */
-
-#ifndef __AMAZON_IRQ
-#define __AMAZON_IRQ
-
-/************************************************************************
- * Interrupt information
-*************************************************************************/
-
-/* these vectors are to handle the interrupts from the internal AMAZON
- interrupt controller. THe INT_NUM values are really just indices into
- an array and are set up so that we can use the INT_NUM as a shift
- to calculate a mask value. */
-#define INT_NUM_IRQ0 8
-#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
-#define INT_NUM_IM0_IRL1 (INT_NUM_IRQ0 + 1)
-#define INT_NUM_IM0_IRL2 (INT_NUM_IRQ0 + 2)
-#define INT_NUM_IM0_IRL3 (INT_NUM_IRQ0 + 3)
-#define INT_NUM_IM0_IRL4 (INT_NUM_IRQ0 + 4)
-#define INT_NUM_IM0_IRL5 (INT_NUM_IRQ0 + 5)
-#define INT_NUM_IM0_IRL6 (INT_NUM_IRQ0 + 6)
-#define INT_NUM_IM0_IRL7 (INT_NUM_IRQ0 + 7)
-#define INT_NUM_IM0_IRL8 (INT_NUM_IRQ0 + 8)
-#define INT_NUM_IM0_IRL9 (INT_NUM_IRQ0 + 9)
-#define INT_NUM_IM0_IRL10 (INT_NUM_IRQ0 + 10)
-#define INT_NUM_IM0_IRL11 (INT_NUM_IRQ0 + 11)
-#define INT_NUM_IM0_IRL12 (INT_NUM_IRQ0 + 12)
-#define INT_NUM_IM0_IRL13 (INT_NUM_IRQ0 + 13)
-#define INT_NUM_IM0_IRL14 (INT_NUM_IRQ0 + 14)
-#define INT_NUM_IM0_IRL15 (INT_NUM_IRQ0 + 15)
-#define INT_NUM_IM0_IRL16 (INT_NUM_IRQ0 + 16)
-#define INT_NUM_IM0_IRL17 (INT_NUM_IRQ0 + 17)
-#define INT_NUM_IM0_IRL18 (INT_NUM_IRQ0 + 18)
-#define INT_NUM_IM0_IRL19 (INT_NUM_IRQ0 + 19)
-#define INT_NUM_IM0_IRL20 (INT_NUM_IRQ0 + 20)
-#define INT_NUM_IM0_IRL21 (INT_NUM_IRQ0 + 21)
-#define INT_NUM_IM0_IRL22 (INT_NUM_IRQ0 + 22)
-#define INT_NUM_IM0_IRL23 (INT_NUM_IRQ0 + 23)
-#define INT_NUM_IM0_IRL24 (INT_NUM_IRQ0 + 24)
-#define INT_NUM_IM0_IRL25 (INT_NUM_IRQ0 + 25)
-#define INT_NUM_IM0_IRL26 (INT_NUM_IRQ0 + 26)
-#define INT_NUM_IM0_IRL27 (INT_NUM_IRQ0 + 27)
-#define INT_NUM_IM0_IRL28 (INT_NUM_IRQ0 + 28)
-#define INT_NUM_IM0_IRL29 (INT_NUM_IRQ0 + 29)
-#define INT_NUM_IM0_IRL30 (INT_NUM_IRQ0 + 30)
-#define INT_NUM_IM0_IRL31 (INT_NUM_IRQ0 + 31)
-
-#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
-#define INT_NUM_IM1_IRL1 (INT_NUM_IM1_IRL0 + 1)
-#define INT_NUM_IM1_IRL2 (INT_NUM_IM1_IRL0 + 2)
-#define INT_NUM_IM1_IRL3 (INT_NUM_IM1_IRL0 + 3)
-#define INT_NUM_IM1_IRL4 (INT_NUM_IM1_IRL0 + 4)
-#define INT_NUM_IM1_IRL5 (INT_NUM_IM1_IRL0 + 5)
-#define INT_NUM_IM1_IRL6 (INT_NUM_IM1_IRL0 + 6)
-#define INT_NUM_IM1_IRL7 (INT_NUM_IM1_IRL0 + 7)
-#define INT_NUM_IM1_IRL8 (INT_NUM_IM1_IRL0 + 8)
-#define INT_NUM_IM1_IRL9 (INT_NUM_IM1_IRL0 + 9)
-#define INT_NUM_IM1_IRL10 (INT_NUM_IM1_IRL0 + 10)
-#define INT_NUM_IM1_IRL11 (INT_NUM_IM1_IRL0 + 11)
-#define INT_NUM_IM1_IRL12 (INT_NUM_IM1_IRL0 + 12)
-#define INT_NUM_IM1_IRL13 (INT_NUM_IM1_IRL0 + 13)
-#define INT_NUM_IM1_IRL14 (INT_NUM_IM1_IRL0 + 14)
-#define INT_NUM_IM1_IRL15 (INT_NUM_IM1_IRL0 + 15)
-#define INT_NUM_IM1_IRL16 (INT_NUM_IM1_IRL0 + 16)
-#define INT_NUM_IM1_IRL17 (INT_NUM_IM1_IRL0 + 17)
-#define INT_NUM_IM1_IRL18 (INT_NUM_IM1_IRL0 + 18)
-#define INT_NUM_IM1_IRL19 (INT_NUM_IM1_IRL0 + 19)
-#define INT_NUM_IM1_IRL20 (INT_NUM_IM1_IRL0 + 20)
-#define INT_NUM_IM1_IRL21 (INT_NUM_IM1_IRL0 + 21)
-#define INT_NUM_IM1_IRL22 (INT_NUM_IM1_IRL0 + 22)
-#define INT_NUM_IM1_IRL23 (INT_NUM_IM1_IRL0 + 23)
-#define INT_NUM_IM1_IRL24 (INT_NUM_IM1_IRL0 + 24)
-#define INT_NUM_IM1_IRL25 (INT_NUM_IM1_IRL0 + 25)
-#define INT_NUM_IM1_IRL26 (INT_NUM_IM1_IRL0 + 26)
-#define INT_NUM_IM1_IRL27 (INT_NUM_IM1_IRL0 + 27)
-#define INT_NUM_IM1_IRL28 (INT_NUM_IM1_IRL0 + 28)
-#define INT_NUM_IM1_IRL29 (INT_NUM_IM1_IRL0 + 29)
-#define INT_NUM_IM1_IRL30 (INT_NUM_IM1_IRL0 + 30)
-#define INT_NUM_IM1_IRL31 (INT_NUM_IM1_IRL0 + 31)
-
-#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
-#define INT_NUM_IM2_IRL1 (INT_NUM_IM2_IRL0 + 1)
-#define INT_NUM_IM2_IRL2 (INT_NUM_IM2_IRL0 + 2)
-#define INT_NUM_IM2_IRL3 (INT_NUM_IM2_IRL0 + 3)
-#define INT_NUM_IM2_IRL4 (INT_NUM_IM2_IRL0 + 4)
-#define INT_NUM_IM2_IRL5 (INT_NUM_IM2_IRL0 + 5)
-#define INT_NUM_IM2_IRL6 (INT_NUM_IM2_IRL0 + 6)
-#define INT_NUM_IM2_IRL7 (INT_NUM_IM2_IRL0 + 7)
-#define INT_NUM_IM2_IRL8 (INT_NUM_IM2_IRL0 + 8)
-#define INT_NUM_IM2_IRL9 (INT_NUM_IM2_IRL0 + 9)
-#define INT_NUM_IM2_IRL10 (INT_NUM_IM2_IRL0 + 10)
-#define INT_NUM_IM2_IRL11 (INT_NUM_IM2_IRL0 + 11)
-#define INT_NUM_IM2_IRL12 (INT_NUM_IM2_IRL0 + 12)
-#define INT_NUM_IM2_IRL13 (INT_NUM_IM2_IRL0 + 13)
-#define INT_NUM_IM2_IRL14 (INT_NUM_IM2_IRL0 + 14)
-#define INT_NUM_IM2_IRL15 (INT_NUM_IM2_IRL0 + 15)
-#define INT_NUM_IM2_IRL16 (INT_NUM_IM2_IRL0 + 16)
-#define INT_NUM_IM2_IRL17 (INT_NUM_IM2_IRL0 + 17)
-#define INT_NUM_IM2_IRL18 (INT_NUM_IM2_IRL0 + 18)
-#define INT_NUM_IM2_IRL19 (INT_NUM_IM2_IRL0 + 19)
-#define INT_NUM_IM2_IRL20 (INT_NUM_IM2_IRL0 + 20)
-#define INT_NUM_IM2_IRL21 (INT_NUM_IM2_IRL0 + 21)
-#define INT_NUM_IM2_IRL22 (INT_NUM_IM2_IRL0 + 22)
-#define INT_NUM_IM2_IRL23 (INT_NUM_IM2_IRL0 + 23)
-#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24)
-#define INT_NUM_IM2_IRL25 (INT_NUM_IM2_IRL0 + 25)
-#define INT_NUM_IM2_IRL26 (INT_NUM_IM2_IRL0 + 26)
-#define INT_NUM_IM2_IRL27 (INT_NUM_IM2_IRL0 + 27)
-#define INT_NUM_IM2_IRL28 (INT_NUM_IM2_IRL0 + 28)
-#define INT_NUM_IM2_IRL29 (INT_NUM_IM2_IRL0 + 29)
-#define INT_NUM_IM2_IRL30 (INT_NUM_IM2_IRL0 + 30)
-#define INT_NUM_IM2_IRL31 (INT_NUM_IM2_IRL0 + 31)
-
-#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
-#define INT_NUM_IM3_IRL1 (INT_NUM_IM3_IRL0 + 1)
-#define INT_NUM_IM3_IRL2 (INT_NUM_IM3_IRL0 + 2)
-#define INT_NUM_IM3_IRL3 (INT_NUM_IM3_IRL0 + 3)
-#define INT_NUM_IM3_IRL4 (INT_NUM_IM3_IRL0 + 4)
-#define INT_NUM_IM3_IRL5 (INT_NUM_IM3_IRL0 + 5)
-#define INT_NUM_IM3_IRL6 (INT_NUM_IM3_IRL0 + 6)
-#define INT_NUM_IM3_IRL7 (INT_NUM_IM3_IRL0 + 7)
-#define INT_NUM_IM3_IRL8 (INT_NUM_IM3_IRL0 + 8)
-#define INT_NUM_IM3_IRL9 (INT_NUM_IM3_IRL0 + 9)
-#define INT_NUM_IM3_IRL10 (INT_NUM_IM3_IRL0 + 10)
-#define INT_NUM_IM3_IRL11 (INT_NUM_IM3_IRL0 + 11)
-#define INT_NUM_IM3_IRL12 (INT_NUM_IM3_IRL0 + 12)
-#define INT_NUM_IM3_IRL13 (INT_NUM_IM3_IRL0 + 13)
-#define INT_NUM_IM3_IRL14 (INT_NUM_IM3_IRL0 + 14)
-#define INT_NUM_IM3_IRL15 (INT_NUM_IM3_IRL0 + 15)
-#define INT_NUM_IM3_IRL16 (INT_NUM_IM3_IRL0 + 16)
-#define INT_NUM_IM3_IRL17 (INT_NUM_IM3_IRL0 + 17)
-#define INT_NUM_IM3_IRL18 (INT_NUM_IM3_IRL0 + 18)
-#define INT_NUM_IM3_IRL19 (INT_NUM_IM3_IRL0 + 19)
-#define INT_NUM_IM3_IRL20 (INT_NUM_IM3_IRL0 + 20)
-#define INT_NUM_IM3_IRL21 (INT_NUM_IM3_IRL0 + 21)
-#define INT_NUM_IM3_IRL22 (INT_NUM_IM3_IRL0 + 22)
-#define INT_NUM_IM3_IRL23 (INT_NUM_IM3_IRL0 + 23)
-#define INT_NUM_IM3_IRL24 (INT_NUM_IM3_IRL0 + 24)
-#define INT_NUM_IM3_IRL25 (INT_NUM_IM3_IRL0 + 25)
-#define INT_NUM_IM3_IRL26 (INT_NUM_IM3_IRL0 + 26)
-#define INT_NUM_IM3_IRL27 (INT_NUM_IM3_IRL0 + 27)
-#define INT_NUM_IM3_IRL28 (INT_NUM_IM3_IRL0 + 28)
-#define INT_NUM_IM3_IRL29 (INT_NUM_IM3_IRL0 + 29)
-#define INT_NUM_IM3_IRL30 (INT_NUM_IM3_IRL0 + 30)
-#define INT_NUM_IM3_IRL31 (INT_NUM_IM3_IRL0 + 31)
-
-#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
-#define INT_NUM_IM4_IRL1 (INT_NUM_IM4_IRL0 + 1)
-#define INT_NUM_IM4_IRL2 (INT_NUM_IM4_IRL0 + 2)
-#define INT_NUM_IM4_IRL3 (INT_NUM_IM4_IRL0 + 3)
-#define INT_NUM_IM4_IRL4 (INT_NUM_IM4_IRL0 + 4)
-#define INT_NUM_IM4_IRL5 (INT_NUM_IM4_IRL0 + 5)
-#define INT_NUM_IM4_IRL6 (INT_NUM_IM4_IRL0 + 6)
-#define INT_NUM_IM4_IRL7 (INT_NUM_IM4_IRL0 + 7)
-#define INT_NUM_IM4_IRL8 (INT_NUM_IM4_IRL0 + 8)
-#define INT_NUM_IM4_IRL9 (INT_NUM_IM4_IRL0 + 9)
-#define INT_NUM_IM4_IRL10 (INT_NUM_IM4_IRL0 + 10)
-#define INT_NUM_IM4_IRL11 (INT_NUM_IM4_IRL0 + 11)
-#define INT_NUM_IM4_IRL12 (INT_NUM_IM4_IRL0 + 12)
-#define INT_NUM_IM4_IRL13 (INT_NUM_IM4_IRL0 + 13)
-#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
-#define INT_NUM_IM4_IRL15 (INT_NUM_IM4_IRL0 + 15)
-#define INT_NUM_IM4_IRL16 (INT_NUM_IM4_IRL0 + 16)
-#define INT_NUM_IM4_IRL17 (INT_NUM_IM4_IRL0 + 17)
-#define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18)
-#define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19)
-#define INT_NUM_IM4_IRL20 (INT_NUM_IM4_IRL0 + 20)
-#define INT_NUM_IM4_IRL21 (INT_NUM_IM4_IRL0 + 21)
-#define INT_NUM_IM4_IRL22 (INT_NUM_IM4_IRL0 + 22)
-#define INT_NUM_IM4_IRL23 (INT_NUM_IM4_IRL0 + 23)
-#define INT_NUM_IM4_IRL24 (INT_NUM_IM4_IRL0 + 24)
-#define INT_NUM_IM4_IRL25 (INT_NUM_IM4_IRL0 + 25)
-#define INT_NUM_IM4_IRL26 (INT_NUM_IM4_IRL0 + 26)
-#define INT_NUM_IM4_IRL27 (INT_NUM_IM4_IRL0 + 27)
-#define INT_NUM_IM4_IRL28 (INT_NUM_IM4_IRL0 + 28)
-#define INT_NUM_IM4_IRL29 (INT_NUM_IM4_IRL0 + 29)
-#define INT_NUM_IM4_IRL30 (INT_NUM_IM4_IRL0 + 30)
-#define INT_NUM_IM4_IRL31 (INT_NUM_IM4_IRL0 + 31)
-
-/****** Interrupt Assigments ***********/
-#define AMAZON_DMA_INT INT_NUM_IM0_IRL0
-#define IFX_SSC_TIR INT_NUM_IM0_IRL29
-#define IFX_SSC_RIR INT_NUM_IM0_IRL30
-#define IFX_SSC_EIR INT_NUM_IM0_IRL31
-
-#define AMAZON_MEI_INT INT_NUM_IM2_IRL8
-
-#define AMAZONASC_TIR INT_NUM_IM4_IRL15/* TX interrupt */
-#define AMAZONASC_RIR INT_NUM_IM4_IRL16/* RX interrupt */
-#define AMAZONASC_EIR INT_NUM_IM4_IRL17/* ERROR interrupt */
-
-#define AMAZON_TIMER6_INT INT_NUM_IM1_IRL23
-
-#define AMAZON_SWIE_INT INT_NUM_IM3_IRL8
-#define AMAZON_CBM_INT INT_NUM_IM3_IRL9
-#define AMAZON_AAL5_INT INT_NUM_IM3_IRL10
-#define AMAZON_HTU_INT INT_NUM_IM3_IRL11
-#define AMAZON_QSB_INT INT_NUM_IM3_IRL12
-#define MIPS_CPU_TIMER_IRQ 7
-#endif /* __AMAZON_IRQ */
+++ /dev/null
-#ifndef AMAZON_MODEL_H
-#define AMAZON_MODEL_H
-/******************************************************************************
- Copyright (c) 2002, Infineon Technologies. All rights reserved.
-
- No Warranty
- Because the program is licensed free of charge, there is no warranty for
- the program, to the extent permitted by applicable law. Except when
- otherwise stated in writing the copyright holders and/or other parties
- provide the program "as is" without warranty of any kind, either
- expressed or implied, including, but not limited to, the implied
- warranties of merchantability and fitness for a particular purpose. The
- entire risk as to the quality and performance of the program is with
- you. should the program prove defective, you assume the cost of all
- necessary servicing, repair or correction.
-
- In no event unless required by applicable law or agreed to in writing
- will any copyright holder, or any other party who may modify and/or
- redistribute the program as permitted above, be liable to you for
- damages, including any general, special, incidental or consequential
- damages arising out of the use or inability to use the program
- (including but not limited to loss of data or data being rendered
- inaccurate or losses sustained by you or third parties or a failure of
- the program to operate with any other programs), even if such holder or
- other party has been advised of the possibility of such damages.
-******************************************************************************/
-#define BOARD_SYSTEM_TYPE "AMAZON"
-#define SYSTEM_MODEL_NAME "Amazon Gateway Package 3.2 Version"
-#endif
+++ /dev/null
-/*
- * ########################################################################
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * port.h
- *
- * Global Amazon port driver header file
- *
- */
-
-/* Modification history */
-/* 21Jun2004 btxu Generate from Inca_IP project */
-
-
-#ifndef PORT_H
-#define PORT_H
-
-struct amazon_port_ioctl_parm {
- int port;
- int pin;
- int value;
-};
-#define AMAZON_PORT_IOC_MAGIC 0xbf
-#define AMAZON_PORT_IOCOD _IOW( AMAZON_PORT_IOC_MAGIC,0,struct amazon_port_ioctl_parm)
-#define AMAZON_PORT_IOCPUDSEL _IOW( AMAZON_PORT_IOC_MAGIC,1,struct amazon_port_ioctl_parm)
-#define AMAZON_PORT_IOCPUDEN _IOW( AMAZON_PORT_IOC_MAGIC,2,struct amazon_port_ioctl_parm)
-#define AMAZON_PORT_IOCSTOFF _IOW( AMAZON_PORT_IOC_MAGIC,3,struct amazon_port_ioctl_parm)
-#define AMAZON_PORT_IOCDIR _IOW( AMAZON_PORT_IOC_MAGIC,4,struct amazon_port_ioctl_parm)
-#define AMAZON_PORT_IOCOUTPUT _IOW( AMAZON_PORT_IOC_MAGIC,5,struct amazon_port_ioctl_parm)
-#define AMAZON_PORT_IOCINPUT _IOWR(AMAZON_PORT_IOC_MAGIC,6,struct amazon_port_ioctl_parm)
-#define AMAZON_PORT_IOCALTSEL0 _IOW( AMAZON_PORT_IOC_MAGIC,7,struct amazon_port_ioctl_parm)
-#define AMAZON_PORT_IOCALTSEL1 _IOW( AMAZON_PORT_IOC_MAGIC,8,struct amazon_port_ioctl_parm)
-
-int amazon_port_reserve_pin(int port, int pin, int module_id);
-int amazon_port_free_pin(int port, int pin, int module_id);
-int amazon_port_set_open_drain(int port, int pin, int module_id);
-int amazon_port_clear_open_drain(int port, int pin, int module_id);
-int amazon_port_set_pudsel(int port, int pin, int module_id);
-int amazon_port_clear_pudsel(int port, int pin, int module_id);
-int amazon_port_set_puden(int port, int pin, int module_id);
-int amazon_port_clear_puden(int port, int pin, int module_id);
-int amazon_port_set_stoff(int port, int pin, int module_id);
-int amazon_port_clear_stoff(int port, int pin, int module_id);
-int amazon_port_set_dir_out(int port, int pin, int module_id);
-int amazon_port_set_dir_in(int port, int pin, int module_id);
-int amazon_port_set_output(int port, int pin, int module_id);
-int amazon_port_clear_output(int port, int pin, int module_id);
-int amazon_port_get_input(int port, int pin, int module_id);
-
-int amazon_port_set_altsel0(int port, int pin, int module_id);
-int amazon_port_clear_altsel0(int port, int pin, int module_id);
-int amazon_port_set_altsel1(int port, int pin, int module_id);
-int amazon_port_clear_altsel1(int port, int pin, int module_id);
-
-
-#endif /* PORT_H */
-
-
+++ /dev/null
-/* incaAscSio.h - (AMAZON) ASC UART tty driver header */
-
-#ifndef __AMAZON_ASC_H
-#define __AMAZON_ASC_H
-
-/* channel operating modes */
-#define ASCOPT_CSIZE 0x00000003
-#define ASCOPT_CS7 0x00000001
-#define ASCOPT_CS8 0x00000002
-#define ASCOPT_PARENB 0x00000004
-#define ASCOPT_STOPB 0x00000008
-#define ASCOPT_PARODD 0x00000010
-#define ASCOPT_CREAD 0x00000020
-
-#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
-
-/* ASC input select (0 or 1) */
-#define CONSOLE_TTY 0
-
-/* use fractional divider for baudrate settings */
-#define AMAZONASC_USE_FDV
-
-#ifdef AMAZONASC_USE_FDV
- #define AMAZONASC_FDV_LOW_BAUDRATE 71
-#ifdef CONFIG_USE_IKOS
- #define AMAZONASC_FDV_HIGH_BAUDRATE 443
-#else
- #define AMAZONASC_FDV_HIGH_BAUDRATE 498
-#endif //CONFIG_USE_IKOS
-#endif /*AMAZONASC_USE_FDV*/
-
-
-#define AMAZONASC_TXFIFO_FL 1
-#define AMAZONASC_RXFIFO_FL 1
-#define AMAZONASC_TXFIFO_FULL 16
-
-/* interrupt lines masks for the ASC device interrupts*/
-/* change these macroses if it's necessary */
-#define AMAZONASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */
-
-#define AMAZONASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */
-#define AMAZONASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */
-#define AMAZONASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */
-#define AMAZONASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/
-
-/* CLC register's bits and bitfields */
-#define ASCCLC_DISR 0x00000001
-#define ASCCLC_DISS 0x00000002
-#define ASCCLC_RMCMASK 0x0000FF00
-#define ASCCLC_RMCOFFSET 8
-
-/* CON register's bits and bitfields */
-#define ASCCON_MODEMASK 0x0007
- #define ASCCON_M_8SYNC 0x0
- #define ASCCON_M_8ASYNC 0x1
- #define ASCCON_M_8IRDAASYNC 0x2
- #define ASCCON_M_7ASYNCPAR 0x3
- #define ASCCON_M_9ASYNC 0x4
- #define ASCCON_M_8WAKEUPASYNC 0x5
- #define ASCCON_M_8ASYNCPAR 0x7
-#define ASCCON_STP 0x0008
-#define ASCCON_REN 0x0010
-#define ASCCON_PEN 0x0020
-#define ASCCON_FEN 0x0040
-#define ASCCON_OEN 0x0080
-#define ASCCON_PE 0x0100
-#define ASCCON_FE 0x0200
-#define ASCCON_OE 0x0400
-#define ASCCON_FDE 0x0800
-#define ASCCON_ODD 0x1000
-#define ASCCON_BRS 0x2000
-#define ASCCON_LB 0x4000
-#define ASCCON_R 0x8000
-#define ASCCON_ANY (ASCCON_PE|ASCCON_FE|ASCCON_OE)
-
-/* WHBCON register's bits and bitfields */
-#define ASCWHBCON_CLRREN 0x0010
-#define ASCWHBCON_SETREN 0x0020
-#define ASCWHBCON_CLRPE 0x0100
-#define ASCWHBCON_CLRFE 0x0200
-#define ASCWHBCON_CLROE 0x0400
-#define ASCWHBCON_SETPE 0x0800
-#define ASCWHBCON_SETFE 0x1000
-#define ASCWHBCON_SETOE 0x2000
-
-/* ABCON register's bits and bitfields */
-#define ASCABCON_ABEN 0x0001
-#define ASCABCON_AUREN 0x0002
-#define ASCABCON_ABSTEN 0x0004
-#define ASCABCON_ABDETEN 0x0008
-#define ASCABCON_FCDETEN 0x0010
-#define ASCABCON_EMMASK 0x0300
- #define ASCABCON_EMOFF 8
- #define ASCABCON_EM_DISAB 0x0
- #define ASCABCON_EM_DURAB 0x1
- #define ASCABCON_EM_ALWAYS 0x2
-#define ASCABCON_TXINV 0x0400
-#define ASCABCON_RXINV 0x0800
-
-/* FDV register mask, offset and bitfields*/
-#define ASCFDV_VALUE_MASK 0x000001FF
-
-/* WHBABCON register's bits and bitfields */
-#define ASCWHBABCON_SETABEN 0x0001
-#define ASCWHBABCON_CLRABEN 0x0002
-
-/* ABSTAT register's bits and bitfields */
-#define ASCABSTAT_FCSDET 0x0001
-#define ASCABSTAT_FCCDET 0x0002
-#define ASCABSTAT_SCSDET 0x0004
-#define ASCABSTAT_SCCDET 0x0008
-#define ASCABSTAT_DETWAIT 0x0010
-
-/* WHBABSTAT register's bits and bitfields */
-#define ASCWHBABSTAT_CLRFCSDET 0x0001
-#define ASCWHBABSTAT_SETFCSDET 0x0002
-#define ASCWHBABSTAT_CLRFCCDET 0x0004
-#define ASCWHBABSTAT_SETFCCDET 0x0008
-#define ASCWHBABSTAT_CLRSCSDET 0x0010
-#define ASCWHBABSTAT_SETSCSDET 0x0020
-#define ASCWHBABSTAT_SETSCCDET 0x0040
-#define ASCWHBABSTAT_CLRSCCDET 0x0080
-#define ASCWHBABSTAT_CLRDETWAIT 0x0100
-#define ASCWHBABSTAT_SETDETWAIT 0x0200
-
-/* TXFCON register's bits and bitfields */
-#define ASCTXFCON_TXFEN 0x0001
-#define ASCTXFCON_TXFFLU 0x0002
-#define ASCTXFCON_TXTMEN 0x0004
-#define ASCTXFCON_TXFITLMASK 0x3F00
-#define ASCTXFCON_TXFITLOFF 8
-
-/* RXFCON register's bits and bitfields */
-#define ASCRXFCON_RXFEN 0x0001
-#define ASCRXFCON_RXFFLU 0x0002
-#define ASCRXFCON_RXTMEN 0x0004
-#define ASCRXFCON_RXFITLMASK 0x3F00
-#define ASCRXFCON_RXFITLOFF 8
-
-/* FSTAT register's bits and bitfields */
-#define ASCFSTAT_RXFFLMASK 0x003F
-#define ASCFSTAT_TXFFLMASK 0x3F00
-#define ASCFSTAT_TXFFLOFF 8
-
-#endif /* __AMAZON_ASC_H */
-
+++ /dev/null
-#
-# Copyright (C) 2006-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/BuildKernel
- $(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.lzma
- mkimage -A mips -O linux -T kernel -C lzma -a 0x80002000 -e \
- 0x80002000 \
- -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \
- -d $(KDIR)/vmlinux.lzma $(KDIR)/uImage
-
- cp $(KDIR)/uImage $(BIN_DIR)/$(IMG_PREFIX)-uImage
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(1).image)
-endef
-
-define Image/Build
- cat $(KDIR)/uImage $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(1).image
- $(call Image/Build/$(1),$(1))
-endef
-
-
-$(eval $(call BuildImage))
+++ /dev/null
---- a/arch/mips/kernel/traps.c
-+++ b/arch/mips/kernel/traps.c
-@@ -1593,7 +1593,16 @@ void __cpuinit per_cpu_trap_init(void)
- if (cpu_has_mips_r2) {
- cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
- cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
-+ if (!cp0_compare_irq)
-+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
-+
- cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
-+ if (!cp0_perfcount_irq)
-+ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
-+
-+ if (arch_fixup_c0_irqs)
-+ arch_fixup_c0_irqs();
-+
- if (cp0_perfcount_irq == cp0_compare_irq)
- cp0_perfcount_irq = -1;
- } else {
---- a/arch/mips/include/asm/irq.h
-+++ b/arch/mips/include/asm/irq.h
-@@ -139,9 +139,11 @@ extern void free_irqno(unsigned int irq)
- * IE7. Since R2 their number has to be read from the c0_intctl register.
- */
- #define CP0_LEGACY_COMPARE_IRQ 7
-+#define CP0_LEGACY_PERFCNT_IRQ 7
-
- extern int cp0_compare_irq;
- extern int cp0_compare_irq_shift;
- extern int cp0_perfcount_irq;
-+extern void __weak arch_fixup_c0_irqs(void);
-
- #endif /* _ASM_IRQ_H */
+++ /dev/null
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -23,6 +23,22 @@
-
- #ifndef CONFIG_MIPS_MT_SMTC
-
-+/*
-+ * Compare interrupt can be routed and latched outside the core,
-+ * so a single execution hazard barrier may not be enough to give
-+ * it time to clear as seen in the Cause register. 4 time the
-+ * pipeline depth seems reasonably conservative, and empirically
-+ * works better in configurations with high CPU/bus clock ratios.
-+ */
-+
-+#define compare_change_hazard() \
-+ do { \
-+ irq_disable_hazard(); \
-+ irq_disable_hazard(); \
-+ irq_disable_hazard(); \
-+ irq_disable_hazard(); \
-+ } while (0)
-+
- static int mips_next_event(unsigned long delta,
- struct clock_event_device *evt)
- {
-@@ -32,6 +48,7 @@ static int mips_next_event(unsigned long
- cnt = read_c0_count();
- cnt += delta;
- write_c0_compare(cnt);
-+ compare_change_hazard();
- res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
- return res;
- }
+++ /dev/null
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -132,6 +132,7 @@ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
- obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
- octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
- obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o
-+obj-$(CONFIG_AMAZON_WDT) += amazon_wdt.o
-
- # PARISC Architecture
-
+++ /dev/null
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -120,6 +120,22 @@ config BCM63XX
- help
- Support for BCM63XX based boards
-
-+config AMAZON
-+ bool "Amazon support (EXPERIMENTAL)"
-+ depends on EXPERIMENTAL
-+ select DMA_NONCOHERENT
-+ select IRQ_CPU
-+ select CEVT_R4K
-+ select CSRC_R4K
-+ select SYS_HAS_CPU_MIPS32_R1
-+ select SYS_HAS_CPU_MIPS32_R2
-+ select HAVE_STD_PC_SERIAL_PORT
-+ select SYS_SUPPORTS_BIG_ENDIAN
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_HAS_EARLY_PRINTK
-+ select HW_HAS_PCI
-+ select SWAP_IO_SPACE
-+
- config MIPS_COBALT
- bool "Cobalt Server"
- select CEVT_R4K
-@@ -813,6 +829,7 @@ config NLM_XLP_BOARD
-
- endchoice
-
-+source "arch/mips/amazon/Kconfig"
- source "arch/mips/alchemy/Kconfig"
- source "arch/mips/ath79/Kconfig"
- source "arch/mips/bcm47xx/Kconfig"
---- a/arch/mips/Kbuild.platforms
-+++ b/arch/mips/Kbuild.platforms
-@@ -6,6 +6,7 @@ platforms += ath79
- platforms += bcm47xx
- platforms += bcm63xx
- platforms += cavium-octeon
-+platforms += amazon
- platforms += cobalt
- platforms += dec
- platforms += emma
---- /dev/null
-+++ b/arch/mips/amazon/Platform
-@@ -0,0 +1,7 @@
-+#
-+# Infineon AMAZON boards
-+#
-+platform-$(CONFIG_AMAZON) += amazon/
-+cflags-$(CONFIG_AMAZON) += \
-+ -I$(srctree)/arch/mips/include/asm/mach-amazon
-+load-$(CONFIG_AMAZON) := 0xffffffff80002000
+++ /dev/null
---- a/drivers/mtd/maps/Makefile
-+++ b/drivers/mtd/maps/Makefile
-@@ -57,3 +57,4 @@ obj-$(CONFIG_MTD_VMU) += vmu-flash.o
- obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o
- obj-$(CONFIG_MTD_LATCH_ADDR) += latch-addr-flash.o
- obj-$(CONFIG_MTD_LANTIQ) += lantiq-flash.o
-+obj-$(CONFIG_AMAZON_MTD) += amazon.o
+++ /dev/null
---- a/drivers/net/ethernet/Makefile
-+++ b/drivers/net/ethernet/Makefile
-@@ -74,3 +74,6 @@ obj-$(CONFIG_NET_VENDOR_TUNDRA) += tundr
- obj-$(CONFIG_NET_VENDOR_VIA) += via/
- obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/
- obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/
-+
-+obj-$(CONFIG_AMAZON_NET_SW) += amazon_sw.o
-+obj-$(CONFIG_ADM6996_SUPPORT) += admmod.o
+++ /dev/null
---- a/drivers/tty/serial/Makefile
-+++ b/drivers/tty/serial/Makefile
-@@ -78,3 +78,4 @@ obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o
- obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o
- obj-$(CONFIG_SERIAL_SIRFSOC) += sirfsoc_uart.o
- obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o
-+obj-$(CONFIG_AMAZON_ASC_UART) += amazon_asc.o
+++ /dev/null
---- a/drivers/mtd/chips/cfi_cmdset_0002.c
-+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
-@@ -1152,6 +1152,9 @@ static int __xipram do_write_oneword(str
- int retry_cnt = 0;
-
- adr += chip->start;
-+#ifdef CONFIG_AMAZON
-+ adr ^= 2;
-+#endif
-
- mutex_lock(&chip->mutex);
- ret = get_chip(map, chip, adr, FL_WRITING);
-@@ -1420,7 +1423,11 @@ static int __xipram do_write_buffer(stru
- z = 0;
- while(z < words * map_bankwidth(map)) {
- datum = map_word_load(map, buf);
-+#ifdef CONFIG_AMAZON
-+ map_write(map, datum, (adr + z) ^ 0x2);
-+#else
- map_write(map, datum, adr + z);
-+#endif
-
- z += map_bankwidth(map);
- buf += map_bankwidth(map);
-@@ -1665,6 +1672,9 @@ static int __xipram do_erase_oneblock(st
- int ret = 0;
-
- adr += chip->start;
-+#ifdef CONFIG_AMAZON
-+ adr ^= 2;
-+#endif
-
- mutex_lock(&chip->mutex);
- ret = get_chip(map, chip, adr, FL_ERASING);
-@@ -1793,6 +1803,10 @@ static int do_atmel_lock(struct map_info
- struct cfi_private *cfi = map->fldrv_priv;
- int ret;
-
-+#ifdef CONFIG_AMAZON
-+ adr ^= 2;
-+#endif
-+
- mutex_lock(&chip->mutex);
- ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
- if (ret)
-@@ -1828,6 +1842,10 @@ static int do_atmel_unlock(struct map_in
- struct cfi_private *cfi = map->fldrv_priv;
- int ret;
-
-+#ifdef CONFIG_AMAZON
-+ adr ^= 2;
-+#endif
-+
- mutex_lock(&chip->mutex);
- ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
- if (ret)
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=bcm53xx
-BOARDNAME:=Broadcom BCM47xx/53xx with ARM CPU
-FEATURES:=squashfs usb pci pcie gpio
-MAINTAINER:=Hauke Mehrtens <hauke@hauke-m.de>
-CPU_TYPE:=cortex-a9
-
-LINUX_VERSION:=3.10.49
-
-include $(INCLUDE_DIR)/target.mk
-
-define Target/Description
- Build firmware images for Broadcom based BCM47xx/53xx routers with ARM CPU, *not* MIPS.
-endef
-
-KERNELNAME:="zImage dtbs"
-
-DEFAULT_PACKAGES += swconfig
-
-$(eval $(call BuildTarget))
+++ /dev/null
-define Package/base-files/install-target
- rm -f $(1)/etc/config/network
-endef
+++ /dev/null
-#!/bin/sh
-#
-# Copyright (C) 2011 OpenWrt.org
-#
-
-[ -e /etc/config/network ] && exit 0
-
-touch /etc/config/network
-
-. /lib/functions/uci-defaults.sh
-
-ucidef_set_interface_loopback
-
-ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2"
-ucidef_add_switch "switch0" "1" "1"
-ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5t"
-ucidef_add_switch_vlan "switch0" "2" "4 5t"
-
-uci commit network
-
-exit 0
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_ARCH_BCM is not set
-CONFIG_ARCH_BCM_5301X=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-# CONFIG_ARCH_MULTI_V6 is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SUNXI is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARCH_VIRT is not set
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-# CONFIG_ARCH_WM8850 is not set
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GLOBAL_TIMER=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_B53=y
-# CONFIG_B53_MMAP_DRIVER is not set
-# CONFIG_B53_PHY_DRIVER is not set
-CONFIG_B53_SRAB_DRIVER=y
-CONFIG_BCMA=y
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_DEBUG=y
-CONFIG_BCMA_DRIVER_ARM=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BGMAC=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CACHE_PL310=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BCM_5301X=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/bcm53xx.S"
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_DEBUG_USER=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_WORK=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_LOCAL_TIMERS=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MPCORE_WATCHDOG is not set
-CONFIG_MTD_OF_PARTS=y
-# CONFIG_MTD_PHYSMAP_OF is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_STOP_MACHINE=y
-CONFIG_SWCONFIG=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_TEGRA_HOST1X is not set
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TREE_RCU=y
-CONFIG_UID16=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-# CONFIG_VFP is not set
-# CONFIG_XEN is not set
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM_5301X=y
-# CONFIG_ARCH_BCM_MOBILE is not set
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GLOBAL_TIMER=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_B53=y
-# CONFIG_B53_MMAP_DRIVER is not set
-# CONFIG_B53_PHY_DRIVER is not set
-CONFIG_B53_SRAB_DRIVER=y
-CONFIG_BCM47XX_NVRAM=y
-CONFIG_BCM53XX_SPROM=y
-CONFIG_BCMA=y
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_DEBUG=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_SOC=y
-# CONFIG_BCM_KONA_WDT is not set
-CONFIG_BGMAC=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CACHE_PL310=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BCM_5301X=y
-# CONFIG_DEBUG_BCM_KONA_UART is not set
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/pl01x.S"
-# CONFIG_DEBUG_LL_UART_8250 is not set
-# CONFIG_DEBUG_LL_UART_PL01X is not set
-# CONFIG_DEBUG_UART_8250 is not set
-CONFIG_DEBUG_UART_PHYS=0x18000300
-CONFIG_DEBUG_UART_PL01X=y
-CONFIG_DEBUG_UART_VIRT=0xf1000300
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_DEBUG_USER=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IOMMU_HELPER=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIGHT_HAVE_PCI=y
-# CONFIG_MLX5_CORE is not set
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_PHYSMAP_OF is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PCI_BCMA=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_STOP_MACHINE=y
-CONFIG_SWCONFIG=y
-CONFIG_SWIOTLB=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TREE_RCU=y
-CONFIG_UID16=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-# CONFIG_VFP is not set
-# CONFIG_XEN is not set
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-# CONFIG_ZBUD is not set
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/Prepare
- rm -f $(KDIR)/fs_mark
- echo -ne '\xde\xad\xc0\xde' > $(KDIR)/fs_mark
- $(call prepare_generic_squashfs,$(KDIR)/fs_mark)
-endef
-
-define Image/Build/Initramfs
- $(call Image/Build/Initramfs/Chk,bcm4708-netgear-r6250,U12H245T00_NETGEAR,2,initramfs)
-endef
-
-define Image/Build/Initramfs/Chk
- $(call Image/Build/Initramfs/DTB,$(1))
- $(STAGING_DIR_HOST)/bin/mkchkimg -o $(BIN_DIR)/openwrt-$(1)-$(4).chk -k $(KDIR)/$(IMG_PREFIX)-$(4)-$(1).trx -b $(2) -r $(3)
-endef
-
-define Image/Build/Initramfs/DTB
- $(call Image/Build/DTB,zImage-initramfs,$(1))
- $(STAGING_DIR_HOST)/bin/trx -o $(KDIR)/$(IMG_PREFIX)-initramfs-$(1).trx \
- -f $(KDIR)/zImage-initramfs-$(1).lzma
-endef
-
-define Image/Build/squashfs/DTB
- $(call Image/Build/DTB,zImage,$(1))
- $(STAGING_DIR_HOST)/bin/trx -o $(KDIR)/$(IMG_PREFIX)-squashfs-$(1).trx \
- -f $(KDIR)/zImage-$(1).lzma \
- -a 1024 -f $(KDIR)/root.squashfs -a 0x10000 -A $(KDIR)/fs_mark
-endef
-
-define Image/Build/squashfs/Chk
- $(call Image/Build/squashfs/DTB,$(1))
- $(STAGING_DIR_HOST)/bin/mkchkimg -o $(BIN_DIR)/openwrt-$(1)-$(4).chk -k $(KDIR)/$(IMG_PREFIX)-$(4)-$(1).trx -b $(2) -r $(3)
-endef
-
-define Image/Build/DTB
- rm -f $(KDIR)/$(1)-$(2).lzma
- rm -f $(KDIR)/$(1)-$(2).dts
- cat $(KDIR)/$(1) $(DTS_DIR)/$(2).dtb > $(KDIR)/$(1)-$(2).dts;
- $(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/$(1)-$(2).dts $(KDIR)/$(1)-$(2).lzma -d16
-endef
-
-define Image/Build
- $(call Image/Build/$(1),$(1))
- $(call Image/Build/squashfs/Chk,bcm4708-netgear-r6250,U12H245T00_NETGEAR,2,squashfs)
-endef
-
-
-$(eval $(call BuildImage))
+++ /dev/null
-From 5afd20a1eeef4db1d694d58931519f65e2003503 Mon Sep 17 00:00:00 2001
-From: Stuart Menefy <stuart.menefy@st.com>
-Date: Wed, 26 Jun 2013 12:48:38 +0100
-Subject: [PATCH 01/18] clocksource: arm_global_timer: Add ARM global timer
- support
-
-This is a simple driver for the global timer module found in the Cortex
-A9-MP cores from revision r1p0 onwards. This should be able to perform
-the functions of the system timer and the local timer in an SMP system.
-
-The global timer has the following features:
- The global timer is a 64-bit incrementing counter with an
-auto-incrementing feature. It continues incrementing after sending
-interrupts. The global timer is memory mapped in the private memory
-region.
- The global timer is accessible to all Cortex-A9 processors in the
-cluster. Each Cortex-A9 processor has a private 64-bit comparator that
-is used to assert a private interrupt when the global timer has reached
-the comparator value. All the Cortex-A9 processors in a design use the
-banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
-Controller as a Private Peripheral Interrupt. The global timer is
-clocked by PERIPHCLK.
-
-Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-CC: Arnd Bergmann <arnd@arndb.de>
-CC: Rob Herring <robherring2@gmail.com>
-CC: Linus Walleij <linus.walleij@linaro.org>
-CC: Will Deacon <will.deacon@arm.com>
-CC: Thomas Gleixner <tglx@linutronix.de>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- .../devicetree/bindings/arm/global_timer.txt | 24 ++
- drivers/clocksource/Kconfig | 13 +
- drivers/clocksource/Makefile | 1 +
- drivers/clocksource/arm_global_timer.c | 321 ++++++++++++++++++++
- 4 files changed, 359 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/arm/global_timer.txt
- create mode 100644 drivers/clocksource/arm_global_timer.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/arm/global_timer.txt
-@@ -0,0 +1,24 @@
-+
-+* ARM Global Timer
-+ Cortex-A9 are often associated with a per-core Global timer.
-+
-+** Timer node required properties:
-+
-+- compatible : Should be "arm,cortex-a9-global-timer"
-+ Driver supports versions r2p0 and above.
-+
-+- interrupts : One interrupt to each core
-+
-+- reg : Specify the base address and the size of the GT timer
-+ register window.
-+
-+- clocks : Should be phandle to a clock.
-+
-+Example:
-+
-+ timer@2c000600 {
-+ compatible = "arm,cortex-a9-global-timer";
-+ reg = <0x2c000600 0x20>;
-+ interrupts = <1 13 0xf01>;
-+ clocks = <&arm_periph_clk>;
-+ };
---- a/drivers/clocksource/Kconfig
-+++ b/drivers/clocksource/Kconfig
-@@ -67,6 +67,19 @@ config ARM_ARCH_TIMER
- bool
- select CLKSRC_OF if OF
-
-+config ARM_GLOBAL_TIMER
-+ bool
-+ select CLKSRC_OF if OF
-+ help
-+ This options enables support for the ARM global timer unit
-+
-+config CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-+ bool
-+ depends on ARM_GLOBAL_TIMER
-+ default y
-+ help
-+ Use ARM global timer clock source as sched_clock
-+
- config CLKSRC_METAG_GENERIC
- def_bool y if METAG
- help
---- a/drivers/clocksource/Makefile
-+++ b/drivers/clocksource/Makefile
-@@ -28,4 +28,5 @@ obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exyno
- obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
-
- obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
-+obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
- obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o
---- /dev/null
-+++ b/drivers/clocksource/arm_global_timer.c
-@@ -0,0 +1,321 @@
-+/*
-+ * drivers/clocksource/arm_global_timer.c
-+ *
-+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
-+ * Author: Stuart Menefy <stuart.menefy@st.com>
-+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/clocksource.h>
-+#include <linux/clockchips.h>
-+#include <linux/cpu.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/of.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_address.h>
-+#include <asm/sched_clock.h>
-+
-+#include <asm/cputype.h>
-+
-+#define GT_COUNTER0 0x00
-+#define GT_COUNTER1 0x04
-+
-+#define GT_CONTROL 0x08
-+#define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */
-+#define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */
-+#define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */
-+#define GT_CONTROL_AUTO_INC BIT(3) /* banked */
-+
-+#define GT_INT_STATUS 0x0c
-+#define GT_INT_STATUS_EVENT_FLAG BIT(0)
-+
-+#define GT_COMP0 0x10
-+#define GT_COMP1 0x14
-+#define GT_AUTO_INC 0x18
-+
-+/*
-+ * We are expecting to be clocked by the ARM peripheral clock.
-+ *
-+ * Note: it is assumed we are using a prescaler value of zero, so this is
-+ * the units for all operations.
-+ */
-+static void __iomem *gt_base;
-+static unsigned long gt_clk_rate;
-+static int gt_ppi;
-+static struct clock_event_device __percpu *gt_evt;
-+
-+/*
-+ * To get the value from the Global Timer Counter register proceed as follows:
-+ * 1. Read the upper 32-bit timer counter register
-+ * 2. Read the lower 32-bit timer counter register
-+ * 3. Read the upper 32-bit timer counter register again. If the value is
-+ * different to the 32-bit upper value read previously, go back to step 2.
-+ * Otherwise the 64-bit timer counter value is correct.
-+ */
-+static u64 gt_counter_read(void)
-+{
-+ u64 counter;
-+ u32 lower;
-+ u32 upper, old_upper;
-+
-+ upper = readl_relaxed(gt_base + GT_COUNTER1);
-+ do {
-+ old_upper = upper;
-+ lower = readl_relaxed(gt_base + GT_COUNTER0);
-+ upper = readl_relaxed(gt_base + GT_COUNTER1);
-+ } while (upper != old_upper);
-+
-+ counter = upper;
-+ counter <<= 32;
-+ counter |= lower;
-+ return counter;
-+}
-+
-+/**
-+ * To ensure that updates to comparator value register do not set the
-+ * Interrupt Status Register proceed as follows:
-+ * 1. Clear the Comp Enable bit in the Timer Control Register.
-+ * 2. Write the lower 32-bit Comparator Value Register.
-+ * 3. Write the upper 32-bit Comparator Value Register.
-+ * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
-+ */
-+static void gt_compare_set(unsigned long delta, int periodic)
-+{
-+ u64 counter = gt_counter_read();
-+ unsigned long ctrl;
-+
-+ counter += delta;
-+ ctrl = GT_CONTROL_TIMER_ENABLE;
-+ writel(ctrl, gt_base + GT_CONTROL);
-+ writel(lower_32_bits(counter), gt_base + GT_COMP0);
-+ writel(upper_32_bits(counter), gt_base + GT_COMP1);
-+
-+ if (periodic) {
-+ writel(delta, gt_base + GT_AUTO_INC);
-+ ctrl |= GT_CONTROL_AUTO_INC;
-+ }
-+
-+ ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
-+ writel(ctrl, gt_base + GT_CONTROL);
-+}
-+
-+static void gt_clockevent_set_mode(enum clock_event_mode mode,
-+ struct clock_event_device *clk)
-+{
-+ unsigned long ctrl;
-+
-+ switch (mode) {
-+ case CLOCK_EVT_MODE_PERIODIC:
-+ gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
-+ break;
-+ case CLOCK_EVT_MODE_ONESHOT:
-+ case CLOCK_EVT_MODE_UNUSED:
-+ case CLOCK_EVT_MODE_SHUTDOWN:
-+ ctrl = readl(gt_base + GT_CONTROL);
-+ ctrl &= ~(GT_CONTROL_COMP_ENABLE |
-+ GT_CONTROL_IRQ_ENABLE | GT_CONTROL_AUTO_INC);
-+ writel(ctrl, gt_base + GT_CONTROL);
-+ break;
-+ default:
-+ break;
-+ }
-+}
-+
-+static int gt_clockevent_set_next_event(unsigned long evt,
-+ struct clock_event_device *unused)
-+{
-+ gt_compare_set(evt, 0);
-+ return 0;
-+}
-+
-+static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
-+{
-+ struct clock_event_device *evt = dev_id;
-+
-+ if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
-+ GT_INT_STATUS_EVENT_FLAG))
-+ return IRQ_NONE;
-+
-+ /**
-+ * ERRATA 740657( Global Timer can send 2 interrupts for
-+ * the same event in single-shot mode)
-+ * Workaround:
-+ * Either disable single-shot mode.
-+ * Or
-+ * Modify the Interrupt Handler to avoid the
-+ * offending sequence. This is achieved by clearing
-+ * the Global Timer flag _after_ having incremented
-+ * the Comparator register value to a higher value.
-+ */
-+ if (evt->mode == CLOCK_EVT_MODE_ONESHOT)
-+ gt_compare_set(ULONG_MAX, 0);
-+
-+ writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
-+ evt->event_handler(evt);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int __cpuinit gt_clockevents_init(struct clock_event_device *clk)
-+{
-+ int cpu = smp_processor_id();
-+
-+ clk->name = "arm_global_timer";
-+ clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
-+ clk->set_mode = gt_clockevent_set_mode;
-+ clk->set_next_event = gt_clockevent_set_next_event;
-+ clk->cpumask = cpumask_of(cpu);
-+ clk->rating = 300;
-+ clk->irq = gt_ppi;
-+ clockevents_config_and_register(clk, gt_clk_rate,
-+ 1, 0xffffffff);
-+ enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
-+ return 0;
-+}
-+
-+static void gt_clockevents_stop(struct clock_event_device *clk)
-+{
-+ gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
-+ disable_percpu_irq(clk->irq);
-+}
-+
-+static cycle_t gt_clocksource_read(struct clocksource *cs)
-+{
-+ return gt_counter_read();
-+}
-+
-+static struct clocksource gt_clocksource = {
-+ .name = "arm_global_timer",
-+ .rating = 300,
-+ .read = gt_clocksource_read,
-+ .mask = CLOCKSOURCE_MASK(64),
-+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-+};
-+
-+#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-+static u32 notrace gt_sched_clock_read(void)
-+{
-+ return gt_counter_read();
-+}
-+#endif
-+
-+static void __init gt_clocksource_init(void)
-+{
-+ writel(0, gt_base + GT_CONTROL);
-+ writel(0, gt_base + GT_COUNTER0);
-+ writel(0, gt_base + GT_COUNTER1);
-+ /* enables timer on all the cores */
-+ writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
-+
-+#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-+ setup_sched_clock(gt_sched_clock_read, 32, gt_clk_rate);
-+#endif
-+ clocksource_register_hz(>_clocksource, gt_clk_rate);
-+}
-+
-+static int __cpuinit gt_cpu_notify(struct notifier_block *self,
-+ unsigned long action, void *hcpu)
-+{
-+ switch (action & ~CPU_TASKS_FROZEN) {
-+ case CPU_STARTING:
-+ gt_clockevents_init(this_cpu_ptr(gt_evt));
-+ break;
-+ case CPU_DYING:
-+ gt_clockevents_stop(this_cpu_ptr(gt_evt));
-+ break;
-+ }
-+
-+ return NOTIFY_OK;
-+}
-+static struct notifier_block gt_cpu_nb __cpuinitdata = {
-+ .notifier_call = gt_cpu_notify,
-+};
-+
-+static void __init global_timer_of_register(struct device_node *np)
-+{
-+ struct clk *gt_clk;
-+ int err = 0;
-+
-+ /*
-+ * In r2p0 the comparators for each processor with the global timer
-+ * fire when the timer value is greater than or equal to. In previous
-+ * revisions the comparators fired when the timer value was equal to.
-+ */
-+ if ((read_cpuid_id() & 0xf0000f) < 0x200000) {
-+ pr_warn("global-timer: non support for this cpu version.\n");
-+ return;
-+ }
-+
-+ gt_ppi = irq_of_parse_and_map(np, 0);
-+ if (!gt_ppi) {
-+ pr_warn("global-timer: unable to parse irq\n");
-+ return;
-+ }
-+
-+ gt_base = of_iomap(np, 0);
-+ if (!gt_base) {
-+ pr_warn("global-timer: invalid base address\n");
-+ return;
-+ }
-+
-+ gt_clk = of_clk_get(np, 0);
-+ if (!IS_ERR(gt_clk)) {
-+ err = clk_prepare_enable(gt_clk);
-+ if (err)
-+ goto out_unmap;
-+ } else {
-+ pr_warn("global-timer: clk not found\n");
-+ err = -EINVAL;
-+ goto out_unmap;
-+ }
-+
-+ gt_clk_rate = clk_get_rate(gt_clk);
-+ gt_evt = alloc_percpu(struct clock_event_device);
-+ if (!gt_evt) {
-+ pr_warn("global-timer: can't allocate memory\n");
-+ err = -ENOMEM;
-+ goto out_clk;
-+ }
-+
-+ err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
-+ "gt", gt_evt);
-+ if (err) {
-+ pr_warn("global-timer: can't register interrupt %d (%d)\n",
-+ gt_ppi, err);
-+ goto out_free;
-+ }
-+
-+ err = register_cpu_notifier(>_cpu_nb);
-+ if (err) {
-+ pr_warn("global-timer: unable to register cpu notifier.\n");
-+ goto out_irq;
-+ }
-+
-+ /* Immediately configure the timer on the boot CPU */
-+ gt_clocksource_init();
-+ gt_clockevents_init(this_cpu_ptr(gt_evt));
-+
-+ return;
-+
-+out_irq:
-+ free_percpu_irq(gt_ppi, gt_evt);
-+out_free:
-+ free_percpu(gt_evt);
-+out_clk:
-+ clk_disable_unprepare(gt_clk);
-+out_unmap:
-+ iounmap(gt_base);
-+ WARN(err, "ARM Global timer register failed (%d)\n", err);
-+}
-+
-+/* Only tested on r2p2 and r3p0 */
-+CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
-+ global_timer_of_register);
+++ /dev/null
-bcm53xx: initial support for the BCM5301/BCM470X SoC
- with ARM CPU
-
-This patch adds support for the BCM5301/BCM470X SoCs with an ARM CPU.
-Currently just booting to a shell is working and nothing else, no
-Ethernet, wifi, flash, ...
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- arch/arm/Kconfig | 2 +
- arch/arm/Kconfig.debug | 5 ++
- arch/arm/Makefile | 1 +
- arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/bcm5301-netgear-r6250.dts | 20 +++++++
- arch/arm/boot/dts/bcm5301.dtsi | 83 +++++++++++++++++++++++++++
- arch/arm/include/debug/bcm53xx.S | 19 ++++++
- arch/arm/mach-bcm53xx/Kconfig | 15 +++++
- arch/arm/mach-bcm53xx/Makefile | 1 +
- arch/arm/mach-bcm53xx/bcm53xx.c | 69 ++++++++++++++++++++++
- 10 files changed, 216 insertions(+)
- create mode 100644 arch/arm/boot/dts/bcm5301-netgear-r6250.dts
- create mode 100644 arch/arm/boot/dts/bcm5301.dtsi
- create mode 100644 arch/arm/include/debug/bcm53xx.S
- create mode 100644 arch/arm/mach-bcm53xx/Kconfig
- create mode 100644 arch/arm/mach-bcm53xx/Makefile
- create mode 100644 arch/arm/mach-bcm53xx/bcm53xx.c
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -922,6 +922,8 @@ source "arch/arm/mach-bcm/Kconfig"
-
- source "arch/arm/mach-bcm2835/Kconfig"
-
-+source "arch/arm/mach-bcm53xx/Kconfig"
-+
- source "arch/arm/mach-clps711x/Kconfig"
-
- source "arch/arm/mach-cns3xxx/Kconfig"
---- a/arch/arm/Kconfig.debug
-+++ b/arch/arm/Kconfig.debug
-@@ -93,6 +93,10 @@ choice
- bool "Kernel low-level debugging on BCM2835 PL011 UART"
- depends on ARCH_BCM2835
-
-+ config DEBUG_BCM_5301X
-+ bool "Kernel low-level debugging on BCM53XX UART1"
-+ depends on ARCH_BCM_5301X
-+
- config DEBUG_CLPS711X_UART1
- bool "Kernel low-level debugging messages via UART1"
- depends on ARCH_CLPS711X
-@@ -620,6 +624,7 @@ endchoice
- config DEBUG_LL_INCLUDE
- string
- default "debug/bcm2835.S" if DEBUG_BCM2835
-+ default "debug/bcm53xx.S" if DEBUG_BCM_5301X
- default "debug/cns3xxx.S" if DEBUG_CNS3XXX
- default "debug/exynos.S" if DEBUG_EXYNOS_UART
- default "debug/highbank.S" if DEBUG_HIGHBANK_UART
---- a/arch/arm/Makefile
-+++ b/arch/arm/Makefile
-@@ -145,6 +145,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x0020
- machine-$(CONFIG_ARCH_AT91) += at91
- machine-$(CONFIG_ARCH_BCM) += bcm
- machine-$(CONFIG_ARCH_BCM2835) += bcm2835
-+machine-$(CONFIG_ARCH_BCM_5301X) += bcm53xx
- machine-$(CONFIG_ARCH_CLPS711X) += clps711x
- machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
- machine-$(CONFIG_ARCH_DAVINCI) += davinci
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -209,6 +209,7 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07
- wm8650-mid.dtb \
- wm8850-w70v2.dtb
- dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
-+dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
-
- targets += dtbs
- targets += $(dtb-y)
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
-@@ -0,0 +1,35 @@
-+/*
-+ * Broadcom BCM470X / BCM5301X arm platform code.
-+ * DTS for Netgear R6250 V1
-+ *
-+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm4708.dtsi"
-+
-+/ {
-+ compatible = "netgear,r6250v1", "brcm,bcm4708";
-+ model = "Netgear R6250 V1 (BCM4708)";
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200";
-+ };
-+
-+ memory {
-+ reg = <0x00000000 0x08000000>;
-+ };
-+
-+ chipcommonA {
-+ uart0: serial@0300 {
-+ status = "okay";
-+ };
-+
-+ uart1: serial@0400 {
-+ status = "okay";
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm4708.dtsi
-@@ -0,0 +1,34 @@
-+/*
-+ * Broadcom BCM470X / BCM5301X ARM platform code.
-+ * DTS for BCM4708 SoC.
-+ *
-+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include "bcm5301x.dtsi"
-+
-+/ {
-+ compatible = "brcm,bcm4708";
-+
-+ cpus {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ cpu@0 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a9";
-+ next-level-cache = <&L2>;
-+ reg = <0x0>;
-+ };
-+
-+ cpu@1 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a9";
-+ next-level-cache = <&L2>;
-+ reg = <0x1>;
-+ };
-+ };
-+
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm5301x.dtsi
-@@ -0,0 +1,95 @@
-+/*
-+ * Broadcom BCM470X / BCM5301X ARM platform code.
-+ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
-+ * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
-+ *
-+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include "skeleton.dtsi"
-+
-+/ {
-+ interrupt-parent = <&gic>;
-+
-+ chipcommonA {
-+ compatible = "simple-bus";
-+ ranges = <0x00000000 0x18000000 0x00001000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ uart0: serial@0300 {
-+ compatible = "ns16550";
-+ reg = <0x0300 0x100>;
-+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-frequency = <100000000>;
-+ status = "disabled";
-+ };
-+
-+ uart1: serial@0400 {
-+ compatible = "ns16550";
-+ reg = <0x0400 0x100>;
-+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-frequency = <100000000>;
-+ status = "disabled";
-+ };
-+ };
-+
-+ mpcore {
-+ compatible = "simple-bus";
-+ ranges = <0x00000000 0x19020000 0x00003000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ scu@0000 {
-+ compatible = "arm,cortex-a9-scu";
-+ reg = <0x0000 0x100>;
-+ };
-+
-+ timer@0200 {
-+ compatible = "arm,cortex-a9-global-timer";
-+ reg = <0x0200 0x100>;
-+ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clk_periph>;
-+ };
-+
-+ local-timer@0600 {
-+ compatible = "arm,cortex-a9-twd-timer";
-+ reg = <0x0600 0x100>;
-+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clk_periph>;
-+ };
-+
-+ gic: interrupt-controller@1000 {
-+ compatible = "arm,cortex-a9-gic";
-+ #interrupt-cells = <3>;
-+ #address-cells = <0>;
-+ interrupt-controller;
-+ reg = <0x1000 0x1000>,
-+ <0x0100 0x100>;
-+ };
-+
-+ L2: cache-controller@2000 {
-+ compatible = "arm,pl310-cache";
-+ reg = <0x2000 0x1000>;
-+ cache-unified;
-+ cache-level = <2>;
-+ };
-+ };
-+
-+ clocks {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ /* As long as we do not have a real clock driver us this
-+ * fixed clock */
-+ clk_periph: periph {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <400000000>;
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm/include/debug/bcm53xx.S
-@@ -0,0 +1,19 @@
-+/*
-+ * Macros used for EARLY_PRINTK, in low-level UART debug console
-+ *
-+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#define BCM53XX_UART1_PHYS 0x18000300
-+#define BCM53XX_UART1_VIRT 0xf1000300
-+#define BCM53XX_UART1_SH 0
-+
-+ .macro addruart, rp, rv, tmp
-+ ldr \rp, =BCM53XX_UART1_PHYS @ MMU off, Physical
-+ ldr \rv, =BCM53XX_UART1_VIRT @ MMU on, Virtual
-+ .endm
-+
-+#define UART_SHIFT BCM53XX_UART1_SH
-+#include <asm/hardware/debug-8250.S>
---- /dev/null
-+++ b/arch/arm/mach-bcm53xx/Kconfig
-@@ -0,0 +1,25 @@
-+config ARCH_BCM_5301X
-+ bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
-+ depends on MMU
-+ select ARM_GIC
-+ select CACHE_L2X0
-+ select HAVE_ARM_SCU if SMP
-+ select HAVE_ARM_TWD if SMP
-+ select HAVE_SMP
-+ select COMMON_CLK
-+ select GENERIC_CLOCKEVENTS
-+ select ARM_GLOBAL_TIMER
-+ select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-+ select MIGHT_HAVE_PCI
-+ help
-+ Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
-+
-+ This is a network SoC line mostly used in home routers and
-+ wifi access points.
-+ This inclused the following SoC: BCM53010, BCM53011, BCM53012,
-+ BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
-+ BCM4708 and BCM4709.
-+
-+ Do not confuse this with the BCM4760 which is a totally
-+ different SoC or with the older BCM47XX and BCM53XX based
-+ network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
---- /dev/null
-+++ b/arch/arm/mach-bcm53xx/Makefile
-@@ -0,0 +1 @@
-+obj-y += bcm53xx.o
---- /dev/null
-+++ b/arch/arm/mach-bcm53xx/bcm53xx.c
-@@ -0,0 +1,70 @@
-+/*
-+ * Broadcom BCM470X / BCM5301X ARM platform code.
-+ *
-+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+#include <linux/of_platform.h>
-+#include <linux/clocksource.h>
-+#include <linux/clk-provider.h>
-+#include <asm/hardware/cache-l2x0.h>
-+
-+#include <asm/mach/arch.h>
-+#include <asm/siginfo.h>
-+#include <asm/signal.h>
-+
-+
-+static bool first_fault = true;
-+
-+static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
-+ struct pt_regs *regs)
-+{
-+ if (fsr == 0x1c06 && first_fault) {
-+ first_fault = false;
-+
-+ /*
-+ * These faults with code 0x1c06 happens for no good reason,
-+ * possibly left over from the CFE boot loader.
-+ */
-+ pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n",
-+ addr, fsr);
-+
-+ /* Returning non-zero causes fault display and panic */
-+ return 0;
-+ }
-+
-+ /* Others should cause a fault */
-+ return 1;
-+}
-+
-+static void __init bcm5301x_init_early(void)
-+{
-+ /* Install our hook */
-+ hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
-+ "imprecise external abort");
-+}
-+
-+static void __init bcm5301x_timer_init(void)
-+{
-+ of_clk_init(NULL);
-+ clocksource_of_init();
-+}
-+
-+static void __init bcm5301x_dt_init(void)
-+{
-+ l2x0_of_init(0, ~0UL);
-+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-+}
-+
-+static const char __initconst *bcm5301x_dt_compat[] = {
-+ "brcm,bcm4708",
-+ NULL,
-+};
-+
-+DT_MACHINE_START(BCM5301X, "BCM5301X")
-+ .init_early = bcm5301x_init_early,
-+ .init_time = bcm5301x_timer_init,
-+ .init_machine = bcm5301x_dt_init,
-+ .dt_compat = bcm5301x_dt_compat,
-+MACHINE_END
+++ /dev/null
-From 22b90bcf616578abe09845c72317ce53312f7faf Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sat, 25 Jan 2014 17:03:07 +0100
-Subject: [PATCH 8/8] ARM: BCM5301X: register bcma bus
-
----
- arch/arm/boot/dts/bcm4708.dtsi | 43 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 43 insertions(+)
-
---- a/arch/arm/boot/dts/bcm4708.dtsi
-+++ b/arch/arm/boot/dts/bcm4708.dtsi
-@@ -31,4 +31,47 @@
- };
- };
-
-+ aix@18000000 {
-+ compatible = "brcm,bus-aix";
-+ reg = <0x18000000 0x1000>;
-+ ranges = <0x00000000 0x18000000 0x00100000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ usb2@0 {
-+ compatible = "brcm,northstar-usb2";
-+ reg = <0x18021000 0x1000>;
-+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ usb3@0 {
-+ compatible = "brcm,northstar-usb3";
-+ reg = <0x18023000 0x1000>;
-+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ gmac@0 {
-+ compatible = "brcm,northstar-gmac";
-+ reg = <0x18024000 0x1000>;
-+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ gmac@1 {
-+ compatible = "brcm,northstar-gmac";
-+ reg = <0x18025000 0x1000>;
-+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ gmac@2 {
-+ compatible = "brcm,northstar-gmac";
-+ reg = <0x18026000 0x1000>;
-+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ gmac@3 {
-+ compatible = "brcm,northstar-gmac";
-+ reg = <0x18027000 0x1000>;
-+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+ };
- };
+++ /dev/null
-From c046c19fc8f1af7cf253fea5b0253143c159948a Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Mon, 6 Jan 2014 23:29:15 +0100
-Subject: [PATCH 6/8] bcma: register bcma as device tree driver
-
-This driver is used by the bcm53xx ARM SoC code.Now it is possible to
-give the address of the chipcommon core in device tree.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- drivers/bcma/host_soc.c | 70 +++++++++++++++++++++++++++++++++++++++++++++
- include/linux/bcma/bcma.h | 2 ++
- 2 files changed, 72 insertions(+)
-
---- a/drivers/bcma/host_soc.c
-+++ b/drivers/bcma/host_soc.c
-@@ -7,6 +7,9 @@
-
- #include "bcma_private.h"
- #include "scan.h"
-+#include <linux/slab.h>
-+#include <linux/module.h>
-+#include <linux/of_address.h>
- #include <linux/bcma/bcma.h>
- #include <linux/bcma/bcma_soc.h>
-
-@@ -173,6 +176,7 @@ int __init bcma_host_soc_register(struct
- /* Host specific */
- bus->hosttype = BCMA_HOSTTYPE_SOC;
- bus->ops = &bcma_host_soc_ops;
-+ bus->host_pdev = NULL;
-
- /* Register */
- err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
-@@ -181,3 +185,69 @@ int __init bcma_host_soc_register(struct
-
- return err;
- }
-+
-+#ifdef CONFIG_OF
-+static int bcma_host_soc_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct device_node *np = dev->of_node;
-+ struct bcma_bus *bus;
-+ int err;
-+
-+ /* Alloc */
-+ bus = devm_kzalloc(dev, sizeof(*bus), GFP_KERNEL);
-+ if (!bus)
-+ return -ENOMEM;
-+
-+ /* Map MMIO */
-+ bus->mmio = of_iomap(np, 0);
-+ if (!bus->mmio)
-+ return -ENOMEM;
-+
-+ /* Host specific */
-+ bus->hosttype = BCMA_HOSTTYPE_SOC;
-+ bus->ops = &bcma_host_soc_ops;
-+ bus->host_pdev = pdev;
-+
-+ /* Register */
-+ err = bcma_bus_register(bus);
-+ if (err)
-+ goto err_unmap_mmio;
-+
-+ platform_set_drvdata(pdev, bus);
-+
-+ return err;
-+
-+err_unmap_mmio:
-+ iounmap(bus->mmio);
-+ return err;
-+}
-+
-+static int bcma_host_soc_remove(struct platform_device *pdev)
-+{
-+ struct bcma_bus *bus = platform_get_drvdata(pdev);
-+
-+ bcma_bus_unregister(bus);
-+ iounmap(bus->mmio);
-+ platform_set_drvdata(pdev, NULL);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id bcma_host_soc_of_match[] = {
-+ { .compatible = "brcm,bus-aix", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, bcma_host_soc_of_match);
-+
-+static struct platform_driver bcma_host_soc_driver = {
-+ .driver = {
-+ .name = "bcma-host-soc",
-+ .owner = THIS_MODULE,
-+ .of_match_table = bcma_host_soc_of_match,
-+ },
-+ .probe = bcma_host_soc_probe,
-+ .remove = bcma_host_soc_remove,
-+};
-+module_platform_driver(bcma_host_soc_driver);
-+#endif /* CONFIG_OF */
---- a/include/linux/bcma/bcma.h
-+++ b/include/linux/bcma/bcma.h
-@@ -322,6 +322,8 @@ struct bcma_bus {
- struct pci_dev *host_pci;
- /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
- struct sdio_func *host_sdio;
-+ /* Pointer to platform device (only for BCMA_HOSTTYPE_SOC) */
-+ struct platform_device *host_pdev;
- };
-
- struct bcma_chipinfo chipinfo;
+++ /dev/null
-From 06a21484198df9a4d34fe5062878d3bf4fc14340 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Thu, 9 Jan 2014 19:40:14 +0100
-Subject: [PATCH 7/8] bcma: get irqs from dt
-
----
- drivers/bcma/main.c | 42 +++++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 41 insertions(+), 1 deletion(-)
-
---- a/drivers/bcma/main.c
-+++ b/drivers/bcma/main.c
-@@ -10,6 +10,8 @@
- #include <linux/platform_device.h>
- #include <linux/bcma/bcma.h>
- #include <linux/slab.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_address.h>
-
- MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
- MODULE_LICENSE("GPL");
-@@ -111,6 +113,38 @@ static void bcma_release_core_dev(struct
- kfree(core);
- }
-
-+static struct device_node *bcma_of_find_child_device(struct platform_device *parent,
-+ struct bcma_device *core)
-+{
-+ struct device_node *node;
-+ u64 size;
-+ const __be32 *reg;
-+
-+ if (!parent || !parent->dev.of_node)
-+ return NULL;
-+
-+ for_each_child_of_node(parent->dev.of_node, node) {
-+ reg = of_get_address(node, 0, &size, 0);
-+ if (!reg)
-+ continue;
-+ if (be32_to_cpup(reg) == core->addr)
-+ return node;
-+ }
-+ return NULL;
-+}
-+
-+static void bcma_of_fill_device(struct platform_device *parent,
-+ struct bcma_device *core)
-+{
-+ struct device_node *node;
-+
-+ node = bcma_of_find_child_device(parent, core);
-+ if (!node)
-+ return;
-+ core->dev.of_node = node;
-+ core->irq = irq_of_parse_and_map(node, 0);
-+}
-+
- static int bcma_register_cores(struct bcma_bus *bus)
- {
- struct bcma_device *core;
-@@ -146,7 +180,13 @@ static int bcma_register_cores(struct bc
- break;
- case BCMA_HOSTTYPE_SOC:
- core->dev.dma_mask = &core->dev.coherent_dma_mask;
-- core->dma_dev = &core->dev;
-+ if (bus->host_pdev) {
-+ core->dma_dev = &bus->host_pdev->dev;
-+ core->dev.parent = &bus->host_pdev->dev;
-+ bcma_of_fill_device(bus->host_pdev, core);
-+ } else {
-+ core->dma_dev = &core->dev;
-+ }
- break;
- case BCMA_HOSTTYPE_SDIO:
- break;
+++ /dev/null
-These are some hackish patches to make the Ethernet driver work somehow
-on this arm core.
-The flash driver is not working, so we removed the nvram reading, this
-should be changed after we have a flash driver.
-The mdelay(1) is a ugly workaround for this arm chip, this seams to be a dma problem.
-
-The PHY says it is not connected by default, just ignore it.
-
---- a/drivers/net/ethernet/broadcom/Kconfig
-+++ b/drivers/net/ethernet/broadcom/Kconfig
-@@ -132,7 +132,7 @@ config BNX2X_SRIOV
-
- config BGMAC
- tristate "BCMA bus GBit core support"
-- depends on BCMA_HOST_SOC && HAS_DMA && BCM47XX
-+ depends on BCMA_HOST_SOC && HAS_DMA
- select PHYLIB
- ---help---
- This driver supports GBit MAC and BCM4706 GBit MAC cores on BCMA bus.
---- a/drivers/net/ethernet/broadcom/bgmac.c
-+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -17,7 +17,11 @@
- #include <linux/interrupt.h>
- #include <linux/dma-mapping.h>
- #include <linux/platform_data/b53.h>
-+#ifdef CONFIG_BCM47XX
- #include <bcm47xx_nvram.h>
-+#else
-+#define bcm47xx_nvram_getenv(a, b, c) -1
-+#endif
-
- static const struct bcma_device_id bgmac_bcma_tbl[] = {
- BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
-@@ -1452,7 +1456,7 @@ static int bgmac_probe(struct bcma_devic
- int err;
-
- /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
-- if (core->core_unit > 1) {
-+ if (core->core_unit > 0) {
- pr_err("Unsupported core_unit %d\n", core->core_unit);
- return -ENOTSUPP;
- }
-@@ -1487,8 +1491,7 @@ static int bgmac_probe(struct bcma_devic
- }
- bgmac->cmn = core->bus->drv_gmac_cmn.core;
-
-- bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
-- sprom->et0phyaddr;
-+ bgmac->phyaddr = BGMAC_PHY_NOREGS; // core->core_unit ? sprom->et1phyaddr : sprom->et0phyaddr;
- bgmac->phyaddr &= BGMAC_PHY_MASK;
- if (bgmac->phyaddr == BGMAC_PHY_MASK) {
- bgmac_err(bgmac, "No PHY found\n");
-@@ -1540,8 +1543,7 @@ static int bgmac_probe(struct bcma_devic
- /* TODO: reset the external phy. Specs are needed */
- bgmac_phy_reset(bgmac);
-
-- bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
-- BGMAC_BFL_ENETROBO);
-+ bgmac->has_robosw = 1;
- if (bgmac->has_robosw)
- bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
-
---- a/drivers/net/phy/phy_device.c
-+++ b/drivers/net/phy/phy_device.c
-@@ -814,7 +814,7 @@ int genphy_update_link(struct phy_device
- return status;
-
- if ((status & BMSR_LSTATUS) == 0)
-- phydev->link = 0;
-+ phydev->link = 1;
- else
- phydev->link = 1;
-
+++ /dev/null
-From 5b293ebe757213993ae93b6cbbf5e1d09b75ac2f Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Tue, 4 Feb 2014 00:01:43 +0100
-Subject: [PATCH 1/3] ARM: BCM5301X: initial support for the BCM5301X/BCM470X
- SoCs with ARM CPU
-
-This patch adds support for the BCM5301X/BCM470X SoCs with an ARM CPUs.
-Currently just booting to a shell is working and nothing else, no
-Ethernet, wifi, flash, ...
-I have some pending patches to make Ethernet work for this device.
-Mostly device tree support for bcma is missing.
-
-This SoC is used in small office and home router with Broadcom SoCs
-it's internal name is Northstar. This code should support the BCM4707,
-BCM4708, BCM4709, BCM53010, BCM53011 and BCM53012 SoC. It uses one or
-two ARM Cortex A9 Cores, some highlights are 2 PCIe 2.0 controllers,
-4 Gigabit Ethernet MACs and a USB 3.0 host controller.
-
-This SoC uses a dual core CPU, but this is currently not implemented.
-More information about this SoC can be found here:
-http://www.anandtech.com/show/5925/broadcom-announces-bcm4708x-and-bcm5301x-socs-for-80211ac-routers
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Acked-by: Christian Daudt <bcm@fixthebug.org>
-Signed-off-by: Matt Porter <mporter@linaro.org>
----
- Documentation/devicetree/bindings/arm/bcm4708.txt | 8 ++++++
- MAINTAINERS | 8 ++++++
- arch/arm/configs/multi_v7_defconfig | 1 +
- arch/arm/mach-bcm/Kconfig | 26 +++++++++++++++++++
- arch/arm/mach-bcm/Makefile | 1 +
- arch/arm/mach-bcm/bcm_5301x.c | 28 +++++++++++++++++++++
- 6 files changed, 72 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/arm/bcm4708.txt
- create mode 100644 arch/arm/mach-bcm/bcm_5301x.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/arm/bcm4708.txt
-@@ -0,0 +1,8 @@
-+Broadcom BCM4708 device tree bindings
-+-------------------------------------------
-+
-+Boards with the BCM4708 SoC shall have the following properties:
-+
-+Required root node property:
-+
-+compatible = "brcm,bcm4708";
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -1883,6 +1883,14 @@ F: arch/arm/boot/dts/bcm2835*
- F: arch/arm/configs/bcm2835_defconfig
- F: drivers/*/*bcm2835*
-
-+BROADCOM BCM5301X ARM ARCHICTURE
-+M: Hauke Mehrtens <hauke@hauke-m.de>
-+L: linux-arm-kernel@lists.infradead.org
-+S: Maintained
-+F: arch/arm/mach-bcm/bcm_5301x.c
-+F: arch/arm/boot/dts/bcm5301x.dtsi
-+F: arch/arm/boot/dts/bcm470*
-+
- BROADCOM TG3 GIGABIT ETHERNET DRIVER
- M: Nithin Nayak Sujir <nsujir@broadcom.com>
- M: Michael Chan <mchan@broadcom.com>
---- a/arch/arm/configs/multi_v7_defconfig
-+++ b/arch/arm/configs/multi_v7_defconfig
-@@ -11,6 +11,7 @@ CONFIG_ARCH_MVEBU=y
- CONFIG_MACH_ARMADA_370=y
- CONFIG_MACH_ARMADA_XP=y
- CONFIG_ARCH_BCM=y
-+CONFIG_ARCH_BCM_5301X=y
- CONFIG_ARCH_BCM_MOBILE=y
- CONFIG_ARCH_BERLIN=y
- CONFIG_MACH_BERLIN_BG2=y
---- a/arch/arm/mach-bcm/Kconfig
-+++ b/arch/arm/mach-bcm/Kconfig
-@@ -32,6 +32,32 @@ config ARCH_BCM_MOBILE
- BCM11130, BCM11140, BCM11351, BCM28145 and
- BCM28155 variants.
-
-+config ARCH_BCM_5301X
-+ bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
-+ depends on MMU
-+ select ARM_GIC
-+ select CACHE_L2X0
-+ select HAVE_ARM_SCU if SMP
-+ select HAVE_ARM_TWD if SMP
-+ select HAVE_SMP
-+ select COMMON_CLK
-+ select GENERIC_CLOCKEVENTS
-+ select ARM_GLOBAL_TIMER
-+ select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-+ select MIGHT_HAVE_PCI
-+ help
-+ Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
-+
-+ This is a network SoC line mostly used in home routers and
-+ wifi access points, it's internal name is Northstar.
-+ This inclused the following SoC: BCM53010, BCM53011, BCM53012,
-+ BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
-+ BCM4708 and BCM4709.
-+
-+ Do not confuse this with the BCM4760 which is a totally
-+ different SoC or with the older BCM47XX and BCM53XX based
-+ network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
-+
- endmenu
-
- endif
---- a/arch/arm/mach-bcm/Makefile
-+++ b/arch/arm/mach-bcm/Makefile
-@@ -13,3 +13,4 @@
- obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
- plus_sec := $(call as-instr,.arch_extension sec,+sec)
- AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec)
-+obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
---- /dev/null
-+++ b/arch/arm/mach-bcm/bcm_5301x.c
-@@ -0,0 +1,28 @@
-+/*
-+ * Broadcom BCM470X / BCM5301X ARM platform code.
-+ *
-+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+#include <linux/of_platform.h>
-+#include <asm/hardware/cache-l2x0.h>
-+
-+#include <asm/mach/arch.h>
-+
-+
-+static void __init bcm5301x_dt_init(void)
-+{
-+ l2x0_of_init(0, ~0UL);
-+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-+}
-+
-+static const char __initconst *bcm5301x_dt_compat[] = {
-+ "brcm,bcm4708",
-+ NULL,
-+};
-+
-+DT_MACHINE_START(BCM5301X, "BCM5301X")
-+ .init_machine = bcm5301x_dt_init,
-+ .dt_compat = bcm5301x_dt_compat,
-+MACHINE_END
+++ /dev/null
-From 065802756b20d878c83290c115f212fc1631cba7 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Tue, 4 Feb 2014 00:01:44 +0100
-Subject: [PATCH 2/3] ARM: BCM5301X: add early debugging support
-
-This adds support for early debugging of BCM5301X SoC.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Acked-by: Christian Daudt <bcm@fixthebug.org>
-Signed-off-by: Matt Porter <mporter@linaro.org>
----
- arch/arm/Kconfig.debug | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/Kconfig.debug
-+++ b/arch/arm/Kconfig.debug
-@@ -106,6 +106,11 @@ choice
- depends on ARCH_BCM2835
- select DEBUG_UART_PL01X
-
-+ config DEBUG_BCM_5301X
-+ bool "Kernel low-level debugging on BCM5301X UART1"
-+ depends on ARCH_BCM_5301X
-+ select DEBUG_UART_PL01X
-+
- config DEBUG_BCM_KONA_UART
- bool "Kernel low-level debugging messages via BCM KONA UART"
- depends on ARCH_BCM
-@@ -1023,6 +1028,7 @@ config DEBUG_UART_PHYS
- default 0x101f1000 if ARCH_VERSATILE
- default 0x101fb000 if DEBUG_NOMADIK_UART
- default 0x16000000 if ARCH_INTEGRATOR
-+ default 0x18000300 if DEBUG_BCM_5301X
- default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
- default 0x20060000 if DEBUG_RK29_UART0
- default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
-@@ -1071,6 +1077,7 @@ config DEBUG_UART_VIRT
- default 0xf0009000 if DEBUG_CNS3XXX
- default 0xf01fb000 if DEBUG_NOMADIK_UART
- default 0xf0201000 if DEBUG_BCM2835
-+ default 0xf1000300 if DEBUG_BCM_5301X
- default 0xf11f1000 if ARCH_VERSATILE
- default 0xf1600000 if ARCH_INTEGRATOR
- default 0xf1c28000 if DEBUG_SUNXI_UART0
+++ /dev/null
-From fdf4850cb5b2e5e549a18b8b41abb001bfb19e9c Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Tue, 4 Feb 2014 00:01:46 +0100
-Subject: [PATCH 3/3] ARM: BCM5301X: workaround suppress fault
-
-Without this patch I am getting a unhandled fault exception like this
-one after "Freeing unused kernel memory":
-
-Freeing unused kernel memory: 1260K (c02c1000 - c03fc000)
-Unhandled fault: imprecise external abort (0x1c06) at 0xb6f89005
-Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
-
-The address which is here 0xb6f89005 changes from boot to boot, with a
-new build the changes are bigger. With kernel 3.10 I have also seen
-this fault at different places in the boot process, but starting with
-3.11 they are always occurring after the "Freeing unused kernel memory"
-message. I never was able to completely boot to userspace without this
-handler. The abort code is constant 0x1c06. This fault just happens
-once in the boot process I have never seen it happing twice or more.
-
-I also tried changing the CPSR.A bit to 0 in init_early, with this code
-like Afzal suggested, but that did not change anything:
-asm volatile("mrs r12, cpsr\n"
- "bic r12, r12, #0x00000100\n"
- "msr cpsr_c, r12" ::: "r12", "cc", "memory");
-
-Disabling the L2 cache by building with CONFIG_CACHE_L2X0 unset did not
-help.
-
-This workaround was copied from the vendor code including most of the
-comments. It says it they think this is caused by the CFE boot loader
-used on this device. I do not have any access to any datasheet or
-errata document to check this.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Acked-by: Christian Daudt <bcm@fixthebug.org>
-Signed-off-by: Matt Porter <mporter@linaro.org>
----
- arch/arm/mach-bcm/bcm_5301x.c | 33 +++++++++++++++++++++++++++++++++
- 1 file changed, 33 insertions(+)
-
---- a/arch/arm/mach-bcm/bcm_5301x.c
-+++ b/arch/arm/mach-bcm/bcm_5301x.c
-@@ -9,8 +9,40 @@
- #include <asm/hardware/cache-l2x0.h>
-
- #include <asm/mach/arch.h>
-+#include <asm/siginfo.h>
-+#include <asm/signal.h>
-
-
-+static bool first_fault = true;
-+
-+static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
-+ struct pt_regs *regs)
-+{
-+ if (fsr == 0x1c06 && first_fault) {
-+ first_fault = false;
-+
-+ /*
-+ * These faults with code 0x1c06 happens for no good reason,
-+ * possibly left over from the CFE boot loader.
-+ */
-+ pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n",
-+ addr, fsr);
-+
-+ /* Returning non-zero causes fault display and panic */
-+ return 0;
-+ }
-+
-+ /* Others should cause a fault */
-+ return 1;
-+}
-+
-+static void __init bcm5301x_init_early(void)
-+{
-+ /* Install our hook */
-+ hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
-+ "imprecise external abort");
-+}
-+
- static void __init bcm5301x_dt_init(void)
- {
- l2x0_of_init(0, ~0UL);
-@@ -23,6 +55,7 @@ static const char __initconst *bcm5301x_
- };
-
- DT_MACHINE_START(BCM5301X, "BCM5301X")
-+ .init_early = bcm5301x_init_early,
- .init_machine = bcm5301x_dt_init,
- .dt_compat = bcm5301x_dt_compat,
- MACHINE_END
+++ /dev/null
-From d27509f19b5f93ea3425cfef782bb3c6541cd44d Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Tue, 4 Feb 2014 00:01:45 +0100
-Subject: [PATCH] ARM: BCM5301X: add dts files for BCM4708 SoC
-
-This uses the newly added BCM5301X SoC code.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
-Acked-by: Christian Daudt <bcm@fixthebug.org>
-Signed-off-by: Matt Porter <mporter@linaro.org>
----
- arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 35 ++++++++++
- arch/arm/boot/dts/bcm4708.dtsi | 34 ++++++++++
- arch/arm/boot/dts/bcm5301x.dtsi | 95 +++++++++++++++++++++++++++
- 4 files changed, 165 insertions(+)
- create mode 100644 arch/arm/boot/dts/bcm4708-netgear-r6250.dts
- create mode 100644 arch/arm/boot/dts/bcm4708.dtsi
- create mode 100644 arch/arm/boot/dts/bcm5301x.dtsi
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -50,6 +50,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rp
- dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
- bcm28155-ap.dtb
- dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
-+dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
- dtb-$(CONFIG_ARCH_BERLIN) += \
- berlin2-sony-nsz-gs7.dtb \
- berlin2cd-google-chromecast.dtb
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
-@@ -0,0 +1,35 @@
-+/*
-+ * Broadcom BCM470X / BCM5301X arm platform code.
-+ * DTS for Netgear R6250 V1
-+ *
-+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm4708.dtsi"
-+
-+/ {
-+ compatible = "netgear,r6250v1", "brcm,bcm4708";
-+ model = "Netgear R6250 V1 (BCM4708)";
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200";
-+ };
-+
-+ memory {
-+ reg = <0x00000000 0x08000000>;
-+ };
-+
-+ chipcommonA {
-+ uart0: serial@0300 {
-+ status = "okay";
-+ };
-+
-+ uart1: serial@0400 {
-+ status = "okay";
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm4708.dtsi
-@@ -0,0 +1,34 @@
-+/*
-+ * Broadcom BCM470X / BCM5301X ARM platform code.
-+ * DTS for BCM4708 SoC.
-+ *
-+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include "bcm5301x.dtsi"
-+
-+/ {
-+ compatible = "brcm,bcm4708";
-+
-+ cpus {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ cpu@0 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a9";
-+ next-level-cache = <&L2>;
-+ reg = <0x0>;
-+ };
-+
-+ cpu@1 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a9";
-+ next-level-cache = <&L2>;
-+ reg = <0x1>;
-+ };
-+ };
-+
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm5301x.dtsi
-@@ -0,0 +1,95 @@
-+/*
-+ * Broadcom BCM470X / BCM5301X ARM platform code.
-+ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
-+ * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
-+ *
-+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include "skeleton.dtsi"
-+
-+/ {
-+ interrupt-parent = <&gic>;
-+
-+ chipcommonA {
-+ compatible = "simple-bus";
-+ ranges = <0x00000000 0x18000000 0x00001000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ uart0: serial@0300 {
-+ compatible = "ns16550";
-+ reg = <0x0300 0x100>;
-+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-frequency = <100000000>;
-+ status = "disabled";
-+ };
-+
-+ uart1: serial@0400 {
-+ compatible = "ns16550";
-+ reg = <0x0400 0x100>;
-+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-frequency = <100000000>;
-+ status = "disabled";
-+ };
-+ };
-+
-+ mpcore {
-+ compatible = "simple-bus";
-+ ranges = <0x00000000 0x19020000 0x00003000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ scu@0000 {
-+ compatible = "arm,cortex-a9-scu";
-+ reg = <0x0000 0x100>;
-+ };
-+
-+ timer@0200 {
-+ compatible = "arm,cortex-a9-global-timer";
-+ reg = <0x0200 0x100>;
-+ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clk_periph>;
-+ };
-+
-+ local-timer@0600 {
-+ compatible = "arm,cortex-a9-twd-timer";
-+ reg = <0x0600 0x100>;
-+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clk_periph>;
-+ };
-+
-+ gic: interrupt-controller@1000 {
-+ compatible = "arm,cortex-a9-gic";
-+ #interrupt-cells = <3>;
-+ #address-cells = <0>;
-+ interrupt-controller;
-+ reg = <0x1000 0x1000>,
-+ <0x0100 0x100>;
-+ };
-+
-+ L2: cache-controller@2000 {
-+ compatible = "arm,pl310-cache";
-+ reg = <0x2000 0x1000>;
-+ cache-unified;
-+ cache-level = <2>;
-+ };
-+ };
-+
-+ clocks {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ /* As long as we do not have a real clock driver us this
-+ * fixed clock */
-+ clk_periph: periph {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <400000000>;
-+ };
-+ };
-+};
+++ /dev/null
-From bd489dfe8c0d7495645cbc8b8c283217ba816fab Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sun, 4 May 2014 16:35:42 +0200
-Subject: [PATCH 02/15] bcm47xx: move the nvram header file into common space
-
-Moving mach-bcm47xx/bcm47xx_nvram.h makes it possible to reuse this
-header on the arm bcm47xx (BCM5301X) devices. This way a driver gets
-the correct functions to access the nvram depending on the SoC it boots
-for.
----
- arch/mips/bcm47xx/board.c | 2 +-
- arch/mips/bcm47xx/nvram.c | 2 +-
- arch/mips/bcm47xx/setup.c | 2 +-
- arch/mips/bcm47xx/sprom.c | 2 +-
- arch/mips/bcm47xx/time.c | 2 +-
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h | 53 ------------------
- drivers/net/ethernet/broadcom/b44.c | 8 +--
- drivers/net/ethernet/broadcom/bgmac.c | 2 +-
- drivers/ssb/driver_chipcommon_pmu.c | 6 +-
- include/linux/bcm47xx_nvram.h | 65 ++++++++++++++++++++++
- 10 files changed, 73 insertions(+), 71 deletions(-)
- delete mode 100644 arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
- create mode 100644 include/linux/bcm47xx_nvram.h
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -2,7 +2,7 @@
- #include <linux/export.h>
- #include <linux/string.h>
- #include <bcm47xx_board.h>
--#include <bcm47xx_nvram.h>
-+#include <linux/bcm47xx_nvram.h>
-
- struct bcm47xx_board_type {
- const enum bcm47xx_board board;
---- a/arch/mips/bcm47xx/nvram.c
-+++ b/arch/mips/bcm47xx/nvram.c
-@@ -17,7 +17,7 @@
- #include <linux/kernel.h>
- #include <linux/string.h>
- #include <asm/addrspace.h>
--#include <bcm47xx_nvram.h>
-+#include <linux/bcm47xx_nvram.h>
- #include <asm/mach-bcm47xx/bcm47xx.h>
-
- static char nvram_buf[NVRAM_SPACE];
---- a/arch/mips/bcm47xx/setup.c
-+++ b/arch/mips/bcm47xx/setup.c
-@@ -42,7 +42,7 @@
- #include <asm/reboot.h>
- #include <asm/time.h>
- #include <bcm47xx.h>
--#include <bcm47xx_nvram.h>
-+#include <linux/bcm47xx_nvram.h>
- #include <bcm47xx_board.h>
-
- union bcm47xx_bus bcm47xx_bus;
---- a/arch/mips/bcm47xx/sprom.c
-+++ b/arch/mips/bcm47xx/sprom.c
-@@ -27,7 +27,7 @@
- */
-
- #include <bcm47xx.h>
--#include <bcm47xx_nvram.h>
-+#include <linux/bcm47xx_nvram.h>
-
- static void create_key(const char *prefix, const char *postfix,
- const char *name, char *buf, int len)
---- a/arch/mips/bcm47xx/time.c
-+++ b/arch/mips/bcm47xx/time.c
-@@ -27,7 +27,7 @@
- #include <linux/ssb/ssb.h>
- #include <asm/time.h>
- #include <bcm47xx.h>
--#include <bcm47xx_nvram.h>
-+#include <linux/bcm47xx_nvram.h>
- #include <bcm47xx_board.h>
-
- void __init plat_time_init(void)
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
-+++ /dev/null
-@@ -1,53 +0,0 @@
--/*
-- * Copyright (C) 2005, Broadcom Corporation
-- * Copyright (C) 2006, Felix Fietkau <nbd@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License as published by the
-- * Free Software Foundation; either version 2 of the License, or (at your
-- * option) any later version.
-- */
--
--#ifndef __BCM47XX_NVRAM_H
--#define __BCM47XX_NVRAM_H
--
--#include <linux/types.h>
--#include <linux/kernel.h>
--
--struct nvram_header {
-- u32 magic;
-- u32 len;
-- u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
-- u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
-- u32 config_ncdl; /* ncdl values for memc */
--};
--
--#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */
--#define NVRAM_VERSION 1
--#define NVRAM_HEADER_SIZE 20
--#define NVRAM_SPACE 0x8000
--
--#define FLASH_MIN 0x00020000 /* Minimum flash size */
--
--#define NVRAM_MAX_VALUE_LEN 255
--#define NVRAM_MAX_PARAM_LEN 64
--
--extern int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len);
--
--static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
--{
-- if (strchr(buf, ':'))
-- sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
-- &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
-- &macaddr[5]);
-- else if (strchr(buf, '-'))
-- sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0],
-- &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
-- &macaddr[5]);
-- else
-- printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
--}
--
--int bcm47xx_nvram_gpio_pin(const char *name);
--
--#endif /* __BCM47XX_NVRAM_H */
---- a/drivers/net/ethernet/broadcom/b44.c
-+++ b/drivers/net/ethernet/broadcom/b44.c
-@@ -31,6 +31,7 @@
- #include <linux/ssb/ssb.h>
- #include <linux/slab.h>
- #include <linux/phy.h>
-+#include <linux/bcm47xx_nvram.h>
-
- #include <asm/uaccess.h>
- #include <asm/io.h>
-@@ -399,8 +400,6 @@ static void b44_set_flow_ctrl(struct b44
- __b44_set_flow_ctrl(bp, pause_enab);
- }
-
--#ifdef CONFIG_BCM47XX
--#include <bcm47xx_nvram.h>
- static void b44_wap54g10_workaround(struct b44 *bp)
- {
- char buf[20];
-@@ -429,11 +428,6 @@ static void b44_wap54g10_workaround(stru
- error:
- pr_warning("PHY: cannot reset MII transceiver isolate bit\n");
- }
--#else
--static inline void b44_wap54g10_workaround(struct b44 *bp)
--{
--}
--#endif
-
- static int b44_setup_phy(struct b44 *bp)
- {
---- a/drivers/net/ethernet/broadcom/bgmac.c
-+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -17,7 +17,7 @@
- #include <linux/interrupt.h>
- #include <linux/dma-mapping.h>
- #include <linux/platform_data/b53.h>
--#include <bcm47xx_nvram.h>
-+#include <linux/bcm47xx_nvram.h>
-
- static const struct bcma_device_id bgmac_bcma_tbl[] = {
- BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
---- a/drivers/ssb/driver_chipcommon_pmu.c
-+++ b/drivers/ssb/driver_chipcommon_pmu.c
-@@ -13,9 +13,7 @@
- #include <linux/ssb/ssb_driver_chipcommon.h>
- #include <linux/delay.h>
- #include <linux/export.h>
--#ifdef CONFIG_BCM47XX
--#include <bcm47xx_nvram.h>
--#endif
-+#include <linux/bcm47xx_nvram.h>
-
- #include "ssb_private.h"
-
-@@ -320,11 +318,9 @@ static void ssb_pmu_pll_init(struct ssb_
- u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
-
- if (bus->bustype == SSB_BUSTYPE_SSB) {
--#ifdef CONFIG_BCM47XX
- char buf[20];
- if (bcm47xx_nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
- crystalfreq = simple_strtoul(buf, NULL, 0);
--#endif
- }
-
- switch (bus->chip_id) {
---- /dev/null
-+++ b/include/linux/bcm47xx_nvram.h
-@@ -0,0 +1,65 @@
-+/*
-+ * Copyright (C) 2005, Broadcom Corporation
-+ * Copyright (C) 2006, Felix Fietkau <nbd@openwrt.org>
-+ * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#ifndef __BCM47XX_NVRAM_H
-+#define __BCM47XX_NVRAM_H
-+
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+
-+struct nvram_header {
-+ u32 magic;
-+ u32 len;
-+ u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
-+ u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
-+ u32 config_ncdl; /* ncdl values for memc */
-+};
-+
-+#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */
-+#define NVRAM_VERSION 1
-+#define NVRAM_HEADER_SIZE 20
-+#define NVRAM_SPACE 0x8000
-+
-+#define FLASH_MIN 0x00020000 /* Minimum flash size */
-+
-+#define NVRAM_MAX_VALUE_LEN 255
-+#define NVRAM_MAX_PARAM_LEN 64
-+
-+#ifdef CONFIG_BCM47XX
-+int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len);
-+
-+int bcm47xx_nvram_gpio_pin(const char *name);
-+#else
-+static inline int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len)
-+{
-+ return -ENXIO;
-+}
-+
-+static inline int bcm47xx_nvram_gpio_pin(const char *name)
-+{
-+ return -ENXIO;
-+}
-+#endif
-+
-+static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
-+{
-+ if (strchr(buf, ':'))
-+ sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
-+ &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
-+ &macaddr[5]);
-+ else if (strchr(buf, '-'))
-+ sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0],
-+ &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
-+ &macaddr[5]);
-+ else
-+ pr_warn("Can not parse mac address: %s\n", buf);
-+}
-+#endif /* __BCM47XX_NVRAM_H */
+++ /dev/null
-From 60a413ed5bc7917f1612df441240f458163b10c1 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sat, 3 May 2014 22:54:59 +0200
-Subject: [PATCH 03/15] bcm47xx-nvram: add new nvram driver with dt support
-
-This adds a new nvrm driver which uses device tree to provide nvram
-access to other drivers. You have to specify the memory ranges where
-the flash chip is mapped and this driver will search there for some
-nvram and parse it. Other drivers can use this driver to access the
-device nvram. The nvram is used to store board configurations like the
-mac address and also for configuration values in the vendor firmware.
----
- arch/mips/bcm47xx/board.c | 36 +++---
- arch/mips/bcm47xx/nvram.c | 7 +-
- arch/mips/bcm47xx/setup.c | 4 +-
- arch/mips/bcm47xx/sprom.c | 4 +-
- arch/mips/bcm47xx/time.c | 2 +-
- drivers/misc/Kconfig | 5 +
- drivers/misc/Makefile | 1 +
- drivers/misc/bcm47xx-nvram.c | 211 ++++++++++++++++++++++++++++++++++
- drivers/net/ethernet/broadcom/b44.c | 2 +-
- drivers/net/ethernet/broadcom/bgmac.c | 4 +-
- drivers/ssb/driver_chipcommon_pmu.c | 2 +-
- include/linux/bcm47xx_nvram.h | 16 ++-
- 12 files changed, 259 insertions(+), 35 deletions(-)
- create mode 100644 drivers/misc/bcm47xx-nvram.c
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -196,50 +196,50 @@ static __init const struct bcm47xx_board
- const struct bcm47xx_board_type_list2 *e2;
- const struct bcm47xx_board_type_list3 *e3;
-
-- if (bcm47xx_nvram_getenv("model_name", buf1, sizeof(buf1)) >= 0) {
-+ if (bcm47xx_nvram_getenv(NULL, "model_name", buf1, sizeof(buf1)) >= 0) {
- for (e1 = bcm47xx_board_list_model_name; e1->value1; e1++) {
- if (!strcmp(buf1, e1->value1))
- return &e1->board;
- }
- }
-
-- if (bcm47xx_nvram_getenv("model_no", buf1, sizeof(buf1)) >= 0) {
-+ if (bcm47xx_nvram_getenv(NULL, "model_no", buf1, sizeof(buf1)) >= 0) {
- for (e1 = bcm47xx_board_list_model_no; e1->value1; e1++) {
- if (strstarts(buf1, e1->value1))
- return &e1->board;
- }
- }
-
-- if (bcm47xx_nvram_getenv("machine_name", buf1, sizeof(buf1)) >= 0) {
-+ if (bcm47xx_nvram_getenv(NULL, "machine_name", buf1, sizeof(buf1)) >= 0) {
- for (e1 = bcm47xx_board_list_machine_name; e1->value1; e1++) {
- if (strstarts(buf1, e1->value1))
- return &e1->board;
- }
- }
-
-- if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0) {
-+ if (bcm47xx_nvram_getenv(NULL, "hardware_version", buf1, sizeof(buf1)) >= 0) {
- for (e1 = bcm47xx_board_list_hardware_version; e1->value1; e1++) {
- if (strstarts(buf1, e1->value1))
- return &e1->board;
- }
- }
-
-- if (bcm47xx_nvram_getenv("productid", buf1, sizeof(buf1)) >= 0) {
-+ if (bcm47xx_nvram_getenv(NULL, "productid", buf1, sizeof(buf1)) >= 0) {
- for (e1 = bcm47xx_board_list_productid; e1->value1; e1++) {
- if (!strcmp(buf1, e1->value1))
- return &e1->board;
- }
- }
-
-- if (bcm47xx_nvram_getenv("ModelId", buf1, sizeof(buf1)) >= 0) {
-+ if (bcm47xx_nvram_getenv(NULL, "ModelId", buf1, sizeof(buf1)) >= 0) {
- for (e1 = bcm47xx_board_list_ModelId; e1->value1; e1++) {
- if (!strcmp(buf1, e1->value1))
- return &e1->board;
- }
- }
-
-- if (bcm47xx_nvram_getenv("melco_id", buf1, sizeof(buf1)) >= 0 ||
-- bcm47xx_nvram_getenv("buf1falo_id", buf1, sizeof(buf1)) >= 0) {
-+ if (bcm47xx_nvram_getenv(NULL, "melco_id", buf1, sizeof(buf1)) >= 0 ||
-+ bcm47xx_nvram_getenv(NULL, "buf1falo_id", buf1, sizeof(buf1)) >= 0) {
- /* buffalo hardware, check id for specific hardware matches */
- for (e1 = bcm47xx_board_list_melco_id; e1->value1; e1++) {
- if (!strcmp(buf1, e1->value1))
-@@ -247,8 +247,8 @@ static __init const struct bcm47xx_board
- }
- }
-
-- if (bcm47xx_nvram_getenv("boot_hw_model", buf1, sizeof(buf1)) >= 0 &&
-- bcm47xx_nvram_getenv("boot_hw_ver", buf2, sizeof(buf2)) >= 0) {
-+ if (bcm47xx_nvram_getenv(NULL, "boot_hw_model", buf1, sizeof(buf1)) >= 0 &&
-+ bcm47xx_nvram_getenv(NULL, "boot_hw_ver", buf2, sizeof(buf2)) >= 0) {
- for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) {
- if (!strcmp(buf1, e2->value1) &&
- !strcmp(buf2, e2->value2))
-@@ -256,16 +256,16 @@ static __init const struct bcm47xx_board
- }
- }
-
-- if (bcm47xx_nvram_getenv("board_id", buf1, sizeof(buf1)) >= 0) {
-+ if (bcm47xx_nvram_getenv(NULL, "board_id", buf1, sizeof(buf1)) >= 0) {
- for (e1 = bcm47xx_board_list_board_id; e1->value1; e1++) {
- if (!strcmp(buf1, e1->value1))
- return &e1->board;
- }
- }
-
-- if (bcm47xx_nvram_getenv("boardtype", buf1, sizeof(buf1)) >= 0 &&
-- bcm47xx_nvram_getenv("boardnum", buf2, sizeof(buf2)) >= 0 &&
-- bcm47xx_nvram_getenv("boardrev", buf3, sizeof(buf3)) >= 0) {
-+ if (bcm47xx_nvram_getenv(NULL, "boardtype", buf1, sizeof(buf1)) >= 0 &&
-+ bcm47xx_nvram_getenv(NULL, "boardnum", buf2, sizeof(buf2)) >= 0 &&
-+ bcm47xx_nvram_getenv(NULL, "boardrev", buf3, sizeof(buf3)) >= 0) {
- for (e3 = bcm47xx_board_list_board; e3->value1; e3++) {
- if (!strcmp(buf1, e3->value1) &&
- !strcmp(buf2, e3->value2) &&
-@@ -286,7 +286,7 @@ void __init bcm47xx_board_detect(void)
- return;
-
- /* check if the nvram is available */
-- err = bcm47xx_nvram_getenv("boardtype", buf, sizeof(buf));
-+ err = bcm47xx_nvram_getenv(NULL, "boardtype", buf, sizeof(buf));
-
- /* init of nvram failed, probably too early now */
- if (err == -ENXIO) {
---- a/arch/mips/bcm47xx/nvram.c
-+++ b/arch/mips/bcm47xx/nvram.c
-@@ -158,7 +158,8 @@ static int nvram_init(void)
- return -ENXIO;
- }
-
--int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len)
-+int bcm47xx_nvram_getenv(const struct device *dev, const char *name, char *val,
-+ size_t val_len)
- {
- char *var, *value, *end, *eq;
- int err;
-@@ -190,7 +191,7 @@ int bcm47xx_nvram_getenv(char *name, cha
- }
- EXPORT_SYMBOL(bcm47xx_nvram_getenv);
-
--int bcm47xx_nvram_gpio_pin(const char *name)
-+int bcm47xx_nvram_gpio_pin(const struct device *dev, const char *name)
- {
- int i, err;
- char nvram_var[10];
-@@ -200,7 +201,7 @@ int bcm47xx_nvram_gpio_pin(const char *n
- err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i);
- if (err <= 0)
- continue;
-- err = bcm47xx_nvram_getenv(nvram_var, buf, sizeof(buf));
-+ err = bcm47xx_nvram_getenv(dev, nvram_var, buf, sizeof(buf));
- if (err <= 0)
- continue;
- if (!strcmp(name, buf))
---- a/arch/mips/bcm47xx/setup.c
-+++ b/arch/mips/bcm47xx/setup.c
-@@ -123,7 +123,7 @@ static int bcm47xx_get_invariants(struct
- memset(&iv->sprom, 0, sizeof(struct ssb_sprom));
- bcm47xx_fill_sprom(&iv->sprom, NULL, false);
-
-- if (bcm47xx_nvram_getenv("cardbus", buf, sizeof(buf)) >= 0)
-+ if (bcm47xx_nvram_getenv(NULL, "cardbus", buf, sizeof(buf)) >= 0)
- iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10);
-
- return 0;
-@@ -146,7 +146,7 @@ static void __init bcm47xx_register_ssb(
- panic("Failed to initialize SSB bus (err %d)", err);
-
- mcore = &bcm47xx_bus.ssb.mipscore;
-- if (bcm47xx_nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
-+ if (bcm47xx_nvram_getenv(NULL, "kernel_args", buf, sizeof(buf)) >= 0) {
- if (strstr(buf, "console=ttyS1")) {
- struct ssb_serial_port port;
-
---- a/arch/mips/bcm47xx/sprom.c
-+++ b/arch/mips/bcm47xx/sprom.c
-@@ -50,10 +50,10 @@ static int get_nvram_var(const char *pre
-
- create_key(prefix, postfix, name, key, sizeof(key));
-
-- err = bcm47xx_nvram_getenv(key, buf, len);
-+ err = bcm47xx_nvram_getenv(NULL, key, buf, len);
- if (fallback && err == -ENOENT && prefix) {
- create_key(NULL, postfix, name, key, sizeof(key));
-- err = bcm47xx_nvram_getenv(key, buf, len);
-+ err = bcm47xx_nvram_getenv(NULL, key, buf, len);
- }
- return err;
- }
---- a/arch/mips/bcm47xx/time.c
-+++ b/arch/mips/bcm47xx/time.c
-@@ -61,7 +61,7 @@ void __init plat_time_init(void)
- }
-
- if (chip_id == 0x5354) {
-- len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf));
-+ len = bcm47xx_nvram_getenv(NULL, "clkfreq", buf, sizeof(buf));
- if (len >= 0 && !strncmp(buf, "200", 4))
- hz = 100000000;
- }
---- a/drivers/misc/Kconfig
-+++ b/drivers/misc/Kconfig
-@@ -515,6 +515,11 @@ config SRAM
- the genalloc API. It is supposed to be used for small on-chip SRAM
- areas found on many SoCs.
-
-+config BCM47XX_NVRAM
-+ tristate "BCM47XX nvram driver"
-+ help
-+ This adds support for the brcm47xx nvram driver.
-+
- source "drivers/misc/c2port/Kconfig"
- source "drivers/misc/eeprom/Kconfig"
- source "drivers/misc/cb710/Kconfig"
---- a/drivers/misc/Makefile
-+++ b/drivers/misc/Makefile
-@@ -54,3 +54,4 @@ obj-$(CONFIG_LATTICE_ECP3_CONFIG) += lat
- obj-$(CONFIG_SRAM) += sram.o
- obj-y += mic/
- obj-$(CONFIG_GENWQE) += genwqe/
-+obj-$(CONFIG_BCM47XX_NVRAM) += bcm47xx-nvram.o
---- /dev/null
-+++ b/drivers/misc/bcm47xx-nvram.c
-@@ -0,0 +1,211 @@
-+/*
-+ * BCM947xx nvram variable access
-+ *
-+ * Copyright (C) 2005 Broadcom Corporation
-+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
-+ * Copyright (C) 2010-2014 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <linux/of_address.h>
-+#include <linux/device.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/bcm47xx_nvram.h>
-+
-+struct bcm47xx_nvram {
-+ size_t nvram_len;
-+ char *nvram_buf;
-+};
-+
-+static const u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000};
-+
-+static u32 find_nvram_size(void __iomem *end)
-+{
-+ struct nvram_header *header;
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {
-+ header = (struct nvram_header *)(end - nvram_sizes[i]);
-+ if (header->magic == NVRAM_HEADER)
-+ return nvram_sizes[i];
-+ }
-+
-+ return 0;
-+}
-+
-+/* Probe for NVRAM header */
-+static int nvram_find_and_copy(struct device *dev, void __iomem *base,
-+ size_t len, char **nvram_buf,
-+ size_t *nvram_len)
-+{
-+ struct nvram_header *header;
-+ int i;
-+ u32 off;
-+ u32 *src, *dst;
-+ u32 size;
-+
-+ /* TODO: when nvram is on nand flash check for bad blocks first. */
-+ off = FLASH_MIN;
-+ while (off <= len) {
-+ /* Windowed flash access */
-+ size = find_nvram_size(base + off);
-+ if (size) {
-+ header = (struct nvram_header *)(base + off - size);
-+ goto found;
-+ }
-+ off <<= 1;
-+ }
-+
-+ /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
-+ header = (struct nvram_header *)(base + 4096);
-+ if (header->magic == NVRAM_HEADER) {
-+ size = NVRAM_SPACE;
-+ goto found;
-+ }
-+
-+ header = (struct nvram_header *)(base + 1024);
-+ if (header->magic == NVRAM_HEADER) {
-+ size = NVRAM_SPACE;
-+ goto found;
-+ }
-+
-+ *nvram_buf = NULL;
-+ *nvram_len = 0;
-+ pr_err("no nvram found\n");
-+ return -ENXIO;
-+
-+found:
-+ if (header->len > size)
-+ pr_err("The nvram size accoridng to the header seems to be bigger than the partition on flash\n");
-+ *nvram_len = min_t(u32, header->len, size);
-+
-+ *nvram_buf = devm_kzalloc(dev, *nvram_len, GFP_KERNEL);
-+ if (!*nvram_buf)
-+ return -ENOMEM;
-+
-+ src = (u32 *) header;
-+ dst = (u32 *) *nvram_buf;
-+ for (i = 0; i < sizeof(struct nvram_header); i += 4)
-+ *dst++ = *src++;
-+ for (; i < *nvram_len; i += 4)
-+ *dst++ = le32_to_cpu(*src++);
-+
-+ return 0;
-+}
-+
-+int bcm47xx_nvram_getenv(const struct device *dev, const char *name, char *val, size_t val_len)
-+{
-+ char *var, *value, *end, *eq;
-+ struct bcm47xx_nvram *nvram;
-+
-+ if (!dev)
-+ return -ENODEV;
-+
-+ nvram = dev_get_drvdata(dev);
-+
-+ if (!name || !nvram || !nvram->nvram_len)
-+ return -EINVAL;
-+
-+ /* Look for name=value and return value */
-+ var = nvram->nvram_buf + sizeof(struct nvram_header);
-+ end = nvram->nvram_buf + nvram->nvram_len - 2;
-+ end[0] = end[1] = '\0';
-+ for (; *var; var = value + strlen(value) + 1) {
-+ eq = strchr(var, '=');
-+ if (!eq)
-+ break;
-+ value = eq + 1;
-+ if ((eq - var) == strlen(name) &&
-+ strncmp(var, name, (eq - var)) == 0) {
-+ return snprintf(val, val_len, "%s", value);
-+ }
-+ }
-+ return -ENOENT;
-+}
-+EXPORT_SYMBOL(bcm47xx_nvram_getenv);
-+
-+int bcm47xx_nvram_gpio_pin(const struct device *dev, const char *name)
-+{
-+ int i, err;
-+ char nvram_var[10];
-+ char buf[30];
-+
-+ if (!dev)
-+ return -ENODEV;
-+
-+ for (i = 0; i < 32; i++) {
-+ err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i);
-+ if (err <= 0)
-+ continue;
-+ err = bcm47xx_nvram_getenv(dev, nvram_var, buf, sizeof(buf));
-+ if (err <= 0)
-+ continue;
-+ if (!strcmp(name, buf))
-+ return i;
-+ }
-+ return -ENOENT;
-+}
-+EXPORT_SYMBOL(bcm47xx_nvram_gpio_pin);
-+
-+static int bcm47xx_nvram_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct device_node *np = dev->of_node;
-+ struct bcm47xx_nvram *nvram;
-+ int err;
-+ struct resource flash_mem;
-+ void __iomem *mmio;
-+
-+ /* Alloc */
-+ nvram = devm_kzalloc(dev, sizeof(*nvram), GFP_KERNEL);
-+ if (!nvram)
-+ return -ENOMEM;
-+
-+ err = of_address_to_resource(np, 0, &flash_mem);
-+ if (err)
-+ return err;
-+
-+ mmio = ioremap_nocache(flash_mem.start, resource_size(&flash_mem));
-+ if (!mmio)
-+ return -ENOMEM;
-+
-+ err = nvram_find_and_copy(dev, mmio, resource_size(&flash_mem), &nvram->nvram_buf, &nvram->nvram_len);
-+ if (err)
-+ goto err_unmap_mmio;
-+
-+ platform_set_drvdata(pdev, nvram);
-+
-+err_unmap_mmio:
-+ iounmap(mmio);
-+ return err;
-+}
-+
-+static const struct of_device_id bcm47xx_nvram_of_match_table[] = {
-+ { .compatible = "brcm,bcm47xx-nvram", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
-+
-+static struct platform_driver bcm47xx_nvram_driver = {
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = "bcm47xx-nvram",
-+ .of_match_table = bcm47xx_nvram_of_match_table,
-+ /* driver unloading/unbinding currently not supported */
-+ .suppress_bind_attrs = true,
-+ },
-+ .probe = bcm47xx_nvram_probe,
-+};
-+module_platform_driver(bcm47xx_nvram_driver);
-+
-+MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
-+MODULE_LICENSE("GPLv2");
---- a/drivers/net/ethernet/broadcom/b44.c
-+++ b/drivers/net/ethernet/broadcom/b44.c
-@@ -411,7 +411,7 @@ static void b44_wap54g10_workaround(stru
- * see https://dev.openwrt.org/ticket/146
- * check and reset bit "isolate"
- */
-- if (bcm47xx_nvram_getenv("boardnum", buf, sizeof(buf)) < 0)
-+ if (bcm47xx_nvram_getenv(NULL, "boardnum", buf, sizeof(buf)) < 0)
- return;
- if (simple_strtoul(buf, NULL, 0) == 2) {
- err = __b44_readphy(bp, 0, MII_BMCR, &val);
---- a/drivers/net/ethernet/broadcom/bgmac.c
-+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -974,7 +974,7 @@ static void bgmac_chip_reset(struct bgma
- BGMAC_CHIPCTL_1_IF_TYPE_MII;
- char buf[4];
-
-- if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
-+ if (bcm47xx_nvram_getenv(NULL, "et_swtype", buf, sizeof(buf)) > 0) {
- if (kstrtou8(buf, 0, &et_swtype))
- bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
- buf);
-@@ -1534,7 +1534,7 @@ static int bgmac_probe(struct bcma_devic
- }
-
- bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
-- if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
-+ if (bcm47xx_nvram_getenv(NULL, "et0_no_txint", NULL, 0) == 0)
- bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
-
- /* TODO: reset the external phy. Specs are needed */
---- a/drivers/ssb/driver_chipcommon_pmu.c
-+++ b/drivers/ssb/driver_chipcommon_pmu.c
-@@ -319,7 +319,7 @@ static void ssb_pmu_pll_init(struct ssb_
-
- if (bus->bustype == SSB_BUSTYPE_SSB) {
- char buf[20];
-- if (bcm47xx_nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
-+ if (bcm47xx_nvram_getenv(NULL, "xtalfreq", buf, sizeof(buf)) >= 0)
- crystalfreq = simple_strtoul(buf, NULL, 0);
- }
-
---- a/include/linux/bcm47xx_nvram.h
-+++ b/include/linux/bcm47xx_nvram.h
-@@ -15,6 +15,8 @@
- #include <linux/types.h>
- #include <linux/kernel.h>
-
-+struct device;
-+
- struct nvram_header {
- u32 magic;
- u32 len;
-@@ -33,17 +35,21 @@ struct nvram_header {
- #define NVRAM_MAX_VALUE_LEN 255
- #define NVRAM_MAX_PARAM_LEN 64
-
--#ifdef CONFIG_BCM47XX
--int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len);
-+#if defined(CONFIG_BCM47XX) || defined(CONFIG_BCM47XX_NVRAM)
-+int bcm47xx_nvram_getenv(const struct device *dev, const char *name, char *val,
-+ size_t val_len);
-
--int bcm47xx_nvram_gpio_pin(const char *name);
-+int bcm47xx_nvram_gpio_pin(const struct device *dev, const char *name);
- #else
--static inline int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len)
-+static inline int bcm47xx_nvram_getenv(const struct device *dev,
-+ const char *name, char *val,
-+ size_t val_len)
- {
- return -ENXIO;
- }
-
--static inline int bcm47xx_nvram_gpio_pin(const char *name)
-+static inline int bcm47xx_nvram_gpio_pin(const struct device *dev,
-+ const char *name)
- {
- return -ENXIO;
- }
+++ /dev/null
-From b113f9d3e140f18e63cbf3408b3dcde372242dc8 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sun, 4 May 2014 13:19:20 +0200
-Subject: [PATCH 04/15] bcm53xx-sprom: add sprom driver
-
-This driver needs an nvram driver and fetches the sprom values from the
-sprom and provides it to any other driver. The calibration data for the
-wifi chip the mac address and some more board description data is
-stores in the sprom.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- drivers/misc/Kconfig | 5 +
- drivers/misc/Makefile | 1 +
- drivers/misc/bcm53xx-sprom.c | 625 +++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 631 insertions(+)
- create mode 100644 drivers/misc/bcm53xx-sprom.c
-
---- a/drivers/misc/Kconfig
-+++ b/drivers/misc/Kconfig
-@@ -520,6 +520,11 @@ config BCM47XX_NVRAM
- help
- This adds support for the brcm47xx nvram driver.
-
-+config BCM53XX_SPROM
-+ tristate "BCM53XX sprom driver"
-+ help
-+ This adds support for the brcm53xx sprom driver.
-+
- source "drivers/misc/c2port/Kconfig"
- source "drivers/misc/eeprom/Kconfig"
- source "drivers/misc/cb710/Kconfig"
---- a/drivers/misc/Makefile
-+++ b/drivers/misc/Makefile
-@@ -55,3 +55,4 @@ obj-$(CONFIG_SRAM) += sram.o
- obj-y += mic/
- obj-$(CONFIG_GENWQE) += genwqe/
- obj-$(CONFIG_BCM47XX_NVRAM) += bcm47xx-nvram.o
-+obj-$(CONFIG_BCM53XX_SPROM) += bcm53xx-sprom.o
---- /dev/null
-+++ b/drivers/misc/bcm53xx-sprom.c
-@@ -0,0 +1,625 @@
-+/*
-+ * BCM947xx nvram variable access
-+ *
-+ * Copyright (C) 2005 Broadcom Corporation
-+ * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
-+ * Copyright (C) 2006 Michael Buesch <m@bues.ch>
-+ * Copyright (C) 2010 Waldemar Brodkorb <wbx@openadk.org>
-+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
-+ * Copyright (C) 2010-2014 Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <linux/of_address.h>
-+#include <linux/device.h>
-+#include <linux/platform_device.h>
-+#include <linux/of_platform.h>
-+#include <linux/io.h>
-+#include <linux/ssb/ssb.h>
-+#include <linux/bcm47xx_nvram.h>
-+
-+struct bcm53xx_sprom_fill {
-+ const char *prefix;
-+ bool fallback;
-+ int (*getenv)(const struct bcm53xx_sprom_fill *fill, const char *name, char *val, size_t val_len);
-+ const void *priv;
-+};
-+
-+static void create_key(const char *prefix, const char *postfix,
-+ const char *name, char *buf, int len)
-+{
-+ if (prefix && postfix)
-+ snprintf(buf, len, "%s%s%s", prefix, name, postfix);
-+ else if (prefix)
-+ snprintf(buf, len, "%s%s", prefix, name);
-+ else if (postfix)
-+ snprintf(buf, len, "%s%s", name, postfix);
-+ else
-+ snprintf(buf, len, "%s", name);
-+}
-+
-+static int get_nvram_var(const struct bcm53xx_sprom_fill *fill, const char *postfix,
-+ const char *name, char *buf, int len)
-+{
-+ char key[40];
-+ int err;
-+
-+ create_key(fill->prefix, postfix, name, key, sizeof(key));
-+
-+ err = fill->getenv(fill, key, buf, len);
-+ if (fill->fallback && err == -ENOENT && fill->prefix) {
-+ create_key(NULL, postfix, name, key, sizeof(key));
-+ err = fill->getenv(fill, key, buf, len);
-+ }
-+ return err;
-+}
-+
-+#define NVRAM_READ_VAL(type) \
-+static void nvram_read_ ## type (const struct bcm53xx_sprom_fill *fill, \
-+ const char *postfix, const char *name, \
-+ type *val, type allset) \
-+{ \
-+ char buf[100]; \
-+ int err; \
-+ type var; \
-+ \
-+ err = get_nvram_var(fill, postfix, name, buf, sizeof(buf)); \
-+ if (err < 0) \
-+ return; \
-+ err = kstrto ## type(strim(buf), 0, &var); \
-+ if (err) { \
-+ pr_warn("can not parse nvram name %s%s%s with value %s got %i\n", \
-+ fill->prefix, name, postfix, buf, err); \
-+ return; \
-+ } \
-+ if (allset && var == allset) \
-+ return; \
-+ *val = var; \
-+}
-+
-+NVRAM_READ_VAL(u8)
-+NVRAM_READ_VAL(s8)
-+NVRAM_READ_VAL(u16)
-+NVRAM_READ_VAL(u32)
-+
-+#undef NVRAM_READ_VAL
-+
-+static void nvram_read_u32_2(const struct bcm53xx_sprom_fill *fill, const char *name,
-+ u16 *val_lo, u16 *val_hi)
-+{
-+ char buf[100];
-+ int err;
-+ u32 val;
-+
-+ err = get_nvram_var(fill, NULL, name, buf, sizeof(buf));
-+ if (err < 0)
-+ return;
-+ err = kstrtou32(strim(buf), 0, &val);
-+ if (err) {
-+ pr_warn("can not parse nvram name %s%s with value %s got %i\n",
-+ fill->prefix, name, buf, err);
-+ return;
-+ }
-+ *val_lo = (val & 0x0000FFFFU);
-+ *val_hi = (val & 0xFFFF0000U) >> 16;
-+}
-+
-+static void nvram_read_leddc(const struct bcm53xx_sprom_fill *fill, const char *name,
-+ u8 *leddc_on_time, u8 *leddc_off_time)
-+{
-+ char buf[100];
-+ int err;
-+ u32 val;
-+
-+ err = get_nvram_var(fill, NULL, name, buf, sizeof(buf));
-+ if (err < 0)
-+ return;
-+ err = kstrtou32(strim(buf), 0, &val);
-+ if (err) {
-+ pr_warn("can not parse nvram name %s%s with value %s got %i\n",
-+ fill->prefix, name, buf, err);
-+ return;
-+ }
-+
-+ if (val == 0xffff || val == 0xffffffff)
-+ return;
-+
-+ *leddc_on_time = val & 0xff;
-+ *leddc_off_time = (val >> 16) & 0xff;
-+}
-+
-+static void nvram_read_macaddr(const struct bcm53xx_sprom_fill *fill, const char *name,
-+ u8 val[6])
-+{
-+ char buf[100];
-+ int err;
-+
-+ err = get_nvram_var(fill, NULL, name, buf, sizeof(buf));
-+ if (err < 0)
-+ return;
-+
-+ bcm47xx_nvram_parse_macaddr(buf, val);
-+}
-+
-+static void nvram_read_alpha2(const struct bcm53xx_sprom_fill *fill, const char *name,
-+ char val[2])
-+{
-+ char buf[10];
-+ int err;
-+
-+ err = get_nvram_var(fill, NULL, name, buf, sizeof(buf));
-+ if (err < 0)
-+ return;
-+ if (buf[0] == '0')
-+ return;
-+ if (strlen(buf) > 2) {
-+ pr_warn("alpha2 is too long %s\n", buf);
-+ return;
-+ }
-+ memcpy(val, buf, 2);
-+}
-+
-+static void bcm53xx_sprom_fill_r1234589(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_u8(fill, NULL, "ledbh0", &sprom->gpio0, 0xff);
-+ nvram_read_u8(fill, NULL, "ledbh1", &sprom->gpio1, 0xff);
-+ nvram_read_u8(fill, NULL, "ledbh2", &sprom->gpio2, 0xff);
-+ nvram_read_u8(fill, NULL, "ledbh3", &sprom->gpio3, 0xff);
-+ nvram_read_u8(fill, NULL, "aa2g", &sprom->ant_available_bg, 0);
-+ nvram_read_u8(fill, NULL, "aa5g", &sprom->ant_available_a, 0);
-+ nvram_read_s8(fill, NULL, "ag0", &sprom->antenna_gain.a0, 0);
-+ nvram_read_s8(fill, NULL, "ag1", &sprom->antenna_gain.a1, 0);
-+ nvram_read_alpha2(fill, "ccode", sprom->alpha2);
-+}
-+
-+static void bcm53xx_sprom_fill_r12389(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_u16(fill, NULL, "pa0b0", &sprom->pa0b0, 0);
-+ nvram_read_u16(fill, NULL, "pa0b1", &sprom->pa0b1, 0);
-+ nvram_read_u16(fill, NULL, "pa0b2", &sprom->pa0b2, 0);
-+ nvram_read_u8(fill, NULL, "pa0itssit", &sprom->itssi_bg, 0);
-+ nvram_read_u8(fill, NULL, "pa0maxpwr", &sprom->maxpwr_bg, 0);
-+ nvram_read_u16(fill, NULL, "pa1b0", &sprom->pa1b0, 0);
-+ nvram_read_u16(fill, NULL, "pa1b1", &sprom->pa1b1, 0);
-+ nvram_read_u16(fill, NULL, "pa1b2", &sprom->pa1b2, 0);
-+ nvram_read_u8(fill, NULL, "pa1itssit", &sprom->itssi_a, 0);
-+ nvram_read_u8(fill, NULL, "pa1maxpwr", &sprom->maxpwr_a, 0);
-+}
-+
-+static void bcm53xx_sprom_fill_r1(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_u16(fill, NULL, "boardflags", &sprom->boardflags_lo, 0);
-+ nvram_read_u8(fill, NULL, "cc", &sprom->country_code, 0);
-+}
-+
-+static void bcm53xx_sprom_fill_r2389(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_u8(fill, NULL, "opo", &sprom->opo, 0);
-+ nvram_read_u16(fill, NULL, "pa1lob0", &sprom->pa1lob0, 0);
-+ nvram_read_u16(fill, NULL, "pa1lob1", &sprom->pa1lob1, 0);
-+ nvram_read_u16(fill, NULL, "pa1lob2", &sprom->pa1lob2, 0);
-+ nvram_read_u16(fill, NULL, "pa1hib0", &sprom->pa1hib0, 0);
-+ nvram_read_u16(fill, NULL, "pa1hib1", &sprom->pa1hib1, 0);
-+ nvram_read_u16(fill, NULL, "pa1hib2", &sprom->pa1hib2, 0);
-+ nvram_read_u8(fill, NULL, "pa1lomaxpwr", &sprom->maxpwr_al, 0);
-+ nvram_read_u8(fill, NULL, "pa1himaxpwr", &sprom->maxpwr_ah, 0);
-+}
-+
-+static void bcm53xx_sprom_fill_r389(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_u8(fill, NULL, "bxa2g", &sprom->bxa2g, 0);
-+ nvram_read_u8(fill, NULL, "rssisav2g", &sprom->rssisav2g, 0);
-+ nvram_read_u8(fill, NULL, "rssismc2g", &sprom->rssismc2g, 0);
-+ nvram_read_u8(fill, NULL, "rssismf2g", &sprom->rssismf2g, 0);
-+ nvram_read_u8(fill, NULL, "bxa5g", &sprom->bxa5g, 0);
-+ nvram_read_u8(fill, NULL, "rssisav5g", &sprom->rssisav5g, 0);
-+ nvram_read_u8(fill, NULL, "rssismc5g", &sprom->rssismc5g, 0);
-+ nvram_read_u8(fill, NULL, "rssismf5g", &sprom->rssismf5g, 0);
-+ nvram_read_u8(fill, NULL, "tri2g", &sprom->tri2g, 0);
-+ nvram_read_u8(fill, NULL, "tri5g", &sprom->tri5g, 0);
-+ nvram_read_u8(fill, NULL, "tri5gl", &sprom->tri5gl, 0);
-+ nvram_read_u8(fill, NULL, "tri5gh", &sprom->tri5gh, 0);
-+ nvram_read_s8(fill, NULL, "rxpo2g", &sprom->rxpo2g, 0);
-+ nvram_read_s8(fill, NULL, "rxpo5g", &sprom->rxpo5g, 0);
-+}
-+
-+static void bcm53xx_sprom_fill_r3(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_u8(fill, NULL, "regrev", &sprom->regrev, 0);
-+ nvram_read_leddc(fill, "leddc", &sprom->leddc_on_time,
-+ &sprom->leddc_off_time);
-+}
-+
-+static void bcm53xx_sprom_fill_r4589(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_u8(fill, NULL, "regrev", &sprom->regrev, 0);
-+ nvram_read_s8(fill, NULL, "ag2", &sprom->antenna_gain.a2, 0);
-+ nvram_read_s8(fill, NULL, "ag3", &sprom->antenna_gain.a3, 0);
-+ nvram_read_u8(fill, NULL, "txchain", &sprom->txchain, 0xf);
-+ nvram_read_u8(fill, NULL, "rxchain", &sprom->rxchain, 0xf);
-+ nvram_read_u8(fill, NULL, "antswitch", &sprom->antswitch, 0xff);
-+ nvram_read_leddc(fill, "leddc", &sprom->leddc_on_time,
-+ &sprom->leddc_off_time);
-+}
-+
-+static void bcm53xx_sprom_fill_r458(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_u16(fill, NULL, "cck2gpo", &sprom->cck2gpo, 0);
-+ nvram_read_u32(fill, NULL, "ofdm2gpo", &sprom->ofdm2gpo, 0);
-+ nvram_read_u32(fill, NULL, "ofdm5gpo", &sprom->ofdm5gpo, 0);
-+ nvram_read_u32(fill, NULL, "ofdm5glpo", &sprom->ofdm5glpo, 0);
-+ nvram_read_u32(fill, NULL, "ofdm5ghpo", &sprom->ofdm5ghpo, 0);
-+ nvram_read_u16(fill, NULL, "cddpo", &sprom->cddpo, 0);
-+ nvram_read_u16(fill, NULL, "stbcpo", &sprom->stbcpo, 0);
-+ nvram_read_u16(fill, NULL, "bw40po", &sprom->bw40po, 0);
-+ nvram_read_u16(fill, NULL, "bwduppo", &sprom->bwduppo, 0);
-+ nvram_read_u16(fill, NULL, "mcs2gpo0", &sprom->mcs2gpo[0], 0);
-+ nvram_read_u16(fill, NULL, "mcs2gpo1", &sprom->mcs2gpo[1], 0);
-+ nvram_read_u16(fill, NULL, "mcs2gpo2", &sprom->mcs2gpo[2], 0);
-+ nvram_read_u16(fill, NULL, "mcs2gpo3", &sprom->mcs2gpo[3], 0);
-+ nvram_read_u16(fill, NULL, "mcs2gpo4", &sprom->mcs2gpo[4], 0);
-+ nvram_read_u16(fill, NULL, "mcs2gpo5", &sprom->mcs2gpo[5], 0);
-+ nvram_read_u16(fill, NULL, "mcs2gpo6", &sprom->mcs2gpo[6], 0);
-+ nvram_read_u16(fill, NULL, "mcs2gpo7", &sprom->mcs2gpo[7], 0);
-+ nvram_read_u16(fill, NULL, "mcs5gpo0", &sprom->mcs5gpo[0], 0);
-+ nvram_read_u16(fill, NULL, "mcs5gpo1", &sprom->mcs5gpo[1], 0);
-+ nvram_read_u16(fill, NULL, "mcs5gpo2", &sprom->mcs5gpo[2], 0);
-+ nvram_read_u16(fill, NULL, "mcs5gpo3", &sprom->mcs5gpo[3], 0);
-+ nvram_read_u16(fill, NULL, "mcs5gpo4", &sprom->mcs5gpo[4], 0);
-+ nvram_read_u16(fill, NULL, "mcs5gpo5", &sprom->mcs5gpo[5], 0);
-+ nvram_read_u16(fill, NULL, "mcs5gpo6", &sprom->mcs5gpo[6], 0);
-+ nvram_read_u16(fill, NULL, "mcs5gpo7", &sprom->mcs5gpo[7], 0);
-+ nvram_read_u16(fill, NULL, "mcs5glpo0", &sprom->mcs5glpo[0], 0);
-+ nvram_read_u16(fill, NULL, "mcs5glpo1", &sprom->mcs5glpo[1], 0);
-+ nvram_read_u16(fill, NULL, "mcs5glpo2", &sprom->mcs5glpo[2], 0);
-+ nvram_read_u16(fill, NULL, "mcs5glpo3", &sprom->mcs5glpo[3], 0);
-+ nvram_read_u16(fill, NULL, "mcs5glpo4", &sprom->mcs5glpo[4], 0);
-+ nvram_read_u16(fill, NULL, "mcs5glpo5", &sprom->mcs5glpo[5], 0);
-+ nvram_read_u16(fill, NULL, "mcs5glpo6", &sprom->mcs5glpo[6], 0);
-+ nvram_read_u16(fill, NULL, "mcs5glpo7", &sprom->mcs5glpo[7], 0);
-+ nvram_read_u16(fill, NULL, "mcs5ghpo0", &sprom->mcs5ghpo[0], 0);
-+ nvram_read_u16(fill, NULL, "mcs5ghpo1", &sprom->mcs5ghpo[1], 0);
-+ nvram_read_u16(fill, NULL, "mcs5ghpo2", &sprom->mcs5ghpo[2], 0);
-+ nvram_read_u16(fill, NULL, "mcs5ghpo3", &sprom->mcs5ghpo[3], 0);
-+ nvram_read_u16(fill, NULL, "mcs5ghpo4", &sprom->mcs5ghpo[4], 0);
-+ nvram_read_u16(fill, NULL, "mcs5ghpo5", &sprom->mcs5ghpo[5], 0);
-+ nvram_read_u16(fill, NULL, "mcs5ghpo6", &sprom->mcs5ghpo[6], 0);
-+ nvram_read_u16(fill, NULL, "mcs5ghpo7", &sprom->mcs5ghpo[7], 0);
-+}
-+
-+static void bcm53xx_sprom_fill_r45(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_u8(fill, NULL, "txpid2ga0", &sprom->txpid2g[0], 0);
-+ nvram_read_u8(fill, NULL, "txpid2ga1", &sprom->txpid2g[1], 0);
-+ nvram_read_u8(fill, NULL, "txpid2ga2", &sprom->txpid2g[2], 0);
-+ nvram_read_u8(fill, NULL, "txpid2ga3", &sprom->txpid2g[3], 0);
-+ nvram_read_u8(fill, NULL, "txpid5ga0", &sprom->txpid5g[0], 0);
-+ nvram_read_u8(fill, NULL, "txpid5ga1", &sprom->txpid5g[1], 0);
-+ nvram_read_u8(fill, NULL, "txpid5ga2", &sprom->txpid5g[2], 0);
-+ nvram_read_u8(fill, NULL, "txpid5ga3", &sprom->txpid5g[3], 0);
-+ nvram_read_u8(fill, NULL, "txpid5gla0", &sprom->txpid5gl[0], 0);
-+ nvram_read_u8(fill, NULL, "txpid5gla1", &sprom->txpid5gl[1], 0);
-+ nvram_read_u8(fill, NULL, "txpid5gla2", &sprom->txpid5gl[2], 0);
-+ nvram_read_u8(fill, NULL, "txpid5gla3", &sprom->txpid5gl[3], 0);
-+ nvram_read_u8(fill, NULL, "txpid5gha0", &sprom->txpid5gh[0], 0);
-+ nvram_read_u8(fill, NULL, "txpid5gha1", &sprom->txpid5gh[1], 0);
-+ nvram_read_u8(fill, NULL, "txpid5gha2", &sprom->txpid5gh[2], 0);
-+ nvram_read_u8(fill, NULL, "txpid5gha3", &sprom->txpid5gh[3], 0);
-+}
-+
-+static void bcm53xx_sprom_fill_r89(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_u8(fill, NULL, "tssipos2g", &sprom->fem.ghz2.tssipos, 0);
-+ nvram_read_u8(fill, NULL, "extpagain2g", &sprom->fem.ghz2.extpa_gain, 0);
-+ nvram_read_u8(fill, NULL, "pdetrange2g", &sprom->fem.ghz2.pdet_range, 0);
-+ nvram_read_u8(fill, NULL, "triso2g", &sprom->fem.ghz2.tr_iso, 0);
-+ nvram_read_u8(fill, NULL, "antswctl2g", &sprom->fem.ghz2.antswlut, 0);
-+ nvram_read_u8(fill, NULL, "tssipos5g", &sprom->fem.ghz5.tssipos, 0);
-+ nvram_read_u8(fill, NULL, "extpagain5g", &sprom->fem.ghz5.extpa_gain, 0);
-+ nvram_read_u8(fill, NULL, "pdetrange5g", &sprom->fem.ghz5.pdet_range, 0);
-+ nvram_read_u8(fill, NULL, "triso5g", &sprom->fem.ghz5.tr_iso, 0);
-+ nvram_read_u8(fill, NULL, "antswctl5g", &sprom->fem.ghz5.antswlut, 0);
-+ nvram_read_u8(fill, NULL, "tempthresh", &sprom->tempthresh, 0);
-+ nvram_read_u8(fill, NULL, "tempoffset", &sprom->tempoffset, 0);
-+ nvram_read_u16(fill, NULL, "rawtempsense", &sprom->rawtempsense, 0);
-+ nvram_read_u8(fill, NULL, "measpower", &sprom->measpower, 0);
-+ nvram_read_u8(fill, NULL, "tempsense_slope", &sprom->tempsense_slope, 0);
-+ nvram_read_u8(fill, NULL, "tempcorrx", &sprom->tempcorrx, 0);
-+ nvram_read_u8(fill, NULL, "tempsense_option", &sprom->tempsense_option, 0);
-+ nvram_read_u8(fill, NULL, "freqoffset_corr", &sprom->freqoffset_corr, 0);
-+ nvram_read_u8(fill, NULL, "iqcal_swp_dis", &sprom->iqcal_swp_dis, 0);
-+ nvram_read_u8(fill, NULL, "hw_iqcal_en", &sprom->hw_iqcal_en, 0);
-+ nvram_read_u8(fill, NULL, "elna2g", &sprom->elna2g, 0);
-+ nvram_read_u8(fill, NULL, "elna5g", &sprom->elna5g, 0);
-+ nvram_read_u8(fill, NULL, "phycal_tempdelta", &sprom->phycal_tempdelta, 0);
-+ nvram_read_u8(fill, NULL, "temps_period", &sprom->temps_period, 0);
-+ nvram_read_u8(fill, NULL, "temps_hysteresis", &sprom->temps_hysteresis, 0);
-+ nvram_read_u8(fill, NULL, "measpower1", &sprom->measpower1, 0);
-+ nvram_read_u8(fill, NULL, "measpower2", &sprom->measpower2, 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr2ga0", &sprom->rxgainerr2ga[0], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr2ga1", &sprom->rxgainerr2ga[1], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr2ga2", &sprom->rxgainerr2ga[2], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr5gla0", &sprom->rxgainerr5gla[0], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr5gla1", &sprom->rxgainerr5gla[1], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr5gla2", &sprom->rxgainerr5gla[2], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr5gma0", &sprom->rxgainerr5gma[0], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr5gma1", &sprom->rxgainerr5gma[1], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr5gma2", &sprom->rxgainerr5gma[2], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr5gha0", &sprom->rxgainerr5gha[0], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr5gha1", &sprom->rxgainerr5gha[1], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr5gha2", &sprom->rxgainerr5gha[2], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr5gua0", &sprom->rxgainerr5gua[0], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr5gua1", &sprom->rxgainerr5gua[1], 0);
-+ nvram_read_u8(fill, NULL, "rxgainerr5gua2", &sprom->rxgainerr5gua[2], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl2ga0", &sprom->noiselvl2ga[0], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl2ga1", &sprom->noiselvl2ga[1], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl2ga2", &sprom->noiselvl2ga[2], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl5gla0", &sprom->noiselvl5gla[0], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl5gla1", &sprom->noiselvl5gla[1], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl5gla2", &sprom->noiselvl5gla[2], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl5gma0", &sprom->noiselvl5gma[0], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl5gma1", &sprom->noiselvl5gma[1], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl5gma2", &sprom->noiselvl5gma[2], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl5gha0", &sprom->noiselvl5gha[0], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl5gha1", &sprom->noiselvl5gha[1], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl5gha2", &sprom->noiselvl5gha[2], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl5gua0", &sprom->noiselvl5gua[0], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl5gua1", &sprom->noiselvl5gua[1], 0);
-+ nvram_read_u8(fill, NULL, "noiselvl5gua2", &sprom->noiselvl5gua[2], 0);
-+ nvram_read_u8(fill, NULL, "pcieingress_war", &sprom->pcieingress_war, 0);
-+}
-+
-+static void bcm53xx_sprom_fill_r9(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_u16(fill, NULL, "cckbw202gpo", &sprom->cckbw202gpo, 0);
-+ nvram_read_u16(fill, NULL, "cckbw20ul2gpo", &sprom->cckbw20ul2gpo, 0);
-+ nvram_read_u32(fill, NULL, "legofdmbw202gpo", &sprom->legofdmbw202gpo, 0);
-+ nvram_read_u32(fill, NULL, "legofdmbw20ul2gpo", &sprom->legofdmbw20ul2gpo, 0);
-+ nvram_read_u32(fill, NULL, "legofdmbw205glpo", &sprom->legofdmbw205glpo, 0);
-+ nvram_read_u32(fill, NULL, "legofdmbw20ul5glpo", &sprom->legofdmbw20ul5glpo, 0);
-+ nvram_read_u32(fill, NULL, "legofdmbw205gmpo", &sprom->legofdmbw205gmpo, 0);
-+ nvram_read_u32(fill, NULL, "legofdmbw20ul5gmpo", &sprom->legofdmbw20ul5gmpo, 0);
-+ nvram_read_u32(fill, NULL, "legofdmbw205ghpo", &sprom->legofdmbw205ghpo, 0);
-+ nvram_read_u32(fill, NULL, "legofdmbw20ul5ghpo", &sprom->legofdmbw20ul5ghpo, 0);
-+ nvram_read_u32(fill, NULL, "mcsbw202gpo", &sprom->mcsbw202gpo, 0);
-+ nvram_read_u32(fill, NULL, "mcsbw20ul2gpo", &sprom->mcsbw20ul2gpo, 0);
-+ nvram_read_u32(fill, NULL, "mcsbw402gpo", &sprom->mcsbw402gpo, 0);
-+ nvram_read_u32(fill, NULL, "mcsbw205glpo", &sprom->mcsbw205glpo, 0);
-+ nvram_read_u32(fill, NULL, "mcsbw20ul5glpo", &sprom->mcsbw20ul5glpo, 0);
-+ nvram_read_u32(fill, NULL, "mcsbw405glpo", &sprom->mcsbw405glpo, 0);
-+ nvram_read_u32(fill, NULL, "mcsbw205gmpo", &sprom->mcsbw205gmpo, 0);
-+ nvram_read_u32(fill, NULL, "mcsbw20ul5gmpo", &sprom->mcsbw20ul5gmpo, 0);
-+ nvram_read_u32(fill, NULL, "mcsbw405gmpo", &sprom->mcsbw405gmpo, 0);
-+ nvram_read_u32(fill, NULL, "mcsbw205ghpo", &sprom->mcsbw205ghpo, 0);
-+ nvram_read_u32(fill, NULL, "mcsbw20ul5ghpo", &sprom->mcsbw20ul5ghpo, 0);
-+ nvram_read_u32(fill, NULL, "mcsbw405ghpo", &sprom->mcsbw405ghpo, 0);
-+ nvram_read_u16(fill, NULL, "mcs32po", &sprom->mcs32po, 0);
-+ nvram_read_u16(fill, NULL, "legofdm40duppo", &sprom->legofdm40duppo, 0);
-+ nvram_read_u8(fill, NULL, "sar2g", &sprom->sar2g, 0);
-+ nvram_read_u8(fill, NULL, "sar5g", &sprom->sar5g, 0);
-+}
-+
-+static void bcm53xx_sprom_fill_path_r4589(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ char postfix[2];
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(sprom->core_pwr_info); i++) {
-+ struct ssb_sprom_core_pwr_info *pwr_info = &sprom->core_pwr_info[i];
-+ snprintf(postfix, sizeof(postfix), "%i", i);
-+ nvram_read_u8(fill, postfix, "maxp2ga", &pwr_info->maxpwr_2g, 0);
-+ nvram_read_u8(fill, postfix, "itt2ga", &pwr_info->itssi_2g, 0);
-+ nvram_read_u8(fill, postfix, "itt5ga", &pwr_info->itssi_5g, 0);
-+ nvram_read_u16(fill, postfix, "pa2gw0a", &pwr_info->pa_2g[0], 0);
-+ nvram_read_u16(fill, postfix, "pa2gw1a", &pwr_info->pa_2g[1], 0);
-+ nvram_read_u16(fill, postfix, "pa2gw2a", &pwr_info->pa_2g[2], 0);
-+ nvram_read_u8(fill, postfix, "maxp5ga", &pwr_info->maxpwr_5g, 0);
-+ nvram_read_u8(fill, postfix, "maxp5gha", &pwr_info->maxpwr_5gh, 0);
-+ nvram_read_u8(fill, postfix, "maxp5gla", &pwr_info->maxpwr_5gl, 0);
-+ nvram_read_u16(fill, postfix, "pa5gw0a", &pwr_info->pa_5g[0], 0);
-+ nvram_read_u16(fill, postfix, "pa5gw1a", &pwr_info->pa_5g[1], 0);
-+ nvram_read_u16(fill, postfix, "pa5gw2a", &pwr_info->pa_5g[2], 0);
-+ nvram_read_u16(fill, postfix, "pa5glw0a", &pwr_info->pa_5gl[0], 0);
-+ nvram_read_u16(fill, postfix, "pa5glw1a", &pwr_info->pa_5gl[1], 0);
-+ nvram_read_u16(fill, postfix, "pa5glw2a", &pwr_info->pa_5gl[2], 0);
-+ nvram_read_u16(fill, postfix, "pa5ghw0a", &pwr_info->pa_5gh[0], 0);
-+ nvram_read_u16(fill, postfix, "pa5ghw1a", &pwr_info->pa_5gh[1], 0);
-+ nvram_read_u16(fill, postfix, "pa5ghw2a", &pwr_info->pa_5gh[2], 0);
-+ }
-+}
-+
-+static void bcm53xx_sprom_fill_path_r45(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ char postfix[2];
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(sprom->core_pwr_info); i++) {
-+ struct ssb_sprom_core_pwr_info *pwr_info = &sprom->core_pwr_info[i];
-+ snprintf(postfix, sizeof(postfix), "%i", i);
-+ nvram_read_u16(fill, postfix, "pa2gw3a", &pwr_info->pa_2g[3], 0);
-+ nvram_read_u16(fill, postfix, "pa5gw3a", &pwr_info->pa_5g[3], 0);
-+ nvram_read_u16(fill, postfix, "pa5glw3a", &pwr_info->pa_5gl[3], 0);
-+ nvram_read_u16(fill, postfix, "pa5ghw3a", &pwr_info->pa_5gh[3], 0);
-+ }
-+}
-+
-+static void bcm53xx_sprom_fill_ethernet(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_macaddr(fill, "et0macaddr", sprom->et0mac);
-+ nvram_read_u8(fill, NULL, "et0mdcport", &sprom->et0mdcport, 0);
-+ nvram_read_u8(fill, NULL, "et0phyaddr", &sprom->et0phyaddr, 0);
-+
-+ nvram_read_macaddr(fill, "et1macaddr", sprom->et1mac);
-+ nvram_read_u8(fill, NULL, "et1mdcport", &sprom->et1mdcport, 0);
-+ nvram_read_u8(fill, NULL, "et1phyaddr", &sprom->et1phyaddr, 0);
-+
-+ nvram_read_macaddr(fill, "macaddr", sprom->il0mac);
-+ nvram_read_macaddr(fill, "il0macaddr", sprom->il0mac);
-+}
-+
-+static void bcm53xx_sprom_fill_board_data(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ nvram_read_u16(fill, NULL, "boardrev", &sprom->board_rev, 0);
-+ nvram_read_u16(fill, NULL, "boardnum", &sprom->board_num, 0);
-+ nvram_read_u16(fill, NULL, "boardtype", &sprom->board_type, 0);
-+ nvram_read_u32_2(fill, "boardflags", &sprom->boardflags_lo,
-+ &sprom->boardflags_hi);
-+ nvram_read_u32_2(fill, "boardflags2", &sprom->boardflags2_lo,
-+ &sprom->boardflags2_hi);
-+}
-+
-+static void bcm53xx_sprom_fill(struct ssb_sprom *sprom,
-+ const struct bcm53xx_sprom_fill *fill)
-+{
-+ bcm53xx_sprom_fill_ethernet(sprom, fill);
-+ bcm53xx_sprom_fill_board_data(sprom, fill);
-+
-+ nvram_read_u8(fill, NULL, "sromrev", &sprom->revision, 0);
-+
-+ switch (sprom->revision) {
-+ case 1:
-+ bcm53xx_sprom_fill_r1234589(sprom, fill);
-+ bcm53xx_sprom_fill_r12389(sprom, fill);
-+ bcm53xx_sprom_fill_r1(sprom, fill);
-+ break;
-+ case 2:
-+ bcm53xx_sprom_fill_r1234589(sprom, fill);
-+ bcm53xx_sprom_fill_r12389(sprom, fill);
-+ bcm53xx_sprom_fill_r2389(sprom, fill);
-+ break;
-+ case 3:
-+ bcm53xx_sprom_fill_r1234589(sprom, fill);
-+ bcm53xx_sprom_fill_r12389(sprom, fill);
-+ bcm53xx_sprom_fill_r2389(sprom, fill);
-+ bcm53xx_sprom_fill_r389(sprom, fill);
-+ bcm53xx_sprom_fill_r3(sprom, fill);
-+ break;
-+ case 4:
-+ case 5:
-+ bcm53xx_sprom_fill_r1234589(sprom, fill);
-+ bcm53xx_sprom_fill_r4589(sprom, fill);
-+ bcm53xx_sprom_fill_r458(sprom, fill);
-+ bcm53xx_sprom_fill_r45(sprom, fill);
-+ bcm53xx_sprom_fill_path_r4589(sprom, fill);
-+ bcm53xx_sprom_fill_path_r45(sprom, fill);
-+ break;
-+ case 8:
-+ bcm53xx_sprom_fill_r1234589(sprom, fill);
-+ bcm53xx_sprom_fill_r12389(sprom, fill);
-+ bcm53xx_sprom_fill_r2389(sprom, fill);
-+ bcm53xx_sprom_fill_r389(sprom, fill);
-+ bcm53xx_sprom_fill_r4589(sprom, fill);
-+ bcm53xx_sprom_fill_r458(sprom, fill);
-+ bcm53xx_sprom_fill_r89(sprom, fill);
-+ bcm53xx_sprom_fill_path_r4589(sprom, fill);
-+ break;
-+ case 9:
-+ bcm53xx_sprom_fill_r1234589(sprom, fill);
-+ bcm53xx_sprom_fill_r12389(sprom, fill);
-+ bcm53xx_sprom_fill_r2389(sprom, fill);
-+ bcm53xx_sprom_fill_r389(sprom, fill);
-+ bcm53xx_sprom_fill_r4589(sprom, fill);
-+ bcm53xx_sprom_fill_r89(sprom, fill);
-+ bcm53xx_sprom_fill_r9(sprom, fill);
-+ bcm53xx_sprom_fill_path_r4589(sprom, fill);
-+ break;
-+ default:
-+ pr_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
-+ sprom->revision);
-+ sprom->revision = 1;
-+ bcm53xx_sprom_fill_r1234589(sprom, fill);
-+ bcm53xx_sprom_fill_r12389(sprom, fill);
-+ bcm53xx_sprom_fill_r1(sprom, fill);
-+ }
-+}
-+
-+static int bcm53xx_sprom_getenv(const struct bcm53xx_sprom_fill *fill,
-+ const char *name, char *val, size_t val_len)
-+{
-+ const struct platform_device *nvram_dev = fill->priv;
-+
-+ return bcm47xx_nvram_getenv(&nvram_dev->dev, name, val, val_len);
-+};
-+
-+static int bcm53xx_sprom_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct device_node *np = dev->of_node;
-+ struct ssb_sprom *sprom;
-+ const phandle *handle;
-+ struct device_node *nvram_node;
-+ struct platform_device *nvram_dev;
-+ struct bcm53xx_sprom_fill fill;
-+
-+ /* Alloc */
-+ sprom = devm_kzalloc(dev, sizeof(*sprom), GFP_KERNEL);
-+ if (!sprom)
-+ return -ENOMEM;
-+
-+ handle = of_get_property(np, "nvram", NULL);
-+ if (!handle)
-+ return -ENOMEM;
-+
-+ nvram_node = of_find_node_by_phandle(be32_to_cpup(handle));
-+ if (!nvram_node)
-+ return -ENOMEM;
-+
-+ nvram_dev = of_find_device_by_node(nvram_node);
-+ if (!nvram_dev)
-+ return -ENOMEM;
-+
-+ fill.prefix = NULL;
-+ fill.fallback = false;
-+ fill.getenv = bcm53xx_sprom_getenv;
-+ fill.priv = nvram_dev;
-+
-+ bcm53xx_sprom_fill(sprom, &fill);
-+
-+ platform_set_drvdata(pdev, sprom);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id bcm53xx_sprom_of_match_table[] = {
-+ { .compatible = "brcm,bcm53xx-sprom", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
-+
-+static struct platform_driver bcm53xx_sprom_driver = {
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = "bcm53xx-sprom",
-+ .of_match_table = bcm53xx_sprom_of_match_table,
-+ /* driver unloading/unbinding currently not supported */
-+ .suppress_bind_attrs = true,
-+ },
-+ .probe = bcm53xx_sprom_probe,
-+};
-+module_platform_driver(bcm53xx_sprom_driver);
-+
-+MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
-+MODULE_LICENSE("GPLv2");
+++ /dev/null
-From bb5d497aeceb8d9f36a1d990538389b54748dfcd Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Mon, 6 Jan 2014 23:29:15 +0100
-Subject: [PATCH 05/15] bcma: register bcma as device tree driver
-
-This driver is used by the bcm53xx ARM SoC code.Now it is possible to
-give the address of the chipcommon core in device tree.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- drivers/bcma/host_soc.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++
- include/linux/bcma/bcma.h | 2 ++
- 2 files changed, 72 insertions(+)
-
---- a/drivers/bcma/host_soc.c
-+++ b/drivers/bcma/host_soc.c
-@@ -7,6 +7,9 @@
-
- #include "bcma_private.h"
- #include "scan.h"
-+#include <linux/slab.h>
-+#include <linux/module.h>
-+#include <linux/of_address.h>
- #include <linux/bcma/bcma.h>
- #include <linux/bcma/bcma_soc.h>
-
-@@ -173,6 +176,7 @@ int __init bcma_host_soc_register(struct
- /* Host specific */
- bus->hosttype = BCMA_HOSTTYPE_SOC;
- bus->ops = &bcma_host_soc_ops;
-+ bus->host_pdev = NULL;
-
- /* Register */
- err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
-@@ -181,3 +185,69 @@ int __init bcma_host_soc_register(struct
-
- return err;
- }
-+
-+#ifdef CONFIG_OF
-+static int bcma_host_soc_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct device_node *np = dev->of_node;
-+ struct bcma_bus *bus;
-+ int err;
-+
-+ /* Alloc */
-+ bus = devm_kzalloc(dev, sizeof(*bus), GFP_KERNEL);
-+ if (!bus)
-+ return -ENOMEM;
-+
-+ /* Map MMIO */
-+ bus->mmio = of_iomap(np, 0);
-+ if (!bus->mmio)
-+ return -ENOMEM;
-+
-+ /* Host specific */
-+ bus->hosttype = BCMA_HOSTTYPE_SOC;
-+ bus->ops = &bcma_host_soc_ops;
-+ bus->host_pdev = pdev;
-+
-+ /* Register */
-+ err = bcma_bus_register(bus);
-+ if (err)
-+ goto err_unmap_mmio;
-+
-+ platform_set_drvdata(pdev, bus);
-+
-+ return err;
-+
-+err_unmap_mmio:
-+ iounmap(bus->mmio);
-+ return err;
-+}
-+
-+static int bcma_host_soc_remove(struct platform_device *pdev)
-+{
-+ struct bcma_bus *bus = platform_get_drvdata(pdev);
-+
-+ bcma_bus_unregister(bus);
-+ iounmap(bus->mmio);
-+ platform_set_drvdata(pdev, NULL);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id bcma_host_soc_of_match[] = {
-+ { .compatible = "brcm,bus-aix", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, bcma_host_soc_of_match);
-+
-+static struct platform_driver bcma_host_soc_driver = {
-+ .driver = {
-+ .name = "bcma-host-soc",
-+ .owner = THIS_MODULE,
-+ .of_match_table = bcma_host_soc_of_match,
-+ },
-+ .probe = bcma_host_soc_probe,
-+ .remove = bcma_host_soc_remove,
-+};
-+module_platform_driver(bcma_host_soc_driver);
-+#endif /* CONFIG_OF */
---- a/include/linux/bcma/bcma.h
-+++ b/include/linux/bcma/bcma.h
-@@ -322,6 +322,8 @@ struct bcma_bus {
- struct pci_dev *host_pci;
- /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
- struct sdio_func *host_sdio;
-+ /* Pointer to platform device (only for BCMA_HOSTTYPE_SOC) */
-+ struct platform_device *host_pdev;
- };
-
- struct bcma_chipinfo chipinfo;
+++ /dev/null
-From 3e59da41882a408064cd23f4c9124a7938bdb91f Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Thu, 9 Jan 2014 19:40:14 +0100
-Subject: [PATCH 06/15] bcma: get irqs from dt
-
-If bcma was registered with device tree it will search for some nodes
-with the irq number and add it to the core configuration.
----
- drivers/bcma/main.c | 42 +++++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 41 insertions(+), 1 deletion(-)
-
---- a/drivers/bcma/main.c
-+++ b/drivers/bcma/main.c
-@@ -10,6 +10,8 @@
- #include <linux/platform_device.h>
- #include <linux/bcma/bcma.h>
- #include <linux/slab.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_address.h>
-
- MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
- MODULE_LICENSE("GPL");
-@@ -120,6 +122,38 @@ static void bcma_release_core_dev(struct
- kfree(core);
- }
-
-+static struct device_node *bcma_of_find_child_device(struct platform_device *parent,
-+ struct bcma_device *core)
-+{
-+ struct device_node *node;
-+ u64 size;
-+ const __be32 *reg;
-+
-+ if (!parent || !parent->dev.of_node)
-+ return NULL;
-+
-+ for_each_child_of_node(parent->dev.of_node, node) {
-+ reg = of_get_address(node, 0, &size, 0);
-+ if (!reg)
-+ continue;
-+ if (be32_to_cpup(reg) == core->addr)
-+ return node;
-+ }
-+ return NULL;
-+}
-+
-+static void bcma_of_fill_device(struct platform_device *parent,
-+ struct bcma_device *core)
-+{
-+ struct device_node *node;
-+
-+ node = bcma_of_find_child_device(parent, core);
-+ if (!node)
-+ return;
-+ core->dev.of_node = node;
-+ core->irq = irq_of_parse_and_map(node, 0);
-+}
-+
- static int bcma_register_cores(struct bcma_bus *bus)
- {
- struct bcma_device *core;
-@@ -155,7 +189,13 @@ static int bcma_register_cores(struct bc
- break;
- case BCMA_HOSTTYPE_SOC:
- core->dev.dma_mask = &core->dev.coherent_dma_mask;
-- core->dma_dev = &core->dev;
-+ if (bus->host_pdev) {
-+ core->dma_dev = &bus->host_pdev->dev;
-+ core->dev.parent = &bus->host_pdev->dev;
-+ bcma_of_fill_device(bus->host_pdev, core);
-+ } else {
-+ core->dma_dev = &core->dev;
-+ }
- break;
- case BCMA_HOSTTYPE_SDIO:
- break;
+++ /dev/null
-From 5d94449a92e4121b408e7cb8931a47984135eeea Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sun, 4 May 2014 14:34:31 +0200
-Subject: [PATCH 07/15] bcma: get sprom from devicetree
-
-This patch make it possible to device an sprom provider in device tree
-and get the sprom from this driver. Every time there is such a provider
-it gets asked for a sprom.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- drivers/bcma/sprom.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 50 insertions(+), 1 deletion(-)
-
---- a/drivers/bcma/sprom.c
-+++ b/drivers/bcma/sprom.c
-@@ -15,6 +15,8 @@
- #include <linux/io.h>
- #include <linux/dma-mapping.h>
- #include <linux/slab.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-
- static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out);
-
-@@ -46,6 +48,46 @@ int bcma_arch_register_fallback_sprom(in
- return 0;
- }
-
-+#ifdef CONFIG_OF
-+static int bcma_fill_sprom_with_dt(struct bcma_bus *bus,
-+ struct ssb_sprom *out)
-+{
-+ const phandle *handle;
-+ struct device_node *sprom_node;
-+ struct platform_device *sprom_dev;
-+ struct ssb_sprom *sprom;
-+
-+ if (!bus->host_pdev || !bus->host_pdev->dev.of_node)
-+ return -ENOENT;
-+
-+ handle = of_get_property(bus->host_pdev->dev.of_node, "sprom", NULL);
-+ if (!handle)
-+ return -ENOENT;
-+
-+ sprom_node = of_find_node_by_phandle(be32_to_cpup(handle));
-+ if (!sprom_node)
-+ return -ENOENT;
-+
-+ sprom_dev = of_find_device_by_node(sprom_node);
-+ if (!sprom_dev)
-+ return -ENOENT;
-+
-+ sprom = platform_get_drvdata(sprom_dev);
-+ if (!sprom)
-+ return -ENOENT;
-+
-+ memcpy(out, sprom, sizeof(*out));
-+
-+ return 0;
-+}
-+#else
-+static int bcma_fill_sprom_with_dt(struct bcma_bus *bus,
-+ struct ssb_sprom *out)
-+{
-+ return -ENOENT;
-+}
-+#endif
-+
- static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
- struct ssb_sprom *out)
- {
-@@ -579,7 +621,14 @@ int bcma_sprom_get(struct bcma_bus *bus)
- u16 *sprom;
- size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
- SSB_SPROMSIZE_WORDS_R10, };
-- int i, err = 0;
-+ int i, err;
-+
-+ err = bcma_fill_sprom_with_dt(bus, &bus->sprom);
-+ if (err == 0) {
-+ bcma_info(bus, "Found sprom from device tree provider\n");
-+ return 0;
-+ }
-+ err = 0;
-
- if (!bus->drv_cc.core)
- return -EOPNOTSUPP;
+++ /dev/null
-From 23bcd5e7cb2aaee48ba8b2351f032a230d948b6f Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sat, 25 Jan 2014 17:03:07 +0100
-Subject: [PATCH 08/15] ARM: BCM5301X: register bcma bus
-
----
- arch/arm/boot/dts/bcm4708.dtsi | 58 ++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 58 insertions(+)
-
---- a/arch/arm/boot/dts/bcm4708.dtsi
-+++ b/arch/arm/boot/dts/bcm4708.dtsi
-@@ -31,4 +31,62 @@
- };
- };
-
-+ nvram0: nvram@0 {
-+ compatible = "brcm,bcm47xx-nvram";
-+ reg = <0x1c000000 0x01000000>;
-+ };
-+
-+ sprom0: sprom@0 {
-+ compatible = "brcm,bcm53xx-sprom";
-+ nvram = <&nvram0>;
-+ };
-+
-+ aix@18000000 {
-+ compatible = "brcm,bus-aix";
-+ reg = <0x18000000 0x1000>;
-+ ranges = <0x00000000 0x18000000 0x00100000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ sprom = <&sprom0>;
-+
-+ usb2@0 {
-+ reg = <0x18021000 0x1000>;
-+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ usb3@0 {
-+ reg = <0x18023000 0x1000>;
-+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ gmac@0 {
-+ reg = <0x18024000 0x1000>;
-+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ gmac@1 {
-+ reg = <0x18025000 0x1000>;
-+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ gmac@2 {
-+ reg = <0x18026000 0x1000>;
-+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ gmac@3 {
-+ reg = <0x18027000 0x1000>;
-+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ pcie@0 {
-+ reg = <0x18012000 0x1000>;
-+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ pcie@1 {
-+ reg = <0x18013000 0x1000>;
-+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+ };
- };
+++ /dev/null
-From f8ea60bbaf880d8d8d99fde3b5155f472e00141f Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Mon, 12 May 2014 20:16:39 +0200
-Subject: [PATCH 09/15] bcma: only map wrap if it is not null
-
-The chipcommon B core does not have a wrap address and it would fail here.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- drivers/bcma/scan.c | 11 +++++++----
- 1 file changed, 7 insertions(+), 4 deletions(-)
-
---- a/drivers/bcma/scan.c
-+++ b/drivers/bcma/scan.c
-@@ -421,10 +421,13 @@ static int bcma_get_next_core(struct bcm
- core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
- if (!core->io_addr)
- return -ENOMEM;
-- core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
-- if (!core->io_wrap) {
-- iounmap(core->io_addr);
-- return -ENOMEM;
-+ if (core->wrap) {
-+ core->io_wrap = ioremap_nocache(core->wrap,
-+ BCMA_CORE_SIZE);
-+ if (!core->io_wrap) {
-+ iounmap(core->io_addr);
-+ return -ENOMEM;
-+ }
- }
- }
- return 0;
+++ /dev/null
-From 9317024aa1d8df94d3b021bc23b57f02a435e96c Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Mon, 12 May 2014 21:57:53 +0200
-Subject: [PATCH 10/15] bcma: store more alternative addresses
-
-Each core could have more than one alternative address. There are cores
-with 8 alternative addresses for different functions. The PHY control
-in the Chip common B core is done through the 2. alternative address
-and not the first one.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- drivers/bcma/scan.c | 9 +++++----
- drivers/usb/host/bcma-hcd.c | 2 +-
- include/linux/bcma/bcma.h | 2 +-
- 3 files changed, 7 insertions(+), 6 deletions(-)
-
---- a/drivers/bcma/scan.c
-+++ b/drivers/bcma/scan.c
-@@ -276,7 +276,7 @@ static int bcma_get_next_core(struct bcm
- struct bcma_device *core)
- {
- u32 tmp;
-- u8 i, j;
-+ u8 i, j, k;
- s32 cia, cib;
- u8 ports[2], wrappers[2];
-
-@@ -367,6 +367,7 @@ static int bcma_get_next_core(struct bcm
- core->addr = tmp;
-
- /* get & parse slave ports */
-+ k = 0;
- for (i = 0; i < ports[1]; i++) {
- for (j = 0; ; j++) {
- tmp = bcma_erom_get_addr_desc(bus, eromptr,
-@@ -376,9 +377,9 @@ static int bcma_get_next_core(struct bcm
- /* pr_debug("erom: slave port %d "
- * "has %d descriptors\n", i, j); */
- break;
-- } else {
-- if (i == 0 && j == 0)
-- core->addr1 = tmp;
-+ } else if (k < 8) {
-+ core->addr_s[k] = tmp;
-+ k++;
- }
- }
- }
---- a/drivers/usb/host/bcma-hcd.c
-+++ b/drivers/usb/host/bcma-hcd.c
-@@ -237,7 +237,7 @@ static int bcma_hcd_probe(struct bcma_de
- bcma_hcd_init_chip(dev);
-
- /* In AI chips EHCI is addrspace 0, OHCI is 1 */
-- ohci_addr = dev->addr1;
-+ ohci_addr = dev->addr_s[0];
- if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749)
- && chipinfo->rev == 0)
- ohci_addr = 0x18009000;
---- a/include/linux/bcma/bcma.h
-+++ b/include/linux/bcma/bcma.h
-@@ -266,7 +266,7 @@ struct bcma_device {
- u8 core_unit;
-
- u32 addr;
-- u32 addr1;
-+ u32 addr_s[8];
- u32 wrap;
-
- void __iomem *io_addr;
+++ /dev/null
-From 6c0df4a483e41ef129caa8948b3bcde7f91de197 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Mon, 12 May 2014 20:33:15 +0200
-Subject: [PATCH 11/15] bcma: add support for chipcommon B core
-
-This core is used on BCM4708 to configure the PCIe and USB3 PHYs and it
-contains the addresses to the Device Management unit. This will be used
-by the PCIe driver first.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- drivers/bcma/Makefile | 1 +
- drivers/bcma/bcma_private.h | 4 ++
- drivers/bcma/driver_chipcommon_b.c | 59 +++++++++++++++++++++++++++++
- drivers/bcma/main.c | 10 +++++
- drivers/bcma/scan.c | 1 +
- include/linux/bcma/bcma.h | 1 +
- include/linux/bcma/bcma_driver_chipcommon.h | 8 ++++
- 7 files changed, 84 insertions(+)
- create mode 100644 drivers/bcma/driver_chipcommon_b.c
-
---- a/drivers/bcma/Makefile
-+++ b/drivers/bcma/Makefile
-@@ -1,5 +1,6 @@
- bcma-y += main.o scan.o core.o sprom.o
- bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
-+bcma-y += driver_chipcommon_b.o
- bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
- bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
- bcma-y += driver_pci.o
---- a/drivers/bcma/bcma_private.h
-+++ b/drivers/bcma/bcma_private.h
-@@ -50,6 +50,10 @@ void bcma_chipco_serial_init(struct bcma
- extern struct platform_device bcma_pflash_dev;
- #endif /* CONFIG_BCMA_DRIVER_MIPS */
-
-+/* driver_chipcommon_b.c */
-+int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
-+void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb);
-+
- /* driver_chipcommon_pmu.c */
- u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
- u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
---- /dev/null
-+++ b/drivers/bcma/driver_chipcommon_b.c
-@@ -0,0 +1,59 @@
-+/*
-+ * Broadcom specific AMBA
-+ * ChipCommon B Unit driver
-+ *
-+ * Copyright 2011, 2014, Hauke Mehrtens <hauke@hauke-m.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include "bcma_private.h"
-+#include <linux/export.h>
-+#include <linux/bcma/bcma.h>
-+
-+static bool bcma_wait_reg(void __iomem *addr, u32 mask, u32 value,
-+ int timeout)
-+{
-+ unsigned long deadline = jiffies + timeout;
-+ u32 val;
-+
-+ do {
-+ val = readl(addr);
-+ if ((val & mask) == value)
-+ return true;
-+ cpu_relax();
-+ udelay(10);
-+ } while (!time_after_eq(jiffies, deadline));
-+
-+ pr_warn("Timeout waiting for register %p!\n", addr);
-+
-+ return false;
-+}
-+
-+void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
-+{
-+ writel(offset, ccb->mii + 0x00);
-+ bcma_wait_reg(ccb->mii + 0x00, 0x0100, 0x0000, 100);
-+ writel(value, ccb->mii + 0x04);
-+ bcma_wait_reg(ccb->mii + 0x00, 0x0100, 0x0000, 100);
-+}
-+EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
-+
-+int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb)
-+{
-+ if (ccb->setup_done)
-+ return 0;
-+
-+ ccb->setup_done = 1;
-+ ccb->mii = ioremap_nocache(ccb->core->addr_s[1], BCMA_CORE_SIZE);
-+ if (!ccb->mii)
-+ return -ENOMEM;
-+
-+ return 0;
-+}
-+
-+void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb)
-+{
-+ if (ccb->mii)
-+ iounmap(ccb->mii);
-+}
---- a/drivers/bcma/main.c
-+++ b/drivers/bcma/main.c
-@@ -164,6 +164,7 @@ static int bcma_register_cores(struct bc
- switch (core->id.id) {
- case BCMA_CORE_4706_CHIPCOMMON:
- case BCMA_CORE_CHIPCOMMON:
-+ case BCMA_CORE_CHIPCOMMON_B:
- case BCMA_CORE_PCI:
- case BCMA_CORE_PCIE:
- case BCMA_CORE_PCIE2:
-@@ -301,6 +302,13 @@ int bcma_bus_register(struct bcma_bus *b
- bcma_core_chipcommon_init(&bus->drv_cc);
- }
-
-+ /* Init CC core */
-+ core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON_B);
-+ if (core) {
-+ bus->drv_cc_b.core = core;
-+ bcma_core_chipcommon_b_init(&bus->drv_cc_b);
-+ }
-+
- /* Init MIPS core */
- core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
- if (core) {
-@@ -355,6 +363,8 @@ void bcma_bus_unregister(struct bcma_bus
- else if (err)
- bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
-
-+ bcma_core_chipcommon_b_free(&bus->drv_cc_b);
-+
- cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
- cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
- cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
---- a/drivers/bcma/scan.c
-+++ b/drivers/bcma/scan.c
-@@ -314,6 +314,7 @@ static int bcma_get_next_core(struct bcm
- /* Some specific cores don't need wrappers */
- switch (core->id.id) {
- case BCMA_CORE_4706_MAC_GBIT_COMMON:
-+ case BCMA_CORE_CHIPCOMMON_B:
- /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
- break;
- default:
---- a/include/linux/bcma/bcma.h
-+++ b/include/linux/bcma/bcma.h
-@@ -337,6 +337,7 @@ struct bcma_bus {
- u8 num;
-
- struct bcma_drv_cc drv_cc;
-+ struct bcma_drv_cc_b drv_cc_b;
- struct bcma_drv_pci drv_pci[2];
- struct bcma_drv_pcie2 drv_pcie2;
- struct bcma_drv_mips drv_mips;
---- a/include/linux/bcma/bcma_driver_chipcommon.h
-+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -644,6 +644,12 @@ struct bcma_drv_cc {
- #endif
- };
-
-+struct bcma_drv_cc_b {
-+ struct bcma_device *core;
-+ u8 setup_done:1;
-+ void __iomem *mii;
-+};
-+
- /* Register access */
- #define bcma_cc_read32(cc, offset) \
- bcma_read32((cc)->core, offset)
-@@ -699,4 +705,6 @@ extern void bcma_pmu_spuravoid_pllupdate
-
- extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
-
-+void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
-+
- #endif /* LINUX_BCMA_DRIVER_CC_H_ */
+++ /dev/null
-From ea422113a5d2778347db6136d95f45a50e2f2d29 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Thu, 29 May 2014 20:54:15 +0200
-Subject: [PATCH 13/15] pci: do not probe too early
-
-Probing is done before the PCIe bridge is fully activated and the
-address spaces does not get assigned to the PCIe devices. Without the
-address space the driver can not register to this device. With this
-patch the driver reregistration is done later.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- drivers/pci/probe.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/pci/probe.c
-+++ b/drivers/pci/probe.c
-@@ -1912,7 +1912,10 @@ struct pci_bus *pci_scan_root_bus(struct
- if (!found)
- pci_bus_update_busn_res_end(b, max);
-
-- pci_bus_add_devices(b);
-+ /* this should be done in arch/arm/kernel/bios32.c, because the
-+ resources for the PCI devices are initilized later and doing
-+ it here will fail. */
-+ /* pci_bus_add_devices(b); */
- return b;
- }
- EXPORT_SYMBOL(pci_scan_root_bus);
+++ /dev/null
-From a0d83e0ad20f6dde0a71ed07da12ca3be8bbdc01 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sun, 18 May 2014 17:15:24 +0200
-Subject: [PATCH 12/15] bcma: add PCI IDs for more devices
-
-This adds the PCI IDs for the BCM4360 and BCM43227.
-Both devices were found on a Netgear R6250 with a BCM4708 ARM SoC.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- drivers/bcma/host_pci.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/bcma/host_pci.c
-+++ b/drivers/bcma/host_pci.c
-@@ -281,6 +281,8 @@ static const struct pci_device_id bcma_p
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
-+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) },
-+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4360) },
- { 0, },
- };
- MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
+++ /dev/null
-From 7475eee716d11f487076f78f26a6e403c06d0c76 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Mon, 12 May 2014 11:55:20 +0200
-Subject: [PATCH 14/15] pcie2-bcma: add new PCIe2 driver for bcma
-
-This driver supports the PCIe controller found on the BCM4708 and
-similar SoCs. The controller itself is automatically detected by bcma.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- arch/arm/mach-bcm/Kconfig | 1 +
- drivers/pci/host/Kconfig | 7 +
- drivers/pci/host/Makefile | 1 +
- drivers/pci/host/pcie2-bcma.c | 594 ++++++++++++++++++++++++++++++++++++++++++
- 4 files changed, 603 insertions(+)
- create mode 100644 drivers/pci/host/pcie2-bcma.c
-
---- a/arch/arm/mach-bcm/Kconfig
-+++ b/arch/arm/mach-bcm/Kconfig
-@@ -45,6 +45,7 @@ config ARCH_BCM_5301X
- select ARM_GLOBAL_TIMER
- select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
- select MIGHT_HAVE_PCI
-+ select PCI_DOMAINS if PCI
- help
- Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
-
---- a/drivers/pci/host/Kconfig
-+++ b/drivers/pci/host/Kconfig
-@@ -33,4 +33,11 @@ config PCI_RCAR_GEN2
- There are 3 internal PCI controllers available with a single
- built-in EHCI/OHCI host controller present on each one.
-
-+config PCI_BCMA
-+ bool "BCMA PCIe2 host controller"
-+ depends on BCMA && OF
-+ help
-+ Say Y here if you want to support a simple generic PCI host
-+ controller, such as the one emulated by kvmtool.
-+
- endmenu
---- a/drivers/pci/host/Makefile
-+++ b/drivers/pci/host/Makefile
-@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
- obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
- obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
- obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
-+obj-$(CONFIG_PCI_BCMA) += pcie2-bcma.o
---- /dev/null
-+++ b/drivers/pci/host/pcie2-bcma.c
-@@ -0,0 +1,594 @@
-+/*
-+ * Northstar PCI-Express driver
-+ * Only supports Root-Complex (RC) mode
-+ *
-+ * Notes:
-+ * PCI Domains are being used to identify the PCIe port 1:1.
-+ *
-+ * Only MEM access is supported, PAX does not support IO.
-+ *
-+ * TODO:
-+ * MSI interrupts,
-+ * DRAM > 128 MBytes (e.g. DMA zones)
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/bug.h>
-+#include <linux/delay.h>
-+#include <linux/pci.h>
-+#include <linux/io.h>
-+#include <linux/ioport.h>
-+#include <linux/interrupt.h>
-+#include <linux/bcma/bcma.h>
-+
-+#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
-+
-+/*
-+ * Register offset definitions
-+ */
-+#define SOC_PCIE_CONTROL 0x000 /* a.k.a. CLK_CONTROL reg */
-+#define SOC_PCIE_PM_STATUS 0x008
-+#define SOC_PCIE_PM_CONTROL 0x00c /* in EP mode only ! */
-+
-+#define SOC_PCIE_EXT_CFG_ADDR 0x120
-+#define SOC_PCIE_EXT_CFG_DATA 0x124
-+#define SOC_PCIE_CFG_ADDR 0x1f8
-+#define SOC_PCIE_CFG_DATA 0x1fc
-+
-+#define SOC_PCIE_SYS_RC_INTX_EN 0x330
-+#define SOC_PCIE_SYS_RC_INTX_CSR 0x334
-+#define SOC_PCIE_SYS_HOST_INTR_EN 0x344
-+#define SOC_PCIE_SYS_HOST_INTR_CSR 0x348
-+
-+#define SOC_PCIE_HDR_OFF 0x400 /* 256 bytes per function */
-+
-+/* 32-bit 4KB in-bound mapping windows for Function 0..3, n=0..7 */
-+#define SOC_PCIE_SYS_IMAP0(f, n) (0xc00 + ((f) << 9)((n) << 2))
-+/* 64-bit in-bound mapping windows for func 0..3 */
-+#define SOC_PCIE_SYS_IMAP1(f) (0xc80 + ((f) << 3))
-+#define SOC_PCIE_SYS_IMAP2(f) (0xcc0 + ((f) << 3))
-+/* 64-bit in-bound address range n=0..2 */
-+#define SOC_PCIE_SYS_IARR(n) (0xd00 + ((n) << 3))
-+/* 64-bit out-bound address filter n=0..2 */
-+#define SOC_PCIE_SYS_OARR(n) (0xd20 + ((n) << 3))
-+/* 64-bit out-bound mapping windows n=0..2 */
-+#define SOC_PCIE_SYS_OMAP(n) (0xd40 + ((n) << 3))
-+
-+#define BCM4360_D11AC_ID 0x43a0
-+#define BCM4360_D11AC2G_ID 0x43a1
-+#define BCM4360_D11AC5G_ID 0x43a2
-+#define BCM4352_D11AC_ID 0x43b1 /* 4352 802.11ac dualband device */
-+#define BCM4352_D11AC2G_ID 0x43b2 /* 4352 802.11ac 2.4G device */
-+#define BCM4352_D11AC5G_ID 0x43b3 /* 4352 802.11ac 5G device */
-+
-+static int bcma_pcie2_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
-+{
-+ struct pci_sys_data *sys = pdev->sysdata;
-+ struct bcma_device *bdev = sys->private_data;
-+
-+ return bdev->irq;
-+}
-+
-+static u32 bcma_pcie2_cfg_base(struct bcma_device *bdev, int busno,
-+ unsigned int devfn, int where)
-+{
-+ int slot = PCI_SLOT(devfn);
-+ int fn = PCI_FUNC(devfn);
-+ u32 addr_reg;
-+
-+ if (busno == 0) {
-+ if (slot >= 1)
-+ return 0;
-+ bcma_write32(bdev, SOC_PCIE_EXT_CFG_ADDR, where & 0xffc);
-+ return SOC_PCIE_EXT_CFG_DATA;
-+ } else {
-+ if (fn > 1)
-+ return 0;
-+ addr_reg = (busno & 0xff) << 20 | (slot << 15) | (fn << 12) |
-+ (where & 0xffc) | (1 & 0x3);
-+
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, addr_reg);
-+ return SOC_PCIE_CFG_DATA;
-+ }
-+}
-+
-+static u32 bcma_pcie2_read_config(struct bcma_device *bdev, int busno,
-+ unsigned int devfn, int where, int size)
-+{
-+ u32 base;
-+ u32 data_reg;
-+
-+ base = bcma_pcie2_cfg_base(bdev, busno, devfn, where);
-+
-+ if (!base)
-+ return ~0UL;
-+
-+ data_reg = bcma_read32(bdev, base);
-+
-+ /* NS: CLASS field is R/O, and set to wrong 0x200 value */
-+ if (busno == 0 && devfn == 0) {
-+ /*
-+ * RC's class is 0x0280, but Linux PCI driver needs 0x604
-+ * for a PCIe bridge. So we must fixup the class code
-+ * to 0x604 here.
-+ */
-+ if ((where & 0xffc) == PCI_CLASS_REVISION) {
-+ data_reg &= 0xff;
-+ data_reg |= 0x604 << 16;
-+ }
-+ }
-+ /* HEADER_TYPE=00 indicates the port in EP mode */
-+
-+ if (size == 4) {
-+ return data_reg;
-+ } else {
-+ u32 mask = (1 << (size * 8)) - 1;
-+ int shift = (where % 4) * 8;
-+ return (data_reg >> shift) & mask;
-+ }
-+}
-+
-+static void bcma_pcie2_write_config(struct bcma_device *bdev, int busno,
-+ unsigned int devfn, int where, int size,
-+ u32 val)
-+{
-+ u32 base;
-+ u32 data_reg;
-+
-+ base = bcma_pcie2_cfg_base(bdev, busno, devfn, where);
-+
-+ if (!base)
-+ return;
-+
-+ if (size < 4) {
-+ u32 mask = (1 << (size * 8)) - 1;
-+ int shift = (where % 4) * 8;
-+ data_reg = bcma_read32(bdev, base);
-+ data_reg &= ~(mask << shift);
-+ data_reg |= (val & mask) << shift;
-+ } else {
-+ data_reg = val;
-+ }
-+
-+ bcma_write32(bdev, base, data_reg);
-+}
-+
-+static u8 bcma_pcie2_read_config8(struct bcma_device *bdev, int busno,
-+ unsigned int devfn, int where)
-+{
-+ return bcma_pcie2_read_config(bdev, busno, devfn, where, 1);
-+}
-+
-+static u16 bcma_pcie2_read_config16(struct bcma_device *bdev, int busno,
-+ unsigned int devfn, int where)
-+{
-+ return bcma_pcie2_read_config(bdev, busno, devfn, where, 2);
-+}
-+
-+static u32 bcma_pcie2_read_config32(struct bcma_device *bdev, int busno,
-+ unsigned int devfn, int where)
-+{
-+ return bcma_pcie2_read_config(bdev, busno, devfn, where, 4);
-+}
-+
-+static void bcma_pcie2_write_config8(struct bcma_device *bdev, int busno,
-+ unsigned int devfn, int where, u8 val)
-+{
-+ return bcma_pcie2_write_config(bdev, busno, devfn, where, 1, val);
-+}
-+
-+static void bcma_pcie2_write_config16(struct bcma_device *bdev, int busno,
-+ unsigned int devfn, int where, u16 val)
-+{
-+ return bcma_pcie2_write_config(bdev, busno, devfn, where, 2, val);
-+}
-+
-+static void bcma_pcie2_write_config32(struct bcma_device *bdev, int busno,
-+ unsigned int devfn, int where, u32 val)
-+{
-+ return bcma_pcie2_write_config(bdev, busno, devfn, where, 4, val);
-+}
-+
-+static int bcma_pcie2_read_config_pci(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 *val)
-+{
-+ struct pci_sys_data *sys = bus->sysdata;
-+ struct bcma_device *bdev = sys->private_data;
-+
-+ *val = bcma_pcie2_read_config(bdev, bus->number, devfn, where, size);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int bcma_pcie2_write_config_pci(struct pci_bus *bus, unsigned int devfn,
-+ int where, int size, u32 val)
-+{
-+ struct pci_sys_data *sys = bus->sysdata;
-+ struct bcma_device *bdev = sys->private_data;
-+
-+ bcma_pcie2_write_config(bdev, bus->number, devfn, where, size, val);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+/*
-+ * Check link status, return 0 if link is up in RC mode,
-+ * otherwise return non-zero
-+ */
-+static int bcma_pcie2_check_link(struct bcma_device *bdev, u32 allow_gen2)
-+{
-+ u32 devfn = 0;
-+ u8 tmp8;
-+ u32 tmp32;
-+
-+ tmp32 = bcma_pcie2_read_config32(bdev, 0, devfn, 0xdc);
-+ tmp32 &= ~0xf;
-+ if (allow_gen2)
-+ tmp32 |= 2;
-+ else {
-+ /* force PCIE GEN1 */
-+ tmp32 |= 1;
-+ }
-+ bcma_pcie2_write_config32(bdev, 0, devfn, 0xdc, tmp32);
-+
-+ /* See if the port is in EP mode, indicated by header type 00 */
-+ tmp8 = bcma_pcie2_read_config8(bdev, 0, devfn, PCI_HEADER_TYPE);
-+ if (tmp8 != PCI_HEADER_TYPE_BRIDGE) {
-+ dev_info(&bdev->dev, "Port %d in End-Point mode - ignored\n",
-+ bdev->core_unit);
-+ return -ENODEV;
-+ }
-+
-+ return 0;
-+}
-+
-+/*
-+ * Initializte the PCIe controller
-+ */
-+static void bcma_pcie2_hw_init(struct bcma_device *bdev)
-+{
-+ u32 devfn = 0;
-+ u32 tmp32;
-+ u16 tmp16;
-+
-+ /* Change MPS and MRRS to 512 */
-+ tmp16 = bcma_pcie2_read_config16(bdev, 0, devfn, 0x4d4);
-+ tmp16 &= ~7;
-+ tmp16 |= 2;
-+ bcma_pcie2_write_config16(bdev, 0, devfn, 0x4d4, tmp16);
-+
-+ tmp32 = bcma_pcie2_read_config32(bdev, 0, devfn, 0xb4);
-+ tmp32 &= ~((7 << 12) | (7 << 5));
-+ tmp32 |= (2 << 12) | (2 << 5);
-+ bcma_pcie2_write_config32(bdev, 0, devfn, 0xb4, tmp32);
-+
-+ /* Turn-on Root-Complex (RC) mode, from reset defailt of EP */
-+
-+ /* The mode is set by straps, can be overwritten via DMU
-+ register <cru_straps_control> bit 5, "1" means RC
-+ */
-+
-+ /* Send a downstream reset */
-+ bcma_write32(bdev, SOC_PCIE_CONTROL, 0x3);
-+ udelay(250);
-+ bcma_write32(bdev, SOC_PCIE_CONTROL, 0x1);
-+ mdelay(250);
-+
-+ /* TBD: take care of PM, check we're on */
-+}
-+
-+/*
-+ * Setup the address translation
-+ */
-+static void bcma_pcie2_map_init(struct bcma_device *bdev)
-+{
-+ unsigned size, i;
-+ u32 addr;
-+
-+ /*
-+ * NOTE:
-+ * All PCI-to-CPU address mapping are 1:1 for simplicity
-+ */
-+
-+ /* Outbound address translation setup */
-+ size = SZ_128M;
-+ addr = bdev->addr_s[0];
-+ BUG_ON(!addr);
-+ BUG_ON(addr & ((1 << 25) - 1)); /* 64MB alignment */
-+
-+ for (i = 0; i < 3; i++) {
-+ const unsigned win_size = SZ_64M;
-+ /* 64-bit LE regs, write low word, high is 0 at reset */
-+ bcma_write32(bdev, SOC_PCIE_SYS_OMAP(i), addr);
-+ bcma_write32(bdev, SOC_PCIE_SYS_OARR(i), addr|0x1);
-+ addr += win_size;
-+ if (size >= win_size)
-+ size -= win_size;
-+ if (size == 0)
-+ break;
-+ }
-+ WARN_ON(size > 0);
-+
-+ /*
-+ * Inbound address translation setup
-+ * Northstar only maps up to 128 MiB inbound, DRAM could be up to 1 GiB.
-+ *
-+ * For now allow access to entire DRAM, assuming it is less than 128MiB,
-+ * otherwise DMA bouncing mechanism may be required.
-+ * Also consider DMA mask to limit DMA physical address
-+ */
-+ size = SZ_128M;
-+ addr = PHYS_OFFSET;
-+
-+ size >>= 20; /* In MB */
-+ size &= 0xff; /* Size is an 8-bit field */
-+
-+ WARN_ON(size == 0);
-+ /* 64-bit LE regs, write low word, high is 0 at reset */
-+ bcma_write32(bdev, SOC_PCIE_SYS_IMAP1(0), addr | 0x1);
-+ bcma_write32(bdev, SOC_PCIE_SYS_IARR(1), addr | size);
-+
-+#ifdef CONFIG_SPARSEMEM
-+ addr = PHYS_OFFSET2;
-+ bcma_write32(bdev, SOC_PCIE_SYS_IMAP2(0), addr | 0x1);
-+ bcma_write32(bdev, SOC_PCIE_SYS_IARR(2), addr | size);
-+#endif
-+}
-+
-+/*
-+ * Setup PCIE Host bridge
-+ */
-+static void bcma_pcie2_bridge_init(struct bcma_device *bdev)
-+{
-+ u32 devfn = 0;
-+ u8 tmp8;
-+ u16 tmp16;
-+
-+ bcma_pcie2_write_config8(bdev, 0, devfn, PCI_PRIMARY_BUS, 0);
-+ bcma_pcie2_write_config8(bdev, 0, devfn, PCI_SECONDARY_BUS, 1);
-+ bcma_pcie2_write_config8(bdev, 0, devfn, PCI_SUBORDINATE_BUS, 4);
-+
-+ tmp8 = bcma_pcie2_read_config8(bdev, 0, devfn, PCI_PRIMARY_BUS);
-+ tmp8 = bcma_pcie2_read_config8(bdev, 0, devfn, PCI_SECONDARY_BUS);
-+ tmp8 = bcma_pcie2_read_config8(bdev, 0, devfn, PCI_SUBORDINATE_BUS);
-+
-+ /* MEM_BASE, MEM_LIM require 1MB alignment */
-+ BUG_ON((bdev->addr_s[0] >> 16) & 0xf);
-+ bcma_pcie2_write_config16(bdev, 0, devfn, PCI_MEMORY_BASE,
-+ bdev->addr_s[0] >> 16);
-+ BUG_ON(((bdev->addr_s[0] + SZ_128M) >> 16) & 0xf);
-+ bcma_pcie2_write_config16(bdev, 0, devfn, PCI_MEMORY_LIMIT,
-+ (bdev->addr_s[0] + SZ_128M) >> 16);
-+
-+ /* These registers are not supported on the NS */
-+ bcma_pcie2_write_config16(bdev, 0, devfn, PCI_IO_BASE_UPPER16, 0);
-+ bcma_pcie2_write_config16(bdev, 0, devfn, PCI_IO_LIMIT_UPPER16, 0);
-+
-+ /* Force class to that of a Bridge */
-+ bcma_pcie2_write_config16(bdev, 0, devfn, PCI_CLASS_DEVICE,
-+ PCI_CLASS_BRIDGE_PCI);
-+
-+ tmp16 = bcma_pcie2_read_config16(bdev, 0, devfn, PCI_CLASS_DEVICE);
-+ tmp16 = bcma_pcie2_read_config16(bdev, 0, devfn, PCI_MEMORY_BASE);
-+ tmp16 = bcma_pcie2_read_config16(bdev, 0, devfn, PCI_MEMORY_LIMIT);
-+}
-+
-+static int bcma_pcie2_allow_gen2_rc(struct bcma_device *bdev)
-+{
-+ u32 vendorid, devid, chipid, chiprev;
-+ u32 val, bar;
-+ void __iomem *base;
-+ int allow = 1;
-+
-+ /* Read PCI vendor/device ID's */
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, 0x0);
-+ val = bcma_read32(bdev, SOC_PCIE_CFG_DATA);
-+ vendorid = val & 0xffff;
-+ devid = val >> 16;
-+ if (vendorid == PCI_VENDOR_ID_BROADCOM &&
-+ (devid == BCMA_CHIP_ID_BCM4360 || devid == BCM4360_D11AC_ID ||
-+ devid == BCM4360_D11AC2G_ID || devid == BCM4360_D11AC5G_ID ||
-+ devid == BCM4352_D11AC_ID || devid == BCM4352_D11AC2G_ID ||
-+ devid == BCM4352_D11AC5G_ID)) {
-+ /* Config BAR0 */
-+ bar = bdev->addr_s[0];
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, 0x10);
-+ bcma_write32(bdev, SOC_PCIE_CFG_DATA, bar);
-+ /* Config BAR0 window to access chipc */
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, 0x80);
-+ bcma_write32(bdev, SOC_PCIE_CFG_DATA, SI_ENUM_BASE);
-+
-+ /* Enable memory resource */
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, 0x4);
-+ val = bcma_read32(bdev, SOC_PCIE_CFG_DATA);
-+ val |= PCI_COMMAND_MEMORY;
-+ bcma_write32(bdev, SOC_PCIE_CFG_DATA, val);
-+ /* Enable memory and bus master */
-+ bcma_write32(bdev, SOC_PCIE_HDR_OFF + 4, 0x6);
-+
-+ /* Read CHIP ID */
-+ base = ioremap(bar, 0x1000);
-+ val = __raw_readl(base);
-+ iounmap(base);
-+ chipid = val & 0xffff;
-+ chiprev = (val >> 16) & 0xf;
-+ if ((chipid == BCMA_CHIP_ID_BCM4360 ||
-+ chipid == BCMA_CHIP_ID_BCM43460 ||
-+ chipid == BCMA_CHIP_ID_BCM4352) && (chiprev < 3))
-+ allow = 0;
-+ }
-+ return allow;
-+}
-+
-+static void bcma_pcie2_3rd_init(struct bcma_bus *bus)
-+{
-+ /* PCIE PLL block register (base 0x8000) */
-+ bcma_chipco_b_mii_write(&bus->drv_cc_b, 0x00000088, 0x57fe8000);
-+ /* Check PCIE PLL lock status */
-+ bcma_chipco_b_mii_write(&bus->drv_cc_b, 0x00000088, 0x67c60000);
-+}
-+
-+/* To improve PCIE phy jitter */
-+static void bcma_pcie2_improve_phy_jitter(struct bcma_bus *bus, int phyaddr)
-+{
-+ u32 val;
-+
-+ /* Change blkaddr */
-+ val = (1 << 30) | (1 << 28) | (phyaddr << 23) | (0x1f << 18) |
-+ (2 << 16) | (0x863 << 4);
-+ bcma_chipco_b_mii_write(&bus->drv_cc_b, 0x0000009a, val);
-+
-+ /* Write 0x0190 to 0x13 regaddr */
-+ val = (1 << 30) | (1 << 28) | (phyaddr << 23) | (0x13 << 18) |
-+ (2 << 16) | 0x0190;
-+ bcma_chipco_b_mii_write(&bus->drv_cc_b, 0x0000009a, val);
-+
-+ /* Write 0x0191 to 0x19 regaddr */
-+ val = (1 << 30) | (1 << 28) | (phyaddr << 23) | (0x19 << 18) |
-+ (2 << 16) | 0x0191;
-+ bcma_chipco_b_mii_write(&bus->drv_cc_b, 0x0000009a, val);
-+}
-+
-+static int bcma_pcie2_setup(int nr, struct pci_sys_data *sys)
-+{
-+ struct bcma_device *bdev = sys->private_data;
-+ struct bcma_bus *bus = bdev->bus;
-+ struct resource *res;
-+ struct bcma_device *arm_core;
-+ u32 cru_straps_ctrl;
-+ int allow_gen2, linkfail;
-+ int phyaddr;
-+
-+ if (bdev->core_unit == 2) {
-+ arm_core = bcma_find_core(bus, BCMA_CORE_ARMCA9);
-+ cru_straps_ctrl = bcma_read32(arm_core, 0x2a0);
-+
-+ /* 3rd PCIE is not selected */
-+ if (cru_straps_ctrl & 0x10)
-+ return -ENODEV;
-+
-+ bcma_pcie2_3rd_init(bus);
-+ phyaddr = 0xf;
-+ } else {
-+ phyaddr = bdev->core_unit;
-+ }
-+ bcma_pcie2_improve_phy_jitter(bus, phyaddr);
-+
-+ /* create mem resource */
-+ res = devm_kzalloc(&bdev->dev, sizeof(*res), GFP_KERNEL);
-+ if (!res) {
-+ dev_info(&bdev->dev, "requesting resource at 0x%x failed\n",
-+ bdev->addr_s[0]);
-+ return -EINVAL;
-+ }
-+ res->start = bdev->addr_s[0];
-+ res->end = res->start + SZ_128M - 1;
-+ res->name = "PCIe Configuration Space";
-+ res->flags = IORESOURCE_MEM;
-+
-+ pci_add_resource(&sys->resources, res);
-+
-+ /* This PCIe controller does not support IO Mem, so use a dummy one. */
-+ res = devm_kzalloc(&bdev->dev, sizeof(*res), GFP_KERNEL);
-+ if (!res) {
-+ dev_info(&bdev->dev, "requesting resource at 0x%x failed\n",
-+ bdev->addr_s[0]);
-+ return -EINVAL;
-+ }
-+ res->start = bdev->addr_s[0];
-+ res->end = res->start + SZ_128M - 1;
-+ res->name = "PCIe Configuration Space";
-+ res->flags = IORESOURCE_IO;
-+
-+ pci_add_resource(&sys->resources, res);
-+
-+ for (allow_gen2 = 0; allow_gen2 <= 1; allow_gen2++) {
-+ bcma_pcie2_hw_init(bdev);
-+ bcma_pcie2_map_init(bdev);
-+
-+ /*
-+ * Skip inactive ports -
-+ * will need to change this for hot-plugging
-+ */
-+ linkfail = bcma_pcie2_check_link(bdev, allow_gen2);
-+ if (linkfail)
-+ break;
-+
-+ bcma_pcie2_bridge_init(bdev);
-+
-+ if (allow_gen2 == 0) {
-+ if (bcma_pcie2_allow_gen2_rc(bdev) == 0)
-+ break;
-+ dev_info(&bdev->dev, "switching to GEN2\n");
-+ }
-+ }
-+
-+ if (linkfail)
-+ return -1;
-+
-+ return 1;
-+}
-+
-+/*
-+ * Methods for accessing configuration registers
-+ */
-+static struct pci_ops bcma_pcie2_ops = {
-+ .read = bcma_pcie2_read_config_pci,
-+ .write = bcma_pcie2_write_config_pci,
-+};
-+
-+static int bcma_pcie2_probe(struct bcma_device *bdev)
-+{
-+ struct hw_pci hw;
-+
-+ dev_info(&bdev->dev, "scanning bus\n");
-+
-+ hw = (struct hw_pci) {
-+ .nr_controllers = 1,
-+ .domain = bdev->core_unit,
-+ .private_data = (void **)&bdev,
-+ .setup = bcma_pcie2_setup,
-+ .map_irq = bcma_pcie2_map_irq,
-+ .ops = &bcma_pcie2_ops,
-+ };
-+
-+ /* Announce this port to ARM/PCI common code */
-+ pci_common_init_dev(&bdev->dev, &hw);
-+
-+ /* Setup virtual-wire interrupts */
-+ bcma_write32(bdev, SOC_PCIE_SYS_RC_INTX_EN, 0xf);
-+
-+ /* Enable memory and bus master */
-+ bcma_write32(bdev, SOC_PCIE_HDR_OFF + 4, 0x6);
-+
-+ return 0;
-+}
-+
-+static const struct bcma_device_id bcma_pcie2_table[] = {
-+ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_PCIEG2, BCMA_ANY_REV, BCMA_ANY_CLASS),
-+ BCMA_CORETABLE_END
-+};
-+MODULE_DEVICE_TABLE(bcma, bcma_pcie2_table);
-+
-+static struct bcma_driver bcma_pcie2_driver = {
-+ .name = KBUILD_MODNAME,
-+ .id_table = bcma_pcie2_table,
-+ .probe = bcma_pcie2_probe,
-+};
-+
-+static int __init bcma_pcie2_init(void)
-+{
-+ return bcma_driver_register(&bcma_pcie2_driver);
-+}
-+module_init(bcma_pcie2_init);
-+
-+static void __exit bcma_pcie2_exit(void)
-+{
-+ bcma_driver_unregister(&bcma_pcie2_driver);
-+}
-+module_exit(bcma_pcie2_exit);
-+
-+MODULE_AUTHOR("Hauke Mehrtens");
-+MODULE_DESCRIPTION("PCIe Gen2 driver for BCMA");
-+MODULE_LICENSE("GPLv2");
+++ /dev/null
-From 0bd576e93a188fd3aab769b622fb3d35fa9bc7a7 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sat, 3 May 2014 19:55:38 +0200
-Subject: [PATCH 15/15] bgmac: some fixes to get bgmac work
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- drivers/net/ethernet/broadcom/Kconfig | 2 +-
- drivers/net/phy/phy_device.c | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/net/ethernet/broadcom/Kconfig
-+++ b/drivers/net/ethernet/broadcom/Kconfig
-@@ -131,7 +131,7 @@ config BNX2X_SRIOV
-
- config BGMAC
- tristate "BCMA bus GBit core support"
-- depends on BCMA_HOST_SOC && HAS_DMA && BCM47XX
-+ depends on BCMA_HOST_SOC && HAS_DMA
- select PHYLIB
- ---help---
- This driver supports GBit MAC and BCM4706 GBit MAC cores on BCMA bus.
---- a/drivers/net/phy/phy_device.c
-+++ b/drivers/net/phy/phy_device.c
-@@ -898,7 +898,7 @@ int genphy_update_link(struct phy_device
- return status;
-
- if ((status & BMSR_LSTATUS) == 0)
-- phydev->link = 0;
-+ phydev->link = 1;
- else
- phydev->link = 1;
-
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Generic
- NAME:=Broadcom SoC, BCM43xx WiFi (b43, default)
-endef
-
-define Profile/Generic/Description
- Package set compatible with hardware any Broadcom BCM47xx or BCM535x
- SoC with a ARM CPU like the BCM4707, BCM4708, BCM4709, BCM53010
-endef
-
-$(eval $(call Profile,Generic))
-
+++ /dev/null
-#
-# Copyright (C) 2009-2011 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=mipsel
-BOARD:=cobalt
-BOARDNAME:=Cobalt Microservers
-FEATURES:=targz pci ext4 display
-CPU_TYPE := 5k
-CPU_CFLAGS_5k := -march=r5000
-MAINTAINER:=Florian Fainelli <florian@openwrt.org>
-
-LINUX_VERSION:=3.3.8
-
-include $(INCLUDE_DIR)/target.mk
-
-define Target/Description
- Build firmware images for Cobalt servers systems (Qube/Qube2/RaQ/RaQ2).
-endef
-
-$(eval $(call BuildTarget))
+++ /dev/null
-#!/bin/sh
-# Copyright (C) 2009-2013 OpenWrt.org
-
-. /lib/functions/leds.sh
-
-status_led="qube::front"
-
-set_state() {
- case "$1" in
- preinit)
- status_led_on
- ;;
- done)
- status_led_off
- ;;
- esac
-}
+++ /dev/null
-# CONFIG_32BIT is not set
-CONFIG_64BIT=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y
-# CONFIG_ARPD is not set
-CONFIG_ATA=y
-CONFIG_BINFMT_ELF32=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLOCK_COMPAT=y
-# CONFIG_BRIDGE is not set
-CONFIG_CEVT_GT641XX=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKBLD_I8253=y
-CONFIG_CLKEVT_I8253=y
-CONFIG_CLKSRC_I8253=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyS0,115200"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMPAT=y
-CONFIG_COMPAT_BRK=y
-CONFIG_COMPAT_NETLINK_MESSAGES=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_NEVADA=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HUGEPAGES=y
-CONFIG_CSRC_R4K=y
-CONFIG_DE2104X=y
-CONFIG_DE2104X_DSL=0
-# CONFIG_DE4X5 is not set
-CONFIG_DEVKMEM=y
-# CONFIG_DM9102 is not set
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DNOTIFY=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ACL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIO_DEVRES=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-# CONFIG_HIGH_RES_TIMERS is not set
-# CONFIG_HUGETLBFS is not set
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_I8253=y
-CONFIG_I8259=y
-CONFIG_INPUT=y
-# CONFIG_INPUT_COBALT_BTNS is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_MULTICAST is not set
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_GT641XX=y
-CONFIG_IRQ_WORK=y
-# CONFIG_JFFS2_FS is not set
-CONFIG_KEXEC=y
-CONFIG_LEDS_COBALT_QUBE=y
-CONFIG_LEDS_COBALT_RAQ=y
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_MII is not set
-CONFIG_MIPS=y
-CONFIG_MIPS32_COMPAT=y
-CONFIG_MIPS32_N32=y
-CONFIG_MIPS32_O32=y
-CONFIG_MIPS_COBALT=y
-CONFIG_MIPS_EXTERNAL_TIMER=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MTD_BLOCK is not set
-# CONFIG_MTD_BLOCK_RO is not set
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_TULIP=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PATA_VIA=y
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_GT64XXX_PCI0=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_RAID_ATTRS=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RELAY=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_SATA_PMP=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SECCOMP=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SYSVIPC_COMPAT=y
-CONFIG_SYS_HAS_CPU_NEVADA=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_HUGETLBFS=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TULIP=y
-CONFIG_TULIP_MMIO=y
-CONFIG_TULIP_MWI=y
-CONFIG_TULIP_NAPI=y
-CONFIG_TULIP_NAPI_HW_MITIGATION=y
-CONFIG_UIDGID_CONVERTED=y
-# CONFIG_ULI526X is not set
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_VLAN_8021Q is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_WATCHDOG is not set
-# CONFIG_WINBOND_840 is not set
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-# CONFIG_32BIT is not set
-CONFIG_64BIT=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARPD is not set
-CONFIG_ATA=y
-CONFIG_BINFMT_ELF32=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLOCK_COMPAT=y
-# CONFIG_BRIDGE is not set
-CONFIG_CEVT_GT641XX=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_R4K_LIB=y
-CONFIG_CLKBLD_I8253=y
-CONFIG_CLKEVT_I8253=y
-CONFIG_CLKSRC_I8253=y
-CONFIG_CMDLINE="console=ttyS0,115200"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMPAT=y
-CONFIG_COMPAT_BRK=y
-CONFIG_COMPAT_NETLINK_MESSAGES=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_NEVADA=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-CONFIG_CSRC_R4K=y
-CONFIG_CSRC_R4K_LIB=y
-CONFIG_DE2104X=y
-CONFIG_DE2104X_DSL=0
-# CONFIG_DE4X5 is not set
-CONFIG_DEVKMEM=y
-# CONFIG_DM9102 is not set
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DNOTIFY=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_ELF_CORE=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ACL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_WRAPPERS=y
-CONFIG_HID=m
-CONFIG_HID_SUPPORT=y
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_I8253=y
-CONFIG_I8259=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_MULTICAST is not set
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_GT641XX=y
-# CONFIG_JFFS2_FS is not set
-CONFIG_KEXEC=y
-CONFIG_LEDS_COBALT_QUBE=y
-CONFIG_LEDS_COBALT_RAQ=y
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_MII is not set
-CONFIG_MIPS=y
-CONFIG_MIPS32_COMPAT=y
-CONFIG_MIPS32_N32=y
-CONFIG_MIPS32_O32=y
-CONFIG_MIPS_COBALT=y
-CONFIG_MIPS_EXTERNAL_TIMER=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MTD_BLOCK is not set
-# CONFIG_MTD_BLOCK_RO is not set
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_TULIP=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PATA_VIA=y
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_GT64XXX_PCI0=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_RAID_ATTRS=y
-CONFIG_RELAY=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_SATA_PMP=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SECCOMP=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SYSVIPC_COMPAT=y
-CONFIG_SYS_HAS_CPU_NEVADA=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TULIP=y
-CONFIG_TULIP_MMIO=y
-CONFIG_TULIP_MWI=y
-CONFIG_TULIP_NAPI=y
-CONFIG_TULIP_NAPI_HW_MITIGATION=y
-# CONFIG_ULI526X is not set
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_VLAN_8021Q is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_WATCHDOG is not set
-# CONFIG_WINBOND_840 is not set
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2009-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/BuildKernel
- cp $(KDIR)/vmlinux.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.elf
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
-endef
-
-define Image/Build
- $(call Image/Build/$(1))
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define KernelPackage/fb-cobalt
- SUBMENU:=$(VIDEO_MENU)
- TITLE:=Cobalt framebuffer support
- DEPENDS:=@TARGET_cobalt +kmod-fb
- KCONFIG:=CONFIG_FB_COBALT
- FILES:=$(LINUX_DIR)/drivers/video/cobalt_lcdfb.ko
- AUTOLOAD:=$(call AutoLoad,50,cobalt_lcdfb)
-endef
-
-define KernelPackage/fb-cobalt/descriptione
- Kernel module for the Cobalt Microservers framebuffer
-endef
-
-$(eval $(call KernelPackage,fb-cobalt))
-
-define KernelPackage/cobalt-btns
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Cobalt buttons support
- DEPENDS:=@TARGET_cobalt +kmod-input-evdev +kmod-input-polldev
- KCONFIG:=CONFIG_INPUT_COBALT_BTNS
- FILES:=$(LINUX_DIR)/drivers/input/misc/cobalt_btns.ko
- AUTOLOAD:=$(call AutoLoad,62,cobalt_btns)
-endef
-
-define KernelPackage/cobalt-btns/description
- Kernel module for the Cobalt Microservers buttons
-endef
-
-$(eval $(call KernelPackage,cobalt-btns))
+++ /dev/null
-#
-# Copyright (C) 2009-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=ep93xx
-BOARDNAME:=Cirrus Logic EP93xx
-FEATURES:=squashfs ext4 targz usb display sound
-CPU_TYPE:=arm920t
-MAINTAINER:=Florian Fainelli <florian@openwrt.org>
-
-LINUX_VERSION:=3.8.13
-
-DEVICE_TYPE:=developerboard
-
-include $(INCLUDE_DIR)/target.mk
-
-KERNELNAME:="uImage"
-
-$(eval $(call BuildTarget))
+++ /dev/null
-::sysinit:/etc/init.d/rcS S boot
-::shutdown:/etc/init.d/rcS K shutdown
-tts/0::askfirst:/bin/ash --login
-ttyAM0::askfirst:/bin/ash --login
-tty1::askfirst:/bin/ash --login
+++ /dev/null
-#!/bin/sh
-# Copyright (C) 2010 OpenWrt.org
-
-. /lib/functions.sh
-
-set_ether_mac() {
- mac=$(sed -n 's/^Serial.* 000000/02/p' /proc/cpuinfo)
- ifconfig eth0 hw ether $mac
-}
-
-boot_hook_add preinit_main set_ether_mac
-
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_EP93XX=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USES_GETTIMEOFFSET=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=16
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_VIC=y
-CONFIG_ARM_VIC_NR=2
-# CONFIG_ARPD is not set
-CONFIG_ATAGS=y
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyAM0,57600 init=/etc/preinit"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CPU_32v4T=y
-CONFIG_CPU_ABRT_EV4T=y
-CONFIG_CPU_ARM920T=y
-CONFIG_CPU_CACHE_V4WT=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRC7=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRUNCH=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_USER is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_EP93XX_EARLY_UART1=y
-# CONFIG_EP93XX_EARLY_UART2 is not set
-# CONFIG_EP93XX_EARLY_UART3 is not set
-CONFIG_EP93XX_ETH=y
-# CONFIG_EP93XX_PWM is not set
-CONFIG_EP93XX_SDCE0_PHYS_OFFSET=y
-# CONFIG_EP93XX_SDCE1_PHYS_OFFSET is not set
-# CONFIG_EP93XX_SDCE2_PHYS_OFFSET is not set
-# CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET is not set
-# CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET is not set
-CONFIG_EP93XX_SOC_COMMON=y
-CONFIG_EP93XX_WATCHDOG=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_EP93XX=y
-CONFIG_GPIO_GENERIC=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HW_CONSOLE=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_INPUT=y
-# CONFIG_INPUT_MISC is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_WORK=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_LEDS_GPIO_REGISTER=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_MACH_EDB9302A is not set
-# CONFIG_MACH_EDB9307A is not set
-# CONFIG_MACH_EDB9315A is not set
-CONFIG_MACH_SIM_ONE=y
-# CONFIG_MACH_SNAPPER_CL15 is not set
-# CONFIG_MACH_VISION_EP9307 is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SPI=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_CFI_STAA=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_RAM=y
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_MACH_MEMORY_H=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_USE_VMALLOC=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_RCU_STALL_COMMON is not set
-# CONFIG_SCHED_HRTICK is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_AMBA_PL010=y
-CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
-# CONFIG_SERIAL_AMBA_PL011 is not set
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_EP93XX=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_BU21013 is not set
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_EP93XX is not set
-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_MAX11801 is not set
-# CONFIG_TOUCHSCREEN_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_ST1232 is not set
-# CONFIG_TOUCHSCREEN_TSC2005 is not set
-# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
-CONFIG_UID16=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB_ARCH_HAS_XHCI is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VIDEO_OUTPUT_CONTROL=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_EP93XX=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USES_GETTIMEOFFSET=y
-# CONFIG_ARCH_VT8500_SINGLE is not set
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=16
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_VIC=y
-CONFIG_ARM_VIC_NR=2
-# CONFIG_ARPD is not set
-CONFIG_ATAGS=y
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyAM0,57600 init=/etc/preinit"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CPU_32v4T=y
-CONFIG_CPU_ABRT_EV4T=y
-CONFIG_CPU_ARM920T=y
-CONFIG_CPU_CACHE_V4WT=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRC7=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRUNCH=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_USER is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_EP93XX_EARLY_UART1=y
-# CONFIG_EP93XX_EARLY_UART2 is not set
-# CONFIG_EP93XX_EARLY_UART3 is not set
-CONFIG_EP93XX_ETH=y
-# CONFIG_EP93XX_PWM is not set
-CONFIG_EP93XX_SDCE0_PHYS_OFFSET=y
-# CONFIG_EP93XX_SDCE1_PHYS_OFFSET is not set
-# CONFIG_EP93XX_SDCE2_PHYS_OFFSET is not set
-# CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET is not set
-# CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET is not set
-CONFIG_EP93XX_SOC_COMMON=y
-CONFIG_EP93XX_WATCHDOG=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_EP93XX=y
-CONFIG_GPIO_GENERIC=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_AOUT=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HW_CONSOLE=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_INPUT=y
-# CONFIG_INPUT_MISC is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_LEDS_GPIO_REGISTER=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_MACH_EDB9302A is not set
-# CONFIG_MACH_EDB9307A is not set
-# CONFIG_MACH_EDB9315A is not set
-CONFIG_MACH_SIM_ONE=y
-# CONFIG_MACH_SNAPPER_CL15 is not set
-# CONFIG_MACH_VISION_EP9307 is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SPI=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_CFI_STAA=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_RAM=y
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_MACH_MEMORY_H=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERCPU_RWSEM=y
-CONFIG_PERF_USE_VMALLOC=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_AMBA_PL010=y
-CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
-# CONFIG_SERIAL_AMBA_PL011 is not set
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_EP93XX=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_BU21013 is not set
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_EP93XX is not set
-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_MAX11801 is not set
-# CONFIG_TOUCHSCREEN_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_ST1232 is not set
-# CONFIG_TOUCHSCREEN_TSC2005 is not set
-# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
-CONFIG_UID16=y
-CONFIG_UIDGID_CONVERTED=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB_ARCH_HAS_XHCI is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VIDEO_OUTPUT_CONTROL=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2009-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage
-fs_squash:=squashfs-only
-fs_all:=all
-fs_4k:=4k
-fs_64k:=64k
-fs_128k:=128k
-
-define Image/BuildKernel
- cp $(KDIR)/uImage $(UIMAGE)
-ifeq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),y)
- cp $(KDIR)/uImage-initramfs $(UIMAGE)-initramfs
-endif
-endef
-
-define Image/Build/jffs2-64k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=64k conv=sync
-endef
-
-define Image/Build/jffs2-128k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync
-endef
-
-define Image/Build
- $(call Image/Build/$(1),$(1))
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-#
-# Copyright (C) 2011 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define KernelPackage/fb-ep93xx
- SUBMENU:=$(VIDEO_MENU)
- TITLE:=EP93xx framebuffer support
- DEPENDS:=@TARGET_ep93xx +kmod-fb +kmod-fb-cfb-fillrect \
- +kmod-fb-cfb-copyarea +kmod-fb-cfb-imgblt
- KCONFIG:=CONFIG_FB_EP93XX
- FILES:=$(LINUX_DIR)/drivers/video/ep93xx-fb.ko
- AUTOLOAD:=$(call AutoLoad,51,ep93xx-fb)
-endef
-
-define KernelPackage/fb-ep93xx/description
- EP93xx framebuffer support
-endef
-
-$(eval $(call KernelPackage,fb-ep93xx))
-
-define KernelPackage/input-keyboard-ep93xx
- SUBMENU:=$(OTHER_MENU)
- TITLE:=EP93xx Matrix Keypad support
- DEPENDS:=@TARGET_ep93xx +!LINUX_3_3:kmod-input-matrixkmap
- KCONFIG:= \
- CONFIG_KEYBOARD_EP93XX \
- CONFIG_INPUT_KEYBOARD=y
- FILES:=$(LINUX_DIR)/drivers/input/keyboard/ep93xx_keypad.ko
- AUTOLOAD:=$(call AutoLoad,62,ep93xx_keypad)
- $(call AddDepends/input)
-endef
-
-define KernelPackage/input-keyboard-ep93xx/description
- EP93xx Matrix Keypad support
-endef
-
-$(eval $(call KernelPackage,input-keyboard-ep93xx))
-
-ifeq ($(strip $(call CompareKernelPatchVer,$(KERNEL_PATCHVER),ge,3.8.0)),1)
-SND_EP93XX_SOC_DIR:=cirrus
-else
-SND_EP93XX_SOC_DIR:=ep93xx
-endif
-
-define KernelPackage/sound-soc-ep93xx
- SUBMENU:=$(SOUND_MENU)
- TITLE:=EP93xx SoC sound support
- DEPENDS:=@TARGET_ep93xx +kmod-sound-core +kmod-sound-soc-core
- KCONFIG:=CONFIG_SND_EP93XX_SOC
- FILES:=$(LINUX_DIR)/sound/soc/$(SND_EP93XX_SOC_DIR)/snd-soc-ep93xx.ko
- AUTOLOAD:=$(call AutoLoad,57,snd-soc-ep93xx)
-endef
-
-define KernelPackage/sound-soc-ep93xx/description
- EP93xx SoC sound support
-endef
-
-$(eval $(call KernelPackage,sound-soc-ep93xx))
-
-# Must be loaded prior to sound-soc-ac97 because it exports
-# soc_ac97_ops
-define KernelPackage/sound-soc-ep93xx-ac97
- SUBMENU:=$(SOUND_MENU)
- TITLE:=EP93xx SoC AC97 support
- DEPENDS:=@TARGET_ep93xx +kmod-sound-soc-core
- KCONFIG:=CONFIG_SND_EP93XX_SOC_AC97
- FILES:=$(LINUX_DIR)/sound/soc/$(SND_EP93XX_SOC_DIR)/snd-soc-ep93xx-ac97.ko
- AUTOLOAD:=$(call AutoLoad,56,snd-soc-ep93xx-ac97)
-endef
-
-define KernelPackage/sound-soc-ep93xx-ac97/description
- EP93xx SoC AC97 support
-endef
-
-$(eval $(call KernelPackage,sound-soc-ep93xx-ac97))
-
-define KernelPackage/sound-soc-ep93xx-simone
- SUBMENU:=$(SOUND_MENU)
- TITLE:=Sim.One EP93xx Soc sound support
- DEPENDS:=@TARGET_ep93xx +kmod-sound-soc-core
- KCONFIG:=CONFIG_SND_EP93XX_SOC_SIMONE
- FILES:=$(LINUX_DIR)/sound/soc/$(SND_EP93XX_SOC_DIR)/snd-soc-simone.ko
- AUTOLOAD:=$(call AutoLoad,59,snd-soc-ep93xx)
-endef
-
-define KernelPackage/sound-soc-ep93xx-simone/description
- SimpleMachines Sim.One sound support
-endef
-
-$(eval $(call KernelPackage,sound-soc-ep93xx-simone))
-
-define KernelPackage/touchscreen-ep93xx
- SUBMENU:=$(OTHER_MENU)
- TITLE:=EP93xx input touchscreen support
- DEPENDS:=@TARGET_ep93xx
- KCONFIG:=CONFIG_TOUCHSCREEN_EP93XX
- FILES:=$(LINUX_DIR)/drivers/input/touchscreen/ep93xx_ts.ko
- AUTOLOAD:=$(call AutoLoad,51,ep93xx_ts)
-endef
-
-define KernelPackage/touchscreen-ep93xx/description
- EP93xx SoC input touchscreen support
-endef
-
-$(eval $(call KernelPackage,touchscreen-ep93xx))
-
+++ /dev/null
-This patch puts the EP93xx chip revision and unique ID into /proc/cpuinfo.
-This is necessary to be able to set a unique MAC address for DHCP purposes
-by adding a line to /etc/network/interfaces:
-
-# Generate a unique locally-assigned MAC address from the CPU serial number
-pre-up ifconfig eth0 hw ether `sed -n 's/^Serial.* 000000/02/p' /proc/cpuinfo`
-
-It uses the chip revision reading code in the ep93xx-chip-revision patch.
-
-Really, this is wrong, since /proc/cpuinfo should report the revision and
-serial number of the ARM920T processor, while these are the rev and serial
-of the EP93xx SoC. In a future kernel (>2.6.34) there may be a new file
-/proc/socinfo for this information.
-
- -martinwguy 14 May 2010
-
---- a/arch/arm/kernel/setup.c
-+++ b/arch/arm/kernel/setup.c
-@@ -56,6 +56,12 @@
- #include <asm/memblock.h>
- #include <asm/virt.h>
-
-+#if defined(CONFIG_ARCH_EP93XX)
-+#include <asm/io.h>
-+#include <mach/platform.h>
-+#include <mach/ep93xx-regs.h>
-+#endif
-+
- #include "atags.h"
-
-
-@@ -953,9 +959,16 @@ static int c_show(struct seq_file *m, vo
- }
-
- seq_printf(m, "Hardware\t: %s\n", machine_name);
-+#if defined(CONFIG_ARCH_EP93XX)
-+ seq_printf(m, "Revision\t: %04x\n",
-+ ep93xx_chip_revision());
-+ seq_printf(m, "Serial\t\t: %016x\n",
-+ *((unsigned int *)EP93XX_SECURITY_UNIQID));
-+#else
- seq_printf(m, "Revision\t: %04x\n", system_rev);
- seq_printf(m, "Serial\t\t: %08x%08x\n",
- system_serial_high, system_serial_low);
-+#endif
-
- return 0;
- }
---- a/arch/arm/mach-ep93xx/soc.h
-+++ b/arch/arm/mach-ep93xx/soc.h
-@@ -82,8 +82,6 @@
- #define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000)
- #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
-
--#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
--
- #define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000)
- #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
-
---- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
-+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
-@@ -38,4 +38,8 @@
- #define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000)
- #define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000)
-
-+#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
-+#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x))
-+#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440)
-+
- #endif
+++ /dev/null
----
- arch/arm/mach-ep93xx/include/mach/hardware.h | 1
- arch/arm/mach-ep93xx/include/mach/regs_touch.h | 95 ++
- drivers/input/touchscreen/Kconfig | 5
- drivers/input/touchscreen/Makefile | 1
- drivers/input/touchscreen/ep93xx_ts.c | 1117 +++++++++++++++++++++++++
- drivers/input/touchscreen/ep93xx_ts.h | 53 +
- 6 files changed, 1272 insertions(+)
-
---- a/drivers/input/touchscreen/Kconfig
-+++ b/drivers/input/touchscreen/Kconfig
-@@ -235,6 +235,15 @@ config TOUCHSCREEN_EGALAX
- To compile this driver as a module, choose M here: the
- module will be called egalax_ts.
-
-+config TOUCHSCREEN_EP93XX
-+ tristate "EP93xx Touchscreen"
-+ depends on ARM && INPUT && ARCH_EP93XX
-+ help
-+ Say Y here to enable support for EP93xx touch screen.
-+
-+ To compile this driver as a module, choose M here:
-+ the module will be called ep93xx_ts.
-+
- config TOUCHSCREEN_FUJITSU
- tristate "Fujitsu serial touchscreen"
- select SERIO
---- a/drivers/input/touchscreen/Makefile
-+++ b/drivers/input/touchscreen/Makefile
-@@ -29,6 +29,7 @@ obj-$(CONFIG_TOUCHSCREEN_GUNZE) += gunz
- obj-$(CONFIG_TOUCHSCREEN_EETI) += eeti_ts.o
- obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o
- obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o
-+obj-$(CONFIG_TOUCHSCREEN_EP93XX) += ep93xx_ts.o
- obj-$(CONFIG_TOUCHSCREEN_FUJITSU) += fujitsu_ts.o
- obj-$(CONFIG_TOUCHSCREEN_ILI210X) += ili210x.o
- obj-$(CONFIG_TOUCHSCREEN_INEXIO) += inexio.o
---- /dev/null
-+++ b/drivers/input/touchscreen/ep93xx_ts.c
-@@ -0,0 +1,1022 @@
-+/*
-+ * linux/drivers/input/touchscreen/ep93xx_ts.c
-+ *
-+ * Copyright (C) 2003-2004 Cirrus Corp.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/delay.h>
-+#include <linux/wait.h>
-+#include <linux/fs.h>
-+#include <linux/sched.h>
-+#include <linux/poll.h>
-+#include <linux/miscdevice.h>
-+#include <linux/init.h>
-+#include <linux/compiler.h>
-+#include <linux/timer.h>
-+#include <linux/interrupt.h>
-+#include <linux/syscalls.h>
-+#include <linux/input.h>
-+#include <linux/semaphore.h>
-+#include <asm/irq.h>
-+#include <mach/hardware.h>
-+#include <asm/io.h>
-+#include "../../../arch/arm/mach-ep93xx/soc.h"
-+
-+/* This stuff should be in ep93xx-regs.h */
-+#define EP93XX_TOUCHSCREEN_REG(x) (EP93XX_TOUCHSCREEN_BASE + (x))
-+/* R/W touchscreen controller setup control register. */
-+#define EP93XX_TOUCHSCREEN_SETUP EP93XX_TOUCHSCREEN_REG(0x00)
-+/* R/W touchscreen controller max/min register. */
-+#define EP93XX_TOUCHSCREEN_XYMAXMIN EP93XX_TOUCHSCREEN_REG(0x04)
-+/* R touchscreen controller result register. */
-+#define EP93XX_TOUCHSCREEN_XYRESULT EP93XX_TOUCHSCREEN_REG(0x08)
-+/* LOCKED R/W touchscreen Switch Matrix control register. */
-+#define EP93XX_TOUCHSCREEN_DISCHARGE EP93XX_TOUCHSCREEN_REG(0x0C)
-+#define EP93XX_TOUCHSCREEN_XSAMPLE EP93XX_TOUCHSCREEN_REG(0x10)
-+#define EP93XX_TOUCHSCREEN_YSAMPLE EP93XX_TOUCHSCREEN_REG(0x14)
-+#define EP93XX_TOUCHSCREEN_DIRECT EP93XX_TOUCHSCREEN_REG(0x18)
-+#define EP93XX_TOUCHSCREEN_DETECT EP93XX_TOUCHSCREEN_REG(0x1C)
-+/* NA R/W touchscreen software lock register. */
-+#define EP93XX_TOUCHSCREEN_SWLOCK EP93XX_TOUCHSCREEN_REG(0x20)
-+/* R/W touchscreen setup control register #2. */
-+#define EP93XX_TOUCHSCREEN_SETUP2 EP93XX_TOUCHSCREEN_REG(0x24)
-+
-+/* These are duplicated in mach-ep93xx/core.c */
-+#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
-+#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
-+#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
-+#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
-+#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
-+
-+/*
-+ * Register bit definitions
-+ */
-+#define TSSETUP_SDLY_MASK 0x000003FF
-+#define TSSETUP_SDLY_SHIFT 0
-+#define TSSETUP_NSMP_4 0x00000000
-+#define TSSETUP_NSMP_8 0x00000400
-+#define TSSETUP_NSMP_16 0x00000800
-+#define TSSETUP_NSMP_32 0x00000C00
-+#define TSSETUP_NSMP_MASK 0x00000C00
-+#define TSSETUP_DEV_4 0x00000000
-+#define TSSETUP_DEV_8 0x00001000
-+#define TSSETUP_DEV_12 0x00002000
-+#define TSSETUP_DEV_16 0x00003000
-+#define TSSETUP_DEV_24 0x00004000
-+#define TSSETUP_DEV_32 0x00005000
-+#define TSSETUP_DEV_64 0x00006000
-+#define TSSETUP_DEV_128 0x00007000
-+#define TSSETUP_ENABLE 0x00008000
-+#define TSSETUP_DLY_MASK 0x03FF0000
-+#define TSSETUP_DLY_SHIFT 16
-+#define TSSETUP_TDTCT 0x80000000
-+
-+#define TSMAXMIN_XMIN_MASK 0x000000FF
-+#define TSMAXMIN_XMIN_SHIFT 0
-+#define TSMAXMIN_YMIN_MASK 0x0000FF00
-+#define TSMAXMIN_YMIN_SHIFT 8
-+#define TSMAXMIN_XMAX_MASK 0x00FF0000
-+#define TSMAXMIN_XMAX_SHIFT 16
-+#define TSMAXMIN_YMAX_MASK 0xFF000000
-+#define TSMAXMIN_YMAX_SHIFT 24
-+
-+#define TSXYRESULT_X_MASK 0x00000FFF
-+#define TSXYRESULT_X_SHIFT 0
-+#define TSXYRESULT_AD_MASK 0x0000FFFF
-+#define TSXYRESULT_AD_SHIFT 0
-+#define TSXYRESULT_Y_MASK 0x0FFF0000
-+#define TSXYRESULT_Y_SHIFT 16
-+#define TSXYRESULT_SDR 0x80000000
-+
-+#define TSX_SAMPLE_MASK 0x00003FFF
-+#define TSX_SAMPLE_SHIFT 0x00
-+#define TSY_SAMPLE_MASK 0x3FFF0000
-+#define TSY_SAMPLE_SHIFT 0x10
-+
-+#define TSSETUP2_TINT 0x00000001
-+#define TSSETUP2_NICOR 0x00000002
-+#define TSSETUP2_PINT 0x00000004
-+#define TSSETUP2_PENSTS 0x00000008
-+#define TSSETUP2_PINTEN 0x00000010
-+#define TSSETUP2_DEVINT 0x00000020
-+#define TSSETUP2_DINTEN 0x00000040
-+#define TSSETUP2_DTMEN 0x00000080
-+#define TSSETUP2_DISDEV 0x00000100
-+#define TSSETUP2_NSIGND 0x00000200
-+#define TSSETUP2_S28EN 0x00000400
-+#define TSSETUP2_RINTEN 0x00000800
-+
-+#define TSXYRESULT_SDR 0x80000000
-+
-+/*
-+ * These are used as trigger levels to know when we have pen up/down.
-+ * The rules:
-+ * 1. TS_HEAVY_INV_PRESSURE < TS_LIGHT_INV_PRESSURE because these
-+ * are Inverse pressure.
-+ * 2. Any touch lighter than TS_LIGHT_INV_PRESSURE is a pen up.
-+ * 3. Any touch heavier than TS_HEAVY_INV_PRESSURE is a pen down.
-+ */
-+#define TS_HEAVY_INV_PRESSURE 0xFE0 /* C00 */
-+#define TS_LIGHT_INV_PRESSURE 0xFFF /* e00 */
-+
-+/*
-+ * If the x, y, or inverse pressure changes more than these values
-+ * between two succeeding points, the point is not reported.
-+ */
-+#define TS_MAX_VALID_XY_CHANGE 0x300
-+#define TS_MAX_VALID_PRESSURE_CHANGE 0x100
-+
-+/*
-+ * This is the minimum Z1 Value that is valid.
-+ */
-+#define MIN_Z1_VALUE 0x50
-+
-+/*
-+ * Settling delay for taking each ADC measurement. Increase this
-+ * if ts is jittery.
-+ */
-+#define EP93XX_TS_ADC_DELAY_USEC 2000
-+
-+/*
-+ * Delay between TS points.
-+ */
-+#define EP93XX_TS_PER_POINT_DELAY_USEC 10000
-+
-+/*
-+ * A few more macros...
-+ */
-+#define TSSETUP_DEFAULT (TSSETUP_NSMP_32 | TSSETUP_DEV_64 | \
-+ ((128<<TSSETUP_SDLY_SHIFT) & TSSETUP_SDLY_MASK) | \
-+ ((128<<TSSETUP_DLY_SHIFT) & TSSETUP_DLY_MASK))
-+
-+#define TSSETUP2_DEFAULT (TSSETUP2_NSIGND)
-+
-+/*
-+ * For now, we use one of the minor numbers from the local/experimental
-+ * range.
-+ */
-+#define EP93XX_TS_MINOR 240
-+
-+/*
-+ * Static Declarations
-+ */
-+static unsigned int guiLastX, guiLastY;
-+static unsigned int guiLastInvPressure;
-+
-+struct TouchScreenSample
-+{
-+ int currentX;
-+ int currentY;
-+ int currentButton;
-+ int currentPressure;
-+ struct timeval currentTime;
-+};
-+
-+/*
-+ * This must match the structure in tslib.
-+ */
-+struct ts_sample {
-+ int x;
-+ int y;
-+ unsigned int pressure;
-+ struct timeval tv;
-+};
-+
-+static struct TouchScreenSample gSample;
-+static int bFreshTouchData;
-+static int bCurrentPenDown;
-+
-+static DECLARE_WAIT_QUEUE_HEAD(queue);
-+static DEFINE_SEMAPHORE(open_sem);
-+static DEFINE_SPINLOCK(event_buffer_lock);
-+static struct fasync_struct *ep93xx_fasync;
-+
-+/*
-+ * Typedef Declarations
-+ */
-+typedef enum {
-+ TS_MODE_UN_INITIALIZED,
-+ TS_MODE_HARDWARE_SCAN,
-+ TS_MODE_SOFT_SCAN
-+} ts_mode_t;
-+
-+static ts_mode_t gScanningMode;
-+
-+typedef enum{
-+ TS_STATE_STOPPED = 0,
-+ TS_STATE_Z1,
-+ TS_STATE_Z2,
-+ TS_STATE_Y,
-+ TS_STATE_X,
-+ TS_STATE_DONE
-+} ts_states_t;
-+
-+typedef struct
-+{
-+ unsigned int uiX;
-+ unsigned int uiY;
-+ unsigned int uiZ1;
-+ unsigned int uiZ2;
-+ ts_states_t state;
-+} ts_struct_t;
-+
-+static ts_struct_t sTouch;
-+
-+/*
-+ * From the spec, here's how to set up the touch screen's switch registers.
-+ */
-+typedef struct
-+{
-+ unsigned int uiDetect;
-+ unsigned int uiDischarge;
-+ unsigned int uiXSample;
-+ unsigned int uiYSample;
-+ unsigned int uiSwitchZ1;
-+ unsigned int uiSwitchZ2;
-+}SwitchStructType;
-+
-+/*
-+ * Here's the switch settings for a 4-wire touchscreen. See the spec
-+ * for how to handle a 4, 7, or 8-wire.
-+ */
-+const static SwitchStructType sSwitchSettings =
-+/* s28en=0 */
-+/* TSDetect TSDischarge TSXSample TSYSample SwitchZ1 SwitchZ2 */
-+ {0x00403604, 0x0007fe04, 0x00081604, 0x00104601, 0x00101601, 0x00101608};
-+
-+/*
-+ * Function declarations
-+ */
-+static void ep93xx_ts_set_direct(unsigned int uiADCSwitch);
-+static irqreturn_t ep93xx_ts_isr(int irq, void *dev_id);
-+static irqreturn_t ep93xx_timer2_isr(int irq, void *dev_id);
-+static void ee93xx_ts_evt_add(int button, int dX, int dY, int Pressure);
-+static ssize_t ep93xx_ts_read(struct file *filp, char *buf,
-+ size_t count, loff_t *l);
-+static unsigned int ep93xx_ts_poll(struct file *filp, poll_table *wait);
-+static int ep93xx_ts_open(struct inode *inode, struct file *filp);
-+static int ep93xx_ts_fasync(int fd, struct file *filp, int on);
-+static int ep93xx_ts_release(struct inode *inode, struct file *filp);
-+static ssize_t ep93xx_ts_write(struct file *file, const char *buffer,
-+ size_t count, loff_t *ppos);
-+static void ep93xx_ts_setup(void);
-+static void ep93xx_ts_shutdown(void);
-+int __init ep93xx_ts_init(void);
-+void __exit ep93xx_ts_exit(void);
-+static unsigned int CalculateInvPressure(void);
-+static unsigned int ADCGetData(unsigned int uiSamples, unsigned int uiMaxDiff);
-+static void TS_Soft_Scan_Mode(void);
-+static void TS_Hardware_Scan_Mode(void);
-+static void ProcessPointData(void);
-+static void Set_Timer2_uSec(unsigned int Delay_mSec);
-+static void Stop_Timer2(void);
-+
-+/*
-+ * ep93xx_ts_isr
-+ */
-+static irqreturn_t ep93xx_ts_isr(int irq, void *dev_id)
-+{
-+ /*
-+ * Note that we don't clear the interrupt here. The interrupt
-+ * gets cleared in TS_Soft_Scan_Mode when the TS ENABLE
-+ * bit is cleared.
-+ */
-+
-+ /*
-+ * Set the ts to manual polling mode and schedule a callback.
-+ * That way we can return from the isr in a reasonable amount of
-+ * time and process the touch in the callback after a brief delay.
-+ */
-+ TS_Soft_Scan_Mode();
-+
-+ return(IRQ_HANDLED);
-+}
-+
-+/*
-+ * Save the current ts 'event' in an atomic fashion.
-+ */
-+static void ee93xx_ts_evt_add(int buttons, int iX, int iY, int iPressure)
-+{
-+ /*
-+ * Note the event, but use spinlocks to keep it from getting
-+ * halfway read if we get interrupted.
-+ */
-+
-+ spin_lock(&event_buffer_lock);
-+
-+ gSample.currentX = iX;
-+ gSample.currentY = iY;
-+ gSample.currentButton = buttons;
-+ gSample.currentPressure = iPressure;
-+ bFreshTouchData = 1;
-+ do_gettimeofday(&gSample.currentTime);
-+
-+ spin_unlock(&event_buffer_lock);
-+
-+ kill_fasync(&ep93xx_fasync, SIGIO, POLL_IN);
-+ wake_up_interruptible(&queue);
-+}
-+
-+
-+static ssize_t ep93xx_ts_read(struct file *filp, char *buf, size_t count, loff_t *l)
-+{
-+ unsigned short data[3];
-+ struct ts_sample ts_data;
-+ int iReturn = -EFAULT;
-+
-+ if (!bFreshTouchData)
-+ {
-+ iReturn = 0;
-+ }
-+ else if (count == sizeof(data))
-+ {
-+ spin_lock_irq(&event_buffer_lock);
-+ bFreshTouchData = 0;
-+ data[0] = gSample.currentX;
-+ data[1] = gSample.currentY;
-+ data[2] = gSample.currentButton;
-+
-+ spin_unlock_irq(&event_buffer_lock);
-+
-+ if (copy_to_user(buf, data, sizeof data))
-+ return -EFAULT;
-+
-+ count -= sizeof(data);
-+
-+ /* return the # of bytes that got read */
-+ iReturn = sizeof(data) ;
-+ }
-+ else if (count == sizeof(struct ts_sample) )
-+ {
-+ spin_lock_irq(&event_buffer_lock);
-+ bFreshTouchData = 0;
-+ ts_data.x = gSample.currentX;
-+ ts_data.y = gSample.currentY;
-+ ts_data.pressure = gSample.currentPressure;
-+ ts_data.tv = gSample.currentTime;
-+ spin_unlock_irq(&event_buffer_lock);
-+
-+ if (copy_to_user(buf, &ts_data, sizeof(struct ts_sample)))
-+ {
-+ iReturn = -EFAULT;
-+ }
-+ else
-+ {
-+ count -= sizeof(ts_data);
-+ iReturn = sizeof(ts_data);
-+ }
-+ }
-+
-+ return iReturn;
-+}
-+
-+static unsigned int ep93xx_ts_poll(struct file *filp, poll_table *wait)
-+{
-+ poll_wait(filp, &queue, wait);
-+
-+ if (bFreshTouchData)
-+ {
-+ return POLLIN | POLLRDNORM;
-+ }
-+
-+ return 0;
-+}
-+
-+static int ep93xx_ts_open(struct inode *inode, struct file *filp)
-+{
-+ if (down_trylock(&open_sem))
-+ {
-+ return -EBUSY;
-+ }
-+
-+ ep93xx_ts_setup();
-+
-+ return 0;
-+}
-+
-+/*
-+ * Asynchronous I/O support.
-+ */
-+static int ep93xx_ts_fasync(int fd, struct file *filp, int on)
-+{
-+ int retval;
-+
-+ retval = fasync_helper(fd, filp, on, &ep93xx_fasync);
-+ if (retval < 0)
-+ {
-+ return retval;
-+ }
-+
-+ return 0;
-+}
-+
-+static int ep93xx_ts_release(struct inode *inode, struct file *filp)
-+{
-+ Stop_Timer2();
-+
-+ /*
-+ * Call our async I/O support to request that this file
-+ * cease to be used for async I/O.
-+ */
-+ ep93xx_ts_fasync(-1, filp, 0);
-+
-+ ep93xx_ts_shutdown();
-+
-+ up(&open_sem);
-+
-+ return 0;
-+}
-+
-+static ssize_t ep93xx_ts_write(struct file *file, const char *buffer, size_t count,
-+ loff_t *ppos)
-+{
-+ return -EINVAL;
-+}
-+
-+
-+static int ep93xx_ts_ioctl(struct inode *inode, struct file *file, uint command, ulong u)
-+{
-+ static const int version = EV_VERSION;
-+ static const u_int32_t bit =(1 << EV_ABS);
-+ static const u_int32_t absbit = (1 << ABS_X) | (1 << ABS_Y) | (1 << ABS_PRESSURE);
-+ int iReturn ;
-+ int i = 0;
-+
-+ switch(command)
-+ {
-+ case EVIOCGVERSION:
-+ i = copy_to_user((void __user *)u, (void *)version, sizeof(version));
-+ iReturn = i ? -EFAULT : 0;
-+ break;
-+
-+ case EVIOCGBIT(0,sizeof(u_int32_t) * 8) :
-+ i = copy_to_user((void __user *)u, (void *)bit, sizeof(bit));
-+ iReturn = i ? -EFAULT : 0;
-+ break;
-+
-+ case EVIOCGBIT(EV_ABS, sizeof(absbit) * 8):
-+ i = copy_to_user((void __user *)u, (void *)absbit, sizeof(absbit));
-+ iReturn = i ? -EFAULT : 0;
-+ break;
-+ default:
-+ iReturn = -1;
-+ break;
-+ }
-+
-+ return iReturn;
-+}
-+
-+static struct file_operations ep93xx_ts_fops = {
-+ owner: THIS_MODULE,
-+ read: ep93xx_ts_read,
-+ write: ep93xx_ts_write,
-+ poll: ep93xx_ts_poll,
-+ open: ep93xx_ts_open,
-+ unlocked_ioctl: ep93xx_ts_ioctl,
-+ release: ep93xx_ts_release,
-+ fasync: ep93xx_ts_fasync,
-+};
-+
-+static struct miscdevice ep93xx_ts_miscdev =
-+{
-+ EP93XX_TS_MINOR,
-+ "ep93xx_ts",
-+ &ep93xx_ts_fops
-+};
-+
-+void ep93xx_ts_setup(void)
-+{
-+ unsigned int uiKTDIV, uiTSXYMaxMin;
-+
-+ /*
-+ * Set the TSEN bit in KTDIV so that we are enabling the clock
-+ * for the touchscreen.
-+ */
-+ uiKTDIV = __raw_readl(EP93XX_SYSCON_KEYTCHCLKDIV);
-+ uiKTDIV |= EP93XX_SYSCON_KEYTCHCLKDIV_TSEN;
-+ ep93xx_syscon_swlocked_write(uiKTDIV, EP93XX_SYSCON_KEYTCHCLKDIV);
-+
-+ /*
-+ * Program the EP93XX_TOUCHSCREEN_SETUP and TSSetup2 registers.
-+ */
-+ __raw_writel(TSSETUP_DEFAULT, EP93XX_TOUCHSCREEN_SETUP);
-+ __raw_writel(TSSETUP2_DEFAULT, EP93XX_TOUCHSCREEN_SETUP2);
-+
-+ /*
-+ * Set the the touch settings.
-+ */
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(sSwitchSettings.uiDischarge, EP93XX_TOUCHSCREEN_DIRECT);
-+
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(sSwitchSettings.uiDischarge, EP93XX_TOUCHSCREEN_DISCHARGE);
-+
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(sSwitchSettings.uiSwitchZ1, EP93XX_TOUCHSCREEN_XSAMPLE);
-+
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(sSwitchSettings.uiSwitchZ2, EP93XX_TOUCHSCREEN_YSAMPLE);
-+
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(sSwitchSettings.uiDetect, EP93XX_TOUCHSCREEN_DETECT);
-+
-+ /*
-+ * X,YMin set to 0x40 = have to drag that many pixels for a new irq.
-+ * X,YMax set to 0x40 = 1024 pixels is the maximum movement within the
-+ * time scan limit.
-+ */
-+ uiTSXYMaxMin = (50 << TSMAXMIN_XMIN_SHIFT) & TSMAXMIN_XMIN_MASK;
-+ uiTSXYMaxMin |= (50 << TSMAXMIN_YMIN_SHIFT) & TSMAXMIN_YMIN_MASK;
-+ uiTSXYMaxMin |= (0xff << TSMAXMIN_XMAX_SHIFT) & TSMAXMIN_XMAX_MASK;
-+ uiTSXYMaxMin |= (0xff << TSMAXMIN_YMAX_SHIFT) & TSMAXMIN_YMAX_MASK;
-+ __raw_writel(uiTSXYMaxMin, EP93XX_TOUCHSCREEN_XYMAXMIN);
-+
-+ bCurrentPenDown = 0;
-+ bFreshTouchData = 0;
-+ guiLastX = 0;
-+ guiLastY = 0;
-+ guiLastInvPressure = 0xffffff;
-+
-+ /*
-+ * Enable the touch screen scanning engine.
-+ */
-+ TS_Hardware_Scan_Mode();
-+}
-+
-+/*
-+ * ep93xx_ts_shutdown
-+ *
-+ */
-+static void
-+ep93xx_ts_shutdown(void)
-+{
-+ unsigned int uiKTDIV;
-+
-+ sTouch.state = TS_STATE_STOPPED;
-+ Stop_Timer2();
-+
-+ /*
-+ * Disable the scanning engine.
-+ */
-+ __raw_writel(0, EP93XX_TOUCHSCREEN_SETUP);
-+ __raw_writel(0, EP93XX_TOUCHSCREEN_SETUP2);
-+
-+ /*
-+ * Clear the TSEN bit in KTDIV so that we are disabling the clock
-+ * for the touchscreen.
-+ */
-+ uiKTDIV = __raw_readl(EP93XX_SYSCON_KEYTCHCLKDIV);
-+ uiKTDIV &= ~EP93XX_SYSCON_KEYTCHCLKDIV_TSEN;
-+ ep93xx_syscon_swlocked_write(uiKTDIV, EP93XX_SYSCON_KEYTCHCLKDIV);
-+
-+} /* ep93xx_ts_shutdown */
-+
-+static irqreturn_t ep93xx_timer2_isr(int irq, void *dev_id)
-+{
-+ switch(sTouch.state)
-+ {
-+ case TS_STATE_STOPPED:
-+ TS_Hardware_Scan_Mode();
-+ break;
-+
-+ /*
-+ * Get the Z1 value for pressure measurement and set up
-+ * the switch register for getting the Z2 measurement.
-+ */
-+ case TS_STATE_Z1:
-+ Set_Timer2_uSec(EP93XX_TS_ADC_DELAY_USEC);
-+ sTouch.uiZ1 = ADCGetData(2, 200);
-+ ep93xx_ts_set_direct(sSwitchSettings.uiSwitchZ2);
-+ sTouch.state = TS_STATE_Z2;
-+ break;
-+
-+ /*
-+ * Get the Z2 value for pressure measurement and set up
-+ * the switch register for getting the Y measurement.
-+ */
-+ case TS_STATE_Z2:
-+ sTouch.uiZ2 = ADCGetData(2, 200);
-+ ep93xx_ts_set_direct(sSwitchSettings.uiYSample);
-+ sTouch.state = TS_STATE_Y;
-+ break;
-+
-+ /*
-+ * Get the Y value and set up the switch register for
-+ * getting the X measurement.
-+ */
-+ case TS_STATE_Y:
-+ sTouch.uiY = ADCGetData(4, 20);
-+ ep93xx_ts_set_direct(sSwitchSettings.uiXSample);
-+ sTouch.state = TS_STATE_X;
-+ break;
-+
-+ /*
-+ * Read the X value. This is the last of the 4 adc values
-+ * we need so we continue on to process the data.
-+ */
-+ case TS_STATE_X:
-+ Stop_Timer2();
-+
-+ sTouch.uiX = ADCGetData(4, 20);
-+
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(sSwitchSettings.uiDischarge, EP93XX_TOUCHSCREEN_DIRECT);
-+
-+ sTouch.state = TS_STATE_DONE;
-+
-+ /*
-+ * Process this set of ADC readings.
-+ */
-+ ProcessPointData();
-+
-+ break;
-+
-+ /*
-+ * Shouldn't get here. But if we do, we can recover...
-+ */
-+ case TS_STATE_DONE:
-+ TS_Hardware_Scan_Mode();
-+ break;
-+ }
-+
-+ /*
-+ * Clear the timer2 interrupt.
-+ */
-+ __raw_writel(1, EP93XX_TIMER2_CLEAR);
-+ return(IRQ_HANDLED);
-+}
-+
-+/*---------------------------------------------------------------------
-+ * ProcessPointData
-+ *
-+ * This routine processes the ADC data into usable point data and then
-+ * puts the driver into hw or sw scanning mode before returning.
-+ *
-+ * We calculate inverse pressure (lower number = more pressure) then
-+ * do a hystheresis with the two pressure values 'light' and 'heavy'.
-+ *
-+ * If we are above the light, we have pen up.
-+ * If we are below the heavy we have pen down.
-+ * As long as the pressure stays below the light, pen stays down.
-+ * When we get above the light again, pen goes back up.
-+ *
-+ */
-+static void ProcessPointData(void)
-+{
-+ int bValidPoint = 0;
-+ unsigned int uiXDiff, uiYDiff, uiInvPressureDiff;
-+ unsigned int uiInvPressure;
-+
-+ /*
-+ * Calculate the current pressure.
-+ */
-+ uiInvPressure = CalculateInvPressure();
-+
-+ /*
-+ * If pen pressure is so light that it is greater than the 'max' setting
-+ * then we consider this to be a pen up.
-+ */
-+ if (uiInvPressure >= TS_LIGHT_INV_PRESSURE)
-+ {
-+ bCurrentPenDown = 0;
-+ ee93xx_ts_evt_add(0, guiLastX, guiLastY, 0);
-+ TS_Hardware_Scan_Mode();
-+ return;
-+ }
-+
-+ /*
-+ * Hysteresis:
-+ * If the pen pressure is hard enough to be less than the 'min' OR
-+ * the pen is already down and is still less than the 'max'...
-+ */
-+ if ((uiInvPressure < TS_HEAVY_INV_PRESSURE) ||
-+ (bCurrentPenDown && (uiInvPressure < TS_LIGHT_INV_PRESSURE)))
-+ {
-+ if (bCurrentPenDown)
-+ {
-+ /*
-+ * If pen was previously down, check the difference between
-+ * the last sample and this one... if the difference between
-+ * samples is too great, ignore the sample.
-+ */
-+ uiXDiff = abs(guiLastX - sTouch.uiX);
-+ uiYDiff = abs(guiLastY - sTouch.uiY);
-+ uiInvPressureDiff = abs(guiLastInvPressure - uiInvPressure);
-+
-+ if (uiXDiff < TS_MAX_VALID_XY_CHANGE
-+ && uiYDiff < TS_MAX_VALID_XY_CHANGE
-+ && uiInvPressureDiff < TS_MAX_VALID_PRESSURE_CHANGE)
-+ {
-+ bValidPoint = 1;
-+ }
-+ }
-+ else
-+ {
-+ bValidPoint = 1;
-+ }
-+
-+ /*
-+ * If either the pen was put down or dragged make a note of it.
-+ */
-+ if (bValidPoint)
-+ {
-+ guiLastX = sTouch.uiX;
-+ guiLastY = sTouch.uiY;
-+ guiLastInvPressure = uiInvPressure;
-+ bCurrentPenDown = 1;
-+ ee93xx_ts_evt_add(1, sTouch.uiX, sTouch.uiY,
-+ 0x7000000 / uiInvPressure);
-+ }
-+
-+ TS_Soft_Scan_Mode();
-+ return;
-+ }
-+
-+ TS_Hardware_Scan_Mode();
-+}
-+
-+static void ep93xx_ts_set_direct(unsigned int uiADCSwitch)
-+{
-+ unsigned int uiResult;
-+
-+ /*
-+ * Set the switch settings in the direct register.
-+ */
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(uiADCSwitch, EP93XX_TOUCHSCREEN_DIRECT);
-+
-+ /*
-+ * Read and throw away the first sample.
-+ */
-+ do {
-+ uiResult = __raw_readl(EP93XX_TOUCHSCREEN_XYRESULT);
-+ } while (!(uiResult & TSXYRESULT_SDR));
-+
-+}
-+
-+static unsigned int ADCGetData(unsigned int uiSamples, unsigned int uiMaxDiff)
-+{
-+ unsigned int uiResult, uiValue, uiCount, uiLowest, uiHighest, uiSum, uiAve;
-+
-+ do
-+ {
-+ /*
-+ * Initialize our values.
-+ */
-+ uiLowest = 0xfffffff;
-+ uiHighest = 0;
-+ uiSum = 0;
-+
-+ for (uiCount = 0; uiCount < uiSamples; uiCount++)
-+ {
-+ /*
-+ * Read the touch screen four more times and average.
-+ */
-+ do {
-+ uiResult = __raw_readl(EP93XX_TOUCHSCREEN_XYRESULT);
-+ } while (!(uiResult & TSXYRESULT_SDR));
-+
-+ uiValue = (uiResult & TSXYRESULT_AD_MASK) >> TSXYRESULT_AD_SHIFT;
-+ uiValue = ((uiValue >> 4) + ((1 + TSXYRESULT_X_MASK)>>1)) & TSXYRESULT_X_MASK;
-+
-+ /*
-+ * Add up the values.
-+ */
-+ uiSum += uiValue;
-+
-+ /*
-+ * Get the lowest and highest values.
-+ */
-+ if (uiValue < uiLowest)
-+ {
-+ uiLowest = uiValue;
-+ }
-+ if (uiValue > uiHighest)
-+ {
-+ uiHighest = uiValue;
-+ }
-+ }
-+ } while ((uiHighest - uiLowest) > uiMaxDiff);
-+
-+ /*
-+ * Calculate the Average value.
-+ */
-+ uiAve = uiSum / uiSamples;
-+
-+ return uiAve;
-+}
-+
-+/*
-+ * CalculateInvPressure
-+ *
-+ * Is the Touch Valid. Touch is not valid if the X or Y value is not
-+ * in range and the pressure is not enough.
-+ *
-+ * Touch resistance can be measured by the following formula:
-+ *
-+ * Rx * X * Z2
-+ * Rtouch = --------- * (-- - 1)
-+ * 4096 Z1
-+ *
-+ * This is simplified in the ration of Rtouch to Rx. The lower the value, the
-+ * higher the pressure.
-+ *
-+ * Z2
-+ * InvPressure = X * (-- - 1)
-+ * Z1
-+ */
-+static unsigned int CalculateInvPressure(void)
-+{
-+ unsigned int uiInvPressure;
-+
-+ /*
-+ * Check to see if the point is valid.
-+ */
-+ if (sTouch.uiZ1 < MIN_Z1_VALUE)
-+ {
-+ uiInvPressure = 0x10000;
-+ }
-+
-+ /*
-+ * Can omit the pressure calculation if you need to get rid of the division.
-+ */
-+ else
-+ {
-+ uiInvPressure = ((sTouch.uiX * sTouch.uiZ2) / sTouch.uiZ1) - sTouch.uiX;
-+ }
-+
-+ return uiInvPressure;
-+}
-+
-+/*
-+ * TS_Hardware_Scan_Mode
-+ *
-+ * Enables the ep93xx ts scanning engine so that when the pen goes down
-+ * we will get an interrupt.
-+ */
-+static void TS_Hardware_Scan_Mode(void)
-+{
-+ unsigned int uiDevCfg;
-+
-+ /*
-+ * Disable the soft scanning engine.
-+ */
-+ sTouch.state = TS_STATE_STOPPED;
-+ Stop_Timer2();
-+
-+ /*
-+ * Clear the TIN (Touchscreen INactive) bit so we can go to
-+ * automatic scanning mode.
-+ */
-+ uiDevCfg = __raw_readl(EP93XX_SYSCON_DEVCFG);
-+ ep93xx_syscon_swlocked_write(uiDevCfg & ~EP93XX_SYSCON_DEVCFG_TIN,
-+ EP93XX_SYSCON_DEVCFG);
-+
-+ /*
-+ * Enable the touch screen scanning state machine by setting
-+ * the ENABLE bit.
-+ */
-+ __raw_writel(TSSETUP_DEFAULT | TSSETUP_ENABLE, EP93XX_TOUCHSCREEN_SETUP);
-+
-+ /*
-+ * Set the flag to show that we are in interrupt mode.
-+ */
-+ gScanningMode = TS_MODE_HARDWARE_SCAN;
-+
-+ /*
-+ * Initialize EP93XX_TOUCHSCREEN_SETUP2 register.
-+ */
-+ __raw_writel(TSSETUP2_DEFAULT, EP93XX_TOUCHSCREEN_SETUP2);
-+
-+}
-+
-+/*
-+ * TS_Soft_Scan_Mode
-+ *
-+ * Sets the touch screen to manual polling mode.
-+ */
-+static void TS_Soft_Scan_Mode(void)
-+{
-+ unsigned int uiDevCfg;
-+
-+ if (gScanningMode != TS_MODE_SOFT_SCAN)
-+ {
-+ /*
-+ * Disable the touch screen scanning state machine by clearing
-+ * the ENABLE bit.
-+ */
-+ __raw_writel(TSSETUP_DEFAULT, EP93XX_TOUCHSCREEN_SETUP);
-+
-+ /*
-+ * Set the TIN bit so we can do manual touchscreen polling.
-+ */
-+ uiDevCfg = __raw_readl(EP93XX_SYSCON_DEVCFG);
-+ ep93xx_syscon_swlocked_write(uiDevCfg | EP93XX_SYSCON_DEVCFG_TIN,
-+ EP93XX_SYSCON_DEVCFG);
-+ }
-+
-+ /*
-+ * Set the switch register up for the first ADC reading
-+ */
-+ ep93xx_ts_set_direct(sSwitchSettings.uiSwitchZ1);
-+
-+ /*
-+ * Initialize our software state machine to know which ADC
-+ * reading to take
-+ */
-+ sTouch.state = TS_STATE_Z1;
-+
-+ /*
-+ * Set the timer so after a mSec or two settling delay it will
-+ * take the first ADC reading.
-+ */
-+ Set_Timer2_uSec(EP93XX_TS_PER_POINT_DELAY_USEC);
-+
-+ /*
-+ * Note that we are in sw scanning mode not hw scanning mode.
-+ */
-+ gScanningMode = TS_MODE_SOFT_SCAN;
-+
-+}
-+
-+static void Set_Timer2_uSec(unsigned int uiDelay_uSec)
-+{
-+ unsigned int uiClockTicks;
-+
-+ /*
-+ * Stop timer 2
-+ */
-+ __raw_writel(0, EP93XX_TIMER2_CONTROL);
-+
-+ uiClockTicks = ((uiDelay_uSec * 508) + 999) / 1000;
-+ __raw_writel(uiClockTicks, EP93XX_TIMER2_LOAD);
-+ __raw_writel(uiClockTicks, EP93XX_TIMER2_VALUE);
-+
-+ /*
-+ * Set up Timer 2 for 508 kHz clock and periodic mode.
-+ */
-+ __raw_writel(0xC8, EP93XX_TIMER2_CONTROL);
-+
-+}
-+
-+static void Stop_Timer2(void)
-+{
-+ __raw_writel(0, EP93XX_TIMER2_CONTROL);
-+}
-+
-+/*
-+ * Initialization and exit routines
-+ */
-+int __init ep93xx_ts_init(void)
-+{
-+ int retval;
-+
-+ retval = request_irq(IRQ_EP93XX_TOUCH, ep93xx_ts_isr,
-+ IRQF_DISABLED, "ep93xx_ts", 0);
-+ if (retval)
-+ {
-+ printk(KERN_WARNING "ep93xx_ts: failed to get touchscreen IRQ\n");
-+ return retval;
-+ }
-+
-+ retval = request_irq(IRQ_EP93XX_TIMER2, ep93xx_timer2_isr,
-+ IRQF_DISABLED, "ep93xx_timer2", 0);
-+ if (retval)
-+ {
-+ printk(KERN_WARNING "ep93xx_ts: failed to get timer2 IRQ\n");
-+ free_irq(IRQ_EP93XX_TOUCH, 0);
-+ return retval;
-+ }
-+
-+ misc_register(&ep93xx_ts_miscdev);
-+
-+ sTouch.state = TS_STATE_STOPPED;
-+ gScanningMode = TS_MODE_UN_INITIALIZED;
-+
-+ printk(KERN_NOTICE "ep93xx touchscreen driver configured for 4-wire operation\n");
-+
-+ return 0;
-+}
-+
-+void __exit ep93xx_ts_exit(void)
-+{
-+ Stop_Timer2();
-+
-+ free_irq(IRQ_EP93XX_TOUCH, 0);
-+ free_irq(IRQ_EP93XX_TIMER2, 0);
-+
-+ misc_deregister(&ep93xx_ts_miscdev);
-+}
-+
-+module_init(ep93xx_ts_init);
-+module_exit(ep93xx_ts_exit);
-+
-+MODULE_DESCRIPTION("Cirrus EP93xx touchscreen driver");
-+MODULE_SUPPORTED_DEVICE("touchscreen/ep93xx");
-+MODULE_LICENSE("GPL");
---- a/arch/arm/mach-ep93xx/core.c
-+++ b/arch/arm/mach-ep93xx/core.c
-@@ -207,6 +207,7 @@ void ep93xx_syscon_swlocked_write(unsign
-
- spin_unlock_irqrestore(&syscon_swlock, flags);
- }
-+EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
-
- void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
- {
+++ /dev/null
-This enables the mmc-over-spi driver for the Sim.One board, based on Mika's
-patch, which used a GPIO for chip select in stead of the default SFRMOUT pin.
-I've modified it to use the usual SFRMOUT; if you've modified your Sim.One
-board to use a GPIO instead, uncomment and modify
-// #define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO15
-in the source file.
- -martinwguy, 14 May 2010
-
-From: Mika Westerberg <mika.westerberg@iki.fi>
-Date: Wed, 28 Apr 2010 08:42:46 +0300
-Subject: [PATCH] ep93xx: simone: added board specific SPI support for MMC/SD cards
-
-This includes setting up EGPIOs 0 and 9 for card detection and chip select
-respectively.
-
---- a/arch/arm/mach-ep93xx/simone.c
-+++ b/arch/arm/mach-ep93xx/simone.c
-@@ -20,10 +20,15 @@
- #include <linux/platform_device.h>
- #include <linux/i2c.h>
- #include <linux/i2c-gpio.h>
-+#include <linux/gpio.h>
-+#include <linux/mmc/host.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/mmc_spi.h>
-
- #include <mach/hardware.h>
- #include <linux/platform_data/video-ep93xx.h>
- #include <mach/gpio-ep93xx.h>
-+#include <linux/platform_data/spi-ep93xx.h>
-
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
-@@ -40,6 +45,135 @@ static struct ep93xxfb_mach_info __initd
- .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
- };
-
-+/*
-+ * GPIO lines used for MMC card detection.
-+ */
-+#define MMC_CARD_DETECT_GPIO EP93XX_GPIO_LINE_EGPIO0
-+
-+/*
-+ * If you have hacked your Sim.One to use a GPIO as SD card chip select
-+ * (SD pin 1), uncomment the following line.
-+ * The example, EGPIO15, is on TP17 near the CPU.
-+ */
-+// #define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO15
-+
-+/*
-+ * MMC SPI chip select GPIO handling. If you are using SFRMOUT (SFRM1) signal,
-+ * you can leave these empty and pass NULL as .controller_data.
-+ */
-+
-+#ifdef MMC_CHIP_SELECT_GPIO
-+static int simone_mmc_spi_setup(struct spi_device *spi)
-+{
-+ unsigned int gpio = MMC_CHIP_SELECT_GPIO;
-+ int err;
-+
-+ err = gpio_request(gpio, spi->modalias);
-+ if (err)
-+ return err;
-+
-+ err = gpio_direction_output(gpio, 1);
-+ if (err) {
-+ gpio_free(gpio);
-+ return err;
-+ }
-+
-+ return 0;
-+}
-+
-+static void simone_mmc_spi_cleanup(struct spi_device *spi)
-+{
-+ unsigned int gpio = MMC_CHIP_SELECT_GPIO;
-+
-+ gpio_set_value(gpio, 1);
-+ gpio_direction_input(gpio);
-+ gpio_free(gpio);
-+}
-+
-+static void simone_mmc_spi_cs_control(struct spi_device *spi, int value)
-+{
-+ gpio_set_value(MMC_CHIP_SELECT_GPIO, value);
-+}
-+
-+static struct ep93xx_spi_chip_ops simone_mmc_spi_ops = {
-+ .setup = simone_mmc_spi_setup,
-+ .cleanup = simone_mmc_spi_cleanup,
-+ .cs_control = simone_mmc_spi_cs_control,
-+};
-+#endif
-+
-+/*
-+ * MMC card detection GPIO setup.
-+ */
-+static int simone_mmc_spi_init(struct device *dev,
-+ irqreturn_t (*irq_handler)(int, void *), void *mmc)
-+{
-+ unsigned int gpio = MMC_CARD_DETECT_GPIO;
-+ int irq, err;
-+
-+ err = gpio_request(gpio, dev_name(dev));
-+ if (err)
-+ return err;
-+
-+ err = gpio_direction_input(gpio);
-+ if (err)
-+ goto fail;
-+
-+ irq = gpio_to_irq(gpio);
-+ if (irq < 0)
-+ goto fail;
-+
-+ err = request_irq(irq, irq_handler, IRQF_TRIGGER_FALLING,
-+ "MMC card detect", mmc);
-+ if (err)
-+ goto fail;
-+
-+ printk(KERN_INFO "%s: using irq %d for MMC card detection\n",
-+ dev_name(dev), irq);
-+
-+ return 0;
-+fail:
-+ gpio_free(gpio);
-+ return err;
-+}
-+
-+static void simone_mmc_spi_exit(struct device *dev, void *mmc)
-+{
-+ unsigned int gpio = MMC_CARD_DETECT_GPIO;
-+
-+ free_irq(gpio_to_irq(gpio), mmc);
-+ gpio_free(gpio);
-+}
-+
-+static struct mmc_spi_platform_data simone_mmc_spi_data = {
-+ .init = simone_mmc_spi_init,
-+ .exit = simone_mmc_spi_exit,
-+ .detect_delay = 500,
-+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
-+};
-+
-+static struct spi_board_info simone_spi_devices[] __initdata = {
-+ {
-+ .modalias = "mmc_spi",
-+#ifdef MMC_CHIP_SELECT_GPIO
-+ .controller_data = &simone_mmc_spi_ops,
-+#endif
-+ .platform_data = &simone_mmc_spi_data,
-+ /*
-+ * We use 10 MHz even though the maximum is 3.7 MHz. The driver
-+ * will limit it automatically to max. frequency.
-+ */
-+ .max_speed_hz = 10 * 1000 * 1000,
-+ .bus_num = 0,
-+ .chip_select = 0,
-+ .mode = SPI_MODE_3,
-+ },
-+};
-+
-+static struct ep93xx_spi_info simone_spi_info __initdata = {
-+ .num_chipselect = ARRAY_SIZE(simone_spi_devices),
-+};
-+
- static struct i2c_gpio_platform_data __initdata simone_i2c_gpio_data = {
- .sda_pin = EP93XX_GPIO_LINE_EEDAT,
- .sda_is_open_drain = 0,
-@@ -74,6 +208,8 @@ static void __init simone_init_machine(v
- ep93xx_register_fb(&simone_fb_info);
- ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
- ARRAY_SIZE(simone_i2c_board_info));
-+ ep93xx_register_spi(&simone_spi_info, simone_spi_devices,
-+ ARRAY_SIZE(simone_spi_devices));
- simone_register_audio();
- }
-
+++ /dev/null
-This patch puts the EP93xx chip revision and unique ID into /proc/cpuinfo.
-This is necessary to be able to set a unique MAC address for DHCP purposes
-by adding a line to /etc/network/interfaces:
-
-# Generate a unique locally-assigned MAC address from the CPU serial number
-pre-up ifconfig eth0 hw ether `sed -n 's/^Serial.* 000000/02/p' /proc/cpuinfo`
-
-It uses the chip revision reading code in the ep93xx-chip-revision patch.
-
-Really, this is wrong, since /proc/cpuinfo should report the revision and
-serial number of the ARM920T processor, while these are the rev and serial
-of the EP93xx SoC. In a future kernel (>2.6.34) there may be a new file
-/proc/socinfo for this information.
-
- -martinwguy 14 May 2010
-
---- a/arch/arm/kernel/setup.c
-+++ b/arch/arm/kernel/setup.c
-@@ -55,6 +55,12 @@
- #include <asm/memblock.h>
- #include <asm/virt.h>
-
-+#if defined(CONFIG_ARCH_EP93XX)
-+#include <asm/io.h>
-+#include <mach/platform.h>
-+#include <mach/ep93xx-regs.h>
-+#endif
-+
- #include "atags.h"
- #include "tcm.h"
-
-@@ -903,9 +909,16 @@ static int c_show(struct seq_file *m, vo
- }
-
- seq_printf(m, "Hardware\t: %s\n", machine_name);
-+#if defined(CONFIG_ARCH_EP93XX)
-+ seq_printf(m, "Revision\t: %04x\n",
-+ ep93xx_chip_revision());
-+ seq_printf(m, "Serial\t\t: %016x\n",
-+ *((unsigned int *)EP93XX_SECURITY_UNIQID));
-+#else
- seq_printf(m, "Revision\t: %04x\n", system_rev);
- seq_printf(m, "Serial\t\t: %08x%08x\n",
- system_serial_high, system_serial_low);
-+#endif
-
- return 0;
- }
---- a/arch/arm/mach-ep93xx/soc.h
-+++ b/arch/arm/mach-ep93xx/soc.h
-@@ -82,8 +82,6 @@
- #define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000)
- #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
-
--#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
--
- #define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000)
- #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
-
---- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
-+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
-@@ -38,4 +38,8 @@
- #define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000)
- #define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000)
-
-+#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
-+#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x))
-+#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440)
-+
- #endif
+++ /dev/null
----
- arch/arm/mach-ep93xx/include/mach/hardware.h | 1
- arch/arm/mach-ep93xx/include/mach/regs_touch.h | 95 ++
- drivers/input/touchscreen/Kconfig | 5
- drivers/input/touchscreen/Makefile | 1
- drivers/input/touchscreen/ep93xx_ts.c | 1117 +++++++++++++++++++++++++
- drivers/input/touchscreen/ep93xx_ts.h | 53 +
- 6 files changed, 1272 insertions(+)
-
---- a/drivers/input/touchscreen/Kconfig
-+++ b/drivers/input/touchscreen/Kconfig
-@@ -235,6 +235,15 @@ config TOUCHSCREEN_EGALAX
- To compile this driver as a module, choose M here: the
- module will be called egalax_ts.
-
-+config TOUCHSCREEN_EP93XX
-+ tristate "EP93xx Touchscreen"
-+ depends on ARM && INPUT && ARCH_EP93XX
-+ help
-+ Say Y here to enable support for EP93xx touch screen.
-+
-+ To compile this driver as a module, choose M here:
-+ the module will be called ep93xx_ts.
-+
- config TOUCHSCREEN_FUJITSU
- tristate "Fujitsu serial touchscreen"
- select SERIO
---- a/drivers/input/touchscreen/Makefile
-+++ b/drivers/input/touchscreen/Makefile
-@@ -29,6 +29,7 @@ obj-$(CONFIG_TOUCHSCREEN_GUNZE) += gunz
- obj-$(CONFIG_TOUCHSCREEN_EETI) += eeti_ts.o
- obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o
- obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o
-+obj-$(CONFIG_TOUCHSCREEN_EP93XX) += ep93xx_ts.o
- obj-$(CONFIG_TOUCHSCREEN_FUJITSU) += fujitsu_ts.o
- obj-$(CONFIG_TOUCHSCREEN_ILI210X) += ili210x.o
- obj-$(CONFIG_TOUCHSCREEN_INEXIO) += inexio.o
---- /dev/null
-+++ b/drivers/input/touchscreen/ep93xx_ts.c
-@@ -0,0 +1,1022 @@
-+/*
-+ * linux/drivers/input/touchscreen/ep93xx_ts.c
-+ *
-+ * Copyright (C) 2003-2004 Cirrus Corp.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/delay.h>
-+#include <linux/wait.h>
-+#include <linux/fs.h>
-+#include <linux/sched.h>
-+#include <linux/poll.h>
-+#include <linux/miscdevice.h>
-+#include <linux/init.h>
-+#include <linux/compiler.h>
-+#include <linux/timer.h>
-+#include <linux/interrupt.h>
-+#include <linux/syscalls.h>
-+#include <linux/input.h>
-+#include <linux/semaphore.h>
-+#include <asm/irq.h>
-+#include <mach/hardware.h>
-+#include <asm/io.h>
-+#include "../../../arch/arm/mach-ep93xx/soc.h"
-+
-+/* This stuff should be in ep93xx-regs.h */
-+#define EP93XX_TOUCHSCREEN_REG(x) (EP93XX_TOUCHSCREEN_BASE + (x))
-+/* R/W touchscreen controller setup control register. */
-+#define EP93XX_TOUCHSCREEN_SETUP EP93XX_TOUCHSCREEN_REG(0x00)
-+/* R/W touchscreen controller max/min register. */
-+#define EP93XX_TOUCHSCREEN_XYMAXMIN EP93XX_TOUCHSCREEN_REG(0x04)
-+/* R touchscreen controller result register. */
-+#define EP93XX_TOUCHSCREEN_XYRESULT EP93XX_TOUCHSCREEN_REG(0x08)
-+/* LOCKED R/W touchscreen Switch Matrix control register. */
-+#define EP93XX_TOUCHSCREEN_DISCHARGE EP93XX_TOUCHSCREEN_REG(0x0C)
-+#define EP93XX_TOUCHSCREEN_XSAMPLE EP93XX_TOUCHSCREEN_REG(0x10)
-+#define EP93XX_TOUCHSCREEN_YSAMPLE EP93XX_TOUCHSCREEN_REG(0x14)
-+#define EP93XX_TOUCHSCREEN_DIRECT EP93XX_TOUCHSCREEN_REG(0x18)
-+#define EP93XX_TOUCHSCREEN_DETECT EP93XX_TOUCHSCREEN_REG(0x1C)
-+/* NA R/W touchscreen software lock register. */
-+#define EP93XX_TOUCHSCREEN_SWLOCK EP93XX_TOUCHSCREEN_REG(0x20)
-+/* R/W touchscreen setup control register #2. */
-+#define EP93XX_TOUCHSCREEN_SETUP2 EP93XX_TOUCHSCREEN_REG(0x24)
-+
-+/* These are duplicated in mach-ep93xx/core.c */
-+#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
-+#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
-+#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
-+#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
-+#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
-+
-+/*
-+ * Register bit definitions
-+ */
-+#define TSSETUP_SDLY_MASK 0x000003FF
-+#define TSSETUP_SDLY_SHIFT 0
-+#define TSSETUP_NSMP_4 0x00000000
-+#define TSSETUP_NSMP_8 0x00000400
-+#define TSSETUP_NSMP_16 0x00000800
-+#define TSSETUP_NSMP_32 0x00000C00
-+#define TSSETUP_NSMP_MASK 0x00000C00
-+#define TSSETUP_DEV_4 0x00000000
-+#define TSSETUP_DEV_8 0x00001000
-+#define TSSETUP_DEV_12 0x00002000
-+#define TSSETUP_DEV_16 0x00003000
-+#define TSSETUP_DEV_24 0x00004000
-+#define TSSETUP_DEV_32 0x00005000
-+#define TSSETUP_DEV_64 0x00006000
-+#define TSSETUP_DEV_128 0x00007000
-+#define TSSETUP_ENABLE 0x00008000
-+#define TSSETUP_DLY_MASK 0x03FF0000
-+#define TSSETUP_DLY_SHIFT 16
-+#define TSSETUP_TDTCT 0x80000000
-+
-+#define TSMAXMIN_XMIN_MASK 0x000000FF
-+#define TSMAXMIN_XMIN_SHIFT 0
-+#define TSMAXMIN_YMIN_MASK 0x0000FF00
-+#define TSMAXMIN_YMIN_SHIFT 8
-+#define TSMAXMIN_XMAX_MASK 0x00FF0000
-+#define TSMAXMIN_XMAX_SHIFT 16
-+#define TSMAXMIN_YMAX_MASK 0xFF000000
-+#define TSMAXMIN_YMAX_SHIFT 24
-+
-+#define TSXYRESULT_X_MASK 0x00000FFF
-+#define TSXYRESULT_X_SHIFT 0
-+#define TSXYRESULT_AD_MASK 0x0000FFFF
-+#define TSXYRESULT_AD_SHIFT 0
-+#define TSXYRESULT_Y_MASK 0x0FFF0000
-+#define TSXYRESULT_Y_SHIFT 16
-+#define TSXYRESULT_SDR 0x80000000
-+
-+#define TSX_SAMPLE_MASK 0x00003FFF
-+#define TSX_SAMPLE_SHIFT 0x00
-+#define TSY_SAMPLE_MASK 0x3FFF0000
-+#define TSY_SAMPLE_SHIFT 0x10
-+
-+#define TSSETUP2_TINT 0x00000001
-+#define TSSETUP2_NICOR 0x00000002
-+#define TSSETUP2_PINT 0x00000004
-+#define TSSETUP2_PENSTS 0x00000008
-+#define TSSETUP2_PINTEN 0x00000010
-+#define TSSETUP2_DEVINT 0x00000020
-+#define TSSETUP2_DINTEN 0x00000040
-+#define TSSETUP2_DTMEN 0x00000080
-+#define TSSETUP2_DISDEV 0x00000100
-+#define TSSETUP2_NSIGND 0x00000200
-+#define TSSETUP2_S28EN 0x00000400
-+#define TSSETUP2_RINTEN 0x00000800
-+
-+#define TSXYRESULT_SDR 0x80000000
-+
-+/*
-+ * These are used as trigger levels to know when we have pen up/down.
-+ * The rules:
-+ * 1. TS_HEAVY_INV_PRESSURE < TS_LIGHT_INV_PRESSURE because these
-+ * are Inverse pressure.
-+ * 2. Any touch lighter than TS_LIGHT_INV_PRESSURE is a pen up.
-+ * 3. Any touch heavier than TS_HEAVY_INV_PRESSURE is a pen down.
-+ */
-+#define TS_HEAVY_INV_PRESSURE 0xFE0 /* C00 */
-+#define TS_LIGHT_INV_PRESSURE 0xFFF /* e00 */
-+
-+/*
-+ * If the x, y, or inverse pressure changes more than these values
-+ * between two succeeding points, the point is not reported.
-+ */
-+#define TS_MAX_VALID_XY_CHANGE 0x300
-+#define TS_MAX_VALID_PRESSURE_CHANGE 0x100
-+
-+/*
-+ * This is the minimum Z1 Value that is valid.
-+ */
-+#define MIN_Z1_VALUE 0x50
-+
-+/*
-+ * Settling delay for taking each ADC measurement. Increase this
-+ * if ts is jittery.
-+ */
-+#define EP93XX_TS_ADC_DELAY_USEC 2000
-+
-+/*
-+ * Delay between TS points.
-+ */
-+#define EP93XX_TS_PER_POINT_DELAY_USEC 10000
-+
-+/*
-+ * A few more macros...
-+ */
-+#define TSSETUP_DEFAULT (TSSETUP_NSMP_32 | TSSETUP_DEV_64 | \
-+ ((128<<TSSETUP_SDLY_SHIFT) & TSSETUP_SDLY_MASK) | \
-+ ((128<<TSSETUP_DLY_SHIFT) & TSSETUP_DLY_MASK))
-+
-+#define TSSETUP2_DEFAULT (TSSETUP2_NSIGND)
-+
-+/*
-+ * For now, we use one of the minor numbers from the local/experimental
-+ * range.
-+ */
-+#define EP93XX_TS_MINOR 240
-+
-+/*
-+ * Static Declarations
-+ */
-+static unsigned int guiLastX, guiLastY;
-+static unsigned int guiLastInvPressure;
-+
-+struct TouchScreenSample
-+{
-+ int currentX;
-+ int currentY;
-+ int currentButton;
-+ int currentPressure;
-+ struct timeval currentTime;
-+};
-+
-+/*
-+ * This must match the structure in tslib.
-+ */
-+struct ts_sample {
-+ int x;
-+ int y;
-+ unsigned int pressure;
-+ struct timeval tv;
-+};
-+
-+static struct TouchScreenSample gSample;
-+static int bFreshTouchData;
-+static int bCurrentPenDown;
-+
-+static DECLARE_WAIT_QUEUE_HEAD(queue);
-+static DEFINE_SEMAPHORE(open_sem);
-+static DEFINE_SPINLOCK(event_buffer_lock);
-+static struct fasync_struct *ep93xx_fasync;
-+
-+/*
-+ * Typedef Declarations
-+ */
-+typedef enum {
-+ TS_MODE_UN_INITIALIZED,
-+ TS_MODE_HARDWARE_SCAN,
-+ TS_MODE_SOFT_SCAN
-+} ts_mode_t;
-+
-+static ts_mode_t gScanningMode;
-+
-+typedef enum{
-+ TS_STATE_STOPPED = 0,
-+ TS_STATE_Z1,
-+ TS_STATE_Z2,
-+ TS_STATE_Y,
-+ TS_STATE_X,
-+ TS_STATE_DONE
-+} ts_states_t;
-+
-+typedef struct
-+{
-+ unsigned int uiX;
-+ unsigned int uiY;
-+ unsigned int uiZ1;
-+ unsigned int uiZ2;
-+ ts_states_t state;
-+} ts_struct_t;
-+
-+static ts_struct_t sTouch;
-+
-+/*
-+ * From the spec, here's how to set up the touch screen's switch registers.
-+ */
-+typedef struct
-+{
-+ unsigned int uiDetect;
-+ unsigned int uiDischarge;
-+ unsigned int uiXSample;
-+ unsigned int uiYSample;
-+ unsigned int uiSwitchZ1;
-+ unsigned int uiSwitchZ2;
-+}SwitchStructType;
-+
-+/*
-+ * Here's the switch settings for a 4-wire touchscreen. See the spec
-+ * for how to handle a 4, 7, or 8-wire.
-+ */
-+const static SwitchStructType sSwitchSettings =
-+/* s28en=0 */
-+/* TSDetect TSDischarge TSXSample TSYSample SwitchZ1 SwitchZ2 */
-+ {0x00403604, 0x0007fe04, 0x00081604, 0x00104601, 0x00101601, 0x00101608};
-+
-+/*
-+ * Function declarations
-+ */
-+static void ep93xx_ts_set_direct(unsigned int uiADCSwitch);
-+static irqreturn_t ep93xx_ts_isr(int irq, void *dev_id);
-+static irqreturn_t ep93xx_timer2_isr(int irq, void *dev_id);
-+static void ee93xx_ts_evt_add(int button, int dX, int dY, int Pressure);
-+static ssize_t ep93xx_ts_read(struct file *filp, char *buf,
-+ size_t count, loff_t *l);
-+static unsigned int ep93xx_ts_poll(struct file *filp, poll_table *wait);
-+static int ep93xx_ts_open(struct inode *inode, struct file *filp);
-+static int ep93xx_ts_fasync(int fd, struct file *filp, int on);
-+static int ep93xx_ts_release(struct inode *inode, struct file *filp);
-+static ssize_t ep93xx_ts_write(struct file *file, const char *buffer,
-+ size_t count, loff_t *ppos);
-+static void ep93xx_ts_setup(void);
-+static void ep93xx_ts_shutdown(void);
-+int __init ep93xx_ts_init(void);
-+void __exit ep93xx_ts_exit(void);
-+static unsigned int CalculateInvPressure(void);
-+static unsigned int ADCGetData(unsigned int uiSamples, unsigned int uiMaxDiff);
-+static void TS_Soft_Scan_Mode(void);
-+static void TS_Hardware_Scan_Mode(void);
-+static void ProcessPointData(void);
-+static void Set_Timer2_uSec(unsigned int Delay_mSec);
-+static void Stop_Timer2(void);
-+
-+/*
-+ * ep93xx_ts_isr
-+ */
-+static irqreturn_t ep93xx_ts_isr(int irq, void *dev_id)
-+{
-+ /*
-+ * Note that we don't clear the interrupt here. The interrupt
-+ * gets cleared in TS_Soft_Scan_Mode when the TS ENABLE
-+ * bit is cleared.
-+ */
-+
-+ /*
-+ * Set the ts to manual polling mode and schedule a callback.
-+ * That way we can return from the isr in a reasonable amount of
-+ * time and process the touch in the callback after a brief delay.
-+ */
-+ TS_Soft_Scan_Mode();
-+
-+ return(IRQ_HANDLED);
-+}
-+
-+/*
-+ * Save the current ts 'event' in an atomic fashion.
-+ */
-+static void ee93xx_ts_evt_add(int buttons, int iX, int iY, int iPressure)
-+{
-+ /*
-+ * Note the event, but use spinlocks to keep it from getting
-+ * halfway read if we get interrupted.
-+ */
-+
-+ spin_lock(&event_buffer_lock);
-+
-+ gSample.currentX = iX;
-+ gSample.currentY = iY;
-+ gSample.currentButton = buttons;
-+ gSample.currentPressure = iPressure;
-+ bFreshTouchData = 1;
-+ do_gettimeofday(&gSample.currentTime);
-+
-+ spin_unlock(&event_buffer_lock);
-+
-+ kill_fasync(&ep93xx_fasync, SIGIO, POLL_IN);
-+ wake_up_interruptible(&queue);
-+}
-+
-+
-+static ssize_t ep93xx_ts_read(struct file *filp, char *buf, size_t count, loff_t *l)
-+{
-+ unsigned short data[3];
-+ struct ts_sample ts_data;
-+ int iReturn = -EFAULT;
-+
-+ if (!bFreshTouchData)
-+ {
-+ iReturn = 0;
-+ }
-+ else if (count == sizeof(data))
-+ {
-+ spin_lock_irq(&event_buffer_lock);
-+ bFreshTouchData = 0;
-+ data[0] = gSample.currentX;
-+ data[1] = gSample.currentY;
-+ data[2] = gSample.currentButton;
-+
-+ spin_unlock_irq(&event_buffer_lock);
-+
-+ if (copy_to_user(buf, data, sizeof data))
-+ return -EFAULT;
-+
-+ count -= sizeof(data);
-+
-+ /* return the # of bytes that got read */
-+ iReturn = sizeof(data) ;
-+ }
-+ else if (count == sizeof(struct ts_sample) )
-+ {
-+ spin_lock_irq(&event_buffer_lock);
-+ bFreshTouchData = 0;
-+ ts_data.x = gSample.currentX;
-+ ts_data.y = gSample.currentY;
-+ ts_data.pressure = gSample.currentPressure;
-+ ts_data.tv = gSample.currentTime;
-+ spin_unlock_irq(&event_buffer_lock);
-+
-+ if (copy_to_user(buf, &ts_data, sizeof(struct ts_sample)))
-+ {
-+ iReturn = -EFAULT;
-+ }
-+ else
-+ {
-+ count -= sizeof(ts_data);
-+ iReturn = sizeof(ts_data);
-+ }
-+ }
-+
-+ return iReturn;
-+}
-+
-+static unsigned int ep93xx_ts_poll(struct file *filp, poll_table *wait)
-+{
-+ poll_wait(filp, &queue, wait);
-+
-+ if (bFreshTouchData)
-+ {
-+ return POLLIN | POLLRDNORM;
-+ }
-+
-+ return 0;
-+}
-+
-+static int ep93xx_ts_open(struct inode *inode, struct file *filp)
-+{
-+ if (down_trylock(&open_sem))
-+ {
-+ return -EBUSY;
-+ }
-+
-+ ep93xx_ts_setup();
-+
-+ return 0;
-+}
-+
-+/*
-+ * Asynchronous I/O support.
-+ */
-+static int ep93xx_ts_fasync(int fd, struct file *filp, int on)
-+{
-+ int retval;
-+
-+ retval = fasync_helper(fd, filp, on, &ep93xx_fasync);
-+ if (retval < 0)
-+ {
-+ return retval;
-+ }
-+
-+ return 0;
-+}
-+
-+static int ep93xx_ts_release(struct inode *inode, struct file *filp)
-+{
-+ Stop_Timer2();
-+
-+ /*
-+ * Call our async I/O support to request that this file
-+ * cease to be used for async I/O.
-+ */
-+ ep93xx_ts_fasync(-1, filp, 0);
-+
-+ ep93xx_ts_shutdown();
-+
-+ up(&open_sem);
-+
-+ return 0;
-+}
-+
-+static ssize_t ep93xx_ts_write(struct file *file, const char *buffer, size_t count,
-+ loff_t *ppos)
-+{
-+ return -EINVAL;
-+}
-+
-+
-+static int ep93xx_ts_ioctl(struct inode *inode, struct file *file, uint command, ulong u)
-+{
-+ static const int version = EV_VERSION;
-+ static const u_int32_t bit =(1 << EV_ABS);
-+ static const u_int32_t absbit = (1 << ABS_X) | (1 << ABS_Y) | (1 << ABS_PRESSURE);
-+ int iReturn ;
-+ int i = 0;
-+
-+ switch(command)
-+ {
-+ case EVIOCGVERSION:
-+ i = copy_to_user((void __user *)u, (void *)version, sizeof(version));
-+ iReturn = i ? -EFAULT : 0;
-+ break;
-+
-+ case EVIOCGBIT(0,sizeof(u_int32_t) * 8) :
-+ i = copy_to_user((void __user *)u, (void *)bit, sizeof(bit));
-+ iReturn = i ? -EFAULT : 0;
-+ break;
-+
-+ case EVIOCGBIT(EV_ABS, sizeof(absbit) * 8):
-+ i = copy_to_user((void __user *)u, (void *)absbit, sizeof(absbit));
-+ iReturn = i ? -EFAULT : 0;
-+ break;
-+ default:
-+ iReturn = -1;
-+ break;
-+ }
-+
-+ return iReturn;
-+}
-+
-+static struct file_operations ep93xx_ts_fops = {
-+ owner: THIS_MODULE,
-+ read: ep93xx_ts_read,
-+ write: ep93xx_ts_write,
-+ poll: ep93xx_ts_poll,
-+ open: ep93xx_ts_open,
-+ unlocked_ioctl: ep93xx_ts_ioctl,
-+ release: ep93xx_ts_release,
-+ fasync: ep93xx_ts_fasync,
-+};
-+
-+static struct miscdevice ep93xx_ts_miscdev =
-+{
-+ EP93XX_TS_MINOR,
-+ "ep93xx_ts",
-+ &ep93xx_ts_fops
-+};
-+
-+void ep93xx_ts_setup(void)
-+{
-+ unsigned int uiKTDIV, uiTSXYMaxMin;
-+
-+ /*
-+ * Set the TSEN bit in KTDIV so that we are enabling the clock
-+ * for the touchscreen.
-+ */
-+ uiKTDIV = __raw_readl(EP93XX_SYSCON_KEYTCHCLKDIV);
-+ uiKTDIV |= EP93XX_SYSCON_KEYTCHCLKDIV_TSEN;
-+ ep93xx_syscon_swlocked_write(uiKTDIV, EP93XX_SYSCON_KEYTCHCLKDIV);
-+
-+ /*
-+ * Program the EP93XX_TOUCHSCREEN_SETUP and TSSetup2 registers.
-+ */
-+ __raw_writel(TSSETUP_DEFAULT, EP93XX_TOUCHSCREEN_SETUP);
-+ __raw_writel(TSSETUP2_DEFAULT, EP93XX_TOUCHSCREEN_SETUP2);
-+
-+ /*
-+ * Set the the touch settings.
-+ */
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(sSwitchSettings.uiDischarge, EP93XX_TOUCHSCREEN_DIRECT);
-+
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(sSwitchSettings.uiDischarge, EP93XX_TOUCHSCREEN_DISCHARGE);
-+
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(sSwitchSettings.uiSwitchZ1, EP93XX_TOUCHSCREEN_XSAMPLE);
-+
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(sSwitchSettings.uiSwitchZ2, EP93XX_TOUCHSCREEN_YSAMPLE);
-+
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(sSwitchSettings.uiDetect, EP93XX_TOUCHSCREEN_DETECT);
-+
-+ /*
-+ * X,YMin set to 0x40 = have to drag that many pixels for a new irq.
-+ * X,YMax set to 0x40 = 1024 pixels is the maximum movement within the
-+ * time scan limit.
-+ */
-+ uiTSXYMaxMin = (50 << TSMAXMIN_XMIN_SHIFT) & TSMAXMIN_XMIN_MASK;
-+ uiTSXYMaxMin |= (50 << TSMAXMIN_YMIN_SHIFT) & TSMAXMIN_YMIN_MASK;
-+ uiTSXYMaxMin |= (0xff << TSMAXMIN_XMAX_SHIFT) & TSMAXMIN_XMAX_MASK;
-+ uiTSXYMaxMin |= (0xff << TSMAXMIN_YMAX_SHIFT) & TSMAXMIN_YMAX_MASK;
-+ __raw_writel(uiTSXYMaxMin, EP93XX_TOUCHSCREEN_XYMAXMIN);
-+
-+ bCurrentPenDown = 0;
-+ bFreshTouchData = 0;
-+ guiLastX = 0;
-+ guiLastY = 0;
-+ guiLastInvPressure = 0xffffff;
-+
-+ /*
-+ * Enable the touch screen scanning engine.
-+ */
-+ TS_Hardware_Scan_Mode();
-+}
-+
-+/*
-+ * ep93xx_ts_shutdown
-+ *
-+ */
-+static void
-+ep93xx_ts_shutdown(void)
-+{
-+ unsigned int uiKTDIV;
-+
-+ sTouch.state = TS_STATE_STOPPED;
-+ Stop_Timer2();
-+
-+ /*
-+ * Disable the scanning engine.
-+ */
-+ __raw_writel(0, EP93XX_TOUCHSCREEN_SETUP);
-+ __raw_writel(0, EP93XX_TOUCHSCREEN_SETUP2);
-+
-+ /*
-+ * Clear the TSEN bit in KTDIV so that we are disabling the clock
-+ * for the touchscreen.
-+ */
-+ uiKTDIV = __raw_readl(EP93XX_SYSCON_KEYTCHCLKDIV);
-+ uiKTDIV &= ~EP93XX_SYSCON_KEYTCHCLKDIV_TSEN;
-+ ep93xx_syscon_swlocked_write(uiKTDIV, EP93XX_SYSCON_KEYTCHCLKDIV);
-+
-+} /* ep93xx_ts_shutdown */
-+
-+static irqreturn_t ep93xx_timer2_isr(int irq, void *dev_id)
-+{
-+ switch(sTouch.state)
-+ {
-+ case TS_STATE_STOPPED:
-+ TS_Hardware_Scan_Mode();
-+ break;
-+
-+ /*
-+ * Get the Z1 value for pressure measurement and set up
-+ * the switch register for getting the Z2 measurement.
-+ */
-+ case TS_STATE_Z1:
-+ Set_Timer2_uSec(EP93XX_TS_ADC_DELAY_USEC);
-+ sTouch.uiZ1 = ADCGetData(2, 200);
-+ ep93xx_ts_set_direct(sSwitchSettings.uiSwitchZ2);
-+ sTouch.state = TS_STATE_Z2;
-+ break;
-+
-+ /*
-+ * Get the Z2 value for pressure measurement and set up
-+ * the switch register for getting the Y measurement.
-+ */
-+ case TS_STATE_Z2:
-+ sTouch.uiZ2 = ADCGetData(2, 200);
-+ ep93xx_ts_set_direct(sSwitchSettings.uiYSample);
-+ sTouch.state = TS_STATE_Y;
-+ break;
-+
-+ /*
-+ * Get the Y value and set up the switch register for
-+ * getting the X measurement.
-+ */
-+ case TS_STATE_Y:
-+ sTouch.uiY = ADCGetData(4, 20);
-+ ep93xx_ts_set_direct(sSwitchSettings.uiXSample);
-+ sTouch.state = TS_STATE_X;
-+ break;
-+
-+ /*
-+ * Read the X value. This is the last of the 4 adc values
-+ * we need so we continue on to process the data.
-+ */
-+ case TS_STATE_X:
-+ Stop_Timer2();
-+
-+ sTouch.uiX = ADCGetData(4, 20);
-+
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(sSwitchSettings.uiDischarge, EP93XX_TOUCHSCREEN_DIRECT);
-+
-+ sTouch.state = TS_STATE_DONE;
-+
-+ /*
-+ * Process this set of ADC readings.
-+ */
-+ ProcessPointData();
-+
-+ break;
-+
-+ /*
-+ * Shouldn't get here. But if we do, we can recover...
-+ */
-+ case TS_STATE_DONE:
-+ TS_Hardware_Scan_Mode();
-+ break;
-+ }
-+
-+ /*
-+ * Clear the timer2 interrupt.
-+ */
-+ __raw_writel(1, EP93XX_TIMER2_CLEAR);
-+ return(IRQ_HANDLED);
-+}
-+
-+/*---------------------------------------------------------------------
-+ * ProcessPointData
-+ *
-+ * This routine processes the ADC data into usable point data and then
-+ * puts the driver into hw or sw scanning mode before returning.
-+ *
-+ * We calculate inverse pressure (lower number = more pressure) then
-+ * do a hystheresis with the two pressure values 'light' and 'heavy'.
-+ *
-+ * If we are above the light, we have pen up.
-+ * If we are below the heavy we have pen down.
-+ * As long as the pressure stays below the light, pen stays down.
-+ * When we get above the light again, pen goes back up.
-+ *
-+ */
-+static void ProcessPointData(void)
-+{
-+ int bValidPoint = 0;
-+ unsigned int uiXDiff, uiYDiff, uiInvPressureDiff;
-+ unsigned int uiInvPressure;
-+
-+ /*
-+ * Calculate the current pressure.
-+ */
-+ uiInvPressure = CalculateInvPressure();
-+
-+ /*
-+ * If pen pressure is so light that it is greater than the 'max' setting
-+ * then we consider this to be a pen up.
-+ */
-+ if (uiInvPressure >= TS_LIGHT_INV_PRESSURE)
-+ {
-+ bCurrentPenDown = 0;
-+ ee93xx_ts_evt_add(0, guiLastX, guiLastY, 0);
-+ TS_Hardware_Scan_Mode();
-+ return;
-+ }
-+
-+ /*
-+ * Hysteresis:
-+ * If the pen pressure is hard enough to be less than the 'min' OR
-+ * the pen is already down and is still less than the 'max'...
-+ */
-+ if ((uiInvPressure < TS_HEAVY_INV_PRESSURE) ||
-+ (bCurrentPenDown && (uiInvPressure < TS_LIGHT_INV_PRESSURE)))
-+ {
-+ if (bCurrentPenDown)
-+ {
-+ /*
-+ * If pen was previously down, check the difference between
-+ * the last sample and this one... if the difference between
-+ * samples is too great, ignore the sample.
-+ */
-+ uiXDiff = abs(guiLastX - sTouch.uiX);
-+ uiYDiff = abs(guiLastY - sTouch.uiY);
-+ uiInvPressureDiff = abs(guiLastInvPressure - uiInvPressure);
-+
-+ if (uiXDiff < TS_MAX_VALID_XY_CHANGE
-+ && uiYDiff < TS_MAX_VALID_XY_CHANGE
-+ && uiInvPressureDiff < TS_MAX_VALID_PRESSURE_CHANGE)
-+ {
-+ bValidPoint = 1;
-+ }
-+ }
-+ else
-+ {
-+ bValidPoint = 1;
-+ }
-+
-+ /*
-+ * If either the pen was put down or dragged make a note of it.
-+ */
-+ if (bValidPoint)
-+ {
-+ guiLastX = sTouch.uiX;
-+ guiLastY = sTouch.uiY;
-+ guiLastInvPressure = uiInvPressure;
-+ bCurrentPenDown = 1;
-+ ee93xx_ts_evt_add(1, sTouch.uiX, sTouch.uiY,
-+ 0x7000000 / uiInvPressure);
-+ }
-+
-+ TS_Soft_Scan_Mode();
-+ return;
-+ }
-+
-+ TS_Hardware_Scan_Mode();
-+}
-+
-+static void ep93xx_ts_set_direct(unsigned int uiADCSwitch)
-+{
-+ unsigned int uiResult;
-+
-+ /*
-+ * Set the switch settings in the direct register.
-+ */
-+ __raw_writel(0xaa, EP93XX_TOUCHSCREEN_SWLOCK);
-+ __raw_writel(uiADCSwitch, EP93XX_TOUCHSCREEN_DIRECT);
-+
-+ /*
-+ * Read and throw away the first sample.
-+ */
-+ do {
-+ uiResult = __raw_readl(EP93XX_TOUCHSCREEN_XYRESULT);
-+ } while (!(uiResult & TSXYRESULT_SDR));
-+
-+}
-+
-+static unsigned int ADCGetData(unsigned int uiSamples, unsigned int uiMaxDiff)
-+{
-+ unsigned int uiResult, uiValue, uiCount, uiLowest, uiHighest, uiSum, uiAve;
-+
-+ do
-+ {
-+ /*
-+ * Initialize our values.
-+ */
-+ uiLowest = 0xfffffff;
-+ uiHighest = 0;
-+ uiSum = 0;
-+
-+ for (uiCount = 0; uiCount < uiSamples; uiCount++)
-+ {
-+ /*
-+ * Read the touch screen four more times and average.
-+ */
-+ do {
-+ uiResult = __raw_readl(EP93XX_TOUCHSCREEN_XYRESULT);
-+ } while (!(uiResult & TSXYRESULT_SDR));
-+
-+ uiValue = (uiResult & TSXYRESULT_AD_MASK) >> TSXYRESULT_AD_SHIFT;
-+ uiValue = ((uiValue >> 4) + ((1 + TSXYRESULT_X_MASK)>>1)) & TSXYRESULT_X_MASK;
-+
-+ /*
-+ * Add up the values.
-+ */
-+ uiSum += uiValue;
-+
-+ /*
-+ * Get the lowest and highest values.
-+ */
-+ if (uiValue < uiLowest)
-+ {
-+ uiLowest = uiValue;
-+ }
-+ if (uiValue > uiHighest)
-+ {
-+ uiHighest = uiValue;
-+ }
-+ }
-+ } while ((uiHighest - uiLowest) > uiMaxDiff);
-+
-+ /*
-+ * Calculate the Average value.
-+ */
-+ uiAve = uiSum / uiSamples;
-+
-+ return uiAve;
-+}
-+
-+/*
-+ * CalculateInvPressure
-+ *
-+ * Is the Touch Valid. Touch is not valid if the X or Y value is not
-+ * in range and the pressure is not enough.
-+ *
-+ * Touch resistance can be measured by the following formula:
-+ *
-+ * Rx * X * Z2
-+ * Rtouch = --------- * (-- - 1)
-+ * 4096 Z1
-+ *
-+ * This is simplified in the ration of Rtouch to Rx. The lower the value, the
-+ * higher the pressure.
-+ *
-+ * Z2
-+ * InvPressure = X * (-- - 1)
-+ * Z1
-+ */
-+static unsigned int CalculateInvPressure(void)
-+{
-+ unsigned int uiInvPressure;
-+
-+ /*
-+ * Check to see if the point is valid.
-+ */
-+ if (sTouch.uiZ1 < MIN_Z1_VALUE)
-+ {
-+ uiInvPressure = 0x10000;
-+ }
-+
-+ /*
-+ * Can omit the pressure calculation if you need to get rid of the division.
-+ */
-+ else
-+ {
-+ uiInvPressure = ((sTouch.uiX * sTouch.uiZ2) / sTouch.uiZ1) - sTouch.uiX;
-+ }
-+
-+ return uiInvPressure;
-+}
-+
-+/*
-+ * TS_Hardware_Scan_Mode
-+ *
-+ * Enables the ep93xx ts scanning engine so that when the pen goes down
-+ * we will get an interrupt.
-+ */
-+static void TS_Hardware_Scan_Mode(void)
-+{
-+ unsigned int uiDevCfg;
-+
-+ /*
-+ * Disable the soft scanning engine.
-+ */
-+ sTouch.state = TS_STATE_STOPPED;
-+ Stop_Timer2();
-+
-+ /*
-+ * Clear the TIN (Touchscreen INactive) bit so we can go to
-+ * automatic scanning mode.
-+ */
-+ uiDevCfg = __raw_readl(EP93XX_SYSCON_DEVCFG);
-+ ep93xx_syscon_swlocked_write(uiDevCfg & ~EP93XX_SYSCON_DEVCFG_TIN,
-+ EP93XX_SYSCON_DEVCFG);
-+
-+ /*
-+ * Enable the touch screen scanning state machine by setting
-+ * the ENABLE bit.
-+ */
-+ __raw_writel(TSSETUP_DEFAULT | TSSETUP_ENABLE, EP93XX_TOUCHSCREEN_SETUP);
-+
-+ /*
-+ * Set the flag to show that we are in interrupt mode.
-+ */
-+ gScanningMode = TS_MODE_HARDWARE_SCAN;
-+
-+ /*
-+ * Initialize EP93XX_TOUCHSCREEN_SETUP2 register.
-+ */
-+ __raw_writel(TSSETUP2_DEFAULT, EP93XX_TOUCHSCREEN_SETUP2);
-+
-+}
-+
-+/*
-+ * TS_Soft_Scan_Mode
-+ *
-+ * Sets the touch screen to manual polling mode.
-+ */
-+static void TS_Soft_Scan_Mode(void)
-+{
-+ unsigned int uiDevCfg;
-+
-+ if (gScanningMode != TS_MODE_SOFT_SCAN)
-+ {
-+ /*
-+ * Disable the touch screen scanning state machine by clearing
-+ * the ENABLE bit.
-+ */
-+ __raw_writel(TSSETUP_DEFAULT, EP93XX_TOUCHSCREEN_SETUP);
-+
-+ /*
-+ * Set the TIN bit so we can do manual touchscreen polling.
-+ */
-+ uiDevCfg = __raw_readl(EP93XX_SYSCON_DEVCFG);
-+ ep93xx_syscon_swlocked_write(uiDevCfg | EP93XX_SYSCON_DEVCFG_TIN,
-+ EP93XX_SYSCON_DEVCFG);
-+ }
-+
-+ /*
-+ * Set the switch register up for the first ADC reading
-+ */
-+ ep93xx_ts_set_direct(sSwitchSettings.uiSwitchZ1);
-+
-+ /*
-+ * Initialize our software state machine to know which ADC
-+ * reading to take
-+ */
-+ sTouch.state = TS_STATE_Z1;
-+
-+ /*
-+ * Set the timer so after a mSec or two settling delay it will
-+ * take the first ADC reading.
-+ */
-+ Set_Timer2_uSec(EP93XX_TS_PER_POINT_DELAY_USEC);
-+
-+ /*
-+ * Note that we are in sw scanning mode not hw scanning mode.
-+ */
-+ gScanningMode = TS_MODE_SOFT_SCAN;
-+
-+}
-+
-+static void Set_Timer2_uSec(unsigned int uiDelay_uSec)
-+{
-+ unsigned int uiClockTicks;
-+
-+ /*
-+ * Stop timer 2
-+ */
-+ __raw_writel(0, EP93XX_TIMER2_CONTROL);
-+
-+ uiClockTicks = ((uiDelay_uSec * 508) + 999) / 1000;
-+ __raw_writel(uiClockTicks, EP93XX_TIMER2_LOAD);
-+ __raw_writel(uiClockTicks, EP93XX_TIMER2_VALUE);
-+
-+ /*
-+ * Set up Timer 2 for 508 kHz clock and periodic mode.
-+ */
-+ __raw_writel(0xC8, EP93XX_TIMER2_CONTROL);
-+
-+}
-+
-+static void Stop_Timer2(void)
-+{
-+ __raw_writel(0, EP93XX_TIMER2_CONTROL);
-+}
-+
-+/*
-+ * Initialization and exit routines
-+ */
-+int __init ep93xx_ts_init(void)
-+{
-+ int retval;
-+
-+ retval = request_irq(IRQ_EP93XX_TOUCH, ep93xx_ts_isr,
-+ IRQF_DISABLED, "ep93xx_ts", 0);
-+ if (retval)
-+ {
-+ printk(KERN_WARNING "ep93xx_ts: failed to get touchscreen IRQ\n");
-+ return retval;
-+ }
-+
-+ retval = request_irq(IRQ_EP93XX_TIMER2, ep93xx_timer2_isr,
-+ IRQF_DISABLED, "ep93xx_timer2", 0);
-+ if (retval)
-+ {
-+ printk(KERN_WARNING "ep93xx_ts: failed to get timer2 IRQ\n");
-+ free_irq(IRQ_EP93XX_TOUCH, 0);
-+ return retval;
-+ }
-+
-+ misc_register(&ep93xx_ts_miscdev);
-+
-+ sTouch.state = TS_STATE_STOPPED;
-+ gScanningMode = TS_MODE_UN_INITIALIZED;
-+
-+ printk(KERN_NOTICE "ep93xx touchscreen driver configured for 4-wire operation\n");
-+
-+ return 0;
-+}
-+
-+void __exit ep93xx_ts_exit(void)
-+{
-+ Stop_Timer2();
-+
-+ free_irq(IRQ_EP93XX_TOUCH, 0);
-+ free_irq(IRQ_EP93XX_TIMER2, 0);
-+
-+ misc_deregister(&ep93xx_ts_miscdev);
-+}
-+
-+module_init(ep93xx_ts_init);
-+module_exit(ep93xx_ts_exit);
-+
-+MODULE_DESCRIPTION("Cirrus EP93xx touchscreen driver");
-+MODULE_SUPPORTED_DEVICE("touchscreen/ep93xx");
-+MODULE_LICENSE("GPL");
---- a/arch/arm/mach-ep93xx/core.c
-+++ b/arch/arm/mach-ep93xx/core.c
-@@ -205,6 +205,7 @@ void ep93xx_syscon_swlocked_write(unsign
-
- spin_unlock_irqrestore(&syscon_swlock, flags);
- }
-+EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
-
- void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
- {
+++ /dev/null
-This enables the mmc-over-spi driver for the Sim.One board, based on Mika's
-patch, which used a GPIO for chip select in stead of the default SFRMOUT pin.
-I've modified it to use the usual SFRMOUT; if you've modified your Sim.One
-board to use a GPIO instead, uncomment and modify
-// #define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO15
-in the source file.
- -martinwguy, 14 May 2010
-
-From: Mika Westerberg <mika.westerberg@iki.fi>
-Date: Wed, 28 Apr 2010 08:42:46 +0300
-Subject: [PATCH] ep93xx: simone: added board specific SPI support for MMC/SD cards
-
-This includes setting up EGPIOs 0 and 9 for card detection and chip select
-respectively.
-
---- a/arch/arm/mach-ep93xx/simone.c
-+++ b/arch/arm/mach-ep93xx/simone.c
-@@ -20,10 +20,15 @@
- #include <linux/platform_device.h>
- #include <linux/i2c.h>
- #include <linux/i2c-gpio.h>
-+#include <linux/gpio.h>
-+#include <linux/mmc/host.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/mmc_spi.h>
-
- #include <mach/hardware.h>
- #include <linux/platform_data/video-ep93xx.h>
- #include <mach/gpio-ep93xx.h>
-+#include <linux/platform_data/spi-ep93xx.h>
-
- #include <asm/hardware/vic.h>
- #include <asm/mach-types.h>
-@@ -41,6 +46,135 @@ static struct ep93xxfb_mach_info __initd
- .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
- };
-
-+/*
-+ * GPIO lines used for MMC card detection.
-+ */
-+#define MMC_CARD_DETECT_GPIO EP93XX_GPIO_LINE_EGPIO0
-+
-+/*
-+ * If you have hacked your Sim.One to use a GPIO as SD card chip select
-+ * (SD pin 1), uncomment the following line.
-+ * The example, EGPIO15, is on TP17 near the CPU.
-+ */
-+// #define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO15
-+
-+/*
-+ * MMC SPI chip select GPIO handling. If you are using SFRMOUT (SFRM1) signal,
-+ * you can leave these empty and pass NULL as .controller_data.
-+ */
-+
-+#ifdef MMC_CHIP_SELECT_GPIO
-+static int simone_mmc_spi_setup(struct spi_device *spi)
-+{
-+ unsigned int gpio = MMC_CHIP_SELECT_GPIO;
-+ int err;
-+
-+ err = gpio_request(gpio, spi->modalias);
-+ if (err)
-+ return err;
-+
-+ err = gpio_direction_output(gpio, 1);
-+ if (err) {
-+ gpio_free(gpio);
-+ return err;
-+ }
-+
-+ return 0;
-+}
-+
-+static void simone_mmc_spi_cleanup(struct spi_device *spi)
-+{
-+ unsigned int gpio = MMC_CHIP_SELECT_GPIO;
-+
-+ gpio_set_value(gpio, 1);
-+ gpio_direction_input(gpio);
-+ gpio_free(gpio);
-+}
-+
-+static void simone_mmc_spi_cs_control(struct spi_device *spi, int value)
-+{
-+ gpio_set_value(MMC_CHIP_SELECT_GPIO, value);
-+}
-+
-+static struct ep93xx_spi_chip_ops simone_mmc_spi_ops = {
-+ .setup = simone_mmc_spi_setup,
-+ .cleanup = simone_mmc_spi_cleanup,
-+ .cs_control = simone_mmc_spi_cs_control,
-+};
-+#endif
-+
-+/*
-+ * MMC card detection GPIO setup.
-+ */
-+static int simone_mmc_spi_init(struct device *dev,
-+ irqreturn_t (*irq_handler)(int, void *), void *mmc)
-+{
-+ unsigned int gpio = MMC_CARD_DETECT_GPIO;
-+ int irq, err;
-+
-+ err = gpio_request(gpio, dev_name(dev));
-+ if (err)
-+ return err;
-+
-+ err = gpio_direction_input(gpio);
-+ if (err)
-+ goto fail;
-+
-+ irq = gpio_to_irq(gpio);
-+ if (irq < 0)
-+ goto fail;
-+
-+ err = request_irq(irq, irq_handler, IRQF_TRIGGER_FALLING,
-+ "MMC card detect", mmc);
-+ if (err)
-+ goto fail;
-+
-+ printk(KERN_INFO "%s: using irq %d for MMC card detection\n",
-+ dev_name(dev), irq);
-+
-+ return 0;
-+fail:
-+ gpio_free(gpio);
-+ return err;
-+}
-+
-+static void simone_mmc_spi_exit(struct device *dev, void *mmc)
-+{
-+ unsigned int gpio = MMC_CARD_DETECT_GPIO;
-+
-+ free_irq(gpio_to_irq(gpio), mmc);
-+ gpio_free(gpio);
-+}
-+
-+static struct mmc_spi_platform_data simone_mmc_spi_data = {
-+ .init = simone_mmc_spi_init,
-+ .exit = simone_mmc_spi_exit,
-+ .detect_delay = 500,
-+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
-+};
-+
-+static struct spi_board_info simone_spi_devices[] __initdata = {
-+ {
-+ .modalias = "mmc_spi",
-+#ifdef MMC_CHIP_SELECT_GPIO
-+ .controller_data = &simone_mmc_spi_ops,
-+#endif
-+ .platform_data = &simone_mmc_spi_data,
-+ /*
-+ * We use 10 MHz even though the maximum is 3.7 MHz. The driver
-+ * will limit it automatically to max. frequency.
-+ */
-+ .max_speed_hz = 10 * 1000 * 1000,
-+ .bus_num = 0,
-+ .chip_select = 0,
-+ .mode = SPI_MODE_3,
-+ },
-+};
-+
-+static struct ep93xx_spi_info simone_spi_info __initdata = {
-+ .num_chipselect = ARRAY_SIZE(simone_spi_devices),
-+};
-+
- static struct i2c_gpio_platform_data __initdata simone_i2c_gpio_data = {
- .sda_pin = EP93XX_GPIO_LINE_EEDAT,
- .sda_is_open_drain = 0,
-@@ -75,6 +209,8 @@ static void __init simone_init_machine(v
- ep93xx_register_fb(&simone_fb_info);
- ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
- ARRAY_SIZE(simone_i2c_board_info));
-+ ep93xx_register_spi(&simone_spi_info, simone_spi_devices,
-+ ARRAY_SIZE(simone_spi_devices));
- simone_register_audio();
- }
-
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Default
- NAME:=Default Profile
- PACKAGES:= \
- kmod-usb-core kmod-usb-ohci
-endef
-
-define Profile/Default/Description
- Default package set compatible with most EP93xx-based boards.
-endef
-$(eval $(call Profile,Default))
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Simone
- NAME:=Simplemachines Sim.One
- PACKAGES:= \
- kmod-input-core \
- kmod-input-evdev \
- kmod-input-keyboard-ep93xx \
- kmod-sound-core \
- kmod-sound-soc-ep93xx \
- kmod-sound-soc-ep93xx-ac97 \
- kmod-sound-soc-ep93xx-simone
-endef
-
-define Profile/Simone/Description
- Package set compatible with the Simplemachines Sim.One board.
-endef
-$(eval $(call Profile,Simone))
+++ /dev/null
-#
-# Copyright (C) 2009-2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=gemini
-BOARDNAME:=Cortina Systems CS351x
-FEATURES:=squashfs pci
-CPU_TYPE:=fa526
-MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
-
-LINUX_VERSION:=3.9.11
-
-KERNELNAME:="zImage"
-
-include $(INCLUDE_DIR)/target.mk
-
-$(eval $(call BuildTarget))
+++ /dev/null
-#!/bin/sh
-
-set_ether_mac() {
- CONFIG_PARTITION="$(grep "VCTL" /proc/mtd | cut -d: -f1)"
- MAC1="$(strings /dev/$CONFIG_PARTITION |grep MAC|cut -d: -f2|cut -c3-14|sed -e 's,\(..\),:\1,g' -e 's,^:,,')"
- MAC2="$(strings /dev/$CONFIG_PARTITION |grep MAC|cut -d: -f8|cut -c3-14|sed -e 's,\(..\),:\1,g' -e 's,^:,,')"
-
- ifconfig eth0 hw ether $MAC1 2>/dev/null
- ifconfig eth1 hw ether $MAC2 2>/dev/null
-}
-
-boot_hook_add preinit_main set_ether_mac
-
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_GEMINI=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_USES_GETTIMEOFFSET=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARPD is not set
-CONFIG_ATAGS=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,19200 mem=32M"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CPU_32v4=y
-CONFIG_CPU_ABRT_EV4=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_FA=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_FA=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_FA526=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_TLB_FA=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_USER is not set
-# CONFIG_DLCI is not set
-CONFIG_DMADEVICES=y
-CONFIG_DNOTIFY=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GEMINI_MEM_SWAP=y
-CONFIG_GEMINI_NET_ENGINE_GMAC=y
-CONFIG_GEMINI_WATCHDOG=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_IRQ_WORK=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_MACH_NAS4220B is not set
-# CONFIG_MACH_RUT100 is not set
-CONFIG_MACH_WBD111=y
-CONFIG_MACH_WBD222=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_MACH_GPIO_H=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_RCU_STALL_COMMON is not set
-# CONFIG_SCHED_HRTICK is not set
-# CONFIG_SCSI_DMA is not set
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_UID16=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_SUPPORT=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WAN=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_GEMINI=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_USES_GETTIMEOFFSET=y
-# CONFIG_ARCH_VT8500_SINGLE is not set
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARPD is not set
-CONFIG_ATA=m
-CONFIG_ATAGS=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,19200 mem=32M"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CPU_32v4=y
-CONFIG_CPU_ABRT_EV4=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_FA=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_FA=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_FA526=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_TLB_FA=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_USER is not set
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DLCI=m
-CONFIG_DLCI_MAX=8
-CONFIG_DMADEVICES=y
-CONFIG_DNOTIFY=y
-# CONFIG_DSCC4 is not set
-# CONFIG_FARSYNC is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_GEMINI_MEM_SWAP=y
-CONFIG_GEMINI_NET_ENGINE_GMAC=y
-CONFIG_GEMINI_WATCHDOG=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_AOUT=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HDLC=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_RAW=m
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_MACH_NAS4220B is not set
-# CONFIG_MACH_RUT100 is not set
-CONFIG_MACH_WBD111=y
-CONFIG_MACH_WBD222=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NLS=m
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PERCPU_RWSEM=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_SCSI=m
-CONFIG_SCSI_MOD=m
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_UID16=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB=m
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_COMMON=m
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WAN=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2009-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/Prepare
-# WBD111: mach id 1690 (0x69a)
- echo -en "\x06\x1c\xa0\xe3\x9a\x10\x81\xe3" > $(KDIR)/$(IMG_PREFIX)-wbd111-zImage
- cat $(KDIR)/zImage >> $(KDIR)/$(IMG_PREFIX)-wbd111-zImage
-# WBD222: mach id 2753 (0xAC1)
- echo -en "\x0a\x1c\xa0\xe3\xc1\x10\x81\xe3" > $(KDIR)/$(IMG_PREFIX)-wbd222-zImage
- cat $(KDIR)/zImage >> $(KDIR)/$(IMG_PREFIX)-wbd222-zImage
-endef
-
-define Image/BuildKernel
-# workaround the bootloader's bug with extra nops
- echo -en "\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1" > $(BIN_DIR)/$(IMG_PREFIX)-wbd111-zImage
- cat $(KDIR)/$(IMG_PREFIX)-wbd111-zImage >> $(BIN_DIR)/$(IMG_PREFIX)-wbd111-zImage
- echo -en "\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1" > $(BIN_DIR)/$(IMG_PREFIX)-wbd222-zImage
- cat $(KDIR)/$(IMG_PREFIX)-wbd222-zImage >> $(BIN_DIR)/$(IMG_PREFIX)-wbd222-zImage
-endef
-
-define Image/Build/jffs2-64k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=64k conv=sync
-endef
-
-define Image/Build/jffs2-128k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync
-endef
-
-define Image/Build
- $(call Image/Build/$(1),$(1))
-
- -$(STAGING_DIR_HOST)/bin/mkfwimage2 \
- -m GEOS -f 0x30000000 -z \
- -v WILI-S.WILIBOARD.v5.00.SL3512.OpenWrt.00000.000000.000000 \
- -o $(BIN_DIR)/$(IMG_PREFIX)-wbd111-$(1).bin \
- -p Kernel:0x020000:0x100000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-wbd111-zImage \
- -p Ramdisk:0x120000:0x500000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-$(1).img
-
- -$(STAGING_DIR_HOST)/bin/mkfwimage2 \
- -m GEOS -f 0x30000000 -z \
- -v WILI-S.WBD222.v5.00.SL3512.OpenWrt.00000.000000.000000 \
- -o $(BIN_DIR)/$(IMG_PREFIX)-wbd222-$(1).bin \
- -p Kernel:0x020000:0x100000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-wbd222-zImage \
- -p Ramdisk:0x120000:0x500000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-$(1).img
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -18,9 +18,9 @@ extern void gemini_map_io(void);
- extern void gemini_init_irq(void);
- extern void gemini_timer_init(void);
- extern void gemini_gpio_init(void);
--extern void platform_register_rtc(void);
-
- /* Common platform devices registration functions */
-+extern int platform_register_rtc(void);
- extern int platform_register_uart(void);
- extern int platform_register_pflash(unsigned int size,
- struct mtd_partition *parts,
---- a/arch/arm/mach-gemini/devices.c
-+++ b/arch/arm/mach-gemini/devices.c
-@@ -17,6 +17,7 @@
- #include <mach/irqs.h>
- #include <mach/hardware.h>
- #include <mach/global_reg.h>
-+#include "common.h"
-
- static struct plat_serial8250_port serial_platform_data[] = {
- {
+++ /dev/null
---- /dev/null
-+++ b/drivers/watchdog/gemini_wdt.c
-@@ -0,0 +1,378 @@
-+/*
-+ * Watchdog driver for Cortina Systems Gemini SoC
-+ *
-+ * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/fs.h>
-+#include <linux/uaccess.h>
-+#include <linux/miscdevice.h>
-+#include <linux/platform_device.h>
-+#include <linux/watchdog.h>
-+#include <linux/slab.h>
-+
-+#define GEMINI_WDCOUNTER 0x0
-+#define GEMINI_WDLOAD 0x4
-+#define GEMINI_WDRESTART 0x8
-+
-+#define WDRESTART_MAGIC 0x5AB9
-+
-+#define GEMINI_WDCR 0xC
-+
-+#define WDCR_CLOCK_5MHZ (1 << 4)
-+#define WDCR_SYS_RST (1 << 1)
-+#define WDCR_ENABLE (1 << 0)
-+
-+#define WDT_CLOCK 5000000 /* 5 MHz */
-+#define WDT_DEFAULT_TIMEOUT 13
-+#define WDT_MAX_TIMEOUT (0xFFFFFFFF / WDT_CLOCK)
-+
-+/* status bits */
-+#define WDT_ACTIVE 0
-+#define WDT_OK_TO_CLOSE 1
-+
-+static unsigned int timeout = WDT_DEFAULT_TIMEOUT;
-+static int nowayout = WATCHDOG_NOWAYOUT;
-+
-+static DEFINE_SPINLOCK(gemini_wdt_lock);
-+
-+static struct platform_device *gemini_wdt_dev;
-+
-+struct gemini_wdt_struct {
-+ struct resource *res;
-+ struct device *dev;
-+ void __iomem *base;
-+ unsigned long status;
-+};
-+
-+static struct watchdog_info gemini_wdt_info = {
-+ .identity = "Gemini watchdog",
-+ .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING |
-+ WDIOF_SETTIMEOUT,
-+};
-+
-+/* Disable the watchdog. */
-+static void gemini_wdt_stop(struct gemini_wdt_struct *gemini_wdt)
-+{
-+ spin_lock(&gemini_wdt_lock);
-+
-+ __raw_writel(0, gemini_wdt->base + GEMINI_WDCR);
-+
-+ clear_bit(WDT_ACTIVE, &gemini_wdt->status);
-+
-+ spin_unlock(&gemini_wdt_lock);
-+}
-+
-+/* Service the watchdog */
-+static void gemini_wdt_service(struct gemini_wdt_struct *gemini_wdt)
-+{
-+ __raw_writel(WDRESTART_MAGIC, gemini_wdt->base + GEMINI_WDRESTART);
-+}
-+
-+/* Enable and reset the watchdog. */
-+static void gemini_wdt_start(struct gemini_wdt_struct *gemini_wdt)
-+{
-+ spin_lock(&gemini_wdt_lock);
-+
-+ __raw_writel(timeout * WDT_CLOCK, gemini_wdt->base + GEMINI_WDLOAD);
-+
-+ gemini_wdt_service(gemini_wdt);
-+
-+ /* set clock before enabling */
-+ __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
-+ gemini_wdt->base + GEMINI_WDCR);
-+
-+ __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
-+ gemini_wdt->base + GEMINI_WDCR);
-+
-+ set_bit(WDT_ACTIVE, &gemini_wdt->status);
-+
-+ spin_unlock(&gemini_wdt_lock);
-+}
-+
-+/* Watchdog device is opened, and watchdog starts running. */
-+static int gemini_wdt_open(struct inode *inode, struct file *file)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(gemini_wdt_dev);
-+
-+ if (test_bit(WDT_ACTIVE, &gemini_wdt->status))
-+ return -EBUSY;
-+
-+ file->private_data = gemini_wdt;
-+
-+ gemini_wdt_start(gemini_wdt);
-+
-+ return nonseekable_open(inode, file);
-+}
-+
-+/* Close the watchdog device. */
-+static int gemini_wdt_close(struct inode *inode, struct file *file)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = file->private_data;
-+
-+ /* Disable the watchdog if possible */
-+ if (test_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status))
-+ gemini_wdt_stop(gemini_wdt);
-+ else
-+ dev_warn(gemini_wdt->dev, "Device closed unexpectedly - timer will not stop\n");
-+
-+ return 0;
-+}
-+
-+/* Handle commands from user-space. */
-+static long gemini_wdt_ioctl(struct file *file, unsigned int cmd,
-+ unsigned long arg)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = file->private_data;
-+
-+ int value;
-+
-+ switch (cmd) {
-+ case WDIOC_KEEPALIVE:
-+ gemini_wdt_service(gemini_wdt);
-+ return 0;
-+
-+ case WDIOC_GETSUPPORT:
-+ return copy_to_user((struct watchdog_info *)arg, &gemini_wdt_info,
-+ sizeof(gemini_wdt_info)) ? -EFAULT : 0;
-+
-+ case WDIOC_SETTIMEOUT:
-+ if (get_user(value, (int *)arg))
-+ return -EFAULT;
-+
-+ if ((value < 1) || (value > WDT_MAX_TIMEOUT))
-+ return -EINVAL;
-+
-+ timeout = value;
-+
-+ /* restart wdt to use new timeout */
-+ gemini_wdt_stop(gemini_wdt);
-+ gemini_wdt_start(gemini_wdt);
-+
-+ /* Fall through */
-+ case WDIOC_GETTIMEOUT:
-+ return put_user(timeout, (int *)arg);
-+
-+ case WDIOC_GETTIMELEFT:
-+ value = __raw_readl(gemini_wdt->base + GEMINI_WDCOUNTER);
-+ return put_user(value / WDT_CLOCK, (int *)arg);
-+
-+ default:
-+ return -ENOTTY;
-+ }
-+}
-+
-+/* Refresh the watchdog whenever device is written to. */
-+static ssize_t gemini_wdt_write(struct file *file, const char *data,
-+ size_t len, loff_t *ppos)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = file->private_data;
-+
-+ if (len) {
-+ if (!nowayout) {
-+ size_t i;
-+
-+ clear_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status);
-+ for (i = 0; i != len; i++) {
-+ char c;
-+
-+ if (get_user(c, data + i))
-+ return -EFAULT;
-+ if (c == 'V')
-+ set_bit(WDT_OK_TO_CLOSE,
-+ &gemini_wdt->status);
-+ }
-+ }
-+ gemini_wdt_service(gemini_wdt);
-+ }
-+
-+ return len;
-+}
-+
-+static const struct file_operations gemini_wdt_fops = {
-+ .owner = THIS_MODULE,
-+ .llseek = no_llseek,
-+ .unlocked_ioctl = gemini_wdt_ioctl,
-+ .open = gemini_wdt_open,
-+ .release = gemini_wdt_close,
-+ .write = gemini_wdt_write,
-+};
-+
-+static struct miscdevice gemini_wdt_miscdev = {
-+ .minor = WATCHDOG_MINOR,
-+ .name = "watchdog",
-+ .fops = &gemini_wdt_fops,
-+};
-+
-+static void gemini_wdt_shutdown(struct platform_device *pdev)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
-+
-+ gemini_wdt_stop(gemini_wdt);
-+}
-+
-+static int gemini_wdt_probe(struct platform_device *pdev)
-+{
-+ int ret;
-+ int res_size;
-+ struct resource *res;
-+ void __iomem *base;
-+ struct gemini_wdt_struct *gemini_wdt;
-+ unsigned int reg;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(&pdev->dev, "can't get device resources\n");
-+ return -ENODEV;
-+ }
-+
-+ res_size = resource_size(res);
-+ if (!request_mem_region(res->start, res_size, res->name)) {
-+ dev_err(&pdev->dev, "can't allocate %d bytes at %d address\n",
-+ res_size, res->start);
-+ return -ENOMEM;
-+ }
-+
-+ base = ioremap(res->start, res_size);
-+ if (!base) {
-+ dev_err(&pdev->dev, "ioremap failed\n");
-+ ret = -EIO;
-+ goto fail0;
-+ }
-+
-+ gemini_wdt = kzalloc(sizeof(struct gemini_wdt_struct), GFP_KERNEL);
-+ if (!gemini_wdt) {
-+ dev_err(&pdev->dev, "can't allocate interface\n");
-+ ret = -ENOMEM;
-+ goto fail1;
-+ }
-+
-+ /* Setup gemini_wdt driver structure */
-+ gemini_wdt->base = base;
-+ gemini_wdt->res = res;
-+
-+ /* Set up platform driver data */
-+ platform_set_drvdata(pdev, gemini_wdt);
-+ gemini_wdt_dev = pdev;
-+
-+ if (gemini_wdt_miscdev.parent) {
-+ ret = -EBUSY;
-+ goto fail2;
-+ }
-+
-+ gemini_wdt_miscdev.parent = &pdev->dev;
-+
-+ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
-+ if (reg & WDCR_ENABLE) {
-+ /* Watchdog was enabled by the bootloader, disable it. */
-+ reg &= ~(WDCR_ENABLE);
-+ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
-+ }
-+
-+ ret = misc_register(&gemini_wdt_miscdev);
-+ if (ret)
-+ goto fail2;
-+
-+ return 0;
-+
-+fail2:
-+ platform_set_drvdata(pdev, NULL);
-+ kfree(gemini_wdt);
-+fail1:
-+ iounmap(base);
-+fail0:
-+ release_mem_region(res->start, res_size);
-+
-+ return ret;
-+}
-+
-+static int gemini_wdt_remove(struct platform_device *pdev)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
-+
-+ platform_set_drvdata(pdev, NULL);
-+ misc_deregister(&gemini_wdt_miscdev);
-+ gemini_wdt_dev = NULL;
-+ iounmap(gemini_wdt->base);
-+ release_mem_region(gemini_wdt->res->start, resource_size(gemini_wdt->res));
-+
-+ kfree(gemini_wdt);
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_PM
-+static int gemini_wdt_suspend(struct platform_device *pdev, pm_message_t message)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
-+ unsigned int reg;
-+
-+ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
-+ reg &= ~(WDCR_WDENABLE);
-+ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
-+
-+ return 0;
-+}
-+
-+static int gemini_wdt_resume(struct platform_device *pdev)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
-+ unsigned int reg;
-+
-+ if (gemini_wdt->status) {
-+ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
-+ reg |= WDCR_WDENABLE;
-+ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
-+ }
-+
-+ return 0;
-+}
-+#else
-+#define gemini_wdt_suspend NULL
-+#define gemini_wdt_resume NULL
-+#endif
-+
-+static struct platform_driver gemini_wdt_driver = {
-+ .probe = gemini_wdt_probe,
-+ .remove = gemini_wdt_remove,
-+ .shutdown = gemini_wdt_shutdown,
-+ .suspend = gemini_wdt_suspend,
-+ .resume = gemini_wdt_resume,
-+ .driver = {
-+ .name = "gemini-wdt",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init gemini_wdt_init(void)
-+{
-+ return platform_driver_probe(&gemini_wdt_driver, gemini_wdt_probe);
-+}
-+
-+static void __exit gemini_wdt_exit(void)
-+{
-+ platform_driver_unregister(&gemini_wdt_driver);
-+}
-+
-+module_init(gemini_wdt_init);
-+module_exit(gemini_wdt_exit);
-+
-+module_param(timeout, uint, 0);
-+MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
-+
-+module_param(nowayout, int, 0);
-+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
-+
-+MODULE_AUTHOR("Paulius Zaleckas");
-+MODULE_DESCRIPTION("Watchdog driver for Gemini");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-+MODULE_ALIAS("platform:gemini-wdt");
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -154,6 +154,16 @@ config 977_WATCHDOG
-
- Not sure? It's safe to say N.
-
-+config GEMINI_WATCHDOG
-+ tristate "Gemini watchdog"
-+ depends on ARCH_GEMINI
-+ help
-+ Say Y here if to include support for the watchdog timer
-+ embedded in the Cortina Systems Gemini family of devices.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called gemini_wdt.
-+
- config IXP4XX_WATCHDOG
- tristate "IXP4xx Watchdog"
- depends on ARCH_IXP4XX
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -36,6 +36,7 @@ obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.
- obj-$(CONFIG_TWL4030_WATCHDOG) += twl4030_wdt.o
- obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
- obj-$(CONFIG_977_WATCHDOG) += wdt977.o
-+obj-$(CONFIG_GEMINI_WATCHDOG) += gemini_wdt.o
- obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
- obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
- obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
+++ /dev/null
---- a/arch/arm/mach-gemini/devices.c
-+++ b/arch/arm/mach-gemini/devices.c
-@@ -117,3 +117,20 @@ int __init platform_register_rtc(void)
- return platform_device_register(&gemini_rtc_device);
- }
-
-+static struct resource wdt_resource = {
-+ .start = GEMINI_WAQTCHDOG_BASE,
-+ .end = GEMINI_WAQTCHDOG_BASE + 0x18,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device wdt_device = {
-+ .name = "gemini-wdt",
-+ .id = 0,
-+ .resource = &wdt_resource,
-+ .num_resources = 1,
-+};
-+
-+int __init platform_register_watchdog(void)
-+{
-+ return platform_device_register(&wdt_device);
-+}
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -25,6 +25,7 @@ extern int platform_register_uart(void);
- extern int platform_register_pflash(unsigned int size,
- struct mtd_partition *parts,
- unsigned int nr_parts);
-+extern int platform_register_watchdog(void);
-
- extern void gemini_restart(char mode, const char *cmd);
-
+++ /dev/null
---- a/arch/arm/mach-gemini/board-nas4220b.c
-+++ b/arch/arm/mach-gemini/board-nas4220b.c
-@@ -95,6 +95,7 @@ static void __init ib4220b_init(void)
- platform_device_register(&ib4220b_led_device);
- platform_device_register(&ib4220b_key_device);
- platform_register_rtc();
-+ platform_register_watchdog();
- }
-
- MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
---- a/arch/arm/mach-gemini/board-wbd111.c
-+++ b/arch/arm/mach-gemini/board-wbd111.c
-@@ -122,6 +122,7 @@ static void __init wbd111_init(void)
- platform_device_register(&wbd111_leds_device);
- platform_device_register(&wbd111_keys_device);
- platform_register_rtc();
-+ platform_register_watchdog();
- }
-
- MACHINE_START(WBD111, "Wiliboard WBD-111")
---- a/arch/arm/mach-gemini/board-wbd222.c
-+++ b/arch/arm/mach-gemini/board-wbd222.c
-@@ -122,6 +122,7 @@ static void __init wbd222_init(void)
- platform_device_register(&wbd222_leds_device);
- platform_device_register(&wbd222_keys_device);
- platform_register_rtc();
-+ platform_register_watchdog();
- }
-
- MACHINE_START(WBD222, "Wiliboard WBD-222")
---- a/arch/arm/mach-gemini/board-rut1xx.c
-+++ b/arch/arm/mach-gemini/board-rut1xx.c
-@@ -80,6 +80,7 @@ static void __init rut1xx_init(void)
- platform_device_register(&rut1xx_leds);
- platform_device_register(&rut1xx_keys_device);
- platform_register_rtc();
-+ platform_register_watchdog();
- }
-
- MACHINE_START(RUT100, "Teltonika RUT100")
+++ /dev/null
---- /dev/null
-+++ b/arch/arm/mach-gemini/include/mach/gmac.h
-@@ -0,0 +1,21 @@
-+/*
-+ * Gemini GMAC specific defines
-+ *
-+ * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+#ifndef __MACH_GMAC_H__
-+#define __MACH_GMAC_H__
-+
-+#include <linux/phy.h>
-+
-+struct gemini_gmac_platform_data {
-+ char *bus_id[2]; /* NULL means that this port is not used */
-+ phy_interface_t interface[2];
-+};
-+
-+#endif /* __MACH_GMAC_H__ */
---- /dev/null
-+++ b/drivers/net/gemini_negmac/gm_gmac.c
-@@ -0,0 +1,1359 @@
-+/*
-+ * Ethernet device driver for Gemini SoC.
-+ *
-+ * Copyright (C) 2006, Storlink, Corp.
-+ * Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/mm.h>
-+#include <linux/compiler.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/init.h>
-+#include <linux/ioport.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/rtnetlink.h>
-+#include <linux/delay.h>
-+#include <linux/ethtool.h>
-+#include <linux/mii.h>
-+#include <linux/phy.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/completion.h>
-+#include <linux/kthread.h>
-+#include <linux/io.h>
-+#include <mach/hardware.h>
-+#include <linux/semaphore.h>
-+#include <mach/irqs.h>
-+#include <linux/skbuff.h>
-+#include <linux/in.h>
-+#include <linux/ip.h>
-+#include <linux/tcp.h>
-+#include <linux/udp.h>
-+#include <mach/gmac.h>
-+
-+#include "gm_gmac.h"
-+
-+/* #define GMAX_TX_INTR_DISABLED */
-+/* #define DO_HW_CHKSUM */
-+/* #define ENABLE_TSO */
-+#define GMAC_USE_TXQ0
-+/* #define GMAC_LEN_1_2_ISSUE */
-+
-+#define DEFAULT_RXQ_MAX_CNT 256
-+
-+/* define chip information */
-+#define DRV_VERSION "0.2"
-+#define SL351x_DRIVER_NAME "Gemini Ethernet driver " DRV_VERSION
-+
-+#ifdef GMAC_LEN_1_2_ISSUE
-+ #define _DEBUG_PREFETCH_NUM 256
-+static int _debug_prefetch_cnt;
-+static char _debug_prefetch_buf[_DEBUG_PREFETCH_NUM][4] __attribute__((aligned(4)));
-+#endif
-+
-+static inline void gmac_write_reg(void __iomem *base, unsigned int offset,
-+ unsigned int data, unsigned int bit_mask)
-+{
-+ unsigned int reg_val;
-+
-+ reg_val = (__raw_readl(base + offset) & (~bit_mask)) | (data & bit_mask);
-+ __raw_writel(reg_val, base + offset);
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_init_free_queue
-+* (1) Initialize the Free Queue Descriptor Base Address & size
-+* Register: TOE_GLOBAL_BASE + 0x0004
-+* (2) Initialize DMA Read/Write pointer for
-+* SW Free Queue and HW Free Queue
-+* (3) Initialize DMA Descriptors for
-+* SW Free Queue and HW Free Queue,
-+*----------------------------------------------------------------------*/
-+static void toe_init_free_queue(struct toe_private *toe)
-+{
-+ int i;
-+ DMA_RWPTR_T rwptr_reg;
-+ void *desc_buf;
-+ GMAC_RXDESC_T *sw_desc_ptr;
-+ struct sk_buff *skb;
-+
-+ desc_buf = dma_alloc_coherent(toe->dev, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
-+ &toe->sw_freeq_desc_base_dma, GFP_KERNEL);
-+ sw_desc_ptr = (GMAC_RXDESC_T *)desc_buf;
-+ if (!desc_buf) {
-+ dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
-+ return;
-+ }
-+ memset(desc_buf, 0, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
-+
-+ /* DMA Queue Base & Size */
-+ __raw_writel((toe->sw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_SW_FREEQ_DESC_POWER,
-+ toe->global_base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
-+
-+ /* init descriptor base */
-+ toe->swfq_desc_base = (unsigned int)desc_buf;
-+
-+ /* SW Free Queue Descriptors */
-+ for (i = 0; i < TOE_SW_FREEQ_DESC_NUM; i++) {
-+ sw_desc_ptr->word0.bits.buffer_size = SW_RX_BUF_SIZE;
-+ skb = dev_alloc_skb(SW_RX_BUF_SIZE); /* allocate socket buffer */
-+ if (!skb) {
-+ dev_err(toe->dev, "%s::skb buffer allocation fail\n", __func__);
-+ return;
-+ }
-+ REG32(skb->data) = (unsigned int)skb;
-+ skb_reserve(skb, SKB_RESERVE_BYTES);
-+ sw_desc_ptr->word2.buf_adr = dma_map_single(toe->dev, skb->data,
-+ SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
-+ DMA_FROM_DEVICE);
-+ sw_desc_ptr++;
-+ }
-+
-+ dma_sync_single_for_device(toe->dev, toe->sw_freeq_desc_base_dma,
-+ TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
-+ DMA_TO_DEVICE);
-+
-+ /* SW Free Queue Read/Write Pointer */
-+ rwptr_reg.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
-+ rwptr_reg.bits.rptr = 0;
-+ __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
-+
-+ /* DMA Queue Base & Size */
-+ __raw_writel(TOE_HW_FREEQ_DESC_POWER,
-+ toe->global_base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
-+ rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
-+ rwptr_reg.bits.rptr = 0;
-+ __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_HWFQ_RWPTR_REG);
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_init_swtx_queue
-+* (2) Initialize the GMAC 0/1 SW TXQ Queue Descriptor Base Address & sizeup
-+* GMAC_SW_TX_QUEUE_BASE_REG(0x0050)
-+* (2) Initialize DMA Read/Write pointer for
-+* GMAC 0/1 SW TX Q0-5
-+*----------------------------------------------------------------------*/
-+static void toe_init_swtx_queue(struct net_device *dev)
-+{
-+ int i;
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ DMA_RWPTR_T rwptr_reg;
-+ void __iomem *rwptr_addr;
-+ void *desc_buf;
-+ unsigned int offset;
-+
-+ desc_buf = dma_alloc_coherent(toe->dev, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
-+ &gmac->swtxq_desc_base_dma, GFP_KERNEL);
-+ gmac->swtxq_desc_base = (unsigned int)desc_buf;
-+ if (!desc_buf) {
-+ dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
-+ return;
-+ }
-+ memset(desc_buf, 0, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
-+ dma_sync_single_for_device(toe->dev, gmac->swtxq_desc_base_dma,
-+ TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
-+ DMA_TO_DEVICE);
-+ __raw_writel((gmac->swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC_SWTXQ_DESC_POWER,
-+ gmac->dma_base_addr + GMAC_SW_TX_QUEUE_BASE_REG);
-+
-+ /* GMAC0 SW TX Q0-Q5 */
-+ offset = 0;
-+ rwptr_reg.bits.wptr = 0;
-+ rwptr_reg.bits.rptr = 0;
-+ rwptr_addr = gmac->dma_base_addr + GMAC_SW_TX_QUEUE0_PTR_REG;
-+ for (i = 0; i < TOE_SW_TXQ_NUM; i++) {
-+ gmac->swtxq[i].rwptr_reg = rwptr_addr;
-+ gmac->swtxq[i].desc_base_dma = (unsigned int)gmac->swtxq_desc_base_dma + offset;
-+ gmac->swtxq[i].desc_base = (unsigned int)desc_buf + offset;
-+ offset += TOE_GMAC_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
-+ __raw_writel(rwptr_reg.bits32, rwptr_addr);
-+ rwptr_addr += 4;
-+ }
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_init_default_queue
-+* (1) Initialize the default 0/1 Queue Header
-+* Register: TOE_DEFAULT_Q0_HDR_BASE (0x60002000)
-+* TOE_DEFAULT_Q1_HDR_BASE (0x60002008)
-+* (2) Initialize Descriptors of Default Queue 0/1
-+*----------------------------------------------------------------------*/
-+static void toe_init_default_queue(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ volatile NONTOE_QHDR_T *qhdr;
-+ GMAC_RXDESC_T *desc_ptr;
-+
-+ desc_ptr = dma_alloc_coherent(toe->dev, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
-+ &gmac->default_desc_base_dma, GFP_KERNEL);
-+ if (!desc_ptr) {
-+ dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
-+ return;
-+ }
-+ memset(desc_ptr, 0, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T));
-+ dma_sync_single_for_device(toe->dev, gmac->default_desc_base_dma,
-+ TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
-+ DMA_TO_DEVICE);
-+ gmac->default_desc_base = (unsigned int)desc_ptr;
-+ qhdr = (volatile NONTOE_QHDR_T *)(toe->global_base + TOE_DEFAULT_Q_HDR_BASE(gmac->port_id));
-+ qhdr->word0.base_size = ((unsigned int)gmac->default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q_DESC_POWER;
-+ qhdr->word1.bits32 = 0;
-+ gmac->default_qhdr = (NONTOE_QHDR_T *)qhdr;
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_init_interrupt_config
-+* Interrupt Select Registers are used to map interrupt to int0 or int1
-+* Int0 and int1 are wired to CPU 0/1 GMAC 0/1
-+* Interrupt Device Inteface data are used to pass device info to
-+* upper device driver or store status/statistics
-+* ISR handler
-+* (1) If status bit ON but masked, the prinf error message (bug issue)
-+* (2) If select bits are for me, handle it, else skip to let
-+* the other ISR handles it.
-+* Notes:
-+* GMACx init routine (for eCOS) or open routine (for Linux)
-+* enable the interrupt bits only which are selected for it.
-+*
-+* Default Setting:
-+* GMAC0 intr bits ------> int0 ----> eth0
-+* GMAC1 intr bits ------> int1 ----> eth1
-+* TOE intr -------------> int0 ----> eth0
-+* Classification Intr --> int0 ----> eth0
-+* Default Q0 -----------> int0 ----> eth0
-+* Default Q1 -----------> int1 ----> eth1
-+*----------------------------------------------------------------------*/
-+static void toe_init_interrupt_config(struct toe_private *toe)
-+{
-+ /* clear all status bits */
-+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
-+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
-+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
-+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
-+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
-+
-+ /* Init select registers */
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
-+
-+ /* disable all interrupt */
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_0_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_2_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_3_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+}
-+
-+static void toe_gmac_hw_start(struct gmac_private *gmac)
-+{
-+ GMAC_DMA_CTRL_T dma_ctrl;
-+
-+ /* program dma control register */
-+ dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
-+ dma_ctrl.bits.rd_enable = 1;
-+ dma_ctrl.bits.td_enable = 1;
-+ dma_ctrl.bits.loopback = 0;
-+ dma_ctrl.bits.drop_small_ack = 0;
-+ dma_ctrl.bits.rd_prot = 0;
-+ dma_ctrl.bits.rd_burst_size = 3;
-+ dma_ctrl.bits.rd_insert_bytes = RX_INSERT_BYTES;
-+ dma_ctrl.bits.rd_bus = 3;
-+ dma_ctrl.bits.td_prot = 0;
-+ dma_ctrl.bits.td_burst_size = 3;
-+ dma_ctrl.bits.td_bus = 3;
-+
-+ __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
-+}
-+
-+static void toe_gmac_hw_stop(struct gmac_private *gmac)
-+{
-+ GMAC_DMA_CTRL_T dma_ctrl;
-+
-+ /* program dma control register */
-+ dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
-+ dma_ctrl.bits.rd_enable = 0;
-+ dma_ctrl.bits.td_enable = 0;
-+ __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
-+}
-+
-+static void toe_gmac_init_chip(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ GMAC_CONFIG2_T config2_val;
-+ GMAC_CONFIG0_T config0;
-+ GMAC_CONFIG1_T config1;
-+ GMAC_STATUS_T status;
-+ GMAC_TX_WCR0_T hw_weigh;
-+ GMAC_TX_WCR1_T sw_weigh;
-+ GMAC_RX_FLTR_T rx_filter;
-+
-+ /* set RX_FLTR register to receive all multicast packet */
-+ rx_filter.bits32 = __raw_readl(gmac->base_addr + GMAC_RX_FLTR);
-+ rx_filter.bits.unicast = 1;
-+ rx_filter.bits.multicast = 1;
-+ rx_filter.bits.broadcast = 1;
-+ __raw_writel(rx_filter.bits32, gmac->base_addr + GMAC_RX_FLTR);
-+
-+ /* set flow control threshold */
-+ config1.bits32 = 0;
-+ config1.bits.set_threshold = 32 / 2;
-+ config1.bits.rel_threshold = 32 / 4 * 3;
-+ __raw_writel(config1.bits32, gmac->base_addr + GMAC_CONFIG1);
-+
-+ /* set flow control threshold */
-+ config2_val.bits32 = 0;
-+ config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM / 4;
-+ config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM / 2;
-+ __raw_writel(config2_val.bits32, gmac->base_addr + GMAC_CONFIG2);
-+
-+ /* disable TX/RX and disable internal loop back */
-+ config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
-+
-+ config0.bits.max_len = 2;
-+
-+ gmac->flow_control_enable = 0;
-+
-+ config0.bits.tx_fc_en = 0; /* disable tx flow control */
-+ config0.bits.rx_fc_en = 0; /* disable rx flow control */
-+ config0.bits.dis_rx = 1; /* disable rx */
-+ config0.bits.dis_tx = 1; /* disable tx */
-+ config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
-+ config0.bits.rx_err_detect = 1;
-+ config0.bits.rgmii_en = 0;
-+ config0.bits.rgmm_edge = 1;
-+ config0.bits.rxc_inv = 0;
-+ config0.bits.ipv4_rx_chksum = 1; /* enable H/W to check ip checksum */
-+ config0.bits.ipv6_rx_chksum = 1; /* enable H/W to check ip checksum */
-+ config0.bits.port0_chk_hwq = 1;
-+ config0.bits.port1_chk_hwq = 1;
-+ config0.bits.port0_chk_toeq = 1;
-+ config0.bits.port1_chk_toeq = 1;
-+ config0.bits.port0_chk_classq = 1;
-+ config0.bits.port1_chk_classq = 1;
-+
-+ __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
-+
-+ hw_weigh.bits32 = 0;
-+ hw_weigh.bits.hw_tq3 = 1;
-+ hw_weigh.bits.hw_tq2 = 1;
-+ hw_weigh.bits.hw_tq1 = 1;
-+ hw_weigh.bits.hw_tq0 = 1;
-+ __raw_writel(hw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_0_REG);
-+
-+ sw_weigh.bits32 = 0;
-+ sw_weigh.bits.sw_tq5 = 1;
-+ sw_weigh.bits.sw_tq4 = 1;
-+ sw_weigh.bits.sw_tq3 = 1;
-+ sw_weigh.bits.sw_tq2 = 1;
-+ sw_weigh.bits.sw_tq1 = 1;
-+ sw_weigh.bits.sw_tq0 = 1;
-+ __raw_writel(sw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_1_REG);
-+
-+ /* set interface type */
-+ status.bits32 = __raw_readl(gmac->base_addr + GMAC_STATUS);
-+
-+ switch (gmac->phydev->interface) {
-+ case PHY_INTERFACE_MODE_MII:
-+ status.bits.mii_rmii = GMAC_PHY_MII;
-+ break;
-+ case PHY_INTERFACE_MODE_GMII:
-+ status.bits.mii_rmii = GMAC_PHY_GMII;
-+ break;
-+ case PHY_INTERFACE_MODE_RGMII:
-+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
-+ break;
-+ default:
-+ dev_err(&dev->dev, "Unsupported MII interface\n");
-+ return;
-+ }
-+
-+ __raw_writel(status.bits32, gmac->base_addr + GMAC_STATUS);
-+}
-+
-+static void toe_init_gmac(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ u32 data;
-+
-+ /* GMAC initialization */
-+ toe_gmac_init_chip(dev);
-+
-+ /* -----------------------------------------------------------
-+ Enable GMAC interrupt & disable loopback
-+ Notes:
-+ GMACx init routine (for eCOS) or open routine (for Linux)
-+ enable the interrupt bits only which are selected for him.
-+ --------------------------------------------------------------*/
-+
-+ /* Enable Interrupt Bits */
-+ if (gmac->port_id == 0) {
-+ gmac->intr0_selected = GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT |
-+ GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT |
-+ GMAC0_SWTQ05_FIN_INT_BIT | GMAC0_SWTQ05_EOF_INT_BIT |
-+ GMAC0_SWTQ04_FIN_INT_BIT | GMAC0_SWTQ04_EOF_INT_BIT |
-+ GMAC0_SWTQ03_FIN_INT_BIT | GMAC0_SWTQ03_EOF_INT_BIT |
-+ GMAC0_SWTQ02_FIN_INT_BIT | GMAC0_SWTQ02_EOF_INT_BIT |
-+ GMAC0_SWTQ01_FIN_INT_BIT | GMAC0_SWTQ01_EOF_INT_BIT |
-+ GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
-+
-+#ifdef GMAX_TX_INTR_DISABLED
-+ gmac->intr0_enabled = 0;
-+#else
-+ gmac->intr0_enabled = GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
-+#endif
-+
-+ gmac->intr1_selected = TOE_IQ_ALL_BITS | TOE_CLASS_RX_INT_BITS |
-+ GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
-+ GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT |
-+ DEFAULT_Q0_INT_BIT;
-+ gmac->intr1_enabled = DEFAULT_Q0_INT_BIT | TOE_IQ_ALL_BITS;
-+ gmac->intr2_selected = 0xffffffff; /* TOE Queue 32-63 FUUL Intr */
-+ gmac->intr2_enabled = 0xffffffff;
-+ gmac->intr3_selected = 0xffffffff; /* TOE Queue 0-31 FUUL Intr */
-+ gmac->intr3_enabled = 0xffffffff;
-+ gmac->intr4_selected = GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
-+ HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
-+ gmac->intr4_enabled = GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
-+
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) & ~gmac->intr0_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) & ~gmac->intr1_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) & ~gmac->intr2_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) & ~gmac->intr3_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) & ~gmac->intr4_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
-+ } else {
-+ gmac->intr0_selected = GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT |
-+ GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT |
-+ GMAC1_SWTQ15_FIN_INT_BIT | GMAC1_SWTQ15_EOF_INT_BIT |
-+ GMAC1_SWTQ14_FIN_INT_BIT | GMAC1_SWTQ14_EOF_INT_BIT |
-+ GMAC1_SWTQ13_FIN_INT_BIT | GMAC1_SWTQ13_EOF_INT_BIT |
-+ GMAC1_SWTQ12_FIN_INT_BIT | GMAC1_SWTQ12_EOF_INT_BIT |
-+ GMAC1_SWTQ11_FIN_INT_BIT | GMAC1_SWTQ11_EOF_INT_BIT |
-+ GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
-+#ifdef GMAX_TX_INTR_DISABLED
-+ gmac->intr0_enabled = 0;
-+#else
-+ gmac->intr0_enabled = GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
-+#endif
-+
-+ gmac->intr1_selected = DEFAULT_Q1_INT_BIT;
-+ gmac->intr1_enabled = DEFAULT_Q1_INT_BIT | TOE_IQ_ALL_BITS;
-+ gmac->intr2_selected = 0; /* TOE Queue 32-63 FUUL Intr */
-+ gmac->intr2_enabled = 0;
-+ gmac->intr3_selected = 0; /* TOE Queue 0-31 FUUL Intr */
-+ gmac->intr3_enabled = 0;
-+ gmac->intr4_selected = GMAC1_INT_BITS;
-+ gmac->intr4_enabled = GMAC1_INT_BITS;
-+
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) | gmac->intr0_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) | gmac->intr1_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) | gmac->intr2_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) | gmac->intr3_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) | gmac->intr4_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
-+ }
-+
-+ /* enable only selected bits */
-+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_0_REG,
-+ gmac->intr0_enabled, gmac->intr0_selected);
-+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_1_REG,
-+ gmac->intr1_enabled, gmac->intr1_selected);
-+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_2_REG,
-+ gmac->intr2_enabled, gmac->intr2_selected);
-+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_3_REG,
-+ gmac->intr3_enabled, gmac->intr3_selected);
-+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_4_REG,
-+ gmac->intr4_enabled, gmac->intr4_selected);
-+
-+ /* start DMA process */
-+ toe_gmac_hw_start(gmac);
-+}
-+
-+static void toe_gmac_enable_tx_rx(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ GMAC_CONFIG0_T config0;
-+
-+ /* enable TX/RX */
-+ config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
-+ config0.bits.dis_rx = 0; /* enable rx */
-+ config0.bits.dis_tx = 0; /* enable tx */
-+ __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
-+}
-+
-+static void toe_gmac_disable_tx_rx(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ GMAC_CONFIG0_T config0;
-+
-+ /* enable TX/RX */
-+ config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
-+ config0.bits.dis_rx = 1; /* disable rx */
-+ config0.bits.dis_tx = 1; /* disable tx */
-+ __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
-+}
-+
-+static void toe_gmac_tx_complete(struct net_device *dev, unsigned int tx_qid)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ GMAC_TXDESC_T *curr_desc;
-+ GMAC_TXDESC_0_T word0;
-+ GMAC_TXDESC_1_T word1;
-+ unsigned int desc_count;
-+ GMAC_SWTXQ_T *swtxq;
-+ DMA_RWPTR_T rwptr;
-+
-+ /* get tx H/W completed descriptor virtual address */
-+ /* check tx status and accumulate tx statistics */
-+ swtxq = &gmac->swtxq[tx_qid];
-+ for (;;) {
-+ rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
-+ if (rwptr.bits.rptr == swtxq->finished_idx)
-+ break;
-+ curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
-+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
-+ swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
-+ sizeof(GMAC_TXDESC_T),
-+ DMA_FROM_DEVICE);
-+ word0.bits32 = curr_desc->word0.bits32;
-+ word1.bits32 = curr_desc->word1.bits32;
-+
-+ if (word0.bits.status_tx_ok) {
-+ dev->stats.tx_bytes += word1.bits.byte_count;
-+ desc_count = word0.bits.desc_count;
-+ if (desc_count == 0) {
-+ dev_err(&dev->dev, "%s::Desc 0x%x = 0x%x, desc_count=%d\n", __func__, (u32)curr_desc, word0.bits32, desc_count);
-+ BUG();
-+ }
-+ while (--desc_count) {
-+ word0.bits.status_tx_ok = 0;
-+ curr_desc->word0.bits32 = word0.bits32;
-+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
-+ swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
-+ sizeof(GMAC_TXDESC_T),
-+ DMA_TO_DEVICE);
-+ swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
-+ curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
-+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
-+ swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
-+ sizeof(GMAC_TXDESC_T),
-+ DMA_FROM_DEVICE);
-+ word0.bits32 = curr_desc->word0.bits32;
-+ }
-+
-+ word0.bits.status_tx_ok = 0;
-+ dev_kfree_skb_any(swtxq->tx_skb[swtxq->finished_idx]);
-+ swtxq->tx_skb[swtxq->finished_idx] = NULL;
-+
-+ curr_desc->word0.bits32 = word0.bits32;
-+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
-+ swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
-+ sizeof(GMAC_TXDESC_T),
-+ DMA_TO_DEVICE);
-+ dev->stats.tx_packets++;
-+ swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
-+ } else {
-+ break;
-+ }
-+ }
-+
-+ if (netif_queue_stopped(dev))
-+ netif_wake_queue(dev);
-+}
-+
-+static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ DMA_RWPTR_T rwptr;
-+ GMAC_TXDESC_T *curr_desc;
-+ int snd_pages = skb_shinfo(skb)->nr_frags + 1; /* get number of descriptor */
-+ int frag_id = 0;
-+ int len, total_len = skb->len;
-+ struct net_device_stats *isPtr = &dev->stats;
-+ unsigned int free_desc;
-+ GMAC_SWTXQ_T *swtxq;
-+ register unsigned long word0, word1, word2, word3;
-+ unsigned short wptr, rptr;
-+
-+#ifdef GMAC_LEN_1_2_ISSUE
-+ int total_pages;
-+ total_pages = snd_pages;
-+#endif
-+
-+ if (skb->len >= 0x10000) {
-+ isPtr->tx_dropped++;
-+ dev_err(&dev->dev, "%s::skb->len %d >= 64K\n", __func__, skb->len);
-+ netif_stop_queue(dev);
-+ return 1;
-+ }
-+
-+#ifdef GMAC_USE_TXQ0
-+ #define tx_qid 0
-+#endif
-+
-+ swtxq = &gmac->swtxq[tx_qid];
-+
-+ rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
-+ wptr = rwptr.bits.wptr;
-+ rptr = rwptr.bits.rptr;
-+
-+ /*
-+ * check finished desc or empty BD
-+ * cannot check by read ptr of RW PTR register,
-+ * because the HW complete to send but the SW may NOT handle it
-+ */
-+#ifdef GMAX_TX_INTR_DISABLED
-+ toe_gmac_tx_complete(dev, tx_qid);
-+#endif
-+ if (wptr >= swtxq->finished_idx)
-+ free_desc = TOE_GMAC_SWTXQ_DESC_NUM - wptr + swtxq->finished_idx;
-+ else
-+ free_desc = swtxq->finished_idx - wptr;
-+
-+ if (free_desc < snd_pages) {
-+ isPtr->tx_dropped++;
-+ netif_stop_queue(dev);
-+ return 1;
-+ }
-+
-+ while (snd_pages) {
-+ dma_addr_t pkt_datap;
-+
-+ curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + wptr;
-+ if (frag_id == 0) {
-+ len = skb_headlen(skb);
-+ pkt_datap = dma_map_single(toe->dev, skb->data, len, DMA_TO_DEVICE);
-+ } else {
-+ skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_id - 1];
-+ len = frag->size;
-+ pkt_datap = dma_map_page(toe->dev, frag->page.p, frag->page_offset, len, DMA_TO_DEVICE);
-+ }
-+
-+ /* set TX descriptor */
-+ word0 = len;
-+ word3 = (dev->mtu + 14) | EOFIE_BIT;
-+
-+#ifdef DO_HW_CHKSUM
-+ if (total_len <= 1514 && ip_hdr(skb) && (ip_hdr(skb)->frag_off & __constant_htons(0x3fff)))
-+ word1 = total_len |
-+ TSS_IP_CHKSUM_BIT |
-+ TSS_IPV6_ENABLE_BIT |
-+ TSS_MTU_ENABLE_BIT;
-+ else
-+ word1 = total_len |
-+ TSS_UDP_CHKSUM_BIT |
-+ TSS_TCP_CHKSUM_BIT |
-+ TSS_IP_CHKSUM_BIT |
-+ TSS_IPV6_ENABLE_BIT |
-+ TSS_MTU_ENABLE_BIT;
-+#else
-+ word1 = total_len | TSS_MTU_ENABLE_BIT;
-+#endif
-+ word2 = (unsigned long)pkt_datap;
-+
-+ if (frag_id == 0)
-+ word3 |= SOF_BIT;
-+
-+ if (snd_pages == 1) {
-+ word3 |= EOF_BIT;
-+ swtxq->tx_skb[wptr] = skb;
-+ } else
-+ swtxq->tx_skb[wptr] = NULL;
-+
-+#ifdef GMAC_LEN_1_2_ISSUE
-+ if ((total_pages != snd_pages) && (len == 1 || len == 2) && ((u32)pkt_datap & 0x03)) {
-+ memcpy((void *)&_debug_prefetch_buf[_debug_prefetch_cnt][0], pkt_datap, len);
-+ pkt_datap = (char *)&_debug_prefetch_buf[_debug_prefetch_cnt][0];
-+ word2 = (unsigned long)__pa(pkt_datap);
-+ _debug_prefetch_cnt++;
-+ if (_debug_prefetch_cnt >= _DEBUG_PREFETCH_NUM)
-+ _debug_prefetch_cnt = 0;
-+ }
-+#endif
-+ curr_desc->word0.bits32 = word0;
-+ curr_desc->word1.bits32 = word1;
-+ curr_desc->word2.bits32 = word2;
-+ curr_desc->word3.bits32 = word3;
-+ free_desc--;
-+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
-+ wptr * sizeof(GMAC_TXDESC_T),
-+ sizeof(GMAC_TXDESC_T),
-+ DMA_TO_DEVICE);
-+ wptr = RWPTR_ADVANCE_ONE(wptr, TOE_GMAC_SWTXQ_DESC_NUM);
-+ frag_id++;
-+ snd_pages--;
-+ }
-+
-+ SET_WPTR(swtxq->rwptr_reg, wptr);
-+ dev->trans_start = jiffies;
-+
-+ return 0;
-+}
-+
-+static void __gmac_set_mac_address(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ unsigned int reg_val;
-+
-+ reg_val = dev->dev_addr[0] + (dev->dev_addr[1] << 8) +
-+ (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
-+ __raw_writel(reg_val, gmac->base_addr + GMAC_STA_ADD0);
-+ reg_val = (__raw_readl(gmac->base_addr + GMAC_STA_ADD1) & 0xFFFF0000) +
-+ dev->dev_addr[4] + (dev->dev_addr[5] << 8);
-+ __raw_writel(reg_val, gmac->base_addr + GMAC_STA_ADD1);
-+}
-+
-+static int gmac_set_mac_address(struct net_device *dev, void *addr)
-+{
-+ struct sockaddr *sa = addr;
-+
-+ memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
-+
-+ __gmac_set_mac_address(dev);
-+
-+ return 0;
-+}
-+
-+static void gmac_get_mac_address(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ unsigned int reg_val;
-+
-+ reg_val = __raw_readl(gmac->base_addr + GMAC_STA_ADD0);
-+ dev->dev_addr[0] = reg_val & 0xFF;
-+ dev->dev_addr[1] = (reg_val >> 8) & 0xFF;
-+ dev->dev_addr[2] = (reg_val >> 16) & 0xFF;
-+ dev->dev_addr[3] = (reg_val >> 24) & 0xFF;
-+ reg_val = __raw_readl(gmac->base_addr + GMAC_STA_ADD1);
-+ dev->dev_addr[4] = reg_val & 0xFF;
-+ dev->dev_addr[5] = (reg_val >> 8) & 0xFF;
-+
-+ if (!is_valid_ether_addr(dev->dev_addr)) {
-+ random_ether_addr(dev->dev_addr);
-+ __gmac_set_mac_address(dev);
-+ }
-+}
-+
-+struct net_device_stats *gmac_get_stats(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+
-+ if (netif_running(dev)) {
-+ unsigned short multicast;
-+
-+ multicast = __raw_readw(gmac->base_addr + GMAC_IN_MCAST) +
-+ __raw_readw(gmac->base_addr + GMAC_IN_BCAST);
-+
-+ dev->stats.rx_dropped += __raw_readw(gmac->base_addr + GMAC_IN_DISCARDS);
-+ dev->stats.rx_errors += __raw_readw(gmac->base_addr + GMAC_IN_ERRORS);
-+ dev->stats.rx_packets += __raw_readl(gmac->base_addr + GMAC_IN_MAC1) + multicast;
-+ dev->stats.multicast += multicast;
-+ }
-+
-+ return &dev->stats;
-+}
-+
-+/* TODO: If possible use crc32 from kernel lib */
-+static unsigned const ethernet_polynomial = 0x04c11db7U;
-+static unsigned int ether_crc(int length, unsigned char *data)
-+{
-+ int crc = -1;
-+ unsigned int i;
-+ unsigned int crc_val = 0;
-+
-+ while (--length >= 0) {
-+ unsigned char current_octet = *data++;
-+ int bit;
-+ for (bit = 0; bit < 8; bit++, current_octet >>= 1)
-+ crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
-+ ethernet_polynomial : 0);
-+ }
-+ crc = ~crc;
-+ for (i = 0; i < 32; i++)
-+ crc_val = crc_val + (((crc << i) & 0x80000000) >> (31 - i));
-+
-+ return crc_val;
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_gmac_fill_free_q
-+* allocate buffers for free queue.
-+*----------------------------------------------------------------------*/
-+static void toe_gmac_fill_free_q(struct toe_private *toe)
-+{
-+ struct sk_buff *skb;
-+ DMA_RWPTR_T fq_rwptr;
-+ GMAC_RXDESC_T *fq_desc;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&toe->freeq_lock, flags);
-+ fq_rwptr.bits32 = __raw_readl(toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
-+ while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
-+ TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
-+ skb = dev_alloc_skb(SW_RX_BUF_SIZE);
-+ if (skb == NULL) {
-+ dev_err(toe->dev, "%s::skb allocation fail\n", __func__);
-+ break;
-+ }
-+ REG32(skb->data) = (unsigned int)skb;
-+ skb_reserve(skb, SKB_RESERVE_BYTES);
-+ fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
-+ TOE_SW_FREEQ_DESC_NUM);
-+ fq_desc = (GMAC_RXDESC_T *)toe->swfq_desc_base + fq_rwptr.bits.wptr;
-+ fq_desc->word2.buf_adr = dma_map_single(toe->dev, skb->data,
-+ SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
-+ DMA_FROM_DEVICE);
-+ dma_sync_single_range_for_device(toe->dev,
-+ toe->sw_freeq_desc_base_dma,
-+ fq_rwptr.bits.wptr * sizeof(GMAC_RXDESC_T),
-+ sizeof(GMAC_RXDESC_T),
-+ DMA_TO_DEVICE);
-+ SET_WPTR(toe->global_base + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
-+ }
-+ spin_unlock_irqrestore(&toe->freeq_lock, flags);
-+}
-+
-+static void fill_free_q_worker(struct work_struct *work)
-+{
-+ struct toe_private *toe = container_of(work, struct toe_private, freq_work);
-+
-+ toe_gmac_fill_free_q(toe);
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_gmac_handle_default_rxq
-+* (1) Get rx Buffer for default Rx queue
-+* (2) notify or call upper-routine to handle it
-+* (3) get a new buffer and insert it into SW free queue
-+* (4) Note: The SW free queue Read-Write Pointer should be locked when accessing
-+*----------------------------------------------------------------------*/
-+static void toe_gmac_handle_default_rxq(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ GMAC_RXDESC_T *curr_desc;
-+ struct sk_buff *skb;
-+ DMA_RWPTR_T rwptr;
-+ unsigned int pkt_size;
-+ int max_cnt;
-+ unsigned int desc_count;
-+ unsigned int chksum_status, rx_status;
-+ struct net_device_stats *isPtr = &dev->stats;
-+
-+ rwptr.bits32 = __raw_readl(&gmac->default_qhdr->word1);
-+ max_cnt = DEFAULT_RXQ_MAX_CNT;
-+ while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr) {
-+ curr_desc = (GMAC_RXDESC_T *)gmac->default_desc_base + rwptr.bits.rptr;
-+ dma_sync_single_range_for_device(toe->dev,
-+ gmac->default_desc_base_dma,
-+ rwptr.bits.rptr * sizeof(GMAC_RXDESC_T),
-+ sizeof(GMAC_RXDESC_T),
-+ DMA_FROM_DEVICE);
-+ rx_status = curr_desc->word0.bits.status;
-+ chksum_status = curr_desc->word0.bits.chksum_status;
-+ pkt_size = curr_desc->word1.bits.byte_count; /* total byte count in a frame */
-+ desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
-+ skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
-+
-+ if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
-+ || (pkt_size < 60) || (chksum_status & 0x4) || rx_status) {
-+ if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
-+ dev_err(&dev->dev, "%s::derr\n", __func__);
-+ if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
-+ dev_err(&dev->dev, "%s::perr\n", __func__);
-+ if (rx_status && (rx_status == 4 || rx_status == 7))
-+ isPtr->rx_crc_errors++;
-+
-+ dev_kfree_skb_irq(skb);
-+ goto bad_frame;
-+ }
-+
-+ if (curr_desc->word0.bits.drop)
-+ dev_warn(&dev->dev, "%s::Drop\n", __func__);
-+
-+ /* get frame information from the first descriptor of the frame */
-+ skb_reserve(skb, RX_INSERT_BYTES); /* 16 byte align the IP fields. */
-+ skb_put(skb, pkt_size);
-+ skb->dev = dev;
-+ skb->protocol = eth_type_trans(skb, dev);
-+ if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK || chksum_status == RX_CHKSUM_IP_OK_ONLY)
-+ skb->ip_summed = CHECKSUM_UNNECESSARY;
-+
-+ netif_rx(skb); /* socket rx */
-+ dev->last_rx = jiffies;
-+
-+ isPtr->rx_bytes += pkt_size;
-+
-+bad_frame:
-+ /* advance one for Rx default Q 0/1 */
-+ rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, TOE_DEFAULT_Q_DESC_NUM);
-+ SET_RPTR(&gmac->default_qhdr->word1, rwptr.bits.rptr);
-+ }
-+
-+ schedule_work(&toe->freq_work);
-+}
-+
-+static irqreturn_t toe_gmac_interrupt(int irq, void *dev_instance)
-+{
-+ struct net_device *dev = dev_instance;
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ unsigned int status0;
-+ unsigned int status1;
-+ unsigned int status2;
-+ unsigned int status3;
-+ unsigned int status4;
-+ int handled = 0;
-+
-+ /* read Interrupt status */
-+ status0 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
-+ status1 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
-+ status2 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
-+ status3 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
-+ status4 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
-+
-+ /* clear interrupts */
-+ if (status0)
-+ __raw_writel(status0, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
-+ if (status1)
-+ __raw_writel(status1, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
-+ if (status2)
-+ __raw_writel(status2, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
-+ if (status3)
-+ __raw_writel(status3, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
-+ if (status4)
-+ __raw_writel(status4, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
-+
-+ /* handle freeq interrupt first */
-+ if (status4 & gmac->intr4_enabled) {
-+ if ((status4 & SWFQ_EMPTY_INT_BIT) && (gmac->intr4_enabled & SWFQ_EMPTY_INT_BIT)) {
-+ toe_gmac_fill_free_q(toe);
-+ handled = 1;
-+ }
-+ }
-+
-+ /* Interrupt Status 1 */
-+ if (status1 & gmac->intr1_enabled) {
-+ /*
-+ * Handle GMAC 0/1 HW Tx queue 0-3 EOF events
-+ * Only count
-+ * TOE, Classification, and default queues interrupts are handled by ISR
-+ * because they should pass packets to upper layer
-+ */
-+ if (gmac->port_id == 0) {
-+ if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q0_INT_BIT)) {
-+ toe_gmac_handle_default_rxq(dev);
-+ handled = 1;
-+ }
-+ } else if (gmac->port_id == 1) {
-+ if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q1_INT_BIT)) {
-+ toe_gmac_handle_default_rxq(dev);
-+ handled = 1;
-+ }
-+ }
-+ }
-+
-+ /* Interrupt Status 0 */
-+ if (status0 & gmac->intr0_enabled) {
-+#ifndef GMAX_TX_INTR_DISABLED
-+ if (gmac->port_id == 1 && netif_running(dev) &&
-+ (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
-+ ||
-+ ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT)))) {
-+ toe_gmac_tx_complete(dev, 0);
-+ handled = 1;
-+ }
-+
-+ if (gmac->port_id == 0 && netif_running(dev) &&
-+ (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
-+ ||
-+ ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT)))) {
-+ toe_gmac_tx_complete(dev, 0);
-+ handled = 1;
-+ }
-+#endif
-+ }
-+
-+ return IRQ_RETVAL(handled);
-+}
-+
-+static int gmac_open(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ int retval;
-+
-+ /* hook ISR */
-+ retval = request_irq(dev->irq, toe_gmac_interrupt, 0, dev->name, dev);
-+ if (retval)
-+ return retval;
-+
-+ toe_init_gmac(dev);
-+
-+ netif_carrier_off(dev);
-+ phy_start(gmac->phydev);
-+
-+ netif_start_queue(dev);
-+
-+ return 0;
-+}
-+
-+static int gmac_close(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+
-+ netif_stop_queue(dev);
-+ mdelay(20);
-+
-+ if (gmac->phydev)
-+ phy_stop(gmac->phydev);
-+
-+ /* stop tx/rx packet */
-+ toe_gmac_disable_tx_rx(dev);
-+ mdelay(20);
-+
-+ /* stop the chip's Tx and Rx DMA processes */
-+ toe_gmac_hw_stop(gmac);
-+
-+ disable_irq(dev->irq);
-+ free_irq(dev->irq, dev);
-+
-+ return 0;
-+}
-+
-+static void gmac_get_phy_status(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ GMAC_CONFIG0_T config0;
-+ GMAC_STATUS_T status, old_status;
-+ struct phy_device *phydev = gmac->phydev;
-+
-+ old_status.bits32 = status.bits32 = __raw_readl(gmac->base_addr + GMAC_STATUS);
-+
-+ status.bits.link = phydev->link;
-+ status.bits.duplex = phydev->duplex;
-+
-+ switch (phydev->speed) {
-+ case 1000:
-+ status.bits.speed = GMAC_SPEED_1000;
-+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
-+ status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
-+ break;
-+ case 100:
-+ status.bits.speed = GMAC_SPEED_100;
-+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
-+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
-+ break;
-+ case 10:
-+ status.bits.speed = GMAC_SPEED_10;
-+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
-+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
-+ break;
-+ default:
-+ dev_warn(&dev->dev, "Not supported PHY speed (%d)\n", phydev->speed);
-+ }
-+
-+ if (phydev->pause) {
-+ if (gmac->flow_control_enable == 0) {
-+ config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
-+ config0.bits.tx_fc_en = 1; /* enable tx flow control */
-+ config0.bits.rx_fc_en = 1; /* enable rx flow control */
-+ __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
-+ dev_info(&dev->dev, "MII flow control enabled\n");
-+ }
-+ gmac->flow_control_enable = 1;
-+ } else {
-+ if (gmac->flow_control_enable == 1) {
-+ config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
-+ config0.bits.tx_fc_en = 0; /* disable tx flow control */
-+ config0.bits.rx_fc_en = 0; /* disable rx flow control */
-+ __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
-+ dev_info(&dev->dev, "MII flow control disabled\n");
-+ }
-+ gmac->flow_control_enable = 0;
-+ }
-+
-+ if (old_status.bits32 != status.bits32) {
-+ toe_gmac_disable_tx_rx(dev);
-+ phy_print_status(phydev);
-+ mdelay(10); /* let GMAC consume packet */
-+ __raw_writel(status.bits32, gmac->base_addr + GMAC_STATUS);
-+ if (status.bits.link)
-+ toe_gmac_enable_tx_rx(dev);
-+ }
-+}
-+
-+static void gmac_set_rx_mode(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ GMAC_RX_FLTR_T filter;
-+ unsigned int mc_filter[2]; /* Multicast hash filter */
-+ int bit_nr;
-+
-+ filter.bits32 = 0;
-+ filter.bits.error = 0;
-+ if (dev->flags & IFF_PROMISC) {
-+ filter.bits.error = 1;
-+ filter.bits.promiscuous = 1;
-+ filter.bits.broadcast = 1;
-+ filter.bits.multicast = 1;
-+ filter.bits.unicast = 1;
-+ mc_filter[1] = mc_filter[0] = 0xffffffff;
-+ } else if (dev->flags & IFF_ALLMULTI) {
-+ filter.bits.broadcast = 1;
-+ filter.bits.multicast = 1;
-+ filter.bits.unicast = 1;
-+ mc_filter[1] = mc_filter[0] = 0xffffffff;
-+ } else {
-+ struct netdev_hw_addr *ha;
-+
-+ filter.bits.broadcast = 1;
-+ filter.bits.multicast = 1;
-+ filter.bits.unicast = 1;
-+ mc_filter[1] = mc_filter[0] = 0;
-+ netdev_for_each_mc_addr(ha, dev) {
-+ bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
-+ if (bit_nr <= 32)
-+ mc_filter[0] = mc_filter[0] | (1 << bit_nr);
-+ else
-+ mc_filter[1] = mc_filter[1] | (1 << (bit_nr - 32));
-+ }
-+ }
-+ __raw_writel(filter.bits32, gmac->base_addr + GMAC_RX_FLTR);
-+ __raw_writel(mc_filter[0], gmac->base_addr + GMAC_MCAST_FIL0);
-+ __raw_writel(mc_filter[1], gmac->base_addr + GMAC_MCAST_FIL1);
-+}
-+
-+static void gmac_tx_timeout(struct net_device *dev)
-+{
-+ if (!netif_queue_stopped(dev))
-+ netif_wake_queue(dev);
-+
-+ dev_warn(&dev->dev, "TX timeout\n");
-+}
-+
-+const static struct net_device_ops gemini_gmac_ops = {
-+ .ndo_open = gmac_open,
-+ .ndo_stop = gmac_close,
-+ .ndo_start_xmit = gmac_start_xmit,
-+ .ndo_get_stats = gmac_get_stats,
-+ .ndo_set_rx_mode = gmac_set_rx_mode,
-+ .ndo_set_mac_address = gmac_set_mac_address,
-+ .ndo_tx_timeout = gmac_tx_timeout,
-+};
-+
-+static void mac_init_drv(struct toe_private *toe)
-+{
-+ QUEUE_THRESHOLD_T threshold;
-+ DMA_SKB_SIZE_T skb_size;
-+
-+ /* clear non TOE Queue Header Area */
-+ memset(toe->global_base + TOE_NONTOE_QUE_HDR_BASE, 0,
-+ NONTOE_Q_HDR_AREA_END - TOE_NONTOE_QUE_HDR_BASE);
-+
-+ /* clear TOE Queue Header Area */
-+ memset(toe->global_base + TOE_TOE_QUE_HDR_BASE, 0,
-+ TOE_Q_HDR_AREA_END - TOE_TOE_QUE_HDR_BASE);
-+
-+ /* Write GLOBAL_QUEUE_THRESHOLD_REG */
-+ threshold.bits32 = 0;
-+ threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
-+ TOE_SW_FREEQ_DESC_NUM / 2;
-+ threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256 / 4 :
-+ TOE_HW_FREEQ_DESC_NUM / 4;
-+ threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256 / 4 :
-+ TOE_TOE_DESC_NUM / 4;
-+ threshold.bits.intrq = (TOE_INTR_DESC_NUM > 256) ? 256 / 4 :
-+ TOE_INTR_DESC_NUM / 4;
-+ __raw_writel(threshold.bits32, toe->global_base + GLOBAL_QUEUE_THRESHOLD_REG);
-+
-+ /* Init skb size */
-+ skb_size.bits.hw_skb_size = HW_RX_BUF_SIZE;
-+ skb_size.bits.sw_skb_size = SW_RX_BUF_SIZE;
-+ __raw_writel(skb_size.bits32, toe->global_base + GLOBAL_DMA_SKB_SIZE_REG);
-+
-+ toe_init_free_queue(toe);
-+ toe_init_interrupt_config(toe);
-+}
-+
-+static int gmac_init_eth(struct platform_device *pdev,
-+ unsigned int num)
-+{
-+ struct gmac_private *gmac;
-+ struct net_device *dev;
-+ struct toe_private *toe = platform_get_drvdata(pdev);
-+ struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
-+
-+ if (!pdata->bus_id[num])
-+ return 0;
-+
-+ dev = alloc_etherdev(sizeof(*gmac));
-+ if (dev == NULL) {
-+ dev_err(&pdev->dev, "Can't allocate ethernet device #%d\n", num);
-+ return -ENOMEM;
-+ }
-+
-+ gmac = netdev_priv(dev);
-+ dev->ml_priv = toe;
-+ toe->net_dev[num] = dev;
-+
-+ gmac->base_addr = toe->global_base + TOE_GMAC_BASE(num);
-+ gmac->dma_base_addr = toe->global_base + TOE_GMAC_DMA_BASE(num);
-+ gmac->port_id = num;
-+
-+ dev->base_addr = (unsigned int) gmac->base_addr;
-+ dev->irq = platform_get_irq(pdev, num);
-+ dev->netdev_ops = &gemini_gmac_ops;
-+ dev->watchdog_timeo = GMAC_DEV_TX_TIMEOUT;
-+ dev->tx_queue_len = TOE_GMAC_SWTXQ_DESC_NUM;
-+
-+#ifdef DO_HW_CHKSUM
-+ dev->features = NETIF_F_SG | NETIF_F_HW_CSUM;
-+#ifdef ENABLE_TSO
-+ dev->features |= NETIF_F_TSO;
-+#endif
-+#endif
-+
-+ toe_init_swtx_queue(dev);
-+ toe_init_default_queue(dev);
-+
-+ gmac_get_mac_address(dev);
-+
-+ /* TODO: Do we need this? */
-+ __raw_writel(0x55aa55aa, gmac->base_addr + GMAC_STA_ADD2);
-+
-+ if (register_netdev(dev))
-+ return -1;
-+
-+ gmac->phydev = phy_connect(dev, pdata->bus_id[num], &gmac_get_phy_status,
-+ pdata->interface[num]);
-+ if (IS_ERR(gmac->phydev))
-+ return PTR_ERR(gmac->phydev);
-+
-+ gmac->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause;
-+ gmac->phydev->advertising = gmac->phydev->supported;
-+
-+ return 0;
-+}
-+
-+static int gmac_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ struct toe_private *toe;
-+ int retval;
-+
-+ if (!pdev->dev.platform_data)
-+ return -EINVAL;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(&pdev->dev, "can't get device resources\n");
-+ return -ENODEV;
-+ }
-+
-+ toe = kzalloc(sizeof(struct toe_private), GFP_KERNEL);
-+ if (!toe)
-+ return -ENOMEM;
-+
-+ toe->dev = &pdev->dev;
-+
-+ toe->global_base = ioremap(res->start, resource_size(res));
-+ if (!toe->global_base) {
-+ dev_err(toe->dev, "ioremap failed\n");
-+ retval = -EIO;
-+ goto err_data;
-+ }
-+
-+ platform_set_drvdata(pdev, toe);
-+
-+ mac_init_drv(toe);
-+
-+ INIT_WORK(&toe->freq_work, fill_free_q_worker);
-+ spin_lock_init(&toe->freeq_lock);
-+
-+ retval = gmac_init_eth(pdev, GMAC_PORT0);
-+ if (retval)
-+ goto err_unmap;
-+ retval = gmac_init_eth(pdev, GMAC_PORT1);
-+ if (retval)
-+ goto err_unmap;
-+
-+ dev_info(&pdev->dev, SL351x_DRIVER_NAME "\n");
-+
-+ return 0;
-+
-+err_unmap:
-+ iounmap(toe->global_base);
-+err_data:
-+ kfree(toe);
-+ return retval;
-+}
-+
-+static int gmac_remove(struct platform_device *pdev)
-+{
-+ struct toe_private *toe = platform_get_drvdata(pdev);
-+ int i;
-+
-+ for (i = 0; i < 2; i++)
-+ if (toe->net_dev[i]) {
-+ unregister_netdev(toe->net_dev[i]);
-+ kfree(toe->net_dev[i]);
-+ }
-+
-+ iounmap(toe->global_base);
-+
-+ kfree(toe);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver gemini_gmac_driver = {
-+ .probe = gmac_probe,
-+ .remove = gmac_remove,
-+ .driver = {
-+ .name = "gemini-gmac",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init gemini_gmac_init(void)
-+{
-+ return platform_driver_register(&gemini_gmac_driver);
-+}
-+
-+static void __exit gemini_gmac_exit(void)
-+{
-+ platform_driver_unregister(&gemini_gmac_driver);
-+}
-+
-+module_init(gemini_gmac_init);
-+module_exit(gemini_gmac_exit);
-+
-+MODULE_AUTHOR("Paulius Zaleckas");
-+MODULE_DESCRIPTION("Ethernet device driver for Gemini SoC");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:gemini-gmac");
---- /dev/null
-+++ b/drivers/net/gemini_negmac/gm_gmac.h
-@@ -0,0 +1,1489 @@
-+/*
-+ * Register definitions for Gemini Ethernet device driver.
-+ *
-+ * Copyright (C) 2006, Storlink, Corp.
-+ * Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+#ifndef _GMAC_SL351x_H
-+#define _GMAC_SL351x_H
-+#include <linux/skbuff.h>
-+
-+#define _PACKED_ __attribute__ ((aligned(1), packed))
-+
-+#ifndef BIT
-+#define BIT(x) (1 << (x))
-+#endif
-+
-+#define REG32(addr) (*(volatile unsigned long * const)(addr))
-+
-+/* Define frame size */
-+#define GMAC_MAX_ETH_FRAME_SIZE 1514
-+#define GMAC_TX_BUF_SIZE ((GMAC_MAX_ETH_FRAME_SIZE + 31) & (~31))
-+
-+#define SW_RX_BUF_SIZE 1536
-+#define HW_RX_BUF_SIZE 1536
-+
-+#define GMAC_DEV_TX_TIMEOUT (10*HZ)
-+#define SKB_RESERVE_BYTES 16
-+
-+/*
-+ * Base Registers
-+ */
-+#define TOE_NONTOE_QUE_HDR_BASE 0x2000
-+#define TOE_TOE_QUE_HDR_BASE 0x3000
-+#define TOE_V_BIT_BASE 0x4000
-+#define TOE_A_BIT_BASE 0x6000
-+#define TOE_GMAC_DMA_BASE(x) (0x8000 + 0x4000 * (x))
-+#define TOE_GMAC_BASE(x) (0xA000 + 0x4000 * (x))
-+
-+/*
-+ * Queue ID
-+ */
-+#define TOE_SW_FREE_QID 0x00
-+#define TOE_HW_FREE_QID 0x01
-+#define TOE_GMAC0_SW_TXQ0_QID 0x02
-+#define TOE_GMAC0_SW_TXQ1_QID 0x03
-+#define TOE_GMAC0_SW_TXQ2_QID 0x04
-+#define TOE_GMAC0_SW_TXQ3_QID 0x05
-+#define TOE_GMAC0_SW_TXQ4_QID 0x06
-+#define TOE_GMAC0_SW_TXQ5_QID 0x07
-+#define TOE_GMAC0_HW_TXQ0_QID 0x08
-+#define TOE_GMAC0_HW_TXQ1_QID 0x09
-+#define TOE_GMAC0_HW_TXQ2_QID 0x0A
-+#define TOE_GMAC0_HW_TXQ3_QID 0x0B
-+#define TOE_GMAC1_SW_TXQ0_QID 0x12
-+#define TOE_GMAC1_SW_TXQ1_QID 0x13
-+#define TOE_GMAC1_SW_TXQ2_QID 0x14
-+#define TOE_GMAC1_SW_TXQ3_QID 0x15
-+#define TOE_GMAC1_SW_TXQ4_QID 0x16
-+#define TOE_GMAC1_SW_TXQ5_QID 0x17
-+#define TOE_GMAC1_HW_TXQ0_QID 0x18
-+#define TOE_GMAC1_HW_TXQ1_QID 0x19
-+#define TOE_GMAC1_HW_TXQ2_QID 0x1A
-+#define TOE_GMAC1_HW_TXQ3_QID 0x1B
-+#define TOE_GMAC0_DEFAULT_QID 0x20
-+#define TOE_GMAC1_DEFAULT_QID 0x21
-+#define TOE_CLASSIFICATION_QID(x) (0x22 + x) // 0x22 ~ 0x2F
-+#define TOE_TOE_QID(x) (0x40 + x) // 0x40 ~ 0x7F
-+
-+/*
-+ * TOE DMA Queue Number should be 2^n, n = 6...12
-+ * TOE DMA Queues are the following queue types:
-+ * SW Free Queue, HW Free Queue,
-+ * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
-+ * They have same descriptor numbers.
-+ * The base address and descriptor number are configured at
-+ * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
-+ */
-+#define TOE_SW_FREEQ_DESC_POWER 8
-+#define TOE_SW_FREEQ_DESC_NUM (1<<TOE_SW_FREEQ_DESC_POWER)
-+#define TOE_HW_FREEQ_DESC_POWER 8
-+#define TOE_HW_FREEQ_DESC_NUM (1<<TOE_HW_FREEQ_DESC_POWER)
-+#define TOE_GMAC_SWTXQ_DESC_POWER 8
-+#define TOE_GMAC_SWTXQ_DESC_NUM (1<<TOE_GMAC_SWTXQ_DESC_POWER)
-+#define TOE_GMAC_HWTXQ_DESC_POWER 8
-+#define TOE_GMAC_HWTXQ_DESC_NUM (1<<TOE_GMAC_HWTXQ_DESC_POWER)
-+#define TOE_DEFAULT_Q_DESC_POWER 8
-+#define TOE_DEFAULT_Q_DESC_NUM (1<<TOE_DEFAULT_Q_DESC_POWER)
-+#define TOE_TOE_DESC_POWER 8
-+#define TOE_TOE_DESC_NUM (1<<TOE_TOE_DESC_POWER)
-+#define TOE_CLASS_DESC_POWER 8
-+#define TOE_CLASS_DESC_NUM (1<<TOE_CLASS_DESC_POWER)
-+#define TOE_INTR_DESC_POWER 8
-+#define TOE_INTR_DESC_NUM (1<<TOE_INTR_DESC_POWER)
-+
-+#define TOE_TOE_QUEUE_MAX 64
-+#define TOE_TOE_QUEUE_NUM 64
-+#define TOE_CLASS_QUEUE_MAX 14
-+#define TOE_CLASS_QUEUE_NUM 14
-+#define TOE_INTR_QUEUE_MAX 4
-+#define TOE_INTR_QUEUE_NUM 4
-+#define TOE_SW_TXQ_MAX 6
-+#define TOE_SW_TXQ_NUM 1
-+#define TOE_HW_TXQ_MAX 4
-+#define TOE_HW_TXQ_NUM 4
-+
-+#define RWPTR_ADVANCE_ONE(x, max) ((x == (max -1)) ? 0 : x+1)
-+#define RWPTR_RECEDE_ONE(x, max) ((x == 0) ? (max -1) : x-1)
-+#define SET_WPTR(addr, data) (*(volatile u16 * const)((u32)(addr) + 2) = (u16)data)
-+#define SET_RPTR(addr, data) (*(volatile u16 * const)((u32)(addr)) = (u16)data)
-+
-+/*
-+ * Global registers
-+ * #define TOE_GLOBAL_BASE (TOE_BASE + 0x0000)
-+ * Base 0x60000000
-+ */
-+#define GLOBAL_TOE_VERSION_REG 0x0000
-+#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004
-+#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008
-+#define GLOBAL_DMA_SKB_SIZE_REG 0x0010
-+#define GLOBAL_SWFQ_RWPTR_REG 0x0014
-+#define GLOBAL_HWFQ_RWPTR_REG 0x0018
-+#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020
-+#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024
-+#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028
-+#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030
-+#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034
-+#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038
-+#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040
-+#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044
-+#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048
-+#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050
-+#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054
-+#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058
-+#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060
-+#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064
-+#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068
-+#define GLOBAL_HASH_TABLE_BASE_REG 0x006C
-+#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070
-+
-+/*
-+ * GMAC 0/1 DMA/TOE register
-+ * #define TOE_GMAC0_DMA_BASE (TOE_BASE + 0x8000)
-+ * #define TOE_GMAC1_DMA_BASE (TOE_BASE + 0xC000)
-+ * Base 0x60008000 or 0x6000C000
-+ */
-+#define GMAC_DMA_CTRL_REG 0x0000
-+#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004
-+#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008
-+#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C
-+#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010
-+#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014
-+#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018
-+#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C
-+#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020
-+#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024
-+#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028
-+#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C
-+#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030
-+#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038
-+#define GMAC_DMA_TX_CURR_DESC_REG 0x003C
-+#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040
-+#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044
-+#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048
-+#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C
-+#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050
-+#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054
-+#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058
-+#define GMAC_DMA_RX_CURR_DESC_REG 0x005C
-+#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060
-+#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064
-+#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068
-+#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C
-+#define GMAC_HASH_ENGINE_REG0 0x0070
-+#define GMAC_HASH_ENGINE_REG1 0x0074
-+/* matching rule 0 Control register 0 */
-+#define GMAC_MR0CR0 0x0078
-+#define GMAC_MR0CR1 0x007C
-+#define GMAC_MR0CR2 0x0080
-+#define GMAC_MR1CR0 0x0084
-+#define GMAC_MR1CR1 0x0088
-+#define GMAC_MR1CR2 0x008C
-+#define GMAC_MR2CR0 0x0090
-+#define GMAC_MR2CR1 0x0094
-+#define GMAC_MR2CR2 0x0098
-+#define GMAC_MR3CR0 0x009C
-+#define GMAC_MR3CR1 0x00A0
-+#define GMAC_MR3CR2 0x00A4
-+/* Support Protocol Regsister 0 */
-+#define GMAC_SPR0 0x00A8
-+#define GMAC_SPR1 0x00AC
-+#define GMAC_SPR2 0x00B0
-+#define GMAC_SPR3 0x00B4
-+#define GMAC_SPR4 0x00B8
-+#define GMAC_SPR5 0x00BC
-+#define GMAC_SPR6 0x00C0
-+#define GMAC_SPR7 0x00C4
-+/* GMAC Hash/Rx/Tx AHB Weighting register */
-+#define GMAC_AHB_WEIGHT_REG 0x00C8
-+
-+/*
-+ * TOE GMAC 0/1 register
-+ * #define TOE_GMAC0_BASE (TOE_BASE + 0xA000)
-+ * #define TOE_GMAC1_BASE (TOE_BASE + 0xE000)
-+ * Base 0x6000A000 or 0x6000E000
-+ */
-+enum GMAC_REGISTER {
-+ GMAC_STA_ADD0 = 0x0000,
-+ GMAC_STA_ADD1 = 0x0004,
-+ GMAC_STA_ADD2 = 0x0008,
-+ GMAC_RX_FLTR = 0x000c,
-+ GMAC_MCAST_FIL0 = 0x0010,
-+ GMAC_MCAST_FIL1 = 0x0014,
-+ GMAC_CONFIG0 = 0x0018,
-+ GMAC_CONFIG1 = 0x001c,
-+ GMAC_CONFIG2 = 0x0020,
-+ GMAC_CONFIG3 = 0x0024,
-+ GMAC_RESERVED = 0x0028,
-+ GMAC_STATUS = 0x002c,
-+ GMAC_IN_DISCARDS= 0x0030,
-+ GMAC_IN_ERRORS = 0x0034,
-+ GMAC_IN_MCAST = 0x0038,
-+ GMAC_IN_BCAST = 0x003c,
-+ GMAC_IN_MAC1 = 0x0040, /* for STA 1 MAC Address */
-+ GMAC_IN_MAC2 = 0x0044 /* for STA 2 MAC Address */
-+};
-+
-+/*
-+ * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int base_size;
-+} DMA_Q_BASE_SIZE_T;
-+#define DMA_Q_BASE_MASK (~0x0f)
-+
-+/*
-+ * DMA SKB Buffer register (offset 0x0008)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0008 {
-+ unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */
-+ unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */
-+ } bits;
-+} DMA_SKB_SIZE_T;
-+
-+/*
-+ * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_000c {
-+ unsigned int rptr : 16; /* Read Ptr, RO */
-+ unsigned int wptr : 16; /* Write Ptr, RW */
-+ } bits;
-+} DMA_RWPTR_T;
-+
-+/*
-+ * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
-+ * see DMA_RWPTR_T structure
-+ */
-+
-+/*
-+ * Interrupt Status Register 0 (offset 0x0020)
-+ * Interrupt Mask Register 0 (offset 0x0024)
-+ * Interrupt Select Register 0 (offset 0x0028)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0020 {
-+ /* GMAC0 SW Tx Queue 0 EOF Interrupt */
-+ unsigned int swtq00_eof : 1;
-+ unsigned int swtq01_eof : 1;
-+ unsigned int swtq02_eof : 1;
-+ unsigned int swtq03_eof : 1;
-+ unsigned int swtq04_eof : 1;
-+ unsigned int swtq05_eof : 1;
-+ /* GMAC1 SW Tx Queue 0 EOF Interrupt */
-+ unsigned int swtq10_eof : 1;
-+ unsigned int swtq11_eof : 1;
-+ unsigned int swtq12_eof : 1;
-+ unsigned int swtq13_eof : 1;
-+ unsigned int swtq14_eof : 1;
-+ unsigned int swtq15_eof : 1;
-+ /* GMAC0 SW Tx Queue 0 Finish Interrupt */
-+ unsigned int swtq00_fin : 1;
-+ unsigned int swtq01_fin : 1;
-+ unsigned int swtq02_fin : 1;
-+ unsigned int swtq03_fin : 1;
-+ unsigned int swtq04_fin : 1;
-+ unsigned int swtq05_fin : 1;
-+ /* GMAC1 SW Tx Queue 0 Finish Interrupt */
-+ unsigned int swtq10_fin : 1;
-+ unsigned int swtq11_fin : 1;
-+ unsigned int swtq12_fin : 1;
-+ unsigned int swtq13_fin : 1;
-+ unsigned int swtq14_fin : 1;
-+ unsigned int swtq15_fin : 1;
-+ /* GMAC0 Rx Descriptor Protocol Error */
-+ unsigned int rxPerr0 : 1;
-+ /* GMAC0 AHB Bus Error while Rx */
-+ unsigned int rxDerr0 : 1;
-+ /* GMAC1 Rx Descriptor Protocol Error */
-+ unsigned int rxPerr1 : 1;
-+ /* GMAC1 AHB Bus Error while Rx */
-+ unsigned int rxDerr1 : 1;
-+ /* GMAC0 Tx Descriptor Protocol Error */
-+ unsigned int txPerr0 : 1;
-+ /* GMAC0 AHB Bus Error while Tx */
-+ unsigned int txDerr0 : 1;
-+ /* GMAC1 Tx Descriptor Protocol Error */
-+ unsigned int txPerr1 : 1;
-+ /* GMAC1 AHB Bus Error while Tx */
-+ unsigned int txDerr1 : 1;
-+ } bits;
-+} INTR_REG0_T;
-+
-+#define GMAC1_TXDERR_INT_BIT BIT(31)
-+#define GMAC1_TXPERR_INT_BIT BIT(30)
-+#define GMAC0_TXDERR_INT_BIT BIT(29)
-+#define GMAC0_TXPERR_INT_BIT BIT(28)
-+#define GMAC1_RXDERR_INT_BIT BIT(27)
-+#define GMAC1_RXPERR_INT_BIT BIT(26)
-+#define GMAC0_RXDERR_INT_BIT BIT(25)
-+#define GMAC0_RXPERR_INT_BIT BIT(24)
-+#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23)
-+#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22)
-+#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21)
-+#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20)
-+#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19)
-+#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18)
-+#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17)
-+#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16)
-+#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15)
-+#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14)
-+#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13)
-+#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12)
-+#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11)
-+#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10)
-+#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9)
-+#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8)
-+#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7)
-+#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6)
-+#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5)
-+#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4)
-+#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3)
-+#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2)
-+#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1)
-+#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0)
-+
-+/*
-+ * Interrupt Status Register 1 (offset 0x0030)
-+ * Interrupt Mask Register 1 (offset 0x0034)
-+ * Interrupt Select Register 1 (offset 0x0038)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0030 {
-+ unsigned int default_q0_eof : 1; /* Default Queue 0 EOF Interrupt */
-+ unsigned int default_q1_eof : 1; /* Default Queue 1 EOF Interrupt */
-+ unsigned int class_rx : 14; /* Classification Queue Rx Interrupt */
-+ unsigned int hwtq00_eof : 1; /* GMAC0 HW Tx Queue0 EOF Interrupt */
-+ unsigned int hwtq01_eof : 1; /* GMAC0 HW Tx Queue1 EOF Interrupt */
-+ unsigned int hwtq02_eof : 1; /* GMAC0 HW Tx Queue2 EOF Interrupt */
-+ unsigned int hwtq03_eof : 1; /* GMAC0 HW Tx Queue3 EOF Interrupt */
-+ unsigned int hwtq10_eof : 1; /* GMAC1 HW Tx Queue0 EOF Interrupt */
-+ unsigned int hwtq11_eof : 1; /* GMAC1 HW Tx Queue1 EOF Interrupt */
-+ unsigned int hwtq12_eof : 1; /* GMAC1 HW Tx Queue2 EOF Interrupt */
-+ unsigned int hwtq13_eof : 1; /* GMAC1 HW Tx Queue3 EOF Interrupt */
-+ unsigned int toe_iq0_intr : 1; /* TOE Interrupt Queue 0 with Interrupts */
-+ unsigned int toe_iq1_intr : 1; /* TOE Interrupt Queue 1 with Interrupts */
-+ unsigned int toe_iq2_intr : 1; /* TOE Interrupt Queue 2 with Interrupts */
-+ unsigned int toe_iq3_intr : 1; /* TOE Interrupt Queue 3 with Interrupts */
-+ unsigned int toe_iq0_full : 1; /* TOE Interrupt Queue 0 Full Interrupt */
-+ unsigned int toe_iq1_full : 1; /* TOE Interrupt Queue 1 Full Interrupt */
-+ unsigned int toe_iq2_full : 1; /* TOE Interrupt Queue 2 Full Interrupt */
-+ unsigned int toe_iq3_full : 1; /* TOE Interrupt Queue 3 Full Interrupt */
-+ } bits;
-+} INTR_REG1_T;
-+
-+#define TOE_IQ3_FULL_INT_BIT BIT(31)
-+#define TOE_IQ2_FULL_INT_BIT BIT(30)
-+#define TOE_IQ1_FULL_INT_BIT BIT(29)
-+#define TOE_IQ0_FULL_INT_BIT BIT(28)
-+#define TOE_IQ3_INT_BIT BIT(27)
-+#define TOE_IQ2_INT_BIT BIT(26)
-+#define TOE_IQ1_INT_BIT BIT(25)
-+#define TOE_IQ0_INT_BIT BIT(24)
-+#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23)
-+#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22)
-+#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21)
-+#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20)
-+#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19)
-+#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18)
-+#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17)
-+#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16)
-+#define CLASS_RX_INT_BIT(x) BIT((x + 2))
-+#define DEFAULT_Q1_INT_BIT BIT(1)
-+#define DEFAULT_Q0_INT_BIT BIT(0)
-+
-+#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
-+ TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
-+#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
-+ TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
-+#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
-+#define TOE_CLASS_RX_INT_BITS 0xfffc
-+
-+/*
-+ * Interrupt Status Register 2 (offset 0x0040)
-+ * Interrupt Mask Register 2 (offset 0x0044)
-+ * Interrupt Select Register 2 (offset 0x0048)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0040 {
-+ unsigned int toe_q0_full : 1; // bit 0 TOE Queue 0 Full Interrupt
-+ unsigned int toe_q1_full : 1; // bit 1 TOE Queue 1 Full Interrupt
-+ unsigned int toe_q2_full : 1; // bit 2 TOE Queue 2 Full Interrupt
-+ unsigned int toe_q3_full : 1; // bit 3 TOE Queue 3 Full Interrupt
-+ unsigned int toe_q4_full : 1; // bit 4 TOE Queue 4 Full Interrupt
-+ unsigned int toe_q5_full : 1; // bit 5 TOE Queue 5 Full Interrupt
-+ unsigned int toe_q6_full : 1; // bit 6 TOE Queue 6 Full Interrupt
-+ unsigned int toe_q7_full : 1; // bit 7 TOE Queue 7 Full Interrupt
-+ unsigned int toe_q8_full : 1; // bit 8 TOE Queue 8 Full Interrupt
-+ unsigned int toe_q9_full : 1; // bit 9 TOE Queue 9 Full Interrupt
-+ unsigned int toe_q10_full : 1; // bit 10 TOE Queue 10 Full Interrupt
-+ unsigned int toe_q11_full : 1; // bit 11 TOE Queue 11 Full Interrupt
-+ unsigned int toe_q12_full : 1; // bit 12 TOE Queue 12 Full Interrupt
-+ unsigned int toe_q13_full : 1; // bit 13 TOE Queue 13 Full Interrupt
-+ unsigned int toe_q14_full : 1; // bit 14 TOE Queue 14 Full Interrupt
-+ unsigned int toe_q15_full : 1; // bit 15 TOE Queue 15 Full Interrupt
-+ unsigned int toe_q16_full : 1; // bit 16 TOE Queue 16 Full Interrupt
-+ unsigned int toe_q17_full : 1; // bit 17 TOE Queue 17 Full Interrupt
-+ unsigned int toe_q18_full : 1; // bit 18 TOE Queue 18 Full Interrupt
-+ unsigned int toe_q19_full : 1; // bit 19 TOE Queue 19 Full Interrupt
-+ unsigned int toe_q20_full : 1; // bit 20 TOE Queue 20 Full Interrupt
-+ unsigned int toe_q21_full : 1; // bit 21 TOE Queue 21 Full Interrupt
-+ unsigned int toe_q22_full : 1; // bit 22 TOE Queue 22 Full Interrupt
-+ unsigned int toe_q23_full : 1; // bit 23 TOE Queue 23 Full Interrupt
-+ unsigned int toe_q24_full : 1; // bit 24 TOE Queue 24 Full Interrupt
-+ unsigned int toe_q25_full : 1; // bit 25 TOE Queue 25 Full Interrupt
-+ unsigned int toe_q26_full : 1; // bit 26 TOE Queue 26 Full Interrupt
-+ unsigned int toe_q27_full : 1; // bit 27 TOE Queue 27 Full Interrupt
-+ unsigned int toe_q28_full : 1; // bit 28 TOE Queue 28 Full Interrupt
-+ unsigned int toe_q29_full : 1; // bit 29 TOE Queue 29 Full Interrupt
-+ unsigned int toe_q30_full : 1; // bit 30 TOE Queue 30 Full Interrupt
-+ unsigned int toe_q31_full : 1; // bit 31 TOE Queue 31 Full Interrupt
-+ } bits;
-+} INTR_REG2_T;
-+
-+#define TOE_QL_FULL_INT_BIT(x) BIT(x)
-+
-+/*
-+ * Interrupt Status Register 3 (offset 0x0050)
-+ * Interrupt Mask Register 3 (offset 0x0054)
-+ * Interrupt Select Register 3 (offset 0x0058)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0050 {
-+ unsigned int toe_q32_full : 1; // bit 32 TOE Queue 32 Full Interrupt
-+ unsigned int toe_q33_full : 1; // bit 33 TOE Queue 33 Full Interrupt
-+ unsigned int toe_q34_full : 1; // bit 34 TOE Queue 34 Full Interrupt
-+ unsigned int toe_q35_full : 1; // bit 35 TOE Queue 35 Full Interrupt
-+ unsigned int toe_q36_full : 1; // bit 36 TOE Queue 36 Full Interrupt
-+ unsigned int toe_q37_full : 1; // bit 37 TOE Queue 37 Full Interrupt
-+ unsigned int toe_q38_full : 1; // bit 38 TOE Queue 38 Full Interrupt
-+ unsigned int toe_q39_full : 1; // bit 39 TOE Queue 39 Full Interrupt
-+ unsigned int toe_q40_full : 1; // bit 40 TOE Queue 40 Full Interrupt
-+ unsigned int toe_q41_full : 1; // bit 41 TOE Queue 41 Full Interrupt
-+ unsigned int toe_q42_full : 1; // bit 42 TOE Queue 42 Full Interrupt
-+ unsigned int toe_q43_full : 1; // bit 43 TOE Queue 43 Full Interrupt
-+ unsigned int toe_q44_full : 1; // bit 44 TOE Queue 44 Full Interrupt
-+ unsigned int toe_q45_full : 1; // bit 45 TOE Queue 45 Full Interrupt
-+ unsigned int toe_q46_full : 1; // bit 46 TOE Queue 46 Full Interrupt
-+ unsigned int toe_q47_full : 1; // bit 47 TOE Queue 47 Full Interrupt
-+ unsigned int toe_q48_full : 1; // bit 48 TOE Queue 48 Full Interrupt
-+ unsigned int toe_q49_full : 1; // bit 49 TOE Queue 49 Full Interrupt
-+ unsigned int toe_q50_full : 1; // bit 50 TOE Queue 50 Full Interrupt
-+ unsigned int toe_q51_full : 1; // bit 51 TOE Queue 51 Full Interrupt
-+ unsigned int toe_q52_full : 1; // bit 52 TOE Queue 52 Full Interrupt
-+ unsigned int toe_q53_full : 1; // bit 53 TOE Queue 53 Full Interrupt
-+ unsigned int toe_q54_full : 1; // bit 54 TOE Queue 54 Full Interrupt
-+ unsigned int toe_q55_full : 1; // bit 55 TOE Queue 55 Full Interrupt
-+ unsigned int toe_q56_full : 1; // bit 56 TOE Queue 56 Full Interrupt
-+ unsigned int toe_q57_full : 1; // bit 57 TOE Queue 57 Full Interrupt
-+ unsigned int toe_q58_full : 1; // bit 58 TOE Queue 58 Full Interrupt
-+ unsigned int toe_q59_full : 1; // bit 59 TOE Queue 59 Full Interrupt
-+ unsigned int toe_q60_full : 1; // bit 60 TOE Queue 60 Full Interrupt
-+ unsigned int toe_q61_full : 1; // bit 61 TOE Queue 61 Full Interrupt
-+ unsigned int toe_q62_full : 1; // bit 62 TOE Queue 62 Full Interrupt
-+ unsigned int toe_q63_full : 1; // bit 63 TOE Queue 63 Full Interrupt
-+ } bits;
-+} INTR_REG3_T;
-+
-+#define TOE_QH_FULL_INT_BIT(x) BIT(x-32)
-+
-+/*
-+ * Interrupt Status Register 4 (offset 0x0060)
-+ * Interrupt Mask Register 4 (offset 0x0064)
-+ * Interrupt Select Register 4 (offset 0x0068)
-+ */
-+typedef union {
-+ unsigned char byte;
-+ struct bit_0060 {
-+ unsigned char status_changed : 1; // Status Changed Intr for RGMII Mode
-+ unsigned char rx_overrun : 1; // GMAC Rx FIFO overrun interrupt
-+ unsigned char tx_pause_off : 1; // received pause off frame interrupt
-+ unsigned char rx_pause_off : 1; // received pause off frame interrupt
-+ unsigned char tx_pause_on : 1; // transmit pause on frame interrupt
-+ unsigned char rx_pause_on : 1; // received pause on frame interrupt
-+ unsigned char cnt_full : 1; // MIB counters half full interrupt
-+ unsigned char reserved : 1; //
-+ } _PACKED_ bits;
-+} _PACKED_ GMAC_INTR_T;
-+
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0060_2 {
-+ unsigned int swfq_empty : 1; // bit 0 Software Free Queue Empty Intr.
-+ unsigned int hwfq_empty : 1; // bit 1 Hardware Free Queue Empty Intr.
-+ unsigned int class_qf_int : 14; // bit 15:2 Classification Rx Queue13-0 Full Intr.
-+ GMAC_INTR_T gmac0;
-+ GMAC_INTR_T gmac1;
-+ } bits;
-+} INTR_REG4_T;
-+
-+#define GMAC1_RESERVED_INT_BIT BIT(31)
-+#define GMAC1_MIB_INT_BIT BIT(30)
-+#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)
-+#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)
-+#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)
-+#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)
-+#define GMAC1_RX_OVERRUN_INT_BIT BIT(25)
-+#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
-+#define GMAC0_RESERVED_INT_BIT BIT(23)
-+#define GMAC0_MIB_INT_BIT BIT(22)
-+#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)
-+#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)
-+#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)
-+#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)
-+#define GMAC0_RX_OVERRUN_INT_BIT BIT(17)
-+#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
-+#define CLASS_RX_FULL_INT_BIT(x) BIT((x+2))
-+#define HWFQ_EMPTY_INT_BIT BIT(1)
-+#define SWFQ_EMPTY_INT_BIT BIT(0)
-+
-+#if 1
-+#define GMAC0_INT_BITS (GMAC0_MIB_INT_BIT)
-+#define GMAC1_INT_BITS (GMAC1_MIB_INT_BIT)
-+#else
-+#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
-+ GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT | \
-+ GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT | \
-+ GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
-+#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
-+ GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT | \
-+ GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT | \
-+ GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
-+#endif
-+
-+#define CLASS_RX_FULL_INT_BITS 0xfffc
-+
-+/*
-+ * GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0070_2 {
-+ unsigned int swfq_empty : 8; // 7:0 Software Free Queue Empty Threshold
-+ unsigned int hwfq_empty : 8; // 15:8 Hardware Free Queue Empty Threshold
-+ unsigned int intrq : 8; // 23:16
-+ unsigned int toe_class : 8; // 31:24
-+ } bits;
-+} QUEUE_THRESHOLD_T;
-+
-+
-+/*
-+ * GMAC DMA Control Register
-+ * GMAC0 offset 0x8000
-+ * GMAC1 offset 0xC000
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8000 {
-+ unsigned int td_bus : 2; // bit 1:0 Peripheral Bus Width
-+ unsigned int td_burst_size : 2; // bit 3:2 TxDMA max burst size for every AHB request
-+ unsigned int td_prot : 4; // bit 7:4 TxDMA protection control
-+ unsigned int rd_bus : 2; // bit 9:8 Peripheral Bus Width
-+ unsigned int rd_burst_size : 2; // bit 11:10 DMA max burst size for every AHB request
-+ unsigned int rd_prot : 4; // bit 15:12 DMA Protection Control
-+ unsigned int rd_insert_bytes : 2; // bit 17:16
-+ unsigned int reserved : 10; // bit 27:18
-+ unsigned int drop_small_ack : 1; // bit 28 1: Drop, 0: Accept
-+ unsigned int loopback : 1; // bit 29 Loopback TxDMA to RxDMA
-+ unsigned int td_enable : 1; // bit 30 Tx DMA Enable
-+ unsigned int rd_enable : 1; // bit 31 Rx DMA Enable
-+ } bits;
-+} GMAC_DMA_CTRL_T;
-+
-+/*
-+ * GMAC Tx Weighting Control Register 0
-+ * GMAC0 offset 0x8004
-+ * GMAC1 offset 0xC004
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8004 {
-+ unsigned int hw_tq0 : 6; // bit 5:0 HW TX Queue 3
-+ unsigned int hw_tq1 : 6; // bit 11:6 HW TX Queue 2
-+ unsigned int hw_tq2 : 6; // bit 17:12 HW TX Queue 1
-+ unsigned int hw_tq3 : 6; // bit 23:18 HW TX Queue 0
-+ unsigned int reserved : 8; // bit 31:24
-+ } bits;
-+} GMAC_TX_WCR0_T; /* Weighting Control Register 0 */
-+
-+/*
-+ * GMAC Tx Weighting Control Register 1
-+ * GMAC0 offset 0x8008
-+ * GMAC1 offset 0xC008
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8008 {
-+ unsigned int sw_tq0 : 5; // bit 4:0 SW TX Queue 0
-+ unsigned int sw_tq1 : 5; // bit 9:5 SW TX Queue 1
-+ unsigned int sw_tq2 : 5; // bit 14:10 SW TX Queue 2
-+ unsigned int sw_tq3 : 5; // bit 19:15 SW TX Queue 3
-+ unsigned int sw_tq4 : 5; // bit 24:20 SW TX Queue 4
-+ unsigned int sw_tq5 : 5; // bit 29:25 SW TX Queue 5
-+ unsigned int reserved : 2; // bit 31:30
-+ } bits;
-+} GMAC_TX_WCR1_T; /* Weighting Control Register 1 */
-+
-+/*
-+ * Queue Read/Write Pointer
-+ * GMAC SW TX Queue 0~5 Read/Write Pointer register
-+ * GMAC0 offset 0x800C ~ 0x8020
-+ * GMAC1 offset 0xC00C ~ 0xC020
-+ * GMAC HW TX Queue 0~3 Read/Write Pointer register
-+ * GMAC0 offset 0x8024 ~ 0x8030
-+ * GMAC1 offset 0xC024 ~ 0xC030
-+ *
-+ * see DMA_RWPTR_T structure
-+ */
-+
-+/*
-+ * GMAC DMA Tx First Description Address Register
-+ * GMAC0 offset 0x8038
-+ * GMAC1 offset 0xC038
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8038 {
-+ unsigned int reserved : 3;
-+ unsigned int td_busy : 1; // bit 3 1: TxDMA busy; 0: TxDMA idle
-+ unsigned int td_first_des_ptr : 28; // bit 31:4 first descriptor address
-+ } bits;
-+} GMAC_TXDMA_FIRST_DESC_T;
-+
-+/*
-+ * GMAC DMA Tx Current Description Address Register
-+ * GMAC0 offset 0x803C
-+ * GMAC1 offset 0xC03C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_803C {
-+ unsigned int reserved : 4;
-+ unsigned int td_curr_desc_ptr : 28; // bit 31:4 current descriptor address
-+ } bits;
-+} GMAC_TXDMA_CURR_DESC_T;
-+
-+/*
-+ * GMAC DMA Tx Description Word 0 Register
-+ * GMAC0 offset 0x8040
-+ * GMAC1 offset 0xC040
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8040 {
-+ unsigned int buffer_size : 16; // bit 15:0 Transfer size
-+ unsigned int desc_count : 6; // bit 21:16 number of descriptors used for the current frame
-+ unsigned int status_tx_ok : 1; // bit 22 Tx Status, 1: Successful 0: Failed
-+ unsigned int status_rvd : 6; // bit 28:23 Tx Status, Reserved bits
-+ unsigned int perr : 1; // bit 29 protocol error during processing this descriptor
-+ unsigned int derr : 1; // bit 30 data error during processing this descriptor
-+ unsigned int reserved : 1; // bit 31
-+ } bits;
-+} GMAC_TXDESC_0_T;
-+
-+/*
-+ * GMAC DMA Tx Description Word 1 Register
-+ * GMAC0 offset 0x8044
-+ * GMAC1 offset 0xC044
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct txdesc_word1 {
-+ unsigned int byte_count : 16; // bit 15: 0 Tx Frame Byte Count
-+ unsigned int mtu_enable : 1; // bit 16 TSS segmentation use MTU setting
-+ unsigned int ip_chksum : 1; // bit 17 IPV4 Header Checksum Enable
-+ unsigned int ipv6_enable : 1; // bit 18 IPV6 Tx Enable
-+ unsigned int tcp_chksum : 1; // bit 19 TCP Checksum Enable
-+ unsigned int udp_chksum : 1; // bit 20 UDP Checksum Enable
-+ unsigned int bypass_tss : 1; // bit 21
-+ unsigned int ip_fixed_len : 1; // bit 22
-+ unsigned int reserved : 9; // bit 31:23 Tx Flag, Reserved
-+ } bits;
-+} GMAC_TXDESC_1_T;
-+
-+#define TSS_IP_FIXED_LEN_BIT BIT(22)
-+#define TSS_UDP_CHKSUM_BIT BIT(20)
-+#define TSS_TCP_CHKSUM_BIT BIT(19)
-+#define TSS_IPV6_ENABLE_BIT BIT(18)
-+#define TSS_IP_CHKSUM_BIT BIT(17)
-+#define TSS_MTU_ENABLE_BIT BIT(16)
-+
-+/*
-+ * GMAC DMA Tx Description Word 2 Register
-+ * GMAC0 offset 0x8048
-+ * GMAC1 offset 0xC048
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int buf_adr;
-+} GMAC_TXDESC_2_T;
-+
-+/*
-+ * GMAC DMA Tx Description Word 3 Register
-+ * GMAC0 offset 0x804C
-+ * GMAC1 offset 0xC04C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct txdesc_word3 {
-+ unsigned int mtu_size : 11; // bit 10: 0 Tx Frame Byte Count
-+ unsigned int reserved : 18; // bit 28:11
-+ unsigned int eofie : 1; // bit 29 End of frame interrupt enable
-+ unsigned int sof_eof : 2; // bit 31:30 11: only one, 10: first, 01: last, 00: linking
-+ } bits;
-+} GMAC_TXDESC_3_T;
-+#define SOF_EOF_BIT_MASK 0x3fffffff
-+#define SOF_BIT 0x80000000
-+#define EOF_BIT 0x40000000
-+#define EOFIE_BIT BIT(29)
-+#define MTU_SIZE_BIT_MASK 0x7ff
-+
-+/*
-+ * GMAC Tx Descriptor
-+ */
-+typedef struct {
-+ GMAC_TXDESC_0_T word0;
-+ GMAC_TXDESC_1_T word1;
-+ GMAC_TXDESC_2_T word2;
-+ GMAC_TXDESC_3_T word3;
-+} GMAC_TXDESC_T;
-+
-+/*
-+ * GMAC DMA Rx First Description Address Register
-+ * GMAC0 offset 0x8058
-+ * GMAC1 offset 0xC058
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8058 {
-+ unsigned int reserved : 3; // bit 2:0
-+ unsigned int rd_busy : 1; // bit 3 1-RxDMA busy; 0-RxDMA idle
-+ unsigned int rd_first_des_ptr : 28; // bit 31:4 first descriptor address
-+ } bits;
-+} GMAC_RXDMA_FIRST_DESC_T;
-+
-+/*
-+ * GMAC DMA Rx Current Description Address Register
-+ * GMAC0 offset 0x805C
-+ * GMAC1 offset 0xC05C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_805C {
-+ unsigned int reserved : 4; // bit 3:0
-+ unsigned int rd_curr_des_ptr : 28; // bit 31:4 current descriptor address
-+ } bits;
-+} GMAC_RXDMA_CURR_DESC_T;
-+
-+/*
-+ * GMAC DMA Rx Description Word 0 Register
-+ * GMAC0 offset 0x8060
-+ * GMAC1 offset 0xC060
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8060 {
-+ unsigned int buffer_size : 16; // bit 15:0 number of descriptors used for the current frame
-+ unsigned int desc_count : 6; // bit 21:16 number of descriptors used for the current frame
-+ unsigned int status : 4; // bit 24:22 Status of rx frame
-+ unsigned int chksum_status : 3; // bit 28:26 Check Sum Status
-+ unsigned int perr : 1; // bit 29 protocol error during processing this descriptor
-+ unsigned int derr : 1; // bit 30 data error during processing this descriptor
-+ unsigned int drop : 1; // bit 31 TOE/CIS Queue Full dropped packet to default queue
-+ } bits;
-+} GMAC_RXDESC_0_T;
-+
-+#define GMAC_RXDESC_0_T_derr BIT(30)
-+#define GMAC_RXDESC_0_T_perr BIT(29)
-+#define GMAC_RXDESC_0_T_chksum_status(x) BIT((x+26))
-+#define GMAC_RXDESC_0_T_status(x) BIT((x+22))
-+#define GMAC_RXDESC_0_T_desc_count(x) BIT((x+16))
-+
-+#define RX_CHKSUM_IP_UDP_TCP_OK 0
-+#define RX_CHKSUM_IP_OK_ONLY 1
-+#define RX_CHKSUM_NONE 2
-+#define RX_CHKSUM_IP_ERR_UNKNOWN 4
-+#define RX_CHKSUM_IP_ERR 5
-+#define RX_CHKSUM_TCP_UDP_ERR 6
-+#define RX_CHKSUM_NUM 8
-+
-+#define RX_STATUS_GOOD_FRAME 0
-+#define RX_STATUS_TOO_LONG_GOOD_CRC 1
-+#define RX_STATUS_RUNT_FRAME 2
-+#define RX_STATUS_SFD_NOT_FOUND 3
-+#define RX_STATUS_CRC_ERROR 4
-+#define RX_STATUS_TOO_LONG_BAD_CRC 5
-+#define RX_STATUS_ALIGNMENT_ERROR 6
-+#define RX_STATUS_TOO_LONG_BAD_ALIGN 7
-+#define RX_STATUS_RX_ERR 8
-+#define RX_STATUS_DA_FILTERED 9
-+#define RX_STATUS_BUFFER_FULL 10
-+#define RX_STATUS_NUM 16
-+
-+
-+/*
-+ * GMAC DMA Rx Description Word 1 Register
-+ * GMAC0 offset 0x8064
-+ * GMAC1 offset 0xC064
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct rxdesc_word1 {
-+ unsigned int byte_count : 16; // bit 15: 0 Rx Frame Byte Count
-+ unsigned int sw_id : 16; // bit 31:16 Software ID
-+ } bits;
-+} GMAC_RXDESC_1_T;
-+
-+/*
-+ * GMAC DMA Rx Description Word 2 Register
-+ * GMAC0 offset 0x8068
-+ * GMAC1 offset 0xC068
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int buf_adr;
-+} GMAC_RXDESC_2_T;
-+
-+#define RX_INSERT_NONE 0
-+#define RX_INSERT_1_BYTE 1
-+#define RX_INSERT_2_BYTE 2
-+#define RX_INSERT_3_BYTE 3
-+
-+#define RX_INSERT_BYTES RX_INSERT_2_BYTE
-+/*
-+ * GMAC DMA Rx Description Word 3 Register
-+ * GMAC0 offset 0x806C
-+ * GMAC1 offset 0xC06C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct rxdesc_word3 {
-+ unsigned int l3_offset : 8; // bit 7: 0 L3 data offset
-+ unsigned int l4_offset : 8; // bit 15: 8 L4 data offset
-+ unsigned int l7_offset : 8; // bit 23: 16 L7 data offset
-+ unsigned int dup_ack : 1; // bit 24 Duplicated ACK detected
-+ unsigned int abnormal : 1; // bit 25 abnormal case found
-+ unsigned int option : 1; // bit 26 IPV4 option or IPV6 extension header
-+ unsigned int out_of_seq : 1; // bit 27 Out of Sequence packet
-+ unsigned int ctrl_flag : 1; // bit 28 Control Flag is present
-+ unsigned int eofie : 1; // bit 29 End of frame interrupt enable
-+ unsigned int sof_eof : 2; // bit 31:30 11: only one, 10: first, 01: last, 00: linking
-+ } bits;
-+} GMAC_RXDESC_3_T;
-+
-+/*
-+ * GMAC Rx Descriptor
-+ */
-+typedef struct {
-+ GMAC_RXDESC_0_T word0;
-+ GMAC_RXDESC_1_T word1;
-+ GMAC_RXDESC_2_T word2;
-+ GMAC_RXDESC_3_T word3;
-+} GMAC_RXDESC_T;
-+
-+/*
-+ * GMAC Hash Engine Enable/Action Register 0 Offset Register
-+ * GMAC0 offset 0x8070
-+ * GMAC1 offset 0xC070
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8070 {
-+ unsigned int mr0hel : 6; // bit 5:0 match rule 0 hash entry size
-+ unsigned int mr0_action : 5; // bit 10:6 Matching Rule 0 action offset
-+ unsigned int reserved0 : 4; // bit 14:11
-+ unsigned int mr0en : 1; // bit 15 Enable Matching Rule 0
-+ unsigned int mr1hel : 6; // bit 21:16 match rule 1 hash entry size
-+ unsigned int mr1_action : 5; // bit 26:22 Matching Rule 1 action offset
-+ unsigned int timing : 3; // bit 29:27
-+ unsigned int reserved1 : 1; // bit 30
-+ unsigned int mr1en : 1; // bit 31 Enable Matching Rule 1
-+ } bits;
-+} GMAC_HASH_ENABLE_REG0_T;
-+
-+/*
-+ * GMAC Hash Engine Enable/Action Register 1 Offset Register
-+ * GMAC0 offset 0x8074
-+ * GMAC1 offset 0xC074
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8074 {
-+ unsigned int mr2hel : 6; // bit 5:0 match rule 2 hash entry size
-+ unsigned int mr2_action : 5; // bit 10:6 Matching Rule 2 action offset
-+ unsigned int reserved2 : 4; // bit 14:11
-+ unsigned int mr2en : 1; // bit 15 Enable Matching Rule 2
-+ unsigned int mr3hel : 6; // bit 21:16 match rule 3 hash entry size
-+ unsigned int mr3_action : 5; // bit 26:22 Matching Rule 3 action offset
-+ unsigned int reserved1 : 4; // bit 30:27
-+ unsigned int mr3en : 1; // bit 31 Enable Matching Rule 3
-+ } bits;
-+} GMAC_HASH_ENABLE_REG1_T;
-+
-+/*
-+ * GMAC Matching Rule Control Register 0
-+ * GMAC0 offset 0x8078
-+ * GMAC1 offset 0xC078
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8078 {
-+ unsigned int sprx : 8; // bit 7:0 Support Protocol Register 7:0
-+ unsigned int reserved2 : 4; // bit 11:8
-+ unsigned int tos_traffic : 1; // bit 12 IPV4 TOS or IPV6 Traffice Class
-+ unsigned int flow_lable : 1; // bit 13 IPV6 Flow label
-+ unsigned int ip_hdr_len : 1; // bit 14 IPV4 Header length
-+ unsigned int ip_version : 1; // bit 15 0: IPV4, 1: IPV6
-+ unsigned int reserved1 : 3; // bit 18:16
-+ unsigned int pppoe : 1; // bit 19 PPPoE Session ID enable
-+ unsigned int vlan : 1; // bit 20 VLAN ID enable
-+ unsigned int ether_type : 1; // bit 21 Ethernet type enable
-+ unsigned int sa : 1; // bit 22 MAC SA enable
-+ unsigned int da : 1; // bit 23 MAC DA enable
-+ unsigned int priority : 3; // bit 26:24 priority if multi-rules matched
-+ unsigned int port : 1; // bit 27 PORT ID matching enable
-+ unsigned int l7 : 1; // bit 28 L7 matching enable
-+ unsigned int l4 : 1; // bit 29 L4 matching enable
-+ unsigned int l3 : 1; // bit 30 L3 matching enable
-+ unsigned int l2 : 1; // bit 31 L2 matching enable
-+ } bits;
-+} GMAC_MRxCR0_T;
-+
-+#define MR_L2_BIT BIT(31)
-+#define MR_L3_BIT BIT(30)
-+#define MR_L4_BIT BIT(29)
-+#define MR_L7_BIT BIT(28)
-+#define MR_PORT_BIT BIT(27)
-+#define MR_PRIORITY_BIT BIT(26)
-+#define MR_DA_BIT BIT(23)
-+#define MR_SA_BIT BIT(22)
-+#define MR_ETHER_TYPE_BIT BIT(21)
-+#define MR_VLAN_BIT BIT(20)
-+#define MR_PPPOE_BIT BIT(19)
-+#define MR_IP_VER_BIT BIT(15)
-+#define MR_IP_HDR_LEN_BIT BIT(14)
-+#define MR_FLOW_LABLE_BIT BIT(13)
-+#define MR_TOS_TRAFFIC_BIT BIT(12)
-+#define MR_SPR_BIT(x) BIT(x)
-+#define MR_SPR_BITS 0xff
-+
-+/*
-+ * GMAC Matching Rule Control Register 1
-+ * GMAC0 offset 0x807C
-+ * GMAC1 offset 0xC07C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_807C {
-+ unsigned int l4_byte0_15 : 16; // bit 15: 0
-+ unsigned int dip_netmask : 7; // bit 22:16 Dest IP net mask, number of mask bits
-+ unsigned int dip : 1; // bit 23 Dest IP
-+ unsigned int sip_netmask : 7; // bit 30:24 Srce IP net mask, number of mask bits
-+ unsigned int sip : 1; // bit 31 Srce IP
-+ } bits;
-+} GMAC_MRxCR1_T;
-+
-+/*
-+ * GMAC Matching Rule Control Register 2
-+ * GMAC0 offset 0x8080
-+ * GMAC1 offset 0xC080
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8080 {
-+ unsigned int l7_byte0_23 : 24; // bit 23:0
-+ unsigned int l4_byte16_24 : 8; // bit 31: 24
-+ } bits;
-+} GMAC_MRxCR2_T;
-+
-+/*
-+ * GMAC Support registers
-+ * GMAC0 offset 0x80A8
-+ * GMAC1 offset 0xC0A8
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_80A8 {
-+ unsigned int protocol : 8; // bit 7:0 Supported protocol
-+ unsigned int swap : 3; // bit 10:8 Swap
-+ unsigned int reserved : 21; // bit 31:11
-+ } bits;
-+} GMAC_SPR_T;
-+
-+/*
-+ * GMAC_AHB_WEIGHT registers
-+ * GMAC0 offset 0x80C8
-+ * GMAC1 offset 0xC0C8
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_80C8 {
-+ unsigned int hash_weight : 5; // 4:0
-+ unsigned int rx_weight : 5; // 9:5
-+ unsigned int tx_weight : 5; // 14:10
-+ unsigned int pre_req : 5; // 19:15 Rx Data Pre Request FIFO Threshold
-+ unsigned int tqDV_threshold : 5; // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
-+ unsigned int reserved : 7; // 31:25
-+ } bits;
-+} GMAC_AHB_WEIGHT_T;
-+
-+/*
-+ * the register structure of GMAC
-+ */
-+
-+/*
-+ * GMAC RX FLTR
-+ * GMAC0 Offset 0xA00C
-+ * GMAC1 Offset 0xE00C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit1_000c {
-+ unsigned int unicast : 1; /* enable receive of unicast frames that are sent to STA address */
-+ unsigned int multicast : 1; /* enable receive of multicast frames that pass multicast filter */
-+ unsigned int broadcast : 1; /* enable receive of broadcast frames */
-+ unsigned int promiscuous : 1; /* enable receive of all frames */
-+ unsigned int error : 1; /* enable receive of all error frames */
-+ unsigned int : 27;
-+ } bits;
-+} GMAC_RX_FLTR_T;
-+
-+/*
-+ * GMAC Configuration 0
-+ * GMAC0 Offset 0xA018
-+ * GMAC1 Offset 0xE018
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit1_0018 {
-+ unsigned int dis_tx : 1; /* 0: disable transmit */
-+ unsigned int dis_rx : 1; /* 1: disable receive */
-+ unsigned int loop_back : 1; /* 2: transmit data loopback enable */
-+ unsigned int flow_ctrl : 1; /* 3: flow control also trigged by Rx queues */
-+ unsigned int adj_ifg : 4; /* 4-7: adjust IFG from 96+/-56 */
-+ unsigned int max_len : 3; /* 8-10 maximum receive frame length allowed */
-+ unsigned int dis_bkoff : 1; /* 11: disable back-off function */
-+ unsigned int dis_col : 1; /* 12: disable 16 collisions abort function */
-+ unsigned int sim_test : 1; /* 13: speed up timers in simulation */
-+ unsigned int rx_fc_en : 1; /* 14: RX flow control enable */
-+ unsigned int tx_fc_en : 1; /* 15: TX flow control enable */
-+ unsigned int rgmii_en : 1; /* 16: RGMII in-band status enable */
-+ unsigned int ipv4_rx_chksum : 1; /* 17: IPv4 RX Checksum enable */
-+ unsigned int ipv6_rx_chksum : 1; /* 18: IPv6 RX Checksum enable */
-+ unsigned int rx_tag_remove : 1; /* 19: Remove Rx VLAN tag */
-+ unsigned int rgmm_edge : 1; // 20
-+ unsigned int rxc_inv : 1; // 21
-+ unsigned int ipv6_exthdr_order : 1; // 22
-+ unsigned int rx_err_detect : 1; // 23
-+ unsigned int port0_chk_hwq : 1; // 24
-+ unsigned int port1_chk_hwq : 1; // 25
-+ unsigned int port0_chk_toeq : 1; // 26
-+ unsigned int port1_chk_toeq : 1; // 27
-+ unsigned int port0_chk_classq : 1; // 28
-+ unsigned int port1_chk_classq : 1; // 29
-+ unsigned int reserved : 2; // 31
-+ } bits;
-+} GMAC_CONFIG0_T;
-+
-+/*
-+ * GMAC Configuration 1
-+ * GMAC0 Offset 0xA01C
-+ * GMAC1 Offset 0xE01C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit1_001c {
-+ unsigned int set_threshold : 8; /* flow control set threshold */
-+ unsigned int rel_threshold : 8; /* flow control release threshold */
-+ unsigned int reserved : 16;
-+ } bits;
-+} GMAC_CONFIG1_T;
-+
-+#define GMAC_FLOWCTRL_SET_MAX 32
-+#define GMAC_FLOWCTRL_SET_MIN 0
-+#define GMAC_FLOWCTRL_RELEASE_MAX 32
-+#define GMAC_FLOWCTRL_RELEASE_MIN 0
-+
-+/*
-+ * GMAC Configuration 2
-+ * GMAC0 Offset 0xA020
-+ * GMAC1 Offset 0xE020
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit1_0020 {
-+ unsigned int set_threshold : 16; /* flow control set threshold */
-+ unsigned int rel_threshold : 16; /* flow control release threshold */
-+ } bits;
-+} GMAC_CONFIG2_T;
-+
-+/*
-+ * GMAC Configuration 3
-+ * GMAC0 Offset 0xA024
-+ * GMAC1 Offset 0xE024
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit1_0024 {
-+ unsigned int set_threshold : 16; /* flow control set threshold */
-+ unsigned int rel_threshold : 16; /* flow control release threshold */
-+ } bits;
-+} GMAC_CONFIG3_T;
-+
-+
-+/*
-+ * GMAC STATUS
-+ * GMAC0 Offset 0xA02C
-+ * GMAC1 Offset 0xE02C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit1_002c {
-+ unsigned int link : 1; /* link status */
-+ unsigned int speed : 2; /* link speed(00->2.5M 01->25M 10->125M) */
-+ unsigned int duplex : 1; /* duplex mode */
-+ unsigned int reserved : 1;
-+ unsigned int mii_rmii : 2; /* PHY interface type */
-+ unsigned int : 25;
-+ } bits;
-+} GMAC_STATUS_T;
-+
-+#define GMAC_SPEED_10 0
-+#define GMAC_SPEED_100 1
-+#define GMAC_SPEED_1000 2
-+
-+#define GMAC_PHY_MII 0
-+#define GMAC_PHY_GMII 1
-+#define GMAC_PHY_RGMII_100_10 2
-+#define GMAC_PHY_RGMII_1000 3
-+
-+/*
-+ * Queue Header
-+ * (1) TOE Queue Header
-+ * (2) Non-TOE Queue Header
-+ * (3) Interrupt Queue Header
-+ *
-+ * memory Layout
-+ * TOE Queue Header
-+ * 0x60003000 +---------------------------+ 0x0000
-+ * | TOE Queue 0 Header |
-+ * | 8 * 4 Bytes |
-+ * +---------------------------+ 0x0020
-+ * | TOE Queue 1 Header |
-+ * | 8 * 4 Bytes |
-+ * +---------------------------+ 0x0040
-+ * | ...... |
-+ * | |
-+ * +---------------------------+
-+ *
-+ * Non TOE Queue Header
-+ * 0x60002000 +---------------------------+ 0x0000
-+ * | Default Queue 0 Header |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+ 0x0008
-+ * | Default Queue 1 Header |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+ 0x0010
-+ * | Classification Queue 0 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+
-+ * | Classification Queue 1 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+ (n * 8 + 0x10)
-+ * | ... |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+ (13 * 8 + 0x10)
-+ * | Classification Queue 13 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+ 0x80
-+ * | Interrupt Queue 0 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+
-+ * | Interrupt Queue 1 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+
-+ * | Interrupt Queue 2 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+
-+ * | Interrupt Queue 3 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+
-+ *
-+ */
-+#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32)
-+#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
-+#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
-+#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10)
-+#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80)
-+#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8)
-+#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
-+/*
-+ * TOE Queue Header Word 0
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int base_size;
-+} TOE_QHDR0_T;
-+
-+#define TOE_QHDR0_BASE_MASK (~0x0f)
-+
-+/*
-+ * TOE Queue Header Word 1
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_qhdr1 {
-+ unsigned int rptr : 16; // bit 15:0
-+ unsigned int wptr : 16; // bit 31:16
-+ } bits;
-+} TOE_QHDR1_T;
-+
-+/*
-+ * TOE Queue Header Word 2
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_qhdr2 {
-+ unsigned int TotalPktSize : 17; // bit 16: 0 Total packet size
-+ unsigned int reserved : 7; // bit 23:17
-+ unsigned int dack : 1; // bit 24 1: Duplicated ACK
-+ unsigned int abn : 1; // bit 25 1: Abnormal case Found
-+ unsigned int tcp_opt : 1; // bit 26 1: Have TCP option
-+ unsigned int ip_opt : 1; // bit 27 1: have IPV4 option or IPV6 Extension header
-+ unsigned int sat : 1; // bit 28 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
-+ unsigned int osq : 1; // bit 29 1: out of sequence
-+ unsigned int ctl : 1; // bit 30 1: have control flag bits (except ack)
-+ unsigned int usd : 1; // bit 31 0: if no data assembled yet
-+ } bits;
-+} TOE_QHDR2_T;
-+
-+/*
-+ * TOE Queue Header Word 3
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int seq_num;
-+} TOE_QHDR3_T;
-+
-+/*
-+ * TOE Queue Header Word 4
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int ack_num;
-+} TOE_QHDR4_T;
-+
-+/*
-+ * TOE Queue Header Word 5
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_qhdr5 {
-+ unsigned int AckCnt : 16; // bit 15:0
-+ unsigned int SeqCnt : 16; // bit 31:16
-+ } bits;
-+} TOE_QHDR5_T;
-+
-+/*
-+ * TOE Queue Header Word 6
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_qhdr6 {
-+ unsigned int WinSize : 16; // bit 15:0
-+ unsigned int iq_num : 2; // bit 17:16
-+ unsigned int MaxPktSize : 14; // bit 31:18
-+ } bits;
-+} TOE_QHDR6_T;
-+
-+/*
-+ * TOE Queue Header Word 7
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_qhdr7 {
-+ unsigned int AckThreshold : 16; // bit 15:0
-+ unsigned int SeqThreshold : 16; // bit 31:16
-+ } bits;
-+} TOE_QHDR7_T;
-+
-+/*
-+ * TOE Queue Header
-+ */
-+typedef struct {
-+ TOE_QHDR0_T word0;
-+ TOE_QHDR1_T word1;
-+ TOE_QHDR2_T word2;
-+ TOE_QHDR3_T word3;
-+ TOE_QHDR4_T word4;
-+ TOE_QHDR5_T word5;
-+ TOE_QHDR6_T word6;
-+ TOE_QHDR7_T word7;
-+} TOE_QHDR_T;
-+
-+/*
-+ * NONTOE Queue Header Word 0
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int base_size;
-+} NONTOE_QHDR0_T;
-+
-+#define NONTOE_QHDR0_BASE_MASK (~0x0f)
-+
-+/*
-+ * NONTOE Queue Header Word 1
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_nonqhdr1 {
-+ unsigned int rptr : 16; // bit 15:0
-+ unsigned int wptr : 16; // bit 31:16
-+ } bits;
-+} NONTOE_QHDR1_T;
-+
-+/*
-+ * Non-TOE Queue Header
-+ */
-+typedef struct {
-+ NONTOE_QHDR0_T word0;
-+ NONTOE_QHDR1_T word1;
-+} NONTOE_QHDR_T;
-+
-+/*
-+ * Interrupt Queue Header Word 0
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_intrqhdr0 {
-+ unsigned int win_size : 16; // bit 15:0 Descriptor Ring Size
-+ unsigned int wptr : 16; // bit 31:16 Write Pointer where hw stopped
-+ } bits;
-+} INTR_QHDR0_T;
-+
-+/*
-+ * Interrupt Queue Header Word 1
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_intrqhdr1 {
-+ unsigned int TotalPktSize : 17; // bit 16: 0 Total packet size
-+ unsigned int tcp_qid : 8; // bit 24:17 TCP Queue ID
-+ unsigned int dack : 1; // bit 25 1: Duplicated ACK
-+ unsigned int abn : 1; // bit 26 1: Abnormal case Found
-+ unsigned int tcp_opt : 1; // bit 27 1: Have TCP option
-+ unsigned int ip_opt : 1; // bit 28 1: have IPV4 option or IPV6 Extension header
-+ unsigned int sat : 1; // bit 29 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
-+ unsigned int osq : 1; // bit 30 1: out of sequence
-+ unsigned int ctl : 1; // bit 31 1: have control flag bits (except ack)
-+ } bits;
-+} INTR_QHDR1_T;
-+
-+/*
-+ * Interrupt Queue Header Word 2
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int seq_num;
-+} INTR_QHDR2_T;
-+
-+/*
-+ * Interrupt Queue Header Word 3
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int ack_num;
-+} INTR_QHDR3_T;
-+
-+/*
-+ * Interrupt Queue Header Word 4
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_intrqhdr4 {
-+ unsigned int AckCnt : 16; // bit 15:0 Ack# change since last ack# intr.
-+ unsigned int SeqCnt : 16; // bit 31:16 Seq# change since last seq# intr.
-+ } bits;
-+} INTR_QHDR4_T;
-+
-+/*
-+ * Interrupt Queue Header
-+ */
-+typedef struct {
-+ INTR_QHDR0_T word0;
-+ INTR_QHDR1_T word1;
-+ INTR_QHDR2_T word2;
-+ INTR_QHDR3_T word3;
-+ INTR_QHDR4_T word4;
-+ unsigned int word5;
-+ unsigned int word6;
-+ unsigned int word7;
-+} INTR_QHDR_T;
-+
-+/*
-+ * GMAC private data
-+ */
-+typedef struct {
-+ void __iomem *rwptr_reg;
-+ unsigned int desc_base;
-+ unsigned int desc_base_dma;
-+ unsigned short finished_idx;
-+ struct sk_buff *tx_skb[TOE_GMAC_SWTXQ_DESC_NUM];
-+} GMAC_SWTXQ_T;
-+
-+struct gmac_private {
-+ struct phy_device *phydev;
-+ unsigned int port_id;
-+ void __iomem *base_addr;
-+ void __iomem *dma_base_addr;
-+ unsigned int swtxq_desc_base;
-+ GMAC_SWTXQ_T swtxq[TOE_SW_TXQ_NUM];
-+ NONTOE_QHDR_T *default_qhdr;
-+ unsigned int default_desc_base;
-+ dma_addr_t default_desc_base_dma;
-+ dma_addr_t swtxq_desc_base_dma;
-+ unsigned int flow_control_enable;
-+ unsigned int intr0_enabled;
-+ unsigned int intr1_enabled;
-+ unsigned int intr2_enabled;
-+ unsigned int intr3_enabled;
-+ unsigned int intr4_enabled;
-+ unsigned int intr0_selected;
-+ unsigned int intr1_selected;
-+ unsigned int intr2_selected;
-+ unsigned int intr3_selected;
-+ unsigned int intr4_selected;
-+};
-+
-+struct toe_private {
-+ void __iomem *global_base;
-+ struct net_device *net_dev[2];
-+ struct device *dev;
-+ struct work_struct freq_work;
-+ spinlock_t freeq_lock;
-+ unsigned int swfq_desc_base;
-+ unsigned int hwfq_desc_base;
-+ unsigned int hwfq_buf_base;
-+ dma_addr_t sw_freeq_desc_base_dma;
-+ dma_addr_t hw_freeq_desc_base_dma;
-+ dma_addr_t hwfq_buf_base_dma;
-+ dma_addr_t hwfq_buf_end_dma;
-+};
-+
-+#define GMAC_PORT0 0
-+#define GMAC_PORT1 1
-+
-+#endif /* _GMAC_SL351x_H */
---- /dev/null
-+++ b/drivers/net/gemini_negmac/Makefile
-@@ -0,0 +1,3 @@
-+obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC)+= gemini_negmac.o
-+
-+gemini_negmac-objs := gm_gmac.o
---- a/drivers/net/Kconfig
-+++ b/drivers/net/Kconfig
-@@ -100,6 +100,13 @@ config NET_FC
- adaptor below. You also should have said Y to "SCSI support" and
- "SCSI generic support".
-
-+config GEMINI_NET_ENGINE_GMAC
-+ tristate "Gemini Gigabit Ethernet support"
-+ depends on ARCH_GEMINI
-+ select PHYLIB
-+ help
-+ This driver supports Gemini TOE and NAT dual Gigabit Ethernet.
-+
- config MII
- tristate "Generic Media Independent Interface device support"
- help
---- a/drivers/net/Makefile
-+++ b/drivers/net/Makefile
-@@ -34,6 +34,7 @@ obj-$(CONFIG_ETRAX_ETHERNET) += cris/
- obj-$(CONFIG_NET_DSA) += dsa/
- obj-$(CONFIG_ETHERNET) += ethernet/
- obj-$(CONFIG_FDDI) += fddi/
-+obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC) += gemini_negmac/
- obj-$(CONFIG_HIPPI) += hippi/
- obj-$(CONFIG_HAMRADIO) += hamradio/
- obj-$(CONFIG_IRDA) += irda/
+++ /dev/null
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -13,6 +13,7 @@
- #define __GEMINI_COMMON_H__
-
- struct mtd_partition;
-+struct gemini_gmac_platform_data;
-
- extern void gemini_map_io(void);
- extern void gemini_init_irq(void);
-@@ -26,6 +27,7 @@ extern int platform_register_pflash(unsi
- struct mtd_partition *parts,
- unsigned int nr_parts);
- extern int platform_register_watchdog(void);
-+extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
-
- extern void gemini_restart(char mode, const char *cmd);
-
---- a/arch/arm/mach-gemini/devices.c
-+++ b/arch/arm/mach-gemini/devices.c
-@@ -17,6 +17,7 @@
- #include <mach/irqs.h>
- #include <mach/hardware.h>
- #include <mach/global_reg.h>
-+#include <mach/gmac.h>
- #include "common.h"
-
- static struct plat_serial8250_port serial_platform_data[] = {
-@@ -134,3 +135,53 @@ int __init platform_register_watchdog(vo
- {
- return platform_device_register(&wdt_device);
- }
-+
-+static struct resource gmac_resources[] = {
-+ {
-+ .start = 0x60000000,
-+ .end = 0x6000ffff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IRQ_GMAC0,
-+ .end = IRQ_GMAC0,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+ {
-+ .start = IRQ_GMAC1,
-+ .end = IRQ_GMAC1,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 gmac_dmamask = 0xffffffffUL;
-+
-+static struct platform_device ethernet_device = {
-+ .name = "gemini-gmac",
-+ .id = 0,
-+ .dev = {
-+ .dma_mask = &gmac_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+ .num_resources = ARRAY_SIZE(gmac_resources),
-+ .resource = gmac_resources,
-+};
-+
-+int __init platform_register_ethernet(struct gemini_gmac_platform_data *pdata)
-+{
-+ unsigned int reg;
-+
-+ reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
-+ reg &= ~(GMAC_GMII | GMAC_1_ENABLE);
-+
-+ if (pdata->bus_id[1])
-+ reg |= GMAC_1_ENABLE;
-+ else if (pdata->interface[0] == PHY_INTERFACE_MODE_GMII)
-+ reg |= GMAC_GMII;
-+
-+ __raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
-+
-+ ethernet_device.dev.platform_data = pdata;
-+
-+ return platform_device_register(ðernet_device);
-+}
+++ /dev/null
---- a/arch/arm/mach-gemini/board-wbd111.c
-+++ b/arch/arm/mach-gemini/board-wbd111.c
-@@ -22,9 +22,29 @@
- #include <asm/mach/arch.h>
- #include <asm/mach/time.h>
-
-+#include <mach/gmac.h>
-
- #include "common.h"
-
-+static struct mdio_gpio_platform_data wbd111_mdio = {
-+ .mdc = 22,
-+ .mdio = 21,
-+ .phy_mask = ~(1 << 1),
-+};
-+
-+static struct platform_device wbd111_phy_device = {
-+ .name = "mdio-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &wbd111_mdio,
-+ },
-+};
-+
-+static struct gemini_gmac_platform_data gmac_data = {
-+ .bus_id[0] = "gpio-0:01",
-+ .interface[0] = PHY_INTERFACE_MODE_MII,
-+};
-+
- static struct gpio_keys_button wbd111_keys[] = {
- {
- .code = KEY_SETUP,
-@@ -123,6 +143,8 @@ static void __init wbd111_init(void)
- platform_device_register(&wbd111_keys_device);
- platform_register_rtc();
- platform_register_watchdog();
-+ platform_device_register(&wbd111_phy_device);
-+ platform_register_ethernet(&gmac_data);
- }
-
- MACHINE_START(WBD111, "Wiliboard WBD-111")
+++ /dev/null
---- a/arch/arm/mach-gemini/board-wbd222.c
-+++ b/arch/arm/mach-gemini/board-wbd222.c
-@@ -22,9 +22,31 @@
- #include <asm/mach/arch.h>
- #include <asm/mach/time.h>
-
-+#include <mach/gmac.h>
-
- #include "common.h"
-
-+static struct mdio_gpio_platform_data wbd222_mdio = {
-+ .mdc = 22,
-+ .mdio = 21,
-+ .phy_mask = ~((1 << 1) | (1 << 3)),
-+};
-+
-+static struct platform_device wbd222_phy_device = {
-+ .name = "mdio-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &wbd222_mdio,
-+ },
-+};
-+
-+static struct gemini_gmac_platform_data gmac_data = {
-+ .bus_id[0] = "gpio-0:01",
-+ .interface[0] = PHY_INTERFACE_MODE_MII,
-+ .bus_id[1] = "gpio-0:03",
-+ .interface[1] = PHY_INTERFACE_MODE_MII,
-+};
-+
- static struct gpio_keys_button wbd222_keys[] = {
- {
- .code = KEY_SETUP,
-@@ -123,6 +145,8 @@ static void __init wbd222_init(void)
- platform_device_register(&wbd222_keys_device);
- platform_register_rtc();
- platform_register_watchdog();
-+ platform_device_register(&wbd222_phy_device);
-+ platform_register_ethernet(&gmac_data);
- }
-
- MACHINE_START(WBD222, "Wiliboard WBD-222")
+++ /dev/null
---- a/arch/arm/mach-gemini/board-rut1xx.c
-+++ b/arch/arm/mach-gemini/board-rut1xx.c
-@@ -15,13 +15,35 @@
- #include <linux/input.h>
- #include <linux/gpio_keys.h>
- #include <linux/sizes.h>
-+#include <linux/mdio-gpio.h>
-
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/time.h>
-
-+#include <mach/gmac.h>
-+
- #include "common.h"
-
-+static struct mdio_gpio_platform_data rut1xx_mdio = {
-+ .mdc = 22,
-+ .mdio = 21,
-+ .phy_mask = ~(1 << 1),
-+};
-+
-+static struct platform_device rut1xx_phy_device = {
-+ .name = "mdio-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &rut1xx_mdio,
-+ },
-+};
-+
-+static struct gemini_gmac_platform_data gmac_data = {
-+ .bus_id[0] = "gpio-0:01",
-+ .interface[0] = PHY_INTERFACE_MODE_MII,
-+};
-+
- static struct gpio_keys_button rut1xx_keys[] = {
- {
- .code = KEY_SETUP,
-@@ -81,6 +103,8 @@ static void __init rut1xx_init(void)
- platform_device_register(&rut1xx_keys_device);
- platform_register_rtc();
- platform_register_watchdog();
-+ platform_device_register(&rut1xx_phy_device);
-+ platform_register_ethernet(&gmac_data);
- }
-
- MACHINE_START(RUT100, "Teltonika RUT100")
+++ /dev/null
---- /dev/null
-+++ b/drivers/usb/host/ehci-fotg2xx.c
-@@ -0,0 +1,459 @@
-+/*
-+ * EHCI Host Controller driver
-+ *
-+ * Copyright (C) 2006 Sony Computer Entertainment Inc.
-+ * Copyright 2006 Sony Corp.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License.
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <mach/hardware.h>
-+
-+#define otg_set(port, bits) writel(readl(hcd->regs + port) | bits, hcd->regs + port)
-+
-+#define otg_clear(port, bits) writel(readl(hcd->regs + port) & ~bits, hcd->regs + port)
-+
-+#define GLOBAL_ISR 0xC0
-+#define GLOBAL_ICR 0xC4
-+
-+#define HCD_MISC 0x40
-+
-+#define OTGC_SCR 0x80
-+#define OTGC_INT_EN 0x88
-+
-+#define GLOBAL_INT_POLARITY (1 << 3)
-+#define GLOBAL_INT_MASK_HC (1 << 2)
-+#define GLOBAL_INT_MASK_OTG (1 << 1)
-+#define GLOBAL_INT_MASK_DEV (1 << 0)
-+
-+#define OTGC_SCR_ID (1 << 21)
-+#define OTGC_SCR_CROLE (1 << 20)
-+#define OTGC_SCR_VBUS_VLD (1 << 19)
-+#define OTGC_SCR_A_SRP_RESP_TYPE (1 << 8)
-+#define OTGC_SCR_A_SRP_DET_EN (1 << 7)
-+#define OTGC_SCR_A_SET_B_HNP_EN (1 << 6)
-+#define OTGC_SCR_A_BUS_DROP (1 << 5)
-+#define OTGC_SCR_A_BUS_REQ (1 << 4)
-+
-+#define OTGC_INT_APLGRMV (1 << 12)
-+#define OTGC_INT_BPLGRMV (1 << 11)
-+#define OTGC_INT_OVC (1 << 10)
-+#define OTGC_INT_IDCHG (1 << 9)
-+#define OTGC_INT_RLCHG (1 << 8)
-+#define OTGC_INT_AVBUSERR (1 << 5)
-+#define OTGC_INT_ASRPDET (1 << 4)
-+#define OTGC_INT_BSRPDN (1 << 0)
-+
-+#define OTGC_INT_A_TYPE (OTGC_INT_ASRPDET|OTGC_INT_AVBUSERR|OTGC_INT_OVC|OTGC_INT_RLCHG|OTGC_INT_IDCHG|OTGC_INT_APLGRMV)
-+#define OTGC_INT_B_TYPE (OTGC_INT_AVBUSERR|OTGC_INT_OVC|OTGC_INT_RLCHG|OTGC_INT_IDCHG)
-+
-+static void fotg2xx_otgc_role_change(struct usb_hcd *hcd);
-+
-+static void fotg2xx_otgc_init(struct usb_hcd *hcd)
-+{
-+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
-+ unsigned int reg;
-+
-+ reg = __raw_readl(hcd->regs + OTGC_SCR);
-+ ehci_info(ehci, "role detected: %s, ",
-+ (reg & OTGC_SCR_CROLE) ? "Peripheral" : "Host");
-+
-+ if (reg & OTGC_SCR_ID)
-+ ehci_info(ehci, "B-Device (may be unsupported!)\n");
-+ else
-+ ehci_info(ehci, "A-Device\n");
-+
-+ /* Enable the SRP detect */
-+ reg &= ~OTGC_SCR_A_SRP_RESP_TYPE;
-+ __raw_writel(reg, hcd->regs + OTGC_SCR);
-+
-+ reg = __raw_readl(hcd->regs + OTGC_INT_EN);
-+ /* clear INT B: bits AVBUSERR | OVC | RLCHG | IDCHG */
-+ reg &= ~OTGC_INT_B_TYPE;
-+ /* set INT A: bits ASRPDET | AVBUSERR | OVC | RLCHG | IDCHG | APLGRMV */
-+ reg |= OTGC_INT_A_TYPE;
-+ __raw_writel(reg, hcd->regs + OTGC_INT_EN);
-+
-+ reg = __raw_readl(hcd->regs + GLOBAL_ICR);
-+ reg &= ~GLOBAL_INT_MASK_OTG;
-+ __raw_writel(reg, hcd->regs + GLOBAL_ICR);
-+
-+ /* setup MISC register, fixes timing problems */
-+ reg = __raw_readl(hcd->regs + HCD_MISC);
-+ reg |= 0xD;
-+ __raw_writel(reg, hcd->regs + HCD_MISC);
-+
-+ fotg2xx_otgc_role_change(hcd);
-+}
-+
-+static void fotg2xx_otgh_close(struct usb_hcd *hcd)
-+{
-+ unsigned int reg;
-+
-+ /* <1>.Enable Interrupt Mask */
-+ reg = __raw_readl(hcd->regs + GLOBAL_ICR);
-+ reg |= GLOBAL_INT_MASK_HC;
-+ __raw_writel(reg, hcd->regs + GLOBAL_ICR);
-+
-+ /* <2>.Clear the Interrupt status */
-+ reg = __raw_readl(hcd->regs + 0x18);
-+ reg &= 0x0000003F;
-+ __raw_writel(reg, hcd->regs + 0x14);
-+}
-+
-+static void fotg2xx_otgh_open(struct usb_hcd *hcd)
-+{
-+ unsigned int reg;
-+
-+ reg = __raw_readl(hcd->regs + OTGC_SCR);
-+ reg &= ~OTGC_SCR_A_SRP_DET_EN;
-+ __raw_writel(reg, hcd->regs + OTGC_SCR);
-+
-+ reg = __raw_readl(hcd->regs + GLOBAL_ICR);
-+ reg &= ~GLOBAL_INT_MASK_HC;
-+ __raw_writel(reg, hcd->regs + GLOBAL_ICR);
-+}
-+
-+/* change to host role */
-+static void fotg2xx_otgc_role_change(struct usb_hcd *hcd)
-+{
-+
-+ /* clear A_SET_B_HNP_EN */
-+ otg_clear(0x80, BIT(6));
-+
-+ /*** Enable VBUS driving */
-+ if (readl(hcd->regs + 0x80) & BIT(19))
-+ printk(KERN_INFO "VBUS already enabled\n");
-+ else {
-+ int cnt = 0;
-+
-+ /* clear A_BUS_DROP */
-+ otg_clear(0x80, BIT(5));
-+
-+ /* set A_BUS_REQ */
-+ otg_set(0x80, BIT(4));
-+
-+ /* set global bus reg to VBUS on */
-+ writel(readl(IO_ADDRESS(0x40000000) + 0x30) | ((BIT(21)|BIT(22))),
-+ IO_ADDRESS(0x40000000) + 0x30);
-+
-+ if (readl(hcd->regs + 0x80) & (1<<19)) {
-+ printk(KERN_INFO "Waiting for VBus");
-+ while (!(readl(hcd->regs + 0x80) & (1<<19)) && (cnt < 80)) {
-+ printk(KERN_CONT ".");
-+ cnt++;
-+ }
-+ printk(KERN_CONT "\n");
-+ } else
-+ printk(KERN_INFO "VBUS enabled.\n");
-+
-+ mdelay(1);
-+ }
-+ fotg2xx_otgh_open(hcd);
-+}
-+
-+static int fotg2xx_ehci_hc_reset(struct usb_hcd *hcd)
-+{
-+ int result;
-+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
-+
-+ ehci->caps = hcd->regs;
-+ ehci->regs = hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
-+
-+ dbg_hcs_params(ehci, "reset");
-+ dbg_hcc_params(ehci, "reset");
-+
-+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
-+ hcd->has_tt = 1;
-+
-+ result = ehci_halt(ehci);
-+ if (result)
-+ return result;
-+
-+ return ehci_init(hcd);
-+}
-+
-+/*
-+ * Name: OTGC_INT_ISR
-+ * Description:This interrupt service routine belongs to the OTG-Controller
-+ * <1>.Check for ID_Change
-+ * <2>.Check for RL_Change
-+ * <3>.Error Detect
-+ * Input: wINTStatus
-+ * Output:void
-+ */
-+void fotg2xx_int_isr(struct usb_hcd *hcd, u32 wINTStatus)
-+{
-+ /* <1>.Check for ID_Change */
-+ if (wINTStatus&OTGC_INT_IDCHG) {
-+ if ((readl(hcd->regs + 0x80) & BIT(21)) != 0)
-+ fotg2xx_otgc_init(hcd); /* Change to B Type */
-+ else
-+ fotg2xx_otgc_init(hcd); /* Change to A Type */
-+
-+ return;
-+ }
-+
-+ /* <2>.Check for RL_Change */
-+ if (wINTStatus&OTGC_INT_RLCHG)
-+ fotg2xx_otgc_role_change(hcd);
-+
-+ /* <3>.Error Detect */
-+ if (wINTStatus&OTGC_INT_AVBUSERR)
-+ printk(KERN_ERR "VBus error!\n");
-+
-+ if (wINTStatus&OTGC_INT_OVC)
-+ printk(KERN_WARNING "Overcurrent detected!\n");
-+
-+ /* <3>.Check for Type-A/Type-B Interrupt */
-+ if ((readl(hcd->regs + 0x80) & BIT(21)) == 0) { /*For Type-A Interrupt*/
-+ if (wINTStatus & (OTGC_INT_A_TYPE | OTGC_INT_ASRPDET)) {
-+ /* <1>.SRP detected => then set global variable */
-+ printk(KERN_WARNING "SRP detected, but not implemented!\n");
-+
-+#if 0
-+ u32 wTempCounter;
-+ /* <2>.Turn on the V Bus */
-+ pFTC_OTG->otg.state = OTG_STATE_A_WAIT_VRISE;
-+ OTGC_enable_vbus_draw_storlink(1);
-+ pFTC_OTG->otg.state = OTG_STATE_A_HOST;
-+ /* <3>.Should waiting for Device-Connect Wait 300ms */
-+ INFO(pFTC_OTG, ">>> OTG-A Waiting for OTG-B Connect,\n");
-+ wTempCounter = 0;
-+ while (mwHost20_PORTSC_ConnectStatus_Rd() == 0) {
-+ mdelay(1);
-+ wTempCounter++;
-+ /* Waiting for 300 ms */
-+ if (wTempCounter > 300) {
-+ mdwOTGC_Control_A_SRP_DET_EN_Clr();
-+ INFO(pFTC_OTG, ">>> OTG-B do not connect under 300 ms...\n");
-+ break;
-+ }
-+ }
-+ /* <4>.If Connect => issue quick Reset */
-+ if (mwHost20_PORTSC_ConnectStatus_Rd() > 0) {
-+ mdelay(300); /* For OPT-A Test */
-+ OTGH_host_quick_Reset();
-+ OTGH_Open();
-+ pFTC_OTG->otg.host->A_Disable_Set_Feature_HNP = 0;
-+ }
-+#endif
-+ }
-+ } else { /* For Type-B Interrupt */
-+ BUG();
-+ }
-+}
-+
-+static irqreturn_t fotg2xx_ehci_irq(int irq, void *devid)
-+{
-+ struct usb_hcd *hcd = devid;
-+ u32 val;
-+
-+ /* OTG Interrupt Status Register */
-+ val = readl(hcd->regs + 0x84);
-+
-+ /* OTG stuff */
-+ if (val) {
-+ /* supposed to do "INT STS Clr" - XXX */
-+ writel(readl(hcd->regs + 0x84) | val, hcd->regs + 0x84);
-+
-+ fotg2xx_int_isr(hcd, val);
-+
-+ /* supposed to do "INT STS Clr" - XXX */
-+ writel(readl(hcd->regs + 0x84) | val, hcd->regs + 0x84);
-+
-+ return IRQ_HANDLED;
-+ }
-+
-+ if ((readl(hcd->regs + 0x80) & BIT(20)) == 0) { /* Role is HOST */
-+ if (readl(hcd->regs + 0xC0) & BIT(2)) { /* INT STS HOST */
-+ /* leave this for ehci irq handler */
-+ return IRQ_NONE;
-+ }
-+ } else
-+ printk(KERN_WARNING
-+ "received irq for peripheral - don't know what to do!\n");
-+
-+ /* do not call the ehci irq handler */
-+ return IRQ_HANDLED;
-+}
-+
-+static int fotg2xx_ehci_run(struct usb_hcd *hcd)
-+{
-+ int retval;
-+
-+ retval = ehci_run(hcd);
-+
-+ fotg2xx_otgh_close(hcd);
-+ fotg2xx_otgc_init(hcd);
-+
-+ return retval;
-+}
-+
-+static const struct hc_driver fotg2xx_ehci_hc_driver = {
-+ .description = hcd_name,
-+ .product_desc = "FOTG2XX EHCI Host Controller",
-+ .hcd_priv_size = sizeof(struct ehci_hcd),
-+ .irq = ehci_irq,
-+ .flags = HCD_MEMORY | HCD_USB2,
-+ .reset = fotg2xx_ehci_hc_reset,
-+ .start = fotg2xx_ehci_run,
-+ .stop = ehci_stop,
-+ .shutdown = ehci_shutdown,
-+
-+ .urb_enqueue = ehci_urb_enqueue,
-+ .urb_dequeue = ehci_urb_dequeue,
-+ .endpoint_disable = ehci_endpoint_disable,
-+ .endpoint_reset = ehci_endpoint_reset,
-+
-+ .get_frame_number = ehci_get_frame,
-+
-+ .hub_status_data = ehci_hub_status_data,
-+ .hub_control = ehci_hub_control,
-+#if defined(CONFIG_PM)
-+ .bus_suspend = ehci_bus_suspend,
-+ .bus_resume = ehci_bus_resume,
-+#endif
-+ .relinquish_port = ehci_relinquish_port,
-+ .port_handed_over = ehci_port_handed_over,
-+
-+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
-+};
-+
-+static int fotg2xx_ehci_probe(struct platform_device *pdev)
-+{
-+ const struct hc_driver *driver = &fotg2xx_ehci_hc_driver;
-+ struct usb_hcd *hcd;
-+ struct resource *res;
-+ int irq;
-+ int retval;
-+
-+ pr_debug("initializing FOTG2XX-SOC USB Controller\n");
-+
-+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+ if (!res) {
-+ dev_err(&pdev->dev,
-+ "Found HC with no IRQ. Check %s setup!\n",
-+ dev_name(&pdev->dev));
-+ return -ENODEV;
-+ }
-+
-+ irq = res->start;
-+
-+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
-+ if (!hcd) {
-+ retval = -ENOMEM;
-+ goto err1;
-+ }
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(&pdev->dev,
-+ "Found HC with no register addr. Check %s setup!\n",
-+ dev_name(&pdev->dev));
-+ retval = -ENODEV;
-+ goto err2;
-+ }
-+
-+ hcd->rsrc_start = res->start;
-+ hcd->rsrc_len = res->end - res->start + 1;
-+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
-+ driver->description)) {
-+ dev_dbg(&pdev->dev, "controller already in use\n");
-+ retval = -EBUSY;
-+ goto err2;
-+ }
-+
-+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
-+ if (hcd->regs == NULL) {
-+ dev_dbg(&pdev->dev, "error mapping memory\n");
-+ retval = -EFAULT;
-+ goto err3;
-+ }
-+
-+
-+ /* set global reg to mini-A host */
-+ writel(readl(IO_ADDRESS(0x40000000) + 0x30) & ~(BIT(30)|BIT(29)),
-+ IO_ADDRESS(0x40000000) + 0x30);
-+
-+ /* USB0&USB1 - VBUS off */
-+ writel(readl(IO_ADDRESS(0x40000000) + 0x30) & ~(BIT(21)|BIT(22)),
-+ IO_ADDRESS(0x40000000) + 0x30);
-+
-+ if ((readl(hcd->regs) == 0x01000010) &&
-+ (readl(hcd->regs + 4) == 0x00000001) &&
-+ (readl(hcd->regs + 8) == 0x00000006)) {
-+ dev_info(&pdev->dev,
-+ "Found Faraday OTG 2XX controller (base = 0x%08lX)\n",
-+ (unsigned long) hcd->rsrc_start);
-+ } else {
-+ dev_err(&pdev->dev, "fotg2xx id mismatch: found %d.%d.%d\n",
-+ readl(hcd->regs + 0x00),
-+ readl(hcd->regs + 0x04),
-+ readl(hcd->regs + 0x08));
-+ retval = -ENODEV;
-+ goto err4;
-+ }
-+
-+ platform_set_drvdata(pdev, hcd);
-+
-+ /* mask interrupts - peripheral, otg, host, hi-active (bits 0,1,2,3) */
-+ otg_set(0xc4, BIT(3)); /* hi active */
-+
-+ otg_set(0xc4, BIT(2)); /* host */
-+ otg_set(0xc4, BIT(1)); /* otg */
-+ otg_set(0xc4, BIT(0)); /* peripheral */
-+
-+ /* register additional interrupt - here we check otg status */
-+ if ((request_irq(irq, &fotg2xx_ehci_irq, IRQF_SHARED | IRQF_DISABLED,
-+ hcd->irq_descr, hcd)) != 0) {
-+ dev_dbg(&pdev->dev, "error requesting irq %d\n", irq);
-+ retval = -EFAULT;
-+ goto err4;
-+ }
-+
-+ retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
-+ if (retval != 0)
-+ goto err4;
-+ return retval;
-+
-+err4:
-+ iounmap(hcd->regs);
-+err3:
-+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-+err2:
-+ usb_put_hcd(hcd);
-+err1:
-+ dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
-+ return retval;
-+}
-+
-+/* may be called without controller electrically present */
-+/* may be called with controller, bus, and devices active */
-+
-+int fotg2xx_ehci_remove(struct platform_device *pdev)
-+{
-+ struct usb_hcd *hcd =
-+ (struct usb_hcd *)platform_get_drvdata(pdev);
-+
-+ usb_remove_hcd(hcd);
-+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-+ iounmap(hcd->regs);
-+ usb_put_hcd(hcd);
-+ platform_set_drvdata(pdev, NULL);
-+
-+ return 0;
-+}
-+
-+MODULE_ALIAS("platform:ehci-fotg2xx");
-+
-+static struct platform_driver fotg2xx_ehci_driver = {
-+ .probe = fotg2xx_ehci_probe,
-+ .remove = fotg2xx_ehci_remove,
-+ .driver = {
-+ .name = "ehci-fotg2xx",
-+ },
-+};
---- a/drivers/usb/host/ehci.h
-+++ b/drivers/usb/host/ehci.h
-@@ -603,7 +603,12 @@ static inline unsigned int
- ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
- {
- if (ehci_is_TDI(ehci)) {
-+#ifdef CONFIG_ARCH_GEMINI
-+ portsc = readl(ehci_to_hcd(ehci)->regs + 0x80);
-+ switch ((portsc>>22)&3) {
-+#else
- switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
-+#endif
- case 0:
- return 0;
- case 1:
---- a/drivers/usb/host/ehci-hcd.c
-+++ b/drivers/usb/host/ehci-hcd.c
-@@ -204,10 +204,12 @@ static int ehci_halt (struct ehci_hcd *e
- * This routine gets called during probe before ehci->command
- * has been initialized, so we can't rely on its value.
- */
-+#ifndef CONFIG_ARCH_GEMINI
- ehci->command &= ~CMD_RUN;
- temp = ehci_readl(ehci, &ehci->regs->command);
- temp &= ~(CMD_RUN | CMD_IAAD);
- ehci_writel(ehci, temp, &ehci->regs->command);
-+#endif
-
- spin_unlock_irq(&ehci->lock);
- synchronize_irq(ehci_to_hcd(ehci)->irq);
-@@ -257,13 +259,17 @@ static int ehci_reset (struct ehci_hcd *
- if (ehci->has_hostpc) {
- ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
- &ehci->regs->usbmode_ex);
-+#ifndef CONFIG_ARCH_GEMINI
- ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
-+#endif
- }
- if (retval)
- return retval;
-
-+#ifndef CONFIG_ARCH_GEMINI
- if (ehci_is_TDI(ehci))
- tdi_reset (ehci);
-+#endif
-
- if (ehci->debug)
- dbgp_external_startup(ehci_to_hcd(ehci));
-@@ -341,11 +347,14 @@ static void ehci_silence_controller(stru
- ehci->rh_state = EHCI_RH_HALTED;
- ehci_turn_off_all_ports(ehci);
-
-+#ifndef CONFIG_ARCH_GEMINI
- /* make BIOS/etc use companion controller during reboot */
- ehci_writel(ehci, 0, &ehci->regs->configured_flag);
-
- /* unblock posted writes */
- ehci_readl(ehci, &ehci->regs->configured_flag);
-+#endif
-+
- spin_unlock_irq(&ehci->lock);
- }
-
-@@ -603,7 +612,9 @@ static int ehci_run (struct usb_hcd *hcd
- // Philips, Intel, and maybe others need CMD_RUN before the
- // root hub will detect new devices (why?); NEC doesn't
- ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
-+#ifndef CONFIG_ARCH_GEMINI
- ehci->command |= CMD_RUN;
-+#endif
- ehci_writel(ehci, ehci->command, &ehci->regs->command);
- dbg_cmd (ehci, "init", ehci->command);
-
-@@ -623,9 +634,11 @@ static int ehci_run (struct usb_hcd *hcd
- */
- down_write(&ehci_cf_port_reset_rwsem);
- ehci->rh_state = EHCI_RH_RUNNING;
-+#ifndef CONFIG_ARCH_GEMINI
- ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
- ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
- msleep(5);
-+#endif /* !CONFIG_ARCH_GEMINI */
- up_write(&ehci_cf_port_reset_rwsem);
- ehci->last_periodic_enable = ktime_get_real();
-
-@@ -1228,6 +1241,11 @@ MODULE_DESCRIPTION(DRIVER_DESC);
- MODULE_AUTHOR (DRIVER_AUTHOR);
- MODULE_LICENSE ("GPL");
-
-+#ifdef CONFIG_ARCH_GEMINI
-+#include "ehci-fotg2xx.c"
-+#define PLATFORM_DRIVER fotg2xx_ehci_driver
-+#endif
-+
- #ifdef CONFIG_USB_EHCI_FSL
- #include "ehci-fsl.c"
- #define PLATFORM_DRIVER ehci_fsl_driver
---- a/drivers/usb/host/ehci-hub.c
-+++ b/drivers/usb/host/ehci-hub.c
-@@ -914,6 +914,12 @@ static int ehci_hub_control (
- /* see what we found out */
- temp = check_reset_complete (ehci, wIndex, status_reg,
- ehci_readl(ehci, status_reg));
-+#ifdef CONFIG_ARCH_GEMINI
-+ /* restart schedule */
-+ ehci_writel(ehci, ehci_readl(ehci, &ehci->regs->command) | CMD_RUN, &ehci->regs->command);
-+
-+// hcd->state = HC_STATE_RUNNING;
-+#endif
- }
-
- if (!(temp & (PORT_RESUME|PORT_RESET))) {
---- a/drivers/usb/Kconfig
-+++ b/drivers/usb/Kconfig
-@@ -47,6 +47,7 @@ config USB_ARCH_HAS_EHCI
- default y if MICROBLAZE
- default y if SPARC_LEON
- default y if ARCH_MMP
-+ default y if ARCH_GEMINI
- default y if MACH_LOONGSON1
- default y if PLAT_ORION
- default PCI
-@@ -96,7 +97,7 @@ config USB
- traditional PC serial port. The bus supplies power to peripherals
- and allows for hot swapping. Up to 127 USB peripherals can be
- connected to a single USB host in a tree structure.
--
-+
- The USB host is the root of the tree, the peripherals are the
- leaves and the inner nodes are special USB devices called hubs.
- Most PCs now have USB host ports, used to connect peripherals
---- a/include/linux/usb/ehci_def.h
-+++ b/include/linux/usb/ehci_def.h
-@@ -111,6 +111,7 @@ struct ehci_regs {
- /* ASYNCLISTADDR: offset 0x18 */
- u32 async_next; /* address of next async queue head */
-
-+#ifndef CONFIG_ARCH_GEMINI
- u32 reserved1[2];
-
- /* TXFILLTUNING: offset 0x24 */
-@@ -118,6 +119,7 @@ struct ehci_regs {
- #define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
-
- u32 reserved2[6];
-+#endif /* !CONFIG_ARCH_GEMINI */
-
- /* CONFIGFLAG: offset 0x40 */
- u32 configured_flag;
+++ /dev/null
---- a/arch/arm/mach-gemini/devices.c
-+++ b/arch/arm/mach-gemini/devices.c
-@@ -185,3 +185,62 @@ int __init platform_register_ethernet(st
-
- return platform_device_register(ðernet_device);
- }
-+
-+static u64 usb0_dmamask = DMA_BIT_MASK(32);
-+static struct resource usb0_resources[] = {
-+ {
-+ .start = 0x68000000,
-+ .end = 0x68000fff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IRQ_USB0,
-+ .end = IRQ_USB0,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 usb1_dmamask = DMA_BIT_MASK(32);
-+static struct resource usb1_resources[] = {
-+ {
-+ .start = 0x69000000,
-+ .end = 0x69000fff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IRQ_USB1,
-+ .end = IRQ_USB1,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct platform_device usb_device[] = {
-+ {
-+ .name = "ehci-fotg2xx",
-+ .id = 0,
-+ .dev = {
-+ .dma_mask = &usb0_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+ .num_resources = ARRAY_SIZE(usb0_resources),
-+ .resource = usb0_resources,
-+ },
-+ {
-+ .name = "ehci-fotg2xx",
-+ .id = 1,
-+ .dev = {
-+ .dma_mask = &usb1_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+ .num_resources = ARRAY_SIZE(usb1_resources),
-+ .resource = usb1_resources,
-+ },
-+};
-+
-+int __init platform_register_usb(unsigned int id)
-+{
-+ if (id > 1)
-+ return -EINVAL;
-+
-+ return platform_device_register(&usb_device[id]);
-+}
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -28,6 +28,7 @@ extern int platform_register_pflash(unsi
- unsigned int nr_parts);
- extern int platform_register_watchdog(void);
- extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
-+extern int platform_register_usb(unsigned int id);
-
- extern void gemini_restart(char mode, const char *cmd);
-
+++ /dev/null
---- a/arch/arm/mach-gemini/board-wbd111.c
-+++ b/arch/arm/mach-gemini/board-wbd111.c
-@@ -145,6 +145,7 @@ static void __init wbd111_init(void)
- platform_register_watchdog();
- platform_device_register(&wbd111_phy_device);
- platform_register_ethernet(&gmac_data);
-+ platform_register_usb(0);
- }
-
- MACHINE_START(WBD111, "Wiliboard WBD-111")
---- a/drivers/usb/host/ehci-hcd.c
-+++ b/drivers/usb/host/ehci-hcd.c
-@@ -99,7 +99,11 @@ module_param (park, uint, S_IRUGO);
- MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
-
- /* for flakey hardware, ignore overcurrent indicators */
-+#ifdef CONFIG_ARCH_GEMINI
-+static bool ignore_oc = 1;
-+#else
- static bool ignore_oc = 0;
-+#endif
- module_param (ignore_oc, bool, S_IRUGO);
- MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
-
+++ /dev/null
---- a/arch/arm/mach-gemini/board-wbd222.c
-+++ b/arch/arm/mach-gemini/board-wbd222.c
-@@ -147,6 +147,7 @@ static void __init wbd222_init(void)
- platform_register_watchdog();
- platform_device_register(&wbd222_phy_device);
- platform_register_ethernet(&gmac_data);
-+ platform_register_usb(0);
- }
-
- MACHINE_START(WBD222, "Wiliboard WBD-222")
+++ /dev/null
---- a/arch/arm/mach-gemini/board-rut1xx.c
-+++ b/arch/arm/mach-gemini/board-rut1xx.c
-@@ -105,6 +105,7 @@ static void __init rut1xx_init(void)
- platform_register_watchdog();
- platform_device_register(&rut1xx_phy_device);
- platform_register_ethernet(&gmac_data);
-+ platform_register_usb(0);
- }
-
- MACHINE_START(RUT100, "Teltonika RUT100")
+++ /dev/null
---- a/arch/arm/mach-gemini/board-nas4220b.c
-+++ b/arch/arm/mach-gemini/board-nas4220b.c
-@@ -96,6 +96,8 @@ static void __init ib4220b_init(void)
- platform_device_register(&ib4220b_key_device);
- platform_register_rtc();
- platform_register_watchdog();
-+ platform_register_usb(0);
-+ platform_register_usb(1);
- }
-
- MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
+++ /dev/null
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -381,6 +381,7 @@ config ARCH_GEMINI
- select ARCH_USES_GETTIMEOFFSET
- select NEED_MACH_GPIO_H
- select CPU_FA526
-+ select MIGHT_HAVE_PCI
- help
- Support for the Cortina Systems Gemini family SoCs
-
---- a/arch/arm/mach-gemini/include/mach/hardware.h
-+++ b/arch/arm/mach-gemini/include/mach/hardware.h
-@@ -71,4 +71,9 @@
- */
- #define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
-
-+/*
-+ * PCI subsystem macros
-+ */
-+#define pcibios_assign_all_busses() 1
-+
- #endif
---- a/arch/arm/mach-gemini/include/mach/irqs.h
-+++ b/arch/arm/mach-gemini/include/mach/irqs.h
-@@ -43,11 +43,14 @@
-
- #define NORMAL_IRQ_NUM 32
-
--#define GPIO_IRQ_BASE NORMAL_IRQ_NUM
-+#define PCI_IRQ_BASE NORMAL_IRQ_NUM
-+#define PCI_IRQ_NUM 4
-+
-+#define GPIO_IRQ_BASE (NORMAL_IRQ_NUM + PCI_IRQ_NUM)
- #define GPIO_IRQ_NUM (3 * 32)
-
- #define ARCH_TIMER_IRQ IRQ_TIMER2
-
--#define NR_IRQS (NORMAL_IRQ_NUM + GPIO_IRQ_NUM)
-+#define NR_IRQS (NORMAL_IRQ_NUM + PCI_IRQ_NUM + GPIO_IRQ_NUM)
-
- #endif /* __MACH_IRQS_H__ */
---- a/arch/arm/mach-gemini/Makefile
-+++ b/arch/arm/mach-gemini/Makefile
-@@ -6,6 +6,8 @@
-
- obj-y := irq.o mm.o time.o devices.o gpio.o idle.o reset.o
-
-+obj-$(CONFIG_PCI) += pci.o
-+
- # Board-specific support
- obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
- obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o
---- a/arch/arm/mach-gemini/mm.c
-+++ b/arch/arm/mach-gemini/mm.c
-@@ -59,6 +59,11 @@ static struct map_desc gemini_io_desc[]
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_PCI_IO_BASE),
-+ .pfn = __phys_to_pfn(GEMINI_PCI_IO_BASE),
-+ .length = SZ_512K,
-+ .type = MT_DEVICE,
-+ }, {
- .virtual = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
- .pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
- .length = SZ_512K,
---- /dev/null
-+++ b/arch/arm/mach-gemini/pci.c
-@@ -0,0 +1,320 @@
-+/*
-+ * Support for Gemini PCI Controller
-+ *
-+ * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
-+ * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-+ *
-+ * based on SL2312 PCI controller code
-+ * Storlink (C) 2003
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/pci.h>
-+#include <linux/irq.h>
-+#include <linux/gpio.h>
-+
-+#include <asm/mach/pci.h>
-+
-+#include <mach/irqs.h>
-+#include <mach/hardware.h>
-+
-+#define GEMINI_PCI_IOSIZE_1M 0x0000
-+
-+#define GEMINI_PCI_PMC 0x40
-+#define GEMINI_PCI_PMCSR 0x44
-+#define GEMINI_PCI_CTRL1 0x48
-+#define GEMINI_PCI_CTRL2 0x4C
-+#define GEMINI_PCI_MEM1_BASE_SIZE 0x50
-+#define GEMINI_PCI_MEM2_BASE_SIZE 0x54
-+#define GEMINI_PCI_MEM3_BASE_SIZE 0x58
-+
-+#define PCI_CTRL2_INTSTS_OFFSET 28
-+#define PCI_CTRL2_INTMASK_OFFSET 22
-+
-+#define GEMINI_PCI_DMA_MASK 0xFFF00000
-+#define GEMINI_PCI_DMA_MEM1_BASE 0x00000000
-+#define GEMINI_PCI_DMA_MEM2_BASE 0x00000000
-+#define GEMINI_PCI_DMA_MEM3_BASE 0x00000000
-+#define GEMINI_PCI_DMA_MEM1_SIZE 7
-+#define GEMINI_PCI_DMA_MEM2_SIZE 6
-+#define GEMINI_PCI_DMA_MEM3_SIZE 6
-+
-+#define PCI_CONF_ENABLE (1 << 31)
-+#define PCI_CONF_WHERE(r) ((r) & 0xFC)
-+#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
-+#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
-+#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
-+
-+#define PCI_IOSIZE_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE))
-+#define PCI_PROT_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x04)
-+#define PCI_CTRL_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x08)
-+#define PCI_SOFTRST_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x10)
-+#define PCI_CONFIG_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x28)
-+#define PCI_DATA_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x2C)
-+
-+
-+static DEFINE_SPINLOCK(gemini_pci_lock);
-+
-+static int gemini_pci_read_config(struct pci_bus* bus, unsigned int fn,
-+ int config, int size, u32* value)
-+{
-+ unsigned long irq_flags;
-+
-+ spin_lock_irqsave(&gemini_pci_lock, irq_flags);
-+
-+ __raw_writel(PCI_CONF_BUS(bus->number) |
-+ PCI_CONF_DEVICE(PCI_SLOT(fn)) |
-+ PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
-+ PCI_CONF_WHERE(config) |
-+ PCI_CONF_ENABLE,
-+ PCI_CONFIG_REG);
-+
-+ *value = __raw_readl(PCI_DATA_REG);
-+
-+ if (size == 1)
-+ *value = (*value >> (8 * (config & 3))) & 0xFF;
-+ else if (size == 2)
-+ *value = (*value >> (8 * (config & 3))) & 0xFFFF;
-+
-+ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
-+
-+ dev_dbg(&bus->dev,
-+ "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
-+ PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int gemini_pci_write_config(struct pci_bus* bus, unsigned int fn,
-+ int config, int size, u32 value)
-+{
-+ unsigned long irq_flags = 0;
-+ int ret = PCIBIOS_SUCCESSFUL;
-+
-+ dev_dbg(&bus->dev,
-+ "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
-+ PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
-+
-+ spin_lock_irqsave(&gemini_pci_lock, irq_flags);
-+
-+ __raw_writel(PCI_CONF_BUS(bus->number) |
-+ PCI_CONF_DEVICE(PCI_SLOT(fn)) |
-+ PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
-+ PCI_CONF_WHERE(config) |
-+ PCI_CONF_ENABLE,
-+ PCI_CONFIG_REG);
-+
-+ switch(size) {
-+ case 4:
-+ __raw_writel(value, PCI_DATA_REG);
-+ break;
-+ case 2:
-+ __raw_writew(value, PCI_DATA_REG + (config & 3));
-+ break;
-+ case 1:
-+ __raw_writeb(value, PCI_DATA_REG + (config & 3));
-+ break;
-+ default:
-+ ret = PCIBIOS_BAD_REGISTER_NUMBER;
-+ }
-+
-+ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
-+
-+ return ret;
-+}
-+
-+static struct pci_ops gemini_pci_ops = {
-+ .read = gemini_pci_read_config,
-+ .write = gemini_pci_write_config,
-+};
-+
-+static struct resource gemini_pci_resource_io = {
-+ .name = "PCI I/O Space",
-+ .start = GEMINI_PCI_IO_BASE,
-+ .end = GEMINI_PCI_IO_BASE + SZ_1M - 1,
-+ .flags = IORESOURCE_IO,
-+};
-+
-+static struct resource gemini_pci_resource_mem = {
-+ .name = "PCI Memory Space",
-+ .start = GEMINI_PCI_MEM_BASE,
-+ .end = GEMINI_PCI_MEM_BASE + SZ_128M - 1,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static int __init gemini_pci_request_resources(struct pci_sys_data *sys)
-+{
-+ if (request_resource(&ioport_resource, &gemini_pci_resource_io))
-+ goto bad_resources;
-+ if (request_resource(&iomem_resource, &gemini_pci_resource_mem))
-+ goto bad_resources;
-+
-+ pci_add_resource(&sys->resources, &gemini_pci_resource_io);
-+ pci_add_resource(&sys->resources, &gemini_pci_resource_mem);
-+
-+ return 0;
-+
-+bad_resources:
-+ pr_err("Gemini PCI: request_resource() failed. "
-+ "Abort PCI bus enumeration.\n");
-+ return -1;
-+}
-+
-+static int __init gemini_pci_setup(int nr, struct pci_sys_data *sys)
-+{
-+ unsigned int cmd;
-+
-+ pcibios_min_io = 0x100;
-+ pcibios_min_mem = 0;
-+
-+ if ((nr > 0) || gemini_pci_request_resources(sys))
-+ return 0;
-+
-+ /* setup I/O space to 1MB size */
-+ __raw_writel(GEMINI_PCI_IOSIZE_1M, PCI_IOSIZE_REG);
-+
-+ /* setup hostbridge */
-+ cmd = __raw_readl(PCI_CTRL_REG);
-+ cmd |= PCI_COMMAND_IO;
-+ cmd |= PCI_COMMAND_MEMORY;
-+ cmd |= PCI_COMMAND_MASTER;
-+ __raw_writel(cmd, PCI_CTRL_REG);
-+
-+ return 1;
-+}
-+
-+static struct pci_bus* __init gemini_pci_scan_bus(int nr, struct pci_sys_data* sys)
-+{
-+ unsigned int reg = 0;
-+ struct pci_bus* bus = 0;
-+
-+ bus = pci_scan_bus(nr, &gemini_pci_ops, sys);
-+ if (bus) {
-+ dev_dbg(&bus->dev, "setting up PCI DMA\n");
-+ reg = (GEMINI_PCI_DMA_MEM1_BASE & GEMINI_PCI_DMA_MASK)
-+ | (GEMINI_PCI_DMA_MEM1_SIZE << 16);
-+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM1_BASE_SIZE, 4, reg);
-+ reg = (GEMINI_PCI_DMA_MEM2_BASE & GEMINI_PCI_DMA_MASK)
-+ | (GEMINI_PCI_DMA_MEM2_SIZE << 16);
-+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM2_BASE_SIZE, 4, reg);
-+ reg = (GEMINI_PCI_DMA_MEM3_BASE & GEMINI_PCI_DMA_MASK)
-+ | (GEMINI_PCI_DMA_MEM3_SIZE << 16);
-+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM3_BASE_SIZE, 4, reg);
-+ }
-+
-+ return bus;
-+}
-+
-+/* Should work with all boards based on original Storlink EVB */
-+static int __init gemini_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ if (slot < 9 || slot > 12)
-+ return -1;
-+
-+ return PCI_IRQ_BASE + (((slot - 9) + (pin - 1)) & 0x3);
-+}
-+
-+static struct hw_pci gemini_hw_pci __initdata = {
-+ .nr_controllers = 1,
-+ .setup = gemini_pci_setup,
-+ .scan = gemini_pci_scan_bus,
-+ .map_irq = gemini_pci_map_irq,
-+};
-+
-+/* we need this for muxed PCI interrupts handling */
-+static struct pci_bus bogus_pci_bus;
-+
-+static void gemini_pci_ack_irq(struct irq_data *d)
-+{
-+ unsigned int irq = d->irq;
-+ unsigned int reg;
-+
-+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
-+ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
-+ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTSTS_OFFSET);
-+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
-+}
-+
-+static void gemini_pci_mask_irq(struct irq_data *d)
-+{
-+ unsigned int irq = d->irq;
-+ unsigned int reg;
-+
-+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
-+ reg &= ~((0xF << PCI_CTRL2_INTSTS_OFFSET)
-+ | (1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET)));
-+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
-+}
-+
-+static void gemini_pci_unmask_irq(struct irq_data *d)
-+{
-+ unsigned int irq = d->irq;
-+ unsigned int reg;
-+
-+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
-+ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
-+ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET);
-+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
-+}
-+
-+static void gemini_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
-+{
-+ unsigned int pci_irq_no, irq_stat, reg, i;
-+
-+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
-+ irq_stat = reg >> PCI_CTRL2_INTSTS_OFFSET;
-+
-+ for (i = 0; i < 4; i++) {
-+
-+ if ((irq_stat & (1 << i)) == 0)
-+ continue;
-+
-+ pci_irq_no = PCI_IRQ_BASE + i;
-+
-+ BUG_ON(!(irq_desc[pci_irq_no].handle_irq));
-+ irq_desc[pci_irq_no].handle_irq(pci_irq_no,
-+ &irq_desc[pci_irq_no]);
-+ }
-+}
-+
-+static struct irq_chip gemini_pci_irq_chip = {
-+ .name = "PCI",
-+ .irq_ack = gemini_pci_ack_irq,
-+ .irq_mask = gemini_pci_mask_irq,
-+ .irq_unmask = gemini_pci_unmask_irq,
-+};
-+
-+static int __init gemini_pci_init(void)
-+{
-+ int i;
-+
-+ for (i = 72; i <= 95; i++)
-+ gpio_request(i, "PCI");
-+
-+ /* initialize our bogus bus */
-+ dev_set_name(&bogus_pci_bus.dev, "PCI IRQ handler");
-+ bogus_pci_bus.number = 0;
-+
-+ /* mask and clear all interrupts */
-+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2 + 2, 2,
-+ 0xF000);
-+
-+ for (i = PCI_IRQ_BASE; i < PCI_IRQ_BASE + 4; i++) {
-+ irq_set_chip_and_handler(i, &gemini_pci_irq_chip,
-+ handle_level_irq);
-+ set_irq_flags(i, IRQF_VALID);
-+ }
-+
-+ irq_set_chained_handler(IRQ_PCI, gemini_pci_irq_handler);
-+
-+ pci_common_init(&gemini_hw_pci);
-+
-+ return 0;
-+}
-+
-+subsys_initcall(gemini_pci_init);
+++ /dev/null
-From patchwork Fri Jan 4 15:30:38 2013
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [RFC,1/3] ARM: gemini: get platform to build again
-Date: Fri, 04 Jan 2013 15:30:38 -0000
-From: Arnd Bergmann <arnd@arndb.de>
-X-Patchwork-Id: 1933501
-Message-Id: <1357313440-20092-1-git-send-email-arnd@arndb.de>
-To: Hans Ulli Kroll <ulli.kroll@googlemail.com>
-Cc: Russell King <rmk+kernel@arm.linux.org.uk>, Arnd Bergmann <arnd@arndb.de>,
- Florian Fainelli <florian@openwrt.org>,
- linux-arm-kernel@lists.infradead.org
-
-There is no defconfig file for gemini, which has lead to a lot
-of bitrot. This makes the broken board files, the gpio implementation
-and the reset logic work again, and fixes the build warnings
-that got introduced with the changes to the readl/writel prototypes.
-
-Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-
----
-(retransmitted because the original was rejected by linux-arm-kernel)
-
- arch/arm/Kconfig | 1 +
- arch/arm/mach-gemini/Makefile | 2 +-
- arch/arm/mach-gemini/board-nas4220b.c | 1 +
- arch/arm/mach-gemini/board-rut1xx.c | 2 ++
- arch/arm/mach-gemini/board-wbd111.c | 1 +
- arch/arm/mach-gemini/board-wbd222.c | 1 +
- arch/arm/mach-gemini/common.h | 2 ++
- arch/arm/mach-gemini/gpio.c | 19 ++++++++++---------
- arch/arm/mach-gemini/include/mach/hardware.h | 2 +-
- arch/arm/mach-gemini/include/mach/system.h | 23 -----------------------
- arch/arm/mach-gemini/irq.c | 4 ++--
- arch/arm/mach-gemini/mm.c | 22 +++++++++++-----------
- arch/arm/mach-gemini/reset.c | 23 +++++++++++++++++++++++
- 13 files changed, 56 insertions(+), 47 deletions(-)
- delete mode 100644 arch/arm/mach-gemini/include/mach/system.h
- create mode 100644 arch/arm/mach-gemini/reset.c
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -410,6 +410,7 @@ config ARCH_GEMINI
- bool "Cortina Systems Gemini"
- select ARCH_REQUIRE_GPIOLIB
- select ARCH_USES_GETTIMEOFFSET
-+ select NEED_MACH_GPIO_H
- select CPU_FA526
- help
- Support for the Cortina Systems Gemini family SoCs
---- a/arch/arm/mach-gemini/Makefile
-+++ b/arch/arm/mach-gemini/Makefile
-@@ -4,7 +4,7 @@
-
- # Object file lists.
-
--obj-y := irq.o mm.o time.o devices.o gpio.o idle.o
-+obj-y := irq.o mm.o time.o devices.o gpio.o idle.o reset.o
-
- # Board-specific support
- obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
---- a/arch/arm/mach-gemini/board-nas4220b.c
-+++ b/arch/arm/mach-gemini/board-nas4220b.c
-@@ -103,4 +103,5 @@ MACHINE_START(NAS4220B, "Raidsonic NAS I
- .init_irq = gemini_init_irq,
- .init_time = gemini_timer_init,
- .init_machine = ib4220b_init,
-+ .restart = gemini_restart,
- MACHINE_END
---- a/arch/arm/mach-gemini/board-rut1xx.c
-+++ b/arch/arm/mach-gemini/board-rut1xx.c
-@@ -14,6 +14,7 @@
- #include <linux/leds.h>
- #include <linux/input.h>
- #include <linux/gpio_keys.h>
-+#include <linux/sizes.h>
-
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
-@@ -87,4 +88,5 @@ MACHINE_START(RUT100, "Teltonika RUT100"
- .init_irq = gemini_init_irq,
- .init_time = gemini_timer_init,
- .init_machine = rut1xx_init,
-+ .restart = gemini_restart,
- MACHINE_END
---- a/arch/arm/mach-gemini/board-wbd111.c
-+++ b/arch/arm/mach-gemini/board-wbd111.c
-@@ -130,4 +130,5 @@ MACHINE_START(WBD111, "Wiliboard WBD-111
- .init_irq = gemini_init_irq,
- .init_time = gemini_timer_init,
- .init_machine = wbd111_init,
-+ .restart = gemini_restart,
- MACHINE_END
---- a/arch/arm/mach-gemini/board-wbd222.c
-+++ b/arch/arm/mach-gemini/board-wbd222.c
-@@ -130,4 +130,5 @@ MACHINE_START(WBD222, "Wiliboard WBD-222
- .init_irq = gemini_init_irq,
- .init_time = gemini_timer_init,
- .init_machine = wbd222_init,
-+ .restart = gemini_restart,
- MACHINE_END
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -26,4 +26,6 @@ extern int platform_register_pflash(unsi
- struct mtd_partition *parts,
- unsigned int nr_parts);
-
-+extern void gemini_restart(char mode, const char *cmd);
-+
- #endif /* __GEMINI_COMMON_H__ */
---- a/arch/arm/mach-gemini/gpio.c
-+++ b/arch/arm/mach-gemini/gpio.c
-@@ -21,6 +21,7 @@
-
- #include <mach/hardware.h>
- #include <mach/irqs.h>
-+#include <mach/gpio.h>
-
- #define GPIO_BASE(x) IO_ADDRESS(GEMINI_GPIO_BASE(x))
-
-@@ -44,7 +45,7 @@
-
- #define GPIO_PORT_NUM 3
-
--static void _set_gpio_irqenable(unsigned int base, unsigned int index,
-+static void _set_gpio_irqenable(void __iomem *base, unsigned int index,
- int enable)
- {
- unsigned int reg;
-@@ -57,7 +58,7 @@ static void _set_gpio_irqenable(unsigned
- static void gpio_ack_irq(struct irq_data *d)
- {
- unsigned int gpio = irq_to_gpio(d->irq);
-- unsigned int base = GPIO_BASE(gpio / 32);
-+ void __iomem *base = GPIO_BASE(gpio / 32);
-
- __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
- }
-@@ -65,7 +66,7 @@ static void gpio_ack_irq(struct irq_data
- static void gpio_mask_irq(struct irq_data *d)
- {
- unsigned int gpio = irq_to_gpio(d->irq);
-- unsigned int base = GPIO_BASE(gpio / 32);
-+ void __iomem *base = GPIO_BASE(gpio / 32);
-
- _set_gpio_irqenable(base, gpio % 32, 0);
- }
-@@ -73,7 +74,7 @@ static void gpio_mask_irq(struct irq_dat
- static void gpio_unmask_irq(struct irq_data *d)
- {
- unsigned int gpio = irq_to_gpio(d->irq);
-- unsigned int base = GPIO_BASE(gpio / 32);
-+ void __iomem *base = GPIO_BASE(gpio / 32);
-
- _set_gpio_irqenable(base, gpio % 32, 1);
- }
-@@ -82,7 +83,7 @@ static int gpio_set_irq_type(struct irq_
- {
- unsigned int gpio = irq_to_gpio(d->irq);
- unsigned int gpio_mask = 1 << (gpio % 32);
-- unsigned int base = GPIO_BASE(gpio / 32);
-+ void __iomem *base = GPIO_BASE(gpio / 32);
- unsigned int reg_both, reg_level, reg_type;
-
- reg_type = __raw_readl(base + GPIO_INT_TYPE);
-@@ -120,7 +121,7 @@ static int gpio_set_irq_type(struct irq_
- __raw_writel(reg_level, base + GPIO_INT_LEVEL);
- __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
-
-- gpio_ack_irq(d->irq);
-+ gpio_ack_irq(d);
-
- return 0;
- }
-@@ -153,7 +154,7 @@ static struct irq_chip gpio_irq_chip = {
- static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
- int dir)
- {
-- unsigned int base = GPIO_BASE(offset / 32);
-+ void __iomem *base = GPIO_BASE(offset / 32);
- unsigned int reg;
-
- reg = __raw_readl(base + GPIO_DIR);
-@@ -166,7 +167,7 @@ static void _set_gpio_direction(struct g
-
- static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
- {
-- unsigned int base = GPIO_BASE(offset / 32);
-+ void __iomem *base = GPIO_BASE(offset / 32);
-
- if (value)
- __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET);
-@@ -176,7 +177,7 @@ static void gemini_gpio_set(struct gpio_
-
- static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset)
- {
-- unsigned int base = GPIO_BASE(offset / 32);
-+ void __iomem *base = GPIO_BASE(offset / 32);
-
- return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1;
- }
---- a/arch/arm/mach-gemini/include/mach/hardware.h
-+++ b/arch/arm/mach-gemini/include/mach/hardware.h
-@@ -69,6 +69,6 @@
- /*
- * macro to get at IO space when running virtually
- */
--#define IO_ADDRESS(x) ((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
-+#define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
-
- #endif
---- a/arch/arm/mach-gemini/include/mach/system.h
-+++ /dev/null
-@@ -1,23 +0,0 @@
--/*
-- * Copyright (C) 2001-2006 Storlink, Corp.
-- * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- */
--#ifndef __MACH_SYSTEM_H
--#define __MACH_SYSTEM_H
--
--#include <linux/io.h>
--#include <mach/hardware.h>
--#include <mach/global_reg.h>
--
--static inline void arch_reset(char mode, const char *cmd)
--{
-- __raw_writel(RESET_GLOBAL | RESET_CPU1,
-- IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
--}
--
--#endif /* __MACH_SYSTEM_H */
---- a/arch/arm/mach-gemini/irq.c
-+++ b/arch/arm/mach-gemini/irq.c
-@@ -65,8 +65,8 @@ static struct irq_chip gemini_irq_chip =
-
- static struct resource irq_resource = {
- .name = "irq_handler",
-- .start = IO_ADDRESS(GEMINI_INTERRUPT_BASE),
-- .end = IO_ADDRESS(FIQ_STATUS(GEMINI_INTERRUPT_BASE)) + 4,
-+ .start = GEMINI_INTERRUPT_BASE,
-+ .end = FIQ_STATUS(GEMINI_INTERRUPT_BASE) + 4,
- };
-
- void __init gemini_init_irq(void)
---- a/arch/arm/mach-gemini/mm.c
-+++ b/arch/arm/mach-gemini/mm.c
-@@ -19,57 +19,57 @@
- /* Page table mapping for I/O region */
- static struct map_desc gemini_io_desc[] __initdata = {
- {
-- .virtual = IO_ADDRESS(GEMINI_GLOBAL_BASE),
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_GLOBAL_BASE),
- .pfn =__phys_to_pfn(GEMINI_GLOBAL_BASE),
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-- .virtual = IO_ADDRESS(GEMINI_UART_BASE),
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_UART_BASE),
- .pfn = __phys_to_pfn(GEMINI_UART_BASE),
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-- .virtual = IO_ADDRESS(GEMINI_TIMER_BASE),
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_TIMER_BASE),
- .pfn = __phys_to_pfn(GEMINI_TIMER_BASE),
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-- .virtual = IO_ADDRESS(GEMINI_INTERRUPT_BASE),
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_INTERRUPT_BASE),
- .pfn = __phys_to_pfn(GEMINI_INTERRUPT_BASE),
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-- .virtual = IO_ADDRESS(GEMINI_POWER_CTRL_BASE),
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_POWER_CTRL_BASE),
- .pfn = __phys_to_pfn(GEMINI_POWER_CTRL_BASE),
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-- .virtual = IO_ADDRESS(GEMINI_GPIO_BASE(0)),
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(0)),
- .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(0)),
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-- .virtual = IO_ADDRESS(GEMINI_GPIO_BASE(1)),
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(1)),
- .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(1)),
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-- .virtual = IO_ADDRESS(GEMINI_GPIO_BASE(2)),
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(2)),
- .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(2)),
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-- .virtual = IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
- .pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-- .virtual = IO_ADDRESS(GEMINI_DRAM_CTRL_BASE),
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_DRAM_CTRL_BASE),
- .pfn = __phys_to_pfn(GEMINI_DRAM_CTRL_BASE),
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-- .virtual = IO_ADDRESS(GEMINI_GENERAL_DMA_BASE),
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_GENERAL_DMA_BASE),
- .pfn = __phys_to_pfn(GEMINI_GENERAL_DMA_BASE),
- .length = SZ_512K,
- .type = MT_DEVICE,
---- /dev/null
-+++ b/arch/arm/mach-gemini/reset.c
-@@ -0,0 +1,23 @@
-+/*
-+ * Copyright (C) 2001-2006 Storlink, Corp.
-+ * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+#ifndef __MACH_SYSTEM_H
-+#define __MACH_SYSTEM_H
-+
-+#include <linux/io.h>
-+#include <mach/hardware.h>
-+#include <mach/global_reg.h>
-+
-+void gemini_restart(char mode, const char *cmd)
-+{
-+ __raw_writel(RESET_GLOBAL | RESET_CPU1,
-+ IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
-+}
-+
-+#endif /* __MACH_SYSTEM_H */
+++ /dev/null
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -18,9 +18,9 @@ extern void gemini_map_io(void);
- extern void gemini_init_irq(void);
- extern void gemini_timer_init(void);
- extern void gemini_gpio_init(void);
--extern void platform_register_rtc(void);
-
- /* Common platform devices registration functions */
-+extern int platform_register_rtc(void);
- extern int platform_register_uart(void);
- extern int platform_register_pflash(unsigned int size,
- struct mtd_partition *parts,
---- a/arch/arm/mach-gemini/devices.c
-+++ b/arch/arm/mach-gemini/devices.c
-@@ -17,6 +17,7 @@
- #include <mach/irqs.h>
- #include <mach/hardware.h>
- #include <mach/global_reg.h>
-+#include "common.h"
-
- static struct plat_serial8250_port serial_platform_data[] = {
- {
+++ /dev/null
---- /dev/null
-+++ b/drivers/watchdog/gemini_wdt.c
-@@ -0,0 +1,378 @@
-+/*
-+ * Watchdog driver for Cortina Systems Gemini SoC
-+ *
-+ * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/fs.h>
-+#include <linux/uaccess.h>
-+#include <linux/miscdevice.h>
-+#include <linux/platform_device.h>
-+#include <linux/watchdog.h>
-+#include <linux/slab.h>
-+
-+#define GEMINI_WDCOUNTER 0x0
-+#define GEMINI_WDLOAD 0x4
-+#define GEMINI_WDRESTART 0x8
-+
-+#define WDRESTART_MAGIC 0x5AB9
-+
-+#define GEMINI_WDCR 0xC
-+
-+#define WDCR_CLOCK_5MHZ (1 << 4)
-+#define WDCR_SYS_RST (1 << 1)
-+#define WDCR_ENABLE (1 << 0)
-+
-+#define WDT_CLOCK 5000000 /* 5 MHz */
-+#define WDT_DEFAULT_TIMEOUT 13
-+#define WDT_MAX_TIMEOUT (0xFFFFFFFF / WDT_CLOCK)
-+
-+/* status bits */
-+#define WDT_ACTIVE 0
-+#define WDT_OK_TO_CLOSE 1
-+
-+static unsigned int timeout = WDT_DEFAULT_TIMEOUT;
-+static int nowayout = WATCHDOG_NOWAYOUT;
-+
-+static DEFINE_SPINLOCK(gemini_wdt_lock);
-+
-+static struct platform_device *gemini_wdt_dev;
-+
-+struct gemini_wdt_struct {
-+ struct resource *res;
-+ struct device *dev;
-+ void __iomem *base;
-+ unsigned long status;
-+};
-+
-+static struct watchdog_info gemini_wdt_info = {
-+ .identity = "Gemini watchdog",
-+ .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING |
-+ WDIOF_SETTIMEOUT,
-+};
-+
-+/* Disable the watchdog. */
-+static void gemini_wdt_stop(struct gemini_wdt_struct *gemini_wdt)
-+{
-+ spin_lock(&gemini_wdt_lock);
-+
-+ __raw_writel(0, gemini_wdt->base + GEMINI_WDCR);
-+
-+ clear_bit(WDT_ACTIVE, &gemini_wdt->status);
-+
-+ spin_unlock(&gemini_wdt_lock);
-+}
-+
-+/* Service the watchdog */
-+static void gemini_wdt_service(struct gemini_wdt_struct *gemini_wdt)
-+{
-+ __raw_writel(WDRESTART_MAGIC, gemini_wdt->base + GEMINI_WDRESTART);
-+}
-+
-+/* Enable and reset the watchdog. */
-+static void gemini_wdt_start(struct gemini_wdt_struct *gemini_wdt)
-+{
-+ spin_lock(&gemini_wdt_lock);
-+
-+ __raw_writel(timeout * WDT_CLOCK, gemini_wdt->base + GEMINI_WDLOAD);
-+
-+ gemini_wdt_service(gemini_wdt);
-+
-+ /* set clock before enabling */
-+ __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
-+ gemini_wdt->base + GEMINI_WDCR);
-+
-+ __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
-+ gemini_wdt->base + GEMINI_WDCR);
-+
-+ set_bit(WDT_ACTIVE, &gemini_wdt->status);
-+
-+ spin_unlock(&gemini_wdt_lock);
-+}
-+
-+/* Watchdog device is opened, and watchdog starts running. */
-+static int gemini_wdt_open(struct inode *inode, struct file *file)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(gemini_wdt_dev);
-+
-+ if (test_bit(WDT_ACTIVE, &gemini_wdt->status))
-+ return -EBUSY;
-+
-+ file->private_data = gemini_wdt;
-+
-+ gemini_wdt_start(gemini_wdt);
-+
-+ return nonseekable_open(inode, file);
-+}
-+
-+/* Close the watchdog device. */
-+static int gemini_wdt_close(struct inode *inode, struct file *file)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = file->private_data;
-+
-+ /* Disable the watchdog if possible */
-+ if (test_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status))
-+ gemini_wdt_stop(gemini_wdt);
-+ else
-+ dev_warn(gemini_wdt->dev, "Device closed unexpectedly - timer will not stop\n");
-+
-+ return 0;
-+}
-+
-+/* Handle commands from user-space. */
-+static long gemini_wdt_ioctl(struct file *file, unsigned int cmd,
-+ unsigned long arg)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = file->private_data;
-+
-+ int value;
-+
-+ switch (cmd) {
-+ case WDIOC_KEEPALIVE:
-+ gemini_wdt_service(gemini_wdt);
-+ return 0;
-+
-+ case WDIOC_GETSUPPORT:
-+ return copy_to_user((struct watchdog_info *)arg, &gemini_wdt_info,
-+ sizeof(gemini_wdt_info)) ? -EFAULT : 0;
-+
-+ case WDIOC_SETTIMEOUT:
-+ if (get_user(value, (int *)arg))
-+ return -EFAULT;
-+
-+ if ((value < 1) || (value > WDT_MAX_TIMEOUT))
-+ return -EINVAL;
-+
-+ timeout = value;
-+
-+ /* restart wdt to use new timeout */
-+ gemini_wdt_stop(gemini_wdt);
-+ gemini_wdt_start(gemini_wdt);
-+
-+ /* Fall through */
-+ case WDIOC_GETTIMEOUT:
-+ return put_user(timeout, (int *)arg);
-+
-+ case WDIOC_GETTIMELEFT:
-+ value = __raw_readl(gemini_wdt->base + GEMINI_WDCOUNTER);
-+ return put_user(value / WDT_CLOCK, (int *)arg);
-+
-+ default:
-+ return -ENOTTY;
-+ }
-+}
-+
-+/* Refresh the watchdog whenever device is written to. */
-+static ssize_t gemini_wdt_write(struct file *file, const char *data,
-+ size_t len, loff_t *ppos)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = file->private_data;
-+
-+ if (len) {
-+ if (!nowayout) {
-+ size_t i;
-+
-+ clear_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status);
-+ for (i = 0; i != len; i++) {
-+ char c;
-+
-+ if (get_user(c, data + i))
-+ return -EFAULT;
-+ if (c == 'V')
-+ set_bit(WDT_OK_TO_CLOSE,
-+ &gemini_wdt->status);
-+ }
-+ }
-+ gemini_wdt_service(gemini_wdt);
-+ }
-+
-+ return len;
-+}
-+
-+static const struct file_operations gemini_wdt_fops = {
-+ .owner = THIS_MODULE,
-+ .llseek = no_llseek,
-+ .unlocked_ioctl = gemini_wdt_ioctl,
-+ .open = gemini_wdt_open,
-+ .release = gemini_wdt_close,
-+ .write = gemini_wdt_write,
-+};
-+
-+static struct miscdevice gemini_wdt_miscdev = {
-+ .minor = WATCHDOG_MINOR,
-+ .name = "watchdog",
-+ .fops = &gemini_wdt_fops,
-+};
-+
-+static void gemini_wdt_shutdown(struct platform_device *pdev)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
-+
-+ gemini_wdt_stop(gemini_wdt);
-+}
-+
-+static int gemini_wdt_probe(struct platform_device *pdev)
-+{
-+ int ret;
-+ int res_size;
-+ struct resource *res;
-+ void __iomem *base;
-+ struct gemini_wdt_struct *gemini_wdt;
-+ unsigned int reg;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(&pdev->dev, "can't get device resources\n");
-+ return -ENODEV;
-+ }
-+
-+ res_size = resource_size(res);
-+ if (!request_mem_region(res->start, res_size, res->name)) {
-+ dev_err(&pdev->dev, "can't allocate %d bytes at %d address\n",
-+ res_size, res->start);
-+ return -ENOMEM;
-+ }
-+
-+ base = ioremap(res->start, res_size);
-+ if (!base) {
-+ dev_err(&pdev->dev, "ioremap failed\n");
-+ ret = -EIO;
-+ goto fail0;
-+ }
-+
-+ gemini_wdt = kzalloc(sizeof(struct gemini_wdt_struct), GFP_KERNEL);
-+ if (!gemini_wdt) {
-+ dev_err(&pdev->dev, "can't allocate interface\n");
-+ ret = -ENOMEM;
-+ goto fail1;
-+ }
-+
-+ /* Setup gemini_wdt driver structure */
-+ gemini_wdt->base = base;
-+ gemini_wdt->res = res;
-+
-+ /* Set up platform driver data */
-+ platform_set_drvdata(pdev, gemini_wdt);
-+ gemini_wdt_dev = pdev;
-+
-+ if (gemini_wdt_miscdev.parent) {
-+ ret = -EBUSY;
-+ goto fail2;
-+ }
-+
-+ gemini_wdt_miscdev.parent = &pdev->dev;
-+
-+ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
-+ if (reg & WDCR_ENABLE) {
-+ /* Watchdog was enabled by the bootloader, disable it. */
-+ reg &= ~(WDCR_ENABLE);
-+ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
-+ }
-+
-+ ret = misc_register(&gemini_wdt_miscdev);
-+ if (ret)
-+ goto fail2;
-+
-+ return 0;
-+
-+fail2:
-+ platform_set_drvdata(pdev, NULL);
-+ kfree(gemini_wdt);
-+fail1:
-+ iounmap(base);
-+fail0:
-+ release_mem_region(res->start, res_size);
-+
-+ return ret;
-+}
-+
-+static int gemini_wdt_remove(struct platform_device *pdev)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
-+
-+ platform_set_drvdata(pdev, NULL);
-+ misc_deregister(&gemini_wdt_miscdev);
-+ gemini_wdt_dev = NULL;
-+ iounmap(gemini_wdt->base);
-+ release_mem_region(gemini_wdt->res->start, resource_size(gemini_wdt->res));
-+
-+ kfree(gemini_wdt);
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_PM
-+static int gemini_wdt_suspend(struct platform_device *pdev, pm_message_t message)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
-+ unsigned int reg;
-+
-+ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
-+ reg &= ~(WDCR_WDENABLE);
-+ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
-+
-+ return 0;
-+}
-+
-+static int gemini_wdt_resume(struct platform_device *pdev)
-+{
-+ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
-+ unsigned int reg;
-+
-+ if (gemini_wdt->status) {
-+ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
-+ reg |= WDCR_WDENABLE;
-+ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
-+ }
-+
-+ return 0;
-+}
-+#else
-+#define gemini_wdt_suspend NULL
-+#define gemini_wdt_resume NULL
-+#endif
-+
-+static struct platform_driver gemini_wdt_driver = {
-+ .probe = gemini_wdt_probe,
-+ .remove = gemini_wdt_remove,
-+ .shutdown = gemini_wdt_shutdown,
-+ .suspend = gemini_wdt_suspend,
-+ .resume = gemini_wdt_resume,
-+ .driver = {
-+ .name = "gemini-wdt",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init gemini_wdt_init(void)
-+{
-+ return platform_driver_probe(&gemini_wdt_driver, gemini_wdt_probe);
-+}
-+
-+static void __exit gemini_wdt_exit(void)
-+{
-+ platform_driver_unregister(&gemini_wdt_driver);
-+}
-+
-+module_init(gemini_wdt_init);
-+module_exit(gemini_wdt_exit);
-+
-+module_param(timeout, uint, 0);
-+MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
-+
-+module_param(nowayout, int, 0);
-+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
-+
-+MODULE_AUTHOR("Paulius Zaleckas");
-+MODULE_DESCRIPTION("Watchdog driver for Gemini");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-+MODULE_ALIAS("platform:gemini-wdt");
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -154,6 +154,16 @@ config 977_WATCHDOG
-
- Not sure? It's safe to say N.
-
-+config GEMINI_WATCHDOG
-+ tristate "Gemini watchdog"
-+ depends on ARCH_GEMINI
-+ help
-+ Say Y here if to include support for the watchdog timer
-+ embedded in the Cortina Systems Gemini family of devices.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called gemini_wdt.
-+
- config IXP4XX_WATCHDOG
- tristate "IXP4xx Watchdog"
- depends on ARCH_IXP4XX
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -36,6 +36,7 @@ obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.
- obj-$(CONFIG_TWL4030_WATCHDOG) += twl4030_wdt.o
- obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
- obj-$(CONFIG_977_WATCHDOG) += wdt977.o
-+obj-$(CONFIG_GEMINI_WATCHDOG) += gemini_wdt.o
- obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
- obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
- obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
+++ /dev/null
---- a/arch/arm/mach-gemini/devices.c
-+++ b/arch/arm/mach-gemini/devices.c
-@@ -117,3 +117,20 @@ int __init platform_register_rtc(void)
- return platform_device_register(&gemini_rtc_device);
- }
-
-+static struct resource wdt_resource = {
-+ .start = GEMINI_WAQTCHDOG_BASE,
-+ .end = GEMINI_WAQTCHDOG_BASE + 0x18,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device wdt_device = {
-+ .name = "gemini-wdt",
-+ .id = 0,
-+ .resource = &wdt_resource,
-+ .num_resources = 1,
-+};
-+
-+int __init platform_register_watchdog(void)
-+{
-+ return platform_device_register(&wdt_device);
-+}
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -25,6 +25,7 @@ extern int platform_register_uart(void);
- extern int platform_register_pflash(unsigned int size,
- struct mtd_partition *parts,
- unsigned int nr_parts);
-+extern int platform_register_watchdog(void);
-
- extern void gemini_restart(char mode, const char *cmd);
-
+++ /dev/null
---- a/arch/arm/mach-gemini/board-nas4220b.c
-+++ b/arch/arm/mach-gemini/board-nas4220b.c
-@@ -95,6 +95,7 @@ static void __init ib4220b_init(void)
- platform_device_register(&ib4220b_led_device);
- platform_device_register(&ib4220b_key_device);
- platform_register_rtc();
-+ platform_register_watchdog();
- }
-
- MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
---- a/arch/arm/mach-gemini/board-wbd111.c
-+++ b/arch/arm/mach-gemini/board-wbd111.c
-@@ -122,6 +122,7 @@ static void __init wbd111_init(void)
- platform_device_register(&wbd111_leds_device);
- platform_device_register(&wbd111_keys_device);
- platform_register_rtc();
-+ platform_register_watchdog();
- }
-
- MACHINE_START(WBD111, "Wiliboard WBD-111")
---- a/arch/arm/mach-gemini/board-wbd222.c
-+++ b/arch/arm/mach-gemini/board-wbd222.c
-@@ -122,6 +122,7 @@ static void __init wbd222_init(void)
- platform_device_register(&wbd222_leds_device);
- platform_device_register(&wbd222_keys_device);
- platform_register_rtc();
-+ platform_register_watchdog();
- }
-
- MACHINE_START(WBD222, "Wiliboard WBD-222")
---- a/arch/arm/mach-gemini/board-rut1xx.c
-+++ b/arch/arm/mach-gemini/board-rut1xx.c
-@@ -80,6 +80,7 @@ static void __init rut1xx_init(void)
- platform_device_register(&rut1xx_leds);
- platform_device_register(&rut1xx_keys_device);
- platform_register_rtc();
-+ platform_register_watchdog();
- }
-
- MACHINE_START(RUT100, "Teltonika RUT100")
+++ /dev/null
---- /dev/null
-+++ b/arch/arm/mach-gemini/include/mach/gmac.h
-@@ -0,0 +1,21 @@
-+/*
-+ * Gemini GMAC specific defines
-+ *
-+ * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+#ifndef __MACH_GMAC_H__
-+#define __MACH_GMAC_H__
-+
-+#include <linux/phy.h>
-+
-+struct gemini_gmac_platform_data {
-+ char *bus_id[2]; /* NULL means that this port is not used */
-+ phy_interface_t interface[2];
-+};
-+
-+#endif /* __MACH_GMAC_H__ */
---- /dev/null
-+++ b/drivers/net/gemini_negmac/gm_gmac.c
-@@ -0,0 +1,1359 @@
-+/*
-+ * Ethernet device driver for Gemini SoC.
-+ *
-+ * Copyright (C) 2006, Storlink, Corp.
-+ * Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/mm.h>
-+#include <linux/compiler.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/init.h>
-+#include <linux/ioport.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/rtnetlink.h>
-+#include <linux/delay.h>
-+#include <linux/ethtool.h>
-+#include <linux/mii.h>
-+#include <linux/phy.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/completion.h>
-+#include <linux/kthread.h>
-+#include <linux/io.h>
-+#include <mach/hardware.h>
-+#include <linux/semaphore.h>
-+#include <mach/irqs.h>
-+#include <linux/skbuff.h>
-+#include <linux/in.h>
-+#include <linux/ip.h>
-+#include <linux/tcp.h>
-+#include <linux/udp.h>
-+#include <mach/gmac.h>
-+
-+#include "gm_gmac.h"
-+
-+/* #define GMAX_TX_INTR_DISABLED */
-+/* #define DO_HW_CHKSUM */
-+/* #define ENABLE_TSO */
-+#define GMAC_USE_TXQ0
-+/* #define GMAC_LEN_1_2_ISSUE */
-+
-+#define DEFAULT_RXQ_MAX_CNT 256
-+
-+/* define chip information */
-+#define DRV_VERSION "0.2"
-+#define SL351x_DRIVER_NAME "Gemini Ethernet driver " DRV_VERSION
-+
-+#ifdef GMAC_LEN_1_2_ISSUE
-+ #define _DEBUG_PREFETCH_NUM 256
-+static int _debug_prefetch_cnt;
-+static char _debug_prefetch_buf[_DEBUG_PREFETCH_NUM][4] __attribute__((aligned(4)));
-+#endif
-+
-+static inline void gmac_write_reg(void __iomem *base, unsigned int offset,
-+ unsigned int data, unsigned int bit_mask)
-+{
-+ unsigned int reg_val;
-+
-+ reg_val = (__raw_readl(base + offset) & (~bit_mask)) | (data & bit_mask);
-+ __raw_writel(reg_val, base + offset);
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_init_free_queue
-+* (1) Initialize the Free Queue Descriptor Base Address & size
-+* Register: TOE_GLOBAL_BASE + 0x0004
-+* (2) Initialize DMA Read/Write pointer for
-+* SW Free Queue and HW Free Queue
-+* (3) Initialize DMA Descriptors for
-+* SW Free Queue and HW Free Queue,
-+*----------------------------------------------------------------------*/
-+static void toe_init_free_queue(struct toe_private *toe)
-+{
-+ int i;
-+ DMA_RWPTR_T rwptr_reg;
-+ void *desc_buf;
-+ GMAC_RXDESC_T *sw_desc_ptr;
-+ struct sk_buff *skb;
-+
-+ desc_buf = dma_alloc_coherent(toe->dev, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
-+ &toe->sw_freeq_desc_base_dma, GFP_KERNEL);
-+ sw_desc_ptr = (GMAC_RXDESC_T *)desc_buf;
-+ if (!desc_buf) {
-+ dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
-+ return;
-+ }
-+ memset(desc_buf, 0, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
-+
-+ /* DMA Queue Base & Size */
-+ __raw_writel((toe->sw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_SW_FREEQ_DESC_POWER,
-+ toe->global_base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
-+
-+ /* init descriptor base */
-+ toe->swfq_desc_base = (unsigned int)desc_buf;
-+
-+ /* SW Free Queue Descriptors */
-+ for (i = 0; i < TOE_SW_FREEQ_DESC_NUM; i++) {
-+ sw_desc_ptr->word0.bits.buffer_size = SW_RX_BUF_SIZE;
-+ skb = dev_alloc_skb(SW_RX_BUF_SIZE); /* allocate socket buffer */
-+ if (!skb) {
-+ dev_err(toe->dev, "%s::skb buffer allocation fail\n", __func__);
-+ return;
-+ }
-+ REG32(skb->data) = (unsigned int)skb;
-+ skb_reserve(skb, SKB_RESERVE_BYTES);
-+ sw_desc_ptr->word2.buf_adr = dma_map_single(toe->dev, skb->data,
-+ SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
-+ DMA_FROM_DEVICE);
-+ sw_desc_ptr++;
-+ }
-+
-+ dma_sync_single_for_device(toe->dev, toe->sw_freeq_desc_base_dma,
-+ TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
-+ DMA_TO_DEVICE);
-+
-+ /* SW Free Queue Read/Write Pointer */
-+ rwptr_reg.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
-+ rwptr_reg.bits.rptr = 0;
-+ __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
-+
-+ /* DMA Queue Base & Size */
-+ __raw_writel(TOE_HW_FREEQ_DESC_POWER,
-+ toe->global_base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
-+ rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
-+ rwptr_reg.bits.rptr = 0;
-+ __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_HWFQ_RWPTR_REG);
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_init_swtx_queue
-+* (2) Initialize the GMAC 0/1 SW TXQ Queue Descriptor Base Address & sizeup
-+* GMAC_SW_TX_QUEUE_BASE_REG(0x0050)
-+* (2) Initialize DMA Read/Write pointer for
-+* GMAC 0/1 SW TX Q0-5
-+*----------------------------------------------------------------------*/
-+static void toe_init_swtx_queue(struct net_device *dev)
-+{
-+ int i;
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ DMA_RWPTR_T rwptr_reg;
-+ void __iomem *rwptr_addr;
-+ void *desc_buf;
-+ unsigned int offset;
-+
-+ desc_buf = dma_alloc_coherent(toe->dev, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
-+ &gmac->swtxq_desc_base_dma, GFP_KERNEL);
-+ gmac->swtxq_desc_base = (unsigned int)desc_buf;
-+ if (!desc_buf) {
-+ dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
-+ return;
-+ }
-+ memset(desc_buf, 0, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
-+ dma_sync_single_for_device(toe->dev, gmac->swtxq_desc_base_dma,
-+ TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
-+ DMA_TO_DEVICE);
-+ __raw_writel((gmac->swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC_SWTXQ_DESC_POWER,
-+ gmac->dma_base_addr + GMAC_SW_TX_QUEUE_BASE_REG);
-+
-+ /* GMAC0 SW TX Q0-Q5 */
-+ offset = 0;
-+ rwptr_reg.bits.wptr = 0;
-+ rwptr_reg.bits.rptr = 0;
-+ rwptr_addr = gmac->dma_base_addr + GMAC_SW_TX_QUEUE0_PTR_REG;
-+ for (i = 0; i < TOE_SW_TXQ_NUM; i++) {
-+ gmac->swtxq[i].rwptr_reg = rwptr_addr;
-+ gmac->swtxq[i].desc_base_dma = (unsigned int)gmac->swtxq_desc_base_dma + offset;
-+ gmac->swtxq[i].desc_base = (unsigned int)desc_buf + offset;
-+ offset += TOE_GMAC_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
-+ __raw_writel(rwptr_reg.bits32, rwptr_addr);
-+ rwptr_addr += 4;
-+ }
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_init_default_queue
-+* (1) Initialize the default 0/1 Queue Header
-+* Register: TOE_DEFAULT_Q0_HDR_BASE (0x60002000)
-+* TOE_DEFAULT_Q1_HDR_BASE (0x60002008)
-+* (2) Initialize Descriptors of Default Queue 0/1
-+*----------------------------------------------------------------------*/
-+static void toe_init_default_queue(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ volatile NONTOE_QHDR_T *qhdr;
-+ GMAC_RXDESC_T *desc_ptr;
-+
-+ desc_ptr = dma_alloc_coherent(toe->dev, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
-+ &gmac->default_desc_base_dma, GFP_KERNEL);
-+ if (!desc_ptr) {
-+ dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
-+ return;
-+ }
-+ memset(desc_ptr, 0, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T));
-+ dma_sync_single_for_device(toe->dev, gmac->default_desc_base_dma,
-+ TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
-+ DMA_TO_DEVICE);
-+ gmac->default_desc_base = (unsigned int)desc_ptr;
-+ qhdr = (volatile NONTOE_QHDR_T *)(toe->global_base + TOE_DEFAULT_Q_HDR_BASE(gmac->port_id));
-+ qhdr->word0.base_size = ((unsigned int)gmac->default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q_DESC_POWER;
-+ qhdr->word1.bits32 = 0;
-+ gmac->default_qhdr = (NONTOE_QHDR_T *)qhdr;
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_init_interrupt_config
-+* Interrupt Select Registers are used to map interrupt to int0 or int1
-+* Int0 and int1 are wired to CPU 0/1 GMAC 0/1
-+* Interrupt Device Inteface data are used to pass device info to
-+* upper device driver or store status/statistics
-+* ISR handler
-+* (1) If status bit ON but masked, the prinf error message (bug issue)
-+* (2) If select bits are for me, handle it, else skip to let
-+* the other ISR handles it.
-+* Notes:
-+* GMACx init routine (for eCOS) or open routine (for Linux)
-+* enable the interrupt bits only which are selected for it.
-+*
-+* Default Setting:
-+* GMAC0 intr bits ------> int0 ----> eth0
-+* GMAC1 intr bits ------> int1 ----> eth1
-+* TOE intr -------------> int0 ----> eth0
-+* Classification Intr --> int0 ----> eth0
-+* Default Q0 -----------> int0 ----> eth0
-+* Default Q1 -----------> int1 ----> eth1
-+*----------------------------------------------------------------------*/
-+static void toe_init_interrupt_config(struct toe_private *toe)
-+{
-+ /* clear all status bits */
-+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
-+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
-+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
-+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
-+ __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
-+
-+ /* Init select registers */
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
-+
-+ /* disable all interrupt */
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_0_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_1_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_2_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_3_REG);
-+ __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_4_REG);
-+}
-+
-+static void toe_gmac_hw_start(struct gmac_private *gmac)
-+{
-+ GMAC_DMA_CTRL_T dma_ctrl;
-+
-+ /* program dma control register */
-+ dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
-+ dma_ctrl.bits.rd_enable = 1;
-+ dma_ctrl.bits.td_enable = 1;
-+ dma_ctrl.bits.loopback = 0;
-+ dma_ctrl.bits.drop_small_ack = 0;
-+ dma_ctrl.bits.rd_prot = 0;
-+ dma_ctrl.bits.rd_burst_size = 3;
-+ dma_ctrl.bits.rd_insert_bytes = RX_INSERT_BYTES;
-+ dma_ctrl.bits.rd_bus = 3;
-+ dma_ctrl.bits.td_prot = 0;
-+ dma_ctrl.bits.td_burst_size = 3;
-+ dma_ctrl.bits.td_bus = 3;
-+
-+ __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
-+}
-+
-+static void toe_gmac_hw_stop(struct gmac_private *gmac)
-+{
-+ GMAC_DMA_CTRL_T dma_ctrl;
-+
-+ /* program dma control register */
-+ dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
-+ dma_ctrl.bits.rd_enable = 0;
-+ dma_ctrl.bits.td_enable = 0;
-+ __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
-+}
-+
-+static void toe_gmac_init_chip(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ GMAC_CONFIG2_T config2_val;
-+ GMAC_CONFIG0_T config0;
-+ GMAC_CONFIG1_T config1;
-+ GMAC_STATUS_T status;
-+ GMAC_TX_WCR0_T hw_weigh;
-+ GMAC_TX_WCR1_T sw_weigh;
-+ GMAC_RX_FLTR_T rx_filter;
-+
-+ /* set RX_FLTR register to receive all multicast packet */
-+ rx_filter.bits32 = __raw_readl(gmac->base_addr + GMAC_RX_FLTR);
-+ rx_filter.bits.unicast = 1;
-+ rx_filter.bits.multicast = 1;
-+ rx_filter.bits.broadcast = 1;
-+ __raw_writel(rx_filter.bits32, gmac->base_addr + GMAC_RX_FLTR);
-+
-+ /* set flow control threshold */
-+ config1.bits32 = 0;
-+ config1.bits.set_threshold = 32 / 2;
-+ config1.bits.rel_threshold = 32 / 4 * 3;
-+ __raw_writel(config1.bits32, gmac->base_addr + GMAC_CONFIG1);
-+
-+ /* set flow control threshold */
-+ config2_val.bits32 = 0;
-+ config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM / 4;
-+ config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM / 2;
-+ __raw_writel(config2_val.bits32, gmac->base_addr + GMAC_CONFIG2);
-+
-+ /* disable TX/RX and disable internal loop back */
-+ config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
-+
-+ config0.bits.max_len = 2;
-+
-+ gmac->flow_control_enable = 0;
-+
-+ config0.bits.tx_fc_en = 0; /* disable tx flow control */
-+ config0.bits.rx_fc_en = 0; /* disable rx flow control */
-+ config0.bits.dis_rx = 1; /* disable rx */
-+ config0.bits.dis_tx = 1; /* disable tx */
-+ config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
-+ config0.bits.rx_err_detect = 1;
-+ config0.bits.rgmii_en = 0;
-+ config0.bits.rgmm_edge = 1;
-+ config0.bits.rxc_inv = 0;
-+ config0.bits.ipv4_rx_chksum = 1; /* enable H/W to check ip checksum */
-+ config0.bits.ipv6_rx_chksum = 1; /* enable H/W to check ip checksum */
-+ config0.bits.port0_chk_hwq = 1;
-+ config0.bits.port1_chk_hwq = 1;
-+ config0.bits.port0_chk_toeq = 1;
-+ config0.bits.port1_chk_toeq = 1;
-+ config0.bits.port0_chk_classq = 1;
-+ config0.bits.port1_chk_classq = 1;
-+
-+ __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
-+
-+ hw_weigh.bits32 = 0;
-+ hw_weigh.bits.hw_tq3 = 1;
-+ hw_weigh.bits.hw_tq2 = 1;
-+ hw_weigh.bits.hw_tq1 = 1;
-+ hw_weigh.bits.hw_tq0 = 1;
-+ __raw_writel(hw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_0_REG);
-+
-+ sw_weigh.bits32 = 0;
-+ sw_weigh.bits.sw_tq5 = 1;
-+ sw_weigh.bits.sw_tq4 = 1;
-+ sw_weigh.bits.sw_tq3 = 1;
-+ sw_weigh.bits.sw_tq2 = 1;
-+ sw_weigh.bits.sw_tq1 = 1;
-+ sw_weigh.bits.sw_tq0 = 1;
-+ __raw_writel(sw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_1_REG);
-+
-+ /* set interface type */
-+ status.bits32 = __raw_readl(gmac->base_addr + GMAC_STATUS);
-+
-+ switch (gmac->phydev->interface) {
-+ case PHY_INTERFACE_MODE_MII:
-+ status.bits.mii_rmii = GMAC_PHY_MII;
-+ break;
-+ case PHY_INTERFACE_MODE_GMII:
-+ status.bits.mii_rmii = GMAC_PHY_GMII;
-+ break;
-+ case PHY_INTERFACE_MODE_RGMII:
-+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
-+ break;
-+ default:
-+ dev_err(&dev->dev, "Unsupported MII interface\n");
-+ return;
-+ }
-+
-+ __raw_writel(status.bits32, gmac->base_addr + GMAC_STATUS);
-+}
-+
-+static void toe_init_gmac(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ u32 data;
-+
-+ /* GMAC initialization */
-+ toe_gmac_init_chip(dev);
-+
-+ /* -----------------------------------------------------------
-+ Enable GMAC interrupt & disable loopback
-+ Notes:
-+ GMACx init routine (for eCOS) or open routine (for Linux)
-+ enable the interrupt bits only which are selected for him.
-+ --------------------------------------------------------------*/
-+
-+ /* Enable Interrupt Bits */
-+ if (gmac->port_id == 0) {
-+ gmac->intr0_selected = GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT |
-+ GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT |
-+ GMAC0_SWTQ05_FIN_INT_BIT | GMAC0_SWTQ05_EOF_INT_BIT |
-+ GMAC0_SWTQ04_FIN_INT_BIT | GMAC0_SWTQ04_EOF_INT_BIT |
-+ GMAC0_SWTQ03_FIN_INT_BIT | GMAC0_SWTQ03_EOF_INT_BIT |
-+ GMAC0_SWTQ02_FIN_INT_BIT | GMAC0_SWTQ02_EOF_INT_BIT |
-+ GMAC0_SWTQ01_FIN_INT_BIT | GMAC0_SWTQ01_EOF_INT_BIT |
-+ GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
-+
-+#ifdef GMAX_TX_INTR_DISABLED
-+ gmac->intr0_enabled = 0;
-+#else
-+ gmac->intr0_enabled = GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
-+#endif
-+
-+ gmac->intr1_selected = TOE_IQ_ALL_BITS | TOE_CLASS_RX_INT_BITS |
-+ GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
-+ GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT |
-+ DEFAULT_Q0_INT_BIT;
-+ gmac->intr1_enabled = DEFAULT_Q0_INT_BIT | TOE_IQ_ALL_BITS;
-+ gmac->intr2_selected = 0xffffffff; /* TOE Queue 32-63 FUUL Intr */
-+ gmac->intr2_enabled = 0xffffffff;
-+ gmac->intr3_selected = 0xffffffff; /* TOE Queue 0-31 FUUL Intr */
-+ gmac->intr3_enabled = 0xffffffff;
-+ gmac->intr4_selected = GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
-+ HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
-+ gmac->intr4_enabled = GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
-+
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) & ~gmac->intr0_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) & ~gmac->intr1_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) & ~gmac->intr2_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) & ~gmac->intr3_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) & ~gmac->intr4_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
-+ } else {
-+ gmac->intr0_selected = GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT |
-+ GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT |
-+ GMAC1_SWTQ15_FIN_INT_BIT | GMAC1_SWTQ15_EOF_INT_BIT |
-+ GMAC1_SWTQ14_FIN_INT_BIT | GMAC1_SWTQ14_EOF_INT_BIT |
-+ GMAC1_SWTQ13_FIN_INT_BIT | GMAC1_SWTQ13_EOF_INT_BIT |
-+ GMAC1_SWTQ12_FIN_INT_BIT | GMAC1_SWTQ12_EOF_INT_BIT |
-+ GMAC1_SWTQ11_FIN_INT_BIT | GMAC1_SWTQ11_EOF_INT_BIT |
-+ GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
-+#ifdef GMAX_TX_INTR_DISABLED
-+ gmac->intr0_enabled = 0;
-+#else
-+ gmac->intr0_enabled = GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
-+#endif
-+
-+ gmac->intr1_selected = DEFAULT_Q1_INT_BIT;
-+ gmac->intr1_enabled = DEFAULT_Q1_INT_BIT | TOE_IQ_ALL_BITS;
-+ gmac->intr2_selected = 0; /* TOE Queue 32-63 FUUL Intr */
-+ gmac->intr2_enabled = 0;
-+ gmac->intr3_selected = 0; /* TOE Queue 0-31 FUUL Intr */
-+ gmac->intr3_enabled = 0;
-+ gmac->intr4_selected = GMAC1_INT_BITS;
-+ gmac->intr4_enabled = GMAC1_INT_BITS;
-+
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) | gmac->intr0_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) | gmac->intr1_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) | gmac->intr2_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) | gmac->intr3_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
-+ data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) | gmac->intr4_selected;
-+ __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
-+ }
-+
-+ /* enable only selected bits */
-+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_0_REG,
-+ gmac->intr0_enabled, gmac->intr0_selected);
-+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_1_REG,
-+ gmac->intr1_enabled, gmac->intr1_selected);
-+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_2_REG,
-+ gmac->intr2_enabled, gmac->intr2_selected);
-+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_3_REG,
-+ gmac->intr3_enabled, gmac->intr3_selected);
-+ gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_4_REG,
-+ gmac->intr4_enabled, gmac->intr4_selected);
-+
-+ /* start DMA process */
-+ toe_gmac_hw_start(gmac);
-+}
-+
-+static void toe_gmac_enable_tx_rx(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ GMAC_CONFIG0_T config0;
-+
-+ /* enable TX/RX */
-+ config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
-+ config0.bits.dis_rx = 0; /* enable rx */
-+ config0.bits.dis_tx = 0; /* enable tx */
-+ __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
-+}
-+
-+static void toe_gmac_disable_tx_rx(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ GMAC_CONFIG0_T config0;
-+
-+ /* enable TX/RX */
-+ config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
-+ config0.bits.dis_rx = 1; /* disable rx */
-+ config0.bits.dis_tx = 1; /* disable tx */
-+ __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
-+}
-+
-+static void toe_gmac_tx_complete(struct net_device *dev, unsigned int tx_qid)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ GMAC_TXDESC_T *curr_desc;
-+ GMAC_TXDESC_0_T word0;
-+ GMAC_TXDESC_1_T word1;
-+ unsigned int desc_count;
-+ GMAC_SWTXQ_T *swtxq;
-+ DMA_RWPTR_T rwptr;
-+
-+ /* get tx H/W completed descriptor virtual address */
-+ /* check tx status and accumulate tx statistics */
-+ swtxq = &gmac->swtxq[tx_qid];
-+ for (;;) {
-+ rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
-+ if (rwptr.bits.rptr == swtxq->finished_idx)
-+ break;
-+ curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
-+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
-+ swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
-+ sizeof(GMAC_TXDESC_T),
-+ DMA_FROM_DEVICE);
-+ word0.bits32 = curr_desc->word0.bits32;
-+ word1.bits32 = curr_desc->word1.bits32;
-+
-+ if (word0.bits.status_tx_ok) {
-+ dev->stats.tx_bytes += word1.bits.byte_count;
-+ desc_count = word0.bits.desc_count;
-+ if (desc_count == 0) {
-+ dev_err(&dev->dev, "%s::Desc 0x%x = 0x%x, desc_count=%d\n", __func__, (u32)curr_desc, word0.bits32, desc_count);
-+ BUG();
-+ }
-+ while (--desc_count) {
-+ word0.bits.status_tx_ok = 0;
-+ curr_desc->word0.bits32 = word0.bits32;
-+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
-+ swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
-+ sizeof(GMAC_TXDESC_T),
-+ DMA_TO_DEVICE);
-+ swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
-+ curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
-+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
-+ swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
-+ sizeof(GMAC_TXDESC_T),
-+ DMA_FROM_DEVICE);
-+ word0.bits32 = curr_desc->word0.bits32;
-+ }
-+
-+ word0.bits.status_tx_ok = 0;
-+ dev_kfree_skb_any(swtxq->tx_skb[swtxq->finished_idx]);
-+ swtxq->tx_skb[swtxq->finished_idx] = NULL;
-+
-+ curr_desc->word0.bits32 = word0.bits32;
-+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
-+ swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
-+ sizeof(GMAC_TXDESC_T),
-+ DMA_TO_DEVICE);
-+ dev->stats.tx_packets++;
-+ swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
-+ } else {
-+ break;
-+ }
-+ }
-+
-+ if (netif_queue_stopped(dev))
-+ netif_wake_queue(dev);
-+}
-+
-+static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ DMA_RWPTR_T rwptr;
-+ GMAC_TXDESC_T *curr_desc;
-+ int snd_pages = skb_shinfo(skb)->nr_frags + 1; /* get number of descriptor */
-+ int frag_id = 0;
-+ int len, total_len = skb->len;
-+ struct net_device_stats *isPtr = &dev->stats;
-+ unsigned int free_desc;
-+ GMAC_SWTXQ_T *swtxq;
-+ register unsigned long word0, word1, word2, word3;
-+ unsigned short wptr, rptr;
-+
-+#ifdef GMAC_LEN_1_2_ISSUE
-+ int total_pages;
-+ total_pages = snd_pages;
-+#endif
-+
-+ if (skb->len >= 0x10000) {
-+ isPtr->tx_dropped++;
-+ dev_err(&dev->dev, "%s::skb->len %d >= 64K\n", __func__, skb->len);
-+ netif_stop_queue(dev);
-+ return 1;
-+ }
-+
-+#ifdef GMAC_USE_TXQ0
-+ #define tx_qid 0
-+#endif
-+
-+ swtxq = &gmac->swtxq[tx_qid];
-+
-+ rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
-+ wptr = rwptr.bits.wptr;
-+ rptr = rwptr.bits.rptr;
-+
-+ /*
-+ * check finished desc or empty BD
-+ * cannot check by read ptr of RW PTR register,
-+ * because the HW complete to send but the SW may NOT handle it
-+ */
-+#ifdef GMAX_TX_INTR_DISABLED
-+ toe_gmac_tx_complete(dev, tx_qid);
-+#endif
-+ if (wptr >= swtxq->finished_idx)
-+ free_desc = TOE_GMAC_SWTXQ_DESC_NUM - wptr + swtxq->finished_idx;
-+ else
-+ free_desc = swtxq->finished_idx - wptr;
-+
-+ if (free_desc < snd_pages) {
-+ isPtr->tx_dropped++;
-+ netif_stop_queue(dev);
-+ return 1;
-+ }
-+
-+ while (snd_pages) {
-+ dma_addr_t pkt_datap;
-+
-+ curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + wptr;
-+ if (frag_id == 0) {
-+ len = skb_headlen(skb);
-+ pkt_datap = dma_map_single(toe->dev, skb->data, len, DMA_TO_DEVICE);
-+ } else {
-+ skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_id - 1];
-+ len = frag->size;
-+ pkt_datap = dma_map_page(toe->dev, frag->page.p, frag->page_offset, len, DMA_TO_DEVICE);
-+ }
-+
-+ /* set TX descriptor */
-+ word0 = len;
-+ word3 = (dev->mtu + 14) | EOFIE_BIT;
-+
-+#ifdef DO_HW_CHKSUM
-+ if (total_len <= 1514 && ip_hdr(skb) && (ip_hdr(skb)->frag_off & __constant_htons(0x3fff)))
-+ word1 = total_len |
-+ TSS_IP_CHKSUM_BIT |
-+ TSS_IPV6_ENABLE_BIT |
-+ TSS_MTU_ENABLE_BIT;
-+ else
-+ word1 = total_len |
-+ TSS_UDP_CHKSUM_BIT |
-+ TSS_TCP_CHKSUM_BIT |
-+ TSS_IP_CHKSUM_BIT |
-+ TSS_IPV6_ENABLE_BIT |
-+ TSS_MTU_ENABLE_BIT;
-+#else
-+ word1 = total_len | TSS_MTU_ENABLE_BIT;
-+#endif
-+ word2 = (unsigned long)pkt_datap;
-+
-+ if (frag_id == 0)
-+ word3 |= SOF_BIT;
-+
-+ if (snd_pages == 1) {
-+ word3 |= EOF_BIT;
-+ swtxq->tx_skb[wptr] = skb;
-+ } else
-+ swtxq->tx_skb[wptr] = NULL;
-+
-+#ifdef GMAC_LEN_1_2_ISSUE
-+ if ((total_pages != snd_pages) && (len == 1 || len == 2) && ((u32)pkt_datap & 0x03)) {
-+ memcpy((void *)&_debug_prefetch_buf[_debug_prefetch_cnt][0], pkt_datap, len);
-+ pkt_datap = (char *)&_debug_prefetch_buf[_debug_prefetch_cnt][0];
-+ word2 = (unsigned long)__pa(pkt_datap);
-+ _debug_prefetch_cnt++;
-+ if (_debug_prefetch_cnt >= _DEBUG_PREFETCH_NUM)
-+ _debug_prefetch_cnt = 0;
-+ }
-+#endif
-+ curr_desc->word0.bits32 = word0;
-+ curr_desc->word1.bits32 = word1;
-+ curr_desc->word2.bits32 = word2;
-+ curr_desc->word3.bits32 = word3;
-+ free_desc--;
-+ dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
-+ wptr * sizeof(GMAC_TXDESC_T),
-+ sizeof(GMAC_TXDESC_T),
-+ DMA_TO_DEVICE);
-+ wptr = RWPTR_ADVANCE_ONE(wptr, TOE_GMAC_SWTXQ_DESC_NUM);
-+ frag_id++;
-+ snd_pages--;
-+ }
-+
-+ SET_WPTR(swtxq->rwptr_reg, wptr);
-+ dev->trans_start = jiffies;
-+
-+ return 0;
-+}
-+
-+static void __gmac_set_mac_address(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ unsigned int reg_val;
-+
-+ reg_val = dev->dev_addr[0] + (dev->dev_addr[1] << 8) +
-+ (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
-+ __raw_writel(reg_val, gmac->base_addr + GMAC_STA_ADD0);
-+ reg_val = (__raw_readl(gmac->base_addr + GMAC_STA_ADD1) & 0xFFFF0000) +
-+ dev->dev_addr[4] + (dev->dev_addr[5] << 8);
-+ __raw_writel(reg_val, gmac->base_addr + GMAC_STA_ADD1);
-+}
-+
-+static int gmac_set_mac_address(struct net_device *dev, void *addr)
-+{
-+ struct sockaddr *sa = addr;
-+
-+ memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
-+
-+ __gmac_set_mac_address(dev);
-+
-+ return 0;
-+}
-+
-+static void gmac_get_mac_address(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ unsigned int reg_val;
-+
-+ reg_val = __raw_readl(gmac->base_addr + GMAC_STA_ADD0);
-+ dev->dev_addr[0] = reg_val & 0xFF;
-+ dev->dev_addr[1] = (reg_val >> 8) & 0xFF;
-+ dev->dev_addr[2] = (reg_val >> 16) & 0xFF;
-+ dev->dev_addr[3] = (reg_val >> 24) & 0xFF;
-+ reg_val = __raw_readl(gmac->base_addr + GMAC_STA_ADD1);
-+ dev->dev_addr[4] = reg_val & 0xFF;
-+ dev->dev_addr[5] = (reg_val >> 8) & 0xFF;
-+
-+ if (!is_valid_ether_addr(dev->dev_addr)) {
-+ random_ether_addr(dev->dev_addr);
-+ __gmac_set_mac_address(dev);
-+ }
-+}
-+
-+struct net_device_stats *gmac_get_stats(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+
-+ if (netif_running(dev)) {
-+ unsigned short multicast;
-+
-+ multicast = __raw_readw(gmac->base_addr + GMAC_IN_MCAST) +
-+ __raw_readw(gmac->base_addr + GMAC_IN_BCAST);
-+
-+ dev->stats.rx_dropped += __raw_readw(gmac->base_addr + GMAC_IN_DISCARDS);
-+ dev->stats.rx_errors += __raw_readw(gmac->base_addr + GMAC_IN_ERRORS);
-+ dev->stats.rx_packets += __raw_readl(gmac->base_addr + GMAC_IN_MAC1) + multicast;
-+ dev->stats.multicast += multicast;
-+ }
-+
-+ return &dev->stats;
-+}
-+
-+/* TODO: If possible use crc32 from kernel lib */
-+static unsigned const ethernet_polynomial = 0x04c11db7U;
-+static unsigned int ether_crc(int length, unsigned char *data)
-+{
-+ int crc = -1;
-+ unsigned int i;
-+ unsigned int crc_val = 0;
-+
-+ while (--length >= 0) {
-+ unsigned char current_octet = *data++;
-+ int bit;
-+ for (bit = 0; bit < 8; bit++, current_octet >>= 1)
-+ crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
-+ ethernet_polynomial : 0);
-+ }
-+ crc = ~crc;
-+ for (i = 0; i < 32; i++)
-+ crc_val = crc_val + (((crc << i) & 0x80000000) >> (31 - i));
-+
-+ return crc_val;
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_gmac_fill_free_q
-+* allocate buffers for free queue.
-+*----------------------------------------------------------------------*/
-+static void toe_gmac_fill_free_q(struct toe_private *toe)
-+{
-+ struct sk_buff *skb;
-+ DMA_RWPTR_T fq_rwptr;
-+ GMAC_RXDESC_T *fq_desc;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&toe->freeq_lock, flags);
-+ fq_rwptr.bits32 = __raw_readl(toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
-+ while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
-+ TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
-+ skb = dev_alloc_skb(SW_RX_BUF_SIZE);
-+ if (skb == NULL) {
-+ dev_err(toe->dev, "%s::skb allocation fail\n", __func__);
-+ break;
-+ }
-+ REG32(skb->data) = (unsigned int)skb;
-+ skb_reserve(skb, SKB_RESERVE_BYTES);
-+ fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
-+ TOE_SW_FREEQ_DESC_NUM);
-+ fq_desc = (GMAC_RXDESC_T *)toe->swfq_desc_base + fq_rwptr.bits.wptr;
-+ fq_desc->word2.buf_adr = dma_map_single(toe->dev, skb->data,
-+ SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
-+ DMA_FROM_DEVICE);
-+ dma_sync_single_range_for_device(toe->dev,
-+ toe->sw_freeq_desc_base_dma,
-+ fq_rwptr.bits.wptr * sizeof(GMAC_RXDESC_T),
-+ sizeof(GMAC_RXDESC_T),
-+ DMA_TO_DEVICE);
-+ SET_WPTR(toe->global_base + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
-+ }
-+ spin_unlock_irqrestore(&toe->freeq_lock, flags);
-+}
-+
-+static void fill_free_q_worker(struct work_struct *work)
-+{
-+ struct toe_private *toe = container_of(work, struct toe_private, freq_work);
-+
-+ toe_gmac_fill_free_q(toe);
-+}
-+
-+/*----------------------------------------------------------------------
-+* toe_gmac_handle_default_rxq
-+* (1) Get rx Buffer for default Rx queue
-+* (2) notify or call upper-routine to handle it
-+* (3) get a new buffer and insert it into SW free queue
-+* (4) Note: The SW free queue Read-Write Pointer should be locked when accessing
-+*----------------------------------------------------------------------*/
-+static void toe_gmac_handle_default_rxq(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ GMAC_RXDESC_T *curr_desc;
-+ struct sk_buff *skb;
-+ DMA_RWPTR_T rwptr;
-+ unsigned int pkt_size;
-+ int max_cnt;
-+ unsigned int desc_count;
-+ unsigned int chksum_status, rx_status;
-+ struct net_device_stats *isPtr = &dev->stats;
-+
-+ rwptr.bits32 = __raw_readl(&gmac->default_qhdr->word1);
-+ max_cnt = DEFAULT_RXQ_MAX_CNT;
-+ while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr) {
-+ curr_desc = (GMAC_RXDESC_T *)gmac->default_desc_base + rwptr.bits.rptr;
-+ dma_sync_single_range_for_device(toe->dev,
-+ gmac->default_desc_base_dma,
-+ rwptr.bits.rptr * sizeof(GMAC_RXDESC_T),
-+ sizeof(GMAC_RXDESC_T),
-+ DMA_FROM_DEVICE);
-+ rx_status = curr_desc->word0.bits.status;
-+ chksum_status = curr_desc->word0.bits.chksum_status;
-+ pkt_size = curr_desc->word1.bits.byte_count; /* total byte count in a frame */
-+ desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
-+ skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
-+
-+ if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
-+ || (pkt_size < 60) || (chksum_status & 0x4) || rx_status) {
-+ if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
-+ dev_err(&dev->dev, "%s::derr\n", __func__);
-+ if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
-+ dev_err(&dev->dev, "%s::perr\n", __func__);
-+ if (rx_status && (rx_status == 4 || rx_status == 7))
-+ isPtr->rx_crc_errors++;
-+
-+ dev_kfree_skb_irq(skb);
-+ goto bad_frame;
-+ }
-+
-+ if (curr_desc->word0.bits.drop)
-+ dev_warn(&dev->dev, "%s::Drop\n", __func__);
-+
-+ /* get frame information from the first descriptor of the frame */
-+ skb_reserve(skb, RX_INSERT_BYTES); /* 16 byte align the IP fields. */
-+ skb_put(skb, pkt_size);
-+ skb->dev = dev;
-+ skb->protocol = eth_type_trans(skb, dev);
-+ if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK || chksum_status == RX_CHKSUM_IP_OK_ONLY)
-+ skb->ip_summed = CHECKSUM_UNNECESSARY;
-+
-+ netif_rx(skb); /* socket rx */
-+ dev->last_rx = jiffies;
-+
-+ isPtr->rx_bytes += pkt_size;
-+
-+bad_frame:
-+ /* advance one for Rx default Q 0/1 */
-+ rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, TOE_DEFAULT_Q_DESC_NUM);
-+ SET_RPTR(&gmac->default_qhdr->word1, rwptr.bits.rptr);
-+ }
-+
-+ schedule_work(&toe->freq_work);
-+}
-+
-+static irqreturn_t toe_gmac_interrupt(int irq, void *dev_instance)
-+{
-+ struct net_device *dev = dev_instance;
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ struct toe_private *toe = dev->ml_priv;
-+ unsigned int status0;
-+ unsigned int status1;
-+ unsigned int status2;
-+ unsigned int status3;
-+ unsigned int status4;
-+ int handled = 0;
-+
-+ /* read Interrupt status */
-+ status0 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
-+ status1 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
-+ status2 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
-+ status3 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
-+ status4 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
-+
-+ /* clear interrupts */
-+ if (status0)
-+ __raw_writel(status0, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
-+ if (status1)
-+ __raw_writel(status1, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
-+ if (status2)
-+ __raw_writel(status2, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
-+ if (status3)
-+ __raw_writel(status3, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
-+ if (status4)
-+ __raw_writel(status4, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
-+
-+ /* handle freeq interrupt first */
-+ if (status4 & gmac->intr4_enabled) {
-+ if ((status4 & SWFQ_EMPTY_INT_BIT) && (gmac->intr4_enabled & SWFQ_EMPTY_INT_BIT)) {
-+ toe_gmac_fill_free_q(toe);
-+ handled = 1;
-+ }
-+ }
-+
-+ /* Interrupt Status 1 */
-+ if (status1 & gmac->intr1_enabled) {
-+ /*
-+ * Handle GMAC 0/1 HW Tx queue 0-3 EOF events
-+ * Only count
-+ * TOE, Classification, and default queues interrupts are handled by ISR
-+ * because they should pass packets to upper layer
-+ */
-+ if (gmac->port_id == 0) {
-+ if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q0_INT_BIT)) {
-+ toe_gmac_handle_default_rxq(dev);
-+ handled = 1;
-+ }
-+ } else if (gmac->port_id == 1) {
-+ if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q1_INT_BIT)) {
-+ toe_gmac_handle_default_rxq(dev);
-+ handled = 1;
-+ }
-+ }
-+ }
-+
-+ /* Interrupt Status 0 */
-+ if (status0 & gmac->intr0_enabled) {
-+#ifndef GMAX_TX_INTR_DISABLED
-+ if (gmac->port_id == 1 && netif_running(dev) &&
-+ (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
-+ ||
-+ ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT)))) {
-+ toe_gmac_tx_complete(dev, 0);
-+ handled = 1;
-+ }
-+
-+ if (gmac->port_id == 0 && netif_running(dev) &&
-+ (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
-+ ||
-+ ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT)))) {
-+ toe_gmac_tx_complete(dev, 0);
-+ handled = 1;
-+ }
-+#endif
-+ }
-+
-+ return IRQ_RETVAL(handled);
-+}
-+
-+static int gmac_open(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ int retval;
-+
-+ /* hook ISR */
-+ retval = request_irq(dev->irq, toe_gmac_interrupt, 0, dev->name, dev);
-+ if (retval)
-+ return retval;
-+
-+ toe_init_gmac(dev);
-+
-+ netif_carrier_off(dev);
-+ phy_start(gmac->phydev);
-+
-+ netif_start_queue(dev);
-+
-+ return 0;
-+}
-+
-+static int gmac_close(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+
-+ netif_stop_queue(dev);
-+ mdelay(20);
-+
-+ if (gmac->phydev)
-+ phy_stop(gmac->phydev);
-+
-+ /* stop tx/rx packet */
-+ toe_gmac_disable_tx_rx(dev);
-+ mdelay(20);
-+
-+ /* stop the chip's Tx and Rx DMA processes */
-+ toe_gmac_hw_stop(gmac);
-+
-+ disable_irq(dev->irq);
-+ free_irq(dev->irq, dev);
-+
-+ return 0;
-+}
-+
-+static void gmac_get_phy_status(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ GMAC_CONFIG0_T config0;
-+ GMAC_STATUS_T status, old_status;
-+ struct phy_device *phydev = gmac->phydev;
-+
-+ old_status.bits32 = status.bits32 = __raw_readl(gmac->base_addr + GMAC_STATUS);
-+
-+ status.bits.link = phydev->link;
-+ status.bits.duplex = phydev->duplex;
-+
-+ switch (phydev->speed) {
-+ case 1000:
-+ status.bits.speed = GMAC_SPEED_1000;
-+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
-+ status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
-+ break;
-+ case 100:
-+ status.bits.speed = GMAC_SPEED_100;
-+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
-+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
-+ break;
-+ case 10:
-+ status.bits.speed = GMAC_SPEED_10;
-+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
-+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
-+ break;
-+ default:
-+ dev_warn(&dev->dev, "Not supported PHY speed (%d)\n", phydev->speed);
-+ }
-+
-+ if (phydev->pause) {
-+ if (gmac->flow_control_enable == 0) {
-+ config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
-+ config0.bits.tx_fc_en = 1; /* enable tx flow control */
-+ config0.bits.rx_fc_en = 1; /* enable rx flow control */
-+ __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
-+ dev_info(&dev->dev, "MII flow control enabled\n");
-+ }
-+ gmac->flow_control_enable = 1;
-+ } else {
-+ if (gmac->flow_control_enable == 1) {
-+ config0.bits32 = __raw_readl(gmac->base_addr + GMAC_CONFIG0);
-+ config0.bits.tx_fc_en = 0; /* disable tx flow control */
-+ config0.bits.rx_fc_en = 0; /* disable rx flow control */
-+ __raw_writel(config0.bits32, gmac->base_addr + GMAC_CONFIG0);
-+ dev_info(&dev->dev, "MII flow control disabled\n");
-+ }
-+ gmac->flow_control_enable = 0;
-+ }
-+
-+ if (old_status.bits32 != status.bits32) {
-+ toe_gmac_disable_tx_rx(dev);
-+ phy_print_status(phydev);
-+ mdelay(10); /* let GMAC consume packet */
-+ __raw_writel(status.bits32, gmac->base_addr + GMAC_STATUS);
-+ if (status.bits.link)
-+ toe_gmac_enable_tx_rx(dev);
-+ }
-+}
-+
-+static void gmac_set_rx_mode(struct net_device *dev)
-+{
-+ struct gmac_private *gmac = netdev_priv(dev);
-+ GMAC_RX_FLTR_T filter;
-+ unsigned int mc_filter[2]; /* Multicast hash filter */
-+ int bit_nr;
-+
-+ filter.bits32 = 0;
-+ filter.bits.error = 0;
-+ if (dev->flags & IFF_PROMISC) {
-+ filter.bits.error = 1;
-+ filter.bits.promiscuous = 1;
-+ filter.bits.broadcast = 1;
-+ filter.bits.multicast = 1;
-+ filter.bits.unicast = 1;
-+ mc_filter[1] = mc_filter[0] = 0xffffffff;
-+ } else if (dev->flags & IFF_ALLMULTI) {
-+ filter.bits.broadcast = 1;
-+ filter.bits.multicast = 1;
-+ filter.bits.unicast = 1;
-+ mc_filter[1] = mc_filter[0] = 0xffffffff;
-+ } else {
-+ struct netdev_hw_addr *ha;
-+
-+ filter.bits.broadcast = 1;
-+ filter.bits.multicast = 1;
-+ filter.bits.unicast = 1;
-+ mc_filter[1] = mc_filter[0] = 0;
-+ netdev_for_each_mc_addr(ha, dev) {
-+ bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
-+ if (bit_nr <= 32)
-+ mc_filter[0] = mc_filter[0] | (1 << bit_nr);
-+ else
-+ mc_filter[1] = mc_filter[1] | (1 << (bit_nr - 32));
-+ }
-+ }
-+ __raw_writel(filter.bits32, gmac->base_addr + GMAC_RX_FLTR);
-+ __raw_writel(mc_filter[0], gmac->base_addr + GMAC_MCAST_FIL0);
-+ __raw_writel(mc_filter[1], gmac->base_addr + GMAC_MCAST_FIL1);
-+}
-+
-+static void gmac_tx_timeout(struct net_device *dev)
-+{
-+ if (!netif_queue_stopped(dev))
-+ netif_wake_queue(dev);
-+
-+ dev_warn(&dev->dev, "TX timeout\n");
-+}
-+
-+const static struct net_device_ops gemini_gmac_ops = {
-+ .ndo_open = gmac_open,
-+ .ndo_stop = gmac_close,
-+ .ndo_start_xmit = gmac_start_xmit,
-+ .ndo_get_stats = gmac_get_stats,
-+ .ndo_set_rx_mode = gmac_set_rx_mode,
-+ .ndo_set_mac_address = gmac_set_mac_address,
-+ .ndo_tx_timeout = gmac_tx_timeout,
-+};
-+
-+static void mac_init_drv(struct toe_private *toe)
-+{
-+ QUEUE_THRESHOLD_T threshold;
-+ DMA_SKB_SIZE_T skb_size;
-+
-+ /* clear non TOE Queue Header Area */
-+ memset(toe->global_base + TOE_NONTOE_QUE_HDR_BASE, 0,
-+ NONTOE_Q_HDR_AREA_END - TOE_NONTOE_QUE_HDR_BASE);
-+
-+ /* clear TOE Queue Header Area */
-+ memset(toe->global_base + TOE_TOE_QUE_HDR_BASE, 0,
-+ TOE_Q_HDR_AREA_END - TOE_TOE_QUE_HDR_BASE);
-+
-+ /* Write GLOBAL_QUEUE_THRESHOLD_REG */
-+ threshold.bits32 = 0;
-+ threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
-+ TOE_SW_FREEQ_DESC_NUM / 2;
-+ threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256 / 4 :
-+ TOE_HW_FREEQ_DESC_NUM / 4;
-+ threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256 / 4 :
-+ TOE_TOE_DESC_NUM / 4;
-+ threshold.bits.intrq = (TOE_INTR_DESC_NUM > 256) ? 256 / 4 :
-+ TOE_INTR_DESC_NUM / 4;
-+ __raw_writel(threshold.bits32, toe->global_base + GLOBAL_QUEUE_THRESHOLD_REG);
-+
-+ /* Init skb size */
-+ skb_size.bits.hw_skb_size = HW_RX_BUF_SIZE;
-+ skb_size.bits.sw_skb_size = SW_RX_BUF_SIZE;
-+ __raw_writel(skb_size.bits32, toe->global_base + GLOBAL_DMA_SKB_SIZE_REG);
-+
-+ toe_init_free_queue(toe);
-+ toe_init_interrupt_config(toe);
-+}
-+
-+static int gmac_init_eth(struct platform_device *pdev,
-+ unsigned int num)
-+{
-+ struct gmac_private *gmac;
-+ struct net_device *dev;
-+ struct toe_private *toe = platform_get_drvdata(pdev);
-+ struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
-+
-+ if (!pdata->bus_id[num])
-+ return 0;
-+
-+ dev = alloc_etherdev(sizeof(*gmac));
-+ if (dev == NULL) {
-+ dev_err(&pdev->dev, "Can't allocate ethernet device #%d\n", num);
-+ return -ENOMEM;
-+ }
-+
-+ gmac = netdev_priv(dev);
-+ dev->ml_priv = toe;
-+ toe->net_dev[num] = dev;
-+
-+ gmac->base_addr = toe->global_base + TOE_GMAC_BASE(num);
-+ gmac->dma_base_addr = toe->global_base + TOE_GMAC_DMA_BASE(num);
-+ gmac->port_id = num;
-+
-+ dev->base_addr = (unsigned int) gmac->base_addr;
-+ dev->irq = platform_get_irq(pdev, num);
-+ dev->netdev_ops = &gemini_gmac_ops;
-+ dev->watchdog_timeo = GMAC_DEV_TX_TIMEOUT;
-+ dev->tx_queue_len = TOE_GMAC_SWTXQ_DESC_NUM;
-+
-+#ifdef DO_HW_CHKSUM
-+ dev->features = NETIF_F_SG | NETIF_F_HW_CSUM;
-+#ifdef ENABLE_TSO
-+ dev->features |= NETIF_F_TSO;
-+#endif
-+#endif
-+
-+ toe_init_swtx_queue(dev);
-+ toe_init_default_queue(dev);
-+
-+ gmac_get_mac_address(dev);
-+
-+ /* TODO: Do we need this? */
-+ __raw_writel(0x55aa55aa, gmac->base_addr + GMAC_STA_ADD2);
-+
-+ if (register_netdev(dev))
-+ return -1;
-+
-+ gmac->phydev = phy_connect(dev, pdata->bus_id[num], &gmac_get_phy_status,
-+ pdata->interface[num]);
-+ if (IS_ERR(gmac->phydev))
-+ return PTR_ERR(gmac->phydev);
-+
-+ gmac->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause;
-+ gmac->phydev->advertising = gmac->phydev->supported;
-+
-+ return 0;
-+}
-+
-+static int gmac_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ struct toe_private *toe;
-+ int retval;
-+
-+ if (!pdev->dev.platform_data)
-+ return -EINVAL;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(&pdev->dev, "can't get device resources\n");
-+ return -ENODEV;
-+ }
-+
-+ toe = kzalloc(sizeof(struct toe_private), GFP_KERNEL);
-+ if (!toe)
-+ return -ENOMEM;
-+
-+ toe->dev = &pdev->dev;
-+
-+ toe->global_base = ioremap(res->start, resource_size(res));
-+ if (!toe->global_base) {
-+ dev_err(toe->dev, "ioremap failed\n");
-+ retval = -EIO;
-+ goto err_data;
-+ }
-+
-+ platform_set_drvdata(pdev, toe);
-+
-+ mac_init_drv(toe);
-+
-+ INIT_WORK(&toe->freq_work, fill_free_q_worker);
-+ spin_lock_init(&toe->freeq_lock);
-+
-+ retval = gmac_init_eth(pdev, GMAC_PORT0);
-+ if (retval)
-+ goto err_unmap;
-+ retval = gmac_init_eth(pdev, GMAC_PORT1);
-+ if (retval)
-+ goto err_unmap;
-+
-+ dev_info(&pdev->dev, SL351x_DRIVER_NAME "\n");
-+
-+ return 0;
-+
-+err_unmap:
-+ iounmap(toe->global_base);
-+err_data:
-+ kfree(toe);
-+ return retval;
-+}
-+
-+static int gmac_remove(struct platform_device *pdev)
-+{
-+ struct toe_private *toe = platform_get_drvdata(pdev);
-+ int i;
-+
-+ for (i = 0; i < 2; i++)
-+ if (toe->net_dev[i]) {
-+ unregister_netdev(toe->net_dev[i]);
-+ kfree(toe->net_dev[i]);
-+ }
-+
-+ iounmap(toe->global_base);
-+
-+ kfree(toe);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver gemini_gmac_driver = {
-+ .probe = gmac_probe,
-+ .remove = gmac_remove,
-+ .driver = {
-+ .name = "gemini-gmac",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init gemini_gmac_init(void)
-+{
-+ return platform_driver_register(&gemini_gmac_driver);
-+}
-+
-+static void __exit gemini_gmac_exit(void)
-+{
-+ platform_driver_unregister(&gemini_gmac_driver);
-+}
-+
-+module_init(gemini_gmac_init);
-+module_exit(gemini_gmac_exit);
-+
-+MODULE_AUTHOR("Paulius Zaleckas");
-+MODULE_DESCRIPTION("Ethernet device driver for Gemini SoC");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:gemini-gmac");
---- /dev/null
-+++ b/drivers/net/gemini_negmac/gm_gmac.h
-@@ -0,0 +1,1489 @@
-+/*
-+ * Register definitions for Gemini Ethernet device driver.
-+ *
-+ * Copyright (C) 2006, Storlink, Corp.
-+ * Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+#ifndef _GMAC_SL351x_H
-+#define _GMAC_SL351x_H
-+#include <linux/skbuff.h>
-+
-+#define _PACKED_ __attribute__ ((aligned(1), packed))
-+
-+#ifndef BIT
-+#define BIT(x) (1 << (x))
-+#endif
-+
-+#define REG32(addr) (*(volatile unsigned long * const)(addr))
-+
-+/* Define frame size */
-+#define GMAC_MAX_ETH_FRAME_SIZE 1514
-+#define GMAC_TX_BUF_SIZE ((GMAC_MAX_ETH_FRAME_SIZE + 31) & (~31))
-+
-+#define SW_RX_BUF_SIZE 1536
-+#define HW_RX_BUF_SIZE 1536
-+
-+#define GMAC_DEV_TX_TIMEOUT (10*HZ)
-+#define SKB_RESERVE_BYTES 16
-+
-+/*
-+ * Base Registers
-+ */
-+#define TOE_NONTOE_QUE_HDR_BASE 0x2000
-+#define TOE_TOE_QUE_HDR_BASE 0x3000
-+#define TOE_V_BIT_BASE 0x4000
-+#define TOE_A_BIT_BASE 0x6000
-+#define TOE_GMAC_DMA_BASE(x) (0x8000 + 0x4000 * (x))
-+#define TOE_GMAC_BASE(x) (0xA000 + 0x4000 * (x))
-+
-+/*
-+ * Queue ID
-+ */
-+#define TOE_SW_FREE_QID 0x00
-+#define TOE_HW_FREE_QID 0x01
-+#define TOE_GMAC0_SW_TXQ0_QID 0x02
-+#define TOE_GMAC0_SW_TXQ1_QID 0x03
-+#define TOE_GMAC0_SW_TXQ2_QID 0x04
-+#define TOE_GMAC0_SW_TXQ3_QID 0x05
-+#define TOE_GMAC0_SW_TXQ4_QID 0x06
-+#define TOE_GMAC0_SW_TXQ5_QID 0x07
-+#define TOE_GMAC0_HW_TXQ0_QID 0x08
-+#define TOE_GMAC0_HW_TXQ1_QID 0x09
-+#define TOE_GMAC0_HW_TXQ2_QID 0x0A
-+#define TOE_GMAC0_HW_TXQ3_QID 0x0B
-+#define TOE_GMAC1_SW_TXQ0_QID 0x12
-+#define TOE_GMAC1_SW_TXQ1_QID 0x13
-+#define TOE_GMAC1_SW_TXQ2_QID 0x14
-+#define TOE_GMAC1_SW_TXQ3_QID 0x15
-+#define TOE_GMAC1_SW_TXQ4_QID 0x16
-+#define TOE_GMAC1_SW_TXQ5_QID 0x17
-+#define TOE_GMAC1_HW_TXQ0_QID 0x18
-+#define TOE_GMAC1_HW_TXQ1_QID 0x19
-+#define TOE_GMAC1_HW_TXQ2_QID 0x1A
-+#define TOE_GMAC1_HW_TXQ3_QID 0x1B
-+#define TOE_GMAC0_DEFAULT_QID 0x20
-+#define TOE_GMAC1_DEFAULT_QID 0x21
-+#define TOE_CLASSIFICATION_QID(x) (0x22 + x) // 0x22 ~ 0x2F
-+#define TOE_TOE_QID(x) (0x40 + x) // 0x40 ~ 0x7F
-+
-+/*
-+ * TOE DMA Queue Number should be 2^n, n = 6...12
-+ * TOE DMA Queues are the following queue types:
-+ * SW Free Queue, HW Free Queue,
-+ * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
-+ * They have same descriptor numbers.
-+ * The base address and descriptor number are configured at
-+ * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
-+ */
-+#define TOE_SW_FREEQ_DESC_POWER 8
-+#define TOE_SW_FREEQ_DESC_NUM (1<<TOE_SW_FREEQ_DESC_POWER)
-+#define TOE_HW_FREEQ_DESC_POWER 8
-+#define TOE_HW_FREEQ_DESC_NUM (1<<TOE_HW_FREEQ_DESC_POWER)
-+#define TOE_GMAC_SWTXQ_DESC_POWER 8
-+#define TOE_GMAC_SWTXQ_DESC_NUM (1<<TOE_GMAC_SWTXQ_DESC_POWER)
-+#define TOE_GMAC_HWTXQ_DESC_POWER 8
-+#define TOE_GMAC_HWTXQ_DESC_NUM (1<<TOE_GMAC_HWTXQ_DESC_POWER)
-+#define TOE_DEFAULT_Q_DESC_POWER 8
-+#define TOE_DEFAULT_Q_DESC_NUM (1<<TOE_DEFAULT_Q_DESC_POWER)
-+#define TOE_TOE_DESC_POWER 8
-+#define TOE_TOE_DESC_NUM (1<<TOE_TOE_DESC_POWER)
-+#define TOE_CLASS_DESC_POWER 8
-+#define TOE_CLASS_DESC_NUM (1<<TOE_CLASS_DESC_POWER)
-+#define TOE_INTR_DESC_POWER 8
-+#define TOE_INTR_DESC_NUM (1<<TOE_INTR_DESC_POWER)
-+
-+#define TOE_TOE_QUEUE_MAX 64
-+#define TOE_TOE_QUEUE_NUM 64
-+#define TOE_CLASS_QUEUE_MAX 14
-+#define TOE_CLASS_QUEUE_NUM 14
-+#define TOE_INTR_QUEUE_MAX 4
-+#define TOE_INTR_QUEUE_NUM 4
-+#define TOE_SW_TXQ_MAX 6
-+#define TOE_SW_TXQ_NUM 1
-+#define TOE_HW_TXQ_MAX 4
-+#define TOE_HW_TXQ_NUM 4
-+
-+#define RWPTR_ADVANCE_ONE(x, max) ((x == (max -1)) ? 0 : x+1)
-+#define RWPTR_RECEDE_ONE(x, max) ((x == 0) ? (max -1) : x-1)
-+#define SET_WPTR(addr, data) (*(volatile u16 * const)((u32)(addr) + 2) = (u16)data)
-+#define SET_RPTR(addr, data) (*(volatile u16 * const)((u32)(addr)) = (u16)data)
-+
-+/*
-+ * Global registers
-+ * #define TOE_GLOBAL_BASE (TOE_BASE + 0x0000)
-+ * Base 0x60000000
-+ */
-+#define GLOBAL_TOE_VERSION_REG 0x0000
-+#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004
-+#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008
-+#define GLOBAL_DMA_SKB_SIZE_REG 0x0010
-+#define GLOBAL_SWFQ_RWPTR_REG 0x0014
-+#define GLOBAL_HWFQ_RWPTR_REG 0x0018
-+#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020
-+#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024
-+#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028
-+#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030
-+#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034
-+#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038
-+#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040
-+#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044
-+#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048
-+#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050
-+#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054
-+#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058
-+#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060
-+#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064
-+#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068
-+#define GLOBAL_HASH_TABLE_BASE_REG 0x006C
-+#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070
-+
-+/*
-+ * GMAC 0/1 DMA/TOE register
-+ * #define TOE_GMAC0_DMA_BASE (TOE_BASE + 0x8000)
-+ * #define TOE_GMAC1_DMA_BASE (TOE_BASE + 0xC000)
-+ * Base 0x60008000 or 0x6000C000
-+ */
-+#define GMAC_DMA_CTRL_REG 0x0000
-+#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004
-+#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008
-+#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C
-+#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010
-+#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014
-+#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018
-+#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C
-+#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020
-+#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024
-+#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028
-+#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C
-+#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030
-+#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038
-+#define GMAC_DMA_TX_CURR_DESC_REG 0x003C
-+#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040
-+#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044
-+#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048
-+#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C
-+#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050
-+#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054
-+#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058
-+#define GMAC_DMA_RX_CURR_DESC_REG 0x005C
-+#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060
-+#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064
-+#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068
-+#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C
-+#define GMAC_HASH_ENGINE_REG0 0x0070
-+#define GMAC_HASH_ENGINE_REG1 0x0074
-+/* matching rule 0 Control register 0 */
-+#define GMAC_MR0CR0 0x0078
-+#define GMAC_MR0CR1 0x007C
-+#define GMAC_MR0CR2 0x0080
-+#define GMAC_MR1CR0 0x0084
-+#define GMAC_MR1CR1 0x0088
-+#define GMAC_MR1CR2 0x008C
-+#define GMAC_MR2CR0 0x0090
-+#define GMAC_MR2CR1 0x0094
-+#define GMAC_MR2CR2 0x0098
-+#define GMAC_MR3CR0 0x009C
-+#define GMAC_MR3CR1 0x00A0
-+#define GMAC_MR3CR2 0x00A4
-+/* Support Protocol Regsister 0 */
-+#define GMAC_SPR0 0x00A8
-+#define GMAC_SPR1 0x00AC
-+#define GMAC_SPR2 0x00B0
-+#define GMAC_SPR3 0x00B4
-+#define GMAC_SPR4 0x00B8
-+#define GMAC_SPR5 0x00BC
-+#define GMAC_SPR6 0x00C0
-+#define GMAC_SPR7 0x00C4
-+/* GMAC Hash/Rx/Tx AHB Weighting register */
-+#define GMAC_AHB_WEIGHT_REG 0x00C8
-+
-+/*
-+ * TOE GMAC 0/1 register
-+ * #define TOE_GMAC0_BASE (TOE_BASE + 0xA000)
-+ * #define TOE_GMAC1_BASE (TOE_BASE + 0xE000)
-+ * Base 0x6000A000 or 0x6000E000
-+ */
-+enum GMAC_REGISTER {
-+ GMAC_STA_ADD0 = 0x0000,
-+ GMAC_STA_ADD1 = 0x0004,
-+ GMAC_STA_ADD2 = 0x0008,
-+ GMAC_RX_FLTR = 0x000c,
-+ GMAC_MCAST_FIL0 = 0x0010,
-+ GMAC_MCAST_FIL1 = 0x0014,
-+ GMAC_CONFIG0 = 0x0018,
-+ GMAC_CONFIG1 = 0x001c,
-+ GMAC_CONFIG2 = 0x0020,
-+ GMAC_CONFIG3 = 0x0024,
-+ GMAC_RESERVED = 0x0028,
-+ GMAC_STATUS = 0x002c,
-+ GMAC_IN_DISCARDS= 0x0030,
-+ GMAC_IN_ERRORS = 0x0034,
-+ GMAC_IN_MCAST = 0x0038,
-+ GMAC_IN_BCAST = 0x003c,
-+ GMAC_IN_MAC1 = 0x0040, /* for STA 1 MAC Address */
-+ GMAC_IN_MAC2 = 0x0044 /* for STA 2 MAC Address */
-+};
-+
-+/*
-+ * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int base_size;
-+} DMA_Q_BASE_SIZE_T;
-+#define DMA_Q_BASE_MASK (~0x0f)
-+
-+/*
-+ * DMA SKB Buffer register (offset 0x0008)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0008 {
-+ unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */
-+ unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */
-+ } bits;
-+} DMA_SKB_SIZE_T;
-+
-+/*
-+ * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_000c {
-+ unsigned int rptr : 16; /* Read Ptr, RO */
-+ unsigned int wptr : 16; /* Write Ptr, RW */
-+ } bits;
-+} DMA_RWPTR_T;
-+
-+/*
-+ * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
-+ * see DMA_RWPTR_T structure
-+ */
-+
-+/*
-+ * Interrupt Status Register 0 (offset 0x0020)
-+ * Interrupt Mask Register 0 (offset 0x0024)
-+ * Interrupt Select Register 0 (offset 0x0028)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0020 {
-+ /* GMAC0 SW Tx Queue 0 EOF Interrupt */
-+ unsigned int swtq00_eof : 1;
-+ unsigned int swtq01_eof : 1;
-+ unsigned int swtq02_eof : 1;
-+ unsigned int swtq03_eof : 1;
-+ unsigned int swtq04_eof : 1;
-+ unsigned int swtq05_eof : 1;
-+ /* GMAC1 SW Tx Queue 0 EOF Interrupt */
-+ unsigned int swtq10_eof : 1;
-+ unsigned int swtq11_eof : 1;
-+ unsigned int swtq12_eof : 1;
-+ unsigned int swtq13_eof : 1;
-+ unsigned int swtq14_eof : 1;
-+ unsigned int swtq15_eof : 1;
-+ /* GMAC0 SW Tx Queue 0 Finish Interrupt */
-+ unsigned int swtq00_fin : 1;
-+ unsigned int swtq01_fin : 1;
-+ unsigned int swtq02_fin : 1;
-+ unsigned int swtq03_fin : 1;
-+ unsigned int swtq04_fin : 1;
-+ unsigned int swtq05_fin : 1;
-+ /* GMAC1 SW Tx Queue 0 Finish Interrupt */
-+ unsigned int swtq10_fin : 1;
-+ unsigned int swtq11_fin : 1;
-+ unsigned int swtq12_fin : 1;
-+ unsigned int swtq13_fin : 1;
-+ unsigned int swtq14_fin : 1;
-+ unsigned int swtq15_fin : 1;
-+ /* GMAC0 Rx Descriptor Protocol Error */
-+ unsigned int rxPerr0 : 1;
-+ /* GMAC0 AHB Bus Error while Rx */
-+ unsigned int rxDerr0 : 1;
-+ /* GMAC1 Rx Descriptor Protocol Error */
-+ unsigned int rxPerr1 : 1;
-+ /* GMAC1 AHB Bus Error while Rx */
-+ unsigned int rxDerr1 : 1;
-+ /* GMAC0 Tx Descriptor Protocol Error */
-+ unsigned int txPerr0 : 1;
-+ /* GMAC0 AHB Bus Error while Tx */
-+ unsigned int txDerr0 : 1;
-+ /* GMAC1 Tx Descriptor Protocol Error */
-+ unsigned int txPerr1 : 1;
-+ /* GMAC1 AHB Bus Error while Tx */
-+ unsigned int txDerr1 : 1;
-+ } bits;
-+} INTR_REG0_T;
-+
-+#define GMAC1_TXDERR_INT_BIT BIT(31)
-+#define GMAC1_TXPERR_INT_BIT BIT(30)
-+#define GMAC0_TXDERR_INT_BIT BIT(29)
-+#define GMAC0_TXPERR_INT_BIT BIT(28)
-+#define GMAC1_RXDERR_INT_BIT BIT(27)
-+#define GMAC1_RXPERR_INT_BIT BIT(26)
-+#define GMAC0_RXDERR_INT_BIT BIT(25)
-+#define GMAC0_RXPERR_INT_BIT BIT(24)
-+#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23)
-+#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22)
-+#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21)
-+#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20)
-+#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19)
-+#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18)
-+#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17)
-+#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16)
-+#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15)
-+#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14)
-+#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13)
-+#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12)
-+#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11)
-+#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10)
-+#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9)
-+#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8)
-+#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7)
-+#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6)
-+#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5)
-+#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4)
-+#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3)
-+#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2)
-+#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1)
-+#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0)
-+
-+/*
-+ * Interrupt Status Register 1 (offset 0x0030)
-+ * Interrupt Mask Register 1 (offset 0x0034)
-+ * Interrupt Select Register 1 (offset 0x0038)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0030 {
-+ unsigned int default_q0_eof : 1; /* Default Queue 0 EOF Interrupt */
-+ unsigned int default_q1_eof : 1; /* Default Queue 1 EOF Interrupt */
-+ unsigned int class_rx : 14; /* Classification Queue Rx Interrupt */
-+ unsigned int hwtq00_eof : 1; /* GMAC0 HW Tx Queue0 EOF Interrupt */
-+ unsigned int hwtq01_eof : 1; /* GMAC0 HW Tx Queue1 EOF Interrupt */
-+ unsigned int hwtq02_eof : 1; /* GMAC0 HW Tx Queue2 EOF Interrupt */
-+ unsigned int hwtq03_eof : 1; /* GMAC0 HW Tx Queue3 EOF Interrupt */
-+ unsigned int hwtq10_eof : 1; /* GMAC1 HW Tx Queue0 EOF Interrupt */
-+ unsigned int hwtq11_eof : 1; /* GMAC1 HW Tx Queue1 EOF Interrupt */
-+ unsigned int hwtq12_eof : 1; /* GMAC1 HW Tx Queue2 EOF Interrupt */
-+ unsigned int hwtq13_eof : 1; /* GMAC1 HW Tx Queue3 EOF Interrupt */
-+ unsigned int toe_iq0_intr : 1; /* TOE Interrupt Queue 0 with Interrupts */
-+ unsigned int toe_iq1_intr : 1; /* TOE Interrupt Queue 1 with Interrupts */
-+ unsigned int toe_iq2_intr : 1; /* TOE Interrupt Queue 2 with Interrupts */
-+ unsigned int toe_iq3_intr : 1; /* TOE Interrupt Queue 3 with Interrupts */
-+ unsigned int toe_iq0_full : 1; /* TOE Interrupt Queue 0 Full Interrupt */
-+ unsigned int toe_iq1_full : 1; /* TOE Interrupt Queue 1 Full Interrupt */
-+ unsigned int toe_iq2_full : 1; /* TOE Interrupt Queue 2 Full Interrupt */
-+ unsigned int toe_iq3_full : 1; /* TOE Interrupt Queue 3 Full Interrupt */
-+ } bits;
-+} INTR_REG1_T;
-+
-+#define TOE_IQ3_FULL_INT_BIT BIT(31)
-+#define TOE_IQ2_FULL_INT_BIT BIT(30)
-+#define TOE_IQ1_FULL_INT_BIT BIT(29)
-+#define TOE_IQ0_FULL_INT_BIT BIT(28)
-+#define TOE_IQ3_INT_BIT BIT(27)
-+#define TOE_IQ2_INT_BIT BIT(26)
-+#define TOE_IQ1_INT_BIT BIT(25)
-+#define TOE_IQ0_INT_BIT BIT(24)
-+#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23)
-+#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22)
-+#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21)
-+#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20)
-+#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19)
-+#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18)
-+#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17)
-+#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16)
-+#define CLASS_RX_INT_BIT(x) BIT((x + 2))
-+#define DEFAULT_Q1_INT_BIT BIT(1)
-+#define DEFAULT_Q0_INT_BIT BIT(0)
-+
-+#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
-+ TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
-+#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
-+ TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
-+#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
-+#define TOE_CLASS_RX_INT_BITS 0xfffc
-+
-+/*
-+ * Interrupt Status Register 2 (offset 0x0040)
-+ * Interrupt Mask Register 2 (offset 0x0044)
-+ * Interrupt Select Register 2 (offset 0x0048)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0040 {
-+ unsigned int toe_q0_full : 1; // bit 0 TOE Queue 0 Full Interrupt
-+ unsigned int toe_q1_full : 1; // bit 1 TOE Queue 1 Full Interrupt
-+ unsigned int toe_q2_full : 1; // bit 2 TOE Queue 2 Full Interrupt
-+ unsigned int toe_q3_full : 1; // bit 3 TOE Queue 3 Full Interrupt
-+ unsigned int toe_q4_full : 1; // bit 4 TOE Queue 4 Full Interrupt
-+ unsigned int toe_q5_full : 1; // bit 5 TOE Queue 5 Full Interrupt
-+ unsigned int toe_q6_full : 1; // bit 6 TOE Queue 6 Full Interrupt
-+ unsigned int toe_q7_full : 1; // bit 7 TOE Queue 7 Full Interrupt
-+ unsigned int toe_q8_full : 1; // bit 8 TOE Queue 8 Full Interrupt
-+ unsigned int toe_q9_full : 1; // bit 9 TOE Queue 9 Full Interrupt
-+ unsigned int toe_q10_full : 1; // bit 10 TOE Queue 10 Full Interrupt
-+ unsigned int toe_q11_full : 1; // bit 11 TOE Queue 11 Full Interrupt
-+ unsigned int toe_q12_full : 1; // bit 12 TOE Queue 12 Full Interrupt
-+ unsigned int toe_q13_full : 1; // bit 13 TOE Queue 13 Full Interrupt
-+ unsigned int toe_q14_full : 1; // bit 14 TOE Queue 14 Full Interrupt
-+ unsigned int toe_q15_full : 1; // bit 15 TOE Queue 15 Full Interrupt
-+ unsigned int toe_q16_full : 1; // bit 16 TOE Queue 16 Full Interrupt
-+ unsigned int toe_q17_full : 1; // bit 17 TOE Queue 17 Full Interrupt
-+ unsigned int toe_q18_full : 1; // bit 18 TOE Queue 18 Full Interrupt
-+ unsigned int toe_q19_full : 1; // bit 19 TOE Queue 19 Full Interrupt
-+ unsigned int toe_q20_full : 1; // bit 20 TOE Queue 20 Full Interrupt
-+ unsigned int toe_q21_full : 1; // bit 21 TOE Queue 21 Full Interrupt
-+ unsigned int toe_q22_full : 1; // bit 22 TOE Queue 22 Full Interrupt
-+ unsigned int toe_q23_full : 1; // bit 23 TOE Queue 23 Full Interrupt
-+ unsigned int toe_q24_full : 1; // bit 24 TOE Queue 24 Full Interrupt
-+ unsigned int toe_q25_full : 1; // bit 25 TOE Queue 25 Full Interrupt
-+ unsigned int toe_q26_full : 1; // bit 26 TOE Queue 26 Full Interrupt
-+ unsigned int toe_q27_full : 1; // bit 27 TOE Queue 27 Full Interrupt
-+ unsigned int toe_q28_full : 1; // bit 28 TOE Queue 28 Full Interrupt
-+ unsigned int toe_q29_full : 1; // bit 29 TOE Queue 29 Full Interrupt
-+ unsigned int toe_q30_full : 1; // bit 30 TOE Queue 30 Full Interrupt
-+ unsigned int toe_q31_full : 1; // bit 31 TOE Queue 31 Full Interrupt
-+ } bits;
-+} INTR_REG2_T;
-+
-+#define TOE_QL_FULL_INT_BIT(x) BIT(x)
-+
-+/*
-+ * Interrupt Status Register 3 (offset 0x0050)
-+ * Interrupt Mask Register 3 (offset 0x0054)
-+ * Interrupt Select Register 3 (offset 0x0058)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0050 {
-+ unsigned int toe_q32_full : 1; // bit 32 TOE Queue 32 Full Interrupt
-+ unsigned int toe_q33_full : 1; // bit 33 TOE Queue 33 Full Interrupt
-+ unsigned int toe_q34_full : 1; // bit 34 TOE Queue 34 Full Interrupt
-+ unsigned int toe_q35_full : 1; // bit 35 TOE Queue 35 Full Interrupt
-+ unsigned int toe_q36_full : 1; // bit 36 TOE Queue 36 Full Interrupt
-+ unsigned int toe_q37_full : 1; // bit 37 TOE Queue 37 Full Interrupt
-+ unsigned int toe_q38_full : 1; // bit 38 TOE Queue 38 Full Interrupt
-+ unsigned int toe_q39_full : 1; // bit 39 TOE Queue 39 Full Interrupt
-+ unsigned int toe_q40_full : 1; // bit 40 TOE Queue 40 Full Interrupt
-+ unsigned int toe_q41_full : 1; // bit 41 TOE Queue 41 Full Interrupt
-+ unsigned int toe_q42_full : 1; // bit 42 TOE Queue 42 Full Interrupt
-+ unsigned int toe_q43_full : 1; // bit 43 TOE Queue 43 Full Interrupt
-+ unsigned int toe_q44_full : 1; // bit 44 TOE Queue 44 Full Interrupt
-+ unsigned int toe_q45_full : 1; // bit 45 TOE Queue 45 Full Interrupt
-+ unsigned int toe_q46_full : 1; // bit 46 TOE Queue 46 Full Interrupt
-+ unsigned int toe_q47_full : 1; // bit 47 TOE Queue 47 Full Interrupt
-+ unsigned int toe_q48_full : 1; // bit 48 TOE Queue 48 Full Interrupt
-+ unsigned int toe_q49_full : 1; // bit 49 TOE Queue 49 Full Interrupt
-+ unsigned int toe_q50_full : 1; // bit 50 TOE Queue 50 Full Interrupt
-+ unsigned int toe_q51_full : 1; // bit 51 TOE Queue 51 Full Interrupt
-+ unsigned int toe_q52_full : 1; // bit 52 TOE Queue 52 Full Interrupt
-+ unsigned int toe_q53_full : 1; // bit 53 TOE Queue 53 Full Interrupt
-+ unsigned int toe_q54_full : 1; // bit 54 TOE Queue 54 Full Interrupt
-+ unsigned int toe_q55_full : 1; // bit 55 TOE Queue 55 Full Interrupt
-+ unsigned int toe_q56_full : 1; // bit 56 TOE Queue 56 Full Interrupt
-+ unsigned int toe_q57_full : 1; // bit 57 TOE Queue 57 Full Interrupt
-+ unsigned int toe_q58_full : 1; // bit 58 TOE Queue 58 Full Interrupt
-+ unsigned int toe_q59_full : 1; // bit 59 TOE Queue 59 Full Interrupt
-+ unsigned int toe_q60_full : 1; // bit 60 TOE Queue 60 Full Interrupt
-+ unsigned int toe_q61_full : 1; // bit 61 TOE Queue 61 Full Interrupt
-+ unsigned int toe_q62_full : 1; // bit 62 TOE Queue 62 Full Interrupt
-+ unsigned int toe_q63_full : 1; // bit 63 TOE Queue 63 Full Interrupt
-+ } bits;
-+} INTR_REG3_T;
-+
-+#define TOE_QH_FULL_INT_BIT(x) BIT(x-32)
-+
-+/*
-+ * Interrupt Status Register 4 (offset 0x0060)
-+ * Interrupt Mask Register 4 (offset 0x0064)
-+ * Interrupt Select Register 4 (offset 0x0068)
-+ */
-+typedef union {
-+ unsigned char byte;
-+ struct bit_0060 {
-+ unsigned char status_changed : 1; // Status Changed Intr for RGMII Mode
-+ unsigned char rx_overrun : 1; // GMAC Rx FIFO overrun interrupt
-+ unsigned char tx_pause_off : 1; // received pause off frame interrupt
-+ unsigned char rx_pause_off : 1; // received pause off frame interrupt
-+ unsigned char tx_pause_on : 1; // transmit pause on frame interrupt
-+ unsigned char rx_pause_on : 1; // received pause on frame interrupt
-+ unsigned char cnt_full : 1; // MIB counters half full interrupt
-+ unsigned char reserved : 1; //
-+ } _PACKED_ bits;
-+} _PACKED_ GMAC_INTR_T;
-+
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0060_2 {
-+ unsigned int swfq_empty : 1; // bit 0 Software Free Queue Empty Intr.
-+ unsigned int hwfq_empty : 1; // bit 1 Hardware Free Queue Empty Intr.
-+ unsigned int class_qf_int : 14; // bit 15:2 Classification Rx Queue13-0 Full Intr.
-+ GMAC_INTR_T gmac0;
-+ GMAC_INTR_T gmac1;
-+ } bits;
-+} INTR_REG4_T;
-+
-+#define GMAC1_RESERVED_INT_BIT BIT(31)
-+#define GMAC1_MIB_INT_BIT BIT(30)
-+#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)
-+#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)
-+#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)
-+#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)
-+#define GMAC1_RX_OVERRUN_INT_BIT BIT(25)
-+#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
-+#define GMAC0_RESERVED_INT_BIT BIT(23)
-+#define GMAC0_MIB_INT_BIT BIT(22)
-+#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)
-+#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)
-+#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)
-+#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)
-+#define GMAC0_RX_OVERRUN_INT_BIT BIT(17)
-+#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
-+#define CLASS_RX_FULL_INT_BIT(x) BIT((x+2))
-+#define HWFQ_EMPTY_INT_BIT BIT(1)
-+#define SWFQ_EMPTY_INT_BIT BIT(0)
-+
-+#if 1
-+#define GMAC0_INT_BITS (GMAC0_MIB_INT_BIT)
-+#define GMAC1_INT_BITS (GMAC1_MIB_INT_BIT)
-+#else
-+#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
-+ GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT | \
-+ GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT | \
-+ GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
-+#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
-+ GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT | \
-+ GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT | \
-+ GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
-+#endif
-+
-+#define CLASS_RX_FULL_INT_BITS 0xfffc
-+
-+/*
-+ * GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070)
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_0070_2 {
-+ unsigned int swfq_empty : 8; // 7:0 Software Free Queue Empty Threshold
-+ unsigned int hwfq_empty : 8; // 15:8 Hardware Free Queue Empty Threshold
-+ unsigned int intrq : 8; // 23:16
-+ unsigned int toe_class : 8; // 31:24
-+ } bits;
-+} QUEUE_THRESHOLD_T;
-+
-+
-+/*
-+ * GMAC DMA Control Register
-+ * GMAC0 offset 0x8000
-+ * GMAC1 offset 0xC000
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8000 {
-+ unsigned int td_bus : 2; // bit 1:0 Peripheral Bus Width
-+ unsigned int td_burst_size : 2; // bit 3:2 TxDMA max burst size for every AHB request
-+ unsigned int td_prot : 4; // bit 7:4 TxDMA protection control
-+ unsigned int rd_bus : 2; // bit 9:8 Peripheral Bus Width
-+ unsigned int rd_burst_size : 2; // bit 11:10 DMA max burst size for every AHB request
-+ unsigned int rd_prot : 4; // bit 15:12 DMA Protection Control
-+ unsigned int rd_insert_bytes : 2; // bit 17:16
-+ unsigned int reserved : 10; // bit 27:18
-+ unsigned int drop_small_ack : 1; // bit 28 1: Drop, 0: Accept
-+ unsigned int loopback : 1; // bit 29 Loopback TxDMA to RxDMA
-+ unsigned int td_enable : 1; // bit 30 Tx DMA Enable
-+ unsigned int rd_enable : 1; // bit 31 Rx DMA Enable
-+ } bits;
-+} GMAC_DMA_CTRL_T;
-+
-+/*
-+ * GMAC Tx Weighting Control Register 0
-+ * GMAC0 offset 0x8004
-+ * GMAC1 offset 0xC004
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8004 {
-+ unsigned int hw_tq0 : 6; // bit 5:0 HW TX Queue 3
-+ unsigned int hw_tq1 : 6; // bit 11:6 HW TX Queue 2
-+ unsigned int hw_tq2 : 6; // bit 17:12 HW TX Queue 1
-+ unsigned int hw_tq3 : 6; // bit 23:18 HW TX Queue 0
-+ unsigned int reserved : 8; // bit 31:24
-+ } bits;
-+} GMAC_TX_WCR0_T; /* Weighting Control Register 0 */
-+
-+/*
-+ * GMAC Tx Weighting Control Register 1
-+ * GMAC0 offset 0x8008
-+ * GMAC1 offset 0xC008
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8008 {
-+ unsigned int sw_tq0 : 5; // bit 4:0 SW TX Queue 0
-+ unsigned int sw_tq1 : 5; // bit 9:5 SW TX Queue 1
-+ unsigned int sw_tq2 : 5; // bit 14:10 SW TX Queue 2
-+ unsigned int sw_tq3 : 5; // bit 19:15 SW TX Queue 3
-+ unsigned int sw_tq4 : 5; // bit 24:20 SW TX Queue 4
-+ unsigned int sw_tq5 : 5; // bit 29:25 SW TX Queue 5
-+ unsigned int reserved : 2; // bit 31:30
-+ } bits;
-+} GMAC_TX_WCR1_T; /* Weighting Control Register 1 */
-+
-+/*
-+ * Queue Read/Write Pointer
-+ * GMAC SW TX Queue 0~5 Read/Write Pointer register
-+ * GMAC0 offset 0x800C ~ 0x8020
-+ * GMAC1 offset 0xC00C ~ 0xC020
-+ * GMAC HW TX Queue 0~3 Read/Write Pointer register
-+ * GMAC0 offset 0x8024 ~ 0x8030
-+ * GMAC1 offset 0xC024 ~ 0xC030
-+ *
-+ * see DMA_RWPTR_T structure
-+ */
-+
-+/*
-+ * GMAC DMA Tx First Description Address Register
-+ * GMAC0 offset 0x8038
-+ * GMAC1 offset 0xC038
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8038 {
-+ unsigned int reserved : 3;
-+ unsigned int td_busy : 1; // bit 3 1: TxDMA busy; 0: TxDMA idle
-+ unsigned int td_first_des_ptr : 28; // bit 31:4 first descriptor address
-+ } bits;
-+} GMAC_TXDMA_FIRST_DESC_T;
-+
-+/*
-+ * GMAC DMA Tx Current Description Address Register
-+ * GMAC0 offset 0x803C
-+ * GMAC1 offset 0xC03C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_803C {
-+ unsigned int reserved : 4;
-+ unsigned int td_curr_desc_ptr : 28; // bit 31:4 current descriptor address
-+ } bits;
-+} GMAC_TXDMA_CURR_DESC_T;
-+
-+/*
-+ * GMAC DMA Tx Description Word 0 Register
-+ * GMAC0 offset 0x8040
-+ * GMAC1 offset 0xC040
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8040 {
-+ unsigned int buffer_size : 16; // bit 15:0 Transfer size
-+ unsigned int desc_count : 6; // bit 21:16 number of descriptors used for the current frame
-+ unsigned int status_tx_ok : 1; // bit 22 Tx Status, 1: Successful 0: Failed
-+ unsigned int status_rvd : 6; // bit 28:23 Tx Status, Reserved bits
-+ unsigned int perr : 1; // bit 29 protocol error during processing this descriptor
-+ unsigned int derr : 1; // bit 30 data error during processing this descriptor
-+ unsigned int reserved : 1; // bit 31
-+ } bits;
-+} GMAC_TXDESC_0_T;
-+
-+/*
-+ * GMAC DMA Tx Description Word 1 Register
-+ * GMAC0 offset 0x8044
-+ * GMAC1 offset 0xC044
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct txdesc_word1 {
-+ unsigned int byte_count : 16; // bit 15: 0 Tx Frame Byte Count
-+ unsigned int mtu_enable : 1; // bit 16 TSS segmentation use MTU setting
-+ unsigned int ip_chksum : 1; // bit 17 IPV4 Header Checksum Enable
-+ unsigned int ipv6_enable : 1; // bit 18 IPV6 Tx Enable
-+ unsigned int tcp_chksum : 1; // bit 19 TCP Checksum Enable
-+ unsigned int udp_chksum : 1; // bit 20 UDP Checksum Enable
-+ unsigned int bypass_tss : 1; // bit 21
-+ unsigned int ip_fixed_len : 1; // bit 22
-+ unsigned int reserved : 9; // bit 31:23 Tx Flag, Reserved
-+ } bits;
-+} GMAC_TXDESC_1_T;
-+
-+#define TSS_IP_FIXED_LEN_BIT BIT(22)
-+#define TSS_UDP_CHKSUM_BIT BIT(20)
-+#define TSS_TCP_CHKSUM_BIT BIT(19)
-+#define TSS_IPV6_ENABLE_BIT BIT(18)
-+#define TSS_IP_CHKSUM_BIT BIT(17)
-+#define TSS_MTU_ENABLE_BIT BIT(16)
-+
-+/*
-+ * GMAC DMA Tx Description Word 2 Register
-+ * GMAC0 offset 0x8048
-+ * GMAC1 offset 0xC048
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int buf_adr;
-+} GMAC_TXDESC_2_T;
-+
-+/*
-+ * GMAC DMA Tx Description Word 3 Register
-+ * GMAC0 offset 0x804C
-+ * GMAC1 offset 0xC04C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct txdesc_word3 {
-+ unsigned int mtu_size : 11; // bit 10: 0 Tx Frame Byte Count
-+ unsigned int reserved : 18; // bit 28:11
-+ unsigned int eofie : 1; // bit 29 End of frame interrupt enable
-+ unsigned int sof_eof : 2; // bit 31:30 11: only one, 10: first, 01: last, 00: linking
-+ } bits;
-+} GMAC_TXDESC_3_T;
-+#define SOF_EOF_BIT_MASK 0x3fffffff
-+#define SOF_BIT 0x80000000
-+#define EOF_BIT 0x40000000
-+#define EOFIE_BIT BIT(29)
-+#define MTU_SIZE_BIT_MASK 0x7ff
-+
-+/*
-+ * GMAC Tx Descriptor
-+ */
-+typedef struct {
-+ GMAC_TXDESC_0_T word0;
-+ GMAC_TXDESC_1_T word1;
-+ GMAC_TXDESC_2_T word2;
-+ GMAC_TXDESC_3_T word3;
-+} GMAC_TXDESC_T;
-+
-+/*
-+ * GMAC DMA Rx First Description Address Register
-+ * GMAC0 offset 0x8058
-+ * GMAC1 offset 0xC058
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8058 {
-+ unsigned int reserved : 3; // bit 2:0
-+ unsigned int rd_busy : 1; // bit 3 1-RxDMA busy; 0-RxDMA idle
-+ unsigned int rd_first_des_ptr : 28; // bit 31:4 first descriptor address
-+ } bits;
-+} GMAC_RXDMA_FIRST_DESC_T;
-+
-+/*
-+ * GMAC DMA Rx Current Description Address Register
-+ * GMAC0 offset 0x805C
-+ * GMAC1 offset 0xC05C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_805C {
-+ unsigned int reserved : 4; // bit 3:0
-+ unsigned int rd_curr_des_ptr : 28; // bit 31:4 current descriptor address
-+ } bits;
-+} GMAC_RXDMA_CURR_DESC_T;
-+
-+/*
-+ * GMAC DMA Rx Description Word 0 Register
-+ * GMAC0 offset 0x8060
-+ * GMAC1 offset 0xC060
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8060 {
-+ unsigned int buffer_size : 16; // bit 15:0 number of descriptors used for the current frame
-+ unsigned int desc_count : 6; // bit 21:16 number of descriptors used for the current frame
-+ unsigned int status : 4; // bit 24:22 Status of rx frame
-+ unsigned int chksum_status : 3; // bit 28:26 Check Sum Status
-+ unsigned int perr : 1; // bit 29 protocol error during processing this descriptor
-+ unsigned int derr : 1; // bit 30 data error during processing this descriptor
-+ unsigned int drop : 1; // bit 31 TOE/CIS Queue Full dropped packet to default queue
-+ } bits;
-+} GMAC_RXDESC_0_T;
-+
-+#define GMAC_RXDESC_0_T_derr BIT(30)
-+#define GMAC_RXDESC_0_T_perr BIT(29)
-+#define GMAC_RXDESC_0_T_chksum_status(x) BIT((x+26))
-+#define GMAC_RXDESC_0_T_status(x) BIT((x+22))
-+#define GMAC_RXDESC_0_T_desc_count(x) BIT((x+16))
-+
-+#define RX_CHKSUM_IP_UDP_TCP_OK 0
-+#define RX_CHKSUM_IP_OK_ONLY 1
-+#define RX_CHKSUM_NONE 2
-+#define RX_CHKSUM_IP_ERR_UNKNOWN 4
-+#define RX_CHKSUM_IP_ERR 5
-+#define RX_CHKSUM_TCP_UDP_ERR 6
-+#define RX_CHKSUM_NUM 8
-+
-+#define RX_STATUS_GOOD_FRAME 0
-+#define RX_STATUS_TOO_LONG_GOOD_CRC 1
-+#define RX_STATUS_RUNT_FRAME 2
-+#define RX_STATUS_SFD_NOT_FOUND 3
-+#define RX_STATUS_CRC_ERROR 4
-+#define RX_STATUS_TOO_LONG_BAD_CRC 5
-+#define RX_STATUS_ALIGNMENT_ERROR 6
-+#define RX_STATUS_TOO_LONG_BAD_ALIGN 7
-+#define RX_STATUS_RX_ERR 8
-+#define RX_STATUS_DA_FILTERED 9
-+#define RX_STATUS_BUFFER_FULL 10
-+#define RX_STATUS_NUM 16
-+
-+
-+/*
-+ * GMAC DMA Rx Description Word 1 Register
-+ * GMAC0 offset 0x8064
-+ * GMAC1 offset 0xC064
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct rxdesc_word1 {
-+ unsigned int byte_count : 16; // bit 15: 0 Rx Frame Byte Count
-+ unsigned int sw_id : 16; // bit 31:16 Software ID
-+ } bits;
-+} GMAC_RXDESC_1_T;
-+
-+/*
-+ * GMAC DMA Rx Description Word 2 Register
-+ * GMAC0 offset 0x8068
-+ * GMAC1 offset 0xC068
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int buf_adr;
-+} GMAC_RXDESC_2_T;
-+
-+#define RX_INSERT_NONE 0
-+#define RX_INSERT_1_BYTE 1
-+#define RX_INSERT_2_BYTE 2
-+#define RX_INSERT_3_BYTE 3
-+
-+#define RX_INSERT_BYTES RX_INSERT_2_BYTE
-+/*
-+ * GMAC DMA Rx Description Word 3 Register
-+ * GMAC0 offset 0x806C
-+ * GMAC1 offset 0xC06C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct rxdesc_word3 {
-+ unsigned int l3_offset : 8; // bit 7: 0 L3 data offset
-+ unsigned int l4_offset : 8; // bit 15: 8 L4 data offset
-+ unsigned int l7_offset : 8; // bit 23: 16 L7 data offset
-+ unsigned int dup_ack : 1; // bit 24 Duplicated ACK detected
-+ unsigned int abnormal : 1; // bit 25 abnormal case found
-+ unsigned int option : 1; // bit 26 IPV4 option or IPV6 extension header
-+ unsigned int out_of_seq : 1; // bit 27 Out of Sequence packet
-+ unsigned int ctrl_flag : 1; // bit 28 Control Flag is present
-+ unsigned int eofie : 1; // bit 29 End of frame interrupt enable
-+ unsigned int sof_eof : 2; // bit 31:30 11: only one, 10: first, 01: last, 00: linking
-+ } bits;
-+} GMAC_RXDESC_3_T;
-+
-+/*
-+ * GMAC Rx Descriptor
-+ */
-+typedef struct {
-+ GMAC_RXDESC_0_T word0;
-+ GMAC_RXDESC_1_T word1;
-+ GMAC_RXDESC_2_T word2;
-+ GMAC_RXDESC_3_T word3;
-+} GMAC_RXDESC_T;
-+
-+/*
-+ * GMAC Hash Engine Enable/Action Register 0 Offset Register
-+ * GMAC0 offset 0x8070
-+ * GMAC1 offset 0xC070
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8070 {
-+ unsigned int mr0hel : 6; // bit 5:0 match rule 0 hash entry size
-+ unsigned int mr0_action : 5; // bit 10:6 Matching Rule 0 action offset
-+ unsigned int reserved0 : 4; // bit 14:11
-+ unsigned int mr0en : 1; // bit 15 Enable Matching Rule 0
-+ unsigned int mr1hel : 6; // bit 21:16 match rule 1 hash entry size
-+ unsigned int mr1_action : 5; // bit 26:22 Matching Rule 1 action offset
-+ unsigned int timing : 3; // bit 29:27
-+ unsigned int reserved1 : 1; // bit 30
-+ unsigned int mr1en : 1; // bit 31 Enable Matching Rule 1
-+ } bits;
-+} GMAC_HASH_ENABLE_REG0_T;
-+
-+/*
-+ * GMAC Hash Engine Enable/Action Register 1 Offset Register
-+ * GMAC0 offset 0x8074
-+ * GMAC1 offset 0xC074
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8074 {
-+ unsigned int mr2hel : 6; // bit 5:0 match rule 2 hash entry size
-+ unsigned int mr2_action : 5; // bit 10:6 Matching Rule 2 action offset
-+ unsigned int reserved2 : 4; // bit 14:11
-+ unsigned int mr2en : 1; // bit 15 Enable Matching Rule 2
-+ unsigned int mr3hel : 6; // bit 21:16 match rule 3 hash entry size
-+ unsigned int mr3_action : 5; // bit 26:22 Matching Rule 3 action offset
-+ unsigned int reserved1 : 4; // bit 30:27
-+ unsigned int mr3en : 1; // bit 31 Enable Matching Rule 3
-+ } bits;
-+} GMAC_HASH_ENABLE_REG1_T;
-+
-+/*
-+ * GMAC Matching Rule Control Register 0
-+ * GMAC0 offset 0x8078
-+ * GMAC1 offset 0xC078
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8078 {
-+ unsigned int sprx : 8; // bit 7:0 Support Protocol Register 7:0
-+ unsigned int reserved2 : 4; // bit 11:8
-+ unsigned int tos_traffic : 1; // bit 12 IPV4 TOS or IPV6 Traffice Class
-+ unsigned int flow_lable : 1; // bit 13 IPV6 Flow label
-+ unsigned int ip_hdr_len : 1; // bit 14 IPV4 Header length
-+ unsigned int ip_version : 1; // bit 15 0: IPV4, 1: IPV6
-+ unsigned int reserved1 : 3; // bit 18:16
-+ unsigned int pppoe : 1; // bit 19 PPPoE Session ID enable
-+ unsigned int vlan : 1; // bit 20 VLAN ID enable
-+ unsigned int ether_type : 1; // bit 21 Ethernet type enable
-+ unsigned int sa : 1; // bit 22 MAC SA enable
-+ unsigned int da : 1; // bit 23 MAC DA enable
-+ unsigned int priority : 3; // bit 26:24 priority if multi-rules matched
-+ unsigned int port : 1; // bit 27 PORT ID matching enable
-+ unsigned int l7 : 1; // bit 28 L7 matching enable
-+ unsigned int l4 : 1; // bit 29 L4 matching enable
-+ unsigned int l3 : 1; // bit 30 L3 matching enable
-+ unsigned int l2 : 1; // bit 31 L2 matching enable
-+ } bits;
-+} GMAC_MRxCR0_T;
-+
-+#define MR_L2_BIT BIT(31)
-+#define MR_L3_BIT BIT(30)
-+#define MR_L4_BIT BIT(29)
-+#define MR_L7_BIT BIT(28)
-+#define MR_PORT_BIT BIT(27)
-+#define MR_PRIORITY_BIT BIT(26)
-+#define MR_DA_BIT BIT(23)
-+#define MR_SA_BIT BIT(22)
-+#define MR_ETHER_TYPE_BIT BIT(21)
-+#define MR_VLAN_BIT BIT(20)
-+#define MR_PPPOE_BIT BIT(19)
-+#define MR_IP_VER_BIT BIT(15)
-+#define MR_IP_HDR_LEN_BIT BIT(14)
-+#define MR_FLOW_LABLE_BIT BIT(13)
-+#define MR_TOS_TRAFFIC_BIT BIT(12)
-+#define MR_SPR_BIT(x) BIT(x)
-+#define MR_SPR_BITS 0xff
-+
-+/*
-+ * GMAC Matching Rule Control Register 1
-+ * GMAC0 offset 0x807C
-+ * GMAC1 offset 0xC07C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_807C {
-+ unsigned int l4_byte0_15 : 16; // bit 15: 0
-+ unsigned int dip_netmask : 7; // bit 22:16 Dest IP net mask, number of mask bits
-+ unsigned int dip : 1; // bit 23 Dest IP
-+ unsigned int sip_netmask : 7; // bit 30:24 Srce IP net mask, number of mask bits
-+ unsigned int sip : 1; // bit 31 Srce IP
-+ } bits;
-+} GMAC_MRxCR1_T;
-+
-+/*
-+ * GMAC Matching Rule Control Register 2
-+ * GMAC0 offset 0x8080
-+ * GMAC1 offset 0xC080
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_8080 {
-+ unsigned int l7_byte0_23 : 24; // bit 23:0
-+ unsigned int l4_byte16_24 : 8; // bit 31: 24
-+ } bits;
-+} GMAC_MRxCR2_T;
-+
-+/*
-+ * GMAC Support registers
-+ * GMAC0 offset 0x80A8
-+ * GMAC1 offset 0xC0A8
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_80A8 {
-+ unsigned int protocol : 8; // bit 7:0 Supported protocol
-+ unsigned int swap : 3; // bit 10:8 Swap
-+ unsigned int reserved : 21; // bit 31:11
-+ } bits;
-+} GMAC_SPR_T;
-+
-+/*
-+ * GMAC_AHB_WEIGHT registers
-+ * GMAC0 offset 0x80C8
-+ * GMAC1 offset 0xC0C8
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_80C8 {
-+ unsigned int hash_weight : 5; // 4:0
-+ unsigned int rx_weight : 5; // 9:5
-+ unsigned int tx_weight : 5; // 14:10
-+ unsigned int pre_req : 5; // 19:15 Rx Data Pre Request FIFO Threshold
-+ unsigned int tqDV_threshold : 5; // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
-+ unsigned int reserved : 7; // 31:25
-+ } bits;
-+} GMAC_AHB_WEIGHT_T;
-+
-+/*
-+ * the register structure of GMAC
-+ */
-+
-+/*
-+ * GMAC RX FLTR
-+ * GMAC0 Offset 0xA00C
-+ * GMAC1 Offset 0xE00C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit1_000c {
-+ unsigned int unicast : 1; /* enable receive of unicast frames that are sent to STA address */
-+ unsigned int multicast : 1; /* enable receive of multicast frames that pass multicast filter */
-+ unsigned int broadcast : 1; /* enable receive of broadcast frames */
-+ unsigned int promiscuous : 1; /* enable receive of all frames */
-+ unsigned int error : 1; /* enable receive of all error frames */
-+ unsigned int : 27;
-+ } bits;
-+} GMAC_RX_FLTR_T;
-+
-+/*
-+ * GMAC Configuration 0
-+ * GMAC0 Offset 0xA018
-+ * GMAC1 Offset 0xE018
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit1_0018 {
-+ unsigned int dis_tx : 1; /* 0: disable transmit */
-+ unsigned int dis_rx : 1; /* 1: disable receive */
-+ unsigned int loop_back : 1; /* 2: transmit data loopback enable */
-+ unsigned int flow_ctrl : 1; /* 3: flow control also trigged by Rx queues */
-+ unsigned int adj_ifg : 4; /* 4-7: adjust IFG from 96+/-56 */
-+ unsigned int max_len : 3; /* 8-10 maximum receive frame length allowed */
-+ unsigned int dis_bkoff : 1; /* 11: disable back-off function */
-+ unsigned int dis_col : 1; /* 12: disable 16 collisions abort function */
-+ unsigned int sim_test : 1; /* 13: speed up timers in simulation */
-+ unsigned int rx_fc_en : 1; /* 14: RX flow control enable */
-+ unsigned int tx_fc_en : 1; /* 15: TX flow control enable */
-+ unsigned int rgmii_en : 1; /* 16: RGMII in-band status enable */
-+ unsigned int ipv4_rx_chksum : 1; /* 17: IPv4 RX Checksum enable */
-+ unsigned int ipv6_rx_chksum : 1; /* 18: IPv6 RX Checksum enable */
-+ unsigned int rx_tag_remove : 1; /* 19: Remove Rx VLAN tag */
-+ unsigned int rgmm_edge : 1; // 20
-+ unsigned int rxc_inv : 1; // 21
-+ unsigned int ipv6_exthdr_order : 1; // 22
-+ unsigned int rx_err_detect : 1; // 23
-+ unsigned int port0_chk_hwq : 1; // 24
-+ unsigned int port1_chk_hwq : 1; // 25
-+ unsigned int port0_chk_toeq : 1; // 26
-+ unsigned int port1_chk_toeq : 1; // 27
-+ unsigned int port0_chk_classq : 1; // 28
-+ unsigned int port1_chk_classq : 1; // 29
-+ unsigned int reserved : 2; // 31
-+ } bits;
-+} GMAC_CONFIG0_T;
-+
-+/*
-+ * GMAC Configuration 1
-+ * GMAC0 Offset 0xA01C
-+ * GMAC1 Offset 0xE01C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit1_001c {
-+ unsigned int set_threshold : 8; /* flow control set threshold */
-+ unsigned int rel_threshold : 8; /* flow control release threshold */
-+ unsigned int reserved : 16;
-+ } bits;
-+} GMAC_CONFIG1_T;
-+
-+#define GMAC_FLOWCTRL_SET_MAX 32
-+#define GMAC_FLOWCTRL_SET_MIN 0
-+#define GMAC_FLOWCTRL_RELEASE_MAX 32
-+#define GMAC_FLOWCTRL_RELEASE_MIN 0
-+
-+/*
-+ * GMAC Configuration 2
-+ * GMAC0 Offset 0xA020
-+ * GMAC1 Offset 0xE020
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit1_0020 {
-+ unsigned int set_threshold : 16; /* flow control set threshold */
-+ unsigned int rel_threshold : 16; /* flow control release threshold */
-+ } bits;
-+} GMAC_CONFIG2_T;
-+
-+/*
-+ * GMAC Configuration 3
-+ * GMAC0 Offset 0xA024
-+ * GMAC1 Offset 0xE024
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit1_0024 {
-+ unsigned int set_threshold : 16; /* flow control set threshold */
-+ unsigned int rel_threshold : 16; /* flow control release threshold */
-+ } bits;
-+} GMAC_CONFIG3_T;
-+
-+
-+/*
-+ * GMAC STATUS
-+ * GMAC0 Offset 0xA02C
-+ * GMAC1 Offset 0xE02C
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit1_002c {
-+ unsigned int link : 1; /* link status */
-+ unsigned int speed : 2; /* link speed(00->2.5M 01->25M 10->125M) */
-+ unsigned int duplex : 1; /* duplex mode */
-+ unsigned int reserved : 1;
-+ unsigned int mii_rmii : 2; /* PHY interface type */
-+ unsigned int : 25;
-+ } bits;
-+} GMAC_STATUS_T;
-+
-+#define GMAC_SPEED_10 0
-+#define GMAC_SPEED_100 1
-+#define GMAC_SPEED_1000 2
-+
-+#define GMAC_PHY_MII 0
-+#define GMAC_PHY_GMII 1
-+#define GMAC_PHY_RGMII_100_10 2
-+#define GMAC_PHY_RGMII_1000 3
-+
-+/*
-+ * Queue Header
-+ * (1) TOE Queue Header
-+ * (2) Non-TOE Queue Header
-+ * (3) Interrupt Queue Header
-+ *
-+ * memory Layout
-+ * TOE Queue Header
-+ * 0x60003000 +---------------------------+ 0x0000
-+ * | TOE Queue 0 Header |
-+ * | 8 * 4 Bytes |
-+ * +---------------------------+ 0x0020
-+ * | TOE Queue 1 Header |
-+ * | 8 * 4 Bytes |
-+ * +---------------------------+ 0x0040
-+ * | ...... |
-+ * | |
-+ * +---------------------------+
-+ *
-+ * Non TOE Queue Header
-+ * 0x60002000 +---------------------------+ 0x0000
-+ * | Default Queue 0 Header |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+ 0x0008
-+ * | Default Queue 1 Header |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+ 0x0010
-+ * | Classification Queue 0 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+
-+ * | Classification Queue 1 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+ (n * 8 + 0x10)
-+ * | ... |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+ (13 * 8 + 0x10)
-+ * | Classification Queue 13 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+ 0x80
-+ * | Interrupt Queue 0 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+
-+ * | Interrupt Queue 1 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+
-+ * | Interrupt Queue 2 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+
-+ * | Interrupt Queue 3 |
-+ * | 2 * 4 Bytes |
-+ * +---------------------------+
-+ *
-+ */
-+#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32)
-+#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
-+#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
-+#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10)
-+#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80)
-+#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8)
-+#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
-+/*
-+ * TOE Queue Header Word 0
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int base_size;
-+} TOE_QHDR0_T;
-+
-+#define TOE_QHDR0_BASE_MASK (~0x0f)
-+
-+/*
-+ * TOE Queue Header Word 1
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_qhdr1 {
-+ unsigned int rptr : 16; // bit 15:0
-+ unsigned int wptr : 16; // bit 31:16
-+ } bits;
-+} TOE_QHDR1_T;
-+
-+/*
-+ * TOE Queue Header Word 2
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_qhdr2 {
-+ unsigned int TotalPktSize : 17; // bit 16: 0 Total packet size
-+ unsigned int reserved : 7; // bit 23:17
-+ unsigned int dack : 1; // bit 24 1: Duplicated ACK
-+ unsigned int abn : 1; // bit 25 1: Abnormal case Found
-+ unsigned int tcp_opt : 1; // bit 26 1: Have TCP option
-+ unsigned int ip_opt : 1; // bit 27 1: have IPV4 option or IPV6 Extension header
-+ unsigned int sat : 1; // bit 28 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
-+ unsigned int osq : 1; // bit 29 1: out of sequence
-+ unsigned int ctl : 1; // bit 30 1: have control flag bits (except ack)
-+ unsigned int usd : 1; // bit 31 0: if no data assembled yet
-+ } bits;
-+} TOE_QHDR2_T;
-+
-+/*
-+ * TOE Queue Header Word 3
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int seq_num;
-+} TOE_QHDR3_T;
-+
-+/*
-+ * TOE Queue Header Word 4
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int ack_num;
-+} TOE_QHDR4_T;
-+
-+/*
-+ * TOE Queue Header Word 5
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_qhdr5 {
-+ unsigned int AckCnt : 16; // bit 15:0
-+ unsigned int SeqCnt : 16; // bit 31:16
-+ } bits;
-+} TOE_QHDR5_T;
-+
-+/*
-+ * TOE Queue Header Word 6
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_qhdr6 {
-+ unsigned int WinSize : 16; // bit 15:0
-+ unsigned int iq_num : 2; // bit 17:16
-+ unsigned int MaxPktSize : 14; // bit 31:18
-+ } bits;
-+} TOE_QHDR6_T;
-+
-+/*
-+ * TOE Queue Header Word 7
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_qhdr7 {
-+ unsigned int AckThreshold : 16; // bit 15:0
-+ unsigned int SeqThreshold : 16; // bit 31:16
-+ } bits;
-+} TOE_QHDR7_T;
-+
-+/*
-+ * TOE Queue Header
-+ */
-+typedef struct {
-+ TOE_QHDR0_T word0;
-+ TOE_QHDR1_T word1;
-+ TOE_QHDR2_T word2;
-+ TOE_QHDR3_T word3;
-+ TOE_QHDR4_T word4;
-+ TOE_QHDR5_T word5;
-+ TOE_QHDR6_T word6;
-+ TOE_QHDR7_T word7;
-+} TOE_QHDR_T;
-+
-+/*
-+ * NONTOE Queue Header Word 0
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int base_size;
-+} NONTOE_QHDR0_T;
-+
-+#define NONTOE_QHDR0_BASE_MASK (~0x0f)
-+
-+/*
-+ * NONTOE Queue Header Word 1
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_nonqhdr1 {
-+ unsigned int rptr : 16; // bit 15:0
-+ unsigned int wptr : 16; // bit 31:16
-+ } bits;
-+} NONTOE_QHDR1_T;
-+
-+/*
-+ * Non-TOE Queue Header
-+ */
-+typedef struct {
-+ NONTOE_QHDR0_T word0;
-+ NONTOE_QHDR1_T word1;
-+} NONTOE_QHDR_T;
-+
-+/*
-+ * Interrupt Queue Header Word 0
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_intrqhdr0 {
-+ unsigned int win_size : 16; // bit 15:0 Descriptor Ring Size
-+ unsigned int wptr : 16; // bit 31:16 Write Pointer where hw stopped
-+ } bits;
-+} INTR_QHDR0_T;
-+
-+/*
-+ * Interrupt Queue Header Word 1
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_intrqhdr1 {
-+ unsigned int TotalPktSize : 17; // bit 16: 0 Total packet size
-+ unsigned int tcp_qid : 8; // bit 24:17 TCP Queue ID
-+ unsigned int dack : 1; // bit 25 1: Duplicated ACK
-+ unsigned int abn : 1; // bit 26 1: Abnormal case Found
-+ unsigned int tcp_opt : 1; // bit 27 1: Have TCP option
-+ unsigned int ip_opt : 1; // bit 28 1: have IPV4 option or IPV6 Extension header
-+ unsigned int sat : 1; // bit 29 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
-+ unsigned int osq : 1; // bit 30 1: out of sequence
-+ unsigned int ctl : 1; // bit 31 1: have control flag bits (except ack)
-+ } bits;
-+} INTR_QHDR1_T;
-+
-+/*
-+ * Interrupt Queue Header Word 2
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int seq_num;
-+} INTR_QHDR2_T;
-+
-+/*
-+ * Interrupt Queue Header Word 3
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ unsigned int ack_num;
-+} INTR_QHDR3_T;
-+
-+/*
-+ * Interrupt Queue Header Word 4
-+ */
-+typedef union {
-+ unsigned int bits32;
-+ struct bit_intrqhdr4 {
-+ unsigned int AckCnt : 16; // bit 15:0 Ack# change since last ack# intr.
-+ unsigned int SeqCnt : 16; // bit 31:16 Seq# change since last seq# intr.
-+ } bits;
-+} INTR_QHDR4_T;
-+
-+/*
-+ * Interrupt Queue Header
-+ */
-+typedef struct {
-+ INTR_QHDR0_T word0;
-+ INTR_QHDR1_T word1;
-+ INTR_QHDR2_T word2;
-+ INTR_QHDR3_T word3;
-+ INTR_QHDR4_T word4;
-+ unsigned int word5;
-+ unsigned int word6;
-+ unsigned int word7;
-+} INTR_QHDR_T;
-+
-+/*
-+ * GMAC private data
-+ */
-+typedef struct {
-+ void __iomem *rwptr_reg;
-+ unsigned int desc_base;
-+ unsigned int desc_base_dma;
-+ unsigned short finished_idx;
-+ struct sk_buff *tx_skb[TOE_GMAC_SWTXQ_DESC_NUM];
-+} GMAC_SWTXQ_T;
-+
-+struct gmac_private {
-+ struct phy_device *phydev;
-+ unsigned int port_id;
-+ void __iomem *base_addr;
-+ void __iomem *dma_base_addr;
-+ unsigned int swtxq_desc_base;
-+ GMAC_SWTXQ_T swtxq[TOE_SW_TXQ_NUM];
-+ NONTOE_QHDR_T *default_qhdr;
-+ unsigned int default_desc_base;
-+ dma_addr_t default_desc_base_dma;
-+ dma_addr_t swtxq_desc_base_dma;
-+ unsigned int flow_control_enable;
-+ unsigned int intr0_enabled;
-+ unsigned int intr1_enabled;
-+ unsigned int intr2_enabled;
-+ unsigned int intr3_enabled;
-+ unsigned int intr4_enabled;
-+ unsigned int intr0_selected;
-+ unsigned int intr1_selected;
-+ unsigned int intr2_selected;
-+ unsigned int intr3_selected;
-+ unsigned int intr4_selected;
-+};
-+
-+struct toe_private {
-+ void __iomem *global_base;
-+ struct net_device *net_dev[2];
-+ struct device *dev;
-+ struct work_struct freq_work;
-+ spinlock_t freeq_lock;
-+ unsigned int swfq_desc_base;
-+ unsigned int hwfq_desc_base;
-+ unsigned int hwfq_buf_base;
-+ dma_addr_t sw_freeq_desc_base_dma;
-+ dma_addr_t hw_freeq_desc_base_dma;
-+ dma_addr_t hwfq_buf_base_dma;
-+ dma_addr_t hwfq_buf_end_dma;
-+};
-+
-+#define GMAC_PORT0 0
-+#define GMAC_PORT1 1
-+
-+#endif /* _GMAC_SL351x_H */
---- /dev/null
-+++ b/drivers/net/gemini_negmac/Makefile
-@@ -0,0 +1,3 @@
-+obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC)+= gemini_negmac.o
-+
-+gemini_negmac-objs := gm_gmac.o
---- a/drivers/net/Kconfig
-+++ b/drivers/net/Kconfig
-@@ -100,6 +100,13 @@ config NET_FC
- adaptor below. You also should have said Y to "SCSI support" and
- "SCSI generic support".
-
-+config GEMINI_NET_ENGINE_GMAC
-+ tristate "Gemini Gigabit Ethernet support"
-+ depends on ARCH_GEMINI
-+ select PHYLIB
-+ help
-+ This driver supports Gemini TOE and NAT dual Gigabit Ethernet.
-+
- config MII
- tristate "Generic Media Independent Interface device support"
- help
---- a/drivers/net/Makefile
-+++ b/drivers/net/Makefile
-@@ -34,6 +34,7 @@ obj-$(CONFIG_ETRAX_ETHERNET) += cris/
- obj-$(CONFIG_NET_DSA) += dsa/
- obj-$(CONFIG_ETHERNET) += ethernet/
- obj-$(CONFIG_FDDI) += fddi/
-+obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC) += gemini_negmac/
- obj-$(CONFIG_HIPPI) += hippi/
- obj-$(CONFIG_HAMRADIO) += hamradio/
- obj-$(CONFIG_IRDA) += irda/
+++ /dev/null
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -13,6 +13,7 @@
- #define __GEMINI_COMMON_H__
-
- struct mtd_partition;
-+struct gemini_gmac_platform_data;
-
- extern void gemini_map_io(void);
- extern void gemini_init_irq(void);
-@@ -26,6 +27,7 @@ extern int platform_register_pflash(unsi
- struct mtd_partition *parts,
- unsigned int nr_parts);
- extern int platform_register_watchdog(void);
-+extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
-
- extern void gemini_restart(char mode, const char *cmd);
-
---- a/arch/arm/mach-gemini/devices.c
-+++ b/arch/arm/mach-gemini/devices.c
-@@ -17,6 +17,7 @@
- #include <mach/irqs.h>
- #include <mach/hardware.h>
- #include <mach/global_reg.h>
-+#include <mach/gmac.h>
- #include "common.h"
-
- static struct plat_serial8250_port serial_platform_data[] = {
-@@ -134,3 +135,53 @@ int __init platform_register_watchdog(vo
- {
- return platform_device_register(&wdt_device);
- }
-+
-+static struct resource gmac_resources[] = {
-+ {
-+ .start = 0x60000000,
-+ .end = 0x6000ffff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IRQ_GMAC0,
-+ .end = IRQ_GMAC0,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+ {
-+ .start = IRQ_GMAC1,
-+ .end = IRQ_GMAC1,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 gmac_dmamask = 0xffffffffUL;
-+
-+static struct platform_device ethernet_device = {
-+ .name = "gemini-gmac",
-+ .id = 0,
-+ .dev = {
-+ .dma_mask = &gmac_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+ .num_resources = ARRAY_SIZE(gmac_resources),
-+ .resource = gmac_resources,
-+};
-+
-+int __init platform_register_ethernet(struct gemini_gmac_platform_data *pdata)
-+{
-+ unsigned int reg;
-+
-+ reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
-+ reg &= ~(GMAC_GMII | GMAC_1_ENABLE);
-+
-+ if (pdata->bus_id[1])
-+ reg |= GMAC_1_ENABLE;
-+ else if (pdata->interface[0] == PHY_INTERFACE_MODE_GMII)
-+ reg |= GMAC_GMII;
-+
-+ __raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
-+
-+ ethernet_device.dev.platform_data = pdata;
-+
-+ return platform_device_register(ðernet_device);
-+}
+++ /dev/null
---- a/arch/arm/mach-gemini/board-wbd111.c
-+++ b/arch/arm/mach-gemini/board-wbd111.c
-@@ -22,9 +22,29 @@
- #include <asm/mach/arch.h>
- #include <asm/mach/time.h>
-
-+#include <mach/gmac.h>
-
- #include "common.h"
-
-+static struct mdio_gpio_platform_data wbd111_mdio = {
-+ .mdc = 22,
-+ .mdio = 21,
-+ .phy_mask = ~(1 << 1),
-+};
-+
-+static struct platform_device wbd111_phy_device = {
-+ .name = "mdio-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &wbd111_mdio,
-+ },
-+};
-+
-+static struct gemini_gmac_platform_data gmac_data = {
-+ .bus_id[0] = "gpio-0:01",
-+ .interface[0] = PHY_INTERFACE_MODE_MII,
-+};
-+
- static struct gpio_keys_button wbd111_keys[] = {
- {
- .code = KEY_SETUP,
-@@ -123,6 +143,8 @@ static void __init wbd111_init(void)
- platform_device_register(&wbd111_keys_device);
- platform_register_rtc();
- platform_register_watchdog();
-+ platform_device_register(&wbd111_phy_device);
-+ platform_register_ethernet(&gmac_data);
- }
-
- MACHINE_START(WBD111, "Wiliboard WBD-111")
+++ /dev/null
---- a/arch/arm/mach-gemini/board-wbd222.c
-+++ b/arch/arm/mach-gemini/board-wbd222.c
-@@ -22,9 +22,31 @@
- #include <asm/mach/arch.h>
- #include <asm/mach/time.h>
-
-+#include <mach/gmac.h>
-
- #include "common.h"
-
-+static struct mdio_gpio_platform_data wbd222_mdio = {
-+ .mdc = 22,
-+ .mdio = 21,
-+ .phy_mask = ~((1 << 1) | (1 << 3)),
-+};
-+
-+static struct platform_device wbd222_phy_device = {
-+ .name = "mdio-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &wbd222_mdio,
-+ },
-+};
-+
-+static struct gemini_gmac_platform_data gmac_data = {
-+ .bus_id[0] = "gpio-0:01",
-+ .interface[0] = PHY_INTERFACE_MODE_MII,
-+ .bus_id[1] = "gpio-0:03",
-+ .interface[1] = PHY_INTERFACE_MODE_MII,
-+};
-+
- static struct gpio_keys_button wbd222_keys[] = {
- {
- .code = KEY_SETUP,
-@@ -123,6 +145,8 @@ static void __init wbd222_init(void)
- platform_device_register(&wbd222_keys_device);
- platform_register_rtc();
- platform_register_watchdog();
-+ platform_device_register(&wbd222_phy_device);
-+ platform_register_ethernet(&gmac_data);
- }
-
- MACHINE_START(WBD222, "Wiliboard WBD-222")
+++ /dev/null
---- a/arch/arm/mach-gemini/board-rut1xx.c
-+++ b/arch/arm/mach-gemini/board-rut1xx.c
-@@ -15,13 +15,35 @@
- #include <linux/input.h>
- #include <linux/gpio_keys.h>
- #include <linux/sizes.h>
-+#include <linux/mdio-gpio.h>
-
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/time.h>
-
-+#include <mach/gmac.h>
-+
- #include "common.h"
-
-+static struct mdio_gpio_platform_data rut1xx_mdio = {
-+ .mdc = 22,
-+ .mdio = 21,
-+ .phy_mask = ~(1 << 1),
-+};
-+
-+static struct platform_device rut1xx_phy_device = {
-+ .name = "mdio-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &rut1xx_mdio,
-+ },
-+};
-+
-+static struct gemini_gmac_platform_data gmac_data = {
-+ .bus_id[0] = "gpio-0:01",
-+ .interface[0] = PHY_INTERFACE_MODE_MII,
-+};
-+
- static struct gpio_keys_button rut1xx_keys[] = {
- {
- .code = KEY_SETUP,
-@@ -81,6 +103,8 @@ static void __init rut1xx_init(void)
- platform_device_register(&rut1xx_keys_device);
- platform_register_rtc();
- platform_register_watchdog();
-+ platform_device_register(&rut1xx_phy_device);
-+ platform_register_ethernet(&gmac_data);
- }
-
- MACHINE_START(RUT100, "Teltonika RUT100")
+++ /dev/null
---- /dev/null
-+++ b/drivers/usb/host/ehci-fotg2xx.c
-@@ -0,0 +1,459 @@
-+/*
-+ * EHCI Host Controller driver
-+ *
-+ * Copyright (C) 2006 Sony Computer Entertainment Inc.
-+ * Copyright 2006 Sony Corp.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License.
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <mach/hardware.h>
-+
-+#define otg_set(port, bits) writel(readl(hcd->regs + port) | bits, hcd->regs + port)
-+
-+#define otg_clear(port, bits) writel(readl(hcd->regs + port) & ~bits, hcd->regs + port)
-+
-+#define GLOBAL_ISR 0xC0
-+#define GLOBAL_ICR 0xC4
-+
-+#define HCD_MISC 0x40
-+
-+#define OTGC_SCR 0x80
-+#define OTGC_INT_EN 0x88
-+
-+#define GLOBAL_INT_POLARITY (1 << 3)
-+#define GLOBAL_INT_MASK_HC (1 << 2)
-+#define GLOBAL_INT_MASK_OTG (1 << 1)
-+#define GLOBAL_INT_MASK_DEV (1 << 0)
-+
-+#define OTGC_SCR_ID (1 << 21)
-+#define OTGC_SCR_CROLE (1 << 20)
-+#define OTGC_SCR_VBUS_VLD (1 << 19)
-+#define OTGC_SCR_A_SRP_RESP_TYPE (1 << 8)
-+#define OTGC_SCR_A_SRP_DET_EN (1 << 7)
-+#define OTGC_SCR_A_SET_B_HNP_EN (1 << 6)
-+#define OTGC_SCR_A_BUS_DROP (1 << 5)
-+#define OTGC_SCR_A_BUS_REQ (1 << 4)
-+
-+#define OTGC_INT_APLGRMV (1 << 12)
-+#define OTGC_INT_BPLGRMV (1 << 11)
-+#define OTGC_INT_OVC (1 << 10)
-+#define OTGC_INT_IDCHG (1 << 9)
-+#define OTGC_INT_RLCHG (1 << 8)
-+#define OTGC_INT_AVBUSERR (1 << 5)
-+#define OTGC_INT_ASRPDET (1 << 4)
-+#define OTGC_INT_BSRPDN (1 << 0)
-+
-+#define OTGC_INT_A_TYPE (OTGC_INT_ASRPDET|OTGC_INT_AVBUSERR|OTGC_INT_OVC|OTGC_INT_RLCHG|OTGC_INT_IDCHG|OTGC_INT_APLGRMV)
-+#define OTGC_INT_B_TYPE (OTGC_INT_AVBUSERR|OTGC_INT_OVC|OTGC_INT_RLCHG|OTGC_INT_IDCHG)
-+
-+static void fotg2xx_otgc_role_change(struct usb_hcd *hcd);
-+
-+static void fotg2xx_otgc_init(struct usb_hcd *hcd)
-+{
-+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
-+ unsigned int reg;
-+
-+ reg = __raw_readl(hcd->regs + OTGC_SCR);
-+ ehci_info(ehci, "role detected: %s, ",
-+ (reg & OTGC_SCR_CROLE) ? "Peripheral" : "Host");
-+
-+ if (reg & OTGC_SCR_ID)
-+ ehci_info(ehci, "B-Device (may be unsupported!)\n");
-+ else
-+ ehci_info(ehci, "A-Device\n");
-+
-+ /* Enable the SRP detect */
-+ reg &= ~OTGC_SCR_A_SRP_RESP_TYPE;
-+ __raw_writel(reg, hcd->regs + OTGC_SCR);
-+
-+ reg = __raw_readl(hcd->regs + OTGC_INT_EN);
-+ /* clear INT B: bits AVBUSERR | OVC | RLCHG | IDCHG */
-+ reg &= ~OTGC_INT_B_TYPE;
-+ /* set INT A: bits ASRPDET | AVBUSERR | OVC | RLCHG | IDCHG | APLGRMV */
-+ reg |= OTGC_INT_A_TYPE;
-+ __raw_writel(reg, hcd->regs + OTGC_INT_EN);
-+
-+ reg = __raw_readl(hcd->regs + GLOBAL_ICR);
-+ reg &= ~GLOBAL_INT_MASK_OTG;
-+ __raw_writel(reg, hcd->regs + GLOBAL_ICR);
-+
-+ /* setup MISC register, fixes timing problems */
-+ reg = __raw_readl(hcd->regs + HCD_MISC);
-+ reg |= 0xD;
-+ __raw_writel(reg, hcd->regs + HCD_MISC);
-+
-+ fotg2xx_otgc_role_change(hcd);
-+}
-+
-+static void fotg2xx_otgh_close(struct usb_hcd *hcd)
-+{
-+ unsigned int reg;
-+
-+ /* <1>.Enable Interrupt Mask */
-+ reg = __raw_readl(hcd->regs + GLOBAL_ICR);
-+ reg |= GLOBAL_INT_MASK_HC;
-+ __raw_writel(reg, hcd->regs + GLOBAL_ICR);
-+
-+ /* <2>.Clear the Interrupt status */
-+ reg = __raw_readl(hcd->regs + 0x18);
-+ reg &= 0x0000003F;
-+ __raw_writel(reg, hcd->regs + 0x14);
-+}
-+
-+static void fotg2xx_otgh_open(struct usb_hcd *hcd)
-+{
-+ unsigned int reg;
-+
-+ reg = __raw_readl(hcd->regs + OTGC_SCR);
-+ reg &= ~OTGC_SCR_A_SRP_DET_EN;
-+ __raw_writel(reg, hcd->regs + OTGC_SCR);
-+
-+ reg = __raw_readl(hcd->regs + GLOBAL_ICR);
-+ reg &= ~GLOBAL_INT_MASK_HC;
-+ __raw_writel(reg, hcd->regs + GLOBAL_ICR);
-+}
-+
-+/* change to host role */
-+static void fotg2xx_otgc_role_change(struct usb_hcd *hcd)
-+{
-+
-+ /* clear A_SET_B_HNP_EN */
-+ otg_clear(0x80, BIT(6));
-+
-+ /*** Enable VBUS driving */
-+ if (readl(hcd->regs + 0x80) & BIT(19))
-+ printk(KERN_INFO "VBUS already enabled\n");
-+ else {
-+ int cnt = 0;
-+
-+ /* clear A_BUS_DROP */
-+ otg_clear(0x80, BIT(5));
-+
-+ /* set A_BUS_REQ */
-+ otg_set(0x80, BIT(4));
-+
-+ /* set global bus reg to VBUS on */
-+ writel(readl(IO_ADDRESS(0x40000000) + 0x30) | ((BIT(21)|BIT(22))),
-+ IO_ADDRESS(0x40000000) + 0x30);
-+
-+ if (readl(hcd->regs + 0x80) & (1<<19)) {
-+ printk(KERN_INFO "Waiting for VBus");
-+ while (!(readl(hcd->regs + 0x80) & (1<<19)) && (cnt < 80)) {
-+ printk(KERN_CONT ".");
-+ cnt++;
-+ }
-+ printk(KERN_CONT "\n");
-+ } else
-+ printk(KERN_INFO "VBUS enabled.\n");
-+
-+ mdelay(1);
-+ }
-+ fotg2xx_otgh_open(hcd);
-+}
-+
-+static int fotg2xx_ehci_hc_reset(struct usb_hcd *hcd)
-+{
-+ int result;
-+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
-+
-+ ehci->caps = hcd->regs;
-+ ehci->regs = hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
-+
-+ dbg_hcs_params(ehci, "reset");
-+ dbg_hcc_params(ehci, "reset");
-+
-+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
-+ hcd->has_tt = 1;
-+
-+ result = ehci_halt(ehci);
-+ if (result)
-+ return result;
-+
-+ return ehci_init(hcd);
-+}
-+
-+/*
-+ * Name: OTGC_INT_ISR
-+ * Description:This interrupt service routine belongs to the OTG-Controller
-+ * <1>.Check for ID_Change
-+ * <2>.Check for RL_Change
-+ * <3>.Error Detect
-+ * Input: wINTStatus
-+ * Output:void
-+ */
-+void fotg2xx_int_isr(struct usb_hcd *hcd, u32 wINTStatus)
-+{
-+ /* <1>.Check for ID_Change */
-+ if (wINTStatus&OTGC_INT_IDCHG) {
-+ if ((readl(hcd->regs + 0x80) & BIT(21)) != 0)
-+ fotg2xx_otgc_init(hcd); /* Change to B Type */
-+ else
-+ fotg2xx_otgc_init(hcd); /* Change to A Type */
-+
-+ return;
-+ }
-+
-+ /* <2>.Check for RL_Change */
-+ if (wINTStatus&OTGC_INT_RLCHG)
-+ fotg2xx_otgc_role_change(hcd);
-+
-+ /* <3>.Error Detect */
-+ if (wINTStatus&OTGC_INT_AVBUSERR)
-+ printk(KERN_ERR "VBus error!\n");
-+
-+ if (wINTStatus&OTGC_INT_OVC)
-+ printk(KERN_WARNING "Overcurrent detected!\n");
-+
-+ /* <3>.Check for Type-A/Type-B Interrupt */
-+ if ((readl(hcd->regs + 0x80) & BIT(21)) == 0) { /*For Type-A Interrupt*/
-+ if (wINTStatus & (OTGC_INT_A_TYPE | OTGC_INT_ASRPDET)) {
-+ /* <1>.SRP detected => then set global variable */
-+ printk(KERN_WARNING "SRP detected, but not implemented!\n");
-+
-+#if 0
-+ u32 wTempCounter;
-+ /* <2>.Turn on the V Bus */
-+ pFTC_OTG->otg.state = OTG_STATE_A_WAIT_VRISE;
-+ OTGC_enable_vbus_draw_storlink(1);
-+ pFTC_OTG->otg.state = OTG_STATE_A_HOST;
-+ /* <3>.Should waiting for Device-Connect Wait 300ms */
-+ INFO(pFTC_OTG, ">>> OTG-A Waiting for OTG-B Connect,\n");
-+ wTempCounter = 0;
-+ while (mwHost20_PORTSC_ConnectStatus_Rd() == 0) {
-+ mdelay(1);
-+ wTempCounter++;
-+ /* Waiting for 300 ms */
-+ if (wTempCounter > 300) {
-+ mdwOTGC_Control_A_SRP_DET_EN_Clr();
-+ INFO(pFTC_OTG, ">>> OTG-B do not connect under 300 ms...\n");
-+ break;
-+ }
-+ }
-+ /* <4>.If Connect => issue quick Reset */
-+ if (mwHost20_PORTSC_ConnectStatus_Rd() > 0) {
-+ mdelay(300); /* For OPT-A Test */
-+ OTGH_host_quick_Reset();
-+ OTGH_Open();
-+ pFTC_OTG->otg.host->A_Disable_Set_Feature_HNP = 0;
-+ }
-+#endif
-+ }
-+ } else { /* For Type-B Interrupt */
-+ BUG();
-+ }
-+}
-+
-+static irqreturn_t fotg2xx_ehci_irq(int irq, void *devid)
-+{
-+ struct usb_hcd *hcd = devid;
-+ u32 val;
-+
-+ /* OTG Interrupt Status Register */
-+ val = readl(hcd->regs + 0x84);
-+
-+ /* OTG stuff */
-+ if (val) {
-+ /* supposed to do "INT STS Clr" - XXX */
-+ writel(readl(hcd->regs + 0x84) | val, hcd->regs + 0x84);
-+
-+ fotg2xx_int_isr(hcd, val);
-+
-+ /* supposed to do "INT STS Clr" - XXX */
-+ writel(readl(hcd->regs + 0x84) | val, hcd->regs + 0x84);
-+
-+ return IRQ_HANDLED;
-+ }
-+
-+ if ((readl(hcd->regs + 0x80) & BIT(20)) == 0) { /* Role is HOST */
-+ if (readl(hcd->regs + 0xC0) & BIT(2)) { /* INT STS HOST */
-+ /* leave this for ehci irq handler */
-+ return IRQ_NONE;
-+ }
-+ } else
-+ printk(KERN_WARNING
-+ "received irq for peripheral - don't know what to do!\n");
-+
-+ /* do not call the ehci irq handler */
-+ return IRQ_HANDLED;
-+}
-+
-+static int fotg2xx_ehci_run(struct usb_hcd *hcd)
-+{
-+ int retval;
-+
-+ retval = ehci_run(hcd);
-+
-+ fotg2xx_otgh_close(hcd);
-+ fotg2xx_otgc_init(hcd);
-+
-+ return retval;
-+}
-+
-+static const struct hc_driver fotg2xx_ehci_hc_driver = {
-+ .description = hcd_name,
-+ .product_desc = "FOTG2XX EHCI Host Controller",
-+ .hcd_priv_size = sizeof(struct ehci_hcd),
-+ .irq = ehci_irq,
-+ .flags = HCD_MEMORY | HCD_USB2,
-+ .reset = fotg2xx_ehci_hc_reset,
-+ .start = fotg2xx_ehci_run,
-+ .stop = ehci_stop,
-+ .shutdown = ehci_shutdown,
-+
-+ .urb_enqueue = ehci_urb_enqueue,
-+ .urb_dequeue = ehci_urb_dequeue,
-+ .endpoint_disable = ehci_endpoint_disable,
-+ .endpoint_reset = ehci_endpoint_reset,
-+
-+ .get_frame_number = ehci_get_frame,
-+
-+ .hub_status_data = ehci_hub_status_data,
-+ .hub_control = ehci_hub_control,
-+#if defined(CONFIG_PM)
-+ .bus_suspend = ehci_bus_suspend,
-+ .bus_resume = ehci_bus_resume,
-+#endif
-+ .relinquish_port = ehci_relinquish_port,
-+ .port_handed_over = ehci_port_handed_over,
-+
-+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
-+};
-+
-+static int fotg2xx_ehci_probe(struct platform_device *pdev)
-+{
-+ const struct hc_driver *driver = &fotg2xx_ehci_hc_driver;
-+ struct usb_hcd *hcd;
-+ struct resource *res;
-+ int irq;
-+ int retval;
-+
-+ pr_debug("initializing FOTG2XX-SOC USB Controller\n");
-+
-+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+ if (!res) {
-+ dev_err(&pdev->dev,
-+ "Found HC with no IRQ. Check %s setup!\n",
-+ dev_name(&pdev->dev));
-+ return -ENODEV;
-+ }
-+
-+ irq = res->start;
-+
-+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
-+ if (!hcd) {
-+ retval = -ENOMEM;
-+ goto err1;
-+ }
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(&pdev->dev,
-+ "Found HC with no register addr. Check %s setup!\n",
-+ dev_name(&pdev->dev));
-+ retval = -ENODEV;
-+ goto err2;
-+ }
-+
-+ hcd->rsrc_start = res->start;
-+ hcd->rsrc_len = res->end - res->start + 1;
-+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
-+ driver->description)) {
-+ dev_dbg(&pdev->dev, "controller already in use\n");
-+ retval = -EBUSY;
-+ goto err2;
-+ }
-+
-+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
-+ if (hcd->regs == NULL) {
-+ dev_dbg(&pdev->dev, "error mapping memory\n");
-+ retval = -EFAULT;
-+ goto err3;
-+ }
-+
-+
-+ /* set global reg to mini-A host */
-+ writel(readl(IO_ADDRESS(0x40000000) + 0x30) & ~(BIT(30)|BIT(29)),
-+ IO_ADDRESS(0x40000000) + 0x30);
-+
-+ /* USB0&USB1 - VBUS off */
-+ writel(readl(IO_ADDRESS(0x40000000) + 0x30) & ~(BIT(21)|BIT(22)),
-+ IO_ADDRESS(0x40000000) + 0x30);
-+
-+ if ((readl(hcd->regs) == 0x01000010) &&
-+ (readl(hcd->regs + 4) == 0x00000001) &&
-+ (readl(hcd->regs + 8) == 0x00000006)) {
-+ dev_info(&pdev->dev,
-+ "Found Faraday OTG 2XX controller (base = 0x%08lX)\n",
-+ (unsigned long) hcd->rsrc_start);
-+ } else {
-+ dev_err(&pdev->dev, "fotg2xx id mismatch: found %d.%d.%d\n",
-+ readl(hcd->regs + 0x00),
-+ readl(hcd->regs + 0x04),
-+ readl(hcd->regs + 0x08));
-+ retval = -ENODEV;
-+ goto err4;
-+ }
-+
-+ platform_set_drvdata(pdev, hcd);
-+
-+ /* mask interrupts - peripheral, otg, host, hi-active (bits 0,1,2,3) */
-+ otg_set(0xc4, BIT(3)); /* hi active */
-+
-+ otg_set(0xc4, BIT(2)); /* host */
-+ otg_set(0xc4, BIT(1)); /* otg */
-+ otg_set(0xc4, BIT(0)); /* peripheral */
-+
-+ /* register additional interrupt - here we check otg status */
-+ if ((request_irq(irq, &fotg2xx_ehci_irq, IRQF_SHARED | IRQF_DISABLED,
-+ hcd->irq_descr, hcd)) != 0) {
-+ dev_dbg(&pdev->dev, "error requesting irq %d\n", irq);
-+ retval = -EFAULT;
-+ goto err4;
-+ }
-+
-+ retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
-+ if (retval != 0)
-+ goto err4;
-+ return retval;
-+
-+err4:
-+ iounmap(hcd->regs);
-+err3:
-+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-+err2:
-+ usb_put_hcd(hcd);
-+err1:
-+ dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
-+ return retval;
-+}
-+
-+/* may be called without controller electrically present */
-+/* may be called with controller, bus, and devices active */
-+
-+int fotg2xx_ehci_remove(struct platform_device *pdev)
-+{
-+ struct usb_hcd *hcd =
-+ (struct usb_hcd *)platform_get_drvdata(pdev);
-+
-+ usb_remove_hcd(hcd);
-+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-+ iounmap(hcd->regs);
-+ usb_put_hcd(hcd);
-+ platform_set_drvdata(pdev, NULL);
-+
-+ return 0;
-+}
-+
-+MODULE_ALIAS("platform:ehci-fotg2xx");
-+
-+static struct platform_driver fotg2xx_ehci_driver = {
-+ .probe = fotg2xx_ehci_probe,
-+ .remove = fotg2xx_ehci_remove,
-+ .driver = {
-+ .name = "ehci-fotg2xx",
-+ },
-+};
---- a/drivers/usb/host/ehci.h
-+++ b/drivers/usb/host/ehci.h
-@@ -600,7 +600,12 @@ static inline unsigned int
- ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
- {
- if (ehci_is_TDI(ehci)) {
-+#ifdef CONFIG_ARCH_GEMINI
-+ portsc = readl(ehci_to_hcd(ehci)->regs + 0x80);
-+ switch ((portsc>>22)&3) {
-+#else
- switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
-+#endif
- case 0:
- return 0;
- case 1:
---- a/drivers/usb/host/ehci-hcd.c
-+++ b/drivers/usb/host/ehci-hcd.c
-@@ -204,10 +204,12 @@ static int ehci_halt (struct ehci_hcd *e
- * This routine gets called during probe before ehci->command
- * has been initialized, so we can't rely on its value.
- */
-+#ifndef CONFIG_ARCH_GEMINI
- ehci->command &= ~CMD_RUN;
- temp = ehci_readl(ehci, &ehci->regs->command);
- temp &= ~(CMD_RUN | CMD_IAAD);
- ehci_writel(ehci, temp, &ehci->regs->command);
-+#endif
-
- spin_unlock_irq(&ehci->lock);
- synchronize_irq(ehci_to_hcd(ehci)->irq);
-@@ -257,13 +259,17 @@ static int ehci_reset (struct ehci_hcd *
- if (ehci->has_hostpc) {
- ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
- &ehci->regs->usbmode_ex);
-+#ifndef CONFIG_ARCH_GEMINI
- ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
-+#endif
- }
- if (retval)
- return retval;
-
-+#ifndef CONFIG_ARCH_GEMINI
- if (ehci_is_TDI(ehci))
- tdi_reset (ehci);
-+#endif
-
- if (ehci->debug)
- dbgp_external_startup(ehci_to_hcd(ehci));
-@@ -341,11 +347,14 @@ static void ehci_silence_controller(stru
- ehci->rh_state = EHCI_RH_HALTED;
- ehci_turn_off_all_ports(ehci);
-
-+#ifndef CONFIG_ARCH_GEMINI
- /* make BIOS/etc use companion controller during reboot */
- ehci_writel(ehci, 0, &ehci->regs->configured_flag);
-
- /* unblock posted writes */
- ehci_readl(ehci, &ehci->regs->configured_flag);
-+#endif
-+
- spin_unlock_irq(&ehci->lock);
- }
-
-@@ -600,7 +609,9 @@ static int ehci_run (struct usb_hcd *hcd
- // Philips, Intel, and maybe others need CMD_RUN before the
- // root hub will detect new devices (why?); NEC doesn't
- ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
-+#ifndef CONFIG_ARCH_GEMINI
- ehci->command |= CMD_RUN;
-+#endif
- ehci_writel(ehci, ehci->command, &ehci->regs->command);
- dbg_cmd (ehci, "init", ehci->command);
-
-@@ -620,9 +631,11 @@ static int ehci_run (struct usb_hcd *hcd
- */
- down_write(&ehci_cf_port_reset_rwsem);
- ehci->rh_state = EHCI_RH_RUNNING;
-+#ifndef CONFIG_ARCH_GEMINI
- ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
- ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
- msleep(5);
-+#endif /* !CONFIG_ARCH_GEMINI */
- up_write(&ehci_cf_port_reset_rwsem);
- ehci->last_periodic_enable = ktime_get_real();
-
-@@ -1238,6 +1251,11 @@ MODULE_DESCRIPTION(DRIVER_DESC);
- MODULE_AUTHOR (DRIVER_AUTHOR);
- MODULE_LICENSE ("GPL");
-
-+#ifdef CONFIG_ARCH_GEMINI
-+#include "ehci-fotg2xx.c"
-+#define PLATFORM_DRIVER fotg2xx_ehci_driver
-+#endif
-+
- #ifdef CONFIG_USB_EHCI_FSL
- #include "ehci-fsl.c"
- #define PLATFORM_DRIVER ehci_fsl_driver
---- a/drivers/usb/host/ehci-hub.c
-+++ b/drivers/usb/host/ehci-hub.c
-@@ -912,6 +912,12 @@ static int ehci_hub_control (
- /* see what we found out */
- temp = check_reset_complete (ehci, wIndex, status_reg,
- ehci_readl(ehci, status_reg));
-+#ifdef CONFIG_ARCH_GEMINI
-+ /* restart schedule */
-+ ehci_writel(ehci, ehci_readl(ehci, &ehci->regs->command) | CMD_RUN, &ehci->regs->command);
-+
-+// hcd->state = HC_STATE_RUNNING;
-+#endif
- }
-
- if (!(temp & (PORT_RESUME|PORT_RESET))) {
---- a/drivers/usb/Kconfig
-+++ b/drivers/usb/Kconfig
-@@ -47,6 +47,7 @@ config USB_ARCH_HAS_EHCI
- default y if MICROBLAZE
- default y if SPARC_LEON
- default y if ARCH_MMP
-+ default y if ARCH_GEMINI
- default y if MACH_LOONGSON1
- default y if PLAT_ORION
- default PCI
-@@ -96,7 +97,7 @@ config USB
- traditional PC serial port. The bus supplies power to peripherals
- and allows for hot swapping. Up to 127 USB peripherals can be
- connected to a single USB host in a tree structure.
--
-+
- The USB host is the root of the tree, the peripherals are the
- leaves and the inner nodes are special USB devices called hubs.
- Most PCs now have USB host ports, used to connect peripherals
---- a/include/linux/usb/ehci_def.h
-+++ b/include/linux/usb/ehci_def.h
-@@ -111,6 +111,7 @@ struct ehci_regs {
- /* ASYNCLISTADDR: offset 0x18 */
- u32 async_next; /* address of next async queue head */
-
-+#ifndef CONFIG_ARCH_GEMINI
- u32 reserved1[2];
-
- /* TXFILLTUNING: offset 0x24 */
-@@ -118,6 +119,7 @@ struct ehci_regs {
- #define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
-
- u32 reserved2[6];
-+#endif /* !CONFIG_ARCH_GEMINI */
-
- /* CONFIGFLAG: offset 0x40 */
- u32 configured_flag;
+++ /dev/null
---- a/arch/arm/mach-gemini/devices.c
-+++ b/arch/arm/mach-gemini/devices.c
-@@ -185,3 +185,62 @@ int __init platform_register_ethernet(st
-
- return platform_device_register(ðernet_device);
- }
-+
-+static u64 usb0_dmamask = DMA_BIT_MASK(32);
-+static struct resource usb0_resources[] = {
-+ {
-+ .start = 0x68000000,
-+ .end = 0x68000fff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IRQ_USB0,
-+ .end = IRQ_USB0,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 usb1_dmamask = DMA_BIT_MASK(32);
-+static struct resource usb1_resources[] = {
-+ {
-+ .start = 0x69000000,
-+ .end = 0x69000fff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IRQ_USB1,
-+ .end = IRQ_USB1,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct platform_device usb_device[] = {
-+ {
-+ .name = "ehci-fotg2xx",
-+ .id = 0,
-+ .dev = {
-+ .dma_mask = &usb0_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+ .num_resources = ARRAY_SIZE(usb0_resources),
-+ .resource = usb0_resources,
-+ },
-+ {
-+ .name = "ehci-fotg2xx",
-+ .id = 1,
-+ .dev = {
-+ .dma_mask = &usb1_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+ .num_resources = ARRAY_SIZE(usb1_resources),
-+ .resource = usb1_resources,
-+ },
-+};
-+
-+int __init platform_register_usb(unsigned int id)
-+{
-+ if (id > 1)
-+ return -EINVAL;
-+
-+ return platform_device_register(&usb_device[id]);
-+}
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -28,6 +28,7 @@ extern int platform_register_pflash(unsi
- unsigned int nr_parts);
- extern int platform_register_watchdog(void);
- extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
-+extern int platform_register_usb(unsigned int id);
-
- extern void gemini_restart(char mode, const char *cmd);
-
+++ /dev/null
---- a/arch/arm/mach-gemini/board-wbd111.c
-+++ b/arch/arm/mach-gemini/board-wbd111.c
-@@ -145,6 +145,7 @@ static void __init wbd111_init(void)
- platform_register_watchdog();
- platform_device_register(&wbd111_phy_device);
- platform_register_ethernet(&gmac_data);
-+ platform_register_usb(0);
- }
-
- MACHINE_START(WBD111, "Wiliboard WBD-111")
---- a/drivers/usb/host/ehci-hcd.c
-+++ b/drivers/usb/host/ehci-hcd.c
-@@ -99,7 +99,11 @@ module_param (park, uint, S_IRUGO);
- MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
-
- /* for flakey hardware, ignore overcurrent indicators */
-+#ifdef CONFIG_ARCH_GEMINI
-+static bool ignore_oc = 1;
-+#else
- static bool ignore_oc = 0;
-+#endif
- module_param (ignore_oc, bool, S_IRUGO);
- MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
-
+++ /dev/null
---- a/arch/arm/mach-gemini/board-wbd222.c
-+++ b/arch/arm/mach-gemini/board-wbd222.c
-@@ -147,6 +147,7 @@ static void __init wbd222_init(void)
- platform_register_watchdog();
- platform_device_register(&wbd222_phy_device);
- platform_register_ethernet(&gmac_data);
-+ platform_register_usb(0);
- }
-
- MACHINE_START(WBD222, "Wiliboard WBD-222")
+++ /dev/null
---- a/arch/arm/mach-gemini/board-rut1xx.c
-+++ b/arch/arm/mach-gemini/board-rut1xx.c
-@@ -105,6 +105,7 @@ static void __init rut1xx_init(void)
- platform_register_watchdog();
- platform_device_register(&rut1xx_phy_device);
- platform_register_ethernet(&gmac_data);
-+ platform_register_usb(0);
- }
-
- MACHINE_START(RUT100, "Teltonika RUT100")
+++ /dev/null
---- a/arch/arm/mach-gemini/board-nas4220b.c
-+++ b/arch/arm/mach-gemini/board-nas4220b.c
-@@ -96,6 +96,8 @@ static void __init ib4220b_init(void)
- platform_device_register(&ib4220b_key_device);
- platform_register_rtc();
- platform_register_watchdog();
-+ platform_register_usb(0);
-+ platform_register_usb(1);
- }
-
- MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
+++ /dev/null
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -412,6 +412,7 @@ config ARCH_GEMINI
- select ARCH_USES_GETTIMEOFFSET
- select NEED_MACH_GPIO_H
- select CPU_FA526
-+ select MIGHT_HAVE_PCI
- help
- Support for the Cortina Systems Gemini family SoCs
-
---- a/arch/arm/mach-gemini/include/mach/hardware.h
-+++ b/arch/arm/mach-gemini/include/mach/hardware.h
-@@ -71,4 +71,9 @@
- */
- #define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
-
-+/*
-+ * PCI subsystem macros
-+ */
-+#define pcibios_assign_all_busses() 1
-+
- #endif
---- a/arch/arm/mach-gemini/include/mach/irqs.h
-+++ b/arch/arm/mach-gemini/include/mach/irqs.h
-@@ -43,11 +43,14 @@
-
- #define NORMAL_IRQ_NUM 32
-
--#define GPIO_IRQ_BASE NORMAL_IRQ_NUM
-+#define PCI_IRQ_BASE NORMAL_IRQ_NUM
-+#define PCI_IRQ_NUM 4
-+
-+#define GPIO_IRQ_BASE (NORMAL_IRQ_NUM + PCI_IRQ_NUM)
- #define GPIO_IRQ_NUM (3 * 32)
-
- #define ARCH_TIMER_IRQ IRQ_TIMER2
-
--#define NR_IRQS (NORMAL_IRQ_NUM + GPIO_IRQ_NUM)
-+#define NR_IRQS (NORMAL_IRQ_NUM + PCI_IRQ_NUM + GPIO_IRQ_NUM)
-
- #endif /* __MACH_IRQS_H__ */
---- a/arch/arm/mach-gemini/Makefile
-+++ b/arch/arm/mach-gemini/Makefile
-@@ -6,6 +6,8 @@
-
- obj-y := irq.o mm.o time.o devices.o gpio.o idle.o reset.o
-
-+obj-$(CONFIG_PCI) += pci.o
-+
- # Board-specific support
- obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
- obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o
---- a/arch/arm/mach-gemini/mm.c
-+++ b/arch/arm/mach-gemini/mm.c
-@@ -59,6 +59,11 @@ static struct map_desc gemini_io_desc[]
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_PCI_IO_BASE),
-+ .pfn = __phys_to_pfn(GEMINI_PCI_IO_BASE),
-+ .length = SZ_512K,
-+ .type = MT_DEVICE,
-+ }, {
- .virtual = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
- .pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
- .length = SZ_512K,
---- /dev/null
-+++ b/arch/arm/mach-gemini/pci.c
-@@ -0,0 +1,320 @@
-+/*
-+ * Support for Gemini PCI Controller
-+ *
-+ * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
-+ * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
-+ *
-+ * based on SL2312 PCI controller code
-+ * Storlink (C) 2003
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/pci.h>
-+#include <linux/irq.h>
-+#include <linux/gpio.h>
-+
-+#include <asm/mach/pci.h>
-+
-+#include <mach/irqs.h>
-+#include <mach/hardware.h>
-+
-+#define GEMINI_PCI_IOSIZE_1M 0x0000
-+
-+#define GEMINI_PCI_PMC 0x40
-+#define GEMINI_PCI_PMCSR 0x44
-+#define GEMINI_PCI_CTRL1 0x48
-+#define GEMINI_PCI_CTRL2 0x4C
-+#define GEMINI_PCI_MEM1_BASE_SIZE 0x50
-+#define GEMINI_PCI_MEM2_BASE_SIZE 0x54
-+#define GEMINI_PCI_MEM3_BASE_SIZE 0x58
-+
-+#define PCI_CTRL2_INTSTS_OFFSET 28
-+#define PCI_CTRL2_INTMASK_OFFSET 22
-+
-+#define GEMINI_PCI_DMA_MASK 0xFFF00000
-+#define GEMINI_PCI_DMA_MEM1_BASE 0x00000000
-+#define GEMINI_PCI_DMA_MEM2_BASE 0x00000000
-+#define GEMINI_PCI_DMA_MEM3_BASE 0x00000000
-+#define GEMINI_PCI_DMA_MEM1_SIZE 7
-+#define GEMINI_PCI_DMA_MEM2_SIZE 6
-+#define GEMINI_PCI_DMA_MEM3_SIZE 6
-+
-+#define PCI_CONF_ENABLE (1 << 31)
-+#define PCI_CONF_WHERE(r) ((r) & 0xFC)
-+#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
-+#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
-+#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
-+
-+#define PCI_IOSIZE_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE))
-+#define PCI_PROT_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x04)
-+#define PCI_CTRL_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x08)
-+#define PCI_SOFTRST_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x10)
-+#define PCI_CONFIG_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x28)
-+#define PCI_DATA_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x2C)
-+
-+
-+static DEFINE_SPINLOCK(gemini_pci_lock);
-+
-+static int gemini_pci_read_config(struct pci_bus* bus, unsigned int fn,
-+ int config, int size, u32* value)
-+{
-+ unsigned long irq_flags;
-+
-+ spin_lock_irqsave(&gemini_pci_lock, irq_flags);
-+
-+ __raw_writel(PCI_CONF_BUS(bus->number) |
-+ PCI_CONF_DEVICE(PCI_SLOT(fn)) |
-+ PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
-+ PCI_CONF_WHERE(config) |
-+ PCI_CONF_ENABLE,
-+ PCI_CONFIG_REG);
-+
-+ *value = __raw_readl(PCI_DATA_REG);
-+
-+ if (size == 1)
-+ *value = (*value >> (8 * (config & 3))) & 0xFF;
-+ else if (size == 2)
-+ *value = (*value >> (8 * (config & 3))) & 0xFFFF;
-+
-+ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
-+
-+ dev_dbg(&bus->dev,
-+ "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
-+ PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int gemini_pci_write_config(struct pci_bus* bus, unsigned int fn,
-+ int config, int size, u32 value)
-+{
-+ unsigned long irq_flags = 0;
-+ int ret = PCIBIOS_SUCCESSFUL;
-+
-+ dev_dbg(&bus->dev,
-+ "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
-+ PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
-+
-+ spin_lock_irqsave(&gemini_pci_lock, irq_flags);
-+
-+ __raw_writel(PCI_CONF_BUS(bus->number) |
-+ PCI_CONF_DEVICE(PCI_SLOT(fn)) |
-+ PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
-+ PCI_CONF_WHERE(config) |
-+ PCI_CONF_ENABLE,
-+ PCI_CONFIG_REG);
-+
-+ switch(size) {
-+ case 4:
-+ __raw_writel(value, PCI_DATA_REG);
-+ break;
-+ case 2:
-+ __raw_writew(value, PCI_DATA_REG + (config & 3));
-+ break;
-+ case 1:
-+ __raw_writeb(value, PCI_DATA_REG + (config & 3));
-+ break;
-+ default:
-+ ret = PCIBIOS_BAD_REGISTER_NUMBER;
-+ }
-+
-+ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
-+
-+ return ret;
-+}
-+
-+static struct pci_ops gemini_pci_ops = {
-+ .read = gemini_pci_read_config,
-+ .write = gemini_pci_write_config,
-+};
-+
-+static struct resource gemini_pci_resource_io = {
-+ .name = "PCI I/O Space",
-+ .start = GEMINI_PCI_IO_BASE,
-+ .end = GEMINI_PCI_IO_BASE + SZ_1M - 1,
-+ .flags = IORESOURCE_IO,
-+};
-+
-+static struct resource gemini_pci_resource_mem = {
-+ .name = "PCI Memory Space",
-+ .start = GEMINI_PCI_MEM_BASE,
-+ .end = GEMINI_PCI_MEM_BASE + SZ_128M - 1,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static int __init gemini_pci_request_resources(struct pci_sys_data *sys)
-+{
-+ if (request_resource(&ioport_resource, &gemini_pci_resource_io))
-+ goto bad_resources;
-+ if (request_resource(&iomem_resource, &gemini_pci_resource_mem))
-+ goto bad_resources;
-+
-+ pci_add_resource(&sys->resources, &gemini_pci_resource_io);
-+ pci_add_resource(&sys->resources, &gemini_pci_resource_mem);
-+
-+ return 0;
-+
-+bad_resources:
-+ pr_err("Gemini PCI: request_resource() failed. "
-+ "Abort PCI bus enumeration.\n");
-+ return -1;
-+}
-+
-+static int __init gemini_pci_setup(int nr, struct pci_sys_data *sys)
-+{
-+ unsigned int cmd;
-+
-+ pcibios_min_io = 0x100;
-+ pcibios_min_mem = 0;
-+
-+ if ((nr > 0) || gemini_pci_request_resources(sys))
-+ return 0;
-+
-+ /* setup I/O space to 1MB size */
-+ __raw_writel(GEMINI_PCI_IOSIZE_1M, PCI_IOSIZE_REG);
-+
-+ /* setup hostbridge */
-+ cmd = __raw_readl(PCI_CTRL_REG);
-+ cmd |= PCI_COMMAND_IO;
-+ cmd |= PCI_COMMAND_MEMORY;
-+ cmd |= PCI_COMMAND_MASTER;
-+ __raw_writel(cmd, PCI_CTRL_REG);
-+
-+ return 1;
-+}
-+
-+static struct pci_bus* __init gemini_pci_scan_bus(int nr, struct pci_sys_data* sys)
-+{
-+ unsigned int reg = 0;
-+ struct pci_bus* bus = 0;
-+
-+ bus = pci_scan_bus(nr, &gemini_pci_ops, sys);
-+ if (bus) {
-+ dev_dbg(&bus->dev, "setting up PCI DMA\n");
-+ reg = (GEMINI_PCI_DMA_MEM1_BASE & GEMINI_PCI_DMA_MASK)
-+ | (GEMINI_PCI_DMA_MEM1_SIZE << 16);
-+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM1_BASE_SIZE, 4, reg);
-+ reg = (GEMINI_PCI_DMA_MEM2_BASE & GEMINI_PCI_DMA_MASK)
-+ | (GEMINI_PCI_DMA_MEM2_SIZE << 16);
-+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM2_BASE_SIZE, 4, reg);
-+ reg = (GEMINI_PCI_DMA_MEM3_BASE & GEMINI_PCI_DMA_MASK)
-+ | (GEMINI_PCI_DMA_MEM3_SIZE << 16);
-+ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM3_BASE_SIZE, 4, reg);
-+ }
-+
-+ return bus;
-+}
-+
-+/* Should work with all boards based on original Storlink EVB */
-+static int __init gemini_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ if (slot < 9 || slot > 12)
-+ return -1;
-+
-+ return PCI_IRQ_BASE + (((slot - 9) + (pin - 1)) & 0x3);
-+}
-+
-+static struct hw_pci gemini_hw_pci __initdata = {
-+ .nr_controllers = 1,
-+ .setup = gemini_pci_setup,
-+ .scan = gemini_pci_scan_bus,
-+ .map_irq = gemini_pci_map_irq,
-+};
-+
-+/* we need this for muxed PCI interrupts handling */
-+static struct pci_bus bogus_pci_bus;
-+
-+static void gemini_pci_ack_irq(struct irq_data *d)
-+{
-+ unsigned int irq = d->irq;
-+ unsigned int reg;
-+
-+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
-+ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
-+ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTSTS_OFFSET);
-+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
-+}
-+
-+static void gemini_pci_mask_irq(struct irq_data *d)
-+{
-+ unsigned int irq = d->irq;
-+ unsigned int reg;
-+
-+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
-+ reg &= ~((0xF << PCI_CTRL2_INTSTS_OFFSET)
-+ | (1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET)));
-+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
-+}
-+
-+static void gemini_pci_unmask_irq(struct irq_data *d)
-+{
-+ unsigned int irq = d->irq;
-+ unsigned int reg;
-+
-+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
-+ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
-+ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET);
-+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
-+}
-+
-+static void gemini_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
-+{
-+ unsigned int pci_irq_no, irq_stat, reg, i;
-+
-+ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®);
-+ irq_stat = reg >> PCI_CTRL2_INTSTS_OFFSET;
-+
-+ for (i = 0; i < 4; i++) {
-+
-+ if ((irq_stat & (1 << i)) == 0)
-+ continue;
-+
-+ pci_irq_no = PCI_IRQ_BASE + i;
-+
-+ BUG_ON(!(irq_desc[pci_irq_no].handle_irq));
-+ irq_desc[pci_irq_no].handle_irq(pci_irq_no,
-+ &irq_desc[pci_irq_no]);
-+ }
-+}
-+
-+static struct irq_chip gemini_pci_irq_chip = {
-+ .name = "PCI",
-+ .irq_ack = gemini_pci_ack_irq,
-+ .irq_mask = gemini_pci_mask_irq,
-+ .irq_unmask = gemini_pci_unmask_irq,
-+};
-+
-+static int __init gemini_pci_init(void)
-+{
-+ int i;
-+
-+ for (i = 72; i <= 95; i++)
-+ gpio_request(i, "PCI");
-+
-+ /* initialize our bogus bus */
-+ dev_set_name(&bogus_pci_bus.dev, "PCI IRQ handler");
-+ bogus_pci_bus.number = 0;
-+
-+ /* mask and clear all interrupts */
-+ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2 + 2, 2,
-+ 0xF000);
-+
-+ for (i = PCI_IRQ_BASE; i < PCI_IRQ_BASE + 4; i++) {
-+ irq_set_chip_and_handler(i, &gemini_pci_irq_chip,
-+ handle_level_irq);
-+ set_irq_flags(i, IRQF_VALID);
-+ }
-+
-+ irq_set_chained_handler(IRQ_PCI, gemini_pci_irq_handler);
-+
-+ pci_common_init(&gemini_hw_pci);
-+
-+ return 0;
-+}
-+
-+subsys_initcall(gemini_pci_init);
+++ /dev/null
-#
-# Copyright (C) 2007-2011 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=iop32x
-BOARDNAME:=Intel IOP32x
-FEATURES:=squashfs broken
-MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
-
-LINUX_VERSION:=3.3.8
-
-include $(INCLUDE_DIR)/target.mk
-
-KERNELNAME:="zImage"
-
-$(eval $(call BuildTarget))
+++ /dev/null
-# Network configuration file
-
-config interface loopback
- option ifname lo
- option proto static
- option ipaddr 127.0.0.1
- option netmask 255.0.0.0
-
-config interface lan
- option ifname eth0
- option proto dhcp
-
-config interface lan6
- option ifname @lan
- option proto dhcpv6
- option reqprefix no
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-CONFIG_ARCH_IOP32X=y
-# CONFIG_ARCH_IQ31244 is not set
-# CONFIG_ARCH_IQ80321 is not set
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
-CONFIG_ARM=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_THUMB is not set
-# CONFIG_ARPD is not set
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATA=m
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_PMU=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CPU_XSCALE=y
-# CONFIG_DEBUG_USER is not set
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DLCI=m
-CONFIG_DLCI_MAX=8
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DNOTIFY=y
-# CONFIG_DSCC4 is not set
-CONFIG_E1000=y
-# CONFIG_FARSYNC is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GPIOLIB=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_AOUT=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SCHED_CLOCK=y
-CONFIG_HAVE_SPARSE_IRQ=y
-CONFIG_HDLC=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_RAW=m
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_IOP3XX is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INTEL_IOP_ADMA=y
-# CONFIG_IOP_WATCHDOG is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-# CONFIG_IWMMXT is not set
-CONFIG_KTIME_SCALAR=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_MACH_EM7210 is not set
-# CONFIG_MACH_GLANTANK is not set
-CONFIG_MACH_N2100=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_DMA=y
-CONFIG_NLS=m
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PLAT_IOP=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_R8169=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_PCF8563=y
-CONFIG_RTC_DRV_X1205=y
-CONFIG_SCSI=m
-CONFIG_SCSI_MOD=m
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_UID16=y
-CONFIG_USB=m
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_COMMON=m
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_OHCI_HCD_PLATFORM is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_UHCI_HCD=m
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WAN=y
-CONFIG_XSCALE_PMU=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2007-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/BuildKernel
- cp $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage
-#
-# XXX - FIXME
-#
-# BIN_DIR=$(BIN_DIR) IMG_PREFIX="$(IMG_PREFIX)" $(TOPDIR)/scripts/arm-magic.sh
-endef
-
-define Image/Build
- $(call Image/Build/$(1),$(1))
-endef
-
-define Image/Build/jffs2-64k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=65536 conv=sync
-endef
-
-define Image/Build/jffs2-128k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=131072 conv=sync
- $(call Image/Build/slug,$(1))
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=131072 conv=sync
- $(call Image/Build/slug,$(1))
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-From 15e9b9b9ed268fa91e52c44d621f3d0296162d15 Mon Sep 17 00:00:00 2001
-From: David Howells <dhowells@redhat.com>
-Date: Fri, 23 Mar 2012 15:37:34 +0000
-Subject: [PATCH] ARM: Fix missing linux/types.h #inclusion in asm/hardware/iop3xx.h
-
-arch/arm/include/asm/hardware/iop3xx.h needs to include linux/types.h to avoid
-the following errors:
-
-In file included from arch/arm/plat-iop/restart.c:10:0:
-/data/fs/linux-2.6-fscache/arch/arm/include/asm/hardware/iop3xx.h:239:1: error: unknown type name 'u32'
-/data/fs/linux-2.6-fscache/arch/arm/include/asm/hardware/iop3xx.h: In function 'read_tmr0':
-/data/fs/linux-2.6-fscache/arch/arm/include/asm/hardware/iop3xx.h:241:2: error: unknown type name 'u32'
-/data/fs/linux-2.6-fscache/arch/arm/include/asm/hardware/iop3xx.h: At top level:
-/data/fs/linux-2.6-fscache/arch/arm/include/asm/hardware/iop3xx.h:246:31: error: unknown type name 'u32'
-...
-
-Signed-off-by: David Howells <dhowells@redhat.com>
----
- arch/arm/include/asm/hardware/iop3xx.h | 3 +++
- 1 files changed, 3 insertions(+), 0 deletions(-)
-
---- a/arch/arm/include/asm/hardware/iop3xx.h
-+++ b/arch/arm/include/asm/hardware/iop3xx.h
-@@ -231,6 +231,9 @@ extern int iop3xx_get_init_atu(void);
-
-
- #ifndef __ASSEMBLY__
-+
-+#include <linux/types.h>
-+
- void iop3xx_map_io(void);
- void iop_init_cp6_handler(void);
- void iop_init_time(unsigned long tickrate);
+++ /dev/null
-From 9f97da78bf018206fb623cd351d454af2f105fe0 Mon Sep 17 00:00:00 2001
-From: David Howells <dhowells@redhat.com>
-Date: Wed, 28 Mar 2012 18:30:01 +0100
-Subject: [PATCH] Disintegrate asm/system.h for ARM
-
-Disintegrate asm/system.h for ARM.
-
-Signed-off-by: David Howells <dhowells@redhat.com>
-cc: Russell King <linux@arm.linux.org.uk>
-cc: linux-arm-kernel@lists.infradead.org
----
- arch/arm/plat-iop/restart.c | 1 +
- 1 files changed, 1 insertions(+), 0 deletions(-)
-
---- a/arch/arm/plat-iop/restart.c
-+++ b/arch/arm/plat-iop/restart.c
-@@ -8,6 +8,7 @@
- * published by the Free Software Foundation.
- */
- #include <asm/hardware/iop3xx.h>
-+#include <asm/system.h>
- #include <mach/hardware.h>
-
- void iop3xx_restart(char mode, const char *cmd)
+++ /dev/null
---- a/arch/arm/plat-iop/pci.c
-+++ b/arch/arm/plat-iop/pci.c
-@@ -221,7 +221,7 @@ int iop3xx_pci_setup(int nr, struct pci_
- return 1;
- }
-
--struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys)
-+struct pci_bus * __devinit iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys)
- {
- return pci_scan_root_bus(NULL, sys->busnr, &iop3xx_ops, sys,
- &sys->resources);
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=mcs814x
-BOARDNAME:=Moschip MCS814x
-FEATURES:=usb squashfs
-CPU_TYPE:=arm926ej-s
-MAINTAINER:=Florian Fainelli <florian@openwrt.org>
-
-LINUX_VERSION:=3.3.8
-
-DEVICE_TYPE:=other
-
-include $(INCLUDE_DIR)/target.mk
-
-DEFAULT_PACKAGES := $(filter-out ppp%,$(DEFAULT_PACKAGES)) \
- kmod-usb-core kmod-usb2 kmod-usb-ohci \
- kmod-usb-storage kmod-fs-vfat \
- kmod-nls-cp437 kmod-nls-iso8859-1 kmod-nls-iso8859-15 \
- kmod-nls-utf8 \
- kmod-mcs814x-wdt kmod-ledtrig-usbdev
-
-KERNELNAME:="zImage dtbs"
-
-$(eval $(call BuildTarget))
+++ /dev/null
-# Copyright (C) 2012 OpenWrt.org
-
-config interface loopback
- option ifname lo
- option proto static
- option ipaddr 127.0.0.1
- option netmask 255.0.0.0
-
-config interface lan
- option ifname eth0
- option proto static
- option ipaddr 192.168.1.1
- option netmask 255.255.255.0
- option ip6assign 60
-
-config interface wan6
- option ifname @wan
- option proto dhcpv6
-
-config globals globals
- option ula_prefix auto
+++ /dev/null
-#!/bin/sh
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-
-. /lib/functions/uci-defaults.sh
-. /lib/mcs814x.sh
-
-board=$(mcs814x_board_name)
-
-case "$board" in
-dlan-usb-extender)
- ucidef_set_led_usbdev "usb" "USB" "dlan-usb-extender:green:usb" "2-1"
- ;;
-rbt-832)
- ucidef_set_led_usbdev "usb1" "USB1" "rbt-832:red:usb0" "1-1"
- ucidef_set_led_usbdev "usb2" "USB2" "rbt-832:red:usb1" "1-2"
- ucidef_set_led_usbdev "usb3" "USB3" "rbt-832:red:usb2" "1-3"
- ucidef_set_led_usbdev "usb4" "USB4" "rbt-832:red:usb3" "1-4"
- ucidef_set_led_netdev "eth" "eth" "rbt-832:red:ethernet" "eth0"
- ;;
-esac
-
-ucidef_commit_leds
-
-exit 0
+++ /dev/null
-#!/bin/sh
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-
-MCS814X_BOARD_NAME=
-MCS814X_MODEL=
-
-mcs814x_board_detect() {
- local machine
- local name
-
- machine=$(cat /proc/device-tree/model)
-
- case "$machine" in
- *"Devolo dLAN USB Extender")
- name="dlan-usb-extender"
- ;;
- *"Tigal RBT-832")
- name="rbt-832"
- ;;
- esac
-
- [ -z "$name" ] && name="unknown"
-
- [ -z "$MCS814X_BOARD_NAME" ] && MCS814X_BOARD_NAME="$name"
- [ -z "$MCS814X_MODEL" ] && MCS814X_MODEL="$machine"
-
- [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/"
-
- echo "$MCS814X_BOARD_NAME" > /tmp/sysinfo/board_name
- echo "$MCS814X_MODEL" > /tmp/sysinfo/model
-}
-
-mcs814x_board_name() {
- local name
-
- [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name)
- [ -z "$name" ] && name="unknown"
-
- echo "$name"
-}
+++ /dev/null
-#!/bin/sh
-
-do_mcs814x() {
- . /lib/mcs814x.sh
-
- mcs814x_board_detect
-}
-
-boot_hook_add preinit_main do_mcs814x
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-CONFIG_ARCH_MCS814X=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USES_GETTIMEOFFSET=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=8
-# CONFIG_ARM_THUMB is not set
-# CONFIG_ARPD is not set
-CONFIG_BCMA_POSSIBLE=y
-CONFIG_BINFMT_MISC=y
-# CONFIG_BLK_DEV is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CMDLINE="earlyprintk"
-CONFIG_CMDLINE_EXTEND=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_ARM926T=y
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_UART_NONE=y
-# CONFIG_DEBUG_USER is not set
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_FIQ=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_MCS814X=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_AOUT=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SPARSE_IRQ=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MCS814X=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQ_DOMAIN=y
-# CONFIG_ISDN is not set
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_SUMMARY is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_KALLSYMS=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-# CONFIG_LEDS_TRIGGER_NETDEV is not set
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-CONFIG_LIBCRC32C=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_DLAN_USB_EXT=y
-CONFIG_MACH_RBT_832=y
-CONFIG_MCS8140=y
-CONFIG_MCS814X_PHY=y
-# CONFIG_MCS814X_WATCHDOG is not set
-CONFIG_MDIO_BOARDINFO=y
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_IMPA7 is not set
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_MACH_MEMORY_H=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_KEY=y
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-15"
-CONFIG_NUPORT_ETHERNET_DRIVER=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARTITION_ADVANCED is not set
-# CONFIG_PCI is not set
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_PROC_DEVICETREE=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-# CONFIG_SWAP is not set
-# CONFIG_SYN_COOKIES is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_UID16=y
-# CONFIG_USB_ARCH_HAS_XHCI is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-# CONFIG_VFP is not set
-# CONFIG_VLAN_8021Q is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-# CONFIG_WEXT_PRIV is not set
-# CONFIG_WEXT_SPY is not set
-# CONFIG_WIRELESS_EXT is not set
-CONFIG_XZ_DEC=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-/*
- * dlan-usb-extender.dts - Device Tree file for Devolo dLAN USB Extender
- *
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * Licensed under GPLv2
- */
-
-/dts-v1/;
-/include/ "mcs8140.dtsi"
-
-/ {
- model = "Devolo dLAN USB Extender";
- compatible = "devolo,dlan-usb-extender", "moschip,mcs8140", "moschip,mcs814x";
-
- chosen {
- bootargs = "mem=16M console=ttyS0,57600 earlyprintk";
- };
-
- ahb {
- vci {
- eth0: ethernet@40084000 {
- phy = <&phy0>;
- phy-mode = "mii";
-
- phy0: ethernet-phy@0 {
- reg = <8>;
- };
- };
-
- adc {
- sdram: memory@0,0 {
- reg = <0 0 0x1000000>;
- };
-
- nor: flash@7,0 {
-
- partition@0 {
- label = "ArmBoot";
- reg = <0 0x30000>;
- };
- partition@30000 {
- label = "Config1";
- reg = <0x30000 0x10000>;
- };
- partition@40000 {
- label = "Config2";
- reg = <0x40000 0x10000>;
- };
- partition@50000 {
- label = "kernel";
- reg = <0x50000 0x100000>;
- };
- partition@150000 {
- label = "rootfs";
- reg = <0x150000 0x3C0000>;
- };
- partition@50001 {
- label = "linux";
- reg = <0x50000 0x4C0000>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- usb {
- label = "dlan-usb-extender:green:usb";
- gpios = <&gpio 19 0>; // gpio 19 active high
- };
- };
- };
- };
-};
-
+++ /dev/null
-/*
- * mcs8140.dtsi - Device Tree Include file for Moschip MCS8140 family SoC
- *
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * Licensed under GPLv2.
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
- model = "Moschip MCS8140 family SoC";
- compatible = "moschip,mcs8140";
- interrupt-parent = <&intc>;
-
- aliases {
- serial0 = &uart0;
- eth0 = ð0;
- };
-
- cpus {
- cpu@0 {
- compatible = "arm,arm926ejs";
- };
- };
-
- ahb {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- vci {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- eth0: ethernet@40084000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "moschip,nuport-mac";
- reg = <0x40084000 0xd8 // mac
- 0x40080000 0x58>; // dma channels
- interrupts = <4 5 29>; /* tx, rx, link */
- nuport-mac,buffer-shifting;
- nuport-mac,link-activity = <0>;
- };
-
- tso@40088000 {
- reg = <0x40088000 0x1c>;
- interrupts = <7>;
- };
-
- i2s@4008c000 {
- compatible = "moschip,mcs814x-i2s";
- reg = <0x4008c000 0x18>;
- interrupts = <8>;
- };
-
- ipsec@40094000 {
- compatible = "moschip,mcs814x-ipsec";
- reg = <0x40094000 0x1d8>;
- interrupts = <16>;
- };
-
- rng@4009c000 {
- compatible = "moschip,mcs814x-rng";
- reg = <0x4009c000 0x8>;
- };
-
- memc@400a8000 {
- reg = <0x400a8000 0x58>;
- };
-
- list-proc@400ac0c0 {
- reg = <0x400ac0c0 0x38>;
- interrupts = <19 27>; // done, error
- };
-
- gpio: gpio@400d0000 {
- compatible = "moschip,mcs814x-gpio";
- reg = <0x400d0000 0x670>;
- interrupts = <10>;
- #gpio-cells = <2>;
- gpio-controller;
- num-gpios = <20>;
- };
-
- eepio: gpio@400d4000 {
- compatible = "moschip,mcs814x-gpio";
- reg = <0x400d4000 0x470>;
- #gpio-cells = <2>;
- gpio-controller;
- num-gpios = <4>;
- };
-
- uart0: serial@400dc000 {
- compatible = "ns16550";
- reg = <0x400dc000 0x20>;
- clock-frequency = <50000000>;
- reg-shift = <2>;
- interrupts = <21>;
- status = "okay";
- };
-
- intc: interrupt-controller@400e4000 {
- #interrupt-cells = <1>;
- compatible = "moschip,mcs814x-intc";
- interrupt-controller;
- interrupt-parent;
- reg = <0x400e4000 0x48>;
- };
-
- m2m@400e8000 {
- reg = <0x400e8000 0x24>;
- interrupts = <17>;
- };
-
- eth-filters@400ec000 {
- reg = <0x400ec000 0x80>;
- };
-
- timer: timer@400f800c {
- compatible = "moschip,mcs814x-timer";
- interrupts = <0>;
- reg = <0x400f800c 0x8>;
- };
-
- watchdog@400f8014 {
- compatible = "moschip,mcs814x-wdt";
- reg = <0x400f8014 0x8>;
- };
-
- adc {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- // 8 64MB chip-selects
- ranges = <0 0 0x00000000 0x4000000 // sdram
- 1 0 0x04000000 0x4000000 // sdram
- 2 0 0x08000000 0x4000000 // reserved
- 3 0 0x0c000000 0x4000000 // flash/localbus
- 4 0 0x10000000 0x4000000 // flash/localbus
- 5 0 0x14000000 0x4000000 // flash/localbus
- 6 0 0x18000000 0x4000000 // flash/localbus
- 7 0 0x1c000000 0x4000000>; // flash/localbus
-
- sdram: memory@0,0 {
- reg = <0 0 0>;
- };
-
- nor: flash@7,0 {
- reg = <7 0 0x4000000>;
- compatible = "cfi-flash";
- bank-width = <1>; // 8-bit external flash
- #address-cells = <1>;
- #size-cells = <1>;
- };
- };
-
- usb0: ehci@400fc000 {
- compatible = "moschip,mcs814x-ehci", "usb-ehci";
- reg = <0x400fc000 0x74>;
- interrupts = <2>;
- };
-
- usb1: ohci@400fd000 {
- compatible = "moschip,mcs814x-ohci", "ohci-le";
- reg = <0x400fd000 0x74>;
- interrupts = <11>;
- };
-
- usb2: ohci@400fe000 {
- compatible = "moschip,mcs814x-ohci", "ohci-le";
- reg = <0x400fe000 0x74>;
- interrupts = <12>;
- };
-
- usb3: otg@400ff000 {
- compatible = "moschip,msc814x-otg", "usb-otg";
- reg = <0x400ff000 0x1000>;
- interrupts = <13>;
- };
- };
-
- };
-};
+++ /dev/null
-/*
- * rbt-832.dts - Device Tree file for Tigal RBT-832
- *
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * Licensed under GPLv2
- */
-
-/dts-v1/;
-/include/ "mcs8140.dtsi"
-
-/ {
- model = "Tigal RBT-832";
- compatible = "tigal,rbt-832", "moschip,mcs8140", "moschip,mcs814x";
-
- chosen {
- bootargs = "mem=32M console=ttyS0,115200 earlyprintk";
- };
-
- ahb {
- vci {
- eth0: ethernet@40084000 {
- nuport-mac,link-activity = <0x01>;
- phy = <&phy0>;
- phy-mode = "mii";
-
- phy0: ethernet-phy@0 {
- reg = <1>;
- };
- };
-
- adc {
- sdram: memory@0,0 {
- reg = <0 0 0x2000000>;
- };
-
- nor: flash@7,0 {
-
- partition@0 {
- label = "ArmBoot";
- reg = <0 0x40000>;
- };
- partition@30000 {
- label = "Enviroment";
- reg = <0x40000 0x20000>;
- };
- partition@50000 {
- label = "bZimage";
- reg = <0x60000 0x1a0000>;
- };
- partition@150000 {
- label = "UserFS";
- reg = <0x200000 0x600000>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- ethernet {
- label = "rbt-832:red:ethernet";
- gpios = <&gpio 0 0>; // gpio 0 active high
- };
-
- usb0 {
- label = "rbt-832:red:usb0";
- gpios = <&gpio 4 0>; // gpio 4 active high
- };
-
- usb1 {
- label = "rbt-832:red:usb1";
- gpios = <&gpio 3 0>; // gpio 3 active high
- };
-
- usb2 {
- label = "rbt-832:red:usb2";
- gpios = <&gpio 2 0>; // gpio 2 active high
- };
-
- usb3 {
- label = "rbt-832:red:usb3";
- gpios = <&gpio 1 0>; // gpio 1 active high
- };
- };
- };
- };
-};
-
+++ /dev/null
-if ARCH_MCS814X
-
-config MCS8140
- bool
- select CPU_ARM926T
-
-menu "Moschip MCS8140 boards"
-
-config MACH_DLAN_USB_EXT
- bool "Devolo dLAN USB Extender"
- select MCS8140
- select NEW_LEDS
- select LEDS_CLASS
- select LEDS_GPIO
- help
- Machine support for the Devolo dLAN USB Extender
-
-config MACH_RBT_832
- bool "Tigal RBT-832"
- select MCS8140
- select NEW_LEDS
- select LEDS_CLASS
- select LEDS_GPIO
- help
- Machine support for the Tigal RBT-832 board
-
-endmenu
-
-endif
+++ /dev/null
-obj-y += clock.o
-obj-y += common.o
-obj-y += irq.o
-obj-y += timer.o
-obj-y += board-mcs8140-dt.o
+++ /dev/null
- zreladdr-y := 0x00008000
-
-dtb-$(CONFIG_MACH_DLAN_USB_EXT) += dlan-usb-extender.dtb
-dtb-$(CONFIG_MACH_RBT_832) += rbt-832.dtb
+++ /dev/null
-/*
- * Setup code for Moschip MCS8140-based board using Device Tree
- *
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * Licensed under GPLv2.
- */
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/gpio.h>
-#include <linux/irqdomain.h>
-#include <linux/of_platform.h>
-
-#include "common.h"
-
-#include <asm/setup.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-static void __init mcs814x_dt_device_init(void)
-{
- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
- mcs814x_init_machine();
-}
-
-static const char *mcs8140_dt_board_compat[] __initdata = {
- "moschip,mcs8140",
- NULL, /* sentinel */
-};
-
-DT_MACHINE_START(mcs8140_dt, "Moschip MCS8140 board")
- /* Maintainer: Florian Fainelli <florian@openwrt.org> */
- .timer = &mcs814x_timer,
- .map_io = mcs814x_map_io,
- .init_early = mcs814x_clk_init,
- .init_irq = mcs814x_of_irq_init,
- .init_machine = mcs814x_dt_device_init,
- .restart = mcs814x_restart,
- .dt_compat = mcs8140_dt_board_compat,
- .handle_irq = mcs814x_handle_irq,
-MACHINE_END
-
+++ /dev/null
-/*
- * Moschip MCS814x clock routines
- *
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * Licensed under GPLv2
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/export.h>
-#include <linux/spinlock.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/clk.h>
-
-#include <mach/mcs814x.h>
-
-#include "common.h"
-
-#define KHZ 1000
-#define MHZ (KHZ * KHZ)
-
-struct clk_ops {
- unsigned long (*get_rate)(struct clk *clk);
- int (*set_rate)(struct clk *clk, unsigned long rate);
- struct clk *(*get_parent)(struct clk *clk);
- int (*enable)(struct clk *clk, int enable);
-};
-
-struct clk {
- struct clk *parent; /* parent clk */
- unsigned long rate; /* clock rate in Hz */
- unsigned long divider; /* clock divider */
- u32 usecount; /* reference count */
- struct clk_ops *ops; /* clock operation */
- u32 enable_reg; /* clock enable register */
- u32 enable_mask; /* clock enable mask */
-};
-
-static unsigned long clk_divide_parent(struct clk *clk)
-{
- if (clk->parent && clk->divider)
- return clk_get_rate(clk->parent) / clk->divider;
- else
- return 0;
-}
-
-static int clk_local_onoff_enable(struct clk *clk, int enable)
-{
- u32 tmp;
-
- /* no enable_reg means the clock is always enabled */
- if (!clk->enable_reg)
- return 0;
-
- tmp = readl_relaxed(mcs814x_sysdbg_base + clk->enable_reg);
- if (!enable)
- tmp &= ~clk->enable_mask;
- else
- tmp |= clk->enable_mask;
-
- writel_relaxed(tmp, mcs814x_sysdbg_base + clk->enable_reg);
-
- return 0;
-}
-
-static struct clk_ops default_clk_ops = {
- .get_rate = clk_divide_parent,
- .enable = clk_local_onoff_enable,
-};
-
-static DEFINE_SPINLOCK(clocks_lock);
-
-static const unsigned long cpu_freq_table[] = {
- 175000,
- 300000,
- 125000,
- 137500,
- 212500,
- 250000,
- 162500,
- 187500,
- 162500,
- 150000,
- 225000,
- 237500,
- 200000,
- 262500,
- 275000,
- 287500
-};
-
-static struct clk clk_cpu;
-
-/* System clock is fixed at 50Mhz */
-static struct clk clk_sys = {
- .rate = 50 * MHZ,
-};
-
-static struct clk clk_sdram;
-
-static struct clk clk_timer0 = {
- .parent = &clk_sdram,
- .divider = 2,
- .ops = &default_clk_ops,
-};
-
-static struct clk clk_timer1_2 = {
- .parent = &clk_sys,
-};
-
-/* Watchdog clock is system clock / 128 */
-static struct clk clk_wdt = {
- .parent = &clk_sys,
- .divider = 128,
- .ops = &default_clk_ops,
-};
-
-static struct clk clk_emac = {
- .ops = &default_clk_ops,
- .enable_reg = SYSDBG_SYSCTL,
- .enable_mask = SYSCTL_EMAC,
-};
-
-static struct clk clk_ephy = {
- .ops = &default_clk_ops,
- .enable_reg = SYSDBG_PLL_CTL,
- .enable_mask = ~SYSCTL_EPHY, /* active low */
-};
-
-static struct clk clk_cipher = {
- .ops = &default_clk_ops,
- .enable_reg = SYSDBG_SYSCTL,
- .enable_mask = SYSCTL_CIPHER,
-};
-
-#define CLK(_dev, _con, _clk) \
-{ .dev_id = (_dev), .con_id = (_con), .clk = (_clk) },
-
-static struct clk_lookup mcs814x_chip_clks[] = {
- CLK("cpu", NULL, &clk_cpu)
- CLK("sys", NULL, &clk_sys)
- CLK("sdram", NULL, &clk_sdram)
- /* 32-bits timer0 */
- CLK("timer0", NULL, &clk_timer0)
- /* 16-bits timer1 */
- CLK("timer1", NULL, &clk_timer1_2)
- /* 64-bits timer2, same as timer 1 */
- CLK("timer2", NULL, &clk_timer1_2)
- CLK(NULL, "wdt", &clk_wdt)
- CLK(NULL, "emac", &clk_emac)
- CLK(NULL, "ephy", &clk_ephy)
- CLK(NULL, "cipher", &clk_cipher)
-};
-
-static void local_clk_disable(struct clk *clk)
-{
- WARN_ON(!clk->usecount);
-
- if (clk->usecount > 0) {
- clk->usecount--;
-
- if ((clk->usecount == 0) && (clk->ops->enable))
- clk->ops->enable(clk, 0);
-
- if (clk->parent)
- local_clk_disable(clk->parent);
- }
-}
-
-static int local_clk_enable(struct clk *clk)
-{
- int ret = 0;
-
- if (clk->parent)
- ret = local_clk_enable(clk->parent);
-
- if (ret)
- return ret;
-
- if ((clk->usecount == 0) && (clk->ops->enable))
- ret = clk->ops->enable(clk, 1);
-
- if (!ret)
- clk->usecount++;
- else if (clk->parent && clk->parent->ops->enable)
- local_clk_disable(clk->parent);
-
- return ret;
-}
-
-int clk_enable(struct clk *clk)
-{
- int ret;
- unsigned long flags;
-
- spin_lock_irqsave(&clocks_lock, flags);
- ret = local_clk_enable(clk);
- spin_unlock_irqrestore(&clocks_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&clocks_lock, flags);
- local_clk_disable(clk);
- spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- if (unlikely(IS_ERR_OR_NULL(clk)))
- return 0;
-
- if (clk->rate)
- return clk->rate;
-
- if (clk->ops && clk->ops->get_rate)
- return clk->ops->get_rate(clk);
-
- return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
- unsigned long flags;
-
- if (unlikely(IS_ERR_OR_NULL(clk)))
- return NULL;
-
- if (!clk->ops || !clk->ops->get_parent)
- return clk->parent;
-
- spin_lock_irqsave(&clocks_lock, flags);
- clk->parent = clk->ops->get_parent(clk);
- spin_unlock_irqrestore(&clocks_lock, flags);
-
- return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-void __init mcs814x_clk_init(void)
-{
- u32 bs1;
- u8 cpu_freq;
-
- clkdev_add_table(mcs814x_chip_clks, ARRAY_SIZE(mcs814x_chip_clks));
-
- /* read the bootstrap registers to know the exact clocking scheme */
- bs1 = readl_relaxed(mcs814x_sysdbg_base + SYSDBG_BS1);
- cpu_freq = (bs1 >> CPU_FREQ_SHIFT) & CPU_FREQ_MASK;
-
- pr_info("CPU frequency: %lu (kHz)\n", cpu_freq_table[cpu_freq]);
- clk_cpu.rate = cpu_freq * KHZ;
-
- /* read SDRAM frequency */
- if (bs1 & SDRAM_FREQ_BIT)
- clk_sdram.rate = 100 * MHZ;
- else
- clk_sdram.rate = 133 * MHZ;
-
- pr_info("SDRAM frequency: %lu (MHz)\n", clk_sdram.rate / MHZ);
-}
-
+++ /dev/null
-/*
- * arch/arm/mach-mcs814x/common.c
- *
- * Core functions for Moschip MCS814x SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/mcs814x.h>
-#include <mach/cpu.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-
-void __iomem *mcs814x_sysdbg_base;
-
-static struct map_desc mcs814x_io_desc[] __initdata = {
- {
- .virtual = MCS814X_IO_BASE,
- .pfn = __phys_to_pfn(MCS814X_IO_START),
- .length = MCS814X_IO_SIZE,
- .type = MT_DEVICE
- },
-};
-
-struct cpu_mode {
- const char *name;
- int gpio_start;
- int gpio_end;
-};
-
-static const struct cpu_mode cpu_modes[] = {
- {
- .name = "I2S",
- .gpio_start = 4,
- .gpio_end = 8,
- },
- {
- .name = "UART",
- .gpio_start = 4,
- .gpio_end = 9,
- },
- {
- .name = "External MII",
- .gpio_start = 0,
- .gpio_end = 16,
- },
- {
- .name = "Normal",
- .gpio_start = -1,
- .gpio_end = -1,
- },
-};
-
-static void mcs814x_eth_hardware_filter_set(u8 value)
-{
- u32 reg;
-
- reg = readl_relaxed(MCS814X_VIRT_BASE + MCS814X_DBGLED);
- if (value)
- reg |= 0x80;
- else
- reg &= ~0x80;
- writel_relaxed(reg, MCS814X_VIRT_BASE + MCS814X_DBGLED);
-}
-
-static void mcs814x_eth_led_cfg_set(u8 cfg)
-{
- u32 reg;
-
- reg = readl_relaxed(mcs814x_sysdbg_base + SYSDBG_BS2);
- reg &= ~LED_CFG_MASK;
- reg |= cfg;
- writel_relaxed(reg, mcs814x_sysdbg_base + SYSDBG_BS2);
-}
-
-static void mcs814x_eth_buffer_shifting_set(u8 value)
-{
- u8 reg;
-
- reg = readb_relaxed(mcs814x_sysdbg_base + SYSDBG_SYSCTL_MAC);
- if (value)
- reg |= BUF_SHIFT_BIT;
- else
- reg &= ~BUF_SHIFT_BIT;
- writeb_relaxed(reg, mcs814x_sysdbg_base + SYSDBG_SYSCTL_MAC);
-}
-
-static struct of_device_id mcs814x_eth_ids[] __initdata = {
- { .compatible = "moschip,nuport-mac", },
- { /* sentinel */ },
-};
-
-/* Configure platform specific knobs based on ethernet device node
- * properties */
-static void mcs814x_eth_init(void)
-{
- struct device_node *np;
- const unsigned int *intspec;
-
- np = of_find_matching_node(NULL, mcs814x_eth_ids);
- if (!np)
- return;
-
- /* hardware filter must always be enabled */
- mcs814x_eth_hardware_filter_set(1);
-
- intspec = of_get_property(np, "nuport-mac,buffer-shifting", NULL);
- if (!intspec)
- mcs814x_eth_buffer_shifting_set(0);
- else
- mcs814x_eth_buffer_shifting_set(1);
-
- intspec = of_get_property(np, "nuport-mac,link-activity", NULL);
- if (intspec)
- mcs814x_eth_led_cfg_set(be32_to_cpup(intspec));
-
- of_node_put(np);
-}
-
-void __init mcs814x_init_machine(void)
-{
- u32 bs2, cpu_mode;
- int gpio;
-
- bs2 = readl_relaxed(mcs814x_sysdbg_base + SYSDBG_BS2);
- cpu_mode = (bs2 >> CPU_MODE_SHIFT) & CPU_MODE_MASK;
-
- pr_info("CPU mode: %s\n", cpu_modes[cpu_mode].name);
-
- /* request the gpios since the pins are muxed for functionnality */
- for (gpio = cpu_modes[cpu_mode].gpio_start;
- gpio == cpu_modes[cpu_mode].gpio_end; gpio++) {
- if (gpio != -1)
- gpio_request(gpio, cpu_modes[cpu_mode].name);
- }
-
- mcs814x_eth_init();
-}
-
-void __init mcs814x_map_io(void)
-{
- iotable_init(mcs814x_io_desc, ARRAY_SIZE(mcs814x_io_desc));
-
- mcs814x_sysdbg_base = ioremap(MCS814X_IO_START + MCS814X_SYSDBG,
- MCS814X_SYSDBG_SIZE);
- if (!mcs814x_sysdbg_base)
- panic("unable to remap sysdbg base");
-}
-
-void mcs814x_restart(char mode, const char *cmd)
-{
- writel_relaxed(~(1 << 31), mcs814x_sysdbg_base);
-}
+++ /dev/null
-#ifndef __ARCH_MCS814X_COMMON_H
-#define __ARCH_MCS814X_COMMON_H
-
-#include <asm/mach/time.h>
-
-void mcs814x_map_io(void);
-void mcs814x_clk_init(void);
-void mcs814x_of_irq_init(void);
-void mcs814x_init_machine(void);
-void mcs814x_handle_irq(struct pt_regs *regs);
-void mcs814x_restart(char mode, const char *cmd);
-extern struct sys_timer mcs814x_timer;
-extern void __iomem *mcs814x_sysdbg_base;
-
-#endif /* __ARCH_MCS814X_COMMON_H */
+++ /dev/null
-#ifndef __ASM_ARCH_CPU_H__
-#define __ASM_ARCH_CPU_H__
-
-#include <asm/cputype.h>
-
-#define MCS8140_ID 0x41069260 /* ARM926EJ-S */
-#define MCS814X_MASK 0xff0ffff0
-
-#ifdef CONFIG_MCS8140
-/* Moschip MCS8140 is based on an ARM926EJ-S core */
-#define soc_is_mcs8140() ((read_cpuid_id() & MCS814X_MASK) == MCS8140_ID)
-#else
-#define soc_is_mcs8140() (0)
-#endif /* !CONFIG_MCS8140 */
-
-#endif /* __ASM_ARCH_CPU_H__ */
+++ /dev/null
-#include <mach/mcs814x.h>
-
- .macro addruart, rp, rv, tmp
- ldr \rp, =MCS814X_PHYS_BASE
- ldr \rv, =MCS814X_VIRT_BASE
- orr \rp, \rp, #MCS814X_UART
- orr \rv, \rv, #MCS814X_UART
- .endm
-
-#define UART_SHIFT 2
-#include <asm/hardware/debug-8250.S>
+++ /dev/null
-#include <mach/mcs814x.h>
- .macro disable_fiq
- .endm
-
- .macro arch_ret_to_user, tmp1, tmp2
- .endm
+++ /dev/null
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-/* new generic GPIO API */
-#include <asm-generic/gpio.h>
-
-#define gpio_get_value __gpio_get_value
-#define gpio_set_value __gpio_set_value
-#define gpio_cansleep __gpio_cansleep
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- return -EINVAL;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return -EINVAL;
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2003 Artec Design Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include "mcs814x.h"
-
-#endif
-
+++ /dev/null
-/*
- * Copyright (C) 2003 Artec Design Ltd.
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't support ins[lb]/outs[lb]. Make them fault.
- */
-#define __raw_readsb(p, d, l) do { *(int *)0 = 0; } while (0)
-#define __raw_readsl(p, d, l) do { *(int *)0 = 0; } while (0)
-#define __raw_writesb(p, d, l) do { *(int *)0 = 0; } while (0)
-#define __raw_writesl(p, d, l) do { *(int *)0 = 0; } while (0)
-
-#define __io(a) __typesafe_io(a)
-#define __mem_pci(a) (a)
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2003 Artec Design Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#define FIQ_START 0
-
-#define NR_IRQS 32
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2003 Artec Design Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_MCS814X_H
-#define __ASM_ARCH_MCS814X_H
-
-#define MCS814X_IO_BASE 0xF0000000
-#define MCS814X_IO_START 0x40000000
-#define MCS814X_IO_SIZE 0x00100000
-
-/* IRQ controller register offset */
-#define MCS814X_IRQ_ICR 0x00
-#define MCS814X_IRQ_ISR 0x04
-#define MCS814X_IRQ_MASK 0x20
-#define MCS814X_IRQ_STS0 0x40
-
-#define MCS814X_PHYS_BASE 0x40000000
-#define MCS814X_VIRT_BASE MCS814X_IO_BASE
-
-#define MCS814X_UART 0x000DC000
-#define MCS814X_DBGLED 0x000EC000
-#define MCS814X_SYSDBG 0x000F8000
-#define MCS814X_SYSDBG_SIZE 0x50
-
-/* System configuration and bootstrap registers */
-#define SYSDBG_BS1 0x00
-#define CPU_FREQ_SHIFT 27
-#define CPU_FREQ_MASK 0x0F
-#define SDRAM_FREQ_BIT (1 << 22)
-
-#define SYSDBG_BS2 0x04
-#define LED_CFG_MASK 0x03
-#define CPU_MODE_SHIFT 23
-#define CPU_MODE_MASK 0x03
-
-#define SYSDBG_SYSCTL_MAC 0x1d
-#define BUF_SHIFT_BIT (1 << 0)
-
-#define SYSDBG_SYSCTL 0x08
-#define SYSCTL_EMAC (1 << 0)
-#define SYSCTL_EPHY (1 << 0) /* active low */
-#define SYSCTL_CIPHER (1 << 16)
-
-#define SYSDBG_PLL_CTL 0x3C
-
-#endif /* __ASM_ARCH_MCS814X_H */
-
+++ /dev/null
-/*
- * Copyright (C) 2003 Artec Design Ltd.
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define PLAT_PHYS_OFFSET UL(0x00000000)
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2003 Artec Design Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_PARAM_H
-#define __ASM_ARCH_PARAM_H
-
-#define HZ 100
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2003 Artec Design Ltd.
- * Copyright (C) 2012 Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
- cpu_do_idle();
-}
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2003 Artec Design Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-/*
- * Timex specification for MCS814X
- */
-#define CLOCK_TICK_RATE 100
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <linux/serial_reg.h>
-#include <asm/io.h>
-#include <mach/mcs814x.h>
-#include <mach/cpu.h>
-
-#define UART_SHIFT (2)
-
-/* cannot be static because the code will be inlined */
-void __iomem *uart_base;
-
-static inline void putc(int c)
-{
- while (!(__raw_readb(uart_base + (UART_LSR << UART_SHIFT)) & UART_LSR_TEMT));
- __raw_writeb(c, uart_base + (UART_TX << UART_SHIFT));
-}
-
-static inline void flush(void)
-{
-}
-
-static inline void arch_decomp_setup(void)
-{
- if (soc_is_mcs8140())
- uart_base = (void __iomem *)(MCS814X_PHYS_BASE +MCS814X_UART);
-}
-
-#define arch_decomp_wdog()
-
-#endif
+++ /dev/null
-/*
- * Moschip MCS814x generic interrupt controller routines
- *
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * Licensed under the GPLv2
- */
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/irqdomain.h>
-
-#include <asm/exception.h>
-#include <asm/mach/irq.h>
-#include <mach/mcs814x.h>
-
-static void __iomem *mcs814x_intc_base;
-
-static void __init mcs814x_alloc_gc(void __iomem *base, unsigned int irq_start,
- unsigned int num)
-{
- struct irq_chip_generic *gc;
- struct irq_chip_type *ct;
-
- gc = irq_alloc_generic_chip("mcs814x-intc", 1,
- irq_start, base, handle_level_irq);
- if (!gc)
- panic("unable to allocate generic irq chip");
-
- ct = gc->chip_types;
- ct->chip.irq_ack = irq_gc_unmask_enable_reg;
- ct->chip.irq_mask = irq_gc_mask_clr_bit;
- ct->chip.irq_unmask = irq_gc_mask_set_bit;
- ct->regs.mask = MCS814X_IRQ_MASK;
- ct->regs.enable = MCS814X_IRQ_ICR;
-
- irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
- IRQ_NOREQUEST, 0);
-
- /* Clear all interrupts */
- writel_relaxed(0xffffffff, base + MCS814X_IRQ_ICR);
-}
-
-asmlinkage void __exception_irq_entry mcs814x_handle_irq(struct pt_regs *regs)
-{
- u32 status, irq;
-
- do {
- /* read the status register */
- status = __raw_readl(mcs814x_intc_base + MCS814X_IRQ_STS0);
- if (!status)
- break;
-
- irq = ffs(status) - 1;
- status |= (1 << irq);
- /* clear the interrupt */
- __raw_writel(status, mcs814x_intc_base + MCS814X_IRQ_STS0);
- /* call the generic handler */
- handle_IRQ(irq, regs);
-
- } while (1);
-}
-
-static const struct of_device_id mcs814x_intc_ids[] = {
- { .compatible = "moschip,mcs814x-intc" },
- { /* sentinel */ },
-};
-
-void __init mcs814x_of_irq_init(void)
-{
- struct device_node *np;
-
- np = of_find_matching_node(NULL, mcs814x_intc_ids);
- if (!np)
- panic("unable to find compatible intc node in dtb\n");
-
- mcs814x_intc_base = of_iomap(np, 0);
- if (!mcs814x_intc_base)
- panic("unable to map intc cpu registers\n");
-
- irq_domain_add_simple(np, 0);
-
- of_node_put(np);
-
- mcs814x_alloc_gc(mcs814x_intc_base, 0, 32);
-}
-
+++ /dev/null
-/*
- * Moschip MCS814x timer routines
- *
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * Licensed under GPLv2
- */
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#include <asm/mach/time.h>
-#include <mach/mcs814x.h>
-
-/* Timer block registers */
-#define TIMER_VAL 0x00
-#define TIMER_CTL 0x04
-#define TIMER_CTL_EN 0x01
-#define TIMER_CTL_DBG 0x02
-
-static u32 last_reload;
-static u32 timer_correct;
-static u32 clock_rate;
-static u32 timer_reload_value;
-static void __iomem *mcs814x_timer_base;
-
-static inline unsigned long ticks2usecs(u32 x)
-{
- return x / (clock_rate / 1000000);
-}
-
-/*
- * Returns number of ms since last clock interrupt. Note that interrupts
- * will have been disabled by do_gettimeoffset()
- */
-static unsigned long mcs814x_gettimeoffset(void)
-{
- u32 ticks = readl_relaxed(mcs814x_timer_base + TIMER_VAL);
-
- if (ticks < last_reload)
- return ticks2usecs(ticks + (u32)(0xffffffff - last_reload));
- else
- return ticks2usecs(ticks - last_reload);
-}
-
-
-static irqreturn_t mcs814x_timer_interrupt(int irq, void *dev_id)
-{
- u32 count = readl_relaxed(mcs814x_timer_base + TIMER_VAL);
-
- /* take into account delay up to this moment */
- last_reload = count + timer_correct + timer_reload_value;
-
- if (last_reload < timer_reload_value) {
- last_reload = timer_reload_value;
- } else {
- if (timer_correct == 0)
- timer_correct = readl_relaxed(mcs814x_timer_base + TIMER_VAL) - count;
- }
- writel_relaxed(last_reload, mcs814x_timer_base + TIMER_VAL);
-
- timer_tick();
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction mcs814x_timer_irq = {
- .name = "mcs814x-timer",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = mcs814x_timer_interrupt,
-};
-
-static struct of_device_id mcs814x_timer_ids[] = {
- { .compatible = "moschip,mcs814x-timer" },
- { /* sentinel */ },
-};
-
-static void __init mcs814x_of_timer_init(void)
-{
- struct device_node *np;
- const unsigned int *intspec;
-
- np = of_find_matching_node(NULL, mcs814x_timer_ids);
- if (!np)
- panic("unable to find compatible timer node in dtb");
-
- mcs814x_timer_base = of_iomap(np, 0);
- if (!mcs814x_timer_base)
- panic("unable to remap timer cpu registers");
-
- intspec = of_get_property(np, "interrupts", NULL);
- if (!intspec)
- panic("no interrupts property for timer");
-
- mcs814x_timer_irq.irq = be32_to_cpup(intspec);
-}
-
-static void __init mcs814x_timer_init(void)
-{
- struct clk *clk;
-
- clk = clk_get_sys("timer0", NULL);
- if (IS_ERR_OR_NULL(clk))
- panic("unable to get timer0 clock");
-
- clock_rate = clk_get_rate(clk);
-
- mcs814x_of_timer_init();
-
- pr_info("Timer frequency: %d (kHz)\n", clock_rate / 1000);
-
- timer_reload_value = 0xffffffff - (clock_rate / HZ);
-
- /* disable timer */
- writel_relaxed(~TIMER_CTL_EN, mcs814x_timer_base + TIMER_CTL);
- writel_relaxed(timer_reload_value, mcs814x_timer_base + TIMER_VAL);
- last_reload = timer_reload_value;
-
- setup_irq(mcs814x_timer_irq.irq, &mcs814x_timer_irq);
- /* enable timer, stop timer in debug mode */
- writel_relaxed(TIMER_CTL_EN | TIMER_CTL_DBG,
- mcs814x_timer_base + TIMER_CTL);
-}
-
-struct sys_timer mcs814x_timer = {
- .init = mcs814x_timer_init,
- .offset = mcs814x_gettimeoffset,
-};
+++ /dev/null
-/*
- * RNG driver for Moschip MCS814x SoC
- *
- * Copyright 2012 (C), Florian Fainelli <florian@openwrt.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/platform_device.h>
-#include <linux/hw_random.h>
-#include <linux/io.h>
-#include <linux/of.h>
-
-#define STAT 0x00
-#define RND 0x04
-
-struct mcs814x_rng_priv {
- void __iomem *regs;
-};
-
-static int mcs814x_rng_data_read(struct hwrng *rng, u32 *buffer)
-{
- struct mcs814x_rng_priv *priv = (struct mcs814x_rng_priv *)rng->priv;
-
- *buffer = readl_relaxed(priv->regs + RND);
-
- return 4;
-}
-
-static int mcs814x_rng_probe(struct platform_device *pdev)
-{
- struct resource *res;
- struct mcs814x_rng_priv *priv;
- struct hwrng *rng;
- int ret;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -ENODEV;
-
- priv = kzalloc(sizeof(*priv), GFP_KERNEL);
- if (!priv) {
- ret = -ENOMEM;
- goto out;
- }
-
- rng = kzalloc(sizeof(*rng), GFP_KERNEL);
- if (!rng) {
- ret = -ENOMEM;
- goto out_priv;
- }
-
- platform_set_drvdata(pdev, rng);
- rng->priv = (unsigned long)priv;
- rng->name = pdev->name;
- rng->data_read = mcs814x_rng_data_read;
-
- priv->regs = devm_request_and_ioremap(&pdev->dev, res);
- if (!priv->regs) {
- ret = -ENOMEM;
- goto out_rng;
- }
-
- ret = hwrng_register(rng);
- if (ret) {
- dev_err(&pdev->dev, "failed to register hwrng driver\n");
- goto out;
- }
-
- dev_info(&pdev->dev, "registered\n");
-
- return ret;
-
-out_rng:
- platform_set_drvdata(pdev, NULL);
- kfree(rng);
-out_priv:
- kfree(priv);
-out:
- return ret;
-}
-
-static int mcs814x_rng_remove(struct platform_device *pdev)
-{
- struct hwrng *rng = platform_get_drvdata(pdev);
- struct mcs814x_rng_priv *priv = (struct mcs814x_rng_priv *)rng->priv;
-
- hwrng_unregister(rng);
- kfree(priv);
- kfree(rng);
- platform_set_drvdata(pdev, NULL);
-
- return 0;
-}
-
-static const struct of_device_id mcs814x_rng_ids[] = {
- { .compatible = "moschip,mcs814x-rng", },
- { /* sentinel */ },
-};
-
-static struct platform_driver mcs814x_rng_driver = {
- .driver = {
- .name = "mcs814x-rng",
- .owner = THIS_MODULE,
- .of_match_table = mcs814x_rng_ids,
- },
- .probe = mcs814x_rng_probe,
- .remove = __devexit_p(mcs814x_rng_remove),
-};
-
-module_platform_driver(mcs814x_rng_driver);
-
-MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
-MODULE_DESCRIPTION("H/W Random Number Generator (RNG) for Moschip MCS814x");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * Moschip MCS814x GPIO support
- *
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * Licensed under the GPLv2
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-struct mcs814x_gpio_chip {
- void __iomem *regs;
- struct gpio_chip chip;
-};
-
-#define GPIO_PIN 0x00
-#define GPIO_DIR 0x04
-
-#define to_mcs814x_gpio_chip(x) container_of(x, struct mcs814x_gpio_chip, chip)
-
-static int mcs814x_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
- struct mcs814x_gpio_chip *mcs814x = to_mcs814x_gpio_chip(chip);
-
- return readl_relaxed(mcs814x->regs + GPIO_PIN) & (1 << offset);
-}
-
-static void mcs814x_gpio_set(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- struct mcs814x_gpio_chip *mcs814x = to_mcs814x_gpio_chip(chip);
- u32 mask;
-
- mask = readl_relaxed(mcs814x->regs + GPIO_PIN);
- if (value)
- mask |= (1 << offset);
- else
- mask &= ~(1 << offset);
- writel_relaxed(mask, mcs814x->regs + GPIO_PIN);
-}
-
-static int mcs814x_gpio_direction_output(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- struct mcs814x_gpio_chip *mcs814x = to_mcs814x_gpio_chip(chip);
- u32 mask;
-
- mask = readl_relaxed(mcs814x->regs + GPIO_DIR);
- mask &= ~(1 << offset);
- writel_relaxed(mask, mcs814x->regs + GPIO_DIR);
-
- return 0;
-}
-
-static int mcs814x_gpio_direction_input(struct gpio_chip *chip,
- unsigned offset)
-{
- struct mcs814x_gpio_chip *mcs814x = to_mcs814x_gpio_chip(chip);
- u32 mask;
-
- mask = readl_relaxed(mcs814x->regs + GPIO_DIR);
- mask |= (1 << offset);
- writel_relaxed(mask, mcs814x->regs + GPIO_DIR);
-
- return 0;
-}
-
-static int __devinit mcs814x_gpio_probe(struct platform_device *pdev)
-{
- struct resource *res;
- struct mcs814x_gpio_chip *mcs814x_chip;
- int ret;
- const unsigned int *num_gpios;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -ENODEV;
-
- num_gpios = of_get_property(pdev->dev.of_node, "num-gpios", NULL);
- if (!num_gpios)
- dev_err(&pdev->dev, "FIXME: no num-gpios property\n");
-
- mcs814x_chip = kzalloc(sizeof(*mcs814x_chip), GFP_KERNEL);
- if (!mcs814x_chip)
- return -ENOMEM;
-
- mcs814x_chip->regs = devm_request_and_ioremap(&pdev->dev, res);
- if (!mcs814x_chip->regs) {
- ret = -ENOMEM;
- goto out;
- }
-
- platform_set_drvdata(pdev, mcs814x_chip);
-
-#ifdef CONFIG_OF_GPIO
- mcs814x_chip->chip.of_node = pdev->dev.of_node;
-#endif
-
- mcs814x_chip->chip.label = pdev->name;
- mcs814x_chip->chip.get = mcs814x_gpio_get;
- mcs814x_chip->chip.set = mcs814x_gpio_set;
- mcs814x_chip->chip.direction_input = mcs814x_gpio_direction_input;
- mcs814x_chip->chip.direction_output = mcs814x_gpio_direction_output;
- mcs814x_chip->chip.ngpio = be32_to_cpup(num_gpios);
- /* we want dynamic base allocation */
- mcs814x_chip->chip.base = -1;
-
- ret = gpiochip_add(&mcs814x_chip->chip);
- if (ret) {
- dev_err(&pdev->dev, "failed to register gpiochip\n");
- goto out;
- }
-
- return 0;
-
-out:
- platform_set_drvdata(pdev, NULL);
- kfree(mcs814x_chip);
- return ret;
-}
-
-static struct of_device_id mcs814x_gpio_ids[] __devinitdata = {
- { .compatible = "moschip,mcs814x-gpio" },
- { /* sentinel */ },
-};
-
-static struct platform_driver mcs814x_gpio_driver = {
- .driver = {
- .name = "mcs814x-gpio",
- .owner = THIS_MODULE,
- .of_match_table = mcs814x_gpio_ids,
- },
- .probe = mcs814x_gpio_probe,
-};
-
-int __init mcs814x_gpio_init(void)
-{
- return platform_driver_register(&mcs814x_gpio_driver);
-}
-postcore_initcall(mcs814x_gpio_init);
+++ /dev/null
-config NUPORT_ETHERNET_DRIVER
- tristate "MCS8140 Ethernet driver"
- depends on ETHERNET && ARCH_MCS814X
- help
+++ /dev/null
-obj-$(CONFIG_NUPORT_ETHERNET_DRIVER) += mcs8140.o
-
-mcs8140-objs := nuport_mac.o
+++ /dev/null
-/*
- * Moschip MCS8140 Ethernet MAC driver
- *
- * Copyright (C) 2003, Moschip Semiconductors
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * Licensed under GPLv2
- */
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/delay.h>
-#include <linux/ethtool.h>
-#include <linux/mii.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/of_mdio.h>
-#include <linux/of_net.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/phy.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-
-#include <asm/unaligned.h>
-#include <asm/sizes.h>
-
-/* Hardware registers */
-#define MAC_BASE_ADDR ((priv->mac_base))
-
-#define CTRL_REG (MAC_BASE_ADDR)
-#define MII_BUSY (1 << 0)
-#define MII_WRITE (1 << 1)
-#define RX_ENABLE (1 << 2)
-#define TX_ENABLE (1 << 3)
-#define DEFER_CHECK (1 << 5)
-#define STRIP_PAD (1 << 8)
-#define DRTRY_DISABLE (1 << 10)
-#define FULL_DUPLEX (1 << 20)
-#define HBD_DISABLE (1 << 28)
-#define MAC_ADDR_HIGH_REG (MAC_BASE_ADDR + 0x04)
-#define MAC_ADDR_LOW_REG (MAC_BASE_ADDR + 0x08)
-#define MII_ADDR_REG (MAC_BASE_ADDR + 0x14)
-#define MII_ADDR_SHIFT (11)
-#define MII_REG_SHIFT (6)
-#define MII_DATA_REG (MAC_BASE_ADDR + 0x18)
-/* Link interrupt registers */
-#define LINK_INT_CSR (MAC_BASE_ADDR + 0xD0)
-#define LINK_INT_EN (1 << 0)
-#define LINK_PHY_ADDR_SHIFT (1)
-#define LINK_PHY_REG_SHIFT (6)
-#define LINK_BIT_UP_SHIFT (11)
-#define LINK_UP (1 << 16)
-#define LINK_INT_POLL_TIME (MAC_BASE_ADDR + 0xD4)
-#define LINK_POLL_MASK ((1 << 20) - 1)
-
-#define DMA_CHAN_WIDTH 32
-#define DMA_RX_CHAN 0
-#define DMA_TX_CHAN 2
-
-/* Receive DMA registers */
-#define RX_DMA_BASE ((priv->dma_base) + \
- (DMA_CHAN_WIDTH * DMA_RX_CHAN))
-#define RX_BUFFER_ADDR (RX_DMA_BASE + 0x00)
-#define RX_MAX_BYTES (RX_DMA_BASE + 0x04)
-#define RX_ACT_BYTES (RX_DMA_BASE + 0x08)
-#define RX_START_DMA (RX_DMA_BASE + 0x0C)
-#define RX_DMA_ENABLE (1 << 0)
-#define RX_DMA_RESET (1 << 1)
-#define RX_DMA_STATUS_FIFO (1 << 12)
-#define RX_DMA_ENH (RX_DMA_BASE + 0x14)
-#define RX_DMA_INT_ENABLE (1 << 1)
-
-/* Transmit DMA registers */
-#define TX_DMA_BASE ((priv->dma_base) + \
- (DMA_CHAN_WIDTH * DMA_TX_CHAN))
-#define TX_BUFFER_ADDR (TX_DMA_BASE + 0x00)
-#define TX_PKT_BYTES (TX_DMA_BASE + 0x04)
-#define TX_BYTES_SENT (TX_DMA_BASE + 0x08)
-#define TX_START_DMA (TX_DMA_BASE + 0x0C)
-#define TX_DMA_ENABLE (1 << 0)
-#define TX_DMA_START_FRAME (1 << 2)
-#define TX_DMA_END_FRAME (1 << 3)
-#define TX_DMA_PAD_DISABLE (1 << 8)
-#define TX_DMA_CRC_DISABLE (1 << 9)
-#define TX_DMA_FIFO_FULL (1 << 16)
-#define TX_DMA_FIFO_EMPTY (1 << 17)
-#define TX_DMA_STATUS_AVAIL (1 << 18)
-#define TX_DMA_RESET (1 << 24)
-#define TX_DMA_STATUS (TX_DMA_BASE + 0x10)
-#define TX_DMA_ENH (TX_DMA_BASE + 0x14)
-#define TX_DMA_ENH_ENABLE (1 << 0)
-#define TX_DMA_INT_FIFO (1 << 1)
-
-#define RX_ALLOC_SIZE SZ_2K
-#define MAX_ETH_FRAME_SIZE 1536
-#define RX_SKB_TAILROOM 128
-#define RX_SKB_HEADROOM (RX_ALLOC_SIZE - \
- (MAX_ETH_FRAME_SIZE + RX_SKB_TAILROOM) + 0)
-
- /* WDT Late COL Lenght COL Type */
-#define ERROR_FILTER_MASK ((1<<14) | (1<<15) | (1<<16) | (1<<17) | (0<<18) | \
- /* MII Dribbling CRC Len/type Control */\
- (1<<19) | (1<<20) | (1<<21) | (0<<24) | (1<<25) | \
- /* Unsup Missed */\
- (1<<26) | (0<<31))
-#define TX_RING_SIZE 30
-#define RX_RING_SIZE 30
-
-static inline u32 nuport_mac_readl(void __iomem *reg)
-{
- return readl_relaxed(reg);
-}
-
-static inline u8 nuport_mac_readb(void __iomem *reg)
-{
- return readb_relaxed(reg);
-}
-
-static inline void nuport_mac_writel(u32 value, void __iomem *reg)
-{
- writel_relaxed(value, reg);
-}
-
-static inline void nuport_mac_writeb(u8 value, void __iomem *reg)
-{
- writel_relaxed(value, reg);
-}
-
-/* MAC private data */
-struct nuport_mac_priv {
- spinlock_t lock;
-
- void __iomem *mac_base;
- void __iomem *dma_base;
-
- int rx_irq;
- int tx_irq;
- int link_irq;
- struct clk *emac_clk;
- struct clk *ephy_clk;
-
- /* Transmit buffers */
- struct sk_buff *tx_skb[TX_RING_SIZE];
- dma_addr_t tx_addr;
- unsigned int valid_txskb[TX_RING_SIZE];
- unsigned int cur_tx;
- unsigned int dma_tx;
- unsigned int tx_full;
-
- /* Receive buffers */
- struct sk_buff *rx_skb[RX_RING_SIZE];
- dma_addr_t rx_addr;
- unsigned int irq_rxskb[RX_RING_SIZE];
- int pkt_len[RX_RING_SIZE];
- unsigned int cur_rx;
- unsigned int dma_rx;
- unsigned int rx_full;
-
- unsigned int first_pkt;
-
- /* Private data */
- struct napi_struct napi;
- struct net_device *dev;
- struct platform_device *pdev;
- struct mii_bus *mii_bus;
- struct phy_device *phydev;
- struct device_node *phy_node;
- phy_interface_t phy_interface;
- int old_link;
- int old_duplex;
- u32 msg_level;
- unsigned int buffer_shifting_len;
-};
-
-static inline int nuport_mac_mii_busy_wait(struct nuport_mac_priv *priv)
-{
- unsigned long curr;
- unsigned long finish = jiffies + 3 * HZ;
-
- do {
- curr = jiffies;
- if (!(nuport_mac_readl(MII_ADDR_REG) & MII_BUSY))
- return 0;
- cpu_relax();
- } while (!time_after_eq(curr, finish));
-
- return -EBUSY;
-}
-
-/* Read from PHY registers */
-static int nuport_mac_mii_read(struct mii_bus *bus,
- int mii_id, int regnum)
-{
- struct net_device *dev = bus->priv;
- struct nuport_mac_priv *priv = netdev_priv(dev);
- int ret;
- u32 val = 0;
-
- ret = nuport_mac_mii_busy_wait(priv);
- if (ret)
- return ret;
-
- val |= (mii_id << MII_ADDR_SHIFT) | (regnum << MII_REG_SHIFT) | MII_BUSY;
- nuport_mac_writel(val, MII_ADDR_REG);
- ret = nuport_mac_mii_busy_wait(priv);
- if (ret)
- return ret;
-
- return nuport_mac_readl(MII_DATA_REG);
-}
-
-static int nuport_mac_mii_write(struct mii_bus *bus, int mii_id,
- int regnum, u16 value)
-{
- struct net_device *dev = bus->priv;
- struct nuport_mac_priv *priv = netdev_priv(dev);
- int ret;
- u32 val = 0;
-
- ret = nuport_mac_mii_busy_wait(priv);
- if (ret)
- return ret;
-
- val |= (mii_id << MII_ADDR_SHIFT) | (regnum << MII_REG_SHIFT);
- val |= MII_BUSY | MII_WRITE;
- nuport_mac_writel(value, MII_DATA_REG);
- nuport_mac_writel(val, MII_ADDR_REG);
-
- return nuport_mac_mii_busy_wait(priv);
-}
-
-static int nuport_mac_mii_reset(struct mii_bus *bus)
-{
- return 0;
-}
-
-static int nuport_mac_start_tx_dma(struct nuport_mac_priv *priv,
- struct sk_buff *skb)
-{
- u32 reg;
- unsigned int timeout = 2048;
-
- while (timeout--) {
- reg = nuport_mac_readl(TX_START_DMA);
- if (!(reg & TX_DMA_ENABLE)) {
- netdev_dbg(priv->dev, "dma ready\n");
- break;
- }
- cpu_relax();
- }
-
- if (!timeout)
- return -EBUSY;
-
- priv->tx_addr = dma_map_single(&priv->pdev->dev, skb->data,
- skb->len, DMA_TO_DEVICE);
- if (dma_mapping_error(&priv->pdev->dev, priv->tx_addr))
- return -ENOMEM;
-
- /* enable enhanced mode */
- nuport_mac_writel(TX_DMA_ENH_ENABLE, TX_DMA_ENH);
- nuport_mac_writel(priv->tx_addr, TX_BUFFER_ADDR);
- nuport_mac_writel((skb->len) - 1, TX_PKT_BYTES);
- wmb();
- reg = TX_DMA_ENABLE | TX_DMA_START_FRAME | TX_DMA_END_FRAME;
- nuport_mac_writel(reg, TX_START_DMA);
-
- return 0;
-}
-
-static void nuport_mac_reset_tx_dma(struct nuport_mac_priv *priv)
-{
- u32 reg;
-
- reg = nuport_mac_readl(TX_START_DMA);
- reg |= TX_DMA_RESET;
- nuport_mac_writel(reg, TX_START_DMA);
-}
-
-static int nuport_mac_start_rx_dma(struct nuport_mac_priv *priv,
- struct sk_buff *skb)
-{
- u32 reg;
- unsigned int timeout = 2048;
-
- while (timeout--) {
- reg = nuport_mac_readl(RX_START_DMA);
- if (!(reg & RX_DMA_ENABLE)) {
- netdev_dbg(priv->dev, "dma ready\n");
- break;
- }
- cpu_relax();
- }
-
- if (!timeout)
- return -EBUSY;
-
- priv->rx_addr = dma_map_single(&priv->pdev->dev, skb->data,
- RX_ALLOC_SIZE, DMA_FROM_DEVICE);
- if (dma_mapping_error(&priv->pdev->dev, priv->rx_addr))
- return -ENOMEM;
-
- nuport_mac_writel(priv->rx_addr, RX_BUFFER_ADDR);
- wmb();
- nuport_mac_writel(RX_DMA_ENABLE, RX_START_DMA);
-
- return 0;
-}
-
-static void nuport_mac_reset_rx_dma(struct nuport_mac_priv *priv)
-{
- u32 reg;
-
- reg = nuport_mac_readl(RX_START_DMA);
- reg |= RX_DMA_RESET;
- nuport_mac_writel(reg, RX_START_DMA);
-}
-
-/* I suppose this might do something, but I am not sure actually */
-static void nuport_mac_disable_rx_dma(struct nuport_mac_priv *priv)
-{
- u32 reg;
-
- reg = nuport_mac_readl(RX_DMA_ENH);
- reg &= ~RX_DMA_INT_ENABLE;
- nuport_mac_writel(reg, RX_DMA_ENH);
-}
-
-static void nuport_mac_enable_rx_dma(struct nuport_mac_priv *priv)
-{
- u32 reg;
-
- reg = nuport_mac_readl(RX_DMA_ENH);
- reg |= RX_DMA_INT_ENABLE;
- nuport_mac_writel(reg, RX_DMA_ENH);
-}
-
-/* Add packets to the transmit queue */
-static int nuport_mac_start_xmit(struct sk_buff *skb, struct net_device *dev)
-{
- unsigned long flags;
- struct nuport_mac_priv *priv = netdev_priv(dev);
- int ret;
-
- if (netif_queue_stopped(dev)) {
- netdev_warn(dev, "netif queue was stopped, restarting\n");
- netif_start_queue(dev);
- }
-
- spin_lock_irqsave(&priv->lock, flags);
- if (priv->first_pkt) {
- ret = nuport_mac_start_tx_dma(priv, skb);
- if (ret) {
- netif_stop_queue(dev);
- spin_unlock_irqrestore(&priv->lock, flags);
- netdev_err(dev, "transmit path busy\n");
- return NETDEV_TX_BUSY;
- }
- priv->first_pkt = 0;
- }
-
- priv->tx_skb[priv->cur_tx] = skb;
- dev->stats.tx_bytes += skb->len;
- dev->stats.tx_packets++;
- priv->valid_txskb[priv->cur_tx] = 1;
- priv->cur_tx++;
- dev->trans_start = jiffies;
-
- if (priv->cur_tx >= TX_RING_SIZE)
- priv->cur_tx = 0;
-
- spin_unlock_irqrestore(&priv->lock, flags);
-
- if (priv->valid_txskb[priv->cur_tx]) {
- priv->tx_full = 1;
- netdev_err(dev, "stopping queue\n");
- netif_stop_queue(dev);
- }
-
- return NETDEV_TX_OK;
-}
-
-static void nuport_mac_adjust_link(struct net_device *dev)
-{
- struct nuport_mac_priv *priv = netdev_priv(dev);
- struct phy_device *phydev = priv->phydev;
- unsigned int status_changed = 0;
- u32 reg;
-
- BUG_ON(!phydev);
-
- if (priv->old_link != phydev->link) {
- status_changed = 1;
- priv->old_link = phydev->link;
- }
-
- if (phydev->link && (priv->old_duplex != phydev->duplex)) {
- reg = nuport_mac_readl(CTRL_REG);
- if (phydev->duplex == DUPLEX_FULL)
- reg |= DUPLEX_FULL;
- else
- reg &= ~DUPLEX_FULL;
- nuport_mac_writel(reg, CTRL_REG);
-
- status_changed = 1;
- priv->old_duplex = phydev->duplex;
- }
-
- if (!status_changed)
- return;
-
- pr_info("%s: link %s", dev->name, phydev->link ?
- "UP" : "DOWN");
- if (phydev->link) {
- pr_cont(" - %d/%s", phydev->speed,
- phydev->duplex == DUPLEX_FULL ? "full" : "half");
- }
- pr_cont("\n");
-}
-
-static irqreturn_t nuport_mac_link_interrupt(int irq, void *dev_id)
-{
- struct net_device *dev = dev_id;
- struct nuport_mac_priv *priv = netdev_priv(dev);
- u32 reg;
- u8 phy_addr;
- unsigned long flags;
- irqreturn_t ret = IRQ_HANDLED;
-
- spin_lock_irqsave(&priv->lock, flags);
- reg = nuport_mac_readl(LINK_INT_CSR);
- phy_addr = (reg >> LINK_PHY_ADDR_SHIFT) & (PHY_MAX_ADDR - 1);
-
- if (phy_addr != priv->phydev->addr) {
- netdev_err(dev, "spurious PHY irq (phy: %d)\n", phy_addr);
- ret = IRQ_NONE;
- goto out;
- }
-
- priv->phydev->link = (reg & LINK_UP);
- nuport_mac_adjust_link(dev);
-
-out:
- spin_unlock_irqrestore(&priv->lock, flags);
- return ret;
-}
-
-static irqreturn_t nuport_mac_tx_interrupt(int irq, void *dev_id)
-{
- struct net_device *dev = (struct net_device *)dev_id;
- struct nuport_mac_priv *priv = netdev_priv(dev);
- struct sk_buff *skb;
- unsigned long flags;
- int ret;
- u32 reg;
-
- spin_lock_irqsave(&priv->lock, flags);
- /* clear status word available if ready */
- reg = nuport_mac_readl(TX_START_DMA);
- if (reg & TX_DMA_STATUS_AVAIL) {
- nuport_mac_writel(reg, TX_START_DMA);
- reg = nuport_mac_readl(TX_DMA_STATUS);
-
- if (reg & 1)
- dev->stats.tx_errors++;
- } else
- netdev_dbg(dev, "no status word: %08x\n", reg);
-
- skb = priv->tx_skb[priv->dma_tx];
- priv->tx_skb[priv->dma_tx] = NULL;
- priv->valid_txskb[priv->dma_tx] = 0;
- dma_unmap_single(&priv->pdev->dev, priv->rx_addr, skb->len,
- DMA_TO_DEVICE);
- dev_kfree_skb_irq(skb);
-
- priv->dma_tx++;
- if (priv->dma_tx >= TX_RING_SIZE)
- priv->dma_tx = 0;
-
- if (!priv->valid_txskb[priv->dma_tx])
- priv->first_pkt = 1;
- else {
- ret = nuport_mac_start_tx_dma(priv, priv->tx_skb[priv->dma_tx]);
- if (ret)
- netdev_err(dev, "failed to restart TX dma\n");
- }
-
- if (priv->tx_full) {
- netdev_dbg(dev, "restarting transmit queue\n");
- netif_wake_queue(dev);
- priv->tx_full = 0;
- }
-
- spin_unlock_irqrestore(&priv->lock, flags);
-
- return IRQ_HANDLED;
-}
-
-static unsigned int nuport_mac_has_work(struct nuport_mac_priv *priv)
-{
- unsigned int i;
-
- for (i = 0; i < RX_RING_SIZE; i++)
- if (priv->rx_skb[i])
- return 1;
-
- return 0;
-}
-
-static irqreturn_t nuport_mac_rx_interrupt(int irq, void *dev_id)
-{
- struct net_device *dev = (struct net_device *)dev_id;
- struct nuport_mac_priv *priv = netdev_priv(dev);
- unsigned long flags;
- int ret;
-
- spin_lock_irqsave(&priv->lock, flags);
- if (!priv->rx_full) {
- priv->pkt_len[priv->dma_rx] = nuport_mac_readl(RX_ACT_BYTES) - 4;
- priv->irq_rxskb[priv->dma_rx] = 0;
- priv->dma_rx++;
-
- if (priv->dma_rx >= RX_RING_SIZE)
- priv->dma_rx = 0;
- } else
- priv->rx_full = 0;
-
- if (priv->irq_rxskb[priv->dma_rx] == 1) {
- ret = nuport_mac_start_rx_dma(priv, priv->rx_skb[priv->dma_rx]);
- if (ret)
- netdev_err(dev, "failed to start rx dma\n");
- } else {
- priv->rx_full = 1;
- netdev_dbg(dev, "RX ring full\n");
- }
-
- if (likely(nuport_mac_has_work(priv))) {
- /* find a way to disable DMA rx irq */
- nuport_mac_disable_rx_dma(priv);
- napi_schedule(&priv->napi);
- }
- spin_unlock_irqrestore(&priv->lock, flags);
-
- return IRQ_HANDLED;
-}
-
-/* Process received packets in tasklet */
-static int nuport_mac_rx(struct net_device *dev, int limit)
-{
- struct nuport_mac_priv *priv = netdev_priv(dev);
- struct sk_buff *skb;
- int len, status;
- int count = 0;
-
- while (count < limit && !priv->irq_rxskb[priv->cur_rx]) {
- skb = priv->rx_skb[priv->cur_rx];
- len = priv->pkt_len[priv->cur_rx];
-
- /* Remove 2 bytes added by RX buffer shifting */
- len = len - priv->buffer_shifting_len;
- skb->data = skb->data + priv->buffer_shifting_len;
-
- /* Get packet status */
- status = get_unaligned((u32 *) (skb->data + len));
-
- dma_unmap_single(&priv->pdev->dev, priv->rx_addr, skb->len,
- DMA_FROM_DEVICE);
-
- /* packet filter failed */
- if (!(status & (1 << 30))) {
- dev_kfree_skb_irq(skb);
- goto exit;
- }
-
- /* missed frame */
- if (status & (1 << 31)) {
- dev->stats.rx_missed_errors++;
- dev_kfree_skb_irq(skb);
- goto exit;
- }
-
- /* Not ethernet type */
- if ((!(status & (1 << 18))) || (status & ERROR_FILTER_MASK))
- dev->stats.rx_errors++;
-
- if (len > MAX_ETH_FRAME_SIZE) {
- dev_kfree_skb_irq(skb);
- goto exit;
- } else
- skb_put(skb, len);
-
- skb->protocol = eth_type_trans(skb, dev);
- dev->stats.rx_packets++;
-
- if (status & (1 << 29))
- skb->pkt_type = PACKET_OTHERHOST;
- if (status & (1 << 27))
- skb->pkt_type = PACKET_MULTICAST;
- if (status & (1 << 28))
- skb->pkt_type = PACKET_BROADCAST;
-
- skb->ip_summed = CHECKSUM_UNNECESSARY;
-
- /* Pass the received packet to network layer */
- status = netif_receive_skb(skb);
- if (status != NET_RX_DROP)
- dev->stats.rx_bytes += len - 4; /* Without CRC */
- else
- dev->stats.rx_dropped++;
-
- dev->last_rx = jiffies;
-
-exit:
- skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE);
- if (!skb)
- goto out;
-
- skb_reserve(skb, RX_SKB_HEADROOM);
- priv->rx_skb[priv->cur_rx] = skb;
- priv->irq_rxskb[priv->cur_rx] = 1;
- priv->cur_rx++;
-
- if (priv->cur_rx >= RX_RING_SIZE)
- priv->cur_rx = 0;
- count++;
- }
-out:
- return count;
-}
-
-static int nuport_mac_poll(struct napi_struct *napi, int budget)
-{
- struct nuport_mac_priv *priv =
- container_of(napi, struct nuport_mac_priv, napi);
- struct net_device *dev = priv->dev;
- int work_done;
-
- work_done = nuport_mac_rx(dev, budget);
-
- if (work_done < budget) {
- napi_complete(napi);
- nuport_mac_enable_rx_dma(priv);
- }
-
- return work_done;
-}
-
-static void nuport_mac_init_tx_ring(struct nuport_mac_priv *priv)
-{
- int i;
-
- priv->cur_tx = priv->dma_tx = priv->tx_full = 0;
- for (i = 0; i < TX_RING_SIZE; i++) {
- priv->tx_skb[i] = NULL;
- priv->valid_txskb[i] = 0;
- }
- priv->first_pkt = 1;
-}
-
-static int nuport_mac_init_rx_ring(struct net_device *dev)
-{
- struct nuport_mac_priv *priv = netdev_priv(dev);
- struct sk_buff *skb;
- int i;
-
- priv->cur_rx = priv->dma_rx = priv->rx_full = 0;
-
- for (i = 0; i < RX_RING_SIZE; i++) {
- skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE);
- if (!skb)
- return -ENOMEM;
- skb_reserve(skb, RX_SKB_HEADROOM);
- priv->rx_skb[i] = skb;
- priv->irq_rxskb[i] = 1;
- }
-
- return 0;
-}
-
-static void nuport_mac_free_rx_ring(struct nuport_mac_priv *priv)
-{
- int i;
-
- for (i = 0; i < RX_RING_SIZE; i++) {
- if (!priv->rx_skb[i])
- continue;
-
- dev_kfree_skb(priv->rx_skb[i]);
- priv->rx_skb[i] = NULL;
- }
-
- if (priv->rx_addr)
- dma_unmap_single(&priv->pdev->dev, priv->rx_addr, RX_ALLOC_SIZE,
- DMA_TO_DEVICE);
-}
-
-static void nuport_mac_read_mac_address(struct net_device *dev)
-{
- struct nuport_mac_priv *priv = netdev_priv(dev);
- int i;
-
- for (i = 0; i < 4; i++)
- dev->dev_addr[i] = nuport_mac_readb(MAC_ADDR_LOW_REG + i);
- dev->dev_addr[4] = nuport_mac_readb(MAC_ADDR_HIGH_REG);
- dev->dev_addr[5] = nuport_mac_readb(MAC_ADDR_HIGH_REG + 1);
-
- if (!is_valid_ether_addr(dev->dev_addr)) {
- dev_info(&priv->pdev->dev, "using random address\n");
- random_ether_addr(dev->dev_addr);
- }
-}
-
-static int nuport_mac_change_mac_address(struct net_device *dev, void *mac_addr)
-{
- struct sockaddr *addr = mac_addr;
- struct nuport_mac_priv *priv = netdev_priv(dev);
- unsigned long *temp = (unsigned long *)dev->dev_addr;
- u32 high, low;
-
- if (netif_running(dev))
- return -EBUSY;
-
- memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
-
- spin_lock_irq(&priv->lock);
-
- nuport_mac_writel(*temp, MAC_ADDR_LOW_REG);
- temp = (unsigned long *)(dev->dev_addr + 4);
- nuport_mac_writel(*temp, MAC_ADDR_HIGH_REG);
-
- low = nuport_mac_readl(MAC_ADDR_LOW_REG);
- high = nuport_mac_readl(MAC_ADDR_HIGH_REG);
-
- spin_unlock_irq(&priv->lock);
-
- return 0;
-}
-
-static int nuport_mac_open(struct net_device *dev)
-{
- int ret;
- struct nuport_mac_priv *priv = netdev_priv(dev);
- unsigned long flags;
- u32 reg = 0;
-
- ret = clk_enable(priv->emac_clk);
- if (ret) {
- netdev_err(dev, "failed to enable EMAC clock\n");
- return ret;
- }
-
- /* Set MAC into full duplex mode by default */
- reg |= RX_ENABLE | TX_ENABLE;
- reg |= DEFER_CHECK | STRIP_PAD | DRTRY_DISABLE;
- reg |= FULL_DUPLEX | HBD_DISABLE;
- nuport_mac_writel(reg, CTRL_REG);
-
- /* set mac address in hardware in case it was not already */
- nuport_mac_change_mac_address(dev, dev->dev_addr);
-
- ret = request_irq(priv->link_irq, &nuport_mac_link_interrupt,
- 0, dev->name, dev);
- if (ret) {
- netdev_err(dev, "unable to request link interrupt\n");
- goto out_emac_clk;
- }
-
- ret = request_irq(priv->tx_irq, &nuport_mac_tx_interrupt,
- 0, dev->name, dev);
- if (ret) {
- netdev_err(dev, "unable to request rx interrupt\n");
- goto out_link_irq;
- }
-
- /* Enable link interrupt monitoring for our PHY address */
- reg = LINK_INT_EN | (priv->phydev->addr << LINK_PHY_ADDR_SHIFT);
- /* MII_BMSR register to be watched */
- reg |= (1 << LINK_PHY_REG_SHIFT);
- /* BMSR_STATUS to be watched in particular */
- reg |= (2 << LINK_BIT_UP_SHIFT);
-
- spin_lock_irqsave(&priv->lock, flags);
- nuport_mac_writel(reg, LINK_INT_CSR);
- nuport_mac_writel(LINK_POLL_MASK, LINK_INT_POLL_TIME);
- spin_unlock_irqrestore(&priv->lock, flags);
-
- phy_start(priv->phydev);
-
- ret = request_irq(priv->rx_irq, &nuport_mac_rx_interrupt,
- 0, dev->name, dev);
- if (ret) {
- netdev_err(dev, "unable to request tx interrupt\n");
- goto out_tx_irq;
- }
-
- netif_start_queue(dev);
-
- nuport_mac_init_tx_ring(priv);
-
- ret = nuport_mac_init_rx_ring(dev);
- if (ret) {
- netdev_err(dev, "rx ring init failed\n");
- goto out_rx_skb;
- }
-
- nuport_mac_reset_tx_dma(priv);
- nuport_mac_reset_rx_dma(priv);
-
- /* Start RX DMA */
- spin_lock_irqsave(&priv->lock, flags);
- ret = nuport_mac_start_rx_dma(priv, priv->rx_skb[0]);
- spin_unlock_irqrestore(&priv->lock, flags);
-
- napi_enable(&priv->napi);
-
- return ret;
-
-out_rx_skb:
- nuport_mac_free_rx_ring(priv);
- free_irq(priv->rx_irq, dev);
-out_tx_irq:
- free_irq(priv->tx_irq, dev);
-out_link_irq:
- free_irq(priv->link_irq, dev);
-out_emac_clk:
- clk_disable(priv->emac_clk);
- return ret;
-}
-
-static int nuport_mac_close(struct net_device *dev)
-{
- u32 reg;
- struct nuport_mac_priv *priv = netdev_priv(dev);
-
- spin_lock_irq(&priv->lock);
- reg = nuport_mac_readl(CTRL_REG);
- reg &= ~(RX_ENABLE | TX_ENABLE);
- nuport_mac_writel(reg, CTRL_REG);
-
- napi_disable(&priv->napi);
- netif_stop_queue(dev);
-
- free_irq(priv->link_irq, dev);
- /* disable PHY polling */
- nuport_mac_writel(0, LINK_INT_CSR);
- nuport_mac_writel(0, LINK_INT_POLL_TIME);
- phy_stop(priv->phydev);
-
- free_irq(priv->tx_irq, dev);
- free_irq(priv->rx_irq, dev);
- spin_unlock_irq(&priv->lock);
-
- nuport_mac_free_rx_ring(priv);
-
- clk_disable(priv->emac_clk);
-
- return 0;
-}
-
-static void nuport_mac_tx_timeout(struct net_device *dev)
-{
- struct nuport_mac_priv *priv = netdev_priv(dev);
- unsigned int i;
-
- netdev_warn(dev, "transmit timeout, attempting recovery\n");
-
- netdev_info(dev, "TX DMA regs\n");
- for (i = 0; i < DMA_CHAN_WIDTH; i += 4)
- netdev_info(dev, "[%02x]: 0x%08x\n", i, nuport_mac_readl(TX_DMA_BASE + i));
- netdev_info(dev, "RX DMA regs\n");
- for (i = 0; i < DMA_CHAN_WIDTH; i += 4)
- netdev_info(dev, "[%02x]: 0x%08x\n", i, nuport_mac_readl(RX_DMA_BASE + i));
-
- nuport_mac_init_tx_ring(priv);
- nuport_mac_reset_tx_dma(priv);
-
- netif_wake_queue(dev);
-}
-
-static int nuport_mac_mii_probe(struct net_device *dev)
-{
- struct nuport_mac_priv *priv = netdev_priv(dev);
- struct phy_device *phydev = NULL;
- int ret;
-
- ret = clk_enable(priv->ephy_clk);
- if (ret) {
- netdev_err(dev, "unable to enable ePHY clk\n");
- return ret;
- }
-
- phydev = phy_find_first(priv->mii_bus);
- if (!phydev) {
- netdev_err(dev, "no PHYs found\n");
- ret = -ENODEV;
- goto out;
- }
-
- phydev = of_phy_connect(dev, priv->phy_node,
- nuport_mac_adjust_link, 0,
- priv->phy_interface);
- if (IS_ERR(phydev)) {
- netdev_err(dev, "could not attach PHY\n");
- ret = PTR_ERR(phydev);
- goto out;
- }
-
- phydev->supported &= PHY_BASIC_FEATURES;
- phydev->advertising = phydev->supported;
- priv->phydev = phydev;
- priv->old_link = 1;
- priv->old_duplex = DUPLEX_FULL;
-
- dev_info(&priv->pdev->dev, "attached PHY driver [%s] "
- "(mii_bus:phy_addr=%d)\n",
- phydev->drv->name, phydev->addr);
-
- return 0;
-
-out:
- /* disable the Ethernet PHY clock for the moment */
- clk_disable(priv->ephy_clk);
-
- return ret;
-}
-
-static void nuport_mac_ethtool_drvinfo(struct net_device *dev,
- struct ethtool_drvinfo *info)
-{
- strncpy(info->driver, "nuport-mac", sizeof(info->driver));
- strncpy(info->version, "0.1", sizeof(info->version));
- strncpy(info->fw_version, "N/A", sizeof(info->fw_version));
- strncpy(info->bus_info, "internal", sizeof(info->bus_info));
- info->n_stats = 0;
- info->testinfo_len = 0;
- info->regdump_len = 0;
- info->eedump_len = 0;
-}
-
-static int nuport_mac_ethtool_get_settings(struct net_device *dev,
- struct ethtool_cmd *cmd)
-{
- struct nuport_mac_priv *priv = netdev_priv(dev);
-
- if (priv->phydev)
- return phy_ethtool_gset(priv->phydev, cmd);
-
- return -EINVAL;
-}
-
-static int nuport_mac_ethtool_set_settings(struct net_device *dev,
- struct ethtool_cmd *cmd)
-{
- struct nuport_mac_priv *priv = netdev_priv(dev);
-
- if (priv->phydev)
- return phy_ethtool_sset(priv->phydev, cmd);
-
- return -EINVAL;
-}
-
-static void nuport_mac_set_msglevel(struct net_device *dev, u32 msg_level)
-{
- struct nuport_mac_priv *priv = netdev_priv(dev);
-
- priv->msg_level = msg_level;
-}
-
-static u32 nuport_mac_get_msglevel(struct net_device *dev)
-{
- struct nuport_mac_priv *priv = netdev_priv(dev);
-
- return priv->msg_level;
-}
-
-static const struct ethtool_ops nuport_mac_ethtool_ops = {
- .get_drvinfo = nuport_mac_ethtool_drvinfo,
- .get_link = ethtool_op_get_link,
- .get_settings = nuport_mac_ethtool_get_settings,
- .set_settings = nuport_mac_ethtool_set_settings,
- .set_msglevel = nuport_mac_set_msglevel,
- .get_msglevel = nuport_mac_get_msglevel,
-};
-
-static const struct net_device_ops nuport_mac_ops = {
- .ndo_open = nuport_mac_open,
- .ndo_stop = nuport_mac_close,
- .ndo_start_xmit = nuport_mac_start_xmit,
- .ndo_change_mtu = eth_change_mtu,
- .ndo_validate_addr = eth_validate_addr,
- .ndo_set_mac_address = nuport_mac_change_mac_address,
- .ndo_tx_timeout = nuport_mac_tx_timeout,
-};
-
-static int __init nuport_mac_probe(struct platform_device *pdev)
-{
- struct net_device *dev;
- struct nuport_mac_priv *priv = NULL;
- struct resource *regs, *dma;
- int ret = 0;
- int rx_irq, tx_irq, link_irq;
- int i;
- const unsigned int *intspec;
-
- dev = alloc_etherdev(sizeof(struct nuport_mac_priv));
- if (!dev) {
- dev_err(&pdev->dev, "no memory for net_device\n");
- return -ENOMEM;
- }
-
- regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- dma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (!regs || !dma) {
- dev_err(&pdev->dev, "failed to get regs resources\n");
- ret = -ENODEV;
- goto out;
- }
-
- rx_irq = platform_get_irq(pdev, 0);
- tx_irq = platform_get_irq(pdev, 1);
- link_irq = platform_get_irq(pdev, 2);
- if (rx_irq < 0 || tx_irq < 0 || link_irq < 0) {
- ret = -ENODEV;
- goto out;
- }
-
- platform_set_drvdata(pdev, dev);
- SET_NETDEV_DEV(dev, &pdev->dev);
- priv = netdev_priv(dev);
- priv->pdev = pdev;
- priv->dev = dev;
- spin_lock_init(&priv->lock);
-
- intspec = of_get_property(pdev->dev.of_node,
- "nuport-mac,buffer-shifting", NULL);
- if (!intspec)
- priv->buffer_shifting_len = 0;
- else
- priv->buffer_shifting_len = 2;
-
- priv->mac_base = devm_request_and_ioremap(&pdev->dev, regs);
- if (!priv->mac_base) {
- dev_err(&pdev->dev, "failed to remap regs\n");
- ret = -ENOMEM;
- goto out_platform;
- }
-
- priv->dma_base = devm_request_and_ioremap(&pdev->dev, dma);
- if (!priv->dma_base) {
- dev_err(&pdev->dev, "failed to remap dma-regs\n");
- ret = -ENOMEM;
- goto out_platform;
- }
-
- priv->emac_clk = clk_get(&pdev->dev, "emac");
- if (IS_ERR_OR_NULL(priv->emac_clk)) {
- dev_err(&pdev->dev, "failed to get emac clk\n");
- ret = PTR_ERR(priv->emac_clk);
- goto out_platform;
- }
-
- priv->ephy_clk = clk_get(&pdev->dev, "ephy");
- if (IS_ERR_OR_NULL(priv->ephy_clk)) {
- dev_err(&pdev->dev, "failed to get ephy clk\n");
- ret = PTR_ERR(priv->ephy_clk);
- goto out_platform;
- }
-
- priv->link_irq = link_irq;
- priv->rx_irq = rx_irq;
- priv->tx_irq = tx_irq;
- priv->msg_level = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK;
- dev->netdev_ops = &nuport_mac_ops;
- dev->ethtool_ops = &nuport_mac_ethtool_ops;
- dev->watchdog_timeo = HZ;
- dev->flags = IFF_BROADCAST; /* Supports Broadcast */
- dev->tx_queue_len = TX_RING_SIZE / 2;
-
- netif_napi_add(dev, &priv->napi, nuport_mac_poll, 64);
-
- priv->phy_node = of_parse_phandle(pdev->dev.of_node, "phy", 0);
- if (!priv->phy_node) {
- dev_err(&pdev->dev, "no associated PHY\n");
- ret = -ENODEV;
- goto out;
- }
-
- priv->phy_interface = of_get_phy_mode(pdev->dev.of_node);
- if (priv->phy_interface < 0) {
- dev_err(&pdev->dev, "invalid PHY mode\n");
- ret = -EINVAL;
- goto out;
- }
-
- priv->mii_bus = mdiobus_alloc();
- if (!priv->mii_bus) {
- dev_err(&pdev->dev, "mii bus allocation failed\n");
- goto out;
- }
-
- priv->mii_bus->priv = dev;
- priv->mii_bus->read = nuport_mac_mii_read;
- priv->mii_bus->write = nuport_mac_mii_write;
- priv->mii_bus->reset = nuport_mac_mii_reset;
- priv->mii_bus->name = "nuport-mac-mii";
- priv->mii_bus->phy_mask = (1 << 0);
- snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
- priv->mii_bus->irq = kzalloc(PHY_MAX_ADDR * sizeof(int), GFP_KERNEL);
- if (!priv->mii_bus->irq) {
- dev_err(&pdev->dev, "failed to allocate mii_bus irqs\n");
- ret = -ENOMEM;
- goto out_mdio;
- }
-
- /* We support PHY interrupts routed back to the MAC */
- for (i = 0; i < PHY_MAX_ADDR; i++)
- priv->mii_bus->irq[i] = PHY_IGNORE_INTERRUPT;
-
- ret = of_mdiobus_register(priv->mii_bus, pdev->dev.of_node);
- if (ret) {
- dev_err(&pdev->dev, "failed to register mii_bus\n");
- goto out_mdio_irq;
- }
-
- ret = nuport_mac_mii_probe(dev);
- if (ret) {
- dev_err(&pdev->dev, "failed to probe MII bus\n");
- goto out_mdio_unregister;
- }
-
- ret = register_netdev(dev);
- if (ret) {
- dev_err(&pdev->dev, "failed to register net_device\n");
- goto out_mdio_probe;
- }
-
- /* read existing mac address */
- nuport_mac_read_mac_address(dev);
-
- dev_info(&pdev->dev, "registered (MAC: %pM)\n", dev->dev_addr);
-
- return ret;
-
-out_mdio_probe:
- phy_disconnect(priv->phydev);
-out_mdio_unregister:
- mdiobus_unregister(priv->mii_bus);
-out_mdio_irq:
- kfree(priv->mii_bus->irq);
-out_mdio:
- mdiobus_free(priv->mii_bus);
-out_platform:
- platform_set_drvdata(pdev, NULL);
-out:
- clk_put(priv->ephy_clk);
- clk_put(priv->emac_clk);
- free_netdev(dev);
- platform_set_drvdata(pdev, NULL);
- return ret;
-}
-
-static int nuport_mac_remove(struct platform_device *pdev)
-{
- struct net_device *dev = platform_get_drvdata(pdev);
- struct nuport_mac_priv *priv = netdev_priv(dev);
-
- unregister_netdev(dev);
- phy_disconnect(priv->phydev);
- mdiobus_unregister(priv->mii_bus);
- kfree(priv->mii_bus->irq);
- mdiobus_free(priv->mii_bus);
- clk_put(priv->ephy_clk);
- clk_put(priv->emac_clk);
- free_netdev(dev);
-
- platform_set_drvdata(pdev, NULL);
-
- return 0;
-}
-
-static struct of_device_id nuport_eth_ids[] __initdata = {
- {.compatible = "moschip,nuport-mac",},
- { /* sentinel */ },
-};
-
-static struct platform_driver nuport_eth_driver = {
- .driver = {
- .name = "nuport-mac",
- .owner = THIS_MODULE,
- .of_match_table = nuport_eth_ids,
- },
- .probe = nuport_mac_probe,
- .remove = __devexit_p(nuport_mac_remove),
-};
-
-module_platform_driver(nuport_eth_driver);
-
-MODULE_AUTHOR("Moschip Semiconductors Ltd.");
-MODULE_DESCRIPTION("Moschip MCS8140 Ethernet MAC driver");
-MODULE_LICENSE("GPL");
+++ /dev/null
-/*
- * Driver for Moschip MCS814x internal PHY
- *
- * Copyright (c) 2012 Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/errno.h>
-#include <linux/unistd.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/spinlock.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/mii.h>
-#include <linux/ethtool.h>
-#include <linux/phy.h>
-
-MODULE_DESCRIPTION("Moschip MCS814x PHY driver");
-MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
-MODULE_LICENSE("GPL");
-
-/* Nothing special about this PHY but its OUI (O) */
-static struct phy_driver mcs8140_driver = {
- .phy_id = 0,
- .name = "Moschip MCS8140",
- .phy_id_mask = 0x02,
- .features = PHY_BASIC_FEATURES,
- .config_aneg = &genphy_config_aneg,
- .read_status = &genphy_read_status,
- .suspend = genphy_suspend,
- .resume = genphy_resume,
- .driver = { .owner = THIS_MODULE,},
-};
-
-static int __init mcs814x_phy_init(void)
-{
- return phy_driver_register(&mcs8140_driver);
-}
-
-static void __exit mcs814x_phy_exit(void)
-{
- phy_driver_unregister(&mcs8140_driver);
-}
-
-module_init(mcs814x_phy_init);
-module_exit(mcs814x_phy_exit);
-
-static struct mdio_device_id __maybe_unused mcs814x_phy_tbl[] = {
- { 0x0, 0x0ffffff0 },
- { }
-};
-
-MODULE_DEVICE_TABLE(mdio, mcs814x_phy_tbl);
+++ /dev/null
-/*
- * MCS814X EHCI Host Controller Driver
- *
- * Based on "ehci-fsl.c" by Randy Vinson <rvinson@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/platform_device.h>
-#include <linux/of.h>
-
-#define MCS814X_EHCI_CAPS_OFFSET 0x68
-
-static int mcs814x_ehci_init(struct usb_hcd *hcd)
-{
- struct ehci_hcd *ehci = hcd_to_ehci(hcd);
- int retval = 0;
-
- ehci->caps = hcd->regs + MCS814X_EHCI_CAPS_OFFSET;
- ehci->regs = hcd->regs
- + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
- ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
- ehci_reset(ehci);
-
- retval = ehci_init(hcd);
- if (retval) {
- pr_err("ehci_init failed\n");
- return retval;
- }
-
- ehci_port_power(ehci, 0);
-
- return retval;
-}
-
-static const struct hc_driver mcs814x_ehci_hc_driver = {
- .description = hcd_name,
- .product_desc = "MCS814X EHCI Host Controller",
- .hcd_priv_size = sizeof(struct ehci_hcd),
- .irq = ehci_irq,
- .flags = HCD_MEMORY | HCD_USB2,
- .reset = mcs814x_ehci_init,
- .start = ehci_run,
- .stop = ehci_stop,
- .shutdown = ehci_shutdown,
- .urb_enqueue = ehci_urb_enqueue,
- .urb_dequeue = ehci_urb_dequeue,
- .endpoint_disable = ehci_endpoint_disable,
- .get_frame_number = ehci_get_frame,
- .hub_status_data = ehci_hub_status_data,
- .hub_control = ehci_hub_control,
-#if defined(CONFIG_PM)
- .bus_suspend = ehci_bus_suspend,
- .bus_resume = ehci_bus_resume,
-#endif
- .relinquish_port = ehci_relinquish_port,
- .port_handed_over = ehci_port_handed_over,
-
- .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
-};
-
-static int mcs814x_ehci_probe(struct platform_device *pdev)
-{
- struct usb_hcd *hcd;
- const struct hc_driver *driver = &mcs814x_ehci_hc_driver;
- struct resource *res;
- int irq;
- int retval;
-
- if (usb_disabled())
- return -ENODEV;
-
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!res) {
- dev_err(&pdev->dev,
- "Found HC with no IRQ. Check %s setup!\n",
- dev_name(&pdev->dev));
- return -ENODEV;
- }
- irq = res->start;
-
- pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
- pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
-
- hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
- if (!hcd) {
- retval = -ENOMEM;
- goto fail_create_hcd;
- }
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(&pdev->dev,
- "Found HC with no register addr. Check %s setup!\n",
- dev_name(&pdev->dev));
- retval = -ENODEV;
- goto fail_request_resource;
- }
- hcd->rsrc_start = res->start;
- hcd->rsrc_len = resource_size(res);
-
- if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
- driver->description)) {
- dev_dbg(&pdev->dev, "controller already in use\n");
- retval = -EBUSY;
- goto fail_request_resource;
- }
-
- hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len);
- if (hcd->regs == NULL) {
- dev_dbg(&pdev->dev, "error mapping memory\n");
- retval = -EFAULT;
- goto fail_ioremap;
- }
-
- retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (retval)
- goto fail_add_hcd;
-
- dev_info(&pdev->dev, "added MCS814X EHCI driver\n");
-
- return retval;
-
-fail_add_hcd:
- iounmap(hcd->regs);
-fail_ioremap:
- release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-fail_request_resource:
- usb_put_hcd(hcd);
-fail_create_hcd:
- dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
- return retval;
-}
-
-static int mcs814x_ehci_remove(struct platform_device *pdev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
-
- usb_remove_hcd(hcd);
- iounmap(hcd->regs);
- release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
- usb_put_hcd(hcd);
-
- return 0;
-}
-
-MODULE_ALIAS("platform:mcs814x-ehci");
-
-static const struct of_device_id mcs814x_ehci_id[] = {
- { .compatible = "moschip,mcs814x-ehci" },
- { .compatible = "usb-ehci" },
- { /* sentinel */ },
-};
-
-static struct platform_driver mcs814x_ehci_driver = {
- .probe = mcs814x_ehci_probe,
- .remove = mcs814x_ehci_remove,
- .driver = {
- .name = "mcs814x-ehci",
- .of_match_table = mcs814x_ehci_id,
- },
-};
+++ /dev/null
-/*
- * OHCI HCD (Host Controller Driver) for USB.
- *
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
- * (C) Copyright 2002 Hewlett-Packard Company
- *
- * Bus Glue for Moschip MCS814x.
- *
- * Written by Christopher Hoover <ch@hpl.hp.com>
- * Based on fragments of previous driver by Russell King et al.
- *
- * Modified for LH7A404 from ohci-sa1111.c
- * by Durgesh Pattamatta <pattamattad@sharpsec.com>
- *
- * Modified for pxa27x from ohci-lh7a404.c
- * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
- *
- * Modified for mcs814x from ohci-mcs814x.c
- * by Lennert Buytenhek <buytenh@wantstofly.org> 28-2-2006
- * Based on an earlier driver by Ray Lehtiniemi
- *
- * This file is licenced under the GPL.
- */
-
-#include <linux/device.h>
-#include <linux/signal.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-
-static int usb_hcd_mcs814x_probe(const struct hc_driver *driver,
- struct platform_device *pdev)
-{
- int retval;
- struct usb_hcd *hcd;
-
- if (pdev->resource[1].flags != IORESOURCE_IRQ) {
- pr_debug("resource[1] is not IORESOURCE_IRQ");
- return -ENOMEM;
- }
-
- pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
- pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
-
- hcd = usb_create_hcd(driver, &pdev->dev, "mcs814x");
- if (hcd == NULL)
- return -ENOMEM;
-
- hcd->rsrc_start = pdev->resource[0].start;
- hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
- if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
- usb_put_hcd(hcd);
- retval = -EBUSY;
- goto err1;
- }
-
- hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
- if (hcd->regs == NULL) {
- pr_debug("ioremap failed");
- retval = -ENOMEM;
- goto err2;
- }
-
- ohci_hcd_init(hcd_to_ohci(hcd));
-
- retval = usb_add_hcd(hcd, pdev->resource[1].start, IRQF_DISABLED);
- if (retval == 0)
- return retval;
-
- iounmap(hcd->regs);
-err2:
- release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-err1:
- usb_put_hcd(hcd);
-
- return retval;
-}
-
-static void usb_hcd_mcs814x_remove(struct usb_hcd *hcd,
- struct platform_device *pdev)
-{
- usb_remove_hcd(hcd);
- iounmap(hcd->regs);
- release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
- usb_put_hcd(hcd);
-}
-
-static int __devinit ohci_mcs814x_start(struct usb_hcd *hcd)
-{
- struct ohci_hcd *ohci = hcd_to_ohci(hcd);
- int ret;
-
- ret = ohci_init(ohci);
- if (ret < 0)
- return ret;
-
- ret = ohci_run(ohci);
- if (ret < 0) {
- ohci_err(ohci, "can't start %s", hcd->self.bus_name);
- ohci_stop(hcd);
- return ret;
- }
-
- return 0;
-}
-
-static struct hc_driver ohci_mcs814x_hc_driver = {
- .description = hcd_name,
- .product_desc = "MCS814X OHCI",
- .hcd_priv_size = sizeof(struct ohci_hcd),
- .irq = ohci_irq,
- .flags = HCD_USB11 | HCD_MEMORY,
- .start = ohci_mcs814x_start,
- .stop = ohci_stop,
- .shutdown = ohci_shutdown,
- .urb_enqueue = ohci_urb_enqueue,
- .urb_dequeue = ohci_urb_dequeue,
- .endpoint_disable = ohci_endpoint_disable,
- .get_frame_number = ohci_get_frame,
- .hub_status_data = ohci_hub_status_data,
- .hub_control = ohci_hub_control,
-#ifdef CONFIG_PM
- .bus_suspend = ohci_bus_suspend,
- .bus_resume = ohci_bus_resume,
-#endif
- .start_port_reset = ohci_start_port_reset,
-};
-
-extern int usb_disabled(void);
-
-static int ohci_hcd_mcs814x_drv_probe(struct platform_device *pdev)
-{
- int ret;
-
- ret = -ENODEV;
- if (!usb_disabled())
- ret = usb_hcd_mcs814x_probe(&ohci_mcs814x_hc_driver, pdev);
-
- return ret;
-}
-
-static int ohci_hcd_mcs814x_drv_remove(struct platform_device *pdev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
-
- usb_hcd_mcs814x_remove(hcd, pdev);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int ohci_hcd_mcs814x_drv_suspend(struct platform_device *pdev, pm_message_t state)
-{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
- struct ohci_hcd *ohci = hcd_to_ohci(hcd);
-
- if (time_before(jiffies, ohci->next_statechange))
- msleep(5);
- ohci->next_statechange = jiffies;
-
- hcd->state = HC_STATE_SUSPENDED;
-
- return 0;
-}
-
-static int ohci_hcd_mcs814x_drv_resume(struct platform_device *pdev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
- struct ohci_hcd *ohci = hcd_to_ohci(hcd);
- int status;
-
- if (time_before(jiffies, ohci->next_statechange))
- msleep(5);
- ohci->next_statechange = jiffies;
-
- ohci_finish_controller_resume(hcd);
- return 0;
-}
-#endif
-
-static const struct of_device_id mcs814x_ohci_id[] = {
- { .compatible = "moschip,mcs814x-ohci" },
- { .compatible = "ohci-le" },
- { /* sentinel */ },
-};
-
-static struct platform_driver ohci_hcd_mcs814x_driver = {
- .probe = ohci_hcd_mcs814x_drv_probe,
- .remove = ohci_hcd_mcs814x_drv_remove,
- .shutdown = usb_hcd_platform_shutdown,
-#ifdef CONFIG_PM
- .suspend = ohci_hcd_mcs814x_drv_suspend,
- .resume = ohci_hcd_mcs814x_drv_resume,
-#endif
- .driver = {
- .name = "mcs814x-ohci",
- .owner = THIS_MODULE,
- .of_match_table = mcs814x_ohci_id,
- },
-};
-
-MODULE_ALIAS("platform:mcs814x-ohci");
+++ /dev/null
-/*
- * Moschip MCS814x Watchdog driver
- *
- * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/miscdevice.h>
-#include <linux/watchdog.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/of.h>
-
-#define WDT_COUNT 0x00
-#define WDT_CTRL 0x04
-#define WDT_CTRL_EN 0x1
-
-/* watchdog frequency */
-#define WDT_MAX_VALUE (0xffffffff)
-
-struct mcs814x_wdt {
- void __iomem *regs;
- spinlock_t lock;
- struct watchdog_device wdt_dev;
- struct clk *clk;
-};
-
-static int mcs814x_wdt_start(struct watchdog_device *dev)
-{
- struct mcs814x_wdt *wdt = watchdog_get_drvdata(dev);
- u32 reg;
-
- spin_lock(&wdt->lock);
- reg = readl_relaxed(wdt->regs + WDT_CTRL);
- reg |= WDT_CTRL_EN;
- writel_relaxed(reg, wdt->regs + WDT_CTRL);
- spin_unlock(&wdt->lock);
-
- return 0;
-}
-
-static int mcs814x_wdt_stop(struct watchdog_device *dev)
-{
- struct mcs814x_wdt *wdt = watchdog_get_drvdata(dev);
- u32 reg;
-
- spin_lock(&wdt->lock);
- reg = readl_relaxed(wdt->regs + WDT_CTRL);
- reg &= ~WDT_CTRL_EN;
- writel_relaxed(reg, wdt->regs + WDT_CTRL);
- spin_unlock(&wdt->lock);
-
- return 0;
-}
-
-static int mcs814x_wdt_set_timeout(struct watchdog_device *dev,
- unsigned int new_timeout)
-{
- struct mcs814x_wdt *wdt = watchdog_get_drvdata(dev);
-
- spin_lock(&wdt->lock);
- /* watchdog counts upward and rollover (0xfffffff -> 0)
- * triggers the reboot
- */
- writel_relaxed(WDT_MAX_VALUE - (new_timeout * clk_get_rate(wdt->clk)),
- wdt->regs + WDT_COUNT);
- spin_unlock(&wdt->lock);
-
- return 0;
-}
-
-static int mcs814x_wdt_ping(struct watchdog_device *dev)
-{
- /* restart the watchdog */
- mcs814x_wdt_stop(dev);
- mcs814x_wdt_set_timeout(dev, dev->timeout);
- mcs814x_wdt_start(dev);
-
- return 0;
-}
-
-static const struct watchdog_info mcs814x_wdt_ident = {
- .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT |
- WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
- .identity = "MCS814x Watchdog",
-};
-
-static struct watchdog_ops mcs814x_wdt_ops = {
- .owner = THIS_MODULE,
- .start = mcs814x_wdt_start,
- .stop = mcs814x_wdt_stop,
- .set_timeout = mcs814x_wdt_set_timeout,
- .ping = mcs814x_wdt_ping,
-};
-
-static int __devinit mcs814x_wdt_probe(struct platform_device *pdev)
-{
- struct resource *res;
- struct mcs814x_wdt *wdt;
- int ret;
- struct clk *clk;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -ENODEV;
-
- clk = clk_get(NULL, "wdt");
- if (IS_ERR_OR_NULL(clk)) {
- dev_err(&pdev->dev, "failed to get watchdog clock\n");
- return PTR_ERR(clk);
- }
-
- wdt = kzalloc(sizeof(*wdt), GFP_KERNEL);
- if (!wdt) {
- ret = -ENOMEM;
- goto out_clk;
- }
-
- spin_lock_init(&wdt->lock);
- wdt->clk = clk;
- wdt->wdt_dev.info = &mcs814x_wdt_ident;
- wdt->wdt_dev.ops = &mcs814x_wdt_ops;
- wdt->wdt_dev.min_timeout = 1;
- /* approximately 10995 secs */
- wdt->wdt_dev.max_timeout = (WDT_MAX_VALUE / clk_get_rate(clk));
-
- platform_set_drvdata(pdev, wdt);
-
- /* only ioremap registers, because the register is shared */
- wdt->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
- if (!wdt->regs) {
- ret = -ENOMEM;
- goto out;
- }
-
- watchdog_set_drvdata(&wdt->wdt_dev, wdt);
-
- ret = watchdog_register_device(&wdt->wdt_dev);
- if (ret) {
- dev_err(&pdev->dev, "cannot register watchdog: %d\n", ret);
- goto out;
- }
-
- dev_info(&pdev->dev, "registered\n");
- return 0;
-
-out:
- platform_set_drvdata(pdev, NULL);
- kfree(wdt);
-out_clk:
- clk_put(clk);
- return ret;
-}
-
-static int __devexit mcs814x_wdt_remove(struct platform_device *pdev)
-{
- struct mcs814x_wdt *wdt = platform_get_drvdata(pdev);
-
- clk_put(wdt->clk);
- watchdog_unregister_device(&wdt->wdt_dev);
- watchdog_set_drvdata(&wdt->wdt_dev, NULL);
- kfree(wdt);
- platform_set_drvdata(pdev, NULL);
-
- return 0;
-}
-
-static const struct of_device_id mcs814x_wdt_ids[] = {
- { .compatible = "moschip,mcs814x-wdt", },
- { /* sentinel */ },
-};
-
-static struct platform_driver mcs814x_wdt_driver = {
- .driver = {
- .name = "mcs814x-wdt",
- .owner = THIS_MODULE,
- .of_match_table = mcs814x_wdt_ids,
- },
- .probe = mcs814x_wdt_probe,
- .remove = __devexit_p(mcs814x_wdt_remove),
-};
-
-module_platform_driver(mcs814x_wdt_driver);
-
-MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
-MODULE_DESCRIPTION("Moschip MCS814x Watchdog driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-MODULE_ALIAS("platform:mcs814x-wdt");
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-TARGET_DTBS := rbt-832 dlan-usb-extender
-
-LOADADDR:=0x00008000
-
-JFFS2_BLOCKSIZE = 128k
-
-UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage
-
-define Image/Build/MkuImage
- mkimage -A arm -O linux -T kernel -a $(LOADADDR) -C none -e $(LOADADDR) \
- -n 'ARM OpenWrt Linux-$(LINUX_VERSION)' -d $(1) $(2);
-endef
-
-define Image/Build/DTB
- cp $(KDIR)/zImage$(2) $(KDIR)/zImage-$(1);
- cat $(LINUX_DIR)/arch/$(ARCH)/boot/$(1).dtb >> $(KDIR)/zImage$(2)-$(1);
- $(call Image/Build/MkuImage,$(KDIR)/zImage$(2)-$(1),$(KDIR)/uImage$(2)-$(1))
- cp $(KDIR)/uImage$(2)-$(1) $(UIMAGE)$(2)-$(1);
-endef
-
-define Image/Build/Profile/dLAN_USB_Extender
- dd if=$(KDIR)/uImage-dlan-usb-extender bs=1M conv=sync of=$(KDIR)/$(IMG_PREFIX)-dlan-usb-extender-upgrade-$(1).bin
- cat $(KDIR)/root.$(1) >> $(KDIR)/$(IMG_PREFIX)-dlan-usb-extender-upgrade-$(1).bin
- cp $(KDIR)/$(IMG_PREFIX)-dlan-usb-extender-upgrade-$(1).bin $(BIN_DIR)/
-endef
-
-define Image/BuildKernel
- $(foreach dtb,$(TARGET_DTBS),$(call Image/Build/DTB,$(dtb)))
-endef
-
-define Image/Build/Initramfs
- $(foreach dtb,$(TARGET_DTBS),$(call Image/Build/DTB,$(dtb),-initramfs))
-endef
-
-define Image/Build/squashfs
- $(STAGING_DIR_HOST)/bin/padjffs2 $(KDIR)/root.squashfs 128
-endef
-
-define Image/Build
- $(call Image/Build/$(1))
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync
- $(call Image/Build/Profile/$(PROFILE),$(1))
-ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
- $(call Image/Build/Initramfs)
-endif
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-
-define KernelPackage/mcs814x-wdt
- SUBMENU:=$(OTHER_MENU)
- DEPENDS:=@TARGET_mcs814x
- TITLE:=MCS814x watchdog driver
- KCONFIG:=CONFIG_MCS814X_WATCHDOG
- FILES:=$(LINUX_DIR)/drivers/$(WATCHDOG_DIR)/mcs814x_wdt.ko
- AUTOLOAD:=$(call AutoLoad,50,mcs814x_wdt)
-endef
-
-define KernelPackage/mcs814x-wdt/description
- Kernel module for the Moschip MCS814x watchdog timer.
-endef
-
-$(eval $(call KernelPackage,mcs814x-wdt))
+++ /dev/null
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -869,6 +869,21 @@ config ARCH_EXYNOS
- help
- Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
-
-+config ARCH_MCS814X
-+ bool "Moschip MCS814x"
-+ select FIQ
-+ select GENERIC_IRQ_CHIP
-+ select GENERIC_GPIO
-+ select ARCH_REQUIRE_GPIOLIB
-+ select CLKDEV_LOOKUP
-+ select ARCH_USES_GETTIMEOFFSET
-+ select NEED_MACH_MEMORY_H
-+ select USB_ARCH_HAS_OHCI
-+ select USB_ARCH_HAS_EHCI
-+ select MULTI_IRQ_HANDLER
-+ help
-+ Support for Moschip MCS814x SoCs (MCS8140).
-+
- config ARCH_SHARK
- bool "Shark"
- select CPU_SA110
-@@ -1065,6 +1080,8 @@ source "arch/arm/plat-samsung/Kconfig"
- source "arch/arm/plat-s3c24xx/Kconfig"
- source "arch/arm/plat-s5p/Kconfig"
-
-+source "arch/arm/mach-mcs814x/Kconfig"
-+
- source "arch/arm/plat-spear/Kconfig"
-
- if ARCH_S3C2410
---- a/arch/arm/Makefile
-+++ b/arch/arm/Makefile
-@@ -179,6 +179,7 @@ machine-$(CONFIG_ARCH_S3C64XX) := s3c64
- machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
- machine-$(CONFIG_ARCH_S5PC100) := s5pc100
- machine-$(CONFIG_ARCH_S5PV210) := s5pv210
-+machine-$(CONFIG_ARCH_MCS814X) := mcs814x
- machine-$(CONFIG_ARCH_EXYNOS4) := exynos
- machine-$(CONFIG_ARCH_SA1100) := sa1100
- machine-$(CONFIG_ARCH_SHARK) := shark
+++ /dev/null
---- a/drivers/net/ethernet/Kconfig
-+++ b/drivers/net/ethernet/Kconfig
-@@ -176,4 +176,6 @@ source "drivers/net/ethernet/via/Kconfig
- source "drivers/net/ethernet/xilinx/Kconfig"
- source "drivers/net/ethernet/xircom/Kconfig"
-
-+source "drivers/net/ethernet/mcs8140/Kconfig"
-+
- endif # ETHERNET
---- a/drivers/net/ethernet/Makefile
-+++ b/drivers/net/ethernet/Makefile
-@@ -74,3 +74,4 @@ obj-$(CONFIG_NET_VENDOR_TUNDRA) += tundr
- obj-$(CONFIG_NET_VENDOR_VIA) += via/
- obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/
- obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/
-+obj-$(CONFIG_NUPORT_ETHERNET_DRIVER) += mcs8140/
+++ /dev/null
---- a/drivers/usb/host/ehci-hcd.c
-+++ b/drivers/usb/host/ehci-hcd.c
-@@ -1381,6 +1381,11 @@ MODULE_LICENSE ("GPL");
- #define PLATFORM_DRIVER ehci_mv_driver
- #endif
-
-+#ifdef CONFIG_ARCH_MCS814X
-+#include "ehci-mcs814x.c"
-+#define PLATFORM_DRIVER mcs814x_ehci_driver
-+#endif
-+
- #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
- !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
- !defined(XILINX_OF_PLATFORM_DRIVER)
---- a/drivers/usb/host/ohci-hcd.c
-+++ b/drivers/usb/host/ohci-hcd.c
-@@ -1121,6 +1121,12 @@ MODULE_LICENSE ("GPL");
- #define PLATFORM_DRIVER ohci_xls_driver
- #endif
-
-+#ifdef CONFIG_ARCH_MCS814X
-+#include "ohci-mcs814x.c"
-+#define PLATFORM_DRIVER ohci_hcd_mcs814x_driver
-+#endif
-+
-+
- #if !defined(PCI_DRIVER) && \
- !defined(PLATFORM_DRIVER) && \
- !defined(OMAP1_PLATFORM_DRIVER) && \
+++ /dev/null
---- a/drivers/char/hw_random/Kconfig
-+++ b/drivers/char/hw_random/Kconfig
-@@ -188,6 +188,18 @@ config HW_RANDOM_TX4939
-
- If unsure, say Y.
-
-+config HW_RANDOM_MCS814X
-+ tristate "Moschip MCS814x Random Number Generator"
-+ depends on HW_RANDOM && ARCH_MCS814X
-+ ---help---
-+ This driver provides kernel-side support for the Random Number
-+ Generator hardware found on Moschip MCS814x processors.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called mcs814x-rng.
-+
-+ If unusure, say Y.
-+
- config HW_RANDOM_MXC_RNGA
- tristate "Freescale i.MX RNGA Random Number Generator"
- depends on HW_RANDOM && ARCH_HAS_RNGA
---- a/drivers/char/hw_random/Makefile
-+++ b/drivers/char/hw_random/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng
- obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
- obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
- obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
-+obj-$(CONFIG_HW_RANDOM_MCS814X) += mcs814x-rng.o
- obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o
- obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o
- obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o
+++ /dev/null
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -343,6 +343,12 @@ config IMX2_WDT
- To compile this driver as a module, choose M here: the
- module will be called imx2_wdt.
-
-+config MCS814X_WATCHDOG
-+ tristate "Moschip MCS814x watchdog"
-+ depends on WATCHDOG_CORE && ARCH_MCS814X
-+ help
-+ Support for the Moschip MCS814x SoCs on-chip watchdog timer.
-+
- # AVR32 Architecture
-
- config AT32AP700X_WDT
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -53,6 +53,7 @@ obj-$(CONFIG_STMP3XXX_WATCHDOG) += stmp3
- obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
- obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o
- obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o
-+obj-$(CONFIG_MCS814X_WATCHDOG) += mcs814x_wdt.o
-
- # AVR32 Architecture
- obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
+++ /dev/null
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -450,6 +450,12 @@ config GPIO_MC33880
- SPI driver for Freescale MC33880 high-side/low-side switch.
- This provides GPIO interface supporting inputs and outputs.
-
-+config GPIO_MCS814X
-+ tristate "Moschip MCS814x GPIO support"
-+ depends on ARCH_MCS814X
-+ help
-+ GPIO driver for Moschip MCS814x SoC gpio controllers.
-+
- config GPIO_74X164
- tristate "74x164 serial-in/parallel-out 8-bits shift register"
- depends on SPI_MASTER
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -26,6 +26,7 @@ obj-$(CONFIG_GPIO_MAX7300) += gpio-max73
- obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o
- obj-$(CONFIG_GPIO_MAX732X) += gpio-max732x.o
- obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o
-+obj-$(CONFIG_GPIO_MCS814X) += gpio-mcs814x.o
- obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o
- obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o
- obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o
+++ /dev/null
-The old logic assumes CMDLINE_FROM_BOOTLOADER vs. CMDLINE_FORCE and
-ignores CMDLINE_EXTEND. Here's the old logic:
-
-- CONFIG_CMDLINE_FORCE=true
- CONFIG_CMDLINE
-- dt bootargs=non-empty:
- dt bootargs
-- dt bootargs=empty, @data is non-empty string
- @data is left unchanged
-- dt bootargs=empty, @data is empty string
- CONFIG_CMDLINE (or "" if that's not defined)
-
-The new logic is now documented in of_fdt.h and is copied here for
-reference:
-
-- CONFIG_CMDLINE_FORCE=true
- CONFIG_CMDLINE
-- CONFIG_CMDLINE_EXTEND=true, @data is non-empty string
- @data + dt bootargs (even if dt bootargs are empty)
-- CONFIG_CMDLINE_EXTEND=true, @data is empty string
- CONFIG_CMDLINE + dt bootargs (even if dt bootargs are empty)
-- CMDLINE_FROM_BOOTLOADER=true, dt bootargs=non-empty:
- dt bootargs
-- CMDLINE_FROM_BOOTLOADER=true, dt bootargs=empty, @data is non-empty string
- @data is left unchanged
-- CMDLINE_FROM_BOOTLOADER=true, dt bootargs=empty, @data is empty string
- CONFIG_CMDLINE (or "" if that's not defined)
-
-Signed-off-by: Doug Anderson <diand...@chromium.org>
-CC: devicetree-discuss@lists.ozlabs.org
-CC: Grant Likely <grant.lik...@secretlab.ca>
-CC: Benjamin Herrenschmidt <b...@kernel.crashing.org>
-CC: Rob Herring <rob.herr...@calxeda.com>
----
-
---- a/drivers/of/fdt.c
-+++ b/drivers/of/fdt.c
-@@ -663,6 +663,29 @@ int __init early_init_dt_scan_memory(uns
- return 0;
- }
-
-+/*
-+ * Convert configs to something easy to use in C code
-+ */
-+#if defined(CONFIG_CMDLINE_FORCE)
-+static const int overwrite_incoming_cmdline = 1;
-+static const int read_dt_cmdline;
-+static const int concat_cmdline;
-+#elif defined(CONFIG_CMDLINE_EXTEND)
-+static const int overwrite_incoming_cmdline;
-+static const int read_dt_cmdline = 1;
-+static const int concat_cmdline = 1;
-+#else /* CMDLINE_FROM_BOOTLOADER */
-+static const int overwrite_incoming_cmdline;
-+static const int read_dt_cmdline = 1;
-+static const int concat_cmdline;
-+#endif
-+
-+#ifdef CONFIG_CMDLINE
-+static const char *config_cmdline = CONFIG_CMDLINE;
-+#else
-+static const char *config_cmdline = "";
-+#endif
-+
- int __init early_init_dt_scan_chosen(unsigned long node, const char *uname,
- int depth, void *data)
- {
-@@ -677,22 +700,26 @@ int __init early_init_dt_scan_chosen(uns
-
- early_init_dt_check_for_initrd(node);
-
-- /* Retrieve command line */
-- p = of_get_flat_dt_prop(node, "bootargs", &l);
-- if (p != NULL && l > 0)
-- strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
--
-- /*
-- * CONFIG_CMDLINE is meant to be a default in case nothing else
-- * managed to set the command line, unless CONFIG_CMDLINE_FORCE
-- * is set in which case we override whatever was found earlier.
-- */
--#ifdef CONFIG_CMDLINE
--#ifndef CONFIG_CMDLINE_FORCE
-- if (!((char *)data)[0])
--#endif
-- strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
--#endif /* CONFIG_CMDLINE */
-+ /* Put CONFIG_CMDLINE in if forced or if data had nothing in it to start */
-+ if (overwrite_incoming_cmdline || !((char *)data)[0])
-+ strlcpy(data, config_cmdline, COMMAND_LINE_SIZE);
-+
-+ /* Retrieve command line unless forcing */
-+ if (read_dt_cmdline) {
-+ p = of_get_flat_dt_prop(node, "bootargs", &l);
-+ if (p != NULL && l > 0) {
-+ if (concat_cmdline) {
-+ strlcat(data, " ", COMMAND_LINE_SIZE);
-+ strlcat(data, p, min_t(int, (int)l,
-+ COMMAND_LINE_SIZE));
-+ } else
-+ strlcpy(data, p, min_t(int, (int)l,
-+ COMMAND_LINE_SIZE));
-+ }
-+ }
-+
-+ pr_debug("Command line is: %s\n", (char*)data);
-+
-
- pr_debug("Command line is: %s\n", (char*)data);
-
---- a/include/linux/of_fdt.h
-+++ b/include/linux/of_fdt.h
-@@ -91,6 +91,27 @@ extern int of_flat_dt_is_compatible(unsi
- extern int of_flat_dt_match(unsigned long node, const char *const *matches);
- extern unsigned long of_get_flat_dt_root(void);
-
-+/*
-+ * early_init_dt_scan_chosen - scan the device tree for ramdisk and bootargs
-+ *
-+ * The boot arguments will be placed into the memory pointed to by @data.
-+ * That memory should be COMMAND_LINE_SIZE big and initialized to be a valid
-+ * (possibly empty) string. Logic for what will be in @data after this
-+ * function finishes:
-+ *
-+ * - CONFIG_CMDLINE_FORCE=true
-+ * CONFIG_CMDLINE
-+ * - CONFIG_CMDLINE_EXTEND=true, @data is non-empty string
-+ * @data + dt bootargs (even if dt bootargs are empty)
-+ * - CONFIG_CMDLINE_EXTEND=true, @data is empty string
-+ * CONFIG_CMDLINE + dt bootargs (even if dt bootargs are empty)
-+ * - CMDLINE_FROM_BOOTLOADER=true, dt bootargs=non-empty:
-+ * dt bootargs
-+ * - CMDLINE_FROM_BOOTLOADER=true, dt bootargs=empty, @data is non-empty string
-+ * @data is left unchanged
-+ * - CMDLINE_FROM_BOOTLOADER=true, dt bootargs=empty, @data is empty string
-+ * CONFIG_CMDLINE (or "" if that's not defined)
-+ */
- extern int early_init_dt_scan_chosen(unsigned long node, const char *uname,
- int depth, void *data);
- extern void early_init_dt_check_for_initrd(unsigned long node);
+++ /dev/null
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -135,6 +135,10 @@ config MICREL_PHY
- ---help---
- Currently has a driver for the KSZ8041
-
-+config MCS814X_PHY
-+ tristate "Driver for the Moschip MCS814x internal PHY"
-+ depends on ARCH_MCS814X
-+
- config FIXED_PHY
- bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
- depends on PHYLIB=y
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -38,3 +38,4 @@ obj-$(CONFIG_STE10XP) += ste10Xp.o
- obj-$(CONFIG_MICREL_PHY) += micrel.o
- obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
- obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
-+obj-$(CONFIG_MCS814X_PHY) += mcs814x.o
+++ /dev/null
---- a/drivers/mtd/chips/cfi_cmdset_0002.c
-+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
-@@ -39,9 +39,9 @@
- #include <linux/mtd/xip.h>
-
- #define AMD_BOOTLOC_BUG
--#define FORCE_WORD_WRITE 0
-+#define FORCE_WORD_WRITE 1
-
--#define MAX_WORD_RETRIES 3
-+#define MAX_WORD_RETRIES 10
-
- #define SST49LF004B 0x0060
- #define SST49LF040B 0x0050
+++ /dev/null
---- a/drivers/usb/host/ohci.h
-+++ b/drivers/usb/host/ohci.h
-@@ -114,7 +114,7 @@ struct td {
- /* PSW is only for ISO. Only 1 PSW entry is used, but on
- * big-endian PPC hardware that's the second entry.
- */
--#define MAXPSW 2
-+#define MAXPSW 8
- __hc16 hwPSW [MAXPSW];
-
- /* rest are purely for the driver's use */
---- a/drivers/usb/host/ohci-hcd.c
-+++ b/drivers/usb/host/ohci-hcd.c
-@@ -497,6 +497,7 @@ static int ohci_init (struct ohci_hcd *o
- {
- int ret;
- struct usb_hcd *hcd = ohci_to_hcd(ohci);
-+ u32 hcca_area;
-
- if (distrust_firmware)
- ohci->flags |= OHCI_QUIRK_HUB_POWER;
-@@ -550,11 +551,13 @@ static int ohci_init (struct ohci_hcd *o
- if (ohci->hcca)
- return 0;
-
-- ohci->hcca = dma_alloc_coherent (hcd->self.controller,
-- sizeof *ohci->hcca, &ohci->hcca_dma, 0);
-+ hcca_area = ohci_readl(ohci, &ohci->regs->hcca);
-+ ohci->hcca = ioremap_nocache(hcca_area, sizeof *ohci->hcca);
- if (!ohci->hcca)
- return -ENOMEM;
-
-+ ohci->hcca_dma = hcca_area;
-+
- if ((ret = ohci_mem_init (ohci)) < 0)
- ohci_stop (hcd);
- else {
-@@ -572,6 +575,7 @@ static int ohci_init (struct ohci_hcd *o
- */
- static int ohci_run (struct ohci_hcd *ohci)
- {
-+ int i = 0;
- u32 mask, val;
- int first = ohci->fminterval == 0;
- struct usb_hcd *hcd = ohci_to_hcd(ohci);
-@@ -622,6 +626,8 @@ static int ohci_run (struct ohci_hcd *oh
- msleep(val);
-
- memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
-+ for (i = 0; i < NUM_INTS; i++)
-+ ohci->hcca->int_table[i] = 0;
-
- /* 2msec timelimit here means no irqs/preempt */
- spin_lock_irq (&ohci->lock);
-@@ -909,9 +915,6 @@ static void ohci_stop (struct usb_hcd *h
- remove_debug_files (ohci);
- ohci_mem_cleanup (ohci);
- if (ohci->hcca) {
-- dma_free_coherent (hcd->self.controller,
-- sizeof *ohci->hcca,
-- ohci->hcca, ohci->hcca_dma);
- ohci->hcca = NULL;
- ohci->hcca_dma = 0;
- }
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Generic
- NAME:=Generic profile
-endef
-
-define Profile/Generic/Description
- Default profile for Moschip MCS814x targets
-endef
-$(eval $(call Profile,Generic))
-
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/dLAN_USB_Extender
- NAME:=Devolo dLAN USB Extender
- PACKAGES:=hpavcfg foot kmod-usb-serial kmod-usb-serial-ftdi \
- wmbus-repeater
-endef
-
-define Profile/dLAN_USB_Extender/Description
- Package set specifically tuned for the Devolo dLAN USB Extender device.
-endef
-$(eval $(call Profile,dLAN_USB_Extender))
-
+++ /dev/null
-#
-# Copyright (C) 2009-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=powerpc
-BOARD:=mpc52xx
-BOARDNAME:=Freescale MPC52xx
-CPU_TYPE:=603e
-FEATURES:=targz ext4
-
-LINUX_VERSION:=3.8.13
-
-include $(INCLUDE_DIR)/target.mk
-
-define Target/Description
- Build images for the Freescale MPC52xx based boards.
-endef
-
-KERNELNAME:="zImage"
-
-$(eval $(call BuildTarget))
+++ /dev/null
-::sysinit:/etc/init.d/rcS S boot
-::shutdown:/etc/init.d/rcS K shutdown
-ttyPSC0::askfirst:/bin/ash --login
+++ /dev/null
-# CONFIG_40x is not set
-# CONFIG_44x is not set
-CONFIG_6xx=y
-# CONFIG_ADVANCED_OPTIONS is not set
-# CONFIG_ALTIVEC is not set
-# CONFIG_AMIGAONE is not set
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_ILOG2_U32=y
-CONFIG_ARCH_HAS_WALK_MEMORY=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_MSI=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-# CONFIG_ARPD is not set
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BOOTX_TEXT is not set
-CONFIG_BOUNCE=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyPSC0,115200"
-CONFIG_CMDLINE_BOOL=y
-CONFIG_COMPAT_BRK=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_RNG2=y
-# CONFIG_CRYPTO_SHA1_PPC is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_DEFAULT_UIMAGE is not set
-CONFIG_DEVKMEM=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_OF=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-# CONFIG_E200 is not set
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EMBEDDED6xx is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_EPAPR_BOOT is not set
-# CONFIG_EPOLL is not set
-CONFIG_EXT4_FS=y
-CONFIG_FEC_MPC52xx=y
-CONFIG_FEC_MPC52xx_MDIO=y
-CONFIG_FREEZER=y
-# CONFIG_FSL_ULI1575 is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_NVRAM=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-# CONFIG_GENERIC_TBSYNC is not set
-CONFIG_GENERIC_TIME_VSYSCALL_OLD=y
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
-# CONFIG_GE_FPGA is not set
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_MPC5200=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAS_RAPIDIO is not set
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-# CONFIG_HVC_RTAS is not set
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IOMMU_HELPER is not set
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_IPIC is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_MROUTE is not set
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_RARP is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_ISA_DMA_API=y
-CONFIG_JBD2=y
-CONFIG_KERNEL_START=0xc0000000
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LOWMEM_SIZE=0x30000000
-CONFIG_LXT_PHY=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIGRATION=y
-# CONFIG_MII is not set
-# CONFIG_MMIO_NVRAM is not set
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MPC5200_WDT=y
-# CONFIG_MPIC is not set
-# CONFIG_MPIC_U3_HT_IRQS is not set
-# CONFIG_MPIC_WEIRD is not set
-# CONFIG_MTD is not set
-# CONFIG_NEED_DMA_MAP_STATE is not set
-# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-# CONFIG_NEW_LEDS is not set
-# CONFIG_NONSTATIC_KERNEL is not set
-CONFIG_NR_IRQS=512
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xc0000000
-CONFIG_PATA_MPC52xx=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PHYLIB=y
-CONFIG_PHYSICAL_START=0x00000000
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_PPC=y
-CONFIG_PPC32=y
-# CONFIG_PPC64 is not set
-# CONFIG_PPC_82xx is not set
-# CONFIG_PPC_83xx is not set
-# CONFIG_PPC_85xx is not set
-# CONFIG_PPC_86xx is not set
-# CONFIG_PPC_8xx is not set
-# CONFIG_PPC_970_NAP is not set
-CONFIG_PPC_BESTCOMM=y
-CONFIG_PPC_BESTCOMM_ATA=y
-CONFIG_PPC_BESTCOMM_FEC=y
-CONFIG_PPC_BOOK3S=y
-CONFIG_PPC_BOOK3S_32=y
-# CONFIG_PPC_CELL is not set
-# CONFIG_PPC_CELL_NATIVE is not set
-# CONFIG_PPC_CHRP is not set
-CONFIG_PPC_CLOCK=y
-# CONFIG_PPC_DCR_MMIO is not set
-# CONFIG_PPC_DCR_NATIVE is not set
-# CONFIG_PPC_DOORBELL is not set
-# CONFIG_PPC_EARLY_DEBUG is not set
-CONFIG_PPC_EFIKA=y
-# CONFIG_PPC_EPAPR_HV_PIC is not set
-CONFIG_PPC_FPU=y
-CONFIG_PPC_HAVE_PMU_SUPPORT=y
-# CONFIG_PPC_I8259 is not set
-# CONFIG_PPC_ICP_HV is not set
-# CONFIG_PPC_ICP_NATIVE is not set
-# CONFIG_PPC_ICS_RTAS is not set
-# CONFIG_PPC_INDIRECT_PCI is not set
-CONFIG_PPC_LIB_RHEAP=y
-# CONFIG_PPC_LITE5200 is not set
-# CONFIG_PPC_MEDIA5200 is not set
-# CONFIG_PPC_MM_SLICES is not set
-# CONFIG_PPC_MPC106 is not set
-# CONFIG_PPC_MPC512x is not set
-# CONFIG_PPC_MPC5200_BUGFIX is not set
-# CONFIG_PPC_MPC5200_LPBFIFO is not set
-# CONFIG_PPC_MPC5200_SIMPLE is not set
-CONFIG_PPC_MPC52xx=y
-CONFIG_PPC_NATIVE=y
-CONFIG_PPC_OF=y
-CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
-# CONFIG_PPC_P7_NAP is not set
-CONFIG_PPC_PCI_CHOICE=y
-# CONFIG_PPC_PMAC is not set
-CONFIG_PPC_RTAS=y
-# CONFIG_PPC_RTAS_DAEMON is not set
-CONFIG_PPC_STD_MMU=y
-CONFIG_PPC_STD_MMU_32=y
-# CONFIG_PPC_UDBG_16550 is not set
-CONFIG_PPC_WERROR=y
-# CONFIG_PPC_WSP is not set
-# CONFIG_PPC_XICS is not set
-# CONFIG_PQ2ADS is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_PROC_PAGE_MONITOR=y
-# CONFIG_RCU_STALL_COMMON is not set
-# CONFIG_RTAS_ERROR_LOGGING is not set
-CONFIG_RTAS_PROC=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_SCHED_HRTICK=y
-CONFIG_SCSI=y
-CONFIG_SECCOMP=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_MPC52xx=y
-CONFIG_SERIAL_MPC52xx_CONSOLE=y
-CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD=115200
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOCK_DIAG=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_SQUASHFS is not set
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_SWIOTLB is not set
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_TASK_SIZE=0xc0000000
-# CONFIG_TAU is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_UDBG_RTAS_CONSOLE is not set
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_VLAN_8021Q is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-# CONFIG_WATCHDOG_RTAS is not set
-CONFIG_WORD_SIZE=32
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_POWERPC=y
+++ /dev/null
-# CONFIG_40x is not set
-# CONFIG_44x is not set
-CONFIG_6xx=y
-# CONFIG_ADVANCED_OPTIONS is not set
-# CONFIG_ALTIVEC is not set
-# CONFIG_AMIGAONE is not set
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_ILOG2_U32=y
-CONFIG_ARCH_HAS_WALK_MEMORY=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
-CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_MSI=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-# CONFIG_ARPD is not set
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BOOTX_TEXT is not set
-CONFIG_BOUNCE=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyPSC0,115200"
-CONFIG_CMDLINE_BOOL=y
-CONFIG_COMPAT_BRK=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_DEFAULT_UIMAGE is not set
-CONFIG_DEVKMEM=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-# CONFIG_E200 is not set
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EMBEDDED6xx is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_EPAPR_BOOT is not set
-# CONFIG_EPOLL is not set
-CONFIG_EXT4_FS=y
-CONFIG_FEC_MPC52xx=y
-CONFIG_FEC_MPC52xx_MDIO=y
-CONFIG_FREEZER=y
-# CONFIG_FSL_ULI1575 is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_NVRAM=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-# CONFIG_GENERIC_TBSYNC is not set
-CONFIG_GENERIC_TIME_VSYSCALL_OLD=y
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
-# CONFIG_GE_FPGA is not set
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_MPC5200=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAS_RAPIDIO is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-# CONFIG_HVC_RTAS is not set
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IOMMU_HELPER is not set
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_IPIC is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_MROUTE is not set
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_RARP is not set
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_ISA_DMA_API=y
-CONFIG_JBD2=y
-CONFIG_KERNEL_START=0xc0000000
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LOWMEM_SIZE=0x30000000
-CONFIG_LXT_PHY=y
-CONFIG_MAX_ACTIVE_REGIONS=32
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIGRATION=y
-# CONFIG_MII is not set
-# CONFIG_MMIO_NVRAM is not set
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MPC5200_WDT=y
-# CONFIG_MPIC is not set
-# CONFIG_MPIC_U3_HT_IRQS is not set
-# CONFIG_MPIC_WEIRD is not set
-# CONFIG_MTD is not set
-# CONFIG_NEED_DMA_MAP_STATE is not set
-# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-# CONFIG_NET_SCHED is not set
-# CONFIG_NEW_LEDS is not set
-# CONFIG_NONSTATIC_KERNEL is not set
-CONFIG_NR_IRQS=512
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xc0000000
-CONFIG_PATA_MPC52xx=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERCPU_RWSEM=y
-CONFIG_PHYLIB=y
-CONFIG_PHYSICAL_START=0x00000000
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_PPC=y
-CONFIG_PPC32=y
-# CONFIG_PPC64 is not set
-# CONFIG_PPC_82xx is not set
-# CONFIG_PPC_83xx is not set
-# CONFIG_PPC_85xx is not set
-# CONFIG_PPC_86xx is not set
-# CONFIG_PPC_8xx is not set
-# CONFIG_PPC_970_NAP is not set
-CONFIG_PPC_BESTCOMM=y
-CONFIG_PPC_BESTCOMM_ATA=y
-CONFIG_PPC_BESTCOMM_FEC=y
-CONFIG_PPC_BOOK3S=y
-CONFIG_PPC_BOOK3S_32=y
-# CONFIG_PPC_CELL is not set
-# CONFIG_PPC_CELL_NATIVE is not set
-# CONFIG_PPC_CHRP is not set
-CONFIG_PPC_CLOCK=y
-# CONFIG_PPC_DCR_MMIO is not set
-# CONFIG_PPC_DCR_NATIVE is not set
-# CONFIG_PPC_EARLY_DEBUG is not set
-CONFIG_PPC_EFIKA=y
-# CONFIG_PPC_EPAPR_HV_PIC is not set
-CONFIG_PPC_FPU=y
-CONFIG_PPC_HAVE_PMU_SUPPORT=y
-# CONFIG_PPC_I8259 is not set
-# CONFIG_PPC_ICP_HV is not set
-# CONFIG_PPC_ICP_NATIVE is not set
-# CONFIG_PPC_ICS_RTAS is not set
-# CONFIG_PPC_INDIRECT_PCI is not set
-CONFIG_PPC_LIB_RHEAP=y
-# CONFIG_PPC_LITE5200 is not set
-# CONFIG_PPC_MEDIA5200 is not set
-# CONFIG_PPC_MM_SLICES is not set
-# CONFIG_PPC_MPC106 is not set
-# CONFIG_PPC_MPC512x is not set
-# CONFIG_PPC_MPC5200_BUGFIX is not set
-# CONFIG_PPC_MPC5200_LPBFIFO is not set
-# CONFIG_PPC_MPC5200_SIMPLE is not set
-CONFIG_PPC_MPC52xx=y
-CONFIG_PPC_NATIVE=y
-CONFIG_PPC_OF=y
-CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
-# CONFIG_PPC_P7_NAP is not set
-CONFIG_PPC_PCI_CHOICE=y
-# CONFIG_PPC_PMAC is not set
-CONFIG_PPC_RTAS=y
-# CONFIG_PPC_RTAS_DAEMON is not set
-CONFIG_PPC_STD_MMU=y
-CONFIG_PPC_STD_MMU_32=y
-# CONFIG_PPC_UDBG_16550 is not set
-CONFIG_PPC_WERROR=y
-# CONFIG_PPC_WSP is not set
-# CONFIG_PPC_XICS is not set
-# CONFIG_PQ2ADS is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_PROC_PAGE_MONITOR=y
-# CONFIG_RD_LZMA is not set
-# CONFIG_RTAS_ERROR_LOGGING is not set
-CONFIG_RTAS_PROC=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_SCHED_HRTICK=y
-CONFIG_SCSI=y
-CONFIG_SECCOMP=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_MPC52xx=y
-CONFIG_SERIAL_MPC52xx_CONSOLE=y
-CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD=115200
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOCK_DIAG=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_SQUASHFS is not set
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_SWIOTLB is not set
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_TASK_SIZE=0xc0000000
-# CONFIG_TAU is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_UDBG_RTAS_CONSOLE is not set
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_SUPPORT=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_VLAN_8021Q is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-# CONFIG_WATCHDOG_RTAS is not set
-CONFIG_WORD_SIZE=32
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_POWERPC=y
+++ /dev/null
-#
-# Copyright (C) 2009-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/BuildKernel
- cp $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage
-endef
-
-define Image/Build/ext2
- cp $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-ext2.img
-endef
-
-define Image/Build
- $(call Image/Build/$(1),$(1))
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-#
-# Copyright (C) 2007-2014 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=powerpc
-BOARD:=mpc83xx
-BOARDNAME:=Freescale MPC83xx
-CPU_TYPE:=603e
-FEATURES:=squashfs targz
-MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
-
-LINUX_VERSION:=3.8.13
-
-include $(INCLUDE_DIR)/target.mk
-
-DEFAULT_PACKAGES += kmod-via-velocity
-
-define Target/Description
- Build firmware images for Freescale MPC83xx based boards (eg. RouterBoard 600).
-endef
-
-KERNELNAME:="uImage dtbImage.rb600 dtbImage.rb333"
-
-$(eval $(call BuildTarget))
+++ /dev/null
-define Package/base-files/install-target
- rm -f $(1)/etc/config/network
-endef
-
-
+++ /dev/null
-::sysinit:/etc/init.d/rcS S boot
-::shutdown:/etc/init.d/rcS K shutdown
-ttyS0::askfirst:/bin/ash --login
-ttyS1::askfirst:/bin/ash --login
+++ /dev/null
-#!/bin/sh
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-
-[ -e /etc/config/network ] && exit 0
-
-touch /etc/config/network
-
-. /lib/functions/uci-defaults.sh
-. /lib/mpc83xx.sh
-
-ucidef_set_interface_loopback
-
-board=$(mpc83xx_board_name)
-
-case "$board" in
-rb333)
- ucidef_set_interfaces_lan_wan "eth0 eth1" "eth2"
- ;;
-
-*)
- ucidef_set_interfaces_lan_wan "eth0" "eth1"
- ;;
-esac
-
-uci commit network
-
-exit 0
+++ /dev/null
-#!/bin/sh
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-
-MPC83XX_BOARD_NAME=
-MPC83XX_MODEL=
-
-mpc83xx_board_detect() {
- local model
- local name
-
- model=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /model/ {print $2}' /proc/cpuinfo)
-
- case "$model" in
- "RB333")
- name="rb333"
- model="MikroTik RouterBOARD 333"
- ;;
- "RB600")
- name="rb600"
- model="MikroTik RouterBOARD 600"
- ;;
- esac
-
- [ -z "$name" ] && name="unknown"
-
- [ -z "$MPC83XX_BOARD_NAME" ] && MPC83XX_BOARD_NAME="$name"
- [ -z "$MPC83XX_MODEL" ] && MPC83XX_MODEL="$model"
-
- [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/"
-
- echo "$MPC83XX_BOARD_NAME" > /tmp/sysinfo/board_name
- echo "$MPC83XX_MODEL" > /tmp/sysinfo/model
-}
-
-mpc83xx_board_name() {
- local name
-
- [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name)
- [ -z "$name" ] && name="unknown"
-
- echo "$name"
-}
+++ /dev/null
-#!/bin/sh
-
-do_mpc83xx() {
- . /lib/mpc83xx.sh
-
- mpc83xx_board_detect
-}
-
-boot_hook_add preinit_main do_mpc83xx
+++ /dev/null
-# CONFIG_40x is not set
-# CONFIG_44x is not set
-CONFIG_6xx=y
-CONFIG_8xxx_WDT=y
-# CONFIG_ADVANCED_OPTIONS is not set
-# CONFIG_ALTIVEC is not set
-# CONFIG_AMIGAONE is not set
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_ILOG2_U32=y
-CONFIG_ARCH_HAS_WALK_MEMORY=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_MSI=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-# CONFIG_ARPD is not set
-# CONFIG_ASP834x is not set
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BOOTX_TEXT is not set
-CONFIG_BOUNCE=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,yaffs2,jffs2"
-CONFIG_CMDLINE_BOOL=y
-CONFIG_COMPAT_BRK=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEV_TALITOS=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_RNG2=y
-# CONFIG_CRYPTO_SHA1_PPC is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_DEFAULT_UIMAGE=y
-CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DTC=y
-# CONFIG_E200 is not set
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EMBEDDED6xx is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_EPAPR_BOOT is not set
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_FIXED_PHY=y
-CONFIG_FSL_DMA=y
-CONFIG_FSL_EMB_PERFMON=y
-CONFIG_FSL_GTM=y
-CONFIG_FSL_LBC=y
-CONFIG_FSL_PCI=y
-CONFIG_FSL_PQ_MDIO=y
-CONFIG_FSL_SOC=y
-# CONFIG_FSL_ULI1575 is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ACL=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_NVRAM=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-# CONFIG_GENERIC_TBSYNC is not set
-CONFIG_GENERIC_TIME_VSYSCALL_OLD=y
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
-# CONFIG_GE_FPGA is not set
-CONFIG_GIANFAR=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_MPC8XXX=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAS_RAPIDIO is not set
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INET_LRO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_INPUT_MISC is not set
-# CONFIG_IOMMU_HELPER is not set
-CONFIG_IOSCHED_CFQ=y
-CONFIG_IPIC=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_ISA_DMA_API=y
-# CONFIG_ISDN is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-# CONFIG_JFFS2_LZMA is not set
-# CONFIG_JFFS2_SUMMARY is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_KERNEL_START=0xc0000000
-# CONFIG_KMETER1 is not set
-# CONFIG_LBDAF is not set
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-# CONFIG_LEDS_TRIGGER_NETDEV is not set
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-CONFIG_LIBCRC32C=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_LOWMEM_SIZE=0x30000000
-# CONFIG_MATH_EMULATION is not set
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MDIO_GPIO=y
-# CONFIG_MMIO_NVRAM is not set
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MPC512X_DMA is not set
-CONFIG_MPC830x_RDB=y
-CONFIG_MPC831x_RDB=y
-CONFIG_MPC832x_MDS=y
-CONFIG_MPC832x_RDB=y
-CONFIG_MPC834x_ITX=y
-CONFIG_MPC834x_MDS=y
-CONFIG_MPC836x_MDS=y
-CONFIG_MPC836x_RDK=y
-CONFIG_MPC837x_MDS=y
-CONFIG_MPC837x_RDB=y
-# CONFIG_MPIC is not set
-# CONFIG_MPIC_U3_HT_IRQS is not set
-# CONFIG_MPIC_WEIRD is not set
-CONFIG_MTD_BLOCK2MTD=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_FSL_ELBC=y
-CONFIG_MTD_NAND_FSL_UPM=y
-CONFIG_MTD_NAND_RB_PPC=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP_OF=y
-# CONFIG_MTD_SM_COMMON is not set
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_BLOCK is not set
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_NEED_DMA_MAP_STATE is not set
-# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_EMATCH=y
-# CONFIG_NONSTATIC_KERNEL is not set
-CONFIG_NR_IRQS=512
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xc0000000
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PATA_RB_PPC=y
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_MSI=y
-CONFIG_PHYLIB=y
-CONFIG_PHYSICAL_START=0x00000000
-CONFIG_POWERNV_MSI=y
-CONFIG_PPC=y
-CONFIG_PPC32=y
-# CONFIG_PPC64 is not set
-# CONFIG_PPC_82xx is not set
-CONFIG_PPC_83xx=y
-# CONFIG_PPC_85xx is not set
-# CONFIG_PPC_86xx is not set
-# CONFIG_PPC_8xx is not set
-# CONFIG_PPC_970_NAP is not set
-CONFIG_PPC_BOOK3S=y
-CONFIG_PPC_BOOK3S_32=y
-# CONFIG_PPC_CELL is not set
-# CONFIG_PPC_CELL_NATIVE is not set
-# CONFIG_PPC_CHRP is not set
-# CONFIG_PPC_CLOCK is not set
-# CONFIG_PPC_DCR_MMIO is not set
-# CONFIG_PPC_DCR_NATIVE is not set
-CONFIG_PPC_DISABLE_WERROR=y
-# CONFIG_PPC_DOORBELL is not set
-# CONFIG_PPC_EARLY_DEBUG is not set
-# CONFIG_PPC_EPAPR_HV_PIC is not set
-CONFIG_PPC_FPU=y
-CONFIG_PPC_HAVE_PMU_SUPPORT=y
-# CONFIG_PPC_I8259 is not set
-# CONFIG_PPC_ICP_HV is not set
-# CONFIG_PPC_ICP_NATIVE is not set
-# CONFIG_PPC_ICS_RTAS is not set
-CONFIG_PPC_INDIRECT_PCI=y
-CONFIG_PPC_LIB_RHEAP=y
-# CONFIG_PPC_MM_SLICES is not set
-# CONFIG_PPC_MPC106 is not set
-# CONFIG_PPC_MPC512x is not set
-# CONFIG_PPC_MPC52xx is not set
-CONFIG_PPC_MPC831x=y
-CONFIG_PPC_MPC832x=y
-CONFIG_PPC_MPC834x=y
-CONFIG_PPC_MPC837x=y
-CONFIG_PPC_MSI_BITMAP=y
-CONFIG_PPC_OF=y
-CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
-# CONFIG_PPC_P7_NAP is not set
-CONFIG_PPC_PCI_CHOICE=y
-# CONFIG_PPC_PMAC is not set
-# CONFIG_PPC_RTAS is not set
-CONFIG_PPC_STD_MMU=y
-CONFIG_PPC_STD_MMU_32=y
-CONFIG_PPC_UDBG_16550=y
-# CONFIG_PPC_WSP is not set
-# CONFIG_PPC_XICS is not set
-# CONFIG_PQ2ADS is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_PROC_PAGE_MONITOR=y
-# CONFIG_PTP_1588_CLOCK_GIANFAR is not set
-CONFIG_QE_GPIO=y
-CONFIG_QUICC_ENGINE=y
-CONFIG_RB_IOMAP=y
-CONFIG_RB_PPC=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SBC834x is not set
-CONFIG_SCHED_HRTICK=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_QE=y
-CONFIG_SERIO=y
-# CONFIG_SERIO_APBPS2 is not set
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_PCIPS2=y
-CONFIG_SERIO_RAW=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_XILINX_XPS_PS2 is not set
-CONFIG_SIMPLE_GPIO=y
-# CONFIG_SLAB is not set
-CONFIG_SLOB=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-# CONFIG_SWAP is not set
-# CONFIG_SWIOTLB is not set
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_TASK_SIZE=0xc0000000
-# CONFIG_TAU is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TMPFS_POSIX_ACL=y
-# CONFIG_UBIFS_FS is not set
-CONFIG_UCC=y
-CONFIG_UCC_FAST=y
-CONFIG_UCC_GETH=y
-CONFIG_UCC_SLOW=y
-# CONFIG_UCC_TDM is not set
-# CONFIG_UGETH_TX_ON_DEMAND is not set
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_VIA_VELOCITY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_VITESSE_PHY_8601_SKEW=y
-CONFIG_WORD_SIZE=32
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_YAFFS_9BYTE_TAGS=y
-# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
-CONFIG_YAFFS_AUTO_YAFFS2=y
-# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
-# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
-CONFIG_YAFFS_DISABLE_TAGS_ECC=y
-# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
-CONFIG_YAFFS_FS=y
-CONFIG_YAFFS_XATTR=y
-CONFIG_YAFFS_YAFFS1=y
-CONFIG_YAFFS_YAFFS2=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
+++ /dev/null
-# CONFIG_40x is not set
-# CONFIG_44x is not set
-CONFIG_6xx=y
-CONFIG_8xxx_WDT=y
-# CONFIG_ADVANCED_OPTIONS is not set
-# CONFIG_ALTIVEC is not set
-# CONFIG_AMIGAONE is not set
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_ILOG2_U32=y
-CONFIG_ARCH_HAS_WALK_MEMORY=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_MSI=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-# CONFIG_ARPD is not set
-# CONFIG_ASP834x is not set
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BOOTX_TEXT is not set
-CONFIG_BOUNCE=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,yaffs2,jffs2"
-CONFIG_CMDLINE_BOOL=y
-CONFIG_COMPAT_BRK=y
-CONFIG_CONFIGFS_FS=m
-CONFIG_CRC16=m
-CONFIG_CRC7=m
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC_T10DIF=m
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_DEV_TALITOS=y
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HMAC=m
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_MD5=m
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_DEFAULT_UIMAGE=y
-CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DTC=y
-# CONFIG_DW_DMAC is not set
-# CONFIG_E200 is not set
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EMBEDDED6xx is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_EPAPR_BOOT is not set
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_FIXED_PHY=y
-CONFIG_FSL_DMA=y
-CONFIG_FSL_EMB_PERFMON=y
-CONFIG_FSL_GTM=y
-CONFIG_FSL_LBC=y
-CONFIG_FSL_PCI=y
-CONFIG_FSL_PQ_MDIO=y
-CONFIG_FSL_SOC=y
-# CONFIG_FSL_ULI1575 is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ACL=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_NVRAM=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-# CONFIG_GENERIC_TBSYNC is not set
-CONFIG_GENERIC_TIME_VSYSCALL_OLD=y
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
-# CONFIG_GE_FPGA is not set
-CONFIG_GIANFAR=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_MPC8XXX=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAS_RAPIDIO is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_INET_AH=m
-CONFIG_INET_DIAG=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_LRO=y
-CONFIG_INET_TCP_DIAG=m
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_TUNNEL=m
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_INPUT_MISC is not set
-# CONFIG_IOMMU_HELPER is not set
-CONFIG_IOSCHED_CFQ=y
-CONFIG_IPIC=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_IP_ROUTE_CLASSID=y
-CONFIG_IP_SCTP=m
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_ISA_DMA_API=y
-# CONFIG_ISDN is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-# CONFIG_JFFS2_LZMA is not set
-# CONFIG_JFFS2_SUMMARY is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_KERNEL_START=0xc0000000
-# CONFIG_KMETER1 is not set
-# CONFIG_LBDAF is not set
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-# CONFIG_LEDS_TRIGGER_NETDEV is not set
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-CONFIG_LIBCRC32C=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_LOWMEM_SIZE=0x30000000
-# CONFIG_MATH_EMULATION is not set
-CONFIG_MAX_ACTIVE_REGIONS=32
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MDIO_GPIO=y
-# CONFIG_MMIO_NVRAM is not set
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MPC512X_DMA is not set
-CONFIG_MPC830x_RDB=y
-CONFIG_MPC831x_RDB=y
-CONFIG_MPC832x_MDS=y
-CONFIG_MPC832x_RDB=y
-CONFIG_MPC834x_ITX=y
-CONFIG_MPC834x_MDS=y
-CONFIG_MPC836x_MDS=y
-CONFIG_MPC836x_RDK=y
-CONFIG_MPC837x_MDS=y
-CONFIG_MPC837x_RDB=y
-# CONFIG_MPIC is not set
-# CONFIG_MPIC_U3_HT_IRQS is not set
-# CONFIG_MPIC_WEIRD is not set
-CONFIG_MTD_BLOCK2MTD=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_FSL_ELBC=y
-# CONFIG_MTD_NAND_FSL_IFC is not set
-CONFIG_MTD_NAND_FSL_UPM=y
-CONFIG_MTD_NAND_RB_PPC=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP_OF=y
-# CONFIG_MTD_SM_COMMON is not set
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_BLOCK is not set
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_NEED_DMA_MAP_STATE is not set
-# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_U32=m
-# CONFIG_NET_DMA is not set
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_IPIP=m
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_TEQL=m
-# CONFIG_NONSTATIC_KERNEL is not set
-CONFIG_NR_IRQS=512
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xc0000000
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PATA_RB_PPC=y
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_MSI=y
-CONFIG_PERCPU_RWSEM=y
-CONFIG_PHYLIB=y
-CONFIG_PHYSICAL_START=0x00000000
-CONFIG_PPC=y
-CONFIG_PPC32=y
-# CONFIG_PPC64 is not set
-# CONFIG_PPC_82xx is not set
-CONFIG_PPC_83xx=y
-# CONFIG_PPC_85xx is not set
-# CONFIG_PPC_86xx is not set
-# CONFIG_PPC_8xx is not set
-# CONFIG_PPC_970_NAP is not set
-CONFIG_PPC_BOOK3S=y
-CONFIG_PPC_BOOK3S_32=y
-# CONFIG_PPC_CELL is not set
-# CONFIG_PPC_CELL_NATIVE is not set
-# CONFIG_PPC_CHRP is not set
-CONFIG_PPC_CLOCK=y
-# CONFIG_PPC_DCR_MMIO is not set
-# CONFIG_PPC_DCR_NATIVE is not set
-CONFIG_PPC_DISABLE_WERROR=y
-# CONFIG_PPC_EARLY_DEBUG is not set
-# CONFIG_PPC_EPAPR_HV_PIC is not set
-CONFIG_PPC_FPU=y
-CONFIG_PPC_HAVE_PMU_SUPPORT=y
-# CONFIG_PPC_I8259 is not set
-# CONFIG_PPC_ICP_HV is not set
-# CONFIG_PPC_ICP_NATIVE is not set
-# CONFIG_PPC_ICS_RTAS is not set
-CONFIG_PPC_INDIRECT_PCI=y
-CONFIG_PPC_LIB_RHEAP=y
-# CONFIG_PPC_MM_SLICES is not set
-# CONFIG_PPC_MPC106 is not set
-# CONFIG_PPC_MPC512x is not set
-# CONFIG_PPC_MPC52xx is not set
-CONFIG_PPC_MPC831x=y
-CONFIG_PPC_MPC832x=y
-CONFIG_PPC_MPC834x=y
-CONFIG_PPC_MPC837x=y
-CONFIG_PPC_MSI_BITMAP=y
-CONFIG_PPC_OF=y
-CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
-# CONFIG_PPC_P7_NAP is not set
-CONFIG_PPC_PCI_CHOICE=y
-# CONFIG_PPC_PMAC is not set
-# CONFIG_PPC_RTAS is not set
-CONFIG_PPC_STD_MMU=y
-CONFIG_PPC_STD_MMU_32=y
-CONFIG_PPC_UDBG_16550=y
-# CONFIG_PPC_WSP is not set
-# CONFIG_PPC_XICS is not set
-# CONFIG_PQ2ADS is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_PROC_PAGE_MONITOR=y
-# CONFIG_PTP_1588_CLOCK_GIANFAR is not set
-CONFIG_QE_GPIO=y
-CONFIG_QUICC_ENGINE=y
-CONFIG_RB_IOMAP=y
-CONFIG_RB_PPC=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SBC834x is not set
-CONFIG_SCHED_HRTICK=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_SCTP_COOKIE_HMAC_MD5=y
-# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set
-# CONFIG_SCTP_DBG_MSG is not set
-# CONFIG_SCTP_DBG_OBJCNT is not set
-CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_QE=y
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_PCIPS2=y
-CONFIG_SERIO_RAW=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_XILINX_XPS_PS2 is not set
-CONFIG_SIMPLE_GPIO=y
-# CONFIG_SLAB is not set
-CONFIG_SLOB=y
-CONFIG_SOCK_DIAG=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-# CONFIG_SWAP is not set
-# CONFIG_SWIOTLB is not set
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_TASK_SIZE=0xc0000000
-# CONFIG_TAU is not set
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TMPFS_POSIX_ACL=y
-# CONFIG_UBIFS_FS is not set
-CONFIG_UCC=y
-CONFIG_UCC_FAST=y
-CONFIG_UCC_GETH=y
-CONFIG_UCC_SLOW=y
-# CONFIG_UCC_TDM is not set
-# CONFIG_UGETH_TX_ON_DEMAND is not set
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_VIA_VELOCITY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_VITESSE_PHY_8601_SKEW=y
-CONFIG_WAN_ROUTER=m
-CONFIG_WORD_SIZE=32
-CONFIG_XFRM_ALGO=m
-CONFIG_XFRM_IPCOMP=m
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_YAFFS_9BYTE_TAGS=y
-# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
-CONFIG_YAFFS_AUTO_YAFFS2=y
-# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
-# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
-CONFIG_YAFFS_DISABLE_TAGS_ECC=y
-# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
-CONFIG_YAFFS_FS=y
-CONFIG_YAFFS_XATTR=y
-CONFIG_YAFFS_YAFFS1=y
-CONFIG_YAFFS_YAFFS2=y
+++ /dev/null
-#!/bin/bash
-#
-# Licensed under the terms of the GNU GPL License version 2 or later.
-#
-# Author: Peter Tyser <ptyser@xes-inc.com>
-#
-# U-Boot firmware supports the booting of images in the Flattened Image
-# Tree (FIT) format. The FIT format uses a device tree structure to
-# describe a kernel image, device tree blob, ramdisk, etc. This script
-# creates an Image Tree Source (.its file) which can be passed to the
-# 'mkimage' utility to generate an Image Tree Blob (.itb file). The .itb
-# file can then be booted by U-Boot (or other bootloaders which support
-# FIT images). See doc/uImage.FIT/howto.txt in U-Boot source code for
-# additional information on FIT images.
-#
-
-usage() {
- echo "Usage: `basename $0` -A arch -C comp -a addr -e entry" \
- "-v version -k kernel [-d dtb] -o its_file"
- echo -e "\t-A ==> set architecture to 'arch'"
- echo -e "\t-C ==> set compression type 'comp'"
- echo -e "\t-a ==> set load address to 'addr' (hex)"
- echo -e "\t-e ==> set entry point to 'entry' (hex)"
- echo -e "\t-v ==> set kernel version to 'version'"
- echo -e "\t-k ==> include kernel image 'kernel'"
- echo -e "\t-d ==> include Device Tree Blob 'dtb'"
- echo -e "\t-o ==> create output file 'its_file'"
- exit 1
-}
-
-while getopts ":A:C:a:d:e:k:o:v:" OPTION
-do
- case $OPTION in
- A ) ARCH=$OPTARG;;
- C ) COMPRESS=$OPTARG;;
- a ) LOAD_ADDR=$OPTARG;;
- d ) DTB=$OPTARG;;
- e ) ENTRY_ADDR=$OPTARG;;
- k ) KERNEL=$OPTARG;;
- o ) OUTPUT=$OPTARG;;
- v ) VERSION=$OPTARG;;
- * ) echo "Invalid option passed to '$0' (options:$@)"
- usage;;
- esac
-done
-
-# Make sure user entered all required parameters
-if [ -z "${ARCH}" ] || [ -z "${COMPRESS}" ] || [ -z "${LOAD_ADDR}" ] || \
- [ -z "${ENTRY_ADDR}" ] || [ -z "${VERSION}" ] || [ -z "${KERNEL}" ] || \
- [ -z "${OUTPUT}" ]; then
- usage
-fi
-
-# Create a default, fully populated DTS file
-DATA="/dts-v1/;
-
-/ {
- description = \"Linux kernel ${VERSION}\";
- #address-cells = <1>;
-
- images {
- kernel@1 {
- description = \"Linux Kernel ${VERSION}\";
- data = /incbin/(\"${KERNEL}\");
- type = \"kernel\";
- arch = \"${ARCH}\";
- os = \"linux\";
- compression = \"${COMPRESS}\";
- load = <${LOAD_ADDR}>;
- entry = <${ENTRY_ADDR}>;
- hash@1 {
- algo = \"crc32\";
- };
- hash@2 {
- algo = \"sha1\";
- };
- };
-
- fdt@1 { /* start fdt */
- description = \"Flattened Device Tree blob\";
- data = /incbin/(\"${DTB}\");
- type = \"flat_dt\";
- arch = \"${ARCH}\";
- compression = \"none\";
- hash@1 {
- algo = \"crc32\";
- };
- hash@2 {
- algo = \"sha1\";
- };
- }; /* end fdt */
- };
-
- configurations {
- default = \"config@1\";
- config@1 {
- description = \"Default Linux kernel\";
- kernel = \"kernel@1\";
- fdt = \"fdt@1\";
- };
- };
-};"
-
-# Conditionally strip fdt information out of tree
-if [ -z "${DTB}" ]; then
- DATA=`echo "$DATA" | sed '/start fdt/,/end fdt/d'`
- DATA=`echo "$DATA" | sed '/fdt/d'`
-fi
-
-# Write .its file to disk
-echo "$DATA" > ${OUTPUT}
+++ /dev/null
-#
-# Copyright (C) 2009-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-
-define Image/Prepare
- $(LINUX_DIR)/scripts/dtc/dtc -O dtb -R 4 -S 0x20000 $(DTS_DIR)/mpc8377_wlan.dts > $(BIN_DIR)/openwrt-mpc83xx-mpc8377_wlan.dtb
-endef
-
-define Image/BuildKernel
- cp $(LINUX_DIR)/arch/powerpc/boot/dtbImage.rb600.elf $(BIN_DIR)/openwrt-$(BOARD)-rb600.elf
- cp $(LINUX_DIR)/arch/powerpc/boot/dtbImage.rb333.elf $(BIN_DIR)/openwrt-$(BOARD)-rb333.elf
- cp $(KDIR)/uImage $(BIN_DIR)/openwrt-$(BOARD)-uImage
-endef
-
-define Image/Build
- $(call Image/Build/$(1),$(1))
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
- ( \
- dd if=$(LINUX_DIR)/arch/powerpc/boot/uImage bs=3072k conv=sync; \
- dd if=$(KDIR)/root.$(1) bs=256k conv=sync; \
- ) > $(BIN_DIR)/$(IMG_PREFIX)-mpc8377_wlan-$(1).img
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define KernelPackage/ata-rbppc-cf
- SUBMENU:=$(BLOCK_MENU)
- TITLE:=RB600 Compact Flash support
- DEPENDS:=@TARGET_mpc83xx
- KCONFIG:= \
- CONFIG_PATA_PLATFORM \
- CONFIG_PATA_RB_PPC
- FILES:=\
- $(LINUX_DIR)/drivers/ata/pata_rbppc_cf.ko
- AUTOLOAD:=$(call AutoLoad,41,pata_rbppc_cf,1)
- $(call AddDepends/ata)
-endef
-
-define KernelPackage/ata-rbppc-cf/description
- RB600 Compact Flash support.
-endef
-
-$(eval $(call KernelPackage,ata-rbppc-cf))
+++ /dev/null
---- a/arch/powerpc/Makefile
-+++ b/arch/powerpc/Makefile
-@@ -177,7 +177,9 @@ all: zImage
-
- # With make 3.82 we cannot mix normal and wildcard targets
- BOOT_TARGETS1 := zImage zImage.initrd uImage
--BOOT_TARGETS2 := zImage% dtbImage% treeImage.% cuImage.% simpleImage.% uImage.%
-+BOOT_TARGETS2 := uImage.fit.% zImage% dtbImage% treeImage.% cuImage.% \
-+ simpleImage.% uImage.%
-+
-
- PHONY += $(BOOT_TARGETS1) $(BOOT_TARGETS2)
-
-@@ -210,6 +212,7 @@ define archhelp
- @echo '* zImage - Build default images selected by kernel config'
- @echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
- @echo ' uImage - U-Boot native image format'
-+ @echo ' uImage.fit.<dt> - U-Boot Flattened Image Tree image format'
- @echo ' cuImage.<dt> - Backwards compatible U-Boot image for older'
- @echo ' versions which do not support device trees'
- @echo ' dtbImage.<dt> - zImage with an embedded device tree blob'
---- a/arch/powerpc/boot/.gitignore
-+++ b/arch/powerpc/boot/.gitignore
-@@ -14,6 +14,7 @@ kernel-vmlinux.strip.c
- kernel-vmlinux.strip.gz
- mktree
- uImage
-+uImage.fit.*
- cuImage.*
- dtbImage.*
- treeImage.*
---- a/arch/powerpc/boot/Makefile
-+++ b/arch/powerpc/boot/Makefile
-@@ -338,6 +338,9 @@ $(obj)/uImage.initrd.%: vmlinux $(obj)/%
- $(obj)/uImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
- $(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb)
-
-+$(obj)/uImage.fit.%: vmlinux $(obj)/%.dtb $(wrapperbits)
-+ $(call if_changed,wrap,uboot.fit,,$(obj)/$*.dtb)
-+
- $(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
- $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
-
-@@ -375,6 +378,7 @@ install: $(CONFIGURE) $(addprefix $(obj)
-
- # anything not in $(targets)
- clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \
-+ uImage.* \
- zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
- zImage.miboot zImage.pmac zImage.pseries \
- zImage.maple simpleImage.* otheros.bld *.dtb
---- a/arch/powerpc/boot/wrapper
-+++ b/arch/powerpc/boot/wrapper
-@@ -47,6 +47,9 @@ CROSS=
- # mkimage wrapper script
- MKIMAGE=$srctree/scripts/mkuboot.sh
-
-+# script to generate an .its file for uImage.fit.* images
-+MKITS=$srctree/scripts/mkits.sh
-+
- # directory for object and other files used by this script
- object=arch/powerpc/boot
- objbin=$object
-@@ -336,6 +339,21 @@ uboot-obs600)
- if [ -z "$cacheit" ]; then
- rm -f "$vmz"
- fi
-+ exit 0
-+ ;;
-+uboot.fit)
-+ rm -f "$ofile"
-+ ${MKITS} -A ppc -C gzip -a $membase -e $membase -v $version \
-+ -d "$srctree/$dtb" -k "$srctree/$vmz" -o "$object/uImage.its"
-+
-+ # mkimage calls dtc for FIT images so use kernel dtc if necessary
-+ export PATH=$PATH:$srctree/scripts/dtc
-+
-+ ${MKIMAGE} -f "$object/uImage.its" "$ofile"
-+ rm "$object/uImage.its"
-+ if [ -z "$cacheit" ]; then
-+ rm -f "$vmz"
-+ fi
- exit 0
- ;;
- esac
+++ /dev/null
---- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
-+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
-@@ -462,4 +462,18 @@
- 0 0x00800000>;
- };
- };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ diag {
-+ gpios = <&gpio1 9 1>;
-+ default-state = "off";
-+ };
-+
-+ wireless {
-+ gpios = <&gpio1 10 1>;
-+ default-state = "off";
-+ };
-+ };
- };
+++ /dev/null
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -68,6 +68,12 @@ config VITESSE_PHY
- ---help---
- Currently supports the vsc8244
-
-+config VITESSE_PHY_8601_SKEW
-+ bool "Enable skew timing to vsc8601"
-+ depends on VITESSE_PHY
-+ ---help---
-+ Apply clock timing adjustments for vsc8601
-+
- config SMSC_PHY
- tristate "Drivers for SMSC PHYs"
- ---help---
---- a/drivers/net/phy/vitesse.c
-+++ b/drivers/net/phy/vitesse.c
-@@ -26,6 +26,11 @@
- #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
- #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
-
-+/* EXT_CON1 Register values for VSC8601 */
-+#define MII_VSC8601_EXTCON1_INIT 0x0000
-+#define MII_VSC8601_EXTCON1_SKEW 0x0100
-+#define MII_VSC8601_EXTCON1_ACTIPHY 0x0020
-+
- /* Vitesse Interrupt Mask Register */
- #define MII_VSC8244_IMASK 0x19
- #define MII_VSC8244_IMASK_IEN 0x8000
-@@ -56,6 +61,7 @@
-
- #define PHY_ID_VSC8244 0x000fc6c0
- #define PHY_ID_VSC8221 0x000fc550
-+#define PHY_ID_VSC8601 0x00070420
-
- MODULE_DESCRIPTION("Vitesse PHY driver");
- MODULE_AUTHOR("Kriston Carson");
-@@ -97,10 +103,34 @@ static int vsc824x_config_init(struct ph
- return err;
- }
-
-+static int vsc8601_config_init(struct phy_device *phydev)
-+{
-+ int err;
-+ int extcon;
-+
-+ err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
-+ MII_VSC8244_AUXCONSTAT_INIT);
-+
-+ if (err < 0)
-+ return err;
-+
-+#ifdef CONFIG_VITESSE_PHY_8601_SKEW
-+ extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
-+ if (err < 0)
-+ return err;
-+
-+ extcon |= MII_VSC8601_EXTCON1_SKEW;
-+
-+ err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
-+#endif
-+
-+ return err;
-+}
-+
- static int vsc824x_ack_interrupt(struct phy_device *phydev)
- {
- int err = 0;
--
-+
- /*
- * Don't bother to ACK the interrupts if interrupts
- * are disabled. The 824x cannot clear the interrupts
-@@ -176,6 +206,19 @@ static struct phy_driver vsc82xx_driver[
- .ack_interrupt = &vsc824x_ack_interrupt,
- .config_intr = &vsc82xx_config_intr,
- .driver = { .owner = THIS_MODULE,},
-+}, {
-+ /* Vitesse 8601 */
-+ .phy_id = PHY_ID_VSC8601,
-+ .name = "Vitesse VSC8601",
-+ .phy_id_mask = 0x000ffff8,
-+ .features = PHY_GBIT_FEATURES,
-+ .flags = PHY_HAS_INTERRUPT,
-+ .config_init = &vsc8601_config_init,
-+ .config_aneg = &genphy_config_aneg,
-+ .read_status = &genphy_read_status,
-+ .ack_interrupt = &vsc824x_ack_interrupt,
-+ .config_intr = &vsc82xx_config_intr,
-+ .driver = { .owner = THIS_MODULE,},
- } };
-
- static int __init vsc82xx_init(void)
+++ /dev/null
---- a/drivers/net/ethernet/freescale/gianfar.c
-+++ b/drivers/net/ethernet/freescale/gianfar.c
-@@ -1016,7 +1016,16 @@ static int gfar_probe(struct platform_de
- /* We need to delay at least 3 TX clocks */
- udelay(2);
-
-- tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
-+ if ((mfspr(SPRN_SVR) & 0xffff) >= 0x0011) {
-+ tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
-+ } else {
-+ /*
-+ * Do not enable flow control on chips earlier than rev 1.1,
-+ * because of the eTSEC27 erratum
-+ */
-+ tempval = 0;
-+ }
-+
- gfar_write(®s->maccfg1, tempval);
-
- /* Initialize MACCFG2. */
+++ /dev/null
---- /dev/null
-+++ b/drivers/misc/ucc_tdm.h
-@@ -0,0 +1,221 @@
-+/*
-+ * drivers/misc/ucc_tdm.h
-+ *
-+ * UCC Based Linux TDM Driver
-+ * This driver is designed to support UCC based TDM for PowerPC processors.
-+ * This driver can interface with SLIC device to run VOIP kind of
-+ * applications.
-+ *
-+ * Author: Ashish Kalra & Poonam Aggrwal
-+ *
-+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#ifndef TDM_H
-+#define TDM_H
-+
-+#define NUM_TS 8
-+#define ACTIVE_CH 8
-+
-+/* SAMPLE_DEPTH is the sample depth is the number of frames before
-+ * an interrupt. Must be a multiple of 4
-+ */
-+#define SAMPLE_DEPTH 80
-+
-+/* define the number of Rx interrupts to go by for initial stuttering */
-+#define STUTTER_INT_CNT 1
-+
-+/* BMRx Field Descriptions to specify tstate and rstate in UCC parameter RAM*/
-+#define EN_BUS_SNOOPING 0x20
-+#define BE_BO 0x10
-+
-+/* UPSMR Register for Transparent UCC controller Bit definitions*/
-+#define NBO 0x00000000 /* Normal Mode 1 bit of data per clock */
-+
-+/* SI Mode register bit definitions */
-+#define NORMAL_OPERATION 0x0000
-+#define AUTO_ECHO 0x0400
-+#define INTERNAL_LB 0x0800
-+#define CONTROL_LB 0x0c00
-+#define SIMODE_CRT (0x8000 >> 9)
-+#define SIMODE_SL (0x8000 >> 10)
-+#define SIMODE_CE (0x8000 >> 11)
-+#define SIMODE_FE (0x8000 >> 12)
-+#define SIMODE_GM (0x8000 >> 13)
-+#define SIMODE_TFSD(val) (val)
-+#define SIMODE_RFSD(val) ((val) << 8)
-+
-+#define SI_TDM_MODE_REGISTER_OFFSET 0
-+
-+#define R_CM 0x02000000
-+#define T_CM 0x02000000
-+
-+#define SET_RX_SI_RAM(n, val) \
-+ out_be16((u16 *)&qe_immr->sir.rx[(n)*2], (u16)(val))
-+
-+#define SET_TX_SI_RAM(n, val) \
-+ out_be16((u16 *)&qe_immr->sir.tx[(n)*2], (u16)(val))
-+
-+/* SI RAM entries */
-+#define SIR_LAST 0x0001
-+#define SIR_CNT(n) ((n) << 2)
-+#define SIR_BYTE 0x0002
-+#define SIR_BIT 0x0000
-+#define SIR_IDLE 0
-+#define SIR_UCC(uccx) (((uccx+9)) << 5)
-+
-+/* BRGC Register Bit definitions */
-+#define BRGC_RESET (0x1<<17)
-+#define BRGC_EN (0x1<<16)
-+#define BRGC_EXTC_QE (0x00<<14)
-+#define BRGC_EXTC_CLK3 (0x01<<14)
-+#define BRGC_EXTC_CLK5 (0x01<<15)
-+#define BRGC_EXTC_CLK9 (0x01<<14)
-+#define BRGC_EXTC_CLK11 (0x01<<14)
-+#define BRGC_EXTC_CLK13 (0x01<<14)
-+#define BRGC_EXTC_CLK15 (0x01<<15)
-+#define BRGC_ATB (0x1<<13)
-+#define BRGC_DIV16 (0x1)
-+
-+/* structure representing UCC transparent parameter RAM */
-+struct ucc_transparent_pram {
-+ __be16 riptr;
-+ __be16 tiptr;
-+ __be16 res0;
-+ __be16 mrblr;
-+ __be32 rstate;
-+ __be32 rbase;
-+ __be16 rbdstat;
-+ __be16 rbdlen;
-+ __be32 rdptr;
-+ __be32 tstate;
-+ __be32 tbase;
-+ __be16 tbdstat;
-+ __be16 tbdlen;
-+ __be32 tdptr;
-+ __be32 rbptr;
-+ __be32 tbptr;
-+ __be32 rcrc;
-+ __be32 res1;
-+ __be32 tcrc;
-+ __be32 res2;
-+ __be32 res3;
-+ __be32 c_mask;
-+ __be32 c_pres;
-+ __be16 disfc;
-+ __be16 crcec;
-+ __be32 res4[4];
-+ __be16 ts_tmp;
-+ __be16 tmp_mb;
-+};
-+
-+#define UCC_TRANSPARENT_PRAM_SIZE 0x100
-+
-+struct tdm_cfg {
-+ u8 com_pin; /* Common receive and transmit pins
-+ * 0 = separate pins
-+ * 1 = common pins
-+ */
-+
-+ u8 fr_sync_level; /* SLx bit Frame Sync Polarity
-+ * 0 = L1R/TSYNC active logic "1"
-+ * 1 = L1R/TSYNC active logic "0"
-+ */
-+
-+ u8 clk_edge; /* CEx bit Tx Rx Clock Edge
-+ * 0 = TX data on rising edge of clock
-+ * RX data on falling edge
-+ * 1 = TX data on falling edge of clock
-+ * RX data on rising edge
-+ */
-+
-+ u8 fr_sync_edge; /* FEx bit Frame sync edge
-+ * Determine when the sync pulses are sampled
-+ * 0 = Falling edge
-+ * 1 = Rising edge
-+ */
-+
-+ u8 rx_fr_sync_delay; /* TFSDx/RFSDx bits Frame Sync Delay
-+ * 00 = no bit delay
-+ * 01 = 1 bit delay
-+ * 10 = 2 bit delay
-+ * 11 = 3 bit delay
-+ */
-+
-+ u8 tx_fr_sync_delay; /* TFSDx/RFSDx bits Frame Sync Delay
-+ * 00 = no bit delay
-+ * 01 = 1 bit delay
-+ * 10 = 2 bit delay
-+ * 11 = 3 bit delay
-+ */
-+
-+ u8 active_num_ts; /* Number of active time slots in TDM
-+ * assume same active Rx/Tx time slots
-+ */
-+};
-+
-+struct ucc_tdm_info {
-+ struct ucc_fast_info uf_info;
-+ u32 ucc_busy;
-+};
-+
-+struct tdm_ctrl {
-+ u32 device_busy;
-+ struct device *device;
-+ struct ucc_fast_private *uf_private;
-+ struct ucc_tdm_info *ut_info;
-+ u32 tdm_port; /* port for this tdm:TDMA,TDMB,TDMC,TDMD */
-+ u32 si; /* serial interface: 0 or 1 */
-+ struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */
-+ u16 rx_mask[8]; /* Active Receive channels LSB is ch0 */
-+ u16 tx_mask[8]; /* Active Transmit channels LSB is ch0 */
-+ /* Only channels less than the number of FRAME_SIZE are implemented */
-+ struct tdm_cfg cfg_ctrl; /* Signaling controls configuration */
-+ u8 *tdm_input_data; /* buffer used for Rx by the tdm */
-+ u8 *tdm_output_data; /* buffer used for Tx by the tdm */
-+
-+ dma_addr_t dma_input_addr; /* dma mapped buffer for TDM Rx */
-+ dma_addr_t dma_output_addr; /* dma mapped buffer for TDM Tx */
-+ u16 physical_num_ts; /* physical number of timeslots in the tdm
-+ frame */
-+ u32 phase_rx; /* cycles through 0, 1, 2 */
-+ u32 phase_tx; /* cycles through 0, 1, 2 */
-+ /*
-+ * the following two variables are for dealing with "stutter" problem
-+ * "stutter" period is about 20 frames or so, varies depending active
-+ * channel num depending on the sample depth, the code should let a
-+ * few Rx interrupts go by
-+ */
-+ u32 tdm_icnt;
-+ u32 tdm_flag;
-+ struct ucc_transparent_pram __iomem *ucc_pram;
-+ struct qe_bd __iomem *tx_bd;
-+ struct qe_bd __iomem *rx_bd;
-+ u32 ucc_pram_offset;
-+ u32 tx_bd_offset;
-+ u32 rx_bd_offset;
-+ u32 rx_ucode_buf_offset;
-+ u32 tx_ucode_buf_offset;
-+ bool leg_slic;
-+ wait_queue_head_t wakeup_event;
-+};
-+
-+struct tdm_client {
-+ u32 client_id;
-+ void (*tdm_read)(u32 client_id, short chn_id,
-+ short *pcm_buffer, short len);
-+ void (*tdm_write)(u32 client_id, short chn_id,
-+ short *pcm_buffer, short len);
-+ wait_queue_head_t *wakeup_event;
-+ };
-+
-+#define MAX_PHASE 1
-+#define NR_BUFS 2
-+#define EFF_ACTIVE_CH ACTIVE_CH / 2
-+
-+#endif
---- /dev/null
-+++ b/drivers/misc/ucc_tdm.c
-@@ -0,0 +1,1017 @@
-+/*
-+ * drivers/misc/ucc_tdm.c
-+ *
-+ * UCC Based Linux TDM Driver
-+ * This driver is designed to support UCC based TDM for PowerPC processors.
-+ * This driver can interface with SLIC device to run VOIP kind of
-+ * applications.
-+ *
-+ * Author: Ashish Kalra & Poonam Aggrwal
-+ *
-+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <generated/autoconf.h>
-+#include <linux/module.h>
-+#include <linux/sched.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/errno.h>
-+#include <linux/types.h>
-+#include <linux/interrupt.h>
-+#include <linux/time.h>
-+#include <linux/skbuff.h>
-+#include <linux/proc_fs.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/string.h>
-+#include <linux/irq.h>
-+#include <linux/of_platform.h>
-+#include <linux/io.h>
-+#include <linux/wait.h>
-+#include <linux/timer.h>
-+
-+#include <asm/immap_qe.h>
-+#include <asm/qe.h>
-+#include <asm/ucc.h>
-+#include <asm/ucc_fast.h>
-+#include <asm/ucc_slow.h>
-+
-+#include "ucc_tdm.h"
-+#define DRV_DESC "Freescale QE UCC TDM Driver"
-+#define DRV_NAME "ucc_tdm"
-+
-+
-+/*
-+ * define the following #define if snooping or hardware-based cache coherency
-+ * is disabled on the UCC transparent controller.This flag enables
-+ * software-based cache-coherency support by explicitly flushing data cache
-+ * contents after setting up the TDM output buffer(s) and invalidating the
-+ * data cache contents before the TDM input buffer(s) are read.
-+ */
-+#undef UCC_CACHE_SNOOPING_DISABLED
-+
-+#define MAX_NUM_TDM_DEVICES 8
-+
-+static struct tdm_ctrl *tdm_ctrl[MAX_NUM_TDM_DEVICES];
-+
-+static int num_tdm_devices;
-+static int num_tdm_clients;
-+
-+static struct ucc_tdm_info utdm_primary_info = {
-+ .uf_info = {
-+ .tsa = 1,
-+ .cdp = 1,
-+ .cds = 1,
-+ .ctsp = 1,
-+ .ctss = 1,
-+ .revd = 1,
-+ .urfs = 0x128,
-+ .utfs = 0x128,
-+ .utfet = 0,
-+ .utftt = 0x128,
-+ .ufpt = 256,
-+ .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT,
-+ .tenc = UCC_FAST_TX_ENCODING_NRZ,
-+ .renc = UCC_FAST_RX_ENCODING_NRZ,
-+ .tcrc = UCC_FAST_16_BIT_CRC,
-+ .synl = UCC_FAST_SYNC_LEN_NOT_USED,
-+ },
-+ .ucc_busy = 0,
-+};
-+
-+static struct ucc_tdm_info utdm_info[8];
-+
-+static void dump_siram(struct tdm_ctrl *tdm_c)
-+{
-+#ifdef DEBUG
-+ int i;
-+ u16 phy_num_ts;
-+
-+ phy_num_ts = tdm_c->physical_num_ts;
-+
-+ pr_debug("SI TxRAM dump\n");
-+ /* each slot entry in SI RAM is of 2 bytes */
-+ for (i = 0; i < phy_num_ts * 2; i++)
-+ pr_debug("%x ", in_8(&qe_immr->sir.tx[i]));
-+ pr_debug("\nSI RxRAM dump\n");
-+ for (i = 0; i < phy_num_ts * 2; i++)
-+ pr_debug("%x ", in_8(&qe_immr->sir.rx[i]));
-+ pr_debug("\n");
-+#endif
-+}
-+
-+static void dump_ucc(struct tdm_ctrl *tdm_c)
-+{
-+#ifdef DEBUG
-+ struct ucc_transparent_pram *ucc_pram;
-+
-+ ucc_pram = tdm_c->ucc_pram;
-+
-+ pr_debug("%s Dumping UCC Registers\n", __FUNCTION__);
-+ ucc_fast_dump_regs(tdm_c->uf_private);
-+ pr_debug("%s Dumping UCC Parameter RAM\n", __FUNCTION__);
-+ pr_debug("rbase = 0x%x\n", in_be32(&ucc_pram->rbase));
-+ pr_debug("rbptr = 0x%x\n", in_be32(&ucc_pram->rbptr));
-+ pr_debug("mrblr = 0x%x\n", in_be16(&ucc_pram->mrblr));
-+ pr_debug("rbdlen = 0x%x\n", in_be16(&ucc_pram->rbdlen));
-+ pr_debug("rbdstat = 0x%x\n", in_be16(&ucc_pram->rbdstat));
-+ pr_debug("rstate = 0x%x\n", in_be32(&ucc_pram->rstate));
-+ pr_debug("rdptr = 0x%x\n", in_be32(&ucc_pram->rdptr));
-+ pr_debug("tbase = 0x%x\n", in_be32(&ucc_pram->tbase));
-+ pr_debug("tbptr = 0x%x\n", in_be32(&ucc_pram->tbptr));
-+ pr_debug("tbdlen = 0x%x\n", in_be16(&ucc_pram->tbdlen));
-+ pr_debug("tbdstat = 0x%x\n", in_be16(&ucc_pram->tbdstat));
-+ pr_debug("tstate = 0x%x\n", in_be32(&ucc_pram->tstate));
-+ pr_debug("tdptr = 0x%x\n", in_be32(&ucc_pram->tdptr));
-+#endif
-+}
-+
-+/*
-+ * For use when a framing bit is not present
-+ * Program current-route SI ram
-+ * Set SIxRAM TDMx
-+ * Entries must be in units of 8.
-+ * SIR_UCC -> Channel Select
-+ * SIR_CNT -> Number of bits or bytes
-+ * SIR_BYTE -> Byte or Bit resolution
-+ * SIR_LAST -> Indicates last entry in SIxRAM
-+ * SIR_IDLE -> The Tx data pin is Tri-stated and the Rx data pin is
-+ * ignored
-+ */
-+static void set_siram(struct tdm_ctrl *tdm_c, enum comm_dir dir)
-+{
-+ const u16 *mask;
-+ u16 temp_mask = 1;
-+ u16 siram_code = 0;
-+ u32 i, j, k;
-+ u32 ucc;
-+ u32 phy_num_ts;
-+
-+ phy_num_ts = tdm_c->physical_num_ts;
-+ ucc = tdm_c->ut_info->uf_info.ucc_num;
-+
-+ if (dir == COMM_DIR_RX)
-+ mask = tdm_c->rx_mask;
-+ else
-+ mask = tdm_c->tx_mask;
-+ k = 0;
-+ j = 0;
-+ for (i = 0; i < phy_num_ts; i++) {
-+ if ((mask[k] & temp_mask) == temp_mask)
-+ siram_code = SIR_UCC(ucc) | SIR_CNT(0) | SIR_BYTE;
-+ else
-+ siram_code = SIR_IDLE | SIR_CNT(0) | SIR_BYTE;
-+ if (dir == COMM_DIR_RX)
-+ out_be16((u16 *)&qe_immr->sir.rx[i * 2], siram_code);
-+ else
-+ out_be16((u16 *)&qe_immr->sir.tx[i * 2], siram_code);
-+ temp_mask = temp_mask << 1;
-+ j++;
-+ if (j >= 16) {
-+ j = 0;
-+ temp_mask = 0x0001;
-+ k++;
-+ }
-+ }
-+ siram_code = siram_code | SIR_LAST;
-+
-+ if (dir == COMM_DIR_RX)
-+ out_be16((u16 *)&qe_immr->sir.rx[(phy_num_ts - 1) * 2],
-+ siram_code);
-+ else
-+ out_be16((u16 *)&qe_immr->sir.tx[(phy_num_ts - 1) * 2],
-+ siram_code);
-+}
-+
-+static void config_si(struct tdm_ctrl *tdm_c)
-+{
-+ u8 rxsyncdelay, txsyncdelay, tdm_port;
-+ u16 sixmr_val = 0;
-+ u32 tdma_mode_off;
-+ u16 *si1_tdm_mode_reg;
-+
-+ tdm_port = tdm_c->tdm_port;
-+
-+ set_siram(tdm_c, COMM_DIR_RX);
-+
-+ set_siram(tdm_c, COMM_DIR_TX);
-+
-+ rxsyncdelay = tdm_c->cfg_ctrl.rx_fr_sync_delay;
-+ txsyncdelay = tdm_c->cfg_ctrl.tx_fr_sync_delay;
-+ if (tdm_c->cfg_ctrl.com_pin)
-+ sixmr_val |= SIMODE_CRT;
-+ if (tdm_c->cfg_ctrl.fr_sync_level == 1)
-+ sixmr_val |= SIMODE_SL;
-+ if (tdm_c->cfg_ctrl.clk_edge == 1)
-+ sixmr_val |= SIMODE_CE;
-+ if (tdm_c->cfg_ctrl.fr_sync_edge == 1)
-+ sixmr_val |= SIMODE_FE;
-+ sixmr_val |= (SIMODE_TFSD(txsyncdelay) | SIMODE_RFSD(rxsyncdelay));
-+
-+ tdma_mode_off = SI_TDM_MODE_REGISTER_OFFSET * tdm_c->tdm_port;
-+
-+ si1_tdm_mode_reg = (u8 *)&qe_immr->si1 + tdma_mode_off;
-+ out_be16(si1_tdm_mode_reg, sixmr_val);
-+
-+ dump_siram(tdm_c);
-+}
-+
-+static int tdm_init(struct tdm_ctrl *tdm_c)
-+{
-+ u32 tdm_port, ucc, act_num_ts;
-+ int ret, i, err;
-+ u32 cecr_subblock;
-+ u32 pram_offset;
-+ u32 rxbdt_offset;
-+ u32 txbdt_offset;
-+ u32 rx_ucode_buf_offset, tx_ucode_buf_offset;
-+ u16 bd_status, bd_len;
-+ enum qe_clock clock;
-+ struct qe_bd __iomem *rx_bd, *tx_bd;
-+
-+ tdm_port = tdm_c->tdm_port;
-+ ucc = tdm_c->ut_info->uf_info.ucc_num;
-+ act_num_ts = tdm_c->cfg_ctrl.active_num_ts;
-+
-+ /*
-+ * TDM Tx and Rx CLKs = 2048 KHz.
-+ */
-+ if (strstr(tdm_c->ut_info->uf_info.tdm_tx_clk, "BRG")) {
-+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_tx_clk);
-+ err = qe_setbrg(clock, 2048000, 1);
-+ if (err < 0) {
-+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
-+ tdm_c->ut_info->uf_info.tdm_tx_clk);
-+ return err;
-+ }
-+ }
-+ if (strstr(tdm_c->ut_info->uf_info.tdm_rx_clk, "BRG")) {
-+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_rx_clk);
-+ err = qe_setbrg(clock, 2048000, 1);
-+ if (err < 0) {
-+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
-+ tdm_c->ut_info->uf_info.tdm_rx_clk);
-+ return err;
-+ }
-+ }
-+ /*
-+ * TDM FSyncs = 4 KHz.
-+ */
-+ if (strstr(tdm_c->ut_info->uf_info.tdm_tx_sync, "BRG")) {
-+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_tx_sync);
-+ err = qe_setbrg(clock, 4000, 1);
-+ if (err < 0) {
-+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
-+ tdm_c->ut_info->uf_info.tdm_tx_sync);
-+ return err;
-+ }
-+ }
-+ if (strstr(tdm_c->ut_info->uf_info.tdm_rx_sync, "BRG")) {
-+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_rx_sync);
-+ err = qe_setbrg(clock, 4000, 1);
-+ if (err < 0) {
-+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
-+ tdm_c->ut_info->uf_info.tdm_rx_sync);
-+ return err;
-+ }
-+ }
-+
-+ tdm_c->ut_info->uf_info.uccm_mask = (u32)
-+ ((UCC_TRANS_UCCE_RXB | UCC_TRANS_UCCE_BSY) << 16);
-+
-+ if (ucc_fast_init(&(tdm_c->ut_info->uf_info), &tdm_c->uf_private)) {
-+ printk(KERN_ERR "%s: Failed to init uccf\n", __FUNCTION__);
-+ return -ENOMEM;
-+ }
-+
-+ ucc_fast_disable(tdm_c->uf_private, COMM_DIR_RX | COMM_DIR_TX);
-+
-+ /* Write to QE CECR, UCCx channel to Stop Transmission */
-+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
-+ qe_issue_cmd(QE_STOP_TX, cecr_subblock,
-+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
-+
-+ pram_offset = qe_muram_alloc(UCC_TRANSPARENT_PRAM_SIZE,
-+ ALIGNMENT_OF_UCC_SLOW_PRAM);
-+ if (IS_ERR_VALUE(pram_offset)) {
-+ printk(KERN_ERR "%s: Cannot allocate MURAM memory for"
-+ " transparent UCC\n", __FUNCTION__);
-+ ret = -ENOMEM;
-+ goto pram_alloc_error;
-+ }
-+
-+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
-+ qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
-+ QE_CR_PROTOCOL_UNSPECIFIED, pram_offset);
-+
-+ tdm_c->ucc_pram = qe_muram_addr(pram_offset);
-+ tdm_c->ucc_pram_offset = pram_offset;
-+
-+ /*
-+ * zero-out pram, this will also ensure RSTATE, TSTATE are cleared, also
-+ * DISFC & CRCEC counters will be initialized.
-+ */
-+ memset(tdm_c->ucc_pram, 0, sizeof(struct ucc_transparent_pram));
-+
-+ /* rbase, tbase alignment is 8. */
-+ rxbdt_offset = qe_muram_alloc(NR_BUFS * sizeof(struct qe_bd),
-+ QE_ALIGNMENT_OF_BD);
-+ if (IS_ERR_VALUE(rxbdt_offset)) {
-+ printk(KERN_ERR "%s: Cannot allocate MURAM memory for RxBDs\n",
-+ __FUNCTION__);
-+ ret = -ENOMEM;
-+ goto rxbd_alloc_error;
-+ }
-+ txbdt_offset = qe_muram_alloc(NR_BUFS * sizeof(struct qe_bd),
-+ QE_ALIGNMENT_OF_BD);
-+ if (IS_ERR_VALUE(txbdt_offset)) {
-+ printk(KERN_ERR "%s: Cannot allocate MURAM memory for TxBDs\n",
-+ __FUNCTION__);
-+ ret = -ENOMEM;
-+ goto txbd_alloc_error;
-+ }
-+ tdm_c->tx_bd = qe_muram_addr(txbdt_offset);
-+ tdm_c->rx_bd = qe_muram_addr(rxbdt_offset);
-+
-+ tdm_c->tx_bd_offset = txbdt_offset;
-+ tdm_c->rx_bd_offset = rxbdt_offset;
-+
-+ rx_bd = tdm_c->rx_bd;
-+ tx_bd = tdm_c->tx_bd;
-+
-+ out_be32(&tdm_c->ucc_pram->rbase, (u32) immrbar_virt_to_phys(rx_bd));
-+ out_be32(&tdm_c->ucc_pram->tbase, (u32) immrbar_virt_to_phys(tx_bd));
-+
-+ for (i = 0; i < NR_BUFS - 1; i++) {
-+ bd_status = (u16) ((R_E | R_CM | R_I) >> 16);
-+ bd_len = 0;
-+ out_be16(&rx_bd->length, bd_len);
-+ out_be16(&rx_bd->status, bd_status);
-+ out_be32(&rx_bd->buf,
-+ tdm_c->dma_input_addr + i * SAMPLE_DEPTH * act_num_ts);
-+ rx_bd += 1;
-+
-+ bd_status = (u16) ((T_R | T_CM) >> 16);
-+ bd_len = SAMPLE_DEPTH * act_num_ts;
-+ out_be16(&tx_bd->length, bd_len);
-+ out_be16(&tx_bd->status, bd_status);
-+ out_be32(&tx_bd->buf,
-+ tdm_c->dma_output_addr + i * SAMPLE_DEPTH * act_num_ts);
-+ tx_bd += 1;
-+ }
-+
-+ bd_status = (u16) ((R_E | R_CM | R_I | R_W) >> 16);
-+ bd_len = 0;
-+ out_be16(&rx_bd->length, bd_len);
-+ out_be16(&rx_bd->status, bd_status);
-+ out_be32(&rx_bd->buf,
-+ tdm_c->dma_input_addr + i * SAMPLE_DEPTH * act_num_ts);
-+
-+ bd_status = (u16) ((T_R | T_CM | T_W) >> 16);
-+ bd_len = SAMPLE_DEPTH * act_num_ts;
-+ out_be16(&tx_bd->length, bd_len);
-+ out_be16(&tx_bd->status, bd_status);
-+ out_be32(&tx_bd->buf,
-+ tdm_c->dma_output_addr + i * SAMPLE_DEPTH * act_num_ts);
-+
-+ config_si(tdm_c);
-+
-+ setbits32(&qe_immr->ic.qimr, (0x80000000UL >> ucc));
-+
-+ rx_ucode_buf_offset = qe_muram_alloc(32, 32);
-+ if (IS_ERR_VALUE(rx_ucode_buf_offset)) {
-+ printk(KERN_ERR "%s: Cannot allocate MURAM mem for Rx"
-+ " ucode buf\n", __FUNCTION__);
-+ ret = -ENOMEM;
-+ goto rxucode_buf_alloc_error;
-+ }
-+
-+ tx_ucode_buf_offset = qe_muram_alloc(32, 32);
-+ if (IS_ERR_VALUE(tx_ucode_buf_offset)) {
-+ printk(KERN_ERR "%s: Cannot allocate MURAM mem for Tx"
-+ " ucode buf\n", __FUNCTION__);
-+ ret = -ENOMEM;
-+ goto txucode_buf_alloc_error;
-+ }
-+ out_be16(&tdm_c->ucc_pram->riptr, (u16) rx_ucode_buf_offset);
-+ out_be16(&tdm_c->ucc_pram->tiptr, (u16) tx_ucode_buf_offset);
-+
-+ tdm_c->rx_ucode_buf_offset = rx_ucode_buf_offset;
-+ tdm_c->tx_ucode_buf_offset = tx_ucode_buf_offset;
-+
-+ /*
-+ * set the receive buffer descriptor maximum size to be
-+ * SAMPLE_DEPTH * number of active RX channels
-+ */
-+ out_be16(&tdm_c->ucc_pram->mrblr, (u16) SAMPLE_DEPTH * act_num_ts);
-+
-+ /*
-+ * enable snooping and BE byte ordering on the UCC pram's
-+ * tstate & rstate registers.
-+ */
-+ out_be32(&tdm_c->ucc_pram->tstate, 0x30000000UL);
-+ out_be32(&tdm_c->ucc_pram->rstate, 0x30000000UL);
-+
-+ /*Put UCC transparent controller into serial interface mode. */
-+ out_be32(&tdm_c->uf_regs->upsmr, 0);
-+
-+ /* Reset TX and RX for UCCx */
-+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
-+ qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
-+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
-+
-+ return 0;
-+
-+txucode_buf_alloc_error:
-+ qe_muram_free(rx_ucode_buf_offset);
-+rxucode_buf_alloc_error:
-+ qe_muram_free(txbdt_offset);
-+txbd_alloc_error:
-+ qe_muram_free(rxbdt_offset);
-+rxbd_alloc_error:
-+ qe_muram_free(pram_offset);
-+pram_alloc_error:
-+ ucc_fast_free(tdm_c->uf_private);
-+ return ret;
-+}
-+
-+static void tdm_deinit(struct tdm_ctrl *tdm_c)
-+{
-+ qe_muram_free(tdm_c->rx_ucode_buf_offset);
-+ qe_muram_free(tdm_c->tx_ucode_buf_offset);
-+
-+ if (tdm_c->rx_bd_offset) {
-+ qe_muram_free(tdm_c->rx_bd_offset);
-+ tdm_c->rx_bd = NULL;
-+ tdm_c->rx_bd_offset = 0;
-+ }
-+ if (tdm_c->tx_bd_offset) {
-+ qe_muram_free(tdm_c->tx_bd_offset);
-+ tdm_c->tx_bd = NULL;
-+ tdm_c->tx_bd_offset = 0;
-+ }
-+ if (tdm_c->ucc_pram_offset) {
-+ qe_muram_free(tdm_c->ucc_pram_offset);
-+ tdm_c->ucc_pram = NULL;
-+ tdm_c->ucc_pram_offset = 0;
-+ }
-+}
-+
-+
-+static irqreturn_t tdm_isr(int irq, void *dev_id)
-+{
-+ u8 *input_tdm_buffer, *output_tdm_buffer;
-+ u32 txb, rxb;
-+ u32 ucc;
-+ register u32 ucce = 0;
-+ struct tdm_ctrl *tdm_c;
-+ tdm_c = (struct tdm_ctrl *)dev_id;
-+
-+ tdm_c->tdm_icnt++;
-+ ucc = tdm_c->ut_info->uf_info.ucc_num;
-+ input_tdm_buffer = tdm_c->tdm_input_data;
-+ output_tdm_buffer = tdm_c->tdm_output_data;
-+
-+ if (in_be32(tdm_c->uf_private->p_ucce) &
-+ (UCC_TRANS_UCCE_BSY << 16)) {
-+ out_be32(tdm_c->uf_private->p_ucce,
-+ (UCC_TRANS_UCCE_BSY << 16));
-+ pr_info("%s: From tdm isr busy interrupt\n",
-+ __FUNCTION__);
-+ dump_ucc(tdm_c);
-+
-+ return IRQ_HANDLED;
-+ }
-+
-+ if (tdm_c->tdm_flag == 1) {
-+ /* track phases for Rx/Tx */
-+ tdm_c->phase_rx += 1;
-+ if (tdm_c->phase_rx == MAX_PHASE)
-+ tdm_c->phase_rx = 0;
-+
-+ tdm_c->phase_tx += 1;
-+ if (tdm_c->phase_tx == MAX_PHASE)
-+ tdm_c->phase_tx = 0;
-+
-+#ifdef CONFIG_TDM_HW_LB_TSA_SLIC
-+ {
-+ u32 temp_rx, temp_tx, phase_tx, phase_rx;
-+ int i;
-+ phase_rx = tdm_c->phase_rx;
-+ phase_tx = tdm_c->phase_tx;
-+ if (phase_rx == 0)
-+ phase_rx = MAX_PHASE;
-+ else
-+ phase_rx -= 1;
-+ if (phase_tx == 0)
-+ phase_tx = MAX_PHASE;
-+ else
-+ phase_tx -= 1;
-+ temp_rx = phase_rx * SAMPLE_DEPTH * ACTIVE_CH;
-+ temp_tx = phase_tx * SAMPLE_DEPTH * ACTIVE_CH;
-+
-+ /*check if loopback received data on TS0 is correct. */
-+ pr_debug("%s: check if loopback received data on TS0"
-+ " is correct\n", __FUNCTION__);
-+ pr_debug("%d,%d ", phase_rx, phase_tx);
-+ for (i = 0; i < 8; i++)
-+ pr_debug("%1d,%1d ",
-+ input_tdm_buffer[temp_rx + i],
-+ output_tdm_buffer[temp_tx + i]);
-+ pr_debug("\n");
-+ }
-+#endif
-+
-+ /* schedule BH */
-+ wake_up_interruptible(&tdm_c->wakeup_event);
-+ } else {
-+ if (tdm_c->tdm_icnt == STUTTER_INT_CNT) {
-+ txb = in_be32(&tdm_c->ucc_pram->tbptr) -
-+ in_be32(&tdm_c->ucc_pram->tbase);
-+ rxb = in_be32(&tdm_c->ucc_pram->rbptr) -
-+ in_be32(&tdm_c->ucc_pram->rbase);
-+ tdm_c->phase_tx = txb / sizeof(struct qe_bd);
-+ tdm_c->phase_rx = rxb / sizeof(struct qe_bd);
-+
-+#ifdef CONFIG_TDM_HW_LB_TSA_SLIC
-+ tdm_c->phase_tx = tdm_c->phase_rx;
-+#endif
-+
-+ /* signal "stuttering" period is over */
-+ tdm_c->tdm_flag = 1;
-+
-+ pr_debug("%s: stuttering period is over\n",
-+ __FUNCTION__);
-+
-+ if (in_be32(tdm_c->uf_private->p_ucce) &
-+ (UCC_TRANS_UCCE_TXE << 16)) {
-+ u32 cecr_subblock;
-+ out_be32(tdm_c->uf_private->p_ucce,
-+ (UCC_TRANS_UCCE_TXE << 16));
-+ pr_debug("%s: From tdm isr txe interrupt\n",
-+ __FUNCTION__);
-+
-+ cecr_subblock =
-+ ucc_fast_get_qe_cr_subblock(ucc);
-+ qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
-+ (u8) QE_CR_PROTOCOL_UNSPECIFIED,
-+ 0);
-+ }
-+ }
-+ }
-+
-+ ucce = (in_be32(tdm_c->uf_private->p_ucce)
-+ & in_be32(tdm_c->uf_private->p_uccm));
-+
-+ out_be32(tdm_c->uf_private->p_ucce, ucce);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int tdm_start(struct tdm_ctrl *tdm_c)
-+{
-+ if (request_irq(tdm_c->ut_info->uf_info.irq, tdm_isr,
-+ 0, "tdm", tdm_c)) {
-+ printk(KERN_ERR "%s: request_irq for tdm_isr failed\n",
-+ __FUNCTION__);
-+ return -ENODEV;
-+ }
-+
-+ ucc_fast_enable(tdm_c->uf_private, COMM_DIR_RX | COMM_DIR_TX);
-+
-+ pr_info("%s 16-bit linear pcm mode active with"
-+ " slots 0 & 2\n", __FUNCTION__);
-+
-+ dump_siram(tdm_c);
-+ dump_ucc(tdm_c);
-+
-+ setbits8(&(qe_immr->si1.siglmr1_h), (0x1 << tdm_c->tdm_port));
-+ pr_info("%s UCC based TDM enabled\n", __FUNCTION__);
-+
-+ return 0;
-+}
-+
-+static void tdm_stop(struct tdm_ctrl *tdm_c)
-+{
-+ u32 port, si;
-+ u32 ucc;
-+ u32 cecr_subblock;
-+
-+ port = tdm_c->tdm_port;
-+ si = tdm_c->si;
-+ ucc = tdm_c->ut_info->uf_info.ucc_num;
-+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
-+
-+ qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
-+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
-+ qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock,
-+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
-+
-+ clrbits8(&qe_immr->si1.siglmr1_h, (0x1 << port));
-+ ucc_fast_disable(tdm_c->uf_private, COMM_DIR_RX);
-+ ucc_fast_disable(tdm_c->uf_private, COMM_DIR_TX);
-+ free_irq(tdm_c->ut_info->uf_info.irq, tdm_c);
-+}
-+
-+
-+static void config_tdm(struct tdm_ctrl *tdm_c)
-+{
-+ u32 i, j, k;
-+
-+ j = 0;
-+ k = 0;
-+
-+ /* Set Mask Bits */
-+ for (i = 0; i < ACTIVE_CH; i++) {
-+ tdm_c->tx_mask[k] |= (1 << j);
-+ tdm_c->rx_mask[k] |= (1 << j);
-+ j++;
-+ if (j >= 16) {
-+ j = 0;
-+ k++;
-+ }
-+ }
-+ /* physical number of slots in a frame */
-+ tdm_c->physical_num_ts = NUM_TS;
-+
-+ /* common receive and transmit pins */
-+ tdm_c->cfg_ctrl.com_pin = 1;
-+
-+ /* L1R/TSYNC active logic "1" */
-+ tdm_c->cfg_ctrl.fr_sync_level = 0;
-+
-+ /*
-+ * TX data on rising edge of clock
-+ * RX data on falling edge
-+ */
-+ tdm_c->cfg_ctrl.clk_edge = 0;
-+
-+ /* Frame sync sampled on falling edge */
-+ tdm_c->cfg_ctrl.fr_sync_edge = 0;
-+
-+ /* no bit delay */
-+ tdm_c->cfg_ctrl.rx_fr_sync_delay = 0;
-+
-+ /* no bit delay */
-+ tdm_c->cfg_ctrl.tx_fr_sync_delay = 0;
-+
-+#ifndef CONFIG_TDM_HW_LB_TSA_SLIC
-+ if (tdm_c->leg_slic) {
-+ /* Need 1 bit delay for Legrity SLIC */
-+ tdm_c->cfg_ctrl.rx_fr_sync_delay = 1;
-+ tdm_c->cfg_ctrl.tx_fr_sync_delay = 1;
-+ pr_info("%s Delay for Legerity!\n", __FUNCTION__);
-+ }
-+#endif
-+
-+ tdm_c->cfg_ctrl.active_num_ts = ACTIVE_CH;
-+}
-+
-+static void tdm_read(u32 client_id, short chn_id, short *pcm_buffer,
-+ short len)
-+{
-+ int i;
-+ u32 phase_rx;
-+ /* point to where to start for the current phase data processing */
-+ u32 temp_rx;
-+
-+ struct tdm_ctrl *tdm_c = tdm_ctrl[client_id];
-+
-+ u16 *input_tdm_buffer =
-+ (u16 *)tdm_c->tdm_input_data;
-+
-+ phase_rx = tdm_c->phase_rx;
-+ if (phase_rx == 0)
-+ phase_rx = MAX_PHASE;
-+ else
-+ phase_rx -= 1;
-+
-+ temp_rx = phase_rx * SAMPLE_DEPTH * EFF_ACTIVE_CH;
-+
-+#ifdef UCC_CACHE_SNOOPING_DISABLED
-+ flush_dcache_range((size_t) &input_tdm_buffer[temp_rx],
-+ (size_t) &input_tdm_buffer[temp_rx +
-+ SAMPLE_DEPTH * ACTIVE_CH]);
-+#endif
-+ for (i = 0; i < len; i++)
-+ pcm_buffer[i] =
-+ input_tdm_buffer[i * EFF_ACTIVE_CH + temp_rx + chn_id];
-+
-+}
-+
-+static void tdm_write(u32 client_id, short chn_id, short *pcm_buffer,
-+ short len)
-+{
-+ int i;
-+ int phase_tx;
-+ u32 txb;
-+ /* point to where to start for the current phase data processing */
-+ int temp_tx;
-+ struct tdm_ctrl *tdm_c = tdm_ctrl[client_id];
-+
-+ u16 *output_tdm_buffer;
-+ output_tdm_buffer = (u16 *)tdm_c->tdm_output_data;
-+ txb = in_be32(&tdm_c->ucc_pram->tbptr) -
-+ in_be32(&tdm_c->ucc_pram->tbase);
-+ phase_tx = txb / sizeof(struct qe_bd);
-+
-+ if (phase_tx == 0)
-+ phase_tx = MAX_PHASE;
-+ else
-+ phase_tx -= 1;
-+
-+ temp_tx = phase_tx * SAMPLE_DEPTH * EFF_ACTIVE_CH;
-+
-+ for (i = 0; i < len; i++)
-+ output_tdm_buffer[i * EFF_ACTIVE_CH + temp_tx + chn_id] =
-+ pcm_buffer[i];
-+
-+#ifdef UCC_CACHE_SNOOPING_DISABLED
-+ flush_dcache_range((size_t) &output_tdm_buffer[temp_tx],
-+ (size_t) &output_tdm_buffer[temp_tx + SAMPLE_DEPTH *
-+ ACTIVE_CH]);
-+#endif
-+}
-+
-+
-+static int tdm_register_client(struct tdm_client *tdm_client)
-+{
-+ u32 i;
-+ if (num_tdm_clients == num_tdm_devices) {
-+ printk(KERN_ERR "all TDM devices busy\n");
-+ return -EBUSY;
-+ }
-+
-+ for (i = 0; i < num_tdm_devices; i++) {
-+ if (!tdm_ctrl[i]->device_busy) {
-+ tdm_ctrl[i]->device_busy = 1;
-+ break;
-+ }
-+ }
-+ num_tdm_clients++;
-+ tdm_client->client_id = i;
-+ tdm_client->tdm_read = tdm_read;
-+ tdm_client->tdm_write = tdm_write;
-+ tdm_client->wakeup_event =
-+ &(tdm_ctrl[i]->wakeup_event);
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(tdm_register_client);
-+
-+static int tdm_deregister_client(struct tdm_client *tdm_client)
-+{
-+ num_tdm_clients--;
-+ tdm_ctrl[tdm_client->client_id]->device_busy = 0;
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(tdm_deregister_client);
-+
-+static int ucc_tdm_probe(struct of_device *ofdev,
-+ const struct of_device_id *match)
-+{
-+ struct device_node *np = ofdev->node;
-+ struct resource res;
-+ const unsigned int *prop;
-+ u32 ucc_num, device_num, err, ret = 0;
-+ struct device_node *np_tmp;
-+ dma_addr_t physaddr;
-+ void *tdm_buff;
-+ struct ucc_tdm_info *ut_info;
-+
-+ prop = of_get_property(np, "device-id", NULL);
-+ if (prop == NULL) {
-+ printk(KERN_ERR "ucc_tdm: device-id missing\n");
-+ return -ENODEV;
-+ }
-+
-+ ucc_num = *prop - 1;
-+ if ((ucc_num < 0) || (ucc_num > 7))
-+ return -ENODEV;
-+
-+ ut_info = &utdm_info[ucc_num];
-+ if (ut_info->ucc_busy) {
-+ printk(KERN_ERR "ucc_tdm: UCC in use by another TDM driver"
-+ "instance\n");
-+ return -EBUSY;
-+ }
-+ if (num_tdm_devices == MAX_NUM_TDM_DEVICES) {
-+ printk(KERN_ERR "ucc_tdm: All TDM devices already"
-+ " initialized\n");
-+ return -ENODEV;
-+ }
-+
-+ ut_info->ucc_busy = 1;
-+ tdm_ctrl[num_tdm_devices++] =
-+ kzalloc(sizeof(struct tdm_ctrl), GFP_KERNEL);
-+ if (!tdm_ctrl[num_tdm_devices - 1]) {
-+ printk(KERN_ERR "ucc_tdm: no memory to allocate for"
-+ " tdm control structure\n");
-+ num_tdm_devices--;
-+ return -ENOMEM;
-+ }
-+ device_num = num_tdm_devices - 1;
-+
-+ tdm_ctrl[device_num]->device = &ofdev->dev;
-+ tdm_ctrl[device_num]->ut_info = ut_info;
-+
-+ tdm_ctrl[device_num]->ut_info->uf_info.ucc_num = ucc_num;
-+
-+ prop = of_get_property(np, "fsl,tdm-num", NULL);
-+ if (prop == NULL) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ tdm_ctrl[device_num]->tdm_port = *prop - 1;
-+
-+ if (tdm_ctrl[device_num]->tdm_port > 3) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ prop = of_get_property(np, "fsl,si-num", NULL);
-+ if (prop == NULL) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ tdm_ctrl[device_num]->si = *prop - 1;
-+
-+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_clk =
-+ of_get_property(np, "fsl,tdm-tx-clk", NULL);
-+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_clk == NULL) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_clk =
-+ of_get_property(np, "fsl,tdm-rx-clk", NULL);
-+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_clk == NULL) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_sync =
-+ of_get_property(np, "fsl,tdm-tx-sync", NULL);
-+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_sync == NULL) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_sync =
-+ of_get_property(np, "fsl,tdm-rx-sync", NULL);
-+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_sync == NULL) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ tdm_ctrl[device_num]->ut_info->uf_info.irq =
-+ irq_of_parse_and_map(np, 0);
-+ err = of_address_to_resource(np, 0, &res);
-+ if (err) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+ tdm_ctrl[device_num]->ut_info->uf_info.regs = res.start;
-+ tdm_ctrl[device_num]->uf_regs = of_iomap(np, 0);
-+
-+ np_tmp = NULL;
-+ np_tmp = of_find_compatible_node(np_tmp, "slic", "legerity-slic");
-+ if (np_tmp != NULL) {
-+ tdm_ctrl[device_num]->leg_slic = 1;
-+ of_node_put(np_tmp);
-+ } else
-+ tdm_ctrl[device_num]->leg_slic = 0;
-+
-+ config_tdm(tdm_ctrl[device_num]);
-+
-+ tdm_buff = dma_alloc_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH *
-+ tdm_ctrl[device_num]->cfg_ctrl.active_num_ts,
-+ &physaddr, GFP_KERNEL);
-+ if (!tdm_buff) {
-+ printk(KERN_ERR "ucc-tdm: could not allocate buffer"
-+ "descriptors\n");
-+ ret = -ENOMEM;
-+ goto alloc_error;
-+ }
-+
-+ tdm_ctrl[device_num]->tdm_input_data = tdm_buff;
-+ tdm_ctrl[device_num]->dma_input_addr = physaddr;
-+
-+ tdm_ctrl[device_num]->tdm_output_data = tdm_buff + NR_BUFS *
-+ SAMPLE_DEPTH * tdm_ctrl[device_num]->cfg_ctrl.active_num_ts;
-+ tdm_ctrl[device_num]->dma_output_addr = physaddr + NR_BUFS *
-+ SAMPLE_DEPTH * tdm_ctrl[device_num]->cfg_ctrl.active_num_ts;
-+
-+ init_waitqueue_head(&(tdm_ctrl[device_num]->wakeup_event));
-+
-+ ret = tdm_init(tdm_ctrl[device_num]);
-+ if (ret != 0)
-+ goto tdm_init_error;
-+
-+ ret = tdm_start(tdm_ctrl[device_num]);
-+ if (ret != 0)
-+ goto tdm_start_error;
-+
-+ dev_set_drvdata(&(ofdev->dev), tdm_ctrl[device_num]);
-+
-+ pr_info("%s UCC based tdm module installed\n", __FUNCTION__);
-+ return 0;
-+
-+tdm_start_error:
-+ tdm_deinit(tdm_ctrl[device_num]);
-+tdm_init_error:
-+ dma_free_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH *
-+ tdm_ctrl[device_num]->cfg_ctrl.active_num_ts,
-+ tdm_ctrl[device_num]->tdm_input_data,
-+ tdm_ctrl[device_num]->dma_input_addr);
-+
-+alloc_error:
-+ irq_dispose_mapping(tdm_ctrl[device_num]->ut_info->uf_info.irq);
-+ iounmap(tdm_ctrl[device_num]->uf_regs);
-+
-+get_property_error:
-+ num_tdm_devices--;
-+ kfree(tdm_ctrl[device_num]);
-+ ut_info->ucc_busy = 0;
-+ return ret;
-+}
-+
-+static int ucc_tdm_remove(struct of_device *ofdev)
-+{
-+ struct tdm_ctrl *tdm_c;
-+ struct ucc_tdm_info *ut_info;
-+ u32 ucc_num;
-+
-+ tdm_c = dev_get_drvdata(&(ofdev->dev));
-+ dev_set_drvdata(&(ofdev->dev), NULL);
-+ ucc_num = tdm_c->ut_info->uf_info.ucc_num;
-+ ut_info = &utdm_info[ucc_num];
-+ tdm_stop(tdm_c);
-+ tdm_deinit(tdm_c);
-+
-+ ucc_fast_free(tdm_c->uf_private);
-+
-+ dma_free_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH *
-+ tdm_c->cfg_ctrl.active_num_ts,
-+ tdm_c->tdm_input_data,
-+ tdm_c->dma_input_addr);
-+
-+ irq_dispose_mapping(tdm_c->ut_info->uf_info.irq);
-+ iounmap(tdm_c->uf_regs);
-+
-+ num_tdm_devices--;
-+ kfree(tdm_c);
-+
-+ ut_info->ucc_busy = 0;
-+
-+ pr_info("%s UCC based tdm module uninstalled\n", __FUNCTION__);
-+ return 0;
-+}
-+
-+const struct of_device_id ucc_tdm_match[] = {
-+ { .type = "tdm", .compatible = "fsl,ucc-tdm", },
-+ {},
-+};
-+
-+MODULE_DEVICE_TABLE(of, ucc_tdm_match);
-+
-+static struct of_platform_driver ucc_tdm_driver = {
-+ .name = DRV_NAME,
-+ .match_table = ucc_tdm_match,
-+ .probe = ucc_tdm_probe,
-+ .remove = ucc_tdm_remove,
-+ .driver = {
-+ .name = DRV_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init ucc_tdm_init(void)
-+{
-+ u32 i;
-+
-+ pr_info("ucc_tdm: " DRV_DESC "\n");
-+ for (i = 0; i < 8; i++)
-+ memcpy(&(utdm_info[i]), &utdm_primary_info,
-+ sizeof(utdm_primary_info));
-+
-+ return of_register_platform_driver(&ucc_tdm_driver);
-+}
-+
-+static void __exit ucc_tdm_exit(void)
-+{
-+ of_unregister_platform_driver(&ucc_tdm_driver);
-+}
-+
-+module_init(ucc_tdm_init);
-+module_exit(ucc_tdm_exit);
-+MODULE_AUTHOR("Freescale Semiconductor, Inc");
-+MODULE_DESCRIPTION(DRV_DESC);
-+MODULE_LICENSE("GPL");
---- a/drivers/misc/Makefile
-+++ b/drivers/misc/Makefile
-@@ -10,6 +10,7 @@ obj-$(CONFIG_INTEL_MID_PTI) += pti.o
- obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
- obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
- obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
-+obj-$(CONFIG_UCC_TDM) += ucc_tdm.o
- obj-$(CONFIG_BMP085) += bmp085.o
- obj-$(CONFIG_BMP085_I2C) += bmp085-i2c.o
- obj-$(CONFIG_BMP085_SPI) += bmp085-spi.o
---- a/drivers/misc/Kconfig
-+++ b/drivers/misc/Kconfig
-@@ -210,6 +210,20 @@ config ATMEL_SSC
-
- If unsure, say N.
-
-+config UCC_TDM
-+ tristate "Freescale UCC TDM Driver"
-+ depends on QUICC_ENGINE && UCC_FAST
-+ default n
-+ help
-+ The TDM driver is for UCC based TDM devices for example, TDM device on
-+ MPC832x RDB. Select it to run PowerVoIP on MPC832x RDB board.
-+ The TDM driver can interface with SLIC kind of devices to transmit
-+ and receive TDM samples. The TDM driver receives Time Division
-+ multiplexed samples(for different channels) from the SLIC device,
-+ demutiplexes them and sends them to the upper layers. At the transmit
-+ end the TDM drivers receives samples for different channels, it
-+ multiplexes them and sends them to the SLIC device.
-+
- config ENCLOSURE_SERVICES
- tristate "Enclosure Services"
- default n
---- a/arch/powerpc/include/asm/ucc_fast.h
-+++ b/arch/powerpc/include/asm/ucc_fast.h
-@@ -150,6 +150,10 @@ struct ucc_fast_info {
- enum ucc_fast_rx_decoding_method renc;
- enum ucc_fast_transparent_tcrc tcrc;
- enum ucc_fast_sync_len synl;
-+ char *tdm_rx_clk;
-+ char *tdm_tx_clk;
-+ char *tdm_rx_sync;
-+ char *tdm_tx_sync;
- };
-
- struct ucc_fast_private {
---- a/arch/powerpc/include/asm/qe.h
-+++ b/arch/powerpc/include/asm/qe.h
-@@ -670,6 +670,14 @@ struct ucc_slow_pram {
- #define UCC_GETH_UCCE_RXF1 0x00000002
- #define UCC_GETH_UCCE_RXF0 0x00000001
-
-+/* Transparent UCC Event Register (UCCE) */
-+#define UCC_TRANS_UCCE_GRA 0x0080
-+#define UCC_TRANS_UCCE_TXE 0x0010
-+#define UCC_TRANS_UCCE_RXF 0x0008
-+#define UCC_TRANS_UCCE_BSY 0x0004
-+#define UCC_TRANS_UCCE_TXB 0x0002
-+#define UCC_TRANS_UCCE_RXB 0x0001
-+
- /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
- #define UCC_UART_UPSMR_FLC 0x8000
- #define UCC_UART_UPSMR_SL 0x4000
+++ /dev/null
---- a/arch/powerpc/boot/Makefile
-+++ b/arch/powerpc/boot/Makefile
-@@ -89,7 +89,8 @@ src-plat-$(CONFIG_44x) += treeboot-ebony
- src-plat-$(CONFIG_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
- src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
- src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
--src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c
-+src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c \
-+ rb600.c rb333.c
- src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
- src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
- cuboot-c2k.c gamecube-head.S \
-@@ -261,6 +262,8 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.
- image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds
- image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds
- image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
-+image-$(CONFIG_RB_PPC) += dtbImage.rb600 \
-+ dtbImage.rb333
-
- # Board ports in arch/powerpc/platform/85xx/Kconfig
- image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
---- /dev/null
-+++ b/arch/powerpc/boot/dts/rb600.dts
-@@ -0,0 +1,283 @@
-+/*
-+ * RouterBOARD 600 series Device Tree Source
-+ *
-+ * Copyright 2009 Michael Guntsche <mike@it-loops.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+/dts-v1/;
-+
-+/ {
-+ model = "RB600";
-+ compatible = "MPC83xx";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ aliases {
-+ ethernet0 = &enet0;
-+ ethernet1 = &enet1;
-+ pci0 = &pci0;
-+ };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
-+ linux,stdout-path = "/soc8343@e0000000/serial@4500";
-+ };
-+
-+ cpus {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ PowerPC,8343E@0 {
-+ device_type = "cpu";
-+ reg = <0x0>;
-+ d-cache-line-size = <0x20>;
-+ i-cache-line-size = <0x20>;
-+ d-cache-size = <0x8000>;
-+ i-cache-size = <0x8000>;
-+ timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
-+ clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
-+ };
-+ };
-+
-+ memory {
-+ device_type = "memory";
-+ reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
-+ };
-+
-+ cf@f9200000 {
-+ lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
-+ interrupt-at-level = <0x0>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x16 0x8>;
-+ lbc_extra_divider = <0x1>;
-+ reg = <0xf9200000 0x200000>;
-+ device_type = "rb,cf";
-+ };
-+
-+ cf@f9000000 {
-+ lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
-+ interrupt-at-level = <0x0>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x14 0x8>;
-+ lbc_extra_divider = <0x1>;
-+ reg = <0xf9000000 0x200000>;
-+ device_type = "rb,cf";
-+ };
-+
-+ flash {
-+ reg = <0xff800000 0x20000>;
-+ };
-+
-+ nnand {
-+ reg = <0xf0000000 0x1000>;
-+ };
-+
-+ nand {
-+ ale = <&gpio 0x6>;
-+ cle = <&gpio 0x5>;
-+ nce = <&gpio 0x4>;
-+ rdy = <&gpio 0x3>;
-+ reg = <0xf8000000 0x1000>;
-+ device_type = "rb,nand";
-+ };
-+
-+ fancon {
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x17 0x8>;
-+ sense = <&gpio 0x7>;
-+ fan_on = <&gpio 0x9>;
-+ };
-+
-+ pci0: pci@e0008500 {
-+ device_type = "pci";
-+ compatible = "fsl,mpc8349-pci";
-+ reg = <0xe0008500 0x100 0xe0008300 0x8>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
-+ bus-range = <0x0 0x0>;
-+ interrupt-map = <
-+ 0x5800 0x0 0x0 0x1 &ipic 0x15 0x8
-+ 0x6000 0x0 0x0 0x1 &ipic 0x30 0x8
-+ 0x6000 0x0 0x0 0x2 &ipic 0x11 0x8
-+ 0x6800 0x0 0x0 0x1 &ipic 0x11 0x8
-+ 0x6800 0x0 0x0 0x2 &ipic 0x12 0x8
-+ 0x7000 0x0 0x0 0x1 &ipic 0x12 0x8
-+ 0x7000 0x0 0x0 0x2 &ipic 0x13 0x8
-+ 0x7800 0x0 0x0 0x1 &ipic 0x13 0x8
-+ 0x7800 0x0 0x0 0x2 &ipic 0x30 0x8
-+ 0x8000 0x0 0x0 0x1 &ipic 0x30 0x8
-+ 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
-+ 0x8000 0x0 0x0 0x3 &ipic 0x11 0x8
-+ 0x8000 0x0 0x0 0x4 &ipic 0x13 0x8
-+ 0xa000 0x0 0x0 0x1 &ipic 0x30 0x8
-+ 0xa000 0x0 0x0 0x2 &ipic 0x11 0x8
-+ 0xa000 0x0 0x0 0x3 &ipic 0x12 0x8
-+ 0xa000 0x0 0x0 0x4 &ipic 0x13 0x8
-+ 0xa800 0x0 0x0 0x1 &ipic 0x11 0x8
-+ 0xa800 0x0 0x0 0x2 &ipic 0x12 0x8
-+ 0xa800 0x0 0x0 0x3 &ipic 0x13 0x8
-+ 0xa800 0x0 0x0 0x4 &ipic 0x30 0x8>;
-+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-+ interrupt-parent = <&ipic>;
-+ };
-+
-+ soc8343@e0000000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ device_type = "soc";
-+ compatible = "simple-bus";
-+ ranges = <0x0 0xe0000000 0x100000>;
-+ reg = <0xe0000000 0x200>;
-+ bus-frequency = <0x1>;
-+
-+ led {
-+ user_led = <0x400 0x8>;
-+ };
-+
-+ beeper {
-+ reg = <0x500 0x100>;
-+ };
-+
-+ gpio: gpio@0 {
-+ reg = <0xc08 0x4>;
-+ device-id = <0x0>;
-+ compatible = "gpio";
-+ device_type = "gpio";
-+ };
-+
-+ dma@82a8 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
-+ reg = <0x82a8 4>;
-+ ranges = <0 0x8100 0x1a8>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ cell-index = <0>;
-+ dma-channel@0 {
-+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0 0x80>;
-+ cell-index = <0>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ dma-channel@80 {
-+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0x80 0x80>;
-+ cell-index = <1>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ dma-channel@100 {
-+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0x100 0x80>;
-+ cell-index = <2>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ dma-channel@180 {
-+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0x180 0x28>;
-+ cell-index = <3>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ };
-+
-+ enet0: ethernet@25000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ cell-index = <0>;
-+ phy-handle = <&phy0>;
-+ tbi-handle = <&tbi0>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
-+ local-mac-address = [00 00 00 00 00 00];
-+ reg = <0x25000 0x1000>;
-+ ranges = <0x0 0x25000 0x1000>;
-+ compatible = "gianfar";
-+ model = "TSEC";
-+ device_type = "network";
-+
-+ mdio@520 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "fsl,gianfar-tbi";
-+ reg = <0x520 0x20>;
-+
-+ tbi0: tbi-phy@11 {
-+ reg = <0x11>;
-+ device_type = "tbi-phy";
-+ };
-+ };
-+ };
-+
-+ enet1: ethernet@24000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ cell-index = <1>;
-+ phy-handle = <&phy1>;
-+ tbi-handle = <&tbi1>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
-+ local-mac-address = [00 00 00 00 00 00];
-+ reg = <0x24000 0x1000>;
-+ ranges = <0x0 0x24000 0x1000>;
-+ compatible = "gianfar";
-+ model = "TSEC";
-+ device_type = "network";
-+
-+ mdio@520 {
-+ #size-cells = <0x0>;
-+ #address-cells = <0x1>;
-+ reg = <0x520 0x20>;
-+ compatible = "fsl,gianfar-mdio";
-+
-+ phy0: ethernet-phy@0 {
-+ device_type = "ethernet-phy";
-+ reg = <0x0>;
-+ };
-+
-+ phy1: ethernet-phy@1 {
-+ device_type = "ethernet-phy";
-+ reg = <0x1>;
-+ };
-+
-+ tbi1: tbi-phy@11 {
-+ reg = <0x11>;
-+ device_type = "tbi-phy";
-+ };
-+ };
-+ };
-+
-+ ipic: pic@700 {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <2>;
-+ reg = <0x700 0x100>;
-+ device_type = "ipic";
-+ };
-+
-+ serial@4500 {
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x9 0x8>;
-+ clock-frequency = <0xfe4f840>;
-+ reg = <0x4500 0x100>;
-+ compatible = "ns16550";
-+ device_type = "serial";
-+ };
-+
-+ wdt@200 {
-+ reg = <0x200 0x100>;
-+ compatible = "mpc83xx_wdt";
-+ device_type = "watchdog";
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/powerpc/boot/rb600.c
-@@ -0,0 +1,70 @@
-+/*
-+ * The RouterBOARD platform -- for booting RB600(A) RouterBOARDs.
-+ *
-+ * Author: Michael Guntsche <mike@it-loops.com>
-+ *
-+ * Copyright (c) 2009 Michael Guntsche
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include "ops.h"
-+#include "types.h"
-+#include "io.h"
-+#include "stdio.h"
-+#include <libfdt.h>
-+
-+BSS_STACK(4*1024);
-+
-+u64 memsize64;
-+const void *fw_dtb;
-+
-+static void rb600_fixups(void)
-+{
-+ const u32 *reg, *timebase, *clock;
-+ int node, size;
-+
-+ dt_fixup_memory(0, memsize64);
-+
-+ /* Set the MAC addresses. */
-+ node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@24000");
-+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
-+ dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg);
-+
-+ node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@25000");
-+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
-+ dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg);
-+
-+ /* Find the CPU timebase and clock frequencies. */
-+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
-+ timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
-+ clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
-+ dt_fixup_cpu_clocks(*clock, *timebase, 0);
-+
-+}
-+
-+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-+ unsigned long r6, unsigned long r7)
-+{
-+ const u32 *reg;
-+ int node, size;
-+
-+ fw_dtb = (const void *)r3;
-+
-+ /* Find the memory range. */
-+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
-+ reg = fdt_getprop(fw_dtb, node, "reg", &size);
-+ memsize64 = reg[1];
-+
-+ /* Now we have the memory size; initialize the heap. */
-+ simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
-+
-+ /* Prepare the device tree and find the console. */
-+ fdt_init(_dtb_start);
-+ serial_console_init();
-+
-+ /* Remaining fixups... */
-+ platform_ops.fixups = rb600_fixups;
-+}
---- a/arch/powerpc/boot/wrapper
-+++ b/arch/powerpc/boot/wrapper
-@@ -217,7 +217,7 @@ ps3)
- make_space=n
- pie=
- ;;
--ep88xc|ep405|ep8248e)
-+ep88xc|ep405|ep8248e|rb600|rb333)
- platformo="$object/fixed-head.o $object/$platform.o"
- binary=y
- ;;
---- a/arch/powerpc/platforms/83xx/Kconfig
-+++ b/arch/powerpc/platforms/83xx/Kconfig
-@@ -38,6 +38,15 @@ config MPC832x_RDB
- help
- This option enables support for the MPC8323 RDB board.
-
-+config RB_PPC
-+ bool "MikroTik RouterBOARD 333/600 series"
-+ select DEFAULT_UIMAGE
-+ select QUICC_ENGINE
-+ select PPC_MPC832x
-+ select PPC_MPC834x
-+ help
-+ This option enables support for MikroTik RouterBOARD 333/600 series boards.
-+
- config MPC834x_MDS
- bool "Freescale MPC834x MDS"
- select DEFAULT_UIMAGE
---- /dev/null
-+++ b/arch/powerpc/boot/dts/rb333.dts
-@@ -0,0 +1,426 @@
-+
-+/*
-+ * RouterBOARD 333 series Device Tree Source
-+ *
-+ * Copyright 2010 Alexandros C. Couloumbis <alex@ozo.com>
-+ * Copyright 2009 Michael Guntsche <mike@it-loops.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
-+ * Warning (ranges_format): "ranges" property in /qe@e0100000/muram@10000 has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1)
-+ * Warning (avoid_default_addr_size): Relying on default #address-cells value for /qe@e0100000/muram@10000/data-only@0
-+ * Warning (avoid_default_addr_size): Relying on default #size-cells value for /qe@e0100000/muram@10000/data-only@0
-+ * Warning (obsolete_chosen_interrupt_controller): /chosen has obsolete "interrupt-controller" property
-+ *
-+ */
-+
-+
-+/dts-v1/;
-+
-+/ {
-+ model = "RB333";
-+ compatible = "MPC83xx";
-+ #size-cells = <1>;
-+ #address-cells = <1>;
-+
-+ aliases {
-+ ethernet0 = &enet0;
-+ ethernet1 = &enet1;
-+ ethernet2 = &enet2;
-+ pci0 = &pci0;
-+ };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
-+ // linux,platform = <0x8062>;
-+ // linux,initrd = <0x488000 0x0>;
-+ linux,stdout-path = "/soc8323@e0000000/serial@4500";
-+ // interrupt-controller = <&ipic>;
-+ };
-+
-+ cpus {
-+ #cpus = <1>;
-+ #size-cells = <0>;
-+ #address-cells = <1>;
-+
-+ PowerPC,8323E@0 {
-+ device_type = "cpu";
-+ reg = <0x0>;
-+ i-cache-size = <0x4000>;
-+ d-cache-size = <0x4000>;
-+ i-cache-line-size = <0x20>;
-+ d-cache-line-size = <0x20>;
-+ // clock-frequency = <0x13de3650>;
-+ // timebase-frequency = <0x1fc9f08>;
-+ timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
-+ clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
-+ 32-bit;
-+ };
-+ };
-+
-+ memory {
-+ device_type = "memory";
-+ reg = <0x0 0x4000000>;
-+ // reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
-+ };
-+
-+ flash {
-+ reg = <0xfe000000 0x20000>;
-+ };
-+
-+ nand {
-+ ale = <&gpio2 0x3>;
-+ cle = <&gpio2 0x2>;
-+ nce = <&gpio2 0x1>;
-+ rdy = <&gpio2 0x0>;
-+ reg = <0xf8000000 0x1000>;
-+ device_type = "rb,nand";
-+ };
-+
-+ nnand {
-+ reg = <0xf0000000 0x1000>;
-+ };
-+
-+ voltage {
-+ voltage_gpio = <&gpio3 0x11>;
-+ };
-+
-+ fancon {
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x14 0x8>;
-+ fan_on = <&gpio0 0x10>;
-+ };
-+
-+ soc8323@e0000000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ device_type = "soc";
-+ compatible = "simple-bus";
-+ ranges = <0x0 0xe0000000 0x00100000>;
-+ reg = <0xe0000000 0x00000200>;
-+ bus-frequency = <1>;
-+
-+ wdt@200 {
-+ device_type = "watchdog";
-+ compatible = "mpc83xx_wdt";
-+ reg = <0x200 0x100>;
-+ };
-+
-+ ipic:pic@700 {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <2>;
-+ reg = <0x700 0x100>;
-+ device_type = "ipic";
-+ };
-+
-+ par_io@1400 {
-+ num-ports = <4>;
-+ device_type = "par_io";
-+ reg = <0x1400 0x100>;
-+
-+ ucc2pio: ucc_pin@02 {
-+ pio-map = <
-+ /* port pin dir open_drain assignment has_irq */
-+ 3 4 3 0 2 0
-+ 3 5 1 0 2 0
-+ 0 18 1 0 1 0
-+ 0 19 1 0 1 0
-+ 0 20 1 0 1 0
-+ 0 21 1 0 1 0
-+ 0 30 1 0 1 0
-+ 3 6 2 0 1 0
-+ 0 29 2 0 1 0
-+ 0 31 2 0 1 0
-+ 0 22 2 0 1 0
-+ 0 23 2 0 1 0
-+ 0 24 2 0 1 0
-+ 0 25 2 0 1 0
-+ 0 28 2 0 1 0
-+ 0 26 2 0 1 0
-+ 3 31 2 0 1 0>;
-+ };
-+
-+ ucc3pio: ucc_pin@03 {
-+ pio-map = <
-+ /* port pin dir open_drain assignment has_irq */
-+ 1 0 1 0 1 0
-+ 1 1 1 0 1 0
-+ 1 2 1 0 1 0
-+ 1 3 1 0 1 0
-+ 1 12 1 0 1 0
-+ 3 24 2 0 1 0
-+ 1 11 2 0 1 0
-+ 1 13 2 0 1 0
-+ 1 4 2 0 1 0
-+ 1 5 2 0 1 0
-+ 1 6 2 0 1 0
-+ 1 7 2 0 1 0
-+ 1 10 2 0 1 0
-+ 1 8 2 0 1 0
-+ 3 29 2 0 1 0>;
-+ };
-+
-+ ucc4pio: ucc_pin@04 {
-+ pio-map = <
-+ /* port pin dir open_drain assignment has_irq */
-+ 1 18 1 0 1 0
-+ 1 19 1 0 1 0
-+ 1 20 1 0 1 0
-+ 1 21 1 0 1 0
-+ 1 30 1 0 1 0
-+ 3 20 2 0 1 0
-+ 1 30 2 0 1 0
-+ 1 31 2 0 1 0
-+ 1 22 2 0 1 0
-+ 1 23 2 0 1 0
-+ 1 24 2 0 1 0
-+ 1 25 2 0 1 0
-+ 1 28 2 0 1 0
-+ 1 26 2 0 1 0
-+ 3 21 2 0 1 0>;
-+ };
-+ };
-+
-+ serial0: serial@4500 {
-+ cell-index = <0>;
-+ device_type = "serial";
-+ compatible = "fsl,ns16550", "ns16550";
-+ reg = <0x4500 0x100>;
-+ clock-frequency = <0x7f27c20>;
-+ interrupts = <9 0x8>;
-+ interrupt-parent = <&ipic>;
-+ };
-+
-+ dma@82a8 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
-+ reg = <0x82a8 4>;
-+ ranges = <0 0x8100 0x1a8>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ cell-index = <0>;
-+ dma-channel@0 {
-+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0 0x80>;
-+ cell-index = <0>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ dma-channel@80 {
-+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0x80 0x80>;
-+ cell-index = <1>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ dma-channel@100 {
-+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0x100 0x80>;
-+ cell-index = <2>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ dma-channel@180 {
-+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0x180 0x28>;
-+ cell-index = <3>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ };
-+
-+ beeper {
-+ gpio = <&gpio3 0x12>;
-+ reg = <0x500 0x100>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x48 0x8>;
-+ };
-+
-+ gpio3: gpio@3 {
-+ reg = <0x144c 0x4>;
-+ device-id = <0x3>;
-+ compatible = "qe_gpio";
-+ device_type = "gpio";
-+ };
-+
-+ gpio2: gpio@2 {
-+ reg = <0x1434 0x4>;
-+ device-id = <0x2>;
-+ compatible = "qe_gpio";
-+ device_type = "gpio";
-+ };
-+
-+ gpio0: gpio@0 {
-+ reg = <0x1404 0x4>;
-+ device-id = <0x0>;
-+ compatible = "qe_gpio";
-+ device_type = "gpio";
-+ };
-+ };
-+
-+ pci0: pci@e0008500 {
-+ device_type = "pci";
-+ // compatible = "83xx";
-+ compatible = "fsl,mpc8349-pci";
-+ reg = <0xe0008500 0x100 0xe0008300 0x8>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ // clock-frequency = <0>;
-+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
-+ bus-range = <0x0 0x0>;
-+ interrupt-map = <
-+ /* IDSEL 0x10 AD16 miniPCI slot 0 */
-+ 0x8000 0x0 0x0 0x1 &ipic 0x11 0x8
-+ 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
-+
-+ /* IDSEL 0x11 AD17 miniPCI slot 1 */
-+ 0x8800 0x0 0x0 0x1 &ipic 0x12 0x8
-+ 0x8800 0x0 0x0 0x2 &ipic 0x13 0x8
-+
-+ /* IDSEL 0x12 AD18 miniPCI slot 2 */
-+ 0x9000 0x0 0x0 0x1 &ipic 0x13 0x8
-+ 0x9000 0x0 0x0 0x2 &ipic 0x11 0x8>;
-+
-+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-+ interrupt-parent = <&ipic>;
-+ // interrupts = <66 0x8>;
-+ };
-+
-+ qe@e0100000 {
-+ reg = <0xe0100000 0x480>;
-+ ranges = <0x0 0xe0100000 0x100000>;
-+ model = "QE";
-+ device_type = "qe";
-+ compatible = "fsl,qe";
-+ #size-cells = <1>;
-+ #address-cells = <1>;
-+ brg-frequency = <0>;
-+ bus-frequency = <0>;
-+ // bus-frequency = <198000000>;
-+ fsl,qe-num-riscs = <1>;
-+ fsl,qe-num-snums = <28>;
-+
-+ qeic: qeic@80 {
-+ interrupt-controller;
-+ compatible = "fsl,qe-ic";
-+ big-endian;
-+ built-in;
-+ reg = <0x80 0x80>;
-+ #interrupt-cells = <1>;
-+ #address-cells = <0>;
-+ device_type = "qeic";
-+ interrupts = <0x20 0x8 0x21 0x8>;
-+ interrupt-parent = <&ipic>;
-+ };
-+
-+ mdio@2120 {
-+ compatible = "ucc_geth_phy";
-+ device_type = "mdio";
-+ reg = <0x3120 0x18>;
-+ #size-cells = <0>;
-+ #address-cells = <1>;
-+
-+ phy3: ethernet-phy@03 {
-+ // interface = <0x3>;
-+ device_type = "ethernet-phy";
-+ reg = <0x3>;
-+ };
-+
-+ phy2: ethernet-phy@02 {
-+ // interface = <0x3>;
-+ device_type = "ethernet-phy";
-+ reg = <0x2>;
-+ };
-+
-+ phy1: ethernet-phy@01 {
-+ // interface = <0x3>;
-+ device_type = "ethernet-phy";
-+ reg = <0x1>;
-+ };
-+ };
-+
-+ enet0: ucc@2200 {
-+ tx-clock = <0x1a>;
-+ rx-clock = <0x1f>;
-+ local-mac-address = [00 00 00 00 00 00];
-+ interrupt-parent = <&qeic>;
-+ interrupts = <0x22>;
-+ reg = <0x2200 0x200>;
-+ device-id = <0x3>;
-+ model = "UCC";
-+ compatible = "ucc_geth";
-+ device_type = "network";
-+ phy-handle = <&phy2>;
-+ pio-handle = <&ucc3pio>;
-+ };
-+
-+ enet1: ucc@3200 {
-+ tx-clock = <0x22>;
-+ rx-clock = <0x20>;
-+ local-mac-address = [00 00 00 00 00 00];
-+ interrupt-parent = <&qeic>;
-+ interrupts = <0x23>;
-+ reg = <0x3200 0x200>;
-+ device-id = <0x4>;
-+ model = "UCC";
-+ compatible = "ucc_geth";
-+ device_type = "network";
-+ phy-handle = <&phy3>;
-+ pio-handle = <&ucc4pio>;
-+ };
-+
-+ enet2: ucc@3000 {
-+ tx-clock = <0x18>;
-+ rx-clock = <0x17>;
-+ local-mac-address = [00 00 00 00 00 00];
-+ interrupt-parent = <&qeic>;
-+ interrupts = <0x21>;
-+ reg = <0x3000 0x200>;
-+ device-id = <0x2>;
-+ model = "UCC";
-+ compatible = "ucc_geth";
-+ device_type = "network";
-+ phy-handle = <&phy1>;
-+ pio-handle = <&ucc2pio>;
-+ };
-+
-+ spi@500 {
-+ mode = "cpu";
-+ interrupt-parent = <&qeic>;
-+ interrupts = <0x1>;
-+ reg = <0x500 0x40>;
-+ compatible = "fsl,spi";
-+ device_type = "spi";
-+ };
-+
-+ spi@4c0 {
-+ mode = "cpu";
-+ interrupt-parent = <&qeic>;
-+ interrupts = <0x2>;
-+ reg = <0x4c0 0x40>;
-+ compatible = "fsl,spi";
-+ device_type = "spi";
-+ };
-+
-+ muram@10000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
-+ ranges = <0x0 0x10000 0x4000>;
-+ device_type = "muram";
-+
-+ data-only@0 {
-+ compatible = "fsl,qe-muram-data",
-+ "fsl,cpm-muram-data";
-+ reg = <0x0 0x4000>;
-+ };
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/powerpc/boot/rb333.c
-@@ -0,0 +1,86 @@
-+/*
-+ * The RouterBOARD platform -- for booting RB333 RouterBOARDs.
-+ *
-+ * Author: Alexandros C. Couloumbis <alex@ozo.com>
-+ * Author: Michael Guntsche <mike@it-loops.com>
-+ *
-+ * Copyright (c) 2010 Alexandros C. Couloumbis
-+ * Copyright (c) 2009 Michael Guntsche
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include "ops.h"
-+#include "types.h"
-+#include "io.h"
-+#include "stdio.h"
-+#include <libfdt.h>
-+
-+BSS_STACK(4*1024);
-+
-+u64 memsize64;
-+const void *fw_dtb;
-+
-+static void rb333_fixups(void)
-+{
-+ const u32 *reg, *timebase, *clock;
-+ int node, size;
-+ void *chosen;
-+ const char* bootargs;
-+
-+ dt_fixup_memory(0, memsize64);
-+
-+ /* Find the CPU timebase and clock frequencies. */
-+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
-+ timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
-+ clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
-+ dt_fixup_cpu_clocks(*clock, *timebase, 0);
-+
-+ /* Set the MAC addresses. */
-+ node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@2200");
-+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
-+ dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg);
-+
-+ node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@3200");
-+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
-+ dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg);
-+
-+ node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@3000");
-+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
-+ dt_fixup_mac_address_by_alias("ethernet2", (const u8 *)reg);
-+
-+ /* Fixup chosen
-+ * The bootloader reads the kernelparm segment and adds the content to
-+ * bootargs. This is needed to specify root and other boot flags.
-+ */
-+ chosen = finddevice("/chosen");
-+ node = fdt_path_offset(fw_dtb, "/chosen");
-+ bootargs = fdt_getprop(fw_dtb, node, "bootargs", &size);
-+ setprop_str(chosen, "bootargs", bootargs);
-+}
-+
-+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-+ unsigned long r6, unsigned long r7)
-+{
-+ const u32 *reg;
-+ int node, size;
-+
-+ fw_dtb = (const void *)r3;
-+
-+ /* Find the memory range. */
-+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
-+ reg = fdt_getprop(fw_dtb, node, "reg", &size);
-+ memsize64 = reg[1];
-+
-+ /* Now we have the memory size; initialize the heap. */
-+ simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
-+
-+ /* Prepare the device tree and find the console. */
-+ fdt_init(_dtb_start);
-+ serial_console_init();
-+
-+ /* Remaining fixups... */
-+ platform_ops.fixups = rb333_fixups;
-+}
---- /dev/null
-+++ b/arch/powerpc/platforms/83xx/rbppc.c
-@@ -0,0 +1,388 @@
-+/*
-+ * Copyright (C) 2010 Alexandros C. Couloumbis <alex@ozo.com>
-+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
-+ * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
-+ * Copyright (C) Mikrotik 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/root_dev.h>
-+#include <linux/initrd.h>
-+#include <linux/interrupt.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_device.h>
-+#include <linux/of_platform.h>
-+#include <linux/pci.h>
-+#include <asm/time.h>
-+#include <asm/ipic.h>
-+#include <asm/udbg.h>
-+#include <asm/qe.h>
-+#include <asm/qe_ic.h>
-+#include <sysdev/fsl_soc.h>
-+#include <sysdev/fsl_pci.h>
-+#include "mpc83xx.h"
-+
-+#define SYSCTL 0x100
-+#define SICRL 0x014
-+
-+#define GTCFR2 0x04
-+#define GTMDR4 0x22
-+#define GTRFR4 0x26
-+#define GTCNR4 0x2e
-+#define GTVER4 0x36
-+#define GTPSR4 0x3e
-+
-+#define GTCFR_BCM 0x40
-+#define GTCFR_STP4 0x20
-+#define GTCFR_RST4 0x10
-+#define GTCFR_STP3 0x02
-+#define GTCFR_RST3 0x01
-+
-+#define GTMDR_ORI 0x10
-+#define GTMDR_FRR 0x08
-+#define GTMDR_ICLK16 0x04
-+
-+extern int par_io_data_set(u8 port, u8 pin, u8 val);
-+extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
-+ int assignment, int has_irq);
-+
-+static unsigned timer_freq;
-+static void *gtm;
-+
-+static int beeper_irq;
-+static unsigned beeper_gpio_pin[2];
-+
-+int rb333model = 0;
-+
-+irqreturn_t rbppc_timer_irq(int irq, void *ptr)
-+{
-+ static int toggle = 0;
-+
-+ par_io_data_set(beeper_gpio_pin[0], beeper_gpio_pin[1], toggle);
-+ toggle = !toggle;
-+
-+ /* ack interrupt */
-+ out_be16(gtm + GTVER4, 3);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+void rbppc_beep(unsigned freq)
-+{
-+ unsigned gtmdr;
-+
-+ if (freq > 5000) freq = 5000;
-+
-+ if (!gtm)
-+ return;
-+ if (!freq) {
-+ out_8(gtm + GTCFR2, GTCFR_STP4 | GTCFR_STP3);
-+ return;
-+ }
-+
-+ out_8(gtm + GTCFR2, GTCFR_RST4 | GTCFR_STP3);
-+ out_be16(gtm + GTPSR4, 255);
-+ gtmdr = GTMDR_FRR | GTMDR_ICLK16;
-+ if (beeper_irq != NO_IRQ) gtmdr |= GTMDR_ORI;
-+ out_be16(gtm + GTMDR4, gtmdr);
-+ out_be16(gtm + GTVER4, 3);
-+
-+ out_be16(gtm + GTRFR4, timer_freq / 16 / 256 / freq / 2);
-+ out_be16(gtm + GTCNR4, 0);
-+}
-+EXPORT_SYMBOL(rbppc_beep);
-+
-+static void __init rbppc_setup_arch(void)
-+{
-+ struct device_node *np;
-+
-+ np = of_find_node_by_type(NULL, "cpu");
-+ if (np) {
-+ const unsigned *fp = of_get_property(np, "clock-frequency", NULL);
-+ loops_per_jiffy = fp ? *fp / HZ : 0;
-+
-+ of_node_put(np);
-+ }
-+
-+ np = of_find_node_by_name(NULL, "serial");
-+ if (np) {
-+ timer_freq =
-+ *(unsigned *) of_get_property(np, "clock-frequency", NULL);
-+ of_node_put(np);
-+ }
-+
-+#ifdef CONFIG_PCI
-+ np = of_find_node_by_type(NULL, "pci");
-+ if (np) {
-+ mpc83xx_add_bridge(np);
-+ }
-+#endif
-+
-+if (rb333model) {
-+
-+#ifdef CONFIG_QUICC_ENGINE
-+ qe_reset();
-+
-+ if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
-+ par_io_init(np);
-+ of_node_put(np);
-+
-+ for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
-+ par_io_of_config(np);
-+ }
-+#endif
-+
-+} /* RB333 */
-+
-+}
-+
-+void __init rbppc_init_IRQ(void)
-+{
-+ struct device_node *np;
-+
-+ np = of_find_node_by_type(NULL, "ipic");
-+ if (np) {
-+ ipic_init(np, 0);
-+ ipic_set_default_priority();
-+ of_node_put(np);
-+ }
-+
-+if (rb333model) {
-+
-+#ifdef CONFIG_QUICC_ENGINE
-+ np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-+ if (!np) {
-+ np = of_find_node_by_type(NULL, "qeic");
-+ if (!np)
-+ return;
-+ }
-+ qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
-+ of_node_put(np);
-+#endif /* CONFIG_QUICC_ENGINE */
-+
-+} /* RB333 */
-+
-+}
-+
-+static int __init rbppc_probe(void)
-+{
-+ char *model;
-+
-+ model = of_get_flat_dt_prop(of_get_flat_dt_root(), "model", NULL);
-+
-+ if (!model)
-+ return 0;
-+
-+ if (strcmp(model, "RB333") == 0) {
-+ rb333model = 1;
-+ return 1;
-+ }
-+
-+ if (strcmp(model, "RB600") == 0)
-+ return 1;
-+
-+ return 0;
-+}
-+
-+static void __init rbppc_beeper_init(struct device_node *beeper)
-+{
-+ struct resource res;
-+ struct device_node *gpio;
-+ const unsigned *pin;
-+ const unsigned *gpio_id;
-+
-+ if (of_address_to_resource(beeper, 0, &res)) {
-+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No region specified\n", beeper->full_name);
-+ return;
-+ }
-+
-+ pin = of_get_property(beeper, "gpio", NULL);
-+ if (pin) {
-+ gpio = of_find_node_by_phandle(pin[0]);
-+
-+ if (!gpio) {
-+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: GPIO handle %x not found\n", beeper->full_name, pin[0]);
-+ return;
-+ }
-+
-+ gpio_id = of_get_property(gpio, "device-id", NULL);
-+ if (!gpio_id) {
-+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No device-id specified in GPIO\n", beeper->full_name);
-+ return;
-+ }
-+
-+ beeper_gpio_pin[0] = *gpio_id;
-+ beeper_gpio_pin[1] = pin[1];
-+
-+ par_io_config_pin(*gpio_id, pin[1], 1, 0, 0, 0);
-+ } else {
-+ void *sysctl;
-+
-+ sysctl = ioremap_nocache(get_immrbase() + SYSCTL, 0x100);
-+ out_be32(sysctl + SICRL,
-+ in_be32(sysctl + SICRL) | (1 << (31 - 19)));
-+ iounmap(sysctl);
-+ }
-+
-+ gtm = ioremap_nocache(res.start, res.end - res.start + 1);
-+
-+ beeper_irq = irq_of_parse_and_map(beeper, 0);
-+ if (beeper_irq != NO_IRQ) {
-+ int e = request_irq(beeper_irq, rbppc_timer_irq, 0, "beeper", NULL);
-+ if (e) {
-+ printk(KERN_ERR "rbppc_beeper_init(%s): Request of beeper irq failed!\n", beeper->full_name);
-+ }
-+ }
-+}
-+
-+#define SBIT(x) (0x80000000 >> (x))
-+#define DBIT(x, y) ((y) << (32 - (((x % 16) + 1) * 2)))
-+
-+#define GPIO_DIR_RB333(x) ((x) + (0x1408 >> 2))
-+#define GPIO_DATA_RB333(x) ((x) + (0x1404 >> 2))
-+
-+#define SICRL_RB600(x) ((x) + (0x114 >> 2))
-+#define GPIO_DIR_RB600(x) ((x) + (0xc00 >> 2))
-+#define GPIO_DATA_RB600(x) ((x) + (0xc08 >> 2))
-+
-+static void rbppc_restart(char *cmd)
-+{
-+ __be32 __iomem *reg;
-+ unsigned rb_model;
-+ struct device_node *root;
-+ unsigned int size;
-+
-+ root = of_find_node_by_path("/");
-+ if (root) {
-+ const char *prop = (char *) of_get_property(root, "model", &size);
-+ rb_model = prop[sizeof("RB") - 1] - '0';
-+ of_node_put(root);
-+ switch (rb_model) {
-+ case 3:
-+ reg = ioremap(get_immrbase(), 0x2000);
-+ local_irq_disable();
-+ out_be32(GPIO_DIR_RB333(reg),
-+ (in_be32(GPIO_DIR_RB333(reg)) & ~DBIT(4, 3)) | DBIT(4, 1));
-+ out_be32(GPIO_DATA_RB333(reg), in_be32(GPIO_DATA_RB333(reg)) & ~SBIT(4));
-+ break;
-+ case 6:
-+ reg = ioremap(get_immrbase(), 0x1000);
-+ local_irq_disable();
-+ out_be32(SICRL_RB600(reg), in_be32(SICRL_RB600(reg)) & ~0x00800000);
-+ out_be32(GPIO_DIR_RB600(reg), in_be32(GPIO_DIR_RB600(reg)) | SBIT(2));
-+ out_be32(GPIO_DATA_RB600(reg), in_be32(GPIO_DATA_RB600(reg)) & ~SBIT(2));
-+ break;
-+ default:
-+ mpc83xx_restart(cmd);
-+ break;
-+ }
-+ }
-+ else mpc83xx_restart(cmd);
-+
-+ for (;;) ;
-+}
-+
-+static void rbppc_halt(void)
-+{
-+ while (1);
-+}
-+
-+static struct of_device_id rbppc_ids[] = {
-+ { .type = "soc", },
-+ { .compatible = "soc", },
-+ { .compatible = "simple-bus", },
-+ { .type = "qe", },
-+ { .compatible = "fsl,qe", },
-+ { .compatible = "gianfar", },
-+ { },
-+};
-+
-+static int __init rbppc_declare_of_platform_devices(void)
-+{
-+ struct device_node *np;
-+ unsigned idx;
-+
-+ of_platform_bus_probe(NULL, rbppc_ids, NULL);
-+
-+ np = of_find_node_by_type(NULL, "mdio");
-+ if (np) {
-+ unsigned len;
-+ unsigned *res;
-+ const unsigned *eres;
-+ struct device_node *ep;
-+
-+ ep = of_find_compatible_node(NULL, "network", "ucc_geth");
-+ if (ep) {
-+ eres = of_get_property(ep, "reg", &len);
-+ res = (unsigned *) of_get_property(np, "reg", &len);
-+ if (res && eres) {
-+ res[0] = eres[0] + 0x120;
-+ }
-+ }
-+ }
-+
-+ np = of_find_node_by_name(NULL, "nand");
-+ if (np) {
-+ of_platform_device_create(np, "nand", NULL);
-+ }
-+
-+ idx = 0;
-+ for_each_node_by_type(np, "rb,cf") {
-+ char dev_name[12];
-+ snprintf(dev_name, sizeof(dev_name), "cf.%u", idx);
-+ of_platform_device_create(np, dev_name, NULL);
-+ ++idx;
-+ }
-+
-+ np = of_find_node_by_name(NULL, "beeper");
-+ if (np) {
-+ rbppc_beeper_init(np);
-+ }
-+
-+ return 0;
-+}
-+machine_device_initcall(rb600, rbppc_declare_of_platform_devices);
-+
-+define_machine(rb600) {
-+ .name = "MikroTik RouterBOARD 333/600 series",
-+ .probe = rbppc_probe,
-+ .setup_arch = rbppc_setup_arch,
-+ .init_IRQ = rbppc_init_IRQ,
-+ .get_irq = ipic_get_irq,
-+ .restart = rbppc_restart,
-+ .halt = rbppc_halt,
-+ .time_init = mpc83xx_time_init,
-+ .calibrate_decr = generic_calibrate_decr,
-+};
-+
-+static void fixup_pcibridge(struct pci_dev *dev)
-+{
-+ if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
-+ /* let the kernel itself set right memory windows */
-+ pci_write_config_word(dev, PCI_MEMORY_BASE, 0);
-+ pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
-+ pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0);
-+ pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
-+ pci_write_config_byte(dev, PCI_IO_BASE, 0);
-+ pci_write_config_byte(dev, PCI_IO_LIMIT, 4 << 4);
-+
-+ pci_write_config_byte(
-+ dev, PCI_COMMAND,
-+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
-+ }
-+}
-+
-+
-+static void fixup_rb604(struct pci_dev *dev)
-+{
-+ pci_write_config_byte(dev, 0xC0, 0x01);
-+}
-+
-+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_pcibridge)
-+DECLARE_PCI_FIXUP_HEADER(0x3388, 0x0021, fixup_rb604)
+++ /dev/null
---- a/arch/powerpc/kernel/Makefile
-+++ b/arch/powerpc/kernel/Makefile
-@@ -117,9 +117,11 @@ obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.
-
- obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
-
-+ifneq ($(CONFIG_RB_IOMAP),y)
- ifneq ($(CONFIG_PPC_INDIRECT_IO),y)
- obj-y += iomap.o
- endif
-+endif
-
- obj64-$(CONFIG_PPC_TRANSACTIONAL_MEM) += tm.o
-
---- a/arch/powerpc/platforms/83xx/Makefile
-+++ b/arch/powerpc/platforms/83xx/Makefile
-@@ -7,6 +7,7 @@ obj-$(CONFIG_MCU_MPC8349EMITX) += mcu_mp
- obj-$(CONFIG_MPC830x_RDB) += mpc830x_rdb.o
- obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o
- obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o
-+obj-$(CONFIG_RB_PPC) += rbppc.o
- obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o
- obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o
- obj-$(CONFIG_MPC836x_MDS) += mpc836x_mds.o
---- a/arch/powerpc/platforms/Kconfig
-+++ b/arch/powerpc/platforms/Kconfig
-@@ -191,6 +191,10 @@ config PPC_INDIRECT_MMIO
- config PPC_IO_WORKAROUNDS
- bool
-
-+config RB_IOMAP
-+ bool
-+ default y if RB_PPC
-+
- source "drivers/cpufreq/Kconfig"
-
- menu "CPU Frequency drivers"
---- a/arch/powerpc/sysdev/Makefile
-+++ b/arch/powerpc/sysdev/Makefile
-@@ -71,3 +71,6 @@ subdir-ccflags-$(CONFIG_PPC_WERROR) := -
- obj-$(CONFIG_PPC_XICS) += xics/
-
- obj-$(CONFIG_GE_FPGA) += ge/
-+
-+obj-$(CONFIG_RB_IOMAP) += rb_iomap.o
-+
---- /dev/null
-+++ b/arch/powerpc/sysdev/rb_iomap.c
-@@ -0,0 +1,204 @@
-+#include <linux/init.h>
-+#include <linux/pci.h>
-+#include <linux/mm.h>
-+#include <asm/io.h>
-+
-+#define LOCALBUS_START 0x40000000
-+#define LOCALBUS_MASK 0x007fffff
-+#define LOCALBUS_REGMASK 0x001fffff
-+
-+static void __iomem *localbus_base;
-+
-+static inline int is_localbus(void __iomem *addr)
-+{
-+ return ((unsigned) addr & ~LOCALBUS_MASK) == LOCALBUS_START;
-+}
-+
-+static inline unsigned localbus_regoff(unsigned reg) {
-+ return (reg << 16) | (((reg ^ 8) & 8) << 17);
-+}
-+
-+static inline void __iomem *localbus_addr(void __iomem *addr)
-+{
-+ return localbus_base
-+ + ((unsigned) addr & LOCALBUS_MASK & ~LOCALBUS_REGMASK)
-+ + localbus_regoff((unsigned) addr & LOCALBUS_REGMASK);
-+}
-+
-+unsigned int ioread8(void __iomem *addr)
-+{
-+ if (is_localbus(addr))
-+ return in_be16(localbus_addr(addr)) >> 8;
-+ return readb(addr);
-+}
-+EXPORT_SYMBOL(ioread8);
-+
-+unsigned int ioread16(void __iomem *addr)
-+{
-+ if (is_localbus(addr))
-+ return le16_to_cpu(in_be16(localbus_addr(addr)));
-+ return readw(addr);
-+}
-+EXPORT_SYMBOL(ioread16);
-+
-+unsigned int ioread16be(void __iomem *addr)
-+{
-+ return in_be16(addr);
-+}
-+EXPORT_SYMBOL(ioread16be);
-+
-+unsigned int ioread32(void __iomem *addr)
-+{
-+ return readl(addr);
-+}
-+EXPORT_SYMBOL(ioread32);
-+
-+unsigned int ioread32be(void __iomem *addr)
-+{
-+ return in_be32(addr);
-+}
-+EXPORT_SYMBOL(ioread32be);
-+
-+void iowrite8(u8 val, void __iomem *addr)
-+{
-+ if (is_localbus(addr))
-+ out_be16(localbus_addr(addr), ((u16) val) << 8);
-+ else
-+ writeb(val, addr);
-+}
-+EXPORT_SYMBOL(iowrite8);
-+
-+void iowrite16(u16 val, void __iomem *addr)
-+{
-+ if (is_localbus(addr))
-+ out_be16(localbus_addr(addr), cpu_to_le16(val));
-+ else
-+ writew(val, addr);
-+}
-+EXPORT_SYMBOL(iowrite16);
-+
-+void iowrite16be(u16 val, void __iomem *addr)
-+{
-+ out_be16(addr, val);
-+}
-+EXPORT_SYMBOL(iowrite16be);
-+
-+void iowrite32(u32 val, void __iomem *addr)
-+{
-+ writel(val, addr);
-+}
-+EXPORT_SYMBOL(iowrite32);
-+
-+void iowrite32be(u32 val, void __iomem *addr)
-+{
-+ out_be32(addr, val);
-+}
-+EXPORT_SYMBOL(iowrite32be);
-+
-+void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
-+{
-+ if (is_localbus(addr)) {
-+ unsigned i;
-+ void *laddr = localbus_addr(addr);
-+ u8 *buf = dst;
-+
-+ for (i = 0; i < count; ++i) {
-+ *buf++ = in_be16(laddr) >> 8;
-+ }
-+ } else {
-+ _insb((u8 __iomem *) addr, dst, count);
-+ }
-+}
-+EXPORT_SYMBOL(ioread8_rep);
-+
-+void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
-+{
-+ if (is_localbus(addr)) {
-+ unsigned i;
-+ void *laddr = localbus_addr(addr);
-+ u16 *buf = dst;
-+
-+ for (i = 0; i < count; ++i) {
-+ *buf++ = in_be16(laddr);
-+ }
-+ } else {
-+ _insw_ns((u16 __iomem *) addr, dst, count);
-+ }
-+}
-+EXPORT_SYMBOL(ioread16_rep);
-+
-+void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
-+{
-+ _insl_ns((u32 __iomem *) addr, dst, count);
-+}
-+EXPORT_SYMBOL(ioread32_rep);
-+
-+void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
-+{
-+ if (is_localbus(addr)) {
-+ unsigned i;
-+ void *laddr = localbus_addr(addr);
-+ const u8 *buf = src;
-+
-+ for (i = 0; i < count; ++i) {
-+ out_be16(laddr, ((u16) *buf++) << 8);
-+ }
-+ } else {
-+ _outsb((u8 __iomem *) addr, src, count);
-+ }
-+}
-+EXPORT_SYMBOL(iowrite8_rep);
-+
-+void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
-+{
-+ if (is_localbus(addr)) {
-+ unsigned i;
-+ void *laddr = localbus_addr(addr);
-+ const u16 *buf = src;
-+
-+ for (i = 0; i < count; ++i) {
-+ out_be16(laddr, *buf++);
-+ }
-+ } else {
-+ _outsw_ns((u16 __iomem *) addr, src, count);
-+ }
-+}
-+EXPORT_SYMBOL(iowrite16_rep);
-+
-+void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
-+{
-+ _outsl_ns((u32 __iomem *) addr, src, count);
-+}
-+EXPORT_SYMBOL(iowrite32_rep);
-+
-+void __iomem *ioport_map(unsigned long port, unsigned int len)
-+{
-+ return (void __iomem *) (port + _IO_BASE);
-+}
-+EXPORT_SYMBOL(ioport_unmap);
-+
-+void ioport_unmap(void __iomem *addr)
-+{
-+ /* Nothing to do */
-+}
-+EXPORT_SYMBOL(ioport_map);
-+
-+void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
-+{
-+ /* Nothing to do */
-+}
-+EXPORT_SYMBOL(pci_iounmap);
-+
-+void __iomem *localbus_map(unsigned long addr, unsigned int len)
-+{
-+ if (!localbus_base)
-+ localbus_base = ioremap(addr & ~LOCALBUS_MASK,
-+ LOCALBUS_MASK + 1);
-+ return (void *) (LOCALBUS_START + (addr & LOCALBUS_MASK));
-+}
-+EXPORT_SYMBOL(localbus_map);
-+
-+void localbus_unmap(void __iomem *addr)
-+{
-+}
-+EXPORT_SYMBOL(localbus_unmap);
---- a/arch/powerpc/platforms/83xx/Kconfig
-+++ b/arch/powerpc/platforms/83xx/Kconfig
-@@ -44,6 +44,7 @@ config RB_PPC
- select QUICC_ENGINE
- select PPC_MPC832x
- select PPC_MPC834x
-+ select RB_IOMAP
- help
- This option enables support for MikroTik RouterBOARD 333/600 series boards.
-
+++ /dev/null
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -938,5 +938,12 @@ config PATA_LEGACY
-
- If unsure, say N.
-
-+config PATA_RB_PPC
-+ tristate "MikroTik RB600 PATA support"
-+ depends on RB_PPC
-+ help
-+ This option enables support for PATA devices on MikroTik RouterBOARD
-+ 600 series boards.
-+
- endif # ATA_SFF
- endif # ATA
---- a/drivers/ata/Makefile
-+++ b/drivers/ata/Makefile
-@@ -92,6 +92,7 @@ obj-$(CONFIG_PATA_PALMLD) += pata_palmld
- obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
- obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
- obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
-+obj-$(CONFIG_PATA_RB_PPC) += pata_rbppc_cf.o
- obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
- obj-$(CONFIG_PATA_SAMSUNG_CF) += pata_samsung_cf.o
-
---- /dev/null
-+++ b/drivers/ata/pata_rbppc_cf.c
-@@ -0,0 +1,699 @@
-+/*
-+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
-+ * Copyright (C) Mikrotik 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <scsi/scsi_host.h>
-+#include <linux/libata.h>
-+#include <linux/of_platform.h>
-+#include <linux/ata_platform.h>
-+#include <linux/slab.h>
-+
-+#define DEBUG_UPM 0
-+
-+#define DRV_NAME "pata_rbppc_cf"
-+#define DRV_VERSION "0.0.2"
-+
-+#define DEV2SEL_OFFSET 0x00100000
-+
-+#define IMMR_LBCFG_OFFSET 0x00005000
-+#define IMMR_LBCFG_SIZE 0x00001000
-+
-+#define LOCAL_BUS_MCMR 0x00000078
-+#define MxMR_OP_MASK 0x30000000
-+#define MxMR_OP_NORMAL 0x00000000
-+#define MxMR_OP_WRITE 0x10000000
-+#define MxMR_OP_READ 0x20000000
-+#define MxMR_OP_RUN 0x30000000
-+#define MxMR_LUPWAIT_LOW 0x08000000
-+#define MxMR_LUPWAIT_HIGH 0x00000000
-+#define MxMR_LUPWAIT_ENABLE 0x00040000
-+#define MxMR_RLF_MASK 0x0003c000
-+#define MxMR_RLF_SHIFT 14
-+#define MxMR_WLF_MASK 0x00003c00
-+#define MxMR_WLF_SHIFT 10
-+#define MxMR_MAD_MASK 0x0000003f
-+#define LOCAL_BUS_MDR 0x00000088
-+#define LOCAL_BUS_LCRR 0x000000D4
-+#define LCRR_CLKDIV_MASK 0x0000000f
-+
-+#define LOOP_SIZE 4
-+
-+#define UPM_READ_SINGLE_OFFSET 0x00
-+#define UPM_WRITE_SINGLE_OFFSET 0x18
-+#define UPM_DATA_SIZE 0x40
-+
-+#define LBT_CPUIN_MIN 0
-+#define LBT_CPUOUT_MIN 1
-+#define LBT_CPUOUT_MAX 2
-+#define LBT_EXTDEL_MIN 3
-+#define LBT_EXTDEL_MAX 4
-+#define LBT_SIZE 5
-+
-+/* UPM machine configuration bits */
-+#define N_BASE 0x00f00000
-+#define N_CS 0xf0000000
-+#define N_CS_H1 0xc0000000
-+#define N_CS_H2 0x30000000
-+#define N_WE 0x0f000000
-+#define N_WE_H1 0x0c000000
-+#define N_WE_H2 0x03000000
-+#define N_OE 0x00030000
-+#define N_OE_H1 0x00020000
-+#define N_OE_H2 0x00010000
-+#define WAEN 0x00001000
-+#define REDO_2 0x00000100
-+#define REDO_3 0x00000200
-+#define REDO_4 0x00000300
-+#define LOOP 0x00000080
-+#define NA 0x00000008
-+#define UTA 0x00000004
-+#define LAST 0x00000001
-+
-+#define REDO_VAL(mult) (REDO_2 * ((mult) - 1))
-+#define REDO_MAX_MULT 4
-+
-+#define READ_BASE (N_BASE | N_WE)
-+#define WRITE_BASE (N_BASE | N_OE)
-+#define EMPTY (N_BASE | N_CS | N_OE | N_WE | LAST)
-+
-+#define EOF_UPM_SETTINGS 0
-+#define ANOTHER_TIMING 1
-+
-+#define OA_CPUIN_MIN 0x01
-+#define OA_CPUOUT_MAX 0x02
-+#define OD_CPUOUT_MIN 0x04
-+#define OA_CPUOUT_DELTA 0x06
-+#define OA_EXTDEL_MAX 0x08
-+#define OD_EXTDEL_MIN 0x10
-+#define OA_EXTDEL_DELTA 0x18
-+#define O_MIN_CYCLE_TIME 0x20
-+#define O_MINUS_PREV 0x40
-+#define O_HALF_CYCLE 0x80
-+
-+extern void __iomem *localbus_map(unsigned long addr, unsigned int len);
-+extern void localbus_unmap(void __iomem *addr);
-+
-+struct rbppc_cf_info {
-+ unsigned lbcfg_addr;
-+ unsigned clk_time_ps;
-+ int cur_mode;
-+ u32 lb_timings[LBT_SIZE];
-+};
-+static struct rbppc_cf_info *rbinfo = NULL;
-+
-+struct upm_setting {
-+ unsigned value;
-+ unsigned ns[7];
-+ unsigned clk_minus;
-+ unsigned group_size;
-+ unsigned options;
-+};
-+
-+static const struct upm_setting cfUpmReadSingle[] = {
-+ { READ_BASE | N_OE,
-+ /* t1 - ADDR setup time */
-+ { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
-+ OA_EXTDEL_MAX) },
-+ { READ_BASE | N_OE_H1,
-+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
-+ { READ_BASE,
-+ /* t2 - OE0 time */
-+ { 290, 290, 290, 80, 70, 65, 55 }, 0, 2, (OA_CPUOUT_MAX |
-+ OA_CPUIN_MIN) },
-+ { READ_BASE | WAEN,
-+ { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
-+ { READ_BASE | UTA,
-+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
-+ { READ_BASE | N_OE,
-+ /* t9 - ADDR hold time */
-+ { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
-+ OD_EXTDEL_MIN) },
-+ { READ_BASE | N_OE | N_CS_H2,
-+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
-+ { READ_BASE | N_OE | N_CS,
-+ /* t6Z -IORD data tristate */
-+ { 30, 30, 30, 30, 30, 20, 20 }, 1, 1, O_MINUS_PREV },
-+ { ANOTHER_TIMING,
-+ /* t2i -IORD recovery time */
-+ { 0, 0, 0, 70, 25, 25, 20 }, 2, 0, 0 },
-+ { ANOTHER_TIMING,
-+ /* CS 0 -> 1 MAX */
-+ { 0, 0, 0, 0, 0, 0, 0 }, 1, 0, (OA_CPUOUT_DELTA |
-+ OA_EXTDEL_MAX) },
-+ { READ_BASE | N_OE | N_CS | LAST,
-+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
-+ { EOF_UPM_SETTINGS,
-+ /* min total cycle time - includes turnaround and ALE cycle */
-+ { 600, 383, 240, 180, 120, 100, 80 }, 2, 0, O_MIN_CYCLE_TIME },
-+};
-+
-+static const struct upm_setting cfUpmWriteSingle[] = {
-+ { WRITE_BASE | N_WE,
-+ /* t1 - ADDR setup time */
-+ { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
-+ OA_EXTDEL_MAX) },
-+ { WRITE_BASE | N_WE_H1,
-+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
-+ { WRITE_BASE,
-+ /* t2 - WE0 time */
-+ { 290, 290, 290, 80, 70, 65, 55 }, 0, 1, OA_CPUOUT_DELTA },
-+ { WRITE_BASE | WAEN,
-+ { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
-+ { WRITE_BASE | N_WE,
-+ /* t9 - ADDR hold time */
-+ { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
-+ OD_EXTDEL_MIN) },
-+ { WRITE_BASE | N_WE | N_CS_H2,
-+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
-+ { WRITE_BASE | N_WE | N_CS,
-+ /* t4 - DATA hold time */
-+ { 30, 20, 15, 10, 10, 10, 10 }, 0, 1, O_MINUS_PREV },
-+ { ANOTHER_TIMING,
-+ /* t2i -IOWR recovery time */
-+ { 0, 0, 0, 70, 25, 25, 20 }, 1, 0, 0 },
-+ { ANOTHER_TIMING,
-+ /* CS 0 -> 1 MAX */
-+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, (OA_CPUOUT_DELTA |
-+ OA_EXTDEL_MAX) },
-+ { WRITE_BASE | N_WE | N_CS | UTA | LAST,
-+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
-+ /* min total cycle time - includes ALE cycle */
-+ { EOF_UPM_SETTINGS,
-+ { 600, 383, 240, 180, 120, 100, 80 }, 1, 0, O_MIN_CYCLE_TIME },
-+};
-+
-+static u8 rbppc_cf_check_status(struct ata_port *ap) {
-+ u8 val = ioread8(ap->ioaddr.status_addr);
-+ if (val == 0xF9)
-+ val = 0x7F;
-+ return val;
-+}
-+
-+static u8 rbppc_cf_check_altstatus(struct ata_port *ap) {
-+ u8 val = ioread8(ap->ioaddr.altstatus_addr);
-+ if (val == 0xF9)
-+ val = 0x7F;
-+ return val;
-+}
-+
-+static void rbppc_cf_dummy_noret(struct ata_port *ap) { }
-+static int rbppc_cf_dummy_ret0(struct ata_port *ap) { return 0; }
-+
-+static int ps2clk(int ps, unsigned clk_time_ps) {
-+ int psMaxOver;
-+ if (ps <= 0) return 0;
-+
-+ /* round down if <= 2% over clk border, but no more than 1/4 clk cycle */
-+ psMaxOver = ps * 2 / 100;
-+ if (4 * psMaxOver > clk_time_ps) {
-+ psMaxOver = clk_time_ps / 4;
-+ }
-+ return (ps + clk_time_ps - 1 - psMaxOver) / clk_time_ps;
-+}
-+
-+static int upm_gen_ps_table(const struct upm_setting *upm,
-+ int mode, struct rbppc_cf_info *info,
-+ int *psFinal) {
-+ int uidx;
-+ int lastUpmValIdx = 0;
-+ int group_start_idx = -1;
-+ int group_left_num = -1;
-+ int clk_time_ps = info->clk_time_ps;
-+
-+ for (uidx = 0; upm[uidx].value != EOF_UPM_SETTINGS; ++uidx) {
-+ const struct upm_setting *us = upm + uidx;
-+ unsigned opt = us->options;
-+ int ps = us->ns[mode] * 1000 - us->clk_minus * clk_time_ps;
-+
-+ if (opt & OA_CPUIN_MIN) ps += info->lb_timings[LBT_CPUIN_MIN];
-+ if (opt & OD_CPUOUT_MIN) ps -= info->lb_timings[LBT_CPUOUT_MIN];
-+ if (opt & OA_CPUOUT_MAX) ps += info->lb_timings[LBT_CPUOUT_MAX];
-+ if (opt & OD_EXTDEL_MIN) ps -= info->lb_timings[LBT_EXTDEL_MIN];
-+ if (opt & OA_EXTDEL_MAX) ps += info->lb_timings[LBT_EXTDEL_MAX];
-+
-+ if (us->value == ANOTHER_TIMING) {
-+ /* use longest timing from alternatives */
-+ if (psFinal[lastUpmValIdx] < ps) {
-+ psFinal[lastUpmValIdx] = ps;
-+ }
-+ ps = 0;
-+ }
-+ else {
-+ if (us->group_size) {
-+ group_start_idx = uidx;
-+ group_left_num = us->group_size;
-+ }
-+ else if (group_left_num > 0) {
-+ /* group time is divided on all group members */
-+ int clk = ps2clk(ps, clk_time_ps);
-+ psFinal[group_start_idx] -= clk * clk_time_ps;
-+ --group_left_num;
-+ }
-+ if ((opt & O_MINUS_PREV) && lastUpmValIdx > 0) {
-+ int clk = ps2clk(psFinal[lastUpmValIdx],
-+ clk_time_ps);
-+ ps -= clk * clk_time_ps;
-+ }
-+ lastUpmValIdx = uidx;
-+ }
-+ psFinal[uidx] = ps;
-+ }
-+ return uidx;
-+}
-+
-+static int free_half(int ps, int clk, int clk_time_ps) {
-+ if (clk < 2) return 0;
-+ return (clk * clk_time_ps - ps) * 2 >= clk_time_ps;
-+}
-+
-+static void upm_gen_clk_table(const struct upm_setting *upm,
-+ int mode, int clk_time_ps,
-+ int max_uidx, const int *psFinal, int *clkFinal) {
-+ int clk_cycle_time;
-+ int clk_total;
-+ int uidx;
-+
-+ /* convert picoseconds to clocks */
-+ clk_total = 0;
-+ for (uidx = 0; uidx < max_uidx; ++uidx) {
-+ int clk = ps2clk(psFinal[uidx], clk_time_ps);
-+ clkFinal[uidx] = clk;
-+ clk_total += clk;
-+ }
-+
-+ /* check possibility of half cycle usage */
-+ for (uidx = 1; uidx < max_uidx - 1; ++uidx) {
-+ if ((upm[uidx].options & O_HALF_CYCLE) &&
-+ free_half(psFinal[uidx - 1], clkFinal[uidx - 1],
-+ clk_time_ps) &&
-+ free_half(psFinal[uidx + 1], clkFinal[uidx + 1],
-+ clk_time_ps)) {
-+ ++clkFinal[uidx];
-+ --clkFinal[uidx - 1];
-+ --clkFinal[uidx + 1];
-+ }
-+ }
-+
-+ if ((upm[max_uidx].options & O_MIN_CYCLE_TIME) == 0) return;
-+
-+ /* check cycle time, adjust timings if needed */
-+ clk_cycle_time = (ps2clk(upm[max_uidx].ns[mode] * 1000, clk_time_ps) -
-+ upm[max_uidx].clk_minus);
-+ uidx = 0;
-+ while (clk_total < clk_cycle_time) {
-+ /* extend all timings in round-robin to match cycle time */
-+ if (clkFinal[uidx]) {
-+#if DEBUG_UPM
-+ printk(KERN_INFO "extending %u by 1 clk\n", uidx);
-+#endif
-+ ++clkFinal[uidx];
-+ ++clk_total;
-+ }
-+ ++uidx;
-+ if (uidx == max_uidx) uidx = 0;
-+ }
-+}
-+
-+static void add_data_val(unsigned val, int *clkLeft, int maxClk,
-+ unsigned *data, int *dataIdx) {
-+ if (*clkLeft == 0) return;
-+
-+ if (maxClk == 0 && *clkLeft >= LOOP_SIZE * 2) {
-+ int times;
-+ int times1;
-+ int times2;
-+
-+ times = *clkLeft / LOOP_SIZE;
-+ if (times > REDO_MAX_MULT * 2) times = REDO_MAX_MULT * 2;
-+ times1 = times / 2;
-+ times2 = times - times1;
-+
-+ val |= LOOP;
-+ data[*dataIdx] = val | REDO_VAL(times1);
-+ ++(*dataIdx);
-+ data[*dataIdx] = val | REDO_VAL(times2);
-+ ++(*dataIdx);
-+
-+ *clkLeft -= times * LOOP_SIZE;
-+ return;
-+ }
-+
-+ if (maxClk < 1 || maxClk > REDO_MAX_MULT) maxClk = REDO_MAX_MULT;
-+ if (*clkLeft < maxClk) maxClk = *clkLeft;
-+
-+ *clkLeft -= maxClk;
-+ val |= REDO_VAL(maxClk);
-+
-+ data[*dataIdx] = val;
-+ ++(*dataIdx);
-+}
-+
-+static int upm_gen_final_data(const struct upm_setting *upm,
-+ int max_uidx, int *clkFinal, unsigned *data) {
-+ int dataIdx;
-+ int uidx;
-+
-+ dataIdx = 0;
-+ for (uidx = 0; uidx < max_uidx; ++uidx) {
-+ int clk = clkFinal[uidx];
-+ while (clk > 0) {
-+ add_data_val(upm[uidx].value, &clk, 0,
-+ data, &dataIdx);
-+ }
-+ }
-+ return dataIdx;
-+}
-+
-+static int conv_upm_table(const struct upm_setting *upm,
-+ int mode, struct rbppc_cf_info *info,
-+ unsigned *data) {
-+#if DEBUG_UPM
-+ int uidx;
-+#endif
-+ int psFinal[32];
-+ int clkFinal[32];
-+ int max_uidx;
-+ int data_len;
-+
-+ max_uidx = upm_gen_ps_table(upm, mode, info, psFinal);
-+
-+ upm_gen_clk_table(upm, mode, info->clk_time_ps, max_uidx,
-+ psFinal, clkFinal);
-+
-+#if DEBUG_UPM
-+ /* dump out debug info */
-+ for (uidx = 0; uidx < max_uidx; ++uidx) {
-+ if (clkFinal[uidx]) {
-+ printk(KERN_INFO "idx %d val %08x clk %d ps %d\n",
-+ uidx, upm[uidx].value,
-+ clkFinal[uidx], psFinal[uidx]);
-+ }
-+ }
-+#endif
-+
-+ data_len = upm_gen_final_data(upm, max_uidx, clkFinal, data);
-+
-+#if DEBUG_UPM
-+ for (uidx = 0; uidx < data_len; ++uidx) {
-+ printk(KERN_INFO "cf UPM x result: idx %d val %08x\n",
-+ uidx, data[uidx]);
-+ }
-+#endif
-+ return 0;
-+}
-+
-+static int gen_upm_data(int mode, struct rbppc_cf_info *info, unsigned *data) {
-+ int i;
-+
-+ for (i = 0; i < UPM_DATA_SIZE; ++i) {
-+ data[i] = EMPTY;
-+ }
-+
-+ if (conv_upm_table(cfUpmReadSingle, mode, info, data + UPM_READ_SINGLE_OFFSET)) {
-+ return -1;
-+ }
-+ if (conv_upm_table(cfUpmWriteSingle, mode, info, data + UPM_WRITE_SINGLE_OFFSET)) {
-+ return -1;
-+ }
-+ return 0;
-+}
-+
-+static void rbppc_cf_program_upm(void *upmMemAddr, volatile void *lbcfg_mxmr, volatile void *lbcfg_mdr, const unsigned *upmData, unsigned offset, unsigned len) {
-+ unsigned i;
-+ unsigned mxmr;
-+
-+ mxmr = in_be32(lbcfg_mxmr);
-+ mxmr &= ~(MxMR_OP_MASK | MxMR_MAD_MASK);
-+ mxmr |= (MxMR_OP_WRITE | offset);
-+ out_be32(lbcfg_mxmr, mxmr);
-+ in_be32(lbcfg_mxmr); /* flush MxMR write */
-+
-+ for (i = 0; i < len; ++i) {
-+ int to;
-+ unsigned data = upmData[i + offset];
-+ out_be32(lbcfg_mdr, data);
-+ in_be32(lbcfg_mdr); /* flush MDR write */
-+
-+ iowrite8(1, upmMemAddr); /* dummy write to any CF addr */
-+
-+ /* wait for dummy write to complete */
-+ for (to = 10000; to >= 0; --to) {
-+ mxmr = in_be32(lbcfg_mxmr);
-+ if (((mxmr ^ (i + 1)) & MxMR_MAD_MASK) == 0) {
-+ break;
-+ }
-+ if (to == 0) {
-+ printk(KERN_ERR "rbppc_cf_program_upm: UPMx program error at 0x%x: Timeout\n", i);
-+ }
-+ }
-+ }
-+ mxmr &= ~(MxMR_OP_MASK | MxMR_RLF_MASK | MxMR_WLF_MASK);
-+ mxmr |= (MxMR_OP_NORMAL | (LOOP_SIZE << MxMR_RLF_SHIFT) | (LOOP_SIZE << MxMR_WLF_SHIFT));
-+ out_be32(lbcfg_mxmr, mxmr);
-+}
-+
-+static int rbppc_cf_update_piomode(struct ata_port *ap, int mode) {
-+ struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
-+ void *lbcfgBase;
-+ unsigned upmData[UPM_DATA_SIZE];
-+
-+ if (gen_upm_data(mode, info, upmData)) {
-+ return -1;
-+ }
-+
-+ lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
-+
-+ rbppc_cf_program_upm(ap->ioaddr.cmd_addr, ((char *)lbcfgBase) + LOCAL_BUS_MCMR, ((char *)lbcfgBase) + LOCAL_BUS_MDR, upmData, 0, UPM_DATA_SIZE);
-+ iounmap(lbcfgBase);
-+ return 0;
-+}
-+
-+static void rbppc_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
-+{
-+ struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
-+ int mode = adev->pio_mode - XFER_PIO_0;
-+
-+ DPRINTK("rbppc_cf_set_piomode: PIO %d\n", mode);
-+ if (mode < 0) mode = 0;
-+ if (mode > 6) mode = 6;
-+
-+ if (info->cur_mode < 0 || info->cur_mode > mode) {
-+ if (rbppc_cf_update_piomode(ap, mode) == 0) {
-+ printk(KERN_INFO "rbppc_cf_set_piomode: PIO mode changed to %d\n", mode);
-+ info->cur_mode = mode;
-+ }
-+ }
-+}
-+
-+static struct scsi_host_template rbppc_cf_sht = {
-+ ATA_BASE_SHT(DRV_NAME),
-+};
-+
-+static struct ata_port_operations rbppc_cf_port_ops = {
-+ .inherits = &ata_bmdma_port_ops,
-+
-+ .sff_check_status = rbppc_cf_check_status,
-+ .sff_check_altstatus = rbppc_cf_check_altstatus,
-+
-+ .set_piomode = rbppc_cf_set_piomode,
-+
-+ .port_start = rbppc_cf_dummy_ret0,
-+
-+ .sff_irq_clear = rbppc_cf_dummy_noret,
-+};
-+
-+static int rbppc_cf_init_info(struct platform_device *pdev, struct rbppc_cf_info *info) {
-+ struct device_node *np;
-+ struct resource res;
-+ const u32 *u32ptr;
-+ void *lbcfgBase;
-+ void *lbcfg_lcrr;
-+ unsigned lbc_clk_khz;
-+ unsigned lbc_extra_divider = 1;
-+ unsigned ccb_freq_hz;
-+ unsigned lb_div;
-+
-+ u32ptr = of_get_property(pdev->dev.of_node, "lbc_extra_divider", NULL);
-+ if (u32ptr && *u32ptr) {
-+ lbc_extra_divider = *u32ptr;
-+#if DEBUG_UPM
-+ printk(KERN_INFO "rbppc_cf_init_info: LBC extra divider %u\n",
-+ lbc_extra_divider);
-+#endif
-+ }
-+
-+ np = of_find_node_by_type(NULL, "serial");
-+ if (!np) {
-+ printk(KERN_ERR "rbppc_cf_init_info: No serial node found\n");
-+ return -1;
-+ }
-+ u32ptr = of_get_property(np, "clock-frequency", NULL);
-+ if (u32ptr == 0 || *u32ptr == 0) {
-+ printk(KERN_ERR "rbppc_cf_init_info: Serial does not have clock-frequency\n");
-+ of_node_put(np);
-+ return -1;
-+ }
-+ ccb_freq_hz = *u32ptr;
-+ of_node_put(np);
-+
-+ np = of_find_node_by_type(NULL, "soc");
-+ if (!np) {
-+ printk(KERN_ERR "rbppc_cf_init_info: No soc node found\n");
-+ return -1;
-+ }
-+ if (of_address_to_resource(np, 0, &res)) {
-+ printk(KERN_ERR "rbppc_cf_init_info: soc does not have resource\n");
-+ of_node_put(np);
-+ return -1;
-+ }
-+ info->lbcfg_addr = res.start + IMMR_LBCFG_OFFSET;
-+ of_node_put(np);
-+
-+ lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
-+ lbcfg_lcrr = ((char*)lbcfgBase) + LOCAL_BUS_LCRR;
-+ lb_div = (in_be32(lbcfg_lcrr) & LCRR_CLKDIV_MASK) * lbc_extra_divider;
-+ iounmap(lbcfgBase);
-+
-+ lbc_clk_khz = ccb_freq_hz / (1000 * lb_div);
-+ info->clk_time_ps = 1000000000 / lbc_clk_khz;
-+ printk(KERN_INFO "rbppc_cf_init_info: Using Local-Bus clock %u kHz %u ps\n",
-+ lbc_clk_khz, info->clk_time_ps);
-+
-+ u32ptr = of_get_property(pdev->dev.of_node, "lb-timings", NULL);
-+ if (u32ptr) {
-+ memcpy(info->lb_timings, u32ptr, LBT_SIZE * sizeof(*u32ptr));
-+#if DEBUG_UPM
-+ printk(KERN_INFO "rbppc_cf_init_info: Got LB timings <%u %u %u %u %u>\n",
-+ u32ptr[0], u32ptr[1], u32ptr[2], u32ptr[3], u32ptr[4]);
-+#endif
-+ }
-+ info->cur_mode = -1;
-+ return 0;
-+}
-+
-+static int rbppc_cf_probe(struct platform_device *pdev)
-+{
-+ struct ata_host *host;
-+ struct ata_port *ap;
-+ struct rbppc_cf_info *info = NULL;
-+ struct resource res;
-+ void *baddr;
-+ const u32 *u32ptr;
-+ int irq_level = 0;
-+ int err = -ENOMEM;
-+
-+ printk(KERN_INFO "rbppc_cf_probe: MikroTik RouterBOARD 600 series Compact Flash PATA driver, version " DRV_VERSION "\n");
-+
-+ if (rbinfo == NULL) {
-+ info = kmalloc(sizeof(*info), GFP_KERNEL);
-+ if (info == NULL) {
-+ printk(KERN_ERR "rbppc_cf_probe: Out of memory\n");
-+ goto err_info;
-+ }
-+ memset(info, 0, sizeof(*info));
-+
-+ if (rbppc_cf_init_info(pdev, info)) {
-+ goto err_info;
-+ }
-+ rbinfo = info;
-+ }
-+
-+ u32ptr = of_get_property(pdev->dev.of_node, "interrupt-at-level", NULL);
-+ if (u32ptr) {
-+ irq_level = *u32ptr;
-+ printk(KERN_INFO "rbppc_cf_probe: IRQ level %u\n", irq_level);
-+ }
-+
-+ if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
-+ printk(KERN_ERR "rbppc_cf_probe: No reg property found\n");
-+ goto err_info;
-+ }
-+
-+ host = ata_host_alloc(&pdev->dev, 1);
-+ if (!host)
-+ goto err_info;
-+
-+ baddr = localbus_map(res.start, res.end - res.start + 1);
-+ host->iomap = baddr;
-+ host->private_data = rbinfo;
-+
-+ ap = host->ports[0];
-+ ap->ops = &rbppc_cf_port_ops;
-+ ap->pio_mask = 0x7F; /* PIO modes 0-6 */
-+ ap->mwdma_mask = 0;
-+
-+ ap->ioaddr.cmd_addr = baddr;
-+ ata_sff_std_ports(&ap->ioaddr);
-+ ap->ioaddr.ctl_addr = ap->ioaddr.cmd_addr + 14;
-+ ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
-+ ap->ioaddr.bmdma_addr = 0;
-+
-+ err = ata_host_activate(
-+ host,
-+ irq_of_parse_and_map(pdev->dev.of_node, 0), ata_sff_interrupt,
-+ irq_level ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW,
-+ &rbppc_cf_sht);
-+ if (!err) return 0;
-+
-+ localbus_unmap(baddr);
-+err_info:
-+ if (info) {
-+ kfree(info);
-+ rbinfo = NULL;
-+ }
-+ return err;
-+}
-+
-+static int rbppc_cf_remove(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct ata_host *host = dev_get_drvdata(dev);
-+
-+ if (host == NULL) return -1;
-+
-+ ata_host_detach(host);
-+ return 0;
-+}
-+
-+static struct of_device_id rbppc_cf_ids[] = {
-+ { .name = "cf", },
-+ { },
-+};
-+
-+static struct platform_driver rbppc_cf_driver = {
-+ .probe = rbppc_cf_probe,
-+ .remove = rbppc_cf_remove,
-+ .driver = {
-+ .name = "rbppc-cf",
-+ .owner = THIS_MODULE,
-+ .of_match_table = rbppc_cf_ids,
-+ },
-+};
-+
-+static int __init rbppc_init(void)
-+{
-+ return platform_driver_register(&rbppc_cf_driver);
-+}
-+
-+static void __exit rbppc_exit(void)
-+{
-+ platform_driver_unregister(&rbppc_cf_driver);
-+}
-+
-+MODULE_AUTHOR("Mikrotikls SIA");
-+MODULE_AUTHOR("Noah Fontes");
-+MODULE_DESCRIPTION("MikroTik RouterBOARD 600 series Compact Flash PATA driver");
-+MODULE_LICENSE("GPL");
-+MODULE_VERSION(DRV_VERSION);
-+
-+module_init(rbppc_init);
-+module_exit(rbppc_exit);
+++ /dev/null
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -432,6 +432,13 @@ config MTD_NAND_PLATFORM
- devices. You will need to provide platform-specific functions
- via platform_data.
-
-+config MTD_NAND_RB_PPC
-+ tristate "MikroTik RB333/600 NAND support"
-+ depends on RB_PPC
-+ help
-+ This option enables support for the NAND device on MikroTik
-+ RouterBOARD 333/600 series boards.
-+
- config MTD_ALAUDA
- tristate "MTD driver for Olympus MAUSB-10 and Fujifilm DPC-R1"
- depends on USB
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -31,6 +31,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27
- obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
- obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
- obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
-+obj-$(CONFIG_MTD_NAND_RB_PPC) += rbppc_nand.o
- obj-$(CONFIG_MTD_ALAUDA) += alauda.o
- obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
- obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
---- /dev/null
-+++ b/drivers/mtd/nand/rbppc_nand.c
-@@ -0,0 +1,250 @@
-+/*
-+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
-+ * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
-+ * Copyright (C) Mikrotik 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/mtd/nand.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_device.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <asm/io.h>
-+
-+#define DRV_NAME "rbppc_nand"
-+#define DRV_VERSION "0.0.2"
-+
-+static struct mtd_info rmtd;
-+static struct nand_chip rnand;
-+
-+struct rbppc_nand_info {
-+ void *gpi;
-+ void *gpo;
-+ void *localbus;
-+
-+ unsigned gpio_rdy;
-+ unsigned gpio_nce;
-+ unsigned gpio_cle;
-+ unsigned gpio_ale;
-+ unsigned gpio_ctrls;
-+};
-+
-+/* We must use the OOB layout from yaffs 1 if we want this to be recognized
-+ * properly. Borrowed from the OpenWRT patches for the RB532.
-+ *
-+ * See <https://dev.openwrt.org/browser/trunk/target/linux/rb532/
-+ * patches-2.6.28/025-rb532_nand_fixup.patch> for more details.
-+ */
-+static struct nand_ecclayout rbppc_nand_oob_16 = {
-+ .eccbytes = 6,
-+ .eccpos = { 8, 9, 10, 13, 14, 15 },
-+ .oobavail = 9,
-+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
-+};
-+
-+static struct mtd_partition rbppc_nand_partition_info[] = {
-+ {
-+ name: "kernel",
-+ offset: 0,
-+ size: 4 * 1024 * 1024,
-+ },
-+ {
-+ name: "rootfs",
-+ offset: MTDPART_OFS_NXTBLK,
-+ size: MTDPART_SIZ_FULL,
-+ },
-+};
-+
-+static int rbppc_nand_dev_ready(struct mtd_info *mtd) {
-+ struct nand_chip *chip = mtd->priv;
-+ struct rbppc_nand_info *priv = chip->priv;
-+
-+ return in_be32(priv->gpi) & priv->gpio_rdy;
-+}
-+
-+static void rbppc_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) {
-+ struct nand_chip *chip = mtd->priv;
-+ struct rbppc_nand_info *priv = chip->priv;
-+
-+ if (ctrl & NAND_CTRL_CHANGE) {
-+ unsigned val = in_be32(priv->gpo);
-+ if (!(val & priv->gpio_nce)) {
-+ /* make sure Local Bus has done NAND operations */
-+ readb(priv->localbus);
-+ }
-+
-+ if (ctrl & NAND_CLE) {
-+ val |= priv->gpio_cle;
-+ } else {
-+ val &= ~priv->gpio_cle;
-+ }
-+ if (ctrl & NAND_ALE) {
-+ val |= priv->gpio_ale;
-+ } else {
-+ val &= ~priv->gpio_ale;
-+ }
-+ if (!(ctrl & NAND_NCE)) {
-+ val |= priv->gpio_nce;
-+ } else {
-+ val &= ~priv->gpio_nce;
-+ }
-+ out_be32(priv->gpo, val);
-+
-+ /* make sure GPIO output has changed */
-+ val ^= in_be32(priv->gpo);
-+ if (val & priv->gpio_ctrls) {
-+ printk(KERN_ERR "rbppc_nand_hwcontrol: NAND GPO change failed 0x%08x\n", val);
-+ }
-+ }
-+
-+ if (cmd != NAND_CMD_NONE) writeb(cmd, chip->IO_ADDR_W);
-+}
-+
-+static void rbppc_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-+{
-+ struct nand_chip *chip = mtd->priv;
-+ memcpy(buf, chip->IO_ADDR_R, len);
-+}
-+
-+static unsigned init_ok = 0;
-+
-+static int rbppc_nand_probe(struct platform_device *pdev)
-+{
-+ struct device_node *gpio;
-+ struct device_node *nnand;
-+ struct resource res;
-+ struct rbppc_nand_info *info;
-+ void *baddr;
-+ const unsigned *rdy, *nce, *cle, *ale;
-+
-+ printk(KERN_INFO "rbppc_nand_probe: MikroTik RouterBOARD 333/600 series NAND driver, version " DRV_VERSION "\n");
-+
-+ info = kmalloc(sizeof(*info), GFP_KERNEL);
-+
-+ rdy = of_get_property(pdev->dev.of_node, "rdy", NULL);
-+ nce = of_get_property(pdev->dev.of_node, "nce", NULL);
-+ cle = of_get_property(pdev->dev.of_node, "cle", NULL);
-+ ale = of_get_property(pdev->dev.of_node, "ale", NULL);
-+
-+ if (!rdy || !nce || !cle || !ale) {
-+ printk(KERN_ERR "rbppc_nand_probe: GPIO properties are missing\n");
-+ goto err;
-+ }
-+ if (rdy[0] != nce[0] || rdy[0] != cle[0] || rdy[0] != ale[0]) {
-+ printk(KERN_ERR "rbppc_nand_probe: Different GPIOs are not supported\n");
-+ goto err;
-+ }
-+
-+ gpio = of_find_node_by_phandle(rdy[0]);
-+ if (!gpio) {
-+ printk(KERN_ERR "rbppc_nand_probe: No GPIO<%x> node found\n", *rdy);
-+ goto err;
-+ }
-+ if (of_address_to_resource(gpio, 0, &res)) {
-+ printk(KERN_ERR "rbppc_nand_probe: No reg property in GPIO found\n");
-+ goto err;
-+ }
-+ info->gpo = ioremap_nocache(res.start, res.end - res.start + 1);
-+
-+ if (!of_address_to_resource(gpio, 1, &res)) {
-+ info->gpi = ioremap_nocache(res.start, res.end - res.start + 1);
-+ } else {
-+ info->gpi = info->gpo;
-+ }
-+ of_node_put(gpio);
-+
-+ info->gpio_rdy = 1 << (31 - rdy[1]);
-+ info->gpio_nce = 1 << (31 - nce[1]);
-+ info->gpio_cle = 1 << (31 - cle[1]);
-+ info->gpio_ale = 1 << (31 - ale[1]);
-+ info->gpio_ctrls = info->gpio_nce | info->gpio_cle | info->gpio_ale;
-+
-+ nnand = of_find_node_by_name(NULL, "nnand");
-+ if (!nnand) {
-+ printk("rbppc_nand_probe: No nNAND found\n");
-+ goto err;
-+ }
-+ if (of_address_to_resource(nnand, 0, &res)) {
-+ printk("rbppc_nand_probe: No reg property in nNAND found\n");
-+ goto err;
-+ }
-+ of_node_put(nnand);
-+ info->localbus = ioremap_nocache(res.start, res.end - res.start + 1);
-+
-+ if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
-+ printk("rbppc_nand_probe: No reg property found\n");
-+ goto err;
-+ }
-+ baddr = ioremap_nocache(res.start, res.end - res.start + 1);
-+
-+ memset(&rnand, 0, sizeof(rnand));
-+ rnand.cmd_ctrl = rbppc_nand_cmd_ctrl;
-+ rnand.dev_ready = rbppc_nand_dev_ready;
-+ rnand.read_buf = rbppc_nand_read_buf;
-+ rnand.IO_ADDR_W = baddr;
-+ rnand.IO_ADDR_R = baddr;
-+ rnand.priv = info;
-+
-+ memset(&rmtd, 0, sizeof(rmtd));
-+ rnand.ecc.mode = NAND_ECC_SOFT;
-+ rnand.ecc.layout = &rbppc_nand_oob_16;
-+ rnand.chip_delay = 25;
-+ rmtd.priv = &rnand;
-+ rmtd.owner = THIS_MODULE;
-+
-+ if (nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)) {
-+ printk(KERN_ERR "rbppc_nand_probe: RouterBOARD NAND device not found\n");
-+ return -ENXIO;
-+ }
-+
-+ mtd_device_parse_register(&rmtd, NULL, 0, rbppc_nand_partition_info, 2);
-+ init_ok = 1;
-+ return 0;
-+
-+err:
-+ kfree(info);
-+ return -1;
-+}
-+
-+static struct of_device_id rbppc_nand_ids[] = {
-+ { .name = "nand", },
-+ { },
-+};
-+
-+static struct platform_driver rbppc_nand_driver = {
-+ .probe = rbppc_nand_probe,
-+ .driver = {
-+ .name = "rbppc-nand",
-+ .owner = THIS_MODULE,
-+ .of_match_table = rbppc_nand_ids,
-+ },
-+};
-+
-+static int __init rbppc_nand_init(void)
-+{
-+ return platform_driver_register(&rbppc_nand_driver);
-+}
-+
-+static void __exit rbppc_nand_exit(void)
-+{
-+ platform_driver_unregister(&rbppc_nand_driver);
-+}
-+
-+MODULE_AUTHOR("Mikrotikls SIA");
-+MODULE_AUTHOR("Noah Fontes");
-+MODULE_AUTHOR("Michael Guntsche");
-+MODULE_DESCRIPTION("MikroTik RouterBOARD 333/600 series NAND driver");
-+MODULE_LICENSE("GPL");
-+MODULE_VERSION(DRV_VERSION);
-+
-+module_init(rbppc_nand_init);
-+module_exit(rbppc_nand_exit);
+++ /dev/null
---- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
-+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
-@@ -81,6 +81,11 @@
- reg = <0x3a0000 0x3c60000>;
- label = "rootfs";
- };
-+
-+ partition1@a0000 {
-+ reg = <0xa0000 0x3f60000>;
-+ label = "firmware";
-+ };
- };
- };
-
-@@ -476,4 +481,8 @@
- default-state = "off";
- };
- };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200 rootfstype=squashfs noinitrd";
-+ };
- };
+++ /dev/null
---- a/arch/powerpc/Makefile
-+++ b/arch/powerpc/Makefile
-@@ -155,7 +155,9 @@ all: zImage
-
- # With make 3.82 we cannot mix normal and wildcard targets
- BOOT_TARGETS1 := zImage zImage.initrd uImage
--BOOT_TARGETS2 := zImage% dtbImage% treeImage.% cuImage.% simpleImage.% uImage.%
-+BOOT_TARGETS2 := uImage.fit.% zImage% dtbImage% treeImage.% cuImage.% \
-+ simpleImage.% uImage.%
-+
-
- PHONY += $(BOOT_TARGETS1) $(BOOT_TARGETS2)
-
-@@ -188,6 +190,7 @@ define archhelp
- @echo '* zImage - Build default images selected by kernel config'
- @echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
- @echo ' uImage - U-Boot native image format'
-+ @echo ' uImage.fit.<dt> - U-Boot Flattened Image Tree image format'
- @echo ' cuImage.<dt> - Backwards compatible U-Boot image for older'
- @echo ' versions which do not support device trees'
- @echo ' dtbImage.<dt> - zImage with an embedded device tree blob'
---- a/arch/powerpc/boot/.gitignore
-+++ b/arch/powerpc/boot/.gitignore
-@@ -14,6 +14,7 @@ kernel-vmlinux.strip.c
- kernel-vmlinux.strip.gz
- mktree
- uImage
-+uImage.fit.*
- cuImage.*
- dtbImage.*
- treeImage.*
---- a/arch/powerpc/boot/Makefile
-+++ b/arch/powerpc/boot/Makefile
-@@ -338,6 +338,9 @@ $(obj)/uImage.initrd.%: vmlinux $(obj)/%
- $(obj)/uImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
- $(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb)
-
-+$(obj)/uImage.fit.%: vmlinux $(obj)/%.dtb $(wrapperbits)
-+ $(call if_changed,wrap,uboot.fit,,$(obj)/$*.dtb)
-+
- $(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
- $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
-
-@@ -375,6 +378,7 @@ install: $(CONFIGURE) $(addprefix $(obj)
-
- # anything not in $(targets)
- clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \
-+ uImage.* \
- zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
- zImage.miboot zImage.pmac zImage.pseries \
- zImage.maple simpleImage.* otheros.bld *.dtb
---- a/arch/powerpc/boot/wrapper
-+++ b/arch/powerpc/boot/wrapper
-@@ -47,6 +47,9 @@ CROSS=
- # mkimage wrapper script
- MKIMAGE=$srctree/scripts/mkuboot.sh
-
-+# script to generate an .its file for uImage.fit.* images
-+MKITS=$srctree/scripts/mkits.sh
-+
- # directory for object and other files used by this script
- object=arch/powerpc/boot
- objbin=$object
-@@ -336,6 +339,21 @@ uboot-obs600)
- if [ -z "$cacheit" ]; then
- rm -f "$vmz"
- fi
-+ exit 0
-+ ;;
-+uboot.fit)
-+ rm -f "$ofile"
-+ ${MKITS} -A ppc -C gzip -a $membase -e $membase -v $version \
-+ -d "$srctree/$dtb" -k "$srctree/$vmz" -o "$object/uImage.its"
-+
-+ # mkimage calls dtc for FIT images so use kernel dtc if necessary
-+ export PATH=$PATH:$srctree/scripts/dtc
-+
-+ ${MKIMAGE} -f "$object/uImage.its" "$ofile"
-+ rm "$object/uImage.its"
-+ if [ -z "$cacheit" ]; then
-+ rm -f "$vmz"
-+ fi
- exit 0
- ;;
- esac
+++ /dev/null
---- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
-+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
-@@ -462,4 +462,18 @@
- 0 0x00800000>;
- };
- };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ diag {
-+ gpios = <&gpio1 9 1>;
-+ default-state = "off";
-+ };
-+
-+ wireless {
-+ gpios = <&gpio1 10 1>;
-+ default-state = "off";
-+ };
-+ };
- };
+++ /dev/null
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -69,6 +69,12 @@ config VITESSE_PHY
- ---help---
- Currently supports the vsc8244
-
-+config VITESSE_PHY_8601_SKEW
-+ bool "Enable skew timing to vsc8601"
-+ depends on VITESSE_PHY
-+ ---help---
-+ Apply clock timing adjustments for vsc8601
-+
- config SMSC_PHY
- tristate "Drivers for SMSC PHYs"
- ---help---
---- a/drivers/net/phy/vitesse.c
-+++ b/drivers/net/phy/vitesse.c
-@@ -26,6 +26,11 @@
- #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
- #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
-
-+/* EXT_CON1 Register values for VSC8601 */
-+#define MII_VSC8601_EXTCON1_INIT 0x0000
-+#define MII_VSC8601_EXTCON1_SKEW 0x0100
-+#define MII_VSC8601_EXTCON1_ACTIPHY 0x0020
-+
- /* Vitesse Interrupt Mask Register */
- #define MII_VSC8244_IMASK 0x19
- #define MII_VSC8244_IMASK_IEN 0x8000
-@@ -56,6 +61,7 @@
-
- #define PHY_ID_VSC8244 0x000fc6c0
- #define PHY_ID_VSC8221 0x000fc550
-+#define PHY_ID_VSC8601 0x00070420
-
- MODULE_DESCRIPTION("Vitesse PHY driver");
- MODULE_AUTHOR("Kriston Carson");
-@@ -98,10 +104,34 @@ static int vsc824x_config_init(struct ph
- return err;
- }
-
-+static int vsc8601_config_init(struct phy_device *phydev)
-+{
-+ int err;
-+ int extcon;
-+
-+ err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
-+ MII_VSC8244_AUXCONSTAT_INIT);
-+
-+ if (err < 0)
-+ return err;
-+
-+#ifdef CONFIG_VITESSE_PHY_8601_SKEW
-+ extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
-+ if (err < 0)
-+ return err;
-+
-+ extcon |= MII_VSC8601_EXTCON1_SKEW;
-+
-+ err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
-+#endif
-+
-+ return err;
-+}
-+
- static int vsc824x_ack_interrupt(struct phy_device *phydev)
- {
- int err = 0;
--
-+
- /*
- * Don't bother to ACK the interrupts if interrupts
- * are disabled. The 824x cannot clear the interrupts
-@@ -177,6 +207,19 @@ static struct phy_driver vsc82xx_driver[
- .ack_interrupt = &vsc824x_ack_interrupt,
- .config_intr = &vsc82xx_config_intr,
- .driver = { .owner = THIS_MODULE,},
-+}, {
-+ /* Vitesse 8601 */
-+ .phy_id = PHY_ID_VSC8601,
-+ .name = "Vitesse VSC8601",
-+ .phy_id_mask = 0x000ffff8,
-+ .features = PHY_GBIT_FEATURES,
-+ .flags = PHY_HAS_INTERRUPT,
-+ .config_init = &vsc8601_config_init,
-+ .config_aneg = &genphy_config_aneg,
-+ .read_status = &genphy_read_status,
-+ .ack_interrupt = &vsc824x_ack_interrupt,
-+ .config_intr = &vsc82xx_config_intr,
-+ .driver = { .owner = THIS_MODULE,},
- } };
-
- static int __init vsc82xx_init(void)
+++ /dev/null
---- a/drivers/net/ethernet/freescale/gianfar.c
-+++ b/drivers/net/ethernet/freescale/gianfar.c
-@@ -1005,7 +1005,16 @@ static int gfar_probe(struct platform_de
- /* We need to delay at least 3 TX clocks */
- udelay(2);
-
-- tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
-+ if ((mfspr(SPRN_SVR) & 0xffff) >= 0x0011) {
-+ tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
-+ } else {
-+ /*
-+ * Do not enable flow control on chips earlier than rev 1.1,
-+ * because of the eTSEC27 erratum
-+ */
-+ tempval = 0;
-+ }
-+
- gfar_write(®s->maccfg1, tempval);
-
- /* Initialize MACCFG2. */
+++ /dev/null
---- /dev/null
-+++ b/drivers/misc/ucc_tdm.h
-@@ -0,0 +1,221 @@
-+/*
-+ * drivers/misc/ucc_tdm.h
-+ *
-+ * UCC Based Linux TDM Driver
-+ * This driver is designed to support UCC based TDM for PowerPC processors.
-+ * This driver can interface with SLIC device to run VOIP kind of
-+ * applications.
-+ *
-+ * Author: Ashish Kalra & Poonam Aggrwal
-+ *
-+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#ifndef TDM_H
-+#define TDM_H
-+
-+#define NUM_TS 8
-+#define ACTIVE_CH 8
-+
-+/* SAMPLE_DEPTH is the sample depth is the number of frames before
-+ * an interrupt. Must be a multiple of 4
-+ */
-+#define SAMPLE_DEPTH 80
-+
-+/* define the number of Rx interrupts to go by for initial stuttering */
-+#define STUTTER_INT_CNT 1
-+
-+/* BMRx Field Descriptions to specify tstate and rstate in UCC parameter RAM*/
-+#define EN_BUS_SNOOPING 0x20
-+#define BE_BO 0x10
-+
-+/* UPSMR Register for Transparent UCC controller Bit definitions*/
-+#define NBO 0x00000000 /* Normal Mode 1 bit of data per clock */
-+
-+/* SI Mode register bit definitions */
-+#define NORMAL_OPERATION 0x0000
-+#define AUTO_ECHO 0x0400
-+#define INTERNAL_LB 0x0800
-+#define CONTROL_LB 0x0c00
-+#define SIMODE_CRT (0x8000 >> 9)
-+#define SIMODE_SL (0x8000 >> 10)
-+#define SIMODE_CE (0x8000 >> 11)
-+#define SIMODE_FE (0x8000 >> 12)
-+#define SIMODE_GM (0x8000 >> 13)
-+#define SIMODE_TFSD(val) (val)
-+#define SIMODE_RFSD(val) ((val) << 8)
-+
-+#define SI_TDM_MODE_REGISTER_OFFSET 0
-+
-+#define R_CM 0x02000000
-+#define T_CM 0x02000000
-+
-+#define SET_RX_SI_RAM(n, val) \
-+ out_be16((u16 *)&qe_immr->sir.rx[(n)*2], (u16)(val))
-+
-+#define SET_TX_SI_RAM(n, val) \
-+ out_be16((u16 *)&qe_immr->sir.tx[(n)*2], (u16)(val))
-+
-+/* SI RAM entries */
-+#define SIR_LAST 0x0001
-+#define SIR_CNT(n) ((n) << 2)
-+#define SIR_BYTE 0x0002
-+#define SIR_BIT 0x0000
-+#define SIR_IDLE 0
-+#define SIR_UCC(uccx) (((uccx+9)) << 5)
-+
-+/* BRGC Register Bit definitions */
-+#define BRGC_RESET (0x1<<17)
-+#define BRGC_EN (0x1<<16)
-+#define BRGC_EXTC_QE (0x00<<14)
-+#define BRGC_EXTC_CLK3 (0x01<<14)
-+#define BRGC_EXTC_CLK5 (0x01<<15)
-+#define BRGC_EXTC_CLK9 (0x01<<14)
-+#define BRGC_EXTC_CLK11 (0x01<<14)
-+#define BRGC_EXTC_CLK13 (0x01<<14)
-+#define BRGC_EXTC_CLK15 (0x01<<15)
-+#define BRGC_ATB (0x1<<13)
-+#define BRGC_DIV16 (0x1)
-+
-+/* structure representing UCC transparent parameter RAM */
-+struct ucc_transparent_pram {
-+ __be16 riptr;
-+ __be16 tiptr;
-+ __be16 res0;
-+ __be16 mrblr;
-+ __be32 rstate;
-+ __be32 rbase;
-+ __be16 rbdstat;
-+ __be16 rbdlen;
-+ __be32 rdptr;
-+ __be32 tstate;
-+ __be32 tbase;
-+ __be16 tbdstat;
-+ __be16 tbdlen;
-+ __be32 tdptr;
-+ __be32 rbptr;
-+ __be32 tbptr;
-+ __be32 rcrc;
-+ __be32 res1;
-+ __be32 tcrc;
-+ __be32 res2;
-+ __be32 res3;
-+ __be32 c_mask;
-+ __be32 c_pres;
-+ __be16 disfc;
-+ __be16 crcec;
-+ __be32 res4[4];
-+ __be16 ts_tmp;
-+ __be16 tmp_mb;
-+};
-+
-+#define UCC_TRANSPARENT_PRAM_SIZE 0x100
-+
-+struct tdm_cfg {
-+ u8 com_pin; /* Common receive and transmit pins
-+ * 0 = separate pins
-+ * 1 = common pins
-+ */
-+
-+ u8 fr_sync_level; /* SLx bit Frame Sync Polarity
-+ * 0 = L1R/TSYNC active logic "1"
-+ * 1 = L1R/TSYNC active logic "0"
-+ */
-+
-+ u8 clk_edge; /* CEx bit Tx Rx Clock Edge
-+ * 0 = TX data on rising edge of clock
-+ * RX data on falling edge
-+ * 1 = TX data on falling edge of clock
-+ * RX data on rising edge
-+ */
-+
-+ u8 fr_sync_edge; /* FEx bit Frame sync edge
-+ * Determine when the sync pulses are sampled
-+ * 0 = Falling edge
-+ * 1 = Rising edge
-+ */
-+
-+ u8 rx_fr_sync_delay; /* TFSDx/RFSDx bits Frame Sync Delay
-+ * 00 = no bit delay
-+ * 01 = 1 bit delay
-+ * 10 = 2 bit delay
-+ * 11 = 3 bit delay
-+ */
-+
-+ u8 tx_fr_sync_delay; /* TFSDx/RFSDx bits Frame Sync Delay
-+ * 00 = no bit delay
-+ * 01 = 1 bit delay
-+ * 10 = 2 bit delay
-+ * 11 = 3 bit delay
-+ */
-+
-+ u8 active_num_ts; /* Number of active time slots in TDM
-+ * assume same active Rx/Tx time slots
-+ */
-+};
-+
-+struct ucc_tdm_info {
-+ struct ucc_fast_info uf_info;
-+ u32 ucc_busy;
-+};
-+
-+struct tdm_ctrl {
-+ u32 device_busy;
-+ struct device *device;
-+ struct ucc_fast_private *uf_private;
-+ struct ucc_tdm_info *ut_info;
-+ u32 tdm_port; /* port for this tdm:TDMA,TDMB,TDMC,TDMD */
-+ u32 si; /* serial interface: 0 or 1 */
-+ struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */
-+ u16 rx_mask[8]; /* Active Receive channels LSB is ch0 */
-+ u16 tx_mask[8]; /* Active Transmit channels LSB is ch0 */
-+ /* Only channels less than the number of FRAME_SIZE are implemented */
-+ struct tdm_cfg cfg_ctrl; /* Signaling controls configuration */
-+ u8 *tdm_input_data; /* buffer used for Rx by the tdm */
-+ u8 *tdm_output_data; /* buffer used for Tx by the tdm */
-+
-+ dma_addr_t dma_input_addr; /* dma mapped buffer for TDM Rx */
-+ dma_addr_t dma_output_addr; /* dma mapped buffer for TDM Tx */
-+ u16 physical_num_ts; /* physical number of timeslots in the tdm
-+ frame */
-+ u32 phase_rx; /* cycles through 0, 1, 2 */
-+ u32 phase_tx; /* cycles through 0, 1, 2 */
-+ /*
-+ * the following two variables are for dealing with "stutter" problem
-+ * "stutter" period is about 20 frames or so, varies depending active
-+ * channel num depending on the sample depth, the code should let a
-+ * few Rx interrupts go by
-+ */
-+ u32 tdm_icnt;
-+ u32 tdm_flag;
-+ struct ucc_transparent_pram __iomem *ucc_pram;
-+ struct qe_bd __iomem *tx_bd;
-+ struct qe_bd __iomem *rx_bd;
-+ u32 ucc_pram_offset;
-+ u32 tx_bd_offset;
-+ u32 rx_bd_offset;
-+ u32 rx_ucode_buf_offset;
-+ u32 tx_ucode_buf_offset;
-+ bool leg_slic;
-+ wait_queue_head_t wakeup_event;
-+};
-+
-+struct tdm_client {
-+ u32 client_id;
-+ void (*tdm_read)(u32 client_id, short chn_id,
-+ short *pcm_buffer, short len);
-+ void (*tdm_write)(u32 client_id, short chn_id,
-+ short *pcm_buffer, short len);
-+ wait_queue_head_t *wakeup_event;
-+ };
-+
-+#define MAX_PHASE 1
-+#define NR_BUFS 2
-+#define EFF_ACTIVE_CH ACTIVE_CH / 2
-+
-+#endif
---- /dev/null
-+++ b/drivers/misc/ucc_tdm.c
-@@ -0,0 +1,1017 @@
-+/*
-+ * drivers/misc/ucc_tdm.c
-+ *
-+ * UCC Based Linux TDM Driver
-+ * This driver is designed to support UCC based TDM for PowerPC processors.
-+ * This driver can interface with SLIC device to run VOIP kind of
-+ * applications.
-+ *
-+ * Author: Ashish Kalra & Poonam Aggrwal
-+ *
-+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <generated/autoconf.h>
-+#include <linux/module.h>
-+#include <linux/sched.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/errno.h>
-+#include <linux/types.h>
-+#include <linux/interrupt.h>
-+#include <linux/time.h>
-+#include <linux/skbuff.h>
-+#include <linux/proc_fs.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/string.h>
-+#include <linux/irq.h>
-+#include <linux/of_platform.h>
-+#include <linux/io.h>
-+#include <linux/wait.h>
-+#include <linux/timer.h>
-+
-+#include <asm/immap_qe.h>
-+#include <asm/qe.h>
-+#include <asm/ucc.h>
-+#include <asm/ucc_fast.h>
-+#include <asm/ucc_slow.h>
-+
-+#include "ucc_tdm.h"
-+#define DRV_DESC "Freescale QE UCC TDM Driver"
-+#define DRV_NAME "ucc_tdm"
-+
-+
-+/*
-+ * define the following #define if snooping or hardware-based cache coherency
-+ * is disabled on the UCC transparent controller.This flag enables
-+ * software-based cache-coherency support by explicitly flushing data cache
-+ * contents after setting up the TDM output buffer(s) and invalidating the
-+ * data cache contents before the TDM input buffer(s) are read.
-+ */
-+#undef UCC_CACHE_SNOOPING_DISABLED
-+
-+#define MAX_NUM_TDM_DEVICES 8
-+
-+static struct tdm_ctrl *tdm_ctrl[MAX_NUM_TDM_DEVICES];
-+
-+static int num_tdm_devices;
-+static int num_tdm_clients;
-+
-+static struct ucc_tdm_info utdm_primary_info = {
-+ .uf_info = {
-+ .tsa = 1,
-+ .cdp = 1,
-+ .cds = 1,
-+ .ctsp = 1,
-+ .ctss = 1,
-+ .revd = 1,
-+ .urfs = 0x128,
-+ .utfs = 0x128,
-+ .utfet = 0,
-+ .utftt = 0x128,
-+ .ufpt = 256,
-+ .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT,
-+ .tenc = UCC_FAST_TX_ENCODING_NRZ,
-+ .renc = UCC_FAST_RX_ENCODING_NRZ,
-+ .tcrc = UCC_FAST_16_BIT_CRC,
-+ .synl = UCC_FAST_SYNC_LEN_NOT_USED,
-+ },
-+ .ucc_busy = 0,
-+};
-+
-+static struct ucc_tdm_info utdm_info[8];
-+
-+static void dump_siram(struct tdm_ctrl *tdm_c)
-+{
-+#ifdef DEBUG
-+ int i;
-+ u16 phy_num_ts;
-+
-+ phy_num_ts = tdm_c->physical_num_ts;
-+
-+ pr_debug("SI TxRAM dump\n");
-+ /* each slot entry in SI RAM is of 2 bytes */
-+ for (i = 0; i < phy_num_ts * 2; i++)
-+ pr_debug("%x ", in_8(&qe_immr->sir.tx[i]));
-+ pr_debug("\nSI RxRAM dump\n");
-+ for (i = 0; i < phy_num_ts * 2; i++)
-+ pr_debug("%x ", in_8(&qe_immr->sir.rx[i]));
-+ pr_debug("\n");
-+#endif
-+}
-+
-+static void dump_ucc(struct tdm_ctrl *tdm_c)
-+{
-+#ifdef DEBUG
-+ struct ucc_transparent_pram *ucc_pram;
-+
-+ ucc_pram = tdm_c->ucc_pram;
-+
-+ pr_debug("%s Dumping UCC Registers\n", __FUNCTION__);
-+ ucc_fast_dump_regs(tdm_c->uf_private);
-+ pr_debug("%s Dumping UCC Parameter RAM\n", __FUNCTION__);
-+ pr_debug("rbase = 0x%x\n", in_be32(&ucc_pram->rbase));
-+ pr_debug("rbptr = 0x%x\n", in_be32(&ucc_pram->rbptr));
-+ pr_debug("mrblr = 0x%x\n", in_be16(&ucc_pram->mrblr));
-+ pr_debug("rbdlen = 0x%x\n", in_be16(&ucc_pram->rbdlen));
-+ pr_debug("rbdstat = 0x%x\n", in_be16(&ucc_pram->rbdstat));
-+ pr_debug("rstate = 0x%x\n", in_be32(&ucc_pram->rstate));
-+ pr_debug("rdptr = 0x%x\n", in_be32(&ucc_pram->rdptr));
-+ pr_debug("tbase = 0x%x\n", in_be32(&ucc_pram->tbase));
-+ pr_debug("tbptr = 0x%x\n", in_be32(&ucc_pram->tbptr));
-+ pr_debug("tbdlen = 0x%x\n", in_be16(&ucc_pram->tbdlen));
-+ pr_debug("tbdstat = 0x%x\n", in_be16(&ucc_pram->tbdstat));
-+ pr_debug("tstate = 0x%x\n", in_be32(&ucc_pram->tstate));
-+ pr_debug("tdptr = 0x%x\n", in_be32(&ucc_pram->tdptr));
-+#endif
-+}
-+
-+/*
-+ * For use when a framing bit is not present
-+ * Program current-route SI ram
-+ * Set SIxRAM TDMx
-+ * Entries must be in units of 8.
-+ * SIR_UCC -> Channel Select
-+ * SIR_CNT -> Number of bits or bytes
-+ * SIR_BYTE -> Byte or Bit resolution
-+ * SIR_LAST -> Indicates last entry in SIxRAM
-+ * SIR_IDLE -> The Tx data pin is Tri-stated and the Rx data pin is
-+ * ignored
-+ */
-+static void set_siram(struct tdm_ctrl *tdm_c, enum comm_dir dir)
-+{
-+ const u16 *mask;
-+ u16 temp_mask = 1;
-+ u16 siram_code = 0;
-+ u32 i, j, k;
-+ u32 ucc;
-+ u32 phy_num_ts;
-+
-+ phy_num_ts = tdm_c->physical_num_ts;
-+ ucc = tdm_c->ut_info->uf_info.ucc_num;
-+
-+ if (dir == COMM_DIR_RX)
-+ mask = tdm_c->rx_mask;
-+ else
-+ mask = tdm_c->tx_mask;
-+ k = 0;
-+ j = 0;
-+ for (i = 0; i < phy_num_ts; i++) {
-+ if ((mask[k] & temp_mask) == temp_mask)
-+ siram_code = SIR_UCC(ucc) | SIR_CNT(0) | SIR_BYTE;
-+ else
-+ siram_code = SIR_IDLE | SIR_CNT(0) | SIR_BYTE;
-+ if (dir == COMM_DIR_RX)
-+ out_be16((u16 *)&qe_immr->sir.rx[i * 2], siram_code);
-+ else
-+ out_be16((u16 *)&qe_immr->sir.tx[i * 2], siram_code);
-+ temp_mask = temp_mask << 1;
-+ j++;
-+ if (j >= 16) {
-+ j = 0;
-+ temp_mask = 0x0001;
-+ k++;
-+ }
-+ }
-+ siram_code = siram_code | SIR_LAST;
-+
-+ if (dir == COMM_DIR_RX)
-+ out_be16((u16 *)&qe_immr->sir.rx[(phy_num_ts - 1) * 2],
-+ siram_code);
-+ else
-+ out_be16((u16 *)&qe_immr->sir.tx[(phy_num_ts - 1) * 2],
-+ siram_code);
-+}
-+
-+static void config_si(struct tdm_ctrl *tdm_c)
-+{
-+ u8 rxsyncdelay, txsyncdelay, tdm_port;
-+ u16 sixmr_val = 0;
-+ u32 tdma_mode_off;
-+ u16 *si1_tdm_mode_reg;
-+
-+ tdm_port = tdm_c->tdm_port;
-+
-+ set_siram(tdm_c, COMM_DIR_RX);
-+
-+ set_siram(tdm_c, COMM_DIR_TX);
-+
-+ rxsyncdelay = tdm_c->cfg_ctrl.rx_fr_sync_delay;
-+ txsyncdelay = tdm_c->cfg_ctrl.tx_fr_sync_delay;
-+ if (tdm_c->cfg_ctrl.com_pin)
-+ sixmr_val |= SIMODE_CRT;
-+ if (tdm_c->cfg_ctrl.fr_sync_level == 1)
-+ sixmr_val |= SIMODE_SL;
-+ if (tdm_c->cfg_ctrl.clk_edge == 1)
-+ sixmr_val |= SIMODE_CE;
-+ if (tdm_c->cfg_ctrl.fr_sync_edge == 1)
-+ sixmr_val |= SIMODE_FE;
-+ sixmr_val |= (SIMODE_TFSD(txsyncdelay) | SIMODE_RFSD(rxsyncdelay));
-+
-+ tdma_mode_off = SI_TDM_MODE_REGISTER_OFFSET * tdm_c->tdm_port;
-+
-+ si1_tdm_mode_reg = (u8 *)&qe_immr->si1 + tdma_mode_off;
-+ out_be16(si1_tdm_mode_reg, sixmr_val);
-+
-+ dump_siram(tdm_c);
-+}
-+
-+static int tdm_init(struct tdm_ctrl *tdm_c)
-+{
-+ u32 tdm_port, ucc, act_num_ts;
-+ int ret, i, err;
-+ u32 cecr_subblock;
-+ u32 pram_offset;
-+ u32 rxbdt_offset;
-+ u32 txbdt_offset;
-+ u32 rx_ucode_buf_offset, tx_ucode_buf_offset;
-+ u16 bd_status, bd_len;
-+ enum qe_clock clock;
-+ struct qe_bd __iomem *rx_bd, *tx_bd;
-+
-+ tdm_port = tdm_c->tdm_port;
-+ ucc = tdm_c->ut_info->uf_info.ucc_num;
-+ act_num_ts = tdm_c->cfg_ctrl.active_num_ts;
-+
-+ /*
-+ * TDM Tx and Rx CLKs = 2048 KHz.
-+ */
-+ if (strstr(tdm_c->ut_info->uf_info.tdm_tx_clk, "BRG")) {
-+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_tx_clk);
-+ err = qe_setbrg(clock, 2048000, 1);
-+ if (err < 0) {
-+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
-+ tdm_c->ut_info->uf_info.tdm_tx_clk);
-+ return err;
-+ }
-+ }
-+ if (strstr(tdm_c->ut_info->uf_info.tdm_rx_clk, "BRG")) {
-+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_rx_clk);
-+ err = qe_setbrg(clock, 2048000, 1);
-+ if (err < 0) {
-+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
-+ tdm_c->ut_info->uf_info.tdm_rx_clk);
-+ return err;
-+ }
-+ }
-+ /*
-+ * TDM FSyncs = 4 KHz.
-+ */
-+ if (strstr(tdm_c->ut_info->uf_info.tdm_tx_sync, "BRG")) {
-+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_tx_sync);
-+ err = qe_setbrg(clock, 4000, 1);
-+ if (err < 0) {
-+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
-+ tdm_c->ut_info->uf_info.tdm_tx_sync);
-+ return err;
-+ }
-+ }
-+ if (strstr(tdm_c->ut_info->uf_info.tdm_rx_sync, "BRG")) {
-+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_rx_sync);
-+ err = qe_setbrg(clock, 4000, 1);
-+ if (err < 0) {
-+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
-+ tdm_c->ut_info->uf_info.tdm_rx_sync);
-+ return err;
-+ }
-+ }
-+
-+ tdm_c->ut_info->uf_info.uccm_mask = (u32)
-+ ((UCC_TRANS_UCCE_RXB | UCC_TRANS_UCCE_BSY) << 16);
-+
-+ if (ucc_fast_init(&(tdm_c->ut_info->uf_info), &tdm_c->uf_private)) {
-+ printk(KERN_ERR "%s: Failed to init uccf\n", __FUNCTION__);
-+ return -ENOMEM;
-+ }
-+
-+ ucc_fast_disable(tdm_c->uf_private, COMM_DIR_RX | COMM_DIR_TX);
-+
-+ /* Write to QE CECR, UCCx channel to Stop Transmission */
-+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
-+ qe_issue_cmd(QE_STOP_TX, cecr_subblock,
-+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
-+
-+ pram_offset = qe_muram_alloc(UCC_TRANSPARENT_PRAM_SIZE,
-+ ALIGNMENT_OF_UCC_SLOW_PRAM);
-+ if (IS_ERR_VALUE(pram_offset)) {
-+ printk(KERN_ERR "%s: Cannot allocate MURAM memory for"
-+ " transparent UCC\n", __FUNCTION__);
-+ ret = -ENOMEM;
-+ goto pram_alloc_error;
-+ }
-+
-+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
-+ qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
-+ QE_CR_PROTOCOL_UNSPECIFIED, pram_offset);
-+
-+ tdm_c->ucc_pram = qe_muram_addr(pram_offset);
-+ tdm_c->ucc_pram_offset = pram_offset;
-+
-+ /*
-+ * zero-out pram, this will also ensure RSTATE, TSTATE are cleared, also
-+ * DISFC & CRCEC counters will be initialized.
-+ */
-+ memset(tdm_c->ucc_pram, 0, sizeof(struct ucc_transparent_pram));
-+
-+ /* rbase, tbase alignment is 8. */
-+ rxbdt_offset = qe_muram_alloc(NR_BUFS * sizeof(struct qe_bd),
-+ QE_ALIGNMENT_OF_BD);
-+ if (IS_ERR_VALUE(rxbdt_offset)) {
-+ printk(KERN_ERR "%s: Cannot allocate MURAM memory for RxBDs\n",
-+ __FUNCTION__);
-+ ret = -ENOMEM;
-+ goto rxbd_alloc_error;
-+ }
-+ txbdt_offset = qe_muram_alloc(NR_BUFS * sizeof(struct qe_bd),
-+ QE_ALIGNMENT_OF_BD);
-+ if (IS_ERR_VALUE(txbdt_offset)) {
-+ printk(KERN_ERR "%s: Cannot allocate MURAM memory for TxBDs\n",
-+ __FUNCTION__);
-+ ret = -ENOMEM;
-+ goto txbd_alloc_error;
-+ }
-+ tdm_c->tx_bd = qe_muram_addr(txbdt_offset);
-+ tdm_c->rx_bd = qe_muram_addr(rxbdt_offset);
-+
-+ tdm_c->tx_bd_offset = txbdt_offset;
-+ tdm_c->rx_bd_offset = rxbdt_offset;
-+
-+ rx_bd = tdm_c->rx_bd;
-+ tx_bd = tdm_c->tx_bd;
-+
-+ out_be32(&tdm_c->ucc_pram->rbase, (u32) immrbar_virt_to_phys(rx_bd));
-+ out_be32(&tdm_c->ucc_pram->tbase, (u32) immrbar_virt_to_phys(tx_bd));
-+
-+ for (i = 0; i < NR_BUFS - 1; i++) {
-+ bd_status = (u16) ((R_E | R_CM | R_I) >> 16);
-+ bd_len = 0;
-+ out_be16(&rx_bd->length, bd_len);
-+ out_be16(&rx_bd->status, bd_status);
-+ out_be32(&rx_bd->buf,
-+ tdm_c->dma_input_addr + i * SAMPLE_DEPTH * act_num_ts);
-+ rx_bd += 1;
-+
-+ bd_status = (u16) ((T_R | T_CM) >> 16);
-+ bd_len = SAMPLE_DEPTH * act_num_ts;
-+ out_be16(&tx_bd->length, bd_len);
-+ out_be16(&tx_bd->status, bd_status);
-+ out_be32(&tx_bd->buf,
-+ tdm_c->dma_output_addr + i * SAMPLE_DEPTH * act_num_ts);
-+ tx_bd += 1;
-+ }
-+
-+ bd_status = (u16) ((R_E | R_CM | R_I | R_W) >> 16);
-+ bd_len = 0;
-+ out_be16(&rx_bd->length, bd_len);
-+ out_be16(&rx_bd->status, bd_status);
-+ out_be32(&rx_bd->buf,
-+ tdm_c->dma_input_addr + i * SAMPLE_DEPTH * act_num_ts);
-+
-+ bd_status = (u16) ((T_R | T_CM | T_W) >> 16);
-+ bd_len = SAMPLE_DEPTH * act_num_ts;
-+ out_be16(&tx_bd->length, bd_len);
-+ out_be16(&tx_bd->status, bd_status);
-+ out_be32(&tx_bd->buf,
-+ tdm_c->dma_output_addr + i * SAMPLE_DEPTH * act_num_ts);
-+
-+ config_si(tdm_c);
-+
-+ setbits32(&qe_immr->ic.qimr, (0x80000000UL >> ucc));
-+
-+ rx_ucode_buf_offset = qe_muram_alloc(32, 32);
-+ if (IS_ERR_VALUE(rx_ucode_buf_offset)) {
-+ printk(KERN_ERR "%s: Cannot allocate MURAM mem for Rx"
-+ " ucode buf\n", __FUNCTION__);
-+ ret = -ENOMEM;
-+ goto rxucode_buf_alloc_error;
-+ }
-+
-+ tx_ucode_buf_offset = qe_muram_alloc(32, 32);
-+ if (IS_ERR_VALUE(tx_ucode_buf_offset)) {
-+ printk(KERN_ERR "%s: Cannot allocate MURAM mem for Tx"
-+ " ucode buf\n", __FUNCTION__);
-+ ret = -ENOMEM;
-+ goto txucode_buf_alloc_error;
-+ }
-+ out_be16(&tdm_c->ucc_pram->riptr, (u16) rx_ucode_buf_offset);
-+ out_be16(&tdm_c->ucc_pram->tiptr, (u16) tx_ucode_buf_offset);
-+
-+ tdm_c->rx_ucode_buf_offset = rx_ucode_buf_offset;
-+ tdm_c->tx_ucode_buf_offset = tx_ucode_buf_offset;
-+
-+ /*
-+ * set the receive buffer descriptor maximum size to be
-+ * SAMPLE_DEPTH * number of active RX channels
-+ */
-+ out_be16(&tdm_c->ucc_pram->mrblr, (u16) SAMPLE_DEPTH * act_num_ts);
-+
-+ /*
-+ * enable snooping and BE byte ordering on the UCC pram's
-+ * tstate & rstate registers.
-+ */
-+ out_be32(&tdm_c->ucc_pram->tstate, 0x30000000UL);
-+ out_be32(&tdm_c->ucc_pram->rstate, 0x30000000UL);
-+
-+ /*Put UCC transparent controller into serial interface mode. */
-+ out_be32(&tdm_c->uf_regs->upsmr, 0);
-+
-+ /* Reset TX and RX for UCCx */
-+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
-+ qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
-+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
-+
-+ return 0;
-+
-+txucode_buf_alloc_error:
-+ qe_muram_free(rx_ucode_buf_offset);
-+rxucode_buf_alloc_error:
-+ qe_muram_free(txbdt_offset);
-+txbd_alloc_error:
-+ qe_muram_free(rxbdt_offset);
-+rxbd_alloc_error:
-+ qe_muram_free(pram_offset);
-+pram_alloc_error:
-+ ucc_fast_free(tdm_c->uf_private);
-+ return ret;
-+}
-+
-+static void tdm_deinit(struct tdm_ctrl *tdm_c)
-+{
-+ qe_muram_free(tdm_c->rx_ucode_buf_offset);
-+ qe_muram_free(tdm_c->tx_ucode_buf_offset);
-+
-+ if (tdm_c->rx_bd_offset) {
-+ qe_muram_free(tdm_c->rx_bd_offset);
-+ tdm_c->rx_bd = NULL;
-+ tdm_c->rx_bd_offset = 0;
-+ }
-+ if (tdm_c->tx_bd_offset) {
-+ qe_muram_free(tdm_c->tx_bd_offset);
-+ tdm_c->tx_bd = NULL;
-+ tdm_c->tx_bd_offset = 0;
-+ }
-+ if (tdm_c->ucc_pram_offset) {
-+ qe_muram_free(tdm_c->ucc_pram_offset);
-+ tdm_c->ucc_pram = NULL;
-+ tdm_c->ucc_pram_offset = 0;
-+ }
-+}
-+
-+
-+static irqreturn_t tdm_isr(int irq, void *dev_id)
-+{
-+ u8 *input_tdm_buffer, *output_tdm_buffer;
-+ u32 txb, rxb;
-+ u32 ucc;
-+ register u32 ucce = 0;
-+ struct tdm_ctrl *tdm_c;
-+ tdm_c = (struct tdm_ctrl *)dev_id;
-+
-+ tdm_c->tdm_icnt++;
-+ ucc = tdm_c->ut_info->uf_info.ucc_num;
-+ input_tdm_buffer = tdm_c->tdm_input_data;
-+ output_tdm_buffer = tdm_c->tdm_output_data;
-+
-+ if (in_be32(tdm_c->uf_private->p_ucce) &
-+ (UCC_TRANS_UCCE_BSY << 16)) {
-+ out_be32(tdm_c->uf_private->p_ucce,
-+ (UCC_TRANS_UCCE_BSY << 16));
-+ pr_info("%s: From tdm isr busy interrupt\n",
-+ __FUNCTION__);
-+ dump_ucc(tdm_c);
-+
-+ return IRQ_HANDLED;
-+ }
-+
-+ if (tdm_c->tdm_flag == 1) {
-+ /* track phases for Rx/Tx */
-+ tdm_c->phase_rx += 1;
-+ if (tdm_c->phase_rx == MAX_PHASE)
-+ tdm_c->phase_rx = 0;
-+
-+ tdm_c->phase_tx += 1;
-+ if (tdm_c->phase_tx == MAX_PHASE)
-+ tdm_c->phase_tx = 0;
-+
-+#ifdef CONFIG_TDM_HW_LB_TSA_SLIC
-+ {
-+ u32 temp_rx, temp_tx, phase_tx, phase_rx;
-+ int i;
-+ phase_rx = tdm_c->phase_rx;
-+ phase_tx = tdm_c->phase_tx;
-+ if (phase_rx == 0)
-+ phase_rx = MAX_PHASE;
-+ else
-+ phase_rx -= 1;
-+ if (phase_tx == 0)
-+ phase_tx = MAX_PHASE;
-+ else
-+ phase_tx -= 1;
-+ temp_rx = phase_rx * SAMPLE_DEPTH * ACTIVE_CH;
-+ temp_tx = phase_tx * SAMPLE_DEPTH * ACTIVE_CH;
-+
-+ /*check if loopback received data on TS0 is correct. */
-+ pr_debug("%s: check if loopback received data on TS0"
-+ " is correct\n", __FUNCTION__);
-+ pr_debug("%d,%d ", phase_rx, phase_tx);
-+ for (i = 0; i < 8; i++)
-+ pr_debug("%1d,%1d ",
-+ input_tdm_buffer[temp_rx + i],
-+ output_tdm_buffer[temp_tx + i]);
-+ pr_debug("\n");
-+ }
-+#endif
-+
-+ /* schedule BH */
-+ wake_up_interruptible(&tdm_c->wakeup_event);
-+ } else {
-+ if (tdm_c->tdm_icnt == STUTTER_INT_CNT) {
-+ txb = in_be32(&tdm_c->ucc_pram->tbptr) -
-+ in_be32(&tdm_c->ucc_pram->tbase);
-+ rxb = in_be32(&tdm_c->ucc_pram->rbptr) -
-+ in_be32(&tdm_c->ucc_pram->rbase);
-+ tdm_c->phase_tx = txb / sizeof(struct qe_bd);
-+ tdm_c->phase_rx = rxb / sizeof(struct qe_bd);
-+
-+#ifdef CONFIG_TDM_HW_LB_TSA_SLIC
-+ tdm_c->phase_tx = tdm_c->phase_rx;
-+#endif
-+
-+ /* signal "stuttering" period is over */
-+ tdm_c->tdm_flag = 1;
-+
-+ pr_debug("%s: stuttering period is over\n",
-+ __FUNCTION__);
-+
-+ if (in_be32(tdm_c->uf_private->p_ucce) &
-+ (UCC_TRANS_UCCE_TXE << 16)) {
-+ u32 cecr_subblock;
-+ out_be32(tdm_c->uf_private->p_ucce,
-+ (UCC_TRANS_UCCE_TXE << 16));
-+ pr_debug("%s: From tdm isr txe interrupt\n",
-+ __FUNCTION__);
-+
-+ cecr_subblock =
-+ ucc_fast_get_qe_cr_subblock(ucc);
-+ qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
-+ (u8) QE_CR_PROTOCOL_UNSPECIFIED,
-+ 0);
-+ }
-+ }
-+ }
-+
-+ ucce = (in_be32(tdm_c->uf_private->p_ucce)
-+ & in_be32(tdm_c->uf_private->p_uccm));
-+
-+ out_be32(tdm_c->uf_private->p_ucce, ucce);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int tdm_start(struct tdm_ctrl *tdm_c)
-+{
-+ if (request_irq(tdm_c->ut_info->uf_info.irq, tdm_isr,
-+ 0, "tdm", tdm_c)) {
-+ printk(KERN_ERR "%s: request_irq for tdm_isr failed\n",
-+ __FUNCTION__);
-+ return -ENODEV;
-+ }
-+
-+ ucc_fast_enable(tdm_c->uf_private, COMM_DIR_RX | COMM_DIR_TX);
-+
-+ pr_info("%s 16-bit linear pcm mode active with"
-+ " slots 0 & 2\n", __FUNCTION__);
-+
-+ dump_siram(tdm_c);
-+ dump_ucc(tdm_c);
-+
-+ setbits8(&(qe_immr->si1.siglmr1_h), (0x1 << tdm_c->tdm_port));
-+ pr_info("%s UCC based TDM enabled\n", __FUNCTION__);
-+
-+ return 0;
-+}
-+
-+static void tdm_stop(struct tdm_ctrl *tdm_c)
-+{
-+ u32 port, si;
-+ u32 ucc;
-+ u32 cecr_subblock;
-+
-+ port = tdm_c->tdm_port;
-+ si = tdm_c->si;
-+ ucc = tdm_c->ut_info->uf_info.ucc_num;
-+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
-+
-+ qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
-+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
-+ qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock,
-+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
-+
-+ clrbits8(&qe_immr->si1.siglmr1_h, (0x1 << port));
-+ ucc_fast_disable(tdm_c->uf_private, COMM_DIR_RX);
-+ ucc_fast_disable(tdm_c->uf_private, COMM_DIR_TX);
-+ free_irq(tdm_c->ut_info->uf_info.irq, tdm_c);
-+}
-+
-+
-+static void config_tdm(struct tdm_ctrl *tdm_c)
-+{
-+ u32 i, j, k;
-+
-+ j = 0;
-+ k = 0;
-+
-+ /* Set Mask Bits */
-+ for (i = 0; i < ACTIVE_CH; i++) {
-+ tdm_c->tx_mask[k] |= (1 << j);
-+ tdm_c->rx_mask[k] |= (1 << j);
-+ j++;
-+ if (j >= 16) {
-+ j = 0;
-+ k++;
-+ }
-+ }
-+ /* physical number of slots in a frame */
-+ tdm_c->physical_num_ts = NUM_TS;
-+
-+ /* common receive and transmit pins */
-+ tdm_c->cfg_ctrl.com_pin = 1;
-+
-+ /* L1R/TSYNC active logic "1" */
-+ tdm_c->cfg_ctrl.fr_sync_level = 0;
-+
-+ /*
-+ * TX data on rising edge of clock
-+ * RX data on falling edge
-+ */
-+ tdm_c->cfg_ctrl.clk_edge = 0;
-+
-+ /* Frame sync sampled on falling edge */
-+ tdm_c->cfg_ctrl.fr_sync_edge = 0;
-+
-+ /* no bit delay */
-+ tdm_c->cfg_ctrl.rx_fr_sync_delay = 0;
-+
-+ /* no bit delay */
-+ tdm_c->cfg_ctrl.tx_fr_sync_delay = 0;
-+
-+#ifndef CONFIG_TDM_HW_LB_TSA_SLIC
-+ if (tdm_c->leg_slic) {
-+ /* Need 1 bit delay for Legrity SLIC */
-+ tdm_c->cfg_ctrl.rx_fr_sync_delay = 1;
-+ tdm_c->cfg_ctrl.tx_fr_sync_delay = 1;
-+ pr_info("%s Delay for Legerity!\n", __FUNCTION__);
-+ }
-+#endif
-+
-+ tdm_c->cfg_ctrl.active_num_ts = ACTIVE_CH;
-+}
-+
-+static void tdm_read(u32 client_id, short chn_id, short *pcm_buffer,
-+ short len)
-+{
-+ int i;
-+ u32 phase_rx;
-+ /* point to where to start for the current phase data processing */
-+ u32 temp_rx;
-+
-+ struct tdm_ctrl *tdm_c = tdm_ctrl[client_id];
-+
-+ u16 *input_tdm_buffer =
-+ (u16 *)tdm_c->tdm_input_data;
-+
-+ phase_rx = tdm_c->phase_rx;
-+ if (phase_rx == 0)
-+ phase_rx = MAX_PHASE;
-+ else
-+ phase_rx -= 1;
-+
-+ temp_rx = phase_rx * SAMPLE_DEPTH * EFF_ACTIVE_CH;
-+
-+#ifdef UCC_CACHE_SNOOPING_DISABLED
-+ flush_dcache_range((size_t) &input_tdm_buffer[temp_rx],
-+ (size_t) &input_tdm_buffer[temp_rx +
-+ SAMPLE_DEPTH * ACTIVE_CH]);
-+#endif
-+ for (i = 0; i < len; i++)
-+ pcm_buffer[i] =
-+ input_tdm_buffer[i * EFF_ACTIVE_CH + temp_rx + chn_id];
-+
-+}
-+
-+static void tdm_write(u32 client_id, short chn_id, short *pcm_buffer,
-+ short len)
-+{
-+ int i;
-+ int phase_tx;
-+ u32 txb;
-+ /* point to where to start for the current phase data processing */
-+ int temp_tx;
-+ struct tdm_ctrl *tdm_c = tdm_ctrl[client_id];
-+
-+ u16 *output_tdm_buffer;
-+ output_tdm_buffer = (u16 *)tdm_c->tdm_output_data;
-+ txb = in_be32(&tdm_c->ucc_pram->tbptr) -
-+ in_be32(&tdm_c->ucc_pram->tbase);
-+ phase_tx = txb / sizeof(struct qe_bd);
-+
-+ if (phase_tx == 0)
-+ phase_tx = MAX_PHASE;
-+ else
-+ phase_tx -= 1;
-+
-+ temp_tx = phase_tx * SAMPLE_DEPTH * EFF_ACTIVE_CH;
-+
-+ for (i = 0; i < len; i++)
-+ output_tdm_buffer[i * EFF_ACTIVE_CH + temp_tx + chn_id] =
-+ pcm_buffer[i];
-+
-+#ifdef UCC_CACHE_SNOOPING_DISABLED
-+ flush_dcache_range((size_t) &output_tdm_buffer[temp_tx],
-+ (size_t) &output_tdm_buffer[temp_tx + SAMPLE_DEPTH *
-+ ACTIVE_CH]);
-+#endif
-+}
-+
-+
-+static int tdm_register_client(struct tdm_client *tdm_client)
-+{
-+ u32 i;
-+ if (num_tdm_clients == num_tdm_devices) {
-+ printk(KERN_ERR "all TDM devices busy\n");
-+ return -EBUSY;
-+ }
-+
-+ for (i = 0; i < num_tdm_devices; i++) {
-+ if (!tdm_ctrl[i]->device_busy) {
-+ tdm_ctrl[i]->device_busy = 1;
-+ break;
-+ }
-+ }
-+ num_tdm_clients++;
-+ tdm_client->client_id = i;
-+ tdm_client->tdm_read = tdm_read;
-+ tdm_client->tdm_write = tdm_write;
-+ tdm_client->wakeup_event =
-+ &(tdm_ctrl[i]->wakeup_event);
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(tdm_register_client);
-+
-+static int tdm_deregister_client(struct tdm_client *tdm_client)
-+{
-+ num_tdm_clients--;
-+ tdm_ctrl[tdm_client->client_id]->device_busy = 0;
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(tdm_deregister_client);
-+
-+static int ucc_tdm_probe(struct of_device *ofdev,
-+ const struct of_device_id *match)
-+{
-+ struct device_node *np = ofdev->node;
-+ struct resource res;
-+ const unsigned int *prop;
-+ u32 ucc_num, device_num, err, ret = 0;
-+ struct device_node *np_tmp;
-+ dma_addr_t physaddr;
-+ void *tdm_buff;
-+ struct ucc_tdm_info *ut_info;
-+
-+ prop = of_get_property(np, "device-id", NULL);
-+ if (prop == NULL) {
-+ printk(KERN_ERR "ucc_tdm: device-id missing\n");
-+ return -ENODEV;
-+ }
-+
-+ ucc_num = *prop - 1;
-+ if ((ucc_num < 0) || (ucc_num > 7))
-+ return -ENODEV;
-+
-+ ut_info = &utdm_info[ucc_num];
-+ if (ut_info->ucc_busy) {
-+ printk(KERN_ERR "ucc_tdm: UCC in use by another TDM driver"
-+ "instance\n");
-+ return -EBUSY;
-+ }
-+ if (num_tdm_devices == MAX_NUM_TDM_DEVICES) {
-+ printk(KERN_ERR "ucc_tdm: All TDM devices already"
-+ " initialized\n");
-+ return -ENODEV;
-+ }
-+
-+ ut_info->ucc_busy = 1;
-+ tdm_ctrl[num_tdm_devices++] =
-+ kzalloc(sizeof(struct tdm_ctrl), GFP_KERNEL);
-+ if (!tdm_ctrl[num_tdm_devices - 1]) {
-+ printk(KERN_ERR "ucc_tdm: no memory to allocate for"
-+ " tdm control structure\n");
-+ num_tdm_devices--;
-+ return -ENOMEM;
-+ }
-+ device_num = num_tdm_devices - 1;
-+
-+ tdm_ctrl[device_num]->device = &ofdev->dev;
-+ tdm_ctrl[device_num]->ut_info = ut_info;
-+
-+ tdm_ctrl[device_num]->ut_info->uf_info.ucc_num = ucc_num;
-+
-+ prop = of_get_property(np, "fsl,tdm-num", NULL);
-+ if (prop == NULL) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ tdm_ctrl[device_num]->tdm_port = *prop - 1;
-+
-+ if (tdm_ctrl[device_num]->tdm_port > 3) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ prop = of_get_property(np, "fsl,si-num", NULL);
-+ if (prop == NULL) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ tdm_ctrl[device_num]->si = *prop - 1;
-+
-+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_clk =
-+ of_get_property(np, "fsl,tdm-tx-clk", NULL);
-+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_clk == NULL) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_clk =
-+ of_get_property(np, "fsl,tdm-rx-clk", NULL);
-+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_clk == NULL) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_sync =
-+ of_get_property(np, "fsl,tdm-tx-sync", NULL);
-+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_sync == NULL) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_sync =
-+ of_get_property(np, "fsl,tdm-rx-sync", NULL);
-+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_sync == NULL) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+
-+ tdm_ctrl[device_num]->ut_info->uf_info.irq =
-+ irq_of_parse_and_map(np, 0);
-+ err = of_address_to_resource(np, 0, &res);
-+ if (err) {
-+ ret = -EINVAL;
-+ goto get_property_error;
-+ }
-+ tdm_ctrl[device_num]->ut_info->uf_info.regs = res.start;
-+ tdm_ctrl[device_num]->uf_regs = of_iomap(np, 0);
-+
-+ np_tmp = NULL;
-+ np_tmp = of_find_compatible_node(np_tmp, "slic", "legerity-slic");
-+ if (np_tmp != NULL) {
-+ tdm_ctrl[device_num]->leg_slic = 1;
-+ of_node_put(np_tmp);
-+ } else
-+ tdm_ctrl[device_num]->leg_slic = 0;
-+
-+ config_tdm(tdm_ctrl[device_num]);
-+
-+ tdm_buff = dma_alloc_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH *
-+ tdm_ctrl[device_num]->cfg_ctrl.active_num_ts,
-+ &physaddr, GFP_KERNEL);
-+ if (!tdm_buff) {
-+ printk(KERN_ERR "ucc-tdm: could not allocate buffer"
-+ "descriptors\n");
-+ ret = -ENOMEM;
-+ goto alloc_error;
-+ }
-+
-+ tdm_ctrl[device_num]->tdm_input_data = tdm_buff;
-+ tdm_ctrl[device_num]->dma_input_addr = physaddr;
-+
-+ tdm_ctrl[device_num]->tdm_output_data = tdm_buff + NR_BUFS *
-+ SAMPLE_DEPTH * tdm_ctrl[device_num]->cfg_ctrl.active_num_ts;
-+ tdm_ctrl[device_num]->dma_output_addr = physaddr + NR_BUFS *
-+ SAMPLE_DEPTH * tdm_ctrl[device_num]->cfg_ctrl.active_num_ts;
-+
-+ init_waitqueue_head(&(tdm_ctrl[device_num]->wakeup_event));
-+
-+ ret = tdm_init(tdm_ctrl[device_num]);
-+ if (ret != 0)
-+ goto tdm_init_error;
-+
-+ ret = tdm_start(tdm_ctrl[device_num]);
-+ if (ret != 0)
-+ goto tdm_start_error;
-+
-+ dev_set_drvdata(&(ofdev->dev), tdm_ctrl[device_num]);
-+
-+ pr_info("%s UCC based tdm module installed\n", __FUNCTION__);
-+ return 0;
-+
-+tdm_start_error:
-+ tdm_deinit(tdm_ctrl[device_num]);
-+tdm_init_error:
-+ dma_free_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH *
-+ tdm_ctrl[device_num]->cfg_ctrl.active_num_ts,
-+ tdm_ctrl[device_num]->tdm_input_data,
-+ tdm_ctrl[device_num]->dma_input_addr);
-+
-+alloc_error:
-+ irq_dispose_mapping(tdm_ctrl[device_num]->ut_info->uf_info.irq);
-+ iounmap(tdm_ctrl[device_num]->uf_regs);
-+
-+get_property_error:
-+ num_tdm_devices--;
-+ kfree(tdm_ctrl[device_num]);
-+ ut_info->ucc_busy = 0;
-+ return ret;
-+}
-+
-+static int ucc_tdm_remove(struct of_device *ofdev)
-+{
-+ struct tdm_ctrl *tdm_c;
-+ struct ucc_tdm_info *ut_info;
-+ u32 ucc_num;
-+
-+ tdm_c = dev_get_drvdata(&(ofdev->dev));
-+ dev_set_drvdata(&(ofdev->dev), NULL);
-+ ucc_num = tdm_c->ut_info->uf_info.ucc_num;
-+ ut_info = &utdm_info[ucc_num];
-+ tdm_stop(tdm_c);
-+ tdm_deinit(tdm_c);
-+
-+ ucc_fast_free(tdm_c->uf_private);
-+
-+ dma_free_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH *
-+ tdm_c->cfg_ctrl.active_num_ts,
-+ tdm_c->tdm_input_data,
-+ tdm_c->dma_input_addr);
-+
-+ irq_dispose_mapping(tdm_c->ut_info->uf_info.irq);
-+ iounmap(tdm_c->uf_regs);
-+
-+ num_tdm_devices--;
-+ kfree(tdm_c);
-+
-+ ut_info->ucc_busy = 0;
-+
-+ pr_info("%s UCC based tdm module uninstalled\n", __FUNCTION__);
-+ return 0;
-+}
-+
-+const struct of_device_id ucc_tdm_match[] = {
-+ { .type = "tdm", .compatible = "fsl,ucc-tdm", },
-+ {},
-+};
-+
-+MODULE_DEVICE_TABLE(of, ucc_tdm_match);
-+
-+static struct of_platform_driver ucc_tdm_driver = {
-+ .name = DRV_NAME,
-+ .match_table = ucc_tdm_match,
-+ .probe = ucc_tdm_probe,
-+ .remove = ucc_tdm_remove,
-+ .driver = {
-+ .name = DRV_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init ucc_tdm_init(void)
-+{
-+ u32 i;
-+
-+ pr_info("ucc_tdm: " DRV_DESC "\n");
-+ for (i = 0; i < 8; i++)
-+ memcpy(&(utdm_info[i]), &utdm_primary_info,
-+ sizeof(utdm_primary_info));
-+
-+ return of_register_platform_driver(&ucc_tdm_driver);
-+}
-+
-+static void __exit ucc_tdm_exit(void)
-+{
-+ of_unregister_platform_driver(&ucc_tdm_driver);
-+}
-+
-+module_init(ucc_tdm_init);
-+module_exit(ucc_tdm_exit);
-+MODULE_AUTHOR("Freescale Semiconductor, Inc");
-+MODULE_DESCRIPTION(DRV_DESC);
-+MODULE_LICENSE("GPL");
---- a/drivers/misc/Makefile
-+++ b/drivers/misc/Makefile
-@@ -10,6 +10,7 @@ obj-$(CONFIG_INTEL_MID_PTI) += pti.o
- obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
- obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
- obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
-+obj-$(CONFIG_UCC_TDM) += ucc_tdm.o
- obj-$(CONFIG_BMP085) += bmp085.o
- obj-$(CONFIG_BMP085_I2C) += bmp085-i2c.o
- obj-$(CONFIG_BMP085_SPI) += bmp085-spi.o
---- a/drivers/misc/Kconfig
-+++ b/drivers/misc/Kconfig
-@@ -202,6 +202,20 @@ config ATMEL_SSC
-
- If unsure, say N.
-
-+config UCC_TDM
-+ tristate "Freescale UCC TDM Driver"
-+ depends on QUICC_ENGINE && UCC_FAST
-+ default n
-+ help
-+ The TDM driver is for UCC based TDM devices for example, TDM device on
-+ MPC832x RDB. Select it to run PowerVoIP on MPC832x RDB board.
-+ The TDM driver can interface with SLIC kind of devices to transmit
-+ and receive TDM samples. The TDM driver receives Time Division
-+ multiplexed samples(for different channels) from the SLIC device,
-+ demutiplexes them and sends them to the upper layers. At the transmit
-+ end the TDM drivers receives samples for different channels, it
-+ multiplexes them and sends them to the SLIC device.
-+
- config ENCLOSURE_SERVICES
- tristate "Enclosure Services"
- default n
---- a/arch/powerpc/include/asm/ucc_fast.h
-+++ b/arch/powerpc/include/asm/ucc_fast.h
-@@ -150,6 +150,10 @@ struct ucc_fast_info {
- enum ucc_fast_rx_decoding_method renc;
- enum ucc_fast_transparent_tcrc tcrc;
- enum ucc_fast_sync_len synl;
-+ char *tdm_rx_clk;
-+ char *tdm_tx_clk;
-+ char *tdm_rx_sync;
-+ char *tdm_tx_sync;
- };
-
- struct ucc_fast_private {
---- a/arch/powerpc/include/asm/qe.h
-+++ b/arch/powerpc/include/asm/qe.h
-@@ -670,6 +670,14 @@ struct ucc_slow_pram {
- #define UCC_GETH_UCCE_RXF1 0x00000002
- #define UCC_GETH_UCCE_RXF0 0x00000001
-
-+/* Transparent UCC Event Register (UCCE) */
-+#define UCC_TRANS_UCCE_GRA 0x0080
-+#define UCC_TRANS_UCCE_TXE 0x0010
-+#define UCC_TRANS_UCCE_RXF 0x0008
-+#define UCC_TRANS_UCCE_BSY 0x0004
-+#define UCC_TRANS_UCCE_TXB 0x0002
-+#define UCC_TRANS_UCCE_RXB 0x0001
-+
- /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
- #define UCC_UART_UPSMR_FLC 0x8000
- #define UCC_UART_UPSMR_SL 0x4000
+++ /dev/null
---- a/arch/powerpc/boot/Makefile
-+++ b/arch/powerpc/boot/Makefile
-@@ -89,7 +89,8 @@ src-plat-$(CONFIG_44x) += treeboot-ebony
- src-plat-$(CONFIG_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
- src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
- src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
--src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c
-+src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c \
-+ rb600.c rb333.c
- src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
- src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
- cuboot-c2k.c gamecube-head.S \
-@@ -261,6 +262,8 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.
- image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds
- image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds
- image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
-+image-$(CONFIG_RB_PPC) += dtbImage.rb600 \
-+ dtbImage.rb333
-
- # Board ports in arch/powerpc/platform/85xx/Kconfig
- image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
---- /dev/null
-+++ b/arch/powerpc/boot/dts/rb600.dts
-@@ -0,0 +1,283 @@
-+/*
-+ * RouterBOARD 600 series Device Tree Source
-+ *
-+ * Copyright 2009 Michael Guntsche <mike@it-loops.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+/dts-v1/;
-+
-+/ {
-+ model = "RB600";
-+ compatible = "MPC83xx";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ aliases {
-+ ethernet0 = &enet0;
-+ ethernet1 = &enet1;
-+ pci0 = &pci0;
-+ };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
-+ linux,stdout-path = "/soc8343@e0000000/serial@4500";
-+ };
-+
-+ cpus {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ PowerPC,8343E@0 {
-+ device_type = "cpu";
-+ reg = <0x0>;
-+ d-cache-line-size = <0x20>;
-+ i-cache-line-size = <0x20>;
-+ d-cache-size = <0x8000>;
-+ i-cache-size = <0x8000>;
-+ timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
-+ clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
-+ };
-+ };
-+
-+ memory {
-+ device_type = "memory";
-+ reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
-+ };
-+
-+ cf@f9200000 {
-+ lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
-+ interrupt-at-level = <0x0>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x16 0x8>;
-+ lbc_extra_divider = <0x1>;
-+ reg = <0xf9200000 0x200000>;
-+ device_type = "rb,cf";
-+ };
-+
-+ cf@f9000000 {
-+ lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
-+ interrupt-at-level = <0x0>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x14 0x8>;
-+ lbc_extra_divider = <0x1>;
-+ reg = <0xf9000000 0x200000>;
-+ device_type = "rb,cf";
-+ };
-+
-+ flash {
-+ reg = <0xff800000 0x20000>;
-+ };
-+
-+ nnand {
-+ reg = <0xf0000000 0x1000>;
-+ };
-+
-+ nand {
-+ ale = <&gpio 0x6>;
-+ cle = <&gpio 0x5>;
-+ nce = <&gpio 0x4>;
-+ rdy = <&gpio 0x3>;
-+ reg = <0xf8000000 0x1000>;
-+ device_type = "rb,nand";
-+ };
-+
-+ fancon {
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x17 0x8>;
-+ sense = <&gpio 0x7>;
-+ fan_on = <&gpio 0x9>;
-+ };
-+
-+ pci0: pci@e0008500 {
-+ device_type = "pci";
-+ compatible = "fsl,mpc8349-pci";
-+ reg = <0xe0008500 0x100 0xe0008300 0x8>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
-+ bus-range = <0x0 0x0>;
-+ interrupt-map = <
-+ 0x5800 0x0 0x0 0x1 &ipic 0x15 0x8
-+ 0x6000 0x0 0x0 0x1 &ipic 0x30 0x8
-+ 0x6000 0x0 0x0 0x2 &ipic 0x11 0x8
-+ 0x6800 0x0 0x0 0x1 &ipic 0x11 0x8
-+ 0x6800 0x0 0x0 0x2 &ipic 0x12 0x8
-+ 0x7000 0x0 0x0 0x1 &ipic 0x12 0x8
-+ 0x7000 0x0 0x0 0x2 &ipic 0x13 0x8
-+ 0x7800 0x0 0x0 0x1 &ipic 0x13 0x8
-+ 0x7800 0x0 0x0 0x2 &ipic 0x30 0x8
-+ 0x8000 0x0 0x0 0x1 &ipic 0x30 0x8
-+ 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
-+ 0x8000 0x0 0x0 0x3 &ipic 0x11 0x8
-+ 0x8000 0x0 0x0 0x4 &ipic 0x13 0x8
-+ 0xa000 0x0 0x0 0x1 &ipic 0x30 0x8
-+ 0xa000 0x0 0x0 0x2 &ipic 0x11 0x8
-+ 0xa000 0x0 0x0 0x3 &ipic 0x12 0x8
-+ 0xa000 0x0 0x0 0x4 &ipic 0x13 0x8
-+ 0xa800 0x0 0x0 0x1 &ipic 0x11 0x8
-+ 0xa800 0x0 0x0 0x2 &ipic 0x12 0x8
-+ 0xa800 0x0 0x0 0x3 &ipic 0x13 0x8
-+ 0xa800 0x0 0x0 0x4 &ipic 0x30 0x8>;
-+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-+ interrupt-parent = <&ipic>;
-+ };
-+
-+ soc8343@e0000000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ device_type = "soc";
-+ compatible = "simple-bus";
-+ ranges = <0x0 0xe0000000 0x100000>;
-+ reg = <0xe0000000 0x200>;
-+ bus-frequency = <0x1>;
-+
-+ led {
-+ user_led = <0x400 0x8>;
-+ };
-+
-+ beeper {
-+ reg = <0x500 0x100>;
-+ };
-+
-+ gpio: gpio@0 {
-+ reg = <0xc08 0x4>;
-+ device-id = <0x0>;
-+ compatible = "gpio";
-+ device_type = "gpio";
-+ };
-+
-+ dma@82a8 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
-+ reg = <0x82a8 4>;
-+ ranges = <0 0x8100 0x1a8>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ cell-index = <0>;
-+ dma-channel@0 {
-+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0 0x80>;
-+ cell-index = <0>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ dma-channel@80 {
-+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0x80 0x80>;
-+ cell-index = <1>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ dma-channel@100 {
-+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0x100 0x80>;
-+ cell-index = <2>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ dma-channel@180 {
-+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0x180 0x28>;
-+ cell-index = <3>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ };
-+
-+ enet0: ethernet@25000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ cell-index = <0>;
-+ phy-handle = <&phy0>;
-+ tbi-handle = <&tbi0>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
-+ local-mac-address = [00 00 00 00 00 00];
-+ reg = <0x25000 0x1000>;
-+ ranges = <0x0 0x25000 0x1000>;
-+ compatible = "gianfar";
-+ model = "TSEC";
-+ device_type = "network";
-+
-+ mdio@520 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "fsl,gianfar-tbi";
-+ reg = <0x520 0x20>;
-+
-+ tbi0: tbi-phy@11 {
-+ reg = <0x11>;
-+ device_type = "tbi-phy";
-+ };
-+ };
-+ };
-+
-+ enet1: ethernet@24000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ cell-index = <1>;
-+ phy-handle = <&phy1>;
-+ tbi-handle = <&tbi1>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
-+ local-mac-address = [00 00 00 00 00 00];
-+ reg = <0x24000 0x1000>;
-+ ranges = <0x0 0x24000 0x1000>;
-+ compatible = "gianfar";
-+ model = "TSEC";
-+ device_type = "network";
-+
-+ mdio@520 {
-+ #size-cells = <0x0>;
-+ #address-cells = <0x1>;
-+ reg = <0x520 0x20>;
-+ compatible = "fsl,gianfar-mdio";
-+
-+ phy0: ethernet-phy@0 {
-+ device_type = "ethernet-phy";
-+ reg = <0x0>;
-+ };
-+
-+ phy1: ethernet-phy@1 {
-+ device_type = "ethernet-phy";
-+ reg = <0x1>;
-+ };
-+
-+ tbi1: tbi-phy@11 {
-+ reg = <0x11>;
-+ device_type = "tbi-phy";
-+ };
-+ };
-+ };
-+
-+ ipic: pic@700 {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <2>;
-+ reg = <0x700 0x100>;
-+ device_type = "ipic";
-+ };
-+
-+ serial@4500 {
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x9 0x8>;
-+ clock-frequency = <0xfe4f840>;
-+ reg = <0x4500 0x100>;
-+ compatible = "ns16550";
-+ device_type = "serial";
-+ };
-+
-+ wdt@200 {
-+ reg = <0x200 0x100>;
-+ compatible = "mpc83xx_wdt";
-+ device_type = "watchdog";
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/powerpc/boot/rb600.c
-@@ -0,0 +1,70 @@
-+/*
-+ * The RouterBOARD platform -- for booting RB600(A) RouterBOARDs.
-+ *
-+ * Author: Michael Guntsche <mike@it-loops.com>
-+ *
-+ * Copyright (c) 2009 Michael Guntsche
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include "ops.h"
-+#include "types.h"
-+#include "io.h"
-+#include "stdio.h"
-+#include <libfdt.h>
-+
-+BSS_STACK(4*1024);
-+
-+u64 memsize64;
-+const void *fw_dtb;
-+
-+static void rb600_fixups(void)
-+{
-+ const u32 *reg, *timebase, *clock;
-+ int node, size;
-+
-+ dt_fixup_memory(0, memsize64);
-+
-+ /* Set the MAC addresses. */
-+ node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@24000");
-+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
-+ dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg);
-+
-+ node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@25000");
-+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
-+ dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg);
-+
-+ /* Find the CPU timebase and clock frequencies. */
-+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
-+ timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
-+ clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
-+ dt_fixup_cpu_clocks(*clock, *timebase, 0);
-+
-+}
-+
-+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-+ unsigned long r6, unsigned long r7)
-+{
-+ const u32 *reg;
-+ int node, size;
-+
-+ fw_dtb = (const void *)r3;
-+
-+ /* Find the memory range. */
-+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
-+ reg = fdt_getprop(fw_dtb, node, "reg", &size);
-+ memsize64 = reg[1];
-+
-+ /* Now we have the memory size; initialize the heap. */
-+ simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
-+
-+ /* Prepare the device tree and find the console. */
-+ fdt_init(_dtb_start);
-+ serial_console_init();
-+
-+ /* Remaining fixups... */
-+ platform_ops.fixups = rb600_fixups;
-+}
---- a/arch/powerpc/boot/wrapper
-+++ b/arch/powerpc/boot/wrapper
-@@ -217,7 +217,7 @@ ps3)
- make_space=n
- pie=
- ;;
--ep88xc|ep405|ep8248e)
-+ep88xc|ep405|ep8248e|rb600|rb333)
- platformo="$object/fixed-head.o $object/$platform.o"
- binary=y
- ;;
---- a/arch/powerpc/platforms/83xx/Kconfig
-+++ b/arch/powerpc/platforms/83xx/Kconfig
-@@ -38,6 +38,15 @@ config MPC832x_RDB
- help
- This option enables support for the MPC8323 RDB board.
-
-+config RB_PPC
-+ bool "MikroTik RouterBOARD 333/600 series"
-+ select DEFAULT_UIMAGE
-+ select QUICC_ENGINE
-+ select PPC_MPC832x
-+ select PPC_MPC834x
-+ help
-+ This option enables support for MikroTik RouterBOARD 333/600 series boards.
-+
- config MPC834x_MDS
- bool "Freescale MPC834x MDS"
- select DEFAULT_UIMAGE
---- /dev/null
-+++ b/arch/powerpc/boot/dts/rb333.dts
-@@ -0,0 +1,426 @@
-+
-+/*
-+ * RouterBOARD 333 series Device Tree Source
-+ *
-+ * Copyright 2010 Alexandros C. Couloumbis <alex@ozo.com>
-+ * Copyright 2009 Michael Guntsche <mike@it-loops.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
-+ * Warning (ranges_format): "ranges" property in /qe@e0100000/muram@10000 has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1)
-+ * Warning (avoid_default_addr_size): Relying on default #address-cells value for /qe@e0100000/muram@10000/data-only@0
-+ * Warning (avoid_default_addr_size): Relying on default #size-cells value for /qe@e0100000/muram@10000/data-only@0
-+ * Warning (obsolete_chosen_interrupt_controller): /chosen has obsolete "interrupt-controller" property
-+ *
-+ */
-+
-+
-+/dts-v1/;
-+
-+/ {
-+ model = "RB333";
-+ compatible = "MPC83xx";
-+ #size-cells = <1>;
-+ #address-cells = <1>;
-+
-+ aliases {
-+ ethernet0 = &enet0;
-+ ethernet1 = &enet1;
-+ ethernet2 = &enet2;
-+ pci0 = &pci0;
-+ };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
-+ // linux,platform = <0x8062>;
-+ // linux,initrd = <0x488000 0x0>;
-+ linux,stdout-path = "/soc8323@e0000000/serial@4500";
-+ // interrupt-controller = <&ipic>;
-+ };
-+
-+ cpus {
-+ #cpus = <1>;
-+ #size-cells = <0>;
-+ #address-cells = <1>;
-+
-+ PowerPC,8323E@0 {
-+ device_type = "cpu";
-+ reg = <0x0>;
-+ i-cache-size = <0x4000>;
-+ d-cache-size = <0x4000>;
-+ i-cache-line-size = <0x20>;
-+ d-cache-line-size = <0x20>;
-+ // clock-frequency = <0x13de3650>;
-+ // timebase-frequency = <0x1fc9f08>;
-+ timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
-+ clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
-+ 32-bit;
-+ };
-+ };
-+
-+ memory {
-+ device_type = "memory";
-+ reg = <0x0 0x4000000>;
-+ // reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
-+ };
-+
-+ flash {
-+ reg = <0xfe000000 0x20000>;
-+ };
-+
-+ nand {
-+ ale = <&gpio2 0x3>;
-+ cle = <&gpio2 0x2>;
-+ nce = <&gpio2 0x1>;
-+ rdy = <&gpio2 0x0>;
-+ reg = <0xf8000000 0x1000>;
-+ device_type = "rb,nand";
-+ };
-+
-+ nnand {
-+ reg = <0xf0000000 0x1000>;
-+ };
-+
-+ voltage {
-+ voltage_gpio = <&gpio3 0x11>;
-+ };
-+
-+ fancon {
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x14 0x8>;
-+ fan_on = <&gpio0 0x10>;
-+ };
-+
-+ soc8323@e0000000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ device_type = "soc";
-+ compatible = "simple-bus";
-+ ranges = <0x0 0xe0000000 0x00100000>;
-+ reg = <0xe0000000 0x00000200>;
-+ bus-frequency = <1>;
-+
-+ wdt@200 {
-+ device_type = "watchdog";
-+ compatible = "mpc83xx_wdt";
-+ reg = <0x200 0x100>;
-+ };
-+
-+ ipic:pic@700 {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <2>;
-+ reg = <0x700 0x100>;
-+ device_type = "ipic";
-+ };
-+
-+ par_io@1400 {
-+ num-ports = <4>;
-+ device_type = "par_io";
-+ reg = <0x1400 0x100>;
-+
-+ ucc2pio: ucc_pin@02 {
-+ pio-map = <
-+ /* port pin dir open_drain assignment has_irq */
-+ 3 4 3 0 2 0
-+ 3 5 1 0 2 0
-+ 0 18 1 0 1 0
-+ 0 19 1 0 1 0
-+ 0 20 1 0 1 0
-+ 0 21 1 0 1 0
-+ 0 30 1 0 1 0
-+ 3 6 2 0 1 0
-+ 0 29 2 0 1 0
-+ 0 31 2 0 1 0
-+ 0 22 2 0 1 0
-+ 0 23 2 0 1 0
-+ 0 24 2 0 1 0
-+ 0 25 2 0 1 0
-+ 0 28 2 0 1 0
-+ 0 26 2 0 1 0
-+ 3 31 2 0 1 0>;
-+ };
-+
-+ ucc3pio: ucc_pin@03 {
-+ pio-map = <
-+ /* port pin dir open_drain assignment has_irq */
-+ 1 0 1 0 1 0
-+ 1 1 1 0 1 0
-+ 1 2 1 0 1 0
-+ 1 3 1 0 1 0
-+ 1 12 1 0 1 0
-+ 3 24 2 0 1 0
-+ 1 11 2 0 1 0
-+ 1 13 2 0 1 0
-+ 1 4 2 0 1 0
-+ 1 5 2 0 1 0
-+ 1 6 2 0 1 0
-+ 1 7 2 0 1 0
-+ 1 10 2 0 1 0
-+ 1 8 2 0 1 0
-+ 3 29 2 0 1 0>;
-+ };
-+
-+ ucc4pio: ucc_pin@04 {
-+ pio-map = <
-+ /* port pin dir open_drain assignment has_irq */
-+ 1 18 1 0 1 0
-+ 1 19 1 0 1 0
-+ 1 20 1 0 1 0
-+ 1 21 1 0 1 0
-+ 1 30 1 0 1 0
-+ 3 20 2 0 1 0
-+ 1 30 2 0 1 0
-+ 1 31 2 0 1 0
-+ 1 22 2 0 1 0
-+ 1 23 2 0 1 0
-+ 1 24 2 0 1 0
-+ 1 25 2 0 1 0
-+ 1 28 2 0 1 0
-+ 1 26 2 0 1 0
-+ 3 21 2 0 1 0>;
-+ };
-+ };
-+
-+ serial0: serial@4500 {
-+ cell-index = <0>;
-+ device_type = "serial";
-+ compatible = "fsl,ns16550", "ns16550";
-+ reg = <0x4500 0x100>;
-+ clock-frequency = <0x7f27c20>;
-+ interrupts = <9 0x8>;
-+ interrupt-parent = <&ipic>;
-+ };
-+
-+ dma@82a8 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
-+ reg = <0x82a8 4>;
-+ ranges = <0 0x8100 0x1a8>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ cell-index = <0>;
-+ dma-channel@0 {
-+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0 0x80>;
-+ cell-index = <0>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ dma-channel@80 {
-+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0x80 0x80>;
-+ cell-index = <1>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ dma-channel@100 {
-+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0x100 0x80>;
-+ cell-index = <2>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ dma-channel@180 {
-+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
-+ reg = <0x180 0x28>;
-+ cell-index = <3>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <71 8>;
-+ };
-+ };
-+
-+ beeper {
-+ gpio = <&gpio3 0x12>;
-+ reg = <0x500 0x100>;
-+ interrupt-parent = <&ipic>;
-+ interrupts = <0x48 0x8>;
-+ };
-+
-+ gpio3: gpio@3 {
-+ reg = <0x144c 0x4>;
-+ device-id = <0x3>;
-+ compatible = "qe_gpio";
-+ device_type = "gpio";
-+ };
-+
-+ gpio2: gpio@2 {
-+ reg = <0x1434 0x4>;
-+ device-id = <0x2>;
-+ compatible = "qe_gpio";
-+ device_type = "gpio";
-+ };
-+
-+ gpio0: gpio@0 {
-+ reg = <0x1404 0x4>;
-+ device-id = <0x0>;
-+ compatible = "qe_gpio";
-+ device_type = "gpio";
-+ };
-+ };
-+
-+ pci0: pci@e0008500 {
-+ device_type = "pci";
-+ // compatible = "83xx";
-+ compatible = "fsl,mpc8349-pci";
-+ reg = <0xe0008500 0x100 0xe0008300 0x8>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ // clock-frequency = <0>;
-+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
-+ bus-range = <0x0 0x0>;
-+ interrupt-map = <
-+ /* IDSEL 0x10 AD16 miniPCI slot 0 */
-+ 0x8000 0x0 0x0 0x1 &ipic 0x11 0x8
-+ 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
-+
-+ /* IDSEL 0x11 AD17 miniPCI slot 1 */
-+ 0x8800 0x0 0x0 0x1 &ipic 0x12 0x8
-+ 0x8800 0x0 0x0 0x2 &ipic 0x13 0x8
-+
-+ /* IDSEL 0x12 AD18 miniPCI slot 2 */
-+ 0x9000 0x0 0x0 0x1 &ipic 0x13 0x8
-+ 0x9000 0x0 0x0 0x2 &ipic 0x11 0x8>;
-+
-+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-+ interrupt-parent = <&ipic>;
-+ // interrupts = <66 0x8>;
-+ };
-+
-+ qe@e0100000 {
-+ reg = <0xe0100000 0x480>;
-+ ranges = <0x0 0xe0100000 0x100000>;
-+ model = "QE";
-+ device_type = "qe";
-+ compatible = "fsl,qe";
-+ #size-cells = <1>;
-+ #address-cells = <1>;
-+ brg-frequency = <0>;
-+ bus-frequency = <0>;
-+ // bus-frequency = <198000000>;
-+ fsl,qe-num-riscs = <1>;
-+ fsl,qe-num-snums = <28>;
-+
-+ qeic: qeic@80 {
-+ interrupt-controller;
-+ compatible = "fsl,qe-ic";
-+ big-endian;
-+ built-in;
-+ reg = <0x80 0x80>;
-+ #interrupt-cells = <1>;
-+ #address-cells = <0>;
-+ device_type = "qeic";
-+ interrupts = <0x20 0x8 0x21 0x8>;
-+ interrupt-parent = <&ipic>;
-+ };
-+
-+ mdio@2120 {
-+ compatible = "ucc_geth_phy";
-+ device_type = "mdio";
-+ reg = <0x3120 0x18>;
-+ #size-cells = <0>;
-+ #address-cells = <1>;
-+
-+ phy3: ethernet-phy@03 {
-+ // interface = <0x3>;
-+ device_type = "ethernet-phy";
-+ reg = <0x3>;
-+ };
-+
-+ phy2: ethernet-phy@02 {
-+ // interface = <0x3>;
-+ device_type = "ethernet-phy";
-+ reg = <0x2>;
-+ };
-+
-+ phy1: ethernet-phy@01 {
-+ // interface = <0x3>;
-+ device_type = "ethernet-phy";
-+ reg = <0x1>;
-+ };
-+ };
-+
-+ enet0: ucc@2200 {
-+ tx-clock = <0x1a>;
-+ rx-clock = <0x1f>;
-+ local-mac-address = [00 00 00 00 00 00];
-+ interrupt-parent = <&qeic>;
-+ interrupts = <0x22>;
-+ reg = <0x2200 0x200>;
-+ device-id = <0x3>;
-+ model = "UCC";
-+ compatible = "ucc_geth";
-+ device_type = "network";
-+ phy-handle = <&phy2>;
-+ pio-handle = <&ucc3pio>;
-+ };
-+
-+ enet1: ucc@3200 {
-+ tx-clock = <0x22>;
-+ rx-clock = <0x20>;
-+ local-mac-address = [00 00 00 00 00 00];
-+ interrupt-parent = <&qeic>;
-+ interrupts = <0x23>;
-+ reg = <0x3200 0x200>;
-+ device-id = <0x4>;
-+ model = "UCC";
-+ compatible = "ucc_geth";
-+ device_type = "network";
-+ phy-handle = <&phy3>;
-+ pio-handle = <&ucc4pio>;
-+ };
-+
-+ enet2: ucc@3000 {
-+ tx-clock = <0x18>;
-+ rx-clock = <0x17>;
-+ local-mac-address = [00 00 00 00 00 00];
-+ interrupt-parent = <&qeic>;
-+ interrupts = <0x21>;
-+ reg = <0x3000 0x200>;
-+ device-id = <0x2>;
-+ model = "UCC";
-+ compatible = "ucc_geth";
-+ device_type = "network";
-+ phy-handle = <&phy1>;
-+ pio-handle = <&ucc2pio>;
-+ };
-+
-+ spi@500 {
-+ mode = "cpu";
-+ interrupt-parent = <&qeic>;
-+ interrupts = <0x1>;
-+ reg = <0x500 0x40>;
-+ compatible = "fsl,spi";
-+ device_type = "spi";
-+ };
-+
-+ spi@4c0 {
-+ mode = "cpu";
-+ interrupt-parent = <&qeic>;
-+ interrupts = <0x2>;
-+ reg = <0x4c0 0x40>;
-+ compatible = "fsl,spi";
-+ device_type = "spi";
-+ };
-+
-+ muram@10000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
-+ ranges = <0x0 0x10000 0x4000>;
-+ device_type = "muram";
-+
-+ data-only@0 {
-+ compatible = "fsl,qe-muram-data",
-+ "fsl,cpm-muram-data";
-+ reg = <0x0 0x4000>;
-+ };
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/powerpc/boot/rb333.c
-@@ -0,0 +1,86 @@
-+/*
-+ * The RouterBOARD platform -- for booting RB333 RouterBOARDs.
-+ *
-+ * Author: Alexandros C. Couloumbis <alex@ozo.com>
-+ * Author: Michael Guntsche <mike@it-loops.com>
-+ *
-+ * Copyright (c) 2010 Alexandros C. Couloumbis
-+ * Copyright (c) 2009 Michael Guntsche
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include "ops.h"
-+#include "types.h"
-+#include "io.h"
-+#include "stdio.h"
-+#include <libfdt.h>
-+
-+BSS_STACK(4*1024);
-+
-+u64 memsize64;
-+const void *fw_dtb;
-+
-+static void rb333_fixups(void)
-+{
-+ const u32 *reg, *timebase, *clock;
-+ int node, size;
-+ void *chosen;
-+ const char* bootargs;
-+
-+ dt_fixup_memory(0, memsize64);
-+
-+ /* Find the CPU timebase and clock frequencies. */
-+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
-+ timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
-+ clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
-+ dt_fixup_cpu_clocks(*clock, *timebase, 0);
-+
-+ /* Set the MAC addresses. */
-+ node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@2200");
-+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
-+ dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg);
-+
-+ node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@3200");
-+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
-+ dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg);
-+
-+ node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@3000");
-+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
-+ dt_fixup_mac_address_by_alias("ethernet2", (const u8 *)reg);
-+
-+ /* Fixup chosen
-+ * The bootloader reads the kernelparm segment and adds the content to
-+ * bootargs. This is needed to specify root and other boot flags.
-+ */
-+ chosen = finddevice("/chosen");
-+ node = fdt_path_offset(fw_dtb, "/chosen");
-+ bootargs = fdt_getprop(fw_dtb, node, "bootargs", &size);
-+ setprop_str(chosen, "bootargs", bootargs);
-+}
-+
-+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-+ unsigned long r6, unsigned long r7)
-+{
-+ const u32 *reg;
-+ int node, size;
-+
-+ fw_dtb = (const void *)r3;
-+
-+ /* Find the memory range. */
-+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
-+ reg = fdt_getprop(fw_dtb, node, "reg", &size);
-+ memsize64 = reg[1];
-+
-+ /* Now we have the memory size; initialize the heap. */
-+ simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
-+
-+ /* Prepare the device tree and find the console. */
-+ fdt_init(_dtb_start);
-+ serial_console_init();
-+
-+ /* Remaining fixups... */
-+ platform_ops.fixups = rb333_fixups;
-+}
---- /dev/null
-+++ b/arch/powerpc/platforms/83xx/rbppc.c
-@@ -0,0 +1,388 @@
-+/*
-+ * Copyright (C) 2010 Alexandros C. Couloumbis <alex@ozo.com>
-+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
-+ * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
-+ * Copyright (C) Mikrotik 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/root_dev.h>
-+#include <linux/initrd.h>
-+#include <linux/interrupt.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_device.h>
-+#include <linux/of_platform.h>
-+#include <linux/pci.h>
-+#include <asm/time.h>
-+#include <asm/ipic.h>
-+#include <asm/udbg.h>
-+#include <asm/qe.h>
-+#include <asm/qe_ic.h>
-+#include <sysdev/fsl_soc.h>
-+#include <sysdev/fsl_pci.h>
-+#include "mpc83xx.h"
-+
-+#define SYSCTL 0x100
-+#define SICRL 0x014
-+
-+#define GTCFR2 0x04
-+#define GTMDR4 0x22
-+#define GTRFR4 0x26
-+#define GTCNR4 0x2e
-+#define GTVER4 0x36
-+#define GTPSR4 0x3e
-+
-+#define GTCFR_BCM 0x40
-+#define GTCFR_STP4 0x20
-+#define GTCFR_RST4 0x10
-+#define GTCFR_STP3 0x02
-+#define GTCFR_RST3 0x01
-+
-+#define GTMDR_ORI 0x10
-+#define GTMDR_FRR 0x08
-+#define GTMDR_ICLK16 0x04
-+
-+extern int par_io_data_set(u8 port, u8 pin, u8 val);
-+extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
-+ int assignment, int has_irq);
-+
-+static unsigned timer_freq;
-+static void *gtm;
-+
-+static int beeper_irq;
-+static unsigned beeper_gpio_pin[2];
-+
-+int rb333model = 0;
-+
-+irqreturn_t rbppc_timer_irq(int irq, void *ptr)
-+{
-+ static int toggle = 0;
-+
-+ par_io_data_set(beeper_gpio_pin[0], beeper_gpio_pin[1], toggle);
-+ toggle = !toggle;
-+
-+ /* ack interrupt */
-+ out_be16(gtm + GTVER4, 3);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+void rbppc_beep(unsigned freq)
-+{
-+ unsigned gtmdr;
-+
-+ if (freq > 5000) freq = 5000;
-+
-+ if (!gtm)
-+ return;
-+ if (!freq) {
-+ out_8(gtm + GTCFR2, GTCFR_STP4 | GTCFR_STP3);
-+ return;
-+ }
-+
-+ out_8(gtm + GTCFR2, GTCFR_RST4 | GTCFR_STP3);
-+ out_be16(gtm + GTPSR4, 255);
-+ gtmdr = GTMDR_FRR | GTMDR_ICLK16;
-+ if (beeper_irq != NO_IRQ) gtmdr |= GTMDR_ORI;
-+ out_be16(gtm + GTMDR4, gtmdr);
-+ out_be16(gtm + GTVER4, 3);
-+
-+ out_be16(gtm + GTRFR4, timer_freq / 16 / 256 / freq / 2);
-+ out_be16(gtm + GTCNR4, 0);
-+}
-+EXPORT_SYMBOL(rbppc_beep);
-+
-+static void __init rbppc_setup_arch(void)
-+{
-+ struct device_node *np;
-+
-+ np = of_find_node_by_type(NULL, "cpu");
-+ if (np) {
-+ const unsigned *fp = of_get_property(np, "clock-frequency", NULL);
-+ loops_per_jiffy = fp ? *fp / HZ : 0;
-+
-+ of_node_put(np);
-+ }
-+
-+ np = of_find_node_by_name(NULL, "serial");
-+ if (np) {
-+ timer_freq =
-+ *(unsigned *) of_get_property(np, "clock-frequency", NULL);
-+ of_node_put(np);
-+ }
-+
-+#ifdef CONFIG_PCI
-+ np = of_find_node_by_type(NULL, "pci");
-+ if (np) {
-+ mpc83xx_add_bridge(np);
-+ }
-+#endif
-+
-+if (rb333model) {
-+
-+#ifdef CONFIG_QUICC_ENGINE
-+ qe_reset();
-+
-+ if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
-+ par_io_init(np);
-+ of_node_put(np);
-+
-+ for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
-+ par_io_of_config(np);
-+ }
-+#endif
-+
-+} /* RB333 */
-+
-+}
-+
-+void __init rbppc_init_IRQ(void)
-+{
-+ struct device_node *np;
-+
-+ np = of_find_node_by_type(NULL, "ipic");
-+ if (np) {
-+ ipic_init(np, 0);
-+ ipic_set_default_priority();
-+ of_node_put(np);
-+ }
-+
-+if (rb333model) {
-+
-+#ifdef CONFIG_QUICC_ENGINE
-+ np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-+ if (!np) {
-+ np = of_find_node_by_type(NULL, "qeic");
-+ if (!np)
-+ return;
-+ }
-+ qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
-+ of_node_put(np);
-+#endif /* CONFIG_QUICC_ENGINE */
-+
-+} /* RB333 */
-+
-+}
-+
-+static int __init rbppc_probe(void)
-+{
-+ char *model;
-+
-+ model = of_get_flat_dt_prop(of_get_flat_dt_root(), "model", NULL);
-+
-+ if (!model)
-+ return 0;
-+
-+ if (strcmp(model, "RB333") == 0) {
-+ rb333model = 1;
-+ return 1;
-+ }
-+
-+ if (strcmp(model, "RB600") == 0)
-+ return 1;
-+
-+ return 0;
-+}
-+
-+static void __init rbppc_beeper_init(struct device_node *beeper)
-+{
-+ struct resource res;
-+ struct device_node *gpio;
-+ const unsigned *pin;
-+ const unsigned *gpio_id;
-+
-+ if (of_address_to_resource(beeper, 0, &res)) {
-+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No region specified\n", beeper->full_name);
-+ return;
-+ }
-+
-+ pin = of_get_property(beeper, "gpio", NULL);
-+ if (pin) {
-+ gpio = of_find_node_by_phandle(pin[0]);
-+
-+ if (!gpio) {
-+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: GPIO handle %x not found\n", beeper->full_name, pin[0]);
-+ return;
-+ }
-+
-+ gpio_id = of_get_property(gpio, "device-id", NULL);
-+ if (!gpio_id) {
-+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No device-id specified in GPIO\n", beeper->full_name);
-+ return;
-+ }
-+
-+ beeper_gpio_pin[0] = *gpio_id;
-+ beeper_gpio_pin[1] = pin[1];
-+
-+ par_io_config_pin(*gpio_id, pin[1], 1, 0, 0, 0);
-+ } else {
-+ void *sysctl;
-+
-+ sysctl = ioremap_nocache(get_immrbase() + SYSCTL, 0x100);
-+ out_be32(sysctl + SICRL,
-+ in_be32(sysctl + SICRL) | (1 << (31 - 19)));
-+ iounmap(sysctl);
-+ }
-+
-+ gtm = ioremap_nocache(res.start, res.end - res.start + 1);
-+
-+ beeper_irq = irq_of_parse_and_map(beeper, 0);
-+ if (beeper_irq != NO_IRQ) {
-+ int e = request_irq(beeper_irq, rbppc_timer_irq, 0, "beeper", NULL);
-+ if (e) {
-+ printk(KERN_ERR "rbppc_beeper_init(%s): Request of beeper irq failed!\n", beeper->full_name);
-+ }
-+ }
-+}
-+
-+#define SBIT(x) (0x80000000 >> (x))
-+#define DBIT(x, y) ((y) << (32 - (((x % 16) + 1) * 2)))
-+
-+#define GPIO_DIR_RB333(x) ((x) + (0x1408 >> 2))
-+#define GPIO_DATA_RB333(x) ((x) + (0x1404 >> 2))
-+
-+#define SICRL_RB600(x) ((x) + (0x114 >> 2))
-+#define GPIO_DIR_RB600(x) ((x) + (0xc00 >> 2))
-+#define GPIO_DATA_RB600(x) ((x) + (0xc08 >> 2))
-+
-+static void rbppc_restart(char *cmd)
-+{
-+ __be32 __iomem *reg;
-+ unsigned rb_model;
-+ struct device_node *root;
-+ unsigned int size;
-+
-+ root = of_find_node_by_path("/");
-+ if (root) {
-+ const char *prop = (char *) of_get_property(root, "model", &size);
-+ rb_model = prop[sizeof("RB") - 1] - '0';
-+ of_node_put(root);
-+ switch (rb_model) {
-+ case 3:
-+ reg = ioremap(get_immrbase(), 0x2000);
-+ local_irq_disable();
-+ out_be32(GPIO_DIR_RB333(reg),
-+ (in_be32(GPIO_DIR_RB333(reg)) & ~DBIT(4, 3)) | DBIT(4, 1));
-+ out_be32(GPIO_DATA_RB333(reg), in_be32(GPIO_DATA_RB333(reg)) & ~SBIT(4));
-+ break;
-+ case 6:
-+ reg = ioremap(get_immrbase(), 0x1000);
-+ local_irq_disable();
-+ out_be32(SICRL_RB600(reg), in_be32(SICRL_RB600(reg)) & ~0x00800000);
-+ out_be32(GPIO_DIR_RB600(reg), in_be32(GPIO_DIR_RB600(reg)) | SBIT(2));
-+ out_be32(GPIO_DATA_RB600(reg), in_be32(GPIO_DATA_RB600(reg)) & ~SBIT(2));
-+ break;
-+ default:
-+ mpc83xx_restart(cmd);
-+ break;
-+ }
-+ }
-+ else mpc83xx_restart(cmd);
-+
-+ for (;;) ;
-+}
-+
-+static void rbppc_halt(void)
-+{
-+ while (1);
-+}
-+
-+static struct of_device_id rbppc_ids[] = {
-+ { .type = "soc", },
-+ { .compatible = "soc", },
-+ { .compatible = "simple-bus", },
-+ { .type = "qe", },
-+ { .compatible = "fsl,qe", },
-+ { .compatible = "gianfar", },
-+ { },
-+};
-+
-+static int __init rbppc_declare_of_platform_devices(void)
-+{
-+ struct device_node *np;
-+ unsigned idx;
-+
-+ of_platform_bus_probe(NULL, rbppc_ids, NULL);
-+
-+ np = of_find_node_by_type(NULL, "mdio");
-+ if (np) {
-+ unsigned len;
-+ unsigned *res;
-+ const unsigned *eres;
-+ struct device_node *ep;
-+
-+ ep = of_find_compatible_node(NULL, "network", "ucc_geth");
-+ if (ep) {
-+ eres = of_get_property(ep, "reg", &len);
-+ res = (unsigned *) of_get_property(np, "reg", &len);
-+ if (res && eres) {
-+ res[0] = eres[0] + 0x120;
-+ }
-+ }
-+ }
-+
-+ np = of_find_node_by_name(NULL, "nand");
-+ if (np) {
-+ of_platform_device_create(np, "nand", NULL);
-+ }
-+
-+ idx = 0;
-+ for_each_node_by_type(np, "rb,cf") {
-+ char dev_name[12];
-+ snprintf(dev_name, sizeof(dev_name), "cf.%u", idx);
-+ of_platform_device_create(np, dev_name, NULL);
-+ ++idx;
-+ }
-+
-+ np = of_find_node_by_name(NULL, "beeper");
-+ if (np) {
-+ rbppc_beeper_init(np);
-+ }
-+
-+ return 0;
-+}
-+machine_device_initcall(rb600, rbppc_declare_of_platform_devices);
-+
-+define_machine(rb600) {
-+ .name = "MikroTik RouterBOARD 333/600 series",
-+ .probe = rbppc_probe,
-+ .setup_arch = rbppc_setup_arch,
-+ .init_IRQ = rbppc_init_IRQ,
-+ .get_irq = ipic_get_irq,
-+ .restart = rbppc_restart,
-+ .halt = rbppc_halt,
-+ .time_init = mpc83xx_time_init,
-+ .calibrate_decr = generic_calibrate_decr,
-+};
-+
-+static void fixup_pcibridge(struct pci_dev *dev)
-+{
-+ if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
-+ /* let the kernel itself set right memory windows */
-+ pci_write_config_word(dev, PCI_MEMORY_BASE, 0);
-+ pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
-+ pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0);
-+ pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
-+ pci_write_config_byte(dev, PCI_IO_BASE, 0);
-+ pci_write_config_byte(dev, PCI_IO_LIMIT, 4 << 4);
-+
-+ pci_write_config_byte(
-+ dev, PCI_COMMAND,
-+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
-+ }
-+}
-+
-+
-+static void fixup_rb604(struct pci_dev *dev)
-+{
-+ pci_write_config_byte(dev, 0xC0, 0x01);
-+}
-+
-+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_pcibridge)
-+DECLARE_PCI_FIXUP_HEADER(0x3388, 0x0021, fixup_rb604)
+++ /dev/null
---- a/arch/powerpc/kernel/Makefile
-+++ b/arch/powerpc/kernel/Makefile
-@@ -118,9 +118,11 @@ obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.
-
- obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
-
-+ifneq ($(CONFIG_RB_IOMAP),y)
- ifneq ($(CONFIG_PPC_INDIRECT_IO),y)
- obj-y += iomap.o
- endif
-+endif
-
- obj-$(CONFIG_PPC64) += $(obj64-y)
- obj-$(CONFIG_PPC32) += $(obj32-y)
---- a/arch/powerpc/platforms/83xx/Makefile
-+++ b/arch/powerpc/platforms/83xx/Makefile
-@@ -7,6 +7,7 @@ obj-$(CONFIG_MCU_MPC8349EMITX) += mcu_mp
- obj-$(CONFIG_MPC830x_RDB) += mpc830x_rdb.o
- obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o
- obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o
-+obj-$(CONFIG_RB_PPC) += rbppc.o
- obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o
- obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o
- obj-$(CONFIG_MPC836x_MDS) += mpc836x_mds.o
---- a/arch/powerpc/platforms/Kconfig
-+++ b/arch/powerpc/platforms/Kconfig
-@@ -192,6 +192,10 @@ config PPC_INDIRECT_MMIO
- config PPC_IO_WORKAROUNDS
- bool
-
-+config RB_IOMAP
-+ bool
-+ default y if RB_PPC
-+
- source "drivers/cpufreq/Kconfig"
-
- menu "CPU Frequency drivers"
---- a/arch/powerpc/sysdev/Makefile
-+++ b/arch/powerpc/sysdev/Makefile
-@@ -69,3 +69,6 @@ subdir-ccflags-$(CONFIG_PPC_WERROR) := -
- obj-$(CONFIG_PPC_XICS) += xics/
-
- obj-$(CONFIG_GE_FPGA) += ge/
-+
-+obj-$(CONFIG_RB_IOMAP) += rb_iomap.o
-+
---- /dev/null
-+++ b/arch/powerpc/sysdev/rb_iomap.c
-@@ -0,0 +1,204 @@
-+#include <linux/init.h>
-+#include <linux/pci.h>
-+#include <linux/mm.h>
-+#include <asm/io.h>
-+
-+#define LOCALBUS_START 0x40000000
-+#define LOCALBUS_MASK 0x007fffff
-+#define LOCALBUS_REGMASK 0x001fffff
-+
-+static void __iomem *localbus_base;
-+
-+static inline int is_localbus(void __iomem *addr)
-+{
-+ return ((unsigned) addr & ~LOCALBUS_MASK) == LOCALBUS_START;
-+}
-+
-+static inline unsigned localbus_regoff(unsigned reg) {
-+ return (reg << 16) | (((reg ^ 8) & 8) << 17);
-+}
-+
-+static inline void __iomem *localbus_addr(void __iomem *addr)
-+{
-+ return localbus_base
-+ + ((unsigned) addr & LOCALBUS_MASK & ~LOCALBUS_REGMASK)
-+ + localbus_regoff((unsigned) addr & LOCALBUS_REGMASK);
-+}
-+
-+unsigned int ioread8(void __iomem *addr)
-+{
-+ if (is_localbus(addr))
-+ return in_be16(localbus_addr(addr)) >> 8;
-+ return readb(addr);
-+}
-+EXPORT_SYMBOL(ioread8);
-+
-+unsigned int ioread16(void __iomem *addr)
-+{
-+ if (is_localbus(addr))
-+ return le16_to_cpu(in_be16(localbus_addr(addr)));
-+ return readw(addr);
-+}
-+EXPORT_SYMBOL(ioread16);
-+
-+unsigned int ioread16be(void __iomem *addr)
-+{
-+ return in_be16(addr);
-+}
-+EXPORT_SYMBOL(ioread16be);
-+
-+unsigned int ioread32(void __iomem *addr)
-+{
-+ return readl(addr);
-+}
-+EXPORT_SYMBOL(ioread32);
-+
-+unsigned int ioread32be(void __iomem *addr)
-+{
-+ return in_be32(addr);
-+}
-+EXPORT_SYMBOL(ioread32be);
-+
-+void iowrite8(u8 val, void __iomem *addr)
-+{
-+ if (is_localbus(addr))
-+ out_be16(localbus_addr(addr), ((u16) val) << 8);
-+ else
-+ writeb(val, addr);
-+}
-+EXPORT_SYMBOL(iowrite8);
-+
-+void iowrite16(u16 val, void __iomem *addr)
-+{
-+ if (is_localbus(addr))
-+ out_be16(localbus_addr(addr), cpu_to_le16(val));
-+ else
-+ writew(val, addr);
-+}
-+EXPORT_SYMBOL(iowrite16);
-+
-+void iowrite16be(u16 val, void __iomem *addr)
-+{
-+ out_be16(addr, val);
-+}
-+EXPORT_SYMBOL(iowrite16be);
-+
-+void iowrite32(u32 val, void __iomem *addr)
-+{
-+ writel(val, addr);
-+}
-+EXPORT_SYMBOL(iowrite32);
-+
-+void iowrite32be(u32 val, void __iomem *addr)
-+{
-+ out_be32(addr, val);
-+}
-+EXPORT_SYMBOL(iowrite32be);
-+
-+void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
-+{
-+ if (is_localbus(addr)) {
-+ unsigned i;
-+ void *laddr = localbus_addr(addr);
-+ u8 *buf = dst;
-+
-+ for (i = 0; i < count; ++i) {
-+ *buf++ = in_be16(laddr) >> 8;
-+ }
-+ } else {
-+ _insb((u8 __iomem *) addr, dst, count);
-+ }
-+}
-+EXPORT_SYMBOL(ioread8_rep);
-+
-+void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
-+{
-+ if (is_localbus(addr)) {
-+ unsigned i;
-+ void *laddr = localbus_addr(addr);
-+ u16 *buf = dst;
-+
-+ for (i = 0; i < count; ++i) {
-+ *buf++ = in_be16(laddr);
-+ }
-+ } else {
-+ _insw_ns((u16 __iomem *) addr, dst, count);
-+ }
-+}
-+EXPORT_SYMBOL(ioread16_rep);
-+
-+void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
-+{
-+ _insl_ns((u32 __iomem *) addr, dst, count);
-+}
-+EXPORT_SYMBOL(ioread32_rep);
-+
-+void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
-+{
-+ if (is_localbus(addr)) {
-+ unsigned i;
-+ void *laddr = localbus_addr(addr);
-+ const u8 *buf = src;
-+
-+ for (i = 0; i < count; ++i) {
-+ out_be16(laddr, ((u16) *buf++) << 8);
-+ }
-+ } else {
-+ _outsb((u8 __iomem *) addr, src, count);
-+ }
-+}
-+EXPORT_SYMBOL(iowrite8_rep);
-+
-+void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
-+{
-+ if (is_localbus(addr)) {
-+ unsigned i;
-+ void *laddr = localbus_addr(addr);
-+ const u16 *buf = src;
-+
-+ for (i = 0; i < count; ++i) {
-+ out_be16(laddr, *buf++);
-+ }
-+ } else {
-+ _outsw_ns((u16 __iomem *) addr, src, count);
-+ }
-+}
-+EXPORT_SYMBOL(iowrite16_rep);
-+
-+void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
-+{
-+ _outsl_ns((u32 __iomem *) addr, src, count);
-+}
-+EXPORT_SYMBOL(iowrite32_rep);
-+
-+void __iomem *ioport_map(unsigned long port, unsigned int len)
-+{
-+ return (void __iomem *) (port + _IO_BASE);
-+}
-+EXPORT_SYMBOL(ioport_unmap);
-+
-+void ioport_unmap(void __iomem *addr)
-+{
-+ /* Nothing to do */
-+}
-+EXPORT_SYMBOL(ioport_map);
-+
-+void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
-+{
-+ /* Nothing to do */
-+}
-+EXPORT_SYMBOL(pci_iounmap);
-+
-+void __iomem *localbus_map(unsigned long addr, unsigned int len)
-+{
-+ if (!localbus_base)
-+ localbus_base = ioremap(addr & ~LOCALBUS_MASK,
-+ LOCALBUS_MASK + 1);
-+ return (void *) (LOCALBUS_START + (addr & LOCALBUS_MASK));
-+}
-+EXPORT_SYMBOL(localbus_map);
-+
-+void localbus_unmap(void __iomem *addr)
-+{
-+}
-+EXPORT_SYMBOL(localbus_unmap);
---- a/arch/powerpc/platforms/83xx/Kconfig
-+++ b/arch/powerpc/platforms/83xx/Kconfig
-@@ -44,6 +44,7 @@ config RB_PPC
- select QUICC_ENGINE
- select PPC_MPC832x
- select PPC_MPC834x
-+ select RB_IOMAP
- help
- This option enables support for MikroTik RouterBOARD 333/600 series boards.
-
+++ /dev/null
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -916,5 +916,12 @@ config PATA_LEGACY
-
- If unsure, say N.
-
-+config PATA_RB_PPC
-+ tristate "MikroTik RB600 PATA support"
-+ depends on RB_PPC
-+ help
-+ This option enables support for PATA devices on MikroTik RouterBOARD
-+ 600 series boards.
-+
- endif # ATA_SFF
- endif # ATA
---- a/drivers/ata/Makefile
-+++ b/drivers/ata/Makefile
-@@ -91,6 +91,7 @@ obj-$(CONFIG_PATA_PALMLD) += pata_palmld
- obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
- obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
- obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
-+obj-$(CONFIG_PATA_RB_PPC) += pata_rbppc_cf.o
- obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
- obj-$(CONFIG_PATA_SAMSUNG_CF) += pata_samsung_cf.o
-
---- /dev/null
-+++ b/drivers/ata/pata_rbppc_cf.c
-@@ -0,0 +1,699 @@
-+/*
-+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
-+ * Copyright (C) Mikrotik 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <scsi/scsi_host.h>
-+#include <linux/libata.h>
-+#include <linux/of_platform.h>
-+#include <linux/ata_platform.h>
-+#include <linux/slab.h>
-+
-+#define DEBUG_UPM 0
-+
-+#define DRV_NAME "pata_rbppc_cf"
-+#define DRV_VERSION "0.0.2"
-+
-+#define DEV2SEL_OFFSET 0x00100000
-+
-+#define IMMR_LBCFG_OFFSET 0x00005000
-+#define IMMR_LBCFG_SIZE 0x00001000
-+
-+#define LOCAL_BUS_MCMR 0x00000078
-+#define MxMR_OP_MASK 0x30000000
-+#define MxMR_OP_NORMAL 0x00000000
-+#define MxMR_OP_WRITE 0x10000000
-+#define MxMR_OP_READ 0x20000000
-+#define MxMR_OP_RUN 0x30000000
-+#define MxMR_LUPWAIT_LOW 0x08000000
-+#define MxMR_LUPWAIT_HIGH 0x00000000
-+#define MxMR_LUPWAIT_ENABLE 0x00040000
-+#define MxMR_RLF_MASK 0x0003c000
-+#define MxMR_RLF_SHIFT 14
-+#define MxMR_WLF_MASK 0x00003c00
-+#define MxMR_WLF_SHIFT 10
-+#define MxMR_MAD_MASK 0x0000003f
-+#define LOCAL_BUS_MDR 0x00000088
-+#define LOCAL_BUS_LCRR 0x000000D4
-+#define LCRR_CLKDIV_MASK 0x0000000f
-+
-+#define LOOP_SIZE 4
-+
-+#define UPM_READ_SINGLE_OFFSET 0x00
-+#define UPM_WRITE_SINGLE_OFFSET 0x18
-+#define UPM_DATA_SIZE 0x40
-+
-+#define LBT_CPUIN_MIN 0
-+#define LBT_CPUOUT_MIN 1
-+#define LBT_CPUOUT_MAX 2
-+#define LBT_EXTDEL_MIN 3
-+#define LBT_EXTDEL_MAX 4
-+#define LBT_SIZE 5
-+
-+/* UPM machine configuration bits */
-+#define N_BASE 0x00f00000
-+#define N_CS 0xf0000000
-+#define N_CS_H1 0xc0000000
-+#define N_CS_H2 0x30000000
-+#define N_WE 0x0f000000
-+#define N_WE_H1 0x0c000000
-+#define N_WE_H2 0x03000000
-+#define N_OE 0x00030000
-+#define N_OE_H1 0x00020000
-+#define N_OE_H2 0x00010000
-+#define WAEN 0x00001000
-+#define REDO_2 0x00000100
-+#define REDO_3 0x00000200
-+#define REDO_4 0x00000300
-+#define LOOP 0x00000080
-+#define NA 0x00000008
-+#define UTA 0x00000004
-+#define LAST 0x00000001
-+
-+#define REDO_VAL(mult) (REDO_2 * ((mult) - 1))
-+#define REDO_MAX_MULT 4
-+
-+#define READ_BASE (N_BASE | N_WE)
-+#define WRITE_BASE (N_BASE | N_OE)
-+#define EMPTY (N_BASE | N_CS | N_OE | N_WE | LAST)
-+
-+#define EOF_UPM_SETTINGS 0
-+#define ANOTHER_TIMING 1
-+
-+#define OA_CPUIN_MIN 0x01
-+#define OA_CPUOUT_MAX 0x02
-+#define OD_CPUOUT_MIN 0x04
-+#define OA_CPUOUT_DELTA 0x06
-+#define OA_EXTDEL_MAX 0x08
-+#define OD_EXTDEL_MIN 0x10
-+#define OA_EXTDEL_DELTA 0x18
-+#define O_MIN_CYCLE_TIME 0x20
-+#define O_MINUS_PREV 0x40
-+#define O_HALF_CYCLE 0x80
-+
-+extern void __iomem *localbus_map(unsigned long addr, unsigned int len);
-+extern void localbus_unmap(void __iomem *addr);
-+
-+struct rbppc_cf_info {
-+ unsigned lbcfg_addr;
-+ unsigned clk_time_ps;
-+ int cur_mode;
-+ u32 lb_timings[LBT_SIZE];
-+};
-+static struct rbppc_cf_info *rbinfo = NULL;
-+
-+struct upm_setting {
-+ unsigned value;
-+ unsigned ns[7];
-+ unsigned clk_minus;
-+ unsigned group_size;
-+ unsigned options;
-+};
-+
-+static const struct upm_setting cfUpmReadSingle[] = {
-+ { READ_BASE | N_OE,
-+ /* t1 - ADDR setup time */
-+ { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
-+ OA_EXTDEL_MAX) },
-+ { READ_BASE | N_OE_H1,
-+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
-+ { READ_BASE,
-+ /* t2 - OE0 time */
-+ { 290, 290, 290, 80, 70, 65, 55 }, 0, 2, (OA_CPUOUT_MAX |
-+ OA_CPUIN_MIN) },
-+ { READ_BASE | WAEN,
-+ { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
-+ { READ_BASE | UTA,
-+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
-+ { READ_BASE | N_OE,
-+ /* t9 - ADDR hold time */
-+ { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
-+ OD_EXTDEL_MIN) },
-+ { READ_BASE | N_OE | N_CS_H2,
-+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
-+ { READ_BASE | N_OE | N_CS,
-+ /* t6Z -IORD data tristate */
-+ { 30, 30, 30, 30, 30, 20, 20 }, 1, 1, O_MINUS_PREV },
-+ { ANOTHER_TIMING,
-+ /* t2i -IORD recovery time */
-+ { 0, 0, 0, 70, 25, 25, 20 }, 2, 0, 0 },
-+ { ANOTHER_TIMING,
-+ /* CS 0 -> 1 MAX */
-+ { 0, 0, 0, 0, 0, 0, 0 }, 1, 0, (OA_CPUOUT_DELTA |
-+ OA_EXTDEL_MAX) },
-+ { READ_BASE | N_OE | N_CS | LAST,
-+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
-+ { EOF_UPM_SETTINGS,
-+ /* min total cycle time - includes turnaround and ALE cycle */
-+ { 600, 383, 240, 180, 120, 100, 80 }, 2, 0, O_MIN_CYCLE_TIME },
-+};
-+
-+static const struct upm_setting cfUpmWriteSingle[] = {
-+ { WRITE_BASE | N_WE,
-+ /* t1 - ADDR setup time */
-+ { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
-+ OA_EXTDEL_MAX) },
-+ { WRITE_BASE | N_WE_H1,
-+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
-+ { WRITE_BASE,
-+ /* t2 - WE0 time */
-+ { 290, 290, 290, 80, 70, 65, 55 }, 0, 1, OA_CPUOUT_DELTA },
-+ { WRITE_BASE | WAEN,
-+ { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
-+ { WRITE_BASE | N_WE,
-+ /* t9 - ADDR hold time */
-+ { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
-+ OD_EXTDEL_MIN) },
-+ { WRITE_BASE | N_WE | N_CS_H2,
-+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
-+ { WRITE_BASE | N_WE | N_CS,
-+ /* t4 - DATA hold time */
-+ { 30, 20, 15, 10, 10, 10, 10 }, 0, 1, O_MINUS_PREV },
-+ { ANOTHER_TIMING,
-+ /* t2i -IOWR recovery time */
-+ { 0, 0, 0, 70, 25, 25, 20 }, 1, 0, 0 },
-+ { ANOTHER_TIMING,
-+ /* CS 0 -> 1 MAX */
-+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, (OA_CPUOUT_DELTA |
-+ OA_EXTDEL_MAX) },
-+ { WRITE_BASE | N_WE | N_CS | UTA | LAST,
-+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
-+ /* min total cycle time - includes ALE cycle */
-+ { EOF_UPM_SETTINGS,
-+ { 600, 383, 240, 180, 120, 100, 80 }, 1, 0, O_MIN_CYCLE_TIME },
-+};
-+
-+static u8 rbppc_cf_check_status(struct ata_port *ap) {
-+ u8 val = ioread8(ap->ioaddr.status_addr);
-+ if (val == 0xF9)
-+ val = 0x7F;
-+ return val;
-+}
-+
-+static u8 rbppc_cf_check_altstatus(struct ata_port *ap) {
-+ u8 val = ioread8(ap->ioaddr.altstatus_addr);
-+ if (val == 0xF9)
-+ val = 0x7F;
-+ return val;
-+}
-+
-+static void rbppc_cf_dummy_noret(struct ata_port *ap) { }
-+static int rbppc_cf_dummy_ret0(struct ata_port *ap) { return 0; }
-+
-+static int ps2clk(int ps, unsigned clk_time_ps) {
-+ int psMaxOver;
-+ if (ps <= 0) return 0;
-+
-+ /* round down if <= 2% over clk border, but no more than 1/4 clk cycle */
-+ psMaxOver = ps * 2 / 100;
-+ if (4 * psMaxOver > clk_time_ps) {
-+ psMaxOver = clk_time_ps / 4;
-+ }
-+ return (ps + clk_time_ps - 1 - psMaxOver) / clk_time_ps;
-+}
-+
-+static int upm_gen_ps_table(const struct upm_setting *upm,
-+ int mode, struct rbppc_cf_info *info,
-+ int *psFinal) {
-+ int uidx;
-+ int lastUpmValIdx = 0;
-+ int group_start_idx = -1;
-+ int group_left_num = -1;
-+ int clk_time_ps = info->clk_time_ps;
-+
-+ for (uidx = 0; upm[uidx].value != EOF_UPM_SETTINGS; ++uidx) {
-+ const struct upm_setting *us = upm + uidx;
-+ unsigned opt = us->options;
-+ int ps = us->ns[mode] * 1000 - us->clk_minus * clk_time_ps;
-+
-+ if (opt & OA_CPUIN_MIN) ps += info->lb_timings[LBT_CPUIN_MIN];
-+ if (opt & OD_CPUOUT_MIN) ps -= info->lb_timings[LBT_CPUOUT_MIN];
-+ if (opt & OA_CPUOUT_MAX) ps += info->lb_timings[LBT_CPUOUT_MAX];
-+ if (opt & OD_EXTDEL_MIN) ps -= info->lb_timings[LBT_EXTDEL_MIN];
-+ if (opt & OA_EXTDEL_MAX) ps += info->lb_timings[LBT_EXTDEL_MAX];
-+
-+ if (us->value == ANOTHER_TIMING) {
-+ /* use longest timing from alternatives */
-+ if (psFinal[lastUpmValIdx] < ps) {
-+ psFinal[lastUpmValIdx] = ps;
-+ }
-+ ps = 0;
-+ }
-+ else {
-+ if (us->group_size) {
-+ group_start_idx = uidx;
-+ group_left_num = us->group_size;
-+ }
-+ else if (group_left_num > 0) {
-+ /* group time is divided on all group members */
-+ int clk = ps2clk(ps, clk_time_ps);
-+ psFinal[group_start_idx] -= clk * clk_time_ps;
-+ --group_left_num;
-+ }
-+ if ((opt & O_MINUS_PREV) && lastUpmValIdx > 0) {
-+ int clk = ps2clk(psFinal[lastUpmValIdx],
-+ clk_time_ps);
-+ ps -= clk * clk_time_ps;
-+ }
-+ lastUpmValIdx = uidx;
-+ }
-+ psFinal[uidx] = ps;
-+ }
-+ return uidx;
-+}
-+
-+static int free_half(int ps, int clk, int clk_time_ps) {
-+ if (clk < 2) return 0;
-+ return (clk * clk_time_ps - ps) * 2 >= clk_time_ps;
-+}
-+
-+static void upm_gen_clk_table(const struct upm_setting *upm,
-+ int mode, int clk_time_ps,
-+ int max_uidx, const int *psFinal, int *clkFinal) {
-+ int clk_cycle_time;
-+ int clk_total;
-+ int uidx;
-+
-+ /* convert picoseconds to clocks */
-+ clk_total = 0;
-+ for (uidx = 0; uidx < max_uidx; ++uidx) {
-+ int clk = ps2clk(psFinal[uidx], clk_time_ps);
-+ clkFinal[uidx] = clk;
-+ clk_total += clk;
-+ }
-+
-+ /* check possibility of half cycle usage */
-+ for (uidx = 1; uidx < max_uidx - 1; ++uidx) {
-+ if ((upm[uidx].options & O_HALF_CYCLE) &&
-+ free_half(psFinal[uidx - 1], clkFinal[uidx - 1],
-+ clk_time_ps) &&
-+ free_half(psFinal[uidx + 1], clkFinal[uidx + 1],
-+ clk_time_ps)) {
-+ ++clkFinal[uidx];
-+ --clkFinal[uidx - 1];
-+ --clkFinal[uidx + 1];
-+ }
-+ }
-+
-+ if ((upm[max_uidx].options & O_MIN_CYCLE_TIME) == 0) return;
-+
-+ /* check cycle time, adjust timings if needed */
-+ clk_cycle_time = (ps2clk(upm[max_uidx].ns[mode] * 1000, clk_time_ps) -
-+ upm[max_uidx].clk_minus);
-+ uidx = 0;
-+ while (clk_total < clk_cycle_time) {
-+ /* extend all timings in round-robin to match cycle time */
-+ if (clkFinal[uidx]) {
-+#if DEBUG_UPM
-+ printk(KERN_INFO "extending %u by 1 clk\n", uidx);
-+#endif
-+ ++clkFinal[uidx];
-+ ++clk_total;
-+ }
-+ ++uidx;
-+ if (uidx == max_uidx) uidx = 0;
-+ }
-+}
-+
-+static void add_data_val(unsigned val, int *clkLeft, int maxClk,
-+ unsigned *data, int *dataIdx) {
-+ if (*clkLeft == 0) return;
-+
-+ if (maxClk == 0 && *clkLeft >= LOOP_SIZE * 2) {
-+ int times;
-+ int times1;
-+ int times2;
-+
-+ times = *clkLeft / LOOP_SIZE;
-+ if (times > REDO_MAX_MULT * 2) times = REDO_MAX_MULT * 2;
-+ times1 = times / 2;
-+ times2 = times - times1;
-+
-+ val |= LOOP;
-+ data[*dataIdx] = val | REDO_VAL(times1);
-+ ++(*dataIdx);
-+ data[*dataIdx] = val | REDO_VAL(times2);
-+ ++(*dataIdx);
-+
-+ *clkLeft -= times * LOOP_SIZE;
-+ return;
-+ }
-+
-+ if (maxClk < 1 || maxClk > REDO_MAX_MULT) maxClk = REDO_MAX_MULT;
-+ if (*clkLeft < maxClk) maxClk = *clkLeft;
-+
-+ *clkLeft -= maxClk;
-+ val |= REDO_VAL(maxClk);
-+
-+ data[*dataIdx] = val;
-+ ++(*dataIdx);
-+}
-+
-+static int upm_gen_final_data(const struct upm_setting *upm,
-+ int max_uidx, int *clkFinal, unsigned *data) {
-+ int dataIdx;
-+ int uidx;
-+
-+ dataIdx = 0;
-+ for (uidx = 0; uidx < max_uidx; ++uidx) {
-+ int clk = clkFinal[uidx];
-+ while (clk > 0) {
-+ add_data_val(upm[uidx].value, &clk, 0,
-+ data, &dataIdx);
-+ }
-+ }
-+ return dataIdx;
-+}
-+
-+static int conv_upm_table(const struct upm_setting *upm,
-+ int mode, struct rbppc_cf_info *info,
-+ unsigned *data) {
-+#if DEBUG_UPM
-+ int uidx;
-+#endif
-+ int psFinal[32];
-+ int clkFinal[32];
-+ int max_uidx;
-+ int data_len;
-+
-+ max_uidx = upm_gen_ps_table(upm, mode, info, psFinal);
-+
-+ upm_gen_clk_table(upm, mode, info->clk_time_ps, max_uidx,
-+ psFinal, clkFinal);
-+
-+#if DEBUG_UPM
-+ /* dump out debug info */
-+ for (uidx = 0; uidx < max_uidx; ++uidx) {
-+ if (clkFinal[uidx]) {
-+ printk(KERN_INFO "idx %d val %08x clk %d ps %d\n",
-+ uidx, upm[uidx].value,
-+ clkFinal[uidx], psFinal[uidx]);
-+ }
-+ }
-+#endif
-+
-+ data_len = upm_gen_final_data(upm, max_uidx, clkFinal, data);
-+
-+#if DEBUG_UPM
-+ for (uidx = 0; uidx < data_len; ++uidx) {
-+ printk(KERN_INFO "cf UPM x result: idx %d val %08x\n",
-+ uidx, data[uidx]);
-+ }
-+#endif
-+ return 0;
-+}
-+
-+static int gen_upm_data(int mode, struct rbppc_cf_info *info, unsigned *data) {
-+ int i;
-+
-+ for (i = 0; i < UPM_DATA_SIZE; ++i) {
-+ data[i] = EMPTY;
-+ }
-+
-+ if (conv_upm_table(cfUpmReadSingle, mode, info, data + UPM_READ_SINGLE_OFFSET)) {
-+ return -1;
-+ }
-+ if (conv_upm_table(cfUpmWriteSingle, mode, info, data + UPM_WRITE_SINGLE_OFFSET)) {
-+ return -1;
-+ }
-+ return 0;
-+}
-+
-+static void rbppc_cf_program_upm(void *upmMemAddr, volatile void *lbcfg_mxmr, volatile void *lbcfg_mdr, const unsigned *upmData, unsigned offset, unsigned len) {
-+ unsigned i;
-+ unsigned mxmr;
-+
-+ mxmr = in_be32(lbcfg_mxmr);
-+ mxmr &= ~(MxMR_OP_MASK | MxMR_MAD_MASK);
-+ mxmr |= (MxMR_OP_WRITE | offset);
-+ out_be32(lbcfg_mxmr, mxmr);
-+ in_be32(lbcfg_mxmr); /* flush MxMR write */
-+
-+ for (i = 0; i < len; ++i) {
-+ int to;
-+ unsigned data = upmData[i + offset];
-+ out_be32(lbcfg_mdr, data);
-+ in_be32(lbcfg_mdr); /* flush MDR write */
-+
-+ iowrite8(1, upmMemAddr); /* dummy write to any CF addr */
-+
-+ /* wait for dummy write to complete */
-+ for (to = 10000; to >= 0; --to) {
-+ mxmr = in_be32(lbcfg_mxmr);
-+ if (((mxmr ^ (i + 1)) & MxMR_MAD_MASK) == 0) {
-+ break;
-+ }
-+ if (to == 0) {
-+ printk(KERN_ERR "rbppc_cf_program_upm: UPMx program error at 0x%x: Timeout\n", i);
-+ }
-+ }
-+ }
-+ mxmr &= ~(MxMR_OP_MASK | MxMR_RLF_MASK | MxMR_WLF_MASK);
-+ mxmr |= (MxMR_OP_NORMAL | (LOOP_SIZE << MxMR_RLF_SHIFT) | (LOOP_SIZE << MxMR_WLF_SHIFT));
-+ out_be32(lbcfg_mxmr, mxmr);
-+}
-+
-+static int rbppc_cf_update_piomode(struct ata_port *ap, int mode) {
-+ struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
-+ void *lbcfgBase;
-+ unsigned upmData[UPM_DATA_SIZE];
-+
-+ if (gen_upm_data(mode, info, upmData)) {
-+ return -1;
-+ }
-+
-+ lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
-+
-+ rbppc_cf_program_upm(ap->ioaddr.cmd_addr, ((char *)lbcfgBase) + LOCAL_BUS_MCMR, ((char *)lbcfgBase) + LOCAL_BUS_MDR, upmData, 0, UPM_DATA_SIZE);
-+ iounmap(lbcfgBase);
-+ return 0;
-+}
-+
-+static void rbppc_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
-+{
-+ struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
-+ int mode = adev->pio_mode - XFER_PIO_0;
-+
-+ DPRINTK("rbppc_cf_set_piomode: PIO %d\n", mode);
-+ if (mode < 0) mode = 0;
-+ if (mode > 6) mode = 6;
-+
-+ if (info->cur_mode < 0 || info->cur_mode > mode) {
-+ if (rbppc_cf_update_piomode(ap, mode) == 0) {
-+ printk(KERN_INFO "rbppc_cf_set_piomode: PIO mode changed to %d\n", mode);
-+ info->cur_mode = mode;
-+ }
-+ }
-+}
-+
-+static struct scsi_host_template rbppc_cf_sht = {
-+ ATA_BASE_SHT(DRV_NAME),
-+};
-+
-+static struct ata_port_operations rbppc_cf_port_ops = {
-+ .inherits = &ata_bmdma_port_ops,
-+
-+ .sff_check_status = rbppc_cf_check_status,
-+ .sff_check_altstatus = rbppc_cf_check_altstatus,
-+
-+ .set_piomode = rbppc_cf_set_piomode,
-+
-+ .port_start = rbppc_cf_dummy_ret0,
-+
-+ .sff_irq_clear = rbppc_cf_dummy_noret,
-+};
-+
-+static int rbppc_cf_init_info(struct platform_device *pdev, struct rbppc_cf_info *info) {
-+ struct device_node *np;
-+ struct resource res;
-+ const u32 *u32ptr;
-+ void *lbcfgBase;
-+ void *lbcfg_lcrr;
-+ unsigned lbc_clk_khz;
-+ unsigned lbc_extra_divider = 1;
-+ unsigned ccb_freq_hz;
-+ unsigned lb_div;
-+
-+ u32ptr = of_get_property(pdev->dev.of_node, "lbc_extra_divider", NULL);
-+ if (u32ptr && *u32ptr) {
-+ lbc_extra_divider = *u32ptr;
-+#if DEBUG_UPM
-+ printk(KERN_INFO "rbppc_cf_init_info: LBC extra divider %u\n",
-+ lbc_extra_divider);
-+#endif
-+ }
-+
-+ np = of_find_node_by_type(NULL, "serial");
-+ if (!np) {
-+ printk(KERN_ERR "rbppc_cf_init_info: No serial node found\n");
-+ return -1;
-+ }
-+ u32ptr = of_get_property(np, "clock-frequency", NULL);
-+ if (u32ptr == 0 || *u32ptr == 0) {
-+ printk(KERN_ERR "rbppc_cf_init_info: Serial does not have clock-frequency\n");
-+ of_node_put(np);
-+ return -1;
-+ }
-+ ccb_freq_hz = *u32ptr;
-+ of_node_put(np);
-+
-+ np = of_find_node_by_type(NULL, "soc");
-+ if (!np) {
-+ printk(KERN_ERR "rbppc_cf_init_info: No soc node found\n");
-+ return -1;
-+ }
-+ if (of_address_to_resource(np, 0, &res)) {
-+ printk(KERN_ERR "rbppc_cf_init_info: soc does not have resource\n");
-+ of_node_put(np);
-+ return -1;
-+ }
-+ info->lbcfg_addr = res.start + IMMR_LBCFG_OFFSET;
-+ of_node_put(np);
-+
-+ lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
-+ lbcfg_lcrr = ((char*)lbcfgBase) + LOCAL_BUS_LCRR;
-+ lb_div = (in_be32(lbcfg_lcrr) & LCRR_CLKDIV_MASK) * lbc_extra_divider;
-+ iounmap(lbcfgBase);
-+
-+ lbc_clk_khz = ccb_freq_hz / (1000 * lb_div);
-+ info->clk_time_ps = 1000000000 / lbc_clk_khz;
-+ printk(KERN_INFO "rbppc_cf_init_info: Using Local-Bus clock %u kHz %u ps\n",
-+ lbc_clk_khz, info->clk_time_ps);
-+
-+ u32ptr = of_get_property(pdev->dev.of_node, "lb-timings", NULL);
-+ if (u32ptr) {
-+ memcpy(info->lb_timings, u32ptr, LBT_SIZE * sizeof(*u32ptr));
-+#if DEBUG_UPM
-+ printk(KERN_INFO "rbppc_cf_init_info: Got LB timings <%u %u %u %u %u>\n",
-+ u32ptr[0], u32ptr[1], u32ptr[2], u32ptr[3], u32ptr[4]);
-+#endif
-+ }
-+ info->cur_mode = -1;
-+ return 0;
-+}
-+
-+static int rbppc_cf_probe(struct platform_device *pdev)
-+{
-+ struct ata_host *host;
-+ struct ata_port *ap;
-+ struct rbppc_cf_info *info = NULL;
-+ struct resource res;
-+ void *baddr;
-+ const u32 *u32ptr;
-+ int irq_level = 0;
-+ int err = -ENOMEM;
-+
-+ printk(KERN_INFO "rbppc_cf_probe: MikroTik RouterBOARD 600 series Compact Flash PATA driver, version " DRV_VERSION "\n");
-+
-+ if (rbinfo == NULL) {
-+ info = kmalloc(sizeof(*info), GFP_KERNEL);
-+ if (info == NULL) {
-+ printk(KERN_ERR "rbppc_cf_probe: Out of memory\n");
-+ goto err_info;
-+ }
-+ memset(info, 0, sizeof(*info));
-+
-+ if (rbppc_cf_init_info(pdev, info)) {
-+ goto err_info;
-+ }
-+ rbinfo = info;
-+ }
-+
-+ u32ptr = of_get_property(pdev->dev.of_node, "interrupt-at-level", NULL);
-+ if (u32ptr) {
-+ irq_level = *u32ptr;
-+ printk(KERN_INFO "rbppc_cf_probe: IRQ level %u\n", irq_level);
-+ }
-+
-+ if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
-+ printk(KERN_ERR "rbppc_cf_probe: No reg property found\n");
-+ goto err_info;
-+ }
-+
-+ host = ata_host_alloc(&pdev->dev, 1);
-+ if (!host)
-+ goto err_info;
-+
-+ baddr = localbus_map(res.start, res.end - res.start + 1);
-+ host->iomap = baddr;
-+ host->private_data = rbinfo;
-+
-+ ap = host->ports[0];
-+ ap->ops = &rbppc_cf_port_ops;
-+ ap->pio_mask = 0x7F; /* PIO modes 0-6 */
-+ ap->mwdma_mask = 0;
-+
-+ ap->ioaddr.cmd_addr = baddr;
-+ ata_sff_std_ports(&ap->ioaddr);
-+ ap->ioaddr.ctl_addr = ap->ioaddr.cmd_addr + 14;
-+ ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
-+ ap->ioaddr.bmdma_addr = 0;
-+
-+ err = ata_host_activate(
-+ host,
-+ irq_of_parse_and_map(pdev->dev.of_node, 0), ata_sff_interrupt,
-+ irq_level ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW,
-+ &rbppc_cf_sht);
-+ if (!err) return 0;
-+
-+ localbus_unmap(baddr);
-+err_info:
-+ if (info) {
-+ kfree(info);
-+ rbinfo = NULL;
-+ }
-+ return err;
-+}
-+
-+static int rbppc_cf_remove(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct ata_host *host = dev_get_drvdata(dev);
-+
-+ if (host == NULL) return -1;
-+
-+ ata_host_detach(host);
-+ return 0;
-+}
-+
-+static struct of_device_id rbppc_cf_ids[] = {
-+ { .name = "cf", },
-+ { },
-+};
-+
-+static struct platform_driver rbppc_cf_driver = {
-+ .probe = rbppc_cf_probe,
-+ .remove = rbppc_cf_remove,
-+ .driver = {
-+ .name = "rbppc-cf",
-+ .owner = THIS_MODULE,
-+ .of_match_table = rbppc_cf_ids,
-+ },
-+};
-+
-+static int __init rbppc_init(void)
-+{
-+ return platform_driver_register(&rbppc_cf_driver);
-+}
-+
-+static void __exit rbppc_exit(void)
-+{
-+ platform_driver_unregister(&rbppc_cf_driver);
-+}
-+
-+MODULE_AUTHOR("Mikrotikls SIA");
-+MODULE_AUTHOR("Noah Fontes");
-+MODULE_DESCRIPTION("MikroTik RouterBOARD 600 series Compact Flash PATA driver");
-+MODULE_LICENSE("GPL");
-+MODULE_VERSION(DRV_VERSION);
-+
-+module_init(rbppc_init);
-+module_exit(rbppc_exit);
+++ /dev/null
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -463,6 +463,13 @@ config MTD_NAND_PLATFORM
- devices. You will need to provide platform-specific functions
- via platform_data.
-
-+config MTD_NAND_RB_PPC
-+ tristate "MikroTik RB333/600 NAND support"
-+ depends on RB_PPC
-+ help
-+ This option enables support for the NAND device on MikroTik
-+ RouterBOARD 333/600 series boards.
-+
- config MTD_ALAUDA
- tristate "MTD driver for Olympus MAUSB-10 and Fujifilm DPC-R1"
- depends on USB
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27
- obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
- obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
- obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
-+obj-$(CONFIG_MTD_NAND_RB_PPC) += rbppc_nand.o
- obj-$(CONFIG_MTD_ALAUDA) += alauda.o
- obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
- obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
---- /dev/null
-+++ b/drivers/mtd/nand/rbppc_nand.c
-@@ -0,0 +1,250 @@
-+/*
-+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
-+ * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
-+ * Copyright (C) Mikrotik 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/mtd/nand.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_device.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <asm/io.h>
-+
-+#define DRV_NAME "rbppc_nand"
-+#define DRV_VERSION "0.0.2"
-+
-+static struct mtd_info rmtd;
-+static struct nand_chip rnand;
-+
-+struct rbppc_nand_info {
-+ void *gpi;
-+ void *gpo;
-+ void *localbus;
-+
-+ unsigned gpio_rdy;
-+ unsigned gpio_nce;
-+ unsigned gpio_cle;
-+ unsigned gpio_ale;
-+ unsigned gpio_ctrls;
-+};
-+
-+/* We must use the OOB layout from yaffs 1 if we want this to be recognized
-+ * properly. Borrowed from the OpenWRT patches for the RB532.
-+ *
-+ * See <https://dev.openwrt.org/browser/trunk/target/linux/rb532/
-+ * patches-2.6.28/025-rb532_nand_fixup.patch> for more details.
-+ */
-+static struct nand_ecclayout rbppc_nand_oob_16 = {
-+ .eccbytes = 6,
-+ .eccpos = { 8, 9, 10, 13, 14, 15 },
-+ .oobavail = 9,
-+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
-+};
-+
-+static struct mtd_partition rbppc_nand_partition_info[] = {
-+ {
-+ name: "kernel",
-+ offset: 0,
-+ size: 4 * 1024 * 1024,
-+ },
-+ {
-+ name: "rootfs",
-+ offset: MTDPART_OFS_NXTBLK,
-+ size: MTDPART_SIZ_FULL,
-+ },
-+};
-+
-+static int rbppc_nand_dev_ready(struct mtd_info *mtd) {
-+ struct nand_chip *chip = mtd->priv;
-+ struct rbppc_nand_info *priv = chip->priv;
-+
-+ return in_be32(priv->gpi) & priv->gpio_rdy;
-+}
-+
-+static void rbppc_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) {
-+ struct nand_chip *chip = mtd->priv;
-+ struct rbppc_nand_info *priv = chip->priv;
-+
-+ if (ctrl & NAND_CTRL_CHANGE) {
-+ unsigned val = in_be32(priv->gpo);
-+ if (!(val & priv->gpio_nce)) {
-+ /* make sure Local Bus has done NAND operations */
-+ readb(priv->localbus);
-+ }
-+
-+ if (ctrl & NAND_CLE) {
-+ val |= priv->gpio_cle;
-+ } else {
-+ val &= ~priv->gpio_cle;
-+ }
-+ if (ctrl & NAND_ALE) {
-+ val |= priv->gpio_ale;
-+ } else {
-+ val &= ~priv->gpio_ale;
-+ }
-+ if (!(ctrl & NAND_NCE)) {
-+ val |= priv->gpio_nce;
-+ } else {
-+ val &= ~priv->gpio_nce;
-+ }
-+ out_be32(priv->gpo, val);
-+
-+ /* make sure GPIO output has changed */
-+ val ^= in_be32(priv->gpo);
-+ if (val & priv->gpio_ctrls) {
-+ printk(KERN_ERR "rbppc_nand_hwcontrol: NAND GPO change failed 0x%08x\n", val);
-+ }
-+ }
-+
-+ if (cmd != NAND_CMD_NONE) writeb(cmd, chip->IO_ADDR_W);
-+}
-+
-+static void rbppc_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-+{
-+ struct nand_chip *chip = mtd->priv;
-+ memcpy(buf, chip->IO_ADDR_R, len);
-+}
-+
-+static unsigned init_ok = 0;
-+
-+static int rbppc_nand_probe(struct platform_device *pdev)
-+{
-+ struct device_node *gpio;
-+ struct device_node *nnand;
-+ struct resource res;
-+ struct rbppc_nand_info *info;
-+ void *baddr;
-+ const unsigned *rdy, *nce, *cle, *ale;
-+
-+ printk(KERN_INFO "rbppc_nand_probe: MikroTik RouterBOARD 333/600 series NAND driver, version " DRV_VERSION "\n");
-+
-+ info = kmalloc(sizeof(*info), GFP_KERNEL);
-+
-+ rdy = of_get_property(pdev->dev.of_node, "rdy", NULL);
-+ nce = of_get_property(pdev->dev.of_node, "nce", NULL);
-+ cle = of_get_property(pdev->dev.of_node, "cle", NULL);
-+ ale = of_get_property(pdev->dev.of_node, "ale", NULL);
-+
-+ if (!rdy || !nce || !cle || !ale) {
-+ printk(KERN_ERR "rbppc_nand_probe: GPIO properties are missing\n");
-+ goto err;
-+ }
-+ if (rdy[0] != nce[0] || rdy[0] != cle[0] || rdy[0] != ale[0]) {
-+ printk(KERN_ERR "rbppc_nand_probe: Different GPIOs are not supported\n");
-+ goto err;
-+ }
-+
-+ gpio = of_find_node_by_phandle(rdy[0]);
-+ if (!gpio) {
-+ printk(KERN_ERR "rbppc_nand_probe: No GPIO<%x> node found\n", *rdy);
-+ goto err;
-+ }
-+ if (of_address_to_resource(gpio, 0, &res)) {
-+ printk(KERN_ERR "rbppc_nand_probe: No reg property in GPIO found\n");
-+ goto err;
-+ }
-+ info->gpo = ioremap_nocache(res.start, res.end - res.start + 1);
-+
-+ if (!of_address_to_resource(gpio, 1, &res)) {
-+ info->gpi = ioremap_nocache(res.start, res.end - res.start + 1);
-+ } else {
-+ info->gpi = info->gpo;
-+ }
-+ of_node_put(gpio);
-+
-+ info->gpio_rdy = 1 << (31 - rdy[1]);
-+ info->gpio_nce = 1 << (31 - nce[1]);
-+ info->gpio_cle = 1 << (31 - cle[1]);
-+ info->gpio_ale = 1 << (31 - ale[1]);
-+ info->gpio_ctrls = info->gpio_nce | info->gpio_cle | info->gpio_ale;
-+
-+ nnand = of_find_node_by_name(NULL, "nnand");
-+ if (!nnand) {
-+ printk("rbppc_nand_probe: No nNAND found\n");
-+ goto err;
-+ }
-+ if (of_address_to_resource(nnand, 0, &res)) {
-+ printk("rbppc_nand_probe: No reg property in nNAND found\n");
-+ goto err;
-+ }
-+ of_node_put(nnand);
-+ info->localbus = ioremap_nocache(res.start, res.end - res.start + 1);
-+
-+ if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
-+ printk("rbppc_nand_probe: No reg property found\n");
-+ goto err;
-+ }
-+ baddr = ioremap_nocache(res.start, res.end - res.start + 1);
-+
-+ memset(&rnand, 0, sizeof(rnand));
-+ rnand.cmd_ctrl = rbppc_nand_cmd_ctrl;
-+ rnand.dev_ready = rbppc_nand_dev_ready;
-+ rnand.read_buf = rbppc_nand_read_buf;
-+ rnand.IO_ADDR_W = baddr;
-+ rnand.IO_ADDR_R = baddr;
-+ rnand.priv = info;
-+
-+ memset(&rmtd, 0, sizeof(rmtd));
-+ rnand.ecc.mode = NAND_ECC_SOFT;
-+ rnand.ecc.layout = &rbppc_nand_oob_16;
-+ rnand.chip_delay = 25;
-+ rmtd.priv = &rnand;
-+ rmtd.owner = THIS_MODULE;
-+
-+ if (nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)) {
-+ printk(KERN_ERR "rbppc_nand_probe: RouterBOARD NAND device not found\n");
-+ return -ENXIO;
-+ }
-+
-+ mtd_device_parse_register(&rmtd, NULL, 0, rbppc_nand_partition_info, 2);
-+ init_ok = 1;
-+ return 0;
-+
-+err:
-+ kfree(info);
-+ return -1;
-+}
-+
-+static struct of_device_id rbppc_nand_ids[] = {
-+ { .name = "nand", },
-+ { },
-+};
-+
-+static struct platform_driver rbppc_nand_driver = {
-+ .probe = rbppc_nand_probe,
-+ .driver = {
-+ .name = "rbppc-nand",
-+ .owner = THIS_MODULE,
-+ .of_match_table = rbppc_nand_ids,
-+ },
-+};
-+
-+static int __init rbppc_nand_init(void)
-+{
-+ return platform_driver_register(&rbppc_nand_driver);
-+}
-+
-+static void __exit rbppc_nand_exit(void)
-+{
-+ platform_driver_unregister(&rbppc_nand_driver);
-+}
-+
-+MODULE_AUTHOR("Mikrotikls SIA");
-+MODULE_AUTHOR("Noah Fontes");
-+MODULE_AUTHOR("Michael Guntsche");
-+MODULE_DESCRIPTION("MikroTik RouterBOARD 333/600 series NAND driver");
-+MODULE_LICENSE("GPL");
-+MODULE_VERSION(DRV_VERSION);
-+
-+module_init(rbppc_nand_init);
-+module_exit(rbppc_nand_exit);
+++ /dev/null
---- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
-+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
-@@ -81,6 +81,11 @@
- reg = <0x3a0000 0x3c60000>;
- label = "rootfs";
- };
-+
-+ partition1@a0000 {
-+ reg = <0xa0000 0x3f60000>;
-+ label = "firmware";
-+ };
- };
- };
-
-@@ -476,4 +481,8 @@
- default-state = "off";
- };
- };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200 rootfstype=squashfs noinitrd";
-+ };
- };
+++ /dev/null
-#
-# Copyright (C) 2012-2014 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=mvebu
-BOARDNAME:=Marvell Armada XP/370
-FEATURES:=targz usb pci pcie gpio nand squashfs
-CPU_TYPE:=cortex-a9
-CPU_SUBTYPE:=vfpv3
-MAINTAINER:=Luka Perkov <luka@openwrt.org>
-
-LINUX_VERSION:=3.14.12
-
-include $(INCLUDE_DIR)/target.mk
-
-KERNELNAME:="zImage dtbs"
-
-DEFAULT_PACKAGES += uboot-envtools
-
-$(eval $(call BuildTarget))
+++ /dev/null
-define Package/base-files/install-target
- rm -f $(1)/etc/config/network
-endef
+++ /dev/null
-#!/bin/sh
-# Copyright (C) 2014 OpenWrt.org
-
-. /lib/functions/leds.sh
-. /lib/mvebu.sh
-
-get_status_led() {
- case $(mvebu_board_name) in
- armada-xp-mamba)
- status_led="mamba:white:power"
- ;;
- esac
-}
-
-set_state() {
- get_status_led
-
- case "$1" in
- preinit)
- status_led_blink_preinit
- ;;
- failsafe)
- status_led_blink_failsafe
- ;;
- done)
- status_led_on
- ;;
- esac
-}
+++ /dev/null
-#!/bin/sh
-#
-# Copyright (C) 2014 OpenWrt.org
-#
-
-. /lib/functions/uci-defaults.sh
-. /lib/mvebu.sh
-
-board=$(mvebu_board_name)
-
-case "$board" in
-armada-xp-mamba)
- ucidef_set_led_netdev "wan" "WAN" "tlc59116:1" "eth1"
- ucidef_set_led_usbdev "usb1" "USB1" "tlc59116:5" "1-1"
- ucidef_set_led_usbdev "usb2" "USB2" "tlc59116:6" "2-2"
- ;;
-
-esac
-
-ucidef_commit_leds
-
-exit 0
+++ /dev/null
-#!/bin/sh
-#
-# Copyright (C) 2014 OpenWrt.org
-#
-
-[ -e /etc/config/network ] && exit 0
-
-touch /etc/config/network
-
-. /lib/functions/uci-defaults.sh
-. /lib/mvebu.sh
-
-ucidef_set_interface_loopback
-
-board=$(mvebu_board_name)
-
-case "$board" in
-armada-xp-mamba)
- ucidef_set_interfaces_lan_wan "eth0" "eth1"
- ;;
-
-*)
- ucidef_set_interface_lan "eth0"
- ;;
-esac
-
-uci commit network
-
-exit 0
+++ /dev/null
-#!/bin/sh
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-
-MVEBU_BOARD_NAME=
-MVEBU_MODEL=
-
-mvebu_board_detect() {
- local machine
- local name
-
- machine=$(cat /proc/device-tree/model)
-
- case "$machine" in
- *"Marvell Armada 370 Evaluation Board")
- name="armada-370-db"
- ;;
- *"Globalscale Mirabox")
- name="mirabox"
- ;;
- *"Marvell Armada 370 Reference Design")
- name="armada-370-rd"
- ;;
- *"Marvell Armada XP Evaluation Board")
- name="armada-xp-db"
- ;;
- *"PlatHome OpenBlocks AX3-4 board")
- name="openblocks-ax3-4"
- ;;
- *"Marvell Armada XP GP Board")
- name="armada-xp-gp"
- ;;
- *"Linksys WRT1900AC (Mamba)")
- name="armada-xp-mamba"
- ;;
- esac
-
- [ -z "$name" ] && name="unknown"
-
- [ -z "$MVEBU_BOARD_NAME" ] && MVEBU_BOARD_NAME="$name"
- [ -z "$MVEBU_MODEL" ] && MVEBU_MODEL="$machine"
-
- [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/"
-
- echo "$MVEBU_BOARD_NAME" > /tmp/sysinfo/board_name
- echo "$MVEBU_MODEL" > /tmp/sysinfo/model
-}
-
-mvebu_board_name() {
- local name
-
- [ -f /tmp/sysinfo/board_name ] || mvebu_board_detect
- [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name)
- [ -z "$name" ] && name="unknown"
-
- echo "$name"
-}
+++ /dev/null
-#
-# Copyright (C) 2014 OpenWrt.org
-#
-
-preinit_set_mac_address() {
- local mac
-
- . /lib/functions.sh
- . /lib/mvebu.sh
-
- case $(mvebu_board_name) in
- armada-xp-mamba)
- mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
- ifconfig eth0 hw ether $mac 2>/dev/null
- ifconfig eth1 hw ether $mac 2>/dev/null
- ;;
- esac
-}
-
-boot_hook_add preinit_main preinit_set_mac_address
+++ /dev/null
-#
-# Copyright (C) 2014 OpenWrt.org
-#
-
-preinit_mount_syscfg() {
-
- . /lib/functions.sh
- . /lib/mvebu.sh
-
- case $(mvebu_board_name) in
- armada-xp-mamba)
- mkdir /tmp/syscfg
- ubiattach -p /dev/mtd8
- mount -t ubifs ubi1:syscfg /tmp/syscfg
- [ -f /tmp/syscfg/sysupgrade.tgz ] && {
- echo "- config restore -"
- cd /
- mv /tmp/syscfg/sysupgrade.tgz /tmp
- tar xzf /tmp/sysupgrade.tgz
- rm -f /tmp/sysupgrade.tgz
- sync
- }
- ;;
- esac
-}
-
-boot_hook_add preinit_main preinit_mount_syscfg
+++ /dev/null
-#
-# Copyright (C) 2014 OpenWrt.org
-#
-
-linksys_get_target_firmware() {
- cur_boot_part=`/usr/sbin/fw_printenv -n boot_part`
- target_firmware=""
- if [ "$cur_boot_part" = "1" ]
- then
- # current primary boot - update alt boot
- target_firmware="kernel2"
- fw_setenv boot_part 2
- fw_setenv bootcmd "run altnandboot"
- elif [ "$cur_boot_part" = "2" ]
- then
- # current alt boot - update primary boot
- target_firmware="kernel1"
- fw_setenv boot_part 1
- fw_setenv bootcmd "run nandboot"
- fi
-
- echo "$target_firmware"
-}
-
-linksys_get_root_magic() {
- (get_image "$@" | dd skip=786432 bs=4 count=1 | hexdump -v -n 4 -e '1/1 "%02x"') 2>/dev/null
-}
-
-platform_do_upgrade_linksys() {
- local magic_long="$(get_magic_long "$1")"
-
- mkdir -p /var/lock
- local part_label="$(linksys_get_target_firmware)"
- touch /var/lock/fw_printenv.lock
-
- if [ ! -n "$part_label" ]
- then
- echo "cannot find target partition"
- exit 1
- fi
-
- local target_mtd=$(find_mtd_part $part_label)
-
- [ "$magic_long" = "73797375" ] && {
- CI_KERNPART="$part_label"
- if [ "$part_label" = "kernel1" ]
- then
- CI_UBIPART="rootfs1"
- else
- CI_UBIPART="rootfs2"
- fi
-
- nand_upgrade_tar "$1"
- }
- [ "$magic_long" = "27051956" ] && {
- # check firmwares' rootfs types
- local target_mtd=$(find_mtd_part $part_label)
- local oldroot="$(linksys_get_root_magic $target_mtd)"
- local newroot="$(linksys_get_root_magic "$1")"
-
- if [ "$newroot" = "55424923" -a "$oldroot" = "55424923" ]
- # we're upgrading from a firmware with UBI to one with UBI
- then
- # erase everything to be safe
- mtd erase $part_label
- get_image "$1" | mtd -n write - $part_label
- else
- get_image "$1" | mtd write - $part_label
- fi
- }
-}
-
-linksys_preupgrade() {
- export RAMFS_COPY_BIN="${RAMFS_COPY_BIN} /usr/sbin/fw_printenv /usr/sbin/fw_setenv"
- export RAMFS_COPY_BIN="${RAMFS_COPY_BIN} /bin/mkdir /bin/touch"
- export RAMFS_COPY_DATA="${RAMFS_COPY_DATA} /etc/fw_env.config /var/lock/fw_printenv.lock"
-
- [ -f /tmp/sysupgrade.tgz ] && {
- cp /tmp/sysupgrade.tgz /tmp/syscfg/sysupgrade.tgz
- }
-}
-
-append sysupgrade_pre_upgrade linksys_preupgrade
+++ /dev/null
-#
-# Copyright (C) 2014 OpenWrt.org
-#
-
-. /lib/mvebu.sh
-
-RAMFS_COPY_DATA=/lib/mvebu.sh
-
-platform_check_image() {
- local board=$(mvebu_board_name)
- local magic_long="$(get_magic_long "$1")"
-
- [ "$#" -gt 1 ] && return 1
-
- case "$board" in
- armada-xp-mamba )
- [ "$magic_long" != "27051956" -a "$magic_long" != "73797375" ] && {
- echo "Invalid image type."
- return 1
- }
- return 0;
- ;;
- esac
-
- echo "Sysupgrade is not yet supported on $board."
- return 1
-}
-
-platform_do_upgrade() {
- local board=$(mvebu_board_name)
-
- case "$board" in
- armada-xp-mamba)
- platform_do_upgrade_linksys "$ARGV"
- ;;
- *)
- default_do_upgrade "$ARGV"
- ;;
- esac
-}
-
-disable_watchdog() {
- killall watchdog
- ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && {
- echo 'Could not disable watchdog'
- return 1
- }
-}
-
-append sysupgrade_pre_upgrade disable_watchdog
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MVEBU=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARMADA_370_CLK=y
-CONFIG_ARMADA_370_XP_TIMER=y
-CONFIG_ARMADA_XP_CLK=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BOUNCE=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CACHE_PL310=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BIG_ENDIAN is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PJ4B=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_XZ=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-# CONFIG_DEBUG_LL_UART_8250 is not set
-# CONFIG_DEBUG_LL_UART_PL01X is not set
-CONFIG_DEBUG_MVEBU_UART=y
-# CONFIG_DEBUG_MVEBU_UART_ALTERNATE is not set
-CONFIG_DEBUG_UART_8250=y
-# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
-CONFIG_DEBUG_UART_8250_SHIFT=2
-# CONFIG_DEBUG_UART_8250_WORD is not set
-CONFIG_DEBUG_UART_PHYS=0xd0012000
-# CONFIG_DEBUG_UART_PL01X is not set
-CONFIG_DEBUG_UART_VIRT=0xfec12000
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_DEBUG_USER=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DTC=y
-# CONFIG_DW_DMAC_CORE is not set
-# CONFIG_DW_DMAC_PCI is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_FIXED_PHY=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_MVEBU=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IOMMU_HELPER=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_DEBUG=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_ARMADA_370=y
-CONFIG_MACH_ARMADA_370_XP=y
-CONFIG_MACH_ARMADA_XP=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MEMORY=y
-CONFIG_MIGHT_HAVE_PCI=y
-# CONFIG_MLX5_CORE is not set
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_PXA3xx=y
-# CONFIG_MTD_SM_COMMON is not set
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_MVEBU_CLK_COMMON=y
-CONFIG_MVEBU_CLK_COREDIV=y
-CONFIG_MVEBU_CLK_CPU=y
-CONFIG_MVEBU_DEVBUS=y
-CONFIG_MVEBU_MBUS=y
-CONFIG_MVMDIO=y
-CONFIG_MVNETA=y
-CONFIG_MV_XOR=y
-CONFIG_NEED_DMA_MAP_STATE=y
-# CONFIG_NEON is not set
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MVEBU=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ARMADA_370=y
-CONFIG_PINCTRL_ARMADA_XP=y
-CONFIG_PINCTRL_MVEBU=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PJ4B_ERRATA_4742=y
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-CONFIG_PLAT_ORION=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_MV is not set
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_ORION=y
-CONFIG_STOP_MACHINE=y
-CONFIG_SWIOTLB=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_STATS=y
-CONFIG_TREE_RCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_XZ=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UID16=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-# CONFIG_XEN is not set
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-# CONFIG_ZBUD is not set
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-/*
- * Device Tree file for the Linksys WRT1900AC (Mamba).
- *
- * Note: this board is shipped with a new generation boot loader that
- * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
- * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be
- * used.
- *
- * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
- *
- * Based on armada-xp-axpwifiap.dts:
- *
- * Copyright (C) 2013 Marvell
- *
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "armada-xp-mv78230.dtsi"
-
-/ {
- model = "Linksys WRT1900AC (Mamba)";
- compatible = "linksys,mamba", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
-
- chosen {
- bootargs = "console=ttyS0,115200 earlyprintk";
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
- };
-
- soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
-
- pcie-controller {
- status = "okay";
-
- /* Etron EJ168 USB 3.0 controller */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* First mini-PCIe port */
- pcie@2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
- };
-
- /* Second mini-PCIe port */
- pcie@3,0 {
- /* Port 0, Lane 3 */
- status = "okay";
- };
- };
-
- internal-regs {
- pinctrl {
- pmx_ge0: pmx-ge0 {
- marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
- "mpp4", "mpp5", "mpp6", "mpp7",
- "mpp8", "mpp9", "mpp10", "mpp11";
- marvell,function = "ge0";
- };
-
- pmx_ge1: pmx-ge1 {
- marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
- "mpp16", "mpp17", "mpp18", "mpp19",
- "mpp20", "mpp21", "mpp22", "mpp23";
- marvell,function = "ge1";
- };
-
- pmx_keys: pmx-keys {
- marvell,pins = "mpp32", "mpp33";
- marvell,function = "gpio";
- };
-
- pmx_spi: pmx-spi {
- marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
- marvell,function = "spi";
- };
-
- power_led_pin: power-led-pin {
- marvell,pins = "mpp40";
- marvell,function = "gpio";
- };
-
- gpio_fan_pin: gpio-fan-pin {
- marvell,pins = "mpp24";
- marvell,function = "gpio";
- };
-
- };
-
- serial@12000 {
- clock-frequency = <250000000>;
- status = "okay";
- };
-
- serial@12100 {
- clock-frequency = <250000000>;
- status = "okay";
- };
-
- sata@a0000 {
- nr-ports = <1>;
- status = "okay";
- };
-
- mdio {
- status = "disabled";
- };
-
- ethernet@70000 {
- pinctrl-0 = <&pmx_ge0>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii-id";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- ethernet@74000 {
- pinctrl-0 = <&pmx_ge1>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii-id";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- /* USB part of the eSATA/USB 2.0 port */
- usb@50000 {
- status = "okay";
- };
-
- i2c@11000 {
- status = "okay";
- clock-frequency = <100000>;
-
- tlc59116@68 {
- #gpio-cells = <2>;
- compatible = "gpio,tlc59116";
- reg = <0x68>;
- gpio-controller;
- };
- };
-
- nand@d0000 {
- status = "okay";
- num-cs = <1>;
- marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
-
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x100000>; /* 1MB */
- read-only;
- };
-
- partition@100000 {
- label = "u_env";
- reg = <0x100000 0x40000>; /* 256KB */
- };
-
- partition@140000 {
- label = "s_env";
- reg = <0x140000 0x40000>; /* 256KB */
- };
-
- partition@900000 {
- label = "devinfo";
- reg = <0x900000 0x100000>; /* 1MB */
- read-only;
- };
-
- partition@a00000 {
- label = "kernel1";
- reg = <0xa00000 0x2800000>; /* 3MB */
- };
-
- partition@d00000 {
- label = "rootfs1";
- reg = <0xd00000 0x2500000>; /* 37MB */
- };
-
- partition@3200000 {
- label = "kernel2";
- reg = <0x3200000 0x2800000>; /* 3MB */
- };
-
- partition@3500000 {
- label = "rootfs2";
- reg = <0x3500000 0x2500000>; /* 37MB */
- };
-
- /* Last MB is for the BBT, i.e. not writable */
- partition@5a00000 {
- label = "syscfg";
- reg = <0x5a00000 0x2600000>; /* 38MB */
- };
- };
-
- spi0: spi@10600 {
- status = "okay";
- pinctrl-0 = <&pmx_spi>;
- pinctrl-names = "default";
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "mr25h256";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <108000000>;
- };
- };
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_keys>;
- pinctrl-names = "default";
-
- button@1 {
- label = "WPS";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
- };
-
- button@2 {
- label = "Factory Reset Button";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&power_led_pin>;
- pinctrl-names = "default";
-
- power {
- label = "mamba:white:power";
- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- };
-
- gpio_fan {
- /* SUNON HA4010V4-0000-C99 */
- compatible = "gpio-fan";
- gpios = <&gpio0 24 0>;
-
- gpio-fan,speed-map = <0 0
- 4500 1>;
- };
-};
+++ /dev/null
-#
-# Copyright (C) 2012-2014 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-TARGET_DTBS := armada-xp-db armada-370-db armada-xp-openblocks-ax3-4 armada-370-mirabox \
- armada-370-rd armada-xp-gp armada-xp-mamba
-
-LOADADDR:=0x00008000
-
-JFFS2_BLOCKSIZE = 128k
-
-UBIFS_OPTS = -F -m 2048 -e 124KiB -c 4096 -U
-UBI_OPTS = -m 2048 -p 128KiB -s 512 -O 2048
-
-KDIR_TMP:=$(KDIR)/tmp
-
-
-UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage
-
-define Image/Build/MkuImage
- mkimage -A arm -O linux -T kernel -a $(LOADADDR) -C none -e $(LOADADDR) \
- -n 'ARM OpenWrt Linux-$(LINUX_VERSION)' -d $(1) $(2);
-endef
-
-define Image/Build/DTB
- cp $(KDIR)/zImage$(2) $(KDIR)/zImage$(2)-$(1);
- cat $(DTS_DIR)/$(1).dtb >> $(KDIR)/zImage$(2)-$(1);
- $(call Image/Build/MkuImage,$(KDIR)/zImage$(2)-$(1),$(KDIR)/uImage$(2)-$(1))
- cp $(KDIR)/uImage$(2)-$(1) $(UIMAGE)$(2)-$(1);
-endef
-
-define Image/BuildKernel
- $(foreach dtb,$(TARGET_DTBS),$(call Image/Build/DTB,$(dtb)))
- ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
- $(call Image/Build/Initramfs)
- endif
-endef
-
-define Image/Build/squashfs
- $(STAGING_DIR_HOST)/bin/padjffs2 $(KDIR)/root.squashfs 128
- $(foreach dtb,$(TARGET_DTBS),$(call Image/Build/UbinizeImage,$(dtb),,squashfs,$(UBI_OPTS));)
- ( \
- dd if=$(KDIR)/uImage-armada-xp-mamba bs=3072k conv=sync; \
- dd if=$(BIN_DIR)/$(IMG_PREFIX)-armada-xp-mamba-squashfs-ubinized.bin \
- bs=2048 conv=sync; \
- ) > $(BIN_DIR)/$(IMG_PREFIX)-armada-xp-mamba-squashfs-factory.img
-endef
-
-define Image/Build/Initramfs
- $(foreach dtb,$(TARGET_DTBS),$(call Image/Build/DTB,$(dtb),-initramfs))
-endef
-
-define BuildSysupgrade
- $(call Image/Build/SysupgradeNAND,$(2),$(1),$(KDIR)/uImage-$(2))
-endef
-
-define Image/Build
- $(call Image/Build/$(1))
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync
- $(foreach dtb,$(TARGET_DTBS),$(call BuildSysupgrade,$(1),$(dtb));)
-ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
- $(call Image/Build/Initramfs)
-endif
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -131,6 +131,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-d
- armada-xp-db.dtb \
- armada-xp-gp.dtb \
- armada-xp-netgear-rn2120.dtb \
-+ armada-xp-mamba.dtb \
- armada-xp-matrix.dtb \
- armada-xp-openblocks-ax3-4.dtb
- dtb-$(CONFIG_ARCH_MXC) += \
+++ /dev/null
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -43,12 +43,10 @@
- };
-
- i2c0: i2c@11000 {
-- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- reg = <0x11000 0x100>;
- };
-
- i2c1: i2c@11100 {
-- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- reg = <0x11100 0x100>;
- };
-
+++ /dev/null
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -487,6 +487,15 @@ config LEDS_BLINKM
- This option enables support for the BlinkM RGB LED connected
- through I2C. Say Y to enable support for the BlinkM LED.
-
-+config LEDS_TLC59116
-+ tristate "LED driver for TLC59116F dimmer"
-+ depends on LEDS_CLASS
-+ depends on I2C
-+ help
-+ This option enables support for Texas Instruments TLC59116F
-+ LED controller. It is generally only useful
-+ as a platform driver
-+
- comment "LED Triggers"
- source "drivers/leds/trigger/Kconfig"
-
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -54,6 +54,7 @@ obj-$(CONFIG_LEDS_ASIC3) += leds-asic3.
- obj-$(CONFIG_LEDS_MAX8997) += leds-max8997.o
- obj-$(CONFIG_LEDS_LM355x) += leds-lm355x.o
- obj-$(CONFIG_LEDS_BLINKM) += leds-blinkm.o
-+obj-$(CONFIG_LEDS_TLC59116) += leds-tlc59116.o
-
- # LED SPI Drivers
- obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o
---- /dev/null
-+++ b/drivers/leds/leds-tlc59116.c
-@@ -0,0 +1,498 @@
-+/*
-+ * Copyright 2014 Belkin Inc.
-+ *
-+ * Author: Belkin Inc.
-+ *
-+ * This file is subject to the terms and conditions of version 2 of
-+ * the GNU General Public License. See the file COPYING in the main
-+ * directory of this archive for more details.
-+ *
-+ * LED driver for various TLC59116 I2C LED drivers
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/delay.h>
-+#include <linux/string.h>
-+#include <linux/ctype.h>
-+#include <linux/leds.h>
-+#include <linux/err.h>
-+#include <linux/i2c.h>
-+#include <linux/workqueue.h>
-+
-+/* LED select registers determine the source that drives LED outputs */
-+#define TLC59116_LED_OFF 0x0 /* Output LOW */
-+#define TLC59116_LED_ON 0x1 /* Output HI-Z */
-+#define TLC59116_DIM 0x2 /* Dimming */
-+#define TLC59116_BLINK 0x3 /* Blinking */
-+
-+#define TLC59116_PINS 16
-+#define TLC59116_REG_MODE1 0x00 /* Mode register 0 */
-+#define MODE1_RESPON_ADDR_MASK 0xF0
-+#define MODE1_NORMAL_MODE (0 << 4)
-+#define MODE1_SPEED_MODE (1 << 4)
-+
-+#define TLC59116_REG_MODE2 0x01 /* Mode register 1 */
-+#define MODE2_DIM (0 << 5)
-+#define MODE2_BLINK (1 << 5)
-+#define MODE2_OCH_STOP (0 << 3)
-+#define MODE2_OCH_ACK (1 << 3)
-+
-+#define TLC59116_REG_PWM0 0x02
-+#define TLC59116_REG_PWM1 0x03
-+#define TLC59116_REG_PWM2 0x04
-+#define TLC59116_REG_PWM3 0x05
-+#define TLC59116_REG_PWM4 0x06
-+#define TLC59116_REG_PWM5 0x07
-+#define TLC59116_REG_PWM6 0x08
-+#define TLC59116_REG_PWM7 0x09
-+#define TLC59116_REG_PWM8 0x0a
-+#define TLC59116_REG_PWM9 0x0b
-+#define TLC59116_REG_PWM10 0x0c
-+#define TLC59116_REG_PWM11 0x0d
-+#define TLC59116_REG_PWM12 0x0e
-+#define TLC59116_REG_PWM13 0x0f
-+#define TLC59116_REG_PWM14 0x10
-+#define TLC59116_REG_PWM15 0x01
-+
-+#define TLC59116_REG_GRPPWM 0x12
-+#define TLC59116_REG_GRPFREQ 0x13
-+
-+#define TLC59116_PERIOD_MIN 41 /* 41ms */
-+#define TLC59116_PERIOD_MAX 10730 /* 10.73s */
-+
-+#define TLC59116_REG_LEDOUT0 0x14 /* LED [3:0] driver output state registers */
-+#define TLC59116_REG_LEDOUT1 0x15 /* LED [7:4] driver output state registers */
-+#define TLC59116_REG_LEDOUT2 0x16 /* LED [11:8] driver output state registers */
-+#define TLC59116_REG_LEDOUT3 0x17 /* LED [15:12] driver output state registers */
-+
-+#define GPIO0_MASK 0x3
-+
-+#define DEBUG 0
-+
-+#if DEBUG > 1
-+#define led_dbg(fmt, arg...) printk(KERN_DEBUG "tlc59116:%s " fmt "\n", __func__ , ## arg)
-+#else
-+#define led_dbg(fmt, arg...)
-+#endif
-+
-+
-+#if DEBUG > 0
-+#define led_info(fmt, arg...) printk("tlc59116:%s " fmt "\n", __func__ , ## arg)
-+#else
-+#define led_info(fmt, arg...)
-+#endif
-+
-+enum tlc59116_type {
-+ tlc59116,
-+};
-+
-+struct tlc59116_chipdef {
-+ int bits;
-+ u8 slv_addr; /* 7-bit slave address mask */
-+ int slv_addr_shift; /* Number of bits to ignore */
-+};
-+
-+static struct tlc59116_chipdef tlc59116_chipdefs[] = {
-+ [tlc59116] = {
-+ .bits = 16,
-+ .slv_addr = /* 1100xxx */ 0x68,
-+ .slv_addr_shift = 3,
-+ },
-+};
-+
-+static const struct i2c_device_id tlc59116_id[] = {
-+ { "tlc59116", tlc59116 },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(i2c, tlc59116_id);
-+
-+struct tlc59116_led {
-+ struct tlc59116_chipdef *chipdef;
-+ struct i2c_client *client;
-+ struct work_struct work;
-+ spinlock_t lock;
-+ enum led_brightness brightness;
-+ struct led_classdev led_cdev;
-+ int led_num; /* 0 .. 8 potentially */
-+ char name[32];
-+};
-+
-+//#define DUMP_REGS
-+
-+#ifdef DUMP_REGS
-+void dump_regs(struct i2c_client *client)
-+{
-+ int i, j = 0;
-+ u8 data;
-+ printk ("\n-------------------------------------\n");
-+ for (i = 0; i< 0x20; i++)
-+ {
-+ data = i2c_smbus_read_byte_data(client, i);
-+ printk ("[0x%x] = 0x%x ",i, data);
-+ j++;
-+ if (j == 5)
-+ {
-+ printk ("\n");
-+ j = 0;
-+ }
-+ }
-+ printk ("\n");
-+}
-+#endif
-+
-+static int tlc59116_set_mode(struct i2c_client *client, uint8_t mode)
-+{
-+ uint8_t val = 0;
-+
-+ if ((mode != MODE2_DIM) && (mode != MODE2_BLINK))
-+ mode = MODE2_DIM;
-+
-+ /* Configure MODE1 register */
-+ val &= 0x0;
-+ val &= MODE1_RESPON_ADDR_MASK;
-+ val |= MODE1_NORMAL_MODE;
-+ i2c_smbus_write_byte_data(client, TLC59116_REG_MODE1, val);
-+
-+ /* Configure MODE2 Reg */
-+ val &= 0x00;
-+ val |= MODE2_OCH_STOP;
-+
-+ val |= mode;
-+
-+ i2c_smbus_write_byte_data(client, TLC59116_REG_MODE2, val);
-+ mdelay(100);
-+
-+ return 0;
-+}
-+
-+static int tlc59116_set_gpio_act(struct i2c_client *client, u8 gpio_no, u8 act_mode)
-+{
-+ char data, addr = 0, i;
-+
-+ if ((gpio_no >= 0) && (gpio_no < 4))
-+ addr = TLC59116_REG_LEDOUT0;
-+ else if ((gpio_no >= 4) && (gpio_no < 8))
-+ addr = TLC59116_REG_LEDOUT1;
-+ else if ((gpio_no >= 8) && (gpio_no < 12))
-+ addr = TLC59116_REG_LEDOUT2;
-+ else if ((gpio_no >=12 ) && (gpio_no < 16))
-+ addr = TLC59116_REG_LEDOUT3;
-+
-+ data = i2c_smbus_read_byte_data(client, addr);
-+
-+ i = (gpio_no % 4) * 2;
-+
-+ data &= ~(GPIO0_MASK << i);
-+ act_mode = act_mode << i;
-+ data |= act_mode;
-+
-+ if(i2c_smbus_write_byte_data(client, addr, data) != 0) {
-+ return -1;
-+ }
-+ return 0;
-+}
-+
-+static int tlc59116_set_gpio(struct i2c_client *client, uint8_t gpio_no, uint8_t val)
-+{
-+ val &= 0x03;
-+ tlc59116_set_gpio_act(client, gpio_no, val);
-+#ifdef DUMP_REGS
-+ dump_regs(client);
-+#endif
-+ return 0;
-+}
-+
-+static int tlc59116_get_gpio(struct i2c_client *client, uint8_t gpio_no)
-+{
-+ uint8_t val, reg, data;
-+
-+ led_dbg("gpio = %d\n", gpio_no);
-+ reg = TLC59116_REG_LEDOUT0;
-+
-+ if ((gpio_no >= 0) && (gpio_no < 4))
-+ reg = TLC59116_REG_LEDOUT0;
-+ else if ((gpio_no >= 4) && (gpio_no < 8)) {
-+ reg = TLC59116_REG_LEDOUT1;
-+ gpio_no = gpio_no - 4;
-+ }
-+ else if ((gpio_no >= 8) && (gpio_no < 12)) {
-+ reg = TLC59116_REG_LEDOUT2;
-+ gpio_no = gpio_no - 8;
-+ }
-+ else if ((gpio_no >=12 ) && (gpio_no < 16)) {
-+ reg = TLC59116_REG_LEDOUT3;
-+ gpio_no = gpio_no - 12;
-+ }
-+
-+ val = i2c_smbus_read_byte_data(client, reg);
-+
-+ data = (val >> (gpio_no * 2)) & 0x03;
-+ return data;
-+}
-+
-+/*
-+ * gpio_no [0..7]
-+ * duty_cycle [0..99]%
-+ *
-+ * */
-+static int tlc59116_individual_brighness_control(struct i2c_client *client, uint8_t gpio_no, uint8_t brightness)
-+{
-+ uint8_t pwm;
-+
-+ pwm = gpio_no + TLC59116_REG_PWM0;
-+ i2c_smbus_write_byte_data(client, pwm, brightness);
-+
-+ return 0;
-+}
-+
-+static void tlc59116_led_work(struct work_struct *work)
-+{
-+ struct tlc59116_led *tlc59116;
-+
-+ tlc59116 = container_of(work, struct tlc59116_led, work);
-+
-+ led_dbg("\nbrighness = %d \n", tlc59116->brightness);
-+ switch (tlc59116->brightness) {
-+ case LED_OFF:
-+ led_info("\nLed off\n");
-+ tlc59116_set_gpio(tlc59116->client, tlc59116->led_num, TLC59116_LED_OFF);
-+ break;
-+
-+ case LED_FULL:
-+ led_info("\nLed on\n");
-+ tlc59116_set_gpio(tlc59116->client, tlc59116->led_num, TLC59116_LED_ON);
-+ break;
-+ default:
-+ led_info("\nBrightness is %d\n", tlc59116->brightness);
-+ if (TLC59116_BLINK != tlc59116_get_gpio(tlc59116->client, tlc59116->led_num))
-+ tlc59116_set_gpio(tlc59116->client, tlc59116->led_num, TLC59116_DIM);
-+
-+ tlc59116_individual_brighness_control(tlc59116->client, tlc59116->led_num, tlc59116->brightness);
-+ break;
-+ }
-+
-+}
-+
-+static void tlc59116_led_set(struct led_classdev *led_cdev, enum led_brightness value)
-+{
-+ struct tlc59116_led *tlc59116;
-+
-+ tlc59116 = container_of(led_cdev, struct tlc59116_led, led_cdev);
-+
-+ spin_lock(&tlc59116->lock);
-+ tlc59116->brightness = value;
-+
-+ /*
-+ * Must use workqueue for the actual I/O since I2C operations
-+ * can sleep.
-+ */
-+ schedule_work(&tlc59116->work);
-+
-+ spin_unlock(&tlc59116->lock);
-+}
-+
-+/*
-+ * delay_on, delay_off: units are in ms
-+ *
-+ */
-+
-+static int tlc59116_set_blink(struct led_classdev *led_cdev,
-+ unsigned long *delay_on,
-+ unsigned long *delay_off)
-+{
-+ struct tlc59116_led *tlc59116;
-+ uint16_t period;
-+ uint16_t duty_cycle;
-+ uint8_t gdc;
-+ uint8_t gfrq;
-+
-+ tlc59116 = container_of(led_cdev, struct tlc59116_led, led_cdev);
-+ led_info ("Blinking: delay_on = %ldms, delay_off = %ldms, brightness = %d\n",
-+ *delay_on, *delay_off, tlc59116->brightness);
-+
-+ // Hardware blinking only for tricolor leds . The rest will have software blinking
-+ if (tlc59116->led_num > 2)
-+ return 1;
-+
-+ if ((*delay_on == 0) && (*delay_off ==0)) {
-+ spin_lock(&tlc59116->lock);
-+
-+ /* MODE2[DMBLNK] = 1 */
-+ tlc59116_set_mode(tlc59116->client, MODE2_BLINK);
-+
-+ /* Set LDRx = 11 */
-+ tlc59116_set_gpio(tlc59116->client, tlc59116->led_num, TLC59116_BLINK);
-+
-+ tlc59116_individual_brighness_control(tlc59116->client, tlc59116->led_num, tlc59116->brightness);
-+ spin_unlock(&tlc59116->lock);
-+ return 0;
-+ }
-+
-+
-+ if ((*delay_on + *delay_off) > TLC59116_PERIOD_MAX)
-+ {
-+ led_dbg ("Max period is %dms\n", TLC59116_PERIOD_MAX);
-+ return -EINVAL;
-+ }
-+
-+ if ((*delay_on + *delay_off) < TLC59116_PERIOD_MIN)
-+ {
-+ *delay_on = TLC59116_PERIOD_MIN/2 + 1;
-+ *delay_off = TLC59116_PERIOD_MIN/2 + 1;
-+ }
-+ period = (*delay_on) + (*delay_off);
-+
-+ duty_cycle = (100 * (*delay_on)) / period;
-+
-+ spin_lock(&tlc59116->lock);
-+
-+ /* MODE2[DMBLNK] = 1 */
-+ tlc59116_set_mode(tlc59116->client, MODE2_BLINK);
-+
-+ /* Set LDRx = 11 */
-+ tlc59116_set_gpio(tlc59116->client, tlc59116->led_num, TLC59116_BLINK);
-+
-+ tlc59116_individual_brighness_control(tlc59116->client, tlc59116->led_num, tlc59116->brightness);
-+
-+ gdc = (duty_cycle * 256)/100;
-+ i2c_smbus_write_byte_data(tlc59116->client, TLC59116_REG_GRPPWM, gdc);
-+
-+ gfrq = (24 * period)/1000 - 1; /* unit is in second (convert from ms to second) */
-+ i2c_smbus_write_byte_data(tlc59116->client, TLC59116_REG_GRPFREQ, gfrq);
-+
-+
-+#ifdef DUMP_REGS
-+ dump_regs(tlc59116->client);
-+#endif
-+
-+ spin_unlock(&tlc59116->lock);
-+ return 0;
-+}
-+
-+static int tlc59116_probe(struct i2c_client *client,
-+ const struct i2c_device_id *id)
-+{
-+ struct tlc59116_led *tlc59116;
-+ struct tlc59116_chipdef *chip;
-+ struct i2c_adapter *adapter;
-+ struct led_platform_data *pdata;
-+ int i, err;
-+
-+ chip = &tlc59116_chipdefs[id->driver_data];
-+ adapter = to_i2c_adapter(client->dev.parent);
-+ pdata = client->dev.platform_data;
-+
-+ /* Make sure the slave address / chip type combo given is possible */
-+ if ((client->addr & ~((1 << chip->slv_addr_shift) - 1)) !=
-+ chip->slv_addr) {
-+ dev_err(&client->dev, "invalid slave address %02x\n",
-+ client->addr);
-+ return -ENODEV;
-+ }
-+
-+ printk(KERN_INFO "leds-tlc59116: Using %s %d-bit LED driver at "
-+ "slave address 0x%02x\n",
-+ id->name, chip->bits, client->addr);
-+
-+ if (!i2c_check_functionality(adapter, I2C_FUNC_I2C))
-+ return -EIO;
-+
-+ if (pdata) {
-+ if (pdata->num_leds != chip->bits) {
-+ dev_err(&client->dev, "board info claims %d LEDs"
-+ " on a %d-bit chip\n",
-+ pdata->num_leds, chip->bits);
-+ return -ENODEV;
-+ }
-+ }
-+
-+ tlc59116 = devm_kzalloc(&client->dev, sizeof(*tlc59116) * chip->bits, GFP_KERNEL);
-+ if (!tlc59116)
-+ return -ENOMEM;
-+
-+ i2c_set_clientdata(client, tlc59116);
-+
-+ for (i = 0; i < chip->bits; i++) {
-+ tlc59116[i].chipdef = chip;
-+ tlc59116[i].client = client;
-+ tlc59116[i].led_num = i;
-+
-+ /* Platform data can specify LED names and default triggers */
-+ if (pdata) {
-+ if (pdata->leds[i].name)
-+ snprintf(tlc59116[i].name,
-+ sizeof(tlc59116[i].name), "tlc59116:%s",
-+ pdata->leds[i].name);
-+ if (pdata->leds[i].default_trigger)
-+ tlc59116[i].led_cdev.default_trigger =
-+ pdata->leds[i].default_trigger;
-+ } else {
-+ snprintf(tlc59116[i].name, sizeof(tlc59116[i].name),
-+ "tlc59116:%d", i);
-+ }
-+
-+ spin_lock_init(&tlc59116[i].lock);
-+
-+ tlc59116[i].led_cdev.name = tlc59116[i].name;
-+ tlc59116[i].led_cdev.brightness_set = tlc59116_led_set;
-+ tlc59116[i].led_cdev.blink_set = tlc59116_set_blink;
-+ tlc59116[i].led_cdev.brightness = 0;
-+
-+ INIT_WORK(&tlc59116[i].work, tlc59116_led_work);
-+
-+ err = led_classdev_register(&client->dev, &tlc59116[i].led_cdev);
-+ if (err < 0)
-+ goto exit;
-+ }
-+
-+ tlc59116_set_mode(client, MODE2_DIM);
-+
-+ /* Turn off LEDs */
-+ for (i = 0; i < chip->bits; i++)
-+ tlc59116_set_gpio(client, i, TLC59116_LED_OFF);
-+
-+ return 0;
-+
-+exit:
-+ while (i--) {
-+ led_classdev_unregister(&tlc59116[i].led_cdev);
-+ cancel_work_sync(&tlc59116[i].work);
-+ }
-+
-+ devm_kfree(&client->dev, tlc59116);
-+ i2c_set_clientdata(client, NULL);
-+
-+ return err;
-+}
-+
-+static int tlc59116_remove(struct i2c_client *client)
-+{
-+ struct tlc59116_led *tlc59116 = i2c_get_clientdata(client);
-+ int i;
-+
-+ for (i = 0; i < tlc59116->chipdef->bits; i++) {
-+ led_classdev_unregister(&tlc59116[i].led_cdev);
-+ cancel_work_sync(&tlc59116[i].work);
-+ }
-+
-+ devm_kfree(&client->dev, tlc59116);
-+ i2c_set_clientdata(client, NULL);
-+
-+ return 0;
-+}
-+
-+static struct i2c_driver tlc59116_driver = {
-+ .driver = {
-+ .name = "leds-tlc59116",
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = tlc59116_probe,
-+ .remove = tlc59116_remove,
-+ .id_table = tlc59116_id,
-+};
-+
-+module_i2c_driver(tlc59116_driver);
-+
-+MODULE_AUTHOR("Belkin Inc.");
-+MODULE_DESCRIPTION("TLC59116 LED driver");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From 67a9ad9b8a6f6ea76ef8fc484ae49970d72d5534 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Wed, 14 May 2014 14:58:06 -0300
-Subject: mtd: nand: Warn the user if the selected ECC strength is too weak
-
-This commit makes use of the chip->ecc_strength_ds and chip->ecc_step_ds which
-contain the datasheet minimum requested ECC strength to produce a noisy warning
-if the configured ECC strength is weaker.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-
---- a/drivers/mtd/nand/nand_base.c
-+++ b/drivers/mtd/nand/nand_base.c
-@@ -3682,6 +3682,39 @@ int nand_scan_ident(struct mtd_info *mtd
- }
- EXPORT_SYMBOL(nand_scan_ident);
-
-+/*
-+ * Check if the chip configuration meet the datasheet requirements.
-+
-+ * If our configuration corrects A bits per B bytes and the minimum
-+ * required correction level is X bits per Y bytes, then we must ensure
-+ * both of the following are true:
-+ *
-+ * (1) A / B >= X / Y
-+ * (2) A >= X
-+ *
-+ * Requirement (1) ensures we can correct for the required bitflip density.
-+ * Requirement (2) ensures we can correct even when all bitflips are clumped
-+ * in the same sector.
-+ */
-+static bool nand_ecc_strength_good(struct mtd_info *mtd)
-+{
-+ struct nand_chip *chip = mtd->priv;
-+ struct nand_ecc_ctrl *ecc = &chip->ecc;
-+ int corr, ds_corr;
-+
-+ if (ecc->size == 0 || chip->ecc_step_ds == 0)
-+ /* Not enough information */
-+ return true;
-+
-+ /*
-+ * We get the number of corrected bits per page to compare
-+ * the correction density.
-+ */
-+ corr = (mtd->writesize * ecc->strength) / ecc->size;
-+ ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
-+
-+ return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
-+}
-
- /**
- * nand_scan_tail - [NAND Interface] Scan for the NAND device
-@@ -3891,6 +3924,9 @@ int nand_scan_tail(struct mtd_info *mtd)
- ecc->layout->oobavail += ecc->layout->oobfree[i].length;
- mtd->oobavail = ecc->layout->oobavail;
-
-+ /* ECC sanity check: warn noisily if it's too weak */
-+ WARN_ON(!nand_ecc_strength_good(mtd));
-+
- /*
- * Set the number of read / write steps for one page depending on ECC
- * mode.
+++ /dev/null
-From 6d9434ebb76157071164b32ad03fbed165c74382 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 24 Feb 2014 19:24:48 -0300
-Subject: of_mtd: Add helpers to get ECC strength and ECC step size
-
-This commit adds simple helpers to obtain the devicetree properties
-that specify the ECC strength and ECC step size to use on a given
-NAND controller.
-
-Acked-by: Boris BREZILLON <b.brezillon.dev@gmail.com>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-
---- a/drivers/of/of_mtd.c
-+++ b/drivers/of/of_mtd.c
-@@ -50,6 +50,40 @@ int of_get_nand_ecc_mode(struct device_n
- EXPORT_SYMBOL_GPL(of_get_nand_ecc_mode);
-
- /**
-+ * of_get_nand_ecc_step_size - Get ECC step size associated to
-+ * the required ECC strength (see below).
-+ * @np: Pointer to the given device_node
-+ *
-+ * return the ECC step size, or errno in error case.
-+ */
-+int of_get_nand_ecc_step_size(struct device_node *np)
-+{
-+ int ret;
-+ u32 val;
-+
-+ ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
-+ return ret ? ret : val;
-+}
-+EXPORT_SYMBOL_GPL(of_get_nand_ecc_step_size);
-+
-+/**
-+ * of_get_nand_ecc_strength - Get required ECC strength over the
-+ * correspnding step size as defined by 'nand-ecc-size'
-+ * @np: Pointer to the given device_node
-+ *
-+ * return the ECC strength, or errno in error case.
-+ */
-+int of_get_nand_ecc_strength(struct device_node *np)
-+{
-+ int ret;
-+ u32 val;
-+
-+ ret = of_property_read_u32(np, "nand-ecc-strength", &val);
-+ return ret ? ret : val;
-+}
-+EXPORT_SYMBOL_GPL(of_get_nand_ecc_strength);
-+
-+/**
- * of_get_nand_bus_width - Get nand bus witdh for given device_node
- * @np: Pointer to the given device_node
- *
---- a/include/linux/of_mtd.h
-+++ b/include/linux/of_mtd.h
-@@ -13,6 +13,8 @@
-
- #include <linux/of.h>
- int of_get_nand_ecc_mode(struct device_node *np);
-+int of_get_nand_ecc_step_size(struct device_node *np);
-+int of_get_nand_ecc_strength(struct device_node *np);
- int of_get_nand_bus_width(struct device_node *np);
- bool of_get_nand_on_flash_bbt(struct device_node *np);
-
-@@ -22,6 +24,16 @@ static inline int of_get_nand_ecc_mode(s
- {
- return -ENOSYS;
- }
-+
-+static inline int of_get_nand_ecc_step_size(struct device_node *np)
-+{
-+ return -ENOSYS;
-+}
-+
-+static inline int of_get_nand_ecc_strength(struct device_node *np)
-+{
-+ return -ENOSYS;
-+}
-
- static inline int of_get_nand_bus_width(struct device_node *np)
- {
+++ /dev/null
-From e634ce51baa52c131e4a35c01bba9e596a0eb86d Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Thu, 27 Feb 2014 14:13:26 -0300
-Subject: mtd: nand: pxa3xx: Print actual ECC strength in error message
-
-The actual ECC strength used to select the ECC scheme is 'ecc_strength'.
-Use it in the error message.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1531,7 +1531,7 @@ KEEP_CONFIG:
- if (!ret) {
- dev_err(&info->pdev->dev,
- "ECC strength %d at page size %d is not supported\n",
-- chip->ecc_strength_ds, mtd->writesize);
-+ ecc_strength, mtd->writesize);
- return -ENODEV;
- }
-
+++ /dev/null
-From eee0166d8ead9d719d794df3e66acd8f83630e05 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Wed, 14 May 2014 14:58:07 -0300
-Subject: mtd: nand: pxa3xx: Clean pxa_ecc_init() error handling
-
-Let's make pxa_ecc_init() return a negative errno on error or zero
-if succesful, which is standard kernel practice. Also, report the
-selected ECC strength and step size, which is important information.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1355,7 +1355,6 @@ static int pxa_ecc_init(struct pxa3xx_na
- ecc->mode = NAND_ECC_HW;
- ecc->size = 512;
- ecc->strength = 1;
-- return 1;
-
- } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
- info->chunk_size = 512;
-@@ -1364,7 +1363,6 @@ static int pxa_ecc_init(struct pxa3xx_na
- ecc->mode = NAND_ECC_HW;
- ecc->size = 512;
- ecc->strength = 1;
-- return 1;
-
- /*
- * Required ECC: 4-bit correction per 512 bytes
-@@ -1379,7 +1377,6 @@ static int pxa_ecc_init(struct pxa3xx_na
- ecc->size = info->chunk_size;
- ecc->layout = &ecc_layout_2KB_bch4bit;
- ecc->strength = 16;
-- return 1;
-
- } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
- info->ecc_bch = 1;
-@@ -1390,7 +1387,6 @@ static int pxa_ecc_init(struct pxa3xx_na
- ecc->size = info->chunk_size;
- ecc->layout = &ecc_layout_4KB_bch4bit;
- ecc->strength = 16;
-- return 1;
-
- /*
- * Required ECC: 8-bit correction per 512 bytes
-@@ -1405,8 +1401,15 @@ static int pxa_ecc_init(struct pxa3xx_na
- ecc->size = info->chunk_size;
- ecc->layout = &ecc_layout_4KB_bch8bit;
- ecc->strength = 16;
-- return 1;
-+ } else {
-+ dev_err(&info->pdev->dev,
-+ "ECC strength %d at page size %d is not supported\n",
-+ strength, page_size);
-+ return -ENODEV;
- }
-+
-+ dev_info(&info->pdev->dev, "ECC strength %d, ECC step size %d\n",
-+ ecc->strength, ecc->size);
- return 0;
- }
-
-@@ -1528,12 +1531,8 @@ KEEP_CONFIG:
-
- ret = pxa_ecc_init(info, &chip->ecc, ecc_strength,
- ecc_step, mtd->writesize);
-- if (!ret) {
-- dev_err(&info->pdev->dev,
-- "ECC strength %d at page size %d is not supported\n",
-- ecc_strength, mtd->writesize);
-- return -ENODEV;
-- }
-+ if (ret)
-+ return ret;
-
- /* calculate addressing information */
- if (mtd->writesize >= 2048)
+++ /dev/null
-From 5b3e507820c6e120bc2680c0d35f9d9d81fcb98d Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Wed, 14 May 2014 14:58:08 -0300
-Subject: mtd: nand: pxa3xx: Use ECC strength and step size devicetree binding
-
-This commit adds support for the user to specify the ECC strength
-and step size through the devicetree. We keep the previous behavior,
-when there is no DT parameter provided.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -1520,8 +1520,13 @@ KEEP_CONFIG:
- }
- }
-
-- ecc_strength = chip->ecc_strength_ds;
-- ecc_step = chip->ecc_step_ds;
-+ if (pdata->ecc_strength && pdata->ecc_step_size) {
-+ ecc_strength = pdata->ecc_strength;
-+ ecc_step = pdata->ecc_step_size;
-+ } else {
-+ ecc_strength = chip->ecc_strength_ds;
-+ ecc_step = chip->ecc_step_ds;
-+ }
-
- /* Set default ECC strength requirements on non-ONFI devices */
- if (ecc_strength < 1 && ecc_step < 1) {
-@@ -1730,6 +1735,14 @@ static int pxa3xx_nand_probe_dt(struct p
- of_property_read_u32(np, "num-cs", &pdata->num_cs);
- pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
-
-+ pdata->ecc_strength = of_get_nand_ecc_strength(np);
-+ if (pdata->ecc_strength < 0)
-+ pdata->ecc_strength = 0;
-+
-+ pdata->ecc_step_size = of_get_nand_ecc_step_size(np);
-+ if (pdata->ecc_step_size < 0)
-+ pdata->ecc_step_size = 0;
-+
- pdev->dev.platform_data = pdata;
-
- return 0;
---- a/include/linux/platform_data/mtd-nand-pxa3xx.h
-+++ b/include/linux/platform_data/mtd-nand-pxa3xx.h
-@@ -58,6 +58,9 @@ struct pxa3xx_nand_platform_data {
- /* use an flash-based bad block table */
- bool flash_bbt;
-
-+ /* requested ECC strength and ECC step size */
-+ int ecc_strength, ecc_step_size;
-+
- const struct mtd_partition *parts[NUM_CHIP_SELECT];
- unsigned int nr_parts[NUM_CHIP_SELECT];
-
+++ /dev/null
-From 9b744942290c168287013f0a19ff7392f65c8107 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 16 May 2014 16:14:03 +0200
-Subject: net: phy: decouple PHY id and PHY address in fixed PHY driver
-
-Until now, the fixed_phy_add() function was taking as argument
-'phy_id', which was used both as the PHY address on the fake fixed
-MDIO bus, and as the PHY id, as available in the MII_PHYSID1 and
-MII_PHYSID2 registers. However, those two informations are completely
-unrelated.
-
-This patch decouples them. The PHY id of fixed PHYs is hardcoded to be
-0x0. Ideally, a really reserved value would be nicer, but there
-doesn't seem to be an easy of making sure a dummy value can be
-assigned to the Linux kernel for such usage.
-
-The PHY address remains passed by the caller of phy_fixed_add().
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-Tested-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
-
---- a/drivers/net/phy/fixed.c
-+++ b/drivers/net/phy/fixed.c
-@@ -31,7 +31,7 @@ struct fixed_mdio_bus {
- };
-
- struct fixed_phy {
-- int id;
-+ int addr;
- u16 regs[MII_REGS_NUM];
- struct phy_device *phydev;
- struct fixed_phy_status status;
-@@ -104,8 +104,8 @@ static int fixed_phy_update_regs(struct
- if (fp->status.asym_pause)
- lpa |= LPA_PAUSE_ASYM;
-
-- fp->regs[MII_PHYSID1] = fp->id >> 16;
-- fp->regs[MII_PHYSID2] = fp->id;
-+ fp->regs[MII_PHYSID1] = 0;
-+ fp->regs[MII_PHYSID2] = 0;
-
- fp->regs[MII_BMSR] = bmsr;
- fp->regs[MII_BMCR] = bmcr;
-@@ -115,7 +115,7 @@ static int fixed_phy_update_regs(struct
- return 0;
- }
-
--static int fixed_mdio_read(struct mii_bus *bus, int phy_id, int reg_num)
-+static int fixed_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num)
- {
- struct fixed_mdio_bus *fmb = bus->priv;
- struct fixed_phy *fp;
-@@ -124,7 +124,7 @@ static int fixed_mdio_read(struct mii_bu
- return -1;
-
- list_for_each_entry(fp, &fmb->phys, node) {
-- if (fp->id == phy_id) {
-+ if (fp->addr == phy_addr) {
- /* Issue callback if user registered it. */
- if (fp->link_update) {
- fp->link_update(fp->phydev->attached_dev,
-@@ -138,7 +138,7 @@ static int fixed_mdio_read(struct mii_bu
- return 0xFFFF;
- }
-
--static int fixed_mdio_write(struct mii_bus *bus, int phy_id, int reg_num,
-+static int fixed_mdio_write(struct mii_bus *bus, int phy_addr, int reg_num,
- u16 val)
- {
- return 0;
-@@ -160,7 +160,7 @@ int fixed_phy_set_link_update(struct phy
- return -EINVAL;
-
- list_for_each_entry(fp, &fmb->phys, node) {
-- if (fp->id == phydev->phy_id) {
-+ if (fp->addr == phydev->addr) {
- fp->link_update = link_update;
- fp->phydev = phydev;
- return 0;
-@@ -171,7 +171,7 @@ int fixed_phy_set_link_update(struct phy
- }
- EXPORT_SYMBOL_GPL(fixed_phy_set_link_update);
-
--int fixed_phy_add(unsigned int irq, int phy_id,
-+int fixed_phy_add(unsigned int irq, int phy_addr,
- struct fixed_phy_status *status)
- {
- int ret;
-@@ -184,9 +184,9 @@ int fixed_phy_add(unsigned int irq, int
-
- memset(fp->regs, 0xFF, sizeof(fp->regs[0]) * MII_REGS_NUM);
-
-- fmb->irqs[phy_id] = irq;
-+ fmb->irqs[phy_addr] = irq;
-
-- fp->id = phy_id;
-+ fp->addr = phy_addr;
- fp->status = *status;
-
- ret = fixed_phy_update_regs(fp);
+++ /dev/null
-From a75951217472c522c324adb0a4de3ba69d656ef5 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 16 May 2014 16:14:04 +0200
-Subject: net: phy: extend fixed driver with fixed_phy_register()
-
-The existing fixed_phy_add() function has several drawbacks that
-prevents it from being used as is for OF-based declaration of fixed
-PHYs:
-
- * The address of the PHY on the fake bus needs to be passed, while a
- dynamic allocation is desired.
-
- * Since the phy_device instantiation is post-poned until the next
- mdiobus scan, there is no way to associate the fixed PHY with its
- OF node, which later prevents of_phy_connect() from finding this
- fixed PHY from a given OF node.
-
-To solve this, this commit introduces fixed_phy_register(), which will
-allocate an available PHY address, add the PHY using fixed_phy_add()
-and instantiate the phy_device structure associated with the provided
-OF node.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Acked-by: Grant Likely <grant.likely@linaro.org>
-Tested-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
-
---- a/drivers/net/phy/fixed.c
-+++ b/drivers/net/phy/fixed.c
-@@ -21,6 +21,7 @@
- #include <linux/phy_fixed.h>
- #include <linux/err.h>
- #include <linux/slab.h>
-+#include <linux/of.h>
-
- #define MII_REGS_NUM 29
-
-@@ -203,6 +204,66 @@ err_regs:
- }
- EXPORT_SYMBOL_GPL(fixed_phy_add);
-
-+void fixed_phy_del(int phy_addr)
-+{
-+ struct fixed_mdio_bus *fmb = &platform_fmb;
-+ struct fixed_phy *fp, *tmp;
-+
-+ list_for_each_entry_safe(fp, tmp, &fmb->phys, node) {
-+ if (fp->addr == phy_addr) {
-+ list_del(&fp->node);
-+ kfree(fp);
-+ return;
-+ }
-+ }
-+}
-+EXPORT_SYMBOL_GPL(fixed_phy_del);
-+
-+static int phy_fixed_addr;
-+static DEFINE_SPINLOCK(phy_fixed_addr_lock);
-+
-+int fixed_phy_register(unsigned int irq,
-+ struct fixed_phy_status *status,
-+ struct device_node *np)
-+{
-+ struct fixed_mdio_bus *fmb = &platform_fmb;
-+ struct phy_device *phy;
-+ int phy_addr;
-+ int ret;
-+
-+ /* Get the next available PHY address, up to PHY_MAX_ADDR */
-+ spin_lock(&phy_fixed_addr_lock);
-+ if (phy_fixed_addr == PHY_MAX_ADDR) {
-+ spin_unlock(&phy_fixed_addr_lock);
-+ return -ENOSPC;
-+ }
-+ phy_addr = phy_fixed_addr++;
-+ spin_unlock(&phy_fixed_addr_lock);
-+
-+ ret = fixed_phy_add(PHY_POLL, phy_addr, status);
-+ if (ret < 0)
-+ return ret;
-+
-+ phy = get_phy_device(fmb->mii_bus, phy_addr, false);
-+ if (!phy || IS_ERR(phy)) {
-+ fixed_phy_del(phy_addr);
-+ return -EINVAL;
-+ }
-+
-+ of_node_get(np);
-+ phy->dev.of_node = np;
-+
-+ ret = phy_device_register(phy);
-+ if (ret) {
-+ phy_device_free(phy);
-+ of_node_put(np);
-+ fixed_phy_del(phy_addr);
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
- static int __init fixed_mdio_bus_init(void)
- {
- struct fixed_mdio_bus *fmb = &platform_fmb;
---- a/include/linux/phy_fixed.h
-+++ b/include/linux/phy_fixed.h
-@@ -9,15 +9,26 @@ struct fixed_phy_status {
- int asym_pause;
- };
-
-+struct device_node;
-+
- #ifdef CONFIG_FIXED_PHY
- extern int fixed_phy_add(unsigned int irq, int phy_id,
- struct fixed_phy_status *status);
-+extern int fixed_phy_register(unsigned int irq,
-+ struct fixed_phy_status *status,
-+ struct device_node *np);
- #else
- static inline int fixed_phy_add(unsigned int irq, int phy_id,
- struct fixed_phy_status *status)
- {
- return -ENODEV;
- }
-+static inline int fixed_phy_register(unsigned int irq,
-+ struct fixed_phy_status *status,
-+ struct device_node *np)
-+{
-+ return -ENODEV;
-+}
- #endif /* CONFIG_FIXED_PHY */
-
- /*
+++ /dev/null
-From 3be2a49e5c08d268f8af0dd4fe89a24ea8cdc339 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 16 May 2014 16:14:05 +0200
-Subject: of: provide a binding for fixed link PHYs
-
-Some Ethernet MACs have a "fixed link", and are not connected to a
-normal MDIO-managed PHY device. For those situations, a Device Tree
-binding allows to describe a "fixed link" using a special PHY node.
-
-This patch adds:
-
- * A documentation for the fixed PHY Device Tree binding.
-
- * An of_phy_is_fixed_link() function that an Ethernet driver can call
- on its PHY phandle to find out whether it's a fixed link PHY or
- not. It should typically be used to know if
- of_phy_register_fixed_link() should be called.
-
- * An of_phy_register_fixed_link() function that instantiates the
- fixed PHY into the PHY subsystem, so that when the driver calls
- of_phy_connect(), the PHY device associated to the OF node will be
- found.
-
-These two additional functions also support the old fixed-link Device
-Tree binding used on PowerPC platforms, so that ultimately, the
-network device drivers for those platforms could be converted to use
-of_phy_is_fixed_link() and of_phy_register_fixed_link() instead of
-of_phy_connect_fixed_link(), while keeping compatibility with their
-respective Device Tree bindings.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-Tested-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/net/fixed-link.txt
-@@ -0,0 +1,30 @@
-+Fixed link Device Tree binding
-+------------------------------
-+
-+Some Ethernet MACs have a "fixed link", and are not connected to a
-+normal MDIO-managed PHY device. For those situations, a Device Tree
-+binding allows to describe a "fixed link".
-+
-+Such a fixed link situation is described by creating a 'fixed-link'
-+sub-node of the Ethernet MAC device node, with the following
-+properties:
-+
-+* 'speed' (integer, mandatory), to indicate the link speed. Accepted
-+ values are 10, 100 and 1000
-+* 'full-duplex' (boolean, optional), to indicate that full duplex is
-+ used. When absent, half duplex is assumed.
-+* 'pause' (boolean, optional), to indicate that pause should be
-+ enabled.
-+* 'asym-pause' (boolean, optional), to indicate that asym_pause should
-+ be enabled.
-+
-+Example:
-+
-+ethernet@0 {
-+ ...
-+ fixed-link {
-+ speed = <1000>;
-+ full-duplex;
-+ };
-+ ...
-+};
---- a/drivers/of/of_mdio.c
-+++ b/drivers/of/of_mdio.c
-@@ -14,6 +14,7 @@
- #include <linux/netdevice.h>
- #include <linux/err.h>
- #include <linux/phy.h>
-+#include <linux/phy_fixed.h>
- #include <linux/of.h>
- #include <linux/of_irq.h>
- #include <linux/of_mdio.h>
-@@ -280,3 +281,69 @@ struct phy_device *of_phy_attach(struct
- return phy_attach_direct(dev, phy, flags, iface) ? NULL : phy;
- }
- EXPORT_SYMBOL(of_phy_attach);
-+
-+#if defined(CONFIG_FIXED_PHY)
-+/*
-+ * of_phy_is_fixed_link() and of_phy_register_fixed_link() must
-+ * support two DT bindings:
-+ * - the old DT binding, where 'fixed-link' was a property with 5
-+ * cells encoding various informations about the fixed PHY
-+ * - the new DT binding, where 'fixed-link' is a sub-node of the
-+ * Ethernet device.
-+ */
-+bool of_phy_is_fixed_link(struct device_node *np)
-+{
-+ struct device_node *dn;
-+ int len;
-+
-+ /* New binding */
-+ dn = of_get_child_by_name(np, "fixed-link");
-+ if (dn) {
-+ of_node_put(dn);
-+ return true;
-+ }
-+
-+ /* Old binding */
-+ if (of_get_property(np, "fixed-link", &len) &&
-+ len == (5 * sizeof(__be32)))
-+ return true;
-+
-+ return false;
-+}
-+EXPORT_SYMBOL(of_phy_is_fixed_link);
-+
-+int of_phy_register_fixed_link(struct device_node *np)
-+{
-+ struct fixed_phy_status status = {};
-+ struct device_node *fixed_link_node;
-+ const __be32 *fixed_link_prop;
-+ int len;
-+
-+ /* New binding */
-+ fixed_link_node = of_get_child_by_name(np, "fixed-link");
-+ if (fixed_link_node) {
-+ status.link = 1;
-+ status.duplex = of_property_read_bool(np, "full-duplex");
-+ if (of_property_read_u32(fixed_link_node, "speed", &status.speed))
-+ return -EINVAL;
-+ status.pause = of_property_read_bool(np, "pause");
-+ status.asym_pause = of_property_read_bool(np, "asym-pause");
-+ of_node_put(fixed_link_node);
-+ return fixed_phy_register(PHY_POLL, &status, np);
-+ }
-+
-+ /* Old binding */
-+ fixed_link_prop = of_get_property(np, "fixed-link", &len);
-+ if (fixed_link_prop && len == (5 * sizeof(__be32))) {
-+ status.link = 1;
-+ status.duplex = be32_to_cpu(fixed_link_prop[1]);
-+ status.speed = be32_to_cpu(fixed_link_prop[2]);
-+ status.pause = be32_to_cpu(fixed_link_prop[3]);
-+ status.asym_pause = be32_to_cpu(fixed_link_prop[4]);
-+ return fixed_phy_register(PHY_POLL, &status, np);
-+ }
-+
-+ return -ENODEV;
-+}
-+EXPORT_SYMBOL(of_phy_register_fixed_link);
-+#endif
---- a/include/linux/of_mdio.h
-+++ b/include/linux/of_mdio.h
-@@ -67,4 +67,19 @@ static inline struct mii_bus *of_mdio_fi
- }
- #endif /* CONFIG_OF */
-
-+#if defined(CONFIG_OF) && defined(CONFIG_FIXED_PHY)
-+extern int of_phy_register_fixed_link(struct device_node *np);
-+extern bool of_phy_is_fixed_link(struct device_node *np);
-+#else
-+static inline int of_phy_register_fixed_link(struct device_node *np)
-+{
-+ return -ENOSYS;
-+}
-+static inline bool of_phy_is_fixed_link(struct device_node *np)
-+{
-+ return false;
-+}
-+#endif
-+
-+
- #endif /* __LINUX_OF_MDIO_H */
+++ /dev/null
-From 83895bedeee6fbf56d887af4280bf9edcc80da60 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 16 May 2014 16:14:06 +0200
-Subject: net: mvneta: add support for fixed links
-
-Following the introduction of of_phy_register_fixed_link(), this patch
-introduces fixed link support in the mvneta driver, for Marvell Armada
-370/XP SOCs.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
-
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -2808,9 +2808,22 @@ static int mvneta_probe(struct platform_
-
- phy_node = of_parse_phandle(dn, "phy", 0);
- if (!phy_node) {
-- dev_err(&pdev->dev, "no associated PHY\n");
-- err = -ENODEV;
-- goto err_free_irq;
-+ if (!of_phy_is_fixed_link(dn)) {
-+ dev_err(&pdev->dev, "no PHY specified\n");
-+ err = -ENODEV;
-+ goto err_free_irq;
-+ }
-+
-+ err = of_phy_register_fixed_link(dn);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "cannot register fixed PHY\n");
-+ goto err_free_irq;
-+ }
-+
-+ /* In the case of a fixed PHY, the DT node associated
-+ * to the PHY is the Ethernet MAC DT node.
-+ */
-+ phy_node = dn;
- }
-
- phy_mode = of_get_phy_mode(dn);
+++ /dev/null
-The WRT1900AC among other Linksys routers uses a dual-firmware layout.
-The bootloader passes the active rootfs in bootargs and also sets the
-rootfstype to jffs2 - which is clearly something we don't want.
-
-Rename both root= and rootfstype= variables to avoid issues and also
-use the former to dynamically rename the active partition to "ubi".
-
-
-Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
-
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -64,6 +64,18 @@ static uint32_t get_cell_size(const void
- return cell_size;
- }
-
-+static void mangle_bootargs(void *fdt, const char *fdt_cmdline)
-+{
-+ char *rootdev;
-+ char *rootfs;
-+
-+ rootdev = strstr(fdt_cmdline, "root=/dev/mtdblock");
-+ strncpy(rootdev, "uboot_active_root=", 18);
-+
-+ rootfs = strstr(fdt_cmdline, "rootfstype");
-+ strncpy(rootfs, "origfstype", 10);
-+}
-+
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
- char cmdline[COMMAND_LINE_SIZE];
-@@ -133,6 +145,9 @@ int atags_to_fdt(void *atag_list, void *
-
- for_each_tag(atag, atag_list) {
- if (atag->hdr.tag == ATAG_CMDLINE) {
-+ /* Rename the original root= and rootfstype= options */
-+ mangle_bootargs(fdt,
-+ atag->u.cmdline.cmdline);
- /* Append the ATAGS command line to the device tree
- * command line.
- * NB: This means that if the same parameter is set in
---- a/arch/arm/boot/compressed/string.c
-+++ b/arch/arm/boot/compressed/string.c
-@@ -111,6 +111,53 @@ char *strchr(const char *s, int c)
- return (char *)s;
- }
-
-+/**
-+ * strncpy - Copy a length-limited, %NUL-terminated string
-+ * @dest: Where to copy the string to
-+ * @src: Where to copy the string from
-+ * @count: The maximum number of bytes to copy
-+ *
-+ * The result is not %NUL-terminated if the source exceeds
-+ * @count bytes.
-+ *
-+ * In the case where the length of @src is less than that of
-+ * count, the remainder of @dest will be padded with %NUL.
-+ *
-+ */
-+char *strncpy(char *dest, const char *src, size_t count)
-+{
-+ char *tmp = dest;
-+
-+ while (count) {
-+ if ((*tmp = *src) != 0)
-+ src++;
-+ tmp++;
-+ count--;
-+ }
-+ return dest;
-+}
-+
-+/**
-+ * strstr - Find the first substring in a %NUL terminated string
-+ * @s1: The string to be searched
-+ * @s2: The string to search for
-+ */
-+char *strstr(const char *s1, const char *s2)
-+{
-+ size_t l1, l2;
-+
-+ l2 = strlen(s2);
-+ if (!l2)
-+ return (char *)s1;
-+ l1 = strlen(s1);
-+ while (l1 >= l2) {
-+ l1--;
-+ if (!memcmp(s1, s2, l2))
-+ return (char *)s1;
-+ s1++;
-+ }
-+ return NULL;
-+}
- #undef memset
-
- void *memset(void *s, int c, size_t count)
---- a/drivers/mtd/ofpart.c
-+++ b/drivers/mtd/ofpart.c
-@@ -25,12 +25,15 @@ static bool node_has_compatible(struct d
- return of_get_property(pp, "compatible", NULL);
- }
-
-+static int uboot_active_root;
-+
- static int parse_ofpart_partitions(struct mtd_info *master,
- struct mtd_partition **pparts,
- struct mtd_part_parser_data *data)
- {
- struct device_node *node;
- const char *partname;
-+ const char *owrtpart = "ubi";
- struct device_node *pp;
- int nr_parts, i;
-
-@@ -78,9 +81,15 @@ static int parse_ofpart_partitions(struc
- (*pparts)[i].offset = of_read_number(reg, a_cells);
- (*pparts)[i].size = of_read_number(reg + a_cells, s_cells);
-
-- partname = of_get_property(pp, "label", &len);
-- if (!partname)
-- partname = of_get_property(pp, "name", &len);
-+ if (uboot_active_root && (i == uboot_active_root)) {
-+ partname = owrtpart;
-+ } else {
-+ partname = of_get_property(pp, "label", &len);
-+
-+ if (!partname)
-+ partname = of_get_property(pp, "name", &len);
-+ }
-+
- (*pparts)[i].name = partname;
-
- if (of_get_property(pp, "read-only", &len))
-@@ -178,6 +187,18 @@ static int __init ofpart_parser_init(voi
- return 0;
- }
-
-+static int __init active_root(char *str)
-+{
-+ get_option(&str, &uboot_active_root);
-+
-+ if (!uboot_active_root)
-+ return 1;
-+
-+ return 1;
-+}
-+
-+__setup("uboot_active_root=", active_root);
-+
- static void __exit ofpart_parser_exit(void)
- {
- deregister_mtd_parser(&ofpart_parser);
+++ /dev/null
-#
-# Copyright (C) 2013-2014 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Generic
- NAME:=Generic (default)
- PACKAGES:= \
- kmod-usb2 kmod-usb3 kmod-usb-storage \
- kmod-of-i2c kmod-i2c-core kmod-i2c-mv64xxx \
- kmod-ata-core kmod-ata-marvell-sata \
- kmod-rtc-marvell kmod-thermal-armada \
- kmod-gpio-button-hotplug kmod-hwmon-tmp421 \
- kmod-hwmon-gpiofan kmod-leds-tlc59116 \
- kmod-ledtrig-usbdev
-endef
-
-define Profile/Generic/Description
- Package set compatible with most supported Marvell Armada 370/XP based boards.
-endef
-
-$(eval $(call Profile,Generic))
+++ /dev/null
-#
-# Copyright (C) 2013-2014 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Evalboards
- NAME:=Evaluation / Development boards
- PACKAGES:= \
- kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \
- kmod-of-i2c kmod-i2c-core kmod-i2c-mv64xxx \
- kmod-ata-core kmod-ata-marvell-sata \
- kmod-rtc-marvell kmod-thermal-armada
-endef
-
-define Profile/Evalboards/Description
- Package set compatible with most Marvell Armada 370/XP development based boards.
-endef
-
-$(eval $(call Profile,Evalboards))
+++ /dev/null
-#
-# Copyright (C) 2013-2014 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=mxs
-BOARDNAME:=Freescale i.MX23/i.MX28 series
-FEATURES:=ext4 rtc usb gpio
-CPU_TYPE:=arm926ej-s
-
-MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
-LINUX_VERSION:=3.13.7
-KERNELNAME:="zImage dtbs"
-
-define Target/Description
- Support for Freescale i.MX23/i.MX28 boards
-endef
-
-include $(INCLUDE_DIR)/target.mk
-
-DEFAULT_PACKAGES += kmod-wdt-stmp3xxx
-
-$(eval $(call BuildTarget))
+++ /dev/null
-#!/bin/sh
-# Copyright (C) 2013 OpenWrt.org
-
-. /lib/functions/leds.sh
-. /lib/mxs.sh
-
-get_status_led() {
- case $(mxs_board_name) in
- duckbill)
- status_led="duckbill:green:status"
- ;;
- olinuxino)
- status_led="green"
- ;;
- *)
- status_led=$(cd /sys/class/leds && ls -1 *:status 2> /dev/null | head -n 1)
- ;;
- esac
-}
-
-set_state() {
- get_status_led
-
- case "$1" in
- preinit)
- status_led_blink_preinit
- ;;
- failsafe)
- status_led_blink_failsafe
- ;;
- done)
- status_led_on
- ;;
- esac
-}
+++ /dev/null
-::sysinit:/etc/init.d/rcS S boot
-::shutdown:/etc/init.d/rcS K shutdown
-ttyAMA0::askfirst:/bin/ash --login
+++ /dev/null
-#!/bin/sh
-# Copyright (C) 2013 OpenWrt.org
-
-[ -e /etc/config/network ] && exit 0
-
-touch /etc/config/network
-
-. /lib/functions/uci-defaults.sh
-. /lib/mxs.sh
-
-ucidef_set_interface_loopback
-
-board=$(mxs_board_name)
-
-case "$board" in
-*)
- ucidef_set_interface_lan 'eth0'
- ;;
-esac
-
-uci commit network
-
-exit 0
+++ /dev/null
-#!/bin/sh
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-
-MXS_BOARD_NAME=
-MXS_MODEL=
-
-mxs_board_detect() {
- local machine
- local name
-
- machine=$(cat /proc/device-tree/model)
-
- case "$machine" in
- *"I2SE Duckbill"*)
- name="duckbill"
- ;;
- *"i.MX23 Olinuxino Low Cost Board")
- name="olinuxino"
- ;;
- esac
-
- [ -z "$name" ] && name="unknown"
-
- [ -z "$MXS_BOARD_NAME" ] && MXS_BOARD_NAME="$name"
- [ -z "$MXS_MODEL" ] && MXS_MODEL="$machine"
-
- [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/"
-
- echo "$MXS_BOARD_NAME" > /tmp/sysinfo/board_name
- echo "$MXS_MODEL" > /tmp/sysinfo/model
-}
-
-mxs_board_name() {
- local name
-
- [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name)
- [ -z "$name" ] && name="unknown"
-
- echo "$name"
-}
+++ /dev/null
-#!/bin/sh
-
-do_mxs() {
- . /lib/mxs.sh
-
- mxs_board_detect
-}
-
-boot_hook_add preinit_main do_mxs
+++ /dev/null
-# CONFIG_AD7303 is not set
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_AMBA_PL08X is not set
-# CONFIG_APDS9300 is not set
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_CPU_AUTO=y
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_MXS=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-# CONFIG_ARCH_NSPIRE is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-# CONFIG_ARCH_WM8505 is not set
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-# CONFIG_BMA180 is not set
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COREDUMP=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_ARM926T=y
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRC16=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_UART_PL01X is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DTC=y
-# CONFIG_DW_DMAC_CORE is not set
-CONFIG_EXT4_FS=y
-CONFIG_FEC=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MXS=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCA=y
-CONFIG_I2C_ALGOPCF=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_DEBUG_ALGO=y
-CONFIG_I2C_DEBUG_BUS=y
-CONFIG_I2C_DEBUG_CORE=y
-CONFIG_I2C_MUX=y
-# CONFIG_I2C_MUX_GPIO is not set
-# CONFIG_I2C_MUX_PCA9541 is not set
-# CONFIG_I2C_MUX_PCA954x is not set
-CONFIG_I2C_MUX_PINCTRL=y
-CONFIG_I2C_MXS=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-# CONFIG_IIO_INTERRUPT_TRIGGER is not set
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_PERIODIC_RTC_TRIGGER=y
-# CONFIG_IIO_ST_PRESS is not set
-CONFIG_IIO_SYSFS_TRIGGER=y
-CONFIG_IIO_TRIGGER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-CONFIG_JBD2=y
-CONFIG_KTIME_SCALAR=y
-# CONFIG_LEDS_REGULATOR is not set
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MCP320X is not set
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_MXS=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_PHYSMAP_OF is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MXS_DMA=y
-# CONFIG_MXS_LRADC is not set
-# CONFIG_NAU7802 is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-# CONFIG_NET_DMA is not set
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_NLS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX23=y
-CONFIG_PINCTRL_IMX28=y
-CONFIG_PINCTRL_MXS=y
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PL330_DMA is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_PPS=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_PTP_1588_CLOCK=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DEBUG=y
-# CONFIG_REGULATOR_DUMMY is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_RFKILL_REGULATOR is not set
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_STMP is not set
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_AMBA_PL010=y
-CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_MXS_AUART=y
-CONFIG_SERIAL_MXS_AUART_CONSOLE=y
-CONFIG_SMSC_PHY=y
-# CONFIG_SND_USB_HIFACE is not set
-CONFIG_SOC_BUS=y
-CONFIG_SOC_IMX23=y
-CONFIG_SOC_IMX28=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-# CONFIG_SPI_MXS is not set
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_STMP_DEVICE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_TMP006 is not set
-CONFIG_UID16=y
-# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-# CONFIG_USB_MXS_PHY is not set
-CONFIG_USB_OTG=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_USBNET=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-# CONFIG_ZBUD is not set
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_AMBA_PL08X is not set
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_CPU_AUTO=y
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_MXS=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-# CONFIG_ARCH_NSPIRE is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-# CONFIG_ARCH_WM8505 is not set
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COREDUMP=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_ARM926T=y
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRC16=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_UART_PL01X is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DTC=y
-# CONFIG_DW_DMAC_CORE is not set
-CONFIG_EXT4_FS=y
-CONFIG_FEC=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MXS=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCA=y
-CONFIG_I2C_ALGOPCF=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_DEBUG_ALGO=y
-CONFIG_I2C_DEBUG_BUS=y
-CONFIG_I2C_DEBUG_CORE=y
-CONFIG_I2C_MUX=y
-# CONFIG_I2C_MUX_GPIO is not set
-# CONFIG_I2C_MUX_PCA9541 is not set
-# CONFIG_I2C_MUX_PCA954x is not set
-CONFIG_I2C_MUX_PINCTRL=y
-CONFIG_I2C_MXS=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_PERIODIC_RTC_TRIGGER=y
-CONFIG_IIO_SYSFS_TRIGGER=y
-CONFIG_IIO_TRIGGER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IOMMU_HELPER=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-CONFIG_JBD2=y
-CONFIG_KTIME_SCALAR=y
-# CONFIG_LEDS_REGULATOR is not set
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_MXS=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_PHYSMAP_OF is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MXS_DMA=y
-# CONFIG_MXS_LRADC is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_NLS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX23=y
-CONFIG_PINCTRL_IMX28=y
-CONFIG_PINCTRL_MXS=y
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PL330_DMA is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_PPS=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_PTP_1588_CLOCK=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DEBUG=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_RFKILL_REGULATOR is not set
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_STMP is not set
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_AMBA_PL010=y
-CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_MXS_AUART=y
-CONFIG_SERIAL_MXS_AUART_CONSOLE=y
-CONFIG_SMSC_PHY=y
-CONFIG_SOC_BUS=y
-CONFIG_SOC_IMX23=y
-CONFIG_SOC_IMX28=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-# CONFIG_SPI_MXS is not set
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_STMP_DEVICE=y
-CONFIG_SWIOTLB=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_UID16=y
-# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-# CONFIG_USB_MXS_PHY is not set
-CONFIG_USB_OTG=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_USBNET=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-# CONFIG_ZBUD is not set
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-/*
- * Copyright (C) 2013 Michael Heimpold <mhei@heimpold.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx28.dtsi"
-
-/ {
- model = "I2SE Duckbill";
- compatible = "i2se,duckbill", "fsl,imx28";
-
- memory {
- reg = <0x40000000 0x08000000>;
- };
-
- apb@80000000 {
- apbh@80000000 {
- ssp0: ssp@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_8bit_pins_a
- &mmc0_cd_cfg &mmc0_sck_cfg>;
- bus-width = <8>;
- vmmc-supply = <®_3p3v>;
- status = "okay";
- };
-
- pinctrl@80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_a>;
-
- hog_pins_a: hog@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- 0x40d3 /* MX28_PAD_ENET0_RX_CLK__GPIO_4_13, PHY Reset */
- >;
- fsl,drive-strength = <0>;
- fsl,voltage = <1>;
- fsl,pull-up = <0>;
- };
-
- led_pins_a: led_gpio@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- 0x3043 /* MX28_PAD_AUART1_RX__GPIO_3_4 */
- 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
- >;
- fsl,drive-strength = <0>;
- fsl,voltage = <1>;
- fsl,pull-up = <0>;
- };
- };
- };
-
- apbx@80040000 {
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
- status = "okay";
- };
-
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb0: usb@80080000 {
- status = "okay";
- };
-
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>;
- phy-supply = <®_3p3v>;
- phy-reset-gpios = <&gpio4 13 0>;
- phy-reset-duration = <100>;
- status = "okay";
- };
- };
-
- regulators {
- compatible = "simple-bus";
-
- reg_3p3v: 3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_a>;
-
- status {
- label = "duckbill:green:status";
- gpios = <&gpio3 5 0>;
- };
-
- failure {
- label = "duckbill:red:status";
- gpios = <&gpio3 4 0>;
- };
- };
-};
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-BOARDS:= \
- imx23-olinuxino \
- imx28-duckbill
-
-define Image/BuildKernel/olinuxino-bootlet
- cat $(LINUX_DIR)/arch/arm/boot/zImage $(DTS_DIR)/imx23-olinuxino.dtb > $(STAGING_DIR)/zImage_dtb
- (cd $(STAGING_DIR); \
- $(STAGING_DIR)/../host/bin/elftosb -z -c ./linux_prebuilt.db -o linux.sb; \
- dd if=/dev/zero of=sd_mmc_bootstream.raw bs=512 count=4; \
- dd if=linux.sb of=$(BIN_DIR)/openwrt-imx23-sbImage ibs=512 seek=4; \
- )
-endef
-
-define Image/BuildKernel/mxs-uboot
- mkimage -A arm -O linux -T kernel -C none \
- -a 0x40008000 -e 0x40008000 \
- -n 'ARM OpenWrt Linux-$(LINUX_VERSION)' \
- -d $(KDIR)/zImage $(KDIR)/uImage
- cp $(KDIR)/uImage $(BIN_DIR)/$(IMG_PREFIX)-uImage
-endef
-
-define Image/BuildKernel
-
- ifeq ($(CONFIG_PACKAGE_imx-bootlets),y)
- $(call Image/BuildKernel/olinuxino-bootlet)
- endif
-
- ifeq ($(CONFIG_PACKAGE_uboot-mxs-mx23_olinuxino),y)
- $(call Image/BuildKernel/mxs-uboot)
- endif
-
- $(CP) $(LINUX_DIR)/arch/arm/boot/zImage $(BIN_DIR)/openwrt-$(BOARD)-zImage
- $(foreach board,$(BOARDS),
- $(CP) $(DTS_DIR)/$(board).dtb $(BIN_DIR)/
- )
-endef
-
-define Image/InstallKernel
-
- ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_KERNEL),)
- mkdir -p $(TARGET_DIR)/boot
- $(CP) $(LINUX_DIR)/arch/arm/boot/zImage $(TARGET_DIR)/boot/
- endif
-
- ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_DTB),)
- mkdir -p $(TARGET_DIR)/boot
- $(foreach board,$(BOARDS),
- $(CP) $(DTS_DIR)/$(board).dtb $(TARGET_DIR)/boot/
- )
- endif
-
-endef
-
-define Image/Build
- $(call Image/Build/$(1))
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-
-define KernelPackage/rtc-stmp3xxx
- SUBMENU:=$(OTHER_MENU)
- TITLE:=STMP3xxx SoC built-in RTC support
- DEPENDS:=@TARGET_mxs
- $(call AddDepends/rtc)
- KCONFIG:= \
- CONFIG_RTC_CLASS=y \
- CONFIG_RTC_DRV_STMP=m
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-stmp3xxx.ko
- AUTOLOAD:=$(call AutoLoad,50,rtc-stmp3xxx)
-endef
-
-$(eval $(call KernelPackage,rtc-stmp3xxx))
-
-define KernelPackage/wdt-stmp3xxx
- SUBMENU:=$(OTHER_MENU)
- TITLE:=STMP3xxx Watchdog timer
- DEPENDS:=kmod-rtc-stmp3xxx
- KCONFIG:=CONFIG_STMP3XXX_RTC_WATCHDOG
- FILES:=$(LINUX_DIR)/drivers/$(WATCHDOG_DIR)/stmp3xxx_rtc_wdt.ko
- AUTOLOAD:=$(call AutoLoad,51,stmp3xxx_rtc_wdt)
-endef
-
-define KernelPackage/wdt-stmp3xxx/description
- Kernel module for STMP3xxx watchdog timer.
-endef
-
-$(eval $(call KernelPackage,wdt-stmp3xxx))
-
-define KernelPackage/usb-chipidea-imx
- TITLE:=Support for ChipIdea controllers on Freescale i.MX SoCs
- DEPENDS:=+kmod-usb-chipidea @TARGET_mxs
- FILES:= \
- $(LINUX_DIR)/drivers/usb/chipidea/ci_hdrc_imx.ko \
- $(LINUX_DIR)/drivers/usb/chipidea/usbmisc_imx.ko
- AUTOLOAD:=$(call AutoLoad,52,usbmisc_imx ci_hdrc_imx,1)
- $(call AddDepends/usb)
-endef
-
-define KernelPackage/usb-chipidea-imx/description
- Kernel support for USB ChipIdea controllers on Freescale i.MX SoCs
-endef
-
-$(eval $(call KernelPackage,usb-chipidea-imx,1))
-
-define KernelPackage/sound-soc-mxs
- TITLE:=Freescale i.MX23/i.MX28 built-in SoC sound support
- KCONFIG:= \
- CONFIG_SND_SOC_MXS_BUILTIN_CODEC \
- CONFIG_SND_MXS_SOC_BUILTIN
- FILES:= \
- $(LINUX_DIR)/sound/soc/mxs/snd-soc-mxs-builtin-audio.ko \
- $(LINUX_DIR)/sound/soc/mxs/snd-soc-mxs-builtin-dai.ko \
- $(LINUX_DIR)/sound/soc/mxs/snd-soc-mxs-builtin-pcm.ko \
- $(LINUX_DIR)/sound/soc/codecs/snd-soc-mxs-builtin-codec.ko
- AUTOLOAD:=$(call AutoLoad,65,snd-soc-mxs-builtin-pcm snd-soc-mxs-builtin-dai snd-soc-mxs-builtin-codec snd-soc-mxs-builtin-audio)
- DEPENDS:=@TARGET_mxs +kmod-sound-soc-core
- $(call AddDepends/sound)
-endef
-
-define KernelPackage/sound-soc-mxs/description
- Kernel support for Freescale i.MX23/i.MX28 built-in SoC audio
-endef
-
-$(eval $(call KernelPackage,sound-soc-mxs))
-
-define KernelPackage/iio-mxs-lradc
- SUBMENU:=$(OTHER_MENU)
- TITLE:=LRADC driver for i.MX23/28
- DEPENDS:=@TARGET_mxs
- KCONFIG:=CONFIG_MXS_LRADC
- FILES:=$(LINUX_DIR)/drivers/staging/iio/adc/mxs-lradc.ko \
- $(LINUX_DIR)/drivers/iio/industrialio-triggered-buffer.ko
- AUTOLOAD:=$(call AutoLoad,70,industrialio-triggered-buffer mxs-lradc)
-endef
-
-define KernelPackage/iio-mxs-lradc/description
- Kernel module for i.MX23/28 LRADC driver
-endef
-
-$(eval $(call KernelPackage,iio-mxs-lradc))
-
-define KernelPackage/crypto-hw-dcp
- TITLE:=i.MX23/28 DCP hardware crypto module
- DEPENDS:=@TARGET_mxs
- KCONFIG:=CONFIG_CRYPTO_DEV_DCP
- FILES:=$(LINUX_DIR)/drivers/crypto/dcp.ko
- AUTOLOAD:=$(call AutoLoad,90,dcp)
- $(call AddDepends/crypto,+kmod-crypto-authenc +kmod-crypto-des)
-endef
-
-define KernelPackage/crypto-hw-dcp/description
- Kernel support for the i.MX23/28 DCP crypto engine
-endef
-
-$(eval $(call KernelPackage,crypto-hw-dcp))
+++ /dev/null
---- a/sound/soc/codecs/Kconfig
-+++ b/sound/soc/codecs/Kconfig
-@@ -125,6 +125,7 @@ config SND_SOC_ALL_CODECS
- select SND_SOC_WM9705 if SND_SOC_AC97_BUS
- select SND_SOC_WM9712 if SND_SOC_AC97_BUS
- select SND_SOC_WM9713 if SND_SOC_AC97_BUS
-+ select SND_SOC_MXS_BUILTIN_CODEC
- help
- Normally ASoC codec drivers are only built if a machine driver which
- uses them is also built since they are only usable with a machine
-@@ -507,6 +508,9 @@ config SND_SOC_WM9712
- config SND_SOC_WM9713
- tristate
-
-+config SND_SOC_MXS_BUILTIN_CODEC
-+ tristate
-+
- # Amp
- config SND_SOC_LM4857
- tristate
---- a/sound/soc/codecs/Makefile
-+++ b/sound/soc/codecs/Makefile
-@@ -118,6 +118,7 @@ snd-soc-wm9705-objs := wm9705.o
- snd-soc-wm9712-objs := wm9712.o
- snd-soc-wm9713-objs := wm9713.o
- snd-soc-wm-hubs-objs := wm_hubs.o
-+snd-soc-mxs-builtin-codec-objs := mxs-builtin-codec.o
-
- # Amp
- snd-soc-max9877-objs := max9877.o
-@@ -242,6 +243,7 @@ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-
- obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o
- obj-$(CONFIG_SND_SOC_WM_ADSP) += snd-soc-wm-adsp.o
- obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o
-+obj-$(CONFIG_SND_SOC_MXS_BUILTIN_CODEC) += snd-soc-mxs-builtin-codec.o
-
- # Amp
- obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o
---- /dev/null
-+++ b/sound/soc/codecs/mxs-builtin-codec.c
-@@ -0,0 +1,1128 @@
-+/*
-+ * mxs-builtin-codec.c -- i.MX233 built-in codec ALSA Soc Audio driver
-+ *
-+ * Author: Michal Ulianko <michal.ulianko@gmail.com>
-+ *
-+ * Based on sound/soc/codecs/mxs-adc-codec.c for kernel 2.6.35
-+ * by Vladislav Buzov <vbuzov@embeddedalley.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+
-+#include "mxs-builtin-codec.h"
-+
-+#ifndef BF
-+#define BF(value, field) (((value) << BP_##field) & BM_##field)
-+#endif
-+
-+/* TODO Delete this and use BM_RTC_PERSISTENT0_RELEASE_GND from header file
-+ * if it works. */
-+#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
-+#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
-+#define BM_RTC_PERSISTENT0_RELEASE_GND BF(0x2, RTC_PERSISTENT0_SPARE_ANALOG)
-+
-+/* TODO Use codec IO function soc snd write etc, instead of __writel __readl */
-+
-+struct mxs_adc_priv {
-+ void __iomem *ain_base;
-+ void __iomem *aout_base;
-+ void __iomem *rtc_base;
-+ struct clk *clk;
-+};
-+
-+static unsigned int mxs_regmap[] = {
-+ HW_AUDIOOUT_CTRL,
-+ HW_AUDIOOUT_STAT,
-+ HW_AUDIOOUT_DACSRR,
-+ HW_AUDIOOUT_DACVOLUME,
-+ HW_AUDIOOUT_DACDEBUG,
-+ HW_AUDIOOUT_HPVOL,
-+ HW_AUDIOOUT_PWRDN,
-+ HW_AUDIOOUT_REFCTRL,
-+ HW_AUDIOOUT_ANACTRL,
-+ HW_AUDIOOUT_TEST,
-+ HW_AUDIOOUT_BISTCTRL,
-+ HW_AUDIOOUT_BISTSTAT0,
-+ HW_AUDIOOUT_BISTSTAT1,
-+ HW_AUDIOOUT_ANACLKCTRL,
-+ HW_AUDIOOUT_DATA,
-+ HW_AUDIOOUT_SPEAKERCTRL,
-+ HW_AUDIOOUT_VERSION,
-+ HW_AUDIOIN_CTRL,
-+ HW_AUDIOIN_STAT,
-+ HW_AUDIOIN_ADCSRR,
-+ HW_AUDIOIN_ADCVOLUME,
-+ HW_AUDIOIN_ADCDEBUG,
-+ HW_AUDIOIN_ADCVOL,
-+ HW_AUDIOIN_MICLINE,
-+ HW_AUDIOIN_ANACLKCTRL,
-+ HW_AUDIOIN_DATA,
-+};
-+
-+static void __iomem *mxs_getreg(struct mxs_adc_priv *mxs_adc, int i)
-+{
-+ if (i <= 16)
-+ return mxs_adc->aout_base + mxs_regmap[i];
-+ else if (i < ADC_REGNUM)
-+ return mxs_adc->ain_base + mxs_regmap[i];
-+ else
-+ return NULL;
-+}
-+
-+static u8 dac_volumn_control_word[] = {
-+ 0x37, 0x5e, 0x7e, 0x8e,
-+ 0x9e, 0xae, 0xb6, 0xbe,
-+ 0xc6, 0xce, 0xd6, 0xde,
-+ 0xe6, 0xee, 0xf6, 0xfe,
-+};
-+
-+struct dac_srr {
-+ u32 rate;
-+ u32 basemult;
-+ u32 src_hold;
-+ u32 src_int;
-+ u32 src_frac;
-+};
-+
-+static struct dac_srr srr_values[] = {
-+ {192000, 0x4, 0x0, 0x0F, 0x13FF},
-+ {176400, 0x4, 0x0, 0x11, 0x0037},
-+ {128000, 0x4, 0x0, 0x17, 0x0E00},
-+ {96000, 0x2, 0x0, 0x0F, 0x13FF},
-+ {88200, 0x2, 0x0, 0x11, 0x0037},
-+ {64000, 0x2, 0x0, 0x17, 0x0E00},
-+ {48000, 0x1, 0x0, 0x0F, 0x13FF},
-+ {44100, 0x1, 0x0, 0x11, 0x0037},
-+ {32000, 0x1, 0x0, 0x17, 0x0E00},
-+ {24000, 0x1, 0x1, 0x0F, 0x13FF},
-+ {22050, 0x1, 0x1, 0x11, 0x0037},
-+ {16000, 0x1, 0x1, 0x17, 0x0E00},
-+ {12000, 0x1, 0x3, 0x0F, 0x13FF},
-+ {11025, 0x1, 0x3, 0x11, 0x0037},
-+ {8000, 0x1, 0x3, 0x17, 0x0E00}
-+};
-+
-+static inline int get_srr_values(int rate)
-+{
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(srr_values); i++)
-+ if (srr_values[i].rate == rate)
-+ return i;
-+
-+ return -1;
-+}
-+
-+/* SoC IO functions */
-+static void mxs_codec_write_cache(struct snd_soc_codec *codec, unsigned int reg, unsigned int value)
-+{
-+ u16 *cache = codec->reg_cache;
-+ if (reg < ADC_REGNUM)
-+ cache[reg] = value;
-+}
-+
-+static int mxs_codec_write(struct snd_soc_codec *codec, unsigned int reg, unsigned int value)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+ unsigned int reg_val;
-+ unsigned int mask = 0xffff;
-+
-+ if (reg >= ADC_REGNUM)
-+ return -EIO;
-+
-+ mxs_codec_write_cache(codec, reg, value);
-+
-+ if (reg & 0x1) {
-+ mask <<= 16;
-+ value <<= 16;
-+ }
-+
-+ reg_val = __raw_readl(mxs_getreg(mxs_adc, reg >> 1));
-+ reg_val = (reg_val & ~mask) | value;
-+ __raw_writel(reg_val, mxs_getreg(mxs_adc, reg >> 1));
-+
-+ return 0;
-+}
-+
-+static unsigned int mxs_codec_read(struct snd_soc_codec *codec, unsigned int reg)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+ unsigned int reg_val;
-+
-+ if (reg >= ADC_REGNUM)
-+ return -1;
-+
-+ reg_val = __raw_readl(mxs_getreg(mxs_adc, reg >> 1));
-+ if (reg & 1)
-+ reg_val >>= 16;
-+
-+ return reg_val & 0xffff;
-+}
-+
-+// static unsigned int mxs_codec_read_cache(struct snd_soc_codec *codec, unsigned int reg)
-+// {
-+// u16 *cache = codec->reg_cache;
-+// if (reg >= ADC_REGNUM)
-+// return -EINVAL;
-+// return cache[reg];
-+// }
-+
-+static void mxs_codec_sync_reg_cache(struct snd_soc_codec *codec)
-+{
-+ int reg;
-+ for (reg = 0; reg < ADC_REGNUM; reg += 1)
-+ mxs_codec_write_cache(codec, reg,
-+ mxs_codec_read(codec, reg));
-+}
-+
-+// static int mxs_codec_restore_reg(struct snd_soc_codec *codec, unsigned int reg)
-+// {
-+// unsigned int cached_val, hw_val;
-+//
-+// cached_val = mxs_codec_read_cache(codec, reg);
-+// hw_val = mxs_codec_read(codec, reg);
-+//
-+// if (hw_val != cached_val)
-+// return mxs_codec_write(codec, reg, cached_val);
-+//
-+// return 0;
-+// }
-+/* END SoC IO functions */
-+
-+/* Codec routines */
-+#define VAG_BASE_VALUE ((1400/2 - 625)/25)
-+
-+static void mxs_codec_dac_set_vag(struct mxs_adc_priv *mxs_adc)
-+{
-+ u32 refctrl_val = __raw_readl(mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL);
-+
-+ refctrl_val &= ~(BM_AUDIOOUT_REFCTRL_VAG_VAL);
-+ refctrl_val &= ~(BM_AUDIOOUT_REFCTRL_VBG_ADJ);
-+ refctrl_val |= BF(VAG_BASE_VALUE, AUDIOOUT_REFCTRL_VAG_VAL) |
-+ BM_AUDIOOUT_REFCTRL_ADJ_VAG |
-+ BF(0xF, AUDIOOUT_REFCTRL_ADC_REFVAL) |
-+ BM_AUDIOOUT_REFCTRL_ADJ_ADC |
-+ BF(0x3, AUDIOOUT_REFCTRL_VBG_ADJ) | BM_AUDIOOUT_REFCTRL_RAISE_REF;
-+
-+ __raw_writel(refctrl_val, mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL);
-+}
-+
-+static bool mxs_codec_dac_is_capless(struct mxs_adc_priv *mxs_adc)
-+{
-+ if ((__raw_readl(mxs_adc->aout_base + HW_AUDIOOUT_PWRDN)
-+ & BM_AUDIOOUT_PWRDN_CAPLESS) == 0)
-+ return false;
-+ else
-+ return true;
-+}
-+
-+static void mxs_codec_dac_arm_short_cm(struct mxs_adc_priv *mxs_adc, bool bShort)
-+{
-+ __raw_writel(BF(3, AUDIOOUT_ANACTRL_SHORTMODE_CM),
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_CM_STS,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ if (bShort)
-+ __raw_writel(BF(1, AUDIOOUT_ANACTRL_SHORTMODE_CM),
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET);
-+}
-+
-+static void mxs_codec_dac_arm_short_lr(struct mxs_adc_priv *mxs_adc, bool bShort)
-+{
-+ __raw_writel(BF(3, AUDIOOUT_ANACTRL_SHORTMODE_LR),
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_LR_STS,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ if (bShort)
-+ __raw_writel(BF(1, AUDIOOUT_ANACTRL_SHORTMODE_LR),
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET);
-+}
-+
-+static void mxs_codec_dac_set_short_trip_level(struct mxs_adc_priv *mxs_adc, u8 u8level)
-+{
-+ __raw_writel(__raw_readl(mxs_adc->aout_base +
-+ HW_AUDIOOUT_ANACTRL)
-+ & (~BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL)
-+ & (~BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR)
-+ | BF(u8level, AUDIOOUT_ANACTRL_SHORT_LVLADJL)
-+ | BF(u8level, AUDIOOUT_ANACTRL_SHORT_LVLADJR),
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL);
-+}
-+
-+static void mxs_codec_dac_arm_short(struct mxs_adc_priv *mxs_adc, bool bLatchCM, bool bLatchLR)
-+{
-+ if (bLatchCM) {
-+ if (mxs_codec_dac_is_capless(mxs_adc))
-+ mxs_codec_dac_arm_short_cm(mxs_adc, true);
-+ } else
-+ mxs_codec_dac_arm_short_cm(mxs_adc, false);
-+
-+ if (bLatchLR)
-+ mxs_codec_dac_arm_short_lr(mxs_adc, true);
-+ else
-+ mxs_codec_dac_arm_short_lr(mxs_adc, false);
-+}
-+
-+static void
-+mxs_codec_dac_power_on(struct mxs_adc_priv *mxs_adc)
-+{
-+ /* Ungate DAC clocks */
-+ __raw_writel(BM_AUDIOOUT_CTRL_CLKGATE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_CLR);
-+ __raw_writel(BM_AUDIOOUT_ANACLKCTRL_CLKGATE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACLKCTRL_CLR);
-+
-+ /* 16 bit word length */
-+ __raw_writel(BM_AUDIOOUT_CTRL_WORD_LENGTH,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET);
-+
-+ /* Arm headphone LR short protect */
-+ mxs_codec_dac_set_short_trip_level(mxs_adc, 0);
-+ mxs_codec_dac_arm_short(mxs_adc, false, true);
-+
-+ /* Update DAC volume over zero crossings */
-+ __raw_writel(BM_AUDIOOUT_DACVOLUME_EN_ZCD,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET);
-+ /* Mute DAC */
-+ __raw_writel(BM_AUDIOOUT_DACVOLUME_MUTE_LEFT |
-+ BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET);
-+
-+ /* Update HP volume over zero crossings */
-+ __raw_writel(BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD,
-+ mxs_adc->aout_base + HW_AUDIOOUT_HPVOL_SET);
-+
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_CLASSAB,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET);
-+
-+ /* Mute HP output */
-+ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_HPVOL_SET);
-+ /* Mute speaker amp */
-+ __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_SPEAKERCTRL_SET);
-+ /* Enable the audioout */
-+ __raw_writel(BM_AUDIOOUT_CTRL_RUN,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET);
-+}
-+
-+static void
-+mxs_codec_dac_power_down(struct mxs_adc_priv *mxs_adc)
-+{
-+ /* Disable the audioout */
-+ __raw_writel(BM_AUDIOOUT_CTRL_RUN,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_CLR);
-+ /* Disable class AB */
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_CLASSAB,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+
-+ /* Set hold to ground */
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_HOLD_GND,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET);
-+
-+ /* Mute HP output */
-+ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_HPVOL_SET);
-+ /* Power down HP output */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET);
-+
-+ /* Mute speaker amp */
-+ __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_SPEAKERCTRL_SET);
-+ /* Power down speaker amp */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_SPEAKER,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET);
-+
-+ /* Mute DAC */
-+ __raw_writel(BM_AUDIOOUT_DACVOLUME_MUTE_LEFT |
-+ BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET);
-+ /* Power down DAC */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_DAC,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET);
-+
-+ /* Gate DAC clocks */
-+ __raw_writel(BM_AUDIOOUT_ANACLKCTRL_CLKGATE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACLKCTRL_SET);
-+ __raw_writel(BM_AUDIOOUT_CTRL_CLKGATE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET);
-+}
-+
-+static void
-+mxs_codec_adc_power_on(struct mxs_adc_priv *mxs_adc)
-+{
-+ u32 reg;
-+
-+ /* Ungate ADC clocks */
-+ __raw_writel(BM_AUDIOIN_CTRL_CLKGATE,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_CLR);
-+ __raw_writel(BM_AUDIOIN_ANACLKCTRL_CLKGATE,
-+ mxs_adc->ain_base + HW_AUDIOIN_ANACLKCTRL_CLR);
-+
-+ /* 16 bit word length */
-+ __raw_writel(BM_AUDIOIN_CTRL_WORD_LENGTH,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_SET);
-+
-+ /* Unmute ADC channels */
-+ __raw_writel(BM_AUDIOIN_ADCVOL_MUTE,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR);
-+
-+ /*
-+ * The MUTE_LEFT and MUTE_RIGHT fields need to be cleared.
-+ * They aren't presented in the datasheet, so this is hardcode.
-+ */
-+ __raw_writel(0x01000100, mxs_adc->ain_base + HW_AUDIOIN_ADCVOLUME_CLR);
-+
-+ /* Set the Input channel gain 3dB */
-+ __raw_writel(BM_AUDIOIN_ADCVOL_GAIN_LEFT,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR);
-+ __raw_writel(BM_AUDIOIN_ADCVOL_GAIN_RIGHT,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR);
-+ __raw_writel(BF(2, AUDIOIN_ADCVOL_GAIN_LEFT),
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET);
-+ __raw_writel(BF(2, AUDIOIN_ADCVOL_GAIN_RIGHT),
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET);
-+
-+ /* Select default input - Microphone */
-+ __raw_writel(BM_AUDIOIN_ADCVOL_SELECT_LEFT,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR);
-+ __raw_writel(BM_AUDIOIN_ADCVOL_SELECT_RIGHT,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR);
-+ __raw_writel(BF
-+ (BV_AUDIOIN_ADCVOL_SELECT__MIC,
-+ AUDIOIN_ADCVOL_SELECT_LEFT),
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET);
-+ __raw_writel(BF
-+ (BV_AUDIOIN_ADCVOL_SELECT__MIC,
-+ AUDIOIN_ADCVOL_SELECT_RIGHT),
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET);
-+
-+ /* Supply bias voltage to microphone */
-+ __raw_writel(BF(1, AUDIOIN_MICLINE_MIC_RESISTOR),
-+ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET);
-+ __raw_writel(BM_AUDIOIN_MICLINE_MIC_SELECT,
-+ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET);
-+ __raw_writel(BF(1, AUDIOIN_MICLINE_MIC_GAIN),
-+ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET);
-+ __raw_writel(BF(7, AUDIOIN_MICLINE_MIC_BIAS),
-+ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET);
-+
-+ /* Set max ADC volume */
-+ reg = __raw_readl(mxs_adc->ain_base + HW_AUDIOIN_ADCVOLUME);
-+ reg &= ~BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT;
-+ reg &= ~BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT;
-+ reg |= BF(ADC_VOLUME_MAX, AUDIOIN_ADCVOLUME_VOLUME_LEFT);
-+ reg |= BF(ADC_VOLUME_MAX, AUDIOIN_ADCVOLUME_VOLUME_RIGHT);
-+ __raw_writel(reg, mxs_adc->ain_base + HW_AUDIOIN_ADCVOLUME);
-+}
-+
-+static void
-+mxs_codec_adc_power_down(struct mxs_adc_priv *mxs_adc)
-+{
-+ /* Mute ADC channels */
-+ __raw_writel(BM_AUDIOIN_ADCVOL_MUTE,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET);
-+
-+ /* Power Down ADC */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_ADC | BM_AUDIOOUT_PWRDN_RIGHT_ADC,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET);
-+
-+ /* Gate ADC clocks */
-+ __raw_writel(BM_AUDIOIN_CTRL_CLKGATE,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_SET);
-+ __raw_writel(BM_AUDIOIN_ANACLKCTRL_CLKGATE,
-+ mxs_adc->ain_base + HW_AUDIOIN_ANACLKCTRL_SET);
-+
-+ /* Disable bias voltage to microphone */
-+ __raw_writel(BF(0, AUDIOIN_MICLINE_MIC_RESISTOR),
-+ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET);
-+}
-+
-+static void mxs_codec_dac_enable(struct mxs_adc_priv *mxs_adc)
-+{
-+ /* Move DAC codec out of reset */
-+ __raw_writel(BM_AUDIOOUT_CTRL_SFTRST,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_CLR);
-+
-+ /* Reduce analog power */
-+ __raw_writel(BM_AUDIOOUT_TEST_HP_I1_ADJ,
-+ mxs_adc->aout_base + HW_AUDIOOUT_TEST_CLR);
-+ __raw_writel(BF(0x1, AUDIOOUT_TEST_HP_I1_ADJ),
-+ mxs_adc->aout_base + HW_AUDIOOUT_TEST_SET);
-+ __raw_writel(BM_AUDIOOUT_REFCTRL_LOW_PWR,
-+ mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL_SET);
-+ __raw_writel(BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS,
-+ mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL_SET);
-+ __raw_writel(BM_AUDIOOUT_REFCTRL_BIAS_CTRL,
-+ mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL_CLR);
-+ __raw_writel(BF(0x1, AUDIOOUT_REFCTRL_BIAS_CTRL),
-+ mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL_CLR);
-+
-+ /* Set Vag value */
-+ mxs_codec_dac_set_vag(mxs_adc);
-+
-+ /* Power on DAC codec */
-+ mxs_codec_dac_power_on(mxs_adc);
-+}
-+
-+static void mxs_codec_dac_disable(struct mxs_adc_priv *mxs_adc)
-+{
-+ mxs_codec_dac_power_down(mxs_adc);
-+}
-+
-+static void mxs_codec_adc_enable(struct mxs_adc_priv *mxs_adc)
-+{
-+ /* Move ADC codec out of reset */
-+ __raw_writel(BM_AUDIOIN_CTRL_SFTRST,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_CLR);
-+
-+ /* Power on ADC codec */
-+ mxs_codec_adc_power_on(mxs_adc);
-+}
-+
-+static void mxs_codec_adc_disable(struct mxs_adc_priv *mxs_adc)
-+{
-+ mxs_codec_adc_power_down(mxs_adc);
-+}
-+
-+static void mxs_codec_startup(struct snd_soc_codec *codec)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+
-+ /* Soft reset DAC block */
-+ __raw_writel(BM_AUDIOOUT_CTRL_SFTRST,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET);
-+ while (!(__raw_readl(mxs_adc->aout_base + HW_AUDIOOUT_CTRL)
-+ & BM_AUDIOOUT_CTRL_CLKGATE)){
-+ }
-+
-+ /* Soft reset ADC block */
-+ __raw_writel(BM_AUDIOIN_CTRL_SFTRST,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_SET);
-+ while (!(__raw_readl(mxs_adc->ain_base + HW_AUDIOIN_CTRL)
-+ & BM_AUDIOIN_CTRL_CLKGATE)){
-+ }
-+
-+ mxs_codec_dac_enable(mxs_adc);
-+ mxs_codec_adc_enable(mxs_adc);
-+
-+ /* Sync regs and cache */
-+ mxs_codec_sync_reg_cache(codec);
-+}
-+
-+static void mxs_codec_stop(struct snd_soc_codec *codec)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+
-+ mxs_codec_dac_disable(mxs_adc);
-+ mxs_codec_adc_disable(mxs_adc);
-+}
-+/* END Codec routines */
-+
-+/* kcontrol */
-+static int dac_info_volsw(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
-+ uinfo->count = 2;
-+ uinfo->value.integer.min = 0;
-+ uinfo->value.integer.max = 0xf;
-+ return 0;
-+}
-+
-+static int dac_get_volsw(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+ int reg, l, r;
-+ int i;
-+
-+ reg = __raw_readl(mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME);
-+
-+ l = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT) >>
-+ BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT;
-+ r = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT) >>
-+ BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT;
-+ /*Left channel */
-+ i = 0;
-+ while (i < 16) {
-+ if (l == dac_volumn_control_word[i]) {
-+ ucontrol->value.integer.value[0] = i;
-+ break;
-+ }
-+ i++;
-+ }
-+ if (i == 16)
-+ ucontrol->value.integer.value[0] = i;
-+ /*Right channel */
-+ i = 0;
-+ while (i < 16) {
-+ if (r == dac_volumn_control_word[i]) {
-+ ucontrol->value.integer.value[1] = i;
-+ break;
-+ }
-+ i++;
-+ }
-+ if (i == 16)
-+ ucontrol->value.integer.value[1] = i;
-+
-+ return 0;
-+}
-+
-+static int dac_put_volsw(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+ int reg, l, r;
-+ int i;
-+
-+ i = ucontrol->value.integer.value[0];
-+ l = dac_volumn_control_word[i];
-+ /*Get dac volume for left channel */
-+ reg = BF(l, AUDIOOUT_DACVOLUME_VOLUME_LEFT);
-+
-+ i = ucontrol->value.integer.value[1];
-+ r = dac_volumn_control_word[i];
-+ /*Get dac volume for right channel */
-+ reg = reg | BF(r, AUDIOOUT_DACVOLUME_VOLUME_RIGHT);
-+
-+ /*Clear left/right dac volume */
-+ __raw_writel(BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT |
-+ BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_CLR);
-+ __raw_writel(reg, mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET);
-+
-+ return 0;
-+}
-+
-+static const char *mxs_codec_adc_input_sel[] = {
-+ "Mic", "Line In 1", "Head Phone", "Line In 2" };
-+
-+static const char *mxs_codec_hp_output_sel[] = { "DAC Out", "Line In 1" };
-+
-+static const char *mxs_codec_adc_3d_sel[] = {
-+ "Off", "Low", "Medium", "High" };
-+
-+static const struct soc_enum mxs_codec_enum[] = {
-+ SOC_ENUM_SINGLE(ADC_ADCVOL_L, 12, 4, mxs_codec_adc_input_sel),
-+ SOC_ENUM_SINGLE(ADC_ADCVOL_L, 4, 4, mxs_codec_adc_input_sel),
-+ SOC_ENUM_SINGLE(DAC_HPVOL_H, 0, 2, mxs_codec_hp_output_sel),
-+ SOC_ENUM_SINGLE(DAC_CTRL_L, 8, 4, mxs_codec_adc_3d_sel),
-+};
-+
-+static const struct snd_kcontrol_new mxs_snd_controls[] = {
-+ /* Playback Volume */
-+ {
-+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
-+ .name = "DAC Playback Volume",
-+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
-+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
-+ .info = dac_info_volsw,
-+ .get = dac_get_volsw,
-+ .put = dac_put_volsw,
-+ },
-+
-+ SOC_DOUBLE_R("DAC Playback Switch",
-+ DAC_VOLUME_H, DAC_VOLUME_L, 8, 0x01, 1),
-+ SOC_DOUBLE("HP Playback Volume", DAC_HPVOL_L, 8, 0, 0x7F, 1),
-+
-+ /* Capture Volume */
-+ SOC_DOUBLE_R("ADC Capture Volume",
-+ ADC_VOLUME_H, ADC_VOLUME_L, 0, 0xFF, 0),
-+ SOC_DOUBLE("ADC PGA Capture Volume", ADC_ADCVOL_L, 8, 0, 0x0F, 0),
-+ SOC_SINGLE("ADC PGA Capture Switch", ADC_ADCVOL_H, 8, 0x1, 1),
-+ SOC_SINGLE("Mic PGA Capture Volume", ADC_MICLINE_L, 0, 0x03, 0),
-+
-+ /* Virtual 3D effect */
-+ SOC_ENUM("3D effect", mxs_codec_enum[3]),
-+};
-+/* END kcontrol */
-+
-+/* DAPM */
-+static int pga_event(struct snd_soc_dapm_widget *w,
-+ struct snd_kcontrol *kcontrol, int event)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(w->codec);
-+
-+ switch (event) {
-+ case SND_SOC_DAPM_PRE_PMU:
-+ /* Prepare powering up HP and SPEAKER output */
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_HOLD_GND,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET);
-+ __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND,
-+ mxs_adc->rtc_base + HW_RTC_PERSISTENT0_SET);
-+ msleep(100);
-+ break;
-+ case SND_SOC_DAPM_POST_PMU:
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_HOLD_GND,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ break;
-+ case SND_SOC_DAPM_POST_PMD:
-+ __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND,
-+ mxs_adc->rtc_base + HW_RTC_PERSISTENT0_CLR);
-+ break;
-+ }
-+ return 0;
-+}
-+
-+static int adc_event(struct snd_soc_dapm_widget *w,
-+ struct snd_kcontrol *kcontrol, int event)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(w->codec);
-+
-+ switch (event) {
-+ case SND_SOC_DAPM_PRE_PMU:
-+ __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND,
-+ mxs_adc->rtc_base + HW_RTC_PERSISTENT0_SET);
-+ msleep(100);
-+ break;
-+ case SND_SOC_DAPM_POST_PMD:
-+ __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND,
-+ mxs_adc->rtc_base + HW_RTC_PERSISTENT0_CLR);
-+ break;
-+ }
-+ return 0;
-+}
-+
-+/* Left ADC Mux */
-+static const struct snd_kcontrol_new mxs_left_adc_controls =
-+SOC_DAPM_ENUM("Route", mxs_codec_enum[0]);
-+
-+/* Right ADC Mux */
-+static const struct snd_kcontrol_new mxs_right_adc_controls =
-+SOC_DAPM_ENUM("Route", mxs_codec_enum[1]);
-+
-+/* Head Phone Mux */
-+static const struct snd_kcontrol_new mxs_hp_controls =
-+SOC_DAPM_ENUM("Route", mxs_codec_enum[2]);
-+
-+static const struct snd_soc_dapm_widget mxs_dapm_widgets[] = {
-+ SND_SOC_DAPM_ADC_E("ADC", "Capture", DAC_PWRDN_L, 8, 1, adc_event,
-+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
-+
-+ SND_SOC_DAPM_DAC("DAC", "Playback", DAC_PWRDN_L, 12, 1),
-+
-+ SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
-+ &mxs_left_adc_controls),
-+ SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
-+ &mxs_right_adc_controls),
-+ SND_SOC_DAPM_MUX("HP Mux", SND_SOC_NOPM, 0, 0,
-+ &mxs_hp_controls),
-+ SND_SOC_DAPM_PGA_E("HP AMP", DAC_PWRDN_L, 0, 1, NULL, 0, pga_event,
-+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
-+ SND_SOC_DAPM_POST_PMD),
-+ SND_SOC_DAPM_PGA("SPEAKER AMP", DAC_PWRDN_H, 8, 1, NULL, 0),
-+ SND_SOC_DAPM_INPUT("LINE1L"),
-+ SND_SOC_DAPM_INPUT("LINE1R"),
-+ SND_SOC_DAPM_INPUT("LINE2L"),
-+ SND_SOC_DAPM_INPUT("LINE2R"),
-+ SND_SOC_DAPM_INPUT("MIC"),
-+
-+ SND_SOC_DAPM_OUTPUT("SPEAKER"),
-+ SND_SOC_DAPM_OUTPUT("HPL"),
-+ SND_SOC_DAPM_OUTPUT("HPR"),
-+};
-+
-+/* routes for sgtl5000 */
-+static const struct snd_soc_dapm_route mxs_dapm_routes[] = {
-+ /* Left ADC Mux */
-+ {"Left ADC Mux", "Mic", "MIC"},
-+ {"Left ADC Mux", "Line In 1", "LINE1L"},
-+ {"Left ADC Mux", "Line In 2", "LINE2L"},
-+ {"Left ADC Mux", "Head Phone", "HPL"},
-+
-+ /* Right ADC Mux */
-+ {"Right ADC Mux", "Mic", "MIC"},
-+ {"Right ADC Mux", "Line In 1", "LINE1R"},
-+ {"Right ADC Mux", "Line In 2", "LINE2R"},
-+ {"Right ADC Mux", "Head Phone", "HPR"},
-+
-+ /* ADC */
-+ {"ADC", NULL, "Left ADC Mux"},
-+ {"ADC", NULL, "Right ADC Mux"},
-+
-+ /* HP Mux */
-+ {"HP Mux", "DAC Out", "DAC"},
-+ {"HP Mux", "Line In 1", "LINE1L"},
-+ {"HP Mux", "Line In 1", "LINE1R"},
-+
-+ /* HP amp */
-+ {"HP AMP", NULL, "HP Mux"},
-+ /* HP output */
-+ {"HPR", NULL, "HP AMP"},
-+ {"HPL", NULL, "HP AMP"},
-+
-+ /* Speaker amp */
-+ {"SPEAKER AMP", NULL, "DAC"},
-+ {"SPEAKER", NULL, "SPEAKER AMP"},
-+};
-+/* END DAPM */
-+
-+static int mxs_set_bias_level(struct snd_soc_codec *codec,
-+ enum snd_soc_bias_level level)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+
-+ pr_debug("dapm level %d\n", level);
-+ switch (level) {
-+ case SND_SOC_BIAS_ON: /* full On */
-+ if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
-+ break;
-+ break;
-+
-+ case SND_SOC_BIAS_PREPARE: /* partial On */
-+ if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
-+ break;
-+ /* Set Capless mode */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_CAPLESS,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_CLR);
-+ break;
-+
-+ case SND_SOC_BIAS_STANDBY: /* Off, with power */
-+ if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
-+ break;
-+ /* Unset Capless mode */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_CAPLESS,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET);
-+ break;
-+
-+ case SND_SOC_BIAS_OFF: /* Off, without power */
-+ if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
-+ break;
-+ /* Unset Capless mode */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_CAPLESS,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET);
-+ break;
-+ }
-+
-+ codec->dapm.bias_level = level;
-+ return 0;
-+}
-+
-+/* MXS-ADC Codec DAI driver */
-+static int mxs_pcm_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params,
-+ struct snd_soc_dai *dai)
-+{
-+ struct snd_soc_codec *codec = dai->codec;
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0;
-+ int i;
-+ u32 srr_value = 0;
-+ u32 src_hold = 0;
-+
-+ i = get_srr_values(params_rate(params));
-+ if (i < 0)
-+ dev_warn(codec->dev, "%s doesn't support rate %d\n",
-+ codec->name, params_rate(params));
-+ else {
-+ src_hold = srr_values[i].src_hold;
-+
-+ srr_value =
-+ BF(srr_values[i].basemult, AUDIOOUT_DACSRR_BASEMULT) |
-+ BF(srr_values[i].src_int, AUDIOOUT_DACSRR_SRC_INT) |
-+ BF(srr_values[i].src_frac, AUDIOOUT_DACSRR_SRC_FRAC) |
-+ BF(src_hold, AUDIOOUT_DACSRR_SRC_HOLD);
-+
-+ if (playback)
-+ __raw_writel(srr_value,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACSRR);
-+ else
-+ __raw_writel(srr_value,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCSRR);
-+ }
-+
-+ switch (params_format(params)) {
-+ case SNDRV_PCM_FORMAT_S16_LE:
-+ if (playback)
-+ __raw_writel(BM_AUDIOOUT_CTRL_WORD_LENGTH,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET);
-+ else
-+ __raw_writel(BM_AUDIOIN_CTRL_WORD_LENGTH,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_SET);
-+
-+ break;
-+
-+ case SNDRV_PCM_FORMAT_S32_LE:
-+ if (playback)
-+ __raw_writel(BM_AUDIOOUT_CTRL_WORD_LENGTH,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_CLR);
-+ else
-+ __raw_writel(BM_AUDIOIN_CTRL_WORD_LENGTH,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_CLR);
-+
-+ break;
-+
-+ default:
-+ dev_warn(codec->dev, "%s doesn't support format %d\n",
-+ codec->name, params_format(params));
-+
-+ }
-+
-+ return 0;
-+}
-+
-+/* mute the codec used by alsa core */
-+static int mxs_codec_dig_mute(struct snd_soc_dai *codec_dai, int mute)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec_dai->codec);
-+ int l, r;
-+ int ll, rr;
-+ u32 reg, reg1, reg2;
-+ u32 dac_mask = BM_AUDIOOUT_DACVOLUME_MUTE_LEFT |
-+ BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT;
-+
-+ if (mute) {
-+ reg = __raw_readl(mxs_adc->aout_base + \
-+ HW_AUDIOOUT_DACVOLUME);
-+
-+ reg1 = reg & ~BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT;
-+ reg1 = reg1 & ~BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT;
-+
-+ l = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT) >>
-+ BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT;
-+ r = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT) >>
-+ BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT;
-+
-+ /* fade out dac vol */
-+ while ((l > DAC_VOLUME_MIN) || (r > DAC_VOLUME_MIN)) {
-+ l -= 0x8;
-+ r -= 0x8;
-+ ll = l > DAC_VOLUME_MIN ? l : DAC_VOLUME_MIN;
-+ rr = r > DAC_VOLUME_MIN ? r : DAC_VOLUME_MIN;
-+ reg2 = reg1 | BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(ll)
-+ | BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(rr);
-+ __raw_writel(reg2,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME);
-+ msleep(1);
-+ }
-+
-+ __raw_writel(dac_mask,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET);
-+ reg = reg | dac_mask;
-+ __raw_writel(reg,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME);
-+ } else
-+ __raw_writel(dac_mask,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_CLR);
-+
-+ return 0;
-+}
-+
-+#define MXS_ADC_RATES SNDRV_PCM_RATE_8000_192000
-+#define MXS_ADC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
-+
-+static const struct snd_soc_dai_ops mxs_codec_dai_ops = {
-+ .hw_params = mxs_pcm_hw_params,
-+ .digital_mute = mxs_codec_dig_mute,
-+};
-+
-+static struct snd_soc_dai_driver mxs_codec_dai_driver = {
-+ .name = "mxs-builtin-codec-dai",
-+ .playback = {
-+ .stream_name = "Playback",
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = MXS_ADC_RATES,
-+ .formats = MXS_ADC_FORMATS,
-+ },
-+ .capture = {
-+ .stream_name = "Capture",
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = MXS_ADC_RATES,
-+ .formats = MXS_ADC_FORMATS,
-+ },
-+ .ops = &mxs_codec_dai_ops,
-+};
-+/* END MXS-ADC Codec DAI driver */
-+
-+/* MXS-ADC Codec driver */
-+static int mxs_codec_driver_probe(struct snd_soc_codec *codec)
-+{
-+ int ret = 0;
-+ /* We don't use snd_soc_codec_set_cache_io because we are using
-+ * our own IO functions: write, read. */
-+
-+ mxs_codec_startup(codec);
-+
-+ /* leading to standby state */
-+ ret = mxs_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-+ if (ret)
-+ goto err;
-+
-+ return 0;
-+
-+err:
-+ mxs_codec_stop(codec);
-+
-+ return ret;
-+}
-+
-+static int mxs_codec_driver_remove(struct snd_soc_codec *codec)
-+{
-+ mxs_codec_stop(codec);
-+
-+ return 0;
-+}
-+
-+// static int mxs_codec_driver_suspend(struct snd_soc_codec *codec)
-+// {
-+// /* TODO Enable power management. */
-+// return 0;
-+// }
-+
-+// static int mxs_codec_driver_resume(struct snd_soc_codec *codec)
-+// {
-+// /* TODO Enable power management. */
-+// return 0;
-+// }
-+
-+static struct snd_soc_codec_driver mxs_codec_driver = {
-+ .probe = mxs_codec_driver_probe,
-+ .remove = mxs_codec_driver_remove,
-+// .suspend = mxs_codec_driver_suspend,
-+// .resume = mxs_codec_driver_resume,
-+ .set_bias_level = mxs_set_bias_level,
-+ .reg_cache_size = ADC_REGNUM,
-+ .reg_word_size = sizeof(u16),
-+ .reg_cache_step = 1,
-+// .reg_cache_default = mxsadc_regs,
-+// .volatile_register = sgtl5000_volatile_register,
-+ .controls = mxs_snd_controls,
-+ .num_controls = ARRAY_SIZE(mxs_snd_controls),
-+ .dapm_widgets = mxs_dapm_widgets,
-+ .num_dapm_widgets = ARRAY_SIZE(mxs_dapm_widgets),
-+ .dapm_routes = mxs_dapm_routes,
-+ .num_dapm_routes = ARRAY_SIZE(mxs_dapm_routes),
-+ .write = mxs_codec_write,
-+ .read = mxs_codec_read,
-+};
-+/* END MXS-ADC Codec driver */
-+
-+/* Underlying platform device that registers codec */
-+static int mxs_adc_probe(struct platform_device *pdev)
-+{
-+ struct mxs_adc_priv *mxs_adc;
-+ struct resource *r;
-+ int ret;
-+
-+ mxs_adc = devm_kzalloc(&pdev->dev, sizeof(struct mxs_adc_priv), GFP_KERNEL);
-+ if (!mxs_adc)
-+ return -ENOMEM;
-+
-+ platform_set_drvdata(pdev, mxs_adc);
-+
-+ /* audio-in IO memory */
-+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audioin");
-+ if (IS_ERR(r)) {
-+ dev_err(&pdev->dev, "failed to get resource\n");
-+ return PTR_ERR(r);
-+ }
-+
-+ mxs_adc->ain_base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
-+ if (IS_ERR(mxs_adc->ain_base)) {
-+ dev_err(&pdev->dev, "ioremap failed\n");
-+ return PTR_ERR(mxs_adc->ain_base);
-+ }
-+
-+ /* audio-out IO memory */
-+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audioout");
-+ if (IS_ERR(r)) {
-+ dev_err(&pdev->dev, "failed to get resource\n");
-+ return PTR_ERR(r);
-+ }
-+
-+ mxs_adc->aout_base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
-+ if (IS_ERR(mxs_adc->aout_base)) {
-+ dev_err(&pdev->dev, "ioremap failed\n");
-+ return PTR_ERR(mxs_adc->aout_base);
-+ }
-+
-+ /* rtc IO memory */
-+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
-+ if (IS_ERR(r)) {
-+ dev_err(&pdev->dev, "failed to get resource\n");
-+ return PTR_ERR(r);
-+ }
-+
-+ mxs_adc->rtc_base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
-+ if (IS_ERR(mxs_adc->rtc_base)) {
-+ dev_err(&pdev->dev, "ioremap failed\n");
-+ return PTR_ERR(mxs_adc->rtc_base);
-+ }
-+
-+ /* Get audio clock */
-+ mxs_adc->clk = devm_clk_get(&pdev->dev, "filt");
-+ if (IS_ERR(mxs_adc->clk)) {
-+ ret = PTR_ERR(mxs_adc->clk);
-+ dev_err(&pdev->dev, "%s: Clock initialization failed\n", __func__);
-+ return ret;
-+ }
-+
-+ /* Turn on audio clock */
-+ ret = clk_prepare_enable(mxs_adc->clk);
-+ if (unlikely(ret != 0)) {
-+ dev_err(&pdev->dev, "%s: Clock prepare or enable failed\n", __func__);
-+ return ret;
-+ }
-+
-+ ret = snd_soc_register_codec(&pdev->dev,
-+ &mxs_codec_driver,&mxs_codec_dai_driver, 1);
-+ if (unlikely(ret != 0)) {
-+ dev_err(&pdev->dev, "Codec registration failed\n");
-+ goto disable_clk;
-+ }
-+
-+ return 0;
-+
-+disable_clk:
-+ clk_disable_unprepare(mxs_adc->clk);
-+ return ret;
-+}
-+
-+static int mxs_adc_remove(struct platform_device *pdev)
-+{
-+ struct mxs_adc_priv *mxs_adc = platform_get_drvdata(pdev);
-+
-+ clk_disable_unprepare(mxs_adc->clk);
-+ snd_soc_unregister_codec(&pdev->dev);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mxs_adc_dt_ids[] = {
-+ { .compatible = "fsl,mxs-builtin-codec", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mxs_adc_dt_ids);
-+
-+static struct platform_driver mxs_adc_driver = {
-+ .driver = {
-+ .name = "mxs-builtin-codec",
-+ .owner = THIS_MODULE,
-+ .of_match_table = mxs_adc_dt_ids,
-+ },
-+ .probe = mxs_adc_probe,
-+ .remove = mxs_adc_remove,
-+};
-+
-+module_platform_driver(mxs_adc_driver);
-+/* END Underlying platform device that registers codec */
-+
-+MODULE_DESCRIPTION("Freescale MXS ADC/DAC SoC Codec Driver");
-+MODULE_AUTHOR("Michal Ulianko <michal.ulianko@gmail.com>");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/sound/soc/codecs/mxs-builtin-codec.h
-@@ -0,0 +1,825 @@
-+#ifndef __MXS_ADC_CODEC_H
-+
-+#include <linux/io.h>
-+
-+/* MXS ADC/DAC registers */
-+#define DAC_CTRL_L 0
-+#define DAC_CTRL_H 1
-+#define DAC_STAT_L 2
-+#define DAC_STAT_H 3
-+#define DAC_SRR_L 4
-+#define DAC_VOLUME_L 6
-+#define DAC_VOLUME_H 7
-+#define DAC_DEBUG_L 8
-+#define DAC_DEBUG_H 9
-+#define DAC_HPVOL_L 10
-+#define DAC_HPVOL_H 11
-+#define DAC_PWRDN_L 12
-+#define DAC_PWRDN_H 13
-+#define DAC_REFCTRL_L 14
-+#define DAC_REFCTRL_H 15
-+#define DAC_ANACTRL_L 16
-+#define DAC_ANACTRL_H 17
-+#define DAC_TEST_L 18
-+#define DAC_TEST_H 19
-+#define DAC_BISTCTRL_L 20
-+#define DAC_BISTCTRL_H 21
-+#define DAC_BISTSTAT0_L 22
-+#define DAC_BISTSTAT0_H 23
-+#define DAC_BISTSTAT1_L 24
-+#define DAC_BISTSTAT1_H 25
-+#define DAC_ANACLKCTRL_L 26
-+#define DAC_ANACLKCTRL_H 27
-+#define DAC_DATA_L 28
-+#define DAC_DATA_H 29
-+#define DAC_SPEAKERCTRL_L 30
-+#define DAC_SPEAKERCTRL_H 31
-+#define DAC_VERSION_L 32
-+#define DAC_VERSION_H 33
-+#define ADC_CTRL_L 34
-+#define ADC_CTRL_H 35
-+#define ADC_STAT_L 36
-+#define ADC_STAT_H 37
-+#define ADC_SRR_L 38
-+#define ADC_SRR_H 39
-+#define ADC_VOLUME_L 40
-+#define ADC_VOLUME_H 41
-+#define ADC_DEBUG_L 42
-+#define ADC_DEBUG_H 43
-+#define ADC_ADCVOL_L 44
-+#define ADC_ADCVOL_H 45
-+#define ADC_MICLINE_L 46
-+#define ADC_MICLINE_H 47
-+#define ADC_ANACLKCTRL_L 48
-+#define ADC_ANACLKCTRL_H 49
-+#define ADC_DATA_L 50
-+#define ADC_DATA_H 51
-+
-+#define ADC_REGNUM 52
-+
-+#define DAC_VOLUME_MIN 0x37
-+#define DAC_VOLUME_MAX 0xFE
-+#define ADC_VOLUME_MIN 0x37
-+#define ADC_VOLUME_MAX 0xFE
-+#define HP_VOLUME_MAX 0x0
-+#define HP_VOLUME_MIN 0x7F
-+#define LO_VOLUME_MAX 0x0
-+#define LO_VOLUME_MIN 0x1F
-+
-+/* RTC */
-+#define HW_RTC_PERSISTENT0 (0x00000060)
-+#define HW_RTC_PERSISTENT0_SET (0x00000064)
-+#define HW_RTC_PERSISTENT0_CLR (0x00000068)
-+#define HW_RTC_PERSISTENT0_TOG (0x0000006c)
-+
-+// TODO
-+//#define BM_RTC_PERSISTENT0_RELEASE_GND 0x00080000
-+
-+/* AUDIOOUT */
-+#define HW_AUDIOOUT_CTRL (0x00000000)
-+#define HW_AUDIOOUT_CTRL_SET (0x00000004)
-+#define HW_AUDIOOUT_CTRL_CLR (0x00000008)
-+#define HW_AUDIOOUT_CTRL_TOG (0x0000000c)
-+
-+#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
-+#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
-+#define BP_AUDIOOUT_CTRL_RSRVD4 21
-+#define BM_AUDIOOUT_CTRL_RSRVD4 0x3FE00000
-+#define BF_AUDIOOUT_CTRL_RSRVD4(v) \
-+ (((v) << 21) & BM_AUDIOOUT_CTRL_RSRVD4)
-+#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT 16
-+#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT 0x001F0000
-+#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) \
-+ (((v) << 16) & BM_AUDIOOUT_CTRL_DMAWAIT_COUNT)
-+#define BM_AUDIOOUT_CTRL_RSRVD3 0x00008000
-+#define BM_AUDIOOUT_CTRL_LR_SWAP 0x00004000
-+#define BM_AUDIOOUT_CTRL_EDGE_SYNC 0x00002000
-+#define BM_AUDIOOUT_CTRL_INVERT_1BIT 0x00001000
-+#define BP_AUDIOOUT_CTRL_RSRVD2 10
-+#define BM_AUDIOOUT_CTRL_RSRVD2 0x00000C00
-+#define BF_AUDIOOUT_CTRL_RSRVD2(v) \
-+ (((v) << 10) & BM_AUDIOOUT_CTRL_RSRVD2)
-+#define BP_AUDIOOUT_CTRL_SS3D_EFFECT 8
-+#define BM_AUDIOOUT_CTRL_SS3D_EFFECT 0x00000300
-+#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v) \
-+ (((v) << 8) & BM_AUDIOOUT_CTRL_SS3D_EFFECT)
-+#define BM_AUDIOOUT_CTRL_RSRVD1 0x00000080
-+#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
-+#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 0x00000020
-+#define BM_AUDIOOUT_CTRL_LOOPBACK 0x00000010
-+#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
-+#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
-+#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
-+#define BM_AUDIOOUT_CTRL_RUN 0x00000001
-+
-+#define HW_AUDIOOUT_STAT (0x00000010)
-+#define HW_AUDIOOUT_STAT_SET (0x00000014)
-+#define HW_AUDIOOUT_STAT_CLR (0x00000018)
-+#define HW_AUDIOOUT_STAT_TOG (0x0000001c)
-+
-+#define BM_AUDIOOUT_STAT_DAC_PRESENT 0x80000000
-+#define BP_AUDIOOUT_STAT_RSRVD1 0
-+#define BM_AUDIOOUT_STAT_RSRVD1 0x7FFFFFFF
-+#define BF_AUDIOOUT_STAT_RSRVD1(v) \
-+ (((v) << 0) & BM_AUDIOOUT_STAT_RSRVD1)
-+
-+#define HW_AUDIOOUT_DACSRR (0x00000020)
-+#define HW_AUDIOOUT_DACSRR_SET (0x00000024)
-+#define HW_AUDIOOUT_DACSRR_CLR (0x00000028)
-+#define HW_AUDIOOUT_DACSRR_TOG (0x0000002c)
-+
-+#define BM_AUDIOOUT_DACSRR_OSR 0x80000000
-+#define BV_AUDIOOUT_DACSRR_OSR__OSR6 0x0
-+#define BV_AUDIOOUT_DACSRR_OSR__OSR12 0x1
-+#define BP_AUDIOOUT_DACSRR_BASEMULT 28
-+#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
-+#define BF_AUDIOOUT_DACSRR_BASEMULT(v) \
-+ (((v) << 28) & BM_AUDIOOUT_DACSRR_BASEMULT)
-+#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE 0x1
-+#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE 0x2
-+#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE 0x4
-+#define BM_AUDIOOUT_DACSRR_RSRVD2 0x08000000
-+#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
-+#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
-+#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v) \
-+ (((v) << 24) & BM_AUDIOOUT_DACSRR_SRC_HOLD)
-+#define BP_AUDIOOUT_DACSRR_RSRVD1 21
-+#define BM_AUDIOOUT_DACSRR_RSRVD1 0x00E00000
-+#define BF_AUDIOOUT_DACSRR_RSRVD1(v) \
-+ (((v) << 21) & BM_AUDIOOUT_DACSRR_RSRVD1)
-+#define BP_AUDIOOUT_DACSRR_SRC_INT 16
-+#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
-+#define BF_AUDIOOUT_DACSRR_SRC_INT(v) \
-+ (((v) << 16) & BM_AUDIOOUT_DACSRR_SRC_INT)
-+#define BP_AUDIOOUT_DACSRR_RSRVD0 13
-+#define BM_AUDIOOUT_DACSRR_RSRVD0 0x0000E000
-+#define BF_AUDIOOUT_DACSRR_RSRVD0(v) \
-+ (((v) << 13) & BM_AUDIOOUT_DACSRR_RSRVD0)
-+#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
-+#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
-+#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v) \
-+ (((v) << 0) & BM_AUDIOOUT_DACSRR_SRC_FRAC)
-+
-+#define HW_AUDIOOUT_DACVOLUME (0x00000030)
-+#define HW_AUDIOOUT_DACVOLUME_SET (0x00000034)
-+#define HW_AUDIOOUT_DACVOLUME_CLR (0x00000038)
-+#define HW_AUDIOOUT_DACVOLUME_TOG (0x0000003c)
-+
-+#define BP_AUDIOOUT_DACVOLUME_RSRVD4 29
-+#define BM_AUDIOOUT_DACVOLUME_RSRVD4 0xE0000000
-+#define BF_AUDIOOUT_DACVOLUME_RSRVD4(v) \
-+ (((v) << 29) & BM_AUDIOOUT_DACVOLUME_RSRVD4)
-+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 0x10000000
-+#define BP_AUDIOOUT_DACVOLUME_RSRVD3 26
-+#define BM_AUDIOOUT_DACVOLUME_RSRVD3 0x0C000000
-+#define BF_AUDIOOUT_DACVOLUME_RSRVD3(v) \
-+ (((v) << 26) & BM_AUDIOOUT_DACVOLUME_RSRVD3)
-+#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
-+#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
-+#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT 16
-+#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT 0x00FF0000
-+#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) \
-+ (((v) << 16) & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT)
-+#define BP_AUDIOOUT_DACVOLUME_RSRVD2 13
-+#define BM_AUDIOOUT_DACVOLUME_RSRVD2 0x0000E000
-+#define BF_AUDIOOUT_DACVOLUME_RSRVD2(v) \
-+ (((v) << 13) & BM_AUDIOOUT_DACVOLUME_RSRVD2)
-+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 0x00001000
-+#define BP_AUDIOOUT_DACVOLUME_RSRVD1 9
-+#define BM_AUDIOOUT_DACVOLUME_RSRVD1 0x00000E00
-+#define BF_AUDIOOUT_DACVOLUME_RSRVD1(v) \
-+ (((v) << 9) & BM_AUDIOOUT_DACVOLUME_RSRVD1)
-+#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
-+#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0
-+#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0x000000FF
-+#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) \
-+ (((v) << 0) & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT)
-+
-+#define HW_AUDIOOUT_DACDEBUG (0x00000040)
-+#define HW_AUDIOOUT_DACDEBUG_SET (0x00000044)
-+#define HW_AUDIOOUT_DACDEBUG_CLR (0x00000048)
-+#define HW_AUDIOOUT_DACDEBUG_TOG (0x0000004c)
-+
-+#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 0x80000000
-+#define BP_AUDIOOUT_DACDEBUG_RSRVD2 12
-+#define BM_AUDIOOUT_DACDEBUG_RSRVD2 0x7FFFF000
-+#define BF_AUDIOOUT_DACDEBUG_RSRVD2(v) \
-+ (((v) << 12) & BM_AUDIOOUT_DACDEBUG_RSRVD2)
-+#define BP_AUDIOOUT_DACDEBUG_RAM_SS 8
-+#define BM_AUDIOOUT_DACDEBUG_RAM_SS 0x00000F00
-+#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v) \
-+ (((v) << 8) & BM_AUDIOOUT_DACDEBUG_RAM_SS)
-+#define BP_AUDIOOUT_DACDEBUG_RSRVD1 6
-+#define BM_AUDIOOUT_DACDEBUG_RSRVD1 0x000000C0
-+#define BF_AUDIOOUT_DACDEBUG_RSRVD1(v) \
-+ (((v) << 6) & BM_AUDIOOUT_DACDEBUG_RSRVD1)
-+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 0x00000020
-+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 0x00000010
-+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 0x00000008
-+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 0x00000004
-+#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ 0x00000002
-+#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS 0x00000001
-+
-+#define HW_AUDIOOUT_HPVOL (0x00000050)
-+#define HW_AUDIOOUT_HPVOL_SET (0x00000054)
-+#define HW_AUDIOOUT_HPVOL_CLR (0x00000058)
-+#define HW_AUDIOOUT_HPVOL_TOG (0x0000005c)
-+
-+#define BP_AUDIOOUT_HPVOL_RSRVD5 29
-+#define BM_AUDIOOUT_HPVOL_RSRVD5 0xE0000000
-+#define BF_AUDIOOUT_HPVOL_RSRVD5(v) \
-+ (((v) << 29) & BM_AUDIOOUT_HPVOL_RSRVD5)
-+#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 0x10000000
-+#define BP_AUDIOOUT_HPVOL_RSRVD4 26
-+#define BM_AUDIOOUT_HPVOL_RSRVD4 0x0C000000
-+#define BF_AUDIOOUT_HPVOL_RSRVD4(v) \
-+ (((v) << 26) & BM_AUDIOOUT_HPVOL_RSRVD4)
-+#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
-+#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
-+#define BP_AUDIOOUT_HPVOL_RSRVD3 17
-+#define BM_AUDIOOUT_HPVOL_RSRVD3 0x00FE0000
-+#define BF_AUDIOOUT_HPVOL_RSRVD3(v) \
-+ (((v) << 17) & BM_AUDIOOUT_HPVOL_RSRVD3)
-+#define BM_AUDIOOUT_HPVOL_SELECT 0x00010000
-+#define BM_AUDIOOUT_HPVOL_RSRVD2 0x00008000
-+#define BP_AUDIOOUT_HPVOL_VOL_LEFT 8
-+#define BM_AUDIOOUT_HPVOL_VOL_LEFT 0x00007F00
-+#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v) \
-+ (((v) << 8) & BM_AUDIOOUT_HPVOL_VOL_LEFT)
-+#define BM_AUDIOOUT_HPVOL_RSRVD1 0x00000080
-+#define BP_AUDIOOUT_HPVOL_VOL_RIGHT 0
-+#define BM_AUDIOOUT_HPVOL_VOL_RIGHT 0x0000007F
-+#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v) \
-+ (((v) << 0) & BM_AUDIOOUT_HPVOL_VOL_RIGHT)
-+
-+#define HW_AUDIOOUT_RESERVED (0x00000060)
-+#define HW_AUDIOOUT_RESERVED_SET (0x00000064)
-+#define HW_AUDIOOUT_RESERVED_CLR (0x00000068)
-+#define HW_AUDIOOUT_RESERVED_TOG (0x0000006c)
-+
-+#define BP_AUDIOOUT_RESERVED_RSRVD1 0
-+#define BM_AUDIOOUT_RESERVED_RSRVD1 0xFFFFFFFF
-+#define BF_AUDIOOUT_RESERVED_RSRVD1(v) (v)
-+
-+#define HW_AUDIOOUT_PWRDN (0x00000070)
-+#define HW_AUDIOOUT_PWRDN_SET (0x00000074)
-+#define HW_AUDIOOUT_PWRDN_CLR (0x00000078)
-+#define HW_AUDIOOUT_PWRDN_TOG (0x0000007c)
-+
-+#define BP_AUDIOOUT_PWRDN_RSRVD7 25
-+#define BM_AUDIOOUT_PWRDN_RSRVD7 0xFE000000
-+#define BF_AUDIOOUT_PWRDN_RSRVD7(v) \
-+ (((v) << 25) & BM_AUDIOOUT_PWRDN_RSRVD7)
-+#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000
-+#define BP_AUDIOOUT_PWRDN_RSRVD6 21
-+#define BM_AUDIOOUT_PWRDN_RSRVD6 0x00E00000
-+#define BF_AUDIOOUT_PWRDN_RSRVD6(v) \
-+ (((v) << 21) & BM_AUDIOOUT_PWRDN_RSRVD6)
-+#define BM_AUDIOOUT_PWRDN_SELFBIAS 0x00100000
-+#define BP_AUDIOOUT_PWRDN_RSRVD5 17
-+#define BM_AUDIOOUT_PWRDN_RSRVD5 0x000E0000
-+#define BF_AUDIOOUT_PWRDN_RSRVD5(v) \
-+ (((v) << 17) & BM_AUDIOOUT_PWRDN_RSRVD5)
-+#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
-+#define BP_AUDIOOUT_PWRDN_RSRVD4 13
-+#define BM_AUDIOOUT_PWRDN_RSRVD4 0x0000E000
-+#define BF_AUDIOOUT_PWRDN_RSRVD4(v) \
-+ (((v) << 13) & BM_AUDIOOUT_PWRDN_RSRVD4)
-+#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
-+#define BP_AUDIOOUT_PWRDN_RSRVD3 9
-+#define BM_AUDIOOUT_PWRDN_RSRVD3 0x00000E00
-+#define BF_AUDIOOUT_PWRDN_RSRVD3(v) \
-+ (((v) << 9) & BM_AUDIOOUT_PWRDN_RSRVD3)
-+#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
-+#define BP_AUDIOOUT_PWRDN_RSRVD2 5
-+#define BM_AUDIOOUT_PWRDN_RSRVD2 0x000000E0
-+#define BF_AUDIOOUT_PWRDN_RSRVD2(v) \
-+ (((v) << 5) & BM_AUDIOOUT_PWRDN_RSRVD2)
-+#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
-+#define BP_AUDIOOUT_PWRDN_RSRVD1 1
-+#define BM_AUDIOOUT_PWRDN_RSRVD1 0x0000000E
-+#define BF_AUDIOOUT_PWRDN_RSRVD1(v) \
-+ (((v) << 1) & BM_AUDIOOUT_PWRDN_RSRVD1)
-+#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
-+
-+#define HW_AUDIOOUT_REFCTRL (0x00000080)
-+#define HW_AUDIOOUT_REFCTRL_SET (0x00000084)
-+#define HW_AUDIOOUT_REFCTRL_CLR (0x00000088)
-+#define HW_AUDIOOUT_REFCTRL_TOG (0x0000008c)
-+
-+#define BP_AUDIOOUT_REFCTRL_RSRVD4 27
-+#define BM_AUDIOOUT_REFCTRL_RSRVD4 0xF8000000
-+#define BF_AUDIOOUT_REFCTRL_RSRVD4(v) \
-+ (((v) << 27) & BM_AUDIOOUT_REFCTRL_RSRVD4)
-+#define BM_AUDIOOUT_REFCTRL_FASTSETTLING 0x04000000
-+#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
-+#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
-+#define BM_AUDIOOUT_REFCTRL_RSRVD3 0x00800000
-+#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
-+#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
-+#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v) \
-+ (((v) << 20) & BM_AUDIOOUT_REFCTRL_VBG_ADJ)
-+#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
-+#define BM_AUDIOOUT_REFCTRL_LW_REF 0x00040000
-+#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
-+#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
-+#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v) \
-+ (((v) << 16) & BM_AUDIOOUT_REFCTRL_BIAS_CTRL)
-+#define BM_AUDIOOUT_REFCTRL_RSRVD2 0x00008000
-+#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 0x00004000
-+#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
-+#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
-+#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
-+#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
-+#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v) \
-+ (((v) << 8) & BM_AUDIOOUT_REFCTRL_ADC_REFVAL)
-+#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
-+#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
-+#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v) \
-+ (((v) << 4) & BM_AUDIOOUT_REFCTRL_VAG_VAL)
-+#define BM_AUDIOOUT_REFCTRL_RSRVD1 0x00000008
-+#define BP_AUDIOOUT_REFCTRL_DAC_ADJ 0
-+#define BM_AUDIOOUT_REFCTRL_DAC_ADJ 0x00000007
-+#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v) \
-+ (((v) << 0) & BM_AUDIOOUT_REFCTRL_DAC_ADJ)
-+
-+#define HW_AUDIOOUT_ANACTRL (0x00000090)
-+#define HW_AUDIOOUT_ANACTRL_SET (0x00000094)
-+#define HW_AUDIOOUT_ANACTRL_CLR (0x00000098)
-+#define HW_AUDIOOUT_ANACTRL_TOG (0x0000009c)
-+
-+#define BP_AUDIOOUT_ANACTRL_RSRVD8 29
-+#define BM_AUDIOOUT_ANACTRL_RSRVD8 0xE0000000
-+#define BF_AUDIOOUT_ANACTRL_RSRVD8(v) \
-+ (((v) << 29) & BM_AUDIOOUT_ANACTRL_RSRVD8)
-+#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS 0x10000000
-+#define BP_AUDIOOUT_ANACTRL_RSRVD7 25
-+#define BM_AUDIOOUT_ANACTRL_RSRVD7 0x0E000000
-+#define BF_AUDIOOUT_ANACTRL_RSRVD7(v) \
-+ (((v) << 25) & BM_AUDIOOUT_ANACTRL_RSRVD7)
-+#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS 0x01000000
-+#define BP_AUDIOOUT_ANACTRL_RSRVD6 22
-+#define BM_AUDIOOUT_ANACTRL_RSRVD6 0x00C00000
-+#define BF_AUDIOOUT_ANACTRL_RSRVD6(v) \
-+ (((v) << 22) & BM_AUDIOOUT_ANACTRL_RSRVD6)
-+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM 20
-+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM 0x00300000
-+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) \
-+ (((v) << 20) & BM_AUDIOOUT_ANACTRL_SHORTMODE_CM)
-+#define BM_AUDIOOUT_ANACTRL_RSRVD5 0x00080000
-+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR 17
-+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR 0x00060000
-+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) \
-+ (((v) << 17) & BM_AUDIOOUT_ANACTRL_SHORTMODE_LR)
-+#define BP_AUDIOOUT_ANACTRL_RSRVD4 15
-+#define BM_AUDIOOUT_ANACTRL_RSRVD4 0x00018000
-+#define BF_AUDIOOUT_ANACTRL_RSRVD4(v) \
-+ (((v) << 15) & BM_AUDIOOUT_ANACTRL_RSRVD4)
-+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL 12
-+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL 0x00007000
-+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) \
-+ (((v) << 12) & BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL)
-+#define BM_AUDIOOUT_ANACTRL_RSRVD3 0x00000800
-+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR 8
-+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR 0x00000700
-+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) \
-+ (((v) << 8) & BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR)
-+#define BP_AUDIOOUT_ANACTRL_RSRVD2 6
-+#define BM_AUDIOOUT_ANACTRL_RSRVD2 0x000000C0
-+#define BF_AUDIOOUT_ANACTRL_RSRVD2(v) \
-+ (((v) << 6) & BM_AUDIOOUT_ANACTRL_RSRVD2)
-+#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
-+#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
-+#define BP_AUDIOOUT_ANACTRL_RSRVD1 0
-+#define BM_AUDIOOUT_ANACTRL_RSRVD1 0x0000000F
-+#define BF_AUDIOOUT_ANACTRL_RSRVD1(v) \
-+ (((v) << 0) & BM_AUDIOOUT_ANACTRL_RSRVD1)
-+
-+#define HW_AUDIOOUT_TEST (0x000000a0)
-+#define HW_AUDIOOUT_TEST_SET (0x000000a4)
-+#define HW_AUDIOOUT_TEST_CLR (0x000000a8)
-+#define HW_AUDIOOUT_TEST_TOG (0x000000ac)
-+
-+#define BM_AUDIOOUT_TEST_RSRVD4 0x80000000
-+#define BP_AUDIOOUT_TEST_HP_ANTIPOP 28
-+#define BM_AUDIOOUT_TEST_HP_ANTIPOP 0x70000000
-+#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v) \
-+ (((v) << 28) & BM_AUDIOOUT_TEST_HP_ANTIPOP)
-+#define BM_AUDIOOUT_TEST_RSRVD3 0x08000000
-+#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP 0x04000000
-+#define BM_AUDIOOUT_TEST_TM_LOOP 0x02000000
-+#define BM_AUDIOOUT_TEST_TM_HPCOMMON 0x01000000
-+#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
-+#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
-+#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v) \
-+ (((v) << 22) & BM_AUDIOOUT_TEST_HP_I1_ADJ)
-+#define BP_AUDIOOUT_TEST_HP_IALL_ADJ 20
-+#define BM_AUDIOOUT_TEST_HP_IALL_ADJ 0x00300000
-+#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v) \
-+ (((v) << 20) & BM_AUDIOOUT_TEST_HP_IALL_ADJ)
-+#define BP_AUDIOOUT_TEST_RSRVD2 14
-+#define BM_AUDIOOUT_TEST_RSRVD2 0x000FC000
-+#define BF_AUDIOOUT_TEST_RSRVD2(v) \
-+ (((v) << 14) & BM_AUDIOOUT_TEST_RSRVD2)
-+#define BM_AUDIOOUT_TEST_VAG_CLASSA 0x00002000
-+#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I 0x00001000
-+#define BP_AUDIOOUT_TEST_RSRVD1 4
-+#define BM_AUDIOOUT_TEST_RSRVD1 0x00000FF0
-+#define BF_AUDIOOUT_TEST_RSRVD1(v) \
-+ (((v) << 4) & BM_AUDIOOUT_TEST_RSRVD1)
-+#define BM_AUDIOOUT_TEST_ADCTODAC_LOOP 0x00000008
-+#define BM_AUDIOOUT_TEST_DAC_CLASSA 0x00000004
-+#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I 0x00000002
-+#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ 0x00000001
-+
-+#define HW_AUDIOOUT_BISTCTRL (0x000000b0)
-+#define HW_AUDIOOUT_BISTCTRL_SET (0x000000b4)
-+#define HW_AUDIOOUT_BISTCTRL_CLR (0x000000b8)
-+#define HW_AUDIOOUT_BISTCTRL_TOG (0x000000bc)
-+
-+#define BP_AUDIOOUT_BISTCTRL_RSVD0 4
-+#define BM_AUDIOOUT_BISTCTRL_RSVD0 0xFFFFFFF0
-+#define BF_AUDIOOUT_BISTCTRL_RSVD0(v) \
-+ (((v) << 4) & BM_AUDIOOUT_BISTCTRL_RSVD0)
-+#define BM_AUDIOOUT_BISTCTRL_FAIL 0x00000008
-+#define BM_AUDIOOUT_BISTCTRL_PASS 0x00000004
-+#define BM_AUDIOOUT_BISTCTRL_DONE 0x00000002
-+#define BM_AUDIOOUT_BISTCTRL_START 0x00000001
-+
-+#define HW_AUDIOOUT_BISTSTAT0 (0x000000c0)
-+#define HW_AUDIOOUT_BISTSTAT0_SET (0x000000c4)
-+#define HW_AUDIOOUT_BISTSTAT0_CLR (0x000000c8)
-+#define HW_AUDIOOUT_BISTSTAT0_TOG (0x000000cc)
-+
-+#define BP_AUDIOOUT_BISTSTAT0_RSVD0 24
-+#define BM_AUDIOOUT_BISTSTAT0_RSVD0 0xFF000000
-+#define BF_AUDIOOUT_BISTSTAT0_RSVD0(v) \
-+ (((v) << 24) & BM_AUDIOOUT_BISTSTAT0_RSVD0)
-+#define BP_AUDIOOUT_BISTSTAT0_DATA 0
-+#define BM_AUDIOOUT_BISTSTAT0_DATA 0x00FFFFFF
-+#define BF_AUDIOOUT_BISTSTAT0_DATA(v) \
-+ (((v) << 0) & BM_AUDIOOUT_BISTSTAT0_DATA)
-+
-+#define HW_AUDIOOUT_BISTSTAT1 (0x000000d0)
-+#define HW_AUDIOOUT_BISTSTAT1_SET (0x000000d4)
-+#define HW_AUDIOOUT_BISTSTAT1_CLR (0x000000d8)
-+#define HW_AUDIOOUT_BISTSTAT1_TOG (0x000000dc)
-+
-+#define BP_AUDIOOUT_BISTSTAT1_RSVD1 29
-+#define BM_AUDIOOUT_BISTSTAT1_RSVD1 0xE0000000
-+#define BF_AUDIOOUT_BISTSTAT1_RSVD1(v) \
-+ (((v) << 29) & BM_AUDIOOUT_BISTSTAT1_RSVD1)
-+#define BP_AUDIOOUT_BISTSTAT1_STATE 24
-+#define BM_AUDIOOUT_BISTSTAT1_STATE 0x1F000000
-+#define BF_AUDIOOUT_BISTSTAT1_STATE(v) \
-+ (((v) << 24) & BM_AUDIOOUT_BISTSTAT1_STATE)
-+#define BP_AUDIOOUT_BISTSTAT1_RSVD0 8
-+#define BM_AUDIOOUT_BISTSTAT1_RSVD0 0x00FFFF00
-+#define BF_AUDIOOUT_BISTSTAT1_RSVD0(v) \
-+ (((v) << 8) & BM_AUDIOOUT_BISTSTAT1_RSVD0)
-+#define BP_AUDIOOUT_BISTSTAT1_ADDR 0
-+#define BM_AUDIOOUT_BISTSTAT1_ADDR 0x000000FF
-+#define BF_AUDIOOUT_BISTSTAT1_ADDR(v) \
-+ (((v) << 0) & BM_AUDIOOUT_BISTSTAT1_ADDR)
-+
-+#define HW_AUDIOOUT_ANACLKCTRL (0x000000e0)
-+#define HW_AUDIOOUT_ANACLKCTRL_SET (0x000000e4)
-+#define HW_AUDIOOUT_ANACLKCTRL_CLR (0x000000e8)
-+#define HW_AUDIOOUT_ANACLKCTRL_TOG (0x000000ec)
-+
-+#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
-+#define BP_AUDIOOUT_ANACLKCTRL_RSRVD3 5
-+#define BM_AUDIOOUT_ANACLKCTRL_RSRVD3 0x7FFFFFE0
-+#define BF_AUDIOOUT_ANACLKCTRL_RSRVD3(v) \
-+ (((v) << 5) & BM_AUDIOOUT_ANACLKCTRL_RSRVD3)
-+#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 0x00000010
-+#define BM_AUDIOOUT_ANACLKCTRL_RSRVD2 0x00000008
-+#define BP_AUDIOOUT_ANACLKCTRL_DACDIV 0
-+#define BM_AUDIOOUT_ANACLKCTRL_DACDIV 0x00000007
-+#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v) \
-+ (((v) << 0) & BM_AUDIOOUT_ANACLKCTRL_DACDIV)
-+
-+#define HW_AUDIOOUT_DATA (0x000000f0)
-+#define HW_AUDIOOUT_DATA_SET (0x000000f4)
-+#define HW_AUDIOOUT_DATA_CLR (0x000000f8)
-+#define HW_AUDIOOUT_DATA_TOG (0x000000fc)
-+
-+#define BP_AUDIOOUT_DATA_HIGH 16
-+#define BM_AUDIOOUT_DATA_HIGH 0xFFFF0000
-+#define BF_AUDIOOUT_DATA_HIGH(v) \
-+ (((v) << 16) & BM_AUDIOOUT_DATA_HIGH)
-+#define BP_AUDIOOUT_DATA_LOW 0
-+#define BM_AUDIOOUT_DATA_LOW 0x0000FFFF
-+#define BF_AUDIOOUT_DATA_LOW(v) \
-+ (((v) << 0) & BM_AUDIOOUT_DATA_LOW)
-+
-+#define HW_AUDIOOUT_SPEAKERCTRL (0x00000100)
-+#define HW_AUDIOOUT_SPEAKERCTRL_SET (0x00000104)
-+#define HW_AUDIOOUT_SPEAKERCTRL_CLR (0x00000108)
-+#define HW_AUDIOOUT_SPEAKERCTRL_TOG (0x0000010c)
-+
-+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD2 25
-+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD2 0xFE000000
-+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(v) \
-+ (((v) << 25) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD2)
-+#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000
-+#define BP_AUDIOOUT_SPEAKERCTRL_I1_ADJ 22
-+#define BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ 0x00C00000
-+#define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v) \
-+ (((v) << 22) & BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ)
-+#define BP_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 20
-+#define BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 0x00300000
-+#define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v) \
-+ (((v) << 20) & BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ)
-+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD1 16
-+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD1 0x000F0000
-+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(v) \
-+ (((v) << 16) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD1)
-+#define BP_AUDIOOUT_SPEAKERCTRL_POSDRIVER 14
-+#define BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER 0x0000C000
-+#define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v) \
-+ (((v) << 14) & BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER)
-+#define BP_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 12
-+#define BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 0x00003000
-+#define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v) \
-+ (((v) << 12) & BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER)
-+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD0 0
-+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD0 0x00000FFF
-+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(v) \
-+ (((v) << 0) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD0)
-+
-+#define HW_AUDIOOUT_VERSION (0x00000200)
-+
-+#define BP_AUDIOOUT_VERSION_MAJOR 24
-+#define BM_AUDIOOUT_VERSION_MAJOR 0xFF000000
-+#define BF_AUDIOOUT_VERSION_MAJOR(v) \
-+ (((v) << 24) & BM_AUDIOOUT_VERSION_MAJOR)
-+#define BP_AUDIOOUT_VERSION_MINOR 16
-+#define BM_AUDIOOUT_VERSION_MINOR 0x00FF0000
-+#define BF_AUDIOOUT_VERSION_MINOR(v) \
-+ (((v) << 16) & BM_AUDIOOUT_VERSION_MINOR)
-+#define BP_AUDIOOUT_VERSION_STEP 0
-+#define BM_AUDIOOUT_VERSION_STEP 0x0000FFFF
-+#define BF_AUDIOOUT_VERSION_STEP(v) \
-+ (((v) << 0) & BM_AUDIOOUT_VERSION_STEP)
-+
-+/* AUDIOIN */
-+#define HW_AUDIOIN_CTRL (0x00000000)
-+#define HW_AUDIOIN_CTRL_SET (0x00000004)
-+#define HW_AUDIOIN_CTRL_CLR (0x00000008)
-+#define HW_AUDIOIN_CTRL_TOG (0x0000000c)
-+
-+#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
-+#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
-+#define BP_AUDIOIN_CTRL_RSRVD3 21
-+#define BM_AUDIOIN_CTRL_RSRVD3 0x3FE00000
-+#define BF_AUDIOIN_CTRL_RSRVD3(v) \
-+ (((v) << 21) & BM_AUDIOIN_CTRL_RSRVD3)
-+#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT 16
-+#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT 0x001F0000
-+#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v) \
-+ (((v) << 16) & BM_AUDIOIN_CTRL_DMAWAIT_COUNT)
-+#define BP_AUDIOIN_CTRL_RSRVD1 11
-+#define BM_AUDIOIN_CTRL_RSRVD1 0x0000F800
-+#define BF_AUDIOIN_CTRL_RSRVD1(v) \
-+ (((v) << 11) & BM_AUDIOIN_CTRL_RSRVD1)
-+#define BM_AUDIOIN_CTRL_LR_SWAP 0x00000400
-+#define BM_AUDIOIN_CTRL_EDGE_SYNC 0x00000200
-+#define BM_AUDIOIN_CTRL_INVERT_1BIT 0x00000100
-+#define BM_AUDIOIN_CTRL_OFFSET_ENABLE 0x00000080
-+#define BM_AUDIOIN_CTRL_HPF_ENABLE 0x00000040
-+#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
-+#define BM_AUDIOIN_CTRL_LOOPBACK 0x00000010
-+#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
-+#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
-+#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
-+#define BM_AUDIOIN_CTRL_RUN 0x00000001
-+
-+#define HW_AUDIOIN_STAT (0x00000010)
-+#define HW_AUDIOIN_STAT_SET (0x00000014)
-+#define HW_AUDIOIN_STAT_CLR (0x00000018)
-+#define HW_AUDIOIN_STAT_TOG (0x0000001c)
-+
-+#define BM_AUDIOIN_STAT_ADC_PRESENT 0x80000000
-+#define BP_AUDIOIN_STAT_RSRVD3 0
-+#define BM_AUDIOIN_STAT_RSRVD3 0x7FFFFFFF
-+#define BF_AUDIOIN_STAT_RSRVD3(v) \
-+ (((v) << 0) & BM_AUDIOIN_STAT_RSRVD3)
-+
-+#define HW_AUDIOIN_ADCSRR (0x00000020)
-+#define HW_AUDIOIN_ADCSRR_SET (0x00000024)
-+#define HW_AUDIOIN_ADCSRR_CLR (0x00000028)
-+#define HW_AUDIOIN_ADCSRR_TOG (0x0000002c)
-+
-+#define BM_AUDIOIN_ADCSRR_OSR 0x80000000
-+#define BV_AUDIOIN_ADCSRR_OSR__OSR6 0x0
-+#define BV_AUDIOIN_ADCSRR_OSR__OSR12 0x1
-+#define BP_AUDIOIN_ADCSRR_BASEMULT 28
-+#define BM_AUDIOIN_ADCSRR_BASEMULT 0x70000000
-+#define BF_AUDIOIN_ADCSRR_BASEMULT(v) \
-+ (((v) << 28) & BM_AUDIOIN_ADCSRR_BASEMULT)
-+#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1
-+#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2
-+#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE 0x4
-+#define BM_AUDIOIN_ADCSRR_RSRVD2 0x08000000
-+#define BP_AUDIOIN_ADCSRR_SRC_HOLD 24
-+#define BM_AUDIOIN_ADCSRR_SRC_HOLD 0x07000000
-+#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v) \
-+ (((v) << 24) & BM_AUDIOIN_ADCSRR_SRC_HOLD)
-+#define BP_AUDIOIN_ADCSRR_RSRVD1 21
-+#define BM_AUDIOIN_ADCSRR_RSRVD1 0x00E00000
-+#define BF_AUDIOIN_ADCSRR_RSRVD1(v) \
-+ (((v) << 21) & BM_AUDIOIN_ADCSRR_RSRVD1)
-+#define BP_AUDIOIN_ADCSRR_SRC_INT 16
-+#define BM_AUDIOIN_ADCSRR_SRC_INT 0x001F0000
-+#define BF_AUDIOIN_ADCSRR_SRC_INT(v) \
-+ (((v) << 16) & BM_AUDIOIN_ADCSRR_SRC_INT)
-+#define BP_AUDIOIN_ADCSRR_RSRVD0 13
-+#define BM_AUDIOIN_ADCSRR_RSRVD0 0x0000E000
-+#define BF_AUDIOIN_ADCSRR_RSRVD0(v) \
-+ (((v) << 13) & BM_AUDIOIN_ADCSRR_RSRVD0)
-+#define BP_AUDIOIN_ADCSRR_SRC_FRAC 0
-+#define BM_AUDIOIN_ADCSRR_SRC_FRAC 0x00001FFF
-+#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v) \
-+ (((v) << 0) & BM_AUDIOIN_ADCSRR_SRC_FRAC)
-+
-+#define HW_AUDIOIN_ADCVOLUME (0x00000030)
-+#define HW_AUDIOIN_ADCVOLUME_SET (0x00000034)
-+#define HW_AUDIOIN_ADCVOLUME_CLR (0x00000038)
-+#define HW_AUDIOIN_ADCVOLUME_TOG (0x0000003c)
-+
-+#define BP_AUDIOIN_ADCVOLUME_RSRVD5 29
-+#define BM_AUDIOIN_ADCVOLUME_RSRVD5 0xE0000000
-+#define BF_AUDIOIN_ADCVOLUME_RSRVD5(v) \
-+ (((v) << 29) & BM_AUDIOIN_ADCVOLUME_RSRVD5)
-+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 0x10000000
-+#define BP_AUDIOIN_ADCVOLUME_RSRVD4 26
-+#define BM_AUDIOIN_ADCVOLUME_RSRVD4 0x0C000000
-+#define BF_AUDIOIN_ADCVOLUME_RSRVD4(v) \
-+ (((v) << 26) & BM_AUDIOIN_ADCVOLUME_RSRVD4)
-+#define BM_AUDIOIN_ADCVOLUME_EN_ZCD 0x02000000
-+#define BM_AUDIOIN_ADCVOLUME_RSRVD3 0x01000000
-+#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
-+#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
-+#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) \
-+ (((v) << 16) & BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT)
-+#define BP_AUDIOIN_ADCVOLUME_RSRVD2 13
-+#define BM_AUDIOIN_ADCVOLUME_RSRVD2 0x0000E000
-+#define BF_AUDIOIN_ADCVOLUME_RSRVD2(v) \
-+ (((v) << 13) & BM_AUDIOIN_ADCVOLUME_RSRVD2)
-+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 0x00001000
-+#define BP_AUDIOIN_ADCVOLUME_RSRVD1 8
-+#define BM_AUDIOIN_ADCVOLUME_RSRVD1 0x00000F00
-+#define BF_AUDIOIN_ADCVOLUME_RSRVD1(v) \
-+ (((v) << 8) & BM_AUDIOIN_ADCVOLUME_RSRVD1)
-+#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
-+#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
-+#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) \
-+ (((v) << 0) & BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT)
-+
-+#define HW_AUDIOIN_ADCDEBUG (0x00000040)
-+#define HW_AUDIOIN_ADCDEBUG_SET (0x00000044)
-+#define HW_AUDIOIN_ADCDEBUG_CLR (0x00000048)
-+#define HW_AUDIOIN_ADCDEBUG_TOG (0x0000004c)
-+
-+#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 0x80000000
-+#define BP_AUDIOIN_ADCDEBUG_RSRVD1 4
-+#define BM_AUDIOIN_ADCDEBUG_RSRVD1 0x7FFFFFF0
-+#define BF_AUDIOIN_ADCDEBUG_RSRVD1(v) \
-+ (((v) << 4) & BM_AUDIOIN_ADCDEBUG_RSRVD1)
-+#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0x00000008
-+#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 0x00000004
-+#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ 0x00000002
-+#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS 0x00000001
-+
-+#define HW_AUDIOIN_ADCVOL (0x00000050)
-+#define HW_AUDIOIN_ADCVOL_SET (0x00000054)
-+#define HW_AUDIOIN_ADCVOL_CLR (0x00000058)
-+#define HW_AUDIOIN_ADCVOL_TOG (0x0000005c)
-+
-+#define BP_AUDIOIN_ADCVOL_RSRVD4 29
-+#define BM_AUDIOIN_ADCVOL_RSRVD4 0xE0000000
-+#define BF_AUDIOIN_ADCVOL_RSRVD4(v) \
-+ (((v) << 29) & BM_AUDIOIN_ADCVOL_RSRVD4)
-+#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 0x10000000
-+#define BP_AUDIOIN_ADCVOL_RSRVD3 26
-+#define BM_AUDIOIN_ADCVOL_RSRVD3 0x0C000000
-+#define BF_AUDIOIN_ADCVOL_RSRVD3(v) \
-+ (((v) << 26) & BM_AUDIOIN_ADCVOL_RSRVD3)
-+#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD 0x02000000
-+#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
-+#define BP_AUDIOIN_ADCVOL_RSRVD2 14
-+#define BM_AUDIOIN_ADCVOL_RSRVD2 0x00FFC000
-+#define BF_AUDIOIN_ADCVOL_RSRVD2(v) \
-+ (((v) << 14) & BM_AUDIOIN_ADCVOL_RSRVD2)
-+#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
-+#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
-+#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v) \
-+ (((v) << 12) & BM_AUDIOIN_ADCVOL_SELECT_LEFT)
-+#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
-+#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
-+#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v) \
-+ (((v) << 8) & BM_AUDIOIN_ADCVOL_GAIN_LEFT)
-+#define BP_AUDIOIN_ADCVOL_RSRVD1 6
-+#define BM_AUDIOIN_ADCVOL_RSRVD1 0x000000C0
-+#define BF_AUDIOIN_ADCVOL_RSRVD1(v) \
-+ (((v) << 6) & BM_AUDIOIN_ADCVOL_RSRVD1)
-+#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
-+#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
-+#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v) \
-+ (((v) << 4) & BM_AUDIOIN_ADCVOL_SELECT_RIGHT)
-+#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
-+#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
-+#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v) \
-+ (((v) << 0) & BM_AUDIOIN_ADCVOL_GAIN_RIGHT)
-+
-+#define HW_AUDIOIN_MICLINE (0x00000060)
-+#define HW_AUDIOIN_MICLINE_SET (0x00000064)
-+#define HW_AUDIOIN_MICLINE_CLR (0x00000068)
-+#define HW_AUDIOIN_MICLINE_TOG (0x0000006c)
-+
-+#define BP_AUDIOIN_MICLINE_RSRVD6 30
-+#define BM_AUDIOIN_MICLINE_RSRVD6 0xC0000000
-+#define BF_AUDIOIN_MICLINE_RSRVD6(v) \
-+ (((v) << 30) & BM_AUDIOIN_MICLINE_RSRVD6)
-+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1 0x20000000
-+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2 0x10000000
-+#define BP_AUDIOIN_MICLINE_RSRVD5 25
-+#define BM_AUDIOIN_MICLINE_RSRVD5 0x0E000000
-+#define BF_AUDIOIN_MICLINE_RSRVD5(v) \
-+ (((v) << 25) & BM_AUDIOIN_MICLINE_RSRVD5)
-+#define BM_AUDIOIN_MICLINE_MIC_SELECT 0x01000000
-+#define BP_AUDIOIN_MICLINE_RSRVD4 22
-+#define BM_AUDIOIN_MICLINE_RSRVD4 0x00C00000
-+#define BF_AUDIOIN_MICLINE_RSRVD4(v) \
-+ (((v) << 22) & BM_AUDIOIN_MICLINE_RSRVD4)
-+#define BP_AUDIOIN_MICLINE_MIC_RESISTOR 20
-+#define BM_AUDIOIN_MICLINE_MIC_RESISTOR 0x00300000
-+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v) \
-+ (((v) << 20) & BM_AUDIOIN_MICLINE_MIC_RESISTOR)
-+#define BM_AUDIOIN_MICLINE_RSRVD3 0x00080000
-+#define BP_AUDIOIN_MICLINE_MIC_BIAS 16
-+#define BM_AUDIOIN_MICLINE_MIC_BIAS 0x00070000
-+#define BF_AUDIOIN_MICLINE_MIC_BIAS(v) \
-+ (((v) << 16) & BM_AUDIOIN_MICLINE_MIC_BIAS)
-+#define BP_AUDIOIN_MICLINE_RSRVD2 6
-+#define BM_AUDIOIN_MICLINE_RSRVD2 0x0000FFC0
-+#define BF_AUDIOIN_MICLINE_RSRVD2(v) \
-+ (((v) << 6) & BM_AUDIOIN_MICLINE_RSRVD2)
-+#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK 4
-+#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK 0x00000030
-+#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v) \
-+ (((v) << 4) & BM_AUDIOIN_MICLINE_MIC_CHOPCLK)
-+#define BP_AUDIOIN_MICLINE_RSRVD1 2
-+#define BM_AUDIOIN_MICLINE_RSRVD1 0x0000000C
-+#define BF_AUDIOIN_MICLINE_RSRVD1(v) \
-+ (((v) << 2) & BM_AUDIOIN_MICLINE_RSRVD1)
-+#define BP_AUDIOIN_MICLINE_MIC_GAIN 0
-+#define BM_AUDIOIN_MICLINE_MIC_GAIN 0x00000003
-+#define BF_AUDIOIN_MICLINE_MIC_GAIN(v) \
-+ (((v) << 0) & BM_AUDIOIN_MICLINE_MIC_GAIN)
-+
-+#define HW_AUDIOIN_ANACLKCTRL (0x00000070)
-+#define HW_AUDIOIN_ANACLKCTRL_SET (0x00000074)
-+#define HW_AUDIOIN_ANACLKCTRL_CLR (0x00000078)
-+#define HW_AUDIOIN_ANACLKCTRL_TOG (0x0000007c)
-+
-+#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
-+#define BP_AUDIOIN_ANACLKCTRL_RSRVD4 11
-+#define BM_AUDIOIN_ANACLKCTRL_RSRVD4 0x7FFFF800
-+#define BF_AUDIOIN_ANACLKCTRL_RSRVD4(v) \
-+ (((v) << 11) & BM_AUDIOIN_ANACLKCTRL_RSRVD4)
-+#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF 0x00000400
-+#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER 0x00000200
-+#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 0x00000100
-+#define BP_AUDIOIN_ANACLKCTRL_RSRVD3 6
-+#define BM_AUDIOIN_ANACLKCTRL_RSRVD3 0x000000C0
-+#define BF_AUDIOIN_ANACLKCTRL_RSRVD3(v) \
-+ (((v) << 6) & BM_AUDIOIN_ANACLKCTRL_RSRVD3)
-+#define BP_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 4
-+#define BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 0x00000030
-+#define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v) \
-+ (((v) << 4) & BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT)
-+#define BM_AUDIOIN_ANACLKCTRL_RSRVD2 0x00000008
-+#define BP_AUDIOIN_ANACLKCTRL_ADCDIV 0
-+#define BM_AUDIOIN_ANACLKCTRL_ADCDIV 0x00000007
-+#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v) \
-+ (((v) << 0) & BM_AUDIOIN_ANACLKCTRL_ADCDIV)
-+
-+#define HW_AUDIOIN_DATA (0x00000080)
-+#define HW_AUDIOIN_DATA_SET (0x00000084)
-+#define HW_AUDIOIN_DATA_CLR (0x00000088)
-+#define HW_AUDIOIN_DATA_TOG (0x0000008c)
-+
-+#define BP_AUDIOIN_DATA_HIGH 16
-+#define BM_AUDIOIN_DATA_HIGH 0xFFFF0000
-+#define BF_AUDIOIN_DATA_HIGH(v) \
-+ (((v) << 16) & BM_AUDIOIN_DATA_HIGH)
-+#define BP_AUDIOIN_DATA_LOW 0
-+#define BM_AUDIOIN_DATA_LOW 0x0000FFFF
-+#define BF_AUDIOIN_DATA_LOW(v) \
-+ (((v) << 0) & BM_AUDIOIN_DATA_LOW)
-+
-+#define BV_AUDIOIN_ADCVOL_SELECT__MIC 0x00
-+
-+#endif /* __MXS_ADC_CODEC_H */
---- a/sound/soc/mxs/Kconfig
-+++ b/sound/soc/mxs/Kconfig
-@@ -18,3 +18,13 @@ config SND_SOC_MXS_SGTL5000
- a sgtl5000 codec.
-
- endif # SND_MXS_SOC
-+
-+
-+config SND_MXS_SOC_BUILTIN
-+ tristate "SoC Audio for Freescale i.MX23 built-in codec"
-+ depends on ARCH_MXS
-+ select SND_SOC_GENERIC_DMAENGINE_PCM
-+ select SND_SOC_MXS_BUILTIN_CODEC
-+ help
-+ Say Y or M if you want to add support for codecs attached to
-+ the MXS SAIF interface.
---- a/sound/soc/mxs/Makefile
-+++ b/sound/soc/mxs/Makefile
-@@ -8,3 +8,12 @@ obj-$(CONFIG_SND_MXS_SOC) += snd-soc-mxs
- snd-soc-mxs-sgtl5000-objs := mxs-sgtl5000.o
-
- obj-$(CONFIG_SND_SOC_MXS_SGTL5000) += snd-soc-mxs-sgtl5000.o
-+
-+# i.MX23 built-in audio Machine and Platform support
-+snd-soc-mxs-builtin-pcm-objs := mxs-builtin-pcm.o
-+snd-soc-mxs-builtin-dai-objs := mxs-builtin-dai.o
-+snd-soc-mxs-builtin-audio-objs := mxs-builtin-audio.o
-+
-+obj-$(CONFIG_SND_MXS_SOC_BUILTIN) += snd-soc-mxs-builtin-pcm.o
-+obj-$(CONFIG_SND_MXS_SOC_BUILTIN) += snd-soc-mxs-builtin-dai.o
-+obj-$(CONFIG_SND_MXS_SOC_BUILTIN) += snd-soc-mxs-builtin-audio.o
---- /dev/null
-+++ b/sound/soc/mxs/mxs-builtin-audio.c
-@@ -0,0 +1,120 @@
-+/*
-+ * mxs-builtin-audio.c -- i.MX233 built-in codec ALSA Soc Audio driver
-+ *
-+ * Author: Michal Ulianko <michal.ulianko@gmail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+#include <sound/soc-dapm.h>
-+#include <asm/mach-types.h>
-+
-+static struct snd_soc_dai_link mxs_adc_dai_link[] = {
-+ {
-+ .name = "MXS ADC/DAC",
-+ .stream_name = "MXS ADC/DAC",
-+ .codec_dai_name = "mxs-builtin-codec-dai",
-+// .codec_name = "mxs-builtin-codec",
-+// .cpu_dai_name = "mxs-builtin-cpu-dai",
-+// .platform_name = "mxs-builtin-cpu-dai",
-+// .ops = &mxs_sgtl5000_hifi_ops,
-+ },
-+};
-+
-+static struct snd_soc_card mxs_adc_audio = {
-+ .name = "mxs-builtin-audio",
-+ .owner = THIS_MODULE,
-+ .dai_link = mxs_adc_dai_link,
-+ .num_links = ARRAY_SIZE(mxs_adc_dai_link),
-+};
-+
-+static int mxsadc_audio_probe_dt(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct device_node *cpu_dai_np, *codec_np;
-+ int ret = 0;
-+
-+ if (!np)
-+ return 1; /* no device tree */
-+
-+ cpu_dai_np = of_parse_phandle(np, "cpu-dai", 0);
-+ codec_np = of_parse_phandle(np, "audio-codec", 0);
-+ if (!cpu_dai_np || !codec_np) {
-+ dev_err(&pdev->dev, "phandle missing or invalid\n");
-+ return -EINVAL;
-+ }
-+
-+ mxs_adc_dai_link[0].codec_name = NULL;
-+ mxs_adc_dai_link[0].codec_of_node = codec_np;
-+ mxs_adc_dai_link[0].cpu_dai_name = NULL;
-+ mxs_adc_dai_link[0].cpu_of_node = cpu_dai_np;
-+ mxs_adc_dai_link[0].platform_name = NULL;
-+ mxs_adc_dai_link[0].platform_of_node = cpu_dai_np;
-+
-+// of_node_put(codec_np);
-+// of_node_put(cpu_dai_np);
-+
-+ return ret;
-+}
-+
-+static int mxsadc_audio_probe(struct platform_device *pdev)
-+{
-+ struct snd_soc_card *card = &mxs_adc_audio;
-+ int ret;
-+
-+ ret = mxsadc_audio_probe_dt(pdev);
-+ if (ret < 0)
-+ return ret;
-+
-+ card->dev = &pdev->dev;
-+ platform_set_drvdata(pdev, card);
-+
-+ ret = snd_soc_register_card(card);
-+ if (ret) {
-+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static int mxsadc_audio_remove(struct platform_device *pdev)
-+{
-+ struct snd_soc_card *card = platform_get_drvdata(pdev);
-+
-+ snd_soc_unregister_card(card);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mxs_adc_audio_dt_ids[] = {
-+ { .compatible = "fsl,mxs-builtin-audio", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mxs_adc_audio_dt_ids);
-+
-+static struct platform_driver mxs_adc_audio_driver = {
-+ .driver = {
-+ .name = "mxs-builtin-audio",
-+ .owner = THIS_MODULE,
-+ .of_match_table = mxs_adc_audio_dt_ids,
-+ },
-+ .probe = mxsadc_audio_probe,
-+ .remove = mxsadc_audio_remove,
-+};
-+
-+module_platform_driver(mxs_adc_audio_driver);
-+
-+MODULE_DESCRIPTION("Freescale MXS ADC/DAC SoC Machine Driver");
-+MODULE_AUTHOR("Michal Ulianko <michal.ulianko@gmail.com>");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/sound/soc/mxs/mxs-builtin-dai.c
-@@ -0,0 +1,588 @@
-+/*
-+ * mxs-builtin-dai.c -- i.MX233 built-in codec ALSA Soc Audio driver
-+ *
-+ * Author: Michal Ulianko <michal.ulianko@gmail.com>
-+ *
-+ * Based on sound/soc/mxs/mxs-adc.c for kernel 2.6.35
-+ * by Vladislav Buzov <vbuzov@embeddedalley.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/platform_device.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+
-+#include "../codecs/mxs-builtin-codec.h"
-+#include "mxs-builtin-pcm.h"
-+
-+#define ADC_VOLUME_MIN 0x37
-+
-+/* TODO Use codec IO function soc snd write etc, instead of __writel __readl */
-+
-+// TODO use container_of
-+struct mxs_irq_data {
-+ struct snd_pcm_substream *substream;
-+ struct mxs_adc_priv *mxs_adc;
-+};
-+
-+struct mxs_adc_priv {
-+ struct mxs_irq_data irq_data;
-+ int dma_adc_err_irq;
-+ int dma_dac_err_irq;
-+ int hp_short_irq;
-+ void __iomem *audioin_base;
-+ void __iomem *audioout_base;
-+ void __iomem *rtc_base;
-+};
-+
-+typedef struct {
-+ struct work_struct work;
-+ struct timer_list timer;
-+
-+ /* target workqueue and CPU ->timer uses to queue ->work */
-+ struct workqueue_struct *wq;
-+ int cpu;
-+
-+ struct mxs_adc_priv *mxs_adc;
-+} my_delayed_work_t;
-+
-+// static struct delayed_work work;
-+// static struct delayed_work adc_ramp_work;
-+// static struct delayed_work dac_ramp_work;
-+// static struct delayed_work test;
-+static my_delayed_work_t work;
-+static my_delayed_work_t adc_ramp_work;
-+static my_delayed_work_t dac_ramp_work;
-+static my_delayed_work_t test;
-+static bool adc_ramp_done = 1;
-+static bool dac_ramp_done = 1;
-+
-+static inline void mxs_adc_schedule_work(struct delayed_work *work)
-+{
-+ schedule_delayed_work(work, HZ / 10);
-+}
-+
-+static void mxs_adc_work(struct work_struct *work)
-+{
-+ struct mxs_adc_priv *mxs_adc = ((my_delayed_work_t *)work)->mxs_adc;
-+ /* disable irq */
-+ disable_irq(mxs_adc->hp_short_irq);
-+
-+ while (true) {
-+ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN_CLR);
-+ msleep(10);
-+ if ((__raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL)
-+ & BM_AUDIOOUT_ANACTRL_SHORT_LR_STS) != 0) {
-+ /* rearm the short protection */
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORTMODE_LR,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_LR_STS,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ __raw_writel(BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(0x1),
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_SET);
-+
-+ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN_SET);
-+ printk(KERN_WARNING "WARNING : Headphone LR short!\r\n");
-+ } else {
-+ printk(KERN_WARNING "INFO : Headphone LR no longer short!\r\n");
-+ break;
-+ }
-+ msleep(1000);
-+ }
-+
-+ /* power up the HEADPHONE and un-mute the HPVOL */
-+ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL_CLR);
-+ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN_CLR);
-+
-+ /* enable irq for next short detect*/
-+ enable_irq(mxs_adc->hp_short_irq);
-+}
-+
-+static void mxs_adc_schedule_ramp_work(struct delayed_work *work)
-+{
-+ schedule_delayed_work(work, msecs_to_jiffies(2));
-+ adc_ramp_done = 0;
-+}
-+
-+static void mxs_adc_ramp_work(struct work_struct *work)
-+{
-+ struct mxs_adc_priv *mxs_adc = ((my_delayed_work_t *)work)->mxs_adc;
-+ u32 reg = 0;
-+ u32 reg1 = 0;
-+ u32 reg2 = 0;
-+ u32 l, r;
-+ u32 ll, rr;
-+ int i;
-+
-+ reg = __raw_readl(mxs_adc->audioin_base + \
-+ HW_AUDIOIN_ADCVOLUME);
-+
-+ reg1 = reg & ~BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT;
-+ reg1 = reg1 & ~BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT;
-+ /* minimize adc volume */
-+ reg2 = reg1 |
-+ BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(ADC_VOLUME_MIN) |
-+ BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(ADC_VOLUME_MIN);
-+ __raw_writel(reg2,
-+ mxs_adc->audioin_base + HW_AUDIOIN_ADCVOLUME);
-+ msleep(1);
-+
-+ l = (reg & BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT) >>
-+ BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT;
-+ r = (reg & BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT) >>
-+ BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT;
-+
-+ /* fade in adc vol */
-+ for (i = ADC_VOLUME_MIN; (i < l) || (i < r);) {
-+ i += 0x8;
-+ ll = i < l ? i : l;
-+ rr = i < r ? i : r;
-+ reg2 = reg1 |
-+ BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(ll) |
-+ BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(rr);
-+ __raw_writel(reg2,
-+ mxs_adc->audioin_base + HW_AUDIOIN_ADCVOLUME);
-+ msleep(1);
-+ }
-+ adc_ramp_done = 1;
-+}
-+
-+static void mxs_dac_schedule_ramp_work(struct delayed_work *work)
-+{
-+ schedule_delayed_work(work, msecs_to_jiffies(2));
-+ dac_ramp_done = 0;
-+}
-+
-+static void mxs_dac_ramp_work(struct work_struct *work)
-+{
-+ struct mxs_adc_priv *mxs_adc = ((my_delayed_work_t *)work)->mxs_adc;
-+ u32 reg = 0;
-+ u32 reg1 = 0;
-+ u32 l, r;
-+ u32 ll, rr;
-+ int i;
-+
-+ /* unmute hp and speaker */
-+ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL_CLR);
-+ __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_SPEAKERCTRL_CLR);
-+
-+ reg = __raw_readl(mxs_adc->audioout_base + \
-+ HW_AUDIOOUT_HPVOL);
-+
-+ reg1 = reg & ~BM_AUDIOOUT_HPVOL_VOL_LEFT;
-+ reg1 = reg1 & ~BM_AUDIOOUT_HPVOL_VOL_RIGHT;
-+
-+ l = (reg & BM_AUDIOOUT_HPVOL_VOL_LEFT) >>
-+ BP_AUDIOOUT_HPVOL_VOL_LEFT;
-+ r = (reg & BM_AUDIOOUT_HPVOL_VOL_RIGHT) >>
-+ BP_AUDIOOUT_HPVOL_VOL_RIGHT;
-+ /* fade in hp vol */
-+ for (i = 0x7f; i > 0 ;) {
-+ i -= 0x8;
-+ ll = i > (int)l ? i : l;
-+ rr = i > (int)r ? i : r;
-+ reg = reg1 | BF_AUDIOOUT_HPVOL_VOL_LEFT(ll)
-+ | BF_AUDIOOUT_HPVOL_VOL_RIGHT(rr);
-+ __raw_writel(reg,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL);
-+ msleep(1);
-+ }
-+ dac_ramp_done = 1;
-+}
-+
-+/* IRQs */
-+static irqreturn_t mxs_short_irq(int irq, void *dev_id)
-+{
-+ struct mxs_adc_priv *mxs_adc = dev_id;
-+ //struct snd_pcm_substream *substream = mxs_adc->irq_data.substream;
-+
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORTMODE_LR,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_LR_STS,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ __raw_writel(BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(0x1),
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_SET);
-+
-+ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL_SET);
-+ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN_SET);
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_CLASSAB,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_SET);
-+
-+ mxs_adc_schedule_work((struct delayed_work *) &work);
-+ return IRQ_HANDLED;
-+}
-+
-+static irqreturn_t mxs_err_irq(int irq, void *dev_id)
-+{
-+ struct mxs_adc_priv *mxs_adc = dev_id;
-+ struct snd_pcm_substream *substream = mxs_adc->irq_data.substream;
-+ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0;
-+ u32 ctrl_reg;
-+ u32 overflow_mask;
-+ u32 underflow_mask;
-+
-+ if (playback) {
-+ ctrl_reg = __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_CTRL);
-+ underflow_mask = BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ;
-+ overflow_mask = BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ;
-+ } else {
-+ ctrl_reg = __raw_readl(mxs_adc->audioin_base + HW_AUDIOIN_CTRL);
-+ underflow_mask = BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ;
-+ overflow_mask = BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ;
-+ }
-+
-+ if (ctrl_reg & underflow_mask) {
-+ printk(KERN_DEBUG "%s underflow detected\n",
-+ playback ? "DAC" : "ADC");
-+
-+ if (playback)
-+ __raw_writel(
-+ BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR);
-+ else
-+ __raw_writel(
-+ BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR);
-+
-+ } else if (ctrl_reg & overflow_mask) {
-+ printk(KERN_DEBUG "%s overflow detected\n",
-+ playback ? "DAC" : "ADC");
-+
-+ if (playback)
-+ __raw_writel(
-+ BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR);
-+ else
-+ __raw_writel(BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR);
-+ } else
-+ printk(KERN_WARNING "Unknown DAC error interrupt\n");
-+
-+ return IRQ_HANDLED;
-+}
-+/* END IRQs */
-+
-+static int mxs_trigger(struct snd_pcm_substream *substream,
-+ int cmd,
-+ struct snd_soc_dai *cpu_dai)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_dai_get_drvdata(cpu_dai);
-+ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0;
-+ int ret = 0;
-+
-+ switch (cmd) {
-+ case SNDRV_PCM_TRIGGER_START:
-+ case SNDRV_PCM_TRIGGER_RESUME:
-+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+
-+ if (playback) {
-+ /* enable the fifo error interrupt */
-+ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_SET);
-+ /* write a data to data reg to trigger the transfer */
-+ __raw_writel(0x0,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_DATA);
-+ mxs_dac_schedule_ramp_work((struct delayed_work *) &dac_ramp_work);
-+ } else {
-+// mxs_dma_get_info(prtd->dma_ch, &dma_info);
-+// cur_bar1 = dma_info.buf_addr;
-+// xfer_count1 = dma_info.xfer_count;
-+
-+ __raw_writel(BM_AUDIOIN_CTRL_RUN,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_SET);
-+ udelay(100);
-+
-+// mxs_dma_get_info(prtd->dma_ch, &dma_info);
-+// cur_bar2 = dma_info.buf_addr;
-+// xfer_count2 = dma_info.xfer_count;
-+//
-+// /* check if DMA getting stuck */
-+// if ((xfer_count1 == xfer_count2) && (cur_bar1 == cur_bar2))
-+// /* read a data from data reg to trigger the receive */
-+// reg = __raw_readl(mxs_adc->audioin_base + HW_AUDIOIN_DATA);
-+
-+ mxs_adc_schedule_ramp_work((struct delayed_work *) &adc_ramp_work);
-+ }
-+ break;
-+
-+ case SNDRV_PCM_TRIGGER_SUSPEND:
-+ case SNDRV_PCM_TRIGGER_STOP:
-+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+
-+ if (playback) {
-+// printk(KERN_INFO "SNDRV_PCM_TRIGGER_START\n");
-+// printk(KERN_INFO "ctrl:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_CTRL));
-+// printk(KERN_INFO "stat:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_STAT));
-+// printk(KERN_INFO "srr:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_DACSRR));
-+// printk(KERN_INFO "vol:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_DACVOLUME));
-+// printk(KERN_INFO "debug:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_DACDEBUG));
-+// printk(KERN_INFO "hpvol:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL));
-+// printk(KERN_INFO "pwrdn:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN));
-+// printk(KERN_INFO "refc:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_REFCTRL));
-+// printk(KERN_INFO "anac:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL));
-+// printk(KERN_INFO "test:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_TEST));
-+// printk(KERN_INFO "bist:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_BISTCTRL));
-+// printk(KERN_INFO "anaclk:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_ANACLKCTRL));
-+
-+ if (dac_ramp_done == 0) {
-+ cancel_delayed_work((struct delayed_work *) &dac_ramp_work);
-+ dac_ramp_done = 1;
-+ }
-+ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL_SET);
-+ __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_SPEAKERCTRL_SET);
-+ /* disable the fifo error interrupt */
-+ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR);
-+ mdelay(50);
-+ } else {
-+ if (adc_ramp_done == 0) {
-+ cancel_delayed_work((struct delayed_work *) &adc_ramp_work);
-+ adc_ramp_done = 1;
-+ }
-+ __raw_writel(BM_AUDIOIN_CTRL_RUN,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR);
-+ }
-+ break;
-+
-+ default:
-+ printk(KERN_ERR "TRIGGER ERROR\n");
-+ ret = -EINVAL;
-+ }
-+
-+ return ret;
-+}
-+
-+static int mxs_startup(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *cpu_dai)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_dai_get_drvdata(cpu_dai);
-+ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0;
-+ mxs_adc->irq_data.mxs_adc = mxs_adc;
-+ mxs_adc->irq_data.substream = substream;
-+
-+ work.mxs_adc = mxs_adc;
-+ adc_ramp_work.mxs_adc = mxs_adc;
-+ dac_ramp_work.mxs_adc = mxs_adc;
-+ test.mxs_adc = mxs_adc;
-+ INIT_DELAYED_WORK(&work, mxs_adc_work);
-+ INIT_DELAYED_WORK(&adc_ramp_work, mxs_adc_ramp_work);
-+ INIT_DELAYED_WORK(&dac_ramp_work, mxs_dac_ramp_work);
-+
-+ /* Enable error interrupt */
-+ if (playback) {
-+ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR);
-+ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR);
-+ } else {
-+ __raw_writel(BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR);
-+ __raw_writel(BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR);
-+ __raw_writel(BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_SET);
-+ }
-+
-+ return 0;
-+}
-+
-+static void mxs_shutdown(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *cpu_dai)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_dai_get_drvdata(cpu_dai);
-+ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0;
-+
-+ /* Disable error interrupt */
-+ if (playback) {
-+ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR);
-+ } else {
-+ __raw_writel(BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR);
-+ }
-+}
-+
-+#define MXS_ADC_RATES SNDRV_PCM_RATE_8000_192000
-+#define MXS_ADC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
-+
-+static const struct snd_soc_dai_ops mxs_adc_dai_ops = {
-+ .startup = mxs_startup,
-+ .trigger = mxs_trigger,
-+ .shutdown = mxs_shutdown,
-+};
-+
-+static int mxs_dai_probe(struct snd_soc_dai *dai)
-+{
-+ // TODO This does not make any sense.
-+ struct mxs_adc_priv *mxs_adc = dev_get_drvdata(dai->dev);
-+
-+ snd_soc_dai_set_drvdata(dai, mxs_adc);
-+
-+ return 0;
-+}
-+
-+static struct snd_soc_dai_driver mxs_adc_dai = {
-+ .name = "mxs-builtin-cpu-dai",
-+ .probe = mxs_dai_probe,
-+ .playback = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = MXS_ADC_RATES,
-+ .formats = MXS_ADC_FORMATS,
-+ },
-+ .capture = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = MXS_ADC_RATES,
-+ .formats = MXS_ADC_FORMATS,
-+ },
-+ .ops = &mxs_adc_dai_ops,
-+};
-+
-+static const struct snd_soc_component_driver mxs_adc_component = {
-+ .name = "mxs-xxx", //TODO change this name
-+};
-+
-+static int mxs_adc_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct mxs_adc_priv *mxs_adc;
-+ int ret = 0;
-+
-+ if (!np)
-+ return -EINVAL;
-+
-+ mxs_adc = devm_kzalloc(&pdev->dev, sizeof(*mxs_adc), GFP_KERNEL);
-+ if (!mxs_adc)
-+ return -ENOMEM;
-+
-+ mxs_adc->audioout_base = devm_ioremap(&pdev->dev, 0x80048000, 0x2000);
-+ if (IS_ERR(mxs_adc->audioout_base))
-+ return PTR_ERR(mxs_adc->audioout_base);
-+
-+ mxs_adc->audioin_base = devm_ioremap(&pdev->dev, 0x8004c000, 0x2000);
-+ if (IS_ERR(mxs_adc->audioin_base))
-+ return PTR_ERR(mxs_adc->audioin_base);
-+
-+ mxs_adc->rtc_base = devm_ioremap(&pdev->dev, 0x8005c000, 0x2000);
-+ if (IS_ERR(mxs_adc->rtc_base))
-+ return PTR_ERR(mxs_adc->rtc_base);
-+
-+ /* Get IRQ numbers */
-+ mxs_adc->dma_adc_err_irq = platform_get_irq(pdev, 0);
-+ if (mxs_adc->dma_adc_err_irq < 0) {
-+ ret = mxs_adc->dma_adc_err_irq;
-+ dev_err(&pdev->dev, "failed to get ADC DMA ERR irq resource: %d\n", ret);
-+ return ret;
-+ }
-+
-+ mxs_adc->dma_dac_err_irq = platform_get_irq(pdev, 1);
-+ if (mxs_adc->dma_dac_err_irq < 0) {
-+ ret = mxs_adc->dma_dac_err_irq;
-+ dev_err(&pdev->dev, "failed to get DAC DMA ERR irq resource: %d\n", ret);
-+ return ret;
-+ }
-+
-+ mxs_adc->hp_short_irq = platform_get_irq(pdev, 2);
-+ if (mxs_adc->hp_short_irq < 0) {
-+ ret = mxs_adc->hp_short_irq;
-+ dev_err(&pdev->dev, "failed to get HP_SHORT irq resource: %d\n", ret);
-+ return ret;
-+ }
-+
-+ /* Request IRQs */
-+ ret = devm_request_irq(&pdev->dev, mxs_adc->dma_adc_err_irq, mxs_err_irq, 0, "MXS DAC and ADC Error",
-+ mxs_adc);
-+ if (ret) {
-+ printk(KERN_ERR "%s: Unable to request ADC/DAC error irq %d\n",
-+ __func__, mxs_adc->dma_adc_err_irq);
-+ return ret;
-+ }
-+
-+ ret = devm_request_irq(&pdev->dev, mxs_adc->dma_dac_err_irq, mxs_err_irq, 0, "MXS DAC and ADC Error",
-+ mxs_adc);
-+ if (ret) {
-+ printk(KERN_ERR "%s: Unable to request ADC/DAC error irq %d\n",
-+ __func__, mxs_adc->dma_dac_err_irq);
-+ return ret;
-+ }
-+
-+ ret = devm_request_irq(&pdev->dev, mxs_adc->hp_short_irq, mxs_short_irq,
-+ IRQF_DISABLED | IRQF_SHARED, "MXS DAC and ADC HP SHORT", mxs_adc);
-+ if (ret) {
-+ printk(KERN_ERR "%s: Unable to request ADC/DAC HP SHORT irq %d\n",
-+ __func__, mxs_adc->hp_short_irq);
-+ return ret;
-+ }
-+
-+ platform_set_drvdata(pdev, mxs_adc);
-+
-+ ret = snd_soc_register_component(&pdev->dev, &mxs_adc_component, &mxs_adc_dai, 1);
-+ if (ret) {
-+ dev_err(&pdev->dev, "register DAI failed\n");
-+ return ret;
-+ }
-+
-+ ret = mxs_adc_pcm_platform_register(&pdev->dev);
-+ if (ret) {
-+ dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
-+ goto failed_pdev_alloc;
-+ }
-+
-+ return 0;
-+
-+failed_pdev_alloc:
-+ snd_soc_unregister_component(&pdev->dev);
-+
-+ return ret;
-+}
-+
-+static int mxs_adc_remove(struct platform_device *pdev)
-+{
-+ mxs_adc_pcm_platform_unregister(&pdev->dev);
-+ snd_soc_unregister_component(&pdev->dev);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mxs_adc_dai_dt_ids[] = {
-+ { .compatible = "fsl,mxs-builtin-cpu-dai", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mxs_adc_dai_dt_ids);
-+
-+static struct platform_driver mxs_adc_dai_driver = {
-+ .probe = mxs_adc_probe,
-+ .remove = mxs_adc_remove,
-+
-+ .driver = {
-+ .name = "mxs-builtin-cpu-dai",
-+ .owner = THIS_MODULE,
-+ .of_match_table = mxs_adc_dai_dt_ids,
-+ },
-+};
-+
-+module_platform_driver(mxs_adc_dai_driver);
-+
-+MODULE_DESCRIPTION("Freescale MXS ADC/DAC SoC Codec DAI Driver");
-+MODULE_AUTHOR("Michal Ulianko <michal.ulianko@gmail.com>");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/sound/soc/mxs/mxs-builtin-pcm.c
-@@ -0,0 +1,69 @@
-+/*
-+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
-+ *
-+ * Based on sound/soc/imx/imx-pcm-dma-mx2.c
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-+ */
-+
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/soc.h>
-+#include <sound/dmaengine_pcm.h>
-+
-+#include "mxs-builtin-pcm.h"
-+
-+static const struct snd_pcm_hardware snd_mxs_hardware = {
-+ .info = SNDRV_PCM_INFO_MMAP |
-+ SNDRV_PCM_INFO_MMAP_VALID |
-+ SNDRV_PCM_INFO_PAUSE |
-+ SNDRV_PCM_INFO_RESUME |
-+ SNDRV_PCM_INFO_INTERLEAVED,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
-+ SNDRV_PCM_FMTBIT_S20_3LE |
-+ SNDRV_PCM_FMTBIT_S24_LE,
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .period_bytes_min = 32,
-+ .period_bytes_max = 8192,
-+ .periods_min = 1,
-+ .periods_max = 52,
-+ .buffer_bytes_max = 64 * 1024,
-+ .fifo_size = 32,
-+};
-+
-+static const struct snd_dmaengine_pcm_config mxs_dmaengine_pcm_config = {
-+ .pcm_hardware = &snd_mxs_hardware,
-+ .prealloc_buffer_size = 64 * 1024,
-+};
-+
-+int mxs_adc_pcm_platform_register(struct device *dev)
-+{
-+ return snd_dmaengine_pcm_register(dev, &mxs_dmaengine_pcm_config,
-+ SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
-+}
-+EXPORT_SYMBOL_GPL(mxs_adc_pcm_platform_register);
-+
-+void mxs_adc_pcm_platform_unregister(struct device *dev)
-+{
-+ snd_dmaengine_pcm_unregister(dev);
-+}
-+EXPORT_SYMBOL_GPL(mxs_adc_pcm_platform_unregister);
-+
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/sound/soc/mxs/mxs-builtin-pcm.h
-@@ -0,0 +1,25 @@
-+/*
-+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-+ */
-+
-+#ifndef _MXS_PCM_H
-+#define _MXS_PCM_H
-+
-+int mxs_adc_pcm_platform_register(struct device *dev);
-+void mxs_adc_pcm_platform_unregister(struct device *dev);
-+
-+#endif
+++ /dev/null
---- a/arch/arm/boot/dts/imx23-olinuxino.dts
-+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
-@@ -84,6 +84,25 @@
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
-+
-+ codec: mxs-builtin-codec {
-+ compatible = "fsl,mxs-builtin-codec";
-+ reg = <0x80048000 0x2000>, <0x8004c000 0x2000>,
-+ <0x8005c000 0x2000>;
-+ reg-names = "audioout", "audioin", "rtc";
-+ clocks = <&clks 31>;
-+ clock-names = "filt";
-+ };
-+
-+ platform_dai: mxs-builtin-cpu-dai {
-+ compatible = "fsl,mxs-builtin-cpu-dai";
-+ reg = <0x80048000 0x2000>, <0x8004c000 0x2000>,
-+ <0x8005c000 0x2000>;
-+ reg-names = "audioout", "audioin", "rtc";
-+ interrupts = <8 6 4>;
-+ dmas = <&dma_apbx 0>, <&dma_apbx 1>;
-+ dma-names = "rx", "tx";
-+ };
- };
- };
-
-@@ -118,4 +137,10 @@
- gpios = <&gpio2 1 1>;
- };
- };
-+
-+ mxs-builtin-audio {
-+ compatible = "fsl,mxs-builtin-audio";
-+ audio-codec = <&codec>;
-+ cpu-dai = <&platform_dai>;
-+ };
- };
+++ /dev/null
---- a/arch/arm/boot/dts/imx23.dtsi
-+++ b/arch/arm/boot/dts/imx23.dtsi
-@@ -337,6 +337,7 @@
-
- dcp@80028000 {
- reg = <0x80028000 0x2000>;
-+ interrupts = <52 53 54>;
- status = "disabled";
- };
-
---- a/arch/arm/boot/dts/imx23-olinuxino.dts
-+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
-@@ -66,6 +66,12 @@
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
- };
-+
-+ dcp@80028000 {
-+ status = "okay";
-+ compatible = "fsl-dcp";
-+ };
-+
- };
-
- apbx@80040000 {
+++ /dev/null
---- a/arch/arm/boot/dts/imx23-olinuxino.dts
-+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
-@@ -109,6 +109,11 @@
- dmas = <&dma_apbx 0>, <&dma_apbx 1>;
- dma-names = "rx", "tx";
- };
-+
-+ lradc@80050000 {
-+ status = "okay";
-+ fsl,lradc-touchscreen-wires = <4>;
-+ };
- };
- };
-
+++ /dev/null
-diff -ruN orig/arch/arm/boot/dts/Makefile new/arch/arm/boot/dts/Makefile
---- orig/arch/arm/boot/dts/Makefile 2013-11-04 00:41:51.000000000 +0100
-+++ new/arch/arm/boot/dts/Makefile 2013-11-11 14:38:07.108808212 +0100
-@@ -159,6 +159,7 @@
- imx28-cfa10057.dtb \
- imx28-cfa10058.dtb \
- imx28-evk.dtb \
-+ imx28-duckbill.dtb \
- imx28-m28evk.dtb \
- imx28-sps1.dtb \
- imx28-tx28.dtb
-diff -ruN orig/arch/arm/mach-mxs/mach-mxs.c new/arch/arm/mach-mxs/mach-mxs.c
---- orig/arch/arm/mach-mxs/mach-mxs.c 2013-11-04 00:41:51.000000000 +0100
-+++ new/arch/arm/mach-mxs/mach-mxs.c 2013-11-11 14:40:07.555397389 +0100
-@@ -159,6 +159,7 @@
- OUI_FSL,
- OUI_DENX,
- OUI_CRYSTALFONTZ,
-+ OUI_I2SE,
- };
-
- static void __init update_fec_mac_prop(enum mac_oui oui)
-@@ -213,6 +214,11 @@
- macaddr[1] = 0xb9;
- macaddr[2] = 0xe1;
- break;
-+ case OUI_I2SE:
-+ macaddr[0] = 0x00;
-+ macaddr[1] = 0x01;
-+ macaddr[2] = 0x87;
-+ break;
- }
- val = ocotp[i];
- macaddr[3] = (val >> 16) & 0xff;
-@@ -423,6 +429,11 @@
- return 0;
- }
-
-+static void __init duckbill_init(void)
-+{
-+ update_fec_mac_prop(OUI_I2SE);
-+}
-+
- static void __init mxs_machine_init(void)
- {
- struct device_node *root;
-@@ -459,6 +470,8 @@
- apx4devkit_init();
- else if (of_machine_is_compatible("crystalfontz,cfa10036"))
- crystalfontz_init();
-+ else if (of_machine_is_compatible("i2se,duckbill"))
-+ duckbill_init();
-
- of_platform_populate(NULL, of_default_bus_match_table,
- NULL, parent);
+++ /dev/null
---- a/sound/soc/codecs/Kconfig
-+++ b/sound/soc/codecs/Kconfig
-@@ -132,6 +132,7 @@ config SND_SOC_ALL_CODECS
- select SND_SOC_WM9705 if SND_SOC_AC97_BUS
- select SND_SOC_WM9712 if SND_SOC_AC97_BUS
- select SND_SOC_WM9713 if SND_SOC_AC97_BUS
-+ select SND_SOC_MXS_BUILTIN_CODEC
- help
- Normally ASoC codec drivers are only built if a machine driver which
- uses them is also built since they are only usable with a machine
-@@ -534,6 +535,9 @@ config SND_SOC_WM9712
- config SND_SOC_WM9713
- tristate
-
-+config SND_SOC_MXS_BUILTIN_CODEC
-+ tristate
-+
- # Amp
- config SND_SOC_LM4857
- tristate
---- a/sound/soc/codecs/Makefile
-+++ b/sound/soc/codecs/Makefile
-@@ -124,6 +124,7 @@ snd-soc-wm9705-objs := wm9705.o
- snd-soc-wm9712-objs := wm9712.o
- snd-soc-wm9713-objs := wm9713.o
- snd-soc-wm-hubs-objs := wm_hubs.o
-+snd-soc-mxs-builtin-codec-objs := mxs-builtin-codec.o
-
- # Amp
- snd-soc-max9877-objs := max9877.o
-@@ -254,6 +255,7 @@ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-
- obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o
- obj-$(CONFIG_SND_SOC_WM_ADSP) += snd-soc-wm-adsp.o
- obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o
-+obj-$(CONFIG_SND_SOC_MXS_BUILTIN_CODEC) += snd-soc-mxs-builtin-codec.o
-
- # Amp
- obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o
---- /dev/null
-+++ b/sound/soc/codecs/mxs-builtin-codec.c
-@@ -0,0 +1,1128 @@
-+/*
-+ * mxs-builtin-codec.c -- i.MX233 built-in codec ALSA Soc Audio driver
-+ *
-+ * Author: Michal Ulianko <michal.ulianko@gmail.com>
-+ *
-+ * Based on sound/soc/codecs/mxs-adc-codec.c for kernel 2.6.35
-+ * by Vladislav Buzov <vbuzov@embeddedalley.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+
-+#include "mxs-builtin-codec.h"
-+
-+#ifndef BF
-+#define BF(value, field) (((value) << BP_##field) & BM_##field)
-+#endif
-+
-+/* TODO Delete this and use BM_RTC_PERSISTENT0_RELEASE_GND from header file
-+ * if it works. */
-+#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
-+#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
-+#define BM_RTC_PERSISTENT0_RELEASE_GND BF(0x2, RTC_PERSISTENT0_SPARE_ANALOG)
-+
-+/* TODO Use codec IO function soc snd write etc, instead of __writel __readl */
-+
-+struct mxs_adc_priv {
-+ void __iomem *ain_base;
-+ void __iomem *aout_base;
-+ void __iomem *rtc_base;
-+ struct clk *clk;
-+};
-+
-+static unsigned int mxs_regmap[] = {
-+ HW_AUDIOOUT_CTRL,
-+ HW_AUDIOOUT_STAT,
-+ HW_AUDIOOUT_DACSRR,
-+ HW_AUDIOOUT_DACVOLUME,
-+ HW_AUDIOOUT_DACDEBUG,
-+ HW_AUDIOOUT_HPVOL,
-+ HW_AUDIOOUT_PWRDN,
-+ HW_AUDIOOUT_REFCTRL,
-+ HW_AUDIOOUT_ANACTRL,
-+ HW_AUDIOOUT_TEST,
-+ HW_AUDIOOUT_BISTCTRL,
-+ HW_AUDIOOUT_BISTSTAT0,
-+ HW_AUDIOOUT_BISTSTAT1,
-+ HW_AUDIOOUT_ANACLKCTRL,
-+ HW_AUDIOOUT_DATA,
-+ HW_AUDIOOUT_SPEAKERCTRL,
-+ HW_AUDIOOUT_VERSION,
-+ HW_AUDIOIN_CTRL,
-+ HW_AUDIOIN_STAT,
-+ HW_AUDIOIN_ADCSRR,
-+ HW_AUDIOIN_ADCVOLUME,
-+ HW_AUDIOIN_ADCDEBUG,
-+ HW_AUDIOIN_ADCVOL,
-+ HW_AUDIOIN_MICLINE,
-+ HW_AUDIOIN_ANACLKCTRL,
-+ HW_AUDIOIN_DATA,
-+};
-+
-+static void __iomem *mxs_getreg(struct mxs_adc_priv *mxs_adc, int i)
-+{
-+ if (i <= 16)
-+ return mxs_adc->aout_base + mxs_regmap[i];
-+ else if (i < ADC_REGNUM)
-+ return mxs_adc->ain_base + mxs_regmap[i];
-+ else
-+ return NULL;
-+}
-+
-+static u8 dac_volumn_control_word[] = {
-+ 0x37, 0x5e, 0x7e, 0x8e,
-+ 0x9e, 0xae, 0xb6, 0xbe,
-+ 0xc6, 0xce, 0xd6, 0xde,
-+ 0xe6, 0xee, 0xf6, 0xfe,
-+};
-+
-+struct dac_srr {
-+ u32 rate;
-+ u32 basemult;
-+ u32 src_hold;
-+ u32 src_int;
-+ u32 src_frac;
-+};
-+
-+static struct dac_srr srr_values[] = {
-+ {192000, 0x4, 0x0, 0x0F, 0x13FF},
-+ {176400, 0x4, 0x0, 0x11, 0x0037},
-+ {128000, 0x4, 0x0, 0x17, 0x0E00},
-+ {96000, 0x2, 0x0, 0x0F, 0x13FF},
-+ {88200, 0x2, 0x0, 0x11, 0x0037},
-+ {64000, 0x2, 0x0, 0x17, 0x0E00},
-+ {48000, 0x1, 0x0, 0x0F, 0x13FF},
-+ {44100, 0x1, 0x0, 0x11, 0x0037},
-+ {32000, 0x1, 0x0, 0x17, 0x0E00},
-+ {24000, 0x1, 0x1, 0x0F, 0x13FF},
-+ {22050, 0x1, 0x1, 0x11, 0x0037},
-+ {16000, 0x1, 0x1, 0x17, 0x0E00},
-+ {12000, 0x1, 0x3, 0x0F, 0x13FF},
-+ {11025, 0x1, 0x3, 0x11, 0x0037},
-+ {8000, 0x1, 0x3, 0x17, 0x0E00}
-+};
-+
-+static inline int get_srr_values(int rate)
-+{
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(srr_values); i++)
-+ if (srr_values[i].rate == rate)
-+ return i;
-+
-+ return -1;
-+}
-+
-+/* SoC IO functions */
-+static void mxs_codec_write_cache(struct snd_soc_codec *codec, unsigned int reg, unsigned int value)
-+{
-+ u16 *cache = codec->reg_cache;
-+ if (reg < ADC_REGNUM)
-+ cache[reg] = value;
-+}
-+
-+static int mxs_codec_write(struct snd_soc_codec *codec, unsigned int reg, unsigned int value)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+ unsigned int reg_val;
-+ unsigned int mask = 0xffff;
-+
-+ if (reg >= ADC_REGNUM)
-+ return -EIO;
-+
-+ mxs_codec_write_cache(codec, reg, value);
-+
-+ if (reg & 0x1) {
-+ mask <<= 16;
-+ value <<= 16;
-+ }
-+
-+ reg_val = __raw_readl(mxs_getreg(mxs_adc, reg >> 1));
-+ reg_val = (reg_val & ~mask) | value;
-+ __raw_writel(reg_val, mxs_getreg(mxs_adc, reg >> 1));
-+
-+ return 0;
-+}
-+
-+static unsigned int mxs_codec_read(struct snd_soc_codec *codec, unsigned int reg)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+ unsigned int reg_val;
-+
-+ if (reg >= ADC_REGNUM)
-+ return -1;
-+
-+ reg_val = __raw_readl(mxs_getreg(mxs_adc, reg >> 1));
-+ if (reg & 1)
-+ reg_val >>= 16;
-+
-+ return reg_val & 0xffff;
-+}
-+
-+// static unsigned int mxs_codec_read_cache(struct snd_soc_codec *codec, unsigned int reg)
-+// {
-+// u16 *cache = codec->reg_cache;
-+// if (reg >= ADC_REGNUM)
-+// return -EINVAL;
-+// return cache[reg];
-+// }
-+
-+static void mxs_codec_sync_reg_cache(struct snd_soc_codec *codec)
-+{
-+ int reg;
-+ for (reg = 0; reg < ADC_REGNUM; reg += 1)
-+ mxs_codec_write_cache(codec, reg,
-+ mxs_codec_read(codec, reg));
-+}
-+
-+// static int mxs_codec_restore_reg(struct snd_soc_codec *codec, unsigned int reg)
-+// {
-+// unsigned int cached_val, hw_val;
-+//
-+// cached_val = mxs_codec_read_cache(codec, reg);
-+// hw_val = mxs_codec_read(codec, reg);
-+//
-+// if (hw_val != cached_val)
-+// return mxs_codec_write(codec, reg, cached_val);
-+//
-+// return 0;
-+// }
-+/* END SoC IO functions */
-+
-+/* Codec routines */
-+#define VAG_BASE_VALUE ((1400/2 - 625)/25)
-+
-+static void mxs_codec_dac_set_vag(struct mxs_adc_priv *mxs_adc)
-+{
-+ u32 refctrl_val = __raw_readl(mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL);
-+
-+ refctrl_val &= ~(BM_AUDIOOUT_REFCTRL_VAG_VAL);
-+ refctrl_val &= ~(BM_AUDIOOUT_REFCTRL_VBG_ADJ);
-+ refctrl_val |= BF(VAG_BASE_VALUE, AUDIOOUT_REFCTRL_VAG_VAL) |
-+ BM_AUDIOOUT_REFCTRL_ADJ_VAG |
-+ BF(0xF, AUDIOOUT_REFCTRL_ADC_REFVAL) |
-+ BM_AUDIOOUT_REFCTRL_ADJ_ADC |
-+ BF(0x3, AUDIOOUT_REFCTRL_VBG_ADJ) | BM_AUDIOOUT_REFCTRL_RAISE_REF;
-+
-+ __raw_writel(refctrl_val, mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL);
-+}
-+
-+static bool mxs_codec_dac_is_capless(struct mxs_adc_priv *mxs_adc)
-+{
-+ if ((__raw_readl(mxs_adc->aout_base + HW_AUDIOOUT_PWRDN)
-+ & BM_AUDIOOUT_PWRDN_CAPLESS) == 0)
-+ return false;
-+ else
-+ return true;
-+}
-+
-+static void mxs_codec_dac_arm_short_cm(struct mxs_adc_priv *mxs_adc, bool bShort)
-+{
-+ __raw_writel(BF(3, AUDIOOUT_ANACTRL_SHORTMODE_CM),
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_CM_STS,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ if (bShort)
-+ __raw_writel(BF(1, AUDIOOUT_ANACTRL_SHORTMODE_CM),
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET);
-+}
-+
-+static void mxs_codec_dac_arm_short_lr(struct mxs_adc_priv *mxs_adc, bool bShort)
-+{
-+ __raw_writel(BF(3, AUDIOOUT_ANACTRL_SHORTMODE_LR),
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_LR_STS,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ if (bShort)
-+ __raw_writel(BF(1, AUDIOOUT_ANACTRL_SHORTMODE_LR),
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET);
-+}
-+
-+static void mxs_codec_dac_set_short_trip_level(struct mxs_adc_priv *mxs_adc, u8 u8level)
-+{
-+ __raw_writel(__raw_readl(mxs_adc->aout_base +
-+ HW_AUDIOOUT_ANACTRL)
-+ & (~BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL)
-+ & (~BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR)
-+ | BF(u8level, AUDIOOUT_ANACTRL_SHORT_LVLADJL)
-+ | BF(u8level, AUDIOOUT_ANACTRL_SHORT_LVLADJR),
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL);
-+}
-+
-+static void mxs_codec_dac_arm_short(struct mxs_adc_priv *mxs_adc, bool bLatchCM, bool bLatchLR)
-+{
-+ if (bLatchCM) {
-+ if (mxs_codec_dac_is_capless(mxs_adc))
-+ mxs_codec_dac_arm_short_cm(mxs_adc, true);
-+ } else
-+ mxs_codec_dac_arm_short_cm(mxs_adc, false);
-+
-+ if (bLatchLR)
-+ mxs_codec_dac_arm_short_lr(mxs_adc, true);
-+ else
-+ mxs_codec_dac_arm_short_lr(mxs_adc, false);
-+}
-+
-+static void
-+mxs_codec_dac_power_on(struct mxs_adc_priv *mxs_adc)
-+{
-+ /* Ungate DAC clocks */
-+ __raw_writel(BM_AUDIOOUT_CTRL_CLKGATE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_CLR);
-+ __raw_writel(BM_AUDIOOUT_ANACLKCTRL_CLKGATE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACLKCTRL_CLR);
-+
-+ /* 16 bit word length */
-+ __raw_writel(BM_AUDIOOUT_CTRL_WORD_LENGTH,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET);
-+
-+ /* Arm headphone LR short protect */
-+ mxs_codec_dac_set_short_trip_level(mxs_adc, 0);
-+ mxs_codec_dac_arm_short(mxs_adc, false, true);
-+
-+ /* Update DAC volume over zero crossings */
-+ __raw_writel(BM_AUDIOOUT_DACVOLUME_EN_ZCD,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET);
-+ /* Mute DAC */
-+ __raw_writel(BM_AUDIOOUT_DACVOLUME_MUTE_LEFT |
-+ BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET);
-+
-+ /* Update HP volume over zero crossings */
-+ __raw_writel(BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD,
-+ mxs_adc->aout_base + HW_AUDIOOUT_HPVOL_SET);
-+
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_CLASSAB,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET);
-+
-+ /* Mute HP output */
-+ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_HPVOL_SET);
-+ /* Mute speaker amp */
-+ __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_SPEAKERCTRL_SET);
-+ /* Enable the audioout */
-+ __raw_writel(BM_AUDIOOUT_CTRL_RUN,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET);
-+}
-+
-+static void
-+mxs_codec_dac_power_down(struct mxs_adc_priv *mxs_adc)
-+{
-+ /* Disable the audioout */
-+ __raw_writel(BM_AUDIOOUT_CTRL_RUN,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_CLR);
-+ /* Disable class AB */
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_CLASSAB,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+
-+ /* Set hold to ground */
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_HOLD_GND,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET);
-+
-+ /* Mute HP output */
-+ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_HPVOL_SET);
-+ /* Power down HP output */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET);
-+
-+ /* Mute speaker amp */
-+ __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_SPEAKERCTRL_SET);
-+ /* Power down speaker amp */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_SPEAKER,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET);
-+
-+ /* Mute DAC */
-+ __raw_writel(BM_AUDIOOUT_DACVOLUME_MUTE_LEFT |
-+ BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET);
-+ /* Power down DAC */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_DAC,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET);
-+
-+ /* Gate DAC clocks */
-+ __raw_writel(BM_AUDIOOUT_ANACLKCTRL_CLKGATE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACLKCTRL_SET);
-+ __raw_writel(BM_AUDIOOUT_CTRL_CLKGATE,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET);
-+}
-+
-+static void
-+mxs_codec_adc_power_on(struct mxs_adc_priv *mxs_adc)
-+{
-+ u32 reg;
-+
-+ /* Ungate ADC clocks */
-+ __raw_writel(BM_AUDIOIN_CTRL_CLKGATE,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_CLR);
-+ __raw_writel(BM_AUDIOIN_ANACLKCTRL_CLKGATE,
-+ mxs_adc->ain_base + HW_AUDIOIN_ANACLKCTRL_CLR);
-+
-+ /* 16 bit word length */
-+ __raw_writel(BM_AUDIOIN_CTRL_WORD_LENGTH,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_SET);
-+
-+ /* Unmute ADC channels */
-+ __raw_writel(BM_AUDIOIN_ADCVOL_MUTE,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR);
-+
-+ /*
-+ * The MUTE_LEFT and MUTE_RIGHT fields need to be cleared.
-+ * They aren't presented in the datasheet, so this is hardcode.
-+ */
-+ __raw_writel(0x01000100, mxs_adc->ain_base + HW_AUDIOIN_ADCVOLUME_CLR);
-+
-+ /* Set the Input channel gain 3dB */
-+ __raw_writel(BM_AUDIOIN_ADCVOL_GAIN_LEFT,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR);
-+ __raw_writel(BM_AUDIOIN_ADCVOL_GAIN_RIGHT,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR);
-+ __raw_writel(BF(2, AUDIOIN_ADCVOL_GAIN_LEFT),
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET);
-+ __raw_writel(BF(2, AUDIOIN_ADCVOL_GAIN_RIGHT),
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET);
-+
-+ /* Select default input - Microphone */
-+ __raw_writel(BM_AUDIOIN_ADCVOL_SELECT_LEFT,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR);
-+ __raw_writel(BM_AUDIOIN_ADCVOL_SELECT_RIGHT,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR);
-+ __raw_writel(BF
-+ (BV_AUDIOIN_ADCVOL_SELECT__MIC,
-+ AUDIOIN_ADCVOL_SELECT_LEFT),
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET);
-+ __raw_writel(BF
-+ (BV_AUDIOIN_ADCVOL_SELECT__MIC,
-+ AUDIOIN_ADCVOL_SELECT_RIGHT),
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET);
-+
-+ /* Supply bias voltage to microphone */
-+ __raw_writel(BF(1, AUDIOIN_MICLINE_MIC_RESISTOR),
-+ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET);
-+ __raw_writel(BM_AUDIOIN_MICLINE_MIC_SELECT,
-+ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET);
-+ __raw_writel(BF(1, AUDIOIN_MICLINE_MIC_GAIN),
-+ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET);
-+ __raw_writel(BF(7, AUDIOIN_MICLINE_MIC_BIAS),
-+ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET);
-+
-+ /* Set max ADC volume */
-+ reg = __raw_readl(mxs_adc->ain_base + HW_AUDIOIN_ADCVOLUME);
-+ reg &= ~BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT;
-+ reg &= ~BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT;
-+ reg |= BF(ADC_VOLUME_MAX, AUDIOIN_ADCVOLUME_VOLUME_LEFT);
-+ reg |= BF(ADC_VOLUME_MAX, AUDIOIN_ADCVOLUME_VOLUME_RIGHT);
-+ __raw_writel(reg, mxs_adc->ain_base + HW_AUDIOIN_ADCVOLUME);
-+}
-+
-+static void
-+mxs_codec_adc_power_down(struct mxs_adc_priv *mxs_adc)
-+{
-+ /* Mute ADC channels */
-+ __raw_writel(BM_AUDIOIN_ADCVOL_MUTE,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET);
-+
-+ /* Power Down ADC */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_ADC | BM_AUDIOOUT_PWRDN_RIGHT_ADC,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET);
-+
-+ /* Gate ADC clocks */
-+ __raw_writel(BM_AUDIOIN_CTRL_CLKGATE,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_SET);
-+ __raw_writel(BM_AUDIOIN_ANACLKCTRL_CLKGATE,
-+ mxs_adc->ain_base + HW_AUDIOIN_ANACLKCTRL_SET);
-+
-+ /* Disable bias voltage to microphone */
-+ __raw_writel(BF(0, AUDIOIN_MICLINE_MIC_RESISTOR),
-+ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET);
-+}
-+
-+static void mxs_codec_dac_enable(struct mxs_adc_priv *mxs_adc)
-+{
-+ /* Move DAC codec out of reset */
-+ __raw_writel(BM_AUDIOOUT_CTRL_SFTRST,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_CLR);
-+
-+ /* Reduce analog power */
-+ __raw_writel(BM_AUDIOOUT_TEST_HP_I1_ADJ,
-+ mxs_adc->aout_base + HW_AUDIOOUT_TEST_CLR);
-+ __raw_writel(BF(0x1, AUDIOOUT_TEST_HP_I1_ADJ),
-+ mxs_adc->aout_base + HW_AUDIOOUT_TEST_SET);
-+ __raw_writel(BM_AUDIOOUT_REFCTRL_LOW_PWR,
-+ mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL_SET);
-+ __raw_writel(BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS,
-+ mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL_SET);
-+ __raw_writel(BM_AUDIOOUT_REFCTRL_BIAS_CTRL,
-+ mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL_CLR);
-+ __raw_writel(BF(0x1, AUDIOOUT_REFCTRL_BIAS_CTRL),
-+ mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL_CLR);
-+
-+ /* Set Vag value */
-+ mxs_codec_dac_set_vag(mxs_adc);
-+
-+ /* Power on DAC codec */
-+ mxs_codec_dac_power_on(mxs_adc);
-+}
-+
-+static void mxs_codec_dac_disable(struct mxs_adc_priv *mxs_adc)
-+{
-+ mxs_codec_dac_power_down(mxs_adc);
-+}
-+
-+static void mxs_codec_adc_enable(struct mxs_adc_priv *mxs_adc)
-+{
-+ /* Move ADC codec out of reset */
-+ __raw_writel(BM_AUDIOIN_CTRL_SFTRST,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_CLR);
-+
-+ /* Power on ADC codec */
-+ mxs_codec_adc_power_on(mxs_adc);
-+}
-+
-+static void mxs_codec_adc_disable(struct mxs_adc_priv *mxs_adc)
-+{
-+ mxs_codec_adc_power_down(mxs_adc);
-+}
-+
-+static void mxs_codec_startup(struct snd_soc_codec *codec)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+
-+ /* Soft reset DAC block */
-+ __raw_writel(BM_AUDIOOUT_CTRL_SFTRST,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET);
-+ while (!(__raw_readl(mxs_adc->aout_base + HW_AUDIOOUT_CTRL)
-+ & BM_AUDIOOUT_CTRL_CLKGATE)){
-+ }
-+
-+ /* Soft reset ADC block */
-+ __raw_writel(BM_AUDIOIN_CTRL_SFTRST,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_SET);
-+ while (!(__raw_readl(mxs_adc->ain_base + HW_AUDIOIN_CTRL)
-+ & BM_AUDIOIN_CTRL_CLKGATE)){
-+ }
-+
-+ mxs_codec_dac_enable(mxs_adc);
-+ mxs_codec_adc_enable(mxs_adc);
-+
-+ /* Sync regs and cache */
-+ mxs_codec_sync_reg_cache(codec);
-+}
-+
-+static void mxs_codec_stop(struct snd_soc_codec *codec)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+
-+ mxs_codec_dac_disable(mxs_adc);
-+ mxs_codec_adc_disable(mxs_adc);
-+}
-+/* END Codec routines */
-+
-+/* kcontrol */
-+static int dac_info_volsw(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
-+ uinfo->count = 2;
-+ uinfo->value.integer.min = 0;
-+ uinfo->value.integer.max = 0xf;
-+ return 0;
-+}
-+
-+static int dac_get_volsw(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+ int reg, l, r;
-+ int i;
-+
-+ reg = __raw_readl(mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME);
-+
-+ l = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT) >>
-+ BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT;
-+ r = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT) >>
-+ BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT;
-+ /*Left channel */
-+ i = 0;
-+ while (i < 16) {
-+ if (l == dac_volumn_control_word[i]) {
-+ ucontrol->value.integer.value[0] = i;
-+ break;
-+ }
-+ i++;
-+ }
-+ if (i == 16)
-+ ucontrol->value.integer.value[0] = i;
-+ /*Right channel */
-+ i = 0;
-+ while (i < 16) {
-+ if (r == dac_volumn_control_word[i]) {
-+ ucontrol->value.integer.value[1] = i;
-+ break;
-+ }
-+ i++;
-+ }
-+ if (i == 16)
-+ ucontrol->value.integer.value[1] = i;
-+
-+ return 0;
-+}
-+
-+static int dac_put_volsw(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+ int reg, l, r;
-+ int i;
-+
-+ i = ucontrol->value.integer.value[0];
-+ l = dac_volumn_control_word[i];
-+ /*Get dac volume for left channel */
-+ reg = BF(l, AUDIOOUT_DACVOLUME_VOLUME_LEFT);
-+
-+ i = ucontrol->value.integer.value[1];
-+ r = dac_volumn_control_word[i];
-+ /*Get dac volume for right channel */
-+ reg = reg | BF(r, AUDIOOUT_DACVOLUME_VOLUME_RIGHT);
-+
-+ /*Clear left/right dac volume */
-+ __raw_writel(BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT |
-+ BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_CLR);
-+ __raw_writel(reg, mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET);
-+
-+ return 0;
-+}
-+
-+static const char *mxs_codec_adc_input_sel[] = {
-+ "Mic", "Line In 1", "Head Phone", "Line In 2" };
-+
-+static const char *mxs_codec_hp_output_sel[] = { "DAC Out", "Line In 1" };
-+
-+static const char *mxs_codec_adc_3d_sel[] = {
-+ "Off", "Low", "Medium", "High" };
-+
-+static const struct soc_enum mxs_codec_enum[] = {
-+ SOC_ENUM_SINGLE(ADC_ADCVOL_L, 12, 4, mxs_codec_adc_input_sel),
-+ SOC_ENUM_SINGLE(ADC_ADCVOL_L, 4, 4, mxs_codec_adc_input_sel),
-+ SOC_ENUM_SINGLE(DAC_HPVOL_H, 0, 2, mxs_codec_hp_output_sel),
-+ SOC_ENUM_SINGLE(DAC_CTRL_L, 8, 4, mxs_codec_adc_3d_sel),
-+};
-+
-+static const struct snd_kcontrol_new mxs_snd_controls[] = {
-+ /* Playback Volume */
-+ {
-+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
-+ .name = "DAC Playback Volume",
-+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
-+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
-+ .info = dac_info_volsw,
-+ .get = dac_get_volsw,
-+ .put = dac_put_volsw,
-+ },
-+
-+ SOC_DOUBLE_R("DAC Playback Switch",
-+ DAC_VOLUME_H, DAC_VOLUME_L, 8, 0x01, 1),
-+ SOC_DOUBLE("HP Playback Volume", DAC_HPVOL_L, 8, 0, 0x7F, 1),
-+
-+ /* Capture Volume */
-+ SOC_DOUBLE_R("ADC Capture Volume",
-+ ADC_VOLUME_H, ADC_VOLUME_L, 0, 0xFF, 0),
-+ SOC_DOUBLE("ADC PGA Capture Volume", ADC_ADCVOL_L, 8, 0, 0x0F, 0),
-+ SOC_SINGLE("ADC PGA Capture Switch", ADC_ADCVOL_H, 8, 0x1, 1),
-+ SOC_SINGLE("Mic PGA Capture Volume", ADC_MICLINE_L, 0, 0x03, 0),
-+
-+ /* Virtual 3D effect */
-+ SOC_ENUM("3D effect", mxs_codec_enum[3]),
-+};
-+/* END kcontrol */
-+
-+/* DAPM */
-+static int pga_event(struct snd_soc_dapm_widget *w,
-+ struct snd_kcontrol *kcontrol, int event)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(w->codec);
-+
-+ switch (event) {
-+ case SND_SOC_DAPM_PRE_PMU:
-+ /* Prepare powering up HP and SPEAKER output */
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_HOLD_GND,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET);
-+ __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND,
-+ mxs_adc->rtc_base + HW_RTC_PERSISTENT0_SET);
-+ msleep(100);
-+ break;
-+ case SND_SOC_DAPM_POST_PMU:
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_HOLD_GND,
-+ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ break;
-+ case SND_SOC_DAPM_POST_PMD:
-+ __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND,
-+ mxs_adc->rtc_base + HW_RTC_PERSISTENT0_CLR);
-+ break;
-+ }
-+ return 0;
-+}
-+
-+static int adc_event(struct snd_soc_dapm_widget *w,
-+ struct snd_kcontrol *kcontrol, int event)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(w->codec);
-+
-+ switch (event) {
-+ case SND_SOC_DAPM_PRE_PMU:
-+ __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND,
-+ mxs_adc->rtc_base + HW_RTC_PERSISTENT0_SET);
-+ msleep(100);
-+ break;
-+ case SND_SOC_DAPM_POST_PMD:
-+ __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND,
-+ mxs_adc->rtc_base + HW_RTC_PERSISTENT0_CLR);
-+ break;
-+ }
-+ return 0;
-+}
-+
-+/* Left ADC Mux */
-+static const struct snd_kcontrol_new mxs_left_adc_controls =
-+SOC_DAPM_ENUM("Route", mxs_codec_enum[0]);
-+
-+/* Right ADC Mux */
-+static const struct snd_kcontrol_new mxs_right_adc_controls =
-+SOC_DAPM_ENUM("Route", mxs_codec_enum[1]);
-+
-+/* Head Phone Mux */
-+static const struct snd_kcontrol_new mxs_hp_controls =
-+SOC_DAPM_ENUM("Route", mxs_codec_enum[2]);
-+
-+static const struct snd_soc_dapm_widget mxs_dapm_widgets[] = {
-+ SND_SOC_DAPM_ADC_E("ADC", "Capture", DAC_PWRDN_L, 8, 1, adc_event,
-+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
-+
-+ SND_SOC_DAPM_DAC("DAC", "Playback", DAC_PWRDN_L, 12, 1),
-+
-+ SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
-+ &mxs_left_adc_controls),
-+ SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
-+ &mxs_right_adc_controls),
-+ SND_SOC_DAPM_MUX("HP Mux", SND_SOC_NOPM, 0, 0,
-+ &mxs_hp_controls),
-+ SND_SOC_DAPM_PGA_E("HP AMP", DAC_PWRDN_L, 0, 1, NULL, 0, pga_event,
-+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
-+ SND_SOC_DAPM_POST_PMD),
-+ SND_SOC_DAPM_PGA("SPEAKER AMP", DAC_PWRDN_H, 8, 1, NULL, 0),
-+ SND_SOC_DAPM_INPUT("LINE1L"),
-+ SND_SOC_DAPM_INPUT("LINE1R"),
-+ SND_SOC_DAPM_INPUT("LINE2L"),
-+ SND_SOC_DAPM_INPUT("LINE2R"),
-+ SND_SOC_DAPM_INPUT("MIC"),
-+
-+ SND_SOC_DAPM_OUTPUT("SPEAKER"),
-+ SND_SOC_DAPM_OUTPUT("HPL"),
-+ SND_SOC_DAPM_OUTPUT("HPR"),
-+};
-+
-+/* routes for sgtl5000 */
-+static const struct snd_soc_dapm_route mxs_dapm_routes[] = {
-+ /* Left ADC Mux */
-+ {"Left ADC Mux", "Mic", "MIC"},
-+ {"Left ADC Mux", "Line In 1", "LINE1L"},
-+ {"Left ADC Mux", "Line In 2", "LINE2L"},
-+ {"Left ADC Mux", "Head Phone", "HPL"},
-+
-+ /* Right ADC Mux */
-+ {"Right ADC Mux", "Mic", "MIC"},
-+ {"Right ADC Mux", "Line In 1", "LINE1R"},
-+ {"Right ADC Mux", "Line In 2", "LINE2R"},
-+ {"Right ADC Mux", "Head Phone", "HPR"},
-+
-+ /* ADC */
-+ {"ADC", NULL, "Left ADC Mux"},
-+ {"ADC", NULL, "Right ADC Mux"},
-+
-+ /* HP Mux */
-+ {"HP Mux", "DAC Out", "DAC"},
-+ {"HP Mux", "Line In 1", "LINE1L"},
-+ {"HP Mux", "Line In 1", "LINE1R"},
-+
-+ /* HP amp */
-+ {"HP AMP", NULL, "HP Mux"},
-+ /* HP output */
-+ {"HPR", NULL, "HP AMP"},
-+ {"HPL", NULL, "HP AMP"},
-+
-+ /* Speaker amp */
-+ {"SPEAKER AMP", NULL, "DAC"},
-+ {"SPEAKER", NULL, "SPEAKER AMP"},
-+};
-+/* END DAPM */
-+
-+static int mxs_set_bias_level(struct snd_soc_codec *codec,
-+ enum snd_soc_bias_level level)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+
-+ pr_debug("dapm level %d\n", level);
-+ switch (level) {
-+ case SND_SOC_BIAS_ON: /* full On */
-+ if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
-+ break;
-+ break;
-+
-+ case SND_SOC_BIAS_PREPARE: /* partial On */
-+ if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
-+ break;
-+ /* Set Capless mode */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_CAPLESS,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_CLR);
-+ break;
-+
-+ case SND_SOC_BIAS_STANDBY: /* Off, with power */
-+ if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
-+ break;
-+ /* Unset Capless mode */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_CAPLESS,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET);
-+ break;
-+
-+ case SND_SOC_BIAS_OFF: /* Off, without power */
-+ if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
-+ break;
-+ /* Unset Capless mode */
-+ __raw_writel(BM_AUDIOOUT_PWRDN_CAPLESS,
-+ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET);
-+ break;
-+ }
-+
-+ codec->dapm.bias_level = level;
-+ return 0;
-+}
-+
-+/* MXS-ADC Codec DAI driver */
-+static int mxs_pcm_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params,
-+ struct snd_soc_dai *dai)
-+{
-+ struct snd_soc_codec *codec = dai->codec;
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec);
-+ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0;
-+ int i;
-+ u32 srr_value = 0;
-+ u32 src_hold = 0;
-+
-+ i = get_srr_values(params_rate(params));
-+ if (i < 0)
-+ dev_warn(codec->dev, "%s doesn't support rate %d\n",
-+ codec->name, params_rate(params));
-+ else {
-+ src_hold = srr_values[i].src_hold;
-+
-+ srr_value =
-+ BF(srr_values[i].basemult, AUDIOOUT_DACSRR_BASEMULT) |
-+ BF(srr_values[i].src_int, AUDIOOUT_DACSRR_SRC_INT) |
-+ BF(srr_values[i].src_frac, AUDIOOUT_DACSRR_SRC_FRAC) |
-+ BF(src_hold, AUDIOOUT_DACSRR_SRC_HOLD);
-+
-+ if (playback)
-+ __raw_writel(srr_value,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACSRR);
-+ else
-+ __raw_writel(srr_value,
-+ mxs_adc->ain_base + HW_AUDIOIN_ADCSRR);
-+ }
-+
-+ switch (params_format(params)) {
-+ case SNDRV_PCM_FORMAT_S16_LE:
-+ if (playback)
-+ __raw_writel(BM_AUDIOOUT_CTRL_WORD_LENGTH,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET);
-+ else
-+ __raw_writel(BM_AUDIOIN_CTRL_WORD_LENGTH,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_SET);
-+
-+ break;
-+
-+ case SNDRV_PCM_FORMAT_S32_LE:
-+ if (playback)
-+ __raw_writel(BM_AUDIOOUT_CTRL_WORD_LENGTH,
-+ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_CLR);
-+ else
-+ __raw_writel(BM_AUDIOIN_CTRL_WORD_LENGTH,
-+ mxs_adc->ain_base + HW_AUDIOIN_CTRL_CLR);
-+
-+ break;
-+
-+ default:
-+ dev_warn(codec->dev, "%s doesn't support format %d\n",
-+ codec->name, params_format(params));
-+
-+ }
-+
-+ return 0;
-+}
-+
-+/* mute the codec used by alsa core */
-+static int mxs_codec_dig_mute(struct snd_soc_dai *codec_dai, int mute)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec_dai->codec);
-+ int l, r;
-+ int ll, rr;
-+ u32 reg, reg1, reg2;
-+ u32 dac_mask = BM_AUDIOOUT_DACVOLUME_MUTE_LEFT |
-+ BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT;
-+
-+ if (mute) {
-+ reg = __raw_readl(mxs_adc->aout_base + \
-+ HW_AUDIOOUT_DACVOLUME);
-+
-+ reg1 = reg & ~BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT;
-+ reg1 = reg1 & ~BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT;
-+
-+ l = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT) >>
-+ BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT;
-+ r = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT) >>
-+ BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT;
-+
-+ /* fade out dac vol */
-+ while ((l > DAC_VOLUME_MIN) || (r > DAC_VOLUME_MIN)) {
-+ l -= 0x8;
-+ r -= 0x8;
-+ ll = l > DAC_VOLUME_MIN ? l : DAC_VOLUME_MIN;
-+ rr = r > DAC_VOLUME_MIN ? r : DAC_VOLUME_MIN;
-+ reg2 = reg1 | BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(ll)
-+ | BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(rr);
-+ __raw_writel(reg2,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME);
-+ msleep(1);
-+ }
-+
-+ __raw_writel(dac_mask,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET);
-+ reg = reg | dac_mask;
-+ __raw_writel(reg,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME);
-+ } else
-+ __raw_writel(dac_mask,
-+ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_CLR);
-+
-+ return 0;
-+}
-+
-+#define MXS_ADC_RATES SNDRV_PCM_RATE_8000_192000
-+#define MXS_ADC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
-+
-+static const struct snd_soc_dai_ops mxs_codec_dai_ops = {
-+ .hw_params = mxs_pcm_hw_params,
-+ .digital_mute = mxs_codec_dig_mute,
-+};
-+
-+static struct snd_soc_dai_driver mxs_codec_dai_driver = {
-+ .name = "mxs-builtin-codec-dai",
-+ .playback = {
-+ .stream_name = "Playback",
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = MXS_ADC_RATES,
-+ .formats = MXS_ADC_FORMATS,
-+ },
-+ .capture = {
-+ .stream_name = "Capture",
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = MXS_ADC_RATES,
-+ .formats = MXS_ADC_FORMATS,
-+ },
-+ .ops = &mxs_codec_dai_ops,
-+};
-+/* END MXS-ADC Codec DAI driver */
-+
-+/* MXS-ADC Codec driver */
-+static int mxs_codec_driver_probe(struct snd_soc_codec *codec)
-+{
-+ int ret = 0;
-+ /* We don't use snd_soc_codec_set_cache_io because we are using
-+ * our own IO functions: write, read. */
-+
-+ mxs_codec_startup(codec);
-+
-+ /* leading to standby state */
-+ ret = mxs_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
-+ if (ret)
-+ goto err;
-+
-+ return 0;
-+
-+err:
-+ mxs_codec_stop(codec);
-+
-+ return ret;
-+}
-+
-+static int mxs_codec_driver_remove(struct snd_soc_codec *codec)
-+{
-+ mxs_codec_stop(codec);
-+
-+ return 0;
-+}
-+
-+// static int mxs_codec_driver_suspend(struct snd_soc_codec *codec)
-+// {
-+// /* TODO Enable power management. */
-+// return 0;
-+// }
-+
-+// static int mxs_codec_driver_resume(struct snd_soc_codec *codec)
-+// {
-+// /* TODO Enable power management. */
-+// return 0;
-+// }
-+
-+static struct snd_soc_codec_driver mxs_codec_driver = {
-+ .probe = mxs_codec_driver_probe,
-+ .remove = mxs_codec_driver_remove,
-+// .suspend = mxs_codec_driver_suspend,
-+// .resume = mxs_codec_driver_resume,
-+ .set_bias_level = mxs_set_bias_level,
-+ .reg_cache_size = ADC_REGNUM,
-+ .reg_word_size = sizeof(u16),
-+ .reg_cache_step = 1,
-+// .reg_cache_default = mxsadc_regs,
-+// .volatile_register = sgtl5000_volatile_register,
-+ .controls = mxs_snd_controls,
-+ .num_controls = ARRAY_SIZE(mxs_snd_controls),
-+ .dapm_widgets = mxs_dapm_widgets,
-+ .num_dapm_widgets = ARRAY_SIZE(mxs_dapm_widgets),
-+ .dapm_routes = mxs_dapm_routes,
-+ .num_dapm_routes = ARRAY_SIZE(mxs_dapm_routes),
-+ .write = mxs_codec_write,
-+ .read = mxs_codec_read,
-+};
-+/* END MXS-ADC Codec driver */
-+
-+/* Underlying platform device that registers codec */
-+static int mxs_adc_probe(struct platform_device *pdev)
-+{
-+ struct mxs_adc_priv *mxs_adc;
-+ struct resource *r;
-+ int ret;
-+
-+ mxs_adc = devm_kzalloc(&pdev->dev, sizeof(struct mxs_adc_priv), GFP_KERNEL);
-+ if (!mxs_adc)
-+ return -ENOMEM;
-+
-+ platform_set_drvdata(pdev, mxs_adc);
-+
-+ /* audio-in IO memory */
-+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audioin");
-+ if (IS_ERR(r)) {
-+ dev_err(&pdev->dev, "failed to get resource\n");
-+ return PTR_ERR(r);
-+ }
-+
-+ mxs_adc->ain_base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
-+ if (IS_ERR(mxs_adc->ain_base)) {
-+ dev_err(&pdev->dev, "ioremap failed\n");
-+ return PTR_ERR(mxs_adc->ain_base);
-+ }
-+
-+ /* audio-out IO memory */
-+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audioout");
-+ if (IS_ERR(r)) {
-+ dev_err(&pdev->dev, "failed to get resource\n");
-+ return PTR_ERR(r);
-+ }
-+
-+ mxs_adc->aout_base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
-+ if (IS_ERR(mxs_adc->aout_base)) {
-+ dev_err(&pdev->dev, "ioremap failed\n");
-+ return PTR_ERR(mxs_adc->aout_base);
-+ }
-+
-+ /* rtc IO memory */
-+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
-+ if (IS_ERR(r)) {
-+ dev_err(&pdev->dev, "failed to get resource\n");
-+ return PTR_ERR(r);
-+ }
-+
-+ mxs_adc->rtc_base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
-+ if (IS_ERR(mxs_adc->rtc_base)) {
-+ dev_err(&pdev->dev, "ioremap failed\n");
-+ return PTR_ERR(mxs_adc->rtc_base);
-+ }
-+
-+ /* Get audio clock */
-+ mxs_adc->clk = devm_clk_get(&pdev->dev, "filt");
-+ if (IS_ERR(mxs_adc->clk)) {
-+ ret = PTR_ERR(mxs_adc->clk);
-+ dev_err(&pdev->dev, "%s: Clock initialization failed\n", __func__);
-+ return ret;
-+ }
-+
-+ /* Turn on audio clock */
-+ ret = clk_prepare_enable(mxs_adc->clk);
-+ if (unlikely(ret != 0)) {
-+ dev_err(&pdev->dev, "%s: Clock prepare or enable failed\n", __func__);
-+ return ret;
-+ }
-+
-+ ret = snd_soc_register_codec(&pdev->dev,
-+ &mxs_codec_driver,&mxs_codec_dai_driver, 1);
-+ if (unlikely(ret != 0)) {
-+ dev_err(&pdev->dev, "Codec registration failed\n");
-+ goto disable_clk;
-+ }
-+
-+ return 0;
-+
-+disable_clk:
-+ clk_disable_unprepare(mxs_adc->clk);
-+ return ret;
-+}
-+
-+static int mxs_adc_remove(struct platform_device *pdev)
-+{
-+ struct mxs_adc_priv *mxs_adc = platform_get_drvdata(pdev);
-+
-+ clk_disable_unprepare(mxs_adc->clk);
-+ snd_soc_unregister_codec(&pdev->dev);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mxs_adc_dt_ids[] = {
-+ { .compatible = "fsl,mxs-builtin-codec", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mxs_adc_dt_ids);
-+
-+static struct platform_driver mxs_adc_driver = {
-+ .driver = {
-+ .name = "mxs-builtin-codec",
-+ .owner = THIS_MODULE,
-+ .of_match_table = mxs_adc_dt_ids,
-+ },
-+ .probe = mxs_adc_probe,
-+ .remove = mxs_adc_remove,
-+};
-+
-+module_platform_driver(mxs_adc_driver);
-+/* END Underlying platform device that registers codec */
-+
-+MODULE_DESCRIPTION("Freescale MXS ADC/DAC SoC Codec Driver");
-+MODULE_AUTHOR("Michal Ulianko <michal.ulianko@gmail.com>");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/sound/soc/codecs/mxs-builtin-codec.h
-@@ -0,0 +1,825 @@
-+#ifndef __MXS_ADC_CODEC_H
-+
-+#include <linux/io.h>
-+
-+/* MXS ADC/DAC registers */
-+#define DAC_CTRL_L 0
-+#define DAC_CTRL_H 1
-+#define DAC_STAT_L 2
-+#define DAC_STAT_H 3
-+#define DAC_SRR_L 4
-+#define DAC_VOLUME_L 6
-+#define DAC_VOLUME_H 7
-+#define DAC_DEBUG_L 8
-+#define DAC_DEBUG_H 9
-+#define DAC_HPVOL_L 10
-+#define DAC_HPVOL_H 11
-+#define DAC_PWRDN_L 12
-+#define DAC_PWRDN_H 13
-+#define DAC_REFCTRL_L 14
-+#define DAC_REFCTRL_H 15
-+#define DAC_ANACTRL_L 16
-+#define DAC_ANACTRL_H 17
-+#define DAC_TEST_L 18
-+#define DAC_TEST_H 19
-+#define DAC_BISTCTRL_L 20
-+#define DAC_BISTCTRL_H 21
-+#define DAC_BISTSTAT0_L 22
-+#define DAC_BISTSTAT0_H 23
-+#define DAC_BISTSTAT1_L 24
-+#define DAC_BISTSTAT1_H 25
-+#define DAC_ANACLKCTRL_L 26
-+#define DAC_ANACLKCTRL_H 27
-+#define DAC_DATA_L 28
-+#define DAC_DATA_H 29
-+#define DAC_SPEAKERCTRL_L 30
-+#define DAC_SPEAKERCTRL_H 31
-+#define DAC_VERSION_L 32
-+#define DAC_VERSION_H 33
-+#define ADC_CTRL_L 34
-+#define ADC_CTRL_H 35
-+#define ADC_STAT_L 36
-+#define ADC_STAT_H 37
-+#define ADC_SRR_L 38
-+#define ADC_SRR_H 39
-+#define ADC_VOLUME_L 40
-+#define ADC_VOLUME_H 41
-+#define ADC_DEBUG_L 42
-+#define ADC_DEBUG_H 43
-+#define ADC_ADCVOL_L 44
-+#define ADC_ADCVOL_H 45
-+#define ADC_MICLINE_L 46
-+#define ADC_MICLINE_H 47
-+#define ADC_ANACLKCTRL_L 48
-+#define ADC_ANACLKCTRL_H 49
-+#define ADC_DATA_L 50
-+#define ADC_DATA_H 51
-+
-+#define ADC_REGNUM 52
-+
-+#define DAC_VOLUME_MIN 0x37
-+#define DAC_VOLUME_MAX 0xFE
-+#define ADC_VOLUME_MIN 0x37
-+#define ADC_VOLUME_MAX 0xFE
-+#define HP_VOLUME_MAX 0x0
-+#define HP_VOLUME_MIN 0x7F
-+#define LO_VOLUME_MAX 0x0
-+#define LO_VOLUME_MIN 0x1F
-+
-+/* RTC */
-+#define HW_RTC_PERSISTENT0 (0x00000060)
-+#define HW_RTC_PERSISTENT0_SET (0x00000064)
-+#define HW_RTC_PERSISTENT0_CLR (0x00000068)
-+#define HW_RTC_PERSISTENT0_TOG (0x0000006c)
-+
-+// TODO
-+//#define BM_RTC_PERSISTENT0_RELEASE_GND 0x00080000
-+
-+/* AUDIOOUT */
-+#define HW_AUDIOOUT_CTRL (0x00000000)
-+#define HW_AUDIOOUT_CTRL_SET (0x00000004)
-+#define HW_AUDIOOUT_CTRL_CLR (0x00000008)
-+#define HW_AUDIOOUT_CTRL_TOG (0x0000000c)
-+
-+#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
-+#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
-+#define BP_AUDIOOUT_CTRL_RSRVD4 21
-+#define BM_AUDIOOUT_CTRL_RSRVD4 0x3FE00000
-+#define BF_AUDIOOUT_CTRL_RSRVD4(v) \
-+ (((v) << 21) & BM_AUDIOOUT_CTRL_RSRVD4)
-+#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT 16
-+#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT 0x001F0000
-+#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) \
-+ (((v) << 16) & BM_AUDIOOUT_CTRL_DMAWAIT_COUNT)
-+#define BM_AUDIOOUT_CTRL_RSRVD3 0x00008000
-+#define BM_AUDIOOUT_CTRL_LR_SWAP 0x00004000
-+#define BM_AUDIOOUT_CTRL_EDGE_SYNC 0x00002000
-+#define BM_AUDIOOUT_CTRL_INVERT_1BIT 0x00001000
-+#define BP_AUDIOOUT_CTRL_RSRVD2 10
-+#define BM_AUDIOOUT_CTRL_RSRVD2 0x00000C00
-+#define BF_AUDIOOUT_CTRL_RSRVD2(v) \
-+ (((v) << 10) & BM_AUDIOOUT_CTRL_RSRVD2)
-+#define BP_AUDIOOUT_CTRL_SS3D_EFFECT 8
-+#define BM_AUDIOOUT_CTRL_SS3D_EFFECT 0x00000300
-+#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v) \
-+ (((v) << 8) & BM_AUDIOOUT_CTRL_SS3D_EFFECT)
-+#define BM_AUDIOOUT_CTRL_RSRVD1 0x00000080
-+#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
-+#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 0x00000020
-+#define BM_AUDIOOUT_CTRL_LOOPBACK 0x00000010
-+#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
-+#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
-+#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
-+#define BM_AUDIOOUT_CTRL_RUN 0x00000001
-+
-+#define HW_AUDIOOUT_STAT (0x00000010)
-+#define HW_AUDIOOUT_STAT_SET (0x00000014)
-+#define HW_AUDIOOUT_STAT_CLR (0x00000018)
-+#define HW_AUDIOOUT_STAT_TOG (0x0000001c)
-+
-+#define BM_AUDIOOUT_STAT_DAC_PRESENT 0x80000000
-+#define BP_AUDIOOUT_STAT_RSRVD1 0
-+#define BM_AUDIOOUT_STAT_RSRVD1 0x7FFFFFFF
-+#define BF_AUDIOOUT_STAT_RSRVD1(v) \
-+ (((v) << 0) & BM_AUDIOOUT_STAT_RSRVD1)
-+
-+#define HW_AUDIOOUT_DACSRR (0x00000020)
-+#define HW_AUDIOOUT_DACSRR_SET (0x00000024)
-+#define HW_AUDIOOUT_DACSRR_CLR (0x00000028)
-+#define HW_AUDIOOUT_DACSRR_TOG (0x0000002c)
-+
-+#define BM_AUDIOOUT_DACSRR_OSR 0x80000000
-+#define BV_AUDIOOUT_DACSRR_OSR__OSR6 0x0
-+#define BV_AUDIOOUT_DACSRR_OSR__OSR12 0x1
-+#define BP_AUDIOOUT_DACSRR_BASEMULT 28
-+#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
-+#define BF_AUDIOOUT_DACSRR_BASEMULT(v) \
-+ (((v) << 28) & BM_AUDIOOUT_DACSRR_BASEMULT)
-+#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE 0x1
-+#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE 0x2
-+#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE 0x4
-+#define BM_AUDIOOUT_DACSRR_RSRVD2 0x08000000
-+#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
-+#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
-+#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v) \
-+ (((v) << 24) & BM_AUDIOOUT_DACSRR_SRC_HOLD)
-+#define BP_AUDIOOUT_DACSRR_RSRVD1 21
-+#define BM_AUDIOOUT_DACSRR_RSRVD1 0x00E00000
-+#define BF_AUDIOOUT_DACSRR_RSRVD1(v) \
-+ (((v) << 21) & BM_AUDIOOUT_DACSRR_RSRVD1)
-+#define BP_AUDIOOUT_DACSRR_SRC_INT 16
-+#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
-+#define BF_AUDIOOUT_DACSRR_SRC_INT(v) \
-+ (((v) << 16) & BM_AUDIOOUT_DACSRR_SRC_INT)
-+#define BP_AUDIOOUT_DACSRR_RSRVD0 13
-+#define BM_AUDIOOUT_DACSRR_RSRVD0 0x0000E000
-+#define BF_AUDIOOUT_DACSRR_RSRVD0(v) \
-+ (((v) << 13) & BM_AUDIOOUT_DACSRR_RSRVD0)
-+#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
-+#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
-+#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v) \
-+ (((v) << 0) & BM_AUDIOOUT_DACSRR_SRC_FRAC)
-+
-+#define HW_AUDIOOUT_DACVOLUME (0x00000030)
-+#define HW_AUDIOOUT_DACVOLUME_SET (0x00000034)
-+#define HW_AUDIOOUT_DACVOLUME_CLR (0x00000038)
-+#define HW_AUDIOOUT_DACVOLUME_TOG (0x0000003c)
-+
-+#define BP_AUDIOOUT_DACVOLUME_RSRVD4 29
-+#define BM_AUDIOOUT_DACVOLUME_RSRVD4 0xE0000000
-+#define BF_AUDIOOUT_DACVOLUME_RSRVD4(v) \
-+ (((v) << 29) & BM_AUDIOOUT_DACVOLUME_RSRVD4)
-+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 0x10000000
-+#define BP_AUDIOOUT_DACVOLUME_RSRVD3 26
-+#define BM_AUDIOOUT_DACVOLUME_RSRVD3 0x0C000000
-+#define BF_AUDIOOUT_DACVOLUME_RSRVD3(v) \
-+ (((v) << 26) & BM_AUDIOOUT_DACVOLUME_RSRVD3)
-+#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
-+#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
-+#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT 16
-+#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT 0x00FF0000
-+#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) \
-+ (((v) << 16) & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT)
-+#define BP_AUDIOOUT_DACVOLUME_RSRVD2 13
-+#define BM_AUDIOOUT_DACVOLUME_RSRVD2 0x0000E000
-+#define BF_AUDIOOUT_DACVOLUME_RSRVD2(v) \
-+ (((v) << 13) & BM_AUDIOOUT_DACVOLUME_RSRVD2)
-+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 0x00001000
-+#define BP_AUDIOOUT_DACVOLUME_RSRVD1 9
-+#define BM_AUDIOOUT_DACVOLUME_RSRVD1 0x00000E00
-+#define BF_AUDIOOUT_DACVOLUME_RSRVD1(v) \
-+ (((v) << 9) & BM_AUDIOOUT_DACVOLUME_RSRVD1)
-+#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
-+#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0
-+#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0x000000FF
-+#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) \
-+ (((v) << 0) & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT)
-+
-+#define HW_AUDIOOUT_DACDEBUG (0x00000040)
-+#define HW_AUDIOOUT_DACDEBUG_SET (0x00000044)
-+#define HW_AUDIOOUT_DACDEBUG_CLR (0x00000048)
-+#define HW_AUDIOOUT_DACDEBUG_TOG (0x0000004c)
-+
-+#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 0x80000000
-+#define BP_AUDIOOUT_DACDEBUG_RSRVD2 12
-+#define BM_AUDIOOUT_DACDEBUG_RSRVD2 0x7FFFF000
-+#define BF_AUDIOOUT_DACDEBUG_RSRVD2(v) \
-+ (((v) << 12) & BM_AUDIOOUT_DACDEBUG_RSRVD2)
-+#define BP_AUDIOOUT_DACDEBUG_RAM_SS 8
-+#define BM_AUDIOOUT_DACDEBUG_RAM_SS 0x00000F00
-+#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v) \
-+ (((v) << 8) & BM_AUDIOOUT_DACDEBUG_RAM_SS)
-+#define BP_AUDIOOUT_DACDEBUG_RSRVD1 6
-+#define BM_AUDIOOUT_DACDEBUG_RSRVD1 0x000000C0
-+#define BF_AUDIOOUT_DACDEBUG_RSRVD1(v) \
-+ (((v) << 6) & BM_AUDIOOUT_DACDEBUG_RSRVD1)
-+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 0x00000020
-+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 0x00000010
-+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 0x00000008
-+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 0x00000004
-+#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ 0x00000002
-+#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS 0x00000001
-+
-+#define HW_AUDIOOUT_HPVOL (0x00000050)
-+#define HW_AUDIOOUT_HPVOL_SET (0x00000054)
-+#define HW_AUDIOOUT_HPVOL_CLR (0x00000058)
-+#define HW_AUDIOOUT_HPVOL_TOG (0x0000005c)
-+
-+#define BP_AUDIOOUT_HPVOL_RSRVD5 29
-+#define BM_AUDIOOUT_HPVOL_RSRVD5 0xE0000000
-+#define BF_AUDIOOUT_HPVOL_RSRVD5(v) \
-+ (((v) << 29) & BM_AUDIOOUT_HPVOL_RSRVD5)
-+#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 0x10000000
-+#define BP_AUDIOOUT_HPVOL_RSRVD4 26
-+#define BM_AUDIOOUT_HPVOL_RSRVD4 0x0C000000
-+#define BF_AUDIOOUT_HPVOL_RSRVD4(v) \
-+ (((v) << 26) & BM_AUDIOOUT_HPVOL_RSRVD4)
-+#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
-+#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
-+#define BP_AUDIOOUT_HPVOL_RSRVD3 17
-+#define BM_AUDIOOUT_HPVOL_RSRVD3 0x00FE0000
-+#define BF_AUDIOOUT_HPVOL_RSRVD3(v) \
-+ (((v) << 17) & BM_AUDIOOUT_HPVOL_RSRVD3)
-+#define BM_AUDIOOUT_HPVOL_SELECT 0x00010000
-+#define BM_AUDIOOUT_HPVOL_RSRVD2 0x00008000
-+#define BP_AUDIOOUT_HPVOL_VOL_LEFT 8
-+#define BM_AUDIOOUT_HPVOL_VOL_LEFT 0x00007F00
-+#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v) \
-+ (((v) << 8) & BM_AUDIOOUT_HPVOL_VOL_LEFT)
-+#define BM_AUDIOOUT_HPVOL_RSRVD1 0x00000080
-+#define BP_AUDIOOUT_HPVOL_VOL_RIGHT 0
-+#define BM_AUDIOOUT_HPVOL_VOL_RIGHT 0x0000007F
-+#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v) \
-+ (((v) << 0) & BM_AUDIOOUT_HPVOL_VOL_RIGHT)
-+
-+#define HW_AUDIOOUT_RESERVED (0x00000060)
-+#define HW_AUDIOOUT_RESERVED_SET (0x00000064)
-+#define HW_AUDIOOUT_RESERVED_CLR (0x00000068)
-+#define HW_AUDIOOUT_RESERVED_TOG (0x0000006c)
-+
-+#define BP_AUDIOOUT_RESERVED_RSRVD1 0
-+#define BM_AUDIOOUT_RESERVED_RSRVD1 0xFFFFFFFF
-+#define BF_AUDIOOUT_RESERVED_RSRVD1(v) (v)
-+
-+#define HW_AUDIOOUT_PWRDN (0x00000070)
-+#define HW_AUDIOOUT_PWRDN_SET (0x00000074)
-+#define HW_AUDIOOUT_PWRDN_CLR (0x00000078)
-+#define HW_AUDIOOUT_PWRDN_TOG (0x0000007c)
-+
-+#define BP_AUDIOOUT_PWRDN_RSRVD7 25
-+#define BM_AUDIOOUT_PWRDN_RSRVD7 0xFE000000
-+#define BF_AUDIOOUT_PWRDN_RSRVD7(v) \
-+ (((v) << 25) & BM_AUDIOOUT_PWRDN_RSRVD7)
-+#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000
-+#define BP_AUDIOOUT_PWRDN_RSRVD6 21
-+#define BM_AUDIOOUT_PWRDN_RSRVD6 0x00E00000
-+#define BF_AUDIOOUT_PWRDN_RSRVD6(v) \
-+ (((v) << 21) & BM_AUDIOOUT_PWRDN_RSRVD6)
-+#define BM_AUDIOOUT_PWRDN_SELFBIAS 0x00100000
-+#define BP_AUDIOOUT_PWRDN_RSRVD5 17
-+#define BM_AUDIOOUT_PWRDN_RSRVD5 0x000E0000
-+#define BF_AUDIOOUT_PWRDN_RSRVD5(v) \
-+ (((v) << 17) & BM_AUDIOOUT_PWRDN_RSRVD5)
-+#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
-+#define BP_AUDIOOUT_PWRDN_RSRVD4 13
-+#define BM_AUDIOOUT_PWRDN_RSRVD4 0x0000E000
-+#define BF_AUDIOOUT_PWRDN_RSRVD4(v) \
-+ (((v) << 13) & BM_AUDIOOUT_PWRDN_RSRVD4)
-+#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
-+#define BP_AUDIOOUT_PWRDN_RSRVD3 9
-+#define BM_AUDIOOUT_PWRDN_RSRVD3 0x00000E00
-+#define BF_AUDIOOUT_PWRDN_RSRVD3(v) \
-+ (((v) << 9) & BM_AUDIOOUT_PWRDN_RSRVD3)
-+#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
-+#define BP_AUDIOOUT_PWRDN_RSRVD2 5
-+#define BM_AUDIOOUT_PWRDN_RSRVD2 0x000000E0
-+#define BF_AUDIOOUT_PWRDN_RSRVD2(v) \
-+ (((v) << 5) & BM_AUDIOOUT_PWRDN_RSRVD2)
-+#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
-+#define BP_AUDIOOUT_PWRDN_RSRVD1 1
-+#define BM_AUDIOOUT_PWRDN_RSRVD1 0x0000000E
-+#define BF_AUDIOOUT_PWRDN_RSRVD1(v) \
-+ (((v) << 1) & BM_AUDIOOUT_PWRDN_RSRVD1)
-+#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
-+
-+#define HW_AUDIOOUT_REFCTRL (0x00000080)
-+#define HW_AUDIOOUT_REFCTRL_SET (0x00000084)
-+#define HW_AUDIOOUT_REFCTRL_CLR (0x00000088)
-+#define HW_AUDIOOUT_REFCTRL_TOG (0x0000008c)
-+
-+#define BP_AUDIOOUT_REFCTRL_RSRVD4 27
-+#define BM_AUDIOOUT_REFCTRL_RSRVD4 0xF8000000
-+#define BF_AUDIOOUT_REFCTRL_RSRVD4(v) \
-+ (((v) << 27) & BM_AUDIOOUT_REFCTRL_RSRVD4)
-+#define BM_AUDIOOUT_REFCTRL_FASTSETTLING 0x04000000
-+#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
-+#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
-+#define BM_AUDIOOUT_REFCTRL_RSRVD3 0x00800000
-+#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
-+#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
-+#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v) \
-+ (((v) << 20) & BM_AUDIOOUT_REFCTRL_VBG_ADJ)
-+#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
-+#define BM_AUDIOOUT_REFCTRL_LW_REF 0x00040000
-+#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
-+#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
-+#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v) \
-+ (((v) << 16) & BM_AUDIOOUT_REFCTRL_BIAS_CTRL)
-+#define BM_AUDIOOUT_REFCTRL_RSRVD2 0x00008000
-+#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 0x00004000
-+#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
-+#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
-+#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
-+#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
-+#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v) \
-+ (((v) << 8) & BM_AUDIOOUT_REFCTRL_ADC_REFVAL)
-+#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
-+#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
-+#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v) \
-+ (((v) << 4) & BM_AUDIOOUT_REFCTRL_VAG_VAL)
-+#define BM_AUDIOOUT_REFCTRL_RSRVD1 0x00000008
-+#define BP_AUDIOOUT_REFCTRL_DAC_ADJ 0
-+#define BM_AUDIOOUT_REFCTRL_DAC_ADJ 0x00000007
-+#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v) \
-+ (((v) << 0) & BM_AUDIOOUT_REFCTRL_DAC_ADJ)
-+
-+#define HW_AUDIOOUT_ANACTRL (0x00000090)
-+#define HW_AUDIOOUT_ANACTRL_SET (0x00000094)
-+#define HW_AUDIOOUT_ANACTRL_CLR (0x00000098)
-+#define HW_AUDIOOUT_ANACTRL_TOG (0x0000009c)
-+
-+#define BP_AUDIOOUT_ANACTRL_RSRVD8 29
-+#define BM_AUDIOOUT_ANACTRL_RSRVD8 0xE0000000
-+#define BF_AUDIOOUT_ANACTRL_RSRVD8(v) \
-+ (((v) << 29) & BM_AUDIOOUT_ANACTRL_RSRVD8)
-+#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS 0x10000000
-+#define BP_AUDIOOUT_ANACTRL_RSRVD7 25
-+#define BM_AUDIOOUT_ANACTRL_RSRVD7 0x0E000000
-+#define BF_AUDIOOUT_ANACTRL_RSRVD7(v) \
-+ (((v) << 25) & BM_AUDIOOUT_ANACTRL_RSRVD7)
-+#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS 0x01000000
-+#define BP_AUDIOOUT_ANACTRL_RSRVD6 22
-+#define BM_AUDIOOUT_ANACTRL_RSRVD6 0x00C00000
-+#define BF_AUDIOOUT_ANACTRL_RSRVD6(v) \
-+ (((v) << 22) & BM_AUDIOOUT_ANACTRL_RSRVD6)
-+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM 20
-+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM 0x00300000
-+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) \
-+ (((v) << 20) & BM_AUDIOOUT_ANACTRL_SHORTMODE_CM)
-+#define BM_AUDIOOUT_ANACTRL_RSRVD5 0x00080000
-+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR 17
-+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR 0x00060000
-+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) \
-+ (((v) << 17) & BM_AUDIOOUT_ANACTRL_SHORTMODE_LR)
-+#define BP_AUDIOOUT_ANACTRL_RSRVD4 15
-+#define BM_AUDIOOUT_ANACTRL_RSRVD4 0x00018000
-+#define BF_AUDIOOUT_ANACTRL_RSRVD4(v) \
-+ (((v) << 15) & BM_AUDIOOUT_ANACTRL_RSRVD4)
-+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL 12
-+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL 0x00007000
-+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) \
-+ (((v) << 12) & BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL)
-+#define BM_AUDIOOUT_ANACTRL_RSRVD3 0x00000800
-+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR 8
-+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR 0x00000700
-+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) \
-+ (((v) << 8) & BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR)
-+#define BP_AUDIOOUT_ANACTRL_RSRVD2 6
-+#define BM_AUDIOOUT_ANACTRL_RSRVD2 0x000000C0
-+#define BF_AUDIOOUT_ANACTRL_RSRVD2(v) \
-+ (((v) << 6) & BM_AUDIOOUT_ANACTRL_RSRVD2)
-+#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
-+#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
-+#define BP_AUDIOOUT_ANACTRL_RSRVD1 0
-+#define BM_AUDIOOUT_ANACTRL_RSRVD1 0x0000000F
-+#define BF_AUDIOOUT_ANACTRL_RSRVD1(v) \
-+ (((v) << 0) & BM_AUDIOOUT_ANACTRL_RSRVD1)
-+
-+#define HW_AUDIOOUT_TEST (0x000000a0)
-+#define HW_AUDIOOUT_TEST_SET (0x000000a4)
-+#define HW_AUDIOOUT_TEST_CLR (0x000000a8)
-+#define HW_AUDIOOUT_TEST_TOG (0x000000ac)
-+
-+#define BM_AUDIOOUT_TEST_RSRVD4 0x80000000
-+#define BP_AUDIOOUT_TEST_HP_ANTIPOP 28
-+#define BM_AUDIOOUT_TEST_HP_ANTIPOP 0x70000000
-+#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v) \
-+ (((v) << 28) & BM_AUDIOOUT_TEST_HP_ANTIPOP)
-+#define BM_AUDIOOUT_TEST_RSRVD3 0x08000000
-+#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP 0x04000000
-+#define BM_AUDIOOUT_TEST_TM_LOOP 0x02000000
-+#define BM_AUDIOOUT_TEST_TM_HPCOMMON 0x01000000
-+#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
-+#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
-+#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v) \
-+ (((v) << 22) & BM_AUDIOOUT_TEST_HP_I1_ADJ)
-+#define BP_AUDIOOUT_TEST_HP_IALL_ADJ 20
-+#define BM_AUDIOOUT_TEST_HP_IALL_ADJ 0x00300000
-+#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v) \
-+ (((v) << 20) & BM_AUDIOOUT_TEST_HP_IALL_ADJ)
-+#define BP_AUDIOOUT_TEST_RSRVD2 14
-+#define BM_AUDIOOUT_TEST_RSRVD2 0x000FC000
-+#define BF_AUDIOOUT_TEST_RSRVD2(v) \
-+ (((v) << 14) & BM_AUDIOOUT_TEST_RSRVD2)
-+#define BM_AUDIOOUT_TEST_VAG_CLASSA 0x00002000
-+#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I 0x00001000
-+#define BP_AUDIOOUT_TEST_RSRVD1 4
-+#define BM_AUDIOOUT_TEST_RSRVD1 0x00000FF0
-+#define BF_AUDIOOUT_TEST_RSRVD1(v) \
-+ (((v) << 4) & BM_AUDIOOUT_TEST_RSRVD1)
-+#define BM_AUDIOOUT_TEST_ADCTODAC_LOOP 0x00000008
-+#define BM_AUDIOOUT_TEST_DAC_CLASSA 0x00000004
-+#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I 0x00000002
-+#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ 0x00000001
-+
-+#define HW_AUDIOOUT_BISTCTRL (0x000000b0)
-+#define HW_AUDIOOUT_BISTCTRL_SET (0x000000b4)
-+#define HW_AUDIOOUT_BISTCTRL_CLR (0x000000b8)
-+#define HW_AUDIOOUT_BISTCTRL_TOG (0x000000bc)
-+
-+#define BP_AUDIOOUT_BISTCTRL_RSVD0 4
-+#define BM_AUDIOOUT_BISTCTRL_RSVD0 0xFFFFFFF0
-+#define BF_AUDIOOUT_BISTCTRL_RSVD0(v) \
-+ (((v) << 4) & BM_AUDIOOUT_BISTCTRL_RSVD0)
-+#define BM_AUDIOOUT_BISTCTRL_FAIL 0x00000008
-+#define BM_AUDIOOUT_BISTCTRL_PASS 0x00000004
-+#define BM_AUDIOOUT_BISTCTRL_DONE 0x00000002
-+#define BM_AUDIOOUT_BISTCTRL_START 0x00000001
-+
-+#define HW_AUDIOOUT_BISTSTAT0 (0x000000c0)
-+#define HW_AUDIOOUT_BISTSTAT0_SET (0x000000c4)
-+#define HW_AUDIOOUT_BISTSTAT0_CLR (0x000000c8)
-+#define HW_AUDIOOUT_BISTSTAT0_TOG (0x000000cc)
-+
-+#define BP_AUDIOOUT_BISTSTAT0_RSVD0 24
-+#define BM_AUDIOOUT_BISTSTAT0_RSVD0 0xFF000000
-+#define BF_AUDIOOUT_BISTSTAT0_RSVD0(v) \
-+ (((v) << 24) & BM_AUDIOOUT_BISTSTAT0_RSVD0)
-+#define BP_AUDIOOUT_BISTSTAT0_DATA 0
-+#define BM_AUDIOOUT_BISTSTAT0_DATA 0x00FFFFFF
-+#define BF_AUDIOOUT_BISTSTAT0_DATA(v) \
-+ (((v) << 0) & BM_AUDIOOUT_BISTSTAT0_DATA)
-+
-+#define HW_AUDIOOUT_BISTSTAT1 (0x000000d0)
-+#define HW_AUDIOOUT_BISTSTAT1_SET (0x000000d4)
-+#define HW_AUDIOOUT_BISTSTAT1_CLR (0x000000d8)
-+#define HW_AUDIOOUT_BISTSTAT1_TOG (0x000000dc)
-+
-+#define BP_AUDIOOUT_BISTSTAT1_RSVD1 29
-+#define BM_AUDIOOUT_BISTSTAT1_RSVD1 0xE0000000
-+#define BF_AUDIOOUT_BISTSTAT1_RSVD1(v) \
-+ (((v) << 29) & BM_AUDIOOUT_BISTSTAT1_RSVD1)
-+#define BP_AUDIOOUT_BISTSTAT1_STATE 24
-+#define BM_AUDIOOUT_BISTSTAT1_STATE 0x1F000000
-+#define BF_AUDIOOUT_BISTSTAT1_STATE(v) \
-+ (((v) << 24) & BM_AUDIOOUT_BISTSTAT1_STATE)
-+#define BP_AUDIOOUT_BISTSTAT1_RSVD0 8
-+#define BM_AUDIOOUT_BISTSTAT1_RSVD0 0x00FFFF00
-+#define BF_AUDIOOUT_BISTSTAT1_RSVD0(v) \
-+ (((v) << 8) & BM_AUDIOOUT_BISTSTAT1_RSVD0)
-+#define BP_AUDIOOUT_BISTSTAT1_ADDR 0
-+#define BM_AUDIOOUT_BISTSTAT1_ADDR 0x000000FF
-+#define BF_AUDIOOUT_BISTSTAT1_ADDR(v) \
-+ (((v) << 0) & BM_AUDIOOUT_BISTSTAT1_ADDR)
-+
-+#define HW_AUDIOOUT_ANACLKCTRL (0x000000e0)
-+#define HW_AUDIOOUT_ANACLKCTRL_SET (0x000000e4)
-+#define HW_AUDIOOUT_ANACLKCTRL_CLR (0x000000e8)
-+#define HW_AUDIOOUT_ANACLKCTRL_TOG (0x000000ec)
-+
-+#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
-+#define BP_AUDIOOUT_ANACLKCTRL_RSRVD3 5
-+#define BM_AUDIOOUT_ANACLKCTRL_RSRVD3 0x7FFFFFE0
-+#define BF_AUDIOOUT_ANACLKCTRL_RSRVD3(v) \
-+ (((v) << 5) & BM_AUDIOOUT_ANACLKCTRL_RSRVD3)
-+#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 0x00000010
-+#define BM_AUDIOOUT_ANACLKCTRL_RSRVD2 0x00000008
-+#define BP_AUDIOOUT_ANACLKCTRL_DACDIV 0
-+#define BM_AUDIOOUT_ANACLKCTRL_DACDIV 0x00000007
-+#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v) \
-+ (((v) << 0) & BM_AUDIOOUT_ANACLKCTRL_DACDIV)
-+
-+#define HW_AUDIOOUT_DATA (0x000000f0)
-+#define HW_AUDIOOUT_DATA_SET (0x000000f4)
-+#define HW_AUDIOOUT_DATA_CLR (0x000000f8)
-+#define HW_AUDIOOUT_DATA_TOG (0x000000fc)
-+
-+#define BP_AUDIOOUT_DATA_HIGH 16
-+#define BM_AUDIOOUT_DATA_HIGH 0xFFFF0000
-+#define BF_AUDIOOUT_DATA_HIGH(v) \
-+ (((v) << 16) & BM_AUDIOOUT_DATA_HIGH)
-+#define BP_AUDIOOUT_DATA_LOW 0
-+#define BM_AUDIOOUT_DATA_LOW 0x0000FFFF
-+#define BF_AUDIOOUT_DATA_LOW(v) \
-+ (((v) << 0) & BM_AUDIOOUT_DATA_LOW)
-+
-+#define HW_AUDIOOUT_SPEAKERCTRL (0x00000100)
-+#define HW_AUDIOOUT_SPEAKERCTRL_SET (0x00000104)
-+#define HW_AUDIOOUT_SPEAKERCTRL_CLR (0x00000108)
-+#define HW_AUDIOOUT_SPEAKERCTRL_TOG (0x0000010c)
-+
-+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD2 25
-+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD2 0xFE000000
-+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(v) \
-+ (((v) << 25) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD2)
-+#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000
-+#define BP_AUDIOOUT_SPEAKERCTRL_I1_ADJ 22
-+#define BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ 0x00C00000
-+#define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v) \
-+ (((v) << 22) & BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ)
-+#define BP_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 20
-+#define BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 0x00300000
-+#define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v) \
-+ (((v) << 20) & BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ)
-+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD1 16
-+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD1 0x000F0000
-+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(v) \
-+ (((v) << 16) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD1)
-+#define BP_AUDIOOUT_SPEAKERCTRL_POSDRIVER 14
-+#define BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER 0x0000C000
-+#define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v) \
-+ (((v) << 14) & BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER)
-+#define BP_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 12
-+#define BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 0x00003000
-+#define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v) \
-+ (((v) << 12) & BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER)
-+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD0 0
-+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD0 0x00000FFF
-+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(v) \
-+ (((v) << 0) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD0)
-+
-+#define HW_AUDIOOUT_VERSION (0x00000200)
-+
-+#define BP_AUDIOOUT_VERSION_MAJOR 24
-+#define BM_AUDIOOUT_VERSION_MAJOR 0xFF000000
-+#define BF_AUDIOOUT_VERSION_MAJOR(v) \
-+ (((v) << 24) & BM_AUDIOOUT_VERSION_MAJOR)
-+#define BP_AUDIOOUT_VERSION_MINOR 16
-+#define BM_AUDIOOUT_VERSION_MINOR 0x00FF0000
-+#define BF_AUDIOOUT_VERSION_MINOR(v) \
-+ (((v) << 16) & BM_AUDIOOUT_VERSION_MINOR)
-+#define BP_AUDIOOUT_VERSION_STEP 0
-+#define BM_AUDIOOUT_VERSION_STEP 0x0000FFFF
-+#define BF_AUDIOOUT_VERSION_STEP(v) \
-+ (((v) << 0) & BM_AUDIOOUT_VERSION_STEP)
-+
-+/* AUDIOIN */
-+#define HW_AUDIOIN_CTRL (0x00000000)
-+#define HW_AUDIOIN_CTRL_SET (0x00000004)
-+#define HW_AUDIOIN_CTRL_CLR (0x00000008)
-+#define HW_AUDIOIN_CTRL_TOG (0x0000000c)
-+
-+#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
-+#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
-+#define BP_AUDIOIN_CTRL_RSRVD3 21
-+#define BM_AUDIOIN_CTRL_RSRVD3 0x3FE00000
-+#define BF_AUDIOIN_CTRL_RSRVD3(v) \
-+ (((v) << 21) & BM_AUDIOIN_CTRL_RSRVD3)
-+#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT 16
-+#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT 0x001F0000
-+#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v) \
-+ (((v) << 16) & BM_AUDIOIN_CTRL_DMAWAIT_COUNT)
-+#define BP_AUDIOIN_CTRL_RSRVD1 11
-+#define BM_AUDIOIN_CTRL_RSRVD1 0x0000F800
-+#define BF_AUDIOIN_CTRL_RSRVD1(v) \
-+ (((v) << 11) & BM_AUDIOIN_CTRL_RSRVD1)
-+#define BM_AUDIOIN_CTRL_LR_SWAP 0x00000400
-+#define BM_AUDIOIN_CTRL_EDGE_SYNC 0x00000200
-+#define BM_AUDIOIN_CTRL_INVERT_1BIT 0x00000100
-+#define BM_AUDIOIN_CTRL_OFFSET_ENABLE 0x00000080
-+#define BM_AUDIOIN_CTRL_HPF_ENABLE 0x00000040
-+#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
-+#define BM_AUDIOIN_CTRL_LOOPBACK 0x00000010
-+#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
-+#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
-+#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
-+#define BM_AUDIOIN_CTRL_RUN 0x00000001
-+
-+#define HW_AUDIOIN_STAT (0x00000010)
-+#define HW_AUDIOIN_STAT_SET (0x00000014)
-+#define HW_AUDIOIN_STAT_CLR (0x00000018)
-+#define HW_AUDIOIN_STAT_TOG (0x0000001c)
-+
-+#define BM_AUDIOIN_STAT_ADC_PRESENT 0x80000000
-+#define BP_AUDIOIN_STAT_RSRVD3 0
-+#define BM_AUDIOIN_STAT_RSRVD3 0x7FFFFFFF
-+#define BF_AUDIOIN_STAT_RSRVD3(v) \
-+ (((v) << 0) & BM_AUDIOIN_STAT_RSRVD3)
-+
-+#define HW_AUDIOIN_ADCSRR (0x00000020)
-+#define HW_AUDIOIN_ADCSRR_SET (0x00000024)
-+#define HW_AUDIOIN_ADCSRR_CLR (0x00000028)
-+#define HW_AUDIOIN_ADCSRR_TOG (0x0000002c)
-+
-+#define BM_AUDIOIN_ADCSRR_OSR 0x80000000
-+#define BV_AUDIOIN_ADCSRR_OSR__OSR6 0x0
-+#define BV_AUDIOIN_ADCSRR_OSR__OSR12 0x1
-+#define BP_AUDIOIN_ADCSRR_BASEMULT 28
-+#define BM_AUDIOIN_ADCSRR_BASEMULT 0x70000000
-+#define BF_AUDIOIN_ADCSRR_BASEMULT(v) \
-+ (((v) << 28) & BM_AUDIOIN_ADCSRR_BASEMULT)
-+#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1
-+#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2
-+#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE 0x4
-+#define BM_AUDIOIN_ADCSRR_RSRVD2 0x08000000
-+#define BP_AUDIOIN_ADCSRR_SRC_HOLD 24
-+#define BM_AUDIOIN_ADCSRR_SRC_HOLD 0x07000000
-+#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v) \
-+ (((v) << 24) & BM_AUDIOIN_ADCSRR_SRC_HOLD)
-+#define BP_AUDIOIN_ADCSRR_RSRVD1 21
-+#define BM_AUDIOIN_ADCSRR_RSRVD1 0x00E00000
-+#define BF_AUDIOIN_ADCSRR_RSRVD1(v) \
-+ (((v) << 21) & BM_AUDIOIN_ADCSRR_RSRVD1)
-+#define BP_AUDIOIN_ADCSRR_SRC_INT 16
-+#define BM_AUDIOIN_ADCSRR_SRC_INT 0x001F0000
-+#define BF_AUDIOIN_ADCSRR_SRC_INT(v) \
-+ (((v) << 16) & BM_AUDIOIN_ADCSRR_SRC_INT)
-+#define BP_AUDIOIN_ADCSRR_RSRVD0 13
-+#define BM_AUDIOIN_ADCSRR_RSRVD0 0x0000E000
-+#define BF_AUDIOIN_ADCSRR_RSRVD0(v) \
-+ (((v) << 13) & BM_AUDIOIN_ADCSRR_RSRVD0)
-+#define BP_AUDIOIN_ADCSRR_SRC_FRAC 0
-+#define BM_AUDIOIN_ADCSRR_SRC_FRAC 0x00001FFF
-+#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v) \
-+ (((v) << 0) & BM_AUDIOIN_ADCSRR_SRC_FRAC)
-+
-+#define HW_AUDIOIN_ADCVOLUME (0x00000030)
-+#define HW_AUDIOIN_ADCVOLUME_SET (0x00000034)
-+#define HW_AUDIOIN_ADCVOLUME_CLR (0x00000038)
-+#define HW_AUDIOIN_ADCVOLUME_TOG (0x0000003c)
-+
-+#define BP_AUDIOIN_ADCVOLUME_RSRVD5 29
-+#define BM_AUDIOIN_ADCVOLUME_RSRVD5 0xE0000000
-+#define BF_AUDIOIN_ADCVOLUME_RSRVD5(v) \
-+ (((v) << 29) & BM_AUDIOIN_ADCVOLUME_RSRVD5)
-+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 0x10000000
-+#define BP_AUDIOIN_ADCVOLUME_RSRVD4 26
-+#define BM_AUDIOIN_ADCVOLUME_RSRVD4 0x0C000000
-+#define BF_AUDIOIN_ADCVOLUME_RSRVD4(v) \
-+ (((v) << 26) & BM_AUDIOIN_ADCVOLUME_RSRVD4)
-+#define BM_AUDIOIN_ADCVOLUME_EN_ZCD 0x02000000
-+#define BM_AUDIOIN_ADCVOLUME_RSRVD3 0x01000000
-+#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
-+#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
-+#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) \
-+ (((v) << 16) & BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT)
-+#define BP_AUDIOIN_ADCVOLUME_RSRVD2 13
-+#define BM_AUDIOIN_ADCVOLUME_RSRVD2 0x0000E000
-+#define BF_AUDIOIN_ADCVOLUME_RSRVD2(v) \
-+ (((v) << 13) & BM_AUDIOIN_ADCVOLUME_RSRVD2)
-+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 0x00001000
-+#define BP_AUDIOIN_ADCVOLUME_RSRVD1 8
-+#define BM_AUDIOIN_ADCVOLUME_RSRVD1 0x00000F00
-+#define BF_AUDIOIN_ADCVOLUME_RSRVD1(v) \
-+ (((v) << 8) & BM_AUDIOIN_ADCVOLUME_RSRVD1)
-+#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
-+#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
-+#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) \
-+ (((v) << 0) & BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT)
-+
-+#define HW_AUDIOIN_ADCDEBUG (0x00000040)
-+#define HW_AUDIOIN_ADCDEBUG_SET (0x00000044)
-+#define HW_AUDIOIN_ADCDEBUG_CLR (0x00000048)
-+#define HW_AUDIOIN_ADCDEBUG_TOG (0x0000004c)
-+
-+#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 0x80000000
-+#define BP_AUDIOIN_ADCDEBUG_RSRVD1 4
-+#define BM_AUDIOIN_ADCDEBUG_RSRVD1 0x7FFFFFF0
-+#define BF_AUDIOIN_ADCDEBUG_RSRVD1(v) \
-+ (((v) << 4) & BM_AUDIOIN_ADCDEBUG_RSRVD1)
-+#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0x00000008
-+#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 0x00000004
-+#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ 0x00000002
-+#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS 0x00000001
-+
-+#define HW_AUDIOIN_ADCVOL (0x00000050)
-+#define HW_AUDIOIN_ADCVOL_SET (0x00000054)
-+#define HW_AUDIOIN_ADCVOL_CLR (0x00000058)
-+#define HW_AUDIOIN_ADCVOL_TOG (0x0000005c)
-+
-+#define BP_AUDIOIN_ADCVOL_RSRVD4 29
-+#define BM_AUDIOIN_ADCVOL_RSRVD4 0xE0000000
-+#define BF_AUDIOIN_ADCVOL_RSRVD4(v) \
-+ (((v) << 29) & BM_AUDIOIN_ADCVOL_RSRVD4)
-+#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 0x10000000
-+#define BP_AUDIOIN_ADCVOL_RSRVD3 26
-+#define BM_AUDIOIN_ADCVOL_RSRVD3 0x0C000000
-+#define BF_AUDIOIN_ADCVOL_RSRVD3(v) \
-+ (((v) << 26) & BM_AUDIOIN_ADCVOL_RSRVD3)
-+#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD 0x02000000
-+#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
-+#define BP_AUDIOIN_ADCVOL_RSRVD2 14
-+#define BM_AUDIOIN_ADCVOL_RSRVD2 0x00FFC000
-+#define BF_AUDIOIN_ADCVOL_RSRVD2(v) \
-+ (((v) << 14) & BM_AUDIOIN_ADCVOL_RSRVD2)
-+#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
-+#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
-+#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v) \
-+ (((v) << 12) & BM_AUDIOIN_ADCVOL_SELECT_LEFT)
-+#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
-+#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
-+#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v) \
-+ (((v) << 8) & BM_AUDIOIN_ADCVOL_GAIN_LEFT)
-+#define BP_AUDIOIN_ADCVOL_RSRVD1 6
-+#define BM_AUDIOIN_ADCVOL_RSRVD1 0x000000C0
-+#define BF_AUDIOIN_ADCVOL_RSRVD1(v) \
-+ (((v) << 6) & BM_AUDIOIN_ADCVOL_RSRVD1)
-+#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
-+#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
-+#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v) \
-+ (((v) << 4) & BM_AUDIOIN_ADCVOL_SELECT_RIGHT)
-+#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
-+#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
-+#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v) \
-+ (((v) << 0) & BM_AUDIOIN_ADCVOL_GAIN_RIGHT)
-+
-+#define HW_AUDIOIN_MICLINE (0x00000060)
-+#define HW_AUDIOIN_MICLINE_SET (0x00000064)
-+#define HW_AUDIOIN_MICLINE_CLR (0x00000068)
-+#define HW_AUDIOIN_MICLINE_TOG (0x0000006c)
-+
-+#define BP_AUDIOIN_MICLINE_RSRVD6 30
-+#define BM_AUDIOIN_MICLINE_RSRVD6 0xC0000000
-+#define BF_AUDIOIN_MICLINE_RSRVD6(v) \
-+ (((v) << 30) & BM_AUDIOIN_MICLINE_RSRVD6)
-+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1 0x20000000
-+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2 0x10000000
-+#define BP_AUDIOIN_MICLINE_RSRVD5 25
-+#define BM_AUDIOIN_MICLINE_RSRVD5 0x0E000000
-+#define BF_AUDIOIN_MICLINE_RSRVD5(v) \
-+ (((v) << 25) & BM_AUDIOIN_MICLINE_RSRVD5)
-+#define BM_AUDIOIN_MICLINE_MIC_SELECT 0x01000000
-+#define BP_AUDIOIN_MICLINE_RSRVD4 22
-+#define BM_AUDIOIN_MICLINE_RSRVD4 0x00C00000
-+#define BF_AUDIOIN_MICLINE_RSRVD4(v) \
-+ (((v) << 22) & BM_AUDIOIN_MICLINE_RSRVD4)
-+#define BP_AUDIOIN_MICLINE_MIC_RESISTOR 20
-+#define BM_AUDIOIN_MICLINE_MIC_RESISTOR 0x00300000
-+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v) \
-+ (((v) << 20) & BM_AUDIOIN_MICLINE_MIC_RESISTOR)
-+#define BM_AUDIOIN_MICLINE_RSRVD3 0x00080000
-+#define BP_AUDIOIN_MICLINE_MIC_BIAS 16
-+#define BM_AUDIOIN_MICLINE_MIC_BIAS 0x00070000
-+#define BF_AUDIOIN_MICLINE_MIC_BIAS(v) \
-+ (((v) << 16) & BM_AUDIOIN_MICLINE_MIC_BIAS)
-+#define BP_AUDIOIN_MICLINE_RSRVD2 6
-+#define BM_AUDIOIN_MICLINE_RSRVD2 0x0000FFC0
-+#define BF_AUDIOIN_MICLINE_RSRVD2(v) \
-+ (((v) << 6) & BM_AUDIOIN_MICLINE_RSRVD2)
-+#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK 4
-+#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK 0x00000030
-+#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v) \
-+ (((v) << 4) & BM_AUDIOIN_MICLINE_MIC_CHOPCLK)
-+#define BP_AUDIOIN_MICLINE_RSRVD1 2
-+#define BM_AUDIOIN_MICLINE_RSRVD1 0x0000000C
-+#define BF_AUDIOIN_MICLINE_RSRVD1(v) \
-+ (((v) << 2) & BM_AUDIOIN_MICLINE_RSRVD1)
-+#define BP_AUDIOIN_MICLINE_MIC_GAIN 0
-+#define BM_AUDIOIN_MICLINE_MIC_GAIN 0x00000003
-+#define BF_AUDIOIN_MICLINE_MIC_GAIN(v) \
-+ (((v) << 0) & BM_AUDIOIN_MICLINE_MIC_GAIN)
-+
-+#define HW_AUDIOIN_ANACLKCTRL (0x00000070)
-+#define HW_AUDIOIN_ANACLKCTRL_SET (0x00000074)
-+#define HW_AUDIOIN_ANACLKCTRL_CLR (0x00000078)
-+#define HW_AUDIOIN_ANACLKCTRL_TOG (0x0000007c)
-+
-+#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
-+#define BP_AUDIOIN_ANACLKCTRL_RSRVD4 11
-+#define BM_AUDIOIN_ANACLKCTRL_RSRVD4 0x7FFFF800
-+#define BF_AUDIOIN_ANACLKCTRL_RSRVD4(v) \
-+ (((v) << 11) & BM_AUDIOIN_ANACLKCTRL_RSRVD4)
-+#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF 0x00000400
-+#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER 0x00000200
-+#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 0x00000100
-+#define BP_AUDIOIN_ANACLKCTRL_RSRVD3 6
-+#define BM_AUDIOIN_ANACLKCTRL_RSRVD3 0x000000C0
-+#define BF_AUDIOIN_ANACLKCTRL_RSRVD3(v) \
-+ (((v) << 6) & BM_AUDIOIN_ANACLKCTRL_RSRVD3)
-+#define BP_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 4
-+#define BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 0x00000030
-+#define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v) \
-+ (((v) << 4) & BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT)
-+#define BM_AUDIOIN_ANACLKCTRL_RSRVD2 0x00000008
-+#define BP_AUDIOIN_ANACLKCTRL_ADCDIV 0
-+#define BM_AUDIOIN_ANACLKCTRL_ADCDIV 0x00000007
-+#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v) \
-+ (((v) << 0) & BM_AUDIOIN_ANACLKCTRL_ADCDIV)
-+
-+#define HW_AUDIOIN_DATA (0x00000080)
-+#define HW_AUDIOIN_DATA_SET (0x00000084)
-+#define HW_AUDIOIN_DATA_CLR (0x00000088)
-+#define HW_AUDIOIN_DATA_TOG (0x0000008c)
-+
-+#define BP_AUDIOIN_DATA_HIGH 16
-+#define BM_AUDIOIN_DATA_HIGH 0xFFFF0000
-+#define BF_AUDIOIN_DATA_HIGH(v) \
-+ (((v) << 16) & BM_AUDIOIN_DATA_HIGH)
-+#define BP_AUDIOIN_DATA_LOW 0
-+#define BM_AUDIOIN_DATA_LOW 0x0000FFFF
-+#define BF_AUDIOIN_DATA_LOW(v) \
-+ (((v) << 0) & BM_AUDIOIN_DATA_LOW)
-+
-+#define BV_AUDIOIN_ADCVOL_SELECT__MIC 0x00
-+
-+#endif /* __MXS_ADC_CODEC_H */
---- a/sound/soc/mxs/Kconfig
-+++ b/sound/soc/mxs/Kconfig
-@@ -19,3 +19,13 @@ config SND_SOC_MXS_SGTL5000
- a sgtl5000 codec.
-
- endif # SND_MXS_SOC
-+
-+
-+config SND_MXS_SOC_BUILTIN
-+ tristate "SoC Audio for Freescale i.MX23 built-in codec"
-+ depends on ARCH_MXS
-+ select SND_SOC_GENERIC_DMAENGINE_PCM
-+ select SND_SOC_MXS_BUILTIN_CODEC
-+ help
-+ Say Y or M if you want to add support for codecs attached to
-+ the MXS SAIF interface.
---- a/sound/soc/mxs/Makefile
-+++ b/sound/soc/mxs/Makefile
-@@ -8,3 +8,12 @@ obj-$(CONFIG_SND_MXS_SOC) += snd-soc-mxs
- snd-soc-mxs-sgtl5000-objs := mxs-sgtl5000.o
-
- obj-$(CONFIG_SND_SOC_MXS_SGTL5000) += snd-soc-mxs-sgtl5000.o
-+
-+# i.MX23 built-in audio Machine and Platform support
-+snd-soc-mxs-builtin-pcm-objs := mxs-builtin-pcm.o
-+snd-soc-mxs-builtin-dai-objs := mxs-builtin-dai.o
-+snd-soc-mxs-builtin-audio-objs := mxs-builtin-audio.o
-+
-+obj-$(CONFIG_SND_MXS_SOC_BUILTIN) += snd-soc-mxs-builtin-pcm.o
-+obj-$(CONFIG_SND_MXS_SOC_BUILTIN) += snd-soc-mxs-builtin-dai.o
-+obj-$(CONFIG_SND_MXS_SOC_BUILTIN) += snd-soc-mxs-builtin-audio.o
---- /dev/null
-+++ b/sound/soc/mxs/mxs-builtin-audio.c
-@@ -0,0 +1,120 @@
-+/*
-+ * mxs-builtin-audio.c -- i.MX233 built-in codec ALSA Soc Audio driver
-+ *
-+ * Author: Michal Ulianko <michal.ulianko@gmail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+#include <sound/soc-dapm.h>
-+#include <asm/mach-types.h>
-+
-+static struct snd_soc_dai_link mxs_adc_dai_link[] = {
-+ {
-+ .name = "MXS ADC/DAC",
-+ .stream_name = "MXS ADC/DAC",
-+ .codec_dai_name = "mxs-builtin-codec-dai",
-+// .codec_name = "mxs-builtin-codec",
-+// .cpu_dai_name = "mxs-builtin-cpu-dai",
-+// .platform_name = "mxs-builtin-cpu-dai",
-+// .ops = &mxs_sgtl5000_hifi_ops,
-+ },
-+};
-+
-+static struct snd_soc_card mxs_adc_audio = {
-+ .name = "mxs-builtin-audio",
-+ .owner = THIS_MODULE,
-+ .dai_link = mxs_adc_dai_link,
-+ .num_links = ARRAY_SIZE(mxs_adc_dai_link),
-+};
-+
-+static int mxsadc_audio_probe_dt(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct device_node *cpu_dai_np, *codec_np;
-+ int ret = 0;
-+
-+ if (!np)
-+ return 1; /* no device tree */
-+
-+ cpu_dai_np = of_parse_phandle(np, "cpu-dai", 0);
-+ codec_np = of_parse_phandle(np, "audio-codec", 0);
-+ if (!cpu_dai_np || !codec_np) {
-+ dev_err(&pdev->dev, "phandle missing or invalid\n");
-+ return -EINVAL;
-+ }
-+
-+ mxs_adc_dai_link[0].codec_name = NULL;
-+ mxs_adc_dai_link[0].codec_of_node = codec_np;
-+ mxs_adc_dai_link[0].cpu_dai_name = NULL;
-+ mxs_adc_dai_link[0].cpu_of_node = cpu_dai_np;
-+ mxs_adc_dai_link[0].platform_name = NULL;
-+ mxs_adc_dai_link[0].platform_of_node = cpu_dai_np;
-+
-+// of_node_put(codec_np);
-+// of_node_put(cpu_dai_np);
-+
-+ return ret;
-+}
-+
-+static int mxsadc_audio_probe(struct platform_device *pdev)
-+{
-+ struct snd_soc_card *card = &mxs_adc_audio;
-+ int ret;
-+
-+ ret = mxsadc_audio_probe_dt(pdev);
-+ if (ret < 0)
-+ return ret;
-+
-+ card->dev = &pdev->dev;
-+ platform_set_drvdata(pdev, card);
-+
-+ ret = snd_soc_register_card(card);
-+ if (ret) {
-+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static int mxsadc_audio_remove(struct platform_device *pdev)
-+{
-+ struct snd_soc_card *card = platform_get_drvdata(pdev);
-+
-+ snd_soc_unregister_card(card);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mxs_adc_audio_dt_ids[] = {
-+ { .compatible = "fsl,mxs-builtin-audio", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mxs_adc_audio_dt_ids);
-+
-+static struct platform_driver mxs_adc_audio_driver = {
-+ .driver = {
-+ .name = "mxs-builtin-audio",
-+ .owner = THIS_MODULE,
-+ .of_match_table = mxs_adc_audio_dt_ids,
-+ },
-+ .probe = mxsadc_audio_probe,
-+ .remove = mxsadc_audio_remove,
-+};
-+
-+module_platform_driver(mxs_adc_audio_driver);
-+
-+MODULE_DESCRIPTION("Freescale MXS ADC/DAC SoC Machine Driver");
-+MODULE_AUTHOR("Michal Ulianko <michal.ulianko@gmail.com>");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/sound/soc/mxs/mxs-builtin-dai.c
-@@ -0,0 +1,588 @@
-+/*
-+ * mxs-builtin-dai.c -- i.MX233 built-in codec ALSA Soc Audio driver
-+ *
-+ * Author: Michal Ulianko <michal.ulianko@gmail.com>
-+ *
-+ * Based on sound/soc/mxs/mxs-adc.c for kernel 2.6.35
-+ * by Vladislav Buzov <vbuzov@embeddedalley.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/platform_device.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+
-+#include "../codecs/mxs-builtin-codec.h"
-+#include "mxs-builtin-pcm.h"
-+
-+#define ADC_VOLUME_MIN 0x37
-+
-+/* TODO Use codec IO function soc snd write etc, instead of __writel __readl */
-+
-+// TODO use container_of
-+struct mxs_irq_data {
-+ struct snd_pcm_substream *substream;
-+ struct mxs_adc_priv *mxs_adc;
-+};
-+
-+struct mxs_adc_priv {
-+ struct mxs_irq_data irq_data;
-+ int dma_adc_err_irq;
-+ int dma_dac_err_irq;
-+ int hp_short_irq;
-+ void __iomem *audioin_base;
-+ void __iomem *audioout_base;
-+ void __iomem *rtc_base;
-+};
-+
-+typedef struct {
-+ struct work_struct work;
-+ struct timer_list timer;
-+
-+ /* target workqueue and CPU ->timer uses to queue ->work */
-+ struct workqueue_struct *wq;
-+ int cpu;
-+
-+ struct mxs_adc_priv *mxs_adc;
-+} my_delayed_work_t;
-+
-+// static struct delayed_work work;
-+// static struct delayed_work adc_ramp_work;
-+// static struct delayed_work dac_ramp_work;
-+// static struct delayed_work test;
-+static my_delayed_work_t work;
-+static my_delayed_work_t adc_ramp_work;
-+static my_delayed_work_t dac_ramp_work;
-+static my_delayed_work_t test;
-+static bool adc_ramp_done = 1;
-+static bool dac_ramp_done = 1;
-+
-+static inline void mxs_adc_schedule_work(struct delayed_work *work)
-+{
-+ schedule_delayed_work(work, HZ / 10);
-+}
-+
-+static void mxs_adc_work(struct work_struct *work)
-+{
-+ struct mxs_adc_priv *mxs_adc = ((my_delayed_work_t *)work)->mxs_adc;
-+ /* disable irq */
-+ disable_irq(mxs_adc->hp_short_irq);
-+
-+ while (true) {
-+ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN_CLR);
-+ msleep(10);
-+ if ((__raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL)
-+ & BM_AUDIOOUT_ANACTRL_SHORT_LR_STS) != 0) {
-+ /* rearm the short protection */
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORTMODE_LR,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_LR_STS,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ __raw_writel(BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(0x1),
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_SET);
-+
-+ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN_SET);
-+ printk(KERN_WARNING "WARNING : Headphone LR short!\r\n");
-+ } else {
-+ printk(KERN_WARNING "INFO : Headphone LR no longer short!\r\n");
-+ break;
-+ }
-+ msleep(1000);
-+ }
-+
-+ /* power up the HEADPHONE and un-mute the HPVOL */
-+ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL_CLR);
-+ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN_CLR);
-+
-+ /* enable irq for next short detect*/
-+ enable_irq(mxs_adc->hp_short_irq);
-+}
-+
-+static void mxs_adc_schedule_ramp_work(struct delayed_work *work)
-+{
-+ schedule_delayed_work(work, msecs_to_jiffies(2));
-+ adc_ramp_done = 0;
-+}
-+
-+static void mxs_adc_ramp_work(struct work_struct *work)
-+{
-+ struct mxs_adc_priv *mxs_adc = ((my_delayed_work_t *)work)->mxs_adc;
-+ u32 reg = 0;
-+ u32 reg1 = 0;
-+ u32 reg2 = 0;
-+ u32 l, r;
-+ u32 ll, rr;
-+ int i;
-+
-+ reg = __raw_readl(mxs_adc->audioin_base + \
-+ HW_AUDIOIN_ADCVOLUME);
-+
-+ reg1 = reg & ~BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT;
-+ reg1 = reg1 & ~BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT;
-+ /* minimize adc volume */
-+ reg2 = reg1 |
-+ BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(ADC_VOLUME_MIN) |
-+ BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(ADC_VOLUME_MIN);
-+ __raw_writel(reg2,
-+ mxs_adc->audioin_base + HW_AUDIOIN_ADCVOLUME);
-+ msleep(1);
-+
-+ l = (reg & BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT) >>
-+ BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT;
-+ r = (reg & BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT) >>
-+ BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT;
-+
-+ /* fade in adc vol */
-+ for (i = ADC_VOLUME_MIN; (i < l) || (i < r);) {
-+ i += 0x8;
-+ ll = i < l ? i : l;
-+ rr = i < r ? i : r;
-+ reg2 = reg1 |
-+ BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(ll) |
-+ BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(rr);
-+ __raw_writel(reg2,
-+ mxs_adc->audioin_base + HW_AUDIOIN_ADCVOLUME);
-+ msleep(1);
-+ }
-+ adc_ramp_done = 1;
-+}
-+
-+static void mxs_dac_schedule_ramp_work(struct delayed_work *work)
-+{
-+ schedule_delayed_work(work, msecs_to_jiffies(2));
-+ dac_ramp_done = 0;
-+}
-+
-+static void mxs_dac_ramp_work(struct work_struct *work)
-+{
-+ struct mxs_adc_priv *mxs_adc = ((my_delayed_work_t *)work)->mxs_adc;
-+ u32 reg = 0;
-+ u32 reg1 = 0;
-+ u32 l, r;
-+ u32 ll, rr;
-+ int i;
-+
-+ /* unmute hp and speaker */
-+ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL_CLR);
-+ __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_SPEAKERCTRL_CLR);
-+
-+ reg = __raw_readl(mxs_adc->audioout_base + \
-+ HW_AUDIOOUT_HPVOL);
-+
-+ reg1 = reg & ~BM_AUDIOOUT_HPVOL_VOL_LEFT;
-+ reg1 = reg1 & ~BM_AUDIOOUT_HPVOL_VOL_RIGHT;
-+
-+ l = (reg & BM_AUDIOOUT_HPVOL_VOL_LEFT) >>
-+ BP_AUDIOOUT_HPVOL_VOL_LEFT;
-+ r = (reg & BM_AUDIOOUT_HPVOL_VOL_RIGHT) >>
-+ BP_AUDIOOUT_HPVOL_VOL_RIGHT;
-+ /* fade in hp vol */
-+ for (i = 0x7f; i > 0 ;) {
-+ i -= 0x8;
-+ ll = i > (int)l ? i : l;
-+ rr = i > (int)r ? i : r;
-+ reg = reg1 | BF_AUDIOOUT_HPVOL_VOL_LEFT(ll)
-+ | BF_AUDIOOUT_HPVOL_VOL_RIGHT(rr);
-+ __raw_writel(reg,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL);
-+ msleep(1);
-+ }
-+ dac_ramp_done = 1;
-+}
-+
-+/* IRQs */
-+static irqreturn_t mxs_short_irq(int irq, void *dev_id)
-+{
-+ struct mxs_adc_priv *mxs_adc = dev_id;
-+ //struct snd_pcm_substream *substream = mxs_adc->irq_data.substream;
-+
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORTMODE_LR,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_LR_STS,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_CLR);
-+ __raw_writel(BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(0x1),
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_SET);
-+
-+ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL_SET);
-+ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN_SET);
-+ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_CLASSAB,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_SET);
-+
-+ mxs_adc_schedule_work((struct delayed_work *) &work);
-+ return IRQ_HANDLED;
-+}
-+
-+static irqreturn_t mxs_err_irq(int irq, void *dev_id)
-+{
-+ struct mxs_adc_priv *mxs_adc = dev_id;
-+ struct snd_pcm_substream *substream = mxs_adc->irq_data.substream;
-+ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0;
-+ u32 ctrl_reg;
-+ u32 overflow_mask;
-+ u32 underflow_mask;
-+
-+ if (playback) {
-+ ctrl_reg = __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_CTRL);
-+ underflow_mask = BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ;
-+ overflow_mask = BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ;
-+ } else {
-+ ctrl_reg = __raw_readl(mxs_adc->audioin_base + HW_AUDIOIN_CTRL);
-+ underflow_mask = BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ;
-+ overflow_mask = BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ;
-+ }
-+
-+ if (ctrl_reg & underflow_mask) {
-+ printk(KERN_DEBUG "%s underflow detected\n",
-+ playback ? "DAC" : "ADC");
-+
-+ if (playback)
-+ __raw_writel(
-+ BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR);
-+ else
-+ __raw_writel(
-+ BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR);
-+
-+ } else if (ctrl_reg & overflow_mask) {
-+ printk(KERN_DEBUG "%s overflow detected\n",
-+ playback ? "DAC" : "ADC");
-+
-+ if (playback)
-+ __raw_writel(
-+ BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR);
-+ else
-+ __raw_writel(BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR);
-+ } else
-+ printk(KERN_WARNING "Unknown DAC error interrupt\n");
-+
-+ return IRQ_HANDLED;
-+}
-+/* END IRQs */
-+
-+static int mxs_trigger(struct snd_pcm_substream *substream,
-+ int cmd,
-+ struct snd_soc_dai *cpu_dai)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_dai_get_drvdata(cpu_dai);
-+ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0;
-+ int ret = 0;
-+
-+ switch (cmd) {
-+ case SNDRV_PCM_TRIGGER_START:
-+ case SNDRV_PCM_TRIGGER_RESUME:
-+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+
-+ if (playback) {
-+ /* enable the fifo error interrupt */
-+ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_SET);
-+ /* write a data to data reg to trigger the transfer */
-+ __raw_writel(0x0,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_DATA);
-+ mxs_dac_schedule_ramp_work((struct delayed_work *) &dac_ramp_work);
-+ } else {
-+// mxs_dma_get_info(prtd->dma_ch, &dma_info);
-+// cur_bar1 = dma_info.buf_addr;
-+// xfer_count1 = dma_info.xfer_count;
-+
-+ __raw_writel(BM_AUDIOIN_CTRL_RUN,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_SET);
-+ udelay(100);
-+
-+// mxs_dma_get_info(prtd->dma_ch, &dma_info);
-+// cur_bar2 = dma_info.buf_addr;
-+// xfer_count2 = dma_info.xfer_count;
-+//
-+// /* check if DMA getting stuck */
-+// if ((xfer_count1 == xfer_count2) && (cur_bar1 == cur_bar2))
-+// /* read a data from data reg to trigger the receive */
-+// reg = __raw_readl(mxs_adc->audioin_base + HW_AUDIOIN_DATA);
-+
-+ mxs_adc_schedule_ramp_work((struct delayed_work *) &adc_ramp_work);
-+ }
-+ break;
-+
-+ case SNDRV_PCM_TRIGGER_SUSPEND:
-+ case SNDRV_PCM_TRIGGER_STOP:
-+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+
-+ if (playback) {
-+// printk(KERN_INFO "SNDRV_PCM_TRIGGER_START\n");
-+// printk(KERN_INFO "ctrl:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_CTRL));
-+// printk(KERN_INFO "stat:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_STAT));
-+// printk(KERN_INFO "srr:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_DACSRR));
-+// printk(KERN_INFO "vol:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_DACVOLUME));
-+// printk(KERN_INFO "debug:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_DACDEBUG));
-+// printk(KERN_INFO "hpvol:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL));
-+// printk(KERN_INFO "pwrdn:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN));
-+// printk(KERN_INFO "refc:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_REFCTRL));
-+// printk(KERN_INFO "anac:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL));
-+// printk(KERN_INFO "test:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_TEST));
-+// printk(KERN_INFO "bist:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_BISTCTRL));
-+// printk(KERN_INFO "anaclk:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_ANACLKCTRL));
-+
-+ if (dac_ramp_done == 0) {
-+ cancel_delayed_work((struct delayed_work *) &dac_ramp_work);
-+ dac_ramp_done = 1;
-+ }
-+ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL_SET);
-+ __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_SPEAKERCTRL_SET);
-+ /* disable the fifo error interrupt */
-+ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR);
-+ mdelay(50);
-+ } else {
-+ if (adc_ramp_done == 0) {
-+ cancel_delayed_work((struct delayed_work *) &adc_ramp_work);
-+ adc_ramp_done = 1;
-+ }
-+ __raw_writel(BM_AUDIOIN_CTRL_RUN,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR);
-+ }
-+ break;
-+
-+ default:
-+ printk(KERN_ERR "TRIGGER ERROR\n");
-+ ret = -EINVAL;
-+ }
-+
-+ return ret;
-+}
-+
-+static int mxs_startup(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *cpu_dai)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_dai_get_drvdata(cpu_dai);
-+ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0;
-+ mxs_adc->irq_data.mxs_adc = mxs_adc;
-+ mxs_adc->irq_data.substream = substream;
-+
-+ work.mxs_adc = mxs_adc;
-+ adc_ramp_work.mxs_adc = mxs_adc;
-+ dac_ramp_work.mxs_adc = mxs_adc;
-+ test.mxs_adc = mxs_adc;
-+ INIT_DELAYED_WORK(&work, mxs_adc_work);
-+ INIT_DELAYED_WORK(&adc_ramp_work, mxs_adc_ramp_work);
-+ INIT_DELAYED_WORK(&dac_ramp_work, mxs_dac_ramp_work);
-+
-+ /* Enable error interrupt */
-+ if (playback) {
-+ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR);
-+ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR);
-+ } else {
-+ __raw_writel(BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR);
-+ __raw_writel(BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR);
-+ __raw_writel(BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_SET);
-+ }
-+
-+ return 0;
-+}
-+
-+static void mxs_shutdown(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *cpu_dai)
-+{
-+ struct mxs_adc_priv *mxs_adc = snd_soc_dai_get_drvdata(cpu_dai);
-+ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0;
-+
-+ /* Disable error interrupt */
-+ if (playback) {
-+ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN,
-+ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR);
-+ } else {
-+ __raw_writel(BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN,
-+ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR);
-+ }
-+}
-+
-+#define MXS_ADC_RATES SNDRV_PCM_RATE_8000_192000
-+#define MXS_ADC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
-+
-+static const struct snd_soc_dai_ops mxs_adc_dai_ops = {
-+ .startup = mxs_startup,
-+ .trigger = mxs_trigger,
-+ .shutdown = mxs_shutdown,
-+};
-+
-+static int mxs_dai_probe(struct snd_soc_dai *dai)
-+{
-+ // TODO This does not make any sense.
-+ struct mxs_adc_priv *mxs_adc = dev_get_drvdata(dai->dev);
-+
-+ snd_soc_dai_set_drvdata(dai, mxs_adc);
-+
-+ return 0;
-+}
-+
-+static struct snd_soc_dai_driver mxs_adc_dai = {
-+ .name = "mxs-builtin-cpu-dai",
-+ .probe = mxs_dai_probe,
-+ .playback = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = MXS_ADC_RATES,
-+ .formats = MXS_ADC_FORMATS,
-+ },
-+ .capture = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = MXS_ADC_RATES,
-+ .formats = MXS_ADC_FORMATS,
-+ },
-+ .ops = &mxs_adc_dai_ops,
-+};
-+
-+static const struct snd_soc_component_driver mxs_adc_component = {
-+ .name = "mxs-xxx", //TODO change this name
-+};
-+
-+static int mxs_adc_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct mxs_adc_priv *mxs_adc;
-+ int ret = 0;
-+
-+ if (!np)
-+ return -EINVAL;
-+
-+ mxs_adc = devm_kzalloc(&pdev->dev, sizeof(*mxs_adc), GFP_KERNEL);
-+ if (!mxs_adc)
-+ return -ENOMEM;
-+
-+ mxs_adc->audioout_base = devm_ioremap(&pdev->dev, 0x80048000, 0x2000);
-+ if (IS_ERR(mxs_adc->audioout_base))
-+ return PTR_ERR(mxs_adc->audioout_base);
-+
-+ mxs_adc->audioin_base = devm_ioremap(&pdev->dev, 0x8004c000, 0x2000);
-+ if (IS_ERR(mxs_adc->audioin_base))
-+ return PTR_ERR(mxs_adc->audioin_base);
-+
-+ mxs_adc->rtc_base = devm_ioremap(&pdev->dev, 0x8005c000, 0x2000);
-+ if (IS_ERR(mxs_adc->rtc_base))
-+ return PTR_ERR(mxs_adc->rtc_base);
-+
-+ /* Get IRQ numbers */
-+ mxs_adc->dma_adc_err_irq = platform_get_irq(pdev, 0);
-+ if (mxs_adc->dma_adc_err_irq < 0) {
-+ ret = mxs_adc->dma_adc_err_irq;
-+ dev_err(&pdev->dev, "failed to get ADC DMA ERR irq resource: %d\n", ret);
-+ return ret;
-+ }
-+
-+ mxs_adc->dma_dac_err_irq = platform_get_irq(pdev, 1);
-+ if (mxs_adc->dma_dac_err_irq < 0) {
-+ ret = mxs_adc->dma_dac_err_irq;
-+ dev_err(&pdev->dev, "failed to get DAC DMA ERR irq resource: %d\n", ret);
-+ return ret;
-+ }
-+
-+ mxs_adc->hp_short_irq = platform_get_irq(pdev, 2);
-+ if (mxs_adc->hp_short_irq < 0) {
-+ ret = mxs_adc->hp_short_irq;
-+ dev_err(&pdev->dev, "failed to get HP_SHORT irq resource: %d\n", ret);
-+ return ret;
-+ }
-+
-+ /* Request IRQs */
-+ ret = devm_request_irq(&pdev->dev, mxs_adc->dma_adc_err_irq, mxs_err_irq, 0, "MXS DAC and ADC Error",
-+ mxs_adc);
-+ if (ret) {
-+ printk(KERN_ERR "%s: Unable to request ADC/DAC error irq %d\n",
-+ __func__, mxs_adc->dma_adc_err_irq);
-+ return ret;
-+ }
-+
-+ ret = devm_request_irq(&pdev->dev, mxs_adc->dma_dac_err_irq, mxs_err_irq, 0, "MXS DAC and ADC Error",
-+ mxs_adc);
-+ if (ret) {
-+ printk(KERN_ERR "%s: Unable to request ADC/DAC error irq %d\n",
-+ __func__, mxs_adc->dma_dac_err_irq);
-+ return ret;
-+ }
-+
-+ ret = devm_request_irq(&pdev->dev, mxs_adc->hp_short_irq, mxs_short_irq,
-+ IRQF_DISABLED | IRQF_SHARED, "MXS DAC and ADC HP SHORT", mxs_adc);
-+ if (ret) {
-+ printk(KERN_ERR "%s: Unable to request ADC/DAC HP SHORT irq %d\n",
-+ __func__, mxs_adc->hp_short_irq);
-+ return ret;
-+ }
-+
-+ platform_set_drvdata(pdev, mxs_adc);
-+
-+ ret = snd_soc_register_component(&pdev->dev, &mxs_adc_component, &mxs_adc_dai, 1);
-+ if (ret) {
-+ dev_err(&pdev->dev, "register DAI failed\n");
-+ return ret;
-+ }
-+
-+ ret = mxs_adc_pcm_platform_register(&pdev->dev);
-+ if (ret) {
-+ dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
-+ goto failed_pdev_alloc;
-+ }
-+
-+ return 0;
-+
-+failed_pdev_alloc:
-+ snd_soc_unregister_component(&pdev->dev);
-+
-+ return ret;
-+}
-+
-+static int mxs_adc_remove(struct platform_device *pdev)
-+{
-+ mxs_adc_pcm_platform_unregister(&pdev->dev);
-+ snd_soc_unregister_component(&pdev->dev);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mxs_adc_dai_dt_ids[] = {
-+ { .compatible = "fsl,mxs-builtin-cpu-dai", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mxs_adc_dai_dt_ids);
-+
-+static struct platform_driver mxs_adc_dai_driver = {
-+ .probe = mxs_adc_probe,
-+ .remove = mxs_adc_remove,
-+
-+ .driver = {
-+ .name = "mxs-builtin-cpu-dai",
-+ .owner = THIS_MODULE,
-+ .of_match_table = mxs_adc_dai_dt_ids,
-+ },
-+};
-+
-+module_platform_driver(mxs_adc_dai_driver);
-+
-+MODULE_DESCRIPTION("Freescale MXS ADC/DAC SoC Codec DAI Driver");
-+MODULE_AUTHOR("Michal Ulianko <michal.ulianko@gmail.com>");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/sound/soc/mxs/mxs-builtin-pcm.c
-@@ -0,0 +1,69 @@
-+/*
-+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
-+ *
-+ * Based on sound/soc/imx/imx-pcm-dma-mx2.c
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-+ */
-+
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/soc.h>
-+#include <sound/dmaengine_pcm.h>
-+
-+#include "mxs-builtin-pcm.h"
-+
-+static const struct snd_pcm_hardware snd_mxs_hardware = {
-+ .info = SNDRV_PCM_INFO_MMAP |
-+ SNDRV_PCM_INFO_MMAP_VALID |
-+ SNDRV_PCM_INFO_PAUSE |
-+ SNDRV_PCM_INFO_RESUME |
-+ SNDRV_PCM_INFO_INTERLEAVED,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
-+ SNDRV_PCM_FMTBIT_S20_3LE |
-+ SNDRV_PCM_FMTBIT_S24_LE,
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .period_bytes_min = 32,
-+ .period_bytes_max = 8192,
-+ .periods_min = 1,
-+ .periods_max = 52,
-+ .buffer_bytes_max = 64 * 1024,
-+ .fifo_size = 32,
-+};
-+
-+static const struct snd_dmaengine_pcm_config mxs_dmaengine_pcm_config = {
-+ .pcm_hardware = &snd_mxs_hardware,
-+ .prealloc_buffer_size = 64 * 1024,
-+};
-+
-+int mxs_adc_pcm_platform_register(struct device *dev)
-+{
-+ return snd_dmaengine_pcm_register(dev, &mxs_dmaengine_pcm_config,
-+ SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
-+}
-+EXPORT_SYMBOL_GPL(mxs_adc_pcm_platform_register);
-+
-+void mxs_adc_pcm_platform_unregister(struct device *dev)
-+{
-+ snd_dmaengine_pcm_unregister(dev);
-+}
-+EXPORT_SYMBOL_GPL(mxs_adc_pcm_platform_unregister);
-+
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/sound/soc/mxs/mxs-builtin-pcm.h
-@@ -0,0 +1,25 @@
-+/*
-+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-+ */
-+
-+#ifndef _MXS_PCM_H
-+#define _MXS_PCM_H
-+
-+int mxs_adc_pcm_platform_register(struct device *dev);
-+void mxs_adc_pcm_platform_unregister(struct device *dev);
-+
-+#endif
+++ /dev/null
---- a/arch/arm/boot/dts/imx23-olinuxino.dts
-+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
-@@ -88,6 +88,25 @@
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
-+
-+ codec: mxs-builtin-codec {
-+ compatible = "fsl,mxs-builtin-codec";
-+ reg = <0x80048000 0x2000>, <0x8004c000 0x2000>,
-+ <0x8005c000 0x2000>;
-+ reg-names = "audioout", "audioin", "rtc";
-+ clocks = <&clks 31>;
-+ clock-names = "filt";
-+ };
-+
-+ platform_dai: mxs-builtin-cpu-dai {
-+ compatible = "fsl,mxs-builtin-cpu-dai";
-+ reg = <0x80048000 0x2000>, <0x8004c000 0x2000>,
-+ <0x8005c000 0x2000>;
-+ reg-names = "audioout", "audioin", "rtc";
-+ interrupts = <8 6 4>;
-+ dmas = <&dma_apbx 0>, <&dma_apbx 1>;
-+ dma-names = "rx", "tx";
-+ };
- };
- };
-
-@@ -122,4 +141,10 @@
- gpios = <&gpio2 1 1>;
- };
- };
-+
-+ mxs-builtin-audio {
-+ compatible = "fsl,mxs-builtin-audio";
-+ audio-codec = <&codec>;
-+ cpu-dai = <&platform_dai>;
-+ };
- };
+++ /dev/null
---- a/arch/arm/boot/dts/imx23.dtsi
-+++ b/arch/arm/boot/dts/imx23.dtsi
-@@ -338,6 +338,7 @@
-
- dcp@80028000 {
- reg = <0x80028000 0x2000>;
-+ interrupts = <52 53 54>;
- status = "disabled";
- };
-
---- a/arch/arm/boot/dts/imx23-olinuxino.dts
-+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
-@@ -66,6 +66,12 @@
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
- };
-+
-+ dcp@80028000 {
-+ status = "okay";
-+ compatible = "fsl-dcp";
-+ };
-+
- };
-
- apbx@80040000 {
+++ /dev/null
---- a/arch/arm/boot/dts/imx23-olinuxino.dts
-+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
-@@ -113,6 +113,11 @@
- dmas = <&dma_apbx 0>, <&dma_apbx 1>;
- dma-names = "rx", "tx";
- };
-+
-+ lradc@80050000 {
-+ status = "okay";
-+ fsl,lradc-touchscreen-wires = <4>;
-+ };
- };
- };
-
+++ /dev/null
---- a/arch/arm/boot/dts/imx23.dtsi
-+++ b/arch/arm/boot/dts/imx23.dtsi
-@@ -146,6 +146,39 @@
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
-+ i2c0_pins_a: i2c0@0 {
-+ reg = <0>;
-+ fsl,pinmux-ids = <
-+ 0x01e0 /* MX23_PAD_I2C_SCL__I2C_SCL */
-+ 0x01f0 /* MX23_PAD_I2C_SDA__I2C_SDA */
-+ >;
-+ fsl,drive-strength = <1>;
-+ fsl,voltage = <1>;
-+ fsl,pull-up = <1>;
-+ };
-+
-+ i2c1_pins_a: i2c1@0 {
-+ reg = <0>;
-+ fsl,pinmux-ids = <
-+ 0x1171 /* MX23_PAD_LCD_ENABLE__I2C_SCL */
-+ 0x1181 /* MX23_PAD_LCD_HSYNC__I2C_SDA */
-+ >;
-+ fsl,drive-strength = <1>;
-+ fsl,voltage = <1>;
-+ fsl,pull-up = <1>;
-+ };
-+
-+ i2c2_pins_a: i2c2@0 {
-+ reg = <0>;
-+ fsl,pinmux-ids = <
-+ 0x2031 /* MX23_PAD_SSP1_DATA1__I2C_SCL */
-+ 0x2041 /* MX23_PAD_SSP1_DATA2__I2C_SDA */
-+ >;
-+ fsl,drive-strength = <1>;
-+ fsl,voltage = <1>;
-+ fsl,pull-up = <1>;
-+ };
-+
- auart0_pins_a: auart0@0 {
- reg = <0>;
- fsl,pinmux-ids = <
-@@ -443,7 +476,12 @@
- };
-
- i2c@80058000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "fsl,imx23-i2c";
- reg = <0x80058000 0x2000>;
-+ interrupts = <27>;
-+ clock-frequency = <100000>;
- dmas = <&dma_apbx 3>;
- dma-names = "rx-tx";
- status = "disabled";
---- a/arch/arm/boot/dts/imx23-olinuxino.dts
-+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
-@@ -79,6 +79,12 @@
- status = "okay";
- };
-
-+ i2c0: i2c@80058000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c1_pins_a>;
-+ status = "okay";
-+ };
-+
- duart: serial@80070000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
-@@ -94,7 +100,7 @@
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
--
-+
- codec: mxs-builtin-codec {
- compatible = "fsl,mxs-builtin-codec";
- reg = <0x80048000 0x2000>, <0x8004c000 0x2000>,
+++ /dev/null
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -164,6 +164,7 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb
- imx28-cfa10057.dtb \
- imx28-cfa10058.dtb \
- imx28-evk.dtb \
-+ imx28-duckbill.dtb \
- imx28-m28cu3.dtb \
- imx28-m28evk.dtb \
- imx28-sps1.dtb \
---- a/arch/arm/mach-mxs/mach-mxs.c
-+++ b/arch/arm/mach-mxs/mach-mxs.c
-@@ -157,6 +157,7 @@ enum mac_oui {
- OUI_FSL,
- OUI_DENX,
- OUI_CRYSTALFONTZ,
-+ OUI_I2SE,
- };
-
- static void __init update_fec_mac_prop(enum mac_oui oui)
-@@ -211,6 +212,11 @@ static void __init update_fec_mac_prop(e
- macaddr[1] = 0xb9;
- macaddr[2] = 0xe1;
- break;
-+ case OUI_I2SE:
-+ macaddr[0] = 0x00;
-+ macaddr[1] = 0x01;
-+ macaddr[2] = 0x87;
-+ break;
- }
- val = ocotp[i];
- macaddr[3] = (val >> 16) & 0xff;
-@@ -426,6 +432,11 @@ static int __init mxs_restart_init(void)
- return 0;
- }
-
-+static void __init duckbill_init(void)
-+{
-+ update_fec_mac_prop(OUI_I2SE);
-+}
-+
- static void __init mxs_machine_init(void)
- {
- struct device_node *root;
-@@ -464,6 +475,8 @@ static void __init mxs_machine_init(void
- crystalfontz_init();
- else if (of_machine_is_compatible("msr,m28cu3"))
- m28cu3_init();
-+ else if (of_machine_is_compatible("i2se,duckbill"))
-+ duckbill_init();
-
- of_platform_populate(NULL, of_default_bus_match_table,
- NULL, parent);
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/duckbill
- NAME:=I2SE Duckbill boards
- DEPENDS:=+@TARGET_ROOTFS_INCLUDE_KERNEL +@TARGET_ROOTFS_INCLUDE_DTB
- FEATURES+=usbgadget
- PACKAGES+= \
- -dnsmasq -firewall -ppp -ip6tables -iptables -6relayd -mtd uboot-envtools \
- kmod-leds-gpio kmod-ledtrig-timer kmod-usb-mxs-phy -kmod-ipt-nathelper
-endef
-
-define Profile/duckbill/Description
- I2SE's Duckbill devices
-endef
-
-$(eval $(call Profile,duckbill))
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/olinuxino-maxi
- NAME:=Olimex OLinuXino Maxi/Mini boards
- PACKAGES += imx-bootlets uboot-mxs-mx23_olinuxino \
- kmod-usb-mxs-phy kmod-usb-net kmod-usb-net-smsc95xx \
- kmod-gpio-mcp23s08 kmod-leds-gpio kmod-ledtrig-heartbeat kmod-rtc-stmp3xxx \
- kmod-sound-core kmod-sound-soc-mxs kmod-iio-mxs-lradc kmod-crypto-hw-dcp
-endef
-
-define Profile/olinuxino-maxi/Description
- Olimex OLinuXino Maxi/Mini boards
-endef
-
-$(eval $(call Profile,olinuxino-maxi))
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/olinuxino-micro
- NAME:=Olimex OLinuXino Micro/Nano boards
- PACKAGES += imx-bootlets uboot-mxs-mx23_olinuxino \
- kmod-usb-mxs-phy kmod-gpio-mcp23s08 kmod-leds-gpio \
- kmod-ledtrig-heartbeat kmod-rtc-stmp3xxx \
- kmod-iio-mxs-lradc kmod-crypto-hw-dcp
-endef
-
-define Profile/olinuxino-micro/Description
- Olimex OLinuXino Micro/Nano boards
-endef
-
-$(eval $(call Profile,olinuxino-micro))
+++ /dev/null
-#
-# Copyright (C) 2012-2014 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=omap
-BOARDNAME:=TI OMAP3/4/AM33xx
-FEATURES:=usb usbgadget ext4 targz fpu audio display nand ubifs
-CPU_TYPE:=cortex-a9
-CPU_SUBTYPE:=vfpv3
-
-LINUX_VERSION:=3.13.7
-
-MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
-
-KERNELNAME:="zImage dtbs"
-
-include $(INCLUDE_DIR)/target.mk
-
-DEFAULT_PACKAGES += uboot-omap-am335x_evm uboot-omap-omap3_beagle uboot-omap-omap3_overo uboot-omap-omap4_panda
-
-define Target/Description
- TI OMAP boards
-endef
-
-$(eval $(call BuildTarget))
+++ /dev/null
-::sysinit:/etc/init.d/rcS S boot
-::shutdown:/etc/init.d/rcS K shutdown
-ttyO0::askfirst:/bin/ash --login
-ttyO2::askfirst:/bin/ash --login
-tty1::askfirst:/bin/ash --login
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_BANDGAP=y
-CONFIG_ARCH_HAS_BARRIERS=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
-CONFIG_ARCH_HAS_OPP=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
-CONFIG_ARCH_NR_GPIO=192
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_ARCH_OMAP4=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_GIC=y
-# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_OMAP2PLUS_CPUFREQ=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AT803X_PHY=y
-# CONFIG_ATH_CARDS is not set
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_AVERAGE=y
-# CONFIG_BACKLIGHT_ADP8860 is not set
-# CONFIG_BACKLIGHT_ADP8870 is not set
-# CONFIG_BACKLIGHT_BD6107 is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-# CONFIG_BACKLIGHT_GPIO is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_BACKLIGHT_LV5207LP is not set
-# CONFIG_BACKLIGHT_PANDORA is not set
-CONFIG_BACKLIGHT_PWM=y
-# CONFIG_BACKLIGHT_TPS65217 is not set
-CONFIG_BCH=y
-CONFIG_BCH_CONST_M=13
-CONFIG_BOUNCE=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CACHE_PL310=y
-CONFIG_CFG80211=m
-# CONFIG_CFG80211_DEBUGFS is not set
-CONFIG_CFG80211_DEFAULT_PS=y
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_INTERNAL_REGDB is not set
-# CONFIG_CFG80211_REG_DEBUG is not set
-CONFIG_CFG80211_WEXT=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-# CONFIG_CLK_TWL6040 is not set
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyO0,115200n8"
-CONFIG_COMMON_CLK=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_TABLE=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CROSSBAR is not set
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_BLKCIPHER2=m
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=m
-CONFIG_CRYPTO_WORKQUEUE=m
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DDR=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_UART_PL01X is not set
-# CONFIG_DEBUG_USER is not set
-# CONFIG_DISPLAY_DRA_EVM_ENCODER_TPD12S015 is not set
-# CONFIG_DISPLAY_ENCODER_SIL9022 is not set
-CONFIG_DISPLAY_PANEL_DPI=y
-CONFIG_DISPLAY_PANEL_DSI_CM=y
-# CONFIG_DISPLAY_PANEL_NEC_NL8048HL11 is not set
-CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01=y
-# CONFIG_DISPLAY_PANEL_SONY_ACX565AKM is not set
-# CONFIG_DISPLAY_PANEL_TFCS9700 is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OMAP=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_DW_DMAC_CORE is not set
-CONFIG_EEPROM_AT24=y
-CONFIG_EXT4_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CFB_REV_PIXELS_IN_BYTE=y
-CONFIG_FB_DA8XX=y
-# CONFIG_FB_DA8XX_TDA998X is not set
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_OMAP2=y
-CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
-CONFIG_FB_OMAP2_NUM_FBS=3
-CONFIG_FIRMWARE_EDID=y
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FREEZER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-# CONFIG_GENERIC_CPUFREQ_CPU0 is not set
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_TPS65910=y
-CONFIG_GPIO_TWL4030=y
-# CONFIG_GPIO_TWL6040 is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_OMAP=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_OMAP=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_MATRIXKMAP=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_INPUT_TWL4030_PWRBUTTON=y
-# CONFIG_INPUT_TWL4030_VIBRA is not set
-# CONFIG_INPUT_TWL6040_VIBRA is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-# CONFIG_KEYBOARD_GPIO is not set
-CONFIG_KEYBOARD_TWL4030=y
-CONFIG_KTIME_SCALAR=y
-# CONFIG_LCD_AMS369FG06 is not set
-CONFIG_LCD_CLASS_DEVICE=y
-# CONFIG_LCD_L4F00242T03 is not set
-# CONFIG_LCD_LD9040 is not set
-# CONFIG_LCD_LMS283GF05 is not set
-# CONFIG_LCD_LTV350QV is not set
-# CONFIG_LCD_PLATFORM is not set
-# CONFIG_LCD_S6E63M0 is not set
-# CONFIG_LCD_TDO24M is not set
-# CONFIG_LCD_VGG2432A4 is not set
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_PWM is not set
-# CONFIG_LEDS_REGULATOR is not set
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAC80211=m
-# CONFIG_MAC80211_DEBUGFS is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-CONFIG_MAC80211_HAS_RC=y
-# CONFIG_MAC80211_HWSIM is not set
-# CONFIG_MAC80211_LEDS is not set
-# CONFIG_MAC80211_MESH is not set
-CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_MINSTREL=y
-CONFIG_MAC80211_RC_MINSTREL_HT=y
-# CONFIG_MAC80211_RC_PID is not set
-# CONFIG_MACH_CM_T35 is not set
-# CONFIG_MACH_CM_T3517 is not set
-# CONFIG_MACH_CRANEBOARD is not set
-# CONFIG_MACH_DEVKIT8000 is not set
-# CONFIG_MACH_IGEP0020 is not set
-# CONFIG_MACH_IGEP0030 is not set
-# CONFIG_MACH_NOKIA_RM680 is not set
-# CONFIG_MACH_NOKIA_RX51 is not set
-# CONFIG_MACH_OMAP3517EVM is not set
-# CONFIG_MACH_OMAP3530_LV_SOM is not set
-# CONFIG_MACH_OMAP3EVM is not set
-CONFIG_MACH_OMAP3_BEAGLE=y
-# CONFIG_MACH_OMAP3_PANDORA is not set
-# CONFIG_MACH_OMAP3_TORPEDO is not set
-# CONFIG_MACH_OMAP_3430SDP is not set
-# CONFIG_MACH_OMAP_3630SDP is not set
-CONFIG_MACH_OMAP_GENERIC=y
-# CONFIG_MACH_OMAP_LDP is not set
-# CONFIG_MACH_OMAP_ZOOM2 is not set
-# CONFIG_MACH_OMAP_ZOOM3 is not set
-CONFIG_MACH_OVERO=y
-# CONFIG_MACH_SBC3530 is not set
-# CONFIG_MACH_TOUCHBOOK is not set
-CONFIG_MAILBOX=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MEMORY=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_TI_AM335X_TSCADC=y
-CONFIG_MFD_TPS65217=y
-# CONFIG_MFD_TPS65218 is not set
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TWL4030_AUDIO=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-# CONFIG_MMC_OMAP is not set
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_DATAFLASH=y
-# CONFIG_MTD_DATAFLASH_OTP is not set
-# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_BCH=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_BCH=y
-CONFIG_MTD_NAND_OMAP2=y
-CONFIG_MTD_NAND_OMAP_BCH=y
-# CONFIG_MTD_NAND_OMAP_BCH4 is not set
-CONFIG_MTD_NAND_OMAP_BCH8=y
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_OF is not set
-# CONFIG_MTD_SM_COMMON is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-# CONFIG_MWIFIEX is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-# CONFIG_NET_DMA is not set
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_RX_BUSY_POLL=y
-# CONFIG_NET_VENDOR_I825XX is not set
-# CONFIG_NL80211_TESTMODE is not set
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OMAP2PLUS_MBOX=y
-CONFIG_OMAP2_DSS=y
-CONFIG_OMAP2_DSS_DPI=y
-CONFIG_OMAP2_DSS_DRA7XX_DPI=y
-CONFIG_OMAP2_DSS_DSI=y
-CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
-CONFIG_OMAP2_DSS_SDI=y
-CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y
-# CONFIG_OMAP2_DSS_VENC is not set
-CONFIG_OMAP2_VRFB=y
-# CONFIG_OMAP3_EMU is not set
-# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
-# CONFIG_OMAP3_SDRC_AC_TIMING is not set
-CONFIG_OMAP4_DSS_HDMI=y
-CONFIG_OMAP4_DSS_HDMI_AUDIO=y
-CONFIG_OMAP4_ERRATA_I688=y
-CONFIG_OMAP5_DSS_HDMI=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_CONTROL_PHY=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_OMAP_INTERCONNECT=y
-CONFIG_OMAP_MBOX=y
-CONFIG_OMAP_MBOX_KFIFO_SIZE=256
-CONFIG_OMAP_MUX=y
-# CONFIG_OMAP_MUX_DEBUG is not set
-CONFIG_OMAP_MUX_WARNINGS=y
-CONFIG_OMAP_OCP2SCP=y
-CONFIG_OMAP_PACKAGE_CBB=y
-# CONFIG_OMAP_PIPE3 is not set
-CONFIG_OMAP_PM_NOOP=y
-CONFIG_OMAP_RESET_CLOCKS=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PINCTRL=y
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_PL310_ERRATA_727915=y
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_OPP=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_AVS=y
-# CONFIG_POWER_AVS_OMAP is not set
-CONFIG_PPS=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PWM=y
-# CONFIG_PWM_PCA9685 is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_PWM_TIECAP=y
-CONFIG_PWM_TIEHRPWM=y
-CONFIG_PWM_TIPWMSS=y
-# CONFIG_PWM_TWL is not set
-# CONFIG_PWM_TWL_LED is not set
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_DUMMY=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_TIAVSCLASS0=y
-CONFIG_REGULATOR_TPS65023=y
-CONFIG_REGULATOR_TPS6507X=y
-CONFIG_REGULATOR_TPS65217=y
-CONFIG_REGULATOR_TPS65910=y
-CONFIG_REGULATOR_TWL4030=y
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_TI=y
-# CONFIG_RFKILL_REGULATOR is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_RTC_DRV_TPS65910=y
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SENSORS_G762 is not set
-# CONFIG_SENSORS_HTU21 is not set
-CONFIG_SENSORS_LM75=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_OMAP=y
-CONFIG_SERIAL_OMAP_CONSOLE=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SMSC911X=y
-# CONFIG_SMSC911X_ARCH_HOOKS is not set
-CONFIG_SND=y
-CONFIG_SND_AM33XX_SOC_EVM=y
-CONFIG_SND_ARM=y
-CONFIG_SND_COMPRESS_OFFLOAD=y
-CONFIG_SND_DAVINCI_SOC=y
-CONFIG_SND_DAVINCI_SOC_MCASP=y
-CONFIG_SND_DMAENGINE_PCM=y
-# CONFIG_SND_EMU10K1_SEQ is not set
-CONFIG_SND_JACK=y
-CONFIG_SND_OMAP_SOC=y
-CONFIG_SND_OMAP_SOC_DMIC=y
-CONFIG_SND_OMAP_SOC_HDMI=y
-CONFIG_SND_OMAP_SOC_MCBSP=y
-CONFIG_SND_OMAP_SOC_MCPDM=y
-CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=y
-CONFIG_SND_OMAP_SOC_OMAP_HDMI=y
-CONFIG_SND_OMAP_SOC_OMAP_TWL4030=y
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-CONFIG_SND_PCM=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_DMIC=y
-CONFIG_SND_SOC_HDMI_CODEC=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-CONFIG_SND_SOC_TLV320AIC3X=y
-CONFIG_SND_SOC_TWL4030=y
-CONFIG_SND_SOC_TWL6040=y
-CONFIG_SND_TIMER=y
-CONFIG_SOC_AM33XX=y
-CONFIG_SOC_AM43XX=y
-CONFIG_SOC_BUS=y
-CONFIG_SOC_HAS_OMAP2_SDRC=y
-# CONFIG_SOC_OMAP3430 is not set
-# CONFIG_SOC_TI81XX is not set
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-# CONFIG_SPI_OMAP24XX is not set
-CONFIG_STOP_MACHINE=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_TIDSPBRIDGE is not set
-CONFIG_TI_CPPI41=y
-CONFIG_TI_CPSW=y
-CONFIG_TI_CPSW_PHY_SEL=y
-CONFIG_TI_CPTS=y
-CONFIG_TI_DAVINCI_CPDMA=y
-# CONFIG_TI_DAVINCI_EMAC is not set
-CONFIG_TI_DAVINCI_MDIO=y
-CONFIG_TI_EDMA=y
-CONFIG_TI_EMIF=y
-CONFIG_TI_PRIV_EDMA=y
-# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_BU21013 is not set
-# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_EGALAX is not set
-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_MAX11801 is not set
-# CONFIG_TOUCHSCREEN_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_ST1232 is not set
-CONFIG_TOUCHSCREEN_TI_AM335X_TSC=y
-# CONFIG_TOUCHSCREEN_TSC2005 is not set
-# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
-CONFIG_TREE_RCU=y
-CONFIG_TWL4030_CORE=y
-# CONFIG_TWL4030_MADC is not set
-CONFIG_TWL4030_POWER=y
-CONFIG_TWL4030_WATCHDOG=y
-CONFIG_TWL6040_CORE=y
-CONFIG_UID16=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_W35UND is not set
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_XEN is not set
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-# CONFIG_ZBUD is not set
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2012-2014 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-UBIFS_OPTS = -F -m 2048 -e 124KiB -c 4096 -U
-UBI_OPTS = -m 2048 -p 128KiB -s 512 -O 2048
-
-define Image/BuildKernel
- $(CP) $(KDIR)/zImage $(BIN_DIR)/openwrt-$(BOARD)-zImage
- ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
- $(CP) $(KDIR)/zImage-initramfs $(BIN_DIR)/openwrt-$(BOARD)-zImage-initramfs
- endif
-
- ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_KERNEL),)
- $(INSTALL_DIR) $(TARGET_DIR)/boot
- $(CP) $(BIN_DIR)/openwrt-$(BOARD)-zImage $(TARGET_DIR)/boot/zImage
- endif
- ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_DTB),)
- $(INSTALL_DIR) $(TARGET_DIR)/boot
- $(CP) $(DTS_DIR)/am335x*.dtb $(TARGET_DIR)/boot/
- $(CP) $(DTS_DIR)/omap3*.dtb $(TARGET_DIR)/boot/
- $(CP) $(DTS_DIR)/omap4*.dtb $(TARGET_DIR)/boot/
- endif
- -mkdir $(BIN_DIR)/dtbs
- -$(CP) $(DTS_DIR)/am335x*.dtb $(BIN_DIR)/dtbs/
- -$(CP) $(DTS_DIR)/omap3*.dtb $(BIN_DIR)/dtbs/
- -$(CP) $(DTS_DIR)/omap4*.dtb $(BIN_DIR)/dtbs/
-endef
-
-define Image/Build
- $(call Image/Build/$(1),$(1))
-endef
-
-define Image/Build/jffs2-64k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=65536 conv=sync
-endef
-
-define Image/Build/jffs2-128k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=131072 conv=sync
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=131072 conv=sync
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-[rootfs]
-# Volume mode (other option is static)
-mode=ubi
-# Source image
-image=root.ubifs
-# Volume ID in UBI image
-vol_id=0
-# Allow for dynamic resize
-vol_type=dynamic
-# Volume name
-vol_name=rootfs
-# Autoresize volume at first mount
-vol_flags=autoresize
-
+++ /dev/null
-From 29f3723bf62d46c238dcc5436787a8ad6b25a385 Mon Sep 17 00:00:00 2001
-From: Lars Poeschel <poeschel@lemonage.de>
-Date: Wed, 7 Aug 2013 13:06:32 +0200
-Subject: [PATCH 02/14] ARM: dts: AM33xx: Correct gpio #interrupt-cells
- property
-
-Following commit ff5c9059 and therefore other omap platforms using
-the gpio-omap driver correct the #interrupt-cells property on am33xx
-too. The omap gpio binding documentaion also states that
-the #interrupt-cells property should be 2.
-
-Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
-Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
-Acked-by: Mark Rutland <mark.rutland@arm.com>
-Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
----
- arch/arm/boot/dts/am33xx.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -106,7 +106,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupt-cells = <1>;
-+ #interrupt-cells = <2>;
- reg = <0x44e07000 0x1000>;
- interrupts = <96>;
- };
-@@ -117,7 +117,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupt-cells = <1>;
-+ #interrupt-cells = <2>;
- reg = <0x4804c000 0x1000>;
- interrupts = <98>;
- };
-@@ -128,7 +128,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupt-cells = <1>;
-+ #interrupt-cells = <2>;
- reg = <0x481ac000 0x1000>;
- interrupts = <32>;
- };
-@@ -139,7 +139,7 @@
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
-- #interrupt-cells = <1>;
-+ #interrupt-cells = <2>;
- reg = <0x481ae000 0x1000>;
- interrupts = <62>;
- };
+++ /dev/null
-From 884d3962ef4787c8cf0b8a7a673531c623d1dff8 Mon Sep 17 00:00:00 2001
-From: Darren Etheridge <detheridge@ti.com>
-Date: Fri, 2 Aug 2013 15:35:36 -0500
-Subject: [PATCH 334/752] video: da8xx-fb: adding dt support
-
-Enhancing driver to enable probe triggered by a corresponding dt entry.
-
-Add da8xx-fb.txt documentation to devicetree section.
-
-Obtain fb_videomode details for the connected lcd panel using the
-display timing details present in DT.
-
-Ensure that platform data is present before checking whether platform
-callback is present (the one used to control backlight). So far this
-was not an issue as driver was purely non-DT triggered, but now DT
-support has been added this check must be performed.
-
-v2: squashing multiple commits from Afzal Mohammed (afzal@ti.com)
-v3: remove superfluous cast
-v4: expose both ti,am3352-lcdc and ti,da830-lcdc for .compatible
- as driver can use enhanced features of all version of the
- silicon block.
-v5: addressed review comments from Prabhakar Lad
-v6: Changed the .compatible naming to match the existing drm bindings
- for am33xx devices
-v7: clarify which compatible to use in the documentation for DA850
-
-Acked-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
-Signed-off-by: Darren Etheridge <detheridge@ti.com>
----
- .../devicetree/bindings/video/da8xx-fb.txt | 42 +++++++++++++
- drivers/video/da8xx-fb.c | 66 +++++++++++++++++++-
- 2 files changed, 105 insertions(+), 3 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/video/da8xx-fb.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/video/da8xx-fb.txt
-@@ -0,0 +1,42 @@
-+TI LCD Controller on DA830/DA850/AM335x SoC's
-+
-+Required properties:
-+- compatible:
-+ DA830, DA850 - "ti,da8xx-tilcdc"
-+ AM335x SoC's - "ti,am33xx-tilcdc"
-+- reg: Address range of lcdc register set
-+- interrupts: lcdc interrupt
-+- display-timings: typical videomode of lcd panel, represented as child.
-+ Refer Documentation/devicetree/bindings/video/display-timing.txt for
-+ display timing binding details. If multiple videomodes are mentioned
-+ in display timings node, typical videomode has to be mentioned as the
-+ native mode or it has to be first child (driver cares only for native
-+ videomode).
-+
-+Recommended properties:
-+- ti,hwmods: Name of the hwmod associated to the LCDC
-+
-+Example for am335x SoC's:
-+
-+lcdc@4830e000 {
-+ compatible = "ti,am33xx-tilcdc";
-+ reg = <0x4830e000 0x1000>;
-+ interrupts = <36>;
-+ ti,hwmods = "lcdc";
-+ status = "okay";
-+ display-timings {
-+ 800x480p62 {
-+ clock-frequency = <30000000>;
-+ hactive = <800>;
-+ vactive = <480>;
-+ hfront-porch = <39>;
-+ hback-porch = <39>;
-+ hsync-len = <47>;
-+ vback-porch = <29>;
-+ vfront-porch = <13>;
-+ vsync-len = <2>;
-+ hsync-active = <1>;
-+ vsync-active = <1>;
-+ };
-+ };
-+};
---- a/drivers/video/da8xx-fb.c
-+++ b/drivers/video/da8xx-fb.c
-@@ -36,6 +36,7 @@
- #include <linux/slab.h>
- #include <linux/delay.h>
- #include <linux/lcm.h>
-+#include <video/of_display_timing.h>
- #include <video/da8xx-fb.h>
- #include <asm/div64.h>
-
-@@ -1312,12 +1313,54 @@ static struct fb_ops da8xx_fb_ops = {
- .fb_blank = cfb_blank,
- };
-
-+static struct lcd_ctrl_config *da8xx_fb_create_cfg(struct platform_device *dev)
-+{
-+ struct lcd_ctrl_config *cfg;
-+
-+ cfg = devm_kzalloc(&dev->dev, sizeof(struct fb_videomode), GFP_KERNEL);
-+ if (!cfg)
-+ return NULL;
-+
-+ /* default values */
-+
-+ if (lcd_revision == LCD_VERSION_1)
-+ cfg->bpp = 16;
-+ else
-+ cfg->bpp = 32;
-+
-+ /*
-+ * For panels so far used with this LCDC, below statement is sufficient.
-+ * For new panels, if required, struct lcd_ctrl_cfg fields to be updated
-+ * with additional/modified values. Those values would have to be then
-+ * obtained from dt(requiring new dt bindings).
-+ */
-+
-+ cfg->panel_shade = COLOR_ACTIVE;
-+
-+ return cfg;
-+}
-+
- static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev)
- {
- struct da8xx_lcdc_platform_data *fb_pdata = dev->dev.platform_data;
- struct fb_videomode *lcdc_info;
-+ struct device_node *np = dev->dev.of_node;
- int i;
-
-+ if (np) {
-+ lcdc_info = devm_kzalloc(&dev->dev,
-+ sizeof(struct fb_videomode),
-+ GFP_KERNEL);
-+ if (!lcdc_info)
-+ return NULL;
-+
-+ if (of_get_fb_videomode(np, lcdc_info, OF_USE_NATIVE_MODE)) {
-+ dev_err(&dev->dev, "timings not available in DT\n");
-+ return NULL;
-+ }
-+ return lcdc_info;
-+ }
-+
- for (i = 0, lcdc_info = known_lcd_panels;
- i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) {
- if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
-@@ -1346,7 +1389,7 @@ static int fb_probe(struct platform_devi
- int ret;
- unsigned long ulcm;
-
-- if (fb_pdata == NULL) {
-+ if (fb_pdata == NULL && !device->dev.of_node) {
- dev_err(&device->dev, "Can not get platform data\n");
- return -ENOENT;
- }
-@@ -1386,7 +1429,10 @@ static int fb_probe(struct platform_devi
- break;
- }
-
-- lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
-+ if (device->dev.of_node)
-+ lcd_cfg = da8xx_fb_create_cfg(device);
-+ else
-+ lcd_cfg = fb_pdata->controller_data;
-
- if (!lcd_cfg) {
- ret = -EINVAL;
-@@ -1405,7 +1451,7 @@ static int fb_probe(struct platform_devi
- par->dev = &device->dev;
- par->lcdc_clk = tmp_lcdc_clk;
- par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
-- if (fb_pdata->panel_power_ctrl) {
-+ if (fb_pdata && fb_pdata->panel_power_ctrl) {
- par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
- par->panel_power_ctrl(1);
- }
-@@ -1653,6 +1699,19 @@ static int fb_resume(struct platform_dev
- #define fb_resume NULL
- #endif
-
-+#if IS_ENABLED(CONFIG_OF)
-+static const struct of_device_id da8xx_fb_of_match[] = {
-+ /*
-+ * this driver supports version 1 and version 2 of the
-+ * Texas Instruments lcd controller (lcdc) hardware block
-+ */
-+ {.compatible = "ti,da8xx-tilcdc", },
-+ {.compatible = "ti,am33xx-tilcdc", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, da8xx_fb_of_match);
-+#endif
-+
- static struct platform_driver da8xx_fb_driver = {
- .probe = fb_probe,
- .remove = fb_remove,
-@@ -1661,6 +1720,7 @@ static struct platform_driver da8xx_fb_d
- .driver = {
- .name = DRIVER_NAME,
- .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(da8xx_fb_of_match),
- },
- };
-
+++ /dev/null
-From 9a1a810516ae9cb3259b898b6879901c5b44fa90 Mon Sep 17 00:00:00 2001
-From: Prathap M S <msprathap@ti.com>
-Date: Mon, 2 Sep 2013 12:05:23 +0530
-Subject: [PATCH 343/752] video: da8xx-fb: Add API to register wait for vsync
- callback
-
-This patch adds APIs to register and unregister wait for vsync callback.
-This is derived from commit id 2d44302545da24fd22912d964102bc31a7489e97
-This commit id was part of 3.2 kernel sources.
-
-Signed-off-by: Prathap M S <msprathap@ti.com>
----
- drivers/video/da8xx-fb.c | 33 +++++++++++++++++++++++++++++++++
- include/video/da8xx-fb.h | 4 ++++
- 2 files changed, 37 insertions(+)
-
---- a/drivers/video/da8xx-fb.c
-+++ b/drivers/video/da8xx-fb.c
-@@ -198,6 +198,9 @@ static struct fb_fix_screeninfo da8xx_fb
- .accel = FB_ACCEL_NONE
- };
-
-+static vsync_callback_t vsync_cb_handler;
-+static void *vsync_cb_arg;
-+
- static struct fb_videomode known_lcd_panels[] = {
- /* Sharp LCD035Q3DG01 */
- [0] = {
-@@ -826,6 +829,32 @@ static int lcd_init(struct da8xx_fb_par
- return 0;
- }
-
-+int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)
-+{
-+ if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {
-+ vsync_cb_arg = arg;
-+ vsync_cb_handler = handler;
-+ } else {
-+ return -EEXIST;
-+ }
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(register_vsync_cb);
-+
-+int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)
-+{
-+ if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {
-+ vsync_cb_handler = NULL;
-+ vsync_cb_arg = NULL;
-+ } else {
-+ return -ENXIO;
-+ }
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(unregister_vsync_cb);
-+
- /* IRQ handler for version 2 of LCDC */
- static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
- {
-@@ -863,6 +892,8 @@ static irqreturn_t lcdc_irq_handler_rev0
- LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
- par->vsync_flag = 1;
- wake_up_interruptible(&par->vsync_wait);
-+ if (vsync_cb_handler)
-+ vsync_cb_handler(vsync_cb_arg);
- }
-
- if (stat & LCD_END_OF_FRAME1) {
-@@ -938,6 +969,8 @@ static irqreturn_t lcdc_irq_handler_rev0
- LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
- par->vsync_flag = 1;
- wake_up_interruptible(&par->vsync_wait);
-+ if (vsync_cb_handler)
-+ vsync_cb_handler(vsync_cb_arg);
- }
- }
-
---- a/include/video/da8xx-fb.h
-+++ b/include/video/da8xx-fb.h
-@@ -91,5 +91,9 @@ struct lcd_sync_arg {
- /* Proprietary FB_SYNC_ flags */
- #define FB_SYNC_CLK_INVERT 0x40000000
-
-+typedef void (*vsync_callback_t)(void *arg);
-+int register_vsync_cb(vsync_callback_t handler, void *arg, int idx);
-+int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx);
-+
- #endif /* ifndef DA8XX_FB_H */
-
+++ /dev/null
-From c99bd415829ef29adf71bb1e1b577650f10e93f5 Mon Sep 17 00:00:00 2001
-From: Darren Etheridge <detheridge@ti.com>
-Date: Mon, 4 Nov 2013 12:27:40 -0600
-Subject: [PATCH 752/752] video/da8xx-fb fix defect with vsync callback
- invocation
-
-Fix defect where SGX is running at half of the expected framerate.
-The original patch (@ commit ID 9a1a810516ae9cb3259b898b6879901c5b44fa90)
-seems to have a mistake where it only calls the callback
-for the even or the odd frames depending on the revision of the LCD controller
-This patch corrects this and invokes the callback for both odd and even frame
-for just the Rev02 version of the LCDC (won't find an SGX GPU on a Rev01).
-
-Signed-off-by: Darren Etheridge <detheridge@ti.com>
----
- drivers/video/da8xx-fb.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/video/da8xx-fb.c
-+++ b/drivers/video/da8xx-fb.c
-@@ -904,6 +904,8 @@ static irqreturn_t lcdc_irq_handler_rev0
- LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
- par->vsync_flag = 1;
- wake_up_interruptible(&par->vsync_wait);
-+ if (vsync_cb_handler)
-+ vsync_cb_handler(vsync_cb_arg);
- }
-
- /* Set only when controller is disabled and at the end of
-@@ -969,8 +971,6 @@ static irqreturn_t lcdc_irq_handler_rev0
- LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
- par->vsync_flag = 1;
- wake_up_interruptible(&par->vsync_wait);
-- if (vsync_cb_handler)
-- vsync_cb_handler(vsync_cb_arg);
- }
- }
-
+++ /dev/null
-Adds AM33XX EDMA support to the am33xx.dtsi as documented in
-Documentation/devicetree/bindings/dma/ti-edma.txt
-
-[Joel Fernandes <joelf@ti.com>]
-Drop DT entries that are non-hardware-description as discussed in [1]
-
-[1] https://patchwork.kernel.org/patch/2226761/
-
-Signed-off-by: Matt Porter <mporter@ti.com>
-Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
-
----
-arch/arm/boot/dts/am33xx.dtsi | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -100,6 +100,18 @@
- reg = <0x48200000 0x1000>;
- };
-
-+ edma: edma@49000000 {
-+ compatible = "ti,edma3";
-+ ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
-+ reg = <0x49000000 0x10000>,
-+ <0x44e10f90 0x10>;
-+ interrupts = <12 13 14>;
-+ #dma-cells = <1>;
-+ dma-channels = <64>;
-+ ti,edma-regions = <4>;
-+ ti,edma-slots = <256>;
-+ };
-+
- gpio0: gpio@44e07000 {
- compatible = "ti,omap4-gpio";
- ti,hwmods = "gpio1";
+++ /dev/null
-Adds DMA resources to the AM33XX SPI nodes.
-
-Signed-off-by: Matt Porter <mporter@ti.com>
-Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
-
----
-arch/arm/boot/dts/am33xx.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -335,6 +335,11 @@
- interrupts = <65>;
- ti,spi-num-cs = <2>;
- ti,hwmods = "spi0";
-+ dmas = <&edma 16
-+ &edma 17
-+ &edma 18
-+ &edma 19>;
-+ dma-names = "tx0", "rx0", "tx1", "rx1";
- status = "disabled";
- };
-
-@@ -346,6 +351,11 @@
- interrupts = <125>;
- ti,spi-num-cs = <2>;
- ti,hwmods = "spi1";
-+ dmas = <&edma 42
-+ &edma 43
-+ &edma 44
-+ &edma 45>;
-+ dma-names = "tx0", "rx0", "tx1", "rx1";
- status = "disabled";
- };
-
+++ /dev/null
-Adds AM33XX MMC support for am335x-bone, am335x-evm and am335x-evmsk boards.
-
-Also added is the DMA binding definitions based on the generic DMA request
-binding.
-
-Additional changes made to DTS:
-* Interrupt, reg and compatible properties added
-* ti,needs-special-hs-handling added
-
-Signed-off-by: Matt Porter <mporter@ti.com>
-Acked-by: Tony Lindgren <tony@atomide.com>
-Signed-off-by: Joel Fernandes <joelf@ti.com>
-
----
-.../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 26 ++++++++++++++-
- arch/arm/boot/dts/am335x-bone.dts | 11 +++++++
- arch/arm/boot/dts/am335x-evm.dts | 7 ++++
- arch/arm/boot/dts/am335x-evmsk.dts | 7 ++++
- arch/arm/boot/dts/am33xx.dtsi | 38 ++++++++++++++++++++++
- 5 files changed, 88 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
-+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
-@@ -20,8 +20,29 @@ ti,dual-volt: boolean, supports dual vol
- ti,non-removable: non-removable slot (like eMMC)
- ti,needs-special-reset: Requires a special softreset sequence
- ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
-+dmas: List of DMA specifiers with the controller specific format
-+as described in the generic DMA client binding. A tx and rx
-+specifier is required.
-+dma-names: List of DMA request names. These strings correspond
-+1:1 with the DMA specifiers listed in dmas. The string naming is
-+to be "rx" and "tx" for RX and TX DMA requests, respectively.
-+
-+Examples:
-+
-+[hwmod populated DMA resources]
-+
-+ mmc1: mmc@0x4809c000 {
-+ compatible = "ti,omap4-hsmmc";
-+ reg = <0x4809c000 0x400>;
-+ ti,hwmods = "mmc1";
-+ ti,dual-volt;
-+ bus-width = <4>;
-+ vmmc-supply = <&vmmc>; /* phandle to regulator node */
-+ ti,non-removable;
-+ };
-+
-+[generic DMA request binding]
-
--Example:
- mmc1: mmc@0x4809c000 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x4809c000 0x400>;
-@@ -30,4 +51,7 @@ Example:
- bus-width = <4>;
- vmmc-supply = <&vmmc>; /* phandle to regulator node */
- ti,non-removable;
-+ dmas = <&edma 24
-+ &edma 25>;
-+ dma-names = "tx", "rx";
- };
---- a/arch/arm/boot/dts/am335x-bone.dts
-+++ b/arch/arm/boot/dts/am335x-bone.dts
-@@ -9,3 +9,14 @@
-
- #include "am33xx.dtsi"
- #include "am335x-bone-common.dtsi"
-+
-+&ldo3_reg {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-always-on;
-+};
-+
-+&mmc1 {
-+ status = "okay";
-+ vmmc-supply = <&ldo3_reg>;
-+};
---- a/arch/arm/boot/dts/am335x-evm.dts
-+++ b/arch/arm/boot/dts/am335x-evm.dts
-@@ -477,6 +477,8 @@
- };
-
- vmmc_reg: regulator@12 {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
-@@ -517,3 +519,8 @@
- ti,adc-channels = <4 5 6 7>;
- };
- };
-+
-+&mmc1 {
-+ status = "okay";
-+ vmmc-supply = <&vmmc_reg>;
-+};
---- a/arch/arm/boot/dts/am335x-evmsk.dts
-+++ b/arch/arm/boot/dts/am335x-evmsk.dts
-@@ -393,6 +393,8 @@
- };
-
- vmmc_reg: regulator@12 {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
-@@ -419,3 +421,8 @@
- phy_id = <&davinci_mdio>, <1>;
- phy-mode = "rgmii-txid";
- };
-+
-+&mmc1 {
-+ status = "okay";
-+ vmmc-supply = <&vmmc_reg>;
-+};
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -240,6 +240,44 @@
- status = "disabled";
- };
-
-+ mmc1: mmc@48060000 {
-+ compatible = "ti,omap4-hsmmc";
-+ ti,hwmods = "mmc1";
-+ ti,dual-volt;
-+ ti,needs-special-reset;
-+ ti,needs-special-hs-handling;
-+ dmas = <&edma 24
-+ &edma 25>;
-+ dma-names = "tx", "rx";
-+ interrupts = <64>;
-+ interrupt-parent = <&intc>;
-+ reg = <0x48060000 0x1000>;
-+ status = "disabled";
-+ };
-+
-+ mmc2: mmc@481d8000 {
-+ compatible = "ti,omap4-hsmmc";
-+ ti,hwmods = "mmc2";
-+ ti,needs-special-reset;
-+ dmas = <&edma 2
-+ &edma 3>;
-+ dma-names = "tx", "rx";
-+ interrupts = <28>;
-+ interrupt-parent = <&intc>;
-+ reg = <0x481d8000 0x1000>;
-+ status = "disabled";
-+ };
-+
-+ mmc3: mmc@47810000 {
-+ compatible = "ti,omap4-hsmmc";
-+ ti,hwmods = "mmc3";
-+ ti,needs-special-reset;
-+ interrupts = <29>;
-+ interrupt-parent = <&intc>;
-+ reg = <0x47810000 0x1000>;
-+ status = "disabled";
-+ };
-+
- wdt2: wdt@44e35000 {
- compatible = "ti,omap3-wdt";
- ti,hwmods = "wd_timer2";
+++ /dev/null
-For modules/IPs/hwmods which do not have
--1- sys->class->reset()
-and
--2- hardreset lines
-and
--3- No way to do an ocp reset (no sysc control)
-the flag 'HWMOD_INIT_NO_RESET' is not much useful.
-
-Cleanup all such instances across various hwmod data files.
-
-Signed-off-by: Rajendra Nayak <rnayak@ti.com>
-
----
-arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 18 +++++++++---------
- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 6 +++---
- arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 6 +++---
- 3 files changed, 15 insertions(+), 15 deletions(-)
-
---- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
-+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
-@@ -52,7 +52,7 @@ static struct omap_hwmod am33xx_emif_hwm
- .name = "emif",
- .class = &am33xx_emif_hwmod_class,
- .clkdm_name = "l3_clkdm",
-- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_ddr_m2_div2_ck",
- .prcm = {
- .omap4 = {
-@@ -74,7 +74,7 @@ static struct omap_hwmod am33xx_l3_main_
- .name = "l3_main",
- .class = &am33xx_l3_hwmod_class,
- .clkdm_name = "l3_clkdm",
-- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
-@@ -96,7 +96,7 @@ static struct omap_hwmod am33xx_l3_instr
- .name = "l3_instr",
- .class = &am33xx_l3_hwmod_class,
- .clkdm_name = "l3_clkdm",
-- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
-@@ -119,7 +119,7 @@ static struct omap_hwmod am33xx_l4_ls_hw
- .name = "l4_ls",
- .class = &am33xx_l4_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
-- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
-@@ -134,7 +134,7 @@ static struct omap_hwmod am33xx_l4_hs_hw
- .name = "l4_hs",
- .class = &am33xx_l4_hwmod_class,
- .clkdm_name = "l4hs_clkdm",
-- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "l4hs_gclk",
- .prcm = {
- .omap4 = {
-@@ -150,7 +150,7 @@ static struct omap_hwmod am33xx_l4_wkup_
- .name = "l4_wkup",
- .class = &am33xx_l4_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
-- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+ .flags = HWMOD_INIT_NO_IDLE,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
-@@ -170,7 +170,7 @@ static struct omap_hwmod am33xx_mpu_hwmo
- .name = "mpu",
- .class = &am33xx_mpu_hwmod_class,
- .clkdm_name = "mpu_clkdm",
-- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_mpu_m2_ck",
- .prcm = {
- .omap4 = {
-@@ -450,7 +450,7 @@ static struct omap_hwmod am33xx_ocmcram_
- .name = "ocmcram",
- .class = &am33xx_ocmcram_hwmod_class,
- .clkdm_name = "l3_clkdm",
-- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
-@@ -532,7 +532,7 @@ static struct omap_hwmod am33xx_control_
- .name = "control",
- .class = &am33xx_control_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
-- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_core_m4_div2_ck",
- .prcm = {
- .omap4 = {
---- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
-+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
-@@ -914,7 +914,7 @@ static struct omap_hwmod omap44xx_emif1_
- .name = "emif1",
- .class = &omap44xx_emif_hwmod_class,
- .clkdm_name = "l3_emif_clkdm",
-- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "ddrphy_ck",
- .prcm = {
- .omap4 = {
-@@ -930,7 +930,7 @@ static struct omap_hwmod omap44xx_emif2_
- .name = "emif2",
- .class = &omap44xx_emif_hwmod_class,
- .clkdm_name = "l3_emif_clkdm",
-- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "ddrphy_ck",
- .prcm = {
- .omap4 = {
-@@ -2193,7 +2193,7 @@ static struct omap_hwmod omap44xx_mpu_hw
- .name = "mpu",
- .class = &omap44xx_mpu_hwmod_class,
- .clkdm_name = "mpuss_clkdm",
-- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_mpu_m2_ck",
- .prcm = {
- .omap4 = {
---- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
-+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
-@@ -352,7 +352,7 @@ static struct omap_hwmod omap54xx_emif1_
- .name = "emif1",
- .class = &omap54xx_emif_hwmod_class,
- .clkdm_name = "emif_clkdm",
-- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_core_h11x2_ck",
- .prcm = {
- .omap4 = {
-@@ -368,7 +368,7 @@ static struct omap_hwmod omap54xx_emif2_
- .name = "emif2",
- .class = &omap54xx_emif_hwmod_class,
- .clkdm_name = "emif_clkdm",
-- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_core_h11x2_ck",
- .prcm = {
- .omap4 = {
-@@ -1135,7 +1135,7 @@ static struct omap_hwmod omap54xx_mpu_hw
- .name = "mpu",
- .class = &omap54xx_mpu_hwmod_class,
- .clkdm_name = "mpu_clkdm",
-- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-+ .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_mpu_m2_ck",
- .prcm = {
- .omap4 = {
+++ /dev/null
-On OMAP we have co-processor IPs, memory controllers,
-GPIOs which control regulators and power switches to
-PMIC, and SoC internal Bus IPs, some or most of which
-should either not be reset or idled or both at init.
-(In some cases there are erratas which prevent an IP
-from being reset)
-Have a way to pass this information from DT.
-
-Update the am33xx/omap4 and omap5 dtsi files with the
-new bindings for modules which either should not be
-idled. reset or both. A later patch would cleanup the
-same information that exists today as part of the hwmod
-data files.
-
-Signed-off-by: Rajendra Nayak <rnayak@ti.com>
-
----
-.../devicetree/bindings/arm/omap/omap.txt | 3 ++-
- arch/arm/boot/dts/am33xx.dtsi | 2 ++
- arch/arm/boot/dts/omap4.dtsi | 3 +++
- arch/arm/boot/dts/omap5.dtsi | 2 ++
- 4 files changed, 9 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/arm/omap/omap.txt
-+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
-@@ -21,7 +21,8 @@ Required properties:
- Optional properties:
- - ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
- during suspend.
--
-+- ti,no-reset-on-init: When present, the module should not be reset at init
-+- ti,no-idle-on-init: When present, the module should not be idled at init
-
- Example:
-
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -667,6 +667,7 @@
- reg = <0x44d00000 0x4000 /* M3 UMEM */
- 0x44d80000 0x2000>; /* M3 DMEM */
- ti,hwmods = "wkup_m3";
-+ ti,no-reset-on-init;
- };
-
- elm: elm@48080000 {
-@@ -697,6 +698,7 @@
- gpmc: gpmc@50000000 {
- compatible = "ti,am3352-gpmc";
- ti,hwmods = "gpmc";
-+ ti,no-idle-on-init;
- reg = <0x50000000 0x2000>;
- interrupts = <100>;
- gpmc,num-cs = <7>;
---- a/arch/arm/boot/dts/omap4.dtsi
-+++ b/arch/arm/boot/dts/omap4.dtsi
-@@ -214,6 +214,7 @@
- gpmc,num-cs = <8>;
- gpmc,num-waitpins = <4>;
- ti,hwmods = "gpmc";
-+ ti,no-idle-on-init;
- };
-
- uart1: serial@4806a000 {
-@@ -492,6 +493,7 @@
- reg = <0x4c000000 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "emif1";
-+ ti,no-idle-on-init;
- phy-type = <1>;
- hw-caps-read-idle-ctrl;
- hw-caps-ll-interface;
-@@ -503,6 +505,7 @@
- reg = <0x4d000000 0x100>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "emif2";
-+ ti,no-idle-on-init;
- phy-type = <1>;
- hw-caps-read-idle-ctrl;
- hw-caps-ll-interface;
---- a/arch/arm/boot/dts/omap5.dtsi
-+++ b/arch/arm/boot/dts/omap5.dtsi
-@@ -607,6 +607,7 @@
- emif1: emif@0x4c000000 {
- compatible = "ti,emif-4d5";
- ti,hwmods = "emif1";
-+ ti,no-idle-on-init;
- phy-type = <2>; /* DDR PHY type: Intelli PHY */
- reg = <0x4c000000 0x400>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-@@ -618,6 +619,7 @@
- emif2: emif@0x4d000000 {
- compatible = "ti,emif-4d5";
- ti,hwmods = "emif2";
-+ ti,no-idle-on-init;
- phy-type = <2>; /* DDR PHY type: Intelli PHY */
- reg = <0x4d000000 0x400>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+++ /dev/null
-From f92d9597f781f6a5a39c73dc71604bd8a21c5299 Mon Sep 17 00:00:00 2001
-From: Rajendra Nayak <rnayak@ti.com>
-Date: Wed, 09 Oct 2013 07:26:55 +0000
-Subject: ARM: OMAP2+: hwmod: Extract no-idle and no-reset info from DT
-
-Now that we have DT bindings to specify which devices should not
-be reset and idled during init, make hwmod extract the information
-(and store them in internal flags) from Device tree.
-
-Signed-off-by: Rajendra Nayak <rnayak@ti.com>
-[paul@pwsan.com: updated to apply]
-Signed-off-by: Paul Walmsley <paul@pwsan.com>
-
----
---- a/arch/arm/mach-omap2/omap_hwmod.c
-+++ b/arch/arm/mach-omap2/omap_hwmod.c
-@@ -2393,6 +2393,8 @@ static struct device_node *of_dev_hwmod_
- /**
- * _init_mpu_rt_base - populate the virtual address for a hwmod
- * @oh: struct omap_hwmod * to locate the virtual address
-+ * @data: (unused, caller should pass NULL)
-+ * @np: struct device_node * of the IP block's device node in the DT data
- *
- * Cache the virtual address used by the MPU to access this IP block's
- * registers. This address is needed early so the OCP registers that
-@@ -2401,11 +2403,11 @@ static struct device_node *of_dev_hwmod_
- * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and
- * -ENXIO on absent or invalid register target address space.
- */
--static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
-+static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
-+ struct device_node *np)
- {
- struct omap_hwmod_addr_space *mem;
- void __iomem *va_start = NULL;
-- struct device_node *np;
-
- if (!oh)
- return -EINVAL;
-@@ -2421,12 +2423,10 @@ static int __init _init_mpu_rt_base(stru
- oh->name);
-
- /* Extract the IO space from device tree blob */
-- if (!of_have_populated_dt())
-+ if (!np)
- return -ENXIO;
-
-- np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
-- if (np)
-- va_start = of_iomap(np, oh->mpu_rt_idx);
-+ va_start = of_iomap(np, oh->mpu_rt_idx);
- } else {
- va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
- }
-@@ -2459,12 +2459,16 @@ static int __init _init_mpu_rt_base(stru
- static int __init _init(struct omap_hwmod *oh, void *data)
- {
- int r;
-+ struct device_node *np = NULL;
-
- if (oh->_state != _HWMOD_STATE_REGISTERED)
- return 0;
-
-+ if (of_have_populated_dt())
-+ np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
-+
- if (oh->class->sysc) {
-- r = _init_mpu_rt_base(oh, NULL);
-+ r = _init_mpu_rt_base(oh, NULL, np);
- if (r < 0) {
- WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n",
- oh->name);
-@@ -2478,6 +2482,12 @@ static int __init _init(struct omap_hwmo
- return -EINVAL;
- }
-
-+ if (np)
-+ if (of_find_property(np, "ti,no-reset-on-init", NULL))
-+ oh->flags |= HWMOD_INIT_NO_RESET;
-+ if (of_find_property(np, "ti,no-idle-on-init", NULL))
-+ oh->flags |= HWMOD_INIT_NO_IDLE;
-+
- oh->_state = _HWMOD_STATE_INITIALIZED;
-
- return 0;
+++ /dev/null
-With DT bindings to specify which devices should not be idled and reset
-at init being in place, and the corresponding dtsi files for am33xx/omap4
-and omap5 updated using those bindings, we can now clean up hwmod internal
-flags for HWMOD_INIT_NO_RESET and HWMOD_INIT_NO_IDLE which were infact used
-to specify the exact same information.
-
-For GPMC, the HWMOD_INIT_NO_RESET flag seems to be added in hwmod not due to
-any errata around the GPMC IP, but rather because any timings
-set by the bootloader are not being correctly programmed by the kernel.
-This seems like something that needs to be fixed as part of GPMC driver
-in the kernel, and hence the flag is left as is in hwmod, which can be
-removed once the driver does what its expected to.
-
-Signed-off-by: Rajendra Nayak <rnayak@ti.com>
-
----
-arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 4 ++--
- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 4 +---
- arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 2 --
- 3 files changed, 3 insertions(+), 7 deletions(-)
-
---- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
-+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
-@@ -198,7 +198,7 @@ static struct omap_hwmod am33xx_wkup_m3_
- .class = &am33xx_wkup_m3_hwmod_class,
- .clkdm_name = "l4_wkup_aon_clkdm",
- /* Keep hardreset asserted */
-- .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
-+ .flags = HWMOD_NO_IDLEST,
- .main_clk = "dpll_core_m4_div2_ck",
- .prcm = {
- .omap4 = {
-@@ -932,7 +932,7 @@ static struct omap_hwmod am33xx_gpmc_hwm
- .name = "gpmc",
- .class = &am33xx_gpmc_hwmod_class,
- .clkdm_name = "l3s_clkdm",
-- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-+ .flags = HWMOD_INIT_NO_RESET,
- .main_clk = "l3s_gclk",
- .prcm = {
- .omap4 = {
---- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
-+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
-@@ -914,7 +914,6 @@ static struct omap_hwmod omap44xx_emif1_
- .name = "emif1",
- .class = &omap44xx_emif_hwmod_class,
- .clkdm_name = "l3_emif_clkdm",
-- .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "ddrphy_ck",
- .prcm = {
- .omap4 = {
-@@ -930,7 +929,6 @@ static struct omap_hwmod omap44xx_emif2_
- .name = "emif2",
- .class = &omap44xx_emif_hwmod_class,
- .clkdm_name = "l3_emif_clkdm",
-- .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "ddrphy_ck",
- .prcm = {
- .omap4 = {
-@@ -1184,7 +1182,7 @@ static struct omap_hwmod omap44xx_gpmc_h
- * the kernel from the board file or DT data.
- * HWMOD_INIT_NO_RESET should be removed ASAP.
- */
-- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-+ .flags = HWMOD_INIT_NO_RESET,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
---- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
-+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
-@@ -352,7 +352,6 @@ static struct omap_hwmod omap54xx_emif1_
- .name = "emif1",
- .class = &omap54xx_emif_hwmod_class,
- .clkdm_name = "emif_clkdm",
-- .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_core_h11x2_ck",
- .prcm = {
- .omap4 = {
-@@ -368,7 +367,6 @@ static struct omap_hwmod omap54xx_emif2_
- .name = "emif2",
- .class = &omap54xx_emif_hwmod_class,
- .clkdm_name = "emif_clkdm",
-- .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_core_h11x2_ck",
- .prcm = {
- .omap4 = {
+++ /dev/null
-Do not reset GPIO0 at boot-up because GPIO0 is used
-on AM335x EVM-SK to control VTT regulators on DDR3.
-
-Without this EVM-SK boards fail to boot-up because
-of DDR3 corruption.
-
-Signed-off-by: Rajendra Nayak <rnayak@ti.com>
-
----
-arch/arm/boot/dts/am335x-evmsk.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm/boot/dts/am335x-evmsk.dts
-+++ b/arch/arm/boot/dts/am335x-evmsk.dts
-@@ -426,3 +426,7 @@
- status = "okay";
- vmmc-supply = <&vmmc_reg>;
- };
-+
-+&gpio0 {
-+ ti,no-reset-on-init;
-+};
+++ /dev/null
-Add the generic AM33XX SHAM module's device tree data and
-enable it for the am335x-evm, am335x-evmsk, and am335x-bone
-platforms. Also add Documentation file describing the data
-for the SHAM module.
-
-[joelf@ti.com: Dropped interrupt-parrent property, documentation fixups]
-CC: Paul Walmsley <paul@pwsan.com>
-Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
-Acked-by: Mark Rutland <mark.rutland@arm.com>
-
----
-.../devicetree/bindings/crypto/omap-sham.txt | 28 ++++++++++++++++++++++
- arch/arm/boot/dts/am335x-bone.dts | 4 ++++
- arch/arm/boot/dts/am335x-evm.dts | 4 ++++
- arch/arm/boot/dts/am335x-evmsk.dts | 4 ++++
- arch/arm/boot/dts/am33xx.dtsi | 9 +++++++
- 5 files changed, 49 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/crypto/omap-sham.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/crypto/omap-sham.txt
-@@ -0,0 +1,28 @@
-+OMAP SoC SHA crypto Module
-+
-+Required properties:
-+
-+- compatible : Should contain entries for this and backward compatible
-+ SHAM versions:
-+ - "ti,omap2-sham" for OMAP2 & OMAP3.
-+ - "ti,omap4-sham" for OMAP4 and AM33XX.
-+ Note that these two versions are incompatible.
-+- ti,hwmods: Name of the hwmod associated with the SHAM module
-+- reg : Offset and length of the register set for the module
-+- interrupts : the interrupt-specifier for the SHAM module.
-+
-+Optional properties:
-+- dmas: DMA specifiers for the rx dma. See the DMA client binding,
-+ Documentation/devicetree/bindings/dma/dma.txt
-+- dma-names: DMA request name. Should be "rx" if a dma is present.
-+
-+Example:
-+ /* AM335x */
-+ sham: sham@53100000 {
-+ compatible = "ti,omap4-sham";
-+ ti,hwmods = "sham";
-+ reg = <0x53100000 0x200>;
-+ interrupts = <109>;
-+ dmas = <&edma 36>;
-+ dma-names = "rx";
-+ };
---- a/arch/arm/boot/dts/am335x-bone.dts
-+++ b/arch/arm/boot/dts/am335x-bone.dts
-@@ -20,3 +20,7 @@
- status = "okay";
- vmmc-supply = <&ldo3_reg>;
- };
-+
-+&sham {
-+ status = "okay";
-+};
---- a/arch/arm/boot/dts/am335x-evm.dts
-+++ b/arch/arm/boot/dts/am335x-evm.dts
-@@ -524,3 +524,7 @@
- status = "okay";
- vmmc-supply = <&vmmc_reg>;
- };
-+
-+&sham {
-+ status = "okay";
-+};
---- a/arch/arm/boot/dts/am335x-evmsk.dts
-+++ b/arch/arm/boot/dts/am335x-evmsk.dts
-@@ -430,3 +430,7 @@
- &gpio0 {
- ti,no-reset-on-init;
- };
-+
-+&sham {
-+ status = "okay";
-+};
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -707,5 +707,14 @@
- #size-cells = <1>;
- status = "disabled";
- };
-+
-+ sham: sham@53100000 {
-+ compatible = "ti,omap4-sham";
-+ ti,hwmods = "sham";
-+ reg = <0x53100000 0x200>;
-+ interrupts = <109>;
-+ dmas = <&edma 36>;
-+ dma-names = "rx";
-+ };
- };
- };
+++ /dev/null
-Add the generic AM33XX AES module's device tree data and
-enable it for the am335x-evm, am335x-evmsk, and am335x-bone
-platforms. Also add Documentation file describing the data
-for the AES module.
-
-[joelf@ti.com: Dropped interrupt-parent propert, documentation fixups]
-
-CC: Paul Walmsley <paul@pwsan.com>
-Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
-
----
-.../devicetree/bindings/crypto/omap-aes.txt | 31 ++++++++++++++++++++++
- arch/arm/boot/dts/am335x-bone.dts | 4 +++
- arch/arm/boot/dts/am335x-evm.dts | 4 +++
- arch/arm/boot/dts/am335x-evmsk.dts | 4 +++
- arch/arm/boot/dts/am33xx.dtsi | 10 +++++++
- 5 files changed, 53 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/crypto/omap-aes.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/crypto/omap-aes.txt
-@@ -0,0 +1,31 @@
-+OMAP SoC AES crypto Module
-+
-+Required properties:
-+
-+- compatible : Should contain entries for this and backward compatible
-+ AES versions:
-+ - "ti,omap2-aes" for OMAP2.
-+ - "ti,omap3-aes" for OMAP3.
-+ - "ti,omap4-aes" for OMAP4 and AM33XX.
-+ Note that the OMAP2 and 3 versions are compatible (OMAP3 supports
-+ more algorithms) but they are incompatible with OMAP4.
-+- ti,hwmods: Name of the hwmod associated with the AES module
-+- reg : Offset and length of the register set for the module
-+- interrupts : the interrupt-specifier for the AES module.
-+
-+Optional properties:
-+- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
-+ Documentation/devicetree/bindings/dma/dma.txt
-+- dma-names: DMA request names should include "tx" and "rx" if present.
-+
-+Example:
-+ /* AM335x */
-+ aes: aes@53500000 {
-+ compatible = "ti,omap4-aes";
-+ ti,hwmods = "aes";
-+ reg = <0x53500000 0xa0>;
-+ interrupts = <102>;
-+ dmas = <&edma 6>,
-+ <&edma 5>;
-+ dma-names = "tx", "rx";
-+ };
---- a/arch/arm/boot/dts/am335x-bone.dts
-+++ b/arch/arm/boot/dts/am335x-bone.dts
-@@ -24,3 +24,7 @@
- &sham {
- status = "okay";
- };
-+
-+&aes {
-+ status = "okay";
-+};
---- a/arch/arm/boot/dts/am335x-evm.dts
-+++ b/arch/arm/boot/dts/am335x-evm.dts
-@@ -528,3 +528,7 @@
- &sham {
- status = "okay";
- };
-+
-+&aes {
-+ status = "okay";
-+};
---- a/arch/arm/boot/dts/am335x-evmsk.dts
-+++ b/arch/arm/boot/dts/am335x-evmsk.dts
-@@ -434,3 +434,7 @@
- &sham {
- status = "okay";
- };
-+
-+&aes {
-+ status = "okay";
-+};
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -716,5 +716,15 @@
- dmas = <&edma 36>;
- dma-names = "rx";
- };
-+
-+ aes: aes@53500000 {
-+ compatible = "ti,omap4-aes";
-+ ti,hwmods = "aes";
-+ reg = <0x53500000 0xa0>;
-+ interrupts = <102>;
-+ dmas = <&edma 6>,
-+ <&edma 5>;
-+ dma-names = "tx", "rx";
-+ };
- };
- };
+++ /dev/null
-AES interrupts were previously not used, but after recent changes to omap-aes
-driver, its being used. We correct the interrupt number to have working PIO
-mode.
-
-Signed-off-by: Joel Fernandes <joelf@ti.com>
-
----
-arch/arm/boot/dts/am33xx.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -721,7 +721,7 @@
- compatible = "ti,omap4-aes";
- ti,hwmods = "aes";
- reg = <0x53500000 0xa0>;
-- interrupts = <102>;
-+ interrupts = <103>;
- dmas = <&edma 6>,
- <&edma 5>;
- dma-names = "tx", "rx";
+++ /dev/null
-Add RNG hwmod data for AM33xx SoC.
-
-Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
-
----
-* Made am33xx_l4_per__rng structure as static to fix sparse warning
-
- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 36 ++++++++++++++++++++++++++++
- 1 file changed, 36 insertions(+)
-
---- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
-+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
-@@ -2480,6 +2480,41 @@ static struct omap_hwmod_ocp_if am33xx_l
- .user = OCP_USER_MPU | OCP_USER_SDMA,
- };
-
-+/* rng */
-+static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
-+ .rev_offs = 0x1fe0,
-+ .sysc_offs = 0x1fe4,
-+ .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
-+ .idlemodes = SIDLE_FORCE | SIDLE_NO,
-+ .sysc_fields = &omap_hwmod_sysc_type1,
-+};
-+
-+static struct omap_hwmod_class am33xx_rng_hwmod_class = {
-+ .name = "rng",
-+ .sysc = &am33xx_rng_sysc,
-+};
-+
-+static struct omap_hwmod am33xx_rng_hwmod = {
-+ .name = "rng",
-+ .class = &am33xx_rng_hwmod_class,
-+ .clkdm_name = "l4ls_clkdm",
-+ .flags = HWMOD_SWSUP_SIDLE,
-+ .main_clk = "rng_fck",
-+ .prcm = {
-+ .omap4 = {
-+ .clkctrl_offs = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,
-+ .modulemode = MODULEMODE_SWCTRL,
-+ },
-+ },
-+};
-+
-+static struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
-+ .master = &am33xx_l4_ls_hwmod,
-+ .slave = &am33xx_rng_hwmod,
-+ .clk = "rng_fck",
-+ .user = OCP_USER_MPU,
-+};
-+
- static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
- &am33xx_l3_main__emif,
- &am33xx_mpu__l3_main,
-@@ -2559,6 +2594,7 @@ static struct omap_hwmod_ocp_if *am33xx_
- &am33xx_cpgmac0__mdio,
- &am33xx_l3_main__sha0,
- &am33xx_l3_main__aes0,
-+ &am33xx_l4_per__rng,
- NULL,
- };
-
+++ /dev/null
-From 13254d51149ce1a0fdbb38fa229c6cc91bcbe6ec Mon Sep 17 00:00:00 2001
-From: Jyri Sarha <jsarha@ti.com>
-Date: Fri, 13 Sep 2013 17:43:18 +0300
-Subject: [PATCH 211/752] ASoC: davinci-evm: Move sysclk logic away from
- evm_hw_params
-
-The sysclk rate does not change runtime so it should be initialized at
-init time.
-
-Signed-off-by: Jyri Sarha <jsarha@ti.com>
----
- sound/soc/davinci/davinci-evm.c | 64 +++++++++++++++++++++++++++------------
- 1 file changed, 44 insertions(+), 20 deletions(-)
-
---- a/sound/soc/davinci/davinci-evm.c
-+++ b/sound/soc/davinci/davinci-evm.c
-@@ -27,6 +27,10 @@
- #include "davinci-i2s.h"
- #include "davinci-mcasp.h"
-
-+struct snd_soc_card_drvdata_davinci {
-+ unsigned sysclk;
-+};
-+
- #define AUDIO_FORMAT (SND_SOC_DAIFMT_DSP_B | \
- SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF)
- static int evm_hw_params(struct snd_pcm_substream *substream,
-@@ -35,27 +39,11 @@ static int evm_hw_params(struct snd_pcm_
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_dai *codec_dai = rtd->codec_dai;
- struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+ struct snd_soc_codec *codec = rtd->codec;
-+ struct snd_soc_card *soc_card = codec->card;
- int ret = 0;
-- unsigned sysclk;
--
-- /* ASP1 on DM355 EVM is clocked by an external oscillator */
-- if (machine_is_davinci_dm355_evm() || machine_is_davinci_dm6467_evm() ||
-- machine_is_davinci_dm365_evm())
-- sysclk = 27000000;
--
-- /* ASP0 in DM6446 EVM is clocked by U55, as configured by
-- * board-dm644x-evm.c using GPIOs from U18. There are six
-- * options; here we "know" we use a 48 KHz sample rate.
-- */
-- else if (machine_is_davinci_evm())
-- sysclk = 12288000;
--
-- else if (machine_is_davinci_da830_evm() ||
-- machine_is_davinci_da850_evm())
-- sysclk = 24576000;
--
-- else
-- return -EINVAL;
-+ unsigned sysclk = ((struct snd_soc_card_drvdata_davinci *)
-+ snd_soc_card_get_drvdata(soc_card))->sysclk;
-
- /* set codec DAI configuration */
- ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT);
-@@ -243,35 +231,65 @@ static struct snd_soc_dai_link da850_evm
- };
-
- /* davinci dm6446 evm audio machine driver */
-+/*
-+ * ASP0 in DM6446 EVM is clocked by U55, as configured by
-+ * board-dm644x-evm.c using GPIOs from U18. There are six
-+ * options; here we "know" we use a 48 KHz sample rate.
-+ */
-+static struct snd_soc_card_drvdata_davinci dm6446_snd_soc_card_drvdata = {
-+ .sysclk = 12288000,
-+};
-+
- static struct snd_soc_card dm6446_snd_soc_card_evm = {
- .name = "DaVinci DM6446 EVM",
- .owner = THIS_MODULE,
- .dai_link = &dm6446_evm_dai,
- .num_links = 1,
-+ .drvdata = &dm6446_snd_soc_card_drvdata,
- };
-
- /* davinci dm355 evm audio machine driver */
-+/* ASP1 on DM355 EVM is clocked by an external oscillator */
-+static struct snd_soc_card_drvdata_davinci dm355_snd_soc_card_drvdata = {
-+ .sysclk = 27000000,
-+};
-+
- static struct snd_soc_card dm355_snd_soc_card_evm = {
- .name = "DaVinci DM355 EVM",
- .owner = THIS_MODULE,
- .dai_link = &dm355_evm_dai,
- .num_links = 1,
-+ .drvdata = &dm355_snd_soc_card_drvdata,
- };
-
- /* davinci dm365 evm audio machine driver */
-+static struct snd_soc_card_drvdata_davinci dm365_snd_soc_card_drvdata = {
-+ .sysclk = 27000000,
-+};
-+
- static struct snd_soc_card dm365_snd_soc_card_evm = {
- .name = "DaVinci DM365 EVM",
- .owner = THIS_MODULE,
- .dai_link = &dm365_evm_dai,
- .num_links = 1,
-+ .drvdata = &dm365_snd_soc_card_drvdata,
- };
-
- /* davinci dm6467 evm audio machine driver */
-+static struct snd_soc_card_drvdata_davinci dm6467_snd_soc_card_drvdata = {
-+ .sysclk = 27000000,
-+};
-+
- static struct snd_soc_card dm6467_snd_soc_card_evm = {
- .name = "DaVinci DM6467 EVM",
- .owner = THIS_MODULE,
- .dai_link = dm6467_evm_dai,
- .num_links = ARRAY_SIZE(dm6467_evm_dai),
-+ .drvdata = &dm6467_snd_soc_card_drvdata,
-+};
-+
-+static struct snd_soc_card_drvdata_davinci da830_snd_soc_card_drvdata = {
-+ .sysclk = 24576000,
- };
-
- static struct snd_soc_card da830_snd_soc_card = {
-@@ -279,6 +297,11 @@ static struct snd_soc_card da830_snd_soc
- .owner = THIS_MODULE,
- .dai_link = &da830_evm_dai,
- .num_links = 1,
-+ .drvdata = &da830_snd_soc_card_drvdata,
-+};
-+
-+static struct snd_soc_card_drvdata_davinci da850_snd_soc_card_drvdata = {
-+ .sysclk = 24576000,
- };
-
- static struct snd_soc_card da850_snd_soc_card = {
-@@ -286,6 +309,7 @@ static struct snd_soc_card da850_snd_soc
- .owner = THIS_MODULE,
- .dai_link = &da850_evm_dai,
- .num_links = 1,
-+ .drvdata = &da850_snd_soc_card_drvdata,
- };
-
- static struct platform_device *evm_snd_device;
+++ /dev/null
-From af9ef849e8700327b807361344427a43c38e823a Mon Sep 17 00:00:00 2001
-From: "Hebbar, Gururaja" <gururaja.hebbar@ti.com>
-Date: Tue, 31 Jul 2012 21:25:38 +0530
-Subject: [PATCH 212/752] ASoC: davinci-evm: Add device tree binding
-
-Device tree support for Davinci Machine driver
-
-When the board boots with device tree, the driver will receive card,
-codec, dai interface details (like the card name, DAPM routing map,
-phandle for the audio components described in the dts file, codec mclk
-speed). The card will be set up based on this information. Since the
-routing is provided via DT we can mark the card fully routed so core
-can take care of disconnecting the unused pins.
-
-Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
-Signed-off-by: Darren Etheridge <detheridge@ti.com>
-Signed-off-by: Jyri Sarha <jsarha@ti.com>
----
- .../bindings/sound/davinci-evm-audio.txt | 58 ++++++++++
- sound/soc/davinci/davinci-evm.c | 120 +++++++++++++++++++-
- 2 files changed, 176 insertions(+), 2 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
-@@ -0,0 +1,58 @@
-+* Texas Instruments SoC audio setups with TLV320AIC3X Codec
-+
-+Required properties:
-+- compatible : "ti,da830-evm-audio" : forDM365/DA8xx/OMAPL1x/AM33xx
-+- ti,model : The user-visible name of this sound complex.
-+- ti,audio-codec : The phandle of the TLV320AIC3x audio codec
-+- ti,mcasp-controller : The phandle of the McASP controller
-+- ti,codec-clock-rate : The Codec Clock rate (in Hz) applied to the Codec
-+- ti,audio-routing : A list of the connections between audio components.
-+ Each entry is a pair of strings, the first being the connection's sink,
-+ the second being the connection's source. Valid names for sources and
-+ sinks are the codec's pins, and the jacks on the board:
-+
-+ TLV320AIC3X pins:
-+
-+ * LLOUT
-+ * RLOUT
-+ * MONO_LOUT
-+ * HPLOUT
-+ * HPROUT
-+ * HPLCOM
-+ * HPRCOM
-+ * MIC3L
-+ * MIC3R
-+ * LINE1L
-+ * LINE2L
-+ * LINE1R
-+ * LINE2R
-+
-+ Board connectors:
-+
-+ * Headphone Jack
-+ * Line Out
-+ * Mic Jack
-+ * Line In
-+
-+
-+Example:
-+
-+sound {
-+ compatible = "ti,da830-evm-audio";
-+ ti,model = "DA830 EVM";
-+ ti,audio-codec = <&tlv320aic3x>;
-+ ti,mcasp-controller = <&mcasp1>;
-+ ti,codec-clock-rate = <12000000>;
-+ ti,audio-routing =
-+ "Headphone Jack", "HPLOUT",
-+ "Headphone Jack", "HPROUT",
-+ "Line Out", "LLOUT",
-+ "Line Out", "RLOUT",
-+ "MIC3L", "Mic Bias 2V",
-+ "MIC3R", "Mic Bias 2V",
-+ "Mic Bias 2V", "Mic Jack",
-+ "LINE1L", "Line In",
-+ "LINE2L", "Line In",
-+ "LINE1R", "Line In",
-+ "LINE2R", "Line In";
-+};
---- a/sound/soc/davinci/davinci-evm.c
-+++ b/sound/soc/davinci/davinci-evm.c
-@@ -16,6 +16,7 @@
- #include <linux/platform_device.h>
- #include <linux/platform_data/edma.h>
- #include <linux/i2c.h>
-+#include <linux/of_platform.h>
- #include <sound/core.h>
- #include <sound/pcm.h>
- #include <sound/soc.h>
-@@ -23,6 +24,8 @@
- #include <asm/dma.h>
- #include <asm/mach-types.h>
-
-+#include <linux/edma.h>
-+
- #include "davinci-pcm.h"
- #include "davinci-i2s.h"
- #include "davinci-mcasp.h"
-@@ -121,13 +124,22 @@ static int evm_aic3x_init(struct snd_soc
- {
- struct snd_soc_codec *codec = rtd->codec;
- struct snd_soc_dapm_context *dapm = &codec->dapm;
-+ struct device_node *np = codec->card->dev->of_node;
-+ int ret;
-
- /* Add davinci-evm specific widgets */
- snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
- ARRAY_SIZE(aic3x_dapm_widgets));
-
-- /* Set up davinci-evm specific audio path audio_map */
-- snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
-+ if (np) {
-+ ret = snd_soc_of_parse_audio_routing(codec->card,
-+ "ti,audio-routing");
-+ if (ret)
-+ return ret;
-+ } else {
-+ /* Set up davinci-evm specific audio path audio_map */
-+ snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
-+ }
-
- /* not connected */
- snd_soc_dapm_disable_pin(dapm, "MONO_LOUT");
-@@ -312,6 +324,98 @@ static struct snd_soc_card da850_snd_soc
- .drvdata = &da850_snd_soc_card_drvdata,
- };
-
-+#if defined(CONFIG_OF)
-+
-+/*
-+ * The struct is used as place holder. It will be completely
-+ * filled with data from dt node.
-+ */
-+static struct snd_soc_dai_link evm_dai_tlv320aic3x = {
-+ .name = "TLV320AIC3X",
-+ .stream_name = "AIC3X",
-+ .codec_dai_name = "tlv320aic3x-hifi",
-+ .ops = &evm_ops,
-+ .init = evm_aic3x_init,
-+};
-+
-+static const struct of_device_id davinci_evm_dt_ids[] = {
-+ {
-+ .compatible = "ti,da830-evm-audio",
-+ .data = (void *) &evm_dai_tlv320aic3x,
-+ },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, davinci_evm_dt_ids);
-+
-+/* davinci evm audio machine driver */
-+static struct snd_soc_card evm_soc_card = {
-+ .owner = THIS_MODULE,
-+ .num_links = 1,
-+};
-+
-+static int davinci_evm_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ const struct of_device_id *match =
-+ of_match_device(of_match_ptr(davinci_evm_dt_ids), &pdev->dev);
-+ struct snd_soc_dai_link *dai = (struct snd_soc_dai_link *) match->data;
-+ struct snd_soc_card_drvdata_davinci *drvdata = NULL;
-+ int ret = 0;
-+
-+ evm_soc_card.dai_link = dai;
-+
-+ dai->codec_of_node = of_parse_phandle(np, "ti,audio-codec", 0);
-+ if (!dai->codec_of_node)
-+ return -EINVAL;
-+
-+ dai->cpu_of_node = of_parse_phandle(np, "ti,mcasp-controller", 0);
-+ if (!dai->cpu_of_node)
-+ return -EINVAL;
-+
-+ dai->platform_of_node = dai->cpu_of_node;
-+
-+ evm_soc_card.dev = &pdev->dev;
-+ ret = snd_soc_of_parse_card_name(&evm_soc_card, "ti,model");
-+ if (ret)
-+ return ret;
-+
-+ drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
-+ if (!drvdata)
-+ return -ENOMEM;
-+
-+ ret = of_property_read_u32(np, "ti,codec-clock-rate", &drvdata->sysclk);
-+ if (ret < 0)
-+ return -EINVAL;
-+
-+ snd_soc_card_set_drvdata(&evm_soc_card, drvdata);
-+ ret = snd_soc_register_card(&evm_soc_card);
-+
-+ if (ret)
-+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
-+
-+ return ret;
-+}
-+
-+static int davinci_evm_remove(struct platform_device *pdev)
-+{
-+ struct snd_soc_card *card = platform_get_drvdata(pdev);
-+
-+ snd_soc_unregister_card(card);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver davinci_evm_driver = {
-+ .probe = davinci_evm_probe,
-+ .remove = davinci_evm_remove,
-+ .driver = {
-+ .name = "davinci_evm",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(davinci_evm_dt_ids),
-+ },
-+};
-+#endif
-+
- static struct platform_device *evm_snd_device;
-
- static int __init evm_init(void)
-@@ -320,6 +424,13 @@ static int __init evm_init(void)
- int index;
- int ret;
-
-+ /*
-+ * If dtb is there, the devices will be created dynamically.
-+ * Only register platfrom driver structure.
-+ */
-+ if (of_have_populated_dt())
-+ return platform_driver_register(&davinci_evm_driver);
-+
- if (machine_is_davinci_evm()) {
- evm_snd_dev_data = &dm6446_snd_soc_card_evm;
- index = 0;
-@@ -355,6 +466,11 @@ static int __init evm_init(void)
-
- static void __exit evm_exit(void)
- {
-+ if (of_have_populated_dt()) {
-+ platform_driver_unregister(&davinci_evm_driver);
-+ return;
-+ }
-+
- platform_device_unregister(evm_snd_device);
- }
-
+++ /dev/null
-From fb2002dbc326d2e408698038b668b19741567a48 Mon Sep 17 00:00:00 2001
-From: Jyri Sarha <jsarha@ti.com>
-Date: Fri, 6 Sep 2013 12:15:00 +0300
-Subject: [PATCH 213/752] ASoC: davinci-mcasp: Add DMA register locations to
- DT
-
-This patch adds DMA register location to mcasp DT bindings. On am33xx
-SoCs the McASP registers are mapped trough L4 interconnect, which is
-not accessible by the DMA controller, so McASP data port is mapped
-trough L3 to a different location.
-
-Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
-Signed-off-by: Darren Etheridge <detheridge@ti.com>
-Signed-off-by: Jyri Sarha <jsarha@ti.com>
----
- .../bindings/sound/davinci-mcasp-audio.txt | 8 ++-
- sound/soc/davinci/davinci-mcasp.c | 59 +++++++++++++-------
- 2 files changed, 46 insertions(+), 21 deletions(-)
-
---- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
-+++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
-@@ -6,7 +6,11 @@ Required properties:
- "ti,da830-mcasp-audio" : for both DA830 & DA850 platforms
- "ti,omap2-mcasp-audio" : for OMAP2 platforms (TI81xx, AM33xx)
-
--- reg : Should contain McASP registers offset and length
-+- reg : Should contain McASP registers address and length for mpu and
-+ optionally for dma controller access.
-+- reg-names : The mandatory reg-range must be named "mpu" and the optional DMA
-+ reg-range must be named "dma". For backward compatibility it is
-+ good to keep "mpu" first in the list.
- - interrupts : Interrupt number for McASP
- - op-mode : I2S/DIT ops mode.
- - tdm-slots : Slots for TDM operation.
-@@ -15,7 +19,6 @@ Required properties:
- to "num-serializer" parameter. Each entry is a number indication
- serializer pin direction. (0 - INACTIVE, 1 - TX, 2 - RX)
-
--
- Optional properties:
-
- - ti,hwmods : Must be "mcasp<n>", n is controller instance starting 0
-@@ -31,6 +34,7 @@ mcasp0: mcasp0@1d00000 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x100000 0x3000>;
-+ reg-names "mpu";
- interrupts = <82 83>;
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
---- a/sound/soc/davinci/davinci-mcasp.c
-+++ b/sound/soc/davinci/davinci-mcasp.c
-@@ -1001,18 +1001,40 @@ static const struct snd_soc_component_dr
- .name = "davinci-mcasp",
- };
-
-+/* Some HW specific values and defaults. The rest is filled in from DT. */
-+static struct snd_platform_data dm646x_mcasp_pdata = {
-+ .tx_dma_offset = 0x400,
-+ .rx_dma_offset = 0x400,
-+ .asp_chan_q = EVENTQ_0,
-+ .version = MCASP_VERSION_1,
-+};
-+
-+static struct snd_platform_data da830_mcasp_pdata = {
-+ .tx_dma_offset = 0x2000,
-+ .rx_dma_offset = 0x2000,
-+ .asp_chan_q = EVENTQ_0,
-+ .version = MCASP_VERSION_2,
-+};
-+
-+static struct snd_platform_data omap2_mcasp_pdata = {
-+ .tx_dma_offset = 0,
-+ .rx_dma_offset = 0,
-+ .asp_chan_q = EVENTQ_0,
-+ .version = MCASP_VERSION_3,
-+};
-+
- static const struct of_device_id mcasp_dt_ids[] = {
- {
- .compatible = "ti,dm646x-mcasp-audio",
-- .data = (void *)MCASP_VERSION_1,
-+ .data = &dm646x_mcasp_pdata,
- },
- {
- .compatible = "ti,da830-mcasp-audio",
-- .data = (void *)MCASP_VERSION_2,
-+ .data = &da830_mcasp_pdata,
- },
- {
- .compatible = "ti,omap2-mcasp-audio",
-- .data = (void *)MCASP_VERSION_3,
-+ .data = &omap2_mcasp_pdata,
- },
- { /* sentinel */ }
- };
-@@ -1035,20 +1057,13 @@ static struct snd_platform_data *davinci
- pdata = pdev->dev.platform_data;
- return pdata;
- } else if (match) {
-- pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
-- if (!pdata) {
-- ret = -ENOMEM;
-- goto nodata;
-- }
-+ pdata = (struct snd_platform_data *) match->data;
- } else {
- /* control shouldn't reach here. something is wrong */
- ret = -EINVAL;
- goto nodata;
- }
-
-- if (match->data)
-- pdata->version = (u8)((int)match->data);
--
- ret = of_property_read_u32(np, "op-mode", &val);
- if (ret >= 0)
- pdata->op_mode = val;
-@@ -1145,10 +1160,15 @@ static int davinci_mcasp_probe(struct pl
- return -EINVAL;
- }
-
-- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
- if (!mem) {
-- dev_err(&pdev->dev, "no mem resource?\n");
-- return -ENODEV;
-+ dev_warn(dev->dev,
-+ "\"mpu\" mem resource not found, using index 0\n");
-+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!mem) {
-+ dev_err(&pdev->dev, "no mem resource?\n");
-+ return -ENODEV;
-+ }
- }
-
- ioarea = devm_request_mem_region(&pdev->dev, mem->start,
-@@ -1182,13 +1202,16 @@ static int davinci_mcasp_probe(struct pl
- dev->rxnumevt = pdata->rxnumevt;
- dev->dev = &pdev->dev;
-
-+ dma = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
-+ if (!dma)
-+ dma = mem;
-+
- dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
- dma_data->asp_chan_q = pdata->asp_chan_q;
- dma_data->ram_chan_q = pdata->ram_chan_q;
- dma_data->sram_pool = pdata->sram_pool;
- dma_data->sram_size = pdata->sram_size_playback;
-- dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
-- mem->start);
-+ dma_data->dma_addr = dma->start + pdata->tx_dma_offset;
-
- /* first TX, then RX */
- res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-@@ -1205,8 +1228,7 @@ static int davinci_mcasp_probe(struct pl
- dma_data->ram_chan_q = pdata->ram_chan_q;
- dma_data->sram_pool = pdata->sram_pool;
- dma_data->sram_size = pdata->sram_size_capture;
-- dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
-- mem->start);
-+ dma_data->dma_addr = dma->start + pdata->rx_dma_offset;
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
- if (!res) {
-@@ -1266,4 +1288,3 @@ module_platform_driver(davinci_mcasp_dri
- MODULE_AUTHOR("Steve Chen");
- MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
- MODULE_LICENSE("GPL");
--
+++ /dev/null
-From ad5d3e5a1218a599ec02c81a3bd599acedeea00f Mon Sep 17 00:00:00 2001
-From: Jyri Sarha <jsarha@ti.com>
-Date: Tue, 17 Sep 2013 12:09:30 +0300
-Subject: [PATCH 214/752] ASoC: davinci-mcasp: Extract DMA channels directly
- from DT
-
-Extract DMA channels directly from DT as they can not be found from
-platform resources anymore. This is a work-around until davinci audio
-driver is updated to use dmaengine.
-
-Signed-off-by: Jyri Sarha <jsarha@ti.com>
----
- .../bindings/sound/davinci-mcasp-audio.txt | 5 +++
- include/linux/platform_data/davinci_asp.h | 2 +
- sound/soc/davinci/davinci-mcasp.c | 47 +++++++++++++-------
- 3 files changed, 39 insertions(+), 15 deletions(-)
-
---- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
-+++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
-@@ -18,6 +18,11 @@ Required properties:
- - serial-dir : A list of serializer pin mode. The list number should be equal
- to "num-serializer" parameter. Each entry is a number indication
- serializer pin direction. (0 - INACTIVE, 1 - TX, 2 - RX)
-+- dmas: two element list of DMA controller phandles and DMA request line
-+ ordered pairs.
-+- dma-names: identifier string for each DMA request line in the dmas property.
-+ These strings correspond 1:1 with the ordered pairs in dmas. The dma
-+ identifiers must be "rx" and "tx".
-
- Optional properties:
-
---- a/include/linux/platform_data/davinci_asp.h
-+++ b/include/linux/platform_data/davinci_asp.h
-@@ -84,6 +84,8 @@ struct snd_platform_data {
- u8 version;
- u8 txnumevt;
- u8 rxnumevt;
-+ int tx_dma_channel;
-+ int rx_dma_channel;
- };
-
- enum {
---- a/sound/soc/davinci/davinci-mcasp.c
-+++ b/sound/soc/davinci/davinci-mcasp.c
-@@ -1047,6 +1047,7 @@ static struct snd_platform_data *davinci
- struct snd_platform_data *pdata = NULL;
- const struct of_device_id *match =
- of_match_device(mcasp_dt_ids, &pdev->dev);
-+ struct of_phandle_args dma_spec;
-
- const u32 *of_serial_dir32;
- u8 *of_serial_dir;
-@@ -1109,6 +1110,28 @@ static struct snd_platform_data *davinci
- pdata->serial_dir = of_serial_dir;
- }
-
-+ ret = of_property_match_string(np, "dma-names", "tx");
-+ if (ret < 0)
-+ goto nodata;
-+
-+ ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
-+ &dma_spec);
-+ if (ret < 0)
-+ goto nodata;
-+
-+ pdata->tx_dma_channel = dma_spec.args[0];
-+
-+ ret = of_property_match_string(np, "dma-names", "rx");
-+ if (ret < 0)
-+ goto nodata;
-+
-+ ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
-+ &dma_spec);
-+ if (ret < 0)
-+ goto nodata;
-+
-+ pdata->rx_dma_channel = dma_spec.args[0];
-+
- ret = of_property_read_u32(np, "tx-num-evt", &val);
- if (ret >= 0)
- pdata->txnumevt = val;
-@@ -1139,7 +1162,7 @@ nodata:
- static int davinci_mcasp_probe(struct platform_device *pdev)
- {
- struct davinci_pcm_dma_params *dma_data;
-- struct resource *mem, *ioarea, *res;
-+ struct resource *mem, *ioarea, *res, *dma;
- struct snd_platform_data *pdata;
- struct davinci_audio_dev *dev;
- int ret;
-@@ -1213,15 +1236,11 @@ static int davinci_mcasp_probe(struct pl
- dma_data->sram_size = pdata->sram_size_playback;
- dma_data->dma_addr = dma->start + pdata->tx_dma_offset;
-
-- /* first TX, then RX */
- res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-- if (!res) {
-- dev_err(&pdev->dev, "no DMA resource\n");
-- ret = -ENODEV;
-- goto err_release_clk;
-- }
--
-- dma_data->channel = res->start;
-+ if (res)
-+ dma_data->channel = res->start;
-+ else
-+ dma_data->channel = pdata->tx_dma_channel;
-
- dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
- dma_data->asp_chan_q = pdata->asp_chan_q;
-@@ -1231,13 +1250,11 @@ static int davinci_mcasp_probe(struct pl
- dma_data->dma_addr = dma->start + pdata->rx_dma_offset;
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
-- if (!res) {
-- dev_err(&pdev->dev, "no DMA resource\n");
-- ret = -ENODEV;
-- goto err_release_clk;
-- }
-+ if (res)
-+ dma_data->channel = res->start;
-+ else
-+ dma_data->channel = pdata->rx_dma_channel;
-
-- dma_data->channel = res->start;
- dev_set_drvdata(&pdev->dev, dev);
- ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
- &davinci_mcasp_dai[pdata->op_mode], 1);
+++ /dev/null
-From 0ecb275625447180dd615256d0c324a0c0c6e76a Mon Sep 17 00:00:00 2001
-From: Jyri Sarha <jsarha@ti.com>
-Date: Thu, 19 Sep 2013 13:20:26 +0300
-Subject: [PATCH 215/752] ASoC: davinci-mcasp: Interrupts property to optional
- and add interrupt-names
-
-Makes interrupts property optional as the interrupts are not currently
-used by the driver and adds interrupt-names property to name listed
-interrupts. Currently know interrupt names are "tx" and "rx".
-
-Signed-off-by: Jyri Sarha <jsarha@ti.com>
----
- Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
-+++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
-@@ -11,7 +11,6 @@ Required properties:
- - reg-names : The mandatory reg-range must be named "mpu" and the optional DMA
- reg-range must be named "dma". For backward compatibility it is
- good to keep "mpu" first in the list.
--- interrupts : Interrupt number for McASP
- - op-mode : I2S/DIT ops mode.
- - tdm-slots : Slots for TDM operation.
- - num-serializer : Serializers used by McASP.
-@@ -31,6 +30,8 @@ Optional properties:
- - rx-num-evt : FIFO levels.
- - sram-size-playback : size of sram to be allocated during playback
- - sram-size-capture : size of sram to be allocated during capture
-+- interrupts : Interrupt numbers for McASP, currently not used by the driver
-+- interrupt-names : Known interrupt names are "tx" and "rx"
-
- Example:
-
-@@ -41,6 +42,7 @@ mcasp0: mcasp0@1d00000 {
- reg = <0x100000 0x3000>;
- reg-names "mpu";
- interrupts = <82 83>;
-+ interrupts-names = "tx", "rx";
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
- num-serializer = <16>;
+++ /dev/null
-From 8f3e1fa024017a6b3d7fd8c2a75ee6ff5e4127f8 Mon Sep 17 00:00:00 2001
-From: "Hebbar, Gururaja" <gururaja.hebbar@ti.com>
-Date: Wed, 1 Aug 2012 12:04:22 +0530
-Subject: [PATCH 216/752] ASoC: davinci: Add support for AM33xx SoC Audio
-
-AM33xx uses same McASP IP as the Davinci Platform. This patch updates
-Kconfig and makefile to enable build for McASP, PCM & Codec drivers.
-
-Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
-Signed-off-by: Darren Etheridge <detheridge@ti.com>
-Signed-off-by: Jyri Sarha <jsarha@ti.com>
----
- sound/soc/davinci/Kconfig | 18 +++++++++++++++---
- sound/soc/davinci/Makefile | 1 +
- 2 files changed, 16 insertions(+), 3 deletions(-)
-
---- a/sound/soc/davinci/Kconfig
-+++ b/sound/soc/davinci/Kconfig
-@@ -1,9 +1,10 @@
- config SND_DAVINCI_SOC
-- tristate "SoC Audio for the TI DAVINCI chip"
-- depends on ARCH_DAVINCI
-+ tristate "SoC Audio for the TI DAVINCI or AM33XX chip"
-+ depends on ARCH_DAVINCI || SOC_AM33XX
- help
-+ Platform driver for daVinci or AM33xx
- Say Y or M if you want to add support for codecs attached to
-- the DAVINCI AC97 or I2S interface. You will also need
-+ the DAVINCI AC97, I2S, or McASP interface. You will also need
- to select the audio interfaces to support below.
-
- config SND_DAVINCI_SOC_I2S
-@@ -15,6 +16,17 @@ config SND_DAVINCI_SOC_MCASP
- config SND_DAVINCI_SOC_VCIF
- tristate
-
-+config SND_AM33XX_SOC_EVM
-+ tristate "SoC Audio for the AM33XX chip based boards"
-+ depends on SND_DAVINCI_SOC && SOC_AM33XX
-+ select SND_SOC_TLV320AIC3X
-+ select SND_DAVINCI_SOC_MCASP
-+ help
-+ Say Y or M if you want to add support for SoC audio on AM33XX
-+ boards using McASP and TLV320AIC3X codec. For example AM335X-EVM,
-+ AM335X-EVMSK, and BeagelBone with AudioCape boards have this
-+ setup.
-+
- config SND_DAVINCI_SOC_EVM
- tristate "SoC Audio support for DaVinci DM6446, DM355 or DM365 EVM"
- depends on SND_DAVINCI_SOC
---- a/sound/soc/davinci/Makefile
-+++ b/sound/soc/davinci/Makefile
-@@ -13,6 +13,7 @@ obj-$(CONFIG_SND_DAVINCI_SOC_VCIF) += sn
- snd-soc-evm-objs := davinci-evm.o
-
- obj-$(CONFIG_SND_DAVINCI_SOC_EVM) += snd-soc-evm.o
-+obj-$(CONFIG_SND_AM33XX_SOC_EVM) += snd-soc-evm.o
- obj-$(CONFIG_SND_DM6467_SOC_EVM) += snd-soc-evm.o
- obj-$(CONFIG_SND_DA830_SOC_EVM) += snd-soc-evm.o
- obj-$(CONFIG_SND_DA850_SOC_EVM) += snd-soc-evm.o
+++ /dev/null
-From 2e8f45c820bc025bac3a5257478f16f73b38d54c Mon Sep 17 00:00:00 2001
-From: Jyri Sarha <jsarha@ti.com>
-Date: Wed, 11 Sep 2013 15:04:56 +0300
-Subject: [PATCH 217/752] ASoC: tlv320aic3x: Add regulators to DT bindings
- document
-
-Add regulator properties to tlv320aic3x DT bindings document.
-
-Signed-off-by: Jyri Sarha <jsarha@ti.com>
----
- Documentation/devicetree/bindings/sound/tlv320aic3x.txt | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
-+++ b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
-@@ -24,10 +24,17 @@ Optional properties:
- 3 - MICBIAS output is connected to AVDD,
- If this node is not mentioned or if the value is incorrect, then MicBias
- is powered down.
-+- AVDD-supply, IOVDD-supply, DRVDD-supply, DVDD-supply : power supplies for the
-+ device as covered in Documentation/devicetree/bindings/regulator/regulator.txt
-
- Example:
-
- tlv320aic3x: tlv320aic3x@1b {
- compatible = "ti,tlv320aic3x";
- reg = <0x1b>;
-+
-+ AVDD-supply = <®ulator>;
-+ IOVDD-supply = <®ulator>;
-+ DRVDD-supply = <®ulator>;
-+ DVDD-supply = <®ulator>;
- };
+++ /dev/null
-From 6afd5cb1f92a1965ffa3c0f304f95ab19b49fa84 Mon Sep 17 00:00:00 2001
-From: Jyri Sarha <jsarha@ti.com>
-Date: Thu, 12 Sep 2013 14:37:08 +0300
-Subject: [PATCH 218/752] ASoC: tlv320aic3x: Add codec pins to DT bindings
- document
-
-Add list of codec pins to tlv320aic3x DT bindings document.
-
-Signed-off-by: Jyri Sarha <jsarha@ti.com>
----
- .../devicetree/bindings/sound/tlv320aic3x.txt | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
-+++ b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
-@@ -27,6 +27,25 @@ Optional properties:
- - AVDD-supply, IOVDD-supply, DRVDD-supply, DVDD-supply : power supplies for the
- device as covered in Documentation/devicetree/bindings/regulator/regulator.txt
-
-+CODEC output pins:
-+ * LLOUT
-+ * RLOUT
-+ * MONO_LOUT
-+ * HPLOUT
-+ * HPROUT
-+ * HPLCOM
-+ * HPRCOM
-+
-+CODEC input pins:
-+ * MIC3L
-+ * MIC3R
-+ * LINE1L
-+ * LINE2L
-+ * LINE1R
-+ * LINE2R
-+
-+The pins can be used in referring sound node's audio-routing property.
-+
- Example:
-
- tlv320aic3x: tlv320aic3x@1b {
+++ /dev/null
-From a049ce751e60451b47fa744342db84db44883e57 Mon Sep 17 00:00:00 2001
-From: Pantelis Antoniou <panto@antoniou-consulting.com>
-Date: Thu, 10 Jan 2013 20:37:45 +0200
-Subject: [PATCH 219/752] ARM/dts: am33xx: Add mcasp0 and mcasp1 device tree
- entries
-
-Add missing mcasp entries in the am33xx.dtsi include file.
-
-Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
-Signed-off-by: Darren Etheridge <detheridge@ti.com>
-Signed-off-by: Jyri Sarha <jsarha@ti.com>
----
- arch/arm/boot/dts/am33xx.dtsi | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -726,5 +726,24 @@
- <&edma 5>;
- dma-names = "tx", "rx";
- };
-+
-+ mcasp0: mcasp@48038000 {
-+ compatible = "ti,omap2-mcasp-audio";
-+ ti,hwmods = "mcasp0";
-+ reg = <0x48038000 0x2000>;
-+ interrupts = <80 81>;
-+ interrupts-names = "tx", "rx";
-+ status = "disabled";
-+ };
-+
-+ mcasp1: mcasp@4803C000 {
-+ compatible = "ti,omap2-mcasp-audio";
-+ ti,hwmods = "mcasp1";
-+ reg = <0x4803C000 0x2000>;
-+ interrupts = <82 83>;
-+ interrupts-names = "tx", "rx";
-+ status = "disabled";
-+ };
-+
- };
- };
+++ /dev/null
-From 15ffa765da3f2427b506472baa72d0f3a90b6be5 Mon Sep 17 00:00:00 2001
-From: Jyri Sarha <jsarha@ti.com>
-Date: Thu, 5 Sep 2013 21:49:35 +0300
-Subject: [PATCH 220/752] ARM/dts: am33xx: mcasp: Add new dma register
- location to reg-property
-
-This patch adds an optional address range to reg property. The range
-describes the register location for DMA controller on am33xx. The both
-address ranges are named accordingly in the reg-names property.
-
-Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
-Signed-off-by: Darren Etheridge <detheridge@ti.com>
-Signed-off-by: Jyri Sarha <jsarha@ti.com>
----
- arch/arm/boot/dts/am33xx.dtsi | 14 ++++++++++++--
- 1 file changed, 12 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -730,19 +730,29 @@
- mcasp0: mcasp@48038000 {
- compatible = "ti,omap2-mcasp-audio";
- ti,hwmods = "mcasp0";
-- reg = <0x48038000 0x2000>;
-+ reg = <0x48038000 0x2000>,
-+ <0x46400000 0x400000>;
-+ reg-names = "mpu", "dma";
- interrupts = <80 81>;
- interrupts-names = "tx", "rx";
- status = "disabled";
-+ dmas = <&edma 8
-+ &edma 9>;
-+ dma-names = "tx", "rx";
- };
-
- mcasp1: mcasp@4803C000 {
- compatible = "ti,omap2-mcasp-audio";
- ti,hwmods = "mcasp1";
-- reg = <0x4803C000 0x2000>;
-+ reg = <0x4803C000 0x2000>,
-+ <0x46400000 0x400000>;
-+ reg-names = "mpu", "dma";
- interrupts = <82 83>;
- interrupts-names = "tx", "rx";
- status = "disabled";
-+ dmas = <&edma 10
-+ &edma 11>;
-+ dma-names = "tx", "rx";
- };
-
- };
+++ /dev/null
-From 2bf66a74b322deebc7c8bba11cab58c18b745608 Mon Sep 17 00:00:00 2001
-From: Darren Etheridge <detheridge@ti.com>
-Date: Wed, 31 Jul 2013 12:38:26 -0500
-Subject: [PATCH 221/752] ARM/dts: am335x-evm: Add audio support for
- am335x-evm.dts
-
-Adds sound, tlv320aic3x, mcasp1, and am335x_evm_audio_pin nodes.
-
-Signed-off-by: Darren Etheridge <detheridge@ti.com>
-Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
-Signed-off-by: Jyri Sarha <jsarha@ti.com>
----
- arch/arm/boot/dts/am335x-evm.dts | 56 ++++++++++++++++++++++++++++++++++++++
- 1 file changed, 56 insertions(+)
-
---- a/arch/arm/boot/dts/am335x-evm.dts
-+++ b/arch/arm/boot/dts/am335x-evm.dts
-@@ -149,6 +149,16 @@
- 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
- >;
- };
-+
-+ am335x_evm_audio_pins: am335x_evm_audio_pins {
-+ pinctrl-single,pins = <
-+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */
-+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */
-+ 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
-+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
-+ >;
-+ };
-+
- };
-
- ocp {
-@@ -244,6 +254,19 @@
- compatible = "ti,tmp275";
- reg = <0x48>;
- };
-+
-+ tlv320aic3x: tlv320aic3x@1b {
-+ compatible = "ti,tlv320aic3x";
-+ reg = <0x1b>;
-+ status = "okay";
-+
-+ /* Regulators */
-+ AVDD-supply = <&vaux2_reg>;
-+ IOVDD-supply = <&vaux2_reg>;
-+ DRVDD-supply = <&vaux2_reg>;
-+ DVDD-supply = <&vbat>;
-+ };
-+
- };
-
- elm: elm@48080000 {
-@@ -340,6 +363,20 @@
- };
- };
- };
-+
-+ sound {
-+ compatible = "ti,da830-evm-audio";
-+ ti,model = "DA830 EVM";
-+ ti,audio-codec = <&tlv320aic3x>;
-+ ti,mcasp-controller = <&mcasp1>;
-+ ti,codec-clock-rate = <12000000>;
-+ ti,audio-routing =
-+ "Headphone Jack", "HPLOUT",
-+ "Headphone Jack", "HPROUT",
-+ "LINE1L", "Line In",
-+ "LINE1R", "Line In";
-+ };
-+
- };
-
- vbat: fixedregulator@0 {
-@@ -407,6 +444,25 @@
-
- #include "tps65910.dtsi"
-
-+&mcasp1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&am335x_evm_audio_pins>;
-+
-+ status = "okay";
-+
-+ op-mode = <0>; /* MCASP_IIS_MODE */
-+ tdm-slots = <2>;
-+ num-serializer = <16>;
-+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
-+ 0 0 1 2
-+ 0 0 0 0
-+ 0 0 0 0
-+ 0 0 0 0
-+ >;
-+ tx-num-evt = <1>;
-+ rx-num-evt = <1>;
-+};
-+
- &tps {
- vcc1-supply = <&vbat>;
- vcc2-supply = <&vbat>;
+++ /dev/null
-From 76b54fecdd214b32f568b2f97102fc1ab5745fa1 Mon Sep 17 00:00:00 2001
-From: Peter Ujfalusi <peter.ujfalusi@ti.com>
-Date: Mon, 23 Sep 2013 10:34:06 +0300
-Subject: [PATCH 222/752] ARM/dts: am335x-evm: Remove blank lines
-
-Clean up the blank lines where they are not needed.
-
-Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
----
- arch/arm/boot/dts/am335x-evm.dts | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/arch/arm/boot/dts/am335x-evm.dts
-+++ b/arch/arm/boot/dts/am335x-evm.dts
-@@ -266,7 +266,6 @@
- DRVDD-supply = <&vaux2_reg>;
- DVDD-supply = <&vbat>;
- };
--
- };
-
- elm: elm@48080000 {
-@@ -376,7 +375,6 @@
- "LINE1L", "Line In",
- "LINE1R", "Line In";
- };
--
- };
-
- vbat: fixedregulator@0 {
+++ /dev/null
-From df3fbecdac2b46b7716c16c185cba357cc55d00a Mon Sep 17 00:00:00 2001
-From: Peter Ujfalusi <peter.ujfalusi@ti.com>
-Date: Mon, 23 Sep 2013 10:34:07 +0300
-Subject: [PATCH 223/752] ARM/dts: am335x-evm: Clarify the audio codec node
-
-The board have tlv320aic3106 codec. Use this name in the dts file instead
-of the generic ltv320aic3x.
-
-Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
----
- arch/arm/boot/dts/am335x-evm.dts | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/arm/boot/dts/am335x-evm.dts
-+++ b/arch/arm/boot/dts/am335x-evm.dts
-@@ -255,8 +255,8 @@
- reg = <0x48>;
- };
-
-- tlv320aic3x: tlv320aic3x@1b {
-- compatible = "ti,tlv320aic3x";
-+ tlv320aic3106: tlv320aic3106@1b {
-+ compatible = "ti,tlv320aic3106";
- reg = <0x1b>;
- status = "okay";
-
-@@ -366,7 +366,7 @@
- sound {
- compatible = "ti,da830-evm-audio";
- ti,model = "DA830 EVM";
-- ti,audio-codec = <&tlv320aic3x>;
-+ ti,audio-codec = <&tlv320aic3106>;
- ti,mcasp-controller = <&mcasp1>;
- ti,codec-clock-rate = <12000000>;
- ti,audio-routing =
+++ /dev/null
-From d4b7ebbadccb4632ad16f07a19cee57aa7b73cdb Mon Sep 17 00:00:00 2001
-From: Peter Ujfalusi <peter.ujfalusi@ti.com>
-Date: Mon, 23 Sep 2013 10:34:08 +0300
-Subject: [PATCH 224/752] ARM/dts: am335x-evm: Add unique name for the sound
- card
-
-Change the name of the sound card to 'AM335x-EVM' from 'DA830 EVM'.
-User space might need to differentiate between the boards when it comes to
-audio setup (mixer config, PCM lookup, etc).
-It is better to use unique name for different boards.
-
-Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
----
- arch/arm/boot/dts/am335x-evm.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/am335x-evm.dts
-+++ b/arch/arm/boot/dts/am335x-evm.dts
-@@ -365,7 +365,7 @@
-
- sound {
- compatible = "ti,da830-evm-audio";
-- ti,model = "DA830 EVM";
-+ ti,model = "AM335x-EVM";
- ti,audio-codec = <&tlv320aic3106>;
- ti,mcasp-controller = <&mcasp1>;
- ti,codec-clock-rate = <12000000>;
+++ /dev/null
-From d4c71e652f457077eac1ad83a9e32d3f11fc99b2 Mon Sep 17 00:00:00 2001
-From: Peter Ujfalusi <peter.ujfalusi@ti.com>
-Date: Mon, 23 Sep 2013 10:34:09 +0300
-Subject: [PATCH 225/752] ARM/dts: am335x-evmsk: Audio support
-
-AM335x EVM-SK have only support for audio playback (stereo jack on the
-board) via tlv320aic3106 codec connected to McASP1.
-Enable the support for audio playback on the board:
-- McASP1 configuration
-- tlv320aic3106 configuration
-- Machine driver.
-
-Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
----
- arch/arm/boot/dts/am335x-evmsk.dts | 51 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 51 insertions(+)
-
---- a/arch/arm/boot/dts/am335x-evmsk.dts
-+++ b/arch/arm/boot/dts/am335x-evmsk.dts
-@@ -158,6 +158,15 @@
- 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
- >;
- };
-+
-+ mcasp1_pins: mcasp1_pins {
-+ pinctrl-single,pins = <
-+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
-+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
-+ 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
-+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
-+ >;
-+ };
- };
-
- ocp {
-@@ -206,6 +215,18 @@
- st,max-limit-y = <550>;
- st,max-limit-z = <750>;
- };
-+
-+ tlv320aic3106: tlv320aic3106@1b {
-+ compatible = "ti,tlv320aic3106";
-+ reg = <0x1b>;
-+ status = "okay";
-+
-+ /* Regulators */
-+ AVDD-supply = <&vaux2_reg>;
-+ IOVDD-supply = <&vaux2_reg>;
-+ DRVDD-supply = <&vaux2_reg>;
-+ DVDD-supply = <&vbat>;
-+ };
- };
-
- musb: usb@47400000 {
-@@ -233,6 +254,17 @@
- pinctrl-0 = <&ecap2_pins>;
- };
- };
-+
-+ sound {
-+ compatible = "ti,da830-evm-audio";
-+ ti,model = "AM335x-EVMSK";
-+ ti,audio-codec = <&tlv320aic3106>;
-+ ti,mcasp-controller = <&mcasp1>;
-+ ti,codec-clock-rate = <24576000>;
-+ ti,audio-routing =
-+ "Headphone Jack", "HPLOUT",
-+ "Headphone Jack", "HPROUT";
-+ };
- };
-
- vbat: fixedregulator@0 {
-@@ -438,3 +470,22 @@
- &aes {
- status = "okay";
- };
-+
-+&mcasp1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mcasp1_pins>;
-+
-+ status = "okay";
-+
-+ op-mode = <0>; /* MCASP_IIS_MODE */
-+ tdm-slots = <2>;
-+ num-serializer = <16>;
-+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
-+ 0 0 1 2
-+ 0 0 0 0
-+ 0 0 0 0
-+ 0 0 0 0
-+ >;
-+ tx-num-evt = <1>;
-+ rx-num-evt = <1>;
-+};
+++ /dev/null
-From fdb8d3521ecae71865df66a84a1cbe13f7daa6f5 Mon Sep 17 00:00:00 2001
-From: Peter Ujfalusi <peter.ujfalusi@ti.com>
-Date: Mon, 23 Sep 2013 11:25:02 +0300
-Subject: [PATCH 226/752] ASoC: davinci: mcasp: Remove redundant
- num-serializer DT parameter
-
-The serial-dir array gives this information so there is no need to have the
-num-serializer property in DT description.
-Just ignore the property in the driver the DTS files can be updated
-separately without regression.
-Update the documentation at the same time for davinci-mcasp
-
-Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
----
- .../bindings/sound/davinci-mcasp-audio.txt | 8 +++----
- sound/soc/davinci/davinci-mcasp.c | 22 +++++---------------
- 2 files changed, 8 insertions(+), 22 deletions(-)
-
---- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
-+++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
-@@ -13,10 +13,9 @@ Required properties:
- good to keep "mpu" first in the list.
- - op-mode : I2S/DIT ops mode.
- - tdm-slots : Slots for TDM operation.
--- num-serializer : Serializers used by McASP.
--- serial-dir : A list of serializer pin mode. The list number should be equal
-- to "num-serializer" parameter. Each entry is a number indication
-- serializer pin direction. (0 - INACTIVE, 1 - TX, 2 - RX)
-+- serial-dir : A list of serializer configuration. Each entry is a number
-+ indication serializer pin direction.
-+ (0 - INACTIVE, 1 - TX, 2 - RX)
- - dmas: two element list of DMA controller phandles and DMA request line
- ordered pairs.
- - dma-names: identifier string for each DMA request line in the dmas property.
-@@ -45,7 +44,6 @@ mcasp0: mcasp0@1d00000 {
- interrupts-names = "tx", "rx";
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
-- num-serializer = <16>;
- serial-dir = <
- 0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */
- 0 0 0 0
---- a/sound/soc/davinci/davinci-mcasp.c
-+++ b/sound/soc/davinci/davinci-mcasp.c
-@@ -1050,7 +1050,6 @@ static struct snd_platform_data *davinci
- struct of_phandle_args dma_spec;
-
- const u32 *of_serial_dir32;
-- u8 *of_serial_dir;
- u32 val;
- int i, ret = 0;
-
-@@ -1081,32 +1080,21 @@ static struct snd_platform_data *davinci
- pdata->tdm_slots = val;
- }
-
-- ret = of_property_read_u32(np, "num-serializer", &val);
-- if (ret >= 0)
-- pdata->num_serializer = val;
--
- of_serial_dir32 = of_get_property(np, "serial-dir", &val);
- val /= sizeof(u32);
-- if (val != pdata->num_serializer) {
-- dev_err(&pdev->dev,
-- "num-serializer(%d) != serial-dir size(%d)\n",
-- pdata->num_serializer, val);
-- ret = -EINVAL;
-- goto nodata;
-- }
--
- if (of_serial_dir32) {
-- of_serial_dir = devm_kzalloc(&pdev->dev,
-- (sizeof(*of_serial_dir) * val),
-- GFP_KERNEL);
-+ u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
-+ (sizeof(*of_serial_dir) * val),
-+ GFP_KERNEL);
- if (!of_serial_dir) {
- ret = -ENOMEM;
- goto nodata;
- }
-
-- for (i = 0; i < pdata->num_serializer; i++)
-+ for (i = 0; i < val; i++)
- of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
-
-+ pdata->num_serializer = val;
- pdata->serial_dir = of_serial_dir;
- }
-
+++ /dev/null
-From 7fd70076a17c2a5b1b4bac0175a25e5d04075e43 Mon Sep 17 00:00:00 2001
-From: Peter Ujfalusi <peter.ujfalusi@ti.com>
-Date: Mon, 23 Sep 2013 11:25:03 +0300
-Subject: [PATCH 227/752] ARM/dts: am335x-evm: Remove num-serializer property
- for mcasp node
-
-The num-serializer property is redundant and the driver no longer needs it.
-
-Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
----
- arch/arm/boot/dts/am335x-evm.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/am335x-evm.dts
-+++ b/arch/arm/boot/dts/am335x-evm.dts
-@@ -450,7 +450,7 @@
-
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
-- num-serializer = <16>;
-+ /* 16 serializer */
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 0 0 1 2
- 0 0 0 0
+++ /dev/null
-From 97977a1534ef27247acc9549f5433ef288f208eb Mon Sep 17 00:00:00 2001
-From: Peter Ujfalusi <peter.ujfalusi@ti.com>
-Date: Mon, 23 Sep 2013 11:25:04 +0300
-Subject: [PATCH 228/752] ARM/dts: am335x-evmsk: Remove num-serializer
- property for mcasp node
-
-The num-serializer property is redundant and the driver no longer needs it.
-
-Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
----
- arch/arm/boot/dts/am335x-evmsk.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/am335x-evmsk.dts
-+++ b/arch/arm/boot/dts/am335x-evmsk.dts
-@@ -479,7 +479,7 @@
-
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
-- num-serializer = <16>;
-+ /* 16 serializer */
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 0 0 1 2
- 0 0 0 0
+++ /dev/null
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -678,6 +678,15 @@
- status = "disabled";
- };
-
-+ lcdc: lcdc@4830e000 {
-+ compatible = "ti,am33xx-tilcdc";
-+ reg = <0x4830e000 0x1000>;
-+ interrupt-parent = <&intc>;
-+ interrupts = <36>;
-+ ti,hwmods = "lcdc";
-+ status = "disabled";
-+ };
-+
- tscadc: tscadc@44e0d000 {
- compatible = "ti,am3359-tscadc";
- reg = <0x44e0d000 0x1000>;
+++ /dev/null
-From patchwork Thu Aug 29 23:27:51 2013
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [1/3] crypto: omap-des: Add omap-des driver for OMAP4/AM43xx
-From: Joel Fernandes <joelf@ti.com>
-X-Patchwork-Id: 2851675
-Message-Id: <1377818873-21174-2-git-send-email-joelf@ti.com>
-To: Herbert Xu <herbert@gondor.hengli.com.au>, "David S. Miller"
- <davem@davemloft.net>, Mark Greer <mgreer@animalcreek.com>, Tony Lindgren
- <tony@atomide.com>, Lokesh Vutla <lokeshvutla@ti.com>
-Cc: Joel Fernandes <joelf@ti.com>,
- Linux OMAP List <linux-omap@vger.kernel.org>,
- Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
- Linux ARM Kernel List <linux-arm-kernel@lists.infradead.org>,
- Linux Crypto Mailing List <linux-crypto@vger.kernel.org>
-Date: Thu, 29 Aug 2013 18:27:51 -0500
-
-Add omap-des driver with platform data for OMAP4. Support added for DES
-ECB and CBC modes.
-
-Where possible, code is reused from omap-aes driver with changes made for
-adjusting key size, block size, removing non-existent encryption modes
-and adding support for OMAP4 platform data and offsets.
-
-Tests have been conducted with the CRYPTO test manager, and functionality
-is verified at different page length alignments.
-
-Signed-off-by: Joel Fernandes <joelf@ti.com>
-
----
-drivers/crypto/omap-des.c | 1192 +++++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 1192 insertions(+)
- create mode 100644 drivers/crypto/omap-des.c
-
---- /dev/null
-+++ b/drivers/crypto/omap-des.c
-@@ -0,0 +1,1192 @@
-+/*
-+ * Cryptographic API.
-+ *
-+ * Support for OMAP DES and Triple DES HW acceleration.
-+ *
-+ * Copyright (c) 2012 Texas Instruments Incorporated
-+ * Author: Joel Fernandes <joelf@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ */
-+
-+#define pr_fmt(fmt) "%s: " fmt, __func__
-+
-+#ifdef DEBUG
-+#define prn(num) printk(#num "=%d\n", num)
-+#define prx(num) printk(#num "=%x\n", num)
-+#else
-+#define prn(num) do { } while (0)
-+#define prx(num) do { } while (0)
-+#endif
-+
-+#include <linux/err.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/errno.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/scatterlist.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dmaengine.h>
-+#include <linux/omap-dma.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/io.h>
-+#include <linux/crypto.h>
-+#include <linux/interrupt.h>
-+#include <crypto/scatterwalk.h>
-+#include <crypto/des.h>
-+
-+#define DST_MAXBURST 2
-+
-+#define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
-+
-+#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
-+
-+#define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
-+ ((x ^ 0x01) * 0x04))
-+
-+#define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
-+
-+#define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
-+#define DES_REG_CTRL_CBC (1 << 4)
-+#define DES_REG_CTRL_TDES (1 << 3)
-+#define DES_REG_CTRL_DIRECTION (1 << 2)
-+#define DES_REG_CTRL_INPUT_READY (1 << 1)
-+#define DES_REG_CTRL_OUTPUT_READY (1 << 0)
-+
-+#define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
-+
-+#define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
-+
-+#define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
-+
-+#define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
-+
-+#define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
-+#define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
-+#define DES_REG_IRQ_DATA_IN BIT(1)
-+#define DES_REG_IRQ_DATA_OUT BIT(2)
-+
-+#define FLAGS_MODE_MASK 0x000f
-+#define FLAGS_ENCRYPT BIT(0)
-+#define FLAGS_CBC BIT(1)
-+#define FLAGS_INIT BIT(4)
-+#define FLAGS_BUSY BIT(6)
-+
-+struct omap_des_ctx {
-+ struct omap_des_dev *dd;
-+
-+ int keylen;
-+ u32 key[DES_KEY_SIZE / sizeof(u32)];
-+ unsigned long flags;
-+};
-+
-+struct omap_des_reqctx {
-+ unsigned long mode;
-+};
-+
-+#define OMAP_DES_QUEUE_LENGTH 1
-+#define OMAP_DES_CACHE_SIZE 0
-+
-+struct omap_des_algs_info {
-+ struct crypto_alg *algs_list;
-+ unsigned int size;
-+ unsigned int registered;
-+};
-+
-+struct omap_des_pdata {
-+ struct omap_des_algs_info *algs_info;
-+ unsigned int algs_info_size;
-+
-+ void (*trigger)(struct omap_des_dev *dd, int length);
-+
-+ u32 key_ofs;
-+ u32 iv_ofs;
-+ u32 ctrl_ofs;
-+ u32 data_ofs;
-+ u32 rev_ofs;
-+ u32 mask_ofs;
-+ u32 irq_enable_ofs;
-+ u32 irq_status_ofs;
-+
-+ u32 dma_enable_in;
-+ u32 dma_enable_out;
-+ u32 dma_start;
-+
-+ u32 major_mask;
-+ u32 major_shift;
-+ u32 minor_mask;
-+ u32 minor_shift;
-+};
-+
-+struct omap_des_dev {
-+ struct list_head list;
-+ unsigned long phys_base;
-+ void __iomem *io_base;
-+ struct omap_des_ctx *ctx;
-+ struct device *dev;
-+ unsigned long flags;
-+ int err;
-+
-+ /* spinlock used for queues */
-+ spinlock_t lock;
-+ struct crypto_queue queue;
-+
-+ struct tasklet_struct done_task;
-+ struct tasklet_struct queue_task;
-+
-+ struct ablkcipher_request *req;
-+ /*
-+ * total is used by PIO mode for book keeping so introduce
-+ * variable total_save as need it to calc page_order
-+ */
-+ size_t total;
-+ size_t total_save;
-+
-+ struct scatterlist *in_sg;
-+ struct scatterlist *out_sg;
-+
-+ /* Buffers for copying for unaligned cases */
-+ struct scatterlist in_sgl;
-+ struct scatterlist out_sgl;
-+ struct scatterlist *orig_out;
-+ int sgs_copied;
-+
-+ struct scatter_walk in_walk;
-+ struct scatter_walk out_walk;
-+ int dma_in;
-+ struct dma_chan *dma_lch_in;
-+ int dma_out;
-+ struct dma_chan *dma_lch_out;
-+ int in_sg_len;
-+ int out_sg_len;
-+ int pio_only;
-+ const struct omap_des_pdata *pdata;
-+};
-+
-+/* keep registered devices data here */
-+static LIST_HEAD(dev_list);
-+static DEFINE_SPINLOCK(list_lock);
-+
-+#ifdef DEBUG
-+#define omap_des_read(dd, offset) \
-+ ({ \
-+ int _read_ret; \
-+ _read_ret = __raw_readl(dd->io_base + offset); \
-+ pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
-+ offset, _read_ret); \
-+ _read_ret; \
-+ })
-+#else
-+static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
-+{
-+ return __raw_readl(dd->io_base + offset);
-+}
-+#endif
-+
-+#ifdef DEBUG
-+#define omap_des_write(dd, offset, value) \
-+ do { \
-+ pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
-+ offset, value); \
-+ __raw_writel(value, dd->io_base + offset); \
-+ } while (0)
-+#else
-+static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
-+ u32 value)
-+{
-+ __raw_writel(value, dd->io_base + offset);
-+}
-+#endif
-+
-+static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
-+ u32 value, u32 mask)
-+{
-+ u32 val;
-+
-+ val = omap_des_read(dd, offset);
-+ val &= ~mask;
-+ val |= value;
-+ omap_des_write(dd, offset, val);
-+}
-+
-+static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
-+ u32 *value, int count)
-+{
-+ for (; count--; value++, offset += 4)
-+ omap_des_write(dd, offset, *value);
-+}
-+
-+static int omap_des_hw_init(struct omap_des_dev *dd)
-+{
-+ /*
-+ * clocks are enabled when request starts and disabled when finished.
-+ * It may be long delays between requests.
-+ * Device might go to off mode to save power.
-+ */
-+ pm_runtime_get_sync(dd->dev);
-+
-+ if (!(dd->flags & FLAGS_INIT)) {
-+ dd->flags |= FLAGS_INIT;
-+ dd->err = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static int omap_des_write_ctrl(struct omap_des_dev *dd)
-+{
-+ unsigned int key32;
-+ int i, err;
-+ u32 val = 0, mask = 0;
-+
-+ err = omap_des_hw_init(dd);
-+ if (err)
-+ return err;
-+
-+ key32 = dd->ctx->keylen / sizeof(u32);
-+
-+ /* it seems a key should always be set even if it has not changed */
-+ for (i = 0; i < key32; i++) {
-+ omap_des_write(dd, DES_REG_KEY(dd, i),
-+ __le32_to_cpu(dd->ctx->key[i]));
-+ }
-+
-+ if ((dd->flags & FLAGS_CBC) && dd->req->info)
-+ omap_des_write_n(dd, DES_REG_IV(dd, 0), dd->req->info, 2);
-+
-+ if (dd->flags & FLAGS_CBC)
-+ val |= DES_REG_CTRL_CBC;
-+ if (dd->flags & FLAGS_ENCRYPT)
-+ val |= DES_REG_CTRL_DIRECTION;
-+
-+ mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION;
-+
-+ omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
-+
-+ return 0;
-+}
-+
-+static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
-+{
-+ u32 mask, val;
-+
-+ omap_des_write(dd, DES_REG_LENGTH_N(0), length);
-+
-+ val = dd->pdata->dma_start;
-+
-+ if (dd->dma_lch_out != NULL)
-+ val |= dd->pdata->dma_enable_out;
-+ if (dd->dma_lch_in != NULL)
-+ val |= dd->pdata->dma_enable_in;
-+
-+ mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
-+ dd->pdata->dma_start;
-+
-+ omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
-+}
-+
-+static void omap_des_dma_stop(struct omap_des_dev *dd)
-+{
-+ u32 mask;
-+
-+ mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
-+ dd->pdata->dma_start;
-+
-+ omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
-+}
-+
-+static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
-+{
-+ struct omap_des_dev *dd = NULL, *tmp;
-+
-+ spin_lock_bh(&list_lock);
-+ if (!ctx->dd) {
-+ list_for_each_entry(tmp, &dev_list, list) {
-+ /* FIXME: take fist available des core */
-+ dd = tmp;
-+ break;
-+ }
-+ ctx->dd = dd;
-+ } else {
-+ /* already found before */
-+ dd = ctx->dd;
-+ }
-+ spin_unlock_bh(&list_lock);
-+
-+ return dd;
-+}
-+
-+static void omap_des_dma_out_callback(void *data)
-+{
-+ struct omap_des_dev *dd = data;
-+
-+ /* dma_lch_out - completed */
-+ tasklet_schedule(&dd->done_task);
-+}
-+
-+static int omap_des_dma_init(struct omap_des_dev *dd)
-+{
-+ int err = -ENOMEM;
-+ dma_cap_mask_t mask;
-+
-+ dd->dma_lch_out = NULL;
-+ dd->dma_lch_in = NULL;
-+
-+ dma_cap_zero(mask);
-+ dma_cap_set(DMA_SLAVE, mask);
-+
-+ dd->dma_lch_in = dma_request_slave_channel_compat(mask,
-+ omap_dma_filter_fn,
-+ &dd->dma_in,
-+ dd->dev, "rx");
-+ if (!dd->dma_lch_in) {
-+ dev_err(dd->dev, "Unable to request in DMA channel\n");
-+ goto err_dma_in;
-+ }
-+
-+ dd->dma_lch_out = dma_request_slave_channel_compat(mask,
-+ omap_dma_filter_fn,
-+ &dd->dma_out,
-+ dd->dev, "tx");
-+ if (!dd->dma_lch_out) {
-+ dev_err(dd->dev, "Unable to request out DMA channel\n");
-+ goto err_dma_out;
-+ }
-+
-+ return 0;
-+
-+err_dma_out:
-+ dma_release_channel(dd->dma_lch_in);
-+err_dma_in:
-+ if (err)
-+ pr_err("error: %d\n", err);
-+ return err;
-+}
-+
-+static void omap_des_dma_cleanup(struct omap_des_dev *dd)
-+{
-+ dma_release_channel(dd->dma_lch_out);
-+ dma_release_channel(dd->dma_lch_in);
-+}
-+
-+static void sg_copy_buf(void *buf, struct scatterlist *sg,
-+ unsigned int start, unsigned int nbytes, int out)
-+{
-+ struct scatter_walk walk;
-+
-+ if (!nbytes)
-+ return;
-+
-+ scatterwalk_start(&walk, sg);
-+ scatterwalk_advance(&walk, start);
-+ scatterwalk_copychunks(buf, &walk, nbytes, out);
-+ scatterwalk_done(&walk, out, 0);
-+}
-+
-+static int omap_des_crypt_dma(struct crypto_tfm *tfm,
-+ struct scatterlist *in_sg, struct scatterlist *out_sg,
-+ int in_sg_len, int out_sg_len)
-+{
-+ struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
-+ struct omap_des_dev *dd = ctx->dd;
-+ struct dma_async_tx_descriptor *tx_in, *tx_out;
-+ struct dma_slave_config cfg;
-+ int ret;
-+
-+ if (dd->pio_only) {
-+ scatterwalk_start(&dd->in_walk, dd->in_sg);
-+ scatterwalk_start(&dd->out_walk, dd->out_sg);
-+
-+ /* Enable DATAIN interrupt and let it take
-+ care of the rest */
-+ omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
-+ return 0;
-+ }
-+
-+ dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
-+
-+ memset(&cfg, 0, sizeof(cfg));
-+
-+ cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
-+ cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
-+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ cfg.src_maxburst = DST_MAXBURST;
-+ cfg.dst_maxburst = DST_MAXBURST;
-+
-+ /* IN */
-+ ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
-+ if (ret) {
-+ dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
-+ DMA_MEM_TO_DEV,
-+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-+ if (!tx_in) {
-+ dev_err(dd->dev, "IN prep_slave_sg() failed\n");
-+ return -EINVAL;
-+ }
-+
-+ /* No callback necessary */
-+ tx_in->callback_param = dd;
-+
-+ /* OUT */
-+ ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
-+ if (ret) {
-+ dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
-+ DMA_DEV_TO_MEM,
-+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-+ if (!tx_out) {
-+ dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
-+ return -EINVAL;
-+ }
-+
-+ tx_out->callback = omap_des_dma_out_callback;
-+ tx_out->callback_param = dd;
-+
-+ dmaengine_submit(tx_in);
-+ dmaengine_submit(tx_out);
-+
-+ dma_async_issue_pending(dd->dma_lch_in);
-+ dma_async_issue_pending(dd->dma_lch_out);
-+
-+ /* start DMA */
-+ dd->pdata->trigger(dd, dd->total);
-+
-+ return 0;
-+}
-+
-+static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
-+{
-+ struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
-+ crypto_ablkcipher_reqtfm(dd->req));
-+ int err;
-+
-+ pr_debug("total: %d\n", dd->total);
-+
-+ if (!dd->pio_only) {
-+ err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
-+ DMA_TO_DEVICE);
-+ if (!err) {
-+ dev_err(dd->dev, "dma_map_sg() error\n");
-+ return -EINVAL;
-+ }
-+
-+ err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
-+ DMA_FROM_DEVICE);
-+ if (!err) {
-+ dev_err(dd->dev, "dma_map_sg() error\n");
-+ return -EINVAL;
-+ }
-+ }
-+
-+ err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
-+ dd->out_sg_len);
-+ if (err && !dd->pio_only) {
-+ dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
-+ dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
-+ DMA_FROM_DEVICE);
-+ }
-+
-+ return err;
-+}
-+
-+static void omap_des_finish_req(struct omap_des_dev *dd, int err)
-+{
-+ struct ablkcipher_request *req = dd->req;
-+
-+ pr_debug("err: %d\n", err);
-+
-+ pm_runtime_put(dd->dev);
-+ dd->flags &= ~FLAGS_BUSY;
-+
-+ req->base.complete(&req->base, err);
-+}
-+
-+static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
-+{
-+ int err = 0;
-+
-+ pr_debug("total: %d\n", dd->total);
-+
-+ omap_des_dma_stop(dd);
-+
-+ dmaengine_terminate_all(dd->dma_lch_in);
-+ dmaengine_terminate_all(dd->dma_lch_out);
-+
-+ dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
-+ dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, DMA_FROM_DEVICE);
-+
-+ return err;
-+}
-+
-+int omap_des_copy_needed(struct scatterlist *sg)
-+{
-+ while (sg) {
-+ if (!IS_ALIGNED(sg->offset, 4))
-+ return -1;
-+ if (!IS_ALIGNED(sg->length, DES_BLOCK_SIZE))
-+ return -1;
-+ sg = sg_next(sg);
-+ }
-+ return 0;
-+}
-+
-+int omap_des_copy_sgs(struct omap_des_dev *dd)
-+{
-+ void *buf_in, *buf_out;
-+ int pages;
-+
-+ pages = dd->total >> PAGE_SHIFT;
-+
-+ if (dd->total & (PAGE_SIZE-1))
-+ pages++;
-+
-+ BUG_ON(!pages);
-+
-+ buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages);
-+ buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages);
-+
-+ if (!buf_in || !buf_out) {
-+ pr_err("Couldn't allocated pages for unaligned cases.\n");
-+ return -1;
-+ }
-+
-+ dd->orig_out = dd->out_sg;
-+
-+ sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0);
-+
-+ sg_init_table(&dd->in_sgl, 1);
-+ sg_set_buf(&dd->in_sgl, buf_in, dd->total);
-+ dd->in_sg = &dd->in_sgl;
-+
-+ sg_init_table(&dd->out_sgl, 1);
-+ sg_set_buf(&dd->out_sgl, buf_out, dd->total);
-+ dd->out_sg = &dd->out_sgl;
-+
-+ return 0;
-+}
-+
-+static int omap_des_handle_queue(struct omap_des_dev *dd,
-+ struct ablkcipher_request *req)
-+{
-+ struct crypto_async_request *async_req, *backlog;
-+ struct omap_des_ctx *ctx;
-+ struct omap_des_reqctx *rctx;
-+ unsigned long flags;
-+ int err, ret = 0;
-+
-+ spin_lock_irqsave(&dd->lock, flags);
-+ if (req)
-+ ret = ablkcipher_enqueue_request(&dd->queue, req);
-+ if (dd->flags & FLAGS_BUSY) {
-+ spin_unlock_irqrestore(&dd->lock, flags);
-+ return ret;
-+ }
-+ backlog = crypto_get_backlog(&dd->queue);
-+ async_req = crypto_dequeue_request(&dd->queue);
-+ if (async_req)
-+ dd->flags |= FLAGS_BUSY;
-+ spin_unlock_irqrestore(&dd->lock, flags);
-+
-+ if (!async_req)
-+ return ret;
-+
-+ if (backlog)
-+ backlog->complete(backlog, -EINPROGRESS);
-+
-+ req = ablkcipher_request_cast(async_req);
-+
-+ /* assign new request to device */
-+ dd->req = req;
-+ dd->total = req->nbytes;
-+ dd->total_save = req->nbytes;
-+ dd->in_sg = req->src;
-+ dd->out_sg = req->dst;
-+
-+ if (omap_des_copy_needed(dd->in_sg) ||
-+ omap_des_copy_needed(dd->out_sg)) {
-+ if (omap_des_copy_sgs(dd))
-+ pr_err("Failed to copy SGs for unaligned cases\n");
-+ dd->sgs_copied = 1;
-+ } else {
-+ dd->sgs_copied = 0;
-+ }
-+
-+ dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, dd->total);
-+ dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, dd->total);
-+ BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0);
-+
-+ rctx = ablkcipher_request_ctx(req);
-+ ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
-+ rctx->mode &= FLAGS_MODE_MASK;
-+ dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
-+
-+ dd->ctx = ctx;
-+ ctx->dd = dd;
-+
-+ err = omap_des_write_ctrl(dd);
-+ if (!err)
-+ err = omap_des_crypt_dma_start(dd);
-+ if (err) {
-+ /* des_task will not finish it, so do it here */
-+ omap_des_finish_req(dd, err);
-+ tasklet_schedule(&dd->queue_task);
-+ }
-+
-+ return ret; /* return ret, which is enqueue return value */
-+}
-+
-+static void omap_des_done_task(unsigned long data)
-+{
-+ struct omap_des_dev *dd = (struct omap_des_dev *)data;
-+ void *buf_in, *buf_out;
-+ int pages;
-+
-+ pr_debug("enter done_task\n");
-+
-+ if (!dd->pio_only) {
-+ dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
-+ DMA_FROM_DEVICE);
-+ dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
-+ dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
-+ DMA_FROM_DEVICE);
-+ omap_des_crypt_dma_stop(dd);
-+ }
-+
-+ if (dd->sgs_copied) {
-+ buf_in = sg_virt(&dd->in_sgl);
-+ buf_out = sg_virt(&dd->out_sgl);
-+
-+ sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1);
-+
-+ pages = get_order(dd->total_save);
-+ free_pages((unsigned long)buf_in, pages);
-+ free_pages((unsigned long)buf_out, pages);
-+ }
-+
-+ omap_des_finish_req(dd, 0);
-+ omap_des_handle_queue(dd, NULL);
-+
-+ pr_debug("exit\n");
-+}
-+
-+static void omap_des_queue_task(unsigned long data)
-+{
-+ struct omap_des_dev *dd = (struct omap_des_dev *)data;
-+
-+ omap_des_handle_queue(dd, NULL);
-+}
-+
-+static int omap_des_crypt(struct ablkcipher_request *req, unsigned long mode)
-+{
-+ struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
-+ crypto_ablkcipher_reqtfm(req));
-+ struct omap_des_reqctx *rctx = ablkcipher_request_ctx(req);
-+ struct omap_des_dev *dd;
-+
-+ pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
-+ !!(mode & FLAGS_ENCRYPT),
-+ !!(mode & FLAGS_CBC));
-+
-+ if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) {
-+ pr_err("request size is not exact amount of DES blocks\n");
-+ return -EINVAL;
-+ }
-+
-+ dd = omap_des_find_dev(ctx);
-+ if (!dd)
-+ return -ENODEV;
-+
-+ rctx->mode = mode;
-+
-+ return omap_des_handle_queue(dd, req);
-+}
-+
-+/* ********************** ALG API ************************************ */
-+
-+static int omap_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
-+ unsigned int keylen)
-+{
-+ struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(tfm);
-+
-+ if (keylen != DES_KEY_SIZE)
-+ return -EINVAL;
-+
-+ pr_debug("enter, keylen: %d\n", keylen);
-+
-+ memcpy(ctx->key, key, keylen);
-+ ctx->keylen = keylen;
-+
-+ return 0;
-+}
-+
-+static int omap_des_ecb_encrypt(struct ablkcipher_request *req)
-+{
-+ return omap_des_crypt(req, FLAGS_ENCRYPT);
-+}
-+
-+static int omap_des_ecb_decrypt(struct ablkcipher_request *req)
-+{
-+ return omap_des_crypt(req, 0);
-+}
-+
-+static int omap_des_cbc_encrypt(struct ablkcipher_request *req)
-+{
-+ return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
-+}
-+
-+static int omap_des_cbc_decrypt(struct ablkcipher_request *req)
-+{
-+ return omap_des_crypt(req, FLAGS_CBC);
-+}
-+
-+static int omap_des_cra_init(struct crypto_tfm *tfm)
-+{
-+ pr_debug("enter\n");
-+
-+ tfm->crt_ablkcipher.reqsize = sizeof(struct omap_des_reqctx);
-+
-+ return 0;
-+}
-+
-+static void omap_des_cra_exit(struct crypto_tfm *tfm)
-+{
-+ pr_debug("enter\n");
-+}
-+
-+/* ********************** ALGS ************************************ */
-+
-+static struct crypto_alg algs_ecb_cbc[] = {
-+{
-+ .cra_name = "ecb(des)",
-+ .cra_driver_name = "ecb-des-omap",
-+ .cra_priority = 100,
-+ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY |
-+ CRYPTO_ALG_ASYNC,
-+ .cra_blocksize = DES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct omap_des_ctx),
-+ .cra_alignmask = 0,
-+ .cra_type = &crypto_ablkcipher_type,
-+ .cra_module = THIS_MODULE,
-+ .cra_init = omap_des_cra_init,
-+ .cra_exit = omap_des_cra_exit,
-+ .cra_u.ablkcipher = {
-+ .min_keysize = DES_KEY_SIZE,
-+ .max_keysize = DES_KEY_SIZE,
-+ .setkey = omap_des_setkey,
-+ .encrypt = omap_des_ecb_encrypt,
-+ .decrypt = omap_des_ecb_decrypt,
-+ }
-+},
-+{
-+ .cra_name = "cbc(des)",
-+ .cra_driver_name = "cbc-des-omap",
-+ .cra_priority = 100,
-+ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY |
-+ CRYPTO_ALG_ASYNC,
-+ .cra_blocksize = DES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct omap_des_ctx),
-+ .cra_alignmask = 0,
-+ .cra_type = &crypto_ablkcipher_type,
-+ .cra_module = THIS_MODULE,
-+ .cra_init = omap_des_cra_init,
-+ .cra_exit = omap_des_cra_exit,
-+ .cra_u.ablkcipher = {
-+ .min_keysize = DES_KEY_SIZE,
-+ .max_keysize = DES_KEY_SIZE,
-+ .ivsize = DES_BLOCK_SIZE,
-+ .setkey = omap_des_setkey,
-+ .encrypt = omap_des_cbc_encrypt,
-+ .decrypt = omap_des_cbc_decrypt,
-+ }
-+}
-+};
-+
-+static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
-+ {
-+ .algs_list = algs_ecb_cbc,
-+ .size = ARRAY_SIZE(algs_ecb_cbc),
-+ },
-+};
-+
-+#ifdef CONFIG_OF
-+static const struct omap_des_pdata omap_des_pdata_omap4 = {
-+ .algs_info = omap_des_algs_info_ecb_cbc,
-+ .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
-+ .trigger = omap_des_dma_trigger_omap4,
-+ .key_ofs = 0x14,
-+ .iv_ofs = 0x18,
-+ .ctrl_ofs = 0x20,
-+ .data_ofs = 0x28,
-+ .rev_ofs = 0x30,
-+ .mask_ofs = 0x34,
-+ .irq_status_ofs = 0x3c,
-+ .irq_enable_ofs = 0x40,
-+ .dma_enable_in = BIT(5),
-+ .dma_enable_out = BIT(6),
-+ .major_mask = 0x0700,
-+ .major_shift = 8,
-+ .minor_mask = 0x003f,
-+ .minor_shift = 0,
-+};
-+
-+static irqreturn_t omap_des_irq(int irq, void *dev_id)
-+{
-+ struct omap_des_dev *dd = dev_id;
-+ u32 status, i;
-+ u32 *src, *dst;
-+
-+ status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
-+ if (status & DES_REG_IRQ_DATA_IN) {
-+ omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
-+
-+ BUG_ON(!dd->in_sg);
-+
-+ BUG_ON(_calc_walked(in) > dd->in_sg->length);
-+
-+ src = sg_virt(dd->in_sg) + _calc_walked(in);
-+
-+ for (i = 0; i < DES_BLOCK_WORDS; i++) {
-+ omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
-+
-+ scatterwalk_advance(&dd->in_walk, 4);
-+ if (dd->in_sg->length == _calc_walked(in)) {
-+ dd->in_sg = scatterwalk_sg_next(dd->in_sg);
-+ if (dd->in_sg) {
-+ scatterwalk_start(&dd->in_walk,
-+ dd->in_sg);
-+ src = sg_virt(dd->in_sg) +
-+ _calc_walked(in);
-+ }
-+ } else {
-+ src++;
-+ }
-+ }
-+
-+ /* Clear IRQ status */
-+ status &= ~DES_REG_IRQ_DATA_IN;
-+ omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
-+
-+ /* Enable DATA_OUT interrupt */
-+ omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
-+
-+ } else if (status & DES_REG_IRQ_DATA_OUT) {
-+ omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
-+
-+ BUG_ON(!dd->out_sg);
-+
-+ BUG_ON(_calc_walked(out) > dd->out_sg->length);
-+
-+ dst = sg_virt(dd->out_sg) + _calc_walked(out);
-+
-+ for (i = 0; i < DES_BLOCK_WORDS; i++) {
-+ *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
-+ scatterwalk_advance(&dd->out_walk, 4);
-+ if (dd->out_sg->length == _calc_walked(out)) {
-+ dd->out_sg = scatterwalk_sg_next(dd->out_sg);
-+ if (dd->out_sg) {
-+ scatterwalk_start(&dd->out_walk,
-+ dd->out_sg);
-+ dst = sg_virt(dd->out_sg) +
-+ _calc_walked(out);
-+ }
-+ } else {
-+ dst++;
-+ }
-+ }
-+
-+ dd->total -= DES_BLOCK_SIZE;
-+
-+ BUG_ON(dd->total < 0);
-+
-+ /* Clear IRQ status */
-+ status &= ~DES_REG_IRQ_DATA_OUT;
-+ omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
-+
-+ if (!dd->total)
-+ /* All bytes read! */
-+ tasklet_schedule(&dd->done_task);
-+ else
-+ /* Enable DATA_IN interrupt for next block */
-+ omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static const struct of_device_id omap_des_of_match[] = {
-+ {
-+ .compatible = "ti,omap4-des",
-+ .data = &omap_des_pdata_omap4,
-+ },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, omap_des_of_match);
-+
-+static int omap_des_get_res_of(struct omap_des_dev *dd,
-+ struct device *dev, struct resource *res)
-+{
-+ struct device_node *node = dev->of_node;
-+ const struct of_device_id *match;
-+ int err = 0;
-+
-+ match = of_match_device(of_match_ptr(omap_des_of_match), dev);
-+ if (!match) {
-+ dev_err(dev, "no compatible OF match\n");
-+ err = -EINVAL;
-+ goto err;
-+ }
-+
-+ err = of_address_to_resource(node, 0, res);
-+ if (err < 0) {
-+ dev_err(dev, "can't translate OF node address\n");
-+ err = -EINVAL;
-+ goto err;
-+ }
-+
-+ dd->dma_out = -1; /* Dummy value that's unused */
-+ dd->dma_in = -1; /* Dummy value that's unused */
-+
-+ dd->pdata = match->data;
-+
-+err:
-+ return err;
-+}
-+#else
-+static const struct of_device_id omap_des_of_match[] = {
-+ {},
-+};
-+
-+static int omap_des_get_res_of(struct omap_des_dev *dd,
-+ struct device *dev, struct resource *res)
-+{
-+ return -EINVAL;
-+}
-+#endif
-+
-+static int omap_des_get_res_pdev(struct omap_des_dev *dd,
-+ struct platform_device *pdev, struct resource *res)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct resource *r;
-+ int err = 0;
-+
-+ /* Get the base address */
-+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!r) {
-+ dev_err(dev, "no MEM resource info\n");
-+ err = -ENODEV;
-+ goto err;
-+ }
-+ memcpy(res, r, sizeof(*res));
-+
-+ /* Get the DMA out channel */
-+ r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-+ if (!r) {
-+ dev_err(dev, "no DMA out resource info\n");
-+ err = -ENODEV;
-+ goto err;
-+ }
-+ dd->dma_out = r->start;
-+
-+ /* Get the DMA in channel */
-+ r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
-+ if (!r) {
-+ dev_err(dev, "no DMA in resource info\n");
-+ err = -ENODEV;
-+ goto err;
-+ }
-+ dd->dma_in = r->start;
-+
-+ /* non-DT devices get pdata from pdev */
-+ dd->pdata = pdev->dev.platform_data;
-+
-+err:
-+ return err;
-+}
-+
-+static int omap_des_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct omap_des_dev *dd;
-+ struct crypto_alg *algp;
-+ struct resource res;
-+ int err = -ENOMEM, i, j, irq = -1;
-+ u32 reg;
-+
-+ dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
-+ if (dd == NULL) {
-+ dev_err(dev, "unable to alloc data struct.\n");
-+ goto err_data;
-+ }
-+ dd->dev = dev;
-+ platform_set_drvdata(pdev, dd);
-+
-+ spin_lock_init(&dd->lock);
-+ crypto_init_queue(&dd->queue, OMAP_DES_QUEUE_LENGTH);
-+
-+ err = (dev->of_node) ? omap_des_get_res_of(dd, dev, &res) :
-+ omap_des_get_res_pdev(dd, pdev, &res);
-+ if (err)
-+ goto err_res;
-+
-+ dd->io_base = devm_request_and_ioremap(dev, &res);
-+ if (!dd->io_base) {
-+ dev_err(dev, "can't ioremap\n");
-+ err = -ENOMEM;
-+ goto err_res;
-+ }
-+ dd->phys_base = res.start;
-+
-+ pm_runtime_enable(dev);
-+ pm_runtime_get_sync(dev);
-+
-+ omap_des_dma_stop(dd);
-+
-+ reg = omap_des_read(dd, DES_REG_REV(dd));
-+
-+ pm_runtime_put_sync(dev);
-+
-+ dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
-+ (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
-+ (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
-+
-+ tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
-+ tasklet_init(&dd->queue_task, omap_des_queue_task, (unsigned long)dd);
-+
-+ err = omap_des_dma_init(dd);
-+ if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
-+ dd->pio_only = 1;
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0) {
-+ dev_err(dev, "can't get IRQ resource\n");
-+ goto err_irq;
-+ }
-+
-+ err = devm_request_irq(dev, irq, omap_des_irq, 0,
-+ dev_name(dev), dd);
-+ if (err) {
-+ dev_err(dev, "Unable to grab omap-des IRQ\n");
-+ goto err_irq;
-+ }
-+ }
-+
-+
-+ INIT_LIST_HEAD(&dd->list);
-+ spin_lock(&list_lock);
-+ list_add_tail(&dd->list, &dev_list);
-+ spin_unlock(&list_lock);
-+
-+ for (i = 0; i < dd->pdata->algs_info_size; i++) {
-+ for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
-+ algp = &dd->pdata->algs_info[i].algs_list[j];
-+
-+ pr_debug("reg alg: %s\n", algp->cra_name);
-+ INIT_LIST_HEAD(&algp->cra_list);
-+
-+ err = crypto_register_alg(algp);
-+ if (err)
-+ goto err_algs;
-+
-+ dd->pdata->algs_info[i].registered++;
-+ }
-+ }
-+
-+ return 0;
-+err_algs:
-+ for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
-+ for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
-+ crypto_unregister_alg(
-+ &dd->pdata->algs_info[i].algs_list[j]);
-+ if (!dd->pio_only)
-+ omap_des_dma_cleanup(dd);
-+err_irq:
-+ tasklet_kill(&dd->done_task);
-+ tasklet_kill(&dd->queue_task);
-+ pm_runtime_disable(dev);
-+err_res:
-+ dd = NULL;
-+err_data:
-+ dev_err(dev, "initialization failed.\n");
-+ return err;
-+}
-+
-+static int omap_des_remove(struct platform_device *pdev)
-+{
-+ struct omap_des_dev *dd = platform_get_drvdata(pdev);
-+ int i, j;
-+
-+ if (!dd)
-+ return -ENODEV;
-+
-+ spin_lock(&list_lock);
-+ list_del(&dd->list);
-+ spin_unlock(&list_lock);
-+
-+ for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
-+ for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
-+ crypto_unregister_alg(
-+ &dd->pdata->algs_info[i].algs_list[j]);
-+
-+ tasklet_kill(&dd->done_task);
-+ tasklet_kill(&dd->queue_task);
-+ omap_des_dma_cleanup(dd);
-+ pm_runtime_disable(dd->dev);
-+ dd = NULL;
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_PM_SLEEP
-+static int omap_des_suspend(struct device *dev)
-+{
-+ pm_runtime_put_sync(dev);
-+ return 0;
-+}
-+
-+static int omap_des_resume(struct device *dev)
-+{
-+ pm_runtime_get_sync(dev);
-+ return 0;
-+}
-+#endif
-+
-+static const struct dev_pm_ops omap_des_pm_ops = {
-+ SET_SYSTEM_SLEEP_PM_OPS(omap_des_suspend, omap_des_resume)
-+};
-+
-+static struct platform_driver omap_des_driver = {
-+ .probe = omap_des_probe,
-+ .remove = omap_des_remove,
-+ .driver = {
-+ .name = "omap-des",
-+ .owner = THIS_MODULE,
-+ .pm = &omap_des_pm_ops,
-+ .of_match_table = omap_des_of_match,
-+ },
-+};
-+
-+module_platform_driver(omap_des_driver);
-+
-+MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");
+++ /dev/null
-From patchwork Thu Aug 29 23:27:52 2013
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [2/3] crypto: omap-des: Add config and build options
-From: Joel Fernandes <joelf@ti.com>
-X-Patchwork-Id: 2851671
-Message-Id: <1377818873-21174-3-git-send-email-joelf@ti.com>
-To: Herbert Xu <herbert@gondor.hengli.com.au>, "David S. Miller"
- <davem@davemloft.net>, Mark Greer <mgreer@animalcreek.com>, Tony Lindgren
- <tony@atomide.com>, Lokesh Vutla <lokeshvutla@ti.com>
-Cc: Joel Fernandes <joelf@ti.com>,
- Linux OMAP List <linux-omap@vger.kernel.org>,
- Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
- Linux ARM Kernel List <linux-arm-kernel@lists.infradead.org>,
- Linux Crypto Mailing List <linux-crypto@vger.kernel.org>
-Date: Thu, 29 Aug 2013 18:27:52 -0500
-
-Add config and build options for the newly added omap-des driver.
-
-Signed-off-by: Joel Fernandes <joelf@ti.com>
-
----
-drivers/crypto/Kconfig | 11 +++++++++++
- drivers/crypto/Makefile | 1 +
- 2 files changed, 12 insertions(+)
-
---- a/drivers/crypto/Kconfig
-+++ b/drivers/crypto/Kconfig
-@@ -263,6 +263,17 @@ config CRYPTO_DEV_OMAP_AES
- OMAP processors have AES module accelerator. Select this if you
- want to use the OMAP module for AES algorithms.
-
-+config CRYPTO_DEV_OMAP_DES
-+ tristate "Support for OMAP DES3DES hw engine"
-+ depends on ARCH_OMAP2PLUS
-+ select CRYPTO_DES
-+ select CRYPTO_BLKCIPHER2
-+ help
-+ OMAP processors have DES/3DES module accelerator. Select this if you
-+ want to use the OMAP module for DES and 3DES algorithms. Currently
-+ the ECB and CBC modes of operation supported by the driver. Also
-+ accesses made on unaligned boundaries are also supported.
-+
- config CRYPTO_DEV_PICOXCELL
- tristate "Support for picoXcell IPSEC and Layer2 crypto engines"
- depends on ARCH_PICOXCELL && HAVE_CLK
---- a/drivers/crypto/Makefile
-+++ b/drivers/crypto/Makefile
-@@ -11,6 +11,7 @@ obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4x
- obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
- obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o
- obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
-+obj-$(CONFIG_CRYPTO_DEV_OMAP_DES) += omap-des.o
- obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
- obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
- obj-$(CONFIG_CRYPTO_DEV_DCP) += dcp.o
+++ /dev/null
-From patchwork Thu Aug 29 23:27:53 2013
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [3/3] crypto: omap-des: Add triple DES (des3_ede) support to driver
-From: Joel Fernandes <joelf@ti.com>
-X-Patchwork-Id: 2851679
-Message-Id: <1377818873-21174-4-git-send-email-joelf@ti.com>
-To: Herbert Xu <herbert@gondor.hengli.com.au>, "David S. Miller"
- <davem@davemloft.net>, Mark Greer <mgreer@animalcreek.com>, Tony Lindgren
- <tony@atomide.com>, Lokesh Vutla <lokeshvutla@ti.com>
-Cc: Joel Fernandes <joelf@ti.com>,
- Linux OMAP List <linux-omap@vger.kernel.org>,
- Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
- Linux ARM Kernel List <linux-arm-kernel@lists.infradead.org>,
- Linux Crypto Mailing List <linux-crypto@vger.kernel.org>
-Date: Thu, 29 Aug 2013 18:27:53 -0500
-
-OMAP DES module supports 3DES operation where 3 64-bit keys are used to
-perform a DES encrypt-decrypt-encrypt (ede) operation on a buffer.
-
-Signed-off-by: Joel Fernandes <joelf@ti.com>
-
----
-drivers/crypto/omap-des.c | 53 ++++++++++++++++++++++++++++++++++++++++++++---
- 1 file changed, 50 insertions(+), 3 deletions(-)
-
---- a/drivers/crypto/omap-des.c
-+++ b/drivers/crypto/omap-des.c
-@@ -83,7 +83,7 @@ struct omap_des_ctx {
- struct omap_des_dev *dd;
-
- int keylen;
-- u32 key[DES_KEY_SIZE / sizeof(u32)];
-+ u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
- unsigned long flags;
- };
-
-@@ -265,8 +265,10 @@ static int omap_des_write_ctrl(struct om
- val |= DES_REG_CTRL_CBC;
- if (dd->flags & FLAGS_ENCRYPT)
- val |= DES_REG_CTRL_DIRECTION;
-+ if (key32 == 6)
-+ val |= DES_REG_CTRL_TDES;
-
-- mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION;
-+ mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
-
- omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
-
-@@ -725,7 +727,7 @@ static int omap_des_setkey(struct crypto
- {
- struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(tfm);
-
-- if (keylen != DES_KEY_SIZE)
-+ if (keylen != DES_KEY_SIZE && keylen != (3*DES_KEY_SIZE))
- return -EINVAL;
-
- pr_debug("enter, keylen: %d\n", keylen);
-@@ -815,6 +817,51 @@ static struct crypto_alg algs_ecb_cbc[]
- .ivsize = DES_BLOCK_SIZE,
- .setkey = omap_des_setkey,
- .encrypt = omap_des_cbc_encrypt,
-+ .decrypt = omap_des_cbc_decrypt,
-+ }
-+},
-+{
-+ .cra_name = "ecb(des3_ede)",
-+ .cra_driver_name = "ecb-des3-omap",
-+ .cra_priority = 100,
-+ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY |
-+ CRYPTO_ALG_ASYNC,
-+ .cra_blocksize = DES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct omap_des_ctx),
-+ .cra_alignmask = 0,
-+ .cra_type = &crypto_ablkcipher_type,
-+ .cra_module = THIS_MODULE,
-+ .cra_init = omap_des_cra_init,
-+ .cra_exit = omap_des_cra_exit,
-+ .cra_u.ablkcipher = {
-+ .min_keysize = 3*DES_KEY_SIZE,
-+ .max_keysize = 3*DES_KEY_SIZE,
-+ .setkey = omap_des_setkey,
-+ .encrypt = omap_des_ecb_encrypt,
-+ .decrypt = omap_des_ecb_decrypt,
-+ }
-+},
-+{
-+ .cra_name = "cbc(des3_ede)",
-+ .cra_driver_name = "cbc-des3-omap",
-+ .cra_priority = 100,
-+ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY |
-+ CRYPTO_ALG_ASYNC,
-+ .cra_blocksize = DES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct omap_des_ctx),
-+ .cra_alignmask = 0,
-+ .cra_type = &crypto_ablkcipher_type,
-+ .cra_module = THIS_MODULE,
-+ .cra_init = omap_des_cra_init,
-+ .cra_exit = omap_des_cra_exit,
-+ .cra_u.ablkcipher = {
-+ .min_keysize = 3*DES_KEY_SIZE,
-+ .max_keysize = 3*DES_KEY_SIZE,
-+ .ivsize = DES_BLOCK_SIZE,
-+ .setkey = omap_des_setkey,
-+ .encrypt = omap_des_cbc_encrypt,
- .decrypt = omap_des_cbc_decrypt,
- }
- }
+++ /dev/null
-From c1bac171c4f203101611110869bd2511c8153974 Mon Sep 17 00:00:00 2001
-From: Nishanth Menon <nm@ti.com>
-Date: Thu, 10 Oct 2013 16:44:41 +0000
-Subject: ARM: dts: omap4-panda-es: Do not reset gpio1
-
-Do not reset GPIO1 at boot-up because GPIO 7 in GPIO1 block is used on
-OMAP4460 PandaBoard-ES to select voltage register in TPS62361 which
-supplies VDD_MPU.
-
-Without this, OMAP4460 PandaBoard-ES boards fail to boot-up because
-MPU voltage switches over to VSET0 voltage value (boot voltage) which
-is not sufficient to operate the device at OPP100.
-
-Signed-off-by: Nishanth Menon <nm@ti.com>
-Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
----
---- a/arch/arm/boot/dts/omap4-panda-es.dts
-+++ b/arch/arm/boot/dts/omap4-panda-es.dts
-@@ -62,3 +62,7 @@
- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- };
- };
-+
-+&gpio1 {
-+ ti,no-reset-on-init;
-+};
+++ /dev/null
-From e7243b7673a20ac28cfdc78c8862587ea8173a39 Mon Sep 17 00:00:00 2001
-From: Markus Pargmann <mpa@pengutronix.de>
-Date: Mon, 14 Oct 2013 12:49:21 +0000
-Subject: ARM: dts: am33xx, change usb ctrl module label
-
-Control module is not usb specific.
-Changes the label to usb_ctrl_mod.
-
-Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
-Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
----
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -406,7 +406,7 @@
- ti,hwmods = "usb_otg_hs";
- status = "disabled";
-
-- ctrl_mod: control@44e10000 {
-+ usb_ctrl_mod: control@44e10000 {
- compatible = "ti,am335x-usb-ctrl-module";
- reg = <0x44e10620 0x10
- 0x44e10648 0x4>;
-@@ -419,7 +419,7 @@
- reg = <0x47401300 0x100>;
- reg-names = "phy";
- status = "disabled";
-- ti,ctrl_mod = <&ctrl_mod>;
-+ ti,ctrl_mod = <&usb_ctrl_mod>;
- };
-
- usb0: usb@47401000 {
-@@ -467,7 +467,7 @@
- reg = <0x47401b00 0x100>;
- reg-names = "phy";
- status = "disabled";
-- ti,ctrl_mod = <&ctrl_mod>;
-+ ti,ctrl_mod = <&usb_ctrl_mod>;
- };
-
- usb1: usb@47401800 {
+++ /dev/null
-From 92d51856d7405fa55bcf3d6f20d7e97e0bf2656c Mon Sep 17 00:00:00 2001
-From: Nishanth Menon <nm@ti.com>
-Date: Wed, 16 Oct 2013 15:39:01 +0000
-Subject: ARM: OMAP3+: do not register non-dt OPP tables for device tree boot
-
-OMAP3+ supports both device tree and non-device tree boot.
-Device tree bindings for OMAP3+ is supposed to be added via dts following:
-Documentation/devicetree/bindings/power/opp.txt
-
-Since we now have device tree entries for OMAP3+ cpu OPPs,
-The current code wrongly adds duplicate OPPs. So, dont register OPPs
-when booting using device tree.
-
-Signed-off-by: Nishanth Menon <nm@ti.com>
-Signed-off-by: Tony Lindgren <tony@atomide.com>
----
---- a/arch/arm/mach-omap2/opp.c
-+++ b/arch/arm/mach-omap2/opp.c
-@@ -17,6 +17,7 @@
- * GNU General Public License for more details.
- */
- #include <linux/module.h>
-+#include <linux/of.h>
- #include <linux/opp.h>
- #include <linux/cpu.h>
-
-@@ -40,6 +41,9 @@ int __init omap_init_opp_table(struct om
- {
- int i, r;
-
-+ if (of_have_populated_dt())
-+ return -EINVAL;
-+
- if (!opp_def || !opp_def_size) {
- pr_err("%s: invalid params!\n", __func__);
- return -EINVAL;
+++ /dev/null
-From 765e7a067eebf372687048ba0242e27f43cf0d71 Mon Sep 17 00:00:00 2001
-From: Nishanth Menon <nm@ti.com>
-Date: Wed, 16 Oct 2013 15:39:02 +0000
-Subject: ARM: OMAP2+: add missing lateinit hook for calling pm late init
-
-AM335x, AM43xx, OMAP5 and DRA7 have missing late init hook. Introduce
-SoC specific hook with a call to OMAP2+ generic lateinit hook. This
-allows the generic late initializations such as cpufreq hooks to be
-active.
-
-Based on out-of-tree patches that need to be introduced in
-mainline, this introduction allows us to provide the foundation for
-further SoC specific features as they are developed.
-
-Cc: Benoit Cousson <bcousson@baylibre.com>
-Cc: Kevin Hilman <khilman@deeprootsystems.com>
-Cc: Paul Walmsley <paul@pwsan.com>
-Cc: Tony Lindgren <tony@atomide.com>
-Signed-off-by: Nishanth Menon <nm@ti.com>
-Signed-off-by: Tony Lindgren <tony@atomide.com>
----
---- a/arch/arm/mach-omap2/board-generic.c
-+++ b/arch/arm/mach-omap2/board-generic.c
-@@ -180,6 +180,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM3
- .init_irq = omap_intc_of_init,
- .handle_irq = omap3_intc_handle_irq,
- .init_machine = omap_generic_init,
-+ .init_late = am33xx_init_late,
- .init_time = omap3_gptimer_timer_init,
- .dt_compat = am33xx_boards_compat,
- .restart = am33xx_restart,
-@@ -219,6 +220,7 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP
- .init_early = omap5_init_early,
- .init_irq = omap_gic_of_init,
- .init_machine = omap_generic_init,
-+ .init_late = omap5_init_late,
- .init_time = omap5_realtime_timer_init,
- .dt_compat = omap5_boards_compat,
- .restart = omap44xx_restart,
-@@ -234,6 +236,7 @@ static const char *am43_boards_compat[]
- DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
- .map_io = am33xx_map_io,
- .init_early = am43xx_init_early,
-+ .init_late = am43xx_init_late,
- .init_irq = omap_gic_of_init,
- .init_machine = omap_generic_init,
- .init_time = omap3_sync32k_timer_init,
-@@ -252,6 +255,7 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA
- .smp = smp_ops(omap4_smp_ops),
- .map_io = omap5_map_io,
- .init_early = dra7xx_init_early,
-+ .init_late = dra7xx_init_late,
- .init_irq = omap_gic_of_init,
- .init_machine = omap_generic_init,
- .init_time = omap5_realtime_timer_init,
---- a/arch/arm/mach-omap2/common.h
-+++ b/arch/arm/mach-omap2/common.h
-@@ -98,6 +98,7 @@ void am35xx_init_early(void);
- void ti81xx_init_early(void);
- void am33xx_init_early(void);
- void am43xx_init_early(void);
-+void am43xx_init_late(void);
- void omap4430_init_early(void);
- void omap5_init_early(void);
- void omap3_init_late(void); /* Do not use this one */
-@@ -109,8 +110,11 @@ void omap35xx_init_late(void);
- void omap3630_init_late(void);
- void am35xx_init_late(void);
- void ti81xx_init_late(void);
-+void am33xx_init_late(void);
-+void omap5_init_late(void);
- int omap2_common_pm_late_init(void);
- void dra7xx_init_early(void);
-+void dra7xx_init_late(void);
-
- #ifdef CONFIG_SOC_BUS
- void omap_soc_device_init(void);
---- a/arch/arm/mach-omap2/io.c
-+++ b/arch/arm/mach-omap2/io.c
-@@ -583,6 +583,11 @@ void __init am33xx_init_early(void)
- omap_hwmod_init_postsetup();
- omap_clk_init = am33xx_clk_init;
- }
-+
-+void __init am33xx_init_late(void)
-+{
-+ omap_common_late_init();
-+}
- #endif
-
- #ifdef CONFIG_SOC_AM43XX
-@@ -596,6 +601,11 @@ void __init am43xx_init_early(void)
- omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
- omap3xxx_check_revision();
- }
-+
-+void __init am43xx_init_late(void)
-+{
-+ omap_common_late_init();
-+}
- #endif
-
- #ifdef CONFIG_ARCH_OMAP4
-@@ -651,6 +661,11 @@ void __init omap5_init_early(void)
- omap54xx_hwmod_init();
- omap_hwmod_init_postsetup();
- }
-+
-+void __init omap5_init_late(void)
-+{
-+ omap_common_late_init();
-+}
- #endif
-
- #ifdef CONFIG_SOC_DRA7XX
-@@ -671,6 +686,11 @@ void __init dra7xx_init_early(void)
- dra7xx_hwmod_init();
- omap_hwmod_init_postsetup();
- }
-+
-+void __init dra7xx_init_late(void)
-+{
-+ omap_common_late_init();
-+}
- #endif
-
-
+++ /dev/null
-From 60c5fc86d01154e2a005bf701f495426ebc81f73 Mon Sep 17 00:00:00 2001
-From: Nishanth Menon <nm@ti.com>
-Date: Wed, 16 Oct 2013 15:39:03 +0000
-Subject: ARM: OMAP3+: use cpu0-cpufreq driver in device tree supported boot
-
-With OMAP3+ and AM33xx supported SoC having defined CPU device tree
-entries with operating-points and clock nodes defined, we can now use
-the SoC generic cpufreq-cpu0 driver by registering appropriate device.
-
-Cc: Benoit Cousson <bcousson@baylibre.com>
-Cc: Kevin Hilman <khilman@deeprootsystems.com>
-Cc: Paul Walmsley <paul@pwsan.com>
-Cc: Tony Lindgren <tony@atomide.com>
-Signed-off-by: Nishanth Menon <nm@ti.com>
-Signed-off-by: Tony Lindgren <tony@atomide.com>
----
---- a/arch/arm/mach-omap2/pm.c
-+++ b/arch/arm/mach-omap2/pm.c
-@@ -266,7 +266,12 @@ static void __init omap4_init_voltages(v
-
- static inline void omap_init_cpufreq(void)
- {
-- struct platform_device_info devinfo = { .name = "omap-cpufreq", };
-+ struct platform_device_info devinfo = { };
-+
-+ if (!of_have_populated_dt())
-+ devinfo.name = "omap-cpufreq";
-+ else
-+ devinfo.name = "cpufreq-cpu0";
- platform_device_register_full(&devinfo);
- }
-
-@@ -300,10 +305,11 @@ int __init omap2_common_pm_late_init(voi
- /* Smartreflex device init */
- omap_devinit_smartreflex();
-
-- /* cpufreq dummy device instantiation */
-- omap_init_cpufreq();
- }
-
-+ /* cpufreq dummy device instantiation */
-+ omap_init_cpufreq();
-+
- #ifdef CONFIG_SUSPEND
- suspend_set_ops(&omap_pm_ops);
- #endif
+++ /dev/null
-From b86684d70f1e45cae4a85686e6f78d5db341fa85 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sre@debian.org>
-Date: Tue, 22 Oct 2013 22:49:37 +0000
-Subject: ARM: dts: TWL4030: Add missing regulators
-
-The twl4030.dtsi is missing some regulators. This patch adds
-the missing ones and orders the regulators alphabetically.
-
-Signed-off-by: Sebastian Reichel <sre@debian.org>
-Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
----
---- a/arch/arm/boot/dts/twl4030.dtsi
-+++ b/arch/arm/boot/dts/twl4030.dtsi
-@@ -23,6 +23,22 @@
- compatible = "ti,twl4030-wdt";
- };
-
-+ vaux1: regulator-vaux1 {
-+ compatible = "ti,twl4030-vaux1";
-+ };
-+
-+ vaux2: regulator-vaux2 {
-+ compatible = "ti,twl4030-vaux2";
-+ };
-+
-+ vaux3: regulator-vaux3 {
-+ compatible = "ti,twl4030-vaux3";
-+ };
-+
-+ vaux4: regulator-vaux4 {
-+ compatible = "ti,twl4030-vaux4";
-+ };
-+
- vcc: regulator-vdd1 {
- compatible = "ti,twl4030-vdd1";
- regulator-min-microvolt = <600000>;
-@@ -35,10 +51,20 @@
- regulator-max-microvolt = <1800000>;
- };
-
-- vpll2: regulator-vpll2 {
-- compatible = "ti,twl4030-vpll2";
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-+ vio: regulator-vio {
-+ compatible = "ti,twl4030-vio";
-+ };
-+
-+ vintana1: regulator-vintana1 {
-+ compatible = "ti,twl4030-vintana1";
-+ };
-+
-+ vintana2: regulator-vintana2 {
-+ compatible = "ti,twl4030-vintana2";
-+ };
-+
-+ vintdig: regulator-vintdig {
-+ compatible = "ti,twl4030-vintdig";
- };
-
- vmmc1: regulator-vmmc1 {
-@@ -65,6 +91,16 @@
- compatible = "ti,twl4030-vusb3v1";
- };
-
-+ vpll1: regulator-vpll1 {
-+ compatible = "ti,twl4030-vpll1";
-+ };
-+
-+ vpll2: regulator-vpll2 {
-+ compatible = "ti,twl4030-vpll2";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ };
-+
- vsim: regulator-vsim {
- compatible = "ti,twl4030-vsim";
- regulator-min-microvolt = <1800000>;
+++ /dev/null
-From a3317d4f2fcd064071bc188cbbc2769dda73e487 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sre@debian.org>
-Date: Tue, 22 Oct 2013 22:49:43 +0000
-Subject: ARM: dts: TWL4030: Add power button support
-
-Enable support for the power button.
-
-Signed-off-by: Sebastian Reichel <sre@debian.org>
-Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
----
---- a/arch/arm/boot/dts/twl4030.dtsi
-+++ b/arch/arm/boot/dts/twl4030.dtsi
-@@ -133,4 +133,9 @@
- compatible = "ti,twl4030-pwmled";
- #pwm-cells = <2>;
- };
-+
-+ twl_pwrbutton: pwrbutton {
-+ compatible = "ti,twl4030-pwrbutton";
-+ interrupts = <8>;
-+ };
- };
+++ /dev/null
-From d4cbe80db468dcfaa058f9f00a332784e5dff316 Mon Sep 17 00:00:00 2001
-From: Suman Anna <s-anna@ti.com>
-Date: Thu, 10 Oct 2013 21:15:35 +0000
-Subject: ARM: dts: AM33XX: Add hwspinlock node
-
-Add the hwspinlock device tree node for AM33xx family
-of SoCs.
-
-Signed-off-by: Suman Anna <s-anna@ti.com>
-Signed-off-by: Tony Lindgren <tony@atomide.com>
----
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -278,6 +278,12 @@
- status = "disabled";
- };
-
-+ hwspinlock: spinlock@480ca000 {
-+ compatible = "ti,omap4-hwspinlock";
-+ reg = <0x480ca000 0x1000>;
-+ ti,hwmods = "spinlock";
-+ };
-+
- wdt2: wdt@44e35000 {
- compatible = "ti,omap3-wdt";
- ti,hwmods = "wd_timer2";
+++ /dev/null
-From ed845d6b78bf32b396f7f1278eed0b87446934b1 Mon Sep 17 00:00:00 2001
-From: Lokesh Vutla <lokeshvutla@ti.com>
-Date: Thu, 29 Aug 2013 12:52:09 +0000
-Subject: ARM: dts: AM33xx: Add RNG node
-
-Add the AM33xx RNG module's device tree data.
-Also add Documentation file describing the data
-for the RNG module.
-
-Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
-Signed-off-by: Tony Lindgren <tony@atomide.com>
----
---- /dev/null
-+++ b/Documentation/devicetree/bindings/hwrng/omap_rng.txt
-@@ -0,0 +1,22 @@
-+OMAP SoC HWRNG Module
-+
-+Required properties:
-+
-+- compatible : Should contain entries for this and backward compatible
-+ RNG versions:
-+ - "ti,omap2-rng" for OMAP2.
-+ - "ti,omap4-rng" for OMAP4, OMAP5 and AM33XX.
-+ Note that these two versions are incompatible.
-+- ti,hwmods: Name of the hwmod associated with the RNG module
-+- reg : Offset and length of the register set for the module
-+- interrupts : the interrupt number for the RNG module.
-+ Only used for "ti,omap4-rng".
-+
-+Example:
-+/* AM335x */
-+rng: rng@48310000 {
-+ compatible = "ti,omap4-rng";
-+ ti,hwmods = "rng";
-+ reg = <0x48310000 0x2000>;
-+ interrupts = <111>;
-+};
---- a/arch/arm/boot/dts/am33xx.dtsi
-+++ b/arch/arm/boot/dts/am33xx.dtsi
-@@ -770,5 +770,12 @@
- dma-names = "tx", "rx";
- };
-
-+ rng: rng@48310000 {
-+ compatible = "ti,omap4-rng";
-+ ti,hwmods = "rng";
-+ reg = <0x48310000 0x2000>;
-+ interrupts = <111>;
-+ };
-+
- };
- };
+++ /dev/null
-When running with DT, we no longer have a board file that can set up the
-platform data for wlcore. Allow this data to be passed from DT.
-
-Since some platforms use a gpio-irq, add support for passing either the
-irq number or the gpio number. For the latter case, the driver will
-request the gpio and convert it to the irq number. If an irq is
-specified, it'll be used as is.
-
-[Arik - the pdev_data pointer does not belong to us and is freed when
-the device is released. Dereference to our private data first.]
-
-Signed-off-by: Ido Yariv <ido@wizery.com>
-Signed-off-by: Arik Nemtsov <arik@wizery.com>
----
- drivers/net/wireless/ti/wlcore/sdio.c | 71 ++++++++++++++++++++++++++++++++---
- include/linux/wl12xx.h | 3 +-
- 2 files changed, 67 insertions(+), 7 deletions(-)
-
---- a/drivers/net/wireless/ti/wlcore/sdio.c
-+++ b/drivers/net/wireless/ti/wlcore/sdio.c
-@@ -34,6 +34,7 @@
- #include <linux/wl12xx.h>
- #include <linux/pm_runtime.h>
- #include <linux/printk.h>
-+#include <linux/of.h>
-
- #include "wlcore.h"
- #include "wl12xx_80211.h"
-@@ -214,6 +215,61 @@ static struct wl1271_if_operations sdio_
- .set_block_size = wl1271_sdio_set_block_size,
- };
-
-+static const struct of_device_id wlcore_of_match[] = {
-+ {
-+ .compatible = "wlcore",
-+ },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, wlcore_of_match);
-+
-+static struct wl12xx_platform_data *get_platform_data(struct device *dev)
-+{
-+ struct wl12xx_platform_data *pdata;
-+ struct device_node *np;
-+ u32 gpio;
-+
-+ pdata = wl12xx_get_platform_data();
-+ if (!IS_ERR(pdata))
-+ return kmemdup(pdata, sizeof(*pdata), GFP_KERNEL);
-+
-+ np = of_find_matching_node(NULL, wlcore_of_match);
-+ if (!np) {
-+ dev_err(dev, "No platform data set\n");
-+ return NULL;
-+ }
-+
-+ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
-+ if (!pdata) {
-+ dev_err(dev, "Can't allocate platform data\n");
-+ return NULL;
-+ }
-+
-+ if (of_property_read_u32(np, "irq", &pdata->irq)) {
-+ if (!of_property_read_u32(np, "gpio", &gpio) &&
-+ !gpio_request_one(gpio, GPIOF_IN, "wlcore_irq")) {
-+ pdata->gpio = gpio;
-+ pdata->irq = gpio_to_irq(gpio);
-+ }
-+ }
-+
-+ /* Optional fields */
-+ pdata->use_eeprom = of_property_read_bool(np, "use-eeprom");
-+ of_property_read_u32(np, "board-ref-clock", &pdata->board_ref_clock);
-+ of_property_read_u32(np, "board-tcxo-clock", &pdata->board_tcxo_clock);
-+ of_property_read_u32(np, "platform-quirks", &pdata->platform_quirks);
-+
-+ return pdata;
-+}
-+
-+static void del_platform_data(struct wl12xx_platform_data *pdata)
-+{
-+ if (pdata->gpio)
-+ gpio_free(pdata->gpio);
-+
-+ kfree(pdata);
-+}
-+
- static int wl1271_probe(struct sdio_func *func,
- const struct sdio_device_id *id)
- {
-@@ -248,12 +304,9 @@ static int wl1271_probe(struct sdio_func
- /* Use block mode for transferring over one block size of data */
- func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
-
-- pdev_data->pdata = wl12xx_get_platform_data();
-- if (IS_ERR(pdev_data->pdata)) {
-- ret = PTR_ERR(pdev_data->pdata);
-- dev_err(glue->dev, "missing wlan platform data: %d\n", ret);
-+ pdev_data->pdata = get_platform_data(&func->dev);
-+ if (!(pdev_data->pdata))
- goto out_free_glue;
-- }
-
- /* if sdio can keep power while host is suspended, enable wow */
- mmcflags = sdio_get_host_pm_caps(func);
-@@ -282,7 +335,7 @@ static int wl1271_probe(struct sdio_func
- if (!glue->core) {
- dev_err(glue->dev, "can't allocate platform_device");
- ret = -ENOMEM;
-- goto out_free_glue;
-+ goto out_free_pdata;
- }
-
- glue->core->dev.parent = &func->dev;
-@@ -316,6 +369,9 @@ static int wl1271_probe(struct sdio_func
- out_dev_put:
- platform_device_put(glue->core);
-
-+out_free_pdata:
-+ del_platform_data(pdev_data->pdata);
-+
- out_free_glue:
- kfree(glue);
-
-@@ -329,11 +385,14 @@ out:
- static void wl1271_remove(struct sdio_func *func)
- {
- struct wl12xx_sdio_glue *glue = sdio_get_drvdata(func);
-+ struct wlcore_platdev_data *pdev_data = glue->core->dev.platform_data;
-+ struct wl12xx_platform_data *pdata = pdev_data->pdata;
-
- /* Undo decrement done above in wl1271_probe */
- pm_runtime_get_noresume(&func->dev);
-
- platform_device_unregister(glue->core);
-+ del_platform_data(pdata);
- kfree(glue);
- }
-
---- a/include/linux/wl12xx.h
-+++ b/include/linux/wl12xx.h
-@@ -51,11 +51,12 @@ enum {
- struct wl12xx_platform_data {
- void (*set_power)(bool enable);
- /* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */
-+ int gpio;
- int irq;
- bool use_eeprom;
- int board_ref_clock;
- int board_tcxo_clock;
-- unsigned long platform_quirks;
-+ u32 platform_quirks;
- bool pwr_in_suspend;
- };
-
+++ /dev/null
-From 157c4071cb8a588c4e619b69447010a0ee68d844 Mon Sep 17 00:00:00 2001
-From: Darren Etheridge <detheridge@ti.com>
-Date: Thu, 17 Oct 2013 14:53:37 -0500
-Subject: [PATCH 568/752] arm: dts: am335x-evmsk: add support for lcd panel
-
-Add the necessary DT entries for probing the LCDC in fbdev and
-setting the correct timings for the NHD-4.3 LCD panel.
----
- arch/arm/boot/dts/am335x-evmsk.dts | 54 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 54 insertions(+)
-
---- a/arch/arm/boot/dts/am335x-evmsk.dts
-+++ b/arch/arm/boot/dts/am335x-evmsk.dts
-@@ -35,6 +35,39 @@
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
-
-+ lcd_pins_s0: lcd_pins_s0 {
-+ pinctrl-single,pins = <
-+ 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
-+ 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
-+ 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
-+ 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
-+ 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
-+ 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
-+ 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
-+ 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
-+ 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
-+ 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
-+ 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
-+ 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
-+ 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
-+ 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
-+ 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
-+ 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
-+ 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
-+ 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
-+ 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
-+ 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
-+ 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
-+ 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
-+ 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
-+ 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
-+ 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
-+ 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
-+ 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
-+ 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
-+ >;
-+ };
-+
- user_leds_s0: user_leds_s0 {
- pinctrl-single,pins = <
- 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
-@@ -255,6 +288,27 @@
- };
- };
-
-+ lcdc: lcdc@4830e000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&lcd_pins_s0>;
-+ status = "okay";
-+ display-timings {
-+ 480x272 {
-+ hactive = <480>;
-+ vactive = <272>;
-+ hback-porch = <43>;
-+ hfront-porch = <8>;
-+ hsync-len = <4>;
-+ vback-porch = <12>;
-+ vfront-porch = <4>;
-+ vsync-len = <10>;
-+ clock-frequency = <9000000>;
-+ hsync-active = <0>;
-+ vsync-active = <0>;
-+ };
-+ };
-+ };
-+
- sound {
- compatible = "ti,da830-evm-audio";
- ti,model = "AM335x-EVMSK";
+++ /dev/null
-From 588b7a5db74c02bcf0b3ac57b6391debffbff74c Mon Sep 17 00:00:00 2001
-From: Felipe Balbi <balbi@ti.com>
-Date: Mon, 21 Oct 2013 15:06:54 -0500
-Subject: [PATCH 582/752] arm: dts: am335x sk: add touchscreen support
-
-Add missing nodes for the touchscreen available
-on AM335x EVM SK.
-
-Signed-off-by: Felipe Balbi <balbi@ti.com>
----
- arch/arm/boot/dts/am335x-evmsk.dts | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm/boot/dts/am335x-evmsk.dts
-+++ b/arch/arm/boot/dts/am335x-evmsk.dts
-@@ -513,6 +513,16 @@
- vmmc-supply = <&vmmc_reg>;
- };
-
-+&tscadc {
-+ status = "okay";
-+ tsc {
-+ ti,wires = <4>;
-+ ti,x-plate-resistance = <200>;
-+ ti,coordinate-readouts = <5>;
-+ ti,wire-config = <0x00 0x11 0x22 0x33>;
-+ };
-+};
-+
- &gpio0 {
- ti,no-reset-on-init;
- };
+++ /dev/null
---- a/arch/arm/boot/dts/am335x-evmsk.dts
-+++ b/arch/arm/boot/dts/am335x-evmsk.dts
-@@ -14,6 +14,7 @@
- /dts-v1/;
-
- #include "am33xx.dtsi"
-+#include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/pwm/pwm.h>
-
- / {
-@@ -200,6 +201,26 @@
- 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
- >;
- };
-+
-+ wilink_pins: pinmux_wilink_pins {
-+ pinctrl-single,pins = <
-+ 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
-+ 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
-+ 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
-+ 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
-+ 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
-+ 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
-+ 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
-+ 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
-+ >;
-+ };
-+ };
-+
-+ wlan {
-+ compatible = "wlcore";
-+ gpio = <31>;
-+
-+ board-ref-clock = <4>;
- };
-
- ocp {
-@@ -335,6 +356,16 @@
- regulator-boot-on;
- };
-
-+ vmmc_wl: fixedregulator@2 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vmmc-wl";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ gpio = <&gpio1 29 0>;
-+ startup-delay-us = <70000>;
-+ enable-active-high;
-+ };
-+
- leds {
- pinctrl-names = "default";
- pinctrl-0 = <&user_leds_s0>;
-@@ -535,6 +566,16 @@
- status = "okay";
- };
-
-+&mmc2 {
-+ status = "okay";
-+ vmmc-supply = <&vmmc_wl>;
-+ bus-width = <4>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wilink_pins>;
-+ ti,non-removable;
-+ keep-power-in-suspend;
-+};
-+
- &mcasp1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcasp1_pins>;
+++ /dev/null
-From 884d3962ef4787c8cf0b8a7a673531c623d1dff8 Mon Sep 17 00:00:00 2001
-From: Darren Etheridge <detheridge@ti.com>
-Date: Fri, 2 Aug 2013 15:35:36 -0500
-Subject: [PATCH 334/752] video: da8xx-fb: adding dt support
-
-Enhancing driver to enable probe triggered by a corresponding dt entry.
-
-Add da8xx-fb.txt documentation to devicetree section.
-
-Obtain fb_videomode details for the connected lcd panel using the
-display timing details present in DT.
-
-Ensure that platform data is present before checking whether platform
-callback is present (the one used to control backlight). So far this
-was not an issue as driver was purely non-DT triggered, but now DT
-support has been added this check must be performed.
-
-v2: squashing multiple commits from Afzal Mohammed (afzal@ti.com)
-v3: remove superfluous cast
-v4: expose both ti,am3352-lcdc and ti,da830-lcdc for .compatible
- as driver can use enhanced features of all version of the
- silicon block.
-v5: addressed review comments from Prabhakar Lad
-v6: Changed the .compatible naming to match the existing drm bindings
- for am33xx devices
-v7: clarify which compatible to use in the documentation for DA850
-
-Acked-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
-Signed-off-by: Darren Etheridge <detheridge@ti.com>
----
- .../devicetree/bindings/video/da8xx-fb.txt | 42 +++++++++++++
- drivers/video/da8xx-fb.c | 66 +++++++++++++++++++-
- 2 files changed, 105 insertions(+), 3 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/video/da8xx-fb.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/video/da8xx-fb.txt
-@@ -0,0 +1,42 @@
-+TI LCD Controller on DA830/DA850/AM335x SoC's
-+
-+Required properties:
-+- compatible:
-+ DA830, DA850 - "ti,da8xx-tilcdc"
-+ AM335x SoC's - "ti,am33xx-tilcdc"
-+- reg: Address range of lcdc register set
-+- interrupts: lcdc interrupt
-+- display-timings: typical videomode of lcd panel, represented as child.
-+ Refer Documentation/devicetree/bindings/video/display-timing.txt for
-+ display timing binding details. If multiple videomodes are mentioned
-+ in display timings node, typical videomode has to be mentioned as the
-+ native mode or it has to be first child (driver cares only for native
-+ videomode).
-+
-+Recommended properties:
-+- ti,hwmods: Name of the hwmod associated to the LCDC
-+
-+Example for am335x SoC's:
-+
-+lcdc@4830e000 {
-+ compatible = "ti,am33xx-tilcdc";
-+ reg = <0x4830e000 0x1000>;
-+ interrupts = <36>;
-+ ti,hwmods = "lcdc";
-+ status = "okay";
-+ display-timings {
-+ 800x480p62 {
-+ clock-frequency = <30000000>;
-+ hactive = <800>;
-+ vactive = <480>;
-+ hfront-porch = <39>;
-+ hback-porch = <39>;
-+ hsync-len = <47>;
-+ vback-porch = <29>;
-+ vfront-porch = <13>;
-+ vsync-len = <2>;
-+ hsync-active = <1>;
-+ vsync-active = <1>;
-+ };
-+ };
-+};
---- a/drivers/video/da8xx-fb.c
-+++ b/drivers/video/da8xx-fb.c
-@@ -36,6 +36,7 @@
- #include <linux/slab.h>
- #include <linux/delay.h>
- #include <linux/lcm.h>
-+#include <video/of_display_timing.h>
- #include <video/da8xx-fb.h>
- #include <asm/div64.h>
-
-@@ -1311,12 +1312,54 @@ static struct fb_ops da8xx_fb_ops = {
- .fb_blank = cfb_blank,
- };
-
-+static struct lcd_ctrl_config *da8xx_fb_create_cfg(struct platform_device *dev)
-+{
-+ struct lcd_ctrl_config *cfg;
-+
-+ cfg = devm_kzalloc(&dev->dev, sizeof(struct fb_videomode), GFP_KERNEL);
-+ if (!cfg)
-+ return NULL;
-+
-+ /* default values */
-+
-+ if (lcd_revision == LCD_VERSION_1)
-+ cfg->bpp = 16;
-+ else
-+ cfg->bpp = 32;
-+
-+ /*
-+ * For panels so far used with this LCDC, below statement is sufficient.
-+ * For new panels, if required, struct lcd_ctrl_cfg fields to be updated
-+ * with additional/modified values. Those values would have to be then
-+ * obtained from dt(requiring new dt bindings).
-+ */
-+
-+ cfg->panel_shade = COLOR_ACTIVE;
-+
-+ return cfg;
-+}
-+
- static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev)
- {
- struct da8xx_lcdc_platform_data *fb_pdata = dev_get_platdata(&dev->dev);
- struct fb_videomode *lcdc_info;
-+ struct device_node *np = dev->dev.of_node;
- int i;
-
-+ if (np) {
-+ lcdc_info = devm_kzalloc(&dev->dev,
-+ sizeof(struct fb_videomode),
-+ GFP_KERNEL);
-+ if (!lcdc_info)
-+ return NULL;
-+
-+ if (of_get_fb_videomode(np, lcdc_info, OF_USE_NATIVE_MODE)) {
-+ dev_err(&dev->dev, "timings not available in DT\n");
-+ return NULL;
-+ }
-+ return lcdc_info;
-+ }
-+
- for (i = 0, lcdc_info = known_lcd_panels;
- i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) {
- if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
-@@ -1345,7 +1388,7 @@ static int fb_probe(struct platform_devi
- int ret;
- unsigned long ulcm;
-
-- if (fb_pdata == NULL) {
-+ if (fb_pdata == NULL && !device->dev.of_node) {
- dev_err(&device->dev, "Can not get platform data\n");
- return -ENOENT;
- }
-@@ -1385,7 +1428,10 @@ static int fb_probe(struct platform_devi
- break;
- }
-
-- lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
-+ if (device->dev.of_node)
-+ lcd_cfg = da8xx_fb_create_cfg(device);
-+ else
-+ lcd_cfg = fb_pdata->controller_data;
-
- if (!lcd_cfg) {
- ret = -EINVAL;
-@@ -1404,7 +1450,7 @@ static int fb_probe(struct platform_devi
- par->dev = &device->dev;
- par->lcdc_clk = tmp_lcdc_clk;
- par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
-- if (fb_pdata->panel_power_ctrl) {
-+ if (fb_pdata && fb_pdata->panel_power_ctrl) {
- par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
- par->panel_power_ctrl(1);
- }
-@@ -1652,6 +1698,19 @@ static int fb_resume(struct platform_dev
- #define fb_resume NULL
- #endif
-
-+#if IS_ENABLED(CONFIG_OF)
-+static const struct of_device_id da8xx_fb_of_match[] = {
-+ /*
-+ * this driver supports version 1 and version 2 of the
-+ * Texas Instruments lcd controller (lcdc) hardware block
-+ */
-+ {.compatible = "ti,da8xx-tilcdc", },
-+ {.compatible = "ti,am33xx-tilcdc", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, da8xx_fb_of_match);
-+#endif
-+
- static struct platform_driver da8xx_fb_driver = {
- .probe = fb_probe,
- .remove = fb_remove,
-@@ -1660,6 +1719,7 @@ static struct platform_driver da8xx_fb_d
- .driver = {
- .name = DRIVER_NAME,
- .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(da8xx_fb_of_match),
- },
- };
- module_platform_driver(da8xx_fb_driver);
+++ /dev/null
-From 9a1a810516ae9cb3259b898b6879901c5b44fa90 Mon Sep 17 00:00:00 2001
-From: Prathap M S <msprathap@ti.com>
-Date: Mon, 2 Sep 2013 12:05:23 +0530
-Subject: [PATCH 343/752] video: da8xx-fb: Add API to register wait for vsync
- callback
-
-This patch adds APIs to register and unregister wait for vsync callback.
-This is derived from commit id 2d44302545da24fd22912d964102bc31a7489e97
-This commit id was part of 3.2 kernel sources.
-
-Signed-off-by: Prathap M S <msprathap@ti.com>
----
- drivers/video/da8xx-fb.c | 33 +++++++++++++++++++++++++++++++++
- include/video/da8xx-fb.h | 4 ++++
- 2 files changed, 37 insertions(+)
-
---- a/drivers/video/da8xx-fb.c
-+++ b/drivers/video/da8xx-fb.c
-@@ -197,6 +197,9 @@ static struct fb_fix_screeninfo da8xx_fb
- .accel = FB_ACCEL_NONE
- };
-
-+static vsync_callback_t vsync_cb_handler;
-+static void *vsync_cb_arg;
-+
- static struct fb_videomode known_lcd_panels[] = {
- /* Sharp LCD035Q3DG01 */
- [0] = {
-@@ -825,6 +828,32 @@ static int lcd_init(struct da8xx_fb_par
- return 0;
- }
-
-+int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)
-+{
-+ if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {
-+ vsync_cb_arg = arg;
-+ vsync_cb_handler = handler;
-+ } else {
-+ return -EEXIST;
-+ }
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(register_vsync_cb);
-+
-+int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)
-+{
-+ if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {
-+ vsync_cb_handler = NULL;
-+ vsync_cb_arg = NULL;
-+ } else {
-+ return -ENXIO;
-+ }
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(unregister_vsync_cb);
-+
- /* IRQ handler for version 2 of LCDC */
- static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
- {
-@@ -862,6 +891,8 @@ static irqreturn_t lcdc_irq_handler_rev0
- LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
- par->vsync_flag = 1;
- wake_up_interruptible(&par->vsync_wait);
-+ if (vsync_cb_handler)
-+ vsync_cb_handler(vsync_cb_arg);
- }
-
- if (stat & LCD_END_OF_FRAME1) {
-@@ -937,6 +968,8 @@ static irqreturn_t lcdc_irq_handler_rev0
- LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
- par->vsync_flag = 1;
- wake_up_interruptible(&par->vsync_wait);
-+ if (vsync_cb_handler)
-+ vsync_cb_handler(vsync_cb_arg);
- }
- }
-
---- a/include/video/da8xx-fb.h
-+++ b/include/video/da8xx-fb.h
-@@ -91,5 +91,9 @@ struct lcd_sync_arg {
- /* Proprietary FB_SYNC_ flags */
- #define FB_SYNC_CLK_INVERT 0x40000000
-
-+typedef void (*vsync_callback_t)(void *arg);
-+int register_vsync_cb(vsync_callback_t handler, void *arg, int idx);
-+int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx);
-+
- #endif /* ifndef DA8XX_FB_H */
-
+++ /dev/null
-From c99bd415829ef29adf71bb1e1b577650f10e93f5 Mon Sep 17 00:00:00 2001
-From: Darren Etheridge <detheridge@ti.com>
-Date: Mon, 4 Nov 2013 12:27:40 -0600
-Subject: [PATCH 752/752] video/da8xx-fb fix defect with vsync callback
- invocation
-
-Fix defect where SGX is running at half of the expected framerate.
-The original patch (@ commit ID 9a1a810516ae9cb3259b898b6879901c5b44fa90)
-seems to have a mistake where it only calls the callback
-for the even or the odd frames depending on the revision of the LCD controller
-This patch corrects this and invokes the callback for both odd and even frame
-for just the Rev02 version of the LCDC (won't find an SGX GPU on a Rev01).
-
-Signed-off-by: Darren Etheridge <detheridge@ti.com>
----
- drivers/video/da8xx-fb.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/video/da8xx-fb.c
-+++ b/drivers/video/da8xx-fb.c
-@@ -903,6 +903,8 @@ static irqreturn_t lcdc_irq_handler_rev0
- LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
- par->vsync_flag = 1;
- wake_up_interruptible(&par->vsync_wait);
-+ if (vsync_cb_handler)
-+ vsync_cb_handler(vsync_cb_arg);
- }
-
- /* Set only when controller is disabled and at the end of
-@@ -968,8 +970,6 @@ static irqreturn_t lcdc_irq_handler_rev0
- LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
- par->vsync_flag = 1;
- wake_up_interruptible(&par->vsync_wait);
-- if (vsync_cb_handler)
-- vsync_cb_handler(vsync_cb_arg);
- }
- }
-
+++ /dev/null
-When running with DT, we no longer have a board file that can set up the
-platform data for wlcore. Allow this data to be passed from DT.
-
-Since some platforms use a gpio-irq, add support for passing either the
-irq number or the gpio number. For the latter case, the driver will
-request the gpio and convert it to the irq number. If an irq is
-specified, it'll be used as is.
-
-[Arik - the pdev_data pointer does not belong to us and is freed when
-the device is released. Dereference to our private data first.]
-
-Signed-off-by: Ido Yariv <ido@wizery.com>
-Signed-off-by: Arik Nemtsov <arik@wizery.com>
----
- drivers/net/wireless/ti/wlcore/sdio.c | 71 ++++++++++++++++++++++++++++++++---
- include/linux/wl12xx.h | 3 +-
- 2 files changed, 67 insertions(+), 7 deletions(-)
-
---- a/drivers/net/wireless/ti/wlcore/sdio.c
-+++ b/drivers/net/wireless/ti/wlcore/sdio.c
-@@ -34,6 +34,7 @@
- #include <linux/wl12xx.h>
- #include <linux/pm_runtime.h>
- #include <linux/printk.h>
-+#include <linux/of.h>
-
- #include "wlcore.h"
- #include "wl12xx_80211.h"
-@@ -214,6 +215,61 @@ static struct wl1271_if_operations sdio_
- .set_block_size = wl1271_sdio_set_block_size,
- };
-
-+static const struct of_device_id wlcore_of_match[] = {
-+ {
-+ .compatible = "wlcore",
-+ },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, wlcore_of_match);
-+
-+static struct wl12xx_platform_data *get_platform_data(struct device *dev)
-+{
-+ struct wl12xx_platform_data *pdata;
-+ struct device_node *np;
-+ u32 gpio;
-+
-+ pdata = wl12xx_get_platform_data();
-+ if (!IS_ERR(pdata))
-+ return kmemdup(pdata, sizeof(*pdata), GFP_KERNEL);
-+
-+ np = of_find_matching_node(NULL, wlcore_of_match);
-+ if (!np) {
-+ dev_err(dev, "No platform data set\n");
-+ return NULL;
-+ }
-+
-+ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
-+ if (!pdata) {
-+ dev_err(dev, "Can't allocate platform data\n");
-+ return NULL;
-+ }
-+
-+ if (of_property_read_u32(np, "irq", &pdata->irq)) {
-+ if (!of_property_read_u32(np, "gpio", &gpio) &&
-+ !gpio_request_one(gpio, GPIOF_IN, "wlcore_irq")) {
-+ pdata->gpio = gpio;
-+ pdata->irq = gpio_to_irq(gpio);
-+ }
-+ }
-+
-+ /* Optional fields */
-+ pdata->use_eeprom = of_property_read_bool(np, "use-eeprom");
-+ of_property_read_u32(np, "board-ref-clock", &pdata->board_ref_clock);
-+ of_property_read_u32(np, "board-tcxo-clock", &pdata->board_tcxo_clock);
-+ of_property_read_u32(np, "platform-quirks", &pdata->platform_quirks);
-+
-+ return pdata;
-+}
-+
-+static void del_platform_data(struct wl12xx_platform_data *pdata)
-+{
-+ if (pdata->gpio)
-+ gpio_free(pdata->gpio);
-+
-+ kfree(pdata);
-+}
-+
- static int wl1271_probe(struct sdio_func *func,
- const struct sdio_device_id *id)
- {
-@@ -248,12 +304,9 @@ static int wl1271_probe(struct sdio_func
- /* Use block mode for transferring over one block size of data */
- func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
-
-- pdev_data->pdata = wl12xx_get_platform_data();
-- if (IS_ERR(pdev_data->pdata)) {
-- ret = PTR_ERR(pdev_data->pdata);
-- dev_err(glue->dev, "missing wlan platform data: %d\n", ret);
-+ pdev_data->pdata = get_platform_data(&func->dev);
-+ if (!(pdev_data->pdata))
- goto out_free_glue;
-- }
-
- /* if sdio can keep power while host is suspended, enable wow */
- mmcflags = sdio_get_host_pm_caps(func);
-@@ -282,7 +335,7 @@ static int wl1271_probe(struct sdio_func
- if (!glue->core) {
- dev_err(glue->dev, "can't allocate platform_device");
- ret = -ENOMEM;
-- goto out_free_glue;
-+ goto out_free_pdata;
- }
-
- glue->core->dev.parent = &func->dev;
-@@ -316,6 +369,9 @@ static int wl1271_probe(struct sdio_func
- out_dev_put:
- platform_device_put(glue->core);
-
-+out_free_pdata:
-+ del_platform_data(pdev_data->pdata);
-+
- out_free_glue:
- kfree(glue);
-
-@@ -329,11 +385,14 @@ out:
- static void wl1271_remove(struct sdio_func *func)
- {
- struct wl12xx_sdio_glue *glue = sdio_get_drvdata(func);
-+ struct wlcore_platdev_data *pdev_data = glue->core->dev.platform_data;
-+ struct wl12xx_platform_data *pdata = pdev_data->pdata;
-
- /* Undo decrement done above in wl1271_probe */
- pm_runtime_get_noresume(&func->dev);
-
- platform_device_unregister(glue->core);
-+ del_platform_data(pdata);
- kfree(glue);
- }
-
---- a/include/linux/wl12xx.h
-+++ b/include/linux/wl12xx.h
-@@ -51,11 +51,12 @@ enum {
- struct wl12xx_platform_data {
- void (*set_power)(bool enable);
- /* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */
-+ int gpio;
- int irq;
- bool use_eeprom;
- int board_ref_clock;
- int board_tcxo_clock;
-- unsigned long platform_quirks;
-+ u32 platform_quirks;
- bool pwr_in_suspend;
- };
-
+++ /dev/null
---- a/arch/arm/boot/dts/am335x-evmsk.dts
-+++ b/arch/arm/boot/dts/am335x-evmsk.dts
-@@ -132,6 +132,39 @@
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
-
-+ lcd_pins_s0: lcd_pins_s0 {
-+ pinctrl-single,pins = <
-+ 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
-+ 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
-+ 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
-+ 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
-+ 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
-+ 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
-+ 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
-+ 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
-+ 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
-+ 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
-+ 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
-+ 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
-+ 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
-+ 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
-+ 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
-+ 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
-+ 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
-+ 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
-+ 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
-+ 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
-+ 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
-+ 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
-+ 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
-+ 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
-+ 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
-+ 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
-+ 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
-+ 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
-+ >;
-+ };
-+
- user_leds_s0: user_leds_s0 {
- pinctrl-single,pins = <
- 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
-@@ -486,6 +519,27 @@
- rx-num-evt = <1>;
- };
-
-+&lcdc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&lcd_pins_s0>;
-+ status = "okay";
-+ display-timings {
-+ 480x272 {
-+ hactive = <480>;
-+ vactive = <272>;
-+ hback-porch = <43>;
-+ hfront-porch = <8>;
-+ hsync-len = <4>;
-+ vback-porch = <12>;
-+ vfront-porch = <4>;
-+ vsync-len = <10>;
-+ clock-frequency = <9000000>;
-+ hsync-active = <0>;
-+ vsync-active = <0>;
-+ };
-+ };
-+};
-+
- &tscadc {
- status = "okay";
- tsc {
+++ /dev/null
---- a/arch/arm/boot/dts/am335x-evmsk.dts
-+++ b/arch/arm/boot/dts/am335x-evmsk.dts
-@@ -14,6 +14,7 @@
- /dts-v1/;
-
- #include "am33xx.dtsi"
-+#include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/pwm/pwm.h>
-
- / {
-@@ -26,6 +27,13 @@
- };
- };
-
-+ wlan {
-+ compatible = "wlcore";
-+
-+ gpio = <31>;
-+ board-ref-clock = <4>;
-+ };
-+
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256 MB */
-@@ -45,6 +53,16 @@
- regulator-boot-on;
- };
-
-+ vmmc_wl: fixedregulator@2 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vmmc-wl";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ gpio = <&gpio1 29 0>;
-+ startup-delay-us = <70000>;
-+ enable-active-high;
-+ };
-+
- leds {
- pinctrl-names = "default";
- pinctrl-0 = <&user_leds_s0>;
-@@ -297,6 +315,20 @@
- 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
- >;
- };
-+
-+ wilink_pins: pinmux_wilink_pins {
-+ pinctrl-single,pins = <
-+ 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
-+ 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
-+ 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
-+ 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
-+ 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
-+ 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
-+ 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
-+ 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
-+ >;
-+ };
-+
- };
-
- &uart0 {
-@@ -503,6 +535,16 @@
- ti,no-reset-on-init;
- };
-
-+&mmc2 {
-+ status = "okay";
-+ vmmc-supply = <&vmmc_wl>;
-+ bus-width = <4>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wilink_pins>;
-+ ti,non-removable;
-+ keep-power-in-suspend;
-+};
-+
- &mcasp1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcasp1_pins>;
+++ /dev/null
---- a/arch/arm/mach-omap2/twl-common.c
-+++ b/arch/arm/mach-omap2/twl-common.c
-@@ -280,6 +280,7 @@ static struct regulator_init_data omap4_
- static struct regulator_init_data omap4_clk32kg_idata = {
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-+ .always_on = true,
- },
- };
-
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Default
- NAME:=Default Profile
-endef
-
-define Profile/Default/Description
- Default package set compatible with most boards.
-endef
-
-$(eval $(call Profile,Default))
+++ /dev/null
-#
-# Copyright (C) 2010-2011 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=omap24xx
-BOARDNAME:=TI OMAP24xx
-MAINTAINER:=Michael Buesch <m@bues.ch>
-FEATURES:=targz squashfs jffs2_nand usb usbgadget display gpio audio broken
-CPU_TYPE:=arm1136j-s
-
-LINUX_VERSION:=3.3.8
-
-define Target/Description
- TI OMAP-24xx
-endef
-
-KERNELNAME:="zImage"
-
-include $(INCLUDE_DIR)/target.mk
-
-$(eval $(call BuildTarget))
+++ /dev/null
-config mount
- option target /maemo/initfs
- option device /dev/mtdblock3
- option fstype jffs2
- option options rw,noatime
- option enabled 0
-
-config mount
- option target /maemo/rootfs
- option device /dev/mtdblock4
- option fstype jffs2
- option options rw,noatime
- option enabled 0
+++ /dev/null
-config interface loopback
- option ifname lo
- option proto static
- option netmask 255.0.0.0
-
-config interface lan
- option proto dhcp
- option netmask 255.255.255.0
-
-config interface usb
- option ifname usb0
- option proto static
- option ipaddr 192.168.168.168
- option netmask 255.255.255.0
- option ip6addr fe80::810:1
+++ /dev/null
-config wifi-device radio0
- option type mac80211
- option phy phy0
- option channel auto
- # TODO: CHANGE THE MAC-ADDRESS:
- option macaddr 00:11:22:33:44:55
- option hwmode 11g
-# option country DE
-
- # REMOVE THIS LINE TO ENABLE WIFI:
- option disabled 1
-
-config wifi-iface
- option device radio0
- option powersave 1
- option network lan
- option mode sta
- option ssid OpenWrt
-# option encryption psk2
-# option key "foobar"
+++ /dev/null
-#!/bin/sh
-
-n810_cal_bme_pmm_extract() {
- [ -x /usr/bin/calvaria ] && {
- /usr/bin/calvaria -p -n bme -i last /dev/mtdblock1 >/lib/firmware/n810-cal-bme-pmm.fw ||\
- echo "CAL-BME extract: Failed to extract blob"
- }
-}
-
-[ "$FIRMWARE" = "n810-cal-bme-pmm.fw" ] && {
- [ -z "$(grep -e 'Nokia N810' /proc/cpuinfo)" ] || {
- [ -e /lib/firmware/n810-cal-bme-pmm.fw ] ||\
- n810_cal_bme_pmm_extract
- }
-}
+++ /dev/null
-#!/bin/sh
-
-p54spi_eeprom_clean() {
- rm -f /tmp/wlan-iq-align /tmp/wlan-tx-gen2
-}
-
-p54spi_eeprom_die() {
- echo "$*"
- p54spi_eeprom_clean
- exit 1
-}
-
-p54spi_eeprom_extract() {
- [ -x /usr/bin/calvaria -a -x /usr/bin/cal2p54 ] && {
- /usr/bin/calvaria -p -n wlan-iq-align -i last /dev/mtdblock1 >/tmp/wlan-iq-align ||\
- p54spi_eeprom_die "p54spi EEPROM: Failed to extract wlan-iq-align"
- /usr/bin/calvaria -p -n wlan-tx-gen2 -i last /dev/mtdblock1 >/tmp/wlan-tx-gen2 ||\
- p54spi_eeprom_die "p54spi EEPROM: Failed to extract wlan-tx-gen2"
- /usr/bin/cal2p54 /tmp/wlan-tx-gen2 /tmp/wlan-iq-align >/lib/firmware/3826.eeprom ||\
- p54spi_eeprom_die "p54spi EEPROM: Failed to generate EEPROM"
- p54spi_eeprom_clean
- }
-}
-
-[ "$FIRMWARE" = "3826.eeprom" ] && {
- [ -z "$(grep -e 'Nokia N810' /proc/cpuinfo)" ] || {
- [ -e /lib/firmware/3826.eeprom ] ||\
- p54spi_eeprom_extract
- }
-}
+++ /dev/null
-#!/bin/sh /etc/rc.common
-# Copyright (C) 2008-2010 OpenWrt.org
-
-START=25
-
-start() {
- [ -c /dev/watchdog -a -x /sbin/watchdog ] || {
- echo "WARNING: Watchdog not available. System will reboot soon!"
- return 1
- }
- /sbin/watchdog -T 63 -t 50 /dev/watchdog
- [ -x /usr/bin/schedtool ] && /usr/bin/schedtool -R -p 60 -n -20 $(pidof watchdog)
-}
-
-stop() {
- killall -q watchdog
-}
+++ /dev/null
-::sysinit:/etc/init.d/rcS S boot
-::shutdown:/etc/init.d/rcS K shutdown
-tts/0::askfirst:/bin/ash --login
-ttyO2::askfirst:/bin/ash --login
-tty1::askfirst:/bin/ash --login
+++ /dev/null
-14706 -12 -3754952 36 -9898 35656000 65536
+++ /dev/null
-# CONFIG_AD2S1200 is not set
-# CONFIG_AD2S1210 is not set
-# CONFIG_AD2S90 is not set
-# CONFIG_AD5064 is not set
-# CONFIG_AD5360 is not set
-# CONFIG_AD5380 is not set
-# CONFIG_AD5421 is not set
-# CONFIG_AD5446 is not set
-# CONFIG_AD5504 is not set
-# CONFIG_AD5624R_SPI is not set
-# CONFIG_AD5686 is not set
-# CONFIG_AD5764 is not set
-# CONFIG_AD5791 is not set
-# CONFIG_AD5930 is not set
-# CONFIG_AD5933 is not set
-# CONFIG_AD7150 is not set
-# CONFIG_AD7152 is not set
-# CONFIG_AD7192 is not set
-# CONFIG_AD7280 is not set
-# CONFIG_AD7291 is not set
-# CONFIG_AD7298 is not set
-# CONFIG_AD7476 is not set
-# CONFIG_AD7606 is not set
-# CONFIG_AD7746 is not set
-# CONFIG_AD7780 is not set
-# CONFIG_AD7793 is not set
-# CONFIG_AD7816 is not set
-# CONFIG_AD7887 is not set
-# CONFIG_AD799X is not set
-# CONFIG_AD9832 is not set
-# CONFIG_AD9834 is not set
-# CONFIG_AD9850 is not set
-# CONFIG_AD9852 is not set
-# CONFIG_AD9910 is not set
-# CONFIG_AD9951 is not set
-# CONFIG_ADE7753 is not set
-# CONFIG_ADE7754 is not set
-# CONFIG_ADE7758 is not set
-# CONFIG_ADE7759 is not set
-# CONFIG_ADE7854 is not set
-# CONFIG_ADIS16060 is not set
-# CONFIG_ADIS16080 is not set
-# CONFIG_ADIS16130 is not set
-CONFIG_ADIS16201=m
-CONFIG_ADIS16203=m
-CONFIG_ADIS16204=m
-# CONFIG_ADIS16209 is not set
-# CONFIG_ADIS16220 is not set
-# CONFIG_ADIS16240 is not set
-# CONFIG_ADIS16260 is not set
-# CONFIG_ADIS16400 is not set
-# CONFIG_ADT7310 is not set
-# CONFIG_ADT7316 is not set
-# CONFIG_ADT7410 is not set
-# CONFIG_ADXRS450 is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_APM_EMULATION=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OMAP=y
-# CONFIG_ARCH_OMAP1 is not set
-CONFIG_ARCH_OMAP2=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
-# CONFIG_ARCH_OMAP3 is not set
-# CONFIG_ARCH_OMAP4 is not set
-CONFIG_ARCH_OMAP_OTG=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
-CONFIG_ARM=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_ERRATA_364296=y
-CONFIG_ARM_ERRATA_411920=y
-# CONFIG_ARM_EXYNOS4210_CPUFREQ is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-# CONFIG_ARPD is not set
-CONFIG_ATAGS_PROC=y
-CONFIG_BINFMT_MISC=y
-# CONFIG_BLK_CGROUP is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_SD=y
-CONFIG_BRIDGE=m
-CONFIG_BT=m
-# CONFIG_BT_HCIH4P is not set
-CONFIG_BT_HCIUART=m
-# CONFIG_BT_HCIUART_BCSP is not set
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CBUS=y
-CONFIG_CBUS_RETU=y
-CONFIG_CBUS_RETU_HEADSET=y
-CONFIG_CBUS_RETU_POWERBUTTON=y
-CONFIG_CBUS_RETU_WDT=y
-CONFIG_CBUS_TAHVO=y
-CONFIG_CBUS_TAHVO_USB=m
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_CFS_BANDWIDTH is not set
-CONFIG_CGROUPS=y
-# CONFIG_CGROUP_CPUACCT is not set
-# CONFIG_CGROUP_DEBUG is not set
-# CONFIG_CGROUP_DEVICE is not set
-# CONFIG_CGROUP_FREEZER is not set
-CONFIG_CGROUP_SCHED=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CMDLINE="root=/dev/mmcblk0p1 rootfstype=ext4,ext3,ext2,squashfs,jffs2 console=tty0 console=ttyO2,115200n8 earlyprintk"
-CONFIG_CMDLINE_FORCE=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-# CONFIG_CPUSETS is not set
-CONFIG_CPU_32v6=y
-CONFIG_CPU_ABRT_EV6=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V6=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_TABLE=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_HAS_PMU=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V6=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_TLB_V6=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CPU_V6=y
-CONFIG_CRC16=y
-CONFIG_CRC7=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_DEV_OMAP_AES=y
-CONFIG_CRYPTO_DEV_OMAP_SHAM=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_MANAGER=m
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_PCOMP2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEFAULT_CFQ=y
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_DEVKMEM=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DNOTIFY=y
-CONFIG_DNS_RESOLVER=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_EXPORTFS=m
-CONFIG_EXT4_FS=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAT_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_OMAP=y
-# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
-CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
-CONFIG_FB_OMAP_LCDC_BLIZZARD=y
-CONFIG_FB_OMAP_LCDC_EXTERNAL=y
-# CONFIG_FB_OMAP_LCDC_HWA742 is not set
-CONFIG_FB_OMAP_LCD_MIPID=y
-# CONFIG_FB_OMAP_MANUAL_UPDATE is not set
-# CONFIG_FB_WMT_GE_ROPS is not set
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_FONTS=y
-# CONFIG_FONT_10x18 is not set
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_SUN8x16 is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FREEZER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ACL=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_AOUT=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MTD_OTP=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SCHED_CLOCK=y
-CONFIG_HAVE_SPARSE_IRQ=y
-CONFIG_HID=y
-CONFIG_HID_APPLE=m
-CONFIG_HID_SUPPORT=y
-CONFIG_HWMON=m
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_OMAP=y
-CONFIG_HZ=128
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_OMAP=y
-CONFIG_IIO=y
-# CONFIG_IIO_BUFFER is not set
-# CONFIG_IIO_SIMPLE_DUMMY is not set
-# CONFIG_IIO_TRIGGER is not set
-CONFIG_INET6_XFRM_MODE_BEET=m
-CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-CONFIG_INET6_XFRM_MODE_TUNNEL=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-CONFIG_INET_TUNNEL=m
-# CONFIG_INLINE_READ_UNLOCK is not set
-# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_UNLOCK is not set
-# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_UNLOCK is not set
-# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
-CONFIG_INPUT=y
-# CONFIG_INPUT_APMPOWER is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_MOUSE=y
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
-CONFIG_INPUT_TABLET=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_SIT=m
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_MROUTE is not set
-CONFIG_IR_LIRC_CODEC=m
-CONFIG_IR_MCE_KBD_DECODER=m
-CONFIG_IR_RC5_SZ_DECODER=m
-# CONFIG_IR_REDRAT3 is not set
-CONFIG_IR_SANYO_DECODER=m
-# CONFIG_ISDN is not set
-# CONFIG_ISP1301_OMAP is not set
-CONFIG_JBD2=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JOYSTICK_A3D is not set
-# CONFIG_JOYSTICK_ADI is not set
-# CONFIG_JOYSTICK_ANALOG is not set
-# CONFIG_JOYSTICK_AS5011 is not set
-# CONFIG_JOYSTICK_COBRA is not set
-# CONFIG_JOYSTICK_GF2K is not set
-# CONFIG_JOYSTICK_GRIP is not set
-# CONFIG_JOYSTICK_GRIP_MP is not set
-# CONFIG_JOYSTICK_GUILLEMOT is not set
-# CONFIG_JOYSTICK_IFORCE is not set
-# CONFIG_JOYSTICK_INTERACT is not set
-# CONFIG_JOYSTICK_JOYDUMP is not set
-# CONFIG_JOYSTICK_MAGELLAN is not set
-# CONFIG_JOYSTICK_SIDEWINDER is not set
-# CONFIG_JOYSTICK_SPACEBALL is not set
-# CONFIG_JOYSTICK_SPACEORB is not set
-# CONFIG_JOYSTICK_STINGER is not set
-# CONFIG_JOYSTICK_TMDC is not set
-# CONFIG_JOYSTICK_TWIDJOY is not set
-# CONFIG_JOYSTICK_WARRIOR is not set
-# CONFIG_JOYSTICK_XPAD is not set
-# CONFIG_JOYSTICK_ZHENHUA is not set
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KEXEC=y
-# CONFIG_KEYBOARD_GPIO is not set
-CONFIG_KEYBOARD_LM8323=y
-# CONFIG_KEYBOARD_OMAP is not set
-CONFIG_KEYBOARD_TSC2301=y
-CONFIG_KEYS=y
-CONFIG_KTIME_SCALAR=y
-# CONFIG_KXSD9 is not set
-# CONFIG_LEDS is not set
-# CONFIG_LEDS_REGULATOR is not set
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LIRC=m
-# CONFIG_LIS3L02DQ is not set
-CONFIG_LLC=m
-CONFIG_LOCKD=m
-CONFIG_LOG_BUF_SHIFT=18
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_NOKIA_N800=y
-CONFIG_MACH_NOKIA_N810=y
-CONFIG_MACH_NOKIA_N810_WIMAX=y
-CONFIG_MACH_NOKIA_N8X0=y
-CONFIG_MACH_OMAP2_TUSB6010=y
-# CONFIG_MACH_OMAP_APOLLON is not set
-# CONFIG_MACH_OMAP_GENERIC is not set
-# CONFIG_MACH_OMAP_H4 is not set
-CONFIG_MACVLAN=m
-CONFIG_MAC_PARTITION=y
-# CONFIG_MAX1363 is not set
-# CONFIG_MAX517 is not set
-CONFIG_MEDIA_ATTACH=y
-CONFIG_MEDIA_SUPPORT=m
-CONFIG_MEDIA_TUNER=m
-CONFIG_MEDIA_TUNER_MC44S803=m
-CONFIG_MEDIA_TUNER_MT20XX=m
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA18271=m
-CONFIG_MEDIA_TUNER_TDA827X=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_TEA5761=m
-CONFIG_MEDIA_TUNER_TEA5767=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC4000=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_MENELAUS=y
-# CONFIG_MFD_T7L66XB is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_OMAP=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SPI=y
-CONFIG_MMC_UNSAFE_RESUME=y
-# CONFIG_MOUSE_BCM5974 is not set
-CONFIG_MOUSE_PS2=m
-# CONFIG_MOUSE_PS2_ALPS is not set
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
-# CONFIG_MOUSE_PS2_SYNAPTICS is not set
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-# CONFIG_MOUSE_PS2_TRACKPOINT is not set
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-CONFIG_MSDOS_FS=y
-CONFIG_MTD_BLOCK2MTD=y
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_ONENAND=y
-# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
-# CONFIG_MTD_ONENAND_GENERIC is not set
-CONFIG_MTD_ONENAND_OMAP2=y
-CONFIG_MTD_ONENAND_OTP=y
-# CONFIG_MTD_ONENAND_SIM is not set
-# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
-# CONFIG_MTD_ROOTFS_ROOT_DEV is not set
-# CONFIG_MTD_ROOTFS_SPLIT is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-# CONFIG_MUSB_PIO_ONLY is not set
-CONFIG_N810BM=m
-CONFIG_NAMESPACES=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-# CONFIG_NETPRIO_CGROUP is not set
-# CONFIG_NET_NS is not set
-# CONFIG_NET_SCHED is not set
-CONFIG_NFSD=m
-# CONFIG_NFSD_FAULT_INJECTION is not set
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_NFS_ACL_SUPPORT=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_USE_KERNEL_DNS=y
-# CONFIG_NFS_USE_LEGACY_DNS is not set
-# CONFIG_NFS_USE_NEW_IDMAPPER is not set
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_NFS_V4_1=y
-CONFIG_NLS=y
-CONFIG_NOP_USB_XCEIV=m
-CONFIG_NO_HZ=y
-# CONFIG_OMAP2_DSS is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_32K_TIMER_HZ=128
-CONFIG_OMAP_BOOT_REASON=y
-CONFIG_OMAP_BOOT_TAG=y
-CONFIG_OMAP_COMPONENT_VERSION=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_OMAP_GPIO_SWITCH=y
-CONFIG_OMAP_MBOX_FWK=y
-CONFIG_OMAP_MBOX_KFIFO_SIZE=256
-CONFIG_OMAP_MCBSP=y
-CONFIG_OMAP_MUX=y
-# CONFIG_OMAP_MUX_DEBUG is not set
-CONFIG_OMAP_MUX_WARNINGS=y
-CONFIG_OMAP_PACKAGE_ZAC=y
-CONFIG_OMAP_PM_NOOP=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_WATCHDOG is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_SLEEP=y
-CONFIG_PNFS_FILE_LAYOUT=m
-CONFIG_POSIX_MQUEUE=y
-CONFIG_POSIX_MQUEUE_SYSCTL=y
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_MPPE=m
-# CONFIG_PPP_MULTILINK is not set
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_RCU_BOOST=y
-CONFIG_RCU_BOOST_DELAY=500
-CONFIG_RCU_BOOST_PRIO=1
-# CONFIG_RC_ATI_REMOTE is not set
-CONFIG_RC_CORE=m
-# CONFIG_RC_LOOPBACK is not set
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=m
-CONFIG_REGMAP_SPI=m
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_AD5398 is not set
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_DUMMY is not set
-# CONFIG_REGULATOR_ISL6271A is not set
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_LP3972 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_REGULATOR_MAX8649 is not set
-# CONFIG_REGULATOR_MAX8660 is not set
-# CONFIG_REGULATOR_MAX8952 is not set
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_REGULATOR_TPS6524X is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_RESOURCE_COUNTERS is not set
-# CONFIG_RFKILL_REGULATOR is not set
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_SCHED_AUTOGROUP=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SENSORS_AK8975 is not set
-# CONFIG_SENSORS_HMC5843 is not set
-# CONFIG_SENSORS_ISL29018 is not set
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_TSL2563=m
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_OMAP=y
-CONFIG_SERIAL_OMAP_CONSOLE=y
-CONFIG_SERIO=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SLAB is not set
-CONFIG_SLHC=m
-CONFIG_SLUB=y
-CONFIG_SND=m
-CONFIG_SND_ARM=y
-# CONFIG_SND_EMU10K1_SEQ is not set
-CONFIG_SND_JACK=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_OMAP_SOC=m
-CONFIG_SND_OMAP_SOC_MCBSP=m
-CONFIG_SND_OMAP_SOC_N810=m
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-CONFIG_SND_PCM=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-CONFIG_SND_SOC=m
-# CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_I2C_AND_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X=m
-CONFIG_SND_SPI=y
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_TIMER=m
-CONFIG_SOC_OMAP2420=y
-# CONFIG_SOC_OMAP2430 is not set
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPEAKUP=m
-CONFIG_SPEAKUP_SYNTH_ACNTPC=m
-CONFIG_SPEAKUP_SYNTH_ACNTSA=m
-CONFIG_SPEAKUP_SYNTH_APOLLO=m
-CONFIG_SPEAKUP_SYNTH_AUDPTR=m
-CONFIG_SPEAKUP_SYNTH_BNS=m
-CONFIG_SPEAKUP_SYNTH_DECEXT=m
-CONFIG_SPEAKUP_SYNTH_DECPC=m
-CONFIG_SPEAKUP_SYNTH_DECTLK=m
-CONFIG_SPEAKUP_SYNTH_DTLK=m
-CONFIG_SPEAKUP_SYNTH_DUMMY=m
-CONFIG_SPEAKUP_SYNTH_KEYPC=m
-CONFIG_SPEAKUP_SYNTH_LTLK=m
-CONFIG_SPEAKUP_SYNTH_SOFT=m
-CONFIG_SPEAKUP_SYNTH_SPKOUT=m
-CONFIG_SPEAKUP_SYNTH_TXPRT=m
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_OMAP24XX=y
-CONFIG_SPI_TSC2301=y
-# CONFIG_SPI_TSC2301_AUDIO is not set
-CONFIG_STP=m
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_BACKCHANNEL=y
-CONFIG_SUNRPC_GSS=m
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_SYN_COOKIES is not set
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_TABLET_USB_ACECAD is not set
-# CONFIG_TABLET_USB_AIPTEK is not set
-# CONFIG_TABLET_USB_GTCO is not set
-# CONFIG_TABLET_USB_HANWANG is not set
-# CONFIG_TABLET_USB_KBTAB is not set
-# CONFIG_TABLET_USB_WACOM is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TINY_PREEMPT_RCU=y
-CONFIG_TMPFS_POSIX_ACL=y
-# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_BU21013 is not set
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_EGALAX is not set
-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_MAX11801 is not set
-# CONFIG_TOUCHSCREEN_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_ST1232 is not set
-CONFIG_TOUCHSCREEN_TSC2005=y
-CONFIG_TOUCHSCREEN_TSC2301=y
-# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
-# CONFIG_TSL2583 is not set
-CONFIG_TUN=m
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_UID16=y
-CONFIG_USB=m
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB_ARCH_HAS_XHCI is not set
-# CONFIG_USB_AUDIO is not set
-CONFIG_USB_COMMON=m
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_EEM is not set
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_USB_GADGET_MUSB_HDRC=m
-CONFIG_USB_GADGET_VBUS_DRAW=100
-CONFIG_USB_GSPCA=m
-CONFIG_USB_G_NCM=m
-CONFIG_USB_HID=m
-# CONFIG_USB_MUSB_AM35X is not set
-CONFIG_USB_MUSB_HDRC=m
-# CONFIG_USB_MUSB_OMAP2PLUS is not set
-CONFIG_USB_MUSB_TUSB6010=m
-CONFIG_USB_NET_CDC_NCM=m
-# CONFIG_USB_OMAP is not set
-CONFIG_USB_OTG_UTILS=y
-# CONFIG_USB_PWC is not set
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_TUSB_OMAP_DMA=y
-CONFIG_USB_USBNET=m
-# CONFIG_USER_NS is not set
-# CONFIG_V4L_PLATFORM_DRIVERS is not set
-CONFIG_V4L_USB_DRIVERS=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_CPIA2 is not set
-CONFIG_VIDEO_DEV=m
-CONFIG_VIDEO_IR_I2C=m
-CONFIG_VIDEO_MEDIA=m
-CONFIG_VIDEO_TCM825X=m
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_COMMON=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_WATCHDOG_NOWAYOUT=y
-# CONFIG_WEXT_PRIV is not set
-# CONFIG_WEXT_SPY is not set
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-# CONFIG_ZBOOT_ROM is not set
-CONFIG_ZBOOT_ROM_BSS=0x10200000
-CONFIG_ZBOOT_ROM_TEXT=0x10C08000
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-NAND_BLOCKSIZE=2048:128k
-
-define Image/BuildKernel
- $(CP) $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage
- chmod 0644 $(BIN_DIR)/$(IMG_PREFIX)-zImage
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-root.$(1))
-endef
-
-define Image/Build
- $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-root.$(1)
- $(call Image/Build/$(1),$(1))
-endef
-
-
-$(eval $(call BuildImage))
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define KernelPackage/sound-soc-omap
- TITLE:=OMAP SoC sound support
- KCONFIG:= \
- CONFIG_SND_OMAP_SOC
- FILES:=$(LINUX_DIR)/sound/soc/omap/snd-soc-omap.ko
- AUTOLOAD:=$(call AutoLoad,60,snd-soc-omap)
- DEPENDS:=@TARGET_omap24xx +kmod-sound-soc-core
- $(call AddDepends/sound)
-endef
-
-$(eval $(call KernelPackage,sound-soc-omap))
-
-
-define KernelPackage/sound-soc-omap-mcbsp
- TITLE:=OMAP SoC MCBSP support
- KCONFIG:= \
- CONFIG_SND_OMAP_SOC_MCBSP
- FILES:=$(LINUX_DIR)/sound/soc/omap/snd-soc-omap-mcbsp.ko
- AUTOLOAD:=$(call AutoLoad,61,snd-soc-omap-mcbsp)
- DEPENDS:=@TARGET_omap24xx +kmod-sound-soc-omap
- $(call AddDepends/sound)
-endef
-
-$(eval $(call KernelPackage,sound-soc-omap-mcbsp))
-
-
-define KernelPackage/sound-soc-n810
- TITLE:=Nokia n810 SoC sound support
- KCONFIG:= \
- CONFIG_SND_OMAP_SOC_N810
- FILES:= \
- $(LINUX_DIR)/sound/soc/codecs/snd-soc-tlv320aic3x.ko \
- $(LINUX_DIR)/sound/soc/omap/snd-soc-n810.ko
- AUTOLOAD:=$(call AutoLoad,65,snd-soc-tlv320aic3x snd-soc-n810)
- DEPENDS:=@TARGET_omap24xx +kmod-sound-soc-omap +kmod-sound-soc-omap-mcbsp
- $(call AddDepends/sound)
-endef
-
-$(eval $(call KernelPackage,sound-soc-n810))
-
-
-define KernelPackage/n810bm
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Nokia N810 battery management driver
- DEPENDS:=@TARGET_omap24xx
- KCONFIG:=CONFIG_N810BM
- FILES:=$(LINUX_DIR)/drivers/cbus/n810bm.ko
- AUTOLOAD:=$(call AutoLoad,01,n810bm)
-endef
-
-define KernelPackage/n810bm/description
- Nokia N810 battery management driver.
- Controls battery power management and battery charging.
-endef
-
-$(eval $(call KernelPackage,n810bm))
-
-
-define KernelPackage/usb-tahvo
- TITLE:=Support for Tahvo (Nokia n810) USB
- KCONFIG:= \
- CONFIG_CBUS_TAHVO_USB \
- CONFIG_CBUS_TAHVO_USB_HOST_BY_DEFAULT=n \
- CONFIG_USB_OHCI_HCD_OMAP1=y \
- CONFIG_USB_GADGET_DEBUG_FS=n
- DEPENDS:=@TARGET_omap24xx +kmod-usb-musb-tusb6010
- FILES:=$(LINUX_DIR)/drivers/cbus/tahvo-usb.ko
- AUTOLOAD:=$(call AutoLoad,45,tahvo-usb)
- $(call AddDepends/usb)
-endef
-
-define KernelPackage/usb-tahvo/description
- Kernel support for Nokia n810 USB OHCI controller.
-endef
-
-$(eval $(call KernelPackage,usb-tahvo))
+++ /dev/null
---- /dev/null
-+++ b/arch/arm/plat-omap/bootreason.c
-@@ -0,0 +1,79 @@
-+/*
-+ * linux/arch/arm/plat-omap/bootreason.c
-+ *
-+ * OMAP Bootreason passing
-+ *
-+ * Copyright (c) 2004 Nokia
-+ *
-+ * Written by David Weinehall <david.weinehall@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+#include <linux/proc_fs.h>
-+#include <linux/errno.h>
-+#include <plat/board.h>
-+
-+static char boot_reason[16];
-+
-+static int omap_bootreason_read_proc(char *page, char **start, off_t off,
-+ int count, int *eof, void *data)
-+{
-+ int len = 0;
-+
-+ len += sprintf(page + len, "%s\n", boot_reason);
-+
-+ *start = page + off;
-+
-+ if (len > off)
-+ len -= off;
-+ else
-+ len = 0;
-+
-+ return len < count ? len : count;
-+}
-+
-+static int __init bootreason_init(void)
-+{
-+ const struct omap_boot_reason_config *cfg;
-+ int reason_valid = 0;
-+
-+ cfg = omap_get_config(OMAP_TAG_BOOT_REASON, struct omap_boot_reason_config);
-+ if (cfg != NULL) {
-+ strncpy(boot_reason, cfg->reason_str, sizeof(cfg->reason_str));
-+ boot_reason[sizeof(cfg->reason_str)] = 0;
-+ reason_valid = 1;
-+ } else {
-+ /* Read the boot reason from the OMAP registers */
-+ }
-+
-+ if (!reason_valid)
-+ return -ENOENT;
-+
-+ printk(KERN_INFO "Bootup reason: %s\n", boot_reason);
-+
-+ if (!create_proc_read_entry("bootreason", S_IRUGO, NULL,
-+ omap_bootreason_read_proc, NULL))
-+ return -ENOMEM;
-+
-+ return 0;
-+}
-+
-+late_initcall(bootreason_init);
---- a/arch/arm/plat-omap/common.c
-+++ b/arch/arm/plat-omap/common.c
-@@ -24,18 +24,90 @@
-
- #include <plat/omap-secure.h>
-
-+#include <asm/setup.h>
-+
-
- #define NO_LENGTH_CHECK 0xffffffff
-
- struct omap_board_config_kernel *omap_board_config __initdata;
- int omap_board_config_size;
-
-+unsigned char omap_bootloader_tag[1024];
-+int omap_bootloader_tag_len;
-+
-+/* used by omap-smp.c and board-4430sdp.c */
-+void __iomem *gic_cpu_base_addr;
-+
-+#ifdef CONFIG_OMAP_BOOT_TAG
-+
-+static int __init parse_tag_omap(const struct tag *tag)
-+{
-+ u32 size = tag->hdr.size - (sizeof(tag->hdr) >> 2);
-+
-+ size <<= 2;
-+ if (size > sizeof(omap_bootloader_tag))
-+ return -1;
-+
-+ memcpy(omap_bootloader_tag, tag->u.omap.data, size);
-+ omap_bootloader_tag_len = size;
-+
-+ return 0;
-+}
-+
-+__tagtable(ATAG_BOARD, parse_tag_omap);
-+
-+#endif
-+
- static const void *__init get_config(u16 tag, size_t len,
- int skip, size_t *len_out)
- {
- struct omap_board_config_kernel *kinfo = NULL;
- int i;
-
-+#ifdef CONFIG_OMAP_BOOT_TAG
-+ struct omap_board_config_entry *info = NULL;
-+
-+ if (omap_bootloader_tag_len > 4)
-+ info = (struct omap_board_config_entry *) omap_bootloader_tag;
-+ while (info != NULL) {
-+ u8 *next;
-+
-+ if (info->tag == tag) {
-+ if (skip == 0)
-+ break;
-+ skip--;
-+ }
-+
-+ if ((info->len & 0x03) != 0) {
-+ /* We bail out to avoid an alignment fault */
-+ printk(KERN_ERR "OMAP peripheral config: Length (%d) not word-aligned (tag %04x)\n",
-+ info->len, info->tag);
-+ return NULL;
-+ }
-+ next = (u8 *) info + sizeof(*info) + info->len;
-+ if (next >= omap_bootloader_tag + omap_bootloader_tag_len)
-+ info = NULL;
-+ else
-+ info = (struct omap_board_config_entry *) next;
-+ }
-+ if (info != NULL) {
-+ /* Check the length as a lame attempt to check for
-+ * binary inconsistency. */
-+ if (len != NO_LENGTH_CHECK) {
-+ /* Word-align len */
-+ if (len & 0x03)
-+ len = (len + 3) & ~0x03;
-+ if (info->len != len) {
-+ printk(KERN_ERR "OMAP peripheral config: Length mismatch with tag %x (want %d, got %d)\n",
-+ tag, len, info->len);
-+ return NULL;
-+ }
-+ }
-+ if (len_out != NULL)
-+ *len_out = info->len;
-+ return info->data;
-+ }
-+#endif
- /* Try to find the config from the board-specific structures
- * in the kernel. */
- for (i = 0; i < omap_board_config_size; i++) {
---- /dev/null
-+++ b/arch/arm/plat-omap/component-version.c
-@@ -0,0 +1,64 @@
-+/*
-+ * linux/arch/arm/plat-omap/component-version.c
-+ *
-+ * Copyright (C) 2005 Nokia Corporation
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/err.h>
-+#include <linux/proc_fs.h>
-+#include <plat/board.h>
-+
-+static int component_version_read_proc(char *page, char **start, off_t off,
-+ int count, int *eof, void *data)
-+{
-+ int len, i;
-+ const struct omap_version_config *ver;
-+ char *p;
-+
-+ i = 0;
-+ p = page;
-+ while ((ver = omap_get_nr_config(OMAP_TAG_VERSION_STR,
-+ struct omap_version_config, i)) != NULL) {
-+ p += sprintf(p, "%-12s%s\n", ver->component, ver->version);
-+ i++;
-+ }
-+
-+ len = (p - page) - off;
-+ if (len < 0)
-+ len = 0;
-+
-+ *eof = (len <= count) ? 1 : 0;
-+ *start = page + off;
-+
-+ return len;
-+}
-+
-+static int __init component_version_init(void)
-+{
-+ if (omap_get_config(OMAP_TAG_VERSION_STR, struct omap_version_config) == NULL)
-+ return -ENODEV;
-+ if (!create_proc_read_entry("component_version", S_IRUGO, NULL,
-+ component_version_read_proc, NULL))
-+ return -ENOMEM;
-+
-+ return 0;
-+}
-+
-+static void __exit component_version_exit(void)
-+{
-+ remove_proc_entry("component_version", NULL);
-+}
-+
-+late_initcall(component_version_init);
-+module_exit(component_version_exit);
-+
-+MODULE_AUTHOR("Juha Yrjölä <juha.yrjola@nokia.com>");
-+MODULE_DESCRIPTION("Component version driver");
-+MODULE_LICENSE("GPL");
---- a/arch/arm/plat-omap/Kconfig
-+++ b/arch/arm/plat-omap/Kconfig
-@@ -84,6 +84,38 @@ config OMAP_RESET_CLOCKS
- probably do not want this option enabled until your
- device drivers work properly.
-
-+config OMAP_BOOT_TAG
-+ bool "OMAP bootloader information passing"
-+ depends on ARCH_OMAP
-+ default n
-+ help
-+ Say Y, if you have a bootloader which passes information
-+ about your board and its peripheral configuration.
-+
-+config OMAP_BOOT_REASON
-+ bool "Support for boot reason"
-+ depends on OMAP_BOOT_TAG
-+ default n
-+ help
-+ Say Y, if you want to have a procfs entry for reading the boot
-+ reason in user-space.
-+
-+config OMAP_COMPONENT_VERSION
-+ bool "Support for component version display"
-+ depends on OMAP_BOOT_TAG && PROC_FS
-+ default n
-+ help
-+ Say Y, if you want to have a procfs entry for reading component
-+ versions (supplied by the bootloader) in user-space.
-+
-+config OMAP_GPIO_SWITCH
-+ bool "GPIO switch support"
-+ help
-+ Say Y, if you want to have support for reporting of GPIO
-+ switches (e.g. cover switches) via sysfs. Your bootloader has
-+ to provide information about the switches to the kernel via the
-+ ATAG_BOARD mechanism if they're not defined by the board config.
-+
- config OMAP_MUX
- bool "OMAP multiplexing support"
- depends on ARCH_OMAP
---- a/arch/arm/plat-omap/Makefile
-+++ b/arch/arm/plat-omap/Makefile
-@@ -20,6 +20,9 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_device.
- obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
-
- obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
-+obj-$(CONFIG_OMAP_BOOT_REASON) += bootreason.o
-+obj-$(CONFIG_OMAP_COMPONENT_VERSION) += component-version.o
-+obj-$(CONFIG_OMAP_GPIO_SWITCH) += gpio-switch.o
- obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
- obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
- i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
---- a/arch/arm/include/asm/setup.h
-+++ b/arch/arm/include/asm/setup.h
-@@ -136,6 +136,13 @@ struct tag_acorn {
- __u8 adfsdrives;
- };
-
-+/* TI OMAP specific information */
-+#define ATAG_BOARD 0x414f4d50
-+
-+struct tag_omap {
-+ u8 data[0];
-+};
-+
- /* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */
- #define ATAG_MEMCLK 0x41000402
-
-@@ -162,6 +169,11 @@ struct tag {
- struct tag_acorn acorn;
-
- /*
-+ * OMAP specific
-+ */
-+ struct tag_omap omap;
-+
-+ /*
- * DC21285 specific
- */
- struct tag_memclk memclk;
---- /dev/null
-+++ b/arch/arm/plat-omap/gpio-switch.c
-@@ -0,0 +1,554 @@
-+/*
-+ * linux/arch/arm/plat-omap/gpio-switch.c
-+ *
-+ * Copyright (C) 2004-2006 Nokia Corporation
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
-+ * and Paul Mundt <paul.mundt@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/sched.h>
-+#include <linux/init.h>
-+#include <linux/list.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/timer.h>
-+#include <linux/err.h>
-+#include <linux/slab.h>
-+#include <linux/gpio.h>
-+#include <plat/hardware.h>
-+#include <plat/irqs.h>
-+#include <plat/mux.h>
-+#include <plat/board.h>
-+#include <plat/gpio-switch.h>
-+
-+struct gpio_switch {
-+ char name[14];
-+ u16 gpio;
-+ unsigned flags:4;
-+ unsigned type:4;
-+ unsigned state:1;
-+ unsigned both_edges:1;
-+
-+ u16 debounce_rising;
-+ u16 debounce_falling;
-+
-+ void (* notify)(void *data, int state);
-+ void *notify_data;
-+
-+ struct work_struct work;
-+ struct timer_list timer;
-+ struct platform_device pdev;
-+
-+ struct list_head node;
-+};
-+
-+static LIST_HEAD(gpio_switches);
-+static struct platform_device *gpio_sw_platform_dev;
-+static struct platform_driver gpio_sw_driver;
-+
-+static const struct omap_gpio_switch *board_gpio_sw_table;
-+static int board_gpio_sw_count;
-+
-+static const char *cover_str[2] = { "open", "closed" };
-+static const char *connection_str[2] = { "disconnected", "connected" };
-+static const char *activity_str[2] = { "inactive", "active" };
-+
-+/*
-+ * GPIO switch state default debounce delay in ms
-+ */
-+#define OMAP_GPIO_SW_DEFAULT_DEBOUNCE 10
-+
-+static const char **get_sw_str(struct gpio_switch *sw)
-+{
-+ switch (sw->type) {
-+ case OMAP_GPIO_SWITCH_TYPE_COVER:
-+ return cover_str;
-+ case OMAP_GPIO_SWITCH_TYPE_CONNECTION:
-+ return connection_str;
-+ case OMAP_GPIO_SWITCH_TYPE_ACTIVITY:
-+ return activity_str;
-+ default:
-+ BUG();
-+ return NULL;
-+ }
-+}
-+
-+static const char *get_sw_type(struct gpio_switch *sw)
-+{
-+ switch (sw->type) {
-+ case OMAP_GPIO_SWITCH_TYPE_COVER:
-+ return "cover";
-+ case OMAP_GPIO_SWITCH_TYPE_CONNECTION:
-+ return "connection";
-+ case OMAP_GPIO_SWITCH_TYPE_ACTIVITY:
-+ return "activity";
-+ default:
-+ BUG();
-+ return NULL;
-+ }
-+}
-+
-+static void print_sw_state(struct gpio_switch *sw, int state)
-+{
-+ const char **str;
-+
-+ str = get_sw_str(sw);
-+ if (str != NULL)
-+ printk(KERN_INFO "%s (GPIO %d) is now %s\n", sw->name, sw->gpio, str[state]);
-+}
-+
-+static int gpio_sw_get_state(struct gpio_switch *sw)
-+{
-+ int state;
-+
-+ state = gpio_get_value(sw->gpio);
-+ if (sw->flags & OMAP_GPIO_SWITCH_FLAG_INVERTED)
-+ state = !state;
-+
-+ return state;
-+}
-+
-+static ssize_t gpio_sw_state_store(struct device *dev,
-+ struct device_attribute *attr,
-+ const char *buf,
-+ size_t count)
-+{
-+ struct gpio_switch *sw = dev_get_drvdata(dev);
-+ const char **str;
-+ char state[16];
-+ int enable;
-+
-+ if (!(sw->flags & OMAP_GPIO_SWITCH_FLAG_OUTPUT))
-+ return -EPERM;
-+
-+ if (sscanf(buf, "%15s", state) != 1)
-+ return -EINVAL;
-+
-+ str = get_sw_str(sw);
-+ if (strcmp(state, str[0]) == 0)
-+ sw->state = enable = 0;
-+ else if (strcmp(state, str[1]) == 0)
-+ sw->state = enable = 1;
-+ else
-+ return -EINVAL;
-+
-+ if (sw->flags & OMAP_GPIO_SWITCH_FLAG_INVERTED)
-+ enable = !enable;
-+ gpio_set_value(sw->gpio, enable);
-+
-+ return count;
-+}
-+
-+static ssize_t gpio_sw_state_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct gpio_switch *sw = dev_get_drvdata(dev);
-+ const char **str;
-+
-+ str = get_sw_str(sw);
-+ return sprintf(buf, "%s\n", str[sw->state]);
-+}
-+
-+static DEVICE_ATTR(state, S_IRUGO | S_IWUSR, gpio_sw_state_show,
-+ gpio_sw_state_store);
-+
-+static ssize_t gpio_sw_type_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct gpio_switch *sw = dev_get_drvdata(dev);
-+
-+ return sprintf(buf, "%s\n", get_sw_type(sw));
-+}
-+
-+static DEVICE_ATTR(type, S_IRUGO, gpio_sw_type_show, NULL);
-+
-+static ssize_t gpio_sw_direction_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct gpio_switch *sw = dev_get_drvdata(dev);
-+ int is_output;
-+
-+ is_output = sw->flags & OMAP_GPIO_SWITCH_FLAG_OUTPUT;
-+ return sprintf(buf, "%s\n", is_output ? "output" : "input");
-+}
-+
-+static DEVICE_ATTR(direction, S_IRUGO, gpio_sw_direction_show, NULL);
-+
-+
-+static irqreturn_t gpio_sw_irq_handler(int irq, void *arg)
-+{
-+ struct gpio_switch *sw = arg;
-+ unsigned long timeout;
-+ int state;
-+
-+ if (!sw->both_edges) {
-+ if (gpio_get_value(sw->gpio))
-+ irq_set_irq_type(OMAP_GPIO_IRQ(sw->gpio), IRQ_TYPE_EDGE_FALLING);
-+ else
-+ irq_set_irq_type(OMAP_GPIO_IRQ(sw->gpio), IRQ_TYPE_EDGE_RISING);
-+ }
-+
-+ state = gpio_sw_get_state(sw);
-+ if (sw->state == state)
-+ return IRQ_HANDLED;
-+
-+ if (state)
-+ timeout = sw->debounce_rising;
-+ else
-+ timeout = sw->debounce_falling;
-+ if (!timeout)
-+ schedule_work(&sw->work);
-+ else
-+ mod_timer(&sw->timer, jiffies + msecs_to_jiffies(timeout));
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static void gpio_sw_timer(unsigned long arg)
-+{
-+ struct gpio_switch *sw = (struct gpio_switch *) arg;
-+
-+ schedule_work(&sw->work);
-+}
-+
-+static void gpio_sw_handler(struct work_struct *work)
-+{
-+ struct gpio_switch *sw = container_of(work, struct gpio_switch, work);
-+ int state;
-+
-+ state = gpio_sw_get_state(sw);
-+ if (sw->state == state)
-+ return;
-+
-+ sw->state = state;
-+ if (sw->notify != NULL)
-+ sw->notify(sw->notify_data, state);
-+ sysfs_notify(&sw->pdev.dev.kobj, NULL, "state");
-+ print_sw_state(sw, state);
-+}
-+
-+static int __init can_do_both_edges(struct gpio_switch *sw)
-+{
-+ if (!cpu_class_is_omap1())
-+ return 1;
-+ if (OMAP_GPIO_IS_MPUIO(sw->gpio))
-+ return 0;
-+ else
-+ return 1;
-+}
-+
-+static void gpio_sw_release(struct device *dev)
-+{
-+}
-+
-+static int __init new_switch(struct gpio_switch *sw)
-+{
-+ int r, direction, trigger;
-+
-+ switch (sw->type) {
-+ case OMAP_GPIO_SWITCH_TYPE_COVER:
-+ case OMAP_GPIO_SWITCH_TYPE_CONNECTION:
-+ case OMAP_GPIO_SWITCH_TYPE_ACTIVITY:
-+ break;
-+ default:
-+ printk(KERN_ERR "invalid GPIO switch type: %d\n", sw->type);
-+ return -EINVAL;
-+ }
-+
-+ sw->pdev.name = sw->name;
-+ sw->pdev.id = -1;
-+
-+ sw->pdev.dev.parent = &gpio_sw_platform_dev->dev;
-+ sw->pdev.dev.driver = &gpio_sw_driver.driver;
-+ sw->pdev.dev.release = gpio_sw_release;
-+
-+ r = platform_device_register(&sw->pdev);
-+ if (r) {
-+ printk(KERN_ERR "gpio-switch: platform device registration "
-+ "failed for %s", sw->name);
-+ return r;
-+ }
-+ dev_set_drvdata(&sw->pdev.dev, sw);
-+
-+ r = gpio_request(sw->gpio, "gpio-switch");
-+ if (r < 0) {
-+ platform_device_unregister(&sw->pdev);
-+ return r;
-+ }
-+
-+ /* input: 1, output: 0 */
-+ direction = !(sw->flags & OMAP_GPIO_SWITCH_FLAG_OUTPUT);
-+ if (direction)
-+ gpio_direction_input(sw->gpio);
-+ else
-+ gpio_direction_output(sw->gpio, 0);
-+
-+ sw->state = gpio_sw_get_state(sw);
-+
-+ r = 0;
-+ r |= device_create_file(&sw->pdev.dev, &dev_attr_state);
-+ r |= device_create_file(&sw->pdev.dev, &dev_attr_type);
-+ r |= device_create_file(&sw->pdev.dev, &dev_attr_direction);
-+ if (r)
-+ printk(KERN_ERR "gpio-switch: attribute file creation "
-+ "failed for %s\n", sw->name);
-+
-+ if (!direction)
-+ return 0;
-+
-+ if (can_do_both_edges(sw)) {
-+ trigger = IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING;
-+ sw->both_edges = 1;
-+ } else {
-+ if (gpio_get_value(sw->gpio))
-+ trigger = IRQF_TRIGGER_FALLING;
-+ else
-+ trigger = IRQF_TRIGGER_RISING;
-+ }
-+ r = request_irq(OMAP_GPIO_IRQ(sw->gpio), gpio_sw_irq_handler,
-+ IRQF_SHARED | trigger, sw->name, sw);
-+ if (r < 0) {
-+ printk(KERN_ERR "gpio-switch: request_irq() failed "
-+ "for GPIO %d\n", sw->gpio);
-+ platform_device_unregister(&sw->pdev);
-+ gpio_free(sw->gpio);
-+ return r;
-+ }
-+
-+ INIT_WORK(&sw->work, gpio_sw_handler);
-+ init_timer(&sw->timer);
-+
-+ sw->timer.function = gpio_sw_timer;
-+ sw->timer.data = (unsigned long)sw;
-+
-+ list_add(&sw->node, &gpio_switches);
-+
-+ return 0;
-+}
-+
-+static int __init add_atag_switches(void)
-+{
-+ const struct omap_gpio_switch_config *cfg;
-+ struct gpio_switch *sw;
-+ int i, r;
-+
-+ for (i = 0; ; i++) {
-+ cfg = omap_get_nr_config(OMAP_TAG_GPIO_SWITCH,
-+ struct omap_gpio_switch_config, i);
-+ if (cfg == NULL)
-+ break;
-+ sw = kzalloc(sizeof(*sw), GFP_KERNEL);
-+ if (sw == NULL) {
-+ printk(KERN_ERR "gpio-switch: kmalloc failed\n");
-+ return -ENOMEM;
-+ }
-+ strncpy(sw->name, cfg->name, sizeof(cfg->name));
-+ sw->gpio = cfg->gpio;
-+ sw->flags = cfg->flags;
-+ sw->type = cfg->type;
-+ sw->debounce_rising = OMAP_GPIO_SW_DEFAULT_DEBOUNCE;
-+ sw->debounce_falling = OMAP_GPIO_SW_DEFAULT_DEBOUNCE;
-+ if ((r = new_switch(sw)) < 0) {
-+ kfree(sw);
-+ return r;
-+ }
-+ }
-+ return 0;
-+}
-+
-+static struct gpio_switch * __init find_switch(int gpio, const char *name)
-+{
-+ struct gpio_switch *sw;
-+
-+ list_for_each_entry(sw, &gpio_switches, node) {
-+ if ((gpio < 0 || sw->gpio != gpio) &&
-+ (name == NULL || strcmp(sw->name, name) != 0))
-+ continue;
-+
-+ if (gpio < 0 || name == NULL)
-+ goto no_check;
-+
-+ if (strcmp(sw->name, name) != 0)
-+ printk("gpio-switch: name mismatch for %d (%s, %s)\n",
-+ gpio, name, sw->name);
-+ else if (sw->gpio != gpio)
-+ printk("gpio-switch: GPIO mismatch for %s (%d, %d)\n",
-+ name, gpio, sw->gpio);
-+no_check:
-+ return sw;
-+ }
-+ return NULL;
-+}
-+
-+static int __init add_board_switches(void)
-+{
-+ int i;
-+
-+ for (i = 0; i < board_gpio_sw_count; i++) {
-+ const struct omap_gpio_switch *cfg;
-+ struct gpio_switch *sw;
-+ int r;
-+
-+ cfg = board_gpio_sw_table + i;
-+ if (strlen(cfg->name) > sizeof(sw->name) - 1)
-+ return -EINVAL;
-+ /* Check whether we only update an existing switch
-+ * or add a new switch. */
-+ sw = find_switch(cfg->gpio, cfg->name);
-+ if (sw != NULL) {
-+ sw->debounce_rising = cfg->debounce_rising;
-+ sw->debounce_falling = cfg->debounce_falling;
-+ sw->notify = cfg->notify;
-+ sw->notify_data = cfg->notify_data;
-+ continue;
-+ } else {
-+ if (cfg->gpio < 0 || cfg->name == NULL) {
-+ printk("gpio-switch: required switch not "
-+ "found (%d, %s)\n", cfg->gpio,
-+ cfg->name);
-+ continue;
-+ }
-+ }
-+ sw = kzalloc(sizeof(*sw), GFP_KERNEL);
-+ if (sw == NULL) {
-+ printk(KERN_ERR "gpio-switch: kmalloc failed\n");
-+ return -ENOMEM;
-+ }
-+ strlcpy(sw->name, cfg->name, sizeof(sw->name));
-+ sw->gpio = cfg->gpio;
-+ sw->flags = cfg->flags;
-+ sw->type = cfg->type;
-+ sw->debounce_rising = cfg->debounce_rising;
-+ sw->debounce_falling = cfg->debounce_falling;
-+ sw->notify = cfg->notify;
-+ sw->notify_data = cfg->notify_data;
-+ if ((r = new_switch(sw)) < 0) {
-+ kfree(sw);
-+ return r;
-+ }
-+ }
-+ return 0;
-+}
-+
-+static void gpio_sw_cleanup(void)
-+{
-+ struct gpio_switch *sw = NULL, *old = NULL;
-+
-+ list_for_each_entry(sw, &gpio_switches, node) {
-+ if (old != NULL)
-+ kfree(old);
-+ flush_scheduled_work();
-+ del_timer_sync(&sw->timer);
-+
-+ free_irq(OMAP_GPIO_IRQ(sw->gpio), sw);
-+
-+ device_remove_file(&sw->pdev.dev, &dev_attr_state);
-+ device_remove_file(&sw->pdev.dev, &dev_attr_type);
-+ device_remove_file(&sw->pdev.dev, &dev_attr_direction);
-+
-+ platform_device_unregister(&sw->pdev);
-+ gpio_free(sw->gpio);
-+ old = sw;
-+ }
-+ kfree(old);
-+}
-+
-+static void __init report_initial_state(void)
-+{
-+ struct gpio_switch *sw;
-+
-+ list_for_each_entry(sw, &gpio_switches, node) {
-+ int state;
-+
-+ state = gpio_get_value(sw->gpio);
-+ if (sw->flags & OMAP_GPIO_SWITCH_FLAG_INVERTED)
-+ state = !state;
-+ if (sw->notify != NULL)
-+ sw->notify(sw->notify_data, state);
-+ print_sw_state(sw, state);
-+ }
-+}
-+
-+static int gpio_sw_remove(struct platform_device *dev)
-+{
-+ return 0;
-+}
-+
-+static struct platform_driver gpio_sw_driver = {
-+ .remove = gpio_sw_remove,
-+ .driver = {
-+ .name = "gpio-switch",
-+ },
-+};
-+
-+void __init omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
-+ int count)
-+{
-+ BUG_ON(board_gpio_sw_table != NULL);
-+
-+ board_gpio_sw_table = tbl;
-+ board_gpio_sw_count = count;
-+}
-+
-+static int __init gpio_sw_init(void)
-+{
-+ int r;
-+
-+ printk(KERN_INFO "OMAP GPIO switch handler initializing\n");
-+
-+ r = platform_driver_register(&gpio_sw_driver);
-+ if (r)
-+ return r;
-+
-+ gpio_sw_platform_dev = platform_device_register_simple("gpio-switch",
-+ -1, NULL, 0);
-+ if (IS_ERR(gpio_sw_platform_dev)) {
-+ r = PTR_ERR(gpio_sw_platform_dev);
-+ goto err1;
-+ }
-+
-+ r = add_atag_switches();
-+ if (r < 0)
-+ goto err2;
-+
-+ r = add_board_switches();
-+ if (r < 0)
-+ goto err2;
-+
-+ report_initial_state();
-+
-+ return 0;
-+err2:
-+ gpio_sw_cleanup();
-+ platform_device_unregister(gpio_sw_platform_dev);
-+err1:
-+ platform_driver_unregister(&gpio_sw_driver);
-+ return r;
-+}
-+
-+static void __exit gpio_sw_exit(void)
-+{
-+ gpio_sw_cleanup();
-+ platform_device_unregister(gpio_sw_platform_dev);
-+ platform_driver_unregister(&gpio_sw_driver);
-+}
-+
-+#ifndef MODULE
-+late_initcall(gpio_sw_init);
-+#else
-+module_init(gpio_sw_init);
-+#endif
-+module_exit(gpio_sw_exit);
-+
-+MODULE_AUTHOR("Juha Yrjölä <juha.yrjola@nokia.com>, Paul Mundt <paul.mundt@nokia.com");
-+MODULE_DESCRIPTION("GPIO switch driver");
-+MODULE_LICENSE("GPL");
---- a/arch/arm/plat-omap/include/plat/board.h
-+++ b/arch/arm/plat-omap/include/plat/board.h
-@@ -151,6 +151,14 @@ struct omap_board_config_kernel {
- const void *data;
- };
-
-+struct omap_gpio_switch_config {
-+ char name[12];
-+ u16 gpio;
-+ int flags:4;
-+ int type:4;
-+ int key_code:24; /* Linux key code */
-+};
-+
- extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
-
- #define omap_get_config(tag, type) \
+++ /dev/null
---- /dev/null
-+++ b/drivers/cbus/cbus.c
-@@ -0,0 +1,335 @@
-+/*
-+ * drivers/cbus/cbus.c
-+ *
-+ * Support functions for CBUS serial protocol
-+ *
-+ * Copyright (C) 2004-2010 Nokia Corporation
-+ * Contact: Felipe Balbi <felipe.balbi@nokia.com>
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
-+ * David Weinehall <david.weinehall@nokia.com>, and
-+ * Mikko Ylinen <mikko.k.ylinen@nokia.com>
-+ *
-+ * Several updates and cleanups by Felipe Balbi <felipe.balbi@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/export.h>
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+#include <linux/gpio.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/cbus.h>
-+
-+#include "cbus.h"
-+
-+#define CBUS_XFER_READ 1
-+#define CBUS_XFER_WRITE 0
-+
-+struct cbus_host {
-+ /* host lock */
-+ spinlock_t lock;
-+
-+ struct device *dev;
-+
-+ int clk_gpio;
-+ int dat_gpio;
-+ int sel_gpio;
-+};
-+
-+/**
-+ * cbus_send_bit - sends one bit over the bus
-+ * @host: the host we're using
-+ * @bit: one bit of information to send
-+ * @input: whether to set data pin as input after sending
-+ */
-+static int cbus_send_bit(struct cbus_host *host, unsigned bit,
-+ unsigned input)
-+{
-+ int ret = 0;
-+
-+ gpio_set_value(host->dat_gpio, bit ? 1 : 0);
-+ gpio_set_value(host->clk_gpio, 1);
-+
-+ /* The data bit is read on the rising edge of CLK */
-+ if (input)
-+ ret = gpio_direction_input(host->dat_gpio);
-+
-+ gpio_set_value(host->clk_gpio, 0);
-+
-+ return ret;
-+}
-+
-+/**
-+ * cbus_send_data - sends @len amount of data over the bus
-+ * @host: the host we're using
-+ * @data: the data to send
-+ * @len: size of the transfer
-+ * @input: whether to set data pin as input after sending
-+ */
-+static int cbus_send_data(struct cbus_host *host, unsigned data, unsigned len,
-+ unsigned input)
-+{
-+ int ret = 0;
-+ int i;
-+
-+ for (i = len; i > 0; i--) {
-+ ret = cbus_send_bit(host, data & (1 << (i - 1)),
-+ input && (i == 1));
-+ if (ret < 0)
-+ goto out;
-+ }
-+
-+out:
-+ return ret;
-+}
-+
-+/**
-+ * cbus_receive_bit - receives one bit from the bus
-+ * @host: the host we're using
-+ */
-+static int cbus_receive_bit(struct cbus_host *host)
-+{
-+ int ret;
-+
-+ gpio_set_value(host->clk_gpio, 1);
-+ ret = gpio_get_value(host->dat_gpio);
-+ if (ret < 0)
-+ goto out;
-+ gpio_set_value(host->clk_gpio, 0);
-+
-+out:
-+ return ret;
-+}
-+
-+/**
-+ * cbus_receive_data - receives @len data from the bus
-+ * @host: the host we're using
-+ * @len: the length of data to receive
-+ */
-+static int cbus_receive_data(struct cbus_host *host, unsigned len)
-+{
-+ int ret = 0;
-+ int i;
-+
-+ for (i = 16; i > 0; i--) {
-+ int bit = cbus_receive_bit(host);
-+
-+ if (bit < 0)
-+ goto out;
-+
-+ if (bit)
-+ ret |= 1 << (i - 1);
-+ }
-+
-+out:
-+ return ret;
-+}
-+
-+/**
-+ * cbus_transfer - transfers data over the bus
-+ * @host: the host we're using
-+ * @rw: read/write flag
-+ * @dev: device address
-+ * @reg: register address
-+ * @data: if @rw == 0 data to send otherwise 0
-+ */
-+static int cbus_transfer(struct cbus_host *host, unsigned rw, unsigned dev,
-+ unsigned reg, unsigned data)
-+{
-+ unsigned long flags;
-+ int input = 0;
-+ int ret = 0;
-+
-+ /* We don't want interrupts disturbing our transfer */
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ /* Reset state and start of transfer, SEL stays down during transfer */
-+ gpio_set_value(host->sel_gpio, 0);
-+
-+ /* Set the DAT pin to output */
-+ gpio_direction_output(host->dat_gpio, 1);
-+
-+ /* Send the device address */
-+ ret = cbus_send_data(host, dev, 3, 0);
-+ if (ret < 0) {
-+ dev_dbg(host->dev, "failed sending device addr\n");
-+ goto out;
-+ }
-+
-+ /* Send the rw flag */
-+ ret = cbus_send_bit(host, rw, 0);
-+ if (ret < 0) {
-+ dev_dbg(host->dev, "failed sending read/write flag\n");
-+ goto out;
-+ }
-+
-+ /* Send the register address */
-+ if (rw)
-+ input = true;
-+
-+ ret = cbus_send_data(host, reg, 5, input);
-+ if (ret < 0) {
-+ dev_dbg(host->dev, "failed sending register addr\n");
-+ goto out;
-+ }
-+
-+ if (!rw) {
-+ ret = cbus_send_data(host, data, 16, 0);
-+ if (ret < 0) {
-+ dev_dbg(host->dev, "failed sending data\n");
-+ goto out;
-+ }
-+ } else {
-+ gpio_set_value(host->clk_gpio, 1);
-+
-+ ret = cbus_receive_data(host, 16);
-+ if (ret < 0) {
-+ dev_dbg(host->dev, "failed receiving data\n");
-+ goto out;
-+ }
-+ }
-+
-+ /* Indicate end of transfer, SEL goes up until next transfer */
-+ gpio_set_value(host->sel_gpio, 1);
-+ gpio_set_value(host->clk_gpio, 1);
-+ gpio_set_value(host->clk_gpio, 0);
-+
-+out:
-+ spin_unlock_irqrestore(&host->lock, flags);
-+
-+ return ret;
-+}
-+
-+/**
-+ * cbus_read_reg - reads a given register from the device
-+ * @child: the child device
-+ * @dev: device address
-+ * @reg: register address
-+ */
-+int cbus_read_reg(struct device *child, unsigned dev, unsigned reg)
-+{
-+ struct cbus_host *host = dev_get_drvdata(child->parent);
-+
-+ return cbus_transfer(host, CBUS_XFER_READ, dev, reg, 0);
-+}
-+EXPORT_SYMBOL(cbus_read_reg);
-+
-+/**
-+ * cbus_write_reg - writes to a given register of the device
-+ * @child: the child device
-+ * @dev: device address
-+ * @reg: register address
-+ * @val: data to be written to @reg
-+ */
-+int cbus_write_reg(struct device *child, unsigned dev, unsigned reg,
-+ unsigned val)
-+{
-+ struct cbus_host *host = dev_get_drvdata(child->parent);
-+
-+ return cbus_transfer(host, CBUS_XFER_WRITE, dev, reg, val);
-+}
-+EXPORT_SYMBOL(cbus_write_reg);
-+
-+static int __init cbus_bus_probe(struct platform_device *pdev)
-+{
-+ struct cbus_host *chost;
-+ struct cbus_host_platform_data *pdata = pdev->dev.platform_data;
-+ int ret;
-+
-+ chost = kzalloc(sizeof(*chost), GFP_KERNEL);
-+ if (chost == NULL)
-+ return -ENOMEM;
-+
-+ spin_lock_init(&chost->lock);
-+
-+ chost->clk_gpio = pdata->clk_gpio;
-+ chost->dat_gpio = pdata->dat_gpio;
-+ chost->sel_gpio = pdata->sel_gpio;
-+ chost->dev = &pdev->dev;
-+
-+ ret = gpio_request(chost->clk_gpio, "CBUS clk");
-+ if (ret < 0)
-+ goto exit1;
-+
-+ ret = gpio_request(chost->dat_gpio, "CBUS data");
-+ if (ret < 0)
-+ goto exit2;
-+
-+ ret = gpio_request(chost->sel_gpio, "CBUS sel");
-+ if (ret < 0)
-+ goto exit3;
-+
-+ gpio_direction_output(chost->clk_gpio, 0);
-+ gpio_direction_input(chost->dat_gpio);
-+ gpio_direction_output(chost->sel_gpio, 1);
-+
-+ gpio_set_value(chost->clk_gpio, 1);
-+ gpio_set_value(chost->clk_gpio, 0);
-+
-+ platform_set_drvdata(pdev, chost);
-+
-+ return 0;
-+exit3:
-+ gpio_free(chost->dat_gpio);
-+exit2:
-+ gpio_free(chost->clk_gpio);
-+exit1:
-+ kfree(chost);
-+
-+ return ret;
-+}
-+
-+static void __exit cbus_bus_remove(struct platform_device *pdev)
-+{
-+ struct cbus_host *chost = platform_get_drvdata(pdev);
-+
-+ gpio_free(chost->sel_gpio);
-+ gpio_free(chost->dat_gpio);
-+ gpio_free(chost->clk_gpio);
-+
-+ kfree(chost);
-+}
-+
-+static struct platform_driver cbus_driver = {
-+ .remove = __exit_p(cbus_bus_remove),
-+ .driver = {
-+ .name = "cbus",
-+ },
-+};
-+
-+static int __init cbus_bus_init(void)
-+{
-+ return platform_driver_probe(&cbus_driver, cbus_bus_probe);
-+}
-+subsys_initcall(cbus_bus_init);
-+
-+static void __exit cbus_bus_exit(void)
-+{
-+ platform_driver_unregister(&cbus_driver);
-+}
-+module_exit(cbus_bus_exit);
-+
-+MODULE_DESCRIPTION("CBUS serial protocol");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Juha Yrjölä");
-+MODULE_AUTHOR("David Weinehall");
-+MODULE_AUTHOR("Mikko Ylinen");
-+MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>");
-+
---- /dev/null
-+++ b/drivers/cbus/cbus.h
-@@ -0,0 +1,30 @@
-+/*
-+ * drivers/cbus/cbus.h
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com> and
-+ * David Weinehall <david.weinehall@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __DRIVERS_CBUS_CBUS_H
-+#define __DRIVERS_CBUS_CBUS_H
-+
-+extern int cbus_read_reg(struct device *, unsigned dev, unsigned reg);
-+extern int cbus_write_reg(struct device *, unsigned dev, unsigned reg,
-+ unsigned val);
-+
-+#endif /* __DRIVERS_CBUS_CBUS_H */
---- /dev/null
-+++ b/drivers/cbus/Kconfig
-@@ -0,0 +1,86 @@
-+#
-+# CBUS device configuration
-+#
-+
-+menu "CBUS support"
-+
-+config CBUS
-+ bool "CBUS support on OMAP"
-+ ---help---
-+ CBUS is a proprietary serial protocol by Nokia. It is mainly
-+ used for accessing Energy Management auxiliary chips.
-+
-+ If you want CBUS support, you should say Y here.
-+
-+config CBUS_TAHVO
-+ depends on CBUS
-+ bool "Support for Tahvo"
-+ ---help---
-+ Tahvo is a mixed signal ASIC with some system features
-+
-+ If you want Tahvo support, you should say Y here.
-+
-+if CBUS_TAHVO
-+
-+config CBUS_TAHVO_USB
-+ depends on USB
-+ depends on ARCH_OMAP
-+ select USB_OTG_UTILS
-+ tristate "Support for Tahvo USB transceiver"
-+ ---help---
-+ If you want Tahvo support for USB transceiver, say Y or M here.
-+
-+config CBUS_TAHVO_USB_HOST_BY_DEFAULT
-+ depends on CBUS_TAHVO_USB && USB_OTG
-+ boolean "Device in USB host mode by default"
-+ ---help---
-+ Say Y here, if you want the device to enter USB host mode
-+ by default on bootup.
-+
-+endif # CBUS_TAHVO
-+
-+config CBUS_RETU
-+ depends on CBUS
-+ bool "Support for Retu"
-+ ---help---
-+ Retu is a mixed signal ASIC with some system features
-+
-+ If you want Retu support, you should say Y here.
-+
-+if CBUS_RETU
-+
-+config CBUS_RETU_POWERBUTTON
-+ depends on INPUT
-+ bool "Support for Retu power button"
-+ ---help---
-+ The power button on Nokia 770 is connected to the Retu ASIC.
-+
-+ If you want support for the Retu power button, you should say Y here.
-+
-+config CBUS_RETU_RTC
-+ depends on RTC_CLASS
-+ depends on ARCH_OMAP
-+ tristate "Support for Retu pseudo-RTC"
-+ ---help---
-+ Say Y here if you want support for the device that alleges to be an
-+ RTC in Retu. This will expose a sysfs interface for it.
-+
-+config CBUS_RETU_WDT
-+ depends on SYSFS && WATCHDOG
-+ depends on ARCH_OMAP
-+ tristate "Support for Retu watchdog timer"
-+ ---help---
-+ Say Y here if you want support for the watchdog in Retu. This will
-+ expose a sysfs interface to grok it.
-+
-+config CBUS_RETU_HEADSET
-+ depends on SYSFS
-+ tristate "Support for headset detection with Retu/Vilma"
-+ ---help---
-+ Say Y here if you want support detecting a headset that's connected
-+ to Retu/Vilma. Detection state and events are exposed through
-+ sysfs.
-+
-+endif # CBUS_RETU
-+
-+endmenu
---- /dev/null
-+++ b/drivers/cbus/Makefile
-@@ -0,0 +1,13 @@
-+#
-+# Makefile for CBUS.
-+#
-+
-+obj-$(CONFIG_CBUS) += cbus.o
-+obj-$(CONFIG_CBUS_TAHVO) += tahvo.o
-+obj-$(CONFIG_CBUS_RETU) += retu.o
-+obj-$(CONFIG_CBUS_TAHVO_USB) += tahvo-usb.o
-+
-+obj-$(CONFIG_CBUS_RETU_POWERBUTTON) += retu-pwrbutton.o
-+obj-$(CONFIG_CBUS_RETU_RTC) += retu-rtc.o
-+obj-$(CONFIG_CBUS_RETU_WDT) += retu-wdt.o
-+obj-$(CONFIG_CBUS_RETU_HEADSET) += retu-headset.o
---- /dev/null
-+++ b/drivers/cbus/retu.c
-@@ -0,0 +1,549 @@
-+/**
-+ * drivers/cbus/retu.c
-+ *
-+ * Support functions for Retu ASIC
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
-+ * David Weinehall <david.weinehall@nokia.com>, and
-+ * Mikko Ylinen <mikko.k.ylinen@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+
-+#include <linux/slab.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/device.h>
-+#include <linux/mutex.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/cbus.h>
-+
-+#include <asm/bitops.h>
-+
-+#include "cbus.h"
-+#include "retu.h"
-+
-+struct retu {
-+ /* Device lock */
-+ struct mutex mutex;
-+ struct device *dev;
-+
-+ int devid;
-+
-+ int irq_base;
-+ int irq_end;
-+
-+ int irq;
-+
-+ int ack;
-+ bool ack_pending;
-+
-+ int mask;
-+ bool mask_pending;
-+
-+ bool is_vilma;
-+};
-+
-+static struct retu *the_retu;
-+
-+/**
-+ * __retu_read_reg - Read a value from a register in Retu
-+ * @retu: pointer to retu structure
-+ * @reg: the register address to read from
-+ */
-+static int __retu_read_reg(struct retu *retu, unsigned reg)
-+{
-+ return cbus_read_reg(retu->dev, retu->devid, reg);
-+}
-+
-+/**
-+ * __retu_write_reg - Writes a value to a register in Retu
-+ * @retu: pointer to retu structure
-+ * @reg: the register address to write to
-+ * @val: the value to write to the register
-+ */
-+static void __retu_write_reg(struct retu *retu, unsigned reg, u16 val)
-+{
-+ cbus_write_reg(retu->dev, retu->devid, reg, val);
-+}
-+
-+/**
-+ * retu_read_reg - Read a value from a register in Retu
-+ * @child: device pointer for the calling child
-+ * @reg: the register to read from
-+ *
-+ * This function returns the contents of the specified register
-+ */
-+int retu_read_reg(struct device *child, unsigned reg)
-+{
-+ struct retu *retu = dev_get_drvdata(child->parent);
-+
-+ return __retu_read_reg(retu, reg);
-+}
-+EXPORT_SYMBOL_GPL(retu_read_reg);
-+
-+/**
-+ * retu_write_reg - Write a value to a register in Retu
-+ * @child: the pointer to our calling child
-+ * @reg: the register to write to
-+ * @val: the value to write to the register
-+ *
-+ * This function writes a value to the specified register
-+ */
-+void retu_write_reg(struct device *child, unsigned reg, u16 val)
-+{
-+ struct retu *retu = dev_get_drvdata(child->parent);
-+
-+ mutex_lock(&retu->mutex);
-+ __retu_write_reg(retu, reg, val);
-+ mutex_unlock(&retu->mutex);
-+}
-+EXPORT_SYMBOL_GPL(retu_write_reg);
-+
-+/**
-+ * retu_set_clear_reg_bits - helper function to read/set/clear bits
-+ * @child: device pointer to calling child
-+ * @reg: the register address
-+ * @set: mask for setting bits
-+ * @clear: mask for clearing bits
-+ */
-+void retu_set_clear_reg_bits(struct device *child, unsigned reg, u16 set,
-+ u16 clear)
-+{
-+ struct retu *retu = dev_get_drvdata(child->parent);
-+ u16 w;
-+
-+ mutex_lock(&retu->mutex);
-+ w = __retu_read_reg(retu, reg);
-+ w &= ~clear;
-+ w |= set;
-+ __retu_write_reg(retu, reg, w);
-+ mutex_unlock(&retu->mutex);
-+}
-+EXPORT_SYMBOL_GPL(retu_set_clear_reg_bits);
-+
-+#define ADC_MAX_CHAN_NUMBER 13
-+
-+/**
-+ * retu_read_adc - Reads AD conversion result
-+ * @child: device pointer to calling child
-+ * @channel: the ADC channel to read from
-+ */
-+int retu_read_adc(struct device *child, int channel)
-+{
-+ struct retu *retu = dev_get_drvdata(child->parent);
-+ int res;
-+
-+ if (!retu)
-+ return -ENODEV;
-+
-+ if (channel < 0 || channel > ADC_MAX_CHAN_NUMBER)
-+ return -EINVAL;
-+
-+ mutex_lock(&retu->mutex);
-+
-+ if ((channel == 8) && retu->is_vilma) {
-+ int scr = __retu_read_reg(retu, RETU_REG_ADCSCR);
-+ int ch = (__retu_read_reg(retu, RETU_REG_ADCR) >> 10) & 0xf;
-+ if (((scr & 0xff) != 0) && (ch != 8))
-+ __retu_write_reg(retu, RETU_REG_ADCSCR, (scr & ~0xff));
-+ }
-+
-+ /* Select the channel and read result */
-+ __retu_write_reg(retu, RETU_REG_ADCR, channel << 10);
-+ res = __retu_read_reg(retu, RETU_REG_ADCR) & 0x3ff;
-+
-+ if (retu->is_vilma)
-+ __retu_write_reg(retu, RETU_REG_ADCR, (1 << 13));
-+
-+ /* Unlock retu */
-+ mutex_unlock(&retu->mutex);
-+
-+ return res;
-+}
-+EXPORT_SYMBOL_GPL(retu_read_adc);
-+
-+static irqreturn_t retu_irq_handler(int irq, void *_retu)
-+{
-+ struct retu *retu = _retu;
-+
-+ u16 idr;
-+ u16 imr;
-+
-+ mutex_lock(&retu->mutex);
-+ idr = __retu_read_reg(retu, RETU_REG_IDR);
-+ imr = __retu_read_reg(retu, RETU_REG_IMR);
-+ mutex_unlock(&retu->mutex);
-+
-+ idr &= ~imr;
-+ if (!idr) {
-+ dev_vdbg(retu->dev, "No IRQ, spurious?\n");
-+ return IRQ_NONE;
-+ }
-+
-+ while (idr) {
-+ unsigned long pending = __ffs(idr);
-+ unsigned int irq;
-+
-+ idr &= ~BIT(pending);
-+ irq = pending + retu->irq_base;
-+ handle_nested_irq(irq);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+/* -------------------------------------------------------------------------- */
-+
-+static void retu_irq_mask(struct irq_data *data)
-+{
-+ struct retu *retu = irq_data_get_irq_chip_data(data);
-+ int irq = data->irq;
-+
-+ retu->mask |= (1 << (irq - retu->irq_base));
-+ retu->mask_pending = true;
-+}
-+
-+static void retu_irq_unmask(struct irq_data *data)
-+{
-+ struct retu *retu = irq_data_get_irq_chip_data(data);
-+ int irq = data->irq;
-+
-+ retu->mask &= ~(1 << (irq - retu->irq_base));
-+ retu->mask_pending = true;
-+
-+}
-+
-+static void retu_irq_ack(struct irq_data *data)
-+{
-+ struct retu *retu = irq_data_get_irq_chip_data(data);
-+ int irq = data->irq;
-+
-+ retu->ack |= (1 << (irq - retu->irq_base));
-+ retu->ack_pending = true;
-+}
-+
-+static void retu_bus_lock(struct irq_data *data)
-+{
-+ struct retu *retu = irq_data_get_irq_chip_data(data);
-+
-+ mutex_lock(&retu->mutex);
-+}
-+
-+static void retu_bus_sync_unlock(struct irq_data *data)
-+{
-+ struct retu *retu = irq_data_get_irq_chip_data(data);
-+
-+ if (retu->mask_pending) {
-+ __retu_write_reg(retu, RETU_REG_IMR, retu->mask);
-+ retu->mask_pending = false;
-+ }
-+
-+ if (retu->ack_pending) {
-+ __retu_write_reg(retu, RETU_REG_IDR, retu->ack);
-+ retu->ack_pending = false;
-+ }
-+
-+ mutex_unlock(&retu->mutex);
-+}
-+
-+static struct irq_chip retu_irq_chip = {
-+ .name = "retu",
-+ .irq_bus_lock = retu_bus_lock,
-+ .irq_bus_sync_unlock = retu_bus_sync_unlock,
-+ .irq_mask = retu_irq_mask,
-+ .irq_unmask = retu_irq_unmask,
-+ .irq_ack = retu_irq_ack,
-+};
-+
-+static inline void retu_irq_setup(int irq)
-+{
-+#ifdef CONFIG_ARM
-+ set_irq_flags(irq, IRQF_VALID);
-+#else
-+ irq_set_noprobe(irq);
-+#endif
-+}
-+
-+static void retu_irq_init(struct retu *retu)
-+{
-+ int base = retu->irq_base;
-+ int end = retu->irq_end;
-+ int irq;
-+
-+ for (irq = base; irq < end; irq++) {
-+ irq_set_chip_data(irq, retu);
-+ irq_set_chip_and_handler(irq, &retu_irq_chip,
-+ handle_simple_irq);
-+ irq_set_nested_thread(irq, 1);
-+ retu_irq_setup(irq);
-+ }
-+}
-+
-+static void retu_irq_exit(struct retu *retu)
-+{
-+ int base = retu->irq_base;
-+ int end = retu->irq_end;
-+ int irq;
-+
-+ for (irq = base; irq < end; irq++) {
-+#ifdef CONFIG_ARM
-+ set_irq_flags(irq, 0);
-+#endif
-+ irq_set_chip_and_handler(irq, NULL, NULL);
-+ irq_set_chip_data(irq, NULL);
-+ }
-+}
-+
-+/* -------------------------------------------------------------------------- */
-+
-+/**
-+ * retu_power_off - Shut down power to system
-+ *
-+ * This function puts the system in power off state
-+ */
-+static void retu_power_off(void)
-+{
-+ struct retu *retu = the_retu;
-+ unsigned reg;
-+
-+ reg = __retu_read_reg(retu, RETU_REG_CC1);
-+
-+ /* Ignore power button state */
-+ __retu_write_reg(retu, RETU_REG_CC1, reg | 2);
-+ /* Expire watchdog immediately */
-+ __retu_write_reg(retu, RETU_REG_WATCHDOG, 0);
-+ /* Wait for poweroff*/
-+ for (;;);
-+}
-+
-+static struct resource generic_resources[] = {
-+ {
-+ .start = -EINVAL, /* fixed later */
-+ .flags = IORESOURCE_IRQ,
-+ },
-+ {
-+ .start = -EINVAL, /* fixed later */
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+/**
-+ * retu_allocate_child - Allocates one Retu child
-+ * @name: name of new child
-+ * @parent: parent device for this child
-+ */
-+static struct device *retu_allocate_child(char *name, struct device *parent,
-+ int irq_base, int irq1, int irq2, int num)
-+{
-+ struct platform_device *pdev;
-+ int status;
-+
-+ pdev = platform_device_alloc(name, -1);
-+ if (!pdev) {
-+ dev_dbg(parent, "can't allocate %s\n", name);
-+ goto err;
-+ }
-+
-+ pdev->dev.parent = parent;
-+
-+ if (num) {
-+ generic_resources[0].start = irq_base + irq1;
-+ generic_resources[1].start = irq_base + irq2;
-+
-+ status = platform_device_add_resources(pdev,
-+ generic_resources, num);
-+ if (status < 0) {
-+ dev_dbg(parent, "can't add resources to %s\n", name);
-+ goto err;
-+ }
-+ }
-+
-+ status = platform_device_add(pdev);
-+ if (status < 0) {
-+ dev_dbg(parent, "can't add %s\n", name);
-+ goto err;
-+ }
-+
-+ return &pdev->dev;
-+
-+err:
-+ platform_device_put(pdev);
-+
-+ return NULL;
-+}
-+
-+/**
-+ * retu_allocate_children - Allocates Retu's children
-+ */
-+static int retu_allocate_children(struct device *parent, int irq_base)
-+{
-+ struct device *child;
-+
-+ child = retu_allocate_child("retu-pwrbutton", parent, irq_base,
-+ RETU_INT_PWR, -1, 1);
-+ if (!child)
-+ return -ENOMEM;
-+
-+ child = retu_allocate_child("retu-headset", parent, irq_base,
-+ RETU_INT_HOOK, -1, 1);
-+ if (!child)
-+ return -ENOMEM;
-+
-+ child = retu_allocate_child("retu-rtc", parent, irq_base,
-+ RETU_INT_RTCS, RETU_INT_RTCA, 2);
-+ if (!child)
-+ return -ENOMEM;
-+
-+ child = retu_allocate_child("retu-wdt", parent, -1, -1, -1, 0);
-+ if (!child)
-+ return -ENOMEM;
-+
-+ return 0;
-+}
-+
-+/**
-+ * retu_probe - Probe for Retu ASIC
-+ * @dev: the Retu device
-+ *
-+ * Probe for the Retu ASIC and allocate memory
-+ * for its device-struct if found
-+ */
-+static int __devinit retu_probe(struct platform_device *pdev)
-+{
-+ struct retu *retu;
-+ struct cbus_retu_platform_data *pdata = pdev->dev.platform_data;
-+
-+ int ret = -ENOMEM;
-+ int rev;
-+
-+ retu = kzalloc(sizeof(*retu), GFP_KERNEL);
-+ if (!retu) {
-+ dev_err(&pdev->dev, "not enough memory\n");
-+ goto err0;
-+ }
-+
-+ platform_set_drvdata(pdev, retu);
-+
-+ ret = irq_alloc_descs(-1, 0, MAX_RETU_IRQ_HANDLERS, 0);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "failed to allocate IRQ descs\n");
-+ goto err1;
-+ }
-+
-+ retu->irq = platform_get_irq(pdev, 0);
-+ retu->irq_base = ret;
-+ retu->irq_end = ret + MAX_RETU_IRQ_HANDLERS;
-+ retu->devid = pdata->devid;
-+ retu->dev = &pdev->dev;
-+ the_retu = retu;
-+
-+ mutex_init(&retu->mutex);
-+
-+ retu_irq_init(retu);
-+
-+ rev = __retu_read_reg(retu, RETU_REG_ASICR) & 0xff;
-+ if (rev & (1 << 7))
-+ retu->is_vilma = true;
-+
-+ dev_info(&pdev->dev, "%s v%d.%d found\n",
-+ retu->is_vilma ? "Vilma" : "Retu",
-+ (rev >> 4) & 0x07, rev & 0x0f);
-+
-+ /* Mask all RETU interrupts */
-+ __retu_write_reg(retu, RETU_REG_IMR, 0xffff);
-+
-+ ret = request_threaded_irq(retu->irq, NULL, retu_irq_handler,
-+ IRQF_ONESHOT, "retu", retu);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "Unable to register IRQ handler\n");
-+ goto err2;
-+ }
-+
-+ irq_set_irq_wake(retu->irq, 1);
-+
-+ /* Register power off function */
-+ pm_power_off = retu_power_off;
-+
-+ ret = retu_allocate_children(&pdev->dev, retu->irq_base);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "Unable to allocate Retu children\n");
-+ goto err3;
-+ }
-+
-+ return 0;
-+
-+err3:
-+ pm_power_off = NULL;
-+ free_irq(retu->irq, retu);
-+
-+err2:
-+ retu_irq_exit(retu);
-+ irq_free_descs(retu->irq_base, MAX_RETU_IRQ_HANDLERS);
-+
-+err1:
-+ kfree(retu);
-+ the_retu = NULL;
-+
-+err0:
-+ return ret;
-+}
-+
-+static int __devexit retu_remove(struct platform_device *pdev)
-+{
-+ struct retu *retu = platform_get_drvdata(pdev);
-+
-+ pm_power_off = NULL;
-+ the_retu = NULL;
-+
-+ free_irq(retu->irq, retu);
-+ retu_irq_exit(retu);
-+ irq_free_descs(retu->irq_base, MAX_RETU_IRQ_HANDLERS);
-+ kfree(retu);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver retu_driver = {
-+ .probe = retu_probe,
-+ .remove = __devexit_p(retu_remove),
-+ .driver = {
-+ .name = "retu",
-+ },
-+};
-+
-+static int __init retu_init(void)
-+{
-+ return platform_driver_register(&retu_driver);
-+}
-+subsys_initcall(retu_init);
-+
-+static void __exit retu_exit(void)
-+{
-+ platform_driver_unregister(&retu_driver);
-+}
-+module_exit(retu_exit);
-+
-+MODULE_DESCRIPTION("Retu ASIC control");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Juha Yrjölä");
-+MODULE_AUTHOR("David Weinehall");
-+MODULE_AUTHOR("Mikko Ylinen");
---- /dev/null
-+++ b/drivers/cbus/retu.h
-@@ -0,0 +1,85 @@
-+/**
-+ * drivers/cbus/retu.h
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com> and
-+ * David Weinehall <david.weinehall@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __DRIVERS_CBUS_RETU_H
-+#define __DRIVERS_CBUS_RETU_H
-+
-+#include <linux/types.h>
-+
-+/* Registers */
-+#define RETU_REG_ASICR 0x00 /* ASIC ID & revision */
-+#define RETU_REG_IDR 0x01 /* Interrupt ID */
-+#define RETU_REG_IMR 0x02 /* Interrupt mask */
-+#define RETU_REG_RTCDSR 0x03 /* RTC seconds register */
-+#define RETU_REG_RTCHMR 0x04 /* RTC hours and minutes register */
-+#define RETU_REG_RTCHMAR 0x05 /* RTC hours and minutes alarm and time set register */
-+#define RETU_REG_RTCCALR 0x06 /* RTC calibration register */
-+#define RETU_REG_ADCR 0x08 /* ADC result */
-+#define RETU_REG_ADCSCR 0x09 /* ADC sample ctrl */
-+#define RETU_REG_CC1 0x0d /* Common control register 1 */
-+#define RETU_REG_CC2 0x0e /* Common control register 2 */
-+#define RETU_REG_CTRL_CLR 0x0f /* Regulator clear register */
-+#define RETU_REG_CTRL_SET 0x10 /* Regulator set register */
-+#define RETU_REG_STATUS 0x16 /* Status register */
-+#define RETU_REG_STATUS_BATAVAIL 0x0100 /* Battery available */
-+#define RETU_REG_STATUS_CHGPLUG 0x1000 /* Charger is plugged in */
-+#define RETU_REG_WATCHDOG 0x17 /* Watchdog register */
-+#define RETU_REG_AUDTXR 0x18 /* Audio Codec Tx register */
-+#define RETU_REG_MAX 0x1f
-+
-+/* Interrupt sources */
-+#define RETU_INT_PWR 0
-+#define RETU_INT_CHAR 1
-+#define RETU_INT_RTCS 2
-+#define RETU_INT_RTCM 3
-+#define RETU_INT_RTCD 4
-+#define RETU_INT_RTCA 5
-+#define RETU_INT_HOOK 6
-+#define RETU_INT_HEAD 7
-+#define RETU_INT_ADCS 8
-+
-+#define MAX_RETU_IRQ_HANDLERS 16
-+
-+/* ADC channels */
-+#define RETU_ADC_GND 0x00 /* Ground */
-+#define RETU_ADC_BSI 0x01 /* Battery Size Indicator */
-+#define RETU_ADC_BATTEMP 0x02 /* Battery temperature */
-+#define RETU_ADC_CHGVOLT 0x03 /* Charger voltage */
-+#define RETU_ADC_HEADSET 0x04 /* Headset detection */
-+#define RETU_ADC_HOOKDET 0x05 /* Hook detection */
-+#define RETU_ADC_RFGP 0x06 /* RF GP */
-+#define RETU_ADC_WBTX 0x07 /* Wideband Tx detection */
-+#define RETU_ADC_BATTVOLT 0x08 /* Battery voltage measurement */
-+#define RETU_ADC_GND2 0x09 /* Ground */
-+#define RETU_ADC_LIGHTSENS 0x0A /* Light sensor */
-+#define RETU_ADC_LIGHTTEMP 0x0B /* Light sensor temperature */
-+#define RETU_ADC_BKUPVOLT 0x0C /* Backup battery voltage */
-+#define RETU_ADC_TEMP 0x0D /* RETU temperature */
-+
-+
-+int retu_read_reg(struct device *child, unsigned reg);
-+void retu_write_reg(struct device *child, unsigned reg, u16 val);
-+void retu_set_clear_reg_bits(struct device *child, unsigned reg, u16 set,
-+ u16 clear);
-+int retu_read_adc(struct device *child, int channel);
-+
-+#endif /* __DRIVERS_CBUS_RETU_H */
---- /dev/null
-+++ b/drivers/cbus/retu-headset.c
-@@ -0,0 +1,359 @@
-+/**
-+ * Retu/Vilma headset detection
-+ *
-+ * Copyright (C) 2006 Nokia Corporation
-+ *
-+ * Written by Juha Yrjölä
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <linux/input.h>
-+#include <linux/platform_device.h>
-+
-+#include "retu.h"
-+
-+#define RETU_ADC_CHANNEL_HOOKDET 0x05
-+
-+#define RETU_HEADSET_KEY KEY_PHONE
-+
-+struct retu_headset {
-+ spinlock_t lock;
-+ struct mutex mutex;
-+ struct device *dev;
-+ struct input_dev *idev;
-+ unsigned bias_enabled;
-+ unsigned detection_enabled;
-+ unsigned pressed;
-+ struct timer_list enable_timer;
-+ struct timer_list detect_timer;
-+ int irq;
-+};
-+
-+static void retu_headset_set_bias(struct retu_headset *hs, int enable)
-+{
-+ if (enable) {
-+ retu_set_clear_reg_bits(hs->dev, RETU_REG_AUDTXR,
-+ (1 << 0) | (1 << 1), 0);
-+ msleep(2);
-+ retu_set_clear_reg_bits(hs->dev, RETU_REG_AUDTXR,
-+ 1 << 3, 0);
-+ } else {
-+ retu_set_clear_reg_bits(hs->dev, RETU_REG_AUDTXR, 0,
-+ (1 << 0) | (1 << 1) | (1 << 3));
-+ }
-+}
-+
-+static void retu_headset_enable(struct retu_headset *hs)
-+{
-+ mutex_lock(&hs->mutex);
-+ if (!hs->bias_enabled) {
-+ hs->bias_enabled = 1;
-+ retu_headset_set_bias(hs, 1);
-+ }
-+ mutex_unlock(&hs->mutex);
-+}
-+
-+static void retu_headset_disable(struct retu_headset *hs)
-+{
-+ mutex_lock(&hs->mutex);
-+ if (hs->bias_enabled) {
-+ hs->bias_enabled = 0;
-+ retu_headset_set_bias(hs, 0);
-+ }
-+ mutex_unlock(&hs->mutex);
-+}
-+
-+static void retu_headset_det_enable(struct retu_headset *hs)
-+{
-+ mutex_lock(&hs->mutex);
-+ if (!hs->detection_enabled) {
-+ hs->detection_enabled = 1;
-+ retu_set_clear_reg_bits(hs->dev, RETU_REG_CC1,
-+ (1 << 10) | (1 << 8), 0);
-+ }
-+ mutex_unlock(&hs->mutex);
-+}
-+
-+static void retu_headset_det_disable(struct retu_headset *hs)
-+{
-+ unsigned long flags;
-+
-+ mutex_lock(&hs->mutex);
-+ if (hs->detection_enabled) {
-+ hs->detection_enabled = 0;
-+ del_timer_sync(&hs->enable_timer);
-+ del_timer_sync(&hs->detect_timer);
-+ spin_lock_irqsave(&hs->lock, flags);
-+ if (hs->pressed)
-+ input_report_key(hs->idev, RETU_HEADSET_KEY, 0);
-+ spin_unlock_irqrestore(&hs->lock, flags);
-+ retu_set_clear_reg_bits(hs->dev, RETU_REG_CC1, 0,
-+ (1 << 10) | (1 << 8));
-+ }
-+ mutex_unlock(&hs->mutex);
-+}
-+
-+static ssize_t retu_headset_hookdet_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ int val;
-+
-+ val = retu_read_adc(dev, RETU_ADC_CHANNEL_HOOKDET);
-+ return sprintf(buf, "%d\n", val);
-+}
-+
-+static DEVICE_ATTR(hookdet, S_IRUGO, retu_headset_hookdet_show, NULL);
-+
-+static ssize_t retu_headset_enable_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct retu_headset *hs = dev_get_drvdata(dev);
-+
-+ return sprintf(buf, "%u\n", hs->bias_enabled);
-+}
-+
-+static ssize_t retu_headset_enable_store(struct device *dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct retu_headset *hs = dev_get_drvdata(dev);
-+ int enable;
-+
-+ if (sscanf(buf, "%u", &enable) != 1)
-+ return -EINVAL;
-+ if (enable)
-+ retu_headset_enable(hs);
-+ else
-+ retu_headset_disable(hs);
-+ return count;
-+}
-+
-+static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR | S_IWGRP,
-+ retu_headset_enable_show, retu_headset_enable_store);
-+
-+static ssize_t retu_headset_enable_det_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct retu_headset *hs = dev_get_drvdata(dev);
-+
-+ return sprintf(buf, "%u\n", hs->detection_enabled);
-+}
-+
-+static ssize_t retu_headset_enable_det_store(struct device *dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct retu_headset *hs = dev_get_drvdata(dev);
-+ int enable;
-+
-+ if (sscanf(buf, "%u", &enable) != 1)
-+ return -EINVAL;
-+ if (enable)
-+ retu_headset_det_enable(hs);
-+ else
-+ retu_headset_det_disable(hs);
-+ return count;
-+}
-+
-+static DEVICE_ATTR(enable_det, S_IRUGO | S_IWUSR | S_IWGRP,
-+ retu_headset_enable_det_show,
-+ retu_headset_enable_det_store);
-+
-+static irqreturn_t retu_headset_hook_interrupt(int irq, void *_hs)
-+{
-+ struct retu_headset *hs = _hs;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&hs->lock, flags);
-+ if (!hs->pressed) {
-+ /* Headset button was just pressed down. */
-+ hs->pressed = 1;
-+ input_report_key(hs->idev, RETU_HEADSET_KEY, 1);
-+ }
-+ spin_unlock_irqrestore(&hs->lock, flags);
-+ retu_set_clear_reg_bits(hs->dev, RETU_REG_CC1, 0,
-+ (1 << 10) | (1 << 8));
-+ mod_timer(&hs->enable_timer, jiffies + msecs_to_jiffies(50));
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static void retu_headset_enable_timer(unsigned long arg)
-+{
-+ struct retu_headset *hs = (struct retu_headset *) arg;
-+
-+ retu_set_clear_reg_bits(hs->dev, RETU_REG_CC1,
-+ (1 << 10) | (1 << 8), 0);
-+ mod_timer(&hs->detect_timer, jiffies + msecs_to_jiffies(350));
-+}
-+
-+static void retu_headset_detect_timer(unsigned long arg)
-+{
-+ struct retu_headset *hs = (struct retu_headset *) arg;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&hs->lock, flags);
-+ if (hs->pressed) {
-+ hs->pressed = 0;
-+ input_report_key(hs->idev, RETU_HEADSET_KEY, 0);
-+ }
-+ spin_unlock_irqrestore(&hs->lock, flags);
-+}
-+
-+static int __init retu_headset_probe(struct platform_device *pdev)
-+{
-+ struct retu_headset *hs;
-+ int irq;
-+ int r;
-+
-+ hs = kzalloc(sizeof(*hs), GFP_KERNEL);
-+ if (hs == NULL)
-+ return -ENOMEM;
-+
-+ hs->dev = &pdev->dev;
-+
-+ hs->idev = input_allocate_device();
-+ if (hs->idev == NULL) {
-+ r = -ENOMEM;
-+ goto err1;
-+ }
-+ hs->idev->name = "retu-headset";
-+ hs->idev->dev.parent = &pdev->dev;
-+ set_bit(EV_KEY, hs->idev->evbit);
-+ set_bit(RETU_HEADSET_KEY, hs->idev->keybit);
-+ r = input_register_device(hs->idev);
-+ if (r < 0)
-+ goto err2;
-+
-+ r = device_create_file(&pdev->dev, &dev_attr_hookdet);
-+ if (r < 0)
-+ goto err3;
-+ r = device_create_file(&pdev->dev, &dev_attr_enable);
-+ if (r < 0)
-+ goto err4;
-+ r = device_create_file(&pdev->dev, &dev_attr_enable_det);
-+ if (r < 0)
-+ goto err5;
-+ platform_set_drvdata(pdev, hs);
-+
-+ spin_lock_init(&hs->lock);
-+ mutex_init(&hs->mutex);
-+ setup_timer(&hs->enable_timer, retu_headset_enable_timer,
-+ (unsigned long) hs);
-+ setup_timer(&hs->detect_timer, retu_headset_detect_timer,
-+ (unsigned long) hs);
-+
-+ irq = platform_get_irq(pdev, 0);
-+ hs->irq = irq;
-+
-+ r = request_threaded_irq(irq, NULL, retu_headset_hook_interrupt, 0,
-+ "hookdet", hs);
-+ if (r != 0) {
-+ dev_err(&pdev->dev, "hookdet IRQ not available\n");
-+ goto err6;
-+ }
-+
-+ return 0;
-+err6:
-+ device_remove_file(&pdev->dev, &dev_attr_enable_det);
-+err5:
-+ device_remove_file(&pdev->dev, &dev_attr_enable);
-+err4:
-+ device_remove_file(&pdev->dev, &dev_attr_hookdet);
-+err3:
-+ input_unregister_device(hs->idev);
-+err2:
-+ input_free_device(hs->idev);
-+err1:
-+ kfree(hs);
-+ return r;
-+}
-+
-+static int retu_headset_remove(struct platform_device *pdev)
-+{
-+ struct retu_headset *hs = platform_get_drvdata(pdev);
-+
-+ device_remove_file(&pdev->dev, &dev_attr_hookdet);
-+ device_remove_file(&pdev->dev, &dev_attr_enable);
-+ device_remove_file(&pdev->dev, &dev_attr_enable_det);
-+ retu_headset_disable(hs);
-+ retu_headset_det_disable(hs);
-+ free_irq(hs->irq, hs);
-+ input_unregister_device(hs->idev);
-+ input_free_device(hs->idev);
-+
-+ return 0;
-+}
-+
-+static int retu_headset_suspend(struct platform_device *pdev,
-+ pm_message_t mesg)
-+{
-+ struct retu_headset *hs = platform_get_drvdata(pdev);
-+
-+ mutex_lock(&hs->mutex);
-+ if (hs->bias_enabled)
-+ retu_headset_set_bias(hs, 0);
-+ mutex_unlock(&hs->mutex);
-+
-+ return 0;
-+}
-+
-+static int retu_headset_resume(struct platform_device *pdev)
-+{
-+ struct retu_headset *hs = platform_get_drvdata(pdev);
-+
-+ mutex_lock(&hs->mutex);
-+ if (hs->bias_enabled)
-+ retu_headset_set_bias(hs, 1);
-+ mutex_unlock(&hs->mutex);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver retu_headset_driver = {
-+ .remove = retu_headset_remove,
-+ .suspend = retu_headset_suspend,
-+ .resume = retu_headset_resume,
-+ .driver = {
-+ .name = "retu-headset",
-+ },
-+};
-+
-+static int __init retu_headset_init(void)
-+{
-+ return platform_driver_probe(&retu_headset_driver, retu_headset_probe);
-+}
-+
-+static void __exit retu_headset_exit(void)
-+{
-+ platform_driver_unregister(&retu_headset_driver);
-+}
-+
-+module_init(retu_headset_init);
-+module_exit(retu_headset_exit);
-+
-+MODULE_DESCRIPTION("Retu/Vilma headset detection");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Juha Yrjölä");
---- /dev/null
-+++ b/drivers/cbus/retu-pwrbutton.c
-@@ -0,0 +1,165 @@
-+/**
-+ * drivers/cbus/retu-pwrbutton.c
-+ *
-+ * Driver for sending retu power button event to input-layer
-+ *
-+ * Copyright (C) 2004-2010 Nokia Corporation
-+ *
-+ * Written by
-+ * Ari Saastamoinen <ari.saastamoinen@elektrobit.com>
-+ * Juha Yrjola <juha.yrjola@solidboot.com>
-+ *
-+ * Contact: Felipe Balbi <felipe.balbi@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/input.h>
-+#include <linux/jiffies.h>
-+#include <linux/bitops.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+
-+#include "retu.h"
-+
-+#define RETU_STATUS_PWRONX (1 << 5)
-+
-+#define PWRBTN_DELAY 20
-+#define PWRBTN_UP 0
-+#define PWRBTN_PRESSED 1
-+
-+struct retu_pwrbutton {
-+ struct input_dev *idev;
-+ struct device *dev;
-+
-+ int state;
-+ int irq;
-+};
-+
-+static irqreturn_t retubutton_irq(int irq, void *_pwr)
-+{
-+ struct retu_pwrbutton *pwr = _pwr;
-+ int state;
-+
-+ if (retu_read_reg(pwr->dev, RETU_REG_STATUS) & RETU_STATUS_PWRONX)
-+ state = PWRBTN_UP;
-+ else
-+ state = PWRBTN_PRESSED;
-+
-+ if (pwr->state != state) {
-+ input_report_key(pwr->idev, KEY_POWER, state);
-+ input_sync(pwr->idev);
-+ pwr->state = state;
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int __init retubutton_probe(struct platform_device *pdev)
-+{
-+ struct retu_pwrbutton *pwr;
-+ int ret = 0;
-+
-+ pwr = kzalloc(sizeof(*pwr), GFP_KERNEL);
-+ if (!pwr) {
-+ dev_err(&pdev->dev, "not enough memory\n");
-+ ret = -ENOMEM;
-+ goto err0;
-+ }
-+
-+ pwr->dev = &pdev->dev;
-+ pwr->irq = platform_get_irq(pdev, 0);
-+ platform_set_drvdata(pdev, pwr);
-+
-+ ret = request_threaded_irq(pwr->irq, NULL, retubutton_irq, 0,
-+ "retu-pwrbutton", pwr);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "Cannot allocate irq\n");
-+ goto err1;
-+ }
-+
-+ pwr->idev = input_allocate_device();
-+ if (!pwr->idev) {
-+ dev_err(&pdev->dev, "can't allocate input device\n");
-+ ret = -ENOMEM;
-+ goto err2;
-+ }
-+
-+ pwr->idev->evbit[0] = BIT_MASK(EV_KEY);
-+ pwr->idev->keybit[BIT_WORD(KEY_POWER)] = BIT_MASK(KEY_POWER);
-+ pwr->idev->name = "retu-pwrbutton";
-+
-+ ret = input_register_device(pwr->idev);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "failed to register input device\n");
-+ goto err3;
-+ }
-+
-+ return 0;
-+
-+err3:
-+ input_free_device(pwr->idev);
-+
-+err2:
-+ free_irq(pwr->irq, pwr);
-+
-+err1:
-+ kfree(pwr);
-+
-+err0:
-+ return ret;
-+}
-+
-+static int __exit retubutton_remove(struct platform_device *pdev)
-+{
-+ struct retu_pwrbutton *pwr = platform_get_drvdata(pdev);
-+
-+ free_irq(pwr->irq, pwr);
-+ input_unregister_device(pwr->idev);
-+ input_free_device(pwr->idev);
-+ kfree(pwr);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver retu_pwrbutton_driver = {
-+ .remove = __exit_p(retubutton_remove),
-+ .driver = {
-+ .name = "retu-pwrbutton",
-+ },
-+};
-+
-+static int __init retubutton_init(void)
-+{
-+ return platform_driver_probe(&retu_pwrbutton_driver, retubutton_probe);
-+}
-+module_init(retubutton_init);
-+
-+static void __exit retubutton_exit(void)
-+{
-+ platform_driver_unregister(&retu_pwrbutton_driver);
-+}
-+module_exit(retubutton_exit);
-+
-+MODULE_DESCRIPTION("Retu Power Button");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Ari Saastamoinen");
-+MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>");
-+
---- /dev/null
-+++ b/drivers/cbus/retu-rtc.c
-@@ -0,0 +1,287 @@
-+/**
-+ * drivers/cbus/retu-rtc.c
-+ *
-+ * Support for Retu RTC
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Paul Mundt <paul.mundt@nokia.com> and
-+ * Igor Stoppa <igor.stoppa@nokia.com>
-+ *
-+ * The Retu RTC is essentially a partial read-only RTC that gives us Retu's
-+ * idea of what time actually is. It's left as a userspace excercise to map
-+ * this back to time in the real world and ensure that calibration settings
-+ * are sane to compensate for any horrible drift (on account of not being able
-+ * to set the clock to anything).
-+ *
-+ * Days are semi-writeable. Namely, Retu will only track 255 days for us
-+ * consecutively, after which the counter is explicitly stuck at 255 until
-+ * someone comes along and clears it with a write. In the event that no one
-+ * comes along and clears it, we no longer have any idea what day it is.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/mutex.h>
-+#include <linux/rtc.h>
-+
-+#include "cbus.h"
-+#include "retu.h"
-+
-+struct retu_rtc {
-+ /* device lock */
-+ struct mutex mutex;
-+ struct device *dev;
-+ struct rtc_device *rtc;
-+
-+ u16 alarm_expired;
-+ int irq_rtcs;
-+ int irq_rtca;
-+};
-+
-+static void retu_rtc_do_reset(struct retu_rtc *rtc)
-+{
-+ u16 ccr1;
-+
-+ ccr1 = retu_read_reg(rtc->dev, RETU_REG_CC1);
-+ /* RTC in reset */
-+ retu_write_reg(rtc->dev, RETU_REG_CC1, ccr1 | 0x0001);
-+ /* RTC in normal operating mode */
-+ retu_write_reg(rtc->dev, RETU_REG_CC1, ccr1 & ~0x0001);
-+
-+ /* Disable alarm and RTC WD */
-+ retu_write_reg(rtc->dev, RETU_REG_RTCHMAR, 0x7f3f);
-+ /* Set Calibration register to default value */
-+ retu_write_reg(rtc->dev, RETU_REG_RTCCALR, 0x00c0);
-+
-+ rtc->alarm_expired = 0;
-+}
-+
-+static irqreturn_t retu_rtc_interrupt(int irq, void *_rtc)
-+{
-+ struct retu_rtc *rtc = _rtc;
-+
-+ mutex_lock(&rtc->mutex);
-+ rtc->alarm_expired = 1;
-+ retu_write_reg(rtc->dev, RETU_REG_RTCHMAR, (24 << 8) | 60);
-+ mutex_unlock(&rtc->mutex);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int retu_rtc_init_irq(struct retu_rtc *rtc)
-+{
-+ int irq;
-+ int ret;
-+
-+ irq = platform_get_irq(to_platform_device(rtc->dev), 0);
-+ rtc->irq_rtcs = irq;
-+
-+ irq = platform_get_irq(to_platform_device(rtc->dev), 1);
-+ rtc->irq_rtca = irq;
-+
-+ ret = request_threaded_irq(rtc->irq_rtcs, NULL, retu_rtc_interrupt,
-+ 0, "RTCS", rtc);
-+ if (ret != 0)
-+ return ret;
-+
-+ ret = request_threaded_irq(rtc->irq_rtca, NULL, retu_rtc_interrupt,
-+ 0, "RTCA", rtc);
-+ if (ret != 0) {
-+ free_irq(rtc->irq_rtcs, rtc);
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static int retu_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
-+{
-+ struct retu_rtc *rtc = dev_get_drvdata(dev);
-+ u16 chmar;
-+
-+ mutex_lock(&rtc->mutex);
-+
-+ chmar = ((alm->time.tm_hour & 0x1f) << 8) | (alm->time.tm_min & 0x3f);
-+ retu_write_reg(rtc->dev, RETU_REG_RTCHMAR, chmar);
-+
-+ mutex_unlock(&rtc->mutex);
-+
-+ return 0;
-+}
-+
-+static int retu_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
-+{
-+ struct retu_rtc *rtc = dev_get_drvdata(dev);
-+ u16 chmar;
-+
-+ mutex_lock(&rtc->mutex);
-+
-+ chmar = retu_read_reg(rtc->dev, RETU_REG_RTCHMAR);
-+
-+ alm->time.tm_hour = (chmar >> 8) & 0x1f;
-+ alm->time.tm_min = chmar & 0x3f;
-+ alm->enabled = !!rtc->alarm_expired;
-+
-+ mutex_unlock(&rtc->mutex);
-+
-+ return 0;
-+}
-+
-+static int retu_rtc_set_time(struct device *dev, struct rtc_time *tm)
-+{
-+ struct retu_rtc *rtc = dev_get_drvdata(dev);
-+ u16 dsr;
-+ u16 hmr;
-+
-+ dsr = ((tm->tm_mday & 0xff) << 8) | (tm->tm_hour & 0xff);
-+ hmr = ((tm->tm_min & 0xff) << 8) | (tm->tm_sec & 0xff);
-+
-+ mutex_lock(&rtc->mutex);
-+
-+ retu_write_reg(rtc->dev, RETU_REG_RTCDSR, dsr);
-+ retu_write_reg(rtc->dev, RETU_REG_RTCHMR, hmr);
-+
-+ mutex_unlock(&rtc->mutex);
-+
-+ return 0;
-+}
-+
-+static int retu_rtc_read_time(struct device *dev, struct rtc_time *tm)
-+{
-+ struct retu_rtc *rtc = dev_get_drvdata(dev);
-+ u16 dsr;
-+ u16 hmr;
-+
-+ /*
-+ * DSR holds days and hours
-+ * HMR hols minutes and seconds
-+ *
-+ * both are 16 bit registers with 8-bit for each field.
-+ */
-+
-+ mutex_lock(&rtc->mutex);
-+
-+ dsr = retu_read_reg(rtc->dev, RETU_REG_RTCDSR);
-+ hmr = retu_read_reg(rtc->dev, RETU_REG_RTCHMR);
-+
-+ tm->tm_sec = hmr & 0xff;
-+ tm->tm_min = hmr >> 8;
-+ tm->tm_hour = dsr & 0xff;
-+ tm->tm_mday = dsr >> 8;
-+
-+ mutex_unlock(&rtc->mutex);
-+
-+ return 0;
-+}
-+
-+static struct rtc_class_ops retu_rtc_ops = {
-+ .read_time = retu_rtc_read_time,
-+ .set_time = retu_rtc_set_time,
-+ .read_alarm = retu_rtc_read_alarm,
-+ .set_alarm = retu_rtc_set_alarm,
-+};
-+
-+static int __init retu_rtc_probe(struct platform_device *pdev)
-+{
-+ struct retu_rtc *rtc;
-+ int r;
-+
-+ rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
-+ if (!rtc) {
-+ dev_err(&pdev->dev, "not enough memory\n");
-+ r = -ENOMEM;
-+ goto err0;
-+ }
-+
-+ rtc->dev = &pdev->dev;
-+ platform_set_drvdata(pdev, rtc);
-+ mutex_init(&rtc->mutex);
-+
-+ rtc->alarm_expired = retu_read_reg(rtc->dev, RETU_REG_IDR) &
-+ (0x1 << RETU_INT_RTCA);
-+
-+ r = retu_rtc_init_irq(rtc);
-+ if (r < 0) {
-+ dev_err(&pdev->dev, "failed to request retu irq\n");
-+ goto err1;
-+ }
-+
-+ /* If the calibration register is zero, we've probably lost power */
-+ if (!(retu_read_reg(rtc->dev, RETU_REG_RTCCALR) & 0x00ff))
-+ retu_rtc_do_reset(rtc);
-+
-+ rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &
-+ retu_rtc_ops, THIS_MODULE);
-+ if (IS_ERR(rtc->rtc)) {
-+ dev_err(&pdev->dev, "can't register RTC device\n");
-+ goto err2;
-+ }
-+
-+ return 0;
-+
-+err2:
-+ free_irq(rtc->irq_rtcs, rtc);
-+ free_irq(rtc->irq_rtca, rtc);
-+
-+err1:
-+ kfree(rtc);
-+
-+err0:
-+ return r;
-+}
-+
-+static int __devexit retu_rtc_remove(struct platform_device *pdev)
-+{
-+ struct retu_rtc *rtc = platform_get_drvdata(pdev);
-+
-+ free_irq(rtc->irq_rtcs, rtc);
-+ free_irq(rtc->irq_rtca, rtc);
-+ rtc_device_unregister(rtc->rtc);
-+ kfree(rtc);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver retu_rtc_driver = {
-+ .remove = __exit_p(retu_rtc_remove),
-+ .driver = {
-+ .name = "retu-rtc",
-+ },
-+};
-+
-+static int __init retu_rtc_init(void)
-+{
-+ return platform_driver_probe(&retu_rtc_driver, retu_rtc_probe);
-+}
-+module_init(retu_rtc_init);
-+
-+static void __exit retu_rtc_exit(void)
-+{
-+ platform_driver_unregister(&retu_rtc_driver);
-+}
-+module_exit(retu_rtc_exit);
-+
-+MODULE_DESCRIPTION("Retu RTC");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Paul Mundt");
-+MODULE_AUTHOR("Igor Stoppa");
-+MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>");
-+
---- /dev/null
-+++ b/drivers/cbus/retu-wdt.c
-@@ -0,0 +1,272 @@
-+/**
-+ * drivers/cbus/retu-wdt.c
-+ *
-+ * Driver for Retu watchdog
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Amit Kucheria <amit.kucheria@nokia.com>
-+ *
-+ * Cleanups by Michael Buesch <mb@bu3sch.de> (C) 2011
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/fs.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+
-+#include <linux/completion.h>
-+#include <linux/errno.h>
-+#include <linux/moduleparam.h>
-+#include <linux/miscdevice.h>
-+#include <linux/watchdog.h>
-+
-+#include <asm/uaccess.h>
-+
-+#include <plat/prcm.h>
-+
-+#include "cbus.h"
-+#include "retu.h"
-+
-+/* Watchdog timeout in seconds */
-+#define RETU_WDT_MIN_TIMER 0
-+#define RETU_WDT_DEFAULT_TIMER 32
-+#define RETU_WDT_MAX_TIMER 63
-+
-+struct retu_wdt_dev {
-+ struct device *dev;
-+ unsigned int period_val; /* Current period of watchdog */
-+ unsigned long users;
-+ struct miscdevice miscdev;
-+ struct delayed_work ping_work;
-+ struct mutex mutex;
-+};
-+
-+
-+static inline void _retu_modify_counter(struct retu_wdt_dev *wdev,
-+ unsigned int new)
-+{
-+ retu_write_reg(wdev->dev, RETU_REG_WATCHDOG, (u16)new);
-+}
-+
-+static int retu_modify_counter(struct retu_wdt_dev *wdev, unsigned int new)
-+{
-+ if (new < RETU_WDT_MIN_TIMER || new > RETU_WDT_MAX_TIMER)
-+ return -EINVAL;
-+
-+ mutex_lock(&wdev->mutex);
-+ wdev->period_val = new;
-+ _retu_modify_counter(wdev, wdev->period_val);
-+ mutex_unlock(&wdev->mutex);
-+
-+ return 0;
-+}
-+
-+/*
-+ * Since retu watchdog cannot be disabled in hardware, we must kick it
-+ * with a timer until userspace watchdog software takes over. Do this
-+ * unless /dev/watchdog is open or CONFIG_WATCHDOG_NOWAYOUT is set.
-+ */
-+static void retu_wdt_ping_enable(struct retu_wdt_dev *wdev)
-+{
-+ _retu_modify_counter(wdev, RETU_WDT_MAX_TIMER);
-+ schedule_delayed_work(&wdev->ping_work,
-+ round_jiffies_relative(RETU_WDT_DEFAULT_TIMER * HZ));
-+}
-+
-+static void retu_wdt_ping_disable(struct retu_wdt_dev *wdev)
-+{
-+ _retu_modify_counter(wdev, RETU_WDT_MAX_TIMER);
-+ cancel_delayed_work_sync(&wdev->ping_work);
-+}
-+
-+static void retu_wdt_ping_work(struct work_struct *work)
-+{
-+ struct retu_wdt_dev *wdev = container_of(to_delayed_work(work),
-+ struct retu_wdt_dev, ping_work);
-+ retu_wdt_ping_enable(wdev);
-+}
-+
-+static int retu_wdt_open(struct inode *inode, struct file *file)
-+{
-+ struct miscdevice *mdev = file->private_data;
-+ struct retu_wdt_dev *wdev = container_of(mdev, struct retu_wdt_dev, miscdev);
-+
-+ if (test_and_set_bit(0, &wdev->users))
-+ return -EBUSY;
-+
-+ retu_wdt_ping_disable(wdev);
-+
-+ return nonseekable_open(inode, file);
-+}
-+
-+static int retu_wdt_release(struct inode *inode, struct file *file)
-+{
-+ struct miscdevice *mdev = file->private_data;
-+ struct retu_wdt_dev *wdev = container_of(mdev, struct retu_wdt_dev, miscdev);
-+
-+#ifndef CONFIG_WATCHDOG_NOWAYOUT
-+ retu_wdt_ping_enable(wdev);
-+#endif
-+ clear_bit(0, &wdev->users);
-+
-+ return 0;
-+}
-+
-+static ssize_t retu_wdt_write(struct file *file, const char __user *data,
-+ size_t len, loff_t *ppos)
-+{
-+ struct miscdevice *mdev = file->private_data;
-+ struct retu_wdt_dev *wdev = container_of(mdev, struct retu_wdt_dev, miscdev);
-+
-+ if (len)
-+ retu_modify_counter(wdev, RETU_WDT_MAX_TIMER);
-+
-+ return len;
-+}
-+
-+static long retu_wdt_ioctl(struct file *file, unsigned int cmd,
-+ unsigned long arg)
-+{
-+ struct miscdevice *mdev = file->private_data;
-+ struct retu_wdt_dev *wdev = container_of(mdev, struct retu_wdt_dev, miscdev);
-+ int new_margin;
-+
-+ static const struct watchdog_info ident = {
-+ .identity = "Retu Watchdog",
-+ .options = WDIOF_SETTIMEOUT,
-+ .firmware_version = 0,
-+ };
-+
-+ switch (cmd) {
-+ default:
-+ return -ENOTTY;
-+ case WDIOC_GETSUPPORT:
-+ return copy_to_user((struct watchdog_info __user *)arg, &ident,
-+ sizeof(ident));
-+ case WDIOC_GETSTATUS:
-+ return put_user(0, (int __user *)arg);
-+ case WDIOC_GETBOOTSTATUS:
-+ if (cpu_is_omap16xx())
-+ return put_user(omap_readw(ARM_SYSST),
-+ (int __user *)arg);
-+ if (cpu_is_omap24xx())
-+ return put_user(omap_prcm_get_reset_sources(),
-+ (int __user *)arg);
-+ case WDIOC_KEEPALIVE:
-+ retu_modify_counter(wdev, RETU_WDT_MAX_TIMER);
-+ break;
-+ case WDIOC_SETTIMEOUT:
-+ if (get_user(new_margin, (int __user *)arg))
-+ return -EFAULT;
-+ retu_modify_counter(wdev, new_margin);
-+ /* Fall through */
-+ case WDIOC_GETTIMEOUT:
-+ return put_user(wdev->period_val, (int __user *)arg);
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct file_operations retu_wdt_fops = {
-+ .owner = THIS_MODULE,
-+ .write = retu_wdt_write,
-+ .unlocked_ioctl = retu_wdt_ioctl,
-+ .open = retu_wdt_open,
-+ .release = retu_wdt_release,
-+};
-+
-+static int __init retu_wdt_probe(struct platform_device *pdev)
-+{
-+ struct retu_wdt_dev *wdev;
-+ int ret;
-+
-+ wdev = kzalloc(sizeof(struct retu_wdt_dev), GFP_KERNEL);
-+ if (!wdev)
-+ return -ENOMEM;
-+
-+ wdev->dev = &pdev->dev;
-+ wdev->period_val = RETU_WDT_DEFAULT_TIMER;
-+ mutex_init(&wdev->mutex);
-+
-+ platform_set_drvdata(pdev, wdev);
-+
-+ wdev->miscdev.parent = &pdev->dev;
-+ wdev->miscdev.minor = WATCHDOG_MINOR;
-+ wdev->miscdev.name = "watchdog";
-+ wdev->miscdev.fops = &retu_wdt_fops;
-+
-+ ret = misc_register(&wdev->miscdev);
-+ if (ret)
-+ goto err_free_wdev;
-+
-+ INIT_DELAYED_WORK(&wdev->ping_work, retu_wdt_ping_work);
-+
-+ /* Kick the watchdog for kernel booting to finish.
-+ * If nowayout is not set, we start the ping work. */
-+#ifdef CONFIG_WATCHDOG_NOWAYOUT
-+ retu_modify_counter(wdev, RETU_WDT_MAX_TIMER);
-+#else
-+ retu_wdt_ping_enable(wdev);
-+#endif
-+
-+ return 0;
-+
-+err_free_wdev:
-+ kfree(wdev);
-+
-+ return ret;
-+}
-+
-+static int __devexit retu_wdt_remove(struct platform_device *pdev)
-+{
-+ struct retu_wdt_dev *wdev;
-+
-+ wdev = platform_get_drvdata(pdev);
-+ misc_deregister(&wdev->miscdev);
-+ cancel_delayed_work_sync(&wdev->ping_work);
-+ kfree(wdev);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver retu_wdt_driver = {
-+ .remove = __exit_p(retu_wdt_remove),
-+ .driver = {
-+ .name = "retu-wdt",
-+ },
-+};
-+
-+static int __init retu_wdt_init(void)
-+{
-+ return platform_driver_probe(&retu_wdt_driver, retu_wdt_probe);
-+}
-+
-+static void __exit retu_wdt_exit(void)
-+{
-+ platform_driver_unregister(&retu_wdt_driver);
-+}
-+
-+module_init(retu_wdt_init);
-+module_exit(retu_wdt_exit);
-+
-+MODULE_DESCRIPTION("Retu WatchDog");
-+MODULE_AUTHOR("Amit Kucheria");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/cbus/tahvo.c
-@@ -0,0 +1,423 @@
-+/**
-+ * drivers/cbus/tahvo.c
-+ *
-+ * Support functions for Tahvo ASIC
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
-+ * David Weinehall <david.weinehall@nokia.com>, and
-+ * Mikko Ylinen <mikko.k.ylinen@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+
-+#include <linux/slab.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/device.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/cbus.h>
-+#include <linux/mutex.h>
-+
-+#include "cbus.h"
-+#include "tahvo.h"
-+
-+struct tahvo {
-+ /* device lock */
-+ struct mutex mutex;
-+ struct device *dev;
-+
-+ int irq_base;
-+ int irq_end;
-+ int irq;
-+
-+ int ack;
-+ int mask;
-+
-+ unsigned int mask_pending:1;
-+ unsigned int ack_pending:1;
-+ unsigned int is_betty:1;
-+};
-+
-+/**
-+ * __tahvo_read_reg - Reads a value from a register in Tahvo
-+ * @tahvo: pointer to tahvo structure
-+ * @reg: the register address to read from
-+ */
-+static int __tahvo_read_reg(struct tahvo *tahvo, unsigned reg)
-+{
-+ return cbus_read_reg(tahvo->dev, CBUS_TAHVO_DEVICE_ID, reg);
-+}
-+
-+/**
-+ * __tahvo_write_reg - Writes a value to a register in Tahvo
-+ * @tahvo: pointer to tahvo structure
-+ * @reg: register address to write to
-+ * @val: the value to be written to @reg
-+ */
-+static void __tahvo_write_reg(struct tahvo *tahvo, unsigned reg, u16 val)
-+{
-+ cbus_write_reg(tahvo->dev, CBUS_TAHVO_DEVICE_ID, reg, val);
-+}
-+
-+/**
-+ * tahvo_read_reg - Read a value from a register in Tahvo
-+ * @child: device pointer from the calling child
-+ * @reg: the register to read from
-+ *
-+ * This function returns the contents of the specified register
-+ */
-+int tahvo_read_reg(struct device *child, unsigned reg)
-+{
-+ struct tahvo *tahvo = dev_get_drvdata(child->parent);
-+
-+ return __tahvo_read_reg(tahvo, reg);
-+}
-+EXPORT_SYMBOL(tahvo_read_reg);
-+
-+/**
-+ * tahvo_write_reg - Write a value to a register in Tahvo
-+ * @child: device pointer from the calling child
-+ * @reg: the register to write to
-+ * @val : the value to write to the register
-+ *
-+ * This function writes a value to the specified register
-+ */
-+void tahvo_write_reg(struct device *child, unsigned reg, u16 val)
-+{
-+ struct tahvo *tahvo = dev_get_drvdata(child->parent);
-+
-+ __tahvo_write_reg(tahvo, reg, val);
-+}
-+EXPORT_SYMBOL(tahvo_write_reg);
-+
-+/**
-+ * tahvo_set_clear_reg_bits - set and clear register bits atomically
-+ * @child: device pointer from the calling child
-+ * @reg: the register to write to
-+ * @bits: the bits to set
-+ *
-+ * This function sets and clears the specified Tahvo register bits atomically
-+ */
-+void tahvo_set_clear_reg_bits(struct device *child, unsigned reg, u16 set,
-+ u16 clear)
-+{
-+ struct tahvo *tahvo = dev_get_drvdata(child->parent);
-+ u16 w;
-+
-+ mutex_lock(&tahvo->mutex);
-+ w = __tahvo_read_reg(tahvo, reg);
-+ w &= ~clear;
-+ w |= set;
-+ __tahvo_write_reg(tahvo, reg, w);
-+ mutex_unlock(&tahvo->mutex);
-+}
-+
-+static irqreturn_t tahvo_irq_handler(int irq, void *_tahvo)
-+{
-+ struct tahvo *tahvo = _tahvo;
-+ u16 id;
-+ u16 im;
-+
-+ id = __tahvo_read_reg(tahvo, TAHVO_REG_IDR);
-+ im = __tahvo_read_reg(tahvo, TAHVO_REG_IMR);
-+ id &= ~im;
-+
-+ if (!id) {
-+ dev_vdbg(tahvo->dev, "No IRQ, spurious ?\n");
-+ return IRQ_NONE;
-+ }
-+
-+ while (id) {
-+ unsigned long pending = __ffs(id);
-+ unsigned int irq;
-+
-+ id &= ~BIT(pending);
-+ irq = pending + tahvo->irq_base;
-+ handle_nested_irq(irq);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+/* -------------------------------------------------------------------------- */
-+
-+static void tahvo_irq_bus_lock(struct irq_data *data)
-+{
-+ struct tahvo *tahvo = irq_data_get_irq_chip_data(data);
-+
-+ mutex_lock(&tahvo->mutex);
-+}
-+
-+static void tahvo_irq_bus_sync_unlock(struct irq_data *data)
-+{
-+ struct tahvo *tahvo = irq_data_get_irq_chip_data(data);
-+
-+ if (tahvo->mask_pending) {
-+ __tahvo_write_reg(tahvo, TAHVO_REG_IMR, tahvo->mask);
-+ tahvo->mask_pending = false;
-+ }
-+
-+ if (tahvo->ack_pending) {
-+ __tahvo_write_reg(tahvo, TAHVO_REG_IDR, tahvo->ack);
-+ tahvo->ack_pending = false;
-+ }
-+
-+ mutex_unlock(&tahvo->mutex);
-+}
-+
-+static void tahvo_irq_mask(struct irq_data *data)
-+{
-+ struct tahvo *tahvo = irq_data_get_irq_chip_data(data);
-+ int irq = data->irq;
-+
-+ tahvo->mask |= (1 << (irq - tahvo->irq_base));
-+ tahvo->mask_pending = true;
-+}
-+
-+static void tahvo_irq_unmask(struct irq_data *data)
-+{
-+ struct tahvo *tahvo = irq_data_get_irq_chip_data(data);
-+ int irq = data->irq;
-+
-+ tahvo->mask &= ~(1 << (irq - tahvo->irq_base));
-+ tahvo->mask_pending = true;
-+}
-+
-+static void tahvo_irq_ack(struct irq_data *data)
-+{
-+ struct tahvo *tahvo = irq_data_get_irq_chip_data(data);
-+ int irq = data->irq;
-+
-+ tahvo->ack |= (1 << (irq - tahvo->irq_base));
-+ tahvo->ack_pending = true;
-+}
-+
-+static struct irq_chip tahvo_irq_chip = {
-+ .name = "tahvo",
-+ .irq_bus_lock = tahvo_irq_bus_lock,
-+ .irq_bus_sync_unlock = tahvo_irq_bus_sync_unlock,
-+ .irq_mask = tahvo_irq_mask,
-+ .irq_unmask = tahvo_irq_unmask,
-+ .irq_ack = tahvo_irq_ack,
-+};
-+
-+static inline void tahvo_irq_setup(int irq)
-+{
-+#ifdef CONFIG_ARM
-+ set_irq_flags(irq, IRQF_VALID);
-+#else
-+ irq_set_noprobe(irq);
-+#endif
-+}
-+
-+static void tahvo_irq_init(struct tahvo *tahvo)
-+{
-+ int base = tahvo->irq_base;
-+ int end = tahvo->irq_end;
-+ int irq;
-+
-+ for (irq = base; irq < end; irq++) {
-+ irq_set_chip_data(irq, tahvo);
-+ irq_set_chip_and_handler(irq, &tahvo_irq_chip,
-+ handle_simple_irq);
-+ irq_set_nested_thread(irq, 1);
-+ tahvo_irq_setup(irq);
-+ }
-+}
-+
-+/* -------------------------------------------------------------------------- */
-+
-+static struct resource generic_resources[] = {
-+ {
-+ .start = -EINVAL, /* fixed later */
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct device *tahvo_allocate_child(const char *name,
-+ struct device *parent, int irq)
-+{
-+ struct platform_device *pdev;
-+ int ret;
-+
-+ pdev = platform_device_alloc(name, -1);
-+ if (!pdev) {
-+ dev_dbg(parent, "can't allocate %s\n", name);
-+ goto err0;
-+ }
-+
-+ pdev->dev.parent = parent;
-+
-+ if (irq > 0) {
-+ generic_resources[0].start = irq;
-+
-+ ret = platform_device_add_resources(pdev, generic_resources,
-+ ARRAY_SIZE(generic_resources));
-+ if (ret < 0) {
-+ dev_dbg(parent, "can't add resources to %s\n", name);
-+ goto err1;
-+ }
-+ }
-+
-+ ret = platform_device_add(pdev);
-+ if (ret < 0) {
-+ dev_dbg(parent, "can't add %s\n", name);
-+ goto err1;
-+ }
-+
-+ return &pdev->dev;
-+
-+err1:
-+ platform_device_put(pdev);
-+
-+err0:
-+ return NULL;
-+}
-+
-+static int tahvo_allocate_children(struct device *parent, int irq_base)
-+{
-+ struct device *child;
-+
-+ child = tahvo_allocate_child("tahvo-usb", parent,
-+ irq_base + TAHVO_INT_VBUSON);
-+ if (!child)
-+ return -ENOMEM;
-+
-+ child = tahvo_allocate_child("tahvo-pwm", parent, -1);
-+ if (!child)
-+ return -ENOMEM;
-+
-+ return 0;
-+}
-+
-+static int __devinit tahvo_probe(struct platform_device *pdev)
-+{
-+ struct tahvo *tahvo;
-+ int rev;
-+ int ret;
-+ int irq;
-+ int id;
-+
-+ tahvo = kzalloc(sizeof(*tahvo), GFP_KERNEL);
-+ if (!tahvo) {
-+ dev_err(&pdev->dev, "not enough memory\n");
-+ ret = -ENOMEM;
-+ goto err0;
-+ }
-+
-+ irq = platform_get_irq(pdev, 0);
-+ platform_set_drvdata(pdev, tahvo);
-+
-+ mutex_init(&tahvo->mutex);
-+
-+ ret = irq_alloc_descs(-1, 0, MAX_TAHVO_IRQ_HANDLERS, 0);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "failed to allocate IRQ descs\n");
-+ goto err1;
-+ }
-+
-+ tahvo->irq_base = ret;
-+ tahvo->irq_end = ret + MAX_TAHVO_IRQ_HANDLERS;
-+ tahvo->dev = &pdev->dev;
-+ tahvo->irq = irq;
-+
-+ tahvo_irq_init(tahvo);
-+
-+ rev = __tahvo_read_reg(tahvo, TAHVO_REG_ASICR);
-+
-+ id = (rev >> 8) & 0xff;
-+
-+ if (id == 0x0b)
-+ tahvo->is_betty = true;
-+
-+ ret = tahvo_allocate_children(&pdev->dev, tahvo->irq_base);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "failed to allocate children\n");
-+ goto err2;
-+ }
-+
-+ dev_err(&pdev->dev, "%s v%d.%d found\n",
-+ tahvo->is_betty ? "Betty" : "Tahvo",
-+ (rev >> 4) & 0x0f, rev & 0x0f);
-+
-+ /* Mask all TAHVO interrupts */
-+ __tahvo_write_reg(tahvo, TAHVO_REG_IMR, 0xffff);
-+
-+ ret = request_threaded_irq(irq, NULL, tahvo_irq_handler,
-+ IRQF_TRIGGER_RISING | IRQF_ONESHOT,
-+ "tahvo", tahvo);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "Unable to register IRQ handler\n");
-+ goto err2;
-+ }
-+
-+ return 0;
-+
-+err2:
-+ irq_free_descs(tahvo->irq_base, MAX_TAHVO_IRQ_HANDLERS);
-+
-+err1:
-+ kfree(tahvo);
-+
-+err0:
-+ return ret;
-+}
-+
-+static int __devexit tahvo_remove(struct platform_device *pdev)
-+{
-+ struct tahvo *tahvo = platform_get_drvdata(pdev);
-+ int irq;
-+
-+ irq = platform_get_irq(pdev, 0);
-+
-+ free_irq(irq, 0);
-+ irq_free_descs(tahvo->irq_base, MAX_TAHVO_IRQ_HANDLERS);
-+ kfree(tahvo);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver tahvo_driver = {
-+ .probe = tahvo_probe,
-+ .remove = __devexit_p(tahvo_remove),
-+ .driver = {
-+ .name = "tahvo",
-+ },
-+};
-+
-+static int __init tahvo_init(void)
-+{
-+ return platform_driver_register(&tahvo_driver);
-+}
-+subsys_initcall(tahvo_init);
-+
-+static void __exit tahvo_exit(void)
-+{
-+ platform_driver_unregister(&tahvo_driver);
-+}
-+module_exit(tahvo_exit);
-+
-+MODULE_DESCRIPTION("Tahvo ASIC control");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Juha Yrjölä");
-+MODULE_AUTHOR("David Weinehall");
-+MODULE_AUTHOR("Mikko Ylinen");
-+
---- /dev/null
-+++ b/drivers/cbus/tahvo.h
-@@ -0,0 +1,58 @@
-+/*
-+ * drivers/cbus/tahvo.h
-+ *
-+ * Copyright (C) 2004, 2005 Nokia Corporation
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com> and
-+ * David Weinehall <david.weinehall@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __DRIVERS_CBUS_TAHVO_H
-+#define __DRIVERS_CBUS_TAHVO_H
-+
-+#include <linux/types.h>
-+
-+/* Registers */
-+#define TAHVO_REG_ASICR 0x00 /* ASIC ID & revision */
-+#define TAHVO_REG_IDR 0x01 /* Interrupt ID */
-+#define TAHVO_REG_IDSR 0x02 /* Interrupt status */
-+#define TAHVO_REG_IMR 0x03 /* Interrupt mask */
-+#define TAHVO_REG_CHGCURR 0x04 /* Charge current control PWM (8-bit) */
-+#define TAHVO_REG_LEDPWMR 0x05 /* LED PWM */
-+#define TAHVO_REG_USBR 0x06 /* USB control */
-+#define TAHVO_REG_CHGCTL 0x08 /* Charge control register */
-+#define TAHVO_REG_CHGCTL_EN 0x0001 /* Global charge enable */
-+#define TAHVO_REG_CHGCTL_PWMOVR 0x0004 /* PWM override. Force charge PWM to 0%/100% duty cycle. */
-+#define TAHVO_REG_CHGCTL_PWMOVRZERO 0x0008 /* If set, PWM override is 0% (If unset -> 100%) */
-+#define TAHVO_REG_CHGCTL_CURMEAS 0x0040 /* Enable battery current measurement. */
-+#define TAHVO_REG_CHGCTL_CURTIMRST 0x0080 /* Current measure timer reset. */
-+#define TAHVO_REG_BATCURRTIMER 0x0c /* Battery current measure timer (8-bit) */
-+#define TAHVO_REG_BATCURR 0x0d /* Battery (dis)charge current (signed 16-bit) */
-+
-+#define TAHVO_REG_MAX 0x0d
-+
-+/* Interrupt sources */
-+#define TAHVO_INT_VBUSON 0
-+#define TAHVO_INT_BATCURR 7 /* Battery current measure timer */
-+
-+#define MAX_TAHVO_IRQ_HANDLERS 8
-+
-+int tahvo_read_reg(struct device *child, unsigned reg);
-+void tahvo_write_reg(struct device *child, unsigned reg, u16 val);
-+void tahvo_set_clear_reg_bits(struct device *child, unsigned reg, u16 set,
-+ u16 clear);
-+
-+#endif /* __DRIVERS_CBUS_TAHVO_H */
---- /dev/null
-+++ b/drivers/cbus/tahvo-usb.c
-@@ -0,0 +1,740 @@
-+/**
-+ * drivers/cbus/tahvo-usb.c
-+ *
-+ * Tahvo USB transeiver
-+ *
-+ * Copyright (C) 2005-2006 Nokia Corporation
-+ *
-+ * Parts copied from drivers/i2c/chips/isp1301_omap.c
-+ * Copyright (C) 2004 Texas Instruments
-+ * Copyright (C) 2004 David Brownell
-+ *
-+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
-+ * Tony Lindgren <tony@atomide.com>, and
-+ * Timo Teräs <timo.teras@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/io.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/usb/ch9.h>
-+#include <linux/usb/gadget.h>
-+#include <linux/usb.h>
-+#include <linux/usb/otg.h>
-+#include <linux/i2c.h>
-+#include <linux/workqueue.h>
-+#include <linux/kobject.h>
-+#include <linux/clk.h>
-+#include <linux/mutex.h>
-+
-+#include <asm/irq.h>
-+#include <plat/usb.h>
-+
-+#include "cbus.h"
-+#include "tahvo.h"
-+
-+#define DRIVER_NAME "tahvo-usb"
-+
-+#define USBR_SLAVE_CONTROL (1 << 8)
-+#define USBR_VPPVIO_SW (1 << 7)
-+#define USBR_SPEED (1 << 6)
-+#define USBR_REGOUT (1 << 5)
-+#define USBR_MASTER_SW2 (1 << 4)
-+#define USBR_MASTER_SW1 (1 << 3)
-+#define USBR_SLAVE_SW (1 << 2)
-+#define USBR_NSUSPEND (1 << 1)
-+#define USBR_SEMODE (1 << 0)
-+
-+/* bits in OTG_CTRL */
-+
-+/* Bits that are controlled by OMAP OTG and are read-only */
-+#define OTG_CTRL_OMAP_MASK (OTG_PULLDOWN|OTG_PULLUP|OTG_DRV_VBUS|\
-+ OTG_PD_VBUS|OTG_PU_VBUS|OTG_PU_ID)
-+/* Bits that are controlled by transceiver */
-+#define OTG_CTRL_XCVR_MASK (OTG_ASESSVLD|OTG_BSESSEND|\
-+ OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID)
-+/* Bits that are controlled by system */
-+#define OTG_CTRL_SYS_MASK (OTG_A_BUSREQ|OTG_A_SETB_HNPEN|OTG_B_BUSREQ|\
-+ OTG_B_HNPEN|OTG_BUSDROP)
-+
-+#if defined(CONFIG_USB_OHCI_HCD) && !defined(CONFIG_USB_OTG)
-+#error tahvo-otg.c does not work with OCHI yet!
-+#endif
-+
-+#define TAHVO_MODE_HOST 0
-+#define TAHVO_MODE_PERIPHERAL 1
-+
-+#ifdef CONFIG_USB_OTG
-+#define TAHVO_MODE(tu) (tu)->tahvo_mode
-+#elif defined(CONFIG_USB_GADGET_OMAP)
-+#define TAHVO_MODE(tu) TAHVO_MODE_PERIPHERAL
-+#else
-+#define TAHVO_MODE(tu) TAHVO_MODE_HOST
-+#endif
-+
-+struct tahvo_usb {
-+ struct device *dev;
-+ struct platform_device *pt_dev;
-+ struct otg_transceiver otg;
-+ int vbus_state;
-+ struct mutex serialize;
-+#ifdef CONFIG_USB_OTG
-+ int tahvo_mode;
-+#endif
-+ struct clk *ick;
-+
-+ int irq;
-+};
-+static struct tahvo_usb *tahvo_usb_device;
-+
-+/*
-+ * ---------------------------------------------------------------------------
-+ * OTG related functions
-+ *
-+ * These shoud be separated into omap-otg.c driver module, as they are used
-+ * by various transceivers. These functions are needed in the UDC-only case
-+ * as well. These functions are copied from GPL isp1301_omap.c
-+ * ---------------------------------------------------------------------------
-+ */
-+static struct platform_device *tahvo_otg_dev;
-+
-+static irqreturn_t omap_otg_irq(int irq, void *arg)
-+{
-+ u16 otg_irq;
-+
-+ otg_irq = omap_readw(OTG_IRQ_SRC);
-+ if (otg_irq & OPRT_CHG) {
-+ omap_writew(OPRT_CHG, OTG_IRQ_SRC);
-+ } else if (otg_irq & B_SRP_TMROUT) {
-+ omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC);
-+ } else if (otg_irq & B_HNP_FAIL) {
-+ omap_writew(B_HNP_FAIL, OTG_IRQ_SRC);
-+ } else if (otg_irq & A_SRP_DETECT) {
-+ omap_writew(A_SRP_DETECT, OTG_IRQ_SRC);
-+ } else if (otg_irq & A_REQ_TMROUT) {
-+ omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC);
-+ } else if (otg_irq & A_VBUS_ERR) {
-+ omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
-+ } else if (otg_irq & DRIVER_SWITCH) {
-+#ifdef CONFIG_USB_OTG
-+ if ((!(omap_readl(OTG_CTRL) & OTG_DRIVER_SEL)) &&
-+ tu->otg.host && tu->otg.state == OTG_STATE_A_HOST) {
-+ /* role is host */
-+ usb_bus_start_enum(tu->otg.host,
-+ tu->otg.host->otg_port);
-+ }
-+#endif
-+ omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC);
-+ } else
-+ return IRQ_NONE;
-+
-+ return IRQ_HANDLED;
-+
-+}
-+
-+static int tahvo_otg_init(void)
-+{
-+ u32 l;
-+
-+#ifdef CONFIG_USB_OTG
-+ if (!tahvo_otg_dev) {
-+ printk("tahvo-usb: no tahvo_otg_dev\n");
-+ return -ENODEV;
-+ }
-+#endif
-+
-+ l = omap_readl(OTG_SYSCON_1);
-+ l &= ~OTG_IDLE_EN;
-+ omap_writel(l, OTG_SYSCON_1);
-+ udelay(100);
-+
-+ /* some of these values are board-specific... */
-+ l = omap_readl(OTG_SYSCON_2);
-+ l |= OTG_EN
-+ /* for B-device: */
-+ | SRP_GPDATA /* 9msec Bdev D+ pulse */
-+ | SRP_GPDVBUS /* discharge after VBUS pulse */
-+ // | (3 << 24) /* 2msec VBUS pulse */
-+ /* for A-device: */
-+ | (0 << 20) /* 200ms nominal A_WAIT_VRISE timer */
-+ | SRP_DPW /* detect 167+ns SRP pulses */
-+ | SRP_DATA | SRP_VBUS; /* accept both kinds of SRP pulse */
-+ omap_writel(l, OTG_SYSCON_2);
-+
-+ omap_writew(DRIVER_SWITCH | OPRT_CHG
-+ | B_SRP_TMROUT | B_HNP_FAIL
-+ | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT,
-+ OTG_IRQ_EN);
-+ l = omap_readl(OTG_SYSCON_2);
-+ l |= OTG_EN;
-+ omap_writel(l, OTG_SYSCON_2);
-+
-+ return 0;
-+}
-+
-+static int __init omap_otg_probe(struct platform_device *pdev)
-+{
-+ int ret;
-+
-+ tahvo_otg_dev = pdev;
-+ ret = tahvo_otg_init();
-+ if (ret != 0) {
-+ printk(KERN_ERR "tahvo-usb: tahvo_otg_init failed\n");
-+ return ret;
-+ }
-+
-+ return request_irq(tahvo_otg_dev->resource[1].start,
-+ omap_otg_irq, IRQF_DISABLED, DRIVER_NAME,
-+ tahvo_usb_device);
-+}
-+
-+static int __exit omap_otg_remove(struct platform_device *pdev)
-+{
-+ free_irq(tahvo_otg_dev->resource[1].start, tahvo_usb_device);
-+ tahvo_otg_dev = NULL;
-+
-+ return 0;
-+}
-+
-+struct platform_driver omap_otg_driver = {
-+ .driver = {
-+ .name = "omap_otg",
-+ },
-+ .remove = __exit_p(omap_otg_remove),
-+};
-+
-+/*
-+ * ---------------------------------------------------------------------------
-+ * Tahvo related functions
-+ * These are Nokia proprietary code, except for the OTG register settings,
-+ * which are copied from isp1301.c
-+ * ---------------------------------------------------------------------------
-+ */
-+static ssize_t vbus_state_show(struct device *device,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct tahvo_usb *tu = dev_get_drvdata(device);
-+ return sprintf(buf, "%d\n", tu->vbus_state);
-+}
-+static DEVICE_ATTR(vbus_state, 0444, vbus_state_show, NULL);
-+
-+int vbus_active = 0;
-+
-+static void check_vbus_state(struct tahvo_usb *tu)
-+{
-+ int reg, prev_state;
-+
-+ reg = tahvo_read_reg(tu->dev, TAHVO_REG_IDSR);
-+ if (reg & 0x01) {
-+ u32 l;
-+
-+ vbus_active = 1;
-+ switch (tu->otg.state) {
-+ case OTG_STATE_B_IDLE:
-+ /* Enable the gadget driver */
-+ if (tu->otg.gadget)
-+ usb_gadget_vbus_connect(tu->otg.gadget);
-+ /* Set B-session valid and not B-sessio ended to indicate
-+ * Vbus to be ok. */
-+ l = omap_readl(OTG_CTRL);
-+ l &= ~OTG_BSESSEND;
-+ l |= OTG_BSESSVLD;
-+ omap_writel(l, OTG_CTRL);
-+
-+ tu->otg.state = OTG_STATE_B_PERIPHERAL;
-+ break;
-+ case OTG_STATE_A_IDLE:
-+ /* Session is now valid assuming the USB hub is driving Vbus */
-+ tu->otg.state = OTG_STATE_A_HOST;
-+ break;
-+ default:
-+ break;
-+ }
-+ printk("USB cable connected\n");
-+ } else {
-+ switch (tu->otg.state) {
-+ case OTG_STATE_B_PERIPHERAL:
-+ if (tu->otg.gadget)
-+ usb_gadget_vbus_disconnect(tu->otg.gadget);
-+ tu->otg.state = OTG_STATE_B_IDLE;
-+ break;
-+ case OTG_STATE_A_HOST:
-+ tu->otg.state = OTG_STATE_A_IDLE;
-+ break;
-+ default:
-+ break;
-+ }
-+ printk("USB cable disconnected\n");
-+ vbus_active = 0;
-+ }
-+
-+ prev_state = tu->vbus_state;
-+ tu->vbus_state = reg & 0x01;
-+ if (prev_state != tu->vbus_state)
-+ sysfs_notify(&tu->pt_dev->dev.kobj, NULL, "vbus_state");
-+}
-+
-+static void tahvo_usb_become_host(struct tahvo_usb *tu)
-+{
-+ u32 l;
-+
-+ /* Clear system and transceiver controlled bits
-+ * also mark the A-session is always valid */
-+ tahvo_otg_init();
-+
-+ l = omap_readl(OTG_CTRL);
-+ l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK);
-+ l |= OTG_ASESSVLD;
-+ omap_writel(l, OTG_CTRL);
-+
-+ /* Power up the transceiver in USB host mode */
-+ tahvo_write_reg(tu->dev, TAHVO_REG_USBR, USBR_REGOUT | USBR_NSUSPEND |
-+ USBR_MASTER_SW2 | USBR_MASTER_SW1);
-+ tu->otg.state = OTG_STATE_A_IDLE;
-+
-+ check_vbus_state(tu);
-+}
-+
-+static void tahvo_usb_stop_host(struct tahvo_usb *tu)
-+{
-+ tu->otg.state = OTG_STATE_A_IDLE;
-+}
-+
-+static void tahvo_usb_become_peripheral(struct tahvo_usb *tu)
-+{
-+ u32 l;
-+
-+ /* Clear system and transceiver controlled bits
-+ * and enable ID to mark peripheral mode and
-+ * BSESSEND to mark no Vbus */
-+ tahvo_otg_init();
-+ l = omap_readl(OTG_CTRL);
-+ l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD);
-+ l |= OTG_ID | OTG_BSESSEND;
-+ omap_writel(l, OTG_CTRL);
-+
-+ /* Power up transceiver and set it in USB perhiperal mode */
-+ tahvo_write_reg(tu->dev, TAHVO_REG_USBR, USBR_SLAVE_CONTROL | USBR_REGOUT | USBR_NSUSPEND | USBR_SLAVE_SW);
-+ tu->otg.state = OTG_STATE_B_IDLE;
-+
-+ check_vbus_state(tu);
-+}
-+
-+static void tahvo_usb_stop_peripheral(struct tahvo_usb *tu)
-+{
-+ u32 l;
-+
-+ l = omap_readl(OTG_CTRL);
-+ l &= ~OTG_BSESSVLD;
-+ l |= OTG_BSESSEND;
-+ omap_writel(l, OTG_CTRL);
-+
-+ if (tu->otg.gadget)
-+ usb_gadget_vbus_disconnect(tu->otg.gadget);
-+ tu->otg.state = OTG_STATE_B_IDLE;
-+
-+}
-+
-+static void tahvo_usb_power_off(struct tahvo_usb *tu)
-+{
-+ u32 l;
-+ int id;
-+
-+ /* Disable gadget controller if any */
-+ if (tu->otg.gadget)
-+ usb_gadget_vbus_disconnect(tu->otg.gadget);
-+
-+ /* Disable OTG and interrupts */
-+ if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
-+ id = OTG_ID;
-+ else
-+ id = 0;
-+ l = omap_readl(OTG_CTRL);
-+ l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD);
-+ l |= id | OTG_BSESSEND;
-+ omap_writel(l, OTG_CTRL);
-+ omap_writew(0, OTG_IRQ_EN);
-+
-+ l = omap_readl(OTG_SYSCON_2);
-+ l &= ~OTG_EN;
-+ omap_writel(l, OTG_SYSCON_2);
-+
-+ l = omap_readl(OTG_SYSCON_1);
-+ l |= OTG_IDLE_EN;
-+ omap_writel(l, OTG_SYSCON_1);
-+
-+ /* Power off transceiver */
-+ tahvo_write_reg(tu->dev, TAHVO_REG_USBR, 0);
-+ tu->otg.state = OTG_STATE_UNDEFINED;
-+}
-+
-+
-+static int tahvo_usb_set_power(struct otg_transceiver *dev, unsigned mA)
-+{
-+ struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
-+
-+ dev_dbg(&tu->pt_dev->dev, "set_power %d mA\n", mA);
-+
-+ if (dev->state == OTG_STATE_B_PERIPHERAL) {
-+ /* REVISIT: Can Tahvo charge battery from VBUS? */
-+ }
-+ return 0;
-+}
-+
-+static int tahvo_usb_set_suspend(struct otg_transceiver *dev, int suspend)
-+{
-+ struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
-+ u16 w;
-+
-+ dev_dbg(&tu->pt_dev->dev, "set_suspend\n");
-+
-+ w = tahvo_read_reg(tu->dev, TAHVO_REG_USBR);
-+ if (suspend)
-+ w &= ~USBR_NSUSPEND;
-+ else
-+ w |= USBR_NSUSPEND;
-+ tahvo_write_reg(tu->dev, TAHVO_REG_USBR, w);
-+
-+ return 0;
-+}
-+
-+static int tahvo_usb_start_srp(struct otg_transceiver *dev)
-+{
-+ struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
-+ u32 otg_ctrl;
-+
-+ dev_dbg(&tu->pt_dev->dev, "start_srp\n");
-+
-+ if (!dev || tu->otg.state != OTG_STATE_B_IDLE)
-+ return -ENODEV;
-+
-+ otg_ctrl = omap_readl(OTG_CTRL);
-+ if (!(otg_ctrl & OTG_BSESSEND))
-+ return -EINVAL;
-+
-+ otg_ctrl |= OTG_B_BUSREQ;
-+ otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_SYS_MASK;
-+ omap_writel(otg_ctrl, OTG_CTRL);
-+ tu->otg.state = OTG_STATE_B_SRP_INIT;
-+
-+ return 0;
-+}
-+
-+static int tahvo_usb_start_hnp(struct otg_transceiver *otg)
-+{
-+ struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
-+
-+ dev_dbg(&tu->pt_dev->dev, "start_hnp\n");
-+#ifdef CONFIG_USB_OTG
-+ /* REVISIT: Add this for OTG */
-+#endif
-+ return -EINVAL;
-+}
-+
-+static int tahvo_usb_set_host(struct otg_transceiver *otg, struct usb_bus *host)
-+{
-+ struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
-+ u32 l;
-+
-+ dev_dbg(&tu->pt_dev->dev, "set_host %p\n", host);
-+
-+ if (otg == NULL)
-+ return -ENODEV;
-+
-+#if defined(CONFIG_USB_OTG) || !defined(CONFIG_USB_GADGET_OMAP)
-+
-+ mutex_lock(&tu->serialize);
-+
-+ if (host == NULL) {
-+ if (TAHVO_MODE(tu) == TAHVO_MODE_HOST)
-+ tahvo_usb_power_off(tu);
-+ tu->otg.host = NULL;
-+ mutex_unlock(&tu->serialize);
-+ return 0;
-+ }
-+
-+ l = omap_readl(OTG_SYSCON_1);
-+ l &= ~(OTG_IDLE_EN | HST_IDLE_EN | DEV_IDLE_EN);
-+ omap_writel(l, OTG_SYSCON_1);
-+
-+ if (TAHVO_MODE(tu) == TAHVO_MODE_HOST) {
-+ tu->otg.host = NULL;
-+ tahvo_usb_become_host(tu);
-+ }
-+
-+ tu->otg.host = host;
-+
-+ mutex_unlock(&tu->serialize);
-+#else
-+ /* No host mode configured, so do not allow host controlled to be set */
-+ return -EINVAL;
-+#endif
-+
-+ return 0;
-+}
-+
-+static int tahvo_usb_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget)
-+{
-+ struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
-+
-+ dev_dbg(&tu->pt_dev->dev, "set_peripheral %p\n", gadget);
-+
-+ if (!otg)
-+ return -ENODEV;
-+
-+#if defined(CONFIG_USB_OTG) || defined(CONFIG_USB_GADGET_OMAP)
-+
-+ mutex_lock(&tu->serialize);
-+
-+ if (!gadget) {
-+ if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
-+ tahvo_usb_power_off(tu);
-+ tu->otg.gadget = NULL;
-+ mutex_unlock(&tu->serialize);
-+ return 0;
-+ }
-+
-+ tu->otg.gadget = gadget;
-+ if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
-+ tahvo_usb_become_peripheral(tu);
-+
-+ mutex_unlock(&tu->serialize);
-+#else
-+ /* No gadget mode configured, so do not allow host controlled to be set */
-+ return -EINVAL;
-+#endif
-+
-+ return 0;
-+}
-+
-+static irqreturn_t tahvo_usb_vbus_interrupt(int irq, void *_tu)
-+{
-+ struct tahvo_usb *tu = _tu;
-+
-+ check_vbus_state(tu);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+#ifdef CONFIG_USB_OTG
-+static ssize_t otg_mode_show(struct device *device,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct tahvo_usb *tu = dev_get_drvdata(device);
-+ switch (tu->tahvo_mode) {
-+ case TAHVO_MODE_HOST:
-+ return sprintf(buf, "host\n");
-+ case TAHVO_MODE_PERIPHERAL:
-+ return sprintf(buf, "peripheral\n");
-+ }
-+ return sprintf(buf, "unknown\n");
-+}
-+
-+static ssize_t otg_mode_store(struct device *device,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct tahvo_usb *tu = dev_get_drvdata(device);
-+ int r;
-+
-+ r = strlen(buf);
-+ mutex_lock(&tu->serialize);
-+ if (strncmp(buf, "host", 4) == 0) {
-+ if (tu->tahvo_mode == TAHVO_MODE_PERIPHERAL)
-+ tahvo_usb_stop_peripheral(tu);
-+ tu->tahvo_mode = TAHVO_MODE_HOST;
-+ if (tu->otg.host) {
-+ printk(KERN_INFO "Selected HOST mode: host controller present.\n");
-+ tahvo_usb_become_host(tu);
-+ } else {
-+ printk(KERN_INFO "Selected HOST mode: no host controller, powering off.\n");
-+ tahvo_usb_power_off(tu);
-+ }
-+ } else if (strncmp(buf, "peripheral", 10) == 0) {
-+ if (tu->tahvo_mode == TAHVO_MODE_HOST)
-+ tahvo_usb_stop_host(tu);
-+ tu->tahvo_mode = TAHVO_MODE_PERIPHERAL;
-+ if (tu->otg.gadget) {
-+ printk(KERN_INFO "Selected PERIPHERAL mode: gadget driver present.\n");
-+ tahvo_usb_become_peripheral(tu);
-+ } else {
-+ printk(KERN_INFO "Selected PERIPHERAL mode: no gadget driver, powering off.\n");
-+ tahvo_usb_power_off(tu);
-+ }
-+ } else
-+ r = -EINVAL;
-+
-+ mutex_unlock(&tu->serialize);
-+ return r;
-+}
-+
-+static DEVICE_ATTR(otg_mode, 0644, otg_mode_show, otg_mode_store);
-+#endif
-+
-+static int __init tahvo_usb_probe(struct platform_device *pdev)
-+{
-+ struct tahvo_usb *tu;
-+ struct device *dev = &pdev->dev;
-+ int ret;
-+ int irq;
-+
-+ dev_dbg(dev, "probe\n");
-+
-+ /* Create driver data */
-+ tu = kzalloc(sizeof(*tu), GFP_KERNEL);
-+ if (!tu)
-+ return -ENOMEM;
-+ tahvo_usb_device = tu;
-+
-+ tu->dev = dev;
-+ tu->pt_dev = pdev;
-+#ifdef CONFIG_USB_OTG
-+ /* Default mode */
-+#ifdef CONFIG_CBUS_TAHVO_USB_HOST_BY_DEFAULT
-+ tu->tahvo_mode = TAHVO_MODE_HOST;
-+#else
-+ tu->tahvo_mode = TAHVO_MODE_PERIPHERAL;
-+#endif
-+#endif
-+
-+ mutex_init(&tu->serialize);
-+
-+ tu->ick = clk_get(NULL, "usb_l4_ick");
-+ if (IS_ERR(tu->ick)) {
-+ dev_err(dev, "Failed to get usb_l4_ick\n");
-+ ret = PTR_ERR(tu->ick);
-+ goto err_free_tu;
-+ }
-+ clk_enable(tu->ick);
-+
-+ /* Set initial state, so that we generate kevents only on
-+ * state changes */
-+ tu->vbus_state = tahvo_read_reg(tu->dev, TAHVO_REG_IDSR) & 0x01;
-+
-+ irq = platform_get_irq(pdev, 0);
-+ tu->irq = irq;
-+
-+ /* We cannot enable interrupt until omap_udc is initialized */
-+ ret = request_threaded_irq(irq, NULL, tahvo_usb_vbus_interrupt,
-+ IRQF_ONESHOT, "tahvo-vbus", tu);
-+ if (ret != 0) {
-+ printk(KERN_ERR "Could not register Tahvo interrupt for VBUS\n");
-+ goto err_release_clk;
-+ }
-+
-+ /* Attributes */
-+ ret = device_create_file(dev, &dev_attr_vbus_state);
-+#ifdef CONFIG_USB_OTG
-+ ret |= device_create_file(dev, &dev_attr_otg_mode);
-+#endif
-+ if (ret)
-+ printk(KERN_ERR "attribute creation failed: %d\n", ret);
-+
-+ /* Create OTG interface */
-+ tahvo_usb_power_off(tu);
-+ tu->otg.state = OTG_STATE_UNDEFINED;
-+ tu->otg.label = DRIVER_NAME;
-+ tu->otg.set_host = tahvo_usb_set_host;
-+ tu->otg.set_peripheral = tahvo_usb_set_peripheral;
-+ tu->otg.set_power = tahvo_usb_set_power;
-+ tu->otg.set_suspend = tahvo_usb_set_suspend;
-+ tu->otg.start_srp = tahvo_usb_start_srp;
-+ tu->otg.start_hnp = tahvo_usb_start_hnp;
-+
-+ ret = otg_set_transceiver(&tu->otg);
-+ if (ret < 0) {
-+ printk(KERN_ERR "Cannot register USB transceiver\n");
-+ goto err_free_irq;
-+ }
-+
-+ dev_set_drvdata(dev, tu);
-+
-+ return 0;
-+
-+err_free_irq:
-+ free_irq(tu->irq, tu);
-+err_release_clk:
-+ clk_disable(tu->ick);
-+ clk_put(tu->ick);
-+err_free_tu:
-+ kfree(tu);
-+ tahvo_usb_device = NULL;
-+
-+ return ret;
-+}
-+
-+static int __exit tahvo_usb_remove(struct platform_device *pdev)
-+{
-+ struct tahvo_usb *tu = platform_get_drvdata(pdev);
-+
-+ dev_dbg(&pdev->dev, "remove\n");
-+
-+ free_irq(tu->irq, tu);
-+ flush_scheduled_work();
-+ otg_set_transceiver(0);
-+ device_remove_file(&pdev->dev, &dev_attr_vbus_state);
-+#ifdef CONFIG_USB_OTG
-+ device_remove_file(&pdev->dev, &dev_attr_otg_mode);
-+#endif
-+ clk_disable(tu->ick);
-+ clk_put(tu->ick);
-+
-+ kfree(tu);
-+ tahvo_usb_device = NULL;
-+
-+ return 0;
-+}
-+
-+static struct platform_driver tahvo_usb_driver = {
-+ .driver = {
-+ .name = "tahvo-usb",
-+ },
-+ .remove = __exit_p(tahvo_usb_remove),
-+};
-+
-+static int __init tahvo_usb_init(void)
-+{
-+ int ret = 0;
-+
-+ ret = platform_driver_probe(&tahvo_usb_driver, tahvo_usb_probe);
-+ if (ret)
-+ return ret;
-+
-+ ret = platform_driver_probe(&omap_otg_driver, omap_otg_probe);
-+ if (ret) {
-+ platform_driver_unregister(&tahvo_usb_driver);
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+subsys_initcall(tahvo_usb_init);
-+
-+static void __exit tahvo_usb_exit(void)
-+{
-+ platform_driver_unregister(&omap_otg_driver);
-+ platform_driver_unregister(&tahvo_usb_driver);
-+}
-+module_exit(tahvo_usb_exit);
-+
-+MODULE_DESCRIPTION("Tahvo USB OTG Transceiver Driver");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Juha Yrjölä, Tony Lindgren, and Timo Teräs");
---- a/drivers/Makefile
-+++ b/drivers/Makefile
-@@ -78,7 +78,7 @@ obj-$(CONFIG_GAMEPORT) += input/gamepor
- obj-$(CONFIG_INPUT) += input/
- obj-$(CONFIG_I2O) += message/
- obj-$(CONFIG_RTC_LIB) += rtc/
--obj-y += i2c/ media/
-+obj-y += i2c/ media/ cbus/
- obj-$(CONFIG_PPS) += pps/
- obj-$(CONFIG_PTP_1588_CLOCK) += ptp/
- obj-$(CONFIG_W1) += w1/
---- a/drivers/Kconfig
-+++ b/drivers/Kconfig
-@@ -2,6 +2,8 @@ menu "Device Drivers"
-
- source "drivers/base/Kconfig"
-
-+source "drivers/cbus/Kconfig"
-+
- source "drivers/connector/Kconfig"
-
- source "drivers/mtd/Kconfig"
+++ /dev/null
---- a/drivers/cbus/tahvo.c
-+++ b/drivers/cbus/tahvo.c
-@@ -104,7 +104,9 @@ void tahvo_write_reg(struct device *chil
- {
- struct tahvo *tahvo = dev_get_drvdata(child->parent);
-
-+ mutex_lock(&tahvo->mutex);
- __tahvo_write_reg(tahvo, reg, val);
-+ mutex_unlock(&tahvo->mutex);
- }
- EXPORT_SYMBOL(tahvo_write_reg);
-
+++ /dev/null
---- a/drivers/cbus/retu.c
-+++ b/drivers/cbus/retu.c
-@@ -53,9 +53,6 @@ struct retu {
-
- int irq;
-
-- int ack;
-- bool ack_pending;
--
- int mask;
- bool mask_pending;
-
-@@ -191,9 +188,10 @@ static irqreturn_t retu_irq_handler(int
- mutex_lock(&retu->mutex);
- idr = __retu_read_reg(retu, RETU_REG_IDR);
- imr = __retu_read_reg(retu, RETU_REG_IMR);
-+ idr &= ~imr;
-+ __retu_write_reg(retu, RETU_REG_IDR, idr);
- mutex_unlock(&retu->mutex);
-
-- idr &= ~imr;
- if (!idr) {
- dev_vdbg(retu->dev, "No IRQ, spurious?\n");
- return IRQ_NONE;
-@@ -232,15 +230,6 @@ static void retu_irq_unmask(struct irq_d
-
- }
-
--static void retu_irq_ack(struct irq_data *data)
--{
-- struct retu *retu = irq_data_get_irq_chip_data(data);
-- int irq = data->irq;
--
-- retu->ack |= (1 << (irq - retu->irq_base));
-- retu->ack_pending = true;
--}
--
- static void retu_bus_lock(struct irq_data *data)
- {
- struct retu *retu = irq_data_get_irq_chip_data(data);
-@@ -257,11 +246,6 @@ static void retu_bus_sync_unlock(struct
- retu->mask_pending = false;
- }
-
-- if (retu->ack_pending) {
-- __retu_write_reg(retu, RETU_REG_IDR, retu->ack);
-- retu->ack_pending = false;
-- }
--
- mutex_unlock(&retu->mutex);
- }
-
-@@ -271,7 +255,6 @@ static struct irq_chip retu_irq_chip = {
- .irq_bus_sync_unlock = retu_bus_sync_unlock,
- .irq_mask = retu_irq_mask,
- .irq_unmask = retu_irq_unmask,
-- .irq_ack = retu_irq_ack,
- };
-
- static inline void retu_irq_setup(int irq)
-@@ -291,8 +274,7 @@ static void retu_irq_init(struct retu *r
-
- for (irq = base; irq < end; irq++) {
- irq_set_chip_data(irq, retu);
-- irq_set_chip_and_handler(irq, &retu_irq_chip,
-- handle_simple_irq);
-+ irq_set_chip(irq, &retu_irq_chip);
- irq_set_nested_thread(irq, 1);
- retu_irq_setup(irq);
- }
---- a/drivers/cbus/tahvo.c
-+++ b/drivers/cbus/tahvo.c
-@@ -48,11 +48,9 @@ struct tahvo {
- int irq_end;
- int irq;
-
-- int ack;
- int mask;
-
- unsigned int mask_pending:1;
-- unsigned int ack_pending:1;
- unsigned int is_betty:1;
- };
-
-@@ -138,9 +136,12 @@ static irqreturn_t tahvo_irq_handler(int
- u16 id;
- u16 im;
-
-+ mutex_lock(&tahvo->mutex);
- id = __tahvo_read_reg(tahvo, TAHVO_REG_IDR);
- im = __tahvo_read_reg(tahvo, TAHVO_REG_IMR);
- id &= ~im;
-+ __tahvo_write_reg(tahvo, TAHVO_REG_IDR, id);
-+ mutex_unlock(&tahvo->mutex);
-
- if (!id) {
- dev_vdbg(tahvo->dev, "No IRQ, spurious ?\n");
-@@ -177,11 +178,6 @@ static void tahvo_irq_bus_sync_unlock(st
- tahvo->mask_pending = false;
- }
-
-- if (tahvo->ack_pending) {
-- __tahvo_write_reg(tahvo, TAHVO_REG_IDR, tahvo->ack);
-- tahvo->ack_pending = false;
-- }
--
- mutex_unlock(&tahvo->mutex);
- }
-
-@@ -203,22 +199,12 @@ static void tahvo_irq_unmask(struct irq_
- tahvo->mask_pending = true;
- }
-
--static void tahvo_irq_ack(struct irq_data *data)
--{
-- struct tahvo *tahvo = irq_data_get_irq_chip_data(data);
-- int irq = data->irq;
--
-- tahvo->ack |= (1 << (irq - tahvo->irq_base));
-- tahvo->ack_pending = true;
--}
--
- static struct irq_chip tahvo_irq_chip = {
- .name = "tahvo",
- .irq_bus_lock = tahvo_irq_bus_lock,
- .irq_bus_sync_unlock = tahvo_irq_bus_sync_unlock,
- .irq_mask = tahvo_irq_mask,
- .irq_unmask = tahvo_irq_unmask,
-- .irq_ack = tahvo_irq_ack,
- };
-
- static inline void tahvo_irq_setup(int irq)
-@@ -238,8 +224,7 @@ static void tahvo_irq_init(struct tahvo
-
- for (irq = base; irq < end; irq++) {
- irq_set_chip_data(irq, tahvo);
-- irq_set_chip_and_handler(irq, &tahvo_irq_chip,
-- handle_simple_irq);
-+ irq_set_chip(irq, &tahvo_irq_chip);
- irq_set_nested_thread(irq, 1);
- tahvo_irq_setup(irq);
- }
+++ /dev/null
---- a/drivers/cbus/retu.c
-+++ b/drivers/cbus/retu.c
-@@ -451,7 +451,8 @@ static int __devinit retu_probe(struct p
- (rev >> 4) & 0x07, rev & 0x0f);
-
- /* Mask all RETU interrupts */
-- __retu_write_reg(retu, RETU_REG_IMR, 0xffff);
-+ retu->mask = 0xFFFF;
-+ __retu_write_reg(retu, RETU_REG_IMR, retu->mask);
-
- ret = request_threaded_irq(retu->irq, NULL, retu_irq_handler,
- IRQF_ONESHOT, "retu", retu);
---- a/drivers/cbus/tahvo.c
-+++ b/drivers/cbus/tahvo.c
-@@ -346,7 +346,8 @@ static int __devinit tahvo_probe(struct
- (rev >> 4) & 0x0f, rev & 0x0f);
-
- /* Mask all TAHVO interrupts */
-- __tahvo_write_reg(tahvo, TAHVO_REG_IMR, 0xffff);
-+ tahvo->mask = 0xFFFF;
-+ __tahvo_write_reg(tahvo, TAHVO_REG_IMR, tahvo->mask);
-
- ret = request_threaded_irq(irq, NULL, tahvo_irq_handler,
- IRQF_TRIGGER_RISING | IRQF_ONESHOT,
+++ /dev/null
---- a/arch/arm/mach-omap2/board-n8x0.c
-+++ b/arch/arm/mach-omap2/board-n8x0.c
-@@ -15,8 +15,11 @@
- #include <linux/delay.h>
- #include <linux/gpio.h>
- #include <linux/init.h>
-+#include <linux/irq.h>
- #include <linux/io.h>
- #include <linux/stddef.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/cbus.h>
- #include <linux/i2c.h>
- #include <linux/spi/spi.h>
- #include <linux/usb/musb.h>
-@@ -193,6 +196,110 @@ static struct omap_onenand_platform_data
- };
- #endif
-
-+#if defined(CONFIG_CBUS) || defined(CONFIG_CBUS_MODULE)
-+
-+static struct cbus_host_platform_data n8x0_cbus_data = {
-+ .clk_gpio = 66,
-+ .dat_gpio = 65,
-+ .sel_gpio = 64,
-+};
-+
-+static struct platform_device n8x0_cbus_device = {
-+ .name = "cbus",
-+ .id = -1,
-+ .dev = {
-+ .platform_data = &n8x0_cbus_data,
-+ },
-+};
-+
-+static struct resource retu_resource[] = {
-+ {
-+ .start = -EINVAL, /* set later */
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct cbus_retu_platform_data n8x0_retu_data = {
-+ .devid = CBUS_RETU_DEVICE_ID,
-+};
-+
-+static struct platform_device retu_device = {
-+ .name = "retu",
-+ .id = -1,
-+ .resource = retu_resource,
-+ .num_resources = ARRAY_SIZE(retu_resource),
-+ .dev = {
-+ .platform_data = &n8x0_retu_data,
-+ .parent = &n8x0_cbus_device.dev,
-+ },
-+};
-+
-+static struct resource tahvo_resource[] = {
-+ {
-+ .start = -EINVAL, /* set later */
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device tahvo_device = {
-+ .name = "tahvo",
-+ .id = -1,
-+ .resource = tahvo_resource,
-+ .num_resources = ARRAY_SIZE(tahvo_resource),
-+ .dev = {
-+ .parent = &n8x0_cbus_device.dev,
-+ },
-+};
-+
-+static void __init n8x0_cbus_init(void)
-+{
-+ int ret;
-+
-+ platform_device_register(&n8x0_cbus_device);
-+
-+ ret = gpio_request(108, "RETU irq");
-+ if (ret < 0) {
-+ pr_err("retu: Unable to reserve IRQ GPIO\n");
-+ return;
-+ }
-+
-+ ret = gpio_direction_input(108);
-+ if (ret < 0) {
-+ pr_err("retu: Unable to change gpio direction\n");
-+ gpio_free(108);
-+ return;
-+ }
-+
-+ irq_set_irq_type(gpio_to_irq(108), IRQ_TYPE_EDGE_RISING);
-+ retu_resource[0].start = gpio_to_irq(108);
-+ platform_device_register(&retu_device);
-+
-+ ret = gpio_request(111, "TAHVO irq");
-+ if (ret) {
-+ pr_err("tahvo: Unable to reserve IRQ GPIO\n");
-+ gpio_free(108);
-+ return;
-+ }
-+
-+ /* Set the pin as input */
-+ ret = gpio_direction_input(111);
-+ if (ret) {
-+ pr_err("tahvo: Unable to change direction\n");
-+ gpio_free(108);
-+ gpio_free(111);
-+ return;
-+ }
-+
-+ tahvo_resource[0].start = gpio_to_irq(111);
-+ platform_device_register(&tahvo_device);
-+}
-+
-+#else
-+static inline void __init n8x0_cbus_init(void)
-+{
-+}
-+#endif
-+
- #if defined(CONFIG_MENELAUS) && \
- (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE))
-
-@@ -671,6 +778,8 @@ static inline void board_serial_init(voi
- static void __init n8x0_init_machine(void)
- {
- omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
-+ n8x0_cbus_init();
-+
- /* FIXME: add n810 spi devices */
- spi_register_board_info(n800_spi_board_info,
- ARRAY_SIZE(n800_spi_board_info));
---- /dev/null
-+++ b/include/linux/platform_data/cbus.h
-@@ -0,0 +1,38 @@
-+/*
-+ * cbus.h - CBUS platform_data definition
-+ *
-+ * Copyright (C) 2004 - 2009 Nokia Corporation
-+ *
-+ * Written by Felipe Balbi <felipe.balbi@nokia.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General
-+ * Public License. See the file "COPYING" in the main directory of this
-+ * archive for more details.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __INCLUDE_LINUX_CBUS_H
-+#define __INCLUDE_LINUX_CBUS_H
-+
-+#define CBUS_RETU_DEVICE_ID 0x01
-+#define CBUS_TAHVO_DEVICE_ID 0x02
-+
-+struct cbus_host_platform_data {
-+ int dat_gpio;
-+ int clk_gpio;
-+ int sel_gpio;
-+};
-+
-+struct cbus_retu_platform_data {
-+ int devid;
-+};
-+
-+#endif /* __INCLUDE_LINUX_CBUS_H */
+++ /dev/null
---- a/drivers/video/omap/omapfb_main.c
-+++ b/drivers/video/omap/omapfb_main.c
-@@ -420,10 +420,10 @@ static void set_fb_fix(struct fb_info *f
- fbi->screen_base = rg->vaddr;
-
- if (!from_init) {
-- mutex_lock(&fbi->mm_lock);
-+ preempt_disable();
- fix->smem_start = rg->paddr;
- fix->smem_len = rg->size;
-- mutex_unlock(&fbi->mm_lock);
-+ preempt_enable();
- } else {
- fix->smem_start = rg->paddr;
- fix->smem_len = rg->size;
-@@ -933,10 +933,10 @@ static int omapfb_setup_mem(struct fb_in
- * plane memory is dealloce'd, the other
- * screen parameters in var / fix are invalid.
- */
-- mutex_lock(&fbi->mm_lock);
-+ preempt_disable();
- fbi->fix.smem_start = 0;
- fbi->fix.smem_len = 0;
-- mutex_unlock(&fbi->mm_lock);
-+ preempt_enable();
- }
- }
- }
---- a/drivers/video/fbmem.c
-+++ b/drivers/video/fbmem.c
-@@ -1383,8 +1383,10 @@ fb_mmap(struct file *file, struct vm_are
- }
-
- /* frame buffer memory */
-+ preempt_disable();
- start = info->fix.smem_start;
- len = PAGE_ALIGN((start & ~PAGE_MASK) + info->fix.smem_len);
-+ preempt_enable();
- if (off >= len) {
- /* memory mapped io */
- off -= len;
+++ /dev/null
---- a/arch/arm/mach-omap2/board-n8x0.c
-+++ b/arch/arm/mach-omap2/board-n8x0.c
-@@ -24,6 +24,7 @@
- #include <linux/spi/spi.h>
- #include <linux/usb/musb.h>
- #include <sound/tlv320aic3x.h>
-+#include <linux/spi/tsc2005.h>
-
- #include <asm/mach/arch.h>
- #include <asm/mach-types.h>
-@@ -43,6 +44,66 @@ static int slot1_cover_open;
- static int slot2_cover_open;
- static struct device *mmc_device;
-
-+#define RX51_TSC2005_RESET_GPIO 94
-+#define RX51_TSC2005_IRQ_GPIO 106
-+
-+#ifdef CONFIG_TOUCHSCREEN_TSC2005
-+static struct tsc2005_platform_data tsc2005_config;
-+static void rx51_tsc2005_set_reset(bool enable)
-+{
-+ gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
-+}
-+
-+static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
-+ .turbo_mode = 0,
-+ .single_channel = 1,
-+};
-+#endif
-+
-+static void __init tsc2005_set_config(void)
-+{
-+ const struct omap_lcd_config *conf;
-+
-+ conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
-+ if (conf != NULL) {
-+#ifdef CONFIG_TOUCHSCREEN_TSC2005
-+ if (strcmp(conf->panel_name, "lph8923") == 0) {
-+ tsc2005_config.ts_x_plate_ohm = 180;
-+ tsc2005_config.ts_pressure_max = 2048;
-+ tsc2005_config.ts_pressure_fudge = 2;
-+ tsc2005_config.ts_x_max = 4096;
-+ tsc2005_config.ts_x_fudge = 4;
-+ tsc2005_config.ts_y_max = 4096;
-+ tsc2005_config.ts_y_fudge = 7;
-+ tsc2005_config.set_reset = rx51_tsc2005_set_reset;
-+ } else if (strcmp(conf->panel_name, "ls041y3") == 0) {
-+ tsc2005_config.ts_x_plate_ohm = 280;
-+ tsc2005_config.ts_pressure_max = 2048;
-+ tsc2005_config.ts_pressure_fudge = 2;
-+ tsc2005_config.ts_x_max = 4096;
-+ tsc2005_config.ts_x_fudge = 4;
-+ tsc2005_config.ts_y_max = 4096;
-+ tsc2005_config.ts_y_fudge = 7;
-+ tsc2005_config.set_reset = rx51_tsc2005_set_reset;
-+ } else {
-+ printk(KERN_ERR "Unknown panel type, set default "
-+ "touchscreen configuration\n");
-+ tsc2005_config.ts_x_plate_ohm = 200;
-+ }
-+#endif
-+ }
-+}
-+
-+static struct omap2_mcspi_device_config mipid_mcspi_config = {
-+ .turbo_mode = 0,
-+ .single_channel = 1,
-+};
-+
-+extern struct mipid_platform_data n8x0_mipid_platform_data;
-+
-+extern void n8x0_mipid_init(void);
-+extern void n8x0_blizzard_init(void);
-+
- #define TUSB6010_ASYNC_CS 1
- #define TUSB6010_SYNC_CS 4
- #define TUSB6010_GPIO_INT 58
-@@ -145,12 +206,29 @@ static struct omap2_mcspi_device_config
-
- static struct spi_board_info n800_spi_board_info[] __initdata = {
- {
-+ .modalias = "lcd_mipid",
-+ .bus_num = 1,
-+ .chip_select = 1,
-+ .max_speed_hz = 4000000,
-+ .controller_data= &mipid_mcspi_config,
-+ .platform_data = &n8x0_mipid_platform_data,
-+ },
-+ {
- .modalias = "p54spi",
- .bus_num = 2,
- .chip_select = 0,
- .max_speed_hz = 48000000,
- .controller_data = &p54spi_mcspi_config,
- },
-+ {
-+ .modalias = "tsc2005",
-+ .bus_num = 1,
-+ .chip_select = 0,
-+ .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
-+ .max_speed_hz = 6000000,
-+ .controller_data = &tsc2005_mcspi_config,
-+ .platform_data = &tsc2005_config,
-+ },
- };
-
- #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
-@@ -781,6 +859,7 @@ static void __init n8x0_init_machine(voi
- n8x0_cbus_init();
-
- /* FIXME: add n810 spi devices */
-+ tsc2005_set_config();
- spi_register_board_info(n800_spi_board_info,
- ARRAY_SIZE(n800_spi_board_info));
- omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1,
-@@ -790,6 +869,8 @@ static void __init n8x0_init_machine(voi
- i2c_register_board_info(2, n810_i2c_board_info_2,
- ARRAY_SIZE(n810_i2c_board_info_2));
- board_serial_init();
-+ n8x0_mipid_init();
-+ n8x0_blizzard_init();
- omap_sdrc_init(NULL, NULL);
- gpmc_onenand_init(board_onenand_data);
- n8x0_mmc_init();
---- /dev/null
-+++ b/arch/arm/mach-omap2/board-n8x0-lcd.c
-@@ -0,0 +1,231 @@
-+/*
-+ * linux/arch/arm/mach-omap2/board-n8x0.c
-+ *
-+ * Copyright (C) 2005-2009 Nokia Corporation
-+ * Author: Juha Yrjola <juha.yrjola@nokia.com>
-+ *
-+ * Modified from mach-omap2/board-generic.c
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/gpio.h>
-+#include <linux/omapfb.h>
-+
-+#include <plat/lcd_mipid.h>
-+#include <plat/blizzard.h>
-+
-+#include "../../../drivers/cbus/tahvo.h"
-+
-+
-+struct tahvo_pwm_device {
-+ struct device *dev;
-+ int tahvo_7bit_backlight;
-+};
-+
-+static struct tahvo_pwm_device *tahvo_pwm;
-+
-+static unsigned int tahvo_pwm_get_backlight_level(struct tahvo_pwm_device *pd)
-+{
-+ unsigned int mask;
-+
-+ if (pd->tahvo_7bit_backlight)
-+ mask = 0x7f;
-+ else
-+ mask = 0x0f;
-+ return tahvo_read_reg(pd->dev, TAHVO_REG_LEDPWMR) & mask;
-+}
-+
-+static unsigned int tahvo_pwm_get_max_backlight_level(struct tahvo_pwm_device *pd)
-+{
-+ if (pd->tahvo_7bit_backlight)
-+ return 0x7f;
-+ return 0x0f;
-+}
-+
-+static void tahvo_pwm_set_backlight_level(struct tahvo_pwm_device *pd, unsigned int level)
-+{
-+ unsigned int max_level;
-+
-+ max_level = tahvo_pwm_get_max_backlight_level(pd);
-+ if (level > max_level)
-+ level = max_level;
-+ tahvo_write_reg(pd->dev, TAHVO_REG_LEDPWMR, level);
-+}
-+
-+static int __init n8x0_tahvo_pwm_probe(struct platform_device *pdev)
-+{
-+ struct tahvo_pwm_device *pd;
-+ unsigned int rev, id;
-+
-+ pd = kzalloc(sizeof(*pd), GFP_KERNEL);
-+ if (WARN_ON(!pd))
-+ return -ENOMEM;
-+ pd->dev = &pdev->dev;
-+
-+ rev = tahvo_read_reg(pd->dev, TAHVO_REG_ASICR);
-+ id = (rev >> 8) & 0xff;
-+ if (id == 0x03) {
-+ if ((rev & 0xff) >= 0x50)
-+ pd->tahvo_7bit_backlight = 1;
-+ } else if (id == 0x0b)
-+ pd->tahvo_7bit_backlight = 1;
-+
-+ dev_set_drvdata(pd->dev, pd);
-+ tahvo_pwm = pd;
-+
-+ return 0;
-+}
-+
-+static struct platform_driver n8x0_tahvo_pwm_driver = {
-+ .driver = {
-+ .name = "tahvo-pwm",
-+ },
-+};
-+
-+static int __init n8x0_tahvo_pwm_init(void)
-+{
-+ return platform_driver_probe(&n8x0_tahvo_pwm_driver, n8x0_tahvo_pwm_probe);
-+}
-+fs_initcall(n8x0_tahvo_pwm_init);
-+
-+static int n8x0_get_backlight_level(struct mipid_platform_data *pdata)
-+{
-+ return tahvo_pwm_get_backlight_level(tahvo_pwm);
-+}
-+
-+static int n8x0_get_max_backlight_level(struct mipid_platform_data *pdata)
-+{
-+ return tahvo_pwm_get_max_backlight_level(tahvo_pwm);
-+}
-+
-+static void n8x0_set_backlight_level(struct mipid_platform_data *pdata, int level)
-+{
-+ tahvo_pwm_set_backlight_level(tahvo_pwm, level);
-+}
-+
-+#define N8X0_BLIZZARD_POWERDOWN_GPIO 15
-+
-+// MIPID LCD Panel
-+
-+static void mipid_shutdown(struct mipid_platform_data *pdata)
-+{
-+ if (pdata->nreset_gpio != -1) {
-+ pr_info("shutdown LCD\n");
-+ gpio_set_value(pdata->nreset_gpio, 0);
-+ msleep(120);
-+ }
-+}
-+
-+struct mipid_platform_data n8x0_mipid_platform_data = {
-+ .shutdown = mipid_shutdown,
-+ .get_bklight_level = n8x0_get_backlight_level,
-+ .set_bklight_level = n8x0_set_backlight_level,
-+ .get_bklight_max = n8x0_get_max_backlight_level,
-+};
-+
-+void __init n8x0_mipid_init(void)
-+{
-+ const struct omap_lcd_config *conf;
-+ int err;
-+
-+ conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
-+ if (conf != NULL) {
-+ n8x0_mipid_platform_data.nreset_gpio = conf->nreset_gpio;
-+ n8x0_mipid_platform_data.data_lines = conf->data_lines;
-+ if (conf->nreset_gpio != -1) {
-+ err = gpio_request(conf->nreset_gpio, "MIPID nreset");
-+ if (err) {
-+ printk(KERN_ERR "N8x0 MIPID failed to request nreset GPIO %d\n",
-+ conf->nreset_gpio);
-+ } else {
-+ err = gpio_direction_output(conf->nreset_gpio, 1);
-+ if (err) {
-+ printk(KERN_ERR "N8x0 MIPID failed to set nreset GPIO %d\n",
-+ conf->nreset_gpio);
-+ }
-+ }
-+ }
-+ printk(KERN_INFO "N8x0 MIPID config loaded");
-+ }
-+ else
-+ printk(KERN_INFO "N8x0 MIPID config not provided");
-+}
-+
-+
-+// Epson Blizzard LCD Controller
-+
-+static struct {
-+ struct clk *sys_ck;
-+} blizzard;
-+
-+static int blizzard_get_clocks(void)
-+{
-+ blizzard.sys_ck = clk_get(0, "osc_ck");
-+ if (IS_ERR(blizzard.sys_ck)) {
-+ printk(KERN_ERR "can't get Blizzard clock\n");
-+ return PTR_ERR(blizzard.sys_ck);
-+ }
-+ return 0;
-+}
-+
-+static unsigned long blizzard_get_clock_rate(struct device *dev)
-+{
-+ return clk_get_rate(blizzard.sys_ck);
-+}
-+
-+static void blizzard_enable_clocks(int enable)
-+{
-+ if (enable)
-+ clk_enable(blizzard.sys_ck);
-+ else
-+ clk_disable(blizzard.sys_ck);
-+}
-+
-+static void blizzard_power_up(struct device *dev)
-+{
-+ /* Vcore to 1.475V */
-+ tahvo_set_clear_reg_bits(tahvo_pwm->dev, 0x07, 0, 0xf);
-+ msleep(10);
-+
-+ blizzard_enable_clocks(1);
-+ gpio_set_value(N8X0_BLIZZARD_POWERDOWN_GPIO, 1);
-+}
-+
-+static void blizzard_power_down(struct device *dev)
-+{
-+ gpio_set_value(N8X0_BLIZZARD_POWERDOWN_GPIO, 0);
-+ blizzard_enable_clocks(0);
-+
-+ /* Vcore to 1.005V */
-+ tahvo_set_clear_reg_bits(tahvo_pwm->dev, 0x07, 0xf, 0);
-+}
-+
-+static struct blizzard_platform_data n8x0_blizzard_data = {
-+ .power_up = blizzard_power_up,
-+ .power_down = blizzard_power_down,
-+ .get_clock_rate = blizzard_get_clock_rate,
-+ .te_connected = 1,
-+};
-+
-+void __init n8x0_blizzard_init(void)
-+{
-+ int r;
-+
-+ r = gpio_request(N8X0_BLIZZARD_POWERDOWN_GPIO, "Blizzard pd");
-+ if (r < 0)
-+ {
-+ printk(KERN_ERR "Can't get N8x0 Blizzard powerdown GPIO %d\n", N8X0_BLIZZARD_POWERDOWN_GPIO);
-+ return;
-+ }
-+ gpio_direction_output(N8X0_BLIZZARD_POWERDOWN_GPIO, 1);
-+
-+ blizzard_get_clocks();
-+ omapfb_set_ctrl_platform_data(&n8x0_blizzard_data);
-+
-+ printk(KERN_INFO "N8x0 Blizzard initialized");
-+}
---- a/arch/arm/mach-omap2/Makefile
-+++ b/arch/arm/mach-omap2/Makefile
-@@ -205,6 +205,7 @@ obj-$(CONFIG_MACH_OMAP3EVM) += board-om
- obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o
- obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o
- obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
-+obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0-lcd.o
- obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o \
- sdram-nokia.o
- obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \
+++ /dev/null
---- a/drivers/video/omap/dispc.c
-+++ b/drivers/video/omap/dispc.c
-@@ -923,14 +923,14 @@ static int get_dss_clocks(void)
- return PTR_ERR(dispc.dss_ick);
- }
-
-- dispc.dss1_fck = clk_get(&dispc.fbdev->dssdev->dev, "fck");
-+ dispc.dss1_fck = clk_get(&dispc.fbdev->dssdev->dev, "dss1_fck");
- if (IS_ERR(dispc.dss1_fck)) {
- dev_err(dispc.fbdev->dev, "can't get dss1_fck\n");
- clk_put(dispc.dss_ick);
- return PTR_ERR(dispc.dss1_fck);
- }
-
-- dispc.dss_54m_fck = clk_get(&dispc.fbdev->dssdev->dev, "tv_clk");
-+ dispc.dss_54m_fck = clk_get(&dispc.fbdev->dssdev->dev, "dss_54m_fck");
- if (IS_ERR(dispc.dss_54m_fck)) {
- dev_err(dispc.fbdev->dev, "can't get tv_fck\n");
- clk_put(dispc.dss_ick);
---- a/drivers/video/omap/rfbi.c
-+++ b/drivers/video/omap/rfbi.c
-@@ -90,7 +90,7 @@ static int rfbi_get_clocks(void)
- return PTR_ERR(rfbi.dss_ick);
- }
-
-- rfbi.dss1_fck = clk_get(&rfbi.fbdev->dssdev->dev, "fck");
-+ rfbi.dss1_fck = clk_get(&rfbi.fbdev->dssdev->dev, "dss1_fck");
- if (IS_ERR(rfbi.dss1_fck)) {
- dev_err(rfbi.fbdev->dev, "can't get dss1_fck\n");
- clk_put(rfbi.dss_ick);
+++ /dev/null
---- a/arch/arm/mach-omap2/omap_hwmod.c
-+++ b/arch/arm/mach-omap2/omap_hwmod.c
-@@ -146,6 +146,8 @@
- #include <plat/omap_hwmod.h>
- #include <plat/prcm.h>
-
-+#include <asm/mach-types.h>
-+
- #include "cm2xxx_3xxx.h"
- #include "cminst44xx.h"
- #include "prm2xxx_3xxx.h"
-@@ -1769,6 +1771,16 @@ static int _setup(struct omap_hwmod *oh,
-
- oh->_state = _HWMOD_STATE_INITIALIZED;
-
-+ if (machine_is_nokia770() ||
-+ machine_is_nokia_n800() ||
-+ machine_is_nokia_n810() ||
-+ machine_is_nokia_n810_wimax()) {
-+ /* Nokia N-series workaround: Don't reset any hwmod. Some drivers expect
-+ * the NOLO bootloader initializations to be effective. */
-+ oh->flags |= HWMOD_INIT_NO_RESET;
-+ printk_once(KERN_INFO "Nokia N-series HWMOD_INIT_NO_RESET workaround enabled\n");
-+ }
-+
- /*
- * In the case of hwmod with hardreset that should not be
- * de-assert at boot time, we have to keep the module
+++ /dev/null
-From 63e56392b9024aceb610d7b4e1979e2d2cebd217 Mon Sep 17 00:00:00 2001
-From: Marat Radchenko <marat@slonopotamus.org>
-Date: Tue, 18 Oct 2011 21:48:23 +0400
-Subject: [PATCH 1/2] TSC2301 driver (touchscreen and keypad)
-
-This patch adds support for TSC2301 touchscreen/keypad/audio chip found on Nokia N800.
-Touchscreen and keypad are fully functional, audio part only provides power management.
----
- drivers/input/keyboard/Kconfig | 6 +
- drivers/input/keyboard/Makefile | 1 +
- drivers/input/keyboard/tsc2301_kp.c | 475 +++++++++++++++
- drivers/input/touchscreen/Kconfig | 6 +
- drivers/input/touchscreen/Makefile | 1 +
- drivers/input/touchscreen/tsc2301_ts.c | 676 +++++++++++++++++++++
- drivers/spi/Kconfig | 22 +
- drivers/spi/Makefile | 3 +
- drivers/spi/tsc2301-core.c | 297 ++++++++++
- drivers/spi/tsc2301-mixer.c | 1003 ++++++++++++++++++++++++++++++++
- include/linux/spi/tsc2301.h | 208 +++++++
- 11 files changed, 2698 insertions(+), 0 deletions(-)
- create mode 100644 drivers/input/keyboard/tsc2301_kp.c
- create mode 100644 drivers/input/touchscreen/tsc2301_ts.c
- create mode 100644 drivers/spi/tsc2301-core.c
- create mode 100644 drivers/spi/tsc2301-mixer.c
- create mode 100644 include/linux/spi/tsc2301.h
-
---- a/drivers/input/keyboard/Kconfig
-+++ b/drivers/input/keyboard/Kconfig
-@@ -547,6 +547,12 @@ config KEYBOARD_TNETV107X
- To compile this driver as a module, choose M here: the
- module will be called tnetv107x-keypad.
-
-+config KEYBOARD_TSC2301
-+ tristate "TSC2301 keypad support"
-+ depends on SPI_TSC2301
-+ help
-+ Say Y here for if you are using the keypad features of TSC2301.
-+
- config KEYBOARD_TWL4030
- tristate "TI TWL4030/TWL5030/TPS659x0 keypad support"
- depends on TWL4030_CORE
---- a/drivers/input/keyboard/Makefile
-+++ b/drivers/input/keyboard/Makefile
-@@ -49,6 +49,7 @@ obj-$(CONFIG_KEYBOARD_SUNKBD) += sunkbd
- obj-$(CONFIG_KEYBOARD_TC3589X) += tc3589x-keypad.o
- obj-$(CONFIG_KEYBOARD_TEGRA) += tegra-kbc.o
- obj-$(CONFIG_KEYBOARD_TNETV107X) += tnetv107x-keypad.o
-+obj-$(CONFIG_KEYBOARD_TSC2301) += tsc2301_kp.o
- obj-$(CONFIG_KEYBOARD_TWL4030) += twl4030_keypad.o
- obj-$(CONFIG_KEYBOARD_XTKBD) += xtkbd.o
- obj-$(CONFIG_KEYBOARD_W90P910) += w90p910_keypad.o
---- /dev/null
-+++ b/drivers/input/keyboard/tsc2301_kp.c
-@@ -0,0 +1,475 @@
-+/*
-+ * TSC2301 keypad driver
-+ *
-+ * Copyright (C) 2005-2006 Nokia Corporation
-+ *
-+ * Written by Jarkko Oikarinen
-+ * Rewritten by Juha Yrjola <juha.yrjola@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/input.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/delay.h>
-+#include <linux/spi/spi.h>
-+
-+#include <linux/spi/tsc2301.h>
-+
-+#define TSC2301_KEYBOARD_PRODUCT_ID 0x0051
-+#define TSC2301_KEYBOARD_PRODUCT_VERSION 0x0001
-+#define TSC2301_DEBOUNCE_TIME_2MS 0x0000
-+#define TSC2301_DEBOUNCE_TIME_10MS 0x0800
-+#define TSC2301_DEBOUNCE_TIME_20MS 0x1000
-+#define TSC2301_DEBOUNCE_TIME_50MS 0x1800
-+#define TSC2301_DEBOUNCE_TIME_60MS 0x2000
-+#define TSC2301_DEBOUNCE_TIME_80MS 0x2800
-+#define TSC2301_DEBOUNCE_TIME_100MS 0x3000
-+#define TSC2301_DEBOUNCE_TIME_120MS 0x3800
-+
-+#define TSC2301_DEBOUNCE_TIME TSC2301_DEBOUNCE_TIME_20MS
-+
-+#define TSC2301_RELEASE_TIMEOUT 50
-+
-+struct tsc2301_kp {
-+ struct input_dev *idev;
-+ char phys[32];
-+ spinlock_t lock;
-+ struct mutex mutex;
-+ struct timer_list timer;
-+ u16 keys_pressed;
-+ unsigned pending:1;
-+ unsigned user_disabled:1;
-+ unsigned disable_depth;
-+
-+ struct spi_transfer read_xfer[4];
-+ struct spi_message read_msg;
-+
-+ u16 data;
-+ u16 mask;
-+
-+ int irq;
-+ s16 keymap[16];
-+};
-+
-+static inline int tsc2301_kp_disabled(struct tsc2301 *tsc)
-+{
-+ return tsc->kp->disable_depth != 0;
-+}
-+
-+static void tsc2301_kp_send_key_events(struct tsc2301 *tsc,
-+ u16 prev_state,
-+ u16 new_state)
-+{
-+ struct tsc2301_kp *kp = tsc->kp;
-+ u16 common, released, pressed;
-+ int i;
-+
-+ common = prev_state & new_state;
-+ released = common ^ prev_state;
-+ pressed = common ^ new_state;
-+ if (!released && !pressed)
-+ return;
-+ for (i = 0; i < 16 && (released || pressed); i++) {
-+ if (released & 1) {
-+ dev_dbg(&tsc->spi->dev, "key %d released\n", i);
-+ input_report_key(kp->idev, kp->keymap[i], 0);
-+ }
-+ released >>= 1;
-+ if (pressed & 1) {
-+ dev_dbg(&tsc->spi->dev, "key %d pressed\n", i);
-+ input_report_key(kp->idev, kp->keymap[i], 1);
-+ }
-+ pressed >>= 1;
-+ }
-+ input_sync(kp->idev);
-+}
-+
-+static inline void _filter_out(struct tsc2301 *tsc, u16 prev_state,
-+ u16 *new_state, int row1, int row2, u8 rect_pat)
-+{
-+ u16 mask;
-+
-+ mask = (rect_pat << (row1 * 4)) | (rect_pat << (row2 * 4));
-+ mask &= ~prev_state;
-+ *new_state &= ~mask;
-+ dev_dbg(&tsc->spi->dev, "filtering ghost keys %02x\n", mask);
-+}
-+
-+static void tsc2301_filter_ghost_keys(struct tsc2301 *tsc, u16 prev_state,
-+ u16 *new_state)
-+{
-+ int row1, row2;
-+ u16 key_map;
-+ u16 row1_map;
-+ static const u8 rect_pat[] = {
-+ 0x3, 0x5, 0x9, 0x6, 0xa, 0xc, 0,
-+ };
-+
-+ key_map = *new_state;
-+ for (row1 = 0; row1 < 4; row1++) {
-+ row1_map = (key_map >> (row1 * 4)) & 0xf;
-+ if (!row1_map)
-+ continue;
-+ for (row2 = row1 + 1; row2 < 4; row2++) {
-+ u16 rect_map = (key_map >> (row2 * 4)) & 0xf;
-+ const u8 *rp;
-+
-+ rect_map &= row1_map;
-+ if (!rect_map)
-+ continue;
-+ for (rp = rect_pat; *rp; rp++)
-+ if ((rect_map & *rp) == *rp)
-+ _filter_out(tsc, prev_state, new_state,
-+ row1, row2, *rp);
-+ }
-+ }
-+}
-+
-+static void tsc2301_kp_timer(unsigned long arg)
-+{
-+ struct tsc2301 *tsc = (void *) arg;
-+ struct tsc2301_kp *kp = tsc->kp;
-+ unsigned long flags;
-+
-+ tsc2301_kp_send_key_events(tsc, kp->keys_pressed, 0);
-+ spin_lock_irqsave(&kp->lock, flags);
-+ kp->keys_pressed = 0;
-+ spin_unlock_irqrestore(&kp->lock, flags);
-+}
-+
-+static void tsc2301_kp_rx(void *arg)
-+{
-+ struct tsc2301 *tsc = arg;
-+ struct tsc2301_kp *kp = tsc->kp;
-+ unsigned long flags;
-+ u16 kp_data;
-+
-+ kp_data = kp->data;
-+ dev_dbg(&tsc->spi->dev, "KP data %04x\n", kp_data);
-+
-+ tsc2301_filter_ghost_keys(tsc, kp->keys_pressed, &kp_data);
-+ tsc2301_kp_send_key_events(tsc, kp->keys_pressed, kp_data);
-+ spin_lock_irqsave(&kp->lock, flags);
-+ kp->keys_pressed = kp_data;
-+ kp->pending = 0;
-+ spin_unlock_irqrestore(&kp->lock, flags);
-+}
-+
-+static irqreturn_t tsc2301_kp_irq_handler(int irq, void *dev_id)
-+{
-+ struct tsc2301 *tsc = dev_id;
-+ struct tsc2301_kp *kp = tsc->kp;
-+ unsigned long flags;
-+ int r;
-+
-+ spin_lock_irqsave(&kp->lock, flags);
-+ if (tsc2301_kp_disabled(tsc)) {
-+ spin_unlock_irqrestore(&kp->lock, flags);
-+ return IRQ_HANDLED;
-+ }
-+ kp->pending = 1;
-+ spin_unlock_irqrestore(&kp->lock, flags);
-+ mod_timer(&kp->timer,
-+ jiffies + msecs_to_jiffies(TSC2301_RELEASE_TIMEOUT));
-+ r = spi_async(tsc->spi, &tsc->kp->read_msg);
-+ if (r)
-+ dev_err(&tsc->spi->dev, "kp: spi_async() failed");
-+ return IRQ_HANDLED;
-+}
-+
-+static void tsc2301_kp_start_scan(struct tsc2301 *tsc)
-+{
-+ tsc2301_write_reg(tsc, TSC2301_REG_KPMASK, tsc->kp->mask);
-+ tsc2301_write_reg(tsc, TSC2301_REG_KEY, TSC2301_DEBOUNCE_TIME);
-+}
-+
-+static void tsc2301_kp_stop_scan(struct tsc2301 *tsc)
-+{
-+ tsc2301_write_reg(tsc, TSC2301_REG_KEY, 1 << 14);
-+}
-+
-+/* Must be called with the mutex held */
-+static void tsc2301_kp_enable(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_kp *kp = tsc->kp;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&kp->lock, flags);
-+ BUG_ON(!tsc2301_kp_disabled(tsc));
-+ if (--kp->disable_depth != 0) {
-+ spin_unlock_irqrestore(&kp->lock, flags);
-+ return;
-+ }
-+ spin_unlock_irqrestore(&kp->lock, flags);
-+
-+ irq_set_irq_type(kp->irq, IRQ_TYPE_EDGE_FALLING);
-+ tsc2301_kp_start_scan(tsc);
-+ enable_irq(kp->irq);
-+}
-+
-+/* Must be called with the mutex held */
-+static int tsc2301_kp_disable(struct tsc2301 *tsc, int release_keys)
-+{
-+ struct tsc2301_kp *kp = tsc->kp;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&kp->lock, flags);
-+ if (kp->disable_depth++ != 0) {
-+ spin_unlock_irqrestore(&kp->lock, flags);
-+ goto out;
-+ }
-+ disable_irq_nosync(kp->irq);
-+ irq_set_irq_type(kp->irq, IRQ_TYPE_NONE);
-+ spin_unlock_irqrestore(&kp->lock, flags);
-+
-+ while (kp->pending) {
-+ msleep(1);
-+ }
-+
-+ tsc2301_kp_stop_scan(tsc);
-+out:
-+ if (!release_keys)
-+ del_timer(&kp->timer); /* let timeout release keys */
-+
-+ return 0;
-+}
-+
-+/* The following workaround is needed for a HW bug triggered by the
-+ * following:
-+ * 1. keep any key pressed
-+ * 2. disable keypad
-+ * 3. release all keys
-+ * 4. reenable keypad
-+ * 5. disable touch screen controller
-+ *
-+ * After this the keypad scanner will get stuck in busy state and won't
-+ * report any interrupts for further keypresses. One way to recover is to
-+ * restart the keypad scanner whenever we enable / disable the
-+ * touchscreen controller.
-+ */
-+void tsc2301_kp_restart(struct tsc2301 *tsc)
-+{
-+ if (!tsc2301_kp_disabled(tsc)) {
-+ tsc2301_kp_start_scan(tsc);
-+ }
-+}
-+
-+static ssize_t tsc2301_kp_disable_show(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct tsc2301 *tsc = dev_get_drvdata(dev);
-+
-+ return sprintf(buf, "%u\n", tsc2301_kp_disabled(tsc) ? 1 : 0);
-+}
-+
-+static ssize_t tsc2301_kp_disable_store(struct device *dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct tsc2301 *tsc = dev_get_drvdata(dev);
-+ struct tsc2301_kp *kp = tsc->kp;
-+ char *endp;
-+ int i;
-+
-+ i = simple_strtoul(buf, &endp, 10);
-+ i = i ? 1 : 0;
-+
-+ mutex_lock(&kp->mutex);
-+ if (i == kp->user_disabled) {
-+ mutex_unlock(&kp->mutex);
-+ return count;
-+ }
-+ kp->user_disabled = i;
-+
-+ if (i)
-+ tsc2301_kp_disable(tsc, 1);
-+ else
-+ tsc2301_kp_enable(tsc);
-+ mutex_unlock(&kp->mutex);
-+
-+ return count;
-+}
-+
-+static DEVICE_ATTR(disable_kp, 0664, tsc2301_kp_disable_show,
-+ tsc2301_kp_disable_store);
-+
-+static const u16 tsc2301_kp_read_data = 0x8000 | TSC2301_REG_KPDATA;
-+
-+static void tsc2301_kp_setup_spi_xfer(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_kp *kp = tsc->kp;
-+ struct spi_message *m = &kp->read_msg;
-+ struct spi_transfer *x = &kp->read_xfer[0];
-+
-+ spi_message_init(&kp->read_msg);
-+
-+ x->tx_buf = &tsc2301_kp_read_data;
-+ x->len = 2;
-+ spi_message_add_tail(x, m);
-+ x++;
-+
-+ x->rx_buf = &kp->data;
-+ x->len = 2;
-+ spi_message_add_tail(x, m);
-+
-+ m->complete = tsc2301_kp_rx;
-+ m->context = tsc;
-+}
-+
-+#ifdef CONFIG_PM
-+int tsc2301_kp_suspend(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_kp *kp = tsc->kp;
-+
-+ mutex_lock(&kp->mutex);
-+ tsc2301_kp_disable(tsc, 1);
-+ mutex_unlock(&kp->mutex);
-+ return 0;
-+}
-+
-+void tsc2301_kp_resume(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_kp *kp = tsc->kp;
-+
-+ mutex_lock(&kp->mutex);
-+ tsc2301_kp_enable(tsc);
-+ mutex_unlock(&kp->mutex);
-+}
-+#endif
-+
-+int __devinit tsc2301_kp_init(struct tsc2301 *tsc,
-+ struct tsc2301_platform_data *pdata)
-+{
-+ struct input_dev *idev;
-+ struct tsc2301_kp *kp;
-+ int r, i;
-+ u16 mask;
-+
-+ if (pdata->keyb_int < 0) {
-+ dev_err(&tsc->spi->dev, "need kbirq");
-+ return -EINVAL;
-+ }
-+
-+ kp = kzalloc(sizeof(*kp), GFP_KERNEL);
-+ if (kp == NULL)
-+ return -ENOMEM;
-+ tsc->kp = kp;
-+
-+ kp->irq = pdata->keyb_int;
-+ spin_lock_init(&kp->lock);
-+ mutex_init(&kp->mutex);
-+
-+ init_timer(&kp->timer);
-+ kp->timer.data = (unsigned long) tsc;
-+ kp->timer.function = tsc2301_kp_timer;
-+
-+ idev = input_allocate_device();
-+ if (idev == NULL) {
-+ r = -ENOMEM;
-+ goto err1;
-+ }
-+ if (pdata->keyb_name)
-+ idev->name = pdata->keyb_name;
-+ else
-+ idev->name = "TSC2301 keypad";
-+ snprintf(kp->phys, sizeof(kp->phys), "%s/input-kp", dev_name(&tsc->spi->dev));
-+ idev->phys = kp->phys;
-+
-+ mask = 0;
-+ idev->evbit[0] = BIT(EV_KEY);
-+ for (i = 0; i < 16; i++) {
-+ if (pdata->keymap[i] > 0) {
-+ set_bit(pdata->keymap[i], idev->keybit);
-+ kp->keymap[i] = pdata->keymap[i];
-+ } else {
-+ kp->keymap[i] = -1;
-+ mask |= 1 << i;
-+ }
-+ }
-+
-+ if (pdata->kp_rep)
-+ set_bit(EV_REP, idev->evbit);
-+
-+ kp->idev = idev;
-+
-+ tsc2301_kp_setup_spi_xfer(tsc);
-+
-+ r = device_create_file(&tsc->spi->dev, &dev_attr_disable_kp);
-+ if (r < 0)
-+ goto err2;
-+
-+ tsc2301_kp_start_scan(tsc);
-+
-+ /* IRQ mode 0 is faulty, it can cause the KBIRQ to get stuck.
-+ * Mode 2 deasserts the IRQ at:
-+ * - HW or SW reset
-+ * - Setting SCS flag in REG_KEY register
-+ * - Releasing all keys
-+ * - Reading the REG_KPDATA
-+ */
-+ tsc2301_write_kbc(tsc, 2);
-+
-+ tsc2301_write_reg(tsc, TSC2301_REG_KPMASK, mask);
-+ kp->mask = mask;
-+
-+ irq_set_irq_type(kp->irq, IRQ_TYPE_EDGE_FALLING);
-+
-+ r = request_irq(kp->irq, tsc2301_kp_irq_handler, 0,
-+ "tsc2301-kp", tsc);
-+ if (r < 0) {
-+ dev_err(&tsc->spi->dev, "unable to get kbirq IRQ");
-+ goto err3;
-+ }
-+ irq_set_irq_wake(kp->irq, 1);
-+
-+ /* We need to read the register once..? */
-+ tsc2301_read_reg(tsc, TSC2301_REG_KPDATA);
-+
-+ r = input_register_device(idev);
-+ if (r < 0) {
-+ dev_err(&tsc->spi->dev, "can't register keypad device\n");
-+ goto err4;
-+ }
-+
-+ return 0;
-+
-+err4:
-+ free_irq(kp->irq, tsc);
-+err3:
-+ tsc2301_kp_stop_scan(tsc);
-+ device_remove_file(&tsc->spi->dev, &dev_attr_disable_kp);
-+err2:
-+ input_free_device(kp->idev);
-+err1:
-+ kfree(kp);
-+ return r;
-+}
-+
-+void __devexit tsc2301_kp_exit(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_kp *kp = tsc->kp;
-+
-+ tsc2301_kp_disable(tsc, 1);
-+ input_unregister_device(kp->idev);
-+ free_irq(kp->irq, tsc);
-+ device_remove_file(&tsc->spi->dev, &dev_attr_disable_kp);
-+
-+ kfree(kp);
-+}
---- a/drivers/input/touchscreen/Kconfig
-+++ b/drivers/input/touchscreen/Kconfig
-@@ -726,6 +726,12 @@ config TOUCHSCREEN_TSC2007
- To compile this driver as a module, choose M here: the
- module will be called tsc2007.
-
-+config TOUCHSCREEN_TSC2301
-+ tristate "TSC2301 touchscreen support"
-+ depends on SPI_TSC2301
-+ help
-+ Say Y here for if you are using the touchscreen features of TSC2301.
-+
- config TOUCHSCREEN_W90X900
- tristate "W90P910 touchscreen driver"
- depends on HAVE_CLK
---- a/drivers/input/touchscreen/Makefile
-+++ b/drivers/input/touchscreen/Makefile
-@@ -52,6 +52,7 @@ obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += to
- obj-$(CONFIG_TOUCHSCREEN_TSC_SERIO) += tsc40.o
- obj-$(CONFIG_TOUCHSCREEN_TSC2005) += tsc2005.o
- obj-$(CONFIG_TOUCHSCREEN_TSC2007) += tsc2007.o
-+obj-$(CONFIG_TOUCHSCREEN_TSC2301) += tsc2301_ts.o
- obj-$(CONFIG_TOUCHSCREEN_UCB1400) += ucb1400_ts.o
- obj-$(CONFIG_TOUCHSCREEN_WACOM_W8001) += wacom_w8001.o
- obj-$(CONFIG_TOUCHSCREEN_WM831X) += wm831x-ts.o
---- /dev/null
-+++ b/drivers/input/touchscreen/tsc2301_ts.c
-@@ -0,0 +1,676 @@
-+/*
-+ * TSC2301 touchscreen driver
-+ *
-+ * Copyright (C) 2005-2008 Nokia Corporation
-+ *
-+ * Written by Jarkko Oikarinen, Imre Deak and Juha Yrjola
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/input.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <linux/spi/spi.h>
-+
-+#include <linux/spi/tsc2301.h>
-+
-+/**
-+ * The touchscreen interface operates as follows:
-+ *
-+ * Initialize:
-+ * Request access to GPIO103 (DAV)
-+ * tsc2301_ts_irq_handler will trigger when DAV line goes down
-+ *
-+ * 1) Pen is pressed against touchscreeen
-+ * 2) TSC2301 performs AD conversion
-+ * 3) After the conversion is done TSC2301 drives DAV line down
-+ * 4) GPIO IRQ is received and tsc2301_ts_irq_handler is called
-+ * 5) tsc2301_ts_irq_handler queues up an spi transfer to fetch
-+ * the x, y, z1, z2 values
-+ * 6) SPI framework calls tsc2301_ts_rx after the coordinates are read
-+ * 7) When the penup_timer expires, there have not been DAV interrupts
-+ * during the last 20ms which means the pen has been lifted.
-+ */
-+
-+
-+#define TSC2301_TOUCHSCREEN_PRODUCT_ID 0x0052
-+#define TSC2301_TOUCHSCREEN_PRODUCT_VERSION 0x0001
-+
-+#define TSC2301_TS_PENUP_TIME 20
-+
-+#define TSC2301_ADCREG_CONVERSION_CTRL_BY_TSC2301 0x8000
-+#define TSC2301_ADCREG_CONVERSION_CTRL_BY_HOST 0x0000
-+
-+#define TSC2301_ADCREG_FUNCTION_NONE 0x0000
-+#define TSC2301_ADCREG_FUNCTION_XY 0x0400
-+#define TSC2301_ADCREG_FUNCTION_XYZ 0x0800
-+#define TSC2301_ADCREG_FUNCTION_X 0x0C00
-+#define TSC2301_ADCREG_FUNCTION_Y 0x1000
-+#define TSC2301_ADCREG_FUNCTION_Z 0x1400
-+#define TSC2301_ADCREG_FUNCTION_DAT1 0x1800
-+#define TSC2301_ADCREG_FUNCTION_DAT2 0x1C00
-+#define TSC2301_ADCREG_FUNCTION_AUX1 0x2000
-+#define TSC2301_ADCREG_FUNCTION_AUX2 0x2400
-+#define TSC2301_ADCREG_FUNCTION_TEMP 0x2800
-+
-+#define TSC2301_ADCREG_RESOLUTION_8BIT 0x0100
-+#define TSC2301_ADCREG_RESOLUTION_10BIT 0x0200
-+#define TSC2301_ADCREG_RESOLUTION_12BIT 0x0300
-+
-+#define TSC2301_ADCREG_AVERAGING_NONE 0x0000
-+#define TSC2301_ADCREG_AVERAGING_4AVG 0x0040
-+#define TSC2301_ADCREG_AVERAGING_8AVG 0x0080
-+#define TSC2301_ADCREG_AVERAGING_16AVG 0x00C0
-+
-+#define TSC2301_ADCREG_CLOCK_8MHZ 0x0000
-+#define TSC2301_ADCREG_CLOCK_4MHZ 0x0010
-+#define TSC2301_ADCREG_CLOCK_2MHZ 0x0020
-+#define TSC2301_ADCREG_CLOCK_1MHZ 0x0030
-+
-+#define TSC2301_ADCREG_VOLTAGE_STAB_0US 0x0000
-+#define TSC2301_ADCREG_VOLTAGE_STAB_100US 0x0002
-+#define TSC2301_ADCREG_VOLTAGE_STAB_500US 0x0004
-+#define TSC2301_ADCREG_VOLTAGE_STAB_1MS 0x0006
-+#define TSC2301_ADCREG_VOLTAGE_STAB_5MS 0x0008
-+#define TSC2301_ADCREG_VOLTAGE_STAB_10MS 0x000A
-+#define TSC2301_ADCREG_VOLTAGE_STAB_50MS 0x000C
-+#define TSC2301_ADCREG_VOLTAGE_STAB_100MS 0x000E
-+
-+#define TSC2301_ADCREG_STOP_CONVERSION 0x4000
-+
-+#define MAX_12BIT ((1 << 12) - 1)
-+
-+#define TS_RECT_SIZE 8
-+#define TSF_MIN_Z1 100
-+#define TSF_MAX_Z2 4000
-+
-+#define TSF_SAMPLES 4
-+
-+struct ts_filter {
-+ int sample_cnt;
-+
-+ int avg_x;
-+ int avg_y;
-+ int avg_z1;
-+ int avg_z2;
-+};
-+
-+struct ts_coords {
-+ u16 x;
-+ u16 y;
-+ u16 z1;
-+ u16 z2;
-+};
-+
-+struct tsc2301_ts {
-+ struct input_dev *idev;
-+ char phys[32];
-+ struct timer_list penup_timer;
-+ struct mutex mutex;
-+
-+ struct spi_transfer read_xfer[2];
-+ struct spi_message read_msg;
-+ struct ts_coords *coords;
-+
-+ struct ts_filter filter;
-+
-+ int hw_avg_max;
-+ u16 x;
-+ u16 y;
-+ u16 p;
-+
-+ u16 x_plate_ohm;
-+ int stab_time;
-+ int max_pressure;
-+ int touch_pressure;
-+
-+ u8 event_sent;
-+ u8 pen_down;
-+ u8 disabled;
-+ u8 disable_depth;
-+
-+ int hw_flags;
-+ int irq;
-+};
-+
-+
-+static const u16 tsc2301_ts_read_data = 0x8000 | TSC2301_REG_X;
-+
-+static int tsc2301_ts_check_config(struct tsc2301_ts *ts, int *hw_flags)
-+{
-+ int flags;
-+
-+ flags = 0;
-+ switch (ts->hw_avg_max) {
-+ case 0:
-+ flags |= TSC2301_ADCREG_AVERAGING_NONE;
-+ break;
-+ case 4:
-+ flags |= TSC2301_ADCREG_AVERAGING_4AVG;
-+ break;
-+ case 8:
-+ flags |= TSC2301_ADCREG_AVERAGING_8AVG;
-+ break;
-+ case 16:
-+ flags |= TSC2301_ADCREG_AVERAGING_16AVG;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ switch (ts->stab_time) {
-+ case 0:
-+ flags |= TSC2301_ADCREG_VOLTAGE_STAB_0US;
-+ break;
-+ case 100:
-+ flags |= TSC2301_ADCREG_VOLTAGE_STAB_100US;
-+ break;
-+ case 500:
-+ flags |= TSC2301_ADCREG_VOLTAGE_STAB_500US;
-+ break;
-+ case 1000:
-+ flags |= TSC2301_ADCREG_VOLTAGE_STAB_1MS;
-+ break;
-+ case 5000:
-+ flags |= TSC2301_ADCREG_VOLTAGE_STAB_5MS;
-+ break;
-+ case 10000:
-+ flags |= TSC2301_ADCREG_VOLTAGE_STAB_10MS;
-+ break;
-+ case 50000:
-+ flags |= TSC2301_ADCREG_VOLTAGE_STAB_50MS;
-+ break;
-+ case 100000:
-+ flags |= TSC2301_ADCREG_VOLTAGE_STAB_100MS;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ *hw_flags = flags;
-+ return 0;
-+}
-+
-+/*
-+ * This odd three-time initialization is to work around a bug in TSC2301.
-+ * See TSC2301 errata for details.
-+ */
-+static int tsc2301_ts_configure(struct tsc2301 *tsc, int flags)
-+{
-+ struct spi_transfer xfer[5];
-+ struct spi_transfer *x;
-+ struct spi_message m;
-+ int i;
-+ u16 val1, val2, val3;
-+ u16 data[10];
-+
-+ val1 = TSC2301_ADCREG_CONVERSION_CTRL_BY_HOST |
-+ TSC2301_ADCREG_STOP_CONVERSION |
-+ TSC2301_ADCREG_FUNCTION_NONE |
-+ TSC2301_ADCREG_RESOLUTION_12BIT |
-+ TSC2301_ADCREG_AVERAGING_NONE |
-+ TSC2301_ADCREG_CLOCK_2MHZ |
-+ TSC2301_ADCREG_VOLTAGE_STAB_100MS;
-+
-+ val2 = TSC2301_ADCREG_CONVERSION_CTRL_BY_HOST |
-+ TSC2301_ADCREG_FUNCTION_XYZ |
-+ TSC2301_ADCREG_RESOLUTION_12BIT |
-+ TSC2301_ADCREG_AVERAGING_16AVG |
-+ TSC2301_ADCREG_CLOCK_1MHZ |
-+ TSC2301_ADCREG_VOLTAGE_STAB_100MS;
-+
-+ /* Averaging and voltage stabilization settings in flags */
-+ val3 = TSC2301_ADCREG_CONVERSION_CTRL_BY_TSC2301 |
-+ TSC2301_ADCREG_FUNCTION_XYZ |
-+ TSC2301_ADCREG_RESOLUTION_12BIT |
-+ TSC2301_ADCREG_CLOCK_2MHZ |
-+ flags;
-+
-+ /* Now we prepare the command for transferring */
-+ data[0] = TSC2301_REG_ADC;
-+ data[1] = val1;
-+ data[2] = TSC2301_REG_ADC;
-+ data[3] = val2;
-+ data[4] = TSC2301_REG_ADC;
-+ data[5] = val3;
-+ data[6] = TSC2301_REG_REF;
-+ data[7] = 1 << 4 | 1 << 2 | 1; /* intref, 100uS settl, 2.5V ref */
-+ data[8] = TSC2301_REG_CONFIG;
-+ data[9] = 3 << 3 | 2 << 0; /* 340uS pre-chrg, 544us delay */
-+
-+ spi_message_init(&m);
-+ m.spi = tsc->spi;
-+
-+ memset(xfer, 0, sizeof(xfer));
-+ x = &xfer[0];
-+
-+ for (i = 0; i < 10; i += 2) {
-+ x->tx_buf = &data[i];
-+ x->len = 4;
-+ if (i != 8)
-+ x->cs_change = 1;
-+ spi_message_add_tail(x, &m);
-+ x++;
-+ }
-+ spi_sync(m.spi, &m);
-+
-+ return 0;
-+}
-+
-+static void tsc2301_ts_start_scan(struct tsc2301 *tsc)
-+{
-+ tsc2301_ts_configure(tsc, tsc->ts->hw_flags);
-+ tsc2301_kp_restart(tsc);
-+}
-+
-+static void tsc2301_ts_stop_scan(struct tsc2301 *tsc)
-+{
-+ tsc2301_write_reg(tsc, TSC2301_REG_ADC, TSC2301_ADCREG_STOP_CONVERSION);
-+ tsc2301_kp_restart(tsc);
-+}
-+
-+static void update_pen_state(struct tsc2301_ts *ts, int x, int y, int pressure)
-+{
-+ if (pressure) {
-+ input_report_abs(ts->idev, ABS_X, x);
-+ input_report_abs(ts->idev, ABS_Y, y);
-+ input_report_abs(ts->idev, ABS_PRESSURE, pressure);
-+ if (!ts->pen_down)
-+ input_report_key(ts->idev, BTN_TOUCH, 1);
-+ ts->pen_down = 1;
-+ } else {
-+ input_report_abs(ts->idev, ABS_PRESSURE, 0);
-+ if (ts->pen_down)
-+ input_report_key(ts->idev, BTN_TOUCH, 0);
-+ ts->pen_down = 0;
-+ }
-+
-+ input_sync(ts->idev);
-+
-+#ifdef VERBOSE
-+ dev_dbg(&tsc->spi->dev, "x %4d y %4d p %4d\n", x, y, pressure);
-+#endif
-+}
-+
-+static int filter(struct tsc2301_ts *ts, int x, int y, int z1, int z2)
-+{
-+ int inside_rect, pressure_limit, Rt;
-+ struct ts_filter *tsf = &ts->filter;
-+
-+ /* validate pressure and position */
-+ if (x > MAX_12BIT || y > MAX_12BIT)
-+ return 0;
-+
-+ /* skip coords if the pressure-components are out of range */
-+ if (z1 < TSF_MIN_Z1 || z2 > TSF_MAX_Z2)
-+ return 0;
-+
-+ /* Use the x,y,z1,z2 directly on the first "pen down" event */
-+ if (ts->event_sent) {
-+ tsf->avg_x += x;
-+ tsf->avg_y += y;
-+ tsf->avg_z1 += z1;
-+ tsf->avg_z2 += z2;
-+
-+ if (++tsf->sample_cnt < TSF_SAMPLES)
-+ return 0;
-+ x = tsf->avg_x / TSF_SAMPLES;
-+ y = tsf->avg_y / TSF_SAMPLES;
-+ z1 = tsf->avg_z1 / TSF_SAMPLES;
-+ z2 = tsf->avg_z2 / TSF_SAMPLES;
-+ }
-+ tsf->sample_cnt = 0;
-+ tsf->avg_x = 0;
-+ tsf->avg_y = 0;
-+ tsf->avg_z1 = 0;
-+ tsf->avg_z2 = 0;
-+
-+ pressure_limit = ts->event_sent? ts->max_pressure: ts->touch_pressure;
-+
-+ /* z1 is always at least 100: */
-+ Rt = x * (z2 - z1) / z1;
-+ Rt = Rt * ts->x_plate_ohm / 4096;
-+ if (Rt > pressure_limit)
-+ return 0;
-+
-+ /* discard the event if it still is within the previous rect - unless
-+ * if the pressure is harder, but then use previous x,y position */
-+ inside_rect = (
-+ x > (int)ts->x - TS_RECT_SIZE && x < (int)ts->x + TS_RECT_SIZE &&
-+ y > (int)ts->y - TS_RECT_SIZE && y < (int)ts->y + TS_RECT_SIZE);
-+
-+ if (!ts->event_sent || !inside_rect) {
-+ ts->x = x;
-+ ts->y = y;
-+ ts->p = Rt;
-+ return 1;
-+ } else if (Rt < ts->p) {
-+ ts->p = Rt;
-+ return 1;
-+ }
-+ return 0;
-+}
-+
-+/*
-+ * This procedure is called by the SPI framework after the coordinates
-+ * have been read from TSC2301
-+ */
-+static void tsc2301_ts_rx(void *arg)
-+{
-+ struct tsc2301 *tsc = arg;
-+ struct tsc2301_ts *ts = tsc->ts;
-+ int send_event;
-+ int x, y, z1, z2;
-+
-+ x = ts->coords->x;
-+ y = ts->coords->y;
-+ z1 = ts->coords->z1;
-+ z2 = ts->coords->z2;
-+
-+ send_event = filter(ts, x, y, z1, z2);
-+ if (send_event) {
-+ update_pen_state(ts, ts->x, ts->y, ts->p);
-+ ts->event_sent = 1;
-+ }
-+
-+ mod_timer(&ts->penup_timer,
-+ jiffies + msecs_to_jiffies(TSC2301_TS_PENUP_TIME));
-+}
-+
-+/*
-+ * Timer is called TSC2301_TS_PENUP_TIME after pen is up
-+ */
-+static void tsc2301_ts_timer_handler(unsigned long data)
-+{
-+ struct tsc2301 *tsc = (struct tsc2301 *)data;
-+ struct tsc2301_ts *ts = tsc->ts;
-+
-+ if (ts->event_sent) {
-+ ts->event_sent = 0;
-+ update_pen_state(ts, 0, 0, 0);
-+ }
-+}
-+
-+/*
-+ * This interrupt is called when pen is down and coordinates are
-+ * available. That is indicated by a falling edge on DEV line.
-+ */
-+static irqreturn_t tsc2301_ts_irq_handler(int irq, void *dev_id)
-+{
-+ struct tsc2301 *tsc = dev_id;
-+ struct tsc2301_ts *ts = tsc->ts;
-+ int r;
-+
-+ r = spi_async(tsc->spi, &ts->read_msg);
-+ if (r)
-+ dev_err(&tsc->spi->dev, "ts: spi_async() failed");
-+
-+ mod_timer(&ts->penup_timer,
-+ jiffies + msecs_to_jiffies(TSC2301_TS_PENUP_TIME));
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static void tsc2301_ts_disable(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_ts *ts = tsc->ts;
-+
-+ if (ts->disable_depth++ != 0)
-+ return;
-+
-+ disable_irq(ts->irq);
-+
-+ /* wait until penup timer expire normally */
-+ do {
-+ msleep(1);
-+ } while (ts->event_sent);
-+
-+ tsc2301_ts_stop_scan(tsc);
-+}
-+
-+static void tsc2301_ts_enable(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_ts *ts = tsc->ts;
-+
-+ if (--ts->disable_depth != 0)
-+ return;
-+
-+ enable_irq(ts->irq);
-+
-+ tsc2301_ts_start_scan(tsc);
-+}
-+
-+#ifdef CONFIG_PM
-+int tsc2301_ts_suspend(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_ts *ts = tsc->ts;
-+
-+ mutex_lock(&ts->mutex);
-+ tsc2301_ts_disable(tsc);
-+ mutex_unlock(&ts->mutex);
-+
-+ return 0;
-+}
-+
-+void tsc2301_ts_resume(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_ts *ts = tsc->ts;
-+
-+ mutex_lock(&ts->mutex);
-+ tsc2301_ts_enable(tsc);
-+ mutex_unlock(&ts->mutex);
-+}
-+#endif
-+
-+static void tsc2301_ts_setup_spi_xfer(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_ts *ts = tsc->ts;
-+ struct spi_message *m = &ts->read_msg;
-+ struct spi_transfer *x = &ts->read_xfer[0];
-+
-+ spi_message_init(m);
-+
-+ x->tx_buf = &tsc2301_ts_read_data;
-+ x->len = 2;
-+ spi_message_add_tail(x, m);
-+
-+ x++;
-+ x->rx_buf = ts->coords;
-+ x->len = 8;
-+ spi_message_add_tail(x, m);
-+
-+ m->complete = tsc2301_ts_rx;
-+ m->context = tsc;
-+}
-+
-+static ssize_t tsc2301_ts_pen_down_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct tsc2301 *tsc = dev_get_drvdata(dev);
-+
-+ return sprintf(buf, "%u\n", tsc->ts->pen_down);
-+}
-+
-+static DEVICE_ATTR(pen_down, S_IRUGO, tsc2301_ts_pen_down_show, NULL);
-+
-+static ssize_t tsc2301_ts_disable_show(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct tsc2301 *tsc = dev_get_drvdata(dev);
-+ struct tsc2301_ts *ts = tsc->ts;
-+
-+ return sprintf(buf, "%u\n", ts->disabled);
-+}
-+
-+static ssize_t tsc2301_ts_disable_store(struct device *dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct tsc2301 *tsc = dev_get_drvdata(dev);
-+ struct tsc2301_ts *ts = tsc->ts;
-+ char *endp;
-+ int i;
-+
-+ i = simple_strtoul(buf, &endp, 10);
-+ i = i ? 1 : 0;
-+ mutex_lock(&ts->mutex);
-+ if (i == ts->disabled) goto out;
-+ ts->disabled = i;
-+
-+ if (i)
-+ tsc2301_ts_disable(tsc);
-+ else
-+ tsc2301_ts_enable(tsc);
-+out:
-+ mutex_unlock(&ts->mutex);
-+ return count;
-+}
-+
-+static DEVICE_ATTR(disable_ts, 0664, tsc2301_ts_disable_show,
-+ tsc2301_ts_disable_store);
-+
-+int __devinit tsc2301_ts_init(struct tsc2301 *tsc,
-+ struct tsc2301_platform_data *pdata)
-+{
-+ struct tsc2301_ts *ts;
-+ struct input_dev *idev;
-+ int r;
-+ int x_max, y_max;
-+ int x_fudge, y_fudge, p_fudge;
-+
-+ if (pdata->dav_int <= 0) {
-+ dev_err(&tsc->spi->dev, "need DAV IRQ");
-+ return -EINVAL;
-+ }
-+
-+ ts = kzalloc(sizeof(*ts), GFP_KERNEL);
-+ if (ts == NULL)
-+ return -ENOMEM;
-+ tsc->ts = ts;
-+
-+ ts->coords = kzalloc(sizeof(*ts->coords), GFP_KERNEL);
-+ if (ts->coords == NULL) {
-+ kfree(ts);
-+ return -ENOMEM;
-+ }
-+
-+ ts->irq = pdata->dav_int;
-+
-+ init_timer(&ts->penup_timer);
-+ setup_timer(&ts->penup_timer, tsc2301_ts_timer_handler,
-+ (unsigned long)tsc);
-+
-+ mutex_init(&ts->mutex);
-+
-+ ts->x_plate_ohm = pdata->ts_x_plate_ohm ? : 280;
-+ ts->hw_avg_max = pdata->ts_hw_avg;
-+ ts->max_pressure = pdata->ts_max_pressure ? : MAX_12BIT;
-+ ts->touch_pressure = pdata->ts_touch_pressure ? : ts->max_pressure;
-+ ts->stab_time = pdata->ts_stab_time;
-+
-+ x_max = pdata->ts_x_max ? : 4096;
-+ y_max = pdata->ts_y_max ? : 4096;
-+ x_fudge = pdata->ts_x_fudge ? : 4;
-+ y_fudge = pdata->ts_y_fudge ? : 8;
-+ p_fudge = pdata->ts_pressure_fudge ? : 2;
-+
-+ if ((r = tsc2301_ts_check_config(ts, &ts->hw_flags))) {
-+ dev_err(&tsc->spi->dev, "invalid configuration\n");
-+ goto err2;
-+ }
-+
-+ idev = input_allocate_device();
-+ if (idev == NULL) {
-+ r = -ENOMEM;
-+ goto err2;
-+ }
-+ idev->name = "TSC2301 touchscreen";
-+ snprintf(ts->phys, sizeof(ts->phys),
-+ "%s/input-ts", dev_name(&tsc->spi->dev));
-+ idev->phys = ts->phys;
-+ idev->dev.parent = &tsc->spi->dev;
-+
-+ idev->evbit[0] = BIT(EV_ABS) | BIT(EV_KEY);
-+ idev->absbit[0] = BIT(ABS_X) | BIT(ABS_Y) | BIT(ABS_PRESSURE);
-+ ts->idev = idev;
-+
-+ tsc2301_ts_setup_spi_xfer(tsc);
-+
-+ /* These parameters should perhaps be configurable? */
-+ input_set_abs_params(idev, ABS_X, 0, x_max, x_fudge, 0);
-+ input_set_abs_params(idev, ABS_Y, 0, y_max, y_fudge, 0);
-+ input_set_abs_params(idev, ABS_PRESSURE, 0, ts->max_pressure,
-+ p_fudge, 0);
-+
-+ tsc2301_ts_start_scan(tsc);
-+
-+ r = request_irq(ts->irq, tsc2301_ts_irq_handler,
-+ IRQF_TRIGGER_FALLING,
-+ "tsc2301-ts", tsc);
-+ if (r < 0) {
-+ dev_err(&tsc->spi->dev, "unable to get DAV IRQ");
-+ goto err3;
-+ }
-+ irq_set_irq_wake(ts->irq, 1);
-+
-+ if (device_create_file(&tsc->spi->dev, &dev_attr_pen_down) < 0)
-+ goto err4;
-+ if (device_create_file(&tsc->spi->dev, &dev_attr_disable_ts) < 0)
-+ goto err5;
-+
-+ r = input_register_device(idev);
-+ if (r < 0) {
-+ dev_err(&tsc->spi->dev, "can't register touchscreen device\n");
-+ goto err6;
-+ }
-+
-+ return 0;
-+err6:
-+ device_remove_file(&tsc->spi->dev, &dev_attr_disable_ts);
-+err5:
-+ device_remove_file(&tsc->spi->dev, &dev_attr_pen_down);
-+err4:
-+ free_irq(ts->irq, tsc);
-+err3:
-+ tsc2301_ts_stop_scan(tsc);
-+ input_free_device(idev);
-+err2:
-+ kfree(ts->coords);
-+ kfree(ts);
-+ return r;
-+}
-+
-+void __devexit tsc2301_ts_exit(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_ts *ts = tsc->ts;
-+
-+ tsc2301_ts_disable(tsc);
-+
-+ device_remove_file(&tsc->spi->dev, &dev_attr_disable_ts);
-+ device_remove_file(&tsc->spi->dev, &dev_attr_pen_down);
-+
-+ free_irq(ts->irq, tsc);
-+ input_unregister_device(ts->idev);
-+
-+ kfree(ts->coords);
-+ kfree(ts);
-+}
-+MODULE_AUTHOR("Jarkko Oikarinen <jarkko.oikarinen@nokia.com>");
-+MODULE_LICENSE("GPL");
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -433,6 +433,28 @@ config SPI_TLE62X0
- sysfs interface, with each line presented as a kind of GPIO
- exposing both switch control and diagnostic feedback.
-
-+config SPI_TSC2301
-+ tristate "TSC2301 driver"
-+ depends on SPI_MASTER
-+ help
-+ Say Y here if you have a TSC2301 chip connected to an SPI
-+ bus on your board.
-+
-+ The TSC2301 is a highly integrated PDA analog interface circuit.
-+ It contains a complete 12-bit A/D resistive touch screen
-+ converter (ADC) including drivers, touch pressure measurement
-+ capability, keypad controller, and 8-bit D/A converter (DAC) output
-+ for LCD contrast control.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called tsc2301.
-+
-+config SPI_TSC2301_AUDIO
-+ boolean "TSC2301 audio support"
-+ depends on SPI_TSC2301 && SND
-+ help
-+ Say Y here for if you are using the audio features of TSC2301.
-+
- #
- # Add new SPI protocol masters in alphabetical order above this line
- #
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -59,4 +59,6 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x
- obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
- obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
- obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
--
-+obj-$(CONFIG_SPI_TSC2301) += tsc2301.o
-+tsc2301-objs := tsc2301-core.o
-+tsc2301-$(CONFIG_SPI_TSC2301_AUDIO) += tsc2301-mixer.o
---- /dev/null
-+++ b/drivers/spi/tsc2301-core.c
-@@ -0,0 +1,297 @@
-+/*
-+ * TSC2301 driver
-+ *
-+ * Copyright (C) 2005, 2006 Nokia Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ *
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/delay.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/tsc2301.h>
-+
-+u16 tsc2301_read_reg(struct tsc2301 *tsc, int reg)
-+{
-+ struct spi_transfer t[2];
-+ struct spi_message m;
-+ u16 data = 0, cmd;
-+
-+ cmd = reg;
-+ cmd |= 0x8000;
-+
-+ memset(t, 0, sizeof(t));
-+ spi_message_init(&m);
-+ m.spi = tsc->spi;
-+
-+ t[0].tx_buf = &cmd;
-+ t[0].rx_buf = NULL;
-+ t[0].len = 2;
-+ spi_message_add_tail(&t[0], &m);
-+
-+ t[1].tx_buf = NULL;
-+ t[1].rx_buf = &data;
-+ t[1].len = 2;
-+ spi_message_add_tail(&t[1], &m);
-+
-+ spi_sync(m.spi, &m);
-+
-+ return data;
-+}
-+
-+void tsc2301_write_reg(struct tsc2301 *tsc, int reg, u16 val)
-+{
-+ struct spi_transfer t;
-+ struct spi_message m;
-+ u16 data[2];
-+
-+ /* Now we prepare the command for transferring */
-+ data[0] = reg;
-+ data[1] = val;
-+
-+ spi_message_init(&m);
-+ m.spi = tsc->spi;
-+
-+ memset(&t, 0, sizeof(t));
-+ t.tx_buf = data;
-+ t.rx_buf = NULL;
-+ t.len = 4;
-+ spi_message_add_tail(&t, &m);
-+
-+ spi_sync(m.spi, &m);
-+}
-+
-+void tsc2301_write_kbc(struct tsc2301 *tsc, int val)
-+{
-+ u16 w;
-+
-+ w = tsc->config2_shadow;
-+ w &= ~(0x03 << 14);
-+ w |= (val & 0x03) << 14;
-+ tsc2301_write_reg(tsc, TSC2301_REG_CONFIG2, w);
-+ tsc->config2_shadow = w;
-+}
-+
-+void tsc2301_write_pll(struct tsc2301 *tsc,
-+ int pll_n, int pll_a, int pll_pdc, int pct_e, int pll_o)
-+{
-+ u16 w;
-+
-+ w = tsc->config2_shadow;
-+ w &= ~0x3fff;
-+ w |= (pll_n & 0x0f) | ((pll_a & 0x0f) << 4) | ((pll_pdc & 0x0f) << 8);
-+ w |= pct_e ? (1 << 12) : 0;
-+ w |= pll_o ? (1 << 13) : 0;
-+ tsc2301_write_reg(tsc, TSC2301_REG_CONFIG2, w);
-+ tsc->config2_shadow = w;
-+}
-+
-+void tsc2301_read_buf(struct tsc2301 *tsc, int reg, u16 *rx_buf, int len)
-+{
-+ struct spi_transfer t[2];
-+ struct spi_message m;
-+ u16 cmd, i;
-+
-+ cmd = reg;
-+ cmd |= 0x8000;
-+
-+ spi_message_init(&m);
-+ m.spi = tsc->spi;
-+
-+ memset(t, 0, sizeof(t));
-+ t[0].tx_buf = &cmd;
-+ t[0].rx_buf = NULL;
-+ t[0].len = 2;
-+ spi_message_add_tail(&t[0], &m);
-+
-+ t[1].tx_buf = NULL;
-+ t[1].rx_buf = rx_buf;
-+ t[1].len = 2 * len;
-+ spi_message_add_tail(&t[1], &m);
-+
-+ spi_sync(m.spi, &m);
-+
-+ for (i = 0; i < len; i++)
-+ printk(KERN_DEBUG "rx_buf[%d]: %04x\n", i, rx_buf[i]);
-+}
-+
-+static int __devinit tsc2301_probe(struct spi_device *spi)
-+{
-+ struct tsc2301 *tsc;
-+ struct tsc2301_platform_data *pdata = spi->dev.platform_data;
-+ int r;
-+ u16 w;
-+
-+ if (!pdata) {
-+ dev_dbg(&spi->dev, "no platform data?\n");
-+ return -ENODEV;
-+ }
-+
-+ tsc = kzalloc(sizeof(*tsc), GFP_KERNEL);
-+ if (tsc == NULL)
-+ return -ENOMEM;
-+
-+ dev_set_drvdata(&spi->dev, tsc);
-+ tsc->spi = spi;
-+
-+ tsc->enable_clock = pdata->enable_clock;
-+ tsc->disable_clock = pdata->disable_clock;
-+
-+ if (pdata->reset_gpio >= 0) {
-+ tsc->reset_gpio = pdata->reset_gpio;
-+ r = gpio_request(tsc->reset_gpio, "TSC2301 reset");
-+ if (r < 0)
-+ goto err1;
-+ gpio_direction_output(tsc->reset_gpio, 1);
-+ mdelay(1);
-+ gpio_set_value(tsc->reset_gpio, 0);
-+ } else
-+ tsc->reset_gpio = -1;
-+
-+ spi->mode = SPI_MODE_1;
-+ spi->bits_per_word = 16;
-+ /* The max speed might've been defined by the board-specific
-+ * struct */
-+ if (!spi->max_speed_hz)
-+ spi->max_speed_hz = TSC2301_HZ;
-+ spi_setup(spi);
-+
-+ /* Soft reset */
-+ tsc2301_write_reg(tsc, TSC2301_REG_RESET, 0xbb00);
-+ msleep(1);
-+
-+ w = tsc2301_read_reg(tsc, TSC2301_REG_ADC);
-+ if (!(w & (1 << 14))) {
-+ dev_err(&spi->dev, "invalid ADC reg value: %04x\n", w);
-+ r = -ENODEV;
-+ goto err1;
-+ }
-+
-+ w = tsc2301_read_reg(tsc, TSC2301_REG_DAC);
-+ if (!(w & (1 << 15))) {
-+ dev_err(&spi->dev, "invalid DAC reg value: %04x\n", w);
-+ r = -ENODEV;
-+ goto err1;
-+ }
-+
-+ /* Stop keypad scanning */
-+ tsc2301_write_reg(tsc, TSC2301_REG_KEY, 0x4000);
-+
-+ /* We have to cache this for read-modify-write, since we can't
-+ * read back BIT15 */
-+ w = tsc2301_read_reg(tsc, TSC2301_REG_CONFIG2);
-+ /* By default BIT15 is set */
-+ w |= 1 << 15;
-+ tsc->config2_shadow = w;
-+
-+ r = tsc2301_kp_init(tsc, pdata);
-+ if (r)
-+ goto err1;
-+ r = tsc2301_ts_init(tsc, pdata);
-+ if (r)
-+ goto err2;
-+ r = tsc2301_mixer_init(tsc, pdata);
-+ if (r)
-+ goto err3;
-+ return 0;
-+
-+err3:
-+ tsc2301_ts_exit(tsc);
-+err2:
-+ tsc2301_kp_exit(tsc);
-+err1:
-+ kfree(tsc);
-+ return r;
-+}
-+
-+static int __devexit tsc2301_remove(struct spi_device *spi)
-+{
-+ struct tsc2301 *tsc = dev_get_drvdata(&spi->dev);
-+
-+ tsc2301_mixer_exit(tsc);
-+ tsc2301_ts_exit(tsc);
-+ tsc2301_kp_exit(tsc);
-+ if (tsc->reset_gpio >= 0)
-+ gpio_free(tsc->reset_gpio);
-+ kfree(tsc);
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_PM
-+static int tsc2301_suspend(struct spi_device *spi, pm_message_t mesg)
-+{
-+ struct tsc2301 *tsc = dev_get_drvdata(&spi->dev);
-+ int r;
-+
-+ if ((r = tsc2301_mixer_suspend(tsc)) < 0)
-+ return r;
-+ if ((r = tsc2301_kp_suspend(tsc)) < 0)
-+ goto err1;
-+ if ((r = tsc2301_ts_suspend(tsc)) < 0)
-+ goto err2;
-+
-+ return 0;
-+err2:
-+ tsc2301_kp_resume(tsc);
-+err1:
-+ tsc2301_mixer_resume(tsc);
-+ return r;
-+}
-+
-+static int tsc2301_resume(struct spi_device *spi)
-+{
-+ struct tsc2301 *tsc = dev_get_drvdata(&spi->dev);
-+
-+ tsc2301_ts_resume(tsc);
-+ tsc2301_kp_resume(tsc);
-+ tsc2301_mixer_resume(tsc);
-+ return 0;
-+}
-+#endif
-+
-+static struct spi_driver tsc2301_driver = {
-+ .driver = {
-+ .name = "tsc2301",
-+ .bus = &spi_bus_type,
-+ .owner = THIS_MODULE,
-+ },
-+#ifdef CONFIG_PM
-+ .suspend = tsc2301_suspend,
-+ .resume = tsc2301_resume,
-+#endif
-+ .probe = tsc2301_probe,
-+ .remove = __devexit_p(tsc2301_remove),
-+};
-+
-+static int __init tsc2301_init(void)
-+{
-+ printk("TSC2301 driver initializing\n");
-+
-+ return spi_register_driver(&tsc2301_driver);
-+}
-+module_init(tsc2301_init);
-+
-+static void __exit tsc2301_exit(void)
-+{
-+ spi_unregister_driver(&tsc2301_driver);
-+}
-+module_exit(tsc2301_exit);
-+
-+MODULE_AUTHOR("Juha Yrjölä <juha.yrjola@nokia.com>");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/spi/tsc2301-mixer.c
-@@ -0,0 +1,1003 @@
-+/*
-+ * ALSA Mixer implementation for TSC2301
-+ *
-+ * Copyright (C) 2006 Nokia Corporation.
-+ *
-+ * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
-+ * Juha Yrjola
-+ *
-+ * Some notes about TSC2301:
-+ * - PLL will stop when DAC and ADC's are powered down.
-+ * - Touchscreen will stop working when audio part is powered up and if audio
-+ * MCLK is stopped. Problem is avoided if audio is powered down before
-+ * stopping MCLK.
-+ * - Audio DAC or audio outputs will activate only after 100 msec from the
-+ * chip power-up. Reason seems to be VCM since there is no this delay if the
-+ * chip and VCM (bit AVPD on PD/MISC) were not powered down. The chip will
-+ * consume about 1 mA if all other audio blocks are powered down except the
-+ * chip itself and VCM. Full power down consumes only about few uA.
-+ * - Power-down transition could happen earliest about 100 msec after the chip
-+ * power-up. Otherwise power-down will fail if there is no that 100 msec
-+ * on time before it. It's not obvious why is that since chip reports
-+ * power-up to be completed and also PLL output on GPIO_0 is active in few
-+ * milliseconds.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
-+ * 02110-1301 USA
-+ *
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/errno.h>
-+#include <linux/delay.h>
-+#include <linux/slab.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/tsc2301.h>
-+
-+#include <sound/core.h>
-+#include <sound/control.h>
-+
-+/* shadow register indexes */
-+enum {
-+ /* audio control and volume registers */
-+ AUDCNTL_INDEX,
-+ ADCVOL_INDEX,
-+ DACVOL_INDEX,
-+ BPVOL_INDEX,
-+ /* keyclick control register (not needed here) */
-+ /* audio power control register */
-+ PD_MISC_INDEX,
-+ /* TSC2301 GPIO control register */
-+ GPIO_INDEX,
-+
-+ SHADOW_REG_COUNT,
-+};
-+
-+/* structure for driver private data */
-+struct tsc2301_mixer {
-+ struct tsc2301 *tsc;
-+ struct mutex mutex;
-+
-+ /* shadow registers holding TSC2301 audio registers. Used to hold
-+ * their states during the sleep and also to reduce communication with
-+ * the chip since get callback functions could get register values
-+ * directly from these shadow registers without needing to read them
-+ * from the chip */
-+ u16 shadow_regs[SHADOW_REG_COUNT];
-+
-+ /* audio controller driver usage of the ADC and DAC */
-+ unsigned adc_enabled:1, dac_enabled:1;
-+ unsigned pll_output:1;
-+ unsigned mclk_enabled;
-+
-+ /* latest audio power-up timestamp */
-+ unsigned long pu_jiffies;
-+
-+ /* these are used when upper layer(s) are going to power-down TSC2301
-+ * before 100 msec is passed from power-up */
-+ struct delayed_work delayed_power_down;
-+ unsigned delayed_pd_active:1;
-+
-+ int (* platform_init)(struct device *);
-+ void (* platform_cleanup)(struct device *);
-+
-+ struct tsc2301_mixer_gpio *mixer_gpios;
-+ int n_mixer_gpios;
-+};
-+
-+#define TSC2301_DAC_DELAY msecs_to_jiffies(100)
-+#define TSC2301_MIN_PU_PERIOD msecs_to_jiffies(100)
-+
-+#define TSC2301_REG_TO_PVAL(reg) \
-+ (TSC2301_REG_TO_PAGE(reg) << 6 | TSC2301_REG_TO_ADDR(reg))
-+#define TSC2301_PVAL_TO_REG(v) \
-+ (TSC2301_REG((((v) >> 6) & 3),((v) & 0x1f)))
-+
-+#define TSC2301_VOLUME_MASK 0x7f
-+#define TSC2301_MIN_ADCVOL 6
-+#define TSC2301_MIN_DACVOL 0
-+#define TSC2301_MIN_BPVOL 31
-+#define TSC2301_MUTE_LEFT_SHIFT 15
-+#define TSC2301_VOL_LEFT_SHIFT 8
-+#define TSC2301_MUTE_RIGHT_SHIFT 7
-+#define TSC2301_VOL_RIGHT_SHIFT 0
-+
-+#define TSC2301_INM_MASK 3
-+#define TSC2301_INML_SHIFT 12
-+#define TSC2301_INMR_SHIFT 10
-+
-+#define TSC2301_MICG_MASK 3
-+#define TSC2301_MICG_MIN 1 /* values 0 & 1 both mean 0 dB */
-+#define TSC2301_MICG_SHIFT 8
-+
-+#define TSC2301_REG_AUDCNTL_MCLK(v) (((v) & 3) << 6)
-+#define TSC2301_REG_AUDCNTL_I2SFS(v) (((v) & 0xf) << 2)
-+#define TSC2301_REG_AUDCNTL_I2SFM(v) (((v) & 3) << 0)
-+
-+#define TSC2301_SINGLE(xname, xindex, reg, shadow_index, shift, mask, min) \
-+{\
-+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
-+ .name = xname, \
-+ .index = xindex, \
-+ .info = snd_tsc2301_info_single, \
-+ .get = snd_tsc2301_get_single, \
-+ .put = snd_tsc2301_put_single, \
-+ .private_value = TSC2301_REG_TO_PVAL(reg) | \
-+ (shadow_index << 8) | (shift << 16) | (mask << 24) | \
-+ (min << 28) \
-+}
-+#define TSC2301_SINGLE_MINVAL(v) (((v) >> 28) & 15)
-+#define TSC2301_SINGLE_SHIFT(v) (((v) >> 16) & 15)
-+#define TSC2301_SINGLE_MASK(v) (((v) >> 24) & 15)
-+
-+#define TSC2301_DOUBLE(xname, xindex, reg, shadow_index, ls, rs, mask, min) \
-+{\
-+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
-+ .name = xname, \
-+ .index = xindex, \
-+ .info = snd_tsc2301_info_double, \
-+ .get = snd_tsc2301_get_double, \
-+ .put = snd_tsc2301_put_double, \
-+ .private_value = TSC2301_REG_TO_PVAL(reg) | \
-+ (shadow_index << 8) | (min << 11) | \
-+ (ls << 16) | (rs << 20) | (mask << 24) \
-+}
-+#define TSC2301_DOUBLE_MINVAL(v) (((v) >> 11) & 0x1f)
-+#define TSC2301_DOUBLE_LEFT_SHIFT(v) (((v) >> 16) & 15)
-+#define TSC2301_DOUBLE_RIGHT_SHIFT(v) (((v) >> 20) & 15)
-+#define TSC2301_DOUBLE_MASK(v) (((v) >> 24) & TSC2301_VOLUME_MASK)
-+
-+#define TSC2301_MUX(xname, xindex, reg, shadow_index, ls, rs, mask) \
-+{\
-+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
-+ .name = xname, \
-+ .index = xindex, \
-+ .info = snd_tsc2301_info_mux, \
-+ .get = snd_tsc2301_get_mux, \
-+ .put = snd_tsc2301_put_mux, \
-+ .private_value = TSC2301_REG_TO_PVAL(reg) | \
-+ (shadow_index << 8) | (ls << 16) | (rs << 20) | (mask << 24) \
-+}
-+#define TSC2301_MUX_LEFT_SHIFT(v) (((v) >> 16) & 15)
-+#define TSC2301_MUX_RIGHT_SHIFT(v) (((v) >> 20) & 15)
-+#define TSC2301_MUX_MASK(v) (((v) >> 24) & TSC2301_VOLUME_MASK)
-+
-+#define TSC2301_BOOL(xname, xindex, reg, shadow_index, shift, invert, state) \
-+{ \
-+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
-+ .name = xname, \
-+ .index = xindex, \
-+ .info = snd_tsc2301_info_bool, \
-+ .get = snd_tsc2301_get_bool, \
-+ .put = snd_tsc2301_put_bool, \
-+ .private_value = TSC2301_REG_TO_PVAL(reg) | \
-+ (shadow_index << 8) | (shift << 16) | \
-+ (invert << 24) | (state << 25) \
-+}
-+#define TSC2301_BOOL_SHIFT(v) (((v) >> 16) & 7)
-+#define TSC2301_BOOL_INVERT(v) (((v) >> 24) & 1)
-+#define TSC2301_BOOL_STATE(v) (((v) >> 25) & 1)
-+
-+#define TSC2301_SHADOW_INDEX(v) (((v) >> 8) & 7)
-+
-+/*
-+ * Power-down handler for additional GPIO mixer controls. GPIO state of GPIO
-+ * controls whose power-down flag is enabled are set to their false/deactivate
-+ * state
-+ *
-+ * Must be called tsc->mixer->mutex locked
-+ */
-+static void tsc2301_gpio_power_down(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_mixer *mix = tsc->mixer;
-+ u16 temp;
-+ int i;
-+
-+ temp = mix->shadow_regs[GPIO_INDEX];
-+ for (i = 0; i < mix->n_mixer_gpios; i++) {
-+ const struct tsc2301_mixer_gpio *mg;
-+
-+ mg = mix->mixer_gpios + i;
-+ if (mg->deactivate_on_pd) {
-+ int gpio = mg->gpio;
-+
-+ temp &= ~(1 << gpio);
-+ temp |= mg->inverted << gpio;
-+ }
-+ }
-+ tsc2301_write_reg(tsc, TSC2301_REG_GPIO, temp);
-+}
-+
-+/*
-+ * Powers down/up audio blocks which are muted or become unused.
-+ * shadow_index >= 0, changes power state of single audio block
-+ * shadow_index < 0, changes power state of all blocks
-+ *
-+ * Must be called tsc->mixer->mutex locked
-+ */
-+#define TSC2301_MUTE_MASK \
-+ ((1 << TSC2301_MUTE_LEFT_SHIFT) | (1 << TSC2301_MUTE_RIGHT_SHIFT))
-+static void tsc2301_power_ctrl(struct tsc2301 *tsc, int shadow_index,
-+ int poll_pdsts)
-+{
-+ struct tsc2301_mixer *mix = tsc->mixer;
-+ u16 pd_ctrl, pd_ctrl_old, w;
-+ unsigned long timeout;
-+ int power_up = 0;
-+
-+ if (mix->delayed_pd_active) {
-+ mix->delayed_pd_active = 0;
-+ mix->mclk_enabled--;
-+ cancel_delayed_work(&mix->delayed_power_down);
-+ }
-+
-+ pd_ctrl = pd_ctrl_old = mix->shadow_regs[PD_MISC_INDEX];
-+ /* power control helper based on used space mixer selections. See
-+ * actual power control decisions below */
-+ if (shadow_index < 0 || shadow_index == ADCVOL_INDEX) {
-+ /* ADC left and right power down control */
-+ if (mix->shadow_regs[ADCVOL_INDEX] &
-+ (1 << TSC2301_MUTE_LEFT_SHIFT))
-+ /* left ADC muted. Power down the left ADC */
-+ pd_ctrl |= TSC2301_REG_PD_MISC_ADPDL;
-+ else
-+ pd_ctrl &= ~TSC2301_REG_PD_MISC_ADPDL;
-+ if (mix->shadow_regs[ADCVOL_INDEX] &
-+ (1 << TSC2301_MUTE_LEFT_SHIFT))
-+ /* right ADC muted. Power down the right ADC */
-+ pd_ctrl |= TSC2301_REG_PD_MISC_ADPDR;
-+ else
-+ pd_ctrl &= ~TSC2301_REG_PD_MISC_ADPDR;
-+ }
-+ if (shadow_index < 0 || shadow_index == DACVOL_INDEX) {
-+ /* DAC power down control */
-+ if ((mix->shadow_regs[DACVOL_INDEX] &
-+ TSC2301_MUTE_MASK) == TSC2301_MUTE_MASK)
-+ /* both DACs muted. Power down the DAC */
-+ pd_ctrl |= TSC2301_REG_PD_MISC_DAPD;
-+ else
-+ pd_ctrl &= ~TSC2301_REG_PD_MISC_DAPD;
-+ }
-+ if (shadow_index < 0 || shadow_index == BPVOL_INDEX) {
-+ /* line bypass power down control */
-+ if ((mix->shadow_regs[BPVOL_INDEX] &
-+ TSC2301_MUTE_MASK) == TSC2301_MUTE_MASK)
-+ /* both line bypasses muted. Power down the bypass
-+ * path */
-+ pd_ctrl |= TSC2301_REG_PD_MISC_ABPD;
-+ else
-+ pd_ctrl &= ~TSC2301_REG_PD_MISC_ABPD;
-+ }
-+ if (shadow_index < 0 || shadow_index == AUDCNTL_INDEX) {
-+ /* mic bias power down control */
-+ if ((mix->shadow_regs[AUDCNTL_INDEX] &
-+ (3 << TSC2301_INML_SHIFT)) &&
-+ (mix->shadow_regs[AUDCNTL_INDEX] &
-+ (3 << TSC2301_INMR_SHIFT)))
-+ /* both ADC channels use other than mic input. Power
-+ * down the mic bias output */
-+ pd_ctrl |= TSC2301_REG_PD_MISC_MIBPD;
-+ else
-+ pd_ctrl &= ~TSC2301_REG_PD_MISC_MIBPD;
-+ }
-+
-+ /* power control decisions based on codec usage and user space mixer
-+ * selections detected above */
-+ pd_ctrl &= ~TSC2301_REG_PD_MISC_APD; /* audio not powered down */
-+ if (mix->mclk_enabled) {
-+ if (!mix->adc_enabled) {
-+ /* ADC not used, power down both ADC's and mic bias
-+ * output independently of user space mixer
-+ * selections */
-+ pd_ctrl |= TSC2301_REG_PD_MISC_ADPDL;
-+ pd_ctrl |= TSC2301_REG_PD_MISC_ADPDR;
-+ pd_ctrl |= TSC2301_REG_PD_MISC_MIBPD;
-+ }
-+ if (!mix->dac_enabled) {
-+ /* DAC not used, power down DAC independently of user
-+ * space mixer selections */
-+ pd_ctrl |= TSC2301_REG_PD_MISC_DAPD;
-+ }
-+
-+ if (mix->pll_output) {
-+ /* GPIO_0 is configured as PLL output so audio
-+ * controller is expecting clock from TSC2301. Either
-+ * ADC or DAC must be active in order to keep PLL on */
-+ if ((pd_ctrl & TSC2301_REG_PD_MISC_ADPDL) &&
-+ (pd_ctrl & TSC2301_REG_PD_MISC_ADPDR) &&
-+ (pd_ctrl & TSC2301_REG_PD_MISC_DAPD)) {
-+ /* neither ADC or DAC used. Force ADC on in
-+ * order to keep PLL active */
-+ pd_ctrl &= ~(TSC2301_REG_PD_MISC_ADPDL |
-+ TSC2301_REG_PD_MISC_ADPDR);
-+ }
-+ }
-+ } else {
-+ /* audio input clock is not enabled so power down DAC and ADC
-+ * in order to shutdown PLL and to keep touchscreen and keypad
-+ * parts working. Touchscreen and keypad use audio clock when
-+ * PLL is on and internal clock otherwise */
-+ pd_ctrl |= TSC2301_REG_PD_MISC_DAPD |
-+ TSC2301_REG_PD_MISC_ADPDL |
-+ TSC2301_REG_PD_MISC_ADPDR;
-+ }
-+
-+ if ((pd_ctrl & TSC2301_REG_PD_MISC_ADPDL) &&
-+ (pd_ctrl & TSC2301_REG_PD_MISC_ADPDR) &&
-+ (pd_ctrl & TSC2301_REG_PD_MISC_DAPD) &&
-+ (pd_ctrl & TSC2301_REG_PD_MISC_ABPD)) {
-+ /* all ADC, DAC and line bypass path unused. Power down the
-+ * whole audio part of the TSC2301 */
-+ pd_ctrl |= TSC2301_REG_PD_MISC_APD;
-+ }
-+
-+ if (pd_ctrl == pd_ctrl_old)
-+ return;
-+
-+ /* power down control changed. Update into TSC2301 */
-+ if ((pd_ctrl ^ pd_ctrl_old) & TSC2301_REG_PD_MISC_APD) {
-+ /* whole audio power state changed. Update GPIO states */
-+ if (pd_ctrl & TSC2301_REG_PD_MISC_APD) {
-+ /* power down GPIO controls before powering down
-+ * the codec */
-+ tsc2301_gpio_power_down(tsc);
-+ /* we must really ensure that codec has been on no less
-+ * than 100 msec before doing power-down */
-+ timeout = mix->pu_jiffies + TSC2301_MIN_PU_PERIOD -
-+ jiffies;
-+ if (timeout <= TSC2301_MIN_PU_PERIOD) {
-+ mix->delayed_pd_active = 1;
-+ mix->mclk_enabled++;
-+ schedule_delayed_work(&mix->delayed_power_down,
-+ timeout + 1);
-+ return;
-+ }
-+ } else
-+ /* restore GPIOs after codec is powered up */
-+ power_up = 1;
-+ }
-+ mix->shadow_regs[PD_MISC_INDEX] = pd_ctrl;
-+ tsc2301_write_reg(tsc, TSC2301_REG_PD_MISC, pd_ctrl);
-+ if (power_up)
-+ mix->pu_jiffies = jiffies;
-+ if (!poll_pdsts) {
-+ if (power_up)
-+ tsc2301_write_reg(tsc, TSC2301_REG_GPIO,
-+ mix->shadow_regs[GPIO_INDEX]);
-+ return;
-+ }
-+
-+ /* wait until power-up/-down is completed */
-+ timeout = jiffies + msecs_to_jiffies(100);
-+ w = 0;
-+ do {
-+ if (time_after(jiffies, timeout)) {
-+ /* Print a warning only if the I2S clock is not
-+ * present / out of sync. This can happen during
-+ * init time, when that clock will be turned on
-+ * by another driver like in the OMAP EAC with
-+ * external clock case.
-+ */
-+ if (w & TSC2301_REG_PD_MISC_OTSYN) {
-+ dev_warn(&tsc->spi->dev,
-+ "I2S clock not in sync or off.\n");
-+ } else {
-+ dev_err(&tsc->spi->dev,
-+ "power-up/-down timed out "
-+ "(0x%04x, 0x%04x -> 0x%04x)\n",
-+ w, pd_ctrl_old, pd_ctrl);
-+ }
-+ goto out;
-+ }
-+ w = tsc2301_read_reg(tsc, TSC2301_REG_PD_MISC);
-+ } while (!(w & TSC2301_REG_PD_MISC_PDSTS));
-+
-+out:
-+ if (((pd_ctrl ^ pd_ctrl_old) & TSC2301_REG_PD_MISC_DAPD) &&
-+ !(pd_ctrl & TSC2301_REG_PD_MISC_DAPD)) {
-+ /* DAC powered up now. Ensure that DAC and audio outputs are
-+ * activated. They are up 100 msec after the chip power-up
-+ * command */
-+ timeout = mix->pu_jiffies + TSC2301_DAC_DELAY - jiffies;
-+ if (timeout <= TSC2301_DAC_DELAY)
-+ schedule_timeout_interruptible(timeout);
-+ /* FIXME: This is lazy. We restore GPIOs only after activating
-+ * the DAC. It would be better to do some kind of delayed GPIO
-+ * restore. That ensures that we restore them also if only ADC
-+ * path is activated. But this is required only if there is
-+ * some input amplifier, bias control, etc. and their power
-+ * state is under TSC GPIO control */
-+ tsc2301_write_reg(tsc, TSC2301_REG_GPIO,
-+ mix->shadow_regs[GPIO_INDEX]);
-+ }
-+}
-+
-+static int snd_tsc2301_info_single(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ int mask = TSC2301_SINGLE_MASK(kcontrol->private_value);
-+ int minval = TSC2301_SINGLE_MINVAL(kcontrol->private_value);
-+
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
-+ uinfo->count = 1;
-+ uinfo->value.integer.min = minval;
-+ uinfo->value.integer.max = mask;
-+
-+ return 0;
-+}
-+
-+static int snd_tsc2301_get_single(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct tsc2301 *tsc = kcontrol->private_data;
-+ unsigned long priv = kcontrol->private_value;
-+ int mask = TSC2301_SINGLE_MASK(priv);
-+ int shift = TSC2301_SINGLE_SHIFT(priv);
-+ int shadow_index = TSC2301_SHADOW_INDEX(priv);
-+ u16 shadow_reg;
-+
-+ shadow_reg = tsc->mixer->shadow_regs[shadow_index];
-+
-+ ucontrol->value.integer.value[0] = (shadow_reg >> shift) & mask;
-+
-+ return 0;
-+}
-+
-+static int snd_tsc2301_put_single(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct tsc2301 *tsc = kcontrol->private_data;
-+ unsigned long priv = kcontrol->private_value;
-+ int mask = TSC2301_SINGLE_MASK(priv);
-+ int shadow_index = TSC2301_SHADOW_INDEX(priv);
-+ u16 shadow_reg, shadow_reg_old;
-+ int shift = TSC2301_SINGLE_SHIFT(priv);
-+ int reg = TSC2301_PVAL_TO_REG(priv);
-+ int changed;
-+
-+ mutex_lock(&tsc->mixer->mutex);
-+ shadow_reg = shadow_reg_old = tsc->mixer->shadow_regs[shadow_index];
-+
-+ /* zero bits to be modified */
-+ shadow_reg &= ~(mask << shift);
-+ /* modify with new value */
-+ shadow_reg |= ((ucontrol->value.integer.value[0] & mask) << shift);
-+
-+ changed = (shadow_reg != shadow_reg_old);
-+ tsc->mixer->shadow_regs[shadow_index] = shadow_reg;
-+
-+ /* update into TSC2301 if necessary */
-+ if (changed)
-+ tsc2301_write_reg(tsc, reg, shadow_reg);
-+ mutex_unlock(&tsc->mixer->mutex);
-+
-+ return changed;
-+}
-+
-+static int snd_tsc2301_info_double(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ /* mask == 1 : Switch
-+ * mask > 1 : Max volume */
-+ int mask = TSC2301_DOUBLE_MASK(kcontrol->private_value);
-+ int minval = TSC2301_DOUBLE_MINVAL(kcontrol->private_value);
-+
-+ uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN :
-+ SNDRV_CTL_ELEM_TYPE_INTEGER;
-+ uinfo->count = 2;
-+ uinfo->value.integer.min = minval;
-+ uinfo->value.integer.max = mask;
-+
-+ return 0;
-+}
-+
-+static int snd_tsc2301_get_double(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct tsc2301 *tsc = kcontrol->private_data;
-+ unsigned long priv = kcontrol->private_value;
-+ /* mask == 1 : Switch
-+ * mask > 1 : Volume */
-+ int mask = TSC2301_DOUBLE_MASK(priv);
-+ int ls = TSC2301_DOUBLE_LEFT_SHIFT(priv);
-+ int rs = TSC2301_DOUBLE_RIGHT_SHIFT(priv);
-+ int shadow_index = TSC2301_SHADOW_INDEX(priv);
-+ u16 shadow_reg;
-+
-+ shadow_reg = tsc->mixer->shadow_regs[shadow_index];
-+
-+ /* invert mute bits for the switches */
-+ if (mask == 1)
-+ shadow_reg = ~shadow_reg;
-+
-+ ucontrol->value.integer.value[0] = (shadow_reg >> ls) & mask;
-+ ucontrol->value.integer.value[1] = (shadow_reg >> rs) & mask;
-+
-+ return 0;
-+}
-+
-+static int snd_tsc2301_put_double(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct tsc2301 *tsc = kcontrol->private_data;
-+ unsigned long priv = kcontrol->private_value;
-+ /* mask == 1 : Switch
-+ * mask > 1 : Volume */
-+ int mask = TSC2301_DOUBLE_MASK(priv);
-+ int shadow_index = TSC2301_SHADOW_INDEX(priv);
-+ u16 shadow_reg, shadow_reg_old;
-+ int ls = TSC2301_DOUBLE_LEFT_SHIFT(priv);
-+ int rs = TSC2301_DOUBLE_RIGHT_SHIFT(priv);
-+ int reg = TSC2301_PVAL_TO_REG(priv);
-+ int changed;
-+
-+ mutex_lock(&tsc->mixer->mutex);
-+ shadow_reg = shadow_reg_old = tsc->mixer->shadow_regs[shadow_index];
-+
-+ /* zero bits to be modified */
-+ shadow_reg &= ~((mask << ls) | (mask << rs));
-+ /* modify with new value */
-+ if (mask == 1) {
-+ /* switch. Invert switch values for the mute bits */
-+ shadow_reg |=
-+ ((~ucontrol->value.integer.value[0] & mask) << ls) |
-+ ((~ucontrol->value.integer.value[1] & mask) << rs);
-+ } else {
-+ /* volume */
-+ shadow_reg |=
-+ (ucontrol->value.integer.value[0] << ls) |
-+ (ucontrol->value.integer.value[1] << rs);
-+ }
-+
-+ changed = (shadow_reg != shadow_reg_old);
-+ tsc->mixer->shadow_regs[shadow_index] = shadow_reg;
-+
-+ /* update into TSC2301 if necessary */
-+ if (changed)
-+ tsc2301_write_reg(tsc, reg, shadow_reg);
-+
-+ if (mask == 1)
-+ /* check is need to power down/up audio blocks in case of
-+ * muted state change */
-+ tsc2301_power_ctrl(tsc, shadow_index, 0);
-+ mutex_unlock(&tsc->mixer->mutex);
-+
-+ return changed;
-+}
-+
-+static int snd_tsc2301_info_mux(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ static char *texts[4] = {"Mic", "Line", "Line swapped", "Line mono"};
-+
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
-+ uinfo->count = 2;
-+ uinfo->value.enumerated.items = 4;
-+ if (uinfo->value.enumerated.item > 3)
-+ uinfo->value.enumerated.item = 3;
-+ strcpy(uinfo->value.enumerated.name,
-+ texts[uinfo->value.enumerated.item]);
-+
-+ return 0;
-+}
-+
-+static int snd_tsc2301_get_mux(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct tsc2301 *tsc = kcontrol->private_data;
-+ unsigned long priv = kcontrol->private_value;
-+ int mask = TSC2301_MUX_MASK(priv);
-+ int ls = TSC2301_MUX_LEFT_SHIFT(priv);
-+ int rs = TSC2301_MUX_RIGHT_SHIFT(priv);
-+ int shadow_index = TSC2301_SHADOW_INDEX(priv);
-+ u16 shadow_reg;
-+
-+ shadow_reg = tsc->mixer->shadow_regs[shadow_index];
-+ ucontrol->value.enumerated.item[0] = (shadow_reg >> ls) & mask;
-+ ucontrol->value.enumerated.item[1] = (shadow_reg >> rs) & mask;
-+
-+ return 0;
-+}
-+
-+static int snd_tsc2301_put_mux(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct tsc2301 *tsc = kcontrol->private_data;
-+ unsigned long priv = kcontrol->private_value;
-+ int mask = TSC2301_MUX_MASK(priv);
-+ int shadow_index = TSC2301_SHADOW_INDEX(priv);
-+ u16 shadow_reg, shadow_reg_old;
-+ int ls = TSC2301_MUX_LEFT_SHIFT(priv);
-+ int rs = TSC2301_MUX_RIGHT_SHIFT(priv);
-+ int reg = TSC2301_PVAL_TO_REG(priv);
-+ int changed;
-+
-+ mutex_lock(&tsc->mixer->mutex);
-+ shadow_reg = shadow_reg_old = tsc->mixer->shadow_regs[shadow_index];
-+
-+ /* zero bits to be modified */
-+ shadow_reg &= ~((mask << ls) | (mask << rs));
-+ /* modify with new value */
-+ shadow_reg |= (ucontrol->value.enumerated.item[0] << ls);
-+ shadow_reg |= (ucontrol->value.enumerated.item[1] << rs);
-+
-+ changed = (shadow_reg != shadow_reg_old);
-+
-+ /* update into TSC2301 if necessary */
-+ if (changed) {
-+ tsc->mixer->shadow_regs[shadow_index] = shadow_reg;
-+ tsc2301_write_reg(tsc, reg, shadow_reg);
-+ }
-+
-+ /* check is need to power up/down audio blocks in case of ADC input
-+ * change */
-+ tsc2301_power_ctrl(tsc, shadow_index, 0);
-+ mutex_unlock(&tsc->mixer->mutex);
-+
-+ return changed;
-+}
-+
-+static int snd_tsc2301_info_bool(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
-+ uinfo->count = 1;
-+ uinfo->value.integer.min = 0;
-+ uinfo->value.integer.max = 1;
-+
-+ return 0;
-+}
-+
-+static int snd_tsc2301_get_bool(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct tsc2301 *tsc = kcontrol->private_data;
-+ unsigned long priv = kcontrol->private_value;
-+ int shadow_index = TSC2301_SHADOW_INDEX(priv);
-+ int shift = TSC2301_BOOL_SHIFT(priv);
-+ int invert = TSC2301_BOOL_INVERT(priv);
-+ u16 shadow_reg;
-+
-+ shadow_reg = tsc->mixer->shadow_regs[shadow_index];
-+ ucontrol->value.integer.value[0] =
-+ invert ^ ((shadow_reg >> shift) & 1);
-+
-+ return 0;
-+}
-+
-+static int snd_tsc2301_put_bool(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct tsc2301 *tsc = kcontrol->private_data;
-+ unsigned long priv = kcontrol->private_value;
-+ int shadow_index = TSC2301_SHADOW_INDEX(priv);
-+ int shift = TSC2301_BOOL_SHIFT(priv);
-+ int invert = TSC2301_BOOL_INVERT(priv);
-+ int reg = TSC2301_PVAL_TO_REG(priv);
-+ u16 shadow_reg, shadow_reg_old;
-+ int changed;
-+
-+ mutex_lock(&tsc->mixer->mutex);
-+ shadow_reg = shadow_reg_old = tsc->mixer->shadow_regs[shadow_index];
-+
-+ /* zero bit to be modified */
-+ shadow_reg &= ~(1 << shift);
-+ /* modify with new value */
-+ shadow_reg |=
-+ (invert ^ (ucontrol->value.integer.value[0] & 1)) << shift;
-+
-+ changed = (shadow_reg != shadow_reg_old);
-+
-+ /* update into TSC2301 if necessary */
-+ if (changed) {
-+ tsc->mixer->shadow_regs[shadow_index] = shadow_reg;
-+ if ((shadow_index == GPIO_INDEX) &&
-+ (tsc->mixer->shadow_regs[PD_MISC_INDEX] &
-+ TSC2301_REG_PD_MISC_APD)) {
-+ /* changing GPIO control and audio is powered down.
-+ * Update GPIO states according to their power-down
-+ * flag */
-+ tsc2301_gpio_power_down(tsc);
-+ } else
-+ tsc2301_write_reg(tsc, reg, shadow_reg);
-+ }
-+ mutex_unlock(&tsc->mixer->mutex);
-+
-+ return changed;
-+}
-+
-+/* TSC2301 internal mixer controls */
-+static struct snd_kcontrol_new snd_tsc2301_controls[] = {
-+ /* stereo ADC input switches and volumes */
-+ TSC2301_DOUBLE("Capture Switch", 0,
-+ TSC2301_REG_ADCVOL, ADCVOL_INDEX,
-+ TSC2301_MUTE_LEFT_SHIFT, TSC2301_MUTE_RIGHT_SHIFT,
-+ 1, 0),
-+ TSC2301_DOUBLE("Capture Volume", 0,
-+ TSC2301_REG_ADCVOL, ADCVOL_INDEX,
-+ TSC2301_VOL_LEFT_SHIFT, TSC2301_VOL_RIGHT_SHIFT,
-+ TSC2301_VOLUME_MASK, TSC2301_MIN_ADCVOL),
-+
-+ /* stereo DAC output switches and volumes */
-+ TSC2301_DOUBLE("PCM Playback Switch", 0,
-+ TSC2301_REG_DACVOL, DACVOL_INDEX,
-+ TSC2301_MUTE_LEFT_SHIFT, TSC2301_MUTE_RIGHT_SHIFT,
-+ 1, 0),
-+ TSC2301_DOUBLE("PCM Playback Volume", 0,
-+ TSC2301_REG_DACVOL, DACVOL_INDEX,
-+ TSC2301_VOL_LEFT_SHIFT, TSC2301_VOL_RIGHT_SHIFT,
-+ TSC2301_VOLUME_MASK, TSC2301_MIN_DACVOL),
-+
-+ /* stereo line input bypass switches and volumes */
-+ TSC2301_DOUBLE("Line Playback Switch", 0,
-+ TSC2301_REG_BPVOL, BPVOL_INDEX,
-+ TSC2301_MUTE_LEFT_SHIFT, TSC2301_MUTE_RIGHT_SHIFT,
-+ 1, 0),
-+ TSC2301_DOUBLE("Line Playback Volume", 0,
-+ TSC2301_REG_BPVOL, BPVOL_INDEX,
-+ TSC2301_VOL_LEFT_SHIFT, TSC2301_VOL_RIGHT_SHIFT,
-+ TSC2301_VOLUME_MASK, TSC2301_MIN_BPVOL),
-+
-+ /* mono microphone input gain */
-+ TSC2301_SINGLE("Mic Boost", 0,
-+ TSC2301_REG_AUDCNTL, AUDCNTL_INDEX,
-+ TSC2301_MICG_SHIFT,
-+ TSC2301_MICG_MASK, TSC2301_MICG_MIN),
-+
-+ /* ADC input sources. Both channels could be selected separately */
-+ TSC2301_MUX("Capture Source", 0,
-+ TSC2301_REG_AUDCNTL, AUDCNTL_INDEX,
-+ TSC2301_INML_SHIFT, TSC2301_INMR_SHIFT,
-+ TSC2301_INM_MASK),
-+};
-+
-+/* must be called tsc->mixer->mutex locked */
-+static void tsc2301_flush_shadow_regs(struct tsc2301 *tsc)
-+{
-+ int i, page, addr;
-+ u16 temp;
-+
-+ page = TSC2301_REG_TO_PAGE(TSC2301_REG_AUDCNTL);
-+ addr = TSC2301_REG_TO_ADDR(TSC2301_REG_AUDCNTL);
-+
-+ for (i = 0; i < 4; i++) {
-+ temp = tsc->mixer->shadow_regs[i];
-+ tsc2301_write_reg(tsc, TSC2301_REG(page, addr + i), temp);
-+ }
-+ temp = tsc->mixer->shadow_regs[GPIO_INDEX];
-+ tsc2301_write_reg(tsc, TSC2301_REG_GPIO, temp);
-+
-+ /* Update power state of all audio blocks depending are they
-+ * muted or unused. */
-+ tsc2301_power_ctrl(tsc, -1, 0);
-+}
-+
-+#ifdef CONFIG_PM
-+int tsc2301_mixer_suspend(struct tsc2301 *tsc)
-+{
-+ /* power down entire audio section inside TSC2301 in case the
-+ * chip is still powered during the system sleep. However this driver
-+ * doesn't require that chip is powered because registers are restored
-+ * in function tsc2301_mixer_resume */
-+ mutex_lock(&tsc->mixer->mutex);
-+ tsc2301_gpio_power_down(tsc);
-+ tsc->mixer->shadow_regs[PD_MISC_INDEX] |= TSC2301_REG_PD_MISC_APD;
-+ tsc2301_write_reg(tsc, TSC2301_REG_PD_MISC,
-+ tsc->mixer->shadow_regs[PD_MISC_INDEX]);
-+ mutex_unlock(&tsc->mixer->mutex);
-+ return 0;
-+}
-+
-+void tsc2301_mixer_resume(struct tsc2301 *tsc)
-+{
-+ /* power up the TSC2301 audio section and restore registers */
-+ mutex_lock(&tsc->mixer->mutex);
-+ tsc->mixer->shadow_regs[PD_MISC_INDEX] &= ~TSC2301_REG_PD_MISC_APD;
-+ tsc2301_flush_shadow_regs(tsc);
-+ mutex_unlock(&tsc->mixer->mutex);
-+}
-+#endif
-+
-+void tsc2301_mixer_enable_mclk(struct device *dev)
-+{
-+ struct tsc2301 *tsc = dev_get_drvdata(dev);
-+ struct tsc2301_mixer *mix = tsc->mixer;
-+
-+ mutex_lock(&mix->mutex);
-+ if (!mix->mclk_enabled++ && tsc->enable_clock != NULL) {
-+ tsc->enable_clock(dev);
-+ }
-+ tsc2301_power_ctrl(tsc, -1, 1);
-+ mutex_unlock(&mix->mutex);
-+}
-+
-+void tsc2301_mixer_disable_mclk(struct device *dev)
-+{
-+ struct tsc2301 *tsc = dev_get_drvdata(dev);
-+ struct tsc2301_mixer *mix = tsc->mixer;
-+
-+ mutex_lock(&mix->mutex);
-+ mix->mclk_enabled--;
-+ tsc2301_power_ctrl(tsc, -1, 1);
-+ if (!mix->mclk_enabled && tsc->disable_clock != NULL) {
-+ tsc->disable_clock(dev);
-+ }
-+ mutex_unlock(&mix->mutex);
-+}
-+
-+static void tsc2301_mixer_delayed_power_down(struct work_struct *work)
-+{
-+ struct tsc2301_mixer *mix = container_of(work, struct tsc2301_mixer,
-+ delayed_power_down.work);
-+ struct tsc2301 *tsc = mix->tsc;
-+
-+ mutex_lock(&mix->mutex);
-+ if (!mix->delayed_pd_active) {
-+ mutex_unlock(&mix->mutex);
-+ return;
-+ }
-+ mix->delayed_pd_active = 0;
-+ mutex_unlock(&mix->mutex);
-+ tsc2301_mixer_disable_mclk(&tsc->spi->dev);
-+}
-+
-+/*
-+ * Allows audio controller driver to notify its usage of ADC and DAC
-+ */
-+void tsc2301_mixer_set_power(struct device *dev, int dac, int adc)
-+{
-+ struct tsc2301 *tsc = dev_get_drvdata(dev);
-+
-+ mutex_lock(&tsc->mixer->mutex);
-+ tsc->mixer->adc_enabled = adc;
-+ tsc->mixer->dac_enabled = dac;
-+
-+ /* update power state of all audio blocks */
-+ tsc2301_power_ctrl(tsc, -1, 1);
-+ mutex_unlock(&tsc->mixer->mutex);
-+}
-+
-+/*
-+ * Registers TSC2301 ALSA Mixer controls for the given sound card
-+ */
-+int tsc2301_mixer_register_controls(struct device *dev, struct snd_card *card)
-+{
-+ struct tsc2301 *tsc = dev_get_drvdata(dev);
-+ struct tsc2301_mixer *mix = tsc->mixer;
-+ int i, err;
-+
-+ /* Register ALSA mixer controls */
-+ for (i = 0; i < ARRAY_SIZE(snd_tsc2301_controls); i++) {
-+ err = snd_ctl_add(card,
-+ snd_ctl_new1(&snd_tsc2301_controls[i], tsc));
-+ if (err < 0)
-+ return err;
-+ }
-+
-+ if (!mix->n_mixer_gpios)
-+ return 0;
-+
-+ /* Register additional GPIO controls if defined */
-+ for (i = 0; i < mix->n_mixer_gpios; i++) {
-+ const struct tsc2301_mixer_gpio *mg = mix->mixer_gpios + i;
-+ struct snd_kcontrol *ctrlp;
-+ struct snd_kcontrol_new ctrl =
-+ TSC2301_BOOL((char *)mg->name, 0,
-+ TSC2301_REG_GPIO, GPIO_INDEX,
-+ mg->gpio, mg->inverted, mg->def_enable);
-+
-+ ctrlp = snd_ctl_new1(&ctrl, tsc);
-+ err = snd_ctl_add(card, ctrlp);
-+ if (err < 0)
-+ return err;
-+ }
-+
-+ return 0;
-+}
-+
-+int tsc2301_mixer_init(struct tsc2301 *tsc,
-+ struct tsc2301_platform_data *pdata)
-+{
-+ struct tsc2301_mixer *mix;
-+ int err = 0;
-+ u16 w;
-+
-+ mix = kzalloc(sizeof(*mix), GFP_KERNEL);
-+ if (mix == NULL)
-+ return -ENOMEM;
-+ tsc->mixer = mix;
-+
-+ mix->tsc = tsc;
-+ mutex_init(&mix->mutex);
-+ mix->platform_init = pdata->codec_init;
-+ mix->platform_cleanup = pdata->codec_cleanup;
-+ mix->pll_output = pdata->pll_output;
-+
-+ INIT_DELAYED_WORK(&mix->delayed_power_down,
-+ tsc2301_mixer_delayed_power_down);
-+
-+ /* initialize shadow register default values */
-+ w = 0xc000;
-+ w |= (pdata->mclk_ratio << 6) | (pdata->i2s_sample_rate << 2);
-+ w |= pdata->i2s_format;
-+ mix->shadow_regs[AUDCNTL_INDEX] = w;
-+ mix->shadow_regs[ADCVOL_INDEX] = 0xd7d7;
-+ mix->shadow_regs[DACVOL_INDEX] = 0xffff;
-+ mix->shadow_regs[BPVOL_INDEX] = 0xe7e7;
-+ mix->shadow_regs[PD_MISC_INDEX] = pdata->power_down_blocks;
-+
-+ /* if extra mixer controls configured, then configure associated
-+ * GPIOs as output and drive their default state */
-+ if (pdata->n_mixer_gpios) {
-+ int i;
-+
-+ w = 0;
-+ for (i = 0; i < pdata->n_mixer_gpios; i++) {
-+ const struct tsc2301_mixer_gpio *mg;
-+ int gpio;
-+
-+ mg = pdata->mixer_gpios + i;
-+ gpio = mg->gpio;
-+ w |= (1 << gpio) << 8;
-+ w |= (mg->inverted ^ mg->def_enable) << gpio;
-+ }
-+ mix->shadow_regs[GPIO_INDEX] = w;
-+
-+ mix->mixer_gpios = kmalloc(sizeof(*pdata->mixer_gpios) *
-+ pdata->n_mixer_gpios,
-+ GFP_KERNEL);
-+ if (mix->mixer_gpios == NULL) {
-+ err = -ENOMEM;
-+ goto err1;
-+ }
-+ memcpy(mix->mixer_gpios, pdata->mixer_gpios,
-+ sizeof(*pdata->mixer_gpios) * pdata->n_mixer_gpios);
-+ mix->n_mixer_gpios = pdata->n_mixer_gpios;
-+ }
-+
-+ /* PLL control */
-+ tsc2301_write_pll(tsc, pdata->pll_n, pdata->pll_a, pdata->pll_pdc,
-+ 0, mix->pll_output ? 0 : 1);
-+
-+ tsc2301_flush_shadow_regs(tsc);
-+
-+ if (mix->platform_init != NULL) {
-+ err = mix->platform_init(&tsc->spi->dev);
-+ if (err < 0)
-+ goto err2;
-+ }
-+
-+ return 0;
-+err2:
-+ if (mix->mixer_gpios != NULL)
-+ kfree(mix->mixer_gpios);
-+err1:
-+ kfree(mix);
-+ return err;
-+}
-+
-+void tsc2301_mixer_exit(struct tsc2301 *tsc)
-+{
-+ struct tsc2301_mixer *mixer = tsc->mixer;
-+
-+ if (mixer->platform_cleanup != NULL)
-+ mixer->platform_cleanup(&tsc->spi->dev);
-+
-+ if (mixer->mixer_gpios != NULL)
-+ kfree(mixer->mixer_gpios);
-+}
-+
-+MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/include/linux/spi/tsc2301.h
-@@ -0,0 +1,208 @@
-+#ifndef _LINUX_SPI_TSC2301_H
-+#define _LINUX_SPI_TSC2301_H
-+
-+#include <linux/types.h>
-+#include <linux/timer.h>
-+
-+struct tsc2301_platform_data {
-+ /*
-+ * Keypad
-+ */
-+ s16 reset_gpio;
-+ s16 keyb_int;
-+ s16 keymap[16]; /* Set a key to a negative value if not used */
-+ unsigned kp_rep:1; /* Enable keypad repeating */
-+ char *keyb_name; /* Keyboard device name */
-+
-+ /*
-+ * Touchscreen
-+ */
-+ s16 dav_int;
-+ u16 ts_x_plate_ohm;
-+ u32 ts_stab_time; /* voltage settling time */
-+ u8 ts_hw_avg; /* HW assiseted averaging. Can be
-+ 0, 4, 8, 16 samples per reading */
-+ u32 ts_max_pressure;/* Samples with bigger pressure value will
-+ be ignored, since the corresponding X, Y
-+ values are unreliable */
-+ u32 ts_touch_pressure; /* Pressure limit until we report a
-+ touch event. After that we switch
-+ to ts_max_pressure. */
-+ u32 ts_pressure_fudge;
-+ u32 ts_x_max;
-+ u32 ts_x_fudge;
-+ u32 ts_y_max;
-+ u32 ts_y_fudge;
-+
-+ /*
-+ * Audio
-+ */
-+ unsigned pll_pdc:4;
-+ unsigned pll_a:4;
-+ unsigned pll_n:4;
-+ unsigned pll_output:1; /* Output PLL on GPIO_0 */
-+
-+ unsigned mclk_ratio:2;
-+ unsigned i2s_sample_rate:4;
-+ unsigned i2s_format:2;
-+ /* Mask for audio blocks to be powered down */
-+ u16 power_down_blocks;
-+
-+ /* Called after codec has been initialized, can be NULL */
-+ int (* codec_init)(struct device *tsc2301_dev);
-+ /* Called when codec is being removed, can be NULL */
-+ void (* codec_cleanup)(struct device *tsc2301_dev);
-+ int (*enable_clock)(struct device *dev);
-+ void (*disable_clock)(struct device *dev);
-+
-+ const struct tsc2301_mixer_gpio {
-+ const char *name;
-+ unsigned gpio:4;
-+ unsigned inverted:1;
-+ unsigned def_enable:1; /* enable by default */
-+ unsigned deactivate_on_pd:1; /* power-down flag */
-+ } *mixer_gpios;
-+ int n_mixer_gpios;
-+};
-+
-+struct tsc2301_kp;
-+struct tsc2301_ts;
-+struct tsc2301_mixer;
-+
-+struct tsc2301 {
-+ struct spi_device *spi;
-+
-+ s16 reset_gpio;
-+ u16 config2_shadow;
-+
-+ struct tsc2301_kp *kp;
-+ struct tsc2301_ts *ts;
-+ struct tsc2301_mixer *mixer;
-+
-+ int (*enable_clock)(struct device *dev);
-+ void (*disable_clock)(struct device *dev);
-+};
-+
-+
-+#define TSC2301_HZ 33000000
-+
-+#define TSC2301_REG(page, addr) (((page) << 11) | ((addr) << 5))
-+#define TSC2301_REG_TO_PAGE(reg) (((reg) >> 11) & 0x03)
-+#define TSC2301_REG_TO_ADDR(reg) (((reg) >> 5) & 0x1f)
-+
-+#define TSC2301_REG_X TSC2301_REG(0, 0)
-+#define TSC2301_REG_Y TSC2301_REG(0, 1)
-+#define TSC2301_REG_Z1 TSC2301_REG(0, 2)
-+#define TSC2301_REG_Z2 TSC2301_REG(0, 3)
-+#define TSC2301_REG_KPDATA TSC2301_REG(0, 4)
-+#define TSC2301_REG_ADC TSC2301_REG(1, 0)
-+#define TSC2301_REG_KEY TSC2301_REG(1, 1)
-+#define TSC2301_REG_DAC TSC2301_REG(1, 2)
-+#define TSC2301_REG_REF TSC2301_REG(1, 3)
-+#define TSC2301_REG_RESET TSC2301_REG(1, 4)
-+#define TSC2301_REG_CONFIG TSC2301_REG(1, 5)
-+#define TSC2301_REG_CONFIG2 TSC2301_REG(1, 6)
-+#define TSC2301_REG_KPMASK TSC2301_REG(1, 16)
-+#define TSC2301_REG_AUDCNTL TSC2301_REG(2, 0)
-+#define TSC2301_REG_ADCVOL TSC2301_REG(2, 1)
-+#define TSC2301_REG_DACVOL TSC2301_REG(2, 2)
-+#define TSC2301_REG_BPVOL TSC2301_REG(2, 3)
-+#define TSC2301_REG_KEYCTL TSC2301_REG(2, 4)
-+#define TSC2301_REG_PD_MISC TSC2301_REG(2, 5)
-+#define TSC2301_REG_GPIO TSC2301_REG(2, 6)
-+#define TSC2301_REG_ADCLKCFG TSC2301_REG(2, 27)
-+
-+#define TSC2301_REG_PD_MISC_APD (1 << 15)
-+#define TSC2301_REG_PD_MISC_AVPD (1 << 14)
-+#define TSC2301_REG_PD_MISC_ABPD (1 << 13)
-+#define TSC2301_REG_PD_MISC_HAPD (1 << 12)
-+#define TSC2301_REG_PD_MISC_MOPD (1 << 11)
-+#define TSC2301_REG_PD_MISC_DAPD (1 << 10)
-+#define TSC2301_REG_PD_MISC_ADPDL (1 << 9)
-+#define TSC2301_REG_PD_MISC_ADPDR (1 << 8)
-+#define TSC2301_REG_PD_MISC_PDSTS (1 << 7)
-+#define TSC2301_REG_PD_MISC_MIBPD (1 << 6)
-+#define TSC2301_REG_PD_MISC_OTSYN (1 << 2)
-+
-+/* I2S sample rate */
-+#define TSC2301_I2S_SR_48000 0x00
-+#define TSC2301_I2S_SR_44100 0x01
-+#define TSC2301_I2S_SR_32000 0x02
-+#define TSC2301_I2S_SR_24000 0x03
-+#define TSC2301_I2S_SR_22050 0x04
-+#define TSC2301_I2S_SR_16000 0x05
-+#define TSC2301_I2S_SR_12000 0x06
-+#define TSC2301_I2S_SR_11050 0x07
-+#define TSC2301_I2S_SR_8000 0x08
-+
-+/* 16-bit, MSB-first. DAC Right-Justified, ADC Left-Justified */
-+#define TSC2301_I2S_FORMAT0 0x00
-+/* 20-bit, MSB-first. DAC Right-Justified, ADC Left-Justified */
-+#define TSC2301_I2S_FORMAT1 0x01
-+/* 20-bit, MSB-first. DAC Left-Justified, ADC Left-Justified */
-+#define TSC2301_I2S_FORMAT2 0x02
-+/* 20-bit, MSB-first */
-+#define TSC2301_I2S_FORMAT3 0x03
-+
-+/* Master Clock Ratio */
-+#define TSC2301_MCLK_256xFS 0x00 /* default */
-+#define TSC2301_MCLK_384xFS 0x01
-+#define TSC2301_MCLK_512xFS 0x02
-+
-+
-+extern u16 tsc2301_read_reg(struct tsc2301 *tsc, int reg);
-+extern void tsc2301_write_reg(struct tsc2301 *tsc, int reg, u16 val);
-+extern void tsc2301_write_kbc(struct tsc2301 *tsc, int val);
-+extern void tsc2301_write_pll(struct tsc2301 *tsc, int pll_n, int pll_a,
-+ int pll_pdc, int pct_e, int pll_o);
-+extern void tsc2301_read_buf(struct tsc2301 *tsc, int reg, u16 *buf, int len);
-+
-+#define TSC2301_DECL_MOD(module) \
-+extern int tsc2301_##module##_init(struct tsc2301 *tsc, \
-+ struct tsc2301_platform_data *pdata); \
-+extern void tsc2301_##module##_exit(struct tsc2301 *tsc); \
-+extern int tsc2301_##module##_suspend(struct tsc2301 *tsc); \
-+extern void tsc2301_##module##_resume(struct tsc2301 *tsc);
-+
-+#define TSC2301_DECL_EMPTY_MOD(module) \
-+static inline int tsc2301_##module##_init(struct tsc2301 *tsc, \
-+ struct tsc2301_platform_data *pdata) \
-+{ \
-+ return 0; \
-+} \
-+static inline void tsc2301_##module##_exit(struct tsc2301 *tsc) {} \
-+static inline int tsc2301_##module##_suspend(struct tsc2301 *tsc) \
-+{ \
-+ return 0; \
-+} \
-+static inline void tsc2301_##module##_resume(struct tsc2301 *tsc) {}
-+
-+#ifdef CONFIG_KEYBOARD_TSC2301
-+TSC2301_DECL_MOD(kp)
-+void tsc2301_kp_restart(struct tsc2301 *tsc);
-+#else
-+TSC2301_DECL_EMPTY_MOD(kp)
-+static inline void tsc2301_kp_restart(struct tsc2301 *tsc) {}
-+#endif
-+
-+#ifdef CONFIG_TOUCHSCREEN_TSC2301
-+TSC2301_DECL_MOD(ts)
-+#else
-+TSC2301_DECL_EMPTY_MOD(ts)
-+#endif
-+
-+#ifdef CONFIG_SPI_TSC2301_AUDIO
-+TSC2301_DECL_MOD(mixer)
-+extern void tsc2301_mixer_set_power(struct device *tsc_dev, int dac, int adc);
-+
-+struct snd_card;
-+extern int tsc2301_mixer_register_controls(struct device *tsc_dev,
-+ struct snd_card *card);
-+#else
-+TSC2301_DECL_EMPTY_MOD(mixer)
-+#endif
-+
-+extern void tsc2301_mixer_enable_mclk(struct device *tsc_dev);
-+extern void tsc2301_mixer_disable_mclk(struct device *tsc_dev);
-+
-+#endif
+++ /dev/null
---- a/arch/arm/mach-omap2/board-n8x0.c
-+++ b/arch/arm/mach-omap2/board-n8x0.c
-@@ -25,6 +25,8 @@
- #include <linux/usb/musb.h>
- #include <sound/tlv320aic3x.h>
- #include <linux/spi/tsc2005.h>
-+#include <linux/input.h>
-+#include <linux/i2c/lm8323.h>
-
- #include <asm/mach/arch.h>
- #include <asm/mach-types.h>
-@@ -37,6 +39,7 @@
- #include <plat/onenand.h>
- #include <plat/mmc.h>
- #include <plat/serial.h>
-+#include <plat/gpio-switch.h>
-
- #include "mux.h"
-
-@@ -104,6 +107,152 @@ extern struct mipid_platform_data n8x0_m
- extern void n8x0_mipid_init(void);
- extern void n8x0_blizzard_init(void);
-
-+/* We map the FN key as LALT to workaround an X keycode problem.
-+ * The XKB map needs to be adjusted to support this. */
-+#define MAP_FN_AS_LEFTALT
-+
-+static s16 rx44_keymap[LM8323_KEYMAP_SIZE] = {
-+ [0x01] = KEY_Q,
-+ [0x02] = KEY_K,
-+ [0x03] = KEY_O,
-+ [0x04] = KEY_P,
-+ [0x05] = KEY_BACKSPACE,
-+ [0x06] = KEY_A,
-+ [0x07] = KEY_S,
-+ [0x08] = KEY_D,
-+ [0x09] = KEY_F,
-+ [0x0a] = KEY_G,
-+ [0x0b] = KEY_H,
-+ [0x0c] = KEY_J,
-+
-+ [0x11] = KEY_W,
-+ [0x12] = KEY_F4,
-+ [0x13] = KEY_L,
-+ [0x14] = KEY_APOSTROPHE,
-+ [0x16] = KEY_Z,
-+ [0x17] = KEY_X,
-+ [0x18] = KEY_C,
-+ [0x19] = KEY_V,
-+ [0x1a] = KEY_B,
-+ [0x1b] = KEY_N,
-+ [0x1c] = KEY_LEFTSHIFT, /* Actually, this is both shift keys */
-+ [0x1f] = KEY_F7,
-+
-+ [0x21] = KEY_E,
-+ [0x22] = KEY_SEMICOLON,
-+ [0x23] = KEY_MINUS,
-+ [0x24] = KEY_EQUAL,
-+#ifdef MAP_FN_AS_LEFTALT
-+ [0x2b] = KEY_LEFTALT,
-+#else
-+ [0x2b] = KEY_FN,
-+#endif
-+ [0x2c] = KEY_M,
-+ [0x2f] = KEY_F8,
-+
-+ [0x31] = KEY_R,
-+ [0x32] = KEY_RIGHTCTRL,
-+ [0x34] = KEY_SPACE,
-+ [0x35] = KEY_COMMA,
-+ [0x37] = KEY_UP,
-+ [0x3c] = KEY_COMPOSE,
-+ [0x3f] = KEY_F6,
-+
-+ [0x41] = KEY_T,
-+ [0x44] = KEY_DOT,
-+ [0x46] = KEY_RIGHT,
-+ [0x4f] = KEY_F5,
-+ [0x51] = KEY_Y,
-+ [0x53] = KEY_DOWN,
-+ [0x55] = KEY_ENTER,
-+ [0x5f] = KEY_ESC,
-+
-+ [0x61] = KEY_U,
-+ [0x64] = KEY_LEFT,
-+
-+ [0x71] = KEY_I,
-+ [0x75] = KEY_KPENTER,
-+};
-+
-+static struct lm8323_platform_data lm8323_pdata = {
-+ .repeat = 0, /* Repeat is handled in userspace for now. */
-+ .keymap = rx44_keymap,
-+ .size_x = 8,
-+ .size_y = 12,
-+ .debounce_time = 12,
-+ .active_time = 500,
-+
-+ .name = "Internal keyboard",
-+ .pwm_names[0] = "n810::keyboard",
-+ .pwm_names[1] = "n810::cover",
-+};
-+
-+#define OMAP_TAG_NOKIA_BT 0x4e01
-+
-+struct omap_bluetooth_config {
-+ u8 chip_type;
-+ u8 bt_wakeup_gpio;
-+ u8 host_wakeup_gpio;
-+ u8 reset_gpio;
-+ u8 bt_uart;
-+ u8 bd_addr[6];
-+ u8 bt_sysclk;
-+};
-+
-+static struct platform_device n8x0_bt_device = {
-+ .name = "hci_h4p",
-+ .id = -1,
-+ .num_resources = 0,
-+};
-+
-+void __init n8x0_bt_init(void)
-+{
-+ const struct omap_bluetooth_config *bt_config;
-+
-+ bt_config = (void *) omap_get_config(OMAP_TAG_NOKIA_BT,
-+ struct omap_bluetooth_config);
-+ n8x0_bt_device.dev.platform_data = (void *) bt_config;
-+ if (platform_device_register(&n8x0_bt_device) < 0)
-+ BUG();
-+}
-+
-+static struct omap_gpio_switch n8x0_gpio_switches[] __initdata = {
-+ {
-+ .name = "headphone",
-+ .gpio = -1,
-+ .debounce_rising = 200,
-+ .debounce_falling = 200,
-+ }, {
-+ .name = "cam_act",
-+ .gpio = -1,
-+ .debounce_rising = 200,
-+ .debounce_falling = 200,
-+ }, {
-+ .name = "cam_turn",
-+ .gpio = -1,
-+ .debounce_rising = 100,
-+ .debounce_falling = 100,
-+ }, {
-+ .name = "slide",
-+ .gpio = -1,
-+ .debounce_rising = 200,
-+ .debounce_falling = 200,
-+ }, {
-+ .name = "kb_lock",
-+ .gpio = -1,
-+ .debounce_rising = 200,
-+ .debounce_falling = 200,
-+ },
-+};
-+
-+static void __init n8x0_gpio_switches_init(void)
-+{
-+ /* The switches are actually registered through ATAG mechanism.
-+ * This just updates the parameters (thus .gpio is -1) */
-+ omap_register_gpio_switches(n8x0_gpio_switches,
-+ ARRAY_SIZE(n8x0_gpio_switches));
-+}
-+
- #define TUSB6010_ASYNC_CS 1
- #define TUSB6010_SYNC_CS 4
- #define TUSB6010_GPIO_INT 58
-@@ -799,6 +948,11 @@ static struct aic3x_pdata n810_aic33_dat
- };
-
- static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
-+ {
-+ I2C_BOARD_INFO("lm8323", 0x45),
-+ .irq = OMAP_GPIO_IRQ(109),
-+ .platform_data = &lm8323_pdata,
-+ },
- {
- I2C_BOARD_INFO("tlv320aic3x", 0x18),
- .platform_data = &n810_aic33_data,
-@@ -856,7 +1010,9 @@ static inline void board_serial_init(voi
- static void __init n8x0_init_machine(void)
- {
- omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
-+ n8x0_gpio_switches_init();
- n8x0_cbus_init();
-+ n8x0_bt_init();
-
- /* FIXME: add n810 spi devices */
- tsc2005_set_config();
+++ /dev/null
-From f0bb9e67f0f13021e5033fed3dfe8ef78fe6a538 Mon Sep 17 00:00:00 2001
-From: Marat Radchenko <marat@slonopotamus.org>
-Date: Tue, 18 Oct 2011 21:52:56 +0400
-Subject: [PATCH 2/2] N800: add TSC2301 board info
-
-This patch adds TSC2301 init logic to N800 board file
----
- arch/arm/mach-omap2/board-n8x0.c | 141 ++++++++++++++++++++++++++++++++++++--
- 1 files changed, 135 insertions(+), 6 deletions(-)
-
---- a/arch/arm/mach-omap2/board-n8x0.c
-+++ b/arch/arm/mach-omap2/board-n8x0.c
-@@ -27,6 +27,7 @@
- #include <linux/spi/tsc2005.h>
- #include <linux/input.h>
- #include <linux/i2c/lm8323.h>
-+#include <linux/spi/tsc2301.h>
-
- #include <asm/mach/arch.h>
- #include <asm/mach-types.h>
-@@ -63,7 +64,75 @@ static struct omap2_mcspi_device_config
- };
- #endif
-
--static void __init tsc2005_set_config(void)
-+#ifdef CONFIG_TOUCHSCREEN_TSC2301
-+
-+#define N800_KEYB_IRQ_GPIO 109
-+
-+static struct tsc2301_platform_data tsc2301_config = {
-+ .reset_gpio = 118,
-+ .keymap = {
-+ -1, /* Event for bit 0 */
-+ KEY_UP, /* Event for bit 1 (up) */
-+ KEY_F5, /* Event for bit 2 (home) */
-+ -1, /* Event for bit 3 */
-+ KEY_LEFT, /* Event for bit 4 (left) */
-+ KEY_ENTER, /* Event for bit 5 (enter) */
-+ KEY_RIGHT, /* Event for bit 6 (right) */
-+ -1, /* Event for bit 7 */
-+ KEY_ESC, /* Event for bit 8 (cycle) */
-+ KEY_DOWN, /* Event for bit 9 (down) */
-+ KEY_F4, /* Event for bit 10 (menu) */
-+ -1, /* Event for bit 11 */
-+ KEY_F8, /* Event for bit 12 (Zoom-) */
-+ KEY_F6, /* Event for bit 13 (FS) */
-+ KEY_F7, /* Event for bit 14 (Zoom+) */
-+ -1, /* Event for bit 15 */
-+ },
-+ .kp_rep = 0,
-+ .keyb_name = "Internal keypad",
-+};
-+
-+static struct omap2_mcspi_device_config tsc2301_mcspi_config = {
-+ .turbo_mode = 0,
-+ .single_channel = 1,
-+};
-+
-+/*
-+ TODO(Marat Radchenko): better pass GPIO to tsc2301 driver and let it
-+ allocate irq itself (as it is already done for touchscreen)
-+ */
-+static void tsc2301_dev_init(void)
-+{
-+ int r;
-+ int gpio = N800_KEYB_IRQ_GPIO;
-+
-+ r = gpio_request(gpio, "tsc2301 KBD IRQ");
-+ if (r >= 0) {
-+ gpio_direction_input(gpio);
-+ tsc2301_config.keyb_int = gpio_to_irq(gpio);
-+ } else {
-+ printk(KERN_ERR "unable to get KBD GPIO");
-+ }
-+
-+ gpio = 103;
-+ r = gpio_request(gpio, "tsc2301 DAV IRQ");
-+ if (r >= 0) {
-+ gpio_direction_input(gpio);
-+ tsc2301_config.dav_int = gpio_to_irq(gpio);
-+ } else {
-+ printk(KERN_ERR "unable to get DAV GPIO");
-+ }
-+}
-+
-+#else
-+
-+static void __init tsc2301_dev_init(void)
-+{
-+}
-+
-+#endif
-+
-+static void __init n8x0_ts_set_config(void)
- {
- const struct omap_lcd_config *conf;
-
-@@ -94,6 +163,37 @@ static void __init tsc2005_set_config(vo
- tsc2005_config.ts_x_plate_ohm = 200;
- }
- #endif
-+
-+#ifdef CONFIG_TOUCHSCREEN_TSC2301
-+ if (strcmp(conf->panel_name, "lph8923") == 0) {
-+ tsc2301_config.ts_x_plate_ohm = 180;
-+ tsc2301_config.ts_hw_avg = 8;
-+ tsc2301_config.ts_max_pressure = 2048;
-+ tsc2301_config.ts_touch_pressure = 400;
-+ tsc2301_config.ts_stab_time = 100;
-+ tsc2301_config.ts_pressure_fudge = 2;
-+ tsc2301_config.ts_x_max = 4096;
-+ tsc2301_config.ts_x_fudge = 4;
-+ tsc2301_config.ts_y_max = 4096;
-+ tsc2301_config.ts_y_fudge = 7;
-+ } else if (strcmp(conf->panel_name, "ls041y3") == 0) {
-+ tsc2301_config.ts_x_plate_ohm = 280;
-+ tsc2301_config.ts_hw_avg = 8;
-+ tsc2301_config.ts_touch_pressure = 400;
-+ tsc2301_config.ts_max_pressure = 2048;
-+ tsc2301_config.ts_stab_time = 1000;
-+ tsc2301_config.ts_pressure_fudge = 2;
-+ tsc2301_config.ts_x_max = 4096;
-+ tsc2301_config.ts_x_fudge = 4;
-+ tsc2301_config.ts_y_max = 4096;
-+ tsc2301_config.ts_y_fudge = 7;
-+ } else {
-+ printk(KERN_ERR "Unknown panel type, set default "
-+ "touchscreen configuration\n");
-+ tsc2301_config.ts_x_plate_ohm = 200;
-+ tsc2301_config.ts_stab_time = 100;
-+ }
-+#endif
- }
- }
-
-@@ -347,13 +447,12 @@ static void __init n8x0_usb_init(void) {
-
- #endif /*CONFIG_USB_MUSB_TUSB6010 */
-
--
- static struct omap2_mcspi_device_config p54spi_mcspi_config = {
- .turbo_mode = 0,
- .single_channel = 1,
- };
-
--static struct spi_board_info n800_spi_board_info[] __initdata = {
-+static struct spi_board_info n8x0_common_spi_board_info[] __initdata = {
- {
- .modalias = "lcd_mipid",
- .bus_num = 1,
-@@ -369,6 +468,10 @@ static struct spi_board_info n800_spi_bo
- .max_speed_hz = 48000000,
- .controller_data = &p54spi_mcspi_config,
- },
-+};
-+
-+static struct spi_board_info n810_spi_board_info[] __initdata = {
-+#ifdef CONFIG_TOUCHSCREEN_TSC2005
- {
- .modalias = "tsc2005",
- .bus_num = 1,
-@@ -378,6 +481,20 @@ static struct spi_board_info n800_spi_bo
- .controller_data = &tsc2005_mcspi_config,
- .platform_data = &tsc2005_config,
- },
-+#endif
-+};
-+
-+static struct spi_board_info n800_spi_board_info[] __initdata = {
-+#if defined(CONFIG_TOUCHSCREEN_TSC2301)
-+ {
-+ .modalias = "tsc2301",
-+ .bus_num = 1,
-+ .chip_select = 0,
-+ .max_speed_hz = 6000000,
-+ .controller_data = &tsc2301_mcspi_config,
-+ .platform_data = &tsc2301_config,
-+ },
-+#endif
- };
-
- #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
-@@ -1015,9 +1132,17 @@ static void __init n8x0_init_machine(voi
- n8x0_bt_init();
-
- /* FIXME: add n810 spi devices */
-- tsc2005_set_config();
-- spi_register_board_info(n800_spi_board_info,
-- ARRAY_SIZE(n800_spi_board_info));
-+ n8x0_ts_set_config();
-+
-+ spi_register_board_info(n8x0_common_spi_board_info,
-+ ARRAY_SIZE(n8x0_common_spi_board_info));
-+ if (machine_is_nokia_n800())
-+ spi_register_board_info(n800_spi_board_info,
-+ ARRAY_SIZE(n800_spi_board_info));
-+ else
-+ spi_register_board_info(n810_spi_board_info,
-+ ARRAY_SIZE(n810_spi_board_info));
-+
- omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1,
- ARRAY_SIZE(n8x0_i2c_board_info_1));
- omap_register_i2c_bus(2, 400, NULL, 0);
-@@ -1027,6 +1152,8 @@ static void __init n8x0_init_machine(voi
- board_serial_init();
- n8x0_mipid_init();
- n8x0_blizzard_init();
-+ if (machine_is_nokia_n800())
-+ tsc2301_dev_init();
- omap_sdrc_init(NULL, NULL);
- gpmc_onenand_init(board_onenand_data);
- n8x0_mmc_init();
+++ /dev/null
----
- arch/arm/mach-omap2/board-n8x0.c | 73 +++++++++++++++++++++++++++++++++++++++
- 1 file changed, 73 insertions(+)
-
---- a/arch/arm/mach-omap2/board-n8x0.c
-+++ b/arch/arm/mach-omap2/board-n8x0.c
-@@ -316,6 +316,77 @@ void __init n8x0_bt_init(void)
- BUG();
- }
-
-+struct gpio_switch_input_dev {
-+ struct input_dev *idev;
-+ unsigned int swcode;
-+};
-+
-+static struct gpio_switch_input_dev *slide_input;
-+static struct gpio_switch_input_dev *kblock_input;
-+
-+static void n8x0_gpio_switch_input_notify(struct gpio_switch_input_dev *gdev,
-+ int state)
-+{
-+ if (gdev) {
-+ input_report_switch(gdev->idev, gdev->swcode, state);
-+ input_sync(gdev->idev);
-+ }
-+}
-+
-+static void n8x0_slide_notify(void *data, int state)
-+{
-+ n8x0_gpio_switch_input_notify(slide_input, state);
-+}
-+
-+static void n8x0_kb_lock_notify(void *data, int state)
-+{
-+ n8x0_gpio_switch_input_notify(kblock_input, state);
-+}
-+
-+static struct gpio_switch_input_dev * __init gpioswitch_input_init(
-+ const char *name,
-+ unsigned int swcode)
-+{
-+ struct gpio_switch_input_dev *gdev;
-+ int err;
-+
-+ gdev = kzalloc(sizeof(*gdev), GFP_KERNEL);
-+ if (!gdev)
-+ goto error;
-+ gdev->swcode = swcode;
-+
-+ gdev->idev = input_allocate_device();
-+ if (!gdev->idev)
-+ goto err_free;
-+
-+ gdev->idev->evbit[0] = BIT_MASK(EV_SW);
-+ gdev->idev->swbit[BIT_WORD(swcode)] = BIT_MASK(swcode);
-+ gdev->idev->name = name;
-+
-+ err = input_register_device(gdev->idev);
-+ if (err)
-+ goto err_free_idev;
-+
-+ return gdev;
-+
-+err_free_idev:
-+ input_free_device(gdev->idev);
-+err_free:
-+ kfree(gdev);
-+error:
-+ return NULL;
-+}
-+
-+static int __init n8x0_gpio_switches_input_init(void)
-+{
-+ slide_input = gpioswitch_input_init("slide", SW_KEYPAD_SLIDE);
-+ kblock_input = gpioswitch_input_init("kb_lock", SW_LID);
-+ if (WARN_ON(!slide_input || !kblock_input))
-+ return -ENODEV;
-+ return 0;
-+}
-+late_initcall(n8x0_gpio_switches_input_init);
-+
- static struct omap_gpio_switch n8x0_gpio_switches[] __initdata = {
- {
- .name = "headphone",
-@@ -337,11 +408,13 @@ static struct omap_gpio_switch n8x0_gpio
- .gpio = -1,
- .debounce_rising = 200,
- .debounce_falling = 200,
-+ .notify = n8x0_slide_notify,
- }, {
- .name = "kb_lock",
- .gpio = -1,
- .debounce_rising = 200,
- .debounce_falling = 200,
-+ .notify = n8x0_kb_lock_notify,
- },
- };
-
+++ /dev/null
----
- drivers/bluetooth/Kconfig | 10
- drivers/bluetooth/Makefile | 1
- drivers/bluetooth/hci_h4p/Makefile | 7
- drivers/bluetooth/hci_h4p/core.c | 1043 ++++++++++++++++++++++++++++++++++++
- drivers/bluetooth/hci_h4p/fw-csr.c | 149 +++++
- drivers/bluetooth/hci_h4p/fw-ti.c | 90 +++
- drivers/bluetooth/hci_h4p/fw.c | 155 +++++
- drivers/bluetooth/hci_h4p/hci_h4p.h | 183 ++++++
- drivers/bluetooth/hci_h4p/sysfs.c | 84 ++
- drivers/bluetooth/hci_h4p/uart.c | 169 +++++
- 10 files changed, 1891 insertions(+)
-
---- /dev/null
-+++ b/drivers/bluetooth/hci_h4p/core.c
-@@ -0,0 +1,1043 @@
-+/*
-+ * This file is part of hci_h4p bluetooth driver
-+ *
-+ * Copyright (C) 2005, 2006 Nokia Corporation.
-+ *
-+ * Contact: Ville Tervo <ville.tervo@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
-+ * 02110-1301 USA
-+ *
-+ */
-+
-+#include <linux/module.h>
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/errno.h>
-+#include <linux/delay.h>
-+#include <linux/spinlock.h>
-+#include <linux/serial_reg.h>
-+#include <linux/skbuff.h>
-+#include <linux/timer.h>
-+#include <linux/device.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/gpio.h>
-+
-+#include <mach/hardware.h>
-+#include <mach/board.h>
-+#include <mach/irqs.h>
-+#include <plat/serial.h>
-+
-+#include <net/bluetooth/bluetooth.h>
-+#include <net/bluetooth/hci_core.h>
-+#include <net/bluetooth/hci.h>
-+
-+#include "hci_h4p.h"
-+
-+#define PM_TIMEOUT 200
-+
-+struct omap_bluetooth_config {
-+ u8 chip_type;
-+ u8 bt_wakeup_gpio;
-+ u8 host_wakeup_gpio;
-+ u8 reset_gpio;
-+ u8 bt_uart;
-+ u8 bd_addr[6];
-+ u8 bt_sysclk;
-+};
-+
-+/* This should be used in function that cannot release clocks */
-+static void hci_h4p_set_clk(struct hci_h4p_info *info, int *clock, int enable)
-+{
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&info->clocks_lock, flags);
-+ if (enable && !*clock) {
-+ NBT_DBG_POWER("Enabling %p\n", clock);
-+ clk_enable(info->uart_fclk);
-+#ifdef CONFIG_ARCH_OMAP2
-+ if (cpu_is_omap24xx()) {
-+ clk_enable(info->uart_iclk);
-+ //omap2_block_sleep();
-+ }
-+#endif
-+ }
-+ if (!enable && *clock) {
-+ NBT_DBG_POWER("Disabling %p\n", clock);
-+ clk_disable(info->uart_fclk);
-+#ifdef CONFIG_ARCH_OMAP2
-+ if (cpu_is_omap24xx()) {
-+ clk_disable(info->uart_iclk);
-+ //omap2_allow_sleep();
-+ }
-+#endif
-+ }
-+
-+ *clock = enable;
-+ spin_unlock_irqrestore(&info->clocks_lock, flags);
-+}
-+
-+/* Power management functions */
-+static void hci_h4p_disable_tx(struct hci_h4p_info *info)
-+{
-+ NBT_DBG_POWER("\n");
-+
-+ if (!info->pm_enabled)
-+ return;
-+
-+ mod_timer(&info->tx_pm_timer, jiffies + msecs_to_jiffies(PM_TIMEOUT));
-+}
-+
-+static void hci_h4p_enable_tx(struct hci_h4p_info *info)
-+{
-+ NBT_DBG_POWER("\n");
-+
-+ if (!info->pm_enabled)
-+ return;
-+
-+ del_timer_sync(&info->tx_pm_timer);
-+ if (info->tx_pm_enabled) {
-+ info->tx_pm_enabled = 0;
-+ hci_h4p_set_clk(info, &info->tx_clocks_en, 1);
-+ gpio_set_value(info->bt_wakeup_gpio, 1);
-+ }
-+}
-+
-+static void hci_h4p_tx_pm_timer(unsigned long data)
-+{
-+ struct hci_h4p_info *info;
-+
-+ NBT_DBG_POWER("\n");
-+
-+ info = (struct hci_h4p_info *)data;
-+
-+ if (hci_h4p_inb(info, UART_LSR) & UART_LSR_TEMT) {
-+ gpio_set_value(info->bt_wakeup_gpio, 0);
-+ hci_h4p_set_clk(info, &info->tx_clocks_en, 0);
-+ info->tx_pm_enabled = 1;
-+ }
-+ else {
-+ mod_timer(&info->tx_pm_timer, jiffies + msecs_to_jiffies(PM_TIMEOUT));
-+ }
-+}
-+
-+static void hci_h4p_disable_rx(struct hci_h4p_info *info)
-+{
-+ if (!info->pm_enabled)
-+ return;
-+
-+ mod_timer(&info->rx_pm_timer, jiffies + msecs_to_jiffies(PM_TIMEOUT));
-+}
-+
-+static void hci_h4p_enable_rx(struct hci_h4p_info *info)
-+{
-+ unsigned long flags;
-+
-+ if (!info->pm_enabled)
-+ return;
-+
-+ del_timer_sync(&info->rx_pm_timer);
-+ spin_lock_irqsave(&info->lock, flags);
-+ if (info->rx_pm_enabled) {
-+ hci_h4p_set_clk(info, &info->rx_clocks_en, 1);
-+ hci_h4p_outb(info, UART_IER, hci_h4p_inb(info, UART_IER) | UART_IER_RDI);
-+ __hci_h4p_set_auto_ctsrts(info, 1, UART_EFR_RTS);
-+ info->rx_pm_enabled = 0;
-+ }
-+ spin_unlock_irqrestore(&info->lock, flags);
-+}
-+
-+static void hci_h4p_rx_pm_timer(unsigned long data)
-+{
-+ unsigned long flags;
-+ struct hci_h4p_info *info = (struct hci_h4p_info *)data;
-+
-+ spin_lock_irqsave(&info->lock, flags);
-+ if (!(hci_h4p_inb(info, UART_LSR) & UART_LSR_DR)) {
-+ __hci_h4p_set_auto_ctsrts(info, 0, UART_EFR_RTS);
-+ hci_h4p_set_rts(info, 0);
-+ hci_h4p_outb(info, UART_IER, hci_h4p_inb(info, UART_IER) & ~UART_IER_RDI);
-+ hci_h4p_set_clk(info, &info->rx_clocks_en, 0);
-+ info->rx_pm_enabled = 1;
-+ }
-+ else {
-+ mod_timer(&info->rx_pm_timer, jiffies + msecs_to_jiffies(PM_TIMEOUT));
-+ }
-+ spin_unlock_irqrestore(&info->lock, flags);
-+}
-+
-+/* Negotiation functions */
-+int hci_h4p_send_alive_packet(struct hci_h4p_info *info)
-+{
-+ NBT_DBG("Sending alive packet\n");
-+
-+ if (!info->alive_cmd_skb)
-+ return -EINVAL;
-+
-+ /* Keep reference to buffer so we can reuse it */
-+ info->alive_cmd_skb = skb_get(info->alive_cmd_skb);
-+
-+ skb_queue_tail(&info->txq, info->alive_cmd_skb);
-+ tasklet_schedule(&info->tx_task);
-+
-+ NBT_DBG("Alive packet sent\n");
-+
-+ return 0;
-+}
-+
-+static void hci_h4p_alive_packet(struct hci_h4p_info *info, struct sk_buff *skb)
-+{
-+ NBT_DBG("Received alive packet\n");
-+ if (skb->data[1] == 0xCC) {
-+ complete(&info->init_completion);
-+ }
-+
-+ kfree_skb(skb);
-+}
-+
-+static int hci_h4p_send_negotiation(struct hci_h4p_info *info, struct sk_buff *skb)
-+{
-+ NBT_DBG("Sending negotiation..\n");
-+
-+ hci_h4p_change_speed(info, INIT_SPEED);
-+
-+ info->init_error = 0;
-+ init_completion(&info->init_completion);
-+ skb_queue_tail(&info->txq, skb);
-+ tasklet_schedule(&info->tx_task);
-+
-+ if (!wait_for_completion_interruptible_timeout(&info->init_completion,
-+ msecs_to_jiffies(1000)))
-+ return -ETIMEDOUT;
-+
-+ NBT_DBG("Negotiation sent\n");
-+ return info->init_error;
-+}
-+
-+static void hci_h4p_negotiation_packet(struct hci_h4p_info *info,
-+ struct sk_buff *skb)
-+{
-+ int err = 0;
-+
-+ if (skb->data[1] == 0x20) {
-+ /* Change to operational settings */
-+ hci_h4p_set_rts(info, 0);
-+
-+ err = hci_h4p_wait_for_cts(info, 0, 100);
-+ if (err < 0)
-+ goto neg_ret;
-+
-+ hci_h4p_change_speed(info, MAX_BAUD_RATE);
-+
-+ err = hci_h4p_wait_for_cts(info, 1, 100);
-+ if (err < 0)
-+ goto neg_ret;
-+
-+ hci_h4p_set_auto_ctsrts(info, 1, UART_EFR_CTS | UART_EFR_RTS);
-+
-+ err = hci_h4p_send_alive_packet(info);
-+ if (err < 0)
-+ goto neg_ret;
-+ } else {
-+ dev_err(info->dev, "Could not negotiate hci_h4p settings\n");
-+ err = -EINVAL;
-+ goto neg_ret;
-+ }
-+
-+ kfree_skb(skb);
-+ return;
-+
-+neg_ret:
-+ info->init_error = err;
-+ complete(&info->init_completion);
-+ kfree_skb(skb);
-+}
-+
-+/* H4 packet handling functions */
-+static int hci_h4p_get_hdr_len(struct hci_h4p_info *info, u8 pkt_type)
-+{
-+ long retval;
-+
-+ switch (pkt_type) {
-+ case H4_EVT_PKT:
-+ retval = HCI_EVENT_HDR_SIZE;
-+ break;
-+ case H4_ACL_PKT:
-+ retval = HCI_ACL_HDR_SIZE;
-+ break;
-+ case H4_SCO_PKT:
-+ retval = HCI_SCO_HDR_SIZE;
-+ break;
-+ case H4_NEG_PKT:
-+ retval = 11;
-+ break;
-+ case H4_ALIVE_PKT:
-+ retval = 3;
-+ break;
-+ default:
-+ dev_err(info->dev, "Unknown H4 packet type 0x%.2x\n", pkt_type);
-+ retval = -1;
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+static unsigned int hci_h4p_get_data_len(struct hci_h4p_info *info,
-+ struct sk_buff *skb)
-+{
-+ long retval = -1;
-+ struct hci_event_hdr *evt_hdr;
-+ struct hci_acl_hdr *acl_hdr;
-+ struct hci_sco_hdr *sco_hdr;
-+
-+ switch (bt_cb(skb)->pkt_type) {
-+ case H4_EVT_PKT:
-+ evt_hdr = (struct hci_event_hdr *)skb->data;
-+ retval = evt_hdr->plen;
-+ break;
-+ case H4_ACL_PKT:
-+ acl_hdr = (struct hci_acl_hdr *)skb->data;
-+ retval = le16_to_cpu(acl_hdr->dlen);
-+ break;
-+ case H4_SCO_PKT:
-+ sco_hdr = (struct hci_sco_hdr *)skb->data;
-+ retval = sco_hdr->dlen;
-+ break;
-+ case H4_NEG_PKT:
-+ retval = 0;
-+ break;
-+ case H4_ALIVE_PKT:
-+ retval = 0;
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+static inline void hci_h4p_recv_frame(struct hci_h4p_info *info,
-+ struct sk_buff *skb)
-+{
-+
-+ if (unlikely(!test_bit(HCI_RUNNING, &info->hdev->flags))) {
-+ NBT_DBG("fw_event\n");
-+ hci_h4p_parse_fw_event(info, skb);
-+ } else {
-+ hci_recv_frame(skb);
-+ NBT_DBG("Frame sent to upper layer\n");
-+ }
-+}
-+
-+static void hci_h4p_rx_tasklet(unsigned long data)
-+{
-+ u8 byte;
-+ unsigned long flags;
-+ struct hci_h4p_info *info = (struct hci_h4p_info *)data;
-+
-+ NBT_DBG("tasklet woke up\n");
-+ NBT_DBG_TRANSFER("rx_tasklet woke up\ndata ");
-+
-+ while (hci_h4p_inb(info, UART_LSR) & UART_LSR_DR) {
-+ byte = hci_h4p_inb(info, UART_RX);
-+ if (info->garbage_bytes) {
-+ info->garbage_bytes--;
-+ continue;
-+ }
-+ if (info->rx_skb == NULL) {
-+ info->rx_skb = bt_skb_alloc(HCI_MAX_FRAME_SIZE, GFP_ATOMIC | GFP_DMA);
-+ if (!info->rx_skb) {
-+ dev_err(info->dev, "Can't allocate memory for new packet\n");
-+ goto finish_task;
-+ }
-+ info->rx_state = WAIT_FOR_PKT_TYPE;
-+ info->rx_skb->dev = (void *)info->hdev;
-+ }
-+ info->hdev->stat.byte_rx++;
-+ NBT_DBG_TRANSFER_NF("0x%.2x ", byte);
-+ switch (info->rx_state) {
-+ case WAIT_FOR_PKT_TYPE:
-+ bt_cb(info->rx_skb)->pkt_type = byte;
-+ info->rx_count = hci_h4p_get_hdr_len(info, byte);
-+ if (info->rx_count < 0) {
-+ info->hdev->stat.err_rx++;
-+ kfree_skb(info->rx_skb);
-+ info->rx_skb = NULL;
-+ } else {
-+ info->rx_state = WAIT_FOR_HEADER;
-+ }
-+ break;
-+ case WAIT_FOR_HEADER:
-+ info->rx_count--;
-+ *skb_put(info->rx_skb, 1) = byte;
-+ if (info->rx_count == 0) {
-+ info->rx_count = hci_h4p_get_data_len(info, info->rx_skb);
-+ if (info->rx_count > skb_tailroom(info->rx_skb)) {
-+ dev_err(info->dev, "Frame is %ld bytes too long.\n",
-+ info->rx_count - skb_tailroom(info->rx_skb));
-+ kfree_skb(info->rx_skb);
-+ info->rx_skb = NULL;
-+ info->garbage_bytes = info->rx_count - skb_tailroom(info->rx_skb);
-+ break;
-+ }
-+ info->rx_state = WAIT_FOR_DATA;
-+
-+ if (bt_cb(info->rx_skb)->pkt_type == H4_NEG_PKT) {
-+ hci_h4p_negotiation_packet(info, info->rx_skb);
-+ info->rx_skb = NULL;
-+ info->rx_state = WAIT_FOR_PKT_TYPE;
-+ goto finish_task;
-+ }
-+ if (bt_cb(info->rx_skb)->pkt_type == H4_ALIVE_PKT) {
-+ hci_h4p_alive_packet(info, info->rx_skb);
-+ info->rx_skb = NULL;
-+ info->rx_state = WAIT_FOR_PKT_TYPE;
-+ goto finish_task;
-+ }
-+ }
-+ break;
-+ case WAIT_FOR_DATA:
-+ info->rx_count--;
-+ *skb_put(info->rx_skb, 1) = byte;
-+ if (info->rx_count == 0) {
-+ /* H4+ devices should allways send word aligned packets */
-+ if (!(info->rx_skb->len % 2)) {
-+ info->garbage_bytes++;
-+ }
-+ hci_h4p_recv_frame(info, info->rx_skb);
-+ info->rx_skb = NULL;
-+ }
-+ break;
-+ default:
-+ WARN_ON(1);
-+ break;
-+ }
-+ }
-+
-+finish_task:
-+ spin_lock_irqsave(&info->lock, flags);
-+ hci_h4p_outb(info, UART_IER, hci_h4p_inb(info, UART_IER) | UART_IER_RDI);
-+ spin_unlock_irqrestore(&info->lock, flags);
-+
-+ NBT_DBG_TRANSFER_NF("\n");
-+ NBT_DBG("rx_ended\n");
-+}
-+
-+static void hci_h4p_tx_tasklet(unsigned long data)
-+{
-+ unsigned int sent = 0;
-+ unsigned long flags;
-+ struct sk_buff *skb;
-+ struct hci_h4p_info *info = (struct hci_h4p_info *)data;
-+
-+ NBT_DBG("tasklet woke up\n");
-+ NBT_DBG_TRANSFER("tx_tasklet woke up\n data ");
-+
-+ skb = skb_dequeue(&info->txq);
-+ if (!skb) {
-+ /* No data in buffer */
-+ NBT_DBG("skb ready\n");
-+ hci_h4p_disable_tx(info);
-+ return;
-+ }
-+
-+ /* Copy data to tx fifo */
-+ while (!(hci_h4p_inb(info, UART_OMAP_SSR) & UART_OMAP_SSR_TXFULL) &&
-+ (sent < skb->len)) {
-+ NBT_DBG_TRANSFER_NF("0x%.2x ", skb->data[sent]);
-+ hci_h4p_outb(info, UART_TX, skb->data[sent]);
-+ sent++;
-+ }
-+
-+ info->hdev->stat.byte_tx += sent;
-+ NBT_DBG_TRANSFER_NF("\n");
-+ if (skb->len == sent) {
-+ kfree_skb(skb);
-+ } else {
-+ skb_pull(skb, sent);
-+ skb_queue_head(&info->txq, skb);
-+ }
-+
-+ spin_lock_irqsave(&info->lock, flags);
-+ hci_h4p_outb(info, UART_IER, hci_h4p_inb(info, UART_IER) | UART_IER_THRI);
-+ spin_unlock_irqrestore(&info->lock, flags);
-+}
-+
-+static irqreturn_t hci_h4p_interrupt(int irq, void *data)
-+{
-+ struct hci_h4p_info *info = (struct hci_h4p_info *)data;
-+ u8 iir, msr;
-+ int ret;
-+ unsigned long flags;
-+
-+ ret = IRQ_NONE;
-+
-+ iir = hci_h4p_inb(info, UART_IIR);
-+ if (iir & UART_IIR_NO_INT) {
-+ dev_err(info->dev, "Interrupt but no reason irq 0x%.2x\n", iir);
-+ return IRQ_HANDLED;
-+ }
-+
-+ NBT_DBG("In interrupt handler iir 0x%.2x\n", iir);
-+
-+ iir &= UART_IIR_ID;
-+
-+ if (iir == UART_IIR_MSI) {
-+ msr = hci_h4p_inb(info, UART_MSR);
-+ ret = IRQ_HANDLED;
-+ }
-+ if (iir == UART_IIR_RLSI) {
-+ hci_h4p_inb(info, UART_RX);
-+ hci_h4p_inb(info, UART_LSR);
-+ ret = IRQ_HANDLED;
-+ }
-+
-+ if (iir == UART_IIR_RDI) {
-+ spin_lock_irqsave(&info->lock, flags);
-+ hci_h4p_outb(info, UART_IER, hci_h4p_inb(info, UART_IER) & ~UART_IER_RDI);
-+ spin_unlock_irqrestore(&info->lock, flags);
-+ tasklet_schedule(&info->rx_task);
-+ ret = IRQ_HANDLED;
-+ }
-+
-+ if (iir == UART_IIR_THRI) {
-+ spin_lock_irqsave(&info->lock, flags);
-+ hci_h4p_outb(info, UART_IER, hci_h4p_inb(info, UART_IER) & ~UART_IER_THRI);
-+ spin_unlock_irqrestore(&info->lock, flags);
-+ tasklet_schedule(&info->tx_task);
-+ ret = IRQ_HANDLED;
-+ }
-+
-+ return ret;
-+}
-+
-+static irqreturn_t hci_h4p_wakeup_interrupt(int irq, void *dev_inst)
-+{
-+ struct hci_h4p_info *info = dev_inst;
-+ int should_wakeup;
-+ struct hci_dev *hdev;
-+
-+ if (!info->hdev)
-+ return IRQ_HANDLED;
-+
-+ hdev = info->hdev;
-+
-+ if (!test_bit(HCI_RUNNING, &hdev->flags))
-+ return IRQ_HANDLED;
-+
-+ should_wakeup = gpio_get_value(info->host_wakeup_gpio);
-+ NBT_DBG_POWER("gpio interrupt %d\n", should_wakeup);
-+ if (should_wakeup) {
-+ hci_h4p_enable_rx(info);
-+ } else {
-+ hci_h4p_disable_rx(info);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int hci_h4p_reset(struct hci_h4p_info *info)
-+{
-+ int err;
-+
-+ hci_h4p_init_uart(info);
-+ hci_h4p_set_rts(info, 0);
-+
-+ gpio_set_value(info->reset_gpio, 0);
-+ msleep(100);
-+ gpio_set_value(info->bt_wakeup_gpio, 1);
-+ gpio_set_value(info->reset_gpio, 1);
-+ msleep(100);
-+
-+ err = hci_h4p_wait_for_cts(info, 1, 10);
-+ if (err < 0) {
-+ dev_err(info->dev, "No cts from bt chip\n");
-+ return err;
-+ }
-+
-+ hci_h4p_set_rts(info, 1);
-+
-+ return 0;
-+}
-+
-+/* hci callback functions */
-+static int hci_h4p_hci_flush(struct hci_dev *hdev)
-+{
-+ struct hci_h4p_info *info;
-+ info = hdev->driver_data;
-+
-+ skb_queue_purge(&info->txq);
-+
-+ return 0;
-+}
-+
-+static int hci_h4p_hci_open(struct hci_dev *hdev)
-+{
-+ struct hci_h4p_info *info;
-+ int err;
-+ struct sk_buff *neg_cmd_skb;
-+ struct sk_buff_head fw_queue;
-+
-+ info = hdev->driver_data;
-+
-+ if (test_bit(HCI_RUNNING, &hdev->flags))
-+ return 0;
-+
-+ skb_queue_head_init(&fw_queue);
-+ err = hci_h4p_read_fw(info, &fw_queue);
-+ if (err < 0) {
-+ dev_err(info->dev, "Cannot read firmware\n");
-+ return err;
-+ }
-+ neg_cmd_skb = skb_dequeue(&fw_queue);
-+ if (!neg_cmd_skb) {
-+ err = -EPROTO;
-+ goto err_clean;
-+ }
-+ info->alive_cmd_skb = skb_dequeue(&fw_queue);
-+ if (!info->alive_cmd_skb) {
-+ err = -EPROTO;
-+ goto err_clean;
-+ }
-+
-+ hci_h4p_set_clk(info, &info->tx_clocks_en, 1);
-+ hci_h4p_set_clk(info, &info->rx_clocks_en, 1);
-+
-+ tasklet_enable(&info->tx_task);
-+ tasklet_enable(&info->rx_task);
-+ info->rx_state = WAIT_FOR_PKT_TYPE;
-+ info->rx_count = 0;
-+ info->garbage_bytes = 0;
-+ info->rx_skb = NULL;
-+ info->pm_enabled = 0;
-+ init_completion(&info->fw_completion);
-+
-+ err = hci_h4p_reset(info);
-+ if (err < 0)
-+ goto err_clean;
-+
-+ err = hci_h4p_send_negotiation(info, neg_cmd_skb);
-+ neg_cmd_skb = NULL;
-+ if (err < 0)
-+ goto err_clean;
-+
-+ err = hci_h4p_send_fw(info, &fw_queue);
-+ if (err < 0) {
-+ dev_err(info->dev, "Sending firmware failed.\n");
-+ goto err_clean;
-+ }
-+
-+ kfree_skb(info->alive_cmd_skb);
-+ info->alive_cmd_skb = NULL;
-+ info->pm_enabled = 1;
-+ info->tx_pm_enabled = 1;
-+ info->rx_pm_enabled = 0;
-+ set_bit(HCI_RUNNING, &hdev->flags);
-+
-+ NBT_DBG("hci up and running\n");
-+ return 0;
-+
-+err_clean:
-+ hci_h4p_hci_flush(hdev);
-+ tasklet_disable(&info->tx_task);
-+ tasklet_disable(&info->rx_task);
-+ hci_h4p_reset_uart(info);
-+ hci_h4p_set_clk(info, &info->tx_clocks_en, 0);
-+ hci_h4p_set_clk(info, &info->rx_clocks_en, 0);
-+ gpio_set_value(info->reset_gpio, 0);
-+ gpio_set_value(info->bt_wakeup_gpio, 0);
-+ skb_queue_purge(&fw_queue);
-+ kfree_skb(neg_cmd_skb);
-+ neg_cmd_skb = NULL;
-+ kfree_skb(info->alive_cmd_skb);
-+ info->alive_cmd_skb = NULL;
-+ kfree_skb(info->rx_skb);
-+
-+ return err;
-+}
-+
-+static int hci_h4p_hci_close(struct hci_dev *hdev)
-+{
-+ struct hci_h4p_info *info = hdev->driver_data;
-+
-+ if (!test_and_clear_bit(HCI_RUNNING, &hdev->flags))
-+ return 0;
-+
-+ hci_h4p_hci_flush(hdev);
-+ del_timer_sync(&info->tx_pm_timer);
-+ del_timer_sync(&info->rx_pm_timer);
-+ tasklet_disable(&info->tx_task);
-+ tasklet_disable(&info->rx_task);
-+ hci_h4p_set_clk(info, &info->tx_clocks_en, 1);
-+ hci_h4p_set_clk(info, &info->rx_clocks_en, 1);
-+ hci_h4p_reset_uart(info);
-+ hci_h4p_set_clk(info, &info->tx_clocks_en, 0);
-+ hci_h4p_set_clk(info, &info->rx_clocks_en, 0);
-+ gpio_set_value(info->reset_gpio, 0);
-+ gpio_set_value(info->bt_wakeup_gpio, 0);
-+ kfree_skb(info->rx_skb);
-+
-+ return 0;
-+}
-+
-+static void hci_h4p_hci_destruct(struct hci_dev *hdev)
-+{
-+}
-+
-+static int hci_h4p_hci_send_frame(struct sk_buff *skb)
-+{
-+ struct hci_h4p_info *info;
-+ struct hci_dev *hdev = (struct hci_dev *)skb->dev;
-+ int err = 0;
-+
-+ if (!hdev) {
-+ printk(KERN_WARNING "hci_h4p: Frame for unknown device\n");
-+ return -ENODEV;
-+ }
-+
-+ NBT_DBG("dev %p, skb %p\n", hdev, skb);
-+
-+ info = hdev->driver_data;
-+
-+ if (!test_bit(HCI_RUNNING, &hdev->flags)) {
-+ dev_warn(info->dev, "Frame for non-running device\n");
-+ return -EIO;
-+ }
-+
-+ switch (bt_cb(skb)->pkt_type) {
-+ case HCI_COMMAND_PKT:
-+ hdev->stat.cmd_tx++;
-+ break;
-+ case HCI_ACLDATA_PKT:
-+ hdev->stat.acl_tx++;
-+ break;
-+ case HCI_SCODATA_PKT:
-+ hdev->stat.sco_tx++;
-+ break;
-+ }
-+
-+ /* Push frame type to skb */
-+ *skb_push(skb, 1) = (bt_cb(skb)->pkt_type);
-+ /* We should allways send word aligned data to h4+ devices */
-+ if (skb->len % 2) {
-+ err = skb_pad(skb, 1);
-+ }
-+ if (err)
-+ return err;
-+
-+ hci_h4p_enable_tx(info);
-+ skb_queue_tail(&info->txq, skb);
-+ tasklet_schedule(&info->tx_task);
-+
-+ return 0;
-+}
-+
-+static int hci_h4p_hci_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long arg)
-+{
-+ return -ENOIOCTLCMD;
-+}
-+
-+static int hci_h4p_register_hdev(struct hci_h4p_info *info)
-+{
-+ struct hci_dev *hdev;
-+
-+ /* Initialize and register HCI device */
-+
-+ hdev = hci_alloc_dev();
-+ if (!hdev) {
-+ dev_err(info->dev, "Can't allocate memory for device\n");
-+ return -ENOMEM;
-+ }
-+ info->hdev = hdev;
-+
-+ hdev->dev_type = HCI_UART;
-+ hdev->driver_data = info;
-+
-+ hdev->open = hci_h4p_hci_open;
-+ hdev->close = hci_h4p_hci_close;
-+ hdev->flush = hci_h4p_hci_flush;
-+ hdev->send = hci_h4p_hci_send_frame;
-+ hdev->destruct = hci_h4p_hci_destruct;
-+ hdev->ioctl = hci_h4p_hci_ioctl;
-+
-+ hdev->owner = THIS_MODULE;
-+
-+ if (hci_register_dev(hdev) < 0) {
-+ dev_err(info->dev, "hci_h4p: Can't register HCI device %s.\n", hdev->name);
-+ return -ENODEV;
-+ }
-+
-+ return 0;
-+}
-+
-+static int hci_h4p_probe(struct platform_device *pdev)
-+{
-+ struct omap_bluetooth_config *bt_config;
-+ struct hci_h4p_info *info;
-+ int irq, err;
-+
-+ dev_info(&pdev->dev, "Registering HCI H4P device\n");
-+ info = kzalloc(sizeof(struct hci_h4p_info), GFP_KERNEL);
-+ if (!info)
-+ return -ENOMEM;
-+
-+ info->dev = &pdev->dev;
-+ info->pm_enabled = 0;
-+ info->tx_pm_enabled = 0;
-+ info->rx_pm_enabled = 0;
-+ info->garbage_bytes = 0;
-+ info->tx_clocks_en = 0;
-+ info->rx_clocks_en = 0;
-+ tasklet_init(&info->tx_task, hci_h4p_tx_tasklet, (unsigned long)info);
-+ tasklet_init(&info->rx_task, hci_h4p_rx_tasklet, (unsigned long)info);
-+ /* hci_h4p_hci_open assumes that tasklet is disabled in startup */
-+ tasklet_disable(&info->tx_task);
-+ tasklet_disable(&info->rx_task);
-+ spin_lock_init(&info->lock);
-+ spin_lock_init(&info->clocks_lock);
-+ skb_queue_head_init(&info->txq);
-+ init_timer(&info->tx_pm_timer);
-+ info->tx_pm_timer.function = hci_h4p_tx_pm_timer;
-+ info->tx_pm_timer.data = (unsigned long)info;
-+ init_timer(&info->rx_pm_timer);
-+ info->rx_pm_timer.function = hci_h4p_rx_pm_timer;
-+ info->rx_pm_timer.data = (unsigned long)info;
-+
-+ if (pdev->dev.platform_data == NULL) {
-+ dev_err(&pdev->dev, "Could not get Bluetooth config data\n");
-+ return -ENODATA;
-+ }
-+
-+ bt_config = pdev->dev.platform_data;
-+ info->chip_type = bt_config->chip_type;
-+ info->bt_wakeup_gpio = bt_config->bt_wakeup_gpio;
-+ info->host_wakeup_gpio = bt_config->host_wakeup_gpio;
-+ info->reset_gpio = bt_config->reset_gpio;
-+ info->bt_sysclk = bt_config->bt_sysclk;
-+
-+ NBT_DBG("RESET gpio: %d\n", info->reset_gpio);
-+ NBT_DBG("BTWU gpio: %d\n", info->bt_wakeup_gpio);
-+ NBT_DBG("HOSTWU gpio: %d\n", info->host_wakeup_gpio);
-+ NBT_DBG("Uart: %d\n", bt_config->bt_uart);
-+ NBT_DBG("sysclk: %d\n", info->bt_sysclk);
-+
-+ err = gpio_request(info->reset_gpio, "BT reset");
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "Cannot get GPIO line %d\n",
-+ info->reset_gpio);
-+ kfree(info);
-+ goto cleanup;
-+ }
-+
-+ err = gpio_request(info->bt_wakeup_gpio, "BT wakeup");
-+ if (err < 0)
-+ {
-+ dev_err(info->dev, "Cannot get GPIO line 0x%d",
-+ info->bt_wakeup_gpio);
-+ gpio_free(info->reset_gpio);
-+ kfree(info);
-+ goto cleanup;
-+ }
-+
-+ err = gpio_request(info->host_wakeup_gpio, "BT host wakeup");
-+ if (err < 0)
-+ {
-+ dev_err(info->dev, "Cannot get GPIO line %d",
-+ info->host_wakeup_gpio);
-+ gpio_free(info->reset_gpio);
-+ gpio_free(info->bt_wakeup_gpio);
-+ kfree(info);
-+ goto cleanup;
-+ }
-+
-+ gpio_direction_output(info->reset_gpio, 0);
-+ gpio_direction_output(info->bt_wakeup_gpio, 0);
-+ gpio_direction_input(info->host_wakeup_gpio);
-+
-+//FIXME
-+#if defined(CONFIG_ARCH_OMAP1)
-+# define OMAP_UART1_BASE OMAP1_UART1_BASE
-+# define OMAP_UART2_BASE OMAP1_UART2_BASE
-+# define OMAP_UART3_BASE OMAP1_UART3_BASE
-+#elif defined(CONFIG_ARCH_OMAP2)
-+# define OMAP_UART1_BASE OMAP2_UART1_BASE
-+# define OMAP_UART2_BASE OMAP2_UART2_BASE
-+# define OMAP_UART3_BASE OMAP2_UART3_BASE
-+#elif defined(CONFIG_ARCH_OMAP3)
-+# define OMAP_UART1_BASE OMAP3_UART1_BASE
-+# define OMAP_UART2_BASE OMAP3_UART2_BASE
-+# define OMAP_UART3_BASE OMAP3_UART3_BASE
-+#elif defined(CONFIG_ARCH_OMAP4)
-+# define OMAP_UART1_BASE OMAP4_UART1_BASE
-+# define OMAP_UART2_BASE OMAP4_UART2_BASE
-+# define OMAP_UART3_BASE OMAP4_UART3_BASE
-+#else
-+# error
-+#endif
-+ switch (bt_config->bt_uart) {
-+ case 1:
-+ if (cpu_is_omap16xx()) {
-+ irq = INT_UART1;
-+ info->uart_fclk = clk_get(NULL, "uart1_ck");
-+ } else if (cpu_is_omap24xx()) {
-+ irq = INT_24XX_UART1_IRQ;
-+ info->uart_iclk = clk_get(NULL, "uart1_ick");
-+ info->uart_fclk = clk_get(NULL, "uart1_fck");
-+ }
-+ /* FIXME: Use platform_get_resource for the port */
-+ info->uart_base = ioremap(OMAP_UART1_BASE, 0x16);
-+ if (!info->uart_base)
-+ goto cleanup;
-+ break;
-+ case 2:
-+ if (cpu_is_omap16xx()) {
-+ irq = INT_UART2;
-+ info->uart_fclk = clk_get(NULL, "uart2_ck");
-+ } else {
-+ irq = INT_24XX_UART2_IRQ;
-+ info->uart_iclk = clk_get(NULL, "uart2_ick");
-+ info->uart_fclk = clk_get(NULL, "uart2_fck");
-+ }
-+ /* FIXME: Use platform_get_resource for the port */
-+ info->uart_base = ioremap(OMAP_UART2_BASE, 0x16);
-+ if (!info->uart_base)
-+ goto cleanup;
-+ break;
-+ case 3:
-+ if (cpu_is_omap16xx()) {
-+ irq = INT_UART3;
-+ info->uart_fclk = clk_get(NULL, "uart3_ck");
-+ } else {
-+ irq = INT_24XX_UART3_IRQ;
-+ info->uart_iclk = clk_get(NULL, "uart3_ick");
-+ info->uart_fclk = clk_get(NULL, "uart3_fck");
-+ }
-+ /* FIXME: Use platform_get_resource for the port */
-+ info->uart_base = ioremap(OMAP_UART3_BASE, 0x16);
-+ if (!info->uart_base)
-+ goto cleanup;
-+ break;
-+ default:
-+ dev_err(info->dev, "No uart defined\n");
-+ goto cleanup;
-+ }
-+
-+ info->irq = irq;
-+ err = request_irq(irq, hci_h4p_interrupt, 0, "hci_h4p", (void *)info);
-+ if (err < 0) {
-+ dev_err(info->dev, "hci_h4p: unable to get IRQ %d\n", irq);
-+ goto cleanup;
-+ }
-+
-+ err = request_irq(gpio_to_irq(info->host_wakeup_gpio),
-+ hci_h4p_wakeup_interrupt,
-+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
-+ "hci_h4p_wkup", (void *)info);
-+ if (err < 0) {
-+ dev_err(info->dev, "hci_h4p: unable to get wakeup IRQ %d\n",
-+ gpio_to_irq(info->host_wakeup_gpio));
-+ free_irq(irq, (void *)info);
-+ goto cleanup;
-+ }
-+
-+ hci_h4p_set_clk(info, &info->tx_clocks_en, 1);
-+ hci_h4p_set_auto_ctsrts(info, 0, UART_EFR_CTS | UART_EFR_RTS);
-+ err = hci_h4p_init_uart(info);
-+ if (err < 0)
-+ goto cleanup_irq;
-+ err = hci_h4p_reset(info);
-+ if (err < 0)
-+ goto cleanup_irq;
-+ err = hci_h4p_wait_for_cts(info, 1, 10);
-+ if (err < 0)
-+ goto cleanup_irq;
-+ hci_h4p_set_clk(info, &info->tx_clocks_en, 0);
-+
-+ platform_set_drvdata(pdev, info);
-+ err = hci_h4p_sysfs_create_files(info->dev);
-+ if (err < 0)
-+ goto cleanup_irq;
-+
-+ if (hci_h4p_register_hdev(info) < 0) {
-+ dev_err(info->dev, "failed to register hci_h4p hci device\n");
-+ goto cleanup_irq;
-+ }
-+ gpio_set_value(info->reset_gpio, 0);
-+
-+ return 0;
-+
-+cleanup_irq:
-+ free_irq(irq, (void *)info);
-+ free_irq(gpio_to_irq(info->host_wakeup_gpio), (void *)info);
-+cleanup:
-+ gpio_set_value(info->reset_gpio, 0);
-+ gpio_free(info->reset_gpio);
-+ gpio_free(info->bt_wakeup_gpio);
-+ gpio_free(info->host_wakeup_gpio);
-+ kfree(info);
-+
-+ return err;
-+
-+}
-+
-+static int hci_h4p_remove(struct platform_device *dev)
-+{
-+ struct hci_h4p_info *info;
-+
-+ info = platform_get_drvdata(dev);
-+
-+ hci_h4p_hci_close(info->hdev);
-+ free_irq(gpio_to_irq(info->host_wakeup_gpio), (void *) info);
-+ hci_free_dev(info->hdev);
-+ gpio_free(info->reset_gpio);
-+ gpio_free(info->bt_wakeup_gpio);
-+ gpio_free(info->host_wakeup_gpio);
-+ free_irq(info->irq, (void *) info);
-+ kfree(info);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver hci_h4p_driver = {
-+ .probe = hci_h4p_probe,
-+ .remove = hci_h4p_remove,
-+ .driver = {
-+ .name = "hci_h4p",
-+ },
-+};
-+
-+static int __init hci_h4p_init(void)
-+{
-+ int err = 0;
-+
-+ /* Register the driver with LDM */
-+ err = platform_driver_register(&hci_h4p_driver);
-+ if (err < 0)
-+ printk(KERN_WARNING "failed to register hci_h4p driver\n");
-+
-+ return err;
-+}
-+
-+static void __exit hci_h4p_exit(void)
-+{
-+ platform_driver_unregister(&hci_h4p_driver);
-+}
-+
-+module_init(hci_h4p_init);
-+module_exit(hci_h4p_exit);
-+
-+MODULE_DESCRIPTION("h4 driver with nokia extensions");
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Ville Tervo");
---- /dev/null
-+++ b/drivers/bluetooth/hci_h4p/fw.c
-@@ -0,0 +1,155 @@
-+/*
-+ * This file is part of hci_h4p bluetooth driver
-+ *
-+ * Copyright (C) 2005, 2006 Nokia Corporation.
-+ *
-+ * Contact: Ville Tervo <ville.tervo@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
-+ * 02110-1301 USA
-+ *
-+ */
-+
-+#include <linux/skbuff.h>
-+#include <linux/firmware.h>
-+#include <linux/clk.h>
-+
-+#include <net/bluetooth/bluetooth.h>
-+
-+#include "hci_h4p.h"
-+
-+#define BT_CHIP_TI 2
-+#define BT_CHIP_CSR 1
-+
-+static int fw_pos;
-+
-+/* Firmware handling */
-+static int hci_h4p_open_firmware(struct hci_h4p_info *info,
-+ const struct firmware **fw_entry)
-+{
-+ int err;
-+
-+ fw_pos = 0;
-+ NBT_DBG_FW("Opening %d firmware\n", info->chip_type);
-+ switch (info->chip_type) {
-+ case BT_CHIP_TI:
-+ err = request_firmware(fw_entry, "brf6150fw.bin", info->dev);
-+ break;
-+ case BT_CHIP_CSR:
-+ err = request_firmware(fw_entry, "bc4fw.bin", info->dev);
-+ break;
-+ default:
-+ dev_err(info->dev, "Invalid chip type\n");
-+ *fw_entry = NULL;
-+ err = -EINVAL;
-+ }
-+
-+ return err;
-+}
-+
-+static void hci_h4p_close_firmware(const struct firmware *fw_entry)
-+{
-+ release_firmware(fw_entry);
-+}
-+
-+/* Read fw. Return length of the command. If no more commands in
-+ * fw 0 is returned. In error case return value is negative.
-+ */
-+static int hci_h4p_read_fw_cmd(struct hci_h4p_info *info, struct sk_buff **skb,
-+ const struct firmware *fw_entry, int how)
-+{
-+ unsigned int cmd_len;
-+
-+ if (fw_pos >= fw_entry->size) {
-+ return 0;
-+ }
-+
-+ cmd_len = fw_entry->data[fw_pos++];
-+ if (!cmd_len)
-+ return 0;
-+
-+ if (fw_pos + cmd_len > fw_entry->size) {
-+ dev_err(info->dev, "Corrupted firmware image\n");
-+ return -EMSGSIZE;
-+ }
-+
-+ *skb = bt_skb_alloc(cmd_len, how);
-+ if (!*skb) {
-+ dev_err(info->dev, "Cannot reserve memory for buffer\n");
-+ return -ENOMEM;
-+ }
-+ memcpy(skb_put(*skb, cmd_len), &fw_entry->data[fw_pos], cmd_len);
-+
-+ fw_pos += cmd_len;
-+
-+ return (*skb)->len;
-+}
-+
-+int hci_h4p_read_fw(struct hci_h4p_info *info, struct sk_buff_head *fw_queue)
-+{
-+ const struct firmware *fw_entry = NULL;
-+ struct sk_buff *skb = NULL;
-+ int err;
-+
-+ err = hci_h4p_open_firmware(info, &fw_entry);
-+ if (err < 0 || !fw_entry)
-+ goto err_clean;
-+
-+ while ((err = hci_h4p_read_fw_cmd(info, &skb, fw_entry, GFP_KERNEL))) {
-+ if (err < 0 || !skb)
-+ goto err_clean;
-+
-+ skb_queue_tail(fw_queue, skb);
-+ }
-+
-+err_clean:
-+ hci_h4p_close_firmware(fw_entry);
-+ return err;
-+}
-+
-+int hci_h4p_send_fw(struct hci_h4p_info *info, struct sk_buff_head *fw_queue)
-+{
-+ int err;
-+
-+ switch(info->chip_type) {
-+ case BT_CHIP_CSR:
-+ err = hci_h4p_bc4_send_fw(info, fw_queue);
-+ break;
-+ case BT_CHIP_TI:
-+ err = hci_h4p_brf6150_send_fw(info, fw_queue);
-+ break;
-+ default:
-+ dev_err(info->dev, "Don't know how to send firmware\n");
-+ err = -EINVAL;
-+ }
-+
-+ return err;
-+}
-+
-+void hci_h4p_parse_fw_event(struct hci_h4p_info *info, struct sk_buff *skb)
-+{
-+ switch (info->chip_type) {
-+ case BT_CHIP_CSR:
-+ hci_h4p_bc4_parse_fw_event(info, skb);
-+ break;
-+ case BT_CHIP_TI:
-+ hci_h4p_brf6150_parse_fw_event(info, skb);
-+ break;
-+ default:
-+ dev_err(info->dev, "Don't know how to parse fw event\n");
-+ info->fw_error = -EINVAL;
-+ }
-+
-+ return;
-+}
---- /dev/null
-+++ b/drivers/bluetooth/hci_h4p/fw-csr.c
-@@ -0,0 +1,149 @@
-+/*
-+ * This file is part of hci_h4p bluetooth driver
-+ *
-+ * Copyright (C) 2005, 2006 Nokia Corporation.
-+ *
-+ * Contact: Ville Tervo <ville.tervo@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
-+ * 02110-1301 USA
-+ *
-+ */
-+
-+#include <linux/skbuff.h>
-+#include <linux/delay.h>
-+#include <linux/serial_reg.h>
-+
-+#include "hci_h4p.h"
-+
-+void hci_h4p_bc4_parse_fw_event(struct hci_h4p_info *info, struct sk_buff *skb)
-+{
-+ /* Check if this is fw packet */
-+ if (skb->data[0] != 0xff) {
-+ hci_recv_frame(skb);
-+ return;
-+ }
-+
-+ if (skb->data[11] || skb->data[12]) {
-+ dev_err(info->dev, "Firmware sending command failed\n");
-+ info->fw_error = -EPROTO;
-+ }
-+
-+ kfree_skb(skb);
-+ complete(&info->fw_completion);
-+}
-+
-+int hci_h4p_bc4_send_fw(struct hci_h4p_info *info,
-+ struct sk_buff_head *fw_queue)
-+{
-+ struct sk_buff *skb;
-+ unsigned int offset;
-+ int retries, count, i;
-+
-+ info->fw_error = 0;
-+
-+ NBT_DBG_FW("Sending firmware\n");
-+ skb = skb_dequeue(fw_queue);
-+
-+ if (!skb)
-+ return -ENOMSG;
-+
-+ info->bdaddr[0] = 0x00;
-+ info->bdaddr[1] = 0x1D;
-+ info->bdaddr[2] = 0x6E;
-+ info->bdaddr[3] = 0xD4;
-+ info->bdaddr[4] = 0xF0;
-+ info->bdaddr[5] = 0x37;
-+
-+ /* Check if this is bd_address packet */
-+ if (skb->data[15] == 0x01 && skb->data[16] == 0x00) {
-+ dev_info(info->dev, "bd_address packet found\n");
-+ offset = 21;
-+ skb->data[offset + 1] = 0x00;
-+ skb->data[offset + 5] = 0x00;
-+ skb->data[offset + 7] = info->bdaddr[0];
-+ skb->data[offset + 6] = info->bdaddr[1];
-+ skb->data[offset + 4] = info->bdaddr[2];
-+ skb->data[offset + 0] = info->bdaddr[3];
-+ skb->data[offset + 3] = info->bdaddr[4];
-+ skb->data[offset + 2] = info->bdaddr[5];
-+ }
-+
-+ for (i = 0; i < 6; i++) {
-+ if (info->bdaddr[i] != 0x00)
-+ break;
-+ }
-+
-+ /* if (i > 5) {
-+ dev_info(info->dev, "Valid bluetooth address not found.\n");
-+ kfree_skb(skb);
-+ return -ENODEV;
-+ } */
-+
-+ for (count = 1; ; count++) {
-+ NBT_DBG_FW("Sending firmware command %d\n", count);
-+ init_completion(&info->fw_completion);
-+ skb_queue_tail(&info->txq, skb);
-+ tasklet_schedule(&info->tx_task);
-+
-+ skb = skb_dequeue(fw_queue);
-+ if (!skb)
-+ break;
-+
-+ if (!wait_for_completion_timeout(&info->fw_completion,
-+ msecs_to_jiffies(1000))) {
-+ dev_err(info->dev, "No reply to fw command\n");
-+ return -ETIMEDOUT;
-+ }
-+
-+ if (info->fw_error) {
-+ dev_err(info->dev, "FW error\n");
-+ return -EPROTO;
-+ }
-+ };
-+
-+ /* Wait for chip warm reset */
-+ retries = 100;
-+ while ((!skb_queue_empty(&info->txq) ||
-+ !(hci_h4p_inb(info, UART_LSR) & UART_LSR_TEMT)) &&
-+ retries--) {
-+ msleep(10);
-+ }
-+ if (!retries) {
-+ dev_err(info->dev, "Transmitter not empty\n");
-+ return -ETIMEDOUT;
-+ }
-+
-+ hci_h4p_change_speed(info, BC4_MAX_BAUD_RATE);
-+
-+ if (hci_h4p_wait_for_cts(info, 1, 100)) {
-+ dev_err(info->dev, "cts didn't go down after final speed change\n");
-+ return -ETIMEDOUT;
-+ }
-+
-+ retries = 100;
-+ do {
-+ init_completion(&info->init_completion);
-+ hci_h4p_send_alive_packet(info);
-+ retries--;
-+ } while (!wait_for_completion_timeout(&info->init_completion, 100) &&
-+ retries > 0);
-+
-+ if (!retries) {
-+ dev_err(info->dev, "No alive reply after speed change\n");
-+ return -ETIMEDOUT;
-+ }
-+
-+ return 0;
-+}
---- /dev/null
-+++ b/drivers/bluetooth/hci_h4p/fw-ti.c
-@@ -0,0 +1,90 @@
-+/*
-+ * This file is part of hci_h4p bluetooth driver
-+ *
-+ * Copyright (C) 2005, 2006 Nokia Corporation.
-+ *
-+ * Contact: Ville Tervo <ville.tervo@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
-+ * 02110-1301 USA
-+ *
-+ */
-+
-+#include <linux/skbuff.h>
-+
-+#include "hci_h4p.h"
-+
-+void hci_h4p_brf6150_parse_fw_event(struct hci_h4p_info *info,
-+ struct sk_buff *skb)
-+{
-+ struct hci_fw_event *ev;
-+ int err = 0;
-+
-+ if (bt_cb(skb)->pkt_type != H4_EVT_PKT) {
-+ dev_err(info->dev, "Got non event fw packet.\n");
-+ err = -EPROTO;
-+ goto ret;
-+ }
-+
-+ ev = (struct hci_fw_event *)skb->data;
-+ if (ev->hev.evt != HCI_EV_CMD_COMPLETE) {
-+ dev_err(info->dev, "Got non cmd complete fw event\n");
-+ err = -EPROTO;
-+ goto ret;
-+ }
-+
-+ if (ev->status != 0) {
-+ dev_err(info->dev, "Got error status from fw command\n");
-+ err = -EPROTO;
-+ goto ret;
-+ }
-+
-+ret:
-+ info->fw_error = err;
-+ complete(&info->fw_completion);
-+}
-+
-+int hci_h4p_brf6150_send_fw(struct hci_h4p_info *info, struct sk_buff_head *fw_queue)
-+{
-+ struct sk_buff *skb;
-+ int err = 0;
-+
-+ info->fw_error = 0;
-+
-+ while ((skb = skb_dequeue(fw_queue)) != NULL) {
-+ /* We should allways send word aligned data to h4+ devices */
-+ if (skb->len % 2) {
-+ err = skb_pad(skb, 1);
-+ }
-+ if (err)
-+ return err;
-+
-+ init_completion(&info->fw_completion);
-+ skb_queue_tail(&info->txq, skb);
-+ tasklet_schedule(&info->tx_task);
-+
-+ if (!wait_for_completion_timeout(&info->fw_completion, HZ)) {
-+ dev_err(info->dev, "Timeout while sending brf6150 fw\n");
-+ return -ETIMEDOUT;
-+ }
-+
-+ if (info->fw_error) {
-+ dev_err(info->dev, "There was fw_error while sending bfr6150 fw\n");
-+ return -EPROTO;
-+ }
-+ }
-+ NBT_DBG_FW("Firmware sent\n");
-+
-+ return 0;
-+}
---- /dev/null
-+++ b/drivers/bluetooth/hci_h4p/hci_h4p.h
-@@ -0,0 +1,183 @@
-+/*
-+ * This file is part of hci_h4p bluetooth driver
-+ *
-+ * Copyright (C) 2005, 2006 Nokia Corporation.
-+ *
-+ * Contact: Ville Tervo <ville.tervo@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
-+ * 02110-1301 USA
-+ *
-+ */
-+
-+#include <mach/board.h>
-+
-+#include <net/bluetooth/bluetooth.h>
-+#include <net/bluetooth/hci_core.h>
-+#include <net/bluetooth/hci.h>
-+
-+#ifndef __DRIVERS_BLUETOOTH_HCI_H4P_H
-+#define __DRIVERS_BLUETOOTH_HCI_H4P_H
-+
-+#define UART_SYSC_OMAP_RESET 0x03
-+#define UART_SYSS_RESETDONE 0x01
-+#define UART_OMAP_SCR_EMPTY_THR 0x08
-+#define UART_OMAP_SCR_WAKEUP 0x10
-+#define UART_OMAP_SSR_WAKEUP 0x02
-+#define UART_OMAP_SSR_TXFULL 0x01
-+
-+#if 0
-+#define NBT_DBG(fmt, arg...) printk("%s: " fmt "" , __FUNCTION__ , ## arg)
-+#else
-+#define NBT_DBG(...)
-+#endif
-+
-+#if 0
-+#define NBT_DBG_FW(fmt, arg...) printk("%s: " fmt "" , __FUNCTION__ , ## arg)
-+#else
-+#define NBT_DBG_FW(...)
-+#endif
-+
-+#if 0
-+#define NBT_DBG_POWER(fmt, arg...) printk("%s: " fmt "" , __FUNCTION__ , ## arg)
-+#else
-+#define NBT_DBG_POWER(...)
-+#endif
-+
-+#if 0
-+#define NBT_DBG_TRANSFER(fmt, arg...) printk("%s: " fmt "" , __FUNCTION__ , ## arg)
-+#else
-+#define NBT_DBG_TRANSFER(...)
-+#endif
-+
-+#if 0
-+#define NBT_DBG_TRANSFER_NF(fmt, arg...) printk(fmt "" , ## arg)
-+#else
-+#define NBT_DBG_TRANSFER_NF(...)
-+#endif
-+
-+#if 0
-+#define NBT_DBG_DMA(fmt, arg...) printk("%s: " fmt "" , __FUNCTION__ , ## arg)
-+#else
-+#define NBT_DBG_DMA(...)
-+#endif
-+
-+struct hci_h4p_info {
-+ struct hci_dev *hdev;
-+ spinlock_t lock;
-+
-+ void __iomem *uart_base;
-+ unsigned long uart_phys_base;
-+ int irq;
-+ struct device *dev;
-+ u8 bdaddr[6];
-+ u8 chip_type;
-+ u8 bt_wakeup_gpio;
-+ u8 host_wakeup_gpio;
-+ u8 reset_gpio;
-+ u8 bt_sysclk;
-+
-+
-+ struct sk_buff_head fw_queue;
-+ struct sk_buff *alive_cmd_skb;
-+ struct completion init_completion;
-+ struct completion fw_completion;
-+ int fw_error;
-+ int init_error;
-+
-+ struct sk_buff_head txq;
-+ struct tasklet_struct tx_task;
-+
-+ struct sk_buff *rx_skb;
-+ long rx_count;
-+ unsigned long rx_state;
-+ unsigned long garbage_bytes;
-+ struct tasklet_struct rx_task;
-+
-+ int pm_enabled;
-+ int tx_pm_enabled;
-+ int rx_pm_enabled;
-+ struct timer_list tx_pm_timer;
-+ struct timer_list rx_pm_timer;
-+
-+ int tx_clocks_en;
-+ int rx_clocks_en;
-+ spinlock_t clocks_lock;
-+ struct clk *uart_iclk;
-+ struct clk *uart_fclk;
-+};
-+
-+#define MAX_BAUD_RATE 921600
-+#define BC4_MAX_BAUD_RATE 3692300
-+#define UART_CLOCK 48000000
-+#define BT_INIT_DIVIDER 320
-+#define BT_BAUDRATE_DIVIDER 384000000
-+#define BT_SYSCLK_DIV 1000
-+#define INIT_SPEED 120000
-+
-+#define H4_TYPE_SIZE 1
-+
-+/* H4+ packet types */
-+#define H4_CMD_PKT 0x01
-+#define H4_ACL_PKT 0x02
-+#define H4_SCO_PKT 0x03
-+#define H4_EVT_PKT 0x04
-+#define H4_NEG_PKT 0x06
-+#define H4_ALIVE_PKT 0x07
-+
-+/* TX states */
-+#define WAIT_FOR_PKT_TYPE 1
-+#define WAIT_FOR_HEADER 2
-+#define WAIT_FOR_DATA 3
-+
-+struct hci_fw_event {
-+ struct hci_event_hdr hev;
-+ struct hci_ev_cmd_complete cmd;
-+ u8 status;
-+} __attribute__ ((packed));
-+
-+struct hci_bc4_set_bdaddr {
-+ u8 type;
-+ struct hci_command_hdr cmd_hdr;
-+} __attribute__ ((packed));
-+
-+int hci_h4p_send_alive_packet(struct hci_h4p_info *info);
-+
-+void hci_h4p_bc4_parse_fw_event(struct hci_h4p_info *info,
-+ struct sk_buff *skb);
-+int hci_h4p_bc4_send_fw(struct hci_h4p_info *info,
-+ struct sk_buff_head *fw_queue);
-+
-+void hci_h4p_brf6150_parse_fw_event(struct hci_h4p_info *info,
-+ struct sk_buff *skb);
-+int hci_h4p_brf6150_send_fw(struct hci_h4p_info *info,
-+ struct sk_buff_head *fw_queue);
-+
-+int hci_h4p_read_fw(struct hci_h4p_info *info, struct sk_buff_head *fw_queue);
-+int hci_h4p_send_fw(struct hci_h4p_info *info, struct sk_buff_head *fw_queue);
-+void hci_h4p_parse_fw_event(struct hci_h4p_info *info, struct sk_buff *skb);
-+
-+int hci_h4p_sysfs_create_files(struct device *dev);
-+
-+void hci_h4p_outb(struct hci_h4p_info *info, unsigned int offset, u8 val);
-+u8 hci_h4p_inb(struct hci_h4p_info *info, unsigned int offset);
-+void hci_h4p_set_rts(struct hci_h4p_info *info, int active);
-+int hci_h4p_wait_for_cts(struct hci_h4p_info *info, int active, int timeout_ms);
-+void __hci_h4p_set_auto_ctsrts(struct hci_h4p_info *info, int on, u8 which);
-+void hci_h4p_set_auto_ctsrts(struct hci_h4p_info *info, int on, u8 which);
-+void hci_h4p_change_speed(struct hci_h4p_info *info, unsigned long speed);
-+int hci_h4p_reset_uart(struct hci_h4p_info *info);
-+int hci_h4p_init_uart(struct hci_h4p_info *info);
-+
-+#endif /* __DRIVERS_BLUETOOTH_HCI_H4P_H */
---- /dev/null
-+++ b/drivers/bluetooth/hci_h4p/Makefile
-@@ -0,0 +1,7 @@
-+#
-+# Makefile for the Linux Bluetooth HCI device drivers.
-+#
-+
-+obj-$(CONFIG_BT_HCIH4P) += hci_h4p.o
-+
-+hci_h4p-objs := core.o fw.o uart.o sysfs.o fw-ti.o fw-csr.o
---- /dev/null
-+++ b/drivers/bluetooth/hci_h4p/sysfs.c
-@@ -0,0 +1,84 @@
-+/*
-+ * This file is part of hci_h4p bluetooth driver
-+ *
-+ * Copyright (C) 2005, 2006 Nokia Corporation.
-+ *
-+ * Contact: Ville Tervo <ville.tervo@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
-+ * 02110-1301 USA
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/platform_device.h>
-+
-+#include "hci_h4p.h"
-+
-+#ifdef CONFIG_SYSFS
-+
-+static ssize_t hci_h4p_store_bdaddr(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct hci_h4p_info *info = (struct hci_h4p_info*)dev_get_drvdata(dev);
-+ unsigned int bdaddr[6];
-+ int ret, i;
-+
-+ dev_info(info->dev, "HCI_H4P_STORE_BDADDR called\n");
-+
-+ ret = sscanf(buf, "%2x:%2x:%2x:%2x:%2x:%2x\n",
-+ &bdaddr[0], &bdaddr[1], &bdaddr[2],
-+ &bdaddr[3], &bdaddr[4], &bdaddr[5]);
-+
-+ if (ret != 6) {
-+ dev_info(info->dev, "bdaddr isn't found\n");
-+ return -EINVAL;
-+ }
-+
-+ //for (i = 0; i < 6; i++)
-+ //info->bdaddr[i] = bdaddr[i] & 0xff;
-+
-+ info->bdaddr[0] = 0x00;
-+ info->bdaddr[1] = 0x1D;
-+ info->bdaddr[2] = 0x6E;
-+ info->bdaddr[3] = 0xD4;
-+ info->bdaddr[4] = 0xF0;
-+ info->bdaddr[5] = 0x37;
-+
-+ return count;
-+}
-+
-+static ssize_t hci_h4p_show_bdaddr(struct device *dev, struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct hci_h4p_info *info = (struct hci_h4p_info*)dev_get_drvdata(dev);
-+
-+ return sprintf(buf, "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
-+ info->bdaddr[0],
-+ info->bdaddr[1],
-+ info->bdaddr[2],
-+ info->bdaddr[3],
-+ info->bdaddr[4],
-+ info->bdaddr[5]);
-+}
-+
-+static DEVICE_ATTR(bdaddr, S_IRUGO | S_IWUSR, hci_h4p_show_bdaddr, hci_h4p_store_bdaddr);
-+int hci_h4p_sysfs_create_files(struct device *dev)
-+{
-+ return device_create_file(dev, &dev_attr_bdaddr);
-+}
-+
-+#endif
---- /dev/null
-+++ b/drivers/bluetooth/hci_h4p/uart.c
-@@ -0,0 +1,169 @@
-+/*
-+ * This file is part of hci_h4p bluetooth driver
-+ *
-+ * Copyright (C) 2005, 2006 Nokia Corporation.
-+ *
-+ * Contact: Ville Tervo <ville.tervo@nokia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
-+ * 02110-1301 USA
-+ *
-+ */
-+
-+#include <linux/serial_reg.h>
-+#include <linux/delay.h>
-+#include <linux/clk.h>
-+
-+#include <asm/io.h>
-+
-+#include "hci_h4p.h"
-+
-+inline void hci_h4p_outb(struct hci_h4p_info *info, unsigned int offset, u8 val)
-+{
-+ offset <<= 2;
-+ __raw_writeb(val, info->uart_base + offset);
-+ //outb(val, info->uart_base + (offset << 2));
-+}
-+
-+inline u8 hci_h4p_inb(struct hci_h4p_info *info, unsigned int offset)
-+{
-+ offset <<= 2;
-+ return (u8)__raw_readb(info->uart_base + offset);
-+ //return (unsigned int)__raw_readb(up->membase + offset);
-+ //return inb(info->uart_base + (offset << 2));
-+}
-+
-+void hci_h4p_set_rts(struct hci_h4p_info *info, int active)
-+{
-+ u8 b;
-+
-+ b = hci_h4p_inb(info, UART_MCR);
-+ if (active)
-+ b |= UART_MCR_RTS;
-+ else
-+ b &= ~UART_MCR_RTS;
-+ hci_h4p_outb(info, UART_MCR, b);
-+}
-+
-+int hci_h4p_wait_for_cts(struct hci_h4p_info *info, int active,
-+ int timeout_ms)
-+{
-+ int okay;
-+ unsigned long timeout;
-+
-+ okay = 0;
-+ timeout = jiffies + msecs_to_jiffies(timeout_ms);
-+ for (;;) {
-+ int state;
-+
-+ state = hci_h4p_inb(info, UART_MSR) & UART_MSR_CTS;
-+ if (active) {
-+ if (state)
-+ return 0;
-+ } else {
-+ if (!state)
-+ return 0;
-+ }
-+ if (time_after(jiffies, timeout))
-+ return -ETIMEDOUT;
-+ }
-+}
-+
-+void __hci_h4p_set_auto_ctsrts(struct hci_h4p_info *info, int on, u8 which)
-+{
-+ u8 lcr, b;
-+
-+ lcr = hci_h4p_inb(info, UART_LCR);
-+ hci_h4p_outb(info, UART_LCR, 0xbf);
-+ b = hci_h4p_inb(info, UART_EFR);
-+ if (on)
-+ b |= which;
-+ else
-+ b &= ~which;
-+ hci_h4p_outb(info, UART_EFR, b);
-+ hci_h4p_outb(info, UART_LCR, lcr);
-+}
-+
-+void hci_h4p_set_auto_ctsrts(struct hci_h4p_info *info, int on, u8 which)
-+{
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&info->lock, flags);
-+ __hci_h4p_set_auto_ctsrts(info, on, which);
-+ spin_unlock_irqrestore(&info->lock, flags);
-+}
-+
-+void hci_h4p_change_speed(struct hci_h4p_info *info, unsigned long speed)
-+{
-+ unsigned int divisor;
-+ u8 lcr, mdr1;
-+
-+ NBT_DBG("Setting speed %lu\n", speed);
-+
-+ if (speed >= 460800) {
-+ divisor = UART_CLOCK / 13 / speed;
-+ mdr1 = 3;
-+ } else {
-+ divisor = UART_CLOCK / 16 / speed;
-+ mdr1 = 0;
-+ }
-+
-+ hci_h4p_outb(info, UART_OMAP_MDR1, 7); /* Make sure UART mode is disabled */
-+ lcr = hci_h4p_inb(info, UART_LCR);
-+ hci_h4p_outb(info, UART_LCR, UART_LCR_DLAB); /* Set DLAB */
-+ hci_h4p_outb(info, UART_DLL, divisor & 0xff); /* Set speed */
-+ hci_h4p_outb(info, UART_DLM, divisor >> 8);
-+ hci_h4p_outb(info, UART_LCR, lcr);
-+ hci_h4p_outb(info, UART_OMAP_MDR1, mdr1); /* Make sure UART mode is enabled */
-+}
-+
-+int hci_h4p_reset_uart(struct hci_h4p_info *info)
-+{
-+ int count = 0;
-+
-+ /* Reset the UART */
-+ hci_h4p_outb(info, UART_OMAP_SYSC, UART_SYSC_OMAP_RESET);
-+ while (!(hci_h4p_inb(info, UART_OMAP_SYSS) & UART_SYSS_RESETDONE)) {
-+ if (count++ > 20000) {
-+ dev_err(info->dev, "hci_h4p: UART reset timeout\n");
-+ return -ENODEV;
-+ }
-+ udelay(1);
-+ }
-+
-+ return 0;
-+}
-+
-+int hci_h4p_init_uart(struct hci_h4p_info *info)
-+{
-+ int err;
-+
-+ err = hci_h4p_reset_uart(info);
-+ if (err < 0)
-+ return err;
-+
-+ /* Enable and setup FIFO */
-+ hci_h4p_outb(info, UART_LCR, UART_LCR_WLEN8);
-+ hci_h4p_outb(info, UART_OMAP_MDR1, 0x00); /* Make sure UART mode is enabled */
-+ hci_h4p_outb(info, UART_OMAP_SCR, 0x80);
-+ hci_h4p_outb(info, UART_EFR, UART_EFR_ECB);
-+ hci_h4p_outb(info, UART_MCR, UART_MCR_TCRTLR);
-+ hci_h4p_outb(info, UART_TI752_TLR, 0x1f);
-+ hci_h4p_outb(info, UART_TI752_TCR, 0xef);
-+ hci_h4p_outb(info, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
-+ UART_FCR_CLEAR_XMIT | UART_FCR_R_TRIG_00);
-+ hci_h4p_outb(info, UART_IER, UART_IER_RDI);
-+
-+ return 0;
-+}
---- a/drivers/bluetooth/Kconfig
-+++ b/drivers/bluetooth/Kconfig
-@@ -173,6 +173,16 @@ config BT_HCIBTUART
- Say Y here to compile support for HCI UART devices into the
- kernel or say M to compile it as module (btuart_cs).
-
-+config BT_HCIH4P
-+ tristate "HCI driver with H4 Nokia extensions"
-+ depends on BT && ARCH_OMAP
-+ help
-+ Bluetooth HCI driver with H4 extensions. This driver provides
-+ support for H4+ Bluetooth chip with vendor-specific H4 extensions.
-+
-+ Say Y here to compile support for h4 extended devices into the kernel
-+ or say M to compile it as module (hci_h4p).
-+
- config BT_HCIVHCI
- tristate "HCI VHCI (Virtual HCI device) driver"
- help
---- a/drivers/bluetooth/Makefile
-+++ b/drivers/bluetooth/Makefile
-@@ -11,6 +11,7 @@ obj-$(CONFIG_BT_HCIDTL1) += dtl1_cs.o
- obj-$(CONFIG_BT_HCIBT3C) += bt3c_cs.o
- obj-$(CONFIG_BT_HCIBLUECARD) += bluecard_cs.o
- obj-$(CONFIG_BT_HCIBTUART) += btuart_cs.o
-+obj-$(CONFIG_BT_HCIH4P) += hci_h4p/
-
- obj-$(CONFIG_BT_HCIBTUSB) += btusb.o
- obj-$(CONFIG_BT_HCIBTSDIO) += btsdio.o
+++ /dev/null
---- a/drivers/bluetooth/hci_h4p/core.c
-+++ b/drivers/bluetooth/hci_h4p/core.c
-@@ -36,9 +36,9 @@
- #include <linux/clk.h>
- #include <linux/gpio.h>
-
--#include <mach/hardware.h>
--#include <mach/board.h>
--#include <mach/irqs.h>
-+#include <plat/hardware.h>
-+#include <plat/board.h>
-+#include <plat/irqs.h>
- #include <plat/serial.h>
-
- #include <net/bluetooth/bluetooth.h>
---- a/drivers/bluetooth/hci_h4p/hci_h4p.h
-+++ b/drivers/bluetooth/hci_h4p/hci_h4p.h
-@@ -21,7 +21,7 @@
- *
- */
-
--#include <mach/board.h>
-+#include <plat/board.h>
-
- #include <net/bluetooth/bluetooth.h>
- #include <net/bluetooth/hci_core.h>
---- a/drivers/bluetooth/hci_h4p/sysfs.c
-+++ b/drivers/bluetooth/hci_h4p/sysfs.c
-@@ -48,15 +48,8 @@ static ssize_t hci_h4p_store_bdaddr(stru
- return -EINVAL;
- }
-
-- //for (i = 0; i < 6; i++)
-- //info->bdaddr[i] = bdaddr[i] & 0xff;
--
-- info->bdaddr[0] = 0x00;
-- info->bdaddr[1] = 0x1D;
-- info->bdaddr[2] = 0x6E;
-- info->bdaddr[3] = 0xD4;
-- info->bdaddr[4] = 0xF0;
-- info->bdaddr[5] = 0x37;
-+ for (i = 0; i < 6; i++)
-+ info->bdaddr[i] = bdaddr[i] & 0xff;
-
- return count;
- }
+++ /dev/null
---- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
-+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
-@@ -235,7 +235,7 @@ struct omap_hwmod_irq_info omap2_timer11
- };
-
- struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
-- { .irq = INT_24XX_UART1_IRQ, },
-+ { .irq = 0, },
- { .irq = -1 }
- };
-
---- a/drivers/tty/serial/omap-serial.c
-+++ b/drivers/tty/serial/omap-serial.c
-@@ -517,8 +517,10 @@ static int serial_omap_startup(struct ua
- /*
- * Allocate the IRQ
- */
-- retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
-- up->name, up);
-+ retval = 0;
-+ if (up->port.irq)
-+ retval = request_irq(up->port.irq, serial_omap_irq,
-+ up->port.irqflags, up->name, up);
- if (retval)
- return retval;
-
-@@ -629,7 +631,8 @@ static void serial_omap_shutdown(struct
- }
-
- pm_runtime_put(&up->pdev->dev);
-- free_irq(up->port.irq, up);
-+ if (up->port.irq)
-+ free_irq(up->port.irq, up);
- }
-
- static inline void
+++ /dev/null
---- a/arch/arm/mach-omap2/board-n8x0.c
-+++ b/arch/arm/mach-omap2/board-n8x0.c
-@@ -41,6 +41,7 @@
- #include <plat/mmc.h>
- #include <plat/serial.h>
- #include <plat/gpio-switch.h>
-+#include <plat/usb.h>
-
- #include "mux.h"
-
-@@ -486,6 +487,14 @@ static struct musb_hdrc_platform_data tu
- .config = &musb_config,
- };
-
-+static struct omap_usb_config n8x0_omap_usb_config __initdata = {
-+ .otg = 1,
-+ .register_host = 1,
-+ .register_dev = 1,
-+ .hmc_mode = 16,
-+ .pins[0] = 6,
-+};
-+
- static void __init n8x0_usb_init(void)
- {
- int ret = 0;
-@@ -507,6 +516,8 @@ static void __init n8x0_usb_init(void)
- if (ret != 0)
- goto err;
-
-+ omap2_usbfs_init(&n8x0_omap_usb_config);
-+
- printk(announce);
-
- return;
+++ /dev/null
----
- drivers/input/evdev.c | 10 +++++++---
- 1 file changed, 7 insertions(+), 3 deletions(-)
-
---- a/drivers/input/evdev.c
-+++ b/drivers/input/evdev.c
-@@ -92,7 +92,7 @@ static void evdev_event(struct input_han
- unsigned int type, unsigned int code, int value)
- {
- struct evdev *evdev = handle->private;
-- struct evdev_client *client;
-+ struct evdev_client *client, *c;
- struct input_event event;
-
- do_gettimeofday(&event.time);
-@@ -103,9 +103,13 @@ static void evdev_event(struct input_han
- rcu_read_lock();
-
- client = rcu_dereference(evdev->grab);
-- if (client)
-+ if (client) {
- evdev_pass_event(client, &event);
-- else
-+ /* Also pass events to clients that did not grab the device. */
-+ list_for_each_entry_rcu(c, &evdev->client_list, node)
-+ if (c != client)
-+ evdev_pass_event(c, &event);
-+ } else
- list_for_each_entry_rcu(client, &evdev->client_list, node)
- evdev_pass_event(client, &event);
-
+++ /dev/null
---- a/drivers/mmc/host/omap.c
-+++ b/drivers/mmc/host/omap.c
-@@ -1456,6 +1456,7 @@ static int __init mmc_omap_probe(struct
- host->dma_ch = -1;
-
- host->irq = irq;
-+ host->reg_shift = (cpu_is_omap7xx() ? 1 : 2);
- host->phys_base = host->mem_res->start;
- host->virt_base = ioremap(res->start, resource_size(res));
- if (!host->virt_base)
-@@ -1495,7 +1496,9 @@ static int __init mmc_omap_probe(struct
- }
- }
-
-- host->reg_shift = (cpu_is_omap7xx() ? 1 : 2);
-+ /* Make sure the detect workqueue was run at least once. */
-+ printk(KERN_INFO "OMAP-mmc: waiting for cards...\n");
-+ mmc_flush_scheduled_work();
-
- return 0;
-
---- a/drivers/mmc/core/core.c
-+++ b/drivers/mmc/core/core.c
-@@ -78,12 +78,13 @@ static int mmc_schedule_delayed_work(str
- }
-
- /*
-- * Internal function. Flush all scheduled work from the MMC work queue.
-+ * Flush all scheduled work from the MMC work queue.
- */
--static void mmc_flush_scheduled_work(void)
-+void mmc_flush_scheduled_work(void)
- {
- flush_workqueue(workqueue);
- }
-+EXPORT_SYMBOL(mmc_flush_scheduled_work);
-
- #ifdef CONFIG_FAIL_MMC_REQUEST
-
---- a/include/linux/mmc/host.h
-+++ b/include/linux/mmc/host.h
-@@ -445,6 +445,8 @@ static inline int mmc_boot_partition_acc
- return !(host->caps2 & MMC_CAP2_BOOTPART_NOACC);
- }
-
-+void mmc_flush_scheduled_work(void);
-+
- #ifdef CONFIG_MMC_CLKGATE
- void mmc_host_clk_hold(struct mmc_host *host);
- void mmc_host_clk_release(struct mmc_host *host);
+++ /dev/null
---- a/arch/arm/mach-omap2/serial.c
-+++ b/arch/arm/mach-omap2/serial.c
-@@ -258,6 +258,8 @@ char *cmdline_find_option(char *str)
- return strstr(saved_command_line, str);
- }
-
-+static struct omap_uart_state statebuf[4];
-+
- static int __init omap_serial_early_init(void)
- {
- do {
-@@ -272,9 +274,9 @@ static int __init omap_serial_early_init
- if (!oh)
- break;
-
-- uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
-- if (WARN_ON(!uart))
-+ if (WARN_ON(num_uarts >= ARRAY_SIZE(statebuf)))
- return -ENODEV;
-+ uart = &statebuf[num_uarts];
-
- uart->oh = oh;
- uart->num = num_uarts++;
+++ /dev/null
---- a/drivers/usb/musb/tusb6010.c
-+++ b/drivers/usb/musb/tusb6010.c
-@@ -221,6 +221,7 @@ void musb_write_fifo(struct musb_hw_ep *
- if (len > 0)
- tusb_fifo_write_unaligned(fifo, buf, len);
- }
-+EXPORT_SYMBOL(musb_write_fifo);
-
- void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
- {
-@@ -268,6 +269,7 @@ void musb_read_fifo(struct musb_hw_ep *h
- if (len > 0)
- tusb_fifo_read_unaligned(fifo, buf, len);
- }
-+EXPORT_SYMBOL(musb_read_fifo);
-
- static struct musb *the_musb;
-
-@@ -1165,7 +1167,7 @@ static const struct musb_platform_ops tu
-
- static u64 tusb_dmamask = DMA_BIT_MASK(32);
-
--static int __init tusb_probe(struct platform_device *pdev)
-+static int tusb_probe(struct platform_device *pdev)
- {
- struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
- struct platform_device *musb;
-@@ -1245,18 +1247,18 @@ static struct platform_driver tusb_drive
- },
- };
-
--MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
--MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
--MODULE_LICENSE("GPL v2");
-+//MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
-+//MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
-+//MODULE_LICENSE("GPL v2");
-
--static int __init tusb_init(void)
-+int musb_hdrc_glue_init(void)
- {
- return platform_driver_probe(&tusb_driver, tusb_probe);
- }
--subsys_initcall(tusb_init);
-+EXPORT_SYMBOL(musb_hdrc_glue_init);
-
--static void __exit tusb_exit(void)
-+void musb_hdrc_glue_exit(void)
- {
- platform_driver_unregister(&tusb_driver);
- }
--module_exit(tusb_exit);
-+EXPORT_SYMBOL(musb_hdrc_glue_exit);
---- a/drivers/usb/musb/musb_core.c
-+++ b/drivers/usb/musb/musb_core.c
-@@ -207,7 +207,7 @@ static struct otg_io_access_ops musb_ulp
-
- /*-------------------------------------------------------------------------*/
-
--#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
-+#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_TUSB6010_MODULE) && !defined(CONFIG_USB_MUSB_BLACKFIN)
-
- /*
- * Load an endpoint's FIFO
-@@ -250,7 +250,7 @@ void musb_write_fifo(struct musb_hw_ep *
- }
- }
-
--#if !defined(CONFIG_USB_MUSB_AM35X)
-+#if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
- /*
- * Unload an endpoint's FIFO
- */
-@@ -2370,8 +2370,13 @@ static struct platform_driver musb_drive
-
- /*-------------------------------------------------------------------------*/
-
-+extern int musb_hdrc_glue_init(void);
-+extern void musb_hdrc_glue_exit(void);
-+
- static int __init musb_init(void)
- {
-+ int err;
-+
- if (usb_disabled())
- return 0;
-
-@@ -2380,7 +2385,17 @@ static int __init musb_init(void)
- ", "
- "otg (peripheral+host)",
- musb_driver_name);
-- return platform_driver_probe(&musb_driver, musb_probe);
-+
-+ err = musb_hdrc_glue_init();
-+ if (err)
-+ return err;
-+ err = platform_driver_probe(&musb_driver, musb_probe);
-+ if (err) {
-+ musb_hdrc_glue_exit();
-+ return err;
-+ }
-+
-+ return 0;
- }
-
- /* make us init after usbcore and i2c (transceivers, regulators, etc)
-@@ -2391,5 +2406,6 @@ fs_initcall(musb_init);
- static void __exit musb_cleanup(void)
- {
- platform_driver_unregister(&musb_driver);
-+ musb_hdrc_glue_exit();
- }
- module_exit(musb_cleanup);
---- a/drivers/usb/Makefile
-+++ b/drivers/usb/Makefile
-@@ -51,7 +51,7 @@ obj-$(CONFIG_EARLY_PRINTK_DBGP) += early
- obj-$(CONFIG_USB_ATM) += atm/
- obj-$(CONFIG_USB_SPEEDTOUCH) += atm/
-
--obj-$(CONFIG_USB_MUSB_HDRC) += musb/
-+obj-y += musb/
- obj-$(CONFIG_USB_RENESAS_USBHS) += renesas_usbhs/
- obj-$(CONFIG_USB_GADGET) += gadget/
-
---- a/drivers/usb/musb/Makefile
-+++ b/drivers/usb/musb/Makefile
-@@ -13,7 +13,7 @@ musb_hdrc-$(CONFIG_DEBUG_FS) += musb_d
- # Hardware Glue Layer
- obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
- obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
--obj-$(CONFIG_USB_MUSB_TUSB6010) += tusb6010.o
-+musb_hdrc-$(subst m,y,$(CONFIG_USB_MUSB_TUSB6010)) += tusb6010.o
- obj-$(CONFIG_USB_MUSB_DAVINCI) += davinci.o
- obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o
- obj-$(CONFIG_USB_MUSB_BLACKFIN) += blackfin.o
+++ /dev/null
---- a/drivers/cbus/Kconfig
-+++ b/drivers/cbus/Kconfig
-@@ -83,4 +83,12 @@ config CBUS_RETU_HEADSET
-
- endif # CBUS_RETU
-
-+config N810BM
-+ depends on CBUS_RETU && CBUS_TAHVO
-+ tristate "Nokia n810 battery management"
-+ ---help---
-+ Nokia n810 device battery management.
-+
-+ If unsure, say N.
-+
- endmenu
---- a/drivers/cbus/Makefile
-+++ b/drivers/cbus/Makefile
-@@ -11,3 +11,6 @@ obj-$(CONFIG_CBUS_RETU_POWERBUTTON) += r
- obj-$(CONFIG_CBUS_RETU_RTC) += retu-rtc.o
- obj-$(CONFIG_CBUS_RETU_WDT) += retu-wdt.o
- obj-$(CONFIG_CBUS_RETU_HEADSET) += retu-headset.o
-+n810bm-y += n810bm_main.o
-+n810bm-y += lipocharge.o
-+obj-$(CONFIG_N810BM) += n810bm.o
---- /dev/null
-+++ b/drivers/cbus/n810bm_main.c
-@@ -0,0 +1,1572 @@
-+/*
-+ * Nokia n810 battery management
-+ *
-+ * WARNING: This driver is based on unconfirmed documentation.
-+ * It is possibly dangerous to use this software.
-+ * Use this software at your own risk!
-+ *
-+ * Copyright (c) 2010-2011 Michael Buesch <mb@bu3sch.de>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#define DEBUG
-+
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/mutex.h>
-+#include <linux/timer.h>
-+#include <linux/firmware.h>
-+#include <linux/bitops.h>
-+#include <linux/workqueue.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+
-+#include "cbus.h"
-+#include "retu.h"
-+#include "tahvo.h"
-+#include "lipocharge.h"
-+
-+
-+#define N810BM_PMM_BLOCK_FILENAME "n810-cal-bme-pmm.fw"
-+#define N810BM_PMM_BLOCK_SIZE 0x600
-+#define N810BM_PMM_GROUP_SIZE 0x200
-+#define N810BM_PMM_ELEM_SIZE 0x10
-+
-+#define N810BM_CHECK_INTERVAL (HZ * 2)
-+#define N810BM_MIN_VOLTAGE_THRES 3200 /* Absolute minimum voltage threshold */
-+
-+
-+/* RETU_ADC_BSI
-+ * The battery size indicator ADC measures the resistance between
-+ * the battery BSI pin and ground. This is used to detect the battery
-+ * capacity, as the BSI resistor is related to capacity.
-+ *
-+ * Manually measured lookup table.
-+ * Hard to measure, thus not very accurate.
-+ *
-+ * Resistance | ADC value
-+ * ========================
-+ * 120k | 0x3AC
-+ * 110k | 0x37C
-+ * 100k | 0x351
-+ * 90k | 0x329
-+ */
-+
-+/* RETU_ADC_BATTVOLT
-+ * Manually measured lookup table.
-+ * Hard to measure, thus not very accurate.
-+ *
-+ * Voltage | ADC value
-+ * =====================
-+ * 2.80V | 0x037
-+ * 2.90V | 0x05E
-+ * 3.00V | 0x090
-+ * 3.10V | 0x0A4
-+ * 3.20V | 0x0CC
-+ * 3.30V | 0x0EF
-+ * 3.40V | 0x115
-+ * 3.50V | 0x136
-+ * 3.60V | 0x15C
-+ * 3.70V | 0x187
-+ * 3.80V | 0x1A5
-+ * 3.90V | 0x1C9
-+ * 4.00V | 0x1ED
-+ * 4.10V | 0x212
-+ * 4.20V | 0x236
-+ */
-+
-+
-+/* PMM block ADC IDs */
-+enum n810bm_pmm_adc_id {
-+ N810BM_PMM_ADC_BATVOLT = 0x01, /* Battery voltage */
-+ N810BM_PMM_ADC_CHGVOLT = 0x02, /* Charger voltage */
-+ N810BM_PMM_ADC_GND2 = 0x03, /* Ground 0V */
-+ N810BM_PMM_ADC_BSI = 0x04, /* Battery size indicator */
-+ N810BM_PMM_ADC_BATTEMP = 0x05, /* Battery temperature */
-+ N810BM_PMM_ADC_HEADSET = 0x06, /* Headset detection */
-+ N810BM_PMM_ADC_HOOKDET = 0x07, /* Hook detection */
-+ N810BM_PMM_ADC_LIGHTSENS = 0x08, /* Light sensor */
-+ N810BM_PMM_ADC_BATCURR = 0x0E, /* Battery current */
-+ N810BM_PMM_ADC_BKUPVOLT = 0x13, /* Backup battery voltage */
-+ N810BM_PMM_ADC_LIGHTTEMP = 0x14, /* Light sensor temperature */
-+ N810BM_PMM_ADC_RFGP = 0x15, /* RF GP */
-+ N810BM_PMM_ADC_WBTX = 0x16, /* Wideband TX detection */
-+ N810BM_PMM_ADC_RETUTEMP = 0x17, /* RETU chip temperature */
-+ N810BM_PMM_ADC_0xFE = 0xFE,
-+};
-+
-+struct n810bm_adc_calib {
-+ enum n810bm_pmm_adc_id id;
-+ u8 flags;
-+ u8 adc_groupnr;
-+ u32 field1;
-+ u32 field2;
-+ u16 field3;
-+ u16 field4;
-+};
-+
-+struct n810bm_calib {
-+ struct n810bm_adc_calib adc[25];
-+};
-+
-+enum n810bm_capacity {
-+ N810BM_CAP_UNKNOWN = -1,
-+ N810BM_CAP_NONE = 0,
-+ N810BM_CAP_1500MAH = 1500, /* 1500 mAh battery */
-+};
-+
-+enum n810bm_notify_flags {
-+ N810BM_NOTIFY_charger_present,
-+ N810BM_NOTIFY_charger_state,
-+ N810BM_NOTIFY_charger_pwm,
-+};
-+
-+struct n810bm {
-+ int tahvo_irq;
-+ bool tahvo_irq_enabled;
-+
-+ bool battery_present; /* A battery is inserted */
-+ bool charger_present; /* The charger is connected */
-+ enum n810bm_capacity capacity; /* The capacity of the inserted battery (if any) */
-+
-+ bool charger_enabled; /* Want to charge? */
-+ struct lipocharge charger; /* Charger subsystem */
-+ unsigned int active_current_pwm; /* Active value of TAHVO_REG_CHGCURR */
-+ int current_measure_enabled; /* Current measure enable refcount */
-+
-+ struct platform_device *pdev;
-+ struct n810bm_calib calib; /* Calibration data */
-+
-+ bool verbose_charge_log; /* Verbose charge logging */
-+
-+ unsigned long notify_flags;
-+ struct work_struct notify_work;
-+ struct delayed_work periodic_check_work;
-+
-+ bool initialized; /* The hardware was initialized */
-+ struct mutex mutex;
-+};
-+
-+static void n810bm_notify_charger_present(struct n810bm *bm);
-+static void n810bm_notify_charger_state(struct n810bm *bm);
-+static void n810bm_notify_charger_pwm(struct n810bm *bm);
-+
-+
-+static struct platform_device *n810bm_retu_device;
-+static struct platform_device *n810bm_tahvo_device;
-+
-+
-+static inline struct n810bm * device_to_n810bm(struct device *dev)
-+{
-+ struct platform_device *pdev = to_platform_device(dev);
-+ struct n810bm *bm = platform_get_drvdata(pdev);
-+
-+ return bm;
-+}
-+
-+static inline bool n810bm_known_battery_present(struct n810bm *bm)
-+{
-+ return bm->battery_present &&
-+ bm->capacity != N810BM_CAP_UNKNOWN &&
-+ bm->capacity != N810BM_CAP_NONE;
-+}
-+
-+static void n810bm_emergency(struct n810bm *bm, const char *message) __noreturn;
-+static void n810bm_emergency(struct n810bm *bm, const char *message)
-+{
-+ printk(KERN_EMERG "n810 battery management fatal fault: %s\n", message);
-+ cbus_emergency();
-+}
-+
-+static u16 tahvo_read(struct n810bm *bm, unsigned int reg)
-+{
-+ return tahvo_read_reg(&n810bm_tahvo_device->dev, reg);
-+}
-+
-+static void tahvo_maskset(struct n810bm *bm, unsigned int reg, u16 mask, u16 set)
-+{
-+ tahvo_set_clear_reg_bits(&n810bm_tahvo_device->dev, reg, set, mask);
-+}
-+
-+static inline void tahvo_write(struct n810bm *bm, unsigned int reg, u16 value)
-+{
-+ tahvo_write_reg(&n810bm_tahvo_device->dev, reg, value);
-+}
-+
-+static inline void tahvo_set(struct n810bm *bm, unsigned int reg, u16 mask)
-+{
-+ tahvo_set_clear_reg_bits(&n810bm_tahvo_device->dev, reg, mask, mask);
-+}
-+
-+static inline void tahvo_clear(struct n810bm *bm, unsigned int reg, u16 mask)
-+{
-+ tahvo_set_clear_reg_bits(&n810bm_tahvo_device->dev, reg, 0, mask);
-+}
-+
-+static u16 retu_read(struct n810bm *bm, unsigned int reg)
-+{
-+ return retu_read_reg(&n810bm_retu_device->dev, reg);
-+}
-+
-+static void retu_maskset(struct n810bm *bm, unsigned int reg, u16 mask, u16 set)
-+{
-+ retu_set_clear_reg_bits(&n810bm_retu_device->dev, reg, set, mask);
-+}
-+
-+static inline void retu_write(struct n810bm *bm, unsigned int reg, u16 value)
-+{
-+ retu_write_reg(&n810bm_retu_device->dev, reg, value);
-+}
-+
-+static int retu_adc_average(struct n810bm *bm, unsigned int chan,
-+ unsigned int nr_passes)
-+{
-+ unsigned int i, value = 0;
-+ int ret;
-+
-+ if (WARN_ON(!nr_passes))
-+ return 0;
-+ for (i = 0; i < nr_passes; i++) {
-+ ret = retu_read_adc(&n810bm_retu_device->dev, chan);
-+ if (ret < 0)
-+ return ret;
-+ value += ret;
-+ }
-+ value /= nr_passes;
-+
-+ return value;
-+}
-+
-+static struct n810bm_adc_calib * n810bm_get_adc_calib(struct n810bm *bm,
-+ enum n810bm_pmm_adc_id id)
-+{
-+ unsigned int index = 0;
-+ struct n810bm_adc_calib *cal;
-+
-+ if (id != N810BM_PMM_ADC_0xFE)
-+ index = (unsigned int)id + 1;
-+ if (index >= ARRAY_SIZE(bm->calib.adc))
-+ return NULL;
-+
-+ cal = &bm->calib.adc[index];
-+ WARN_ON(cal->id && cal->id != id);
-+
-+ return cal;
-+}
-+
-+static int pmm_record_get(struct n810bm *bm,
-+ const struct firmware *pmm_block,
-+ void *buffer, size_t length,
-+ unsigned int group, unsigned int element, unsigned int offset)
-+{
-+ const u8 *pmm_area = pmm_block->data;
-+ u8 active_group_mask;
-+
-+ if (pmm_block->size != N810BM_PMM_BLOCK_SIZE)
-+ return -EINVAL;
-+ if (group >= N810BM_PMM_BLOCK_SIZE / N810BM_PMM_GROUP_SIZE)
-+ return -EINVAL;
-+ if (element >= N810BM_PMM_GROUP_SIZE / N810BM_PMM_ELEM_SIZE)
-+ return -EINVAL;
-+ if (offset >= N810BM_PMM_ELEM_SIZE || length > N810BM_PMM_ELEM_SIZE ||
-+ length + offset > N810BM_PMM_ELEM_SIZE)
-+ return -EINVAL;
-+
-+ active_group_mask = pmm_area[16];
-+ if (!(active_group_mask & (1 << group))) {
-+ dev_dbg(&bm->pdev->dev, "pwm_record_get: Requested group %u, "
-+ "but group is not active", group);
-+ return -ENOENT;
-+ }
-+
-+ memcpy(buffer,
-+ pmm_area + group * N810BM_PMM_GROUP_SIZE
-+ + element * N810BM_PMM_ELEM_SIZE
-+ + offset,
-+ length);
-+
-+ return 0;
-+}
-+
-+/* PMM block group 1 element */
-+struct group1_element {
-+ u8 id;
-+ u8 flags;
-+ u8 adc_groupnr;
-+ u8 _padding;
-+ __le32 field1;
-+ __le32 field2;
-+} __packed;
-+
-+static int extract_group1_elem(struct n810bm *bm,
-+ const struct firmware *pmm_block,
-+ const enum n810bm_pmm_adc_id *pmm_adc_ids, size_t nr_pmm_adc_ids,
-+ u32 field1_mask, u32 field2_mask)
-+{
-+ struct group1_element elem;
-+ int err;
-+ unsigned int i, element_nr;
-+ struct n810bm_adc_calib *adc_calib;
-+
-+ for (i = 0; i < nr_pmm_adc_ids; i++) {
-+ element_nr = (unsigned int)(pmm_adc_ids[i]) + 3;
-+
-+ err = pmm_record_get(bm, pmm_block, &elem, sizeof(elem),
-+ 1, element_nr, 0);
-+ if (err)
-+ continue;
-+ adc_calib = n810bm_get_adc_calib(bm, elem.id);
-+ if (!adc_calib) {
-+ dev_err(&bm->pdev->dev, "extract_group1_elem: "
-+ "Could not get calib element for 0x%02X",
-+ elem.id);
-+ return -EINVAL;
-+ }
-+
-+ if (adc_calib->flags == elem.flags) {
-+ adc_calib->field1 = le32_to_cpu(elem.field1) & field1_mask;
-+ adc_calib->field2 = le32_to_cpu(elem.field2) & field2_mask;
-+ } else {
-+ dev_dbg(&bm->pdev->dev, "extract_group1_elem: "
-+ "Not extracting fields due to flags mismatch: "
-+ "0x%02X vs 0x%02X",
-+ adc_calib->flags, elem.flags);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int n810bm_parse_pmm_group1(struct n810bm *bm,
-+ const struct firmware *pmm_block)
-+{
-+ struct n810bm_adc_calib *adc_calib;
-+ struct group1_element elem;
-+ int err;
-+
-+ static const enum n810bm_pmm_adc_id pmm_adc_ids_1[] = {
-+ N810BM_PMM_ADC_BATVOLT,
-+ N810BM_PMM_ADC_CHGVOLT,
-+ N810BM_PMM_ADC_BKUPVOLT,
-+ N810BM_PMM_ADC_BATCURR,
-+ };
-+ static const enum n810bm_pmm_adc_id pmm_adc_ids_2[] = {
-+ N810BM_PMM_ADC_BSI,
-+ };
-+ static const enum n810bm_pmm_adc_id pmm_adc_ids_3[] = {
-+ N810BM_PMM_ADC_BATTEMP,
-+ };
-+
-+ /* Parse element 2 */
-+ err = pmm_record_get(bm, pmm_block, &elem, sizeof(elem),
-+ 1, 2, 0);
-+ if (err) {
-+ dev_err(&bm->pdev->dev,
-+ "PMM: Failed to get group 1 / element 2");
-+ return err;
-+ }
-+ if (elem.id == N810BM_PMM_ADC_0xFE && elem.flags == 0x05) {
-+ adc_calib = n810bm_get_adc_calib(bm, elem.id);
-+ if (!adc_calib) {
-+ dev_err(&bm->pdev->dev,
-+ "calib extract: Failed to get 0xFE calib");
-+ return -EINVAL;
-+ }
-+ adc_calib->id = elem.id;
-+ adc_calib->flags = elem.flags;
-+ adc_calib->field1 = le32_to_cpu(elem.field1);
-+ adc_calib->field2 = le32_to_cpu(elem.field2);
-+ }
-+
-+ err = extract_group1_elem(bm, pmm_block,
-+ pmm_adc_ids_1, ARRAY_SIZE(pmm_adc_ids_1),
-+ 0xFFFFFFFF, 0xFFFFFFFF);
-+ if (err)
-+ return err;
-+ err = extract_group1_elem(bm, pmm_block,
-+ pmm_adc_ids_2, ARRAY_SIZE(pmm_adc_ids_2),
-+ 0xFFFFFFFF, 0);
-+ if (err)
-+ return err;
-+ err = extract_group1_elem(bm, pmm_block,
-+ pmm_adc_ids_3, ARRAY_SIZE(pmm_adc_ids_3),
-+ 0xFFFFFFFF, 0x0000FFFF);
-+ if (err)
-+ return err;
-+
-+ return 0;
-+}
-+
-+static int n810bm_parse_pmm_group2(struct n810bm *bm,
-+ const struct firmware *pmm_block)
-+{
-+ dev_err(&bm->pdev->dev, "TODO: CAL BME PMM group 2 parser not implemented, yet");
-+ return -EOPNOTSUPP;
-+}
-+
-+static void n810bm_adc_calib_set_defaults(struct n810bm *bm)
-+{
-+ struct n810bm_adc_calib *adc_calib;
-+ unsigned int i;
-+
-+ static const struct n810bm_adc_calib defaults[] = {
-+ /* ADC group-nr 0 */
-+ {
-+ .id = N810BM_PMM_ADC_HEADSET,
-+ .flags = 0x00,
-+ .adc_groupnr = 0,
-+ }, {
-+ .id = N810BM_PMM_ADC_HOOKDET,
-+ .flags = 0x00,
-+ .adc_groupnr = 0,
-+ }, {
-+ .id = N810BM_PMM_ADC_RFGP,
-+ .flags = 0x00,
-+ .adc_groupnr = 0,
-+ }, {
-+ .id = N810BM_PMM_ADC_LIGHTSENS,
-+ .flags = 0x00,
-+ .adc_groupnr = 0,
-+ }, {
-+ .id = N810BM_PMM_ADC_WBTX,
-+ .flags = 0x00,
-+ .adc_groupnr = 0,
-+ }, {
-+ .id = N810BM_PMM_ADC_RETUTEMP,
-+ .flags = 0x00,
-+ .adc_groupnr = 0,
-+ }, {
-+ .id = N810BM_PMM_ADC_GND2,
-+ .flags = 0x00,
-+ .adc_groupnr = 0,
-+ },
-+ /* ADC group-nr 1 */
-+ {
-+ .id = N810BM_PMM_ADC_0xFE,
-+ .flags = 0x05,
-+ .adc_groupnr = 1,
-+ .field1 = (u32)-2,
-+ .field2 = 13189,
-+ }, {
-+ .id = N810BM_PMM_ADC_BATVOLT,
-+ .flags = 0x01,
-+ .adc_groupnr = 1,
-+ .field1 = 2527,
-+ .field2 = 21373,
-+ }, {
-+ .id = N810BM_PMM_ADC_CHGVOLT,
-+ .flags = 0x01,
-+ .adc_groupnr = 1,
-+ .field1 = 0,
-+ .field2 = 129848,
-+ }, {
-+ .id = N810BM_PMM_ADC_BKUPVOLT,
-+ .flags = 0x01,
-+ .adc_groupnr = 1,
-+ .field1 = 0,
-+ .field2 = 20000,
-+ }, {
-+ .id = N810BM_PMM_ADC_BATCURR,
-+ .flags = 0x06,
-+ .adc_groupnr = 1,
-+ .field1 = 0,
-+ .field2 = 9660,
-+ },
-+ /* ADC group-nr 2 */
-+ {
-+ .id = N810BM_PMM_ADC_BSI,
-+ .flags = 0x02,
-+ .adc_groupnr = 2,
-+ .field1 = 1169,
-+ .field2 = 0,
-+ },
-+ /* ADC group-nr 3 */
-+ {
-+ .id = N810BM_PMM_ADC_BATTEMP,
-+ .flags = 0x03,
-+ .adc_groupnr = 3,
-+ .field1 = 265423000,
-+ .field2 = 298,
-+ },
-+ /* ADC group-nr 4 */
-+ {
-+ .id = N810BM_PMM_ADC_LIGHTTEMP,
-+ .flags = 0x04,
-+ .adc_groupnr = 4,
-+ .field1 = 19533778,
-+ .field2 = 308019670,
-+ .field3 = 4700,
-+ .field4 = 2500,
-+ },
-+ };
-+
-+ /* Clear the array */
-+ memset(&bm->calib.adc, 0, sizeof(bm->calib.adc));
-+ for (i = 0; i < ARRAY_SIZE(bm->calib.adc); i++)
-+ bm->calib.adc[i].flags = 0xFF;
-+
-+ /* Copy the defaults */
-+ for (i = 0; i < ARRAY_SIZE(defaults); i++) {
-+ adc_calib = n810bm_get_adc_calib(bm, defaults[i].id);
-+ if (WARN_ON(!adc_calib))
-+ continue;
-+ *adc_calib = defaults[i];
-+ }
-+}
-+
-+static int n810bm_parse_pmm_block(struct n810bm *bm,
-+ const struct firmware *pmm_block)
-+{
-+ u8 byte;
-+ int err;
-+ unsigned int i, count;
-+ struct n810bm_adc_calib *adc_calib;
-+
-+ /* Initialize to defaults */
-+ n810bm_adc_calib_set_defaults(bm);
-+
-+ /* Parse the PMM data */
-+ err = pmm_record_get(bm, pmm_block, &byte, sizeof(byte),
-+ 1, 0, 0); /* group 1 / element 0 */
-+ err |= (byte != 0x01);
-+ err |= pmm_record_get(bm, pmm_block, &byte, sizeof(byte),
-+ 1, 1, 0); /* group 1 / element 1 */
-+ err |= (byte != 0x01);
-+ if (err)
-+ err = n810bm_parse_pmm_group2(bm, pmm_block);
-+ else
-+ err = n810bm_parse_pmm_group1(bm, pmm_block);
-+ if (err)
-+ return err;
-+
-+ /* Sanity checks */
-+ for (i = 0, count = 0; i < ARRAY_SIZE(bm->calib.adc); i++) {
-+ adc_calib = &bm->calib.adc[i];
-+ if (adc_calib->flags == 0xFF)
-+ continue;
-+ switch (adc_calib->id) {
-+ case N810BM_PMM_ADC_BATVOLT:
-+ if (adc_calib->field1 < 2400 ||
-+ adc_calib->field1 > 2700)
-+ goto value_check_fail;
-+ if (adc_calib->field2 < 20000 ||
-+ adc_calib->field2 > 23000)
-+ goto value_check_fail;
-+ count++;
-+ break;
-+ case N810BM_PMM_ADC_BSI:
-+ if (adc_calib->field1 < 1100 ||
-+ adc_calib->field1 > 1300)
-+ goto value_check_fail;
-+ count++;
-+ break;
-+ case N810BM_PMM_ADC_BATCURR:
-+ if (adc_calib->field2 < 7000 ||
-+ adc_calib->field2 > 12000)
-+ goto value_check_fail;
-+ count++;
-+ break;
-+ case N810BM_PMM_ADC_0xFE:
-+ if ((s32)adc_calib->field1 > 14 ||
-+ (s32)adc_calib->field1 < -14)
-+ goto value_check_fail;
-+ if (adc_calib->field2 < 13000 ||
-+ adc_calib->field2 > 13350)
-+ goto value_check_fail;
-+ count++;
-+ break;
-+ case N810BM_PMM_ADC_CHGVOLT:
-+ case N810BM_PMM_ADC_BATTEMP:
-+ case N810BM_PMM_ADC_BKUPVOLT:
-+ count++;
-+ break;
-+ case N810BM_PMM_ADC_GND2:
-+ case N810BM_PMM_ADC_HOOKDET:
-+ case N810BM_PMM_ADC_LIGHTSENS:
-+ case N810BM_PMM_ADC_HEADSET:
-+ case N810BM_PMM_ADC_LIGHTTEMP:
-+ case N810BM_PMM_ADC_RFGP:
-+ case N810BM_PMM_ADC_WBTX:
-+ case N810BM_PMM_ADC_RETUTEMP:
-+ break;
-+ }
-+ dev_dbg(&bm->pdev->dev,
-+ "ADC 0x%02X calib: 0x%02X 0x%02X 0x%08X 0x%08X 0x%04X 0x%04X",
-+ adc_calib->id, adc_calib->flags, adc_calib->adc_groupnr,
-+ adc_calib->field1, adc_calib->field2,
-+ adc_calib->field3, adc_calib->field4);
-+ }
-+ if (count != 7) {
-+ dev_err(&bm->pdev->dev, "PMM sanity check: Did not find "
-+ "all required values (count=%u)", count);
-+ goto check_fail;
-+ }
-+
-+ return 0;
-+
-+value_check_fail:
-+ dev_err(&bm->pdev->dev, "PMM image sanity check failed "
-+ "(id=%02X, field1=%08X, field2=%08X)",
-+ adc_calib->id, adc_calib->field1, adc_calib->field2);
-+check_fail:
-+ return -EILSEQ;
-+}
-+
-+/* Set the current measure timer that triggers on Tahvo IRQ 7
-+ * An interval of zero disables the timer. */
-+static void n810bm_set_current_measure_timer(struct n810bm *bm,
-+ u16 millisec_interval)
-+{
-+ u16 value = millisec_interval;
-+
-+ if (value <= 0xF905) {
-+ value = ((u64)0x10624DD3 * (u64)(value + 0xF9)) >> 32;
-+ value /= 16;
-+ } else
-+ value = 0xFF;
-+
-+ tahvo_write(bm, TAHVO_REG_BATCURRTIMER, value & 0xFF);
-+
-+ tahvo_set(bm, TAHVO_REG_CHGCTL,
-+ TAHVO_REG_CHGCTL_CURTIMRST);
-+ tahvo_clear(bm, TAHVO_REG_CHGCTL,
-+ TAHVO_REG_CHGCTL_CURTIMRST);
-+
-+ if (millisec_interval) {
-+ if (!bm->tahvo_irq_enabled) {
-+ bm->tahvo_irq_enabled = 1;
-+ enable_irq(bm->tahvo_irq);
-+ }
-+ } else {
-+ if (bm->tahvo_irq_enabled) {
-+ bm->tahvo_irq_enabled = 0;
-+ disable_irq_nosync(bm->tahvo_irq);
-+ }
-+ }
-+
-+ //TODO also do a software timer for safety.
-+}
-+
-+static void n810bm_enable_current_measure(struct n810bm *bm)
-+{
-+ WARN_ON(bm->current_measure_enabled < 0);
-+ if (!bm->current_measure_enabled) {
-+ /* Enable the current measurement circuitry */
-+ tahvo_set(bm, TAHVO_REG_CHGCTL,
-+ TAHVO_REG_CHGCTL_CURMEAS);
-+ dev_dbg(&bm->pdev->dev,
-+ "Current measurement circuitry enabled");
-+ }
-+ bm->current_measure_enabled++;
-+}
-+
-+static void n810bm_disable_current_measure(struct n810bm *bm)
-+{
-+ bm->current_measure_enabled--;
-+ WARN_ON(bm->current_measure_enabled < 0);
-+ if (!bm->current_measure_enabled) {
-+ /* Disable the current measurement circuitry */
-+ tahvo_clear(bm, TAHVO_REG_CHGCTL,
-+ TAHVO_REG_CHGCTL_CURMEAS);
-+ dev_dbg(&bm->pdev->dev,
-+ "Current measurement circuitry disabled");
-+ }
-+}
-+
-+/* Measure the actual battery current. Returns a signed value in mA.
-+ * Does only work, if current measurement was enabled. */
-+static int n810bm_measure_batt_current(struct n810bm *bm)
-+{
-+ u16 retval;
-+ int adc = 0, ma, i;
-+
-+ if (WARN_ON(bm->current_measure_enabled <= 0))
-+ return 0;
-+ for (i = 0; i < 3; i++) {
-+ retval = tahvo_read(bm, TAHVO_REG_BATCURR);
-+ adc += (s16)retval; /* Value is signed */
-+ }
-+ adc /= 3;
-+
-+ //TODO convert to mA
-+ ma = adc;
-+
-+ return ma;
-+}
-+
-+/* Requires bm->mutex locked */
-+static int n810bm_measure_batt_current_async(struct n810bm *bm)
-+{
-+ int ma;
-+ bool charging = lipocharge_is_charging(&bm->charger);
-+
-+ n810bm_enable_current_measure(bm);
-+ if (!charging)
-+ WARN_ON(bm->active_current_pwm != 0);
-+ tahvo_maskset(bm, TAHVO_REG_CHGCTL,
-+ TAHVO_REG_CHGCTL_EN |
-+ TAHVO_REG_CHGCTL_PWMOVR |
-+ TAHVO_REG_CHGCTL_PWMOVRZERO,
-+ TAHVO_REG_CHGCTL_EN |
-+ TAHVO_REG_CHGCTL_PWMOVR |
-+ (charging ? 0 : TAHVO_REG_CHGCTL_PWMOVRZERO));
-+ ma = n810bm_measure_batt_current(bm);
-+ tahvo_maskset(bm, TAHVO_REG_CHGCTL,
-+ TAHVO_REG_CHGCTL_EN |
-+ TAHVO_REG_CHGCTL_PWMOVR |
-+ TAHVO_REG_CHGCTL_PWMOVRZERO,
-+ (charging ? TAHVO_REG_CHGCTL_EN : 0));
-+ n810bm_disable_current_measure(bm);
-+
-+ return ma;
-+}
-+
-+static int adc_sanity_check(struct n810bm *bm, unsigned int channel)
-+{
-+ int value;
-+
-+ value = retu_read_adc(&n810bm_retu_device->dev, channel);
-+ if (value < 0) {
-+ dev_err(&bm->pdev->dev, "Failed to read GND ADC channel %u",
-+ channel);
-+ return -EIO;
-+ }
-+ dev_dbg(&bm->pdev->dev,
-+ "GND ADC channel %u sanity check got value: %d",
-+ channel, value);
-+ if (value > 5) {
-+ n810bm_emergency(bm, "GND ADC sanity check failed");
-+ return -EIO;
-+ }
-+
-+ return 0;
-+}
-+
-+static int n810bm_check_adc_sanity(struct n810bm *bm)
-+{
-+ int err;
-+
-+ /* Discard one conversion */
-+ retu_write(bm, RETU_REG_ADCSCR, 0);
-+ retu_read_adc(&n810bm_retu_device->dev, RETU_ADC_GND2);
-+
-+ err = adc_sanity_check(bm, RETU_ADC_GND2);
-+ if (err)
-+ return err;
-+
-+ return 0;
-+}
-+
-+/* Measure the battery voltage. Returns the value in mV (or negative value on error). */
-+static int n810bm_measure_batt_voltage(struct n810bm *bm)
-+{
-+ int adc;
-+ unsigned int mv;
-+ const unsigned int scale = 1000;
-+
-+ adc = retu_adc_average(bm, RETU_ADC_BATTVOLT, 5);
-+ if (adc < 0)
-+ return adc;
-+ if (adc <= 0x37)
-+ return 2800;
-+ mv = 2800 + ((adc - 0x37) * (((4200 - 2800) * scale) / (0x236 - 0x37))) / scale;
-+
-+ //TODO compensate for power consumption
-+ //TODO honor calibration values
-+
-+ return mv;
-+}
-+
-+/* Measure the charger voltage. Returns the value in mV (or negative value on error). */
-+static int n810bm_measure_charger_voltage(struct n810bm *bm)
-+{
-+ int adc;
-+ unsigned int mv;
-+
-+ adc = retu_adc_average(bm, RETU_ADC_CHGVOLT, 5);
-+ if (adc < 0)
-+ return adc;
-+ //TODO convert to mV
-+ mv = adc;
-+
-+ return mv;
-+}
-+
-+/* Measure backup battery voltage. Returns the value in mV (or negative value on error). */
-+static int n810bm_measure_backup_batt_voltage(struct n810bm *bm)
-+{
-+ int adc;
-+ unsigned int mv;
-+
-+ adc = retu_adc_average(bm, RETU_ADC_BKUPVOLT, 3);
-+ if (adc < 0)
-+ return adc;
-+ //TODO convert to mV
-+ mv = adc;
-+
-+ return mv;
-+}
-+
-+/* Measure the battery temperature. Returns the value in K (or negative value on error). */
-+static int n810bm_measure_batt_temp(struct n810bm *bm)
-+{
-+ int adc;
-+ unsigned int k;
-+
-+ adc = retu_adc_average(bm, RETU_ADC_BATTEMP, 3);
-+ if (adc < 0)
-+ return adc;
-+ //TODO convert to K
-+ k = adc;
-+
-+ return k;
-+}
-+
-+/* Read the battery capacity via BSI pin. */
-+static enum n810bm_capacity n810bm_read_batt_capacity(struct n810bm *bm)
-+{
-+ int adc;
-+ const unsigned int hyst = 20;
-+
-+ adc = retu_adc_average(bm, RETU_ADC_BSI, 5);
-+ if (adc < 0) {
-+ dev_err(&bm->pdev->dev, "Failed to read BSI ADC");
-+ return N810BM_CAP_UNKNOWN;
-+ }
-+
-+ if (adc >= 0x3B5 - hyst && adc <= 0x3B5 + hyst)
-+ return N810BM_CAP_1500MAH;
-+
-+ dev_err(&bm->pdev->dev, "Capacity indicator 0x%X unknown", adc);
-+
-+ return N810BM_CAP_UNKNOWN;
-+}
-+
-+/* Convert a battery voltage (in mV) to percentage. */
-+static unsigned int n810bm_mvolt2percent(unsigned int mv)
-+{
-+ const unsigned int minv = 3700;
-+ const unsigned int maxv = 4150;
-+ unsigned int percent;
-+
-+ mv = clamp(mv, minv, maxv);
-+ percent = (mv - minv) * 100 / (maxv - minv);
-+
-+ return percent;
-+}
-+
-+static void n810bm_start_charge(struct n810bm *bm)
-+{
-+ int err;
-+
-+ WARN_ON(!bm->battery_present);
-+ WARN_ON(!bm->charger_present);
-+
-+ /* Set PWM to zero */
-+ bm->active_current_pwm = 0;
-+ tahvo_write(bm, TAHVO_REG_CHGCURR, bm->active_current_pwm);
-+
-+ /* Charge global enable */
-+ tahvo_maskset(bm, TAHVO_REG_CHGCTL,
-+ TAHVO_REG_CHGCTL_EN |
-+ TAHVO_REG_CHGCTL_PWMOVR |
-+ TAHVO_REG_CHGCTL_PWMOVRZERO,
-+ TAHVO_REG_CHGCTL_EN);
-+
-+ WARN_ON((int)bm->capacity <= 0);
-+ bm->charger.capacity = bm->capacity;
-+ err = lipocharge_start(&bm->charger);
-+ WARN_ON(err);
-+
-+ /* Initialize current measurement circuitry */
-+ n810bm_enable_current_measure(bm);
-+ n810bm_set_current_measure_timer(bm, 250);
-+
-+ dev_info(&bm->pdev->dev, "Charging battery");
-+ n810bm_notify_charger_state(bm);
-+ n810bm_notify_charger_pwm(bm);
-+}
-+
-+static void n810bm_stop_charge(struct n810bm *bm)
-+{
-+ if (lipocharge_is_charging(&bm->charger)) {
-+ n810bm_set_current_measure_timer(bm, 0);
-+ n810bm_disable_current_measure(bm);
-+ }
-+ lipocharge_stop(&bm->charger);
-+
-+ /* Set PWM to zero */
-+ bm->active_current_pwm = 0;
-+ tahvo_write(bm, TAHVO_REG_CHGCURR, bm->active_current_pwm);
-+
-+ /* Charge global disable */
-+ tahvo_maskset(bm, TAHVO_REG_CHGCTL,
-+ TAHVO_REG_CHGCTL_EN |
-+ TAHVO_REG_CHGCTL_PWMOVR |
-+ TAHVO_REG_CHGCTL_PWMOVRZERO,
-+ 0);
-+
-+ dev_info(&bm->pdev->dev, "Not charging battery");
-+ n810bm_notify_charger_state(bm);
-+ n810bm_notify_charger_pwm(bm);
-+}
-+
-+/* Periodic check */
-+static void n810bm_periodic_check_work(struct work_struct *work)
-+{
-+ struct n810bm *bm = container_of(to_delayed_work(work),
-+ struct n810bm, periodic_check_work);
-+ u16 status;
-+ bool battery_was_present, charger_was_present;
-+ int mv;
-+
-+ mutex_lock(&bm->mutex);
-+
-+ status = retu_read(bm, RETU_REG_STATUS);
-+ battery_was_present = bm->battery_present;
-+ charger_was_present = bm->charger_present;
-+ bm->battery_present = !!(status & RETU_REG_STATUS_BATAVAIL);
-+ bm->charger_present = !!(status & RETU_REG_STATUS_CHGPLUG);
-+
-+ if (bm->battery_present != battery_was_present) {
-+ /* Battery state changed */
-+ if (bm->battery_present) {
-+ bm->capacity = n810bm_read_batt_capacity(bm);
-+ if (bm->capacity == N810BM_CAP_UNKNOWN) {
-+ dev_err(&bm->pdev->dev, "Unknown battery detected");
-+ } else {
-+ dev_info(&bm->pdev->dev, "Detected %u mAh battery",
-+ (unsigned int)bm->capacity);
-+ }
-+ } else {
-+ bm->capacity = N810BM_CAP_NONE;
-+ dev_info(&bm->pdev->dev, "The main battery was removed");
-+ //TODO disable charging
-+ }
-+ }
-+
-+ if (bm->charger_present != charger_was_present) {
-+ /* Charger state changed */
-+ dev_info(&bm->pdev->dev, "The charger was %s",
-+ bm->charger_present ? "plugged in" : "removed");
-+ n810bm_notify_charger_present(bm);
-+ }
-+
-+ if ((bm->battery_present && !bm->charger_present) ||
-+ !n810bm_known_battery_present(bm)){
-+ /* We're draining the battery */
-+ mv = n810bm_measure_batt_voltage(bm);
-+ if (mv < 0) {
-+ n810bm_emergency(bm,
-+ "check: Failed to measure voltage");
-+ }
-+ if (mv < N810BM_MIN_VOLTAGE_THRES) {
-+ n810bm_emergency(bm,
-+ "check: Minimum voltage threshold reached");
-+ }
-+ }
-+
-+ if (bm->charger_present && n810bm_known_battery_present(bm)) {
-+ /* Known battery and charger are connected */
-+ if (bm->charger_enabled) {
-+ /* Charger is enabled */
-+ if (!lipocharge_is_charging(&bm->charger)) {
-+ //TODO start charging, if battery is below some threshold
-+ n810bm_start_charge(bm);
-+ }
-+ }
-+ }
-+
-+ if (lipocharge_is_charging(&bm->charger) && !bm->charger_present) {
-+ /* Charger was unplugged. */
-+ n810bm_stop_charge(bm);
-+ }
-+
-+ mutex_unlock(&bm->mutex);
-+ schedule_delayed_work(&bm->periodic_check_work,
-+ round_jiffies_relative(N810BM_CHECK_INTERVAL));
-+}
-+
-+/*XXX
-+static void n810bm_adc_irq_handler(unsigned long data)
-+{
-+ struct n810bm *bm = (struct n810bm *)data;
-+
-+ retu_ack_irq(RETU_INT_ADCS);
-+ //TODO
-+dev_info(&bm->pdev->dev, "ADC interrupt triggered\n");
-+}
-+*/
-+
-+static irqreturn_t n810bm_tahvo_current_measure_irq_handler(int irq, void *data)
-+{
-+ struct n810bm *bm = data;
-+ int res, ma, mv, temp;
-+
-+ mutex_lock(&bm->mutex);
-+ if (!lipocharge_is_charging(&bm->charger))
-+ goto out_unlock;
-+
-+ tahvo_maskset(bm, TAHVO_REG_CHGCTL,
-+ TAHVO_REG_CHGCTL_PWMOVR |
-+ TAHVO_REG_CHGCTL_PWMOVRZERO,
-+ TAHVO_REG_CHGCTL_PWMOVR);
-+ ma = n810bm_measure_batt_current(bm);
-+ tahvo_maskset(bm, TAHVO_REG_CHGCTL,
-+ TAHVO_REG_CHGCTL_PWMOVR |
-+ TAHVO_REG_CHGCTL_PWMOVRZERO,
-+ TAHVO_REG_CHGCTL_PWMOVR |
-+ TAHVO_REG_CHGCTL_PWMOVRZERO);
-+ msleep(10);
-+ mv = n810bm_measure_batt_voltage(bm);
-+ tahvo_maskset(bm, TAHVO_REG_CHGCTL,
-+ TAHVO_REG_CHGCTL_PWMOVR |
-+ TAHVO_REG_CHGCTL_PWMOVRZERO,
-+ 0);
-+ temp = n810bm_measure_batt_temp(bm);
-+ if (WARN_ON(mv < 0))
-+ goto out_unlock;
-+ if (WARN_ON(temp < 0))
-+ goto out_unlock;
-+
-+ if (bm->verbose_charge_log) {
-+ dev_info(&bm->pdev->dev,
-+ "Battery charge state: %d mV, %d mA (%s)",
-+ mv, ma,
-+ (ma <= 0) ? "discharging" : "charging");
-+ }
-+ res = lipocharge_update_state(&bm->charger, mv, ma, temp);
-+ if (res) {
-+ if (res > 0)
-+ dev_info(&bm->pdev->dev, "Battery fully charged");
-+ n810bm_stop_charge(bm);
-+ }
-+out_unlock:
-+ mutex_unlock(&bm->mutex);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+#define DEFINE_ATTR_NOTIFY(attr_name) \
-+ void n810bm_notify_##attr_name(struct n810bm *bm) \
-+ { \
-+ set_bit(N810BM_NOTIFY_##attr_name, &bm->notify_flags); \
-+ wmb(); \
-+ schedule_work(&bm->notify_work); \
-+ }
-+
-+#define DEFINE_SHOW_INT_FUNC(name, member) \
-+ static ssize_t n810bm_attr_##name##_show(struct device *dev, \
-+ struct device_attribute *attr, \
-+ char *buf) \
-+ { \
-+ struct n810bm *bm = device_to_n810bm(dev); \
-+ ssize_t count; \
-+ \
-+ mutex_lock(&bm->mutex); \
-+ count = snprintf(buf, PAGE_SIZE, "%d\n", (int)(bm->member)); \
-+ mutex_unlock(&bm->mutex); \
-+ \
-+ return count; \
-+ }
-+
-+#define DEFINE_STORE_INT_FUNC(name, member) \
-+ static ssize_t n810bm_attr_##name##_store(struct device *dev, \
-+ struct device_attribute *attr,\
-+ const char *buf, size_t count)\
-+ { \
-+ struct n810bm *bm = device_to_n810bm(dev); \
-+ long val; \
-+ int err; \
-+ \
-+ mutex_lock(&bm->mutex); \
-+ err = strict_strtol(buf, 0, &val); \
-+ if (!err) \
-+ bm->member = (typeof(bm->member))val; \
-+ mutex_unlock(&bm->mutex); \
-+ \
-+ return err ? err : count; \
-+ }
-+
-+#define DEFINE_ATTR_SHOW_INT(name, member) \
-+ DEFINE_SHOW_INT_FUNC(name, member) \
-+ static DEVICE_ATTR(name, S_IRUGO, \
-+ n810bm_attr_##name##_show, NULL);
-+
-+#define DEFINE_ATTR_SHOW_STORE_INT(name, member) \
-+ DEFINE_SHOW_INT_FUNC(name, member) \
-+ DEFINE_STORE_INT_FUNC(name, member) \
-+ static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, \
-+ n810bm_attr_##name##_show, \
-+ n810bm_attr_##name##_store);
-+
-+DEFINE_ATTR_SHOW_INT(battery_present, battery_present);
-+DEFINE_ATTR_SHOW_INT(charger_present, charger_present);
-+static DEFINE_ATTR_NOTIFY(charger_present);
-+DEFINE_ATTR_SHOW_INT(charger_state, charger.state);
-+static DEFINE_ATTR_NOTIFY(charger_state);
-+DEFINE_ATTR_SHOW_INT(charger_pwm, active_current_pwm);
-+static DEFINE_ATTR_NOTIFY(charger_pwm);
-+DEFINE_ATTR_SHOW_STORE_INT(charger_enable, charger_enabled);
-+DEFINE_ATTR_SHOW_STORE_INT(charger_verbose, verbose_charge_log);
-+
-+static ssize_t n810bm_attr_battery_level_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct n810bm *bm = device_to_n810bm(dev);
-+ ssize_t count = -ENODEV;
-+ int millivolt;
-+
-+ mutex_lock(&bm->mutex);
-+ if (!bm->battery_present || lipocharge_is_charging(&bm->charger))
-+ millivolt = 0;
-+ else
-+ millivolt = n810bm_measure_batt_voltage(bm);
-+ if (millivolt >= 0) {
-+ count = snprintf(buf, PAGE_SIZE, "%u\n",
-+ n810bm_mvolt2percent(millivolt));
-+ }
-+ mutex_unlock(&bm->mutex);
-+
-+ return count;
-+}
-+static DEVICE_ATTR(battery_level, S_IRUGO,
-+ n810bm_attr_battery_level_show, NULL);
-+
-+static ssize_t n810bm_attr_battery_capacity_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct n810bm *bm = device_to_n810bm(dev);
-+ ssize_t count;
-+ int capacity = 0;
-+
-+ mutex_lock(&bm->mutex);
-+ if (n810bm_known_battery_present(bm))
-+ capacity = (int)bm->capacity;
-+ count = snprintf(buf, PAGE_SIZE, "%d\n", capacity);
-+ mutex_unlock(&bm->mutex);
-+
-+ return count;
-+}
-+static DEVICE_ATTR(battery_capacity, S_IRUGO,
-+ n810bm_attr_battery_capacity_show, NULL);
-+
-+static ssize_t n810bm_attr_battery_temp_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct n810bm *bm = device_to_n810bm(dev);
-+ ssize_t count = -ENODEV;
-+ int k;
-+
-+ mutex_lock(&bm->mutex);
-+ k = n810bm_measure_batt_temp(bm);
-+ if (k >= 0)
-+ count = snprintf(buf, PAGE_SIZE, "%d\n", k);
-+ mutex_unlock(&bm->mutex);
-+
-+ return count;
-+}
-+static DEVICE_ATTR(battery_temp, S_IRUGO,
-+ n810bm_attr_battery_temp_show, NULL);
-+
-+static ssize_t n810bm_attr_charger_voltage_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct n810bm *bm = device_to_n810bm(dev);
-+ ssize_t count = -ENODEV;
-+ int mv = 0;
-+
-+ mutex_lock(&bm->mutex);
-+ if (bm->charger_present)
-+ mv = n810bm_measure_charger_voltage(bm);
-+ if (mv >= 0)
-+ count = snprintf(buf, PAGE_SIZE, "%d\n", mv);
-+ mutex_unlock(&bm->mutex);
-+
-+ return count;
-+}
-+static DEVICE_ATTR(charger_voltage, S_IRUGO,
-+ n810bm_attr_charger_voltage_show, NULL);
-+
-+static ssize_t n810bm_attr_backup_battery_voltage_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct n810bm *bm = device_to_n810bm(dev);
-+ ssize_t count = -ENODEV;
-+ int mv;
-+
-+ mutex_lock(&bm->mutex);
-+ mv = n810bm_measure_backup_batt_voltage(bm);
-+ if (mv >= 0)
-+ count = snprintf(buf, PAGE_SIZE, "%d\n", mv);
-+ mutex_unlock(&bm->mutex);
-+
-+ return count;
-+}
-+static DEVICE_ATTR(backup_battery_voltage, S_IRUGO,
-+ n810bm_attr_backup_battery_voltage_show, NULL);
-+
-+static ssize_t n810bm_attr_battery_current_show(struct device *dev,
-+ struct device_attribute *attr,
-+ char *buf)
-+{
-+ struct n810bm *bm = device_to_n810bm(dev);
-+ ssize_t count = -ENODEV;
-+ int ma = 0;
-+
-+ mutex_lock(&bm->mutex);
-+ if (bm->battery_present)
-+ ma = n810bm_measure_batt_current_async(bm);
-+ count = snprintf(buf, PAGE_SIZE, "%d\n", ma);
-+ mutex_unlock(&bm->mutex);
-+
-+ return count;
-+}
-+static DEVICE_ATTR(battery_current, S_IRUGO,
-+ n810bm_attr_battery_current_show, NULL);
-+
-+static const struct device_attribute *n810bm_attrs[] = {
-+ &dev_attr_battery_present,
-+ &dev_attr_battery_level,
-+ &dev_attr_battery_current,
-+ &dev_attr_battery_capacity,
-+ &dev_attr_battery_temp,
-+ &dev_attr_backup_battery_voltage,
-+ &dev_attr_charger_present,
-+ &dev_attr_charger_state,
-+ &dev_attr_charger_verbose,
-+ &dev_attr_charger_voltage,
-+ &dev_attr_charger_enable,
-+ &dev_attr_charger_pwm,
-+};
-+
-+static void n810bm_notify_work(struct work_struct *work)
-+{
-+ struct n810bm *bm = container_of(work, struct n810bm, notify_work);
-+ unsigned long notify_flags;
-+
-+ notify_flags = xchg(&bm->notify_flags, 0);
-+ mb();
-+
-+#define do_notify(attr_name) \
-+ do { \
-+ if (notify_flags & (1 << N810BM_NOTIFY_##attr_name)) { \
-+ sysfs_notify(&bm->pdev->dev.kobj, NULL, \
-+ dev_attr_##attr_name.attr.name); \
-+ } \
-+ } while (0)
-+
-+ do_notify(charger_present);
-+ do_notify(charger_state);
-+ do_notify(charger_pwm);
-+}
-+
-+static int n810bm_charger_set_current_pwm(struct lipocharge *c,
-+ unsigned int duty_cycle)
-+{
-+ struct n810bm *bm = container_of(c, struct n810bm, charger);
-+ int err = -EINVAL;
-+
-+ WARN_ON(!mutex_is_locked(&bm->mutex));
-+ if (WARN_ON(duty_cycle > 0xFF))
-+ goto out;
-+ if (WARN_ON(!bm->charger_enabled))
-+ goto out;
-+ if (WARN_ON(!bm->battery_present || !bm->charger_present))
-+ goto out;
-+
-+ if (duty_cycle != bm->active_current_pwm) {
-+ bm->active_current_pwm = duty_cycle;
-+ tahvo_write(bm, TAHVO_REG_CHGCURR, duty_cycle);
-+ n810bm_notify_charger_pwm(bm);
-+ }
-+
-+ err = 0;
-+out:
-+
-+ return err;
-+}
-+
-+static void n810bm_charger_emergency(struct lipocharge *c)
-+{
-+ struct n810bm *bm = container_of(c, struct n810bm, charger);
-+
-+ n810bm_emergency(bm, "Battery charger fault");
-+}
-+
-+static void n810bm_hw_exit(struct n810bm *bm)
-+{
-+ n810bm_stop_charge(bm);
-+ retu_write(bm, RETU_REG_ADCSCR, 0);
-+}
-+
-+static int n810bm_hw_init(struct n810bm *bm)
-+{
-+ int err;
-+
-+ err = n810bm_check_adc_sanity(bm);
-+ if (err)
-+ return err;
-+
-+ n810bm_stop_charge(bm);
-+
-+ return 0;
-+}
-+
-+static void n810bm_cancel_and_flush_work(struct n810bm *bm)
-+{
-+ cancel_delayed_work_sync(&bm->periodic_check_work);
-+ cancel_work_sync(&bm->notify_work);
-+ flush_scheduled_work();
-+}
-+
-+static int n810bm_device_init(struct n810bm *bm)
-+{
-+ int attr_index;
-+ int err;
-+
-+ bm->charger.rate = LIPORATE_p6C;
-+ bm->charger.top_voltage = 4100;
-+ bm->charger.duty_cycle_max = 0xFF;
-+ bm->charger.set_current_pwm = n810bm_charger_set_current_pwm;
-+ bm->charger.emergency = n810bm_charger_emergency;
-+ lipocharge_init(&bm->charger, &bm->pdev->dev);
-+
-+ err = n810bm_hw_init(bm);
-+ if (err)
-+ goto error;
-+ for (attr_index = 0; attr_index < ARRAY_SIZE(n810bm_attrs); attr_index++) {
-+ err = device_create_file(&bm->pdev->dev, n810bm_attrs[attr_index]);
-+ if (err)
-+ goto err_unwind_attrs;
-+ }
-+/*XXX
-+ err = retu_request_irq(RETU_INT_ADCS,
-+ n810bm_adc_irq_handler,
-+ (unsigned long)bm, "n810bm");
-+ if (err)
-+ goto err_unwind_attrs;
-+*/
-+ bm->tahvo_irq = platform_get_irq(n810bm_tahvo_device, 0);
-+ err = request_threaded_irq(bm->tahvo_irq, NULL,
-+ n810bm_tahvo_current_measure_irq_handler,
-+ IRQF_ONESHOT, "tahvo-n810bm", bm);
-+ if (err)
-+ goto err_free_retu_irq;
-+ disable_irq_nosync(bm->tahvo_irq);
-+ bm->tahvo_irq_enabled = 0;
-+
-+ schedule_delayed_work(&bm->periodic_check_work,
-+ round_jiffies_relative(N810BM_CHECK_INTERVAL));
-+
-+ bm->initialized = 1;
-+ dev_info(&bm->pdev->dev, "Battery management initialized");
-+
-+ return 0;
-+
-+err_free_retu_irq:
-+//XXX retu_free_irq(RETU_INT_ADCS);
-+err_unwind_attrs:
-+ for (attr_index--; attr_index >= 0; attr_index--)
-+ device_remove_file(&bm->pdev->dev, n810bm_attrs[attr_index]);
-+/*err_exit:*/
-+ n810bm_hw_exit(bm);
-+error:
-+ n810bm_cancel_and_flush_work(bm);
-+
-+ return err;
-+}
-+
-+static void n810bm_device_exit(struct n810bm *bm)
-+{
-+ int i;
-+
-+ if (!bm->initialized)
-+ return;
-+
-+ lipocharge_exit(&bm->charger);
-+ free_irq(bm->tahvo_irq, bm);
-+//XXX retu_free_irq(RETU_INT_ADCS);
-+ for (i = 0; i < ARRAY_SIZE(n810bm_attrs); i++)
-+ device_remove_file(&bm->pdev->dev, n810bm_attrs[i]);
-+
-+ n810bm_cancel_and_flush_work(bm);
-+
-+ n810bm_hw_exit(bm);
-+
-+ bm->initialized = 0;
-+}
-+
-+static void n810bm_pmm_block_found(const struct firmware *fw, void *context)
-+{
-+ struct n810bm *bm = context;
-+ int err;
-+
-+ if (!fw) {
-+ dev_err(&bm->pdev->dev,
-+ "CAL PMM block image file not found");
-+ goto err_release;
-+ }
-+ if (fw->size != N810BM_PMM_BLOCK_SIZE ||
-+ memcmp(fw->data, "BME-PMM-BLOCK01", 15) != 0) {
-+ dev_err(&bm->pdev->dev,
-+ "CAL PMM block image file has an invalid format");
-+ goto err_release;
-+ }
-+
-+ err = n810bm_parse_pmm_block(bm, fw);
-+ if (err)
-+ goto err_release;
-+ release_firmware(fw);
-+
-+ err = n810bm_device_init(bm);
-+ if (err) {
-+ dev_err(&bm->pdev->dev,
-+ "Failed to initialized battery management (%d)", err);
-+ goto error;
-+ }
-+
-+ return;
-+err_release:
-+ release_firmware(fw);
-+error:
-+ return;
-+}
-+
-+static int __devinit n810bm_probe(void)
-+{
-+ struct n810bm *bm;
-+ int err;
-+
-+ if (!n810bm_retu_device || !n810bm_tahvo_device)
-+ return 0;
-+
-+ bm = kzalloc(sizeof(*bm), GFP_KERNEL);
-+ if (!bm)
-+ return -ENOMEM;
-+ bm->pdev = n810bm_retu_device;
-+ platform_set_drvdata(n810bm_retu_device, bm);
-+ platform_set_drvdata(n810bm_tahvo_device, bm);
-+ mutex_init(&bm->mutex);
-+ INIT_DELAYED_WORK(&bm->periodic_check_work, n810bm_periodic_check_work);
-+ INIT_WORK(&bm->notify_work, n810bm_notify_work);
-+
-+ dev_info(&bm->pdev->dev, "Requesting CAL BME PMM block firmware file "
-+ N810BM_PMM_BLOCK_FILENAME);
-+ err = request_firmware_nowait(THIS_MODULE, 1,
-+ N810BM_PMM_BLOCK_FILENAME,
-+ &bm->pdev->dev, GFP_KERNEL,
-+ bm, n810bm_pmm_block_found);
-+ if (err) {
-+ dev_err(&bm->pdev->dev,
-+ "Failed to request CAL PMM block image file (%d)", err);
-+ goto err_free;
-+ }
-+
-+ return 0;
-+
-+err_free:
-+ kfree(bm);
-+
-+ return err;
-+}
-+
-+static void __devexit n810bm_remove(void)
-+{
-+ struct n810bm *bm;
-+
-+ if (!n810bm_retu_device || !n810bm_tahvo_device)
-+ return;
-+ bm = platform_get_drvdata(n810bm_retu_device);
-+
-+ n810bm_device_exit(bm);
-+
-+ kfree(bm);
-+ platform_set_drvdata(n810bm_retu_device, NULL);
-+ platform_set_drvdata(n810bm_tahvo_device, NULL);
-+}
-+
-+static int __devinit n810bm_retu_probe(struct platform_device *pdev)
-+{
-+ n810bm_retu_device = pdev;
-+ return n810bm_probe();
-+}
-+
-+static int __devexit n810bm_retu_remove(struct platform_device *pdev)
-+{
-+ n810bm_remove();
-+ n810bm_retu_device = NULL;
-+ return 0;
-+}
-+
-+static int __devinit n810bm_tahvo_probe(struct platform_device *pdev)
-+{
-+ n810bm_tahvo_device = pdev;
-+ return n810bm_probe();
-+}
-+
-+static int __devexit n810bm_tahvo_remove(struct platform_device *pdev)
-+{
-+ n810bm_remove();
-+ n810bm_tahvo_device = NULL;
-+ return 0;
-+}
-+
-+static struct platform_driver n810bm_retu_driver = {
-+ .remove = __devexit_p(n810bm_retu_remove),
-+ .driver = {
-+ .name = "retu-n810bm",
-+ }
-+};
-+
-+static struct platform_driver n810bm_tahvo_driver = {
-+ .remove = __devexit_p(n810bm_tahvo_remove),
-+ .driver = {
-+ .name = "tahvo-n810bm",
-+ }
-+};
-+
-+static int __init n810bm_modinit(void)
-+{
-+ int err;
-+
-+ err = platform_driver_probe(&n810bm_retu_driver, n810bm_retu_probe);
-+ if (err)
-+ return err;
-+ err = platform_driver_probe(&n810bm_tahvo_driver, n810bm_tahvo_probe);
-+ if (err) {
-+ platform_driver_unregister(&n810bm_retu_driver);
-+ return err;
-+ }
-+
-+ return 0;
-+}
-+module_init(n810bm_modinit);
-+
-+static void __exit n810bm_modexit(void)
-+{
-+ platform_driver_unregister(&n810bm_tahvo_driver);
-+ platform_driver_unregister(&n810bm_retu_driver);
-+}
-+module_exit(n810bm_modexit);
-+
-+MODULE_DESCRIPTION("Nokia n810 battery management");
-+MODULE_FIRMWARE(N810BM_PMM_BLOCK_FILENAME);
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Michael Buesch");
---- /dev/null
-+++ b/drivers/cbus/lipocharge.c
-@@ -0,0 +1,183 @@
-+/*
-+ * Generic LIPO battery charger
-+ *
-+ * Copyright (c) 2010-2011 Michael Buesch <mb@bu3sch.de>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#define DEBUG
-+
-+#include "lipocharge.h"
-+
-+#include <linux/slab.h>
-+
-+
-+/* Hysteresis constants */
-+#define CURRENT_HYST 30 /* mA */
-+#define VOLTAGE_HYST 10 /* mV */
-+
-+/* Threshold constants */
-+#define FINISH_CURRENT_PERCENT 3
-+
-+
-+/* Returns the requested first-stage charge current in mA */
-+static inline unsigned int get_stage1_charge_current(struct lipocharge *c)
-+{
-+ /* current = (capacity * C) */
-+ return c->capacity * c->rate / 1000;
-+}
-+
-+void lipocharge_init(struct lipocharge *c, struct device *dev)
-+{
-+ c->dev = dev;
-+ c->state = LIPO_IDLE;
-+}
-+
-+void lipocharge_exit(struct lipocharge *c)
-+{
-+ c->state = LIPO_IDLE;
-+}
-+
-+int lipocharge_start(struct lipocharge *c)
-+{
-+ int err;
-+
-+ if (c->state != LIPO_IDLE)
-+ return -EBUSY;
-+ if (!c->set_current_pwm || !c->emergency)
-+ return -EINVAL;
-+ if (!c->top_voltage || c->top_voltage > 4200)
-+ return -EINVAL;
-+
-+ c->active_duty_cycle = 0;
-+ err = c->set_current_pwm(c, c->active_duty_cycle);
-+ if (err)
-+ return err;
-+ c->state = LIPO_FIRST_STAGE;
-+
-+ return 0;
-+}
-+
-+void lipocharge_stop(struct lipocharge *c)
-+{
-+ if (c->state == LIPO_IDLE)
-+ return;
-+ c->state = LIPO_IDLE;
-+}
-+
-+static int lipocharge_increase_current(struct lipocharge *c,
-+ unsigned int inc_permille)
-+{
-+ int old_pwm, new_pwm;
-+
-+ if (c->active_duty_cycle >= c->duty_cycle_max)
-+ return 0;
-+
-+ old_pwm = c->active_duty_cycle;
-+ new_pwm = old_pwm + (c->duty_cycle_max * inc_permille / 1000);
-+ new_pwm = min(new_pwm, (int)c->duty_cycle_max);
-+ c->active_duty_cycle = new_pwm;
-+
-+ dev_dbg(c->dev, "lipo: Increasing duty_cycle by "
-+ "%u permille (0x%02X -> 0x%02X)",
-+ inc_permille, old_pwm, new_pwm);
-+
-+ return c->set_current_pwm(c, c->active_duty_cycle);
-+}
-+
-+static int lipocharge_decrease_current(struct lipocharge *c,
-+ unsigned int dec_permille)
-+{
-+ int old_pwm, new_pwm;
-+
-+ if (c->active_duty_cycle <= 0)
-+ return 0;
-+
-+ old_pwm = c->active_duty_cycle;
-+ new_pwm = old_pwm - (c->duty_cycle_max * dec_permille / 1000);
-+ new_pwm = max(0, new_pwm);
-+ c->active_duty_cycle = new_pwm;
-+
-+ dev_dbg(c->dev, "lipo: Decreasing duty_cycle by "
-+ "%u permille (0x%02X -> 0x%02X)",
-+ dec_permille, old_pwm, new_pwm);
-+
-+ return c->set_current_pwm(c, c->active_duty_cycle);
-+}
-+
-+/** lipocharge_update_state - Update the charge state
-+ * @c: The context.
-+ * @voltage_mV: The measured battery voltage.
-+ * @current_mA: The measured charge current.
-+ * negative -> drain.
-+ * positive -> charge.
-+ * @temp_K: Battery temperature in K.
-+ *
-+ * Returns 0 on success, -1 on error.
-+ * Returns 1, if the charging process is finished.
-+ */
-+int lipocharge_update_state(struct lipocharge *c,
-+ unsigned int voltage_mV,
-+ int current_mA,
-+ unsigned int temp_K)
-+{
-+ int requested_current, current_diff;
-+ int err;
-+ unsigned int permille;
-+
-+ //TODO temp
-+
-+restart:
-+ switch (c->state) {
-+ case LIPO_IDLE:
-+ dev_err(c->dev, "%s: called while idle", __func__);
-+ return -EINVAL;
-+ case LIPO_FIRST_STAGE: /* Constant current */
-+//printk("GOT %u %d %u\n", voltage_mV, current_mA, temp_K);
-+ if (voltage_mV >= c->top_voltage) {
-+ /* Float voltage reached.
-+ * Switch charger mode to "constant current" */
-+ c->state = LIPO_SECOND_STAGE;
-+ dev_dbg(c->dev, "Switched to second charging stage.");
-+ goto restart;
-+ }
-+ /* Float voltage not reached, yet.
-+ * Try to get the requested constant current. */
-+ requested_current = get_stage1_charge_current(c);
-+ if (current_mA < 0)
-+ current_mA = 0;
-+ current_diff = requested_current - current_mA;
-+ if (abs(requested_current - current_mA) > CURRENT_HYST) {
-+ if (current_diff > 0) {
-+ /* Increase current */
-+ permille = current_diff * 1000 / requested_current;
-+ permille /= 2;
-+ err = lipocharge_increase_current(c, permille);
-+ if (err)
-+ return err;
-+ } else {
-+ /* Decrease current */
-+ permille = (-current_diff) * 1000 / requested_current;
-+ permille /= 2;
-+ err = lipocharge_decrease_current(c, permille);
-+ if (err)
-+ return err;
-+ }
-+ }
-+ break;
-+ case LIPO_SECOND_STAGE: /* Constant voltage */
-+ //TODO
-+ break;
-+ }
-+
-+ return 0;
-+}
---- /dev/null
-+++ b/drivers/cbus/lipocharge.h
-@@ -0,0 +1,60 @@
-+#ifndef LIPOCHARGE_H_
-+#define LIPOCHARGE_H_
-+
-+#include <linux/types.h>
-+#include <linux/device.h>
-+
-+
-+#define LIPORATE(a,b) (((a) * 1000) + ((b) * 100))
-+#define LIPORATE_p6C LIPORATE(0,6) /* 0.6C */
-+
-+enum lipocharge_state {
-+ LIPO_IDLE = 0, /* Not charging */
-+ LIPO_FIRST_STAGE, /* Charging: constant current */
-+ LIPO_SECOND_STAGE, /* Charging: constant voltage */
-+};
-+
-+/** struct lipocharge - A generic LIPO charger
-+ *
-+ * @capacity: Battery capacity in mAh.
-+ * @rate: Charge rate.
-+ * @top_voltage: Fully charged voltage, in mV.
-+ * @duty_cycle_max: Max value for duty_cycle.
-+ *
-+ * @set_charge_current: Set the charge current PWM duty cycle.
-+ * @emergency: Something went wrong. Force shutdown.
-+ */
-+struct lipocharge {
-+ unsigned int capacity;
-+ unsigned int rate;
-+ unsigned int top_voltage;
-+ unsigned int duty_cycle_max;
-+
-+ int (*set_current_pwm)(struct lipocharge *c, unsigned int duty_cycle);
-+ void (*emergency)(struct lipocharge *c);
-+
-+ /* internal */
-+ struct device *dev;
-+ enum lipocharge_state state;
-+ unsigned int active_duty_cycle;
-+
-+ //TODO implement timer to cut power after maximum charge time.
-+};
-+
-+void lipocharge_init(struct lipocharge *c, struct device *dev);
-+void lipocharge_exit(struct lipocharge *c);
-+
-+int lipocharge_start(struct lipocharge *c);
-+void lipocharge_stop(struct lipocharge *c);
-+
-+int lipocharge_update_state(struct lipocharge *c,
-+ unsigned int voltage_mV,
-+ int current_mA,
-+ unsigned int temp_K);
-+
-+static inline bool lipocharge_is_charging(struct lipocharge *c)
-+{
-+ return (c->state != LIPO_IDLE);
-+}
-+
-+#endif /* LIPOCHARGE_H_ */
---- a/drivers/cbus/cbus.c
-+++ b/drivers/cbus/cbus.c
-@@ -36,6 +36,7 @@
- #include <linux/gpio.h>
- #include <linux/platform_device.h>
- #include <linux/platform_data/cbus.h>
-+#include <linux/reboot.h>
-
- #include "cbus.h"
-
-@@ -326,6 +327,13 @@ static void __exit cbus_bus_exit(void)
- }
- module_exit(cbus_bus_exit);
-
-+void cbus_emergency(void)
-+{
-+ machine_power_off();
-+ panic("cbus: Failed to halt machine in emergency state\n");
-+}
-+EXPORT_SYMBOL(cbus_emergency);
-+
- MODULE_DESCRIPTION("CBUS serial protocol");
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Juha Yrjölä");
---- a/drivers/cbus/cbus.h
-+++ b/drivers/cbus/cbus.h
-@@ -27,4 +27,6 @@ extern int cbus_read_reg(struct device *
- extern int cbus_write_reg(struct device *, unsigned dev, unsigned reg,
- unsigned val);
-
-+void cbus_emergency(void) __noreturn;
-+
- #endif /* __DRIVERS_CBUS_CBUS_H */
---- a/drivers/cbus/retu.c
-+++ b/drivers/cbus/retu.c
-@@ -399,6 +399,11 @@ static int retu_allocate_children(struct
- if (!child)
- return -ENOMEM;
-
-+ child = retu_allocate_child("retu-n810bm", parent, irq_base,
-+ RETU_INT_ADCS, -1, 1);
-+ if (!child)
-+ return -ENOMEM;
-+
- return 0;
- }
-
---- a/drivers/cbus/tahvo.c
-+++ b/drivers/cbus/tahvo.c
-@@ -129,6 +129,7 @@ void tahvo_set_clear_reg_bits(struct dev
- __tahvo_write_reg(tahvo, reg, w);
- mutex_unlock(&tahvo->mutex);
- }
-+EXPORT_SYMBOL(tahvo_set_clear_reg_bits);
-
- static irqreturn_t tahvo_irq_handler(int irq, void *_tahvo)
- {
-@@ -292,6 +293,11 @@ static int tahvo_allocate_children(struc
- if (!child)
- return -ENOMEM;
-
-+ child = tahvo_allocate_child("tahvo-n810bm", parent,
-+ irq_base + TAHVO_INT_BATCURR);
-+ if (!child)
-+ return -ENOMEM;
-+
- return 0;
- }
-
+++ /dev/null
---- a/arch/arm/plat-omap/omap_device.c
-+++ b/arch/arm/plat-omap/omap_device.c
-@@ -619,7 +619,7 @@ static void omap_device_delete(struct om
- * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
- * passes along the return value of omap_device_build_ss().
- */
--struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
-+struct platform_device *__init omap_device_build(const char *pdev_name, int pdev_id,
- struct omap_hwmod *oh, void *pdata,
- int pdata_len,
- struct omap_device_pm_latency *pm_lats,
-@@ -652,7 +652,7 @@ struct platform_device *omap_device_buil
- * platform_device record. Returns an ERR_PTR() on error, or passes
- * along the return value of omap_device_register().
- */
--struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
-+struct platform_device *__init omap_device_build_ss(const char *pdev_name, int pdev_id,
- struct omap_hwmod **ohs, int oh_cnt,
- void *pdata, int pdata_len,
- struct omap_device_pm_latency *pm_lats,
-@@ -717,7 +717,7 @@ odbs_exit:
- * platform_early_add_device() on the underlying platform_device.
- * Returns 0 by default.
- */
--static int omap_early_device_register(struct platform_device *pdev)
-+static int __init omap_early_device_register(struct platform_device *pdev)
- {
- struct platform_device *devices[1];
-
---- a/arch/arm/plat-omap/common.c
-+++ b/arch/arm/plat-omap/common.c
-@@ -29,7 +29,7 @@
-
- #define NO_LENGTH_CHECK 0xffffffff
-
--struct omap_board_config_kernel *omap_board_config __initdata;
-+struct omap_board_config_kernel *omap_board_config;
- int omap_board_config_size;
-
- unsigned char omap_bootloader_tag[1024];
-@@ -58,7 +58,7 @@ __tagtable(ATAG_BOARD, parse_tag_omap);
-
- #endif
-
--static const void *__init get_config(u16 tag, size_t len,
-+static const void *get_config(u16 tag, size_t len,
- int skip, size_t *len_out)
- {
- struct omap_board_config_kernel *kinfo = NULL;
-@@ -125,12 +125,12 @@ static const void *__init get_config(u16
- return kinfo->data;
- }
-
--const void *__init __omap_get_config(u16 tag, size_t len, int nr)
-+const void *__omap_get_config(u16 tag, size_t len, int nr)
- {
- return get_config(tag, len, nr, NULL);
- }
-
--const void *__init omap_get_var_config(u16 tag, size_t *len)
-+const void *omap_get_var_config(u16 tag, size_t *len)
- {
- return get_config(tag, NO_LENGTH_CHECK, 0, len);
- }
---- a/arch/arm/mach-omap2/devices.c
-+++ b/arch/arm/mach-omap2/devices.c
-@@ -380,7 +380,7 @@ static inline void omap_init_dmic(void)
-
- #include <plat/mcspi.h>
-
--static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
-+static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused)
- {
- struct platform_device *pdev;
- char *name = "omap2_mcspi";
---- a/arch/arm/mach-omap2/gpio.c
-+++ b/arch/arm/mach-omap2/gpio.c
-@@ -24,7 +24,7 @@
- #include <plat/omap_hwmod.h>
- #include <plat/omap_device.h>
-
--static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
-+static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
- {
- struct platform_device *pdev;
- struct omap_gpio_platform_data *pdata;
---- a/arch/arm/mach-omap2/mcbsp.c
-+++ b/arch/arm/mach-omap2/mcbsp.c
-@@ -122,7 +122,7 @@ static int omap3_enable_st_clock(unsigne
- return 0;
- }
-
--static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
-+static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
- {
- int id, count = 1;
- char *name = "omap-mcbsp";
---- a/arch/arm/plat-omap/include/plat/board.h
-+++ b/arch/arm/plat-omap/include/plat/board.h
-@@ -159,14 +159,14 @@ struct omap_gpio_switch_config {
- int key_code:24; /* Linux key code */
- };
-
--extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
-+extern const void * __omap_get_config(u16 tag, size_t len, int nr);
-
- #define omap_get_config(tag, type) \
- ((const type *) __omap_get_config((tag), sizeof(type), 0))
- #define omap_get_nr_config(tag, type, nr) \
- ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
-
--extern const void *__init omap_get_var_config(u16 tag, size_t *len);
-+extern const void * omap_get_var_config(u16 tag, size_t *len);
-
- extern struct omap_board_config_kernel *omap_board_config;
- extern int omap_board_config_size;
+++ /dev/null
-#
-# Copyright (C) 2010-2011 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/n810-base
- NAME:=Nokia n810 (base)
- PACKAGES:= \
- block-mount \
- gpsd \
- ip iw kmod-p54-spi wpa-supplicant \
- dnsmasq dropbear \
- pwrtray-backend \
- kmod-fs-vfat kmod-fs-msdos \
- kmod-input-evdev \
- kmod-leds-gpio \
- kmod-usb-tahvo kmod-usb-eth-gadget \
- kmod-usb-net kmod-usb-net-cdc-ether kmod-usb-net-pegasus kmod-usb-net-rndis \
- kmod-usb-storage kmod-usb-hid \
- kmod-bluetooth kmod-bluetooth-hci-h4p bluez-utils bluez-hcidump \
- kmod-n810bm maemo-kexec calvaria \
- schedtool
-endef
-
-define Profile/n810-base/Description
- Minimal package set for Nokia n810 hardware.
-endef
-$(eval $(call Profile,n810-base))
-
+++ /dev/null
-#
-# Copyright (C) 2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/n810-gui
- $(call Profile/n810-base)
- NAME:=Nokia n810 (GUI)
- PACKAGES+= \
- xserver-xorg xinit xauth xkeyboard-config xkbdata xterm \
- xf86-video-omapfb xf86-input-tslib xf86-input-evdev \
- openbox tint2 matchbox-keyboard \
- pwrtray
-endef
-
-define Profile/n810-gui/Description
- Graphical user interface package set for Nokia n810 hardware.
-endef
-$(eval $(call Profile,n810-gui))
-
+++ /dev/null
-#
-# Copyright (C) 2007-2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=powerpc
-BOARD:=ppc44x
-BOARDNAME:=AMCC/IBM PPC44x
-FEATURES:=squashfs broken
-CPU_TYPE:=440
-MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
-
-LINUX_VERSION:=3.10.49
-
-include $(INCLUDE_DIR)/target.mk
-
-DEFAULT_PACKAGES := $(filter-out ppp%,$(DEFAULT_PACKAGES))
-
-define Target/Description
- Build firmware images for AMCC/IBM PPC44x based boards.
-endef
-
-KERNELNAME:="uImage cuImage.taishan"
-
-$(eval $(call BuildTarget))
+++ /dev/null
-::sysinit:/etc/init.d/rcS S boot
-::shutdown:/etc/init.d/rcS K shutdown
-ttyS0::askfirst:/bin/ash --login
-ttyS1::askfirst:/bin/ash --login
+++ /dev/null
-# CONFIG_40x is not set
-CONFIG_440GX=y
-CONFIG_44x=y
-CONFIG_460EX=y
-CONFIG_4xx=y
-CONFIG_4xx_SOC=y
-# CONFIG_ADVANCED_OPTIONS is not set
-# CONFIG_ARCHES is not set
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_ILOG2_U32=y
-CONFIG_ARCH_HAS_WALK_MEMORY=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
-CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_MSI=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-CONFIG_AUDIT_ARCH=y
-# CONFIG_BAMBOO is not set
-# CONFIG_BLUESTONE is not set
-CONFIG_BOOKE=y
-CONFIG_BOUNCE=y
-CONFIG_CANYONLANDS=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/mtdblock1 rootfstype=squashfs,jffs2 noinitrd"
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CONSISTENT_SIZE=0x00200000
-# CONFIG_CRYPTO_SHA1_PPC is not set
-# CONFIG_DEFAULT_UIMAGE is not set
-CONFIG_DTC=y
-# CONFIG_E200 is not set
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EBONY is not set
-# CONFIG_EIGER is not set
-# CONFIG_EPAPR_BOOT is not set
-CONFIG_EXTRA_TARGETS="uImage"
-# CONFIG_FSL_ULI1575 is not set
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_NVRAM=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-# CONFIG_GENERIC_TBSYNC is not set
-CONFIG_GENERIC_TIME_VSYSCALL_OLD=y
-# CONFIG_GEN_RTC is not set
-# CONFIG_GE_FPGA is not set
-# CONFIG_GLACIER is not set
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAS_RAPIDIO is not set
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_IBM_EMAC=y
-CONFIG_IBM_EMAC_EMAC4=y
-CONFIG_IBM_EMAC_POLL_WEIGHT=32
-CONFIG_IBM_EMAC_RGMII=y
-CONFIG_IBM_EMAC_RXB=128
-CONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256
-CONFIG_IBM_EMAC_RX_SKB_HEADROOM=0
-CONFIG_IBM_EMAC_TAH=y
-CONFIG_IBM_EMAC_TXB=128
-CONFIG_IBM_EMAC_ZMII=y
-# CONFIG_ICON is not set
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IOMMU_HELPER is not set
-# CONFIG_IPIC is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_ISA_DMA_API=y
-# CONFIG_KATMAI is not set
-CONFIG_KERNEL_START=0xc0000000
-CONFIG_LOWMEM_SIZE=0x30000000
-# CONFIG_MATH_EMULATION is not set
-# CONFIG_MMIO_NVRAM is not set
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MPIC is not set
-# CONFIG_MPIC_U3_HT_IRQS is not set
-# CONFIG_MPIC_WEIRD is not set
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_NEED_DMA_MAP_STATE=y
-# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-# CONFIG_NONSTATIC_KERNEL is not set
-CONFIG_NOT_COHERENT_CACHE=y
-CONFIG_NR_IRQS=512
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xc0000000
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_MSI=y
-CONFIG_PHYSICAL_START=0x00000000
-CONFIG_PHYS_64BIT=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_POWERNV_MSI is not set
-CONFIG_PPC=y
-CONFIG_PPC32=y
-CONFIG_PPC44x_SIMPLE=y
-CONFIG_PPC4xx_MSI=y
-# CONFIG_PPC4xx_OCM is not set
-CONFIG_PPC4xx_PCI_EXPRESS=y
-# CONFIG_PPC64 is not set
-# CONFIG_PPC_47x is not set
-# CONFIG_PPC_85xx is not set
-# CONFIG_PPC_8xx is not set
-# CONFIG_PPC_970_NAP is not set
-CONFIG_PPC_ADV_DEBUG_DACS=2
-CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y
-CONFIG_PPC_ADV_DEBUG_DVCS=2
-CONFIG_PPC_ADV_DEBUG_IACS=4
-CONFIG_PPC_ADV_DEBUG_REGS=y
-# CONFIG_PPC_BOOK3S_32 is not set
-# CONFIG_PPC_CELL is not set
-# CONFIG_PPC_CELL_NATIVE is not set
-# CONFIG_PPC_CLOCK is not set
-CONFIG_PPC_DCR=y
-# CONFIG_PPC_DCR_MMIO is not set
-CONFIG_PPC_DCR_NATIVE=y
-# CONFIG_PPC_DOORBELL is not set
-# CONFIG_PPC_EARLY_DEBUG is not set
-# CONFIG_PPC_EPAPR_HV_PIC is not set
-CONFIG_PPC_FPU=y
-# CONFIG_PPC_I8259 is not set
-# CONFIG_PPC_ICP_HV is not set
-# CONFIG_PPC_ICP_NATIVE is not set
-# CONFIG_PPC_ICS_RTAS is not set
-CONFIG_PPC_INDIRECT_PCI=y
-CONFIG_PPC_MMU_NOHASH=y
-# CONFIG_PPC_MM_SLICES is not set
-# CONFIG_PPC_MPC106 is not set
-CONFIG_PPC_MSI_BITMAP=y
-CONFIG_PPC_OF=y
-# CONFIG_PPC_P7_NAP is not set
-CONFIG_PPC_PCI_CHOICE=y
-# CONFIG_PPC_RTAS is not set
-CONFIG_PPC_UDBG_16550=y
-CONFIG_PPC_WERROR=y
-# CONFIG_PPC_WSP is not set
-# CONFIG_PPC_XICS is not set
-# CONFIG_PQ2ADS is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_PTE_64BIT=y
-# CONFIG_RAINIER is not set
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SAM440EP is not set
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SEQUOIA is not set
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_SWIOTLB is not set
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_TAISHAN=y
-CONFIG_TASK_SIZE=0xc0000000
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_WARP is not set
-CONFIG_WORD_SIZE=32
-# CONFIG_XILINX_SYSACE is not set
-# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_POWERPC=y
-# CONFIG_YOSEMITE is not set
+++ /dev/null
-#
-# Copyright (C) 2007-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-JFFS2_BLOCKSIZE=256k
-
-define Image/Prepare
- $(LINUX_DIR)/scripts/dtc/dtc -O dtb -R 4 -S 0x20000 $(DTS_DIR)/canyonlands.dts > $(KDIR)/openwrt-canyonlands.dtb
-endef
-
-define Image/BuildKernel
- cp $(KDIR)/uImage $(BIN_DIR)/$(IMG_PREFIX)-uImage
-endef
-
-define Image/Build
- $(call Image/Build/$(1),$(1))
-endef
-
-define Image/Build/jffs2-256k
- ( \
- dd if=$(KDIR)/uImage bs=2048k conv=sync; \
- dd if=$(KDIR)/root.$(1) bs=256k conv=sync; \
- ) > $(BIN_DIR)/$(IMG_PREFIX)-jffs2.img
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
- ( \
- dd if=$(KDIR)/cuImage.taishan bs=2048k conv=sync; \
- dd if=$(KDIR)/root.$(1) bs=256k conv=sync; \
- ) > $(BIN_DIR)/$(IMG_PREFIX)-taishan-$(1).img
- ( \
- dd if=$(KDIR)/uImage bs=1920k conv=sync; \
- dd if=$(KDIR)/openwrt-canyonlands.dtb bs=128k conv=sync; \
- dd if=$(KDIR)/root.$(1) bs=256k conv=sync; \
- ) > $(BIN_DIR)/$(IMG_PREFIX)-canyonlands-$(1).img
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
---- a/arch/powerpc/boot/dts/taishan.dts
-+++ b/arch/powerpc/boot/dts/taishan.dts
-@@ -195,15 +195,15 @@
- #size-cells = <1>;
- partition@0 {
- label = "kernel";
-- reg = <0x0 0x180000>;
-+ reg = <0x0 0x200000>;
- };
-- partition@180000 {
-- label = "root";
-- reg = <0x180000 0x200000>;
-+ partition@200000 {
-+ label = "rootfs";
-+ reg = <0x200000 0x3c00000>;
- };
-- partition@380000 {
-- label = "user";
-- reg = <0x380000 0x3bc0000>;
-+ partition@3e00000 {
-+ label = "diagnostics";
-+ reg = <0x3e00000 0x140000>;
- };
- partition@3f40000 {
- label = "env";
---- a/arch/powerpc/boot/dts/canyonlands.dts
-+++ b/arch/powerpc/boot/dts/canyonlands.dts
-@@ -222,24 +222,12 @@
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
-- label = "kernel";
-- reg = <0x00000000 0x001e0000>;
-- };
-- partition@1e0000 {
-- label = "dtb";
-- reg = <0x001e0000 0x00020000>;
-+ label = "kernel+dtb";
-+ reg = <0x00000000 0x00200000>;
- };
- partition@200000 {
-- label = "ramdisk";
-- reg = <0x00200000 0x01400000>;
-- };
-- partition@1600000 {
-- label = "jffs2";
-- reg = <0x01600000 0x00400000>;
-- };
-- partition@1a00000 {
-- label = "user";
-- reg = <0x01a00000 0x02560000>;
-+ label = "rootfs";
-+ reg = <0x00200000 0x03d60000>;
- };
- partition@3f60000 {
- label = "env";
+++ /dev/null
---- a/arch/powerpc/boot/dts/taishan.dts
-+++ b/arch/powerpc/boot/dts/taishan.dts
-@@ -423,5 +423,6 @@
-
- chosen {
- linux,stdout-path = "/plb/opb/serial@40000300";
-+ bootargs = "console=ttyS1,115200 root=/dev/mtdblock1 rootfstype=squashfs noinitrd";
- };
- };
+++ /dev/null
-#
-# Copyright (C) 2006-2011 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=pxa
-BOARDNAME:=Marvell/Intel PXA2xx
-FEATURES:=squashfs
-MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
-
-LINUX_VERSION:=3.3.8
-
-include $(INCLUDE_DIR)/target.mk
-
-define Target/Description
- Build images for PXA2xx systems, eg. Gumstix.
-endef
-
-KERNELNAME:="uImage"
-
-$(eval $(call BuildTarget))
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_GUMSTIX=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-# CONFIG_ARCH_LUBBOCK is not set
-CONFIG_ARCH_MTD_XIP=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_ARCH_PXA_PALM is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARCH_VIPER is not set
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-# CONFIG_ARM_APPENDED_DTB is not set
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_THUMB is not set
-# CONFIG_ARPD is not set
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CACHE_XSC3L2=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_PXA300=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CPU_XSC3=y
-CONFIG_CPU_XSCALE=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_USER is not set
-CONFIG_DTC=y
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_EPOLL is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_PXA=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_PWM=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_IO_36=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_WORK=y
-CONFIG_IWMMXT=y
-CONFIG_KTIME_SCALAR=y
-# CONFIG_MACH_ARCOM_ZEUS is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_BALLOON3 is not set
-# CONFIG_MACH_CAPC7117 is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_COLIBRI300 is not set
-# CONFIG_MACH_COLIBRI320 is not set
-# CONFIG_MACH_CSB726 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_EXEDA is not set
-# CONFIG_MACH_GUMSTIX_F is not set
-CONFIG_MACH_GUMSTIX_VERDEX=y
-# CONFIG_MACH_H4700 is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_HIMALAYA is not set
-# CONFIG_MACH_ICONTROL is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_MACH_PCM027 is not set
-CONFIG_MACH_PXA3XX_DT=y
-# CONFIG_MACH_RAUMFELD_CONNECTOR is not set
-# CONFIG_MACH_RAUMFELD_RC is not set
-# CONFIG_MACH_RAUMFELD_SPEAKER is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_STARGATE2 is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_VPAC270 is not set
-# CONFIG_MACH_XCEP is not set
-# CONFIG_MACH_ZIPIT2 is not set
-# CONFIG_MACH_ZYLONITE300 is not set
-# CONFIG_MACH_ZYLONITE320 is not set
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_PXA=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_OF is not set
-CONFIG_MTD_PXA2XX=y
-# CONFIG_MTD_XIP is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_MACH_GPIO_H=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-# CONFIG_PACKET is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PLAT_PXA=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PXA27x=y
-CONFIG_PXA3xx=y
-# CONFIG_PXA_EZX is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_RCU_STALL_COMMON is not set
-# CONFIG_SA1100_WATCHDOG is not set
-CONFIG_SCHED_HRTICK=y
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SMSC911X=y
-# CONFIG_SMSC911X_ARCH_HOOKS is not set
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_TRIZEPS_PXA is not set
-CONFIG_UID16=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB_ARCH_HAS_XHCI is not set
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-# CONFIG_VLAN_8021Q is not set
-CONFIG_XSCALE_PMU=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_GUMSTIX=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-# CONFIG_ARCH_LUBBOCK is not set
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_ARCH_PXA_V7 is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
-# CONFIG_ARCH_VIPER is not set
-CONFIG_ARM=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_THUMB is not set
-# CONFIG_ARPD is not set
-CONFIG_ATA=m
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BLK_DEV_IDECS=m
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_PMU=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CPU_XSCALE=y
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_LL_UART_NONE is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_EPOLL is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_PXA=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_AOUT=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SCHED_CLOCK=y
-CONFIG_HAVE_SPARSE_IRQ=y
-CONFIG_I2C=m
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_PXA=m
-CONFIG_I2C_PXA_SLAVE=y
-CONFIG_IDE=m
-CONFIG_IWMMXT=y
-CONFIG_KTIME_SCALAR=y
-# CONFIG_MACH_ARCOM_ZEUS is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_BALLOON3 is not set
-# CONFIG_MACH_CAPC7117 is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_COLIBRI300 is not set
-# CONFIG_MACH_COLIBRI320 is not set
-# CONFIG_MACH_CSB726 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_EXEDA is not set
-# CONFIG_MACH_GUMSTIX_F is not set
-CONFIG_MACH_GUMSTIX_VERDEX=y
-# CONFIG_MACH_H4700 is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_HIMALAYA is not set
-# CONFIG_MACH_ICONTROL is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_MACH_RAUMFELD_CONNECTOR is not set
-# CONFIG_MACH_RAUMFELD_RC is not set
-# CONFIG_MACH_RAUMFELD_SPEAKER is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_STARGATE2 is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_VPAC270 is not set
-# CONFIG_MACH_XCEP is not set
-# CONFIG_MACH_ZIPIT2 is not set
-# CONFIG_MACH_ZYLONITE300 is not set
-# CONFIG_MACH_ZYLONITE320 is not set
-CONFIG_MDIO_BOARDINFO=y
-# CONFIG_MFD_T7L66XB is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_PXA=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PXA2XX=y
-# CONFIG_MTD_XIP is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-# CONFIG_PACKET is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PATA_PCMCIA=m
-# CONFIG_PATA_PXA is not set
-CONFIG_PCCARD=m
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_PXA2XX=m
-CONFIG_PCMCIA_SOC_COMMON=m
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PLAT_PXA=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PXA27x=y
-# CONFIG_PXA_EZX is not set
-# CONFIG_PXA_SHARPSL is not set
-CONFIG_SA1100_WATCHDOG=m
-CONFIG_SCSI=m
-CONFIG_SCSI_MOD=m
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_PROC_FS is not set
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIO=m
-CONFIG_SERIO_LIBPS2=m
-CONFIG_SERIO_SERPORT=m
-CONFIG_SMC911X=m
-CONFIG_SMC91X=m
-CONFIG_SMSC911X=y
-# CONFIG_SMSC911X_ARCH_HOOKS is not set
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_TRIZEPS_PXA is not set
-CONFIG_UID16=y
-CONFIG_UNIX=m
-CONFIG_VECTORS_BASE=0xffff0000
-# CONFIG_VLAN_8021Q is not set
-CONFIG_XSCALE_PMU=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2008-2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/BuildKernel
- cp $(KDIR)/uImage $(BIN_DIR)/$(IMG_PREFIX)-uImage
-endef
-
-# Build a fake flash image for usage in Qemu
-define Image/Build/Gumstix
- dd if=/dev/zero bs=128k count=256 of=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-qemu-flash.img
- dd if=$(BIN_DIR)/openwrt-pxa-gumstix-u-boot.bin conv=notrunc bs=128k \
- of=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-qemu-flash.img
- dd if=$(KDIR)/root.$(1) conv=notrunc bs=128k seek=2 \
- of=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-qemu-flash.img
- dd if=$(KDIR)/uImage conv=notrunc bs=128k seek=248 \
- of=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-qemu-flash.img
-endef
-
-define Image/Build
- $(call Image/Build/$(1),$(1))
- $(call Image/Build/$(PROFILE),$(1))
-endef
-
-define Image/Build/jffs2-64k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=64k conv=sync
-endef
-
-define Image/Build/jffs2-128k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-From 4f4bb58cba3a6c44e9f9f113609287d9d50be9c4 Mon Sep 17 00:00:00 2001
-From: Joseph Kortje <jpktech@rogers.com>
-Date: Wed, 28 Oct 2009 21:11:28 -0400
-Subject: [PATCH] [ARM] Gumstix Verdex Pro arch support
-
-add an option for Verdex Pro when ARCH_GUMSTIX is selected, and
-factor earlier Gumstix support into a seperate option
-
-Signed-off-by: Bobby Powers <bobbypowers@gmail.com>
----
- arch/arm/mach-pxa/Kconfig | 29 +-
- arch/arm/mach-pxa/Makefile | 3 +-
- arch/arm/mach-pxa/gumstix-verdex.c | 749 +++++++++++++++++++++++++++
- arch/arm/mach-pxa/include/mach/mfp-pxa27x.h | 1 +
- 4 files changed, 772 insertions(+), 10 deletions(-)
- create mode 100644 arch/arm/mach-pxa/gumstix-verdex.c
-
---- a/arch/arm/mach-pxa/Kconfig
-+++ b/arch/arm/mach-pxa/Kconfig
-@@ -129,23 +129,34 @@ config MACH_CAPC7117
- select PXA3xx
-
- config ARCH_GUMSTIX
-- bool "Gumstix XScale 255 boards"
-- select PXA25x
-+ bool "Gumstix boards"
- help
-- Say Y here if you intend to run this kernel on
-- Basix, Connex, ws-200ax, ws-400ax systems
-+ Say Y here if you intend to run this kernel on a
-+ gumstix computer.
-
--choice
-- prompt "Gumstix Carrier/Expansion Board"
- depends on ARCH_GUMSTIX
-
--config GUMSTIX_AM200EPD
-+config MACH_GUMSTIX_F
-+ bool "Gumstix Basix/Connex ..."
-+ depends on ARCH_GUMSTIX
-+ select PXA25x
-+
-+ choice
-+ prompt "Gumstix Carrier/Expansion Board"
-+ depends on MACH_GUMSTIX_F
-+
-+ config GUMSTIX_AM200EPD
- bool "Enable AM200EPD board support"
-
--config GUMSTIX_AM300EPD
-+ config GUMSTIX_AM300EPD
- bool "Enable AM300EPD board support"
-
--endchoice
-+ endchoice
-+
-+config MACH_GUMSTIX_VERDEX
-+ bool "Gumstix VERDEX ..."
-+ depends on ARCH_GUMSTIX
-+ select PXA27x
-
- config MACH_INTELMOTE2
- bool "Intel Mote 2 Platform"
---- a/arch/arm/mach-pxa/Makefile
-+++ b/arch/arm/mach-pxa/Makefile
-@@ -45,7 +45,8 @@ endif
- obj-$(CONFIG_MACH_EM_X270) += em-x270.o
- obj-$(CONFIG_MACH_CM_X300) += cm-x300.o
- obj-$(CONFIG_MACH_CAPC7117) += capc7117.o mxm8x10.o
--obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o
-+obj-$(CONFIG_MACH_GUMSTIX_F) += gumstix.o
-+obj-$(CONFIG_MACH_GUMSTIX_VERDEX) += gumstix-verdex.o
- obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o
- obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o
- obj-$(CONFIG_MACH_INTELMOTE2) += stargate2.o
---- /dev/null
-+++ b/arch/arm/mach-pxa/gumstix-verdex.c
-@@ -0,0 +1,794 @@
-+/*
-+ * linux/arch/arm/mach-pxa/gumstix-verdex.c
-+ *
-+ * Support for the Gumstix verdex motherboard.
-+ *
-+ * Original Author: Craig Hughes
-+ * Created: Feb 14, 2008
-+ * Copyright: Craig Hughes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * Implemented based on lubbock.c by Nicolas Pitre and code from Craig
-+ * Hughes
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/interrupt.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/i2c/tsc2007.h>
-+#include <linux/i2c/pxa-i2c.h>
-+#include <linux/gpio.h>
-+#include <linux/gpio-pxa.h>
-+
-+#include <asm/setup.h>
-+#include <asm/memory.h>
-+#include <asm/mach-types.h>
-+#include <asm/irq.h>
-+#include <asm/sizes.h>
-+#include <asm/io.h>
-+
-+#include <asm/mach/arch.h>
-+#include <asm/mach/map.h>
-+#include <asm/mach/irq.h>
-+#include <asm/mach/flash.h>
-+
-+#include <linux/platform_data/mmc-pxamci.h>
-+#include <mach/udc.h>
-+#include <linux/platform_data/video-pxafb.h>
-+#include <linux/platform_data/usb-ohci-pxa27x.h>
-+#include <mach/pxa27x.h>
-+#include <mach/pxa27x-udc.h>
-+#include <mach/gpio.h>
-+
-+#include <mach/gumstix.h>
-+
-+#include "generic.h"
-+
-+#include <linux/delay.h>
-+
-+static struct resource flash_resource = {
-+ .start = 0x00000000,
-+ .end = SZ_64M - 1,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct mtd_partition gumstix_partitions[] = {
-+ {
-+ .name = "u-boot",
-+ .size = 0x00040000,
-+ .offset = 0,
-+ .mask_flags = MTD_WRITEABLE /* force read-only */
-+ } , {
-+ .name = "rootfs",
-+ .size = 0x01ec0000,
-+ .offset = 0x00040000
-+ } , {
-+ .name = "kernel",
-+ .size = 0x00100000,
-+ .offset = 0x01f00000
-+ }
-+};
-+
-+static struct flash_platform_data gumstix_flash_data = {
-+ .map_name = "cfi_probe",
-+ .parts = gumstix_partitions,
-+ .nr_parts = ARRAY_SIZE(gumstix_partitions),
-+ .width = 2,
-+};
-+
-+static struct platform_device gumstix_flash_device = {
-+ .name = "pxa2xx-flash",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &gumstix_flash_data,
-+ },
-+ .resource = &flash_resource,
-+ .num_resources = 1,
-+};
-+
-+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) \
-+ || defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
-+
-+#include <linux/smsc911x.h>
-+
-+static struct resource verdex_smsc911x_resources[] = {
-+ [0] = {
-+ .name = "smsc911x-memory",
-+ .start = PXA_CS1_PHYS,
-+ .end = PXA_CS1_PHYS + 0x000fffff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0),
-+ .end = PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0),
-+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
-+ },
-+};
-+
-+static struct smsc911x_platform_config verdex_smsc911x_config = {
-+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
-+ .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
-+ .phy_interface = PHY_INTERFACE_MODE_MII,
-+};
-+
-+static struct platform_device verdex_smsc911x_device = {
-+ .name = "smsc911x",
-+ .id = -1,
-+ .num_resources = ARRAY_SIZE(verdex_smsc911x_resources),
-+ .resource = verdex_smsc911x_resources,
-+ .dev = {
-+ .platform_data = &verdex_smsc911x_config,
-+ },
-+};
-+#endif
-+
-+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-+static void __init verdex_init_smsc911x(void)
-+{
-+
-+ printk(KERN_INFO "Initializing Gumstix verdex smsc911x\n");
-+
-+ if (gpio_request(GPIO_GUMSTIX_ETH0_RST, "SMSC911x_ETH0_RST") != 0) {
-+ printk(KERN_ERR "could not obtain gpio for SMSC911x_ETH0_RST\n");
-+ goto err_request_gpio_eth0_rst;
-+ }
-+
-+ if (gpio_request(GPIO_GUMSTIX_ETH0, "SMSC911x_ETH0_IRQ") != 0) {
-+ printk(KERN_ERR "could not obtain gpio for SMSC911x_ETH0_IRQ\n");
-+ goto err_request_gpio_eth0_irq;
-+ }
-+
-+ if (gpio_direction_output(GPIO_GUMSTIX_ETH0_RST, 0) != 0) {
-+ printk(KERN_ERR "could not set SMSC911x_ETH0_RST pin to output\n");
-+ goto err_dir;
-+ }
-+
-+ gpio_set_value(GPIO_GUMSTIX_ETH0_RST, 0);
-+
-+ msleep(500); // Hold RESET for at least 200ms
-+
-+ gpio_set_value(GPIO_GUMSTIX_ETH0_RST, 1);
-+
-+ msleep(50);
-+
-+ if (gpio_direction_input(GPIO_GUMSTIX_ETH0) != 0) {
-+ printk(KERN_ERR "could not set SMSC911x_ETH0_IRQ pin to input\n");
-+ goto err_dir;
-+ }
-+
-+ gpio_export(GPIO_GUMSTIX_ETH0, 0);
-+ platform_device_register(&verdex_smsc911x_device);
-+ return;
-+
-+err_dir:
-+ gpio_free(GPIO_GUMSTIX_ETH0_RST);
-+
-+err_request_gpio_eth0_irq:
-+ gpio_free(GPIO_GUMSTIX_ETH0);
-+
-+err_request_gpio_eth0_rst:
-+ return;
-+}
-+
-+#else
-+static void __init verdex_init_smsc911x(void) { return; }
-+#endif
-+
-+static unsigned long verdex_pin_config[] = {
-+ /* MMC */
-+ GPIO32_MMC_CLK,
-+ GPIO112_MMC_CMD,
-+ GPIO92_MMC_DAT_0,
-+ GPIO109_MMC_DAT_1,
-+ GPIO110_MMC_DAT_2,
-+ GPIO111_MMC_DAT_3,
-+
-+ /* BTUART */
-+ GPIO42_BTUART_RXD,
-+ GPIO43_BTUART_TXD,
-+ GPIO44_BTUART_CTS,
-+ GPIO45_BTUART_RTS,
-+
-+ /* STUART */
-+ GPIO46_STUART_RXD,
-+ GPIO47_STUART_TXD,
-+
-+ /* FFUART */
-+ GPIO34_FFUART_RXD,
-+ GPIO39_FFUART_TXD,
-+
-+ /* SSP 2 */
-+ GPIO19_SSP2_SCLK,
-+ GPIO14_SSP2_SFRM,
-+ GPIO13_SSP2_TXD,
-+ GPIO11_SSP2_RXD,
-+
-+ /* SDRAM and local bus */
-+ GPIO49_nPWE,
-+ GPIO15_nCS_1,
-+
-+ /* I2C */
-+ GPIO117_I2C_SCL,
-+ GPIO118_I2C_SDA,
-+
-+ /* PWM 0 */
-+ GPIO16_PWM0_OUT,
-+
-+ /* BRIGHTNESS */
-+ GPIO17_PWM1_OUT,
-+
-+ /* LCD */
-+ GPIO58_LCD_LDD_0,
-+ GPIO59_LCD_LDD_1,
-+ GPIO60_LCD_LDD_2,
-+ GPIO61_LCD_LDD_3,
-+ GPIO62_LCD_LDD_4,
-+ GPIO63_LCD_LDD_5,
-+ GPIO64_LCD_LDD_6,
-+ GPIO65_LCD_LDD_7,
-+ GPIO66_LCD_LDD_8,
-+ GPIO67_LCD_LDD_9,
-+ GPIO68_LCD_LDD_10,
-+ GPIO69_LCD_LDD_11,
-+ GPIO70_LCD_LDD_12,
-+ GPIO71_LCD_LDD_13,
-+ GPIO72_LCD_LDD_14,
-+ GPIO73_LCD_LDD_15,
-+ GPIO74_LCD_FCLK,
-+ GPIO75_LCD_LCLK,
-+ GPIO76_LCD_PCLK,
-+#ifdef CONFIG_FB_PXA_SHARP_LQ043_PSP
-+ /* DISP must be always high while screen is on */
-+ /* Done below in verdex_init */
-+#else
-+ GPIO77_LCD_BIAS,
-+#endif
-+};
-+
-+#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
-+
-+static unsigned long gpio_ntschg_0[] = {
-+ GPIO104_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_nCD_0_MD);
-+};
-+
-+static unsigned long gpio_ntschg_1[] = {
-+ GPIO18_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_nSTSCHG_1_MD);
-+ GPIO36_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_nCD_1_MD);
-+ GPIO27_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_PRDY_nBSY_1_MD);
-+};
-+
-+static unsigned long gpio_prdy_nbsy_old[] = {
-+ GPIO111_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_nSTSCHG_0_MD);
-+ GPIO109_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_PRDY_nBSY_0_OLD_MD);
-+};
-+
-+static unsigned long gpio_prdy_nbsy[] = {
-+ GPIO96_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_PRDY_nBSY_0_MD);
-+};
-+
-+static unsigned long gpio_nhw_init[] = {
-+ GPIO48_nPOE, // pxa_gpio_mode(GPIO_GUMSTIX_nPOE_MD);
-+ GPIO102_nPCE_1, // pxa_gpio_mode(GPIO_GUMSTIX_nPCE_1_MD);
-+ GPIO105_nPCE_2, // pxa_gpio_mode(GPIO_GUMSTIX_nPCE_2_MD);
-+ GPIO104_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_nCD_0_MD);
-+
-+ GPIO49_nPWE, // pxa_gpio_mode(GPIO_GUMSTIX_nPWE_MD);
-+ GPIO50_nPIOR, // pxa_gpio_mode(GPIO_GUMSTIX_nPIOR_MD);
-+ GPIO51_nPIOW, // pxa_gpio_mode(GPIO_GUMSTIX_nPIOW_MD);
-+ GPIO79_PSKTSEL, // pxa_gpio_mode(GPIO_GUMSTIX_pSKTSEL_MD);
-+ GPIO55_nPREG, // pxa_gpio_mode(GPIO_GUMSTIX_nPREG_MD);
-+ GPIO56_nPWAIT, // pxa_gpio_mode(GPIO_GUMSTIX_nPWAIT_MD);
-+ GPIO57_nIOIS16, // pxa_gpio_mode(GPIO_GUMSTIX_nIOIS16_MD);
-+};
-+
-+static int net_cf_vx_mode = 0;
-+static int pcmcia_cf_nr = 2;
-+
-+inline void __init gumstix_pcmcia_cpld_clk(void)
-+{
-+ gpio_set_value(GPIO_GUMSTIX_nPOE, 0);
-+ gpio_set_value(GPIO_GUMSTIX_nPOE, 1);
-+}
-+
-+inline unsigned char __init gumstix_pcmcia_cpld_read_bits(int bits)
-+{
-+ unsigned char result = 0;
-+ unsigned int shift = 0;
-+ while(bits--)
-+ {
-+ result |= !!(gpio_get_value(GPIO_GUMSTIX_nCD_0) & GPIO_bit(GPIO_GUMSTIX_nCD_0)) << shift;
-+ shift ++;
-+ gumstix_pcmcia_cpld_clk();
-+ }
-+ printk("CPLD responded with: %02x\n",result);
-+ return result;
-+}
-+
-+/* We use the CPLD on the CF-CF card to read a value from a shift register. If we can read that
-+ * magic sequence, then we have 2 CF cards; otherwise we assume just one
-+ * The CPLD will send the value of the shift register on GPIO11 (the CD line for slot 0)
-+ * when RESET is held in reset. We use GPIO48 (nPOE) as a clock signal,
-+ * GPIO52/53 (card enable for both cards) to control read/write to the shift register
-+ */
-+static void __init gumstix_count_cards(void)
-+{
-+ if ((gpio_request(GPIO_GUMSTIX_nPOE, "GPIO_GUMSTIX_nPOE") == 0) &&
-+ (gpio_direction_output(GPIO_GUMSTIX_nPOE, 1) == 0))
-+ gpio_export(GPIO_GUMSTIX_nPOE, 0);
-+ else
-+ printk(KERN_ERR "could not obtain gpio for GPIO_GUMSTIX_nPOE\n");
-+
-+ if ((gpio_request(GPIO_GUMSTIX_nPCE_1, "GPIO_GUMSTIX_nPCE_1") == 0) &&
-+ (gpio_direction_output(GPIO_GUMSTIX_nPCE_1, 1) == 0))
-+ gpio_export(GPIO_GUMSTIX_nPCE_1, 0);
-+ else
-+ printk(KERN_ERR "could not obtain gpio for GPIO_GUMSTIX_nPCE_1\n");
-+
-+ if ((gpio_request(GPIO_GUMSTIX_nPCE_2, "GPIO_GUMSTIX_nPCE_2") == 0) &&
-+ (gpio_direction_output(GPIO_GUMSTIX_nPCE_2, 1) == 0))
-+ gpio_export(GPIO_GUMSTIX_nPCE_2, 0);
-+ else
-+ printk(KERN_ERR "could not obtain gpio for GPIO_GUMSTIX_nPCE_2\n");
-+
-+ if ((gpio_request(GPIO_GUMSTIX_nCD_0, "GPIO_GUMSTIX_nCD_0") == 0) &&
-+ (gpio_direction_input(GPIO_GUMSTIX_nCD_0) == 0))
-+ gpio_export(GPIO_GUMSTIX_nCD_0, 0);
-+ else
-+ printk(KERN_ERR "could not obtain gpio for GPIO_GUMSTIX_nCD_0\n");
-+
-+ if (net_cf_vx_mode) {
-+ if ((gpio_request(GPIO_GUMSTIX_CF_OLD_RESET, "GPIO_GUMSTIX_CF_OLD_RESET") == 0) &&
-+ (gpio_direction_output(GPIO_GUMSTIX_CF_OLD_RESET, 1) == 0)) {
-+ gpio_export(GPIO_GUMSTIX_CF_OLD_RESET, 0);
-+ } else {
-+ printk(KERN_ERR "could not obtain gpio for GPIO_GUMSTIX_CF_OLD_RESET\n");
-+ }
-+ } else {
-+ if ((gpio_request(GPIO_GUMSTIX_CF_RESET, "GPIO_GUMSTIX_CF_RESET") == 0) &&
-+ (gpio_direction_output(GPIO_GUMSTIX_CF_RESET, 1) == 0)) {
-+ gpio_export(GPIO_GUMSTIX_CF_RESET, 0);
-+ } else {
-+ printk(KERN_ERR "could not obtain gpio for GPIO_GUMSTIX_CF_RESET\n");
-+ }
-+ }
-+
-+ // Setup the shift register
-+ gpio_set_value(GPIO_GUMSTIX_nPCE_1, 1);
-+ gpio_set_value(GPIO_GUMSTIX_nPCE_2, 0);
-+
-+ // Tick the clock to program the shift register
-+ gumstix_pcmcia_cpld_clk();
-+
-+ // Now set shift register into read mode
-+ gpio_set_value(GPIO_GUMSTIX_nPCE_1, 0);
-+ gpio_set_value(GPIO_GUMSTIX_nPCE_2, 1);
-+
-+ // We can read the bits now -- 0xC2 means "Dual compact flash"
-+ if(gumstix_pcmcia_cpld_read_bits(8) != 0xC2)
-+ {
-+ // We do not have 2 CF slots
-+ pcmcia_cf_nr = 1;
-+ }
-+
-+ udelay(50);
-+
-+ if (net_cf_vx_mode) {
-+ gpio_set_value(GPIO_GUMSTIX_CF_OLD_RESET, 0);
-+ gpio_free(GPIO_GUMSTIX_CF_OLD_RESET);
-+ } else {
-+ gpio_set_value(GPIO_GUMSTIX_CF_RESET, 0);
-+ gpio_free(GPIO_GUMSTIX_CF_RESET);
-+ }
-+
-+ printk(KERN_INFO "found %d CF slots\n", pcmcia_cf_nr);
-+
-+ gpio_free(GPIO_GUMSTIX_nPCE_2);
-+ gpio_free(GPIO_GUMSTIX_nPCE_1);
-+ gpio_free(GPIO_GUMSTIX_nPOE);
-+ return;
-+}
-+
-+#define SMC_IO_EXTENT 16
-+#define BANK_SELECT 14
-+
-+static void __init verdex_pcmcia_pin_config(void)
-+{
-+ struct resource *res;
-+ void *network_controller_memory;
-+ struct platform_device *pdev = &verdex_smsc911x_device;
-+
-+ printk(KERN_INFO "Initializing Gumstix verdex pcmcia\n");
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (res == NULL) {
-+ printk(KERN_ERR "no memory resource defined\n");
-+ goto err_done;
-+ }
-+
-+ res = request_mem_region(res->start, SMC_IO_EXTENT, "smc91x probe");
-+ if (res == NULL) {
-+ printk(KERN_ERR "failed to request memory resource\n");
-+ goto err_done;
-+ }
-+
-+ // We check for the possibility of SMSC91c111 (reg base offset 0x300 from CS1 base)
-+ network_controller_memory = ioremap(res->start + 0x300, SMC_IO_EXTENT);
-+ if (network_controller_memory == NULL) {
-+ printk(KERN_ERR "failed to ioremap() registers\n");
-+ goto err_free_mem;
-+ }
-+
-+ // Look for the special 91c111 value in the bank select register
-+ if((0xff00 & readw(network_controller_memory+BANK_SELECT)) == 0x3300) {
-+ printk(KERN_INFO "Detected netCF-vx board: pcmcia using older GPIO configuration\n");
-+ net_cf_vx_mode = 1;
-+ } else {
-+ printk(KERN_INFO "Not netCF-vx board: pcmcia using newer GPIO configuration\n");
-+ net_cf_vx_mode = 0;
-+ }
-+
-+ iounmap(network_controller_memory);
-+err_free_mem:
-+ release_mem_region(res->start, SMC_IO_EXTENT);
-+err_done:
-+
-+ gumstix_count_cards(); // this can update pcmcia_cf_nr
-+
-+ // If pcmcia_cf_nr is 1 then we do not have 2 CF slots
-+ // Note: logic sequence was altered from previous kernel revs
-+ // so that this works as intended now.
-+ if (pcmcia_cf_nr != 0)
-+ {
-+ pxa2xx_mfp_config(ARRAY_AND_SIZE(gpio_ntschg_0));
-+
-+ if(net_cf_vx_mode)
-+ pxa2xx_mfp_config(gpio_prdy_nbsy_old, 1);
-+ else
-+ pxa2xx_mfp_config(gpio_prdy_nbsy, 1);
-+
-+ } else {
-+ // Note: this reconfigures pin GPIO18 to be GPIO-IN so make
-+ // sure that this only gets done for the old dual slot board
-+ // since that pin is an active AF1 out-mode signal (RDY) on
-+ // newer boards and changing the pin mode on the newer boards
-+ // would result in memory corruption for the NIC (and hang during
-+ // PHY test).
-+ pxa2xx_mfp_config(ARRAY_AND_SIZE(gpio_ntschg_1));
-+ }
-+
-+ pxa2xx_mfp_config(ARRAY_AND_SIZE(gpio_nhw_init));
-+ return;
-+}
-+
-+int __init gumstix_get_cf_cards(void)
-+{
-+ return pcmcia_cf_nr;
-+}
-+EXPORT_SYMBOL(gumstix_get_cf_cards);
-+
-+#ifdef CONFIG_MACH_GUMSTIX_VERDEX
-+int __init gumstix_check_if_netCF_vx(void)
-+{
-+ return net_cf_vx_mode;
-+}
-+EXPORT_SYMBOL(gumstix_check_if_netCF_vx);
-+#endif
-+
-+#endif
-+
-+#if defined(CONFIG_FB_PXA_SHARP_LQ043_PSP) || defined(CONFIG_FB_PXA_SAMSUNG_LTE430WQ_F0C)
-+static void gumstix_lcd_backlight(int on_or_off)
-+{
-+ int err;
-+ err = gpio_request(17, "LCD BACKLIGHT");
-+ if (err) {
-+ //pr_warning("Gumstix Verdex: Failed to request LCD Backlight gpio\n");
-+ return;
-+ }
-+
-+ if(on_or_off) {
-+ gpio_direction_input(17);
-+ } else {
-+ gpio_set_value(17, 0);
-+ gpio_direction_output(17, 0);
-+ gpio_set_value(17, 0);
-+ }
-+
-+ return;
-+}
-+#endif
-+
-+#ifdef CONFIG_FB_PXA_ALPS_CDOLLAR
-+static struct pxafb_mode_info gumstix_fb_mode = {
-+ .pixclock = 300000,
-+ .xres = 240,
-+ .yres = 320,
-+ .bpp = 16,
-+ .hsync_len = 2,
-+ .left_margin = 1,
-+ .right_margin = 1,
-+ .vsync_len = 3,
-+ .upper_margin = 0,
-+ .lower_margin = 0,
-+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-+};
-+
-+static struct pxafb_mach_info gumstix_fb_info = {
-+ .modes = &gumstix_fb_mode,
-+ .num_modes = 1,
-+ .lccr0 = LCCR0_Pas | LCCR0_Sngl | LCCR0_Color,
-+ .lccr3 = LCCR3_PixFlEdg,
-+};
-+#elif defined(CONFIG_FB_PXA_SHARP_LQ043_PSP)
-+static struct pxafb_mode_info gumstix_fb_mode = {
-+ .pixclock = 110000,
-+ .xres = 480,
-+ .yres = 272,
-+ .bpp = 16,
-+ .hsync_len = 41,
-+ .left_margin = 2,
-+ .right_margin = 2,
-+ .vsync_len = 10,
-+ .upper_margin = 2,
-+ .lower_margin = 2,
-+ .sync = 0, // Hsync and Vsync both active low
-+};
-+
-+static struct pxafb_mach_info gumstix_fb_info = {
-+ .modes = &gumstix_fb_mode,
-+ .num_modes = 1,
-+ .lccr0 = LCCR0_Act | LCCR0_Sngl | LCCR0_Color,
-+ .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | (0 << 30),
-+ .pxafb_backlight_power = &gumstix_lcd_backlight,
-+};
-+#elif defined(CONFIG_FB_PXA_SAMSUNG_LTE430WQ_F0C)
-+static struct pxafb_mode_info gumstix_fb_mode = {
-+ .pixclock = 108696, // 9.2MHz typical DOTCLK from datasheet
-+ .xres = 480,
-+ .hsync_len = 41, // HLW from datasheet: 41 typ
-+ .left_margin = 4, // HBP - HLW from datasheet: 45 - 41 = 4
-+ .right_margin = 8, // HFP from datasheet: 8 typ
-+ .yres = 272,
-+ .vsync_len = 10, // VLW from datasheet: 10 typ
-+ .upper_margin = 2, // VBP - VLW from datasheet: 12 - 10 = 2
-+ .lower_margin = 4, // VFP from datasheet: 4 typ
-+ .bpp = 16,
-+ .sync = 0, // Hsync and Vsync both active low
-+};
-+
-+static struct pxafb_mach_info gumstix_fb_info = {
-+ .modes = &gumstix_fb_mode,
-+ .num_modes = 1,
-+ .lccr0 = LCCR0_Act | LCCR0_Sngl | LCCR0_Color,
-+ .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | (0 << 30),
-+ .pxafb_backlight_power = &gumstix_lcd_backlight,
-+};
-+#endif
-+
-+static struct platform_device verdex_audio_device = {
-+ .name = "pxa2xx-ac97",
-+ .id = -1,
-+};
-+
-+static struct platform_device *devices[] __initdata = {
-+ &gumstix_flash_device,
-+ &verdex_audio_device,
-+};
-+
-+/* PXA27x OHCI controller setup */
-+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-+static int ohci_verdex_init(struct device *dev)
-+{
-+ // Turn on port 2 in host mode
-+ UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
-+
-+ /* See drivers/usb/host/ohci-pxa27x.c for further details but
-+ ENABLE_PORT_ALL flag is equivalent to using this old sequence:
-+ UHCHR = (UHCHR) &
-+ ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
-+ */
-+ return 0;
-+}
-+
-+static struct pxaohci_platform_data verdex_ohci_platform_data = {
-+ .port_mode = PMM_PERPORT_MODE,
-+ .flags = ENABLE_PORT_ALL,
-+ .init = ohci_verdex_init,
-+};
-+
-+static void __init verdex_ohci_init(void)
-+{
-+ pxa_set_ohci_info(&verdex_ohci_platform_data);
-+}
-+#else
-+static void __init verdex_ohci_init(void) {
-+ printk(KERN_INFO "Gumstix verdex host usb ohci is disabled\n");
-+}
-+#endif
-+
-+
-+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-+static struct pxamci_platform_data verdex_mci_platform_data;
-+
-+static int verdex_mci_init(struct device *dev, irq_handler_t detect_int,
-+ void *data)
-+{
-+ /* GPIO setup for MMC on the 120-pin connector is done in verdex_init.
-+ * There is no card detect on a uSD connector so no interrupt to
-+ * register. There is no WP detect GPIO line either.
-+ */
-+
-+ return 0;
-+}
-+
-+static struct pxamci_platform_data verdex_mci_platform_data = {
-+ .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
-+ .init = verdex_mci_init,
-+ .gpio_card_detect = -1,
-+ .gpio_card_ro = -1,
-+ .gpio_power = -1,
-+};
-+
-+static void __init verdex_mmc_init(void)
-+{
-+ pxa_set_mci_info(&verdex_mci_platform_data);
-+}
-+#else
-+static void __init verdex_mmc_init(void)
-+{
-+ printk(KERN_INFO "Gumstix verdex mmc disabled\n");
-+}
-+#endif
-+
-+#if defined(CONFIG_USB_GADGET_PXA2XX) || defined(CONFIG_USB_GADGET_PXA2XX_MODULE)
-+static struct pxa2xx_udc_mach_info verdex_udc_info __initdata = {
-+ .gpio_vbus = GPIO35,
-+ .gpio_pullup = GPIO41,
-+};
-+
-+static void __init verdex_udc_init(void)
-+{
-+ pxa_set_udc_info(&verdex_udc_info);
-+}
-+#else
-+static void __init verdex_udc_init(void)
-+{
-+ printk(KERN_INFO "Gumstix verdex udc is disabled\n");
-+}
-+#endif
-+
-+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-+
-+#if defined(CONFIG_TOUCHSCREEN_TSC2003) || defined(CONFIG_TOUCHSCREEN_TSC2003_MODULE)
-+
-+#define VERDEX_GPIO_PENDOWN 16
-+
-+static int tsc2003_init_platform_hw(void)
-+{
-+ return 0;
-+}
-+
-+static void tsc2003_exit_platform_hw(void)
-+{
-+ return;
-+}
-+
-+static void tsc2003_clear_penirq(void)
-+{
-+ return;
-+}
-+
-+static int tsc2003_get_pendown_state(void)
-+{
-+ return !gpio_get_value(VERDEX_GPIO_PENDOWN);
-+}
-+
-+static struct tsc2007_platform_data tsc2003_config = {
-+ .model = 2003,
-+ .x_plate_ohms = 100,
-+ .get_pendown_state = tsc2003_get_pendown_state,
-+ .clear_penirq = tsc2003_clear_penirq,
-+ .init_platform_hw = tsc2003_init_platform_hw,
-+ .exit_platform_hw = tsc2003_exit_platform_hw,
-+};
-+#endif
-+
-+static struct i2c_board_info __initdata verdex_i2c_board_info[] = {
-+#if defined(CONFIG_RTC_DRV_DS1307) || defined(CONFIG_RTC_DRV_DS1307_MODULE)
-+ {
-+ I2C_BOARD_INFO("rtc-ds1307", 0x68),
-+ },
-+#endif
-+#if defined(CONFIG_TOUCHSCREEN_TSC2003) || defined(CONFIG_TOUCHSCREEN_TSC2003_MODULE)
-+ {
-+ I2C_BOARD_INFO("tsc2003", 0x48),
-+ .platform_data = &tsc2003_config,
-+ .irq = IRQ_GPIO(VERDEX_GPIO_PENDOWN),
-+ },
-+#endif
-+};
-+
-+static struct i2c_pxa_platform_data verdex_i2c_pwr_info = {
-+ .fast_mode = 1,
-+};
-+
-+static struct i2c_pxa_platform_data verdex_i2c_info = {
-+ .fast_mode = 1,
-+};
-+
-+static void __init verdex_i2c_init(void)
-+{
-+ printk(KERN_INFO "Initializing Gumstix verdex i2c\n");
-+
-+#if defined(CONFIG_TOUCHSCREEN_TSC2003) || defined(CONFIG_TOUCHSCREEN_TSC2003_MODULE)
-+ if ((gpio_request(VERDEX_GPIO_PENDOWN, "TSC2003_PENDOWN") == 0) &&
-+ (gpio_direction_input(VERDEX_GPIO_PENDOWN) == 0)) {
-+ gpio_export(VERDEX_GPIO_PENDOWN, 0);
-+ } else {
-+ printk(KERN_ERR "could not obtain gpio for TSC2003_PENDOWN\n");
-+ return;
-+ }
-+#endif
-+
-+ i2c_register_board_info(0, verdex_i2c_board_info,
-+ ARRAY_SIZE(verdex_i2c_board_info));
-+ pxa_set_i2c_info(&verdex_i2c_info);
-+ pxa27x_set_i2c_power_info(&verdex_i2c_pwr_info);
-+}
-+#else
-+static inline void verdex_i2c_init(void) {}
-+#endif
-+
-+#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
-+static void __init verdex_pcmcia_init(void)
-+{
-+ verdex_pcmcia_pin_config();
-+}
-+#else
-+static void __init verdex_pcmcia_init(void) {
-+ printk(KERN_INFO "Gumstix verdex pcmcia is disabled\n");
-+}
-+#endif
-+
-+
-+static void __init verdex_init(void)
-+{
-+ pxa2xx_mfp_config(ARRAY_AND_SIZE(verdex_pin_config));
-+
-+#ifdef CONFIG_FB_PXA_SHARP_LQ043_PSP
-+ /* DISP must be always high while screen is on */
-+ gpio_direction_output(GPIO77, 0);
-+ gpio_set_value(GPIO77, 1);
-+#endif
-+ verdex_udc_init();
-+ verdex_mmc_init();
-+ verdex_ohci_init();
-+ verdex_i2c_init();
-+ verdex_init_smsc911x();
-+ verdex_pcmcia_init();
-+
-+#if defined(CONFIG_FB_PXA_ALPS_CDOLLAR) || defined(CONFIG_FB_PXA_SHARP_LQ043_PSP) || defined(CONFIG_FB_PXA_SAMSUNG_LTE430WQ_F0C)
-+ printk(KERN_INFO "Initializing Gumstix verdex FB info\n");
-+ set_pxa_fb_info(&gumstix_fb_info);
-+#endif
-+ printk(KERN_INFO "Initializing Gumstix platform_add_devices\n");
-+ (void) platform_add_devices(devices, ARRAY_SIZE(devices));
-+}
-+
-+MACHINE_START(GUMSTIX, "Gumstix verdex")
-+ .atag_offset = 0x100, /* match u-boot bi_boot_params */
-+ .map_io = pxa27x_map_io,
-+ .init_irq = pxa27x_init_irq,
-+ .handle_irq = pxa27x_handle_irq,
-+ .init_time = pxa_timer_init,
-+ .init_machine = verdex_init,
-+ .restart = pxa_restart,
-+MACHINE_END
---- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
-+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
-@@ -109,6 +109,7 @@
- #define GPIO54_nPCE_2 MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
- #define GPIO78_nPCE_2 MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH)
- #define GPIO87_nPCE_2 MFP_CFG_IN(GPIO87, AF1)
-+#define GPIO105_nPCE_2 MFP_CFG_OUT(GPIO105, AF1, DRIVE_HIGH)
- #define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
- #define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
- #define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
+++ /dev/null
-From eb92a178eceae4e5d18bbb442b8e44cb88457d60 Mon Sep 17 00:00:00 2001
-From: Joseph Kortje <jpktech@rogers.com>
-Date: Wed, 28 Oct 2009 21:25:57 -0400
-Subject: [PATCH] [ARM] Gumstix Verdex LCD config options
-
-add options to Kconfig for Verdex LCD support
-
-Signed-off-by: Bobby Powers <bobbypowers@gmail.com>
----
- drivers/video/Kconfig | 31 +++++++++++++++++++++++++++++++
- 1 files changed, 31 insertions(+), 0 deletions(-)
-
---- a/drivers/video/Kconfig
-+++ b/drivers/video/Kconfig
-@@ -1905,6 +1905,37 @@ config FB_PXA
- say M here and read <file:Documentation/kbuild/modules.txt>.
-
- If unsure, say N.
-+choice
-+ depends on FB_PXA
-+ prompt "LCD Panel"
-+ default FB_PXA_SAMSUNG_LTE430WQ_F0C
-+
-+config FB_PXA_ALPS_CDOLLAR
-+ boolean "Chris Dollar's ALPS screen"
-+ ---help---
-+ Enable definitions (over-ridable on the kernel command line if
-+ "PXA LCD command line parameters" is also selected) for an ALPS
-+ screen which Chris Dollar uses
-+
-+config FB_PXA_SHARP_LQ043_PSP
-+ boolean "SHARP LQ043... series"
-+ ---help---
-+ Enable definitions (over-ridable on the kernel command line if
-+ "PXA LCD command line parameters" is also selected) for a SHARP
-+ LQ043... screen, such as the one used by the PSP. These screens are
-+ the ones normally sold by gumstix with its boards.
-+
-+config FB_PXA_SAMSUNG_LTE430WQ_F0C
-+ boolean "Samsung LTE430WQ-F0C (standard gumstix LCD)"
-+ ---help---
-+ Enable definitions for a Samsung LTE430WQ-F0C LCD panel, such as the ones resold
-+ by gumstix for use with their "LCD-Ready" boards.
-+
-+config FB_PXA_NONEOFTHEABOVE
-+ boolean "None of the above"
-+
-+endchoice
-+
-
- config FB_PXA_OVERLAY
- bool "Support PXA27x/PXA3xx Overlay(s) as framebuffer"
+++ /dev/null
-From adb6abbe4e3bc17c20cdc70e4a4357f1633d4970 Mon Sep 17 00:00:00 2001
-From: Joseph Kortje <jpktech@rogers.com>
-Date: Wed, 28 Oct 2009 21:49:11 -0400
-Subject: [PATCH] [ARM] gumstix.h: Verdex Pro support
-
-Added a bunch of ifdefs to support both original gumstix boards
-as well as the Verdex Pro in gumstix.h
-
-Signed-off-by: Bobby Powers <bobbypowers@gmail.com>
----
- arch/arm/mach-pxa/include/mach/gumstix.h | 160 ++++++++++++++++++++++++------
- 1 files changed, 130 insertions(+), 30 deletions(-)
-
---- a/arch/arm/mach-pxa/include/mach/gumstix.h
-+++ b/arch/arm/mach-pxa/include/mach/gumstix.h
-@@ -6,6 +6,9 @@
- * published by the Free Software Foundation.
- */
-
-+#if !defined(__ASM_ARCH_MFP_PXA27X_H) && !defined(__ASM_ARCH_MFP_PXA25X_H)
-+ #error You need to include either mfp-pxa27x.h or mfp-pxa25x.h
-+#endif
-
- /* BTRESET - Reset line to Bluetooth module, active low signal. */
- #define GPIO_GUMSTIX_BTRESET 7
-@@ -20,9 +23,18 @@ this moves to GPIO17 and GPIO37. */
- /* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn
- has detected a cable insertion; driven low otherwise. */
-
-+#ifndef CONFIG_MACH_GUMSTIX_VERDEX
-+
- #define GPIO_GUMSTIX_USB_GPIOn 35
- #define GPIO_GUMSTIX_USB_GPIOx 41
-
-+#else
-+
-+#define GPIO_GUMSTIX_USB_GPIOn 100
-+#define GPIO_GUMSTIX_USB_GPIOx 27
-+
-+#endif
-+
- /* usb state change */
- #define GUMSTIX_USB_INTR_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_USB_GPIOn)
-
-@@ -42,48 +54,136 @@ has detected a cable insertion; driven l
- * ETH_RST provides a hardware reset line to the ethernet chip
- * ETH is the IRQ line in from the ethernet chip to the PXA
- */
-+#ifndef CONFIG_MACH_GUMSTIX_VERDEX
- #define GPIO_GUMSTIX_ETH0_RST 80
--#define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
-+#define GPIO_GUMSTIX_ETH0 36
-+#else
-+#define GPIO_GUMSTIX_ETH0_RST 107
-+#define GPIO_GUMSTIX_ETH0 99
-+#endif
- #define GPIO_GUMSTIX_ETH1_RST 52
--#define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
-+#define GPIO_GUMSTIX_ETH1 27
-
--#define GPIO_GUMSTIX_ETH0 36
-+#define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
-+#define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
- #define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN)
--#define GUMSTIX_ETH0_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0)
--#define GPIO_GUMSTIX_ETH1 27
- #define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN)
--#define GUMSTIX_ETH1_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1)
--
-
--/* CF reset line */
--#define GPIO8_RESET 8
-+#define GUMSTIX_ETH0_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0)
-+#define GUMSTIX_ETH1_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1)
-
--/* CF slot 0 */
--#define GPIO4_nBVD1 4
--#define GPIO4_nSTSCHG GPIO4_nBVD1
--#define GPIO11_nCD 11
--#define GPIO26_PRDY_nBSY 26
--#define GUMSTIX_S0_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO4_nSTSCHG)
--#define GUMSTIX_S0_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO11_nCD)
--#define GUMSTIX_S0_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO26_PRDY_nBSY)
-+ /* CF reset line */
-+#define GPIO8_CF_RESET 8
-+#define GPIO97_CF_RESET 97
-+#define GPIO110_CF_RESET 110
-+
-+#ifndef CONFIG_MACH_GUMSTIX_VERDEX
-+#define GPIO_GUMSTIX_CF_RESET GPIO8_CF_RESET
-+#else
-+#define GPIO_GUMSTIX_CF_RESET GPIO97_CF_RESET
-+#endif
-+
-+#define GPIO_GUMSTIX_CF_OLD_RESET GPIO110_CF_RESET
-+
-+/* CF signals shared by both sockets */
-+#define GPIO_GUMSTIX_nPOE 48
-+#define GPIO_GUMSTIX_nPWE 49
-+#define GPIO_GUMSTIX_nPIOR 50
-+#define GPIO_GUMSTIX_nPIOW 51
-+
-+#ifndef CONFIG_MACH_GUMSTIX_VERDEX
-+#define GPIO_GUMSTIX_nPCE_1 52
-+#define GPIO_GUMSTIX_nPCE_2 53
-+#define GPIO_GUMSTIX_pSKTSEL 54
-+#else
-+#define GPIO_GUMSTIX_nPCE_1 102
-+#define GPIO_GUMSTIX_nPCE_2 105
-+#define GPIO_GUMSTIX_pSKTSEL 79
-+#endif
-+
-+#define GPIO_GUMSTIX_nPREG 55
-+#define GPIO_GUMSTIX_nPWAIT 56
-+#define GPIO_GUMSTIX_nIOIS16 57
-+
-+/* Pin mode definitions correspond to mfp-pxa2[57]x.h */
-+#define GPIO_GUMSTIX_nPOE_MD GPIO48_nPOE
-+#define GPIO_GUMSTIX_nPWE_MD GPIO49_nPWE
-+#define GPIO_GUMSTIX_nPIOR_MD GPIO50_nPIOR
-+#define GPIO_GUMSTIX_nPIOW_MD GPIO51_nPIOW
-+
-+#ifndef CONFIG_MACH_GUMSTIX_VERDEX
-+#define GPIO_GUMSTIX_nPCE_1_MD GPIO52_nPCE_1
-+#define GPIO_GUMSTIX_nPCE_2_MD GPIO53_nPCE_2
-+#define GPIO_GUMSTIX_pSKTSEL_MD GPIO54_pSKTSEL
-+#else
-+#define GPIO_GUMSTIX_nPCE_1_MD GPIO102_nPCE_1
-+#define GPIO_GUMSTIX_nPCE_2_MD GPIO105_nPCE_2
-+#define GPIO_GUMSTIX_pSKTSEL_MD GPIO79_pSKTSEL
-+#endif
-+
-+#define GPIO_GUMSTIX_nPREG_MD GPIO55_nPREG
-+#define GPIO_GUMSTIX_nPWAIT_MD GPIO56_nPWAIT
-+#define GPIO_GUMSTIX_nIOIS16_MD GPIO57_nIOIS16
-+
-+ /* CF slot 0 */
-+#define GPIO4_nBVD1_0 4
-+#define GPIO4_nSTSCHG_0 GPIO4_nBVD1_0
-+#define GPIO11_nCD_0 11
-+#define GPIO26_PRDY_nBSY_0 26
-+
-+#define GPIO111_nBVD1_0 111
-+#define GPIO111_nSTSCHG_0 GPIO111_nBVD1_0
-+#define GPIO104_nCD_0 104
-+#define GPIO96_PRDY_nBSY_0 96
-+#define GPIO109_PRDY_nBSY_0 109
-+
-+#ifndef CONFIG_MACH_GUMSTIX_VERDEX
-+#define GPIO_GUMSTIX_nBVD1_0 GPIO4_nBVD1_0
-+#define GPIO_GUMSTIX_nSTSCHG_0 GPIO4_nSTSCHG_0
-+#define GPIO_GUMSTIX_nCD_0 GPIO11_nCD_0
-+#define GPIO_GUMSTIX_PRDY_nBSY_0 GPIO26_PRDY_nBSY_0
-+#else
-+#define GPIO_GUMSTIX_nBVD1_0 GPIO111_nBVD1_0
-+#define GPIO_GUMSTIX_nSTSCHG_0 GPIO111_nSTSCHG_0
-+#define GPIO_GUMSTIX_nCD_0 GPIO104_nCD_0
-+#define GPIO_GUMSTIX_PRDY_nBSY_0 GPIO96_PRDY_nBSY_0
-+#endif
-+
-+#define GPIO_GUMSTIX_PRDY_nBSY_0_OLD GPIO109_PRDY_nBSY_0
-+#define GUMSTIX_S0_PRDY_nBSY_OLD_IRQ PXA_GPIO_TO_IRQ(GPIO109_PRDY_nBSY_0)
-+
-+#define GUMSTIX_S0_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_nSTSCHG_0)
-+#define GUMSTIX_S0_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_nCD_0)
-+#define GUMSTIX_S0_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_PRDY_nBSY_0)
-
- /* CF slot 1 */
--#define GPIO18_nBVD1 18
--#define GPIO18_nSTSCHG GPIO18_nBVD1
--#define GPIO36_nCD 36
--#define GPIO27_PRDY_nBSY 27
--#define GUMSTIX_S1_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG)
--#define GUMSTIX_S1_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO36_nCD)
--#define GUMSTIX_S1_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY)
--
--/* CF GPIO line modes */
--#define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN)
--#define GPIO8_RESET_MD (GPIO8_RESET | GPIO_OUT)
--#define GPIO11_nCD_MD (GPIO11_nCD | GPIO_IN)
--#define GPIO18_nSTSCHG_MD (GPIO18_nSTSCHG | GPIO_IN)
--#define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN)
--#define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN)
--#define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN)
-+#define GPIO18_nBVD1_1 18
-+#define GPIO18_nSTSCHG_1 GPIO18_nBVD1_1
-+#define GPIO36_nCD_1 36
-+#define GPIO27_PRDY_nBSY_1 27
-+
-+#define GPIO_GUMSTIX_nBVD1_1 GPIO18_nBVD1_1
-+#define GPIO_GUMSTIX_nSTSCHG_1 GPIO18_nSTSCHG_1
-+#define GPIO_GUMSTIX_nCD_1 GPIO36_nCD_1
-+#define GPIO_GUMSTIX_PRDY_nBSY_1 GPIO27_PRDY_nBSY_1
-+
-+#define GUMSTIX_S1_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG_1)
-+#define GUMSTIX_S1_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO36_nCD_1)
-+#define GUMSTIX_S1_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY_1)
-+
-+/* CF GPIO line modes - correspond to mfp-pxa2[57]x.h */
-+#define GPIO_GUMSTIX_CF_RESET_MD (GPIO_GUMSTIX_CF_RESET | GPIO_OUT)
-+#define GPIO_GUMSTIX_CF_OLD_RESET_MD (GPIO_GUMSTIX_CF_OLD_RESET | GPIO_OUT)
-+
-+#define GPIO_GUMSTIX_nSTSCHG_0_MD GPIO111_GPIO
-+#define GPIO_GUMSTIX_nCD_0_MD GPIO104_GPIO
-+
-+#define GPIO_GUMSTIX_PRDY_nBSY_0_MD GPIO96_GPIO
-+#define GPIO_GUMSTIX_PRDY_nBSY_0_OLD_MD GPIO109_GPIO
-+
-+#define GPIO_GUMSTIX_nSTSCHG_1_MD GPIO18_GPIO
-+#define GPIO_GUMSTIX_nCD_1_MD GPIO36_GPIO
-+#define GPIO_GUMSTIX_PRDY_nBSY_1_MD GPIO27_GPIO
-
- /* for expansion boards that can't be programatically detected */
- extern int am200_init(void);
+++ /dev/null
-From 7645a459feb02f7aae4c3a5724b7800495d1b659 Mon Sep 17 00:00:00 2001
-From: Bobby Powers <bobbypowers@gmail.com>
-Date: Wed, 28 Oct 2009 22:41:31 -0400
-Subject: [PATCH] [ARM] smsc911x: Verdex Pro support
-
-Basically Joseph Kortje's patch, cleaned up to apply to Linus's
-tree. Some of the smsc911x.c had been applied already
-
-Signed-off-by: Bobby Powers <bobbypowers@gmail.com>
----
- drivers/net/smsc911x.c | 50 +++++++++++++++++++++++++++++++++++++--------
- drivers/net/smsc911x.h | 2 +-
- include/linux/smsc911x.h | 11 ++++++++++
- 3 files changed, 53 insertions(+), 10 deletions(-)
-
---- a/drivers/net/ethernet/smsc/smsc911x.c
-+++ b/drivers/net/ethernet/smsc/smsc911x.c
-@@ -60,6 +60,7 @@
- #include <linux/of_device.h>
- #include <linux/of_gpio.h>
- #include <linux/of_net.h>
-+#include <asm/system_info.h>
- #include "smsc911x.h"
-
- #define SMSC_CHIPNAME "smsc911x"
-@@ -1514,7 +1515,7 @@ static int smsc911x_open(struct net_devi
- SMSC_WARN(pdata, ifup,
- "Timed out waiting for EEPROM busy bit to clear");
-
-- smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
-+ smsc911x_reg_write(pdata, GPIO_CFG, GPIO_CFG_LED1_EN_ | GPIO_CFG_LED2_EN_ | (1 << 20));
-
- /* The soft reset above cleared the device's MAC address,
- * restore it from local copy (set in probe) */
-@@ -1525,8 +1526,8 @@ static int smsc911x_open(struct net_devi
- /* Initialise irqs, but leave all sources disabled */
- smsc911x_disable_irq_chip(dev);
-
-- /* Set interrupt deassertion to 100uS */
-- intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
-+ /* Set interrupt deassertion to 22*10uS */
-+ intcfg = ((22 << 24) | INT_CFG_IRQ_EN_);
-
- if (pdata->config.irq_polarity) {
- SMSC_TRACE(pdata, ifup, "irq polarity: active high");
-@@ -1552,7 +1553,7 @@ static int smsc911x_open(struct net_devi
- temp |= INT_EN_SW_INT_EN_;
- smsc911x_reg_write(pdata, INT_EN, temp);
-
-- timeout = 1000;
-+ timeout = 2000;
- while (timeout--) {
- if (pdata->software_irq_signal)
- break;
-@@ -2370,6 +2371,38 @@ static inline int smsc911x_probe_config_
- }
- #endif /* CONFIG_OF */
-
-+static inline unsigned int is_gumstix_oui(u8 *addr)
-+{
-+ return (addr[0] == 0x00 && addr[1] == 0x15 && addr[2] == 0xC9);
-+}
-+
-+/**
-+ * gen_serial_ether_addr - Generate software assigned Ethernet address
-+ * based on the system_serial number
-+ * @addr: Pointer to a six-byte array containing the Ethernet address
-+ *
-+ * Generate an Ethernet address (MAC) that is not multicast
-+ * and has the local assigned bit set, keyed on the system_serial
-+ */
-+static inline void gen_serial_ether_addr(u8 *addr)
-+{
-+ static u8 ether_serial_digit = 0;
-+ addr [0] = system_serial_high >> 8;
-+ addr [1] = system_serial_high;
-+ addr [2] = system_serial_low >> 24;
-+ addr [3] = system_serial_low >> 16;
-+ addr [4] = system_serial_low >> 8;
-+ addr [5] = (system_serial_low & 0xc0) | /* top bits are from system serial */
-+ (1 << 4) | /* 2 bits identify interface type 1=ether, 2=usb, 3&4 undef */
-+ ((ether_serial_digit++) & 0x0f); /* 15 possible interfaces of each type */
-+
-+ if(!is_gumstix_oui(addr))
-+ {
-+ addr [0] &= 0xfe; /* clear multicast bit */
-+ addr [0] |= 0x02; /* set local assignment bit (IEEE802) */
-+ }
-+}
-+
- static int smsc911x_drv_probe(struct platform_device *pdev)
- {
- struct device_node *np = pdev->dev.of_node;
-@@ -2516,11 +2549,11 @@ static int smsc911x_drv_probe(struct pla
- SMSC_TRACE(pdata, probe,
- "Mac Address is read from LAN911x EEPROM");
- } else {
-- /* eeprom values are invalid, generate random MAC */
-- eth_hw_addr_random(dev);
-+ /* eeprom values are invalid, generate MAC from serial number */
-+ gen_serial_ether_addr(dev->dev_addr);
- smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
- SMSC_TRACE(pdata, probe,
-- "MAC Address is set to eth_random_addr");
-+ "MAC Address is derived from system serial number");
- }
- }
-
+++ /dev/null
-From 76a102bd5c9d792db19c6c72eafdecea0311a0c9 Mon Sep 17 00:00:00 2001
-From: Craig Hughes <craig@gumstix.com>
-Date: Fri, 30 Oct 2009 14:16:27 -0400
-Subject: [PATCH] [ARM] pxa: Gumstix Verdex PCMCIA support
-
-Needed for the Libertas CS wireless device.
-
-Signed-off-by: Bobby Powers <bobbypowers@gmail.com>
----
- drivers/pcmcia/Kconfig | 3 +-
- drivers/pcmcia/Makefile | 3 +
- drivers/pcmcia/pxa2xx_gumstix.c | 194 +++++++++++++++++++++++++++++++++++++++
- 3 files changed, 199 insertions(+), 1 deletions(-)
- create mode 100644 drivers/pcmcia/pxa2xx_gumstix.c
-
---- a/drivers/pcmcia/Kconfig
-+++ b/drivers/pcmcia/Kconfig
-@@ -217,7 +217,7 @@ config PCMCIA_PXA2XX
- || MACH_ARMCORE || ARCH_PXA_PALM || TRIZEPS_PCMCIA \
- || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2 \
- || MACH_VPAC270 || MACH_BALLOON3 || MACH_COLIBRI \
-- || MACH_COLIBRI320 || MACH_H4700)
-+ || MACH_COLIBRI320 || MACH_H4700 || ARCH_GUMSTIX)
- select PCMCIA_SA1111 if ARCH_LUBBOCK && SA1111
- select PCMCIA_SOC_COMMON
- help
---- a/drivers/pcmcia/Makefile
-+++ b/drivers/pcmcia/Makefile
-@@ -71,6 +71,9 @@ pxa2xx-obj-$(CONFIG_MACH_COLIBRI) += px
- pxa2xx-obj-$(CONFIG_MACH_COLIBRI320) += pxa2xx_colibri.o
- pxa2xx-obj-$(CONFIG_MACH_H4700) += pxa2xx_hx4700.o
-
-+pxa2xx-obj-$(CONFIG_MACH_GUMSTIX_VERDEX) += pxa2xx_cs.o
-+pxa2xx_cs-objs := pxa2xx_gumstix.o
-+
- obj-$(CONFIG_PCMCIA_PXA2XX) += pxa2xx_base.o $(pxa2xx-obj-y)
-
- obj-$(CONFIG_PCMCIA_XXS1500) += xxs1500_ss.o
---- /dev/null
-+++ b/drivers/pcmcia/pxa2xx_gumstix.c
-@@ -0,0 +1,168 @@
-+/*
-+ * linux/drivers/pcmcia/pxa2xx_gumstix.c
-+ *
-+ * Gumstix PCMCIA specific routines. Based on Mainstone
-+ *
-+ * Copyright 2004, Craig Hughes <craig@gumstix.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/gpio.h>
-+
-+#include <linux/delay.h>
-+#include <linux/platform_device.h>
-+
-+#include <linux/gpio-pxa.h>
-+
-+#include <pcmcia/ss.h>
-+
-+#include <mach/hardware.h>
-+#include <asm/mach-types.h>
-+
-+#include <mach/pxa27x.h>
-+
-+#include <asm/io.h>
-+#include <mach/gpio.h>
-+#include <mach/gumstix.h>
-+#include "soc_common.h"
-+
-+#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
-+
-+#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
-+#define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
-+
-+static int net_cf_vx_mode = 0;
-+
-+static int gumstix_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
-+{
-+/* Note: The verdex_pcmcia_pin_config is moved to gumstix_verdex.c in order to use mfp_pxa2xx_config
-+ for board-specific pin configuration instead of the old deprecated pxa_gpio_mode function. Thus,
-+ only the IRQ init is still needed to be done here. */
-+ if (skt->nr == 0) {
-+ skt->socket.pci_irq = (net_cf_vx_mode == 0) ? GUMSTIX_S0_PRDY_nBSY_IRQ : GUMSTIX_S0_PRDY_nBSY_OLD_IRQ;
-+ skt->stat[SOC_STAT_CD].gpio = GUMSTIX_S0_nCD_IRQ;
-+ skt->stat[SOC_STAT_CD].name = "CF0 nCD";
-+ skt->stat[SOC_STAT_RDY].gpio = GUMSTIX_S0_nSTSCHG_IRQ;
-+ skt->stat[SOC_STAT_RDY].name = "CF0 nSTSCHG";
-+ } else {
-+ skt->socket.pci_irq = GUMSTIX_S1_PRDY_nBSY_IRQ;
-+ skt->stat[SOC_STAT_CD].gpio = GUMSTIX_S1_nCD_IRQ;
-+ skt->stat[SOC_STAT_CD].name = "CF1 nCD";
-+ skt->stat[SOC_STAT_RDY].gpio = GUMSTIX_S1_nSTSCHG_IRQ;
-+ skt->stat[SOC_STAT_RDY].name = "CF1 nSTSCHG";
-+ }
-+
-+ return 0;
-+}
-+
-+static void gumstix_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
-+{
-+ if (net_cf_vx_mode) {
-+ gpio_free(GPIO_GUMSTIX_CF_OLD_RESET);
-+ } else {
-+ gpio_free(GPIO_GUMSTIX_CF_RESET);
-+ }
-+
-+}
-+
-+static void gumstix_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
-+ struct pcmcia_state *state)
-+{
-+ unsigned int cd, prdy_nbsy, nbvd1;
-+ if(skt->nr == 0)
-+ {
-+ cd = GPIO_GUMSTIX_nCD_0;
-+ if(net_cf_vx_mode)
-+ prdy_nbsy = GPIO_GUMSTIX_PRDY_nBSY_0_OLD;
-+ else
-+ prdy_nbsy = GPIO_GUMSTIX_PRDY_nBSY_0;
-+ nbvd1 = GPIO_GUMSTIX_nBVD1_0;
-+ } else {
-+ cd = GPIO_GUMSTIX_nCD_1;
-+ prdy_nbsy = GPIO_GUMSTIX_PRDY_nBSY_1;
-+ nbvd1 = GPIO_GUMSTIX_nBVD1_1;
-+ }
-+ state->detect = !!gpio_get_value(cd);
-+ state->ready = !!gpio_get_value(prdy_nbsy);
-+ state->bvd1 = !!gpio_get_value(nbvd1);
-+ state->bvd2 = 1;
-+ state->vs_3v = 0;
-+ state->vs_Xv = 0;
-+ state->wrprot = 0;
-+}
-+
-+static int gumstix_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
-+ const socket_state_t *state)
-+{
-+ return 0;
-+}
-+
-+static struct pcmcia_low_level gumstix_pcmcia_ops = {
-+ .owner = THIS_MODULE,
-+ .hw_init = gumstix_pcmcia_hw_init,
-+ .hw_shutdown = gumstix_pcmcia_hw_shutdown,
-+ .socket_state = gumstix_pcmcia_socket_state,
-+ .configure_socket = gumstix_pcmcia_configure_socket,
-+ .nr = 2,
-+};
-+
-+static struct platform_device *gumstix_pcmcia_device;
-+
-+extern int __init gumstix_get_cf_cards(void);
-+
-+#ifdef CONFIG_MACH_GUMSTIX_VERDEX
-+extern int __init gumstix_check_if_netCF_vx(void);
-+#endif
-+
-+static int __init gumstix_pcmcia_init(void)
-+{
-+ int ret;
-+
-+#ifdef CONFIG_MACH_GUMSTIX_VERDEX
-+ net_cf_vx_mode = gumstix_check_if_netCF_vx();
-+#endif
-+
-+ gumstix_pcmcia_ops.nr = gumstix_get_cf_cards();
-+
-+ gumstix_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
-+ if (!gumstix_pcmcia_device)
-+ return -ENOMEM;
-+
-+ ret = platform_device_add_data(gumstix_pcmcia_device, &gumstix_pcmcia_ops,
-+ sizeof(gumstix_pcmcia_ops));
-+
-+ if (ret == 0) {
-+ printk(KERN_INFO "Registering gumstix PCMCIA interface.\n");
-+ ret = platform_device_add(gumstix_pcmcia_device);
-+ }
-+
-+ if (ret)
-+ platform_device_put(gumstix_pcmcia_device);
-+
-+ return ret;
-+}
-+
-+static void __exit gumstix_pcmcia_exit(void)
-+{
-+ /*
-+ * This call is supposed to free our gumstix_pcmcia_device.
-+ * Unfortunately platform_device don't have a free method, and
-+ * we can't assume it's free of any reference at this point so we
-+ * can't free it either.
-+ */
-+ platform_device_unregister(gumstix_pcmcia_device);
-+}
-+
-+fs_initcall(gumstix_pcmcia_init);
-+module_exit(gumstix_pcmcia_exit);
-+
-+MODULE_LICENSE("GPL");
+++ /dev/null
---- a/kernel/printk.c
-+++ b/kernel/printk.c
-@@ -48,6 +48,10 @@
-
- #include <asm/uaccess.h>
-
-+#ifdef CONFIG_DEBUG_LL
-+extern void printascii(char *);
-+#endif /* CONFIG_DEBUG_LL */
-+
- #define CREATE_TRACE_POINTS
- #include <trace/events/printk.h>
-
-@@ -1578,6 +1582,10 @@ asmlinkage int vprintk_emit(int facility
- }
- }
-
-+#ifdef CONFIG_DEBUG_LL
-+ printascii(printk_buf);
-+#endif
-+
- if (level == -1)
- level = default_message_loglevel;
-
+++ /dev/null
-From 4f4bb58cba3a6c44e9f9f113609287d9d50be9c4 Mon Sep 17 00:00:00 2001
-From: Joseph Kortje <jpktech@rogers.com>
-Date: Wed, 28 Oct 2009 21:11:28 -0400
-Subject: [PATCH] [ARM] Gumstix Verdex Pro arch support
-
-add an option for Verdex Pro when ARCH_GUMSTIX is selected, and
-factor earlier Gumstix support into a seperate option
-
-Signed-off-by: Bobby Powers <bobbypowers@gmail.com>
----
- arch/arm/mach-pxa/Kconfig | 29 +-
- arch/arm/mach-pxa/Makefile | 3 +-
- arch/arm/mach-pxa/gumstix-verdex.c | 749 +++++++++++++++++++++++++++
- arch/arm/mach-pxa/include/mach/mfp-pxa27x.h | 1 +
- 4 files changed, 772 insertions(+), 10 deletions(-)
- create mode 100644 arch/arm/mach-pxa/gumstix-verdex.c
-
---- a/arch/arm/mach-pxa/Kconfig
-+++ b/arch/arm/mach-pxa/Kconfig
-@@ -134,23 +134,34 @@ config MACH_CAPC7117
- select PXA3xx
-
- config ARCH_GUMSTIX
-- bool "Gumstix XScale 255 boards"
-- select PXA25x
-+ bool "Gumstix boards"
- help
-- Say Y here if you intend to run this kernel on
-- Basix, Connex, ws-200ax, ws-400ax systems
-+ Say Y here if you intend to run this kernel on a
-+ gumstix computer.
-
--choice
-- prompt "Gumstix Carrier/Expansion Board"
- depends on ARCH_GUMSTIX
-
--config GUMSTIX_AM200EPD
-+config MACH_GUMSTIX_F
-+ bool "Gumstix Basix/Connex ..."
-+ depends on ARCH_GUMSTIX
-+ select PXA25x
-+
-+ choice
-+ prompt "Gumstix Carrier/Expansion Board"
-+ depends on MACH_GUMSTIX_F
-+
-+ config GUMSTIX_AM200EPD
- bool "Enable AM200EPD board support"
-
--config GUMSTIX_AM300EPD
-+ config GUMSTIX_AM300EPD
- bool "Enable AM300EPD board support"
-
--endchoice
-+ endchoice
-+
-+config MACH_GUMSTIX_VERDEX
-+ bool "Gumstix VERDEX ..."
-+ depends on ARCH_GUMSTIX
-+ select PXA27x
-
- config MACH_INTELMOTE2
- bool "Intel Mote 2 Platform"
---- a/arch/arm/mach-pxa/Makefile
-+++ b/arch/arm/mach-pxa/Makefile
-@@ -51,7 +51,8 @@ endif
- obj-$(CONFIG_MACH_EM_X270) += em-x270.o
- obj-$(CONFIG_MACH_CM_X300) += cm-x300.o
- obj-$(CONFIG_MACH_CAPC7117) += capc7117.o mxm8x10.o
--obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o
-+obj-$(CONFIG_MACH_GUMSTIX_F) += gumstix.o
-+obj-$(CONFIG_MACH_GUMSTIX_VERDEX) += gumstix-verdex.o
- obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o
- obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o
- obj-$(CONFIG_MACH_INTELMOTE2) += stargate2.o
---- /dev/null
-+++ b/arch/arm/mach-pxa/gumstix-verdex.c
-@@ -0,0 +1,794 @@
-+/*
-+ * linux/arch/arm/mach-pxa/gumstix-verdex.c
-+ *
-+ * Support for the Gumstix verdex motherboard.
-+ *
-+ * Original Author: Craig Hughes
-+ * Created: Feb 14, 2008
-+ * Copyright: Craig Hughes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * Implemented based on lubbock.c by Nicolas Pitre and code from Craig
-+ * Hughes
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/interrupt.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/i2c/tsc2007.h>
-+#include <linux/i2c/pxa-i2c.h>
-+#include <linux/gpio.h>
-+#include <linux/gpio-pxa.h>
-+
-+#include <asm/setup.h>
-+#include <asm/memory.h>
-+#include <asm/mach-types.h>
-+#include <asm/irq.h>
-+#include <asm/sizes.h>
-+#include <asm/io.h>
-+
-+#include <asm/mach/arch.h>
-+#include <asm/mach/map.h>
-+#include <asm/mach/irq.h>
-+#include <asm/mach/flash.h>
-+
-+#include <mach/mmc.h>
-+#include <mach/udc.h>
-+#include <mach/pxafb.h>
-+#include <mach/ohci.h>
-+#include <mach/pxa27x.h>
-+#include <mach/pxa27x-udc.h>
-+#include <mach/gpio.h>
-+
-+#include <mach/gumstix.h>
-+
-+#include "generic.h"
-+
-+#include <linux/delay.h>
-+
-+static struct resource flash_resource = {
-+ .start = 0x00000000,
-+ .end = SZ_64M - 1,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct mtd_partition gumstix_partitions[] = {
-+ {
-+ .name = "u-boot",
-+ .size = 0x00040000,
-+ .offset = 0,
-+ .mask_flags = MTD_WRITEABLE /* force read-only */
-+ } , {
-+ .name = "rootfs",
-+ .size = 0x01ec0000,
-+ .offset = 0x00040000
-+ } , {
-+ .name = "kernel",
-+ .size = 0x00100000,
-+ .offset = 0x01f00000
-+ }
-+};
-+
-+static struct flash_platform_data gumstix_flash_data = {
-+ .map_name = "cfi_probe",
-+ .parts = gumstix_partitions,
-+ .nr_parts = ARRAY_SIZE(gumstix_partitions),
-+ .width = 2,
-+};
-+
-+static struct platform_device gumstix_flash_device = {
-+ .name = "pxa2xx-flash",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &gumstix_flash_data,
-+ },
-+ .resource = &flash_resource,
-+ .num_resources = 1,
-+};
-+
-+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) \
-+ || defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
-+
-+#include <linux/smsc911x.h>
-+
-+static struct resource verdex_smsc911x_resources[] = {
-+ [0] = {
-+ .name = "smsc911x-memory",
-+ .start = PXA_CS1_PHYS,
-+ .end = PXA_CS1_PHYS + 0x000fffff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0),
-+ .end = PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0),
-+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
-+ },
-+};
-+
-+static struct smsc911x_platform_config verdex_smsc911x_config = {
-+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
-+ .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
-+ .phy_interface = PHY_INTERFACE_MODE_MII,
-+};
-+
-+static struct platform_device verdex_smsc911x_device = {
-+ .name = "smsc911x",
-+ .id = -1,
-+ .num_resources = ARRAY_SIZE(verdex_smsc911x_resources),
-+ .resource = verdex_smsc911x_resources,
-+ .dev = {
-+ .platform_data = &verdex_smsc911x_config,
-+ },
-+};
-+#endif
-+
-+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-+static void __init verdex_init_smsc911x(void)
-+{
-+
-+ printk(KERN_INFO "Initializing Gumstix verdex smsc911x\n");
-+
-+ if (gpio_request(GPIO_GUMSTIX_ETH0_RST, "SMSC911x_ETH0_RST") != 0) {
-+ printk(KERN_ERR "could not obtain gpio for SMSC911x_ETH0_RST\n");
-+ goto err_request_gpio_eth0_rst;
-+ }
-+
-+ if (gpio_request(GPIO_GUMSTIX_ETH0, "SMSC911x_ETH0_IRQ") != 0) {
-+ printk(KERN_ERR "could not obtain gpio for SMSC911x_ETH0_IRQ\n");
-+ goto err_request_gpio_eth0_irq;
-+ }
-+
-+ if (gpio_direction_output(GPIO_GUMSTIX_ETH0_RST, 0) != 0) {
-+ printk(KERN_ERR "could not set SMSC911x_ETH0_RST pin to output\n");
-+ goto err_dir;
-+ }
-+
-+ gpio_set_value(GPIO_GUMSTIX_ETH0_RST, 0);
-+
-+ msleep(500); // Hold RESET for at least 200ms
-+
-+ gpio_set_value(GPIO_GUMSTIX_ETH0_RST, 1);
-+
-+ msleep(50);
-+
-+ if (gpio_direction_input(GPIO_GUMSTIX_ETH0) != 0) {
-+ printk(KERN_ERR "could not set SMSC911x_ETH0_IRQ pin to input\n");
-+ goto err_dir;
-+ }
-+
-+ gpio_export(GPIO_GUMSTIX_ETH0, 0);
-+ platform_device_register(&verdex_smsc911x_device);
-+ return;
-+
-+err_dir:
-+ gpio_free(GPIO_GUMSTIX_ETH0_RST);
-+
-+err_request_gpio_eth0_irq:
-+ gpio_free(GPIO_GUMSTIX_ETH0);
-+
-+err_request_gpio_eth0_rst:
-+ return;
-+}
-+
-+#else
-+static void __init verdex_init_smsc911x(void) { return; }
-+#endif
-+
-+static unsigned long verdex_pin_config[] = {
-+ /* MMC */
-+ GPIO32_MMC_CLK,
-+ GPIO112_MMC_CMD,
-+ GPIO92_MMC_DAT_0,
-+ GPIO109_MMC_DAT_1,
-+ GPIO110_MMC_DAT_2,
-+ GPIO111_MMC_DAT_3,
-+
-+ /* BTUART */
-+ GPIO42_BTUART_RXD,
-+ GPIO43_BTUART_TXD,
-+ GPIO44_BTUART_CTS,
-+ GPIO45_BTUART_RTS,
-+
-+ /* STUART */
-+ GPIO46_STUART_RXD,
-+ GPIO47_STUART_TXD,
-+
-+ /* FFUART */
-+ GPIO34_FFUART_RXD,
-+ GPIO39_FFUART_TXD,
-+
-+ /* SSP 2 */
-+ GPIO19_SSP2_SCLK,
-+ GPIO14_SSP2_SFRM,
-+ GPIO13_SSP2_TXD,
-+ GPIO11_SSP2_RXD,
-+
-+ /* SDRAM and local bus */
-+ GPIO49_nPWE,
-+ GPIO15_nCS_1,
-+
-+ /* I2C */
-+ GPIO117_I2C_SCL,
-+ GPIO118_I2C_SDA,
-+
-+ /* PWM 0 */
-+ GPIO16_PWM0_OUT,
-+
-+ /* BRIGHTNESS */
-+ GPIO17_PWM1_OUT,
-+
-+ /* LCD */
-+ GPIO58_LCD_LDD_0,
-+ GPIO59_LCD_LDD_1,
-+ GPIO60_LCD_LDD_2,
-+ GPIO61_LCD_LDD_3,
-+ GPIO62_LCD_LDD_4,
-+ GPIO63_LCD_LDD_5,
-+ GPIO64_LCD_LDD_6,
-+ GPIO65_LCD_LDD_7,
-+ GPIO66_LCD_LDD_8,
-+ GPIO67_LCD_LDD_9,
-+ GPIO68_LCD_LDD_10,
-+ GPIO69_LCD_LDD_11,
-+ GPIO70_LCD_LDD_12,
-+ GPIO71_LCD_LDD_13,
-+ GPIO72_LCD_LDD_14,
-+ GPIO73_LCD_LDD_15,
-+ GPIO74_LCD_FCLK,
-+ GPIO75_LCD_LCLK,
-+ GPIO76_LCD_PCLK,
-+#ifdef CONFIG_FB_PXA_SHARP_LQ043_PSP
-+ /* DISP must be always high while screen is on */
-+ /* Done below in verdex_init */
-+#else
-+ GPIO77_LCD_BIAS,
-+#endif
-+};
-+
-+#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
-+
-+static unsigned long gpio_ntschg_0[] = {
-+ GPIO104_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_nCD_0_MD);
-+};
-+
-+static unsigned long gpio_ntschg_1[] = {
-+ GPIO18_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_nSTSCHG_1_MD);
-+ GPIO36_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_nCD_1_MD);
-+ GPIO27_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_PRDY_nBSY_1_MD);
-+};
-+
-+static unsigned long gpio_prdy_nbsy_old[] = {
-+ GPIO111_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_nSTSCHG_0_MD);
-+ GPIO109_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_PRDY_nBSY_0_OLD_MD);
-+};
-+
-+static unsigned long gpio_prdy_nbsy[] = {
-+ GPIO96_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_PRDY_nBSY_0_MD);
-+};
-+
-+static unsigned long gpio_nhw_init[] = {
-+ GPIO48_nPOE, // pxa_gpio_mode(GPIO_GUMSTIX_nPOE_MD);
-+ GPIO102_nPCE_1, // pxa_gpio_mode(GPIO_GUMSTIX_nPCE_1_MD);
-+ GPIO105_nPCE_2, // pxa_gpio_mode(GPIO_GUMSTIX_nPCE_2_MD);
-+ GPIO104_GPIO, // pxa_gpio_mode(GPIO_GUMSTIX_nCD_0_MD);
-+
-+ GPIO49_nPWE, // pxa_gpio_mode(GPIO_GUMSTIX_nPWE_MD);
-+ GPIO50_nPIOR, // pxa_gpio_mode(GPIO_GUMSTIX_nPIOR_MD);
-+ GPIO51_nPIOW, // pxa_gpio_mode(GPIO_GUMSTIX_nPIOW_MD);
-+ GPIO79_PSKTSEL, // pxa_gpio_mode(GPIO_GUMSTIX_pSKTSEL_MD);
-+ GPIO55_nPREG, // pxa_gpio_mode(GPIO_GUMSTIX_nPREG_MD);
-+ GPIO56_nPWAIT, // pxa_gpio_mode(GPIO_GUMSTIX_nPWAIT_MD);
-+ GPIO57_nIOIS16, // pxa_gpio_mode(GPIO_GUMSTIX_nIOIS16_MD);
-+};
-+
-+static int net_cf_vx_mode = 0;
-+static int pcmcia_cf_nr = 2;
-+
-+inline void __init gumstix_pcmcia_cpld_clk(void)
-+{
-+ gpio_set_value(GPIO_GUMSTIX_nPOE, 0);
-+ gpio_set_value(GPIO_GUMSTIX_nPOE, 1);
-+}
-+
-+inline unsigned char __init gumstix_pcmcia_cpld_read_bits(int bits)
-+{
-+ unsigned char result = 0;
-+ unsigned int shift = 0;
-+ while(bits--)
-+ {
-+ result |= !!(gpio_get_value(GPIO_GUMSTIX_nCD_0) & GPIO_bit(GPIO_GUMSTIX_nCD_0)) << shift;
-+ shift ++;
-+ gumstix_pcmcia_cpld_clk();
-+ }
-+ printk("CPLD responded with: %02x\n",result);
-+ return result;
-+}
-+
-+/* We use the CPLD on the CF-CF card to read a value from a shift register. If we can read that
-+ * magic sequence, then we have 2 CF cards; otherwise we assume just one
-+ * The CPLD will send the value of the shift register on GPIO11 (the CD line for slot 0)
-+ * when RESET is held in reset. We use GPIO48 (nPOE) as a clock signal,
-+ * GPIO52/53 (card enable for both cards) to control read/write to the shift register
-+ */
-+static void __init gumstix_count_cards(void)
-+{
-+ if ((gpio_request(GPIO_GUMSTIX_nPOE, "GPIO_GUMSTIX_nPOE") == 0) &&
-+ (gpio_direction_output(GPIO_GUMSTIX_nPOE, 1) == 0))
-+ gpio_export(GPIO_GUMSTIX_nPOE, 0);
-+ else
-+ printk(KERN_ERR "could not obtain gpio for GPIO_GUMSTIX_nPOE\n");
-+
-+ if ((gpio_request(GPIO_GUMSTIX_nPCE_1, "GPIO_GUMSTIX_nPCE_1") == 0) &&
-+ (gpio_direction_output(GPIO_GUMSTIX_nPCE_1, 1) == 0))
-+ gpio_export(GPIO_GUMSTIX_nPCE_1, 0);
-+ else
-+ printk(KERN_ERR "could not obtain gpio for GPIO_GUMSTIX_nPCE_1\n");
-+
-+ if ((gpio_request(GPIO_GUMSTIX_nPCE_2, "GPIO_GUMSTIX_nPCE_2") == 0) &&
-+ (gpio_direction_output(GPIO_GUMSTIX_nPCE_2, 1) == 0))
-+ gpio_export(GPIO_GUMSTIX_nPCE_2, 0);
-+ else
-+ printk(KERN_ERR "could not obtain gpio for GPIO_GUMSTIX_nPCE_2\n");
-+
-+ if ((gpio_request(GPIO_GUMSTIX_nCD_0, "GPIO_GUMSTIX_nCD_0") == 0) &&
-+ (gpio_direction_input(GPIO_GUMSTIX_nCD_0) == 0))
-+ gpio_export(GPIO_GUMSTIX_nCD_0, 0);
-+ else
-+ printk(KERN_ERR "could not obtain gpio for GPIO_GUMSTIX_nCD_0\n");
-+
-+ if (net_cf_vx_mode) {
-+ if ((gpio_request(GPIO_GUMSTIX_CF_OLD_RESET, "GPIO_GUMSTIX_CF_OLD_RESET") == 0) &&
-+ (gpio_direction_output(GPIO_GUMSTIX_CF_OLD_RESET, 1) == 0)) {
-+ gpio_export(GPIO_GUMSTIX_CF_OLD_RESET, 0);
-+ } else {
-+ printk(KERN_ERR "could not obtain gpio for GPIO_GUMSTIX_CF_OLD_RESET\n");
-+ }
-+ } else {
-+ if ((gpio_request(GPIO_GUMSTIX_CF_RESET, "GPIO_GUMSTIX_CF_RESET") == 0) &&
-+ (gpio_direction_output(GPIO_GUMSTIX_CF_RESET, 1) == 0)) {
-+ gpio_export(GPIO_GUMSTIX_CF_RESET, 0);
-+ } else {
-+ printk(KERN_ERR "could not obtain gpio for GPIO_GUMSTIX_CF_RESET\n");
-+ }
-+ }
-+
-+ // Setup the shift register
-+ gpio_set_value(GPIO_GUMSTIX_nPCE_1, 1);
-+ gpio_set_value(GPIO_GUMSTIX_nPCE_2, 0);
-+
-+ // Tick the clock to program the shift register
-+ gumstix_pcmcia_cpld_clk();
-+
-+ // Now set shift register into read mode
-+ gpio_set_value(GPIO_GUMSTIX_nPCE_1, 0);
-+ gpio_set_value(GPIO_GUMSTIX_nPCE_2, 1);
-+
-+ // We can read the bits now -- 0xC2 means "Dual compact flash"
-+ if(gumstix_pcmcia_cpld_read_bits(8) != 0xC2)
-+ {
-+ // We do not have 2 CF slots
-+ pcmcia_cf_nr = 1;
-+ }
-+
-+ udelay(50);
-+
-+ if (net_cf_vx_mode) {
-+ gpio_set_value(GPIO_GUMSTIX_CF_OLD_RESET, 0);
-+ gpio_free(GPIO_GUMSTIX_CF_OLD_RESET);
-+ } else {
-+ gpio_set_value(GPIO_GUMSTIX_CF_RESET, 0);
-+ gpio_free(GPIO_GUMSTIX_CF_RESET);
-+ }
-+
-+ printk(KERN_INFO "found %d CF slots\n", pcmcia_cf_nr);
-+
-+ gpio_free(GPIO_GUMSTIX_nPCE_2);
-+ gpio_free(GPIO_GUMSTIX_nPCE_1);
-+ gpio_free(GPIO_GUMSTIX_nPOE);
-+ return;
-+}
-+
-+#define SMC_IO_EXTENT 16
-+#define BANK_SELECT 14
-+
-+static void __init verdex_pcmcia_pin_config(void)
-+{
-+ struct resource *res;
-+ void *network_controller_memory;
-+ struct platform_device *pdev = &verdex_smsc911x_device;
-+
-+ printk(KERN_INFO "Initializing Gumstix verdex pcmcia\n");
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (res == NULL) {
-+ printk(KERN_ERR "no memory resource defined\n");
-+ goto err_done;
-+ }
-+
-+ res = request_mem_region(res->start, SMC_IO_EXTENT, "smc91x probe");
-+ if (res == NULL) {
-+ printk(KERN_ERR "failed to request memory resource\n");
-+ goto err_done;
-+ }
-+
-+ // We check for the possibility of SMSC91c111 (reg base offset 0x300 from CS1 base)
-+ network_controller_memory = ioremap(res->start + 0x300, SMC_IO_EXTENT);
-+ if (network_controller_memory == NULL) {
-+ printk(KERN_ERR "failed to ioremap() registers\n");
-+ goto err_free_mem;
-+ }
-+
-+ // Look for the special 91c111 value in the bank select register
-+ if((0xff00 & readw(network_controller_memory+BANK_SELECT)) == 0x3300) {
-+ printk(KERN_INFO "Detected netCF-vx board: pcmcia using older GPIO configuration\n");
-+ net_cf_vx_mode = 1;
-+ } else {
-+ printk(KERN_INFO "Not netCF-vx board: pcmcia using newer GPIO configuration\n");
-+ net_cf_vx_mode = 0;
-+ }
-+
-+ iounmap(network_controller_memory);
-+err_free_mem:
-+ release_mem_region(res->start, SMC_IO_EXTENT);
-+err_done:
-+
-+ gumstix_count_cards(); // this can update pcmcia_cf_nr
-+
-+ // If pcmcia_cf_nr is 1 then we do not have 2 CF slots
-+ // Note: logic sequence was altered from previous kernel revs
-+ // so that this works as intended now.
-+ if (pcmcia_cf_nr != 0)
-+ {
-+ pxa2xx_mfp_config(ARRAY_AND_SIZE(gpio_ntschg_0));
-+
-+ if(net_cf_vx_mode)
-+ pxa2xx_mfp_config(gpio_prdy_nbsy_old, 1);
-+ else
-+ pxa2xx_mfp_config(gpio_prdy_nbsy, 1);
-+
-+ } else {
-+ // Note: this reconfigures pin GPIO18 to be GPIO-IN so make
-+ // sure that this only gets done for the old dual slot board
-+ // since that pin is an active AF1 out-mode signal (RDY) on
-+ // newer boards and changing the pin mode on the newer boards
-+ // would result in memory corruption for the NIC (and hang during
-+ // PHY test).
-+ pxa2xx_mfp_config(ARRAY_AND_SIZE(gpio_ntschg_1));
-+ }
-+
-+ pxa2xx_mfp_config(ARRAY_AND_SIZE(gpio_nhw_init));
-+ return;
-+}
-+
-+int __init gumstix_get_cf_cards(void)
-+{
-+ return pcmcia_cf_nr;
-+}
-+EXPORT_SYMBOL(gumstix_get_cf_cards);
-+
-+#ifdef CONFIG_MACH_GUMSTIX_VERDEX
-+int __init gumstix_check_if_netCF_vx(void)
-+{
-+ return net_cf_vx_mode;
-+}
-+EXPORT_SYMBOL(gumstix_check_if_netCF_vx);
-+#endif
-+
-+#endif
-+
-+#if defined(CONFIG_FB_PXA_SHARP_LQ043_PSP) || defined(CONFIG_FB_PXA_SAMSUNG_LTE430WQ_F0C)
-+static void gumstix_lcd_backlight(int on_or_off)
-+{
-+ int err;
-+ err = gpio_request(17, "LCD BACKLIGHT");
-+ if (err) {
-+ //pr_warning("Gumstix Verdex: Failed to request LCD Backlight gpio\n");
-+ return;
-+ }
-+
-+ if(on_or_off) {
-+ gpio_direction_input(17);
-+ } else {
-+ gpio_set_value(17, 0);
-+ gpio_direction_output(17, 0);
-+ gpio_set_value(17, 0);
-+ }
-+
-+ return;
-+}
-+#endif
-+
-+#ifdef CONFIG_FB_PXA_ALPS_CDOLLAR
-+static struct pxafb_mode_info gumstix_fb_mode = {
-+ .pixclock = 300000,
-+ .xres = 240,
-+ .yres = 320,
-+ .bpp = 16,
-+ .hsync_len = 2,
-+ .left_margin = 1,
-+ .right_margin = 1,
-+ .vsync_len = 3,
-+ .upper_margin = 0,
-+ .lower_margin = 0,
-+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-+};
-+
-+static struct pxafb_mach_info gumstix_fb_info = {
-+ .modes = &gumstix_fb_mode,
-+ .num_modes = 1,
-+ .lccr0 = LCCR0_Pas | LCCR0_Sngl | LCCR0_Color,
-+ .lccr3 = LCCR3_PixFlEdg,
-+};
-+#elif defined(CONFIG_FB_PXA_SHARP_LQ043_PSP)
-+static struct pxafb_mode_info gumstix_fb_mode = {
-+ .pixclock = 110000,
-+ .xres = 480,
-+ .yres = 272,
-+ .bpp = 16,
-+ .hsync_len = 41,
-+ .left_margin = 2,
-+ .right_margin = 2,
-+ .vsync_len = 10,
-+ .upper_margin = 2,
-+ .lower_margin = 2,
-+ .sync = 0, // Hsync and Vsync both active low
-+};
-+
-+static struct pxafb_mach_info gumstix_fb_info = {
-+ .modes = &gumstix_fb_mode,
-+ .num_modes = 1,
-+ .lccr0 = LCCR0_Act | LCCR0_Sngl | LCCR0_Color,
-+ .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | (0 << 30),
-+ .pxafb_backlight_power = &gumstix_lcd_backlight,
-+};
-+#elif defined(CONFIG_FB_PXA_SAMSUNG_LTE430WQ_F0C)
-+static struct pxafb_mode_info gumstix_fb_mode = {
-+ .pixclock = 108696, // 9.2MHz typical DOTCLK from datasheet
-+ .xres = 480,
-+ .hsync_len = 41, // HLW from datasheet: 41 typ
-+ .left_margin = 4, // HBP - HLW from datasheet: 45 - 41 = 4
-+ .right_margin = 8, // HFP from datasheet: 8 typ
-+ .yres = 272,
-+ .vsync_len = 10, // VLW from datasheet: 10 typ
-+ .upper_margin = 2, // VBP - VLW from datasheet: 12 - 10 = 2
-+ .lower_margin = 4, // VFP from datasheet: 4 typ
-+ .bpp = 16,
-+ .sync = 0, // Hsync and Vsync both active low
-+};
-+
-+static struct pxafb_mach_info gumstix_fb_info = {
-+ .modes = &gumstix_fb_mode,
-+ .num_modes = 1,
-+ .lccr0 = LCCR0_Act | LCCR0_Sngl | LCCR0_Color,
-+ .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | (0 << 30),
-+ .pxafb_backlight_power = &gumstix_lcd_backlight,
-+};
-+#endif
-+
-+static struct platform_device verdex_audio_device = {
-+ .name = "pxa2xx-ac97",
-+ .id = -1,
-+};
-+
-+static struct platform_device *devices[] __initdata = {
-+ &gumstix_flash_device,
-+ &verdex_audio_device,
-+};
-+
-+/* PXA27x OHCI controller setup */
-+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-+static int ohci_verdex_init(struct device *dev)
-+{
-+ // Turn on port 2 in host mode
-+ UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
-+
-+ /* See drivers/usb/host/ohci-pxa27x.c for further details but
-+ ENABLE_PORT_ALL flag is equivalent to using this old sequence:
-+ UHCHR = (UHCHR) &
-+ ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
-+ */
-+ return 0;
-+}
-+
-+static struct pxaohci_platform_data verdex_ohci_platform_data = {
-+ .port_mode = PMM_PERPORT_MODE,
-+ .flags = ENABLE_PORT_ALL,
-+ .init = ohci_verdex_init,
-+};
-+
-+static void __init verdex_ohci_init(void)
-+{
-+ pxa_set_ohci_info(&verdex_ohci_platform_data);
-+}
-+#else
-+static void __init verdex_ohci_init(void) {
-+ printk(KERN_INFO "Gumstix verdex host usb ohci is disabled\n");
-+}
-+#endif
-+
-+
-+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-+static struct pxamci_platform_data verdex_mci_platform_data;
-+
-+static int verdex_mci_init(struct device *dev, irq_handler_t detect_int,
-+ void *data)
-+{
-+ /* GPIO setup for MMC on the 120-pin connector is done in verdex_init.
-+ * There is no card detect on a uSD connector so no interrupt to
-+ * register. There is no WP detect GPIO line either.
-+ */
-+
-+ return 0;
-+}
-+
-+static struct pxamci_platform_data verdex_mci_platform_data = {
-+ .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
-+ .init = verdex_mci_init,
-+ .gpio_card_detect = -1,
-+ .gpio_card_ro = -1,
-+ .gpio_power = -1,
-+};
-+
-+static void __init verdex_mmc_init(void)
-+{
-+ pxa_set_mci_info(&verdex_mci_platform_data);
-+}
-+#else
-+static void __init verdex_mmc_init(void)
-+{
-+ printk(KERN_INFO "Gumstix verdex mmc disabled\n");
-+}
-+#endif
-+
-+#if defined(CONFIG_USB_GADGET_PXA2XX) || defined(CONFIG_USB_GADGET_PXA2XX_MODULE)
-+static struct pxa2xx_udc_mach_info verdex_udc_info __initdata = {
-+ .gpio_vbus = GPIO35,
-+ .gpio_pullup = GPIO41,
-+};
-+
-+static void __init verdex_udc_init(void)
-+{
-+ pxa_set_udc_info(&verdex_udc_info);
-+}
-+#else
-+static void __init verdex_udc_init(void)
-+{
-+ printk(KERN_INFO "Gumstix verdex udc is disabled\n");
-+}
-+#endif
-+
-+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-+
-+#if defined(CONFIG_TOUCHSCREEN_TSC2003) || defined(CONFIG_TOUCHSCREEN_TSC2003_MODULE)
-+
-+#define VERDEX_GPIO_PENDOWN 16
-+
-+static int tsc2003_init_platform_hw(void)
-+{
-+ return 0;
-+}
-+
-+static void tsc2003_exit_platform_hw(void)
-+{
-+ return;
-+}
-+
-+static void tsc2003_clear_penirq(void)
-+{
-+ return;
-+}
-+
-+static int tsc2003_get_pendown_state(void)
-+{
-+ return !gpio_get_value(VERDEX_GPIO_PENDOWN);
-+}
-+
-+static struct tsc2007_platform_data tsc2003_config = {
-+ .model = 2003,
-+ .x_plate_ohms = 100,
-+ .get_pendown_state = tsc2003_get_pendown_state,
-+ .clear_penirq = tsc2003_clear_penirq,
-+ .init_platform_hw = tsc2003_init_platform_hw,
-+ .exit_platform_hw = tsc2003_exit_platform_hw,
-+};
-+#endif
-+
-+static struct i2c_board_info __initdata verdex_i2c_board_info[] = {
-+#if defined(CONFIG_RTC_DRV_DS1307) || defined(CONFIG_RTC_DRV_DS1307_MODULE)
-+ {
-+ I2C_BOARD_INFO("rtc-ds1307", 0x68),
-+ },
-+#endif
-+#if defined(CONFIG_TOUCHSCREEN_TSC2003) || defined(CONFIG_TOUCHSCREEN_TSC2003_MODULE)
-+ {
-+ I2C_BOARD_INFO("tsc2003", 0x48),
-+ .platform_data = &tsc2003_config,
-+ .irq = IRQ_GPIO(VERDEX_GPIO_PENDOWN),
-+ },
-+#endif
-+};
-+
-+static struct i2c_pxa_platform_data verdex_i2c_pwr_info = {
-+ .fast_mode = 1,
-+};
-+
-+static struct i2c_pxa_platform_data verdex_i2c_info = {
-+ .fast_mode = 1,
-+};
-+
-+static void __init verdex_i2c_init(void)
-+{
-+ printk(KERN_INFO "Initializing Gumstix verdex i2c\n");
-+
-+#if defined(CONFIG_TOUCHSCREEN_TSC2003) || defined(CONFIG_TOUCHSCREEN_TSC2003_MODULE)
-+ if ((gpio_request(VERDEX_GPIO_PENDOWN, "TSC2003_PENDOWN") == 0) &&
-+ (gpio_direction_input(VERDEX_GPIO_PENDOWN) == 0)) {
-+ gpio_export(VERDEX_GPIO_PENDOWN, 0);
-+ } else {
-+ printk(KERN_ERR "could not obtain gpio for TSC2003_PENDOWN\n");
-+ return;
-+ }
-+#endif
-+
-+ i2c_register_board_info(0, verdex_i2c_board_info,
-+ ARRAY_SIZE(verdex_i2c_board_info));
-+ pxa_set_i2c_info(&verdex_i2c_info);
-+ pxa27x_set_i2c_power_info(&verdex_i2c_pwr_info);
-+}
-+#else
-+static inline void verdex_i2c_init(void) {}
-+#endif
-+
-+#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
-+static void __init verdex_pcmcia_init(void)
-+{
-+ verdex_pcmcia_pin_config();
-+}
-+#else
-+static void __init verdex_pcmcia_init(void) {
-+ printk(KERN_INFO "Gumstix verdex pcmcia is disabled\n");
-+}
-+#endif
-+
-+
-+static void __init verdex_init(void)
-+{
-+ pxa2xx_mfp_config(ARRAY_AND_SIZE(verdex_pin_config));
-+
-+#ifdef CONFIG_FB_PXA_SHARP_LQ043_PSP
-+ /* DISP must be always high while screen is on */
-+ gpio_direction_output(GPIO77, 0);
-+ gpio_set_value(GPIO77, 1);
-+#endif
-+ verdex_udc_init();
-+ verdex_mmc_init();
-+ verdex_ohci_init();
-+ verdex_i2c_init();
-+ verdex_init_smsc911x();
-+ verdex_pcmcia_init();
-+
-+#if defined(CONFIG_FB_PXA_ALPS_CDOLLAR) || defined(CONFIG_FB_PXA_SHARP_LQ043_PSP) || defined(CONFIG_FB_PXA_SAMSUNG_LTE430WQ_F0C)
-+ printk(KERN_INFO "Initializing Gumstix verdex FB info\n");
-+ set_pxa_fb_info(&gumstix_fb_info);
-+#endif
-+ printk(KERN_INFO "Initializing Gumstix platform_add_devices\n");
-+ (void) platform_add_devices(devices, ARRAY_SIZE(devices));
-+}
-+
-+MACHINE_START(GUMSTIX, "Gumstix verdex")
-+ .atag_offset = 0x100, /* match u-boot bi_boot_params */
-+ .map_io = pxa27x_map_io,
-+ .init_irq = pxa27x_init_irq,
-+ .handle_irq = pxa27x_handle_irq,
-+ .timer = &pxa_timer,
-+ .init_machine = verdex_init,
-+ .restart = pxa_restart,
-+MACHINE_END
---- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
-+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
-@@ -109,6 +109,7 @@
- #define GPIO54_nPCE_2 MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
- #define GPIO78_nPCE_2 MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH)
- #define GPIO87_nPCE_2 MFP_CFG_IN(GPIO87, AF1)
-+#define GPIO105_nPCE_2 MFP_CFG_OUT(GPIO105, AF1, DRIVE_HIGH)
- #define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
- #define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
- #define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
+++ /dev/null
-From eb92a178eceae4e5d18bbb442b8e44cb88457d60 Mon Sep 17 00:00:00 2001
-From: Joseph Kortje <jpktech@rogers.com>
-Date: Wed, 28 Oct 2009 21:25:57 -0400
-Subject: [PATCH] [ARM] Gumstix Verdex LCD config options
-
-add options to Kconfig for Verdex LCD support
-
-Signed-off-by: Bobby Powers <bobbypowers@gmail.com>
----
- drivers/video/Kconfig | 31 +++++++++++++++++++++++++++++++
- 1 files changed, 31 insertions(+), 0 deletions(-)
-
---- a/drivers/video/Kconfig
-+++ b/drivers/video/Kconfig
-@@ -1892,6 +1892,37 @@ config FB_PXA
- say M here and read <file:Documentation/kbuild/modules.txt>.
-
- If unsure, say N.
-+choice
-+ depends on FB_PXA
-+ prompt "LCD Panel"
-+ default FB_PXA_SAMSUNG_LTE430WQ_F0C
-+
-+config FB_PXA_ALPS_CDOLLAR
-+ boolean "Chris Dollar's ALPS screen"
-+ ---help---
-+ Enable definitions (over-ridable on the kernel command line if
-+ "PXA LCD command line parameters" is also selected) for an ALPS
-+ screen which Chris Dollar uses
-+
-+config FB_PXA_SHARP_LQ043_PSP
-+ boolean "SHARP LQ043... series"
-+ ---help---
-+ Enable definitions (over-ridable on the kernel command line if
-+ "PXA LCD command line parameters" is also selected) for a SHARP
-+ LQ043... screen, such as the one used by the PSP. These screens are
-+ the ones normally sold by gumstix with its boards.
-+
-+config FB_PXA_SAMSUNG_LTE430WQ_F0C
-+ boolean "Samsung LTE430WQ-F0C (standard gumstix LCD)"
-+ ---help---
-+ Enable definitions for a Samsung LTE430WQ-F0C LCD panel, such as the ones resold
-+ by gumstix for use with their "LCD-Ready" boards.
-+
-+config FB_PXA_NONEOFTHEABOVE
-+ boolean "None of the above"
-+
-+endchoice
-+
-
- config FB_PXA_OVERLAY
- bool "Support PXA27x/PXA3xx Overlay(s) as framebuffer"
+++ /dev/null
-From adb6abbe4e3bc17c20cdc70e4a4357f1633d4970 Mon Sep 17 00:00:00 2001
-From: Joseph Kortje <jpktech@rogers.com>
-Date: Wed, 28 Oct 2009 21:49:11 -0400
-Subject: [PATCH] [ARM] gumstix.h: Verdex Pro support
-
-Added a bunch of ifdefs to support both original gumstix boards
-as well as the Verdex Pro in gumstix.h
-
-Signed-off-by: Bobby Powers <bobbypowers@gmail.com>
----
- arch/arm/mach-pxa/include/mach/gumstix.h | 160 ++++++++++++++++++++++++------
- 1 files changed, 130 insertions(+), 30 deletions(-)
-
---- a/arch/arm/mach-pxa/include/mach/gumstix.h
-+++ b/arch/arm/mach-pxa/include/mach/gumstix.h
-@@ -6,6 +6,9 @@
- * published by the Free Software Foundation.
- */
-
-+#if !defined(__ASM_ARCH_MFP_PXA27X_H) && !defined(__ASM_ARCH_MFP_PXA25X_H)
-+ #error You need to include either mfp-pxa27x.h or mfp-pxa25x.h
-+#endif
-
- /* BTRESET - Reset line to Bluetooth module, active low signal. */
- #define GPIO_GUMSTIX_BTRESET 7
-@@ -20,9 +23,18 @@ this moves to GPIO17 and GPIO37. */
- /* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn
- has detected a cable insertion; driven low otherwise. */
-
-+#ifndef CONFIG_MACH_GUMSTIX_VERDEX
-+
- #define GPIO_GUMSTIX_USB_GPIOn 35
- #define GPIO_GUMSTIX_USB_GPIOx 41
-
-+#else
-+
-+#define GPIO_GUMSTIX_USB_GPIOn 100
-+#define GPIO_GUMSTIX_USB_GPIOx 27
-+
-+#endif
-+
- /* usb state change */
- #define GUMSTIX_USB_INTR_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_USB_GPIOn)
-
-@@ -42,48 +54,136 @@ has detected a cable insertion; driven l
- * ETH_RST provides a hardware reset line to the ethernet chip
- * ETH is the IRQ line in from the ethernet chip to the PXA
- */
-+#ifndef CONFIG_MACH_GUMSTIX_VERDEX
- #define GPIO_GUMSTIX_ETH0_RST 80
--#define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
-+#define GPIO_GUMSTIX_ETH0 36
-+#else
-+#define GPIO_GUMSTIX_ETH0_RST 107
-+#define GPIO_GUMSTIX_ETH0 99
-+#endif
- #define GPIO_GUMSTIX_ETH1_RST 52
--#define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
-+#define GPIO_GUMSTIX_ETH1 27
-
--#define GPIO_GUMSTIX_ETH0 36
-+#define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
-+#define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
- #define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN)
--#define GUMSTIX_ETH0_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0)
--#define GPIO_GUMSTIX_ETH1 27
- #define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN)
--#define GUMSTIX_ETH1_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1)
--
-
--/* CF reset line */
--#define GPIO8_RESET 8
-+#define GUMSTIX_ETH0_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0)
-+#define GUMSTIX_ETH1_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1)
-
--/* CF slot 0 */
--#define GPIO4_nBVD1 4
--#define GPIO4_nSTSCHG GPIO4_nBVD1
--#define GPIO11_nCD 11
--#define GPIO26_PRDY_nBSY 26
--#define GUMSTIX_S0_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO4_nSTSCHG)
--#define GUMSTIX_S0_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO11_nCD)
--#define GUMSTIX_S0_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO26_PRDY_nBSY)
-+ /* CF reset line */
-+#define GPIO8_CF_RESET 8
-+#define GPIO97_CF_RESET 97
-+#define GPIO110_CF_RESET 110
-+
-+#ifndef CONFIG_MACH_GUMSTIX_VERDEX
-+#define GPIO_GUMSTIX_CF_RESET GPIO8_CF_RESET
-+#else
-+#define GPIO_GUMSTIX_CF_RESET GPIO97_CF_RESET
-+#endif
-+
-+#define GPIO_GUMSTIX_CF_OLD_RESET GPIO110_CF_RESET
-+
-+/* CF signals shared by both sockets */
-+#define GPIO_GUMSTIX_nPOE 48
-+#define GPIO_GUMSTIX_nPWE 49
-+#define GPIO_GUMSTIX_nPIOR 50
-+#define GPIO_GUMSTIX_nPIOW 51
-+
-+#ifndef CONFIG_MACH_GUMSTIX_VERDEX
-+#define GPIO_GUMSTIX_nPCE_1 52
-+#define GPIO_GUMSTIX_nPCE_2 53
-+#define GPIO_GUMSTIX_pSKTSEL 54
-+#else
-+#define GPIO_GUMSTIX_nPCE_1 102
-+#define GPIO_GUMSTIX_nPCE_2 105
-+#define GPIO_GUMSTIX_pSKTSEL 79
-+#endif
-+
-+#define GPIO_GUMSTIX_nPREG 55
-+#define GPIO_GUMSTIX_nPWAIT 56
-+#define GPIO_GUMSTIX_nIOIS16 57
-+
-+/* Pin mode definitions correspond to mfp-pxa2[57]x.h */
-+#define GPIO_GUMSTIX_nPOE_MD GPIO48_nPOE
-+#define GPIO_GUMSTIX_nPWE_MD GPIO49_nPWE
-+#define GPIO_GUMSTIX_nPIOR_MD GPIO50_nPIOR
-+#define GPIO_GUMSTIX_nPIOW_MD GPIO51_nPIOW
-+
-+#ifndef CONFIG_MACH_GUMSTIX_VERDEX
-+#define GPIO_GUMSTIX_nPCE_1_MD GPIO52_nPCE_1
-+#define GPIO_GUMSTIX_nPCE_2_MD GPIO53_nPCE_2
-+#define GPIO_GUMSTIX_pSKTSEL_MD GPIO54_pSKTSEL
-+#else
-+#define GPIO_GUMSTIX_nPCE_1_MD GPIO102_nPCE_1
-+#define GPIO_GUMSTIX_nPCE_2_MD GPIO105_nPCE_2
-+#define GPIO_GUMSTIX_pSKTSEL_MD GPIO79_pSKTSEL
-+#endif
-+
-+#define GPIO_GUMSTIX_nPREG_MD GPIO55_nPREG
-+#define GPIO_GUMSTIX_nPWAIT_MD GPIO56_nPWAIT
-+#define GPIO_GUMSTIX_nIOIS16_MD GPIO57_nIOIS16
-+
-+ /* CF slot 0 */
-+#define GPIO4_nBVD1_0 4
-+#define GPIO4_nSTSCHG_0 GPIO4_nBVD1_0
-+#define GPIO11_nCD_0 11
-+#define GPIO26_PRDY_nBSY_0 26
-+
-+#define GPIO111_nBVD1_0 111
-+#define GPIO111_nSTSCHG_0 GPIO111_nBVD1_0
-+#define GPIO104_nCD_0 104
-+#define GPIO96_PRDY_nBSY_0 96
-+#define GPIO109_PRDY_nBSY_0 109
-+
-+#ifndef CONFIG_MACH_GUMSTIX_VERDEX
-+#define GPIO_GUMSTIX_nBVD1_0 GPIO4_nBVD1_0
-+#define GPIO_GUMSTIX_nSTSCHG_0 GPIO4_nSTSCHG_0
-+#define GPIO_GUMSTIX_nCD_0 GPIO11_nCD_0
-+#define GPIO_GUMSTIX_PRDY_nBSY_0 GPIO26_PRDY_nBSY_0
-+#else
-+#define GPIO_GUMSTIX_nBVD1_0 GPIO111_nBVD1_0
-+#define GPIO_GUMSTIX_nSTSCHG_0 GPIO111_nSTSCHG_0
-+#define GPIO_GUMSTIX_nCD_0 GPIO104_nCD_0
-+#define GPIO_GUMSTIX_PRDY_nBSY_0 GPIO96_PRDY_nBSY_0
-+#endif
-+
-+#define GPIO_GUMSTIX_PRDY_nBSY_0_OLD GPIO109_PRDY_nBSY_0
-+#define GUMSTIX_S0_PRDY_nBSY_OLD_IRQ PXA_GPIO_TO_IRQ(GPIO109_PRDY_nBSY_0)
-+
-+#define GUMSTIX_S0_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_nSTSCHG_0)
-+#define GUMSTIX_S0_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_nCD_0)
-+#define GUMSTIX_S0_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_PRDY_nBSY_0)
-
- /* CF slot 1 */
--#define GPIO18_nBVD1 18
--#define GPIO18_nSTSCHG GPIO18_nBVD1
--#define GPIO36_nCD 36
--#define GPIO27_PRDY_nBSY 27
--#define GUMSTIX_S1_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG)
--#define GUMSTIX_S1_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO36_nCD)
--#define GUMSTIX_S1_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY)
--
--/* CF GPIO line modes */
--#define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN)
--#define GPIO8_RESET_MD (GPIO8_RESET | GPIO_OUT)
--#define GPIO11_nCD_MD (GPIO11_nCD | GPIO_IN)
--#define GPIO18_nSTSCHG_MD (GPIO18_nSTSCHG | GPIO_IN)
--#define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN)
--#define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN)
--#define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN)
-+#define GPIO18_nBVD1_1 18
-+#define GPIO18_nSTSCHG_1 GPIO18_nBVD1_1
-+#define GPIO36_nCD_1 36
-+#define GPIO27_PRDY_nBSY_1 27
-+
-+#define GPIO_GUMSTIX_nBVD1_1 GPIO18_nBVD1_1
-+#define GPIO_GUMSTIX_nSTSCHG_1 GPIO18_nSTSCHG_1
-+#define GPIO_GUMSTIX_nCD_1 GPIO36_nCD_1
-+#define GPIO_GUMSTIX_PRDY_nBSY_1 GPIO27_PRDY_nBSY_1
-+
-+#define GUMSTIX_S1_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG_1)
-+#define GUMSTIX_S1_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO36_nCD_1)
-+#define GUMSTIX_S1_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY_1)
-+
-+/* CF GPIO line modes - correspond to mfp-pxa2[57]x.h */
-+#define GPIO_GUMSTIX_CF_RESET_MD (GPIO_GUMSTIX_CF_RESET | GPIO_OUT)
-+#define GPIO_GUMSTIX_CF_OLD_RESET_MD (GPIO_GUMSTIX_CF_OLD_RESET | GPIO_OUT)
-+
-+#define GPIO_GUMSTIX_nSTSCHG_0_MD GPIO111_GPIO
-+#define GPIO_GUMSTIX_nCD_0_MD GPIO104_GPIO
-+
-+#define GPIO_GUMSTIX_PRDY_nBSY_0_MD GPIO96_GPIO
-+#define GPIO_GUMSTIX_PRDY_nBSY_0_OLD_MD GPIO109_GPIO
-+
-+#define GPIO_GUMSTIX_nSTSCHG_1_MD GPIO18_GPIO
-+#define GPIO_GUMSTIX_nCD_1_MD GPIO36_GPIO
-+#define GPIO_GUMSTIX_PRDY_nBSY_1_MD GPIO27_GPIO
-
- /* for expansion boards that can't be programatically detected */
- extern int am200_init(void);
+++ /dev/null
-From 7645a459feb02f7aae4c3a5724b7800495d1b659 Mon Sep 17 00:00:00 2001
-From: Bobby Powers <bobbypowers@gmail.com>
-Date: Wed, 28 Oct 2009 22:41:31 -0400
-Subject: [PATCH] [ARM] smsc911x: Verdex Pro support
-
-Basically Joseph Kortje's patch, cleaned up to apply to Linus's
-tree. Some of the smsc911x.c had been applied already
-
-Signed-off-by: Bobby Powers <bobbypowers@gmail.com>
----
- drivers/net/smsc911x.c | 50 +++++++++++++++++++++++++++++++++++++--------
- drivers/net/smsc911x.h | 2 +-
- include/linux/smsc911x.h | 11 ++++++++++
- 3 files changed, 53 insertions(+), 10 deletions(-)
-
---- a/drivers/net/ethernet/smsc/smsc911x.c
-+++ b/drivers/net/ethernet/smsc/smsc911x.c
-@@ -1485,7 +1485,7 @@ static int smsc911x_open(struct net_devi
- SMSC_WARN(pdata, ifup,
- "Timed out waiting for EEPROM busy bit to clear");
-
-- smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
-+ smsc911x_reg_write(pdata, GPIO_CFG, GPIO_CFG_LED1_EN_ | GPIO_CFG_LED2_EN_ | (1 << 20));
-
- /* The soft reset above cleared the device's MAC address,
- * restore it from local copy (set in probe) */
-@@ -1497,8 +1497,8 @@ static int smsc911x_open(struct net_devi
- smsc911x_reg_write(pdata, INT_EN, 0);
- smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
-
-- /* Set interrupt deassertion to 100uS */
-- intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
-+ /* Set interrupt deassertion to 22*10uS */
-+ intcfg = ((22 << 24) | INT_CFG_IRQ_EN_);
-
- if (pdata->config.irq_polarity) {
- SMSC_TRACE(pdata, ifup, "irq polarity: active high");
-@@ -1524,7 +1524,7 @@ static int smsc911x_open(struct net_devi
- temp |= INT_EN_SW_INT_EN_;
- smsc911x_reg_write(pdata, INT_EN, temp);
-
-- timeout = 1000;
-+ timeout = 2000;
- while (timeout--) {
- if (pdata->software_irq_signal)
- break;
-@@ -2332,6 +2332,38 @@ static inline int smsc911x_probe_config_
- }
- #endif /* CONFIG_OF */
-
-+static inline unsigned int is_gumstix_oui(u8 *addr)
-+{
-+ return (addr[0] == 0x00 && addr[1] == 0x15 && addr[2] == 0xC9);
-+}
-+
-+/**
-+ * gen_serial_ether_addr - Generate software assigned Ethernet address
-+ * based on the system_serial number
-+ * @addr: Pointer to a six-byte array containing the Ethernet address
-+ *
-+ * Generate an Ethernet address (MAC) that is not multicast
-+ * and has the local assigned bit set, keyed on the system_serial
-+ */
-+static inline void gen_serial_ether_addr(u8 *addr)
-+{
-+ static u8 ether_serial_digit = 0;
-+ addr [0] = system_serial_high >> 8;
-+ addr [1] = system_serial_high;
-+ addr [2] = system_serial_low >> 24;
-+ addr [3] = system_serial_low >> 16;
-+ addr [4] = system_serial_low >> 8;
-+ addr [5] = (system_serial_low & 0xc0) | /* top bits are from system serial */
-+ (1 << 4) | /* 2 bits identify interface type 1=ether, 2=usb, 3&4 undef */
-+ ((ether_serial_digit++) & 0x0f); /* 15 possible interfaces of each type */
-+
-+ if(!is_gumstix_oui(addr))
-+ {
-+ addr [0] &= 0xfe; /* clear multicast bit */
-+ addr [0] |= 0x02; /* set local assignment bit (IEEE802) */
-+ }
-+}
-+
- static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
- {
- struct device_node *np = pdev->dev.of_node;
-@@ -2481,11 +2513,11 @@ static int __devinit smsc911x_drv_probe(
- SMSC_TRACE(pdata, probe,
- "Mac Address is read from LAN911x EEPROM");
- } else {
-- /* eeprom values are invalid, generate random MAC */
-- random_ether_addr(dev->dev_addr);
-+ /* eeprom values are invalid, generate MAC from serial number */
-+ gen_serial_ether_addr(dev->dev_addr);
- smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
- SMSC_TRACE(pdata, probe,
-- "MAC Address is set to random_ether_addr");
-+ "MAC Address is derived from system serial number");
- }
- }
-
+++ /dev/null
-From 76a102bd5c9d792db19c6c72eafdecea0311a0c9 Mon Sep 17 00:00:00 2001
-From: Craig Hughes <craig@gumstix.com>
-Date: Fri, 30 Oct 2009 14:16:27 -0400
-Subject: [PATCH] [ARM] pxa: Gumstix Verdex PCMCIA support
-
-Needed for the Libertas CS wireless device.
-
-Signed-off-by: Bobby Powers <bobbypowers@gmail.com>
----
- drivers/pcmcia/Kconfig | 3 +-
- drivers/pcmcia/Makefile | 3 +
- drivers/pcmcia/pxa2xx_gumstix.c | 194 +++++++++++++++++++++++++++++++++++++++
- 3 files changed, 199 insertions(+), 1 deletions(-)
- create mode 100644 drivers/pcmcia/pxa2xx_gumstix.c
-
---- a/drivers/pcmcia/Kconfig
-+++ b/drivers/pcmcia/Kconfig
-@@ -212,7 +212,7 @@ config PCMCIA_PXA2XX
- || MACH_ARMCORE || ARCH_PXA_PALM || TRIZEPS_PCMCIA \
- || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2 \
- || MACH_VPAC270 || MACH_BALLOON3 || MACH_COLIBRI \
-- || MACH_COLIBRI320)
-+ || MACH_COLIBRI320 || ARCH_GUMSTIX)
- select PCMCIA_SOC_COMMON
- help
- Say Y here to include support for the PXA2xx PCMCIA controller
---- a/drivers/pcmcia/Makefile
-+++ b/drivers/pcmcia/Makefile
-@@ -70,6 +70,9 @@ pxa2xx-obj-$(CONFIG_MACH_BALLOON3) += p
- pxa2xx-obj-$(CONFIG_MACH_COLIBRI) += pxa2xx_colibri.o
- pxa2xx-obj-$(CONFIG_MACH_COLIBRI320) += pxa2xx_colibri.o
-
-+pxa2xx-obj-$(CONFIG_MACH_GUMSTIX_VERDEX) += pxa2xx_cs.o
-+pxa2xx_cs-objs := pxa2xx_gumstix.o
-+
- obj-$(CONFIG_PCMCIA_PXA2XX) += pxa2xx_base.o $(pxa2xx-obj-y)
-
- obj-$(CONFIG_PCMCIA_XXS1500) += xxs1500_ss.o
---- /dev/null
-+++ b/drivers/pcmcia/pxa2xx_gumstix.c
-@@ -0,0 +1,195 @@
-+/*
-+ * linux/drivers/pcmcia/pxa2xx_gumstix.c
-+ *
-+ * Gumstix PCMCIA specific routines. Based on Mainstone
-+ *
-+ * Copyright 2004, Craig Hughes <craig@gumstix.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/gpio.h>
-+
-+#include <linux/delay.h>
-+#include <linux/platform_device.h>
-+
-+#include <linux/gpio-pxa.h>
-+
-+#include <pcmcia/ss.h>
-+
-+#include <mach/hardware.h>
-+#include <asm/mach-types.h>
-+
-+#include <mach/pxa27x.h>
-+
-+#include <asm/io.h>
-+#include <mach/gpio.h>
-+#include <mach/gumstix.h>
-+#include "soc_common.h"
-+
-+#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
-+
-+#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
-+#define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
-+
-+static struct pcmcia_irqs gumstix_pcmcia_irqs0[] = {
-+ { 0, GUMSTIX_S0_nCD_IRQ, "CF0 nCD" },
-+ { 0, GUMSTIX_S0_nSTSCHG_IRQ, "CF0 nSTSCHG" },
-+};
-+
-+static struct pcmcia_irqs gumstix_pcmcia_irqs1[] = {
-+ { 1, GUMSTIX_S1_nCD_IRQ, "CF1 nCD" },
-+ { 1, GUMSTIX_S1_nSTSCHG_IRQ, "CF1 nSTSCHG" },
-+};
-+
-+
-+static int net_cf_vx_mode = 0;
-+
-+static int gumstix_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
-+{
-+/* Note: The verdex_pcmcia_pin_config is moved to gumstix_verdex.c in order to use mfp_pxa2xx_config
-+ for board-specific pin configuration instead of the old deprecated pxa_gpio_mode function. Thus,
-+ only the IRQ init is still needed to be done here. */
-+ skt->socket.pci_irq = (skt->nr == 0) ? ((net_cf_vx_mode == 0) ? GUMSTIX_S0_PRDY_nBSY_IRQ : GUMSTIX_S0_PRDY_nBSY_OLD_IRQ) : GUMSTIX_S1_PRDY_nBSY_IRQ;
-+
-+ return (skt->nr == 0) ? soc_pcmcia_request_irqs(skt, gumstix_pcmcia_irqs0, ARRAY_SIZE(gumstix_pcmcia_irqs0)) :
-+ soc_pcmcia_request_irqs(skt, gumstix_pcmcia_irqs1, ARRAY_SIZE(gumstix_pcmcia_irqs1));
-+}
-+
-+static void gumstix_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
-+{
-+ if(skt->nr == 0)
-+ {
-+ soc_pcmcia_free_irqs(skt, gumstix_pcmcia_irqs0, ARRAY_SIZE(gumstix_pcmcia_irqs0));
-+ } else {
-+ soc_pcmcia_free_irqs(skt, gumstix_pcmcia_irqs1, ARRAY_SIZE(gumstix_pcmcia_irqs1));
-+ }
-+
-+ if (net_cf_vx_mode) {
-+ gpio_free(GPIO_GUMSTIX_CF_OLD_RESET);
-+ } else {
-+ gpio_free(GPIO_GUMSTIX_CF_RESET);
-+ }
-+
-+}
-+
-+static void gumstix_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
-+ struct pcmcia_state *state)
-+{
-+ unsigned int cd, prdy_nbsy, nbvd1;
-+ if(skt->nr == 0)
-+ {
-+ cd = GPIO_GUMSTIX_nCD_0;
-+ if(net_cf_vx_mode)
-+ prdy_nbsy = GPIO_GUMSTIX_PRDY_nBSY_0_OLD;
-+ else
-+ prdy_nbsy = GPIO_GUMSTIX_PRDY_nBSY_0;
-+ nbvd1 = GPIO_GUMSTIX_nBVD1_0;
-+ } else {
-+ cd = GPIO_GUMSTIX_nCD_1;
-+ prdy_nbsy = GPIO_GUMSTIX_PRDY_nBSY_1;
-+ nbvd1 = GPIO_GUMSTIX_nBVD1_1;
-+ }
-+ state->detect = !!gpio_get_value(cd);
-+ state->ready = !!gpio_get_value(prdy_nbsy);
-+ state->bvd1 = !!gpio_get_value(nbvd1);
-+ state->bvd2 = 1;
-+ state->vs_3v = 0;
-+ state->vs_Xv = 0;
-+ state->wrprot = 0;
-+}
-+
-+static int gumstix_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
-+ const socket_state_t *state)
-+{
-+ return 0;
-+}
-+
-+static void gumstix_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
-+{
-+ if(skt->nr) {
-+ soc_pcmcia_enable_irqs(skt, gumstix_pcmcia_irqs0, ARRAY_SIZE(gumstix_pcmcia_irqs0));
-+ } else {
-+ soc_pcmcia_enable_irqs(skt, gumstix_pcmcia_irqs1, ARRAY_SIZE(gumstix_pcmcia_irqs1));
-+ }
-+}
-+
-+static void gumstix_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
-+{
-+ if(skt->nr) {
-+ soc_pcmcia_disable_irqs(skt, gumstix_pcmcia_irqs0, ARRAY_SIZE(gumstix_pcmcia_irqs0));
-+ } else {
-+ soc_pcmcia_disable_irqs(skt, gumstix_pcmcia_irqs1, ARRAY_SIZE(gumstix_pcmcia_irqs1));
-+ }
-+}
-+
-+static struct pcmcia_low_level gumstix_pcmcia_ops = {
-+ .owner = THIS_MODULE,
-+ .hw_init = gumstix_pcmcia_hw_init,
-+ .hw_shutdown = gumstix_pcmcia_hw_shutdown,
-+ .socket_state = gumstix_pcmcia_socket_state,
-+ .configure_socket = gumstix_pcmcia_configure_socket,
-+ .socket_init = gumstix_pcmcia_socket_init,
-+ .socket_suspend = gumstix_pcmcia_socket_suspend,
-+ .nr = 2,
-+};
-+
-+static struct platform_device *gumstix_pcmcia_device;
-+
-+extern int __init gumstix_get_cf_cards(void);
-+
-+#ifdef CONFIG_MACH_GUMSTIX_VERDEX
-+extern int __init gumstix_check_if_netCF_vx(void);
-+#endif
-+
-+static int __init gumstix_pcmcia_init(void)
-+{
-+ int ret;
-+
-+#ifdef CONFIG_MACH_GUMSTIX_VERDEX
-+ net_cf_vx_mode = gumstix_check_if_netCF_vx();
-+#endif
-+
-+ gumstix_pcmcia_ops.nr = gumstix_get_cf_cards();
-+
-+ gumstix_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
-+ if (!gumstix_pcmcia_device)
-+ return -ENOMEM;
-+
-+ ret = platform_device_add_data(gumstix_pcmcia_device, &gumstix_pcmcia_ops,
-+ sizeof(gumstix_pcmcia_ops));
-+
-+ if (ret == 0) {
-+ printk(KERN_INFO "Registering gumstix PCMCIA interface.\n");
-+ ret = platform_device_add(gumstix_pcmcia_device);
-+ }
-+
-+ if (ret)
-+ platform_device_put(gumstix_pcmcia_device);
-+
-+ return ret;
-+}
-+
-+static void __exit gumstix_pcmcia_exit(void)
-+{
-+ /*
-+ * This call is supposed to free our gumstix_pcmcia_device.
-+ * Unfortunately platform_device don't have a free method, and
-+ * we can't assume it's free of any reference at this point so we
-+ * can't free it either.
-+ */
-+ platform_device_unregister(gumstix_pcmcia_device);
-+}
-+
-+fs_initcall(gumstix_pcmcia_init);
-+module_exit(gumstix_pcmcia_exit);
-+
-+MODULE_LICENSE("GPL");
+++ /dev/null
---- a/kernel/printk.c
-+++ b/kernel/printk.c
-@@ -44,6 +44,10 @@
-
- #include <asm/uaccess.h>
-
-+#ifdef CONFIG_DEBUG_LL
-+extern void printascii(char *);
-+#endif /* CONFIG_DEBUG_LL */
-+
- /*
- * Architectures can override it:
- */
-@@ -900,6 +904,10 @@ asmlinkage int vprintk(const char *fmt,
- }
- }
-
-+#ifdef CONFIG_DEBUG_LL
-+ printascii(printk_buf);
-+#endif
-+
- /*
- * Copy the output into log_buf. If the caller didn't provide
- * the appropriate log prefix, we insert them here
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Default
- NAME:=Default Profile
- PACKAGES:=
-endef
-
-define Profile/Default/Description
- Default PXA Profile
-endef
-$(eval $(call Profile,Default))
-
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Gumstix
- NAME:=Gumstix
- PACKAGES:=uboot-pxa-gumstix
-endef
-
-define Profile/Atheros-ath5k/Description
- Package set compatible with the Gumstix boards
-endef
-$(eval $(call Profile,Gumstix))
-
+++ /dev/null
-#
-# Copyright (C) 2006-2011 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=mips
-BOARD:=sibyte
-BOARDNAME:=Broadcom/SiByte SB-1
-FEATURES:=fpu ramdisk broken
-CPU_TYPE:=sb1
-CPU_CFLAGS_sb1:=-march=sb1
-MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
-
-LINUX_VERSION:=3.3.8
-
-include $(INCLUDE_DIR)/target.mk
-
-define Target/Description
- Build firmware images for Broadcom/SiByte SB-1 boards
-endef
-
-$(eval $(call BuildTarget))
+++ /dev/null
-# Copyright (C) 2006-2009 OpenWrt.org
-
-::sysinit:/etc/init.d/rcS
-duart0::askfirst:/bin/ash --login
+++ /dev/null
-# CONFIG_32BIT is not set
-CONFIG_64BIT=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARPD is not set
-CONFIG_BINFMT_ELF32=y
-CONFIG_BLOCK_COMPAT=y
-CONFIG_BOOT_ELF32=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_CEVT_SB1250=y
-CONFIG_CFE=y
-CONFIG_COMPAT=y
-CONFIG_COMPAT_NETLINK_MESSAGES=y
-CONFIG_CONNECTOR=m
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-CONFIG_CPU_SB1=y
-# CONFIG_CPU_SB1_PASS_2_112x is not set
-CONFIG_CPU_SB1_PASS_3=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_SB1250=y
-# CONFIG_CYCLADES is not set
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DMA_COHERENT=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_WRAPPERS=y
-CONFIG_HWMON=y
-CONFIG_HWMON_DEBUG_CHIP=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=m
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_SIBYTE=y
-CONFIG_INITRAMFS_ROOT_GID=0
-CONFIG_INITRAMFS_ROOT_UID=0
-CONFIG_INITRAMFS_SOURCE="../../root"
-CONFIG_INPUT=m
-# CONFIG_IP_ROUTE_VERBOSE is not set
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_FORCED_THREADING=y
-# CONFIG_ISI is not set
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-CONFIG_MIPS32_COMPAT=y
-# CONFIG_MIPS32_N32 is not set
-CONFIG_MIPS32_O32=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MOXA_INTELLIO is not set
-# CONFIG_MOXA_SMARTIO is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-# CONFIG_N_HDLC is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_ROCKETPORT is not set
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_CMOS is not set
-CONFIG_RTC_DRV_M41T80=y
-# CONFIG_RTC_DRV_M41T80_WDT is not set
-CONFIG_SB1250_MAC=y
-# CONFIG_SB1XXX_CORELIS is not set
-# CONFIG_SB1_CERR_STALL is not set
-# CONFIG_SB1_CEX_ALWAYS_FATAL is not set
-# CONFIG_SCSI_DMA is not set
-CONFIG_SENSORS_LM90=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_SERIAL_SB1250_DUART=y
-CONFIG_SERIAL_SB1250_DUART_CONSOLE=y
-CONFIG_SIBYTE_BCM1125H=y
-CONFIG_SIBYTE_BCM112X=y
-# CONFIG_SIBYTE_BUS_WATCHER is not set
-# CONFIG_SIBYTE_CFE_CONSOLE is not set
-# CONFIG_SIBYTE_DMA_PAGEOPS is not set
-CONFIG_SIBYTE_ENABLE_LDT_IF_PCI=y
-CONFIG_SIBYTE_HAS_LDT=y
-CONFIG_SIBYTE_HAS_ZBUS_PROFILING=y
-CONFIG_SIBYTE_RHONE=y
-CONFIG_SIBYTE_SB1xxx_SOC=y
-# CONFIG_SIBYTE_TBPROF is not set
-# CONFIG_STALDRV is not set
-CONFIG_SWAP_IO_SPACE=y
-# CONFIG_SYNCLINKMP is not set
-# CONFIG_SYNCLINK_GT is not set
-CONFIG_SYSVIPC_COMPAT=y
-CONFIG_SYS_HAS_CPU_SB1=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-# CONFIG_WATCHDOG is not set
-CONFIG_WEAK_ORDERING=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2007-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/BuildKernel
- cp $(LINUX_DIR)/vmlinux $(BIN_DIR)/$(IMG_PREFIX)-vmlinux
-# uImage
- dd if=$(KDIR)/vmlinux of=$(KDIR)/$(IMG_PREFIX)-vmlinux bs=64k conv=sync
- mkimage -A mips -O linux -T kernel -a 0x80100000 -C none -e \
- 0x80100000 \
- -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \
- -d $(KDIR)/$(IMG_PREFIX)-vmlinux $(BIN_DIR)/$(IMG_PREFIX)-uImage
-endef
-
-define Image/Build
- $(call Image/Build/$(1),$(1))
-endef
-
-define Image/Build/jffs2-64k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=65536 conv=sync
-endef
-
-define Image/Build/jffs2-128k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=131072 conv=sync
- $(call Image/Build/slug,$(1))
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=131072 conv=sync
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
---- a/arch/mips/sibyte/swarm/platform.c
-+++ b/arch/mips/sibyte/swarm/platform.c
-@@ -5,6 +5,7 @@
- #include <linux/platform_device.h>
- #include <linux/ata_platform.h>
-
-+#include <asm/addrspace.h>
- #include <asm/sibyte/board.h>
- #include <asm/sibyte/sb1250_genbus.h>
- #include <asm/sibyte/sb1250_regs.h>
-@@ -137,3 +138,71 @@ static int __init sb1250_device_init(voi
- return ret;
- }
- device_initcall(sb1250_device_init);
-+
-+#ifdef CONFIG_SIBYTE_RHONE
-+
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/physmap.h>
-+
-+/* The board has 16MB flash but CFE sets up only 2MB */
-+#define PHYS_TO_K1(a) CKSEG1ADDR(a)
-+#define BOOTROM_SIZE 0x100
-+
-+static void fixup_cs0_size(void)
-+{
-+ SBWRITECSR(((A_IO_EXT_CS_BASE(0)) + R_IO_EXT_MULT_SIZE), BOOTROM_SIZE);
-+}
-+
-+static struct mtd_partition flash_parts[] = {
-+ {
-+ .name = "cfe",
-+ .offset = 0x00000000,
-+ .size = 0x00200000,
-+ .mask_flags = MTD_WRITEABLE,
-+ },
-+ {
-+ .name = "os",
-+ .offset = 0x00200000,
-+ .size = 0x00d00000,
-+ },
-+ {
-+ .name = "environment",
-+ .offset = 0x00f00000,
-+ .size = 0x00100000,
-+ .mask_flags = MTD_WRITEABLE,
-+ },
-+};
-+
-+static struct physmap_flash_data flash_data = {
-+ .width = 1,
-+ .nr_parts = ARRAY_SIZE(flash_parts),
-+ .parts = flash_parts,
-+};
-+
-+static struct resource flash_resource = {
-+ .start = 0x1fc00000,
-+ .end = 0x20bfffff,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device flash_device = {
-+ .name = "physmap-flash",
-+ .id = 0,
-+ .resource = &flash_resource,
-+ .num_resources = 1,
-+ .dev = {
-+ .platform_data = &flash_data,
-+ },
-+};
-+
-+static int __init flash_setup(void)
-+{
-+ fixup_cs0_size();
-+ platform_device_register(&flash_device);
-+
-+ return 0;
-+};
-+
-+device_initcall(flash_setup);
-+
-+#endif /* CONFIG_SIBYTE_RHONE */
+++ /dev/null
---- a/drivers/rtc/rtc-m41t80.c
-+++ b/drivers/rtc/rtc-m41t80.c
-@@ -6,6 +6,7 @@
- * Based on m41t00.c by Mark A. Greer <mgreer@mvista.com>
- *
- * 2006 (c) mycable GmbH
-+ * Copyright (c) 2008 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
-@@ -38,6 +39,8 @@
- #define M41T80_REG_DAY 5
- #define M41T80_REG_MON 6
- #define M41T80_REG_YEAR 7
-+#define M41T80_REG_CONTROL 8
-+#define M41T80_REG_WATCHDOG 9
- #define M41T80_REG_ALARM_MON 0xa
- #define M41T80_REG_ALARM_DAY 0xb
- #define M41T80_REG_ALARM_HOUR 0xc
-@@ -66,7 +69,7 @@
- #define M41T80_FEATURE_WD (1 << 3) /* Extra watchdog resolution */
- #define M41T80_FEATURE_SQ_ALT (1 << 4) /* RSx bits are in reg 4 */
-
--#define DRV_VERSION "0.05"
-+#define DRV_VERSION "0.06"
-
- static DEFINE_MUTEX(m41t80_rtc_mutex);
- static const struct i2c_device_id m41t80_id[] = {
-@@ -89,31 +92,88 @@ struct m41t80_data {
- struct rtc_device *rtc;
- };
-
--static int m41t80_get_datetime(struct i2c_client *client,
-- struct rtc_time *tm)
-+
-+static int m41t80_write_block_data(struct i2c_client *client,
-+ u8 reg, u8 num, u8 *buf)
- {
-- u8 buf[M41T80_DATETIME_REG_SIZE], dt_addr[1] = { M41T80_REG_SEC };
-- struct i2c_msg msgs[] = {
-- {
-- .addr = client->addr,
-- .flags = 0,
-- .len = 1,
-- .buf = dt_addr,
-- },
-- {
-- .addr = client->addr,
-- .flags = I2C_M_RD,
-- .len = M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC,
-- .buf = buf + M41T80_REG_SEC,
-- },
-- };
-+ int i, rc;
-
-- if (i2c_transfer(client->adapter, msgs, 2) < 0) {
-- dev_err(&client->dev, "read error\n");
-- return -EIO;
-+ if (i2c_check_functionality(client->adapter,
-+ I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) {
-+ i = i2c_smbus_write_i2c_block_data(client, reg, num, buf);
-+ } else {
-+ for (i = 0; i < num; i++) {
-+ rc = i2c_smbus_write_byte_data(client, reg + i,
-+ buf[i]);
-+ if (rc < 0) {
-+ i = rc;
-+ goto out;
-+ }
-+ }
- }
-+out:
-+ return i;
-+}
-+
-+static int m41t80_read_block_data(struct i2c_client *client,
-+ u8 reg, u8 num, u8 *buf)
-+{
-+ int i, rc;
-+
-+ if (i2c_check_functionality(client->adapter,
-+ I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
-+ i = i2c_smbus_read_i2c_block_data(client, reg, num, buf);
-+ } else {
-+ for (i = 0; i < num; i++) {
-+ rc = i2c_smbus_read_byte_data(client, reg + i);
-+ if (rc < 0) {
-+ i = rc;
-+ goto out;
-+ }
-+ buf[i] = rc;
-+ }
-+ }
-+out:
-+ return i;
-+}
-+
-+static int m41t80_get_datetime(struct i2c_client *client, struct rtc_time *tm)
-+{
-+ u8 buf[M41T80_DATETIME_REG_SIZE];
-+ int loops = 2;
-+ int sec0, sec1;
-+
-+ /*
-+ * Time registers are latched by this chip if an I2C block
-+ * transfer is used, but with SMBus-style byte accesses
-+ * this is not the case, so check seconds for a wraparound.
-+ */
-+ do {
-+ if (m41t80_read_block_data(client, M41T80_REG_SEC,
-+ M41T80_DATETIME_REG_SIZE -
-+ M41T80_REG_SEC,
-+ buf + M41T80_REG_SEC) < 0) {
-+ dev_err(&client->dev, "read error\n");
-+ return -EIO;
-+ }
-+ if (i2c_check_functionality(client->adapter,
-+ I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
-+ sec1 = buf[M41T80_REG_SEC];
-+ break;
-+ }
-+
-+ sec0 = buf[M41T80_REG_SEC];
-+ sec1 = i2c_smbus_read_byte_data(client, M41T80_REG_SEC);
-+ if (sec1 < 0) {
-+ dev_err(&client->dev, "read error\n");
-+ return -EIO;
-+ }
-+
-+ sec0 = bcd2bin(sec0 & 0x7f);
-+ sec1 = bcd2bin(sec1 & 0x7f);
-+ } while (sec1 < sec0 && --loops);
-
-- tm->tm_sec = bcd2bin(buf[M41T80_REG_SEC] & 0x7f);
-+ tm->tm_sec = sec1;
- tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f);
- tm->tm_hour = bcd2bin(buf[M41T80_REG_HOUR] & 0x3f);
- tm->tm_mday = bcd2bin(buf[M41T80_REG_DAY] & 0x3f);
-@@ -128,39 +188,16 @@ static int m41t80_get_datetime(struct i2
- /* Sets the given date and time to the real time clock. */
- static int m41t80_set_datetime(struct i2c_client *client, struct rtc_time *tm)
- {
-- u8 wbuf[1 + M41T80_DATETIME_REG_SIZE];
-- u8 *buf = &wbuf[1];
-- u8 dt_addr[1] = { M41T80_REG_SEC };
-- struct i2c_msg msgs_in[] = {
-- {
-- .addr = client->addr,
-- .flags = 0,
-- .len = 1,
-- .buf = dt_addr,
-- },
-- {
-- .addr = client->addr,
-- .flags = I2C_M_RD,
-- .len = M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC,
-- .buf = buf + M41T80_REG_SEC,
-- },
-- };
-- struct i2c_msg msgs[] = {
-- {
-- .addr = client->addr,
-- .flags = 0,
-- .len = 1 + M41T80_DATETIME_REG_SIZE,
-- .buf = wbuf,
-- },
-- };
-+ u8 buf[M41T80_DATETIME_REG_SIZE];
-
- /* Read current reg values into buf[1..7] */
-- if (i2c_transfer(client->adapter, msgs_in, 2) < 0) {
-+ if (m41t80_read_block_data(client, M41T80_REG_SEC,
-+ M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC,
-+ buf + M41T80_REG_SEC) < 0) {
- dev_err(&client->dev, "read error\n");
- return -EIO;
- }
-
-- wbuf[0] = 0; /* offset into rtc's regs */
- /* Merge time-data and register flags into buf[0..7] */
- buf[M41T80_REG_SSEC] = 0;
- buf[M41T80_REG_SEC] =
-@@ -178,7 +215,8 @@ static int m41t80_set_datetime(struct i2
- /* assume 20YY not 19YY */
- buf[M41T80_REG_YEAR] = bin2bcd(tm->tm_year % 100);
-
-- if (i2c_transfer(client->adapter, msgs, 1) != 1) {
-+ if (m41t80_write_block_data(client, M41T80_REG_SSEC,
-+ M41T80_DATETIME_REG_SIZE, buf) < 0) {
- dev_err(&client->dev, "write error\n");
- return -EIO;
- }
-@@ -238,34 +276,11 @@ err:
- static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t)
- {
- struct i2c_client *client = to_i2c_client(dev);
-- u8 wbuf[1 + M41T80_ALARM_REG_SIZE];
-- u8 *buf = &wbuf[1];
-+ u8 buf[M41T80_ALARM_REG_SIZE];
- u8 *reg = buf - M41T80_REG_ALARM_MON;
-- u8 dt_addr[1] = { M41T80_REG_ALARM_MON };
-- struct i2c_msg msgs_in[] = {
-- {
-- .addr = client->addr,
-- .flags = 0,
-- .len = 1,
-- .buf = dt_addr,
-- },
-- {
-- .addr = client->addr,
-- .flags = I2C_M_RD,
-- .len = M41T80_ALARM_REG_SIZE,
-- .buf = buf,
-- },
-- };
-- struct i2c_msg msgs[] = {
-- {
-- .addr = client->addr,
-- .flags = 0,
-- .len = 1 + M41T80_ALARM_REG_SIZE,
-- .buf = wbuf,
-- },
-- };
-
-- if (i2c_transfer(client->adapter, msgs_in, 2) < 0) {
-+ if (m41t80_read_block_data(client, M41T80_REG_ALARM_MON,
-+ M41T80_ALARM_REG_SIZE, buf) < 0) {
- dev_err(&client->dev, "read error\n");
- return -EIO;
- }
-@@ -275,7 +290,6 @@ static int m41t80_rtc_set_alarm(struct d
- reg[M41T80_REG_ALARM_MIN] = 0;
- reg[M41T80_REG_ALARM_SEC] = 0;
-
-- wbuf[0] = M41T80_REG_ALARM_MON; /* offset into rtc's regs */
- reg[M41T80_REG_ALARM_SEC] |= t->time.tm_sec >= 0 ?
- bin2bcd(t->time.tm_sec) : 0x80;
- reg[M41T80_REG_ALARM_MIN] |= t->time.tm_min >= 0 ?
-@@ -289,7 +303,8 @@ static int m41t80_rtc_set_alarm(struct d
- else
- reg[M41T80_REG_ALARM_DAY] |= 0x40;
-
-- if (i2c_transfer(client->adapter, msgs, 1) != 1) {
-+ if (m41t80_write_block_data(client, M41T80_REG_ALARM_MON,
-+ M41T80_ALARM_REG_SIZE, buf) < 0) {
- dev_err(&client->dev, "write error\n");
- return -EIO;
- }
-@@ -309,24 +324,10 @@ static int m41t80_rtc_read_alarm(struct
- {
- struct i2c_client *client = to_i2c_client(dev);
- u8 buf[M41T80_ALARM_REG_SIZE + 1]; /* all alarm regs and flags */
-- u8 dt_addr[1] = { M41T80_REG_ALARM_MON };
- u8 *reg = buf - M41T80_REG_ALARM_MON;
-- struct i2c_msg msgs[] = {
-- {
-- .addr = client->addr,
-- .flags = 0,
-- .len = 1,
-- .buf = dt_addr,
-- },
-- {
-- .addr = client->addr,
-- .flags = I2C_M_RD,
-- .len = M41T80_ALARM_REG_SIZE + 1,
-- .buf = buf,
-- },
-- };
-
-- if (i2c_transfer(client->adapter, msgs, 2) < 0) {
-+ if (m41t80_read_block_data(client, M41T80_REG_ALARM_MON,
-+ M41T80_ALARM_REG_SIZE + 1, buf) < 0) {
- dev_err(&client->dev, "read error\n");
- return -EIO;
- }
-@@ -508,26 +509,16 @@ static int boot_flag;
- */
- static void wdt_ping(void)
- {
-- unsigned char i2c_data[2];
-- struct i2c_msg msgs1[1] = {
-- {
-- .addr = save_client->addr,
-- .flags = 0,
-- .len = 2,
-- .buf = i2c_data,
-- },
-- };
-- struct m41t80_data *clientdata = i2c_get_clientdata(save_client);
-+ u8 wdt = 0x80; /* WDS = 1 (0x80) */
-
-- i2c_data[0] = 0x09; /* watchdog register */
-+ struct m41t80_data *clientdata = i2c_get_clientdata(save_client);
-
- if (wdt_margin > 31)
-- i2c_data[1] = (wdt_margin & 0xFC) | 0x83; /* resolution = 4s */
-+ /* mulitplier = WD_TIMO / 4, resolution = 4s (0x3) */
-+ wdt |= (wdt_margin & 0xfc) | 0x3;
- else
-- /*
-- * WDS = 1 (0x80), mulitplier = WD_TIMO, resolution = 1s (0x02)
-- */
-- i2c_data[1] = wdt_margin<<2 | 0x82;
-+ /* mulitplier = WD_TIMO, resolution = 1s (0x2) */
-+ wdt |= wdt_margin << 2 | 0x2;
-
- /*
- * M41T65 has three bits for watchdog resolution. Don't set bit 7, as
-@@ -536,7 +527,7 @@ static void wdt_ping(void)
- if (clientdata->features & M41T80_FEATURE_WD)
- i2c_data[1] &= ~M41T80_WATCHDOG_RB2;
-
-- i2c_transfer(save_client->adapter, msgs1, 1);
-+ i2c_smbus_write_byte_data(save_client, M41T80_REG_WATCHDOG, wdt);
- }
-
- /**
-@@ -546,36 +537,8 @@ static void wdt_ping(void)
- */
- static void wdt_disable(void)
- {
-- unsigned char i2c_data[2], i2c_buf[0x10];
-- struct i2c_msg msgs0[2] = {
-- {
-- .addr = save_client->addr,
-- .flags = 0,
-- .len = 1,
-- .buf = i2c_data,
-- },
-- {
-- .addr = save_client->addr,
-- .flags = I2C_M_RD,
-- .len = 1,
-- .buf = i2c_buf,
-- },
-- };
-- struct i2c_msg msgs1[1] = {
-- {
-- .addr = save_client->addr,
-- .flags = 0,
-- .len = 2,
-- .buf = i2c_data,
-- },
-- };
--
-- i2c_data[0] = 0x09;
-- i2c_transfer(save_client->adapter, msgs0, 2);
--
-- i2c_data[0] = 0x09;
-- i2c_data[1] = 0x00;
-- i2c_transfer(save_client->adapter, msgs1, 1);
-+ i2c_smbus_read_byte_data(save_client, M41T80_REG_WATCHDOG);
-+ i2c_smbus_write_byte_data(save_client, M41T80_REG_WATCHDOG, 0);
- }
-
- /**
-@@ -777,8 +740,8 @@ static int m41t80_probe(struct i2c_clien
- struct rtc_time tm;
- struct m41t80_data *clientdata = NULL;
-
-- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C
-- | I2C_FUNC_SMBUS_BYTE_DATA)) {
-+ if (!i2c_check_functionality(client->adapter,
-+ I2C_FUNC_SMBUS_BYTE_DATA)) {
- rc = -ENODEV;
- goto exit;
- }
+++ /dev/null
---- a/arch/mips/sibyte/swarm/setup.c
-+++ b/arch/mips/sibyte/swarm/setup.c
-@@ -56,14 +56,6 @@ extern void sb1250_setup(void);
- #error invalid SiByte board configuration
- #endif
-
--extern int xicor_probe(void);
--extern int xicor_set_time(unsigned long);
--extern unsigned long xicor_get_time(void);
--
--extern int m41t81_probe(void);
--extern int m41t81_set_time(unsigned long);
--extern unsigned long m41t81_get_time(void);
--
- const char *get_system_type(void)
- {
- return "SiByte " SIBYTE_BOARD_NAME;
-@@ -79,49 +71,18 @@ int swarm_be_handler(struct pt_regs *reg
- return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
- }
-
--enum swarm_rtc_type {
-- RTC_NONE,
-- RTC_XICOR,
-- RTC_M41T81,
--};
--
--enum swarm_rtc_type swarm_rtc_type;
--
- void read_persistent_clock(struct timespec *ts)
- {
- unsigned long sec;
-
-- switch (swarm_rtc_type) {
-- case RTC_XICOR:
-- sec = xicor_get_time();
-- break;
--
-- case RTC_M41T81:
-- sec = m41t81_get_time();
-- break;
--
-- case RTC_NONE:
-- default:
-- sec = mktime(2000, 1, 1, 0, 0, 0);
-- break;
-- }
-+ sec = mktime(2000, 1, 1, 0, 0, 0);
- ts->tv_sec = sec;
- ts->tv_nsec = 0;
- }
-
- int rtc_mips_set_time(unsigned long sec)
- {
-- switch (swarm_rtc_type) {
-- case RTC_XICOR:
-- return xicor_set_time(sec);
--
-- case RTC_M41T81:
-- return m41t81_set_time(sec);
--
-- case RTC_NONE:
-- default:
- return -1;
-- }
- }
-
- void __init plat_mem_setup(void)
-@@ -138,11 +99,6 @@ void __init plat_mem_setup(void)
-
- board_be_handler = swarm_be_handler;
-
-- if (xicor_probe())
-- swarm_rtc_type = RTC_XICOR;
-- if (m41t81_probe())
-- swarm_rtc_type = RTC_M41T81;
--
- #ifdef CONFIG_VT
- screen_info = (struct screen_info) {
- .orig_video_page = 52,
+++ /dev/null
---- a/arch/mips/sibyte/swarm/swarm-i2c.c
-+++ b/arch/mips/sibyte/swarm/swarm-i2c.c
-@@ -13,6 +13,11 @@
- #include <linux/init.h>
- #include <linux/kernel.h>
-
-+static struct i2c_board_info swarm_i2c_info0[] __initdata = {
-+ {
-+ I2C_BOARD_INFO("lm90", 0x2a),
-+ },
-+};
-
- static struct i2c_board_info swarm_i2c_info1[] __initdata = {
- {
-@@ -24,6 +29,8 @@ static int __init swarm_i2c_init(void)
- {
- int err;
-
-+ err = i2c_register_board_info(0, swarm_i2c_info0,
-+ ARRAY_SIZE(swarm_i2c_info0));
- err = i2c_register_board_info(1, swarm_i2c_info1,
- ARRAY_SIZE(swarm_i2c_info1));
- if (err < 0)
+++ /dev/null
---- a/arch/mips/Makefile
-+++ b/arch/mips/Makefile
-@@ -90,8 +90,8 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin
- cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
- cflags-y += -msoft-float
- LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
--KBUILD_AFLAGS_MODULE += -mno-long-calls
--KBUILD_CFLAGS_MODULE += -mno-long-calls
-+KBUILD_AFLAGS_MODULE += -mlong-calls
-+KBUILD_CFLAGS_MODULE += -mlong-calls
-
- cflags-y += -ffreestanding
-
---- a/arch/mips/include/asm/module.h
-+++ b/arch/mips/include/asm/module.h
-@@ -9,11 +9,6 @@ struct mod_arch_specific {
- struct list_head dbe_list;
- const struct exception_table_entry *dbe_start;
- const struct exception_table_entry *dbe_end;
--
-- void *phys_plt_tbl;
-- void *virt_plt_tbl;
-- unsigned int phys_plt_offset;
-- unsigned int virt_plt_offset;
- };
-
- typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */
---- a/arch/mips/kernel/module.c
-+++ b/arch/mips/kernel/module.c
-@@ -44,117 +44,6 @@ static struct mips_hi16 *mips_hi16_list;
- static LIST_HEAD(dbe_list);
- static DEFINE_SPINLOCK(dbe_lock);
-
--/*
-- * Get the potential max trampolines size required of the init and
-- * non-init sections. Only used if we cannot find enough contiguous
-- * physically mapped memory to put the module into.
-- */
--static unsigned int
--get_plt_size(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs,
-- const char *secstrings, unsigned int symindex, bool is_init)
--{
-- unsigned long ret = 0;
-- unsigned int i, j;
-- Elf_Sym *syms;
--
-- /* Everything marked ALLOC (this includes the exported symbols) */
-- for (i = 1; i < hdr->e_shnum; ++i) {
-- unsigned int info = sechdrs[i].sh_info;
--
-- if (sechdrs[i].sh_type != SHT_REL
-- && sechdrs[i].sh_type != SHT_RELA)
-- continue;
--
-- /* Not a valid relocation section? */
-- if (info >= hdr->e_shnum)
-- continue;
--
-- /* Don't bother with non-allocated sections */
-- if (!(sechdrs[info].sh_flags & SHF_ALLOC))
-- continue;
--
-- /* If it's called *.init*, and we're not init, we're
-- not interested */
-- if ((strstr(secstrings + sechdrs[i].sh_name, ".init") != 0)
-- != is_init)
-- continue;
--
-- syms = (Elf_Sym *) sechdrs[symindex].sh_addr;
-- if (sechdrs[i].sh_type == SHT_REL) {
-- Elf_Mips_Rel *rel = (void *) sechdrs[i].sh_addr;
-- unsigned int size = sechdrs[i].sh_size / sizeof(*rel);
--
-- for (j = 0; j < size; ++j) {
-- Elf_Sym *sym;
--
-- if (ELF_MIPS_R_TYPE(rel[j]) != R_MIPS_26)
-- continue;
--
-- sym = syms + ELF_MIPS_R_SYM(rel[j]);
-- if (!is_init && sym->st_shndx != SHN_UNDEF)
-- continue;
--
-- ret += 4 * sizeof(int);
-- }
-- } else {
-- Elf_Mips_Rela *rela = (void *) sechdrs[i].sh_addr;
-- unsigned int size = sechdrs[i].sh_size / sizeof(*rela);
--
-- for (j = 0; j < size; ++j) {
-- Elf_Sym *sym;
--
-- if (ELF_MIPS_R_TYPE(rela[j]) != R_MIPS_26)
-- continue;
--
-- sym = syms + ELF_MIPS_R_SYM(rela[j]);
-- if (!is_init && sym->st_shndx != SHN_UNDEF)
-- continue;
--
-- ret += 4 * sizeof(int);
-- }
-- }
-- }
--
-- return ret;
--}
--
--#ifndef MODULE_START
--static void *alloc_phys(unsigned long size)
--{
-- unsigned order;
-- struct page *page;
-- struct page *p;
--
-- size = PAGE_ALIGN(size);
-- order = get_order(size);
--
-- page = alloc_pages(GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN |
-- __GFP_THISNODE, order);
-- if (!page)
-- return NULL;
--
-- split_page(page, order);
--
-- for (p = page + (size >> PAGE_SHIFT); p < page + (1 << order); ++p)
-- __free_page(p);
--
-- return page_address(page);
--}
--#endif
--
--static void free_phys(void *ptr, unsigned long size)
--{
-- struct page *page;
-- struct page *end;
--
-- page = virt_to_page(ptr);
-- end = page + (PAGE_ALIGN(size) >> PAGE_SHIFT);
--
-- for (; page < end; ++page)
-- __free_page(page);
--}
--
--
- void *module_alloc(unsigned long size)
- {
- #ifdef MODULE_START
-@@ -162,99 +51,21 @@ void *module_alloc(unsigned long size)
- GFP_KERNEL, PAGE_KERNEL, -1,
- __builtin_return_address(0));
- #else
-- void *ptr;
--
- if (size == 0)
- return NULL;
--
-- ptr = alloc_phys(size);
--
-- /* If we failed to allocate physically contiguous memory,
-- * fall back to regular vmalloc. The module loader code will
-- * create jump tables to handle long jumps */
-- if (!ptr)
-- return vmalloc(size);
--
-- return ptr;
--#endif
--}
--
--static inline bool is_phys_addr(void *ptr)
--{
--#ifdef CONFIG_64BIT
-- return (KSEGX((unsigned long)ptr) == CKSEG0);
--#else
-- return (KSEGX(ptr) == KSEG0);
-+ return vmalloc(size);
- #endif
- }
-
- /* Free memory returned from module_alloc */
- void module_free(struct module *mod, void *module_region)
- {
-- if (is_phys_addr(module_region)) {
-- if (mod->module_init == module_region)
-- free_phys(module_region, mod->init_size);
-- else if (mod->module_core == module_region)
-- free_phys(module_region, mod->core_size);
-- else
-- BUG();
-- } else {
-- vfree(module_region);
-- }
--}
--
--static void *__module_alloc(int size, bool phys)
--{
-- void *ptr;
--
-- if (phys)
-- ptr = kmalloc(size, GFP_KERNEL);
-- else
-- ptr = vmalloc(size);
-- return ptr;
--}
--
--static void __module_free(void *ptr)
--{
-- if (is_phys_addr(ptr))
-- kfree(ptr);
-- else
-- vfree(ptr);
-+ vfree(module_region);
- }
-
- int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
- char *secstrings, struct module *mod)
- {
-- unsigned int symindex = 0;
-- unsigned int core_size, init_size;
-- int i;
--
-- for (i = 1; i < hdr->e_shnum; i++)
-- if (sechdrs[i].sh_type == SHT_SYMTAB)
-- symindex = i;
--
-- core_size = get_plt_size(hdr, sechdrs, secstrings, symindex, false);
-- init_size = get_plt_size(hdr, sechdrs, secstrings, symindex, true);
--
-- mod->arch.phys_plt_offset = 0;
-- mod->arch.virt_plt_offset = 0;
-- mod->arch.phys_plt_tbl = NULL;
-- mod->arch.virt_plt_tbl = NULL;
--
-- if ((core_size + init_size) == 0)
-- return 0;
--
-- mod->arch.phys_plt_tbl = __module_alloc(core_size + init_size, 1);
-- if (!mod->arch.phys_plt_tbl)
-- return -ENOMEM;
--
-- mod->arch.virt_plt_tbl = __module_alloc(core_size + init_size, 0);
-- if (!mod->arch.virt_plt_tbl) {
-- __module_free(mod->arch.phys_plt_tbl);
-- mod->arch.phys_plt_tbl = NULL;
-- return -ENOMEM;
-- }
--
- return 0;
- }
-
-@@ -277,36 +88,28 @@ static int apply_r_mips_32_rela(struct m
- return 0;
- }
-
--static Elf_Addr add_plt_entry_to(unsigned *plt_offset,
-- void *start, Elf_Addr v)
-+static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v)
- {
-- unsigned *tramp = start + *plt_offset;
-- *plt_offset += 4 * sizeof(int);
--
-- /* adjust carry for addiu */
-- if (v & 0x00008000)
-- v += 0x10000;
--
-- tramp[0] = 0x3c190000 | (v >> 16); /* lui t9, hi16 */
-- tramp[1] = 0x27390000 | (v & 0xffff); /* addiu t9, t9, lo16 */
-- tramp[2] = 0x03200008; /* jr t9 */
-- tramp[3] = 0x00000000; /* nop */
-+ if (v % 4) {
-+ pr_err("module %s: dangerous R_MIPS_26 REL relocation\n",
-+ me->name);
-+ return -ENOEXEC;
-+ }
-
-- return (Elf_Addr) tramp;
--}
-+ if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
-+ printk(KERN_ERR
-+ "module %s: relocation overflow\n",
-+ me->name);
-+ return -ENOEXEC;
-+ }
-
--static Elf_Addr add_plt_entry(struct module *me, void *location, Elf_Addr v)
--{
-- if (is_phys_addr(location))
-- return add_plt_entry_to(&me->arch.phys_plt_offset,
-- me->arch.phys_plt_tbl, v);
-- else
-- return add_plt_entry_to(&me->arch.virt_plt_offset,
-- me->arch.virt_plt_tbl, v);
-+ *location = (*location & ~0x03ffffff) |
-+ ((*location + (v >> 2)) & 0x03ffffff);
-
-+ return 0;
- }
-
--static int set_r_mips_26(struct module *me, u32 *location, u32 ofs, Elf_Addr v)
-+static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v)
- {
- if (v % 4) {
- pr_err("module %s: dangerous R_MIPS_26 RELArelocation\n",
-@@ -315,31 +118,17 @@ static int set_r_mips_26(struct module *
- }
-
- if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
-- v = add_plt_entry(me, location, v + (ofs << 2));
-- if (!v) {
-- printk(KERN_ERR
-+ printk(KERN_ERR
- "module %s: relocation overflow\n",
- me->name);
-- return -ENOEXEC;
-- }
-- ofs = 0;
-+ return -ENOEXEC;
- }
-
-- *location = (*location & ~0x03ffffff) | ((ofs + (v >> 2)) & 0x03ffffff);
-+ *location = (*location & ~0x03ffffff) | ((v >> 2) & 0x03ffffff);
-
- return 0;
- }
-
--static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v)
--{
-- return set_r_mips_26(me, location, *location & 0x03ffffff, v);
--}
--
--static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v)
--{
-- return set_r_mips_26(me, location, 0, v);
--}
--
- static int apply_r_mips_hi16_rel(struct module *me, u32 *location, Elf_Addr v)
- {
- struct mips_hi16 *n;
-@@ -607,32 +396,11 @@ int module_finalize(const Elf_Ehdr *hdr,
- list_add(&me->arch.dbe_list, &dbe_list);
- spin_unlock_irq(&dbe_lock);
- }
--
-- /* Get rid of the fixup trampoline if we're running the module
-- * from physically mapped address space */
-- if (me->arch.phys_plt_offset == 0) {
-- __module_free(me->arch.phys_plt_tbl);
-- me->arch.phys_plt_tbl = NULL;
-- }
-- if (me->arch.virt_plt_offset == 0) {
-- __module_free(me->arch.virt_plt_tbl);
-- me->arch.virt_plt_tbl = NULL;
-- }
--
- return 0;
- }
-
- void module_arch_cleanup(struct module *mod)
- {
-- if (mod->arch.phys_plt_tbl) {
-- __module_free(mod->arch.phys_plt_tbl);
-- mod->arch.phys_plt_tbl = NULL;
-- }
-- if (mod->arch.virt_plt_tbl) {
-- __module_free(mod->arch.virt_plt_tbl);
-- mod->arch.virt_plt_tbl = NULL;
-- }
--
- spin_lock_irq(&dbe_lock);
- list_del(&mod->arch.dbe_list);
- spin_unlock_irq(&dbe_lock);
+++ /dev/null
-#
-# Copyright (C) 2010-2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=sparc
-BOARD:=sparc
-BOARDNAME:=Sun UltraSPARC
-FEATURES+=fpu tgz ext4 squashfs broken
-
-LINUX_VERSION:=3.10.49
-MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
-
-include $(INCLUDE_DIR)/target.mk
-
-$(eval $(call BuildTarget))
+++ /dev/null
-CONFIG_64BIT=y
-CONFIG_ARCH_DEFCONFIG="arch/sparc/configs/sparc64_defconfig"
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_ARCH_NO_VIRT_TO_BUS=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_MSI=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-# CONFIG_ARPD is not set
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH=y
-# CONFIG_BBC_I2C is not set
-CONFIG_BCMA_POSSIBLE=y
-CONFIG_BITS=64
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLOCK_COMPAT=y
-# CONFIG_BRIDGE is not set
-CONFIG_CMDLINE="console=ttyS0 init=/etc/preinit"
-CONFIG_CMDLINE_BOOL=y
-CONFIG_COMPAT=y
-CONFIG_COMPAT_BINFMT_ELF=y
-CONFIG_COMPAT_BRK=y
-CONFIG_COMPAT_NETLINK_MESSAGES=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRAMFS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_DCFLUSH is not set
-CONFIG_DECOMPRESS_LZMA=y
-# CONFIG_DISPLAY7SEG is not set
-CONFIG_DNOTIFY=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EARLYFB=y
-CONFIG_ELF_CORE=y
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_ENVCTRL is not set
-CONFIG_FB=y
-# CONFIG_FB_GRVGA is not set
-# CONFIG_FB_SBUS is not set
-# CONFIG_FB_WMT_GE_ROPS is not set
-# CONFIG_FB_XVR1000 is not set
-# CONFIG_FB_XVR2500 is not set
-# CONFIG_FB_XVR500 is not set
-CONFIG_FIRMWARE_IN_KERNEL=y
-# CONFIG_FONTS is not set
-# CONFIG_FONT_SUN12x22 is not set
-CONFIG_FONT_SUN8x16=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ACL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-# CONFIG_GRETH is not set
-# CONFIG_HAMRADIO is not set
-CONFIG_HAPPYMEAL=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MEMORY_PRESENT=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_RCU_TABLE_FREE=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_SYSCALL_WRAPPERS=y
-CONFIG_HID=m
-CONFIG_HID_SUPPORT=y
-# CONFIG_HUGETLBFS is not set
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_SPARCSPKR is not set
-CONFIG_IOMMU_HELPER=y
-CONFIG_IRQ_PREFLOW_FASTEOI=y
-# CONFIG_LEDS_SUNFIRE is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_MTD is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NR_CPUS=4
-# CONFIG_NUMA is not set
-# CONFIG_OBP_FLASH is not set
-CONFIG_OF=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PROMTREE=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PATA_CMD64X=y
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_RELAY=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BQ4802=y
-CONFIG_RTC_DRV_M48T59=y
-CONFIG_RTC_DRV_STARFIRE=y
-CONFIG_RTC_DRV_SUN4V=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_SATA_PMP=y
-CONFIG_SBUS=y
-CONFIG_SBUSCHAR=y
-CONFIG_SCHED_HRTICK=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SECCOMP=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_SUNCORE=y
-# CONFIG_SERIAL_SUNHV is not set
-CONFIG_SERIAL_SUNSAB=y
-CONFIG_SERIAL_SUNSAB_CONSOLE=y
-CONFIG_SERIAL_SUNSU=y
-CONFIG_SERIAL_SUNSU_CONSOLE=y
-# CONFIG_SERIAL_SUNZILOG is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SMP=y
-CONFIG_SPARC=y
-# CONFIG_SPARC32 is not set
-CONFIG_SPARC64=y
-# CONFIG_SPARC64_PAGE_SIZE_64KB is not set
-CONFIG_SPARC64_PAGE_SIZE_8KB=y
-CONFIG_SPARC64_PCI=y
-CONFIG_SPARC64_SMP=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_STOP_MACHINE=y
-# CONFIG_SUNBMAC is not set
-# CONFIG_SUNLANCE is not set
-# CONFIG_SUNQE is not set
-# CONFIG_SUN_LDOMS is not set
-CONFIG_SUN_OPENPROMFS=y
-CONFIG_SUN_OPENPROMIO=y
-CONFIG_SUN_PARTITION=y
-CONFIG_SYSVIPC_COMPAT=y
-# CONFIG_TADPOLE_TS102_UCTRL is not set
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TREE_RCU=y
-CONFIG_UID16=y
-# CONFIG_US3_MC is not set
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-# CONFIG_VLAN_8021Q is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_WATCHDOG is not set
-CONFIG_XPS=y
-CONFIG_XZ_DEC=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-#
-# Copyright (C) 2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/Prepare
- cp $(LINUX_DIR)/arch/sparc/boot/zImage $(KDIR)/zImage
-endef
-
-define Image/BuildKernel
- mkdir -p $(BIN_DIR)
- cp $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage
-# cp $(KDIR)/vmlinux.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.elf
-endef
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
-endef
-
-define Image/Build
- $(call Image/Build/$(1))
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-root.$(1) bs=128k conv=sync
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-#
-# Copyright (C) 2013-2014 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=sunxi
-BOARDNAME:=Allwinner A1x/A20/A3x
-FEATURES:=fpu usb ext4 display rtc
-CPU_TYPE:=cortex-a8
-CPU_SUBTYPE:=vfpv3
-MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
-
-LINUX_VERSION:=3.13.7
-KERNELNAME:="zImage dtbs"
-DEFAULT_PACKAGES += uboot-envtools uboot-sunxi kmod-eeprom-sunxi kmod-wdt-sunxi
-
-# A10: Cortex-A8
-# A13: Cortex-A8
-# A20: dual Cortex-A7
-# A31: quad Cortex-A7
-
-include $(INCLUDE_DIR)/target.mk
-
-$(eval $(call BuildTarget))
+++ /dev/null
-define Package/base-files/install-target
- rm -f $(1)/etc/config/network
-endef
+++ /dev/null
-::sysinit:/etc/init.d/rcS S boot
-::shutdown:/etc/init.d/rcS K shutdown
-tts/0::askfirst:/bin/ash --login
-ttyS0::askfirst:/bin/ash --login
-tty1::askfirst:/bin/ash --login
+++ /dev/null
-#!/bin/sh
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-
-[ -e /etc/config/network ] && exit 0
-
-touch /etc/config/network
-
-. /lib/functions/uci-defaults.sh
-
-ucidef_set_interface_loopback
-
-case "`cat /proc/device-tree/model`" in
-"Cubietech Cubieboard" |\
-"Cubietech Cubieboard2" |\
-"LinkSprite pcDuino" |\
-"LinkSprite pcDuino V3" |\
-"Olimex A10-OLinuXino-LIME" |\
-"Olimex A20-Olinuxino Micro")
- ucidef_set_interface_lan 'eth0'
- ;;
-"Olimex A13-Olinuxino")
- ucidef_set_interface_lan 'wlan0'
- ;;
-esac
-
-uci commit network
-
-exit 0
+++ /dev/null
-#!/bin/sh
-
-do_sunxi() {
- . /lib/sunxi.sh
-
- sunxi_board_detect
-}
-
-boot_hook_add preinit_main do_sunxi
+++ /dev/null
-#!/bin/sh
-
-# defaults
-SUNXI_BOARD_NAME="generic sunxi"
-SUNXI_BOARD_MODEL="generic sunxi"
-SUNXI_ENV_DEV=/dev/mmcblk0
-
-#Helper functions
-get_cmdline_opt()
-{
-cat /proc/cmdline | awk -F$1= '{print $2}' | awk '{print $1}'
-}
-
-#Since fw_getenv doesn't work with blockdevs let's make a hack
-uboot_getenv()
-{
- dd if=$SUNXI_ENV_DEV bs=1024 skip=544 count=128 2>dev/null |\strings|grep $1|cut -d"=" -f2
-}
-
-#Actual routines go below
-sunxi_env_dev()
-{
- local dev
- dev=`get_cmdline_opt root|cut -d"p" -f1`
- SUNXI_ENV_DEV=$dev
- echo "probing $dev for uboot env data"
-}
-
-sunxi_board_detect() {
- local board
- local model
- sunxi_env_dev
- [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/"
- board="`uboot_getenv wrt_board`"
- model="`uboot_getenv wrt_model`"
- if [ "$board" != "" ]; then
- SUNXI_BOARD_NAME="$board"
- fi
- if [ "$model" != "" ]; then
- SUNXI_BOARD_MODEL="$model"
- fi
- echo "$SUNXI_BOARD_NAME" > /tmp/sysinfo/board_name
- echo "$SUNXI_BOARD_MODEL" > /tmp/sysinfo/model
- echo "Detected $SUNXI_BOARD_NAME // $SUNXI_BOARD_MODEL"
-}
+++ /dev/null
-CONFIG_AHCI_SUNXI=y
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=288
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_ERRATA_430973=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_AUDIT=y
-# CONFIG_AUDITSYSCALL is not set
-CONFIG_AUDIT_GENERIC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_AVERAGE=y
-CONFIG_BCH=y
-CONFIG_BINFMT_MISC=y
-CONFIG_BLK_CGROUP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_BOUNCE=y
-CONFIG_BRIDGE_IGMP_SNOOPING=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CFQ_GROUP_IOSCHED=y
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_FREEZER=y
-# CONFIG_CGROUP_PERF is not set
-# CONFIG_CGROUP_SCHED is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk rootwait root=/dev/mmcblk0p2"
-CONFIG_CMDLINE_FORCE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACTION=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONNECTOR=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPUSETS=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-# CONFIG_DEBUG_BLK_CGROUP is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_UART_PL01X is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_DIRECT_IO=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_OF=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DWMAC_SUNXI=y
-# CONFIG_DW_DMAC_CORE is not set
-CONFIG_DYNAMIC_DEBUG=y
-# CONFIG_EEPROM_SUNXI_SID is not set
-CONFIG_ELF_CORE=y
-# CONFIG_EMBEDDED is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_EXPERT is not set
-CONFIG_EXT4_FS=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FRAME_WARN=2048
-CONFIG_FREEZER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GARP=y
-CONFIG_GENERIC_ACL=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_MUX=y
-# CONFIG_I2C_MUX_GPIO is not set
-# CONFIG_I2C_MUX_PCA9541 is not set
-# CONFIG_I2C_MUX_PCA954x is not set
-CONFIG_I2C_MUX_PINCTRL=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_INPUT_MISC is not set
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_IPC_NS=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_BOOTP is not set
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_RARP is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KALLSYMS=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEYBOARD_SUN4I_LRADC=y
-CONFIG_KSM=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_REGULATOR is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MDIO_SUN4I=y
-# CONFIG_MEMCG is not set
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_SUNXI=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NAMESPACES=y
-CONFIG_NEED_DMA_MAP_STATE=y
-# CONFIG_NEON is not set
-# CONFIG_NETPRIO_CGROUP is not set
-# CONFIG_NET_CLS_CGROUP is not set
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_NS=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_NET_VENDOR_ALLWINNER=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARTITION_ADVANCED is not set
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_SUN4I_USB=y
-CONFIG_PID_NS=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINCTRL_SUNXI=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_PTP_1588_CLOCK=y
-# CONFIG_QFMT_V1 is not set
-# CONFIG_QFMT_V2 is not set
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_RCU_BOOST is not set
-CONFIG_RCU_CPU_STALL_VERBOSE=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_LZO=y
-CONFIG_RD_XZ=y
-CONFIG_REGMAP=y
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-CONFIG_RELAY=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESOURCE_COUNTERS=y
-# CONFIG_RFKILL_REGULATOR is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SCHED_HRTICK=y
-CONFIG_SCSI=y
-CONFIG_SECURITYFS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_NR_UARTS=8
-CONFIG_SERIAL_8250_RUNTIME_UARTS=8
-CONFIG_SERIAL_8250_SYSRQ=y
-CONFIG_SERIO=y
-# CONFIG_SERIO_APBPS2 is not set
-# CONFIG_SERIO_OLPC_APSP is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLUB_DEBUG_ON is not set
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_SUN4I=y
-# CONFIG_SPI_SUN6I is not set
-# CONFIG_STAGING is not set
-# CONFIG_STMMAC_DA is not set
-# CONFIG_STMMAC_DEBUG_FS is not set
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_STOP_MACHINE=y
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_SUN4I_EMAC is not set
-CONFIG_SUN4I_TIMER=y
-CONFIG_SUN5I_HSTIMER=y
-CONFIG_SUNXI_WATCHDOG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_TASK_XACCT=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TOUCHSCREEN_SUN4I=y
-CONFIG_TREE_PREEMPT_RCU=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UID16=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USER_NS is not set
-CONFIG_USE_OF=y
-CONFIG_UTS_NS=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_XEN is not set
-CONFIG_XFRM_ALGO=y
-CONFIG_XFRM_USER=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-# CONFIG_ZBUD is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-/*
- * Copyright 2014 Zoltan HERPAI
- * Zoltan HERPAI <wigyori@uid0.hu>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-/include/ "sun7i-a20.dtsi"
-/include/ "sunxi-ahci-reg.dtsi"
-/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Lemaker bananaPi";
- compatible = "lemaker,bananapi", "allwinner,sun7i-a20";
-
- aliases {
- spi0 = &spi1;
- spi1 = &spi2;
- };
-
- soc@01c00000 {
- spi1: spi@01c06000 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins_a>;
- status = "okay";
- };
-
- spi2: spi@01c17000 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
- };
-
- mmc0: mmc@01c0f000 {
- pinctrl-names = "default", "default";
- pinctrl-0 = <&mmc0_pins_a>;
- pinctrl-1 = <&mmc0_cd_pin_bananapi>;
- cd-gpios = <&pio 7 10 0>; /* PH10 */
- status = "okay";
- };
-
- usbphy: phy@01c13400 {
- usb1_vbus-supply = <®_usb1_vbus>;
- usb2_vbus-supply = <®_usb2_vbus>;
- status = "okay";
- };
-
- ehci0: usb@01c14000 {
- status = "okay";
- };
-
- ohci0: usb@01c14400 {
- status = "okay";
- };
-
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
- };
-
- ehci1: usb@01c1c000 {
- status = "okay";
- };
-
- ohci1: usb@01c1c400 {
- status = "okay";
- };
-
- pinctrl@01c20800 {
- led_pins_bananapi: led_pins@0 {
- allwinner,pins = "PH2";
- allwinner,function = "gpio_out";
- allwinner,drive = <1>;
- allwinner,pull = <0>;
- };
-
- mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
- allwinner,pins = "PH10";
- allwinner,function = "gpio_in";
- allwinner,drive = <0>;
- allwinner,pull = <1>;
- };
- };
-
- lradc: lradc@01c22800 {
- allwinner,chan0-step = <200>;
- linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN
- KEY_MENU KEY_SEARCH KEY_HOME
- KEY_ESC KEY_ENTER>;
- status = "okay";
- };
-
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
- };
-
- uart6: serial@01c29800 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart6_pins_a>;
- status = "okay";
- };
-
- uart7: serial@01c29c00 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
- status = "okay";
- };
-
- i2c0: i2c@01c2ac00 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
- };
-
- i2c1: i2c@01c2b000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
- status = "okay";
- };
-
- i2c2: i2c@01c2b400 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
- status = "okay";
- };
-
- gmac: ethernet@01c50000 {
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
- phy = <&phy1>;
- phy-mode = "mii";
- status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_bananapi>;
-
- green {
- label = "bananapi:green:usr";
- gpios = <&pio 7 2 0>;
- default-state = "on";
- };
- };
-};
+++ /dev/null
-/*
- * Copyright 2013 Oliver Schinagl
- *
- * Oliver Schinagl <oliver@schinagl.nl>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-/include/ "sun7i-a20.dtsi"
-
-/ {
- model = "Cubietech Cubietruck";
- compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
-
- soc@01c00000 {
- pinctrl@01c20800 {
- led_pins_cubietruck: led_pins@0 {
- allwinner,pins = "PH7", "PH11", "PH20", "PH21";
- allwinner,function = "gpio_out";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-
- usb1_vbus_pin: usb1_vbus_pin@0 {
- allwinner,pins = "PH6";
- allwinner,function = "gpio_out";
- allwinner,drive = <0>;
- allwinner,pull = <2>;
- };
-
- usb2_vbus_pin: usb2_vbus_pin@0 {
- allwinner,pins = "PH3";
- allwinner,function = "gpio_out";
- allwinner,drive = <0>;
- allwinner,pull = <2>;
- };
- };
-
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_cubietruck>;
-
- blue {
- label = "cubietruck:blue:usr";
- gpios = <&pio 7 21 0>;
- };
-
- orange {
- label = "cubietruck:orange:usr";
- gpios = <&pio 7 20 0>;
- };
-
- white {
- label = "cubietruck:white:usr";
- gpios = <&pio 7 11 0>;
- };
-
- green {
- label = "cubietruck:green:usr";
- gpios = <&pio 7 7 0>;
- };
- };
-};
+++ /dev/null
-/*
- * Copyright 2014 Zoltan HERPAI
- * Zoltan HERPAI <wigyori@uid0.hu>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-/include/ "sun7i-a20.dtsi"
-/include/ "sunxi-ahci-reg.dtsi"
-/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "LinkSprite pcDuino V3";
- compatible = "linksprite,a20-pcduino", "allwinner,sun7i-a20";
-
- aliases {
- spi0 = &spi1;
- spi1 = &spi2;
- };
-
- soc@01c00000 {
- spi1: spi@01c06000 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins_a>;
- status = "okay";
- };
-
- spi2: spi@01c17000 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
- };
-
- mmc0: mmc@01c0f000 {
- pinctrl-names = "default", "default";
- pinctrl-0 = <&mmc0_pins_a>;
- pinctrl-1 = <&mmc0_cd_pin_reference_design>;
- cd-gpios = <&pio 7 1 0>; /* PH1 */
- status = "okay";
- };
-
- usbphy: phy@01c13400 {
- usb1_vbus-supply = <®_usb1_vbus>;
- usb2_vbus-supply = <®_usb2_vbus>;
- status = "okay";
- };
-
- ehci0: usb@01c14000 {
- status = "okay";
- };
-
- ohci0: usb@01c14400 {
- status = "okay";
- };
-
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
- };
-
- ehci1: usb@01c1c000 {
- status = "okay";
- };
-
- ohci1: usb@01c1c400 {
- status = "okay";
- };
-
- pinctrl@01c20800 {
- led_pins_pcduino3: led_pins@0 {
- allwinner,pins = "PH2";
- allwinner,function = "gpio_out";
- allwinner,drive = <1>;
- allwinner,pull = <0>;
- };
- };
-
- lradc: lradc@01c22800 {
- allwinner,chan0-step = <200>;
- linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN
- KEY_MENU KEY_SEARCH KEY_HOME
- KEY_ESC KEY_ENTER>;
- status = "okay";
- };
-
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
- };
-
- uart6: serial@01c29800 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart6_pins_a>;
- status = "okay";
- };
-
- uart7: serial@01c29c00 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
- status = "okay";
- };
-
- i2c0: i2c@01c2ac00 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
- };
-
- i2c1: i2c@01c2b000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
- status = "okay";
- };
-
- i2c2: i2c@01c2b400 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
- status = "okay";
- };
-
- gmac: ethernet@01c50000 {
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
- phy = <&phy1>;
- phy-mode = "mii";
- status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_pcduino3>;
-
- green {
- label = "a20-pcduino:green:usr";
- gpios = <&pio 7 2 0>;
- default-state = "on";
- };
- };
-};
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-BOARDS:= \
- sun4i-a10-cubieboard \
- sun4i-a10-olinuxino-lime \
- sun4i-a10-pcduino \
- sun5i-a13-olinuxino \
- sun6i-a31-colombus \
- sun7i-a20-bananapi \
- sun7i-a20-cubieboard2 \
- sun7i-a20-cubietruck \
- sun7i-a20-olinuxino-micro \
- sun7i-a20-pcduino3
-
-define Image/BuildKernel
- mkimage -A arm -O linux -T kernel -C none \
- -a 0x40008000 -e 0x40008000 \
- -n 'ARM OpenWrt Linux-$(LINUX_VERSION)' \
- -d $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-uImage
-
- ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
- $(CP) $(KDIR)/zImage-initramfs $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs
- echo -ne '\x00\x00\x00\x00' >> $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs
- $(call Image/BuildKernel/MkuImage, \
- none, 0x40008000, 0x40008000, \
- $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs, \
- $(BIN_DIR)/$(IMG_PREFIX)-uImage-initramfs \
- )
- endif
-
- $(foreach board,$(BOARDS),
- $(CP) $(DTS_DIR)/$(board).dtb $(BIN_DIR)/
- )
-endef
-
-define Image/Build
- $(call Image/Build/$(1),$(1))
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-root.$(1) bs=128k conv=sync
-endef
-
-$(eval $(call BuildImage))
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-
-define KernelPackage/rtc-sunxi
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Sunxi SoC built-in RTC support
- DEPENDS:=@TARGET_sunxi
- $(call AddDepends/rtc)
- KCONFIG:= \
- CONFIG_RTC_CLASS=y \
- CONFIG_RTC_DRV_SUNXI=m
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-sunxi.ko
- AUTOLOAD:=$(call AutoLoad,50,rtc-sunxi)
-endef
-
-define KernelPackage/rtc-sunxi/description
- Support for the AllWinner sunXi SoC's onboard RTC
-endef
-
-$(eval $(call KernelPackage,rtc-sunxi))
-
-define KernelPackage/eeprom-sunxi
- SUBMENU:=$(OTHER_MENU)
- TITLE:=AllWinner Security ID fuse support
- DEPENDS:=@TARGET_sunxi
- KCONFIG:= \
- CONFIG_EEPROM_SUNXI_SID
- FILES:=$(LINUX_DIR)/drivers/misc/eeprom/sunxi_sid.ko
- AUTOLOAD:=$(call AutoLoad,50,sunxi_sid)
-endef
-
-define KernelPackage/eeprom-sunxi/description
- Support for the AllWinner Security ID fuse support
-endef
-
-$(eval $(call KernelPackage,eeprom-sunxi))
-
-define KernelPackage/ata-sunxi
- TITLE:=AllWinner sunXi AHCI SATA support
- SUBMENU:=$(BLOCK_MENU)
- DEPENDS:=@TARGET_sunxi +kmod-scsi-core
- KCONFIG:=\
- CONFIG_AHCI_SUNXI \
- CONFIG_SATA_AHCI_PLATFORM
- FILES:=$(LINUX_DIR)/drivers/ata/ahci_sunxi.ko
- AUTOLOAD:=$(call AutoLoad,41,ahci_sunxi,1)
-endef
-
-define KernelPackage/ata-sunxi/description
- SATA support for the AllWinner sunXi SoC's onboard AHCI SATA
-endef
-
-$(eval $(call KernelPackage,ata-sunxi))
-
-define KernelPackage/sun4i-emac
- SUBMENU:=$(NETWORK_DEVICES_MENU)
- TITLE:=AllWinner EMAC Ethernet support
- DEPENDS:=@TARGET_sunxi
- KCONFIG:=CONFIG_SUN4I_EMAC
- FILES:=$(LINUX_DIR)/drivers/net/ethernet/allwinner/sun4i-emac.ko
- AUTOLOAD:=$(call AutoProbe,sun4i-emac)
-endef
-
-$(eval $(call KernelPackage,sun4i-emac))
-
-
-define KernelPackage/wdt-sunxi
- SUBMENU:=$(OTHER_MENU)
- TITLE:=AllWinner sunXi Watchdog timer
- DEPENDS:=@TARGET_sunxi
- KCONFIG:=CONFIG_SUNXI_WATCHDOG
- FILES:=$(LINUX_DIR)/drivers/$(WATCHDOG_DIR)/sunxi_wdt.ko
- AUTOLOAD:=$(call AutoLoad,51,sunxi_wdt)
-endef
-
-define KernelPackage/wdt-sunxi/description
- Kernel module for AllWinner sunXi watchdog timer.
-endef
-
-$(eval $(call KernelPackage,wdt-sunxi))
-
+++ /dev/null
-From a968e9dc5983d258a4aa7e496d58c92e9e4cf670 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Sat, 14 Sep 2013 21:37:59 -0300
-Subject: [PATCH] clk: composite: .determine_rate support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds .determine_rate support to the composite clock. It will
-use the .determine_rate callback from the rate component if available,
-and fall back on the mux component otherwise. This allows composite
-clocks to enjoy the benefits of automatic clock reparenting.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clk/clk-composite.c | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
---- a/drivers/clk/clk-composite.c
-+++ b/drivers/clk/clk-composite.c
-@@ -55,6 +55,30 @@ static unsigned long clk_composite_recal
- return rate_ops->recalc_rate(rate_hw, parent_rate);
- }
-
-+static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
-+ unsigned long *best_parent_rate,
-+ struct clk **best_parent_p)
-+{
-+ struct clk_composite *composite = to_clk_composite(hw);
-+ const struct clk_ops *rate_ops = composite->rate_ops;
-+ const struct clk_ops *mux_ops = composite->mux_ops;
-+ struct clk_hw *rate_hw = composite->rate_hw;
-+ struct clk_hw *mux_hw = composite->mux_hw;
-+
-+ if (rate_hw && rate_ops && rate_ops->determine_rate) {
-+ rate_hw->clk = hw->clk;
-+ return rate_ops->determine_rate(rate_hw, rate, best_parent_rate,
-+ best_parent_p);
-+ } else if (mux_hw && mux_ops && mux_ops->determine_rate) {
-+ mux_hw->clk = hw->clk;
-+ return mux_ops->determine_rate(rate_hw, rate, best_parent_rate,
-+ best_parent_p);
-+ } else {
-+ pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
-+ return 0;
-+ }
-+}
-+
- static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
- {
-@@ -147,6 +171,8 @@ struct clk *clk_register_composite(struc
- composite->mux_ops = mux_ops;
- clk_composite_ops->get_parent = clk_composite_get_parent;
- clk_composite_ops->set_parent = clk_composite_set_parent;
-+ if (mux_ops->determine_rate)
-+ clk_composite_ops->determine_rate = clk_composite_determine_rate;
- }
-
- if (rate_hw && rate_ops) {
-@@ -170,6 +196,8 @@ struct clk *clk_register_composite(struc
- composite->rate_hw = rate_hw;
- composite->rate_ops = rate_ops;
- clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
-+ if (rate_ops->determine_rate)
-+ clk_composite_ops->determine_rate = clk_composite_determine_rate;
- }
-
- if (gate_hw && gate_ops) {
+++ /dev/null
-From b3cb099f8b0cbe56fcfbb4fb9c7cce48afff41f0 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Fri, 20 Sep 2013 22:03:10 -0300
-Subject: [PATCH] clk: sunxi: factors: fix off-by-one masks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The previous code would generate one bit too long masks, and was
-needlessly complicated. This patch replaces it by simpler code that can
-generate the masks correctly.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clk/sunxi/clk-factors.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/sunxi/clk-factors.c
-+++ b/drivers/clk/sunxi/clk-factors.c
-@@ -40,7 +40,7 @@ struct clk_factors {
-
- #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
-
--#define SETMASK(len, pos) (((-1U) >> (31-len)) << (pos))
-+#define SETMASK(len, pos) (((1U << (len)) - 1) << (pos))
- #define CLRMASK(len, pos) (~(SETMASK(len, pos)))
- #define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit))
-
+++ /dev/null
-From 789bea92aba0256a7f5309992327df8729333750 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Fri, 20 Sep 2013 22:03:11 -0300
-Subject: [PATCH] clk: sunxi: factors: clear variables before using them
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Random bits may get into our factors if we don't clear n, k, m and p.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clk/sunxi/clk-factors.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/sunxi/clk-factors.c
-+++ b/drivers/clk/sunxi/clk-factors.c
-@@ -88,7 +88,7 @@ static long clk_factors_round_rate(struc
- static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
- {
-- u8 n, k, m, p;
-+ u8 n = 0, k = 0, m = 0, p = 0;
- u32 reg;
- struct clk_factors *factors = to_clk_factors(hw);
- struct clk_factors_config *config = factors->config;
+++ /dev/null
-From 7df19a0adca7806e081479eecb07365652c26ef5 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Fri, 20 Sep 2013 22:03:12 -0300
-Subject: [PATCH] clk: sunxi: protect core clocks from accidental shutdown
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Some important clocks may get disabled as a side effect of another clock
-being disabled, because they have no consumers. This patch implements a
-mechanism so those clocks can be claimed by the driver and therefore
-remain enabled at all times.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-
-Conflicts:
- drivers/clk/sunxi/clk-sunxi.c
----
- drivers/clk/sunxi/clk-sunxi.c | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -616,6 +616,31 @@ static void __init of_sunxi_table_clock_
- }
- }
-
-+/**
-+ * System clock protection
-+ *
-+ * By enabling these critical clocks, we prevent their accidental gating
-+ * by the framework
-+ */
-+static void __init sunxi_clock_protect(void)
-+{
-+ struct clk *clk;
-+
-+ /* memory bus clock - sun5i+ */
-+ clk = clk_get(NULL, "mbus");
-+ if (!IS_ERR(clk)) {
-+ clk_prepare_enable(clk);
-+ clk_put(clk);
-+ }
-+
-+ /* DDR clock - sun4i+ */
-+ clk = clk_get(NULL, "pll5_ddr");
-+ if (!IS_ERR(clk)) {
-+ clk_prepare_enable(clk);
-+ clk_put(clk);
-+ }
-+}
-+
- static void __init sunxi_init_clocks(struct device_node *np)
- {
- /* Register factor clocks */
-@@ -629,6 +654,9 @@ static void __init sunxi_init_clocks(str
-
- /* Register gate clocks */
- of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
-+
-+ /* Enable core system clocks */
-+ sunxi_clock_protect();
- }
- CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
- CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
+++ /dev/null
-From 9dc8189536f4c59bb7ad8c736021cefc1488bf74 Mon Sep 17 00:00:00 2001
-From: "Victor N. Ramos Mello" <victornrm@gmail.com>
-Date: Fri, 18 Oct 2013 20:27:51 -0300
-Subject: [PATCH] drivers: clk: sunxi: Fix memory leakage in clk-sunxi.c
-
-Fix a possible memory leak in sun4i_osc_clk_setup().
-Moved clock-frequency check to save superfluous allocation.
-
-Signed-off-by: Victor N. Ramos Mello <victornrm@gmail.com>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clk/sunxi/clk-sunxi.c | 28 +++++++++++++++++-----------
- 1 file changed, 17 insertions(+), 11 deletions(-)
-
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -37,18 +37,16 @@ static void __init sun4i_osc_clk_setup(s
- const char *clk_name = node->name;
- u32 rate;
-
-+ if (of_property_read_u32(node, "clock-frequency", &rate))
-+ return;
-+
- /* allocate fixed-rate and gate clock structs */
- fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
- if (!fixed)
- return;
- gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
-- if (!gate) {
-- kfree(fixed);
-- return;
-- }
--
-- if (of_property_read_u32(node, "clock-frequency", &rate))
-- return;
-+ if (!gate)
-+ goto err_free_fixed;
-
- /* set up gate and fixed rate properties */
- gate->reg = of_iomap(node, 0);
-@@ -63,10 +61,18 @@ static void __init sun4i_osc_clk_setup(s
- &gate->hw, &clk_gate_ops,
- CLK_IS_ROOT);
-
-- if (!IS_ERR(clk)) {
-- of_clk_add_provider(node, of_clk_src_simple_get, clk);
-- clk_register_clkdev(clk, clk_name, NULL);
-- }
-+ if (IS_ERR(clk))
-+ goto err_free_gate;
-+
-+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
-+ clk_register_clkdev(clk, clk_name, NULL);
-+
-+ return;
-+
-+err_free_gate:
-+ kfree(gate);
-+err_free_fixed:
-+ kfree(fixed);
- }
- CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
-
+++ /dev/null
-From 8015cea648c452bbfe0fc820dcb1185beaeb8736 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Tue, 24 Sep 2013 11:07:43 +0300
-Subject: [PATCH] reset: Add Allwinner SoCs Reset Controller Driver
-
-The Allwinner A31 and most of the other Allwinner SoCs have an IP
-maintaining a few other IPs in the SoC in reset by default. Among these
-IPs are the A31's High Speed Timers, hence why we can't use the regular
-driver construct in every cases, and need to call the registering
-function directly during machine initialisation.
-
-Apart from this, the implementation is fairly straightforward, and could
-easily be moved to a generic MMIO-based reset controller driver if the
-need ever arise.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
----
- drivers/reset/Makefile | 1 +
- drivers/reset/reset-sunxi.c | 175 ++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 176 insertions(+)
- create mode 100644 drivers/reset/reset-sunxi.c
-
---- a/drivers/reset/Makefile
-+++ b/drivers/reset/Makefile
-@@ -1 +1,2 @@
- obj-$(CONFIG_RESET_CONTROLLER) += core.o
-+obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
---- /dev/null
-+++ b/drivers/reset/reset-sunxi.c
-@@ -0,0 +1,175 @@
-+/*
-+ * Allwinner SoCs Reset Controller driver
-+ *
-+ * Copyright 2013 Maxime Ripard
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset-controller.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+#include <linux/types.h>
-+
-+struct sunxi_reset_data {
-+ spinlock_t lock;
-+ void __iomem *membase;
-+ struct reset_controller_dev rcdev;
-+};
-+
-+static int sunxi_reset_assert(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ struct sunxi_reset_data *data = container_of(rcdev,
-+ struct sunxi_reset_data,
-+ rcdev);
-+ int bank = id / BITS_PER_LONG;
-+ int offset = id % BITS_PER_LONG;
-+ unsigned long flags;
-+ u32 reg;
-+
-+ spin_lock_irqsave(&data->lock, flags);
-+
-+ reg = readl(data->membase + (bank * 4));
-+ writel(reg & ~BIT(offset), data->membase + (bank * 4));
-+
-+ spin_unlock_irqrestore(&data->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int sunxi_reset_deassert(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ struct sunxi_reset_data *data = container_of(rcdev,
-+ struct sunxi_reset_data,
-+ rcdev);
-+ int bank = id / BITS_PER_LONG;
-+ int offset = id % BITS_PER_LONG;
-+ unsigned long flags;
-+ u32 reg;
-+
-+ spin_lock_irqsave(&data->lock, flags);
-+
-+ reg = readl(data->membase + (bank * 4));
-+ writel(reg | BIT(offset), data->membase + (bank * 4));
-+
-+ spin_unlock_irqrestore(&data->lock, flags);
-+
-+ return 0;
-+}
-+
-+static struct reset_control_ops sunxi_reset_ops = {
-+ .assert = sunxi_reset_assert,
-+ .deassert = sunxi_reset_deassert,
-+};
-+
-+static int sunxi_reset_init(struct device_node *np)
-+{
-+ struct sunxi_reset_data *data;
-+ struct resource res;
-+ resource_size_t size;
-+ int ret;
-+
-+ data = kzalloc(sizeof(*data), GFP_KERNEL);
-+ if (!data)
-+ return -ENOMEM;
-+
-+ ret = of_address_to_resource(np, 0, &res);
-+ if (ret)
-+ goto err_alloc;
-+
-+ size = resource_size(&res);
-+ if (!request_mem_region(res.start, size, np->name)) {
-+ ret = -EBUSY;
-+ goto err_alloc;
-+ }
-+
-+ data->membase = ioremap(res.start, size);
-+ if (!data->membase) {
-+ ret = -ENOMEM;
-+ goto err_alloc;
-+ }
-+
-+ data->rcdev.owner = THIS_MODULE;
-+ data->rcdev.nr_resets = size * 32;
-+ data->rcdev.ops = &sunxi_reset_ops;
-+ data->rcdev.of_node = np;
-+ reset_controller_register(&data->rcdev);
-+
-+ return 0;
-+
-+err_alloc:
-+ kfree(data);
-+ return ret;
-+};
-+
-+/*
-+ * These are the reset controller we need to initialize early on in
-+ * our system, before we can even think of using a regular device
-+ * driver for it.
-+ */
-+static const struct of_device_id sunxi_early_reset_dt_ids[] __initdata = {
-+ { .compatible = "allwinner,sun6i-a31-ahb1-reset", },
-+ { /* sentinel */ },
-+};
-+
-+void __init sun6i_reset_init(void)
-+{
-+ struct device_node *np;
-+
-+ for_each_matching_node(np, sunxi_early_reset_dt_ids)
-+ sunxi_reset_init(np);
-+}
-+
-+/*
-+ * And these are the controllers we can register through the regular
-+ * device model.
-+ */
-+static const struct of_device_id sunxi_reset_dt_ids[] = {
-+ { .compatible = "allwinner,sun6i-a31-clock-reset", },
-+ { /* sentinel */ },
-+};
-+MODULE_DEVICE_TABLE(of, sunxi_reset_dt_ids);
-+
-+static int sunxi_reset_probe(struct platform_device *pdev)
-+{
-+ return sunxi_reset_init(pdev->dev.of_node);
-+}
-+
-+static int sunxi_reset_remove(struct platform_device *pdev)
-+{
-+ struct sunxi_reset_data *data = platform_get_drvdata(pdev);
-+
-+ reset_controller_unregister(&data->rcdev);
-+ iounmap(data->membase);
-+ kfree(data);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver sunxi_reset_driver = {
-+ .probe = sunxi_reset_probe,
-+ .remove = sunxi_reset_remove,
-+ .driver = {
-+ .name = "sunxi-reset",
-+ .owner = THIS_MODULE,
-+ .of_match_table = sunxi_reset_dt_ids,
-+ },
-+};
-+module_platform_driver(sunxi_reset_driver);
-+
-+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
-+MODULE_DESCRIPTION("Allwinner SoCs Reset Controller Driver");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From 73f948fb57f489ed8252fa8480575c91f027200d Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Tue, 24 Sep 2013 11:09:55 +0300
-Subject: [PATCH] ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER
-
-The A31 has a reset controller, and we have to select this option to
-have access to the reset controller framework.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
----
- arch/arm/mach-sunxi/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/mach-sunxi/Kconfig
-+++ b/arch/arm/mach-sunxi/Kconfig
-@@ -1,5 +1,6 @@
- config ARCH_SUNXI
- bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
-+ select ARCH_HAS_RESET_CONTROLLER
- select ARCH_REQUIRE_GPIOLIB
- select ARM_GIC
- select CLKSRC_MMIO
+++ /dev/null
-From dae0e37c2df466f5eb6459d05f392e86b4236666 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 5 Oct 2013 14:53:48 +0200
-Subject: [PATCH] ARM: sunxi: Register the A31 reset IP in init_time
-
-The A31 has a reset IP that maintains a few other IPs in reset by
-default. Among these IPs are the UARTs, and most notably the timers. We
-thus need to register the reset driver before initializing the timers so
-that the reset timer can use the reset framework.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
----
- arch/arm/mach-sunxi/sunxi.c | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
---- a/arch/arm/mach-sunxi/sunxi.c
-+++ b/arch/arm/mach-sunxi/sunxi.c
-@@ -10,6 +10,8 @@
- * warranty of any kind, whether express or implied.
- */
-
-+#include <linux/clk-provider.h>
-+#include <linux/clocksource.h>
- #include <linux/delay.h>
- #include <linux/kernel.h>
- #include <linux/init.h>
-@@ -132,8 +134,17 @@ static const char * const sun6i_board_dt
- NULL,
- };
-
-+extern void __init sun6i_reset_init(void);
-+static void __init sun6i_timer_init(void)
-+{
-+ of_clk_init(NULL);
-+ sun6i_reset_init();
-+ clocksource_of_init();
-+}
-+
- DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
- .init_machine = sunxi_dt_init,
-+ .init_time = sun6i_timer_init,
- .dt_compat = sun6i_board_dt_compat,
- .restart = sun6i_restart,
- MACHINE_END
+++ /dev/null
-From 6f5002c91f35f6b171bc608b87b3f2b55451f32b Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 3 Nov 2013 10:30:13 +0100
-Subject: [PATCH] ARM: sun6i: Add SMP support for the Allwinner A31
-
-The A31 is a quad Cortex-A7. Add the logic to use the IPs used to
-control the CPU configuration and the CPU power so that we can bring up
-secondary CPUs at boot.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/mach-sunxi/Makefile | 1 +
- arch/arm/mach-sunxi/common.h | 19 +++++++
- arch/arm/mach-sunxi/headsmp.S | 9 +++
- arch/arm/mach-sunxi/platsmp.c | 124 ++++++++++++++++++++++++++++++++++++++++++
- arch/arm/mach-sunxi/sunxi.c | 3 +
- 5 files changed, 156 insertions(+)
- create mode 100644 arch/arm/mach-sunxi/common.h
- create mode 100644 arch/arm/mach-sunxi/headsmp.S
- create mode 100644 arch/arm/mach-sunxi/platsmp.c
-
---- a/arch/arm/mach-sunxi/Makefile
-+++ b/arch/arm/mach-sunxi/Makefile
-@@ -1 +1,2 @@
- obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
---- /dev/null
-+++ b/arch/arm/mach-sunxi/common.h
-@@ -0,0 +1,19 @@
-+/*
-+ * Core functions for Allwinner SoCs
-+ *
-+ * Copyright (C) 2013 Maxime Ripard
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#ifndef __ARCH_SUNXI_COMMON_H_
-+#define __ARCH_SUNXI_COMMON_H_
-+
-+void sun6i_secondary_startup(void);
-+extern struct smp_operations sun6i_smp_ops;
-+
-+#endif /* __ARCH_SUNXI_COMMON_H_ */
---- /dev/null
-+++ b/arch/arm/mach-sunxi/headsmp.S
-@@ -0,0 +1,9 @@
-+#include <linux/linkage.h>
-+#include <linux/init.h>
-+
-+ .section ".text.head", "ax"
-+
-+ENTRY(sun6i_secondary_startup)
-+ msr cpsr_fsxc, #0xd3
-+ b secondary_startup
-+ENDPROC(sun6i_secondary_startup)
---- /dev/null
-+++ b/arch/arm/mach-sunxi/platsmp.c
-@@ -0,0 +1,124 @@
-+/*
-+ * SMP support for Allwinner SoCs
-+ *
-+ * Copyright (C) 2013 Maxime Ripard
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * Based on code
-+ * Copyright (C) 2012-2013 Allwinner Ltd.
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/memory.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/smp.h>
-+
-+#include "common.h"
-+
-+#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
-+#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
-+#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
-+#define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08)
-+#define CPUCFG_GEN_CTRL_REG 0x184
-+#define CPUCFG_PRIVATE0_REG 0x1a4
-+#define CPUCFG_PRIVATE1_REG 0x1a8
-+#define CPUCFG_DBG_CTL0_REG 0x1e0
-+#define CPUCFG_DBG_CTL1_REG 0x1e4
-+
-+#define PRCM_CPU_PWROFF_REG 0x100
-+#define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140)
-+
-+static void __iomem *cpucfg_membase;
-+static void __iomem *prcm_membase;
-+
-+static DEFINE_SPINLOCK(cpu_lock);
-+
-+static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
-+{
-+ struct device_node *node;
-+
-+ node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
-+ if (!node) {
-+ pr_err("Missing A31 PRCM node in the device tree\n");
-+ return;
-+ }
-+
-+ prcm_membase = of_iomap(node, 0);
-+ if (!prcm_membase) {
-+ pr_err("Couldn't map A31 PRCM registers\n");
-+ return;
-+ }
-+
-+ node = of_find_compatible_node(NULL, NULL,
-+ "allwinner,sun6i-a31-cpuconfig");
-+ if (!node) {
-+ pr_err("Missing A31 CPU config node in the device tree\n");
-+ return;
-+ }
-+
-+ cpucfg_membase = of_iomap(node, 0);
-+ if (!cpucfg_membase)
-+ pr_err("Couldn't map A31 CPU config registers\n");
-+
-+}
-+
-+static int sun6i_smp_boot_secondary(unsigned int cpu,
-+ struct task_struct *idle)
-+{
-+ u32 reg;
-+ int i;
-+
-+ if (!(prcm_membase && cpucfg_membase))
-+ return -EFAULT;
-+
-+ spin_lock(&cpu_lock);
-+
-+ /* Set CPU boot address */
-+ writel(virt_to_phys(sun6i_secondary_startup),
-+ cpucfg_membase + CPUCFG_PRIVATE0_REG);
-+
-+ /* Assert the CPU core in reset */
-+ writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
-+
-+ /* Assert the L1 cache in reset */
-+ reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
-+ writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
-+
-+ /* Disable external debug access */
-+ reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
-+ writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
-+
-+ /* Power up the CPU */
-+ for (i = 0; i <= 8; i++)
-+ writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
-+ mdelay(10);
-+
-+ /* Clear CPU power-off gating */
-+ reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
-+ writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
-+ mdelay(1);
-+
-+ /* Deassert the CPU core reset */
-+ writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
-+
-+ /* Enable back the external debug accesses */
-+ reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
-+ writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
-+
-+ spin_unlock(&cpu_lock);
-+
-+ return 0;
-+}
-+
-+struct smp_operations sun6i_smp_ops __initdata = {
-+ .smp_prepare_cpus = sun6i_smp_prepare_cpus,
-+ .smp_boot_secondary = sun6i_smp_boot_secondary,
-+};
---- a/arch/arm/mach-sunxi/sunxi.c
-+++ b/arch/arm/mach-sunxi/sunxi.c
-@@ -25,6 +25,8 @@
- #include <asm/mach/map.h>
- #include <asm/system_misc.h>
-
-+#include "common.h"
-+
- #define SUN4I_WATCHDOG_CTRL_REG 0x00
- #define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
- #define SUN4I_WATCHDOG_MODE_REG 0x04
-@@ -147,6 +149,7 @@ DT_MACHINE_START(SUN6I_DT, "Allwinner su
- .init_time = sun6i_timer_init,
- .dt_compat = sun6i_board_dt_compat,
- .restart = sun6i_restart,
-+ .smp = smp_ops(sun6i_smp_ops),
- MACHINE_END
-
- static const char * const sun7i_board_dt_compat[] = {
+++ /dev/null
-From f88dc0623908b574d9dcdae8815ccd0829fc6828 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Tue, 24 Sep 2013 11:10:41 +0300
-Subject: [PATCH] ARM: sun6i: Add the reset controller to the DTSI
-
-The A31 has a reset controller IP that maintains a few other IPs in
-reset, among which we can find the UARTs, high speed timers or the I2C.
-Now that we have support for them, add the reset controllers to the DTSI.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -212,6 +212,24 @@
- };
- };
-
-+ ahb1_rst: reset@01c202c0 {
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun6i-a31-ahb1-reset";
-+ reg = <0x01c202c0 0xc>;
-+ };
-+
-+ apb1_rst: reset@01c202d0 {
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun6i-a31-clock-reset";
-+ reg = <0x01c202d0 0x4>;
-+ };
-+
-+ apb2_rst: reset@01c202d8 {
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun6i-a31-clock-reset";
-+ reg = <0x01c202d8 0x4>;
-+ };
-+
- timer@01c20c00 {
- compatible = "allwinner,sun4i-timer";
- reg = <0x01c20c00 0xa0>;
-@@ -235,6 +253,7 @@
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 16>;
-+ resets = <&apb2_rst 16>;
- status = "disabled";
- };
-
-@@ -245,6 +264,7 @@
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 17>;
-+ resets = <&apb2_rst 17>;
- status = "disabled";
- };
-
-@@ -255,6 +275,7 @@
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 18>;
-+ resets = <&apb2_rst 18>;
- status = "disabled";
- };
-
-@@ -265,6 +286,7 @@
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 19>;
-+ resets = <&apb2_rst 19>;
- status = "disabled";
- };
-
-@@ -275,6 +297,7 @@
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 20>;
-+ resets = <&apb2_rst 20>;
- status = "disabled";
- };
-
-@@ -285,6 +308,7 @@
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 21>;
-+ resets = <&apb2_rst 21>;
- status = "disabled";
- };
-
+++ /dev/null
-From abc12cd5c39556824cc9022db6eddc64e8e8dbe9 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Wed, 23 Oct 2013 17:54:39 +0100
-Subject: [PATCH] clockevent: sun4i: Fill the irq field in the clockevent
- structure
-
-The clock event structure irq field was not filled previously to the
-interrupt we're using.
-
-This was resulting in the timer not being used at all when using a
-configuration with SMP enabled on a system with several CPUs, and with
-the cpumask set to the cpu_possible_mask.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clocksource/sun4i_timer.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/clocksource/sun4i_timer.c
-+++ b/drivers/clocksource/sun4i_timer.c
-@@ -191,6 +191,7 @@ static void __init sun4i_timer_init(stru
- writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
-
- sun4i_clockevent.cpumask = cpumask_of(0);
-+ sun4i_clockevent.irq = irq;
-
- clockevents_config_and_register(&sun4i_clockevent, rate,
- TIMER_SYNC_TICKS, 0xffffffff);
+++ /dev/null
-From 64a9fa131380f9cef9328d0cf9f2d49a538e6dd2 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Wed, 9 Oct 2013 22:44:56 +0200
-Subject: [PATCH] clocksource: sun4i: change CPU mask to cpu_possible_mask
-
-The interrupt for the timer is a shared processor interrupt, so any CPU
-found in the system can handle it. Switch to our cpumask to
-cpu_possible_mask instead of cpumask_of(0).
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clocksource/sun4i_timer.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clocksource/sun4i_timer.c
-+++ b/drivers/clocksource/sun4i_timer.c
-@@ -190,7 +190,7 @@ static void __init sun4i_timer_init(stru
- val = readl(timer_base + TIMER_IRQ_EN_REG);
- writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
-
-- sun4i_clockevent.cpumask = cpumask_of(0);
-+ sun4i_clockevent.cpumask = cpu_possible_mask;
- sun4i_clockevent.irq = irq;
-
- clockevents_config_and_register(&sun4i_clockevent, rate,
+++ /dev/null
-From a4eb936767bd6a63d54734b9ce48932609ce58eb Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:01:48 +0100
-Subject: [PATCH] clocksource: sun4i: Increase a bit the clock event and
- sources rating
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We want to keep this driver as the default provider of the clock events
-and source, yet some other driver might fit in the "desired" category of
-ratings. Hence, we need to increase a bit the rating so that we can have
-more flexibility in the ratings we choose.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Tested-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/clocksource/sun4i_timer.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/clocksource/sun4i_timer.c
-+++ b/drivers/clocksource/sun4i_timer.c
-@@ -114,7 +114,7 @@ static int sun4i_clkevt_next_event(unsig
-
- static struct clock_event_device sun4i_clockevent = {
- .name = "sun4i_tick",
-- .rating = 300,
-+ .rating = 350,
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .set_mode = sun4i_clkevt_mode,
- .set_next_event = sun4i_clkevt_next_event,
-@@ -172,7 +172,7 @@ static void __init sun4i_timer_init(stru
-
- setup_sched_clock(sun4i_timer_sched_read, 32, rate);
- clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
-- rate, 300, 32, clocksource_mmio_readl_down);
-+ rate, 350, 32, clocksource_mmio_readl_down);
-
- ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
-
+++ /dev/null
-From 9212bc4a3752e9a4db2f73afd99278eb28e5dcff Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:32 -0300
-Subject: [PATCH] clk: sunxi: register factors clocks behind composite
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit reworks factors clock registration to be done behind a
-composite clock. This allows us to additionally add a gate, mux or
-divisors, as it will be needed by some future PLLs.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clk/sunxi/clk-factors.c | 63 +------------------------------------
- drivers/clk/sunxi/clk-factors.h | 16 +++++-----
- drivers/clk/sunxi/clk-sunxi.c | 70 ++++++++++++++++++++++++++++++++++++++---
- 3 files changed, 76 insertions(+), 73 deletions(-)
-
---- a/drivers/clk/sunxi/clk-factors.c
-+++ b/drivers/clk/sunxi/clk-factors.c
-@@ -30,14 +30,6 @@
- * parent - fixed parent. No clk_set_parent support
- */
-
--struct clk_factors {
-- struct clk_hw hw;
-- void __iomem *reg;
-- struct clk_factors_config *config;
-- void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
-- spinlock_t *lock;
--};
--
- #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
-
- #define SETMASK(len, pos) (((1U << (len)) - 1) << (pos))
-@@ -120,61 +112,8 @@ static int clk_factors_set_rate(struct c
- return 0;
- }
-
--static const struct clk_ops clk_factors_ops = {
-+const struct clk_ops clk_factors_ops = {
- .recalc_rate = clk_factors_recalc_rate,
- .round_rate = clk_factors_round_rate,
- .set_rate = clk_factors_set_rate,
- };
--
--/**
-- * clk_register_factors - register a factors clock with
-- * the clock framework
-- * @dev: device registering this clock
-- * @name: name of this clock
-- * @parent_name: name of clock's parent
-- * @flags: framework-specific flags
-- * @reg: register address to adjust factors
-- * @config: shift and width of factors n, k, m and p
-- * @get_factors: function to calculate the factors for a given frequency
-- * @lock: shared register lock for this clock
-- */
--struct clk *clk_register_factors(struct device *dev, const char *name,
-- const char *parent_name,
-- unsigned long flags, void __iomem *reg,
-- struct clk_factors_config *config,
-- void (*get_factors)(u32 *rate, u32 parent,
-- u8 *n, u8 *k, u8 *m, u8 *p),
-- spinlock_t *lock)
--{
-- struct clk_factors *factors;
-- struct clk *clk;
-- struct clk_init_data init;
--
-- /* allocate the factors */
-- factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
-- if (!factors) {
-- pr_err("%s: could not allocate factors clk\n", __func__);
-- return ERR_PTR(-ENOMEM);
-- }
--
-- init.name = name;
-- init.ops = &clk_factors_ops;
-- init.flags = flags;
-- init.parent_names = (parent_name ? &parent_name : NULL);
-- init.num_parents = (parent_name ? 1 : 0);
--
-- /* struct clk_factors assignments */
-- factors->reg = reg;
-- factors->config = config;
-- factors->lock = lock;
-- factors->hw.init = &init;
-- factors->get_factors = get_factors;
--
-- /* register the clock */
-- clk = clk_register(dev, &factors->hw);
--
-- if (IS_ERR(clk))
-- kfree(factors);
--
-- return clk;
--}
---- a/drivers/clk/sunxi/clk-factors.h
-+++ b/drivers/clk/sunxi/clk-factors.h
-@@ -17,11 +17,13 @@ struct clk_factors_config {
- u8 pwidth;
- };
-
--struct clk *clk_register_factors(struct device *dev, const char *name,
-- const char *parent_name,
-- unsigned long flags, void __iomem *reg,
-- struct clk_factors_config *config,
-- void (*get_factors) (u32 *rate, u32 parent_rate,
-- u8 *n, u8 *k, u8 *m, u8 *p),
-- spinlock_t *lock);
-+struct clk_factors {
-+ struct clk_hw hw;
-+ void __iomem *reg;
-+ struct clk_factors_config *config;
-+ void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
-+ spinlock_t *lock;
-+};
-+
-+extern const struct clk_ops clk_factors_ops;
- #endif
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -23,6 +23,9 @@
-
- static DEFINE_SPINLOCK(clk_lock);
-
-+/* Maximum number of parents our clocks have */
-+#define SUNXI_MAX_PARENTS 5
-+
- /**
- * sun4i_osc_clk_setup() - Setup function for gatable oscillator
- */
-@@ -261,7 +264,11 @@ static void sun4i_get_apb1_factors(u32 *
- * sunxi_factors_clk_setup() - Setup function for factor clocks
- */
-
-+#define SUNXI_FACTORS_MUX_MASK 0x3
-+
- struct factors_data {
-+ int enable;
-+ int mux;
- struct clk_factors_config *table;
- void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
- };
-@@ -312,16 +319,71 @@ static void __init sunxi_factors_clk_set
- struct factors_data *data)
- {
- struct clk *clk;
-+ struct clk_factors *factors;
-+ struct clk_gate *gate = NULL;
-+ struct clk_mux *mux = NULL;
-+ struct clk_hw *gate_hw = NULL;
-+ struct clk_hw *mux_hw = NULL;
- const char *clk_name = node->name;
-- const char *parent;
-+ const char *parents[SUNXI_MAX_PARENTS];
- void *reg;
-+ int i = 0;
-
- reg = of_iomap(node, 0);
-
-- parent = of_clk_get_parent_name(node, 0);
-+ /* if we have a mux, we will have >1 parents */
-+ while (i < SUNXI_MAX_PARENTS &&
-+ (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
-+ i++;
-+
-+ factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
-+ if (!factors)
-+ return;
-+
-+ /* Add a gate if this factor clock can be gated */
-+ if (data->enable) {
-+ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
-+ if (!gate) {
-+ kfree(factors);
-+ return;
-+ }
-+
-+ /* set up gate properties */
-+ gate->reg = reg;
-+ gate->bit_idx = data->enable;
-+ gate->lock = &clk_lock;
-+ gate_hw = &gate->hw;
-+ }
-+
-+ /* Add a mux if this factor clock can be muxed */
-+ if (data->mux) {
-+ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
-+ if (!mux) {
-+ kfree(factors);
-+ kfree(gate);
-+ return;
-+ }
-+
-+ /* set up gate properties */
-+ mux->reg = reg;
-+ mux->shift = data->mux;
-+ mux->mask = SUNXI_FACTORS_MUX_MASK;
-+ mux->lock = &clk_lock;
-+ mux_hw = &mux->hw;
-+ }
-
-- clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
-- data->table, data->getter, &clk_lock);
-+ /* set up factors properties */
-+ factors->reg = reg;
-+ factors->config = data->table;
-+ factors->get_factors = data->getter;
-+ factors->lock = &clk_lock;
-+
-+ clk = clk_register_composite(NULL, clk_name,
-+ parents, i,
-+ mux_hw, &clk_mux_ops,
-+ &factors->hw, &clk_factors_ops,
-+ gate_hw, &clk_gate_ops,
-+ i ? 0 : CLK_IS_ROOT);
-
- if (!IS_ERR(clk)) {
- of_clk_add_provider(node, of_clk_src_simple_get, clk);
+++ /dev/null
-From 33574f94b0d4d8bc8af732fbcb4f911c3dd8c96b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:33 -0300
-Subject: [PATCH] clk: sunxi: clean the magic number of mux parents
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This was pointed out during the review of the factor patches. Let's
-indicate what does that magic 5 mean.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -420,13 +420,14 @@ static void __init sunxi_mux_clk_setup(s
- {
- struct clk *clk;
- const char *clk_name = node->name;
-- const char *parents[5];
-+ const char *parents[SUNXI_MAX_PARENTS];
- void *reg;
- int i = 0;
-
- reg = of_iomap(node, 0);
-
-- while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
-+ while (i < SUNXI_MAX_PARENTS &&
-+ (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
- i++;
-
- clk = clk_register_mux(NULL, clk_name, parents, i,
+++ /dev/null
-From 3d56b9643ff9fff3c7ceb095e03f4ab7e149b9ce Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:34 -0300
-Subject: [PATCH] clk: sunxi: add gating support to PLL1
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds gating support to PLL1 on the clock driver. This makes
-the PLL1 implementation fully compatible with PLL4 as well.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Mike Turquette <mturquette@linaro.org>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 2 +-
- drivers/clk/sunxi/clk-sunxi.c | 2 ++
- 2 files changed, 3 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -7,7 +7,7 @@ This binding uses the common clock bindi
- Required properties:
- - compatible : shall be one of the following:
- "allwinner,sun4i-osc-clk" - for a gatable oscillator
-- "allwinner,sun4i-pll1-clk" - for the main PLL clock
-+ "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
- "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
- "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
- "allwinner,sun4i-axi-clk" - for the AXI clock
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -301,11 +301,13 @@ static struct clk_factors_config sun4i_a
- };
-
- static const struct factors_data sun4i_pll1_data __initconst = {
-+ .enable = 31,
- .table = &sun4i_pll1_config,
- .getter = sun4i_get_pll1_factors,
- };
-
- static const struct factors_data sun6i_a31_pll1_data __initconst = {
-+ .enable = 31,
- .table = &sun6i_a31_pll1_config,
- .getter = sun6i_a31_get_pll1_factors,
- };
+++ /dev/null
-From ff0b5fdb65bc7f10af7e83bb0919cb6bec2dc624 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:35 -0300
-Subject: [PATCH] ARM: sunxi: add PLL4 support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
-device trees. PLL4 is compatible with PLL1.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++++++
- arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++
- 4 files changed, 28 insertions(+)
-
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -66,6 +66,13 @@
- clocks = <&osc24M>;
- };
-
-+ pll4: pll4@01c20018 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-pll1-clk";
-+ reg = <0x01c20018 0x4>;
-+ clocks = <&osc24M>;
-+ };
-+
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -63,6 +63,13 @@
- clocks = <&osc24M>;
- };
-
-+ pll4: pll4@01c20018 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-pll1-clk";
-+ reg = <0x01c20018 0x4>;
-+ clocks = <&osc24M>;
-+ };
-+
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -67,6 +67,13 @@
- clocks = <&osc24M>;
- };
-
-+ pll4: pll4@01c20018 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-pll1-clk";
-+ reg = <0x01c20018 0x4>;
-+ clocks = <&osc24M>;
-+ };
-+
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -62,6 +62,13 @@
- clocks = <&osc24M>;
- };
-
-+ pll4: pll4@01c20018 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-pll1-clk";
-+ reg = <0x01c20018 0x4>;
-+ clocks = <&osc24M>;
-+ };
-+
- /*
- * This is a dummy clock, to be used as placeholder on
- * other mux clocks when a specific parent clock is not
+++ /dev/null
-From 8a3282a0a185108e37e7a48437b58d956ff56f4a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:36 -0300
-Subject: [PATCH] clk: sunxi: make factors_clk_setup return the clock it
- registers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We will be needing this to register a factor clock as parent with leaf
-divisors on a single call.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Mike Turquette <mturquette@linaro.org>
----
- drivers/clk/sunxi/clk-sunxi.c | 15 ++++++++-------
- 1 file changed, 8 insertions(+), 7 deletions(-)
-
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -317,8 +317,8 @@ static const struct factors_data sun4i_a
- .getter = sun4i_get_apb1_factors,
- };
-
--static void __init sunxi_factors_clk_setup(struct device_node *node,
-- struct factors_data *data)
-+static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
-+ const struct factors_data *data)
- {
- struct clk *clk;
- struct clk_factors *factors;
-@@ -340,14 +340,14 @@ static void __init sunxi_factors_clk_set
-
- factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
- if (!factors)
-- return;
-+ return NULL;
-
- /* Add a gate if this factor clock can be gated */
- if (data->enable) {
- gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
- if (!gate) {
- kfree(factors);
-- return;
-+ return NULL;
- }
-
- /* set up gate properties */
-@@ -363,7 +363,7 @@ static void __init sunxi_factors_clk_set
- if (!mux) {
- kfree(factors);
- kfree(gate);
-- return;
-+ return NULL;
- }
-
- /* set up gate properties */
-@@ -384,13 +384,14 @@ static void __init sunxi_factors_clk_set
- parents, i,
- mux_hw, &clk_mux_ops,
- &factors->hw, &clk_factors_ops,
-- gate_hw, &clk_gate_ops,
-- i ? 0 : CLK_IS_ROOT);
-+ gate_hw, &clk_gate_ops, 0);
-
- if (!IS_ERR(clk)) {
- of_clk_add_provider(node, of_clk_src_simple_get, clk);
- clk_register_clkdev(clk, clk_name, NULL);
- }
-+
-+ return clk;
- }
-
-
+++ /dev/null
-From 655893a197a5134a371a5c6b579f1bbce03ab413 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:37 -0300
-Subject: [PATCH] clk: sunxi: add PLL5 and PLL6 support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit implements PLL5 and PLL6 support on the sunxi clock driver.
-These PLLs use a similar factor clock, but differ on their outputs.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Mike Turquette <mturquette@linaro.org>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 2 +
- drivers/clk/sunxi/clk-sunxi.c | 230 ++++++++++++++++++++++
- 2 files changed, 232 insertions(+)
-
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -9,6 +9,8 @@ Required properties:
- "allwinner,sun4i-osc-clk" - for a gatable oscillator
- "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
- "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
-+ "allwinner,sun4i-pll5-clk" - for the PLL5 clock
-+ "allwinner,sun4i-pll6-clk" - for the PLL6 clock
- "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
- "allwinner,sun4i-axi-clk" - for the AXI clock
- "allwinner,sun4i-axi-gates-clk" - for the AXI gates
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -218,6 +218,40 @@ static void sun6i_a31_get_pll1_factors(u
- }
-
- /**
-+ * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
-+ * PLL5 rate is calculated as follows
-+ * rate = parent_rate * n * (k + 1)
-+ * parent_rate is always 24Mhz
-+ */
-+
-+static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
-+ u8 *n, u8 *k, u8 *m, u8 *p)
-+{
-+ u8 div;
-+
-+ /* Normalize value to a parent_rate multiple (24M) */
-+ div = *freq / parent_rate;
-+ *freq = parent_rate * div;
-+
-+ /* we were called to round the frequency, we can now return */
-+ if (n == NULL)
-+ return;
-+
-+ if (div < 31)
-+ *k = 0;
-+ else if (div / 2 < 31)
-+ *k = 1;
-+ else if (div / 3 < 31)
-+ *k = 2;
-+ else
-+ *k = 3;
-+
-+ *n = DIV_ROUND_UP(div, (*k+1));
-+}
-+
-+
-+
-+/**
- * sun4i_get_apb1_factors() - calculates m, p factors for APB1
- * APB1 rate is calculated as follows
- * rate = (parent_rate >> p) / (m + 1);
-@@ -293,6 +327,13 @@ static struct clk_factors_config sun6i_a
- .mwidth = 2,
- };
-
-+static struct clk_factors_config sun4i_pll5_config = {
-+ .nshift = 8,
-+ .nwidth = 5,
-+ .kshift = 4,
-+ .kwidth = 2,
-+};
-+
- static struct clk_factors_config sun4i_apb1_config = {
- .mshift = 0,
- .mwidth = 5,
-@@ -312,6 +353,12 @@ static const struct factors_data sun6i_a
- .getter = sun6i_a31_get_pll1_factors,
- };
-
-+static const struct factors_data sun4i_pll5_data __initconst = {
-+ .enable = 31,
-+ .table = &sun4i_pll5_config,
-+ .getter = sun4i_get_pll5_factors,
-+};
-+
- static const struct factors_data sun4i_apb1_data __initconst = {
- .table = &sun4i_apb1_config,
- .getter = sun4i_get_apb1_factors,
-@@ -627,6 +674,179 @@ static void __init sunxi_gates_clk_setup
- of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- }
-
-+
-+
-+/**
-+ * sunxi_divs_clk_setup() helper data
-+ */
-+
-+#define SUNXI_DIVS_MAX_QTY 2
-+#define SUNXI_DIVISOR_WIDTH 2
-+
-+struct divs_data {
-+ const struct factors_data *factors; /* data for the factor clock */
-+ struct {
-+ u8 fixed; /* is it a fixed divisor? if not... */
-+ struct clk_div_table *table; /* is it a table based divisor? */
-+ u8 shift; /* otherwise it's a normal divisor with this shift */
-+ u8 pow; /* is it power-of-two based? */
-+ u8 gate; /* is it independently gateable? */
-+ } div[SUNXI_DIVS_MAX_QTY];
-+};
-+
-+static struct clk_div_table pll6_sata_tbl[] = {
-+ { .val = 0, .div = 6, },
-+ { .val = 1, .div = 12, },
-+ { .val = 2, .div = 18, },
-+ { .val = 3, .div = 24, },
-+ { } /* sentinel */
-+};
-+
-+static const struct divs_data pll5_divs_data __initconst = {
-+ .factors = &sun4i_pll5_data,
-+ .div = {
-+ { .shift = 0, .pow = 0, }, /* M, DDR */
-+ { .shift = 16, .pow = 1, }, /* P, other */
-+ }
-+};
-+
-+static const struct divs_data pll6_divs_data __initconst = {
-+ .factors = &sun4i_pll5_data,
-+ .div = {
-+ { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
-+ { .fixed = 2 }, /* P, other */
-+ }
-+};
-+
-+/**
-+ * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
-+ *
-+ * These clocks look something like this
-+ * ________________________
-+ * | ___divisor 1---|----> to consumer
-+ * parent >--| pll___/___divisor 2---|----> to consumer
-+ * | \_______________|____> to consumer
-+ * |________________________|
-+ */
-+
-+static void __init sunxi_divs_clk_setup(struct device_node *node,
-+ struct divs_data *data)
-+{
-+ struct clk_onecell_data *clk_data;
-+ const char *parent = node->name;
-+ const char *clk_name;
-+ struct clk **clks, *pclk;
-+ struct clk_hw *gate_hw, *rate_hw;
-+ const struct clk_ops *rate_ops;
-+ struct clk_gate *gate = NULL;
-+ struct clk_fixed_factor *fix_factor;
-+ struct clk_divider *divider;
-+ void *reg;
-+ int i = 0;
-+ int flags, clkflags;
-+
-+ /* Set up factor clock that we will be dividing */
-+ pclk = sunxi_factors_clk_setup(node, data->factors);
-+
-+ reg = of_iomap(node, 0);
-+
-+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
-+ if (!clk_data)
-+ return;
-+
-+ clks = kzalloc(SUNXI_DIVS_MAX_QTY * sizeof(struct clk *), GFP_KERNEL);
-+ if (!clks)
-+ goto free_clkdata;
-+
-+ clk_data->clks = clks;
-+
-+ /* It's not a good idea to have automatic reparenting changing
-+ * our RAM clock! */
-+ clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
-+
-+ for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
-+ if (of_property_read_string_index(node, "clock-output-names",
-+ i, &clk_name) != 0)
-+ break;
-+
-+ gate_hw = NULL;
-+ rate_hw = NULL;
-+ rate_ops = NULL;
-+
-+ /* If this leaf clock can be gated, create a gate */
-+ if (data->div[i].gate) {
-+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
-+ if (!gate)
-+ goto free_clks;
-+
-+ gate->reg = reg;
-+ gate->bit_idx = data->div[i].gate;
-+ gate->lock = &clk_lock;
-+
-+ gate_hw = &gate->hw;
-+ }
-+
-+ /* Leaves can be fixed or configurable divisors */
-+ if (data->div[i].fixed) {
-+ fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
-+ if (!fix_factor)
-+ goto free_gate;
-+
-+ fix_factor->mult = 1;
-+ fix_factor->div = data->div[i].fixed;
-+
-+ rate_hw = &fix_factor->hw;
-+ rate_ops = &clk_fixed_factor_ops;
-+ } else {
-+ divider = kzalloc(sizeof(*divider), GFP_KERNEL);
-+ if (!divider)
-+ goto free_gate;
-+
-+ flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
-+
-+ divider->reg = reg;
-+ divider->shift = data->div[i].shift;
-+ divider->width = SUNXI_DIVISOR_WIDTH;
-+ divider->flags = flags;
-+ divider->lock = &clk_lock;
-+ divider->table = data->div[i].table;
-+
-+ rate_hw = ÷r->hw;
-+ rate_ops = &clk_divider_ops;
-+ }
-+
-+ /* Wrap the (potential) gate and the divisor on a composite
-+ * clock to unify them */
-+ clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
-+ NULL, NULL,
-+ rate_hw, rate_ops,
-+ gate_hw, &clk_gate_ops,
-+ clkflags);
-+
-+ WARN_ON(IS_ERR(clk_data->clks[i]));
-+ clk_register_clkdev(clks[i], clk_name, NULL);
-+ }
-+
-+ /* The last clock available on the getter is the parent */
-+ clks[i++] = pclk;
-+
-+ /* Adjust to the real max */
-+ clk_data->clk_num = i;
-+
-+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+ return;
-+
-+free_gate:
-+ kfree(gate);
-+free_clks:
-+ kfree(clks);
-+free_clkdata:
-+ kfree(clk_data);
-+}
-+
-+
-+
- /* Matches for factors clocks */
- static const struct of_device_id clk_factors_match[] __initconst = {
- {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
-@@ -644,6 +864,13 @@ static const struct of_device_id clk_div
- {}
- };
-
-+/* Matches for divided outputs */
-+static const struct of_device_id clk_divs_match[] __initconst = {
-+ {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,},
-+ {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,},
-+ {}
-+};
-+
- /* Matches for mux clocks */
- static const struct of_device_id clk_mux_match[] __initconst = {
- {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
-@@ -721,6 +948,9 @@ static void __init sunxi_init_clocks(str
- /* Register divider clocks */
- of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
-
-+ /* Register divided output clocks */
-+ of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
-+
- /* Register mux clocks */
- of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
-
+++ /dev/null
-From 6d3ca59232090bff1b5e1abfd3417a3859e47425 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:38 -0300
-Subject: [PATCH] ARM: sunxi: add PLL5 and PLL6 support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
-device trees.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 19 +++++++++++++++++--
- arch/arm/boot/dts/sun5i-a10s.dtsi | 19 +++++++++++++++++--
- arch/arm/boot/dts/sun5i-a13.dtsi | 19 +++++++++++++++++--
- arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++------------
- 4 files changed, 67 insertions(+), 18 deletions(-)
-
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -73,6 +73,22 @@
- clocks = <&osc24M>;
- };
-
-+ pll5: pll5@01c20020 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll5-clk";
-+ reg = <0x01c20020 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll5_ddr", "pll5_other";
-+ };
-+
-+ pll6: pll6@01c20028 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll6-clk";
-+ reg = <0x01c20028 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
-+ };
-+
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
-@@ -138,12 +154,11 @@
- "apb0_ir1", "apb0_keypad";
- };
-
-- /* dummy is pll62 */
- apb1_mux: apb1_mux@01c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
-- clocks = <&osc24M>, <&dummy>, <&osc32k>;
-+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- };
-
- apb1: apb1@01c20058 {
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -70,6 +70,22 @@
- clocks = <&osc24M>;
- };
-
-+ pll5: pll5@01c20020 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll5-clk";
-+ reg = <0x01c20020 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll5_ddr", "pll5_other";
-+ };
-+
-+ pll6: pll6@01c20028 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll6-clk";
-+ reg = <0x01c20028 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
-+ };
-+
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
-@@ -130,12 +146,11 @@
- "apb0_ir", "apb0_keypad";
- };
-
-- /* dummy is pll62 */
- apb1_mux: apb1_mux@01c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
-- clocks = <&osc24M>, <&dummy>, <&osc32k>;
-+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- };
-
- apb1: apb1@01c20058 {
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -74,6 +74,22 @@
- clocks = <&osc24M>;
- };
-
-+ pll5: pll5@01c20020 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll5-clk";
-+ reg = <0x01c20020 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll5_ddr", "pll5_other";
-+ };
-+
-+ pll6: pll6@01c20028 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll6-clk";
-+ reg = <0x01c20028 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
-+ };
-+
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
-@@ -132,12 +148,11 @@
- clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
- };
-
-- /* dummy is pll6 */
- apb1_mux: apb1_mux@01c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
-- clocks = <&osc24M>, <&dummy>, <&osc32k>;
-+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- };
-
- apb1: apb1@01c20058 {
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -69,23 +69,27 @@
- clocks = <&osc24M>;
- };
-
-- /*
-- * This is a dummy clock, to be used as placeholder on
-- * other mux clocks when a specific parent clock is not
-- * yet implemented. It should be dropped when the driver
-- * is complete.
-- */
-- pll6: pll6 {
-- #clock-cells = <0>;
-- compatible = "fixed-clock";
-- clock-frequency = <0>;
-+ pll5: pll5@01c20020 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll5-clk";
-+ reg = <0x01c20020 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll5_ddr", "pll5_other";
-+ };
-+
-+ pll6: pll6@01c20028 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll6-clk";
-+ reg = <0x01c20028 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
- };
-
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-cpu-clk";
- reg = <0x01c20054 0x4>;
-- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
-+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
- };
-
- axi: axi@01c20054 {
-@@ -144,7 +148,7 @@
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
-- clocks = <&osc24M>, <&pll6>, <&osc32k>;
-+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- };
-
- apb1: apb1@01c20058 {
+++ /dev/null
-From bdc913d1ef5143a8728ae414fcb90f9ed87a58da Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:39 -0300
-Subject: [PATCH] clk: sunxi: mod0 support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit implements support for the "module 0" type of clocks, as
-used by MMC, IR, NAND, SATA and other components.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Mike Turquette <mturquette@linaro.org>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 5 +-
- drivers/clk/sunxi/clk-sunxi.c | 57 +++++++++++++++++++++++
- 2 files changed, 61 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -35,10 +35,13 @@ Required properties:
- "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
- "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
- "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
-+ "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
-
- Required properties for all clocks:
- - reg : shall be the control register address for the clock.
--- clocks : shall be the input parent clock(s) phandle for the clock
-+- clocks : shall be the input parent clock(s) phandle for the clock. For
-+ multiplexed clocks, the list order must match the hardware
-+ programming order.
- - #clock-cells : from common clock binding; shall be set to 0 except for
- "allwinner,*-gates-clk" where it shall be set to 1
-
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -295,6 +295,47 @@ static void sun4i_get_apb1_factors(u32 *
-
-
- /**
-+ * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
-+ * MMC rate is calculated as follows
-+ * rate = (parent_rate >> p) / (m + 1);
-+ */
-+
-+static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
-+ u8 *n, u8 *k, u8 *m, u8 *p)
-+{
-+ u8 div, calcm, calcp;
-+
-+ /* These clocks can only divide, so we will never be able to achieve
-+ * frequencies higher than the parent frequency */
-+ if (*freq > parent_rate)
-+ *freq = parent_rate;
-+
-+ div = parent_rate / *freq;
-+
-+ if (div < 16)
-+ calcp = 0;
-+ else if (div / 2 < 16)
-+ calcp = 1;
-+ else if (div / 4 < 16)
-+ calcp = 2;
-+ else
-+ calcp = 3;
-+
-+ calcm = DIV_ROUND_UP(div, 1 << calcp);
-+
-+ *freq = (parent_rate >> calcp) / calcm;
-+
-+ /* we were called to round the frequency, we can now return */
-+ if (n == NULL)
-+ return;
-+
-+ *m = calcm - 1;
-+ *p = calcp;
-+}
-+
-+
-+
-+/**
- * sunxi_factors_clk_setup() - Setup function for factor clocks
- */
-
-@@ -341,6 +382,14 @@ static struct clk_factors_config sun4i_a
- .pwidth = 2,
- };
-
-+/* user manual says "n" but it's really "p" */
-+static struct clk_factors_config sun4i_mod0_config = {
-+ .mshift = 0,
-+ .mwidth = 4,
-+ .pshift = 16,
-+ .pwidth = 2,
-+};
-+
- static const struct factors_data sun4i_pll1_data __initconst = {
- .enable = 31,
- .table = &sun4i_pll1_config,
-@@ -364,6 +413,13 @@ static const struct factors_data sun4i_a
- .getter = sun4i_get_apb1_factors,
- };
-
-+static const struct factors_data sun4i_mod0_data __initconst = {
-+ .enable = 31,
-+ .mux = 24,
-+ .table = &sun4i_mod0_config,
-+ .getter = sun4i_get_mod0_factors,
-+};
-+
- static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
- const struct factors_data *data)
- {
-@@ -852,6 +908,7 @@ static const struct of_device_id clk_fac
- {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
- {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
- {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
-+ {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
- {}
- };
-
+++ /dev/null
-From 7d47b009bf287bf5e0817f47c40e32b7ec0e8151 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:40 -0300
-Subject: [PATCH] clk: sunxi: support better factor DT nodes
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The DT nodes should look like
-
- abc_clk: clk@deadbeef {
- ...
- clock-output-names = "abc";
- }
-
-But our old DT nodes look like
-
- abc: abc@deadbeef {
- ...
- }
-
-So, let's support both formats, until we can transition everything
-to the new, correct one.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -441,6 +441,15 @@ static struct clk * __init sunxi_factors
- (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
- i++;
-
-+ /* Nodes should be providing the name via clock-output-names
-+ * but originally our dts didn't, and so we used node->name.
-+ * The new, better nodes look like clk@deadbeef, so we pull the
-+ * name just in this case */
-+ if (!strcmp("clk", clk_name)) {
-+ of_property_read_string_index(node, "clock-output-names",
-+ 0, &clk_name);
-+ }
-+
- factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
- if (!factors)
- return NULL;
+++ /dev/null
-From dda274b6f95902b619af1fb14f26e231bb420371 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:41 -0300
-Subject: [PATCH] ARM: sun4i: dt: mod0 clocks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds all the mod0 clocks present on sun4i to its device tree
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 120 +++++++++++++++++++++++++++++++++++++++
- 1 file changed, 120 insertions(+)
-
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -180,6 +180,126 @@
- "apb1_uart4", "apb1_uart5", "apb1_uart6",
- "apb1_uart7";
- };
-+
-+ nand_clk: clk@01c20080 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20080 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "nand";
-+ };
-+
-+ ms_clk: clk@01c20084 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20084 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ms";
-+ };
-+
-+ mmc0_clk: clk@01c20088 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20088 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc0";
-+ };
-+
-+ mmc1_clk: clk@01c2008c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2008c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc1";
-+ };
-+
-+ mmc2_clk: clk@01c20090 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20090 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc2";
-+ };
-+
-+ mmc3_clk: clk@01c20094 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20094 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc3";
-+ };
-+
-+ ts_clk: clk@01c20098 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20098 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ts";
-+ };
-+
-+ ss_clk: clk@01c2009c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2009c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ss";
-+ };
-+
-+ spi0_clk: clk@01c200a0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi0";
-+ };
-+
-+ spi1_clk: clk@01c200a4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi1";
-+ };
-+
-+ spi2_clk: clk@01c200a8 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a8 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi2";
-+ };
-+
-+ pata_clk: clk@01c200ac {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200ac 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "pata";
-+ };
-+
-+ ir0_clk: clk@01c200b0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200b0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ir0";
-+ };
-+
-+ ir1_clk: clk@01c200b4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200b4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ir1";
-+ };
-+
-+ spi3_clk: clk@01c200d4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200d4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi3";
-+ };
- };
-
- soc@01c00000 {
+++ /dev/null
-From 9a8d3f21c94099a2bcd79ac1684cc8020fd98df2 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:42 -0300
-Subject: [PATCH] ARM: sun5i: dt: mod0 clocks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds all the mod0 clocks available on A10 and A13. The list
-has been constructed by looking at the Allwinner code release for A10S
-and A13.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 88 +++++++++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 88 +++++++++++++++++++++++++++++++++++++++
- 2 files changed, 176 insertions(+)
-
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -169,6 +169,94 @@
- "apb1_i2c2", "apb1_uart0", "apb1_uart1",
- "apb1_uart2", "apb1_uart3";
- };
-+
-+ nand_clk: clk@01c20080 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20080 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "nand";
-+ };
-+
-+ ms_clk: clk@01c20084 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20084 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ms";
-+ };
-+
-+ mmc0_clk: clk@01c20088 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20088 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc0";
-+ };
-+
-+ mmc1_clk: clk@01c2008c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2008c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc1";
-+ };
-+
-+ mmc2_clk: clk@01c20090 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20090 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc2";
-+ };
-+
-+ ts_clk: clk@01c20098 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20098 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ts";
-+ };
-+
-+ ss_clk: clk@01c2009c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2009c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ss";
-+ };
-+
-+ spi0_clk: clk@01c200a0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi0";
-+ };
-+
-+ spi1_clk: clk@01c200a4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi1";
-+ };
-+
-+ spi2_clk: clk@01c200a8 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a8 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi2";
-+ };
-+
-+ ir0_clk: clk@01c200b0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200b0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ir0";
-+ };
- };
-
- soc@01c00000 {
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -170,6 +170,94 @@
- clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart1", "apb1_uart3";
- };
-+
-+ nand_clk: clk@01c20080 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20080 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "nand";
-+ };
-+
-+ ms_clk: clk@01c20084 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20084 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ms";
-+ };
-+
-+ mmc0_clk: clk@01c20088 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20088 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc0";
-+ };
-+
-+ mmc1_clk: clk@01c2008c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2008c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc1";
-+ };
-+
-+ mmc2_clk: clk@01c20090 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20090 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc2";
-+ };
-+
-+ ts_clk: clk@01c20098 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20098 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ts";
-+ };
-+
-+ ss_clk: clk@01c2009c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2009c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ss";
-+ };
-+
-+ spi0_clk: clk@01c200a0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi0";
-+ };
-+
-+ spi1_clk: clk@01c200a4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi1";
-+ };
-+
-+ spi2_clk: clk@01c200a8 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a8 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi2";
-+ };
-+
-+ ir0_clk: clk@01c200b0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200b0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ir0";
-+ };
- };
-
- soc@01c00000 {
+++ /dev/null
-From d7904e075e3378bec09333b6a3247b3146b3dd91 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:43 -0300
-Subject: [PATCH] ARM: sun7i: dt: mod0 clocks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds all the mod0 clocks available on A20 to its device
-tree. This list was created by looking at AW's code release.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 120 +++++++++++++++++++++++++++++++++++++++
- 1 file changed, 120 insertions(+)
-
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -170,6 +170,126 @@
- "apb1_uart2", "apb1_uart3", "apb1_uart4",
- "apb1_uart5", "apb1_uart6", "apb1_uart7";
- };
-+
-+ nand_clk: clk@01c20080 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20080 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "nand";
-+ };
-+
-+ ms_clk: clk@01c20084 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20084 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ms";
-+ };
-+
-+ mmc0_clk: clk@01c20088 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20088 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc0";
-+ };
-+
-+ mmc1_clk: clk@01c2008c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2008c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc1";
-+ };
-+
-+ mmc2_clk: clk@01c20090 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20090 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc2";
-+ };
-+
-+ mmc3_clk: clk@01c20094 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20094 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc3";
-+ };
-+
-+ ts_clk: clk@01c20098 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20098 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ts";
-+ };
-+
-+ ss_clk: clk@01c2009c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2009c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ss";
-+ };
-+
-+ spi0_clk: clk@01c200a0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi0";
-+ };
-+
-+ spi1_clk: clk@01c200a4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi1";
-+ };
-+
-+ spi2_clk: clk@01c200a8 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a8 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi2";
-+ };
-+
-+ pata_clk: clk@01c200ac {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200ac 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "pata";
-+ };
-+
-+ ir0_clk: clk@01c200b0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200b0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ir0";
-+ };
-+
-+ ir1_clk: clk@01c200b4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200b4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ir1";
-+ };
-+
-+ spi3_clk: clk@01c200d4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200d4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi3";
-+ };
- };
-
- soc@01c00000 {
+++ /dev/null
-From 04b5b3f9c83c0c0b472c4704d83ec7f56a485a21 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Thu, 5 Sep 2013 19:52:41 -0300
-Subject: [PATCH] clk: sunxi: factors: automatic reparenting support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit implements .determine_rate, so that our factor clocks can be
-reparented when needed.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-factors.c | 36 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 36 insertions(+)
-
---- a/drivers/clk/sunxi/clk-factors.c
-+++ b/drivers/clk/sunxi/clk-factors.c
-@@ -77,6 +77,41 @@ static long clk_factors_round_rate(struc
- return rate;
- }
-
-+static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
-+ unsigned long *best_parent_rate,
-+ struct clk **best_parent_p)
-+{
-+ struct clk *clk = hw->clk, *parent, *best_parent = NULL;
-+ int i, num_parents;
-+ unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
-+
-+ /* find the parent that can help provide the fastest rate <= rate */
-+ num_parents = __clk_get_num_parents(clk);
-+ for (i = 0; i < num_parents; i++) {
-+ parent = clk_get_parent_by_index(clk, i);
-+ if (!parent)
-+ continue;
-+ if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
-+ parent_rate = __clk_round_rate(parent, rate);
-+ else
-+ parent_rate = __clk_get_rate(parent);
-+
-+ child_rate = clk_factors_round_rate(hw, rate, &parent_rate);
-+
-+ if (child_rate <= rate && child_rate > best_child_rate) {
-+ best_parent = parent;
-+ best = parent_rate;
-+ best_child_rate = child_rate;
-+ }
-+ }
-+
-+ if (best_parent)
-+ *best_parent_p = best_parent;
-+ *best_parent_rate = best;
-+
-+ return best_child_rate;
-+}
-+
- static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
- {
-@@ -113,6 +148,7 @@ static int clk_factors_set_rate(struct c
- }
-
- const struct clk_ops clk_factors_ops = {
-+ .determine_rate = clk_factors_determine_rate,
- .recalc_rate = clk_factors_recalc_rate,
- .round_rate = clk_factors_round_rate,
- .set_rate = clk_factors_set_rate,
+++ /dev/null
-From d3861805e84e1b54073e20dc499b9380b38bb7ab Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 3 Nov 2013 10:30:12 +0100
-Subject: [PATCH] ARM: sun6i: dt: Add IP needed to bring up the additional
- cores
-
-Add the PRCM and CPU configuration units needed for SMP in the A31 DTSI.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -322,5 +322,15 @@
- #interrupt-cells = <3>;
- interrupts = <1 9 0xf04>;
- };
-+
-+ cpucfg@01f01c00 {
-+ compatible = "allwinner,sun6i-a31-cpuconfig";
-+ reg = <0x01f01c00 0x300>;
-+ };
-+
-+ prcm@01f01c00 {
-+ compatible = "allwinner,sun6i-a31-prcm";
-+ reg = <0x01f01400 0x200>;
-+ };
- };
- };
+++ /dev/null
-From 0aff0370cbffeadc14456556b904c80e30b3717e Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Wed, 1 Jan 2014 10:30:48 +0800
-Subject: [PATCH] ARM: dts: sun7i: external clock outputs
-
-This commit adds the two external clock outputs available on A20 to
-its device tree. A dummy fixed factor clock is also added to serve as
-the first input of the clock outputs, which according to AW's A20 user
-manual, is the 24MHz oscillator divided by 750.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index edad6f1..0d54998 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -303,6 +303,34 @@
- clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
- clock-output-names = "mbus";
- };
-+
-+ /*
-+ * Dummy clock used by output clocks
-+ */
-+ osc24M_32k: clk@1 {
-+ #clock-cells = <0>;
-+ compatible = "fixed-factor-clock";
-+ clock-div = <750>;
-+ clock-mult = <1>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "osc24M_32k";
-+ };
-+
-+ clk_out_a: clk@01c201f0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun7i-a20-out-clk";
-+ reg = <0x01c201f0 0x4>;
-+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
-+ clock-output-names = "clk_out_a";
-+ };
-+
-+ clk_out_b: clk@01c201f4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun7i-a20-out-clk";
-+ reg = <0x01c201f4 0x4>;
-+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
-+ clock-output-names = "clk_out_b";
-+ };
- };
-
- soc@01c00000 {
---
-1.8.5.5
-
+++ /dev/null
-From dfb12c0c35b6cca5e55f40870b65af87988adb3e Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:41 +0800
-Subject: [PATCH] ARM: dts: sun4i: rename clock node names to clk@N
-
-Device tree naming conventions state that node names should match
-node function. Change fully functioning clock nodes to match and
-add clock-output-names to all sunxi clock nodes.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 30 ++++++++++++++++++++----------
- 1 file changed, 20 insertions(+), 10 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 28273f9..26cf191 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -58,34 +58,38 @@
- clock-frequency = <0>;
- };
-
-- osc24M: osc24M@01c20050 {
-+ osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-osc-clk";
- reg = <0x01c20050 0x4>;
- clock-frequency = <24000000>;
-+ clock-output-names = "osc24M";
- };
-
-- osc32k: osc32k {
-+ osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
-+ clock-output-names = "osc32k";
- };
-
-- pll1: pll1@01c20000 {
-+ pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll1";
- };
-
-- pll4: pll4@01c20018 {
-+ pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll4";
- };
-
-- pll5: pll5@01c20020 {
-+ pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll5-clk";
- reg = <0x01c20020 0x4>;
-@@ -93,7 +97,7 @@
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
-- pll6: pll6@01c20028 {
-+ pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll6-clk";
- reg = <0x01c20028 0x4>;
-@@ -107,6 +111,7 @@
- compatible = "allwinner,sun4i-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
-+ clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
-@@ -114,9 +119,10 @@
- compatible = "allwinner,sun4i-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
-+ clock-output-names = "axi";
- };
-
-- axi_gates: axi_gates@01c2005c {
-+ axi_gates: clk@01c2005c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-axi-gates-clk";
- reg = <0x01c2005c 0x4>;
-@@ -129,9 +135,10 @@
- compatible = "allwinner,sun4i-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>;
-+ clock-output-names = "ahb";
- };
-
-- ahb_gates: ahb_gates@01c20060 {
-+ ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
-@@ -154,9 +161,10 @@
- compatible = "allwinner,sun4i-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
-+ clock-output-names = "apb0";
- };
-
-- apb0_gates: apb0_gates@01c20068 {
-+ apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
-@@ -171,6 +179,7 @@
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-+ clock-output-names = "apb1_mux";
- };
-
- apb1: apb1@01c20058 {
-@@ -178,9 +187,10 @@
- compatible = "allwinner,sun4i-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&apb1_mux>;
-+ clock-output-names = "apb1";
- };
-
-- apb1_gates: apb1_gates@01c2006c {
-+ apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
---
-1.8.5.5
-
+++ /dev/null
-From 3dce8324949eaa1ab4b750e8422ce78ddceb7aa4 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:42 +0800
-Subject: [PATCH] ARM: dts: sun5i: rename clock node names to clk@N
-
-Device tree naming conventions state that node names should match
-node function. Change fully functioning clock nodes to match and
-add clock-output-names to all sunxi clock nodes.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 30 ++++++++++++++++++++----------
- arch/arm/boot/dts/sun5i-a13.dtsi | 30 ++++++++++++++++++++----------
- 2 files changed, 40 insertions(+), 20 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 2318082..b114be7 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -51,34 +51,38 @@
- clock-frequency = <0>;
- };
-
-- osc24M: osc24M@01c20050 {
-+ osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-osc-clk";
- reg = <0x01c20050 0x4>;
- clock-frequency = <24000000>;
-+ clock-output-names = "osc24M";
- };
-
-- osc32k: osc32k {
-+ osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
-+ clock-output-names = "osc32k";
- };
-
-- pll1: pll1@01c20000 {
-+ pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll1";
- };
-
-- pll4: pll4@01c20018 {
-+ pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll4";
- };
-
-- pll5: pll5@01c20020 {
-+ pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll5-clk";
- reg = <0x01c20020 0x4>;
-@@ -86,7 +90,7 @@
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
-- pll6: pll6@01c20028 {
-+ pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll6-clk";
- reg = <0x01c20028 0x4>;
-@@ -100,6 +104,7 @@
- compatible = "allwinner,sun4i-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
-+ clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
-@@ -107,9 +112,10 @@
- compatible = "allwinner,sun4i-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
-+ clock-output-names = "axi";
- };
-
-- axi_gates: axi_gates@01c2005c {
-+ axi_gates: clk@01c2005c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-axi-gates-clk";
- reg = <0x01c2005c 0x4>;
-@@ -122,9 +128,10 @@
- compatible = "allwinner,sun4i-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>;
-+ clock-output-names = "ahb";
- };
-
-- ahb_gates: ahb_gates@01c20060 {
-+ ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
-@@ -143,9 +150,10 @@
- compatible = "allwinner,sun4i-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
-+ clock-output-names = "apb0";
- };
-
-- apb0_gates: apb0_gates@01c20068 {
-+ apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
-@@ -159,6 +167,7 @@
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-+ clock-output-names = "apb1_mux";
- };
-
- apb1: apb1@01c20058 {
-@@ -166,9 +175,10 @@
- compatible = "allwinner,sun4i-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&apb1_mux>;
-+ clock-output-names = "apb1";
- };
-
-- apb1_gates: apb1_gates@01c2006c {
-+ apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 6de40b6..5c121fc 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -52,34 +52,38 @@
- clock-frequency = <0>;
- };
-
-- osc24M: osc24M@01c20050 {
-+ osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-osc-clk";
- reg = <0x01c20050 0x4>;
- clock-frequency = <24000000>;
-+ clock-output-names = "osc24M";
- };
-
-- osc32k: osc32k {
-+ osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
-+ clock-output-names = "osc32k";
- };
-
-- pll1: pll1@01c20000 {
-+ pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll1";
- };
-
-- pll4: pll4@01c20018 {
-+ pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll4";
- };
-
-- pll5: pll5@01c20020 {
-+ pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll5-clk";
- reg = <0x01c20020 0x4>;
-@@ -87,7 +91,7 @@
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
-- pll6: pll6@01c20028 {
-+ pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll6-clk";
- reg = <0x01c20028 0x4>;
-@@ -101,6 +105,7 @@
- compatible = "allwinner,sun4i-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
-+ clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
-@@ -108,9 +113,10 @@
- compatible = "allwinner,sun4i-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
-+ clock-output-names = "axi";
- };
-
-- axi_gates: axi_gates@01c2005c {
-+ axi_gates: clk@01c2005c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-axi-gates-clk";
- reg = <0x01c2005c 0x4>;
-@@ -123,9 +129,10 @@
- compatible = "allwinner,sun4i-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>;
-+ clock-output-names = "ahb";
- };
-
-- ahb_gates: ahb_gates@01c20060 {
-+ ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
-@@ -143,9 +150,10 @@
- compatible = "allwinner,sun4i-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
-+ clock-output-names = "apb0";
- };
-
-- apb0_gates: apb0_gates@01c20068 {
-+ apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
-@@ -158,6 +166,7 @@
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-+ clock-output-names = "apb1_mux";
- };
-
- apb1: apb1@01c20058 {
-@@ -165,9 +174,10 @@
- compatible = "allwinner,sun4i-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&apb1_mux>;
-+ clock-output-names = "apb1";
- };
-
-- apb1_gates: apb1_gates@01c2006c {
-+ apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
---
-1.8.5.5
-
+++ /dev/null
-From 5cd0fa24e51d342f175d31ecb72c2e957a6bd0af Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:43 +0800
-Subject: [PATCH] ARM: dts: sun6i: rename clock node names to clk@N
-
-Device tree naming conventions state that node names should match
-node function. Change fully functioning clock nodes to match and
-add clock-output-names to all sunxi clock nodes.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 19 ++++++++++++++-----
- 1 file changed, 14 insertions(+), 5 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
-index fc07f70..d3f1995 100644
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -70,17 +70,19 @@
- clock-frequency = <24000000>;
- };
-
-- osc32k: osc32k {
-+ osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
-+ clock-output-names = "osc32k";
- };
-
-- pll1: pll1@01c20000 {
-+ pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun6i-a31-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll1";
- };
-
- pll6: clk@01c20028 {
-@@ -103,6 +105,7 @@
- * Allwinner.
- */
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
-+ clock-output-names = "cpu";
- };
-
- axi: axi@01c20050 {
-@@ -110,6 +113,7 @@
- compatible = "allwinner,sun4i-axi-clk";
- reg = <0x01c20050 0x4>;
- clocks = <&cpu>;
-+ clock-output-names = "axi";
- };
-
- ahb1_mux: ahb1_mux@01c20054 {
-@@ -117,6 +121,7 @@
- compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
-+ clock-output-names = "ahb1_mux";
- };
-
- ahb1: ahb1@01c20054 {
-@@ -124,9 +129,10 @@
- compatible = "allwinner,sun4i-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb1_mux>;
-+ clock-output-names = "ahb1";
- };
-
-- ahb1_gates: ahb1_gates@01c20060 {
-+ ahb1_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
- reg = <0x01c20060 0x8>;
-@@ -152,9 +158,10 @@
- compatible = "allwinner,sun4i-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb1>;
-+ clock-output-names = "apb1";
- };
-
-- apb1_gates: apb1_gates@01c20060 {
-+ apb1_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-apb1-gates-clk";
- reg = <0x01c20068 0x4>;
-@@ -169,6 +176,7 @@
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
-+ clock-output-names = "apb2_mux";
- };
-
- apb2: apb2@01c20058 {
-@@ -176,9 +184,10 @@
- compatible = "allwinner,sun6i-a31-apb2-div-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&apb2_mux>;
-+ clock-output-names = "apb2";
- };
-
-- apb2_gates: apb2_gates@01c2006c {
-+ apb2_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-apb2-gates-clk";
- reg = <0x01c2006c 0x4>;
---
-1.8.5.5
-
+++ /dev/null
-From cb6050998de262d5acf2207c5451d4f5995a5bff Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:44 +0800
-Subject: [PATCH] ARM: dts: sun7i: rename clock node names to clk@N
-
-Device tree naming conventions state that node names should match
-node function. Change fully functioning clock nodes to match and
-add clock-output-names to all sunxi clock nodes.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 25 +++++++++++++++++--------
- 1 file changed, 17 insertions(+), 8 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index fe0fe47..cefd7ac 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -54,11 +54,12 @@
- #size-cells = <1>;
- ranges;
-
-- osc24M: osc24M@01c20050 {
-+ osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-osc-clk";
- reg = <0x01c20050 0x4>;
- clock-frequency = <24000000>;
-+ clock-output-names = "osc24M";
- };
-
- osc32k: clk@0 {
-@@ -68,21 +69,23 @@
- clock-output-names = "osc32k";
- };
-
-- pll1: pll1@01c20000 {
-+ pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll1";
- };
-
-- pll4: pll4@01c20018 {
-+ pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll4";
- };
-
-- pll5: pll5@01c20020 {
-+ pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll5-clk";
- reg = <0x01c20020 0x4>;
-@@ -90,7 +93,7 @@
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
-- pll6: pll6@01c20028 {
-+ pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll6-clk";
- reg = <0x01c20028 0x4>;
-@@ -103,6 +106,7 @@
- compatible = "allwinner,sun4i-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
-+ clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
-@@ -110,6 +114,7 @@
- compatible = "allwinner,sun4i-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
-+ clock-output-names = "axi";
- };
-
- ahb: ahb@01c20054 {
-@@ -117,9 +122,10 @@
- compatible = "allwinner,sun4i-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>;
-+ clock-output-names = "ahb";
- };
-
-- ahb_gates: ahb_gates@01c20060 {
-+ ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun7i-a20-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
-@@ -144,9 +150,10 @@
- compatible = "allwinner,sun4i-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
-+ clock-output-names = "apb0";
- };
-
-- apb0_gates: apb0_gates@01c20068 {
-+ apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun7i-a20-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
-@@ -162,6 +169,7 @@
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-+ clock-output-names = "apb1_mux";
- };
-
- apb1: apb1@01c20058 {
-@@ -169,9 +177,10 @@
- compatible = "allwinner,sun4i-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&apb1_mux>;
-+ clock-output-names = "apb1";
- };
-
-- apb1_gates: apb1_gates@01c2006c {
-+ apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun7i-a20-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
---
-1.8.5.5
-
+++ /dev/null
-From 538d4a6ca5f41039d906f28be82e0f4d26ec8ac9 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:44 -0300
-Subject: [PATCH] ARM: sunxi: dt: add nodes for the mbus clock
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-mbus is the memory bus clock, and it is present on both sun5i and sun7i
-machines. Its register layout is compatible with the mod0 one.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 8 ++++++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
- 3 files changed, 24 insertions(+)
-
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -257,6 +257,14 @@
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ir0";
- };
-+
-+ mbus_clk: clk@01c2015c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2015c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mbus";
-+ };
- };
-
- soc@01c00000 {
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -258,6 +258,14 @@
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ir0";
- };
-+
-+ mbus_clk: clk@01c2015c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2015c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mbus";
-+ };
- };
-
- soc@01c00000 {
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -290,6 +290,14 @@
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi3";
- };
-+
-+ mbus_clk: clk@01c2015c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2015c 0x4>;
-+ clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
-+ clock-output-names = "mbus";
-+ };
- };
-
- soc@01c00000 {
+++ /dev/null
-From 2af807481169af627dc63f98b773c33d85020658 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Fri, 15 Nov 2013 15:26:44 -0300
-Subject: [PATCH] ARM: sunxi: dt: add EMAC aliases
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-U-Boot uses the ethernet0 alias to locate the right node to fill in
-the MAC address of the first ethernet interface. This patch adds the
-alias on all the sunxi SoCs with EMAC. In this way, people using
-ethernet in U-Boot (eg, for tftp) can keep a consistent address on both
-U-Boot and Linux with no additional effort.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 4 ++++
- arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++++
- 3 files changed, 12 insertions(+)
-
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -15,6 +15,10 @@
- / {
- interrupt-parent = <&intc>;
-
-+ aliases {
-+ ethernet0 = &emac;
-+ };
-+
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -16,6 +16,10 @@
- / {
- interrupt-parent = <&intc>;
-
-+ aliases {
-+ ethernet0 = &emac;
-+ };
-+
- cpus {
- cpu@0 {
- compatible = "arm,cortex-a8";
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -16,6 +16,10 @@
- / {
- interrupt-parent = <&gic>;
-
-+ aliases {
-+ ethernet0 = &emac;
-+ };
-+
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
+++ /dev/null
-From dfd4430579f5e53324c00e9e21fb0929bb46542c Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Sat, 7 Dec 2013 01:29:43 +0800
-Subject: [PATCH] ARM: dts: sun7i: Add ethernet alias for GMAC
-
-U-Boot will insert MAC address into the device tree image.
-It looks up ethernet[0-5] aliases to find the ethernet nodes.
-Alias GMAC as ethernet0, as it is the only ethernet controller used.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -17,7 +17,7 @@
- interrupt-parent = <&gic>;
-
- aliases {
-- ethernet0 = &emac;
-+ ethernet0 = &gmac;
- };
-
- cpus {
+++ /dev/null
-From fdc4530902ed845fc0f31b9bbcc45e05fefe21da Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 1 Dec 2013 22:40:34 +0100
-Subject: [PATCH] ARM: dts: sun7i: Add arch timers
-
-Note this requires a new enough uboot, otherwise things won't work, ie:
-
-https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-next
-or:
-http://xenbits.xen.org/gitweb/?p=people/ianc/u-boot.git;a=shortlog;h=refs/heads/devel/sunxi-psci
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index f4ecd79..fa2ef07 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -370,6 +370,14 @@
- };
- };
-
-+ timer {
-+ compatible = "arm,armv7-timer";
-+ interrupts = <1 13 0xf08>,
-+ <1 14 0xf08>,
-+ <1 11 0xf08>,
-+ <1 10 0xf08>;
-+ };
-+
- soc@01c00000 {
- compatible = "simple-bus";
- #address-cells = <1>;
---
-1.8.5.5
-
+++ /dev/null
-From aad62992a2921436ec7c054f8b80bc916b8cc9d7 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 14 Dec 2013 16:26:17 +0100
-Subject: [PATCH] ARM: dts: sun5i: Add new sun5i-a13-olinuxino-micro board
-
-The A13-OLinuXino-MICRO is a small dev-board with the Allwinner A13 SoC:
-https://www.olimex.com/Products/OLinuXino/A13/A13-OLinuXino-MICRO/
-
-Features:
-A13 Cortex A8 processor at 1GHz, 3D Mali400 GPU
-256 MB RAM (128Mbit x 16)
-5VDC input power supply with own ICs, noise immune design
-1 USB host
-1 USB OTG which can power the board
-SD-card connector for booting the Linux image
-VGA video output
-LCD signals available on connector so you still can use LCD if you disable VGA/HDMI
-Audio output
-Microphone input pads (no connector)
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 68 +++++++++++++++++++++++++
- 2 files changed, 69 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -255,6 +255,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
- sun4i-a10-hackberry.dtb \
- sun5i-a10s-olinuxino-micro.dtb \
- sun5i-a13-olinuxino.dtb \
-+ sun5i-a13-olinuxino-micro.dtb \
- sun6i-a31-colombus.dtb \
- sun7i-a20-cubieboard2.dtb \
- sun7i-a20-cubietruck.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
-@@ -0,0 +1,68 @@
-+/*
-+ * Copyright 2012 Maxime Ripard
-+ * Copyright 2013 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/dts-v1/;
-+/include/ "sun5i-a13.dtsi"
-+
-+/ {
-+ model = "Olimex A13-Olinuxino Micro";
-+ compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
-+
-+ soc@01c00000 {
-+ pinctrl@01c20800 {
-+ led_pins_olinuxinom: led_pins@0 {
-+ allwinner,pins = "PG9";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <1>;
-+ allwinner,pull = <0>;
-+ };
-+ };
-+
-+ uart1: serial@01c28400 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart1_pins_b>;
-+ status = "okay";
-+ };
-+
-+ i2c0: i2c@01c2ac00 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c0_pins_a>;
-+ status = "okay";
-+ };
-+
-+ i2c1: i2c@01c2b000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c1_pins_a>;
-+ status = "okay";
-+ };
-+
-+ i2c2: i2c@01c2b400 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c2_pins_a>;
-+ status = "okay";
-+ };
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&led_pins_olinuxinom>;
-+
-+ power {
-+ label = "a13-olinuxino-micro:green:power";
-+ gpios = <&pio 6 9 0>;
-+ default-state = "on";
-+ };
-+ };
-+};
+++ /dev/null
-From c6890cadc2129a07d69f3dcbfca66522c27b8069 Mon Sep 17 00:00:00 2001
-From: Carlo Caione <carlo.caione@gmail.com>
-Date: Sat, 16 Nov 2013 18:33:54 +0100
-Subject: [PATCH] ARM: sun4i/sun7i: RTC driver
-
-This patch introduces the driver for the RTC in the Allwinner A10 and
-A20 SoCs.
-
-Signed-off-by: Carlo Caione <carlo.caione@gmail.com>
-Acked-by: Alessandro Zummo <a.zummo@towertech.it>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/rtc/Kconfig | 7 +
- drivers/rtc/Makefile | 1 +
- drivers/rtc/rtc-sunxi.c | 523 ++++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 531 insertions(+)
- create mode 100644 drivers/rtc/rtc-sunxi.c
-
---- a/drivers/rtc/Kconfig
-+++ b/drivers/rtc/Kconfig
-@@ -1122,6 +1122,13 @@ config RTC_DRV_SUN4V
- If you say Y here you will get support for the Hypervisor
- based RTC on SUN4V systems.
-
-+config RTC_DRV_SUNXI
-+ tristate "Allwinner sun4i/sun7i RTC"
-+ depends on ARCH_SUNXI
-+ help
-+ If you say Y here you will get support for the RTC found on
-+ Allwinner A10/A20.
-+
- config RTC_DRV_STARFIRE
- bool "Starfire RTC"
- depends on SPARC64
---- a/drivers/rtc/Makefile
-+++ b/drivers/rtc/Makefile
-@@ -119,6 +119,7 @@ obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-st
- obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o
- obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o
- obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o
-+obj-$(CONFIG_RTC_DRV_SUNXI) += rtc-sunxi.o
- obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o
- obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o
- obj-$(CONFIG_RTC_DRV_TILE) += rtc-tile.o
---- /dev/null
-+++ b/drivers/rtc/rtc-sunxi.c
-@@ -0,0 +1,523 @@
-+/*
-+ * An RTC driver for Allwinner A10/A20
-+ *
-+ * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/fs.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/rtc.h>
-+#include <linux/types.h>
-+
-+#define SUNXI_LOSC_CTRL 0x0000
-+#define SUNXI_LOSC_CTRL_RTC_HMS_ACC BIT(8)
-+#define SUNXI_LOSC_CTRL_RTC_YMD_ACC BIT(7)
-+
-+#define SUNXI_RTC_YMD 0x0004
-+
-+#define SUNXI_RTC_HMS 0x0008
-+
-+#define SUNXI_ALRM_DHMS 0x000c
-+
-+#define SUNXI_ALRM_EN 0x0014
-+#define SUNXI_ALRM_EN_CNT_EN BIT(8)
-+
-+#define SUNXI_ALRM_IRQ_EN 0x0018
-+#define SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
-+
-+#define SUNXI_ALRM_IRQ_STA 0x001c
-+#define SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
-+
-+#define SUNXI_MASK_DH 0x0000001f
-+#define SUNXI_MASK_SM 0x0000003f
-+#define SUNXI_MASK_M 0x0000000f
-+#define SUNXI_MASK_LY 0x00000001
-+#define SUNXI_MASK_D 0x00000ffe
-+#define SUNXI_MASK_M 0x0000000f
-+
-+#define SUNXI_GET(x, mask, shift) (((x) & ((mask) << (shift))) \
-+ >> (shift))
-+
-+#define SUNXI_SET(x, mask, shift) (((x) & (mask)) << (shift))
-+
-+/*
-+ * Get date values
-+ */
-+#define SUNXI_DATE_GET_DAY_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 0)
-+#define SUNXI_DATE_GET_MON_VALUE(x) SUNXI_GET(x, SUNXI_MASK_M, 8)
-+#define SUNXI_DATE_GET_YEAR_VALUE(x, mask) SUNXI_GET(x, mask, 16)
-+
-+/*
-+ * Get time values
-+ */
-+#define SUNXI_TIME_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0)
-+#define SUNXI_TIME_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8)
-+#define SUNXI_TIME_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16)
-+
-+/*
-+ * Get alarm values
-+ */
-+#define SUNXI_ALRM_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0)
-+#define SUNXI_ALRM_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8)
-+#define SUNXI_ALRM_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16)
-+
-+/*
-+ * Set date values
-+ */
-+#define SUNXI_DATE_SET_DAY_VALUE(x) SUNXI_DATE_GET_DAY_VALUE(x)
-+#define SUNXI_DATE_SET_MON_VALUE(x) SUNXI_SET(x, SUNXI_MASK_M, 8)
-+#define SUNXI_DATE_SET_YEAR_VALUE(x, mask) SUNXI_SET(x, mask, 16)
-+#define SUNXI_LEAP_SET_VALUE(x, shift) SUNXI_SET(x, SUNXI_MASK_LY, shift)
-+
-+/*
-+ * Set time values
-+ */
-+#define SUNXI_TIME_SET_SEC_VALUE(x) SUNXI_TIME_GET_SEC_VALUE(x)
-+#define SUNXI_TIME_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8)
-+#define SUNXI_TIME_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16)
-+
-+/*
-+ * Set alarm values
-+ */
-+#define SUNXI_ALRM_SET_SEC_VALUE(x) SUNXI_ALRM_GET_SEC_VALUE(x)
-+#define SUNXI_ALRM_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8)
-+#define SUNXI_ALRM_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16)
-+#define SUNXI_ALRM_SET_DAY_VALUE(x) SUNXI_SET(x, SUNXI_MASK_D, 21)
-+
-+/*
-+ * Time unit conversions
-+ */
-+#define SEC_IN_MIN 60
-+#define SEC_IN_HOUR (60 * SEC_IN_MIN)
-+#define SEC_IN_DAY (24 * SEC_IN_HOUR)
-+
-+/*
-+ * The year parameter passed to the driver is usually an offset relative to
-+ * the year 1900. This macro is used to convert this offset to another one
-+ * relative to the minimum year allowed by the hardware.
-+ */
-+#define SUNXI_YEAR_OFF(x) ((x)->min - 1900)
-+
-+/*
-+ * min and max year are arbitrary set considering the limited range of the
-+ * hardware register field
-+ */
-+struct sunxi_rtc_data_year {
-+ unsigned int min; /* min year allowed */
-+ unsigned int max; /* max year allowed */
-+ unsigned int mask; /* mask for the year field */
-+ unsigned char leap_shift; /* bit shift to get the leap year */
-+};
-+
-+static struct sunxi_rtc_data_year data_year_param[] = {
-+ [0] = {
-+ .min = 2010,
-+ .max = 2073,
-+ .mask = 0x3f,
-+ .leap_shift = 22,
-+ },
-+ [1] = {
-+ .min = 1970,
-+ .max = 2225,
-+ .mask = 0xff,
-+ .leap_shift = 24,
-+ },
-+};
-+
-+struct sunxi_rtc_dev {
-+ struct rtc_device *rtc;
-+ struct device *dev;
-+ struct sunxi_rtc_data_year *data_year;
-+ void __iomem *base;
-+ int irq;
-+};
-+
-+static irqreturn_t sunxi_rtc_alarmirq(int irq, void *id)
-+{
-+ struct sunxi_rtc_dev *chip = (struct sunxi_rtc_dev *) id;
-+ u32 val;
-+
-+ val = readl(chip->base + SUNXI_ALRM_IRQ_STA);
-+
-+ if (val & SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND) {
-+ val |= SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND;
-+ writel(val, chip->base + SUNXI_ALRM_IRQ_STA);
-+
-+ rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
-+
-+ return IRQ_HANDLED;
-+ }
-+
-+ return IRQ_NONE;
-+}
-+
-+static void sunxi_rtc_setaie(int to, struct sunxi_rtc_dev *chip)
-+{
-+ u32 alrm_val = 0;
-+ u32 alrm_irq_val = 0;
-+
-+ if (to) {
-+ alrm_val = readl(chip->base + SUNXI_ALRM_EN);
-+ alrm_val |= SUNXI_ALRM_EN_CNT_EN;
-+
-+ alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN);
-+ alrm_irq_val |= SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN;
-+ } else {
-+ writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND,
-+ chip->base + SUNXI_ALRM_IRQ_STA);
-+ }
-+
-+ writel(alrm_val, chip->base + SUNXI_ALRM_EN);
-+ writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN);
-+}
-+
-+static int sunxi_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
-+{
-+ struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
-+ struct rtc_time *alrm_tm = &wkalrm->time;
-+ u32 alrm;
-+ u32 alrm_en;
-+ u32 date;
-+
-+ alrm = readl(chip->base + SUNXI_ALRM_DHMS);
-+ date = readl(chip->base + SUNXI_RTC_YMD);
-+
-+ alrm_tm->tm_sec = SUNXI_ALRM_GET_SEC_VALUE(alrm);
-+ alrm_tm->tm_min = SUNXI_ALRM_GET_MIN_VALUE(alrm);
-+ alrm_tm->tm_hour = SUNXI_ALRM_GET_HOUR_VALUE(alrm);
-+
-+ alrm_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
-+ alrm_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
-+ alrm_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
-+ chip->data_year->mask);
-+
-+ alrm_tm->tm_mon -= 1;
-+
-+ /*
-+ * switch from (data_year->min)-relative offset to
-+ * a (1900)-relative one
-+ */
-+ alrm_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
-+
-+ alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN);
-+ if (alrm_en & SUNXI_ALRM_EN_CNT_EN)
-+ wkalrm->enabled = 1;
-+
-+ return 0;
-+}
-+
-+static int sunxi_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
-+{
-+ struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
-+ u32 date, time;
-+
-+ /*
-+ * read again in case it changes
-+ */
-+ do {
-+ date = readl(chip->base + SUNXI_RTC_YMD);
-+ time = readl(chip->base + SUNXI_RTC_HMS);
-+ } while ((date != readl(chip->base + SUNXI_RTC_YMD)) ||
-+ (time != readl(chip->base + SUNXI_RTC_HMS)));
-+
-+ rtc_tm->tm_sec = SUNXI_TIME_GET_SEC_VALUE(time);
-+ rtc_tm->tm_min = SUNXI_TIME_GET_MIN_VALUE(time);
-+ rtc_tm->tm_hour = SUNXI_TIME_GET_HOUR_VALUE(time);
-+
-+ rtc_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
-+ rtc_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
-+ rtc_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
-+ chip->data_year->mask);
-+
-+ rtc_tm->tm_mon -= 1;
-+
-+ /*
-+ * switch from (data_year->min)-relative offset to
-+ * a (1900)-relative one
-+ */
-+ rtc_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
-+
-+ return rtc_valid_tm(rtc_tm);
-+}
-+
-+static int sunxi_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
-+{
-+ struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
-+ struct rtc_time *alrm_tm = &wkalrm->time;
-+ struct rtc_time tm_now;
-+ u32 alrm = 0;
-+ unsigned long time_now = 0;
-+ unsigned long time_set = 0;
-+ unsigned long time_gap = 0;
-+ unsigned long time_gap_day = 0;
-+ unsigned long time_gap_hour = 0;
-+ unsigned long time_gap_min = 0;
-+ int ret = 0;
-+
-+ ret = sunxi_rtc_gettime(dev, &tm_now);
-+ if (ret < 0) {
-+ dev_err(dev, "Error in getting time\n");
-+ return -EINVAL;
-+ }
-+
-+ rtc_tm_to_time(alrm_tm, &time_set);
-+ rtc_tm_to_time(&tm_now, &time_now);
-+ if (time_set <= time_now) {
-+ dev_err(dev, "Date to set in the past\n");
-+ return -EINVAL;
-+ }
-+
-+ time_gap = time_set - time_now;
-+ time_gap_day = time_gap / SEC_IN_DAY;
-+ time_gap -= time_gap_day * SEC_IN_DAY;
-+ time_gap_hour = time_gap / SEC_IN_HOUR;
-+ time_gap -= time_gap_hour * SEC_IN_HOUR;
-+ time_gap_min = time_gap / SEC_IN_MIN;
-+ time_gap -= time_gap_min * SEC_IN_MIN;
-+
-+ if (time_gap_day > 255) {
-+ dev_err(dev, "Day must be in the range 0 - 255\n");
-+ return -EINVAL;
-+ }
-+
-+ sunxi_rtc_setaie(0, chip);
-+ writel(0, chip->base + SUNXI_ALRM_DHMS);
-+ usleep_range(100, 300);
-+
-+ alrm = SUNXI_ALRM_SET_SEC_VALUE(time_gap) |
-+ SUNXI_ALRM_SET_MIN_VALUE(time_gap_min) |
-+ SUNXI_ALRM_SET_HOUR_VALUE(time_gap_hour) |
-+ SUNXI_ALRM_SET_DAY_VALUE(time_gap_day);
-+ writel(alrm, chip->base + SUNXI_ALRM_DHMS);
-+
-+ writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
-+ writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN);
-+
-+ sunxi_rtc_setaie(wkalrm->enabled, chip);
-+
-+ return 0;
-+}
-+
-+static int sunxi_rtc_wait(struct sunxi_rtc_dev *chip, int offset,
-+ unsigned int mask, unsigned int ms_timeout)
-+{
-+ const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
-+ u32 reg;
-+
-+ do {
-+ reg = readl(chip->base + offset);
-+ reg &= mask;
-+
-+ if (reg == mask)
-+ return 0;
-+
-+ } while (time_before(jiffies, timeout));
-+
-+ return -ETIMEDOUT;
-+}
-+
-+static int sunxi_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
-+{
-+ struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
-+ u32 date = 0;
-+ u32 time = 0;
-+ int year;
-+
-+ /*
-+ * the input rtc_tm->tm_year is the offset relative to 1900. We use
-+ * the SUNXI_YEAR_OFF macro to rebase it with respect to the min year
-+ * allowed by the hardware
-+ */
-+
-+ year = rtc_tm->tm_year + 1900;
-+ if (year < chip->data_year->min || year > chip->data_year->max) {
-+ dev_err(dev, "rtc only supports year in range %d - %d\n",
-+ chip->data_year->min, chip->data_year->max);
-+ return -EINVAL;
-+ }
-+
-+ rtc_tm->tm_year -= SUNXI_YEAR_OFF(chip->data_year);
-+ rtc_tm->tm_mon += 1;
-+
-+ date = SUNXI_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
-+ SUNXI_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
-+ SUNXI_DATE_SET_YEAR_VALUE(rtc_tm->tm_year,
-+ chip->data_year->mask);
-+
-+ if (is_leap_year(year))
-+ date |= SUNXI_LEAP_SET_VALUE(1, chip->data_year->leap_shift);
-+
-+ time = SUNXI_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
-+ SUNXI_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
-+ SUNXI_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
-+
-+ writel(0, chip->base + SUNXI_RTC_HMS);
-+ writel(0, chip->base + SUNXI_RTC_YMD);
-+
-+ writel(time, chip->base + SUNXI_RTC_HMS);
-+
-+ /*
-+ * After writing the RTC HH-MM-SS register, the
-+ * SUNXI_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
-+ * be cleared until the real writing operation is finished
-+ */
-+
-+ if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
-+ SUNXI_LOSC_CTRL_RTC_HMS_ACC, 50)) {
-+ dev_err(dev, "Failed to set rtc time.\n");
-+ return -1;
-+ }
-+
-+ writel(date, chip->base + SUNXI_RTC_YMD);
-+
-+ /*
-+ * After writing the RTC YY-MM-DD register, the
-+ * SUNXI_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
-+ * be cleared until the real writing operation is finished
-+ */
-+
-+ if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
-+ SUNXI_LOSC_CTRL_RTC_YMD_ACC, 50)) {
-+ dev_err(dev, "Failed to set rtc time.\n");
-+ return -1;
-+ }
-+
-+ return 0;
-+}
-+
-+static int sunxi_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
-+{
-+ struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
-+
-+ if (!enabled)
-+ sunxi_rtc_setaie(enabled, chip);
-+
-+ return 0;
-+}
-+
-+static const struct rtc_class_ops sunxi_rtc_ops = {
-+ .read_time = sunxi_rtc_gettime,
-+ .set_time = sunxi_rtc_settime,
-+ .read_alarm = sunxi_rtc_getalarm,
-+ .set_alarm = sunxi_rtc_setalarm,
-+ .alarm_irq_enable = sunxi_rtc_alarm_irq_enable
-+};
-+
-+static const struct of_device_id sunxi_rtc_dt_ids[] = {
-+ { .compatible = "allwinner,sun4i-rtc", .data = &data_year_param[0] },
-+ { .compatible = "allwinner,sun7i-a20-rtc", .data = &data_year_param[1] },
-+ { /* sentinel */ },
-+};
-+MODULE_DEVICE_TABLE(of, sunxi_rtc_dt_ids);
-+
-+static int sunxi_rtc_probe(struct platform_device *pdev)
-+{
-+ struct sunxi_rtc_dev *chip;
-+ struct resource *res;
-+ const struct of_device_id *of_id;
-+ int ret;
-+
-+ chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
-+ if (!chip)
-+ return -ENOMEM;
-+
-+ platform_set_drvdata(pdev, chip);
-+ chip->dev = &pdev->dev;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ chip->base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(chip->base))
-+ return PTR_ERR(chip->base);
-+
-+ chip->irq = platform_get_irq(pdev, 0);
-+ if (chip->irq < 0) {
-+ dev_err(&pdev->dev, "No IRQ resource\n");
-+ return chip->irq;
-+ }
-+ ret = devm_request_irq(&pdev->dev, chip->irq, sunxi_rtc_alarmirq,
-+ 0, dev_name(&pdev->dev), chip);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Could not request IRQ\n");
-+ return ret;
-+ }
-+
-+ of_id = of_match_device(sunxi_rtc_dt_ids, &pdev->dev);
-+ if (!of_id) {
-+ dev_err(&pdev->dev, "Unable to setup RTC data\n");
-+ return -ENODEV;
-+ }
-+ chip->data_year = (struct sunxi_rtc_data_year *) of_id->data;
-+
-+ /* clear the alarm count value */
-+ writel(0, chip->base + SUNXI_ALRM_DHMS);
-+
-+ /* disable alarm, not generate irq pending */
-+ writel(0, chip->base + SUNXI_ALRM_EN);
-+
-+ /* disable alarm week/cnt irq, unset to cpu */
-+ writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
-+
-+ /* clear alarm week/cnt irq pending */
-+ writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base +
-+ SUNXI_ALRM_IRQ_STA);
-+
-+ chip->rtc = rtc_device_register("rtc-sunxi", &pdev->dev,
-+ &sunxi_rtc_ops, THIS_MODULE);
-+ if (IS_ERR(chip->rtc)) {
-+ dev_err(&pdev->dev, "unable to register device\n");
-+ return PTR_ERR(chip->rtc);
-+ }
-+
-+ dev_info(&pdev->dev, "RTC enabled\n");
-+
-+ return 0;
-+}
-+
-+static int sunxi_rtc_remove(struct platform_device *pdev)
-+{
-+ struct sunxi_rtc_dev *chip = platform_get_drvdata(pdev);
-+
-+ rtc_device_unregister(chip->rtc);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver sunxi_rtc_driver = {
-+ .probe = sunxi_rtc_probe,
-+ .remove = sunxi_rtc_remove,
-+ .driver = {
-+ .name = "sunxi-rtc",
-+ .owner = THIS_MODULE,
-+ .of_match_table = sunxi_rtc_dt_ids,
-+ },
-+};
-+
-+module_platform_driver(sunxi_rtc_driver);
-+
-+MODULE_DESCRIPTION("sunxi RTC driver");
-+MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From b15b9f68606134222f7aff5120c8ef70ffab92b8 Mon Sep 17 00:00:00 2001
-From: Carlo Caione <carlo.caione@gmail.com>
-Date: Wed, 16 Oct 2013 20:30:26 +0200
-Subject: [PATCH] ARM: dts: sun4i/sun7i: add RTC node
-
-Add the RTC node to DTS for Allwinner A10 and Allwinner A20.
-
-Signed-off-by: Carlo Caione <carlo.caione@gmail.com>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 6 ++++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 6 ++++++
- 2 files changed, 12 insertions(+)
-
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -412,6 +412,12 @@
- reg = <0x01c20c90 0x10>;
- };
-
-+ rtc: rtc@01c20d00 {
-+ compatible = "allwinner,sun4i-rtc";
-+ reg = <0x01c20d00 0x20>;
-+ interrupts = <24>;
-+ };
-+
- sid: eeprom@01c23800 {
- compatible = "allwinner,sun4i-sid";
- reg = <0x01c23800 0x10>;
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -416,6 +416,12 @@
- reg = <0x01c20c90 0x10>;
- };
-
-+ rtc: rtc@01c20d00 {
-+ compatible = "allwinner,sun7i-a20-rtc";
-+ reg = <0x01c20d00 0x20>;
-+ interrupts = <0 24 1>;
-+ };
-+
- sid: eeprom@01c23800 {
- compatible = "allwinner,sun7i-a20-sid";
- reg = <0x01c23800 0x200>;
+++ /dev/null
-From 3bf30f6381f9287eb99ce096bf2fa327a69c8a71 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:01:48 +0100
-Subject: [PATCH] clocksource: Add Allwinner SoCs HS timers driver
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Most of the Allwinner SoCs (at this time, all but the A10) also have a
-High Speed timers that are not using the 24MHz oscillator as a source
-but rather the AHB clock running much faster.
-
-The IP is slightly different between the A10s/A13 and the one used in
-the A20/A31, since the latter have 4 timers available, while the former
-have only 2 of them.
-
-[dlezcano] : Fixed conflict with b788beda "Order Kconfig options
- alphabetically"
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Tested-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- .../bindings/timer/allwinner,sun5i-a13-hstimer.txt | 22 +++
- arch/arm/mach-sunxi/Kconfig | 1 +
- drivers/clocksource/Kconfig | 4 +
- drivers/clocksource/Makefile | 1 +
- drivers/clocksource/timer-sun5i.c | 192 +++++++++++++++++++++
- 5 files changed, 220 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
- create mode 100644 drivers/clocksource/timer-sun5i.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
-@@ -0,0 +1,22 @@
-+Allwinner SoCs High Speed Timer Controller
-+
-+Required properties:
-+
-+- compatible : should be "allwinner,sun5i-a13-hstimer" or
-+ "allwinner,sun7i-a20-hstimer"
-+- reg : Specifies base physical address and size of the registers.
-+- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
-+ one)
-+- clocks: phandle to the source clock (usually the AHB clock)
-+
-+Example:
-+
-+timer@01c60000 {
-+ compatible = "allwinner,sun7i-a20-hstimer";
-+ reg = <0x01c60000 0x1000>;
-+ interrupts = <0 51 1>,
-+ <0 52 1>,
-+ <0 53 1>,
-+ <0 54 1>;
-+ clocks = <&ahb1_gates 19>;
-+};
---- a/arch/arm/mach-sunxi/Kconfig
-+++ b/arch/arm/mach-sunxi/Kconfig
-@@ -13,3 +13,4 @@ config ARCH_SUNXI
- select PINCTRL_SUNXI
- select SPARSE_IRQ
- select SUN4I_TIMER
-+ select SUN5I_HSTIMER
---- a/drivers/clocksource/Kconfig
-+++ b/drivers/clocksource/Kconfig
-@@ -37,6 +37,10 @@ config SUN4I_TIMER
- select CLKSRC_MMIO
- bool
-
-+config SUN5I_HSTIMER
-+ select CLKSRC_MMIO
-+ bool
-+
- config VT8500_TIMER
- bool
-
---- a/drivers/clocksource/Makefile
-+++ b/drivers/clocksource/Makefile
-@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_MOXART) += moxart_time
- obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
- obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
- obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
-+obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o
- obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
- obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
- obj-$(CONFIG_ARCH_NSPIRE) += zevio-timer.o
---- /dev/null
-+++ b/drivers/clocksource/timer-sun5i.c
-@@ -0,0 +1,192 @@
-+/*
-+ * Allwinner SoCs hstimer driver.
-+ *
-+ * Copyright (C) 2013 Maxime Ripard
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clockchips.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/irqreturn.h>
-+#include <linux/sched_clock.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_irq.h>
-+
-+#define TIMER_IRQ_EN_REG 0x00
-+#define TIMER_IRQ_EN(val) BIT(val)
-+#define TIMER_IRQ_ST_REG 0x04
-+#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
-+#define TIMER_CTL_ENABLE BIT(0)
-+#define TIMER_CTL_RELOAD BIT(1)
-+#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
-+#define TIMER_CTL_ONESHOT BIT(7)
-+#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
-+#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
-+#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
-+#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
-+
-+#define TIMER_SYNC_TICKS 3
-+
-+static void __iomem *timer_base;
-+static u32 ticks_per_jiffy;
-+
-+/*
-+ * When we disable a timer, we need to wait at least for 2 cycles of
-+ * the timer source clock. We will use for that the clocksource timer
-+ * that is already setup and runs at the same frequency than the other
-+ * timers, and we never will be disabled.
-+ */
-+static void sun5i_clkevt_sync(void)
-+{
-+ u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1));
-+
-+ while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
-+ cpu_relax();
-+}
-+
-+static void sun5i_clkevt_time_stop(u8 timer)
-+{
-+ u32 val = readl(timer_base + TIMER_CTL_REG(timer));
-+ writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
-+
-+ sun5i_clkevt_sync();
-+}
-+
-+static void sun5i_clkevt_time_setup(u8 timer, u32 delay)
-+{
-+ writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
-+}
-+
-+static void sun5i_clkevt_time_start(u8 timer, bool periodic)
-+{
-+ u32 val = readl(timer_base + TIMER_CTL_REG(timer));
-+
-+ if (periodic)
-+ val &= ~TIMER_CTL_ONESHOT;
-+ else
-+ val |= TIMER_CTL_ONESHOT;
-+
-+ writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
-+ timer_base + TIMER_CTL_REG(timer));
-+}
-+
-+static void sun5i_clkevt_mode(enum clock_event_mode mode,
-+ struct clock_event_device *clk)
-+{
-+ switch (mode) {
-+ case CLOCK_EVT_MODE_PERIODIC:
-+ sun5i_clkevt_time_stop(0);
-+ sun5i_clkevt_time_setup(0, ticks_per_jiffy);
-+ sun5i_clkevt_time_start(0, true);
-+ break;
-+ case CLOCK_EVT_MODE_ONESHOT:
-+ sun5i_clkevt_time_stop(0);
-+ sun5i_clkevt_time_start(0, false);
-+ break;
-+ case CLOCK_EVT_MODE_UNUSED:
-+ case CLOCK_EVT_MODE_SHUTDOWN:
-+ default:
-+ sun5i_clkevt_time_stop(0);
-+ break;
-+ }
-+}
-+
-+static int sun5i_clkevt_next_event(unsigned long evt,
-+ struct clock_event_device *unused)
-+{
-+ sun5i_clkevt_time_stop(0);
-+ sun5i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
-+ sun5i_clkevt_time_start(0, false);
-+
-+ return 0;
-+}
-+
-+static struct clock_event_device sun5i_clockevent = {
-+ .name = "sun5i_tick",
-+ .rating = 340,
-+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-+ .set_mode = sun5i_clkevt_mode,
-+ .set_next_event = sun5i_clkevt_next_event,
-+};
-+
-+
-+static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
-+{
-+ struct clock_event_device *evt = (struct clock_event_device *)dev_id;
-+
-+ writel(0x1, timer_base + TIMER_IRQ_ST_REG);
-+ evt->event_handler(evt);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction sun5i_timer_irq = {
-+ .name = "sun5i_timer0",
-+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
-+ .handler = sun5i_timer_interrupt,
-+ .dev_id = &sun5i_clockevent,
-+};
-+
-+static u32 sun5i_timer_sched_read(void)
-+{
-+ return ~readl(timer_base + TIMER_CNTVAL_LO_REG(1));
-+}
-+
-+static void __init sun5i_timer_init(struct device_node *node)
-+{
-+ unsigned long rate;
-+ struct clk *clk;
-+ int ret, irq;
-+ u32 val;
-+
-+ timer_base = of_iomap(node, 0);
-+ if (!timer_base)
-+ panic("Can't map registers");
-+
-+ irq = irq_of_parse_and_map(node, 0);
-+ if (irq <= 0)
-+ panic("Can't parse IRQ");
-+
-+ clk = of_clk_get(node, 0);
-+ if (IS_ERR(clk))
-+ panic("Can't get timer clock");
-+ clk_prepare_enable(clk);
-+ rate = clk_get_rate(clk);
-+
-+ writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
-+ writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
-+ timer_base + TIMER_CTL_REG(1));
-+
-+ setup_sched_clock(sun5i_timer_sched_read, 32, rate);
-+ clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name,
-+ rate, 340, 32, clocksource_mmio_readl_down);
-+
-+ ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
-+
-+ ret = setup_irq(irq, &sun5i_timer_irq);
-+ if (ret)
-+ pr_warn("failed to setup irq %d\n", irq);
-+
-+ /* Enable timer0 interrupt */
-+ val = readl(timer_base + TIMER_IRQ_EN_REG);
-+ writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
-+
-+ sun5i_clockevent.cpumask = cpu_possible_mask;
-+ sun5i_clockevent.irq = irq;
-+
-+ clockevents_config_and_register(&sun5i_clockevent, rate,
-+ TIMER_SYNC_TICKS, 0xffffffff);
-+}
-+CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
-+ sun5i_timer_init);
-+CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
-+ sun5i_timer_init);
+++ /dev/null
-From 5ace5467690055b1772dcac69dd1377735b8a34b Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:01:48 +0100
-Subject: [PATCH] ARM: sun5i: a10s: Add support for the High Speed Timers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The Allwinner A10s has support for two high speed timers. Now that we
-have a driver to support it, we can enable them in the device tree.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Tested-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -454,5 +454,12 @@
- clock-frequency = <100000>;
- status = "disabled";
- };
-+
-+ timer@01c60000 {
-+ compatible = "allwinner,sun5i-a13-hstimer";
-+ reg = <0x01c60000 0x1000>;
-+ interrupts = <82>, <83>;
-+ clocks = <&ahb_gates 28>;
-+ };
- };
- };
+++ /dev/null
-From 22a3eff19679e0e592e061201690670a2f5fdba7 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:01:48 +0100
-Subject: [PATCH] ARM: sun5i: a13: Add support for the High Speed Timers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The Allwinner A13 has support for two high speed timers. Now that we
-have a driver to support it, we can enable them in the device tree.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Tested-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -391,5 +391,12 @@
- clock-frequency = <100000>;
- status = "disabled";
- };
-+
-+ timer@01c60000 {
-+ compatible = "allwinner,sun5i-a13-hstimer";
-+ reg = <0x01c60000 0x1000>;
-+ interrupts = <82>, <83>;
-+ clocks = <&ahb_gates 28>;
-+ };
- };
- };
+++ /dev/null
-From 6c23e1fa6bd220b8f5665c150c83d4c016d95482 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:01:48 +0100
-Subject: [PATCH] ARM: sun7i: a20: Add support for the High Speed Timers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The Allwinner A20 has support for four high speed timers. Apart for the
-number of timers (4 vs 2), it's basically the same logic than the high
-speed timers found in the sun5i chips.
-
-Now that we have a driver to support it, we can enable them in the
-device tree.
-
-[dlezcano] : Fixed conflict with 428abbb8 "Enable the I2C controllers"
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Tested-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -552,6 +552,16 @@
- status = "disabled";
- };
-
-+ hstimer@01c60000 {
-+ compatible = "allwinner,sun7i-a20-hstimer";
-+ reg = <0x01c60000 0x1000>;
-+ interrupts = <0 81 4>,
-+ <0 82 4>,
-+ <0 83 4>,
-+ <0 84 4>;
-+ clocks = <&ahb_gates 28>;
-+ };
-+
- gic: interrupt-controller@01c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
- reg = <0x01c81000 0x1000>,
+++ /dev/null
-From 28a9c5d93113cab73dd3a4b4a74a983151c08b9d Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Fri, 20 Dec 2013 22:41:09 +0100
-Subject: [PATCH] ARM: sun6i: a31: Add support for the High Speed Timers
-
-The Allwinner A31 has support for four high speed timers. Apart for the
-number of timers (4 vs 2), it's basically the same logic than the high
-speed timers found in the sun5i chips.
-
-Now that we have a driver to support it, we can enable them in the
-device tree.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -312,6 +312,17 @@
- status = "disabled";
- };
-
-+ hstimer@01c60000 {
-+ compatible = "allwinner,sun7i-a20-hstimer";
-+ reg = <0x01c60000 0x1000>;
-+ interrupts = <0 51 4>,
-+ <0 52 4>,
-+ <0 53 4>,
-+ <0 54 4>;
-+ clocks = <&ahb1_gates 19>;
-+ resets = <&ahb1_rst 19>;
-+ };
-+
- gic: interrupt-controller@01c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
- reg = <0x01c81000 0x1000>,
+++ /dev/null
-From bc7a0478e6dac1304fdfdb6f3056f438b632da62 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:48 +0800
-Subject: [PATCH] ARM: dts: sun7i: Add GMAC clock node to sun7i DTSI
-
-The GMAC uses 1 of 2 sources for its transmit clock, depending on the
-PHY interface mode. Add both sources as dummy clocks, and as parents
-to the GMAC clock node.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index cefd7ac..7d98edc 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -322,6 +322,34 @@
- };
-
- /*
-+ * The following two are dummy clocks, placeholders used in the gmac_tx
-+ * clock. The gmac driver will choose one parent depending on the PHY
-+ * interface mode, using clk_set_rate auto-reparenting.
-+ * The actual TX clock rate is not controlled by the gmac_tx clock.
-+ */
-+ mii_phy_tx_clk: clk@2 {
-+ #clock-cells = <0>;
-+ compatible = "fixed-clock";
-+ clock-frequency = <25000000>;
-+ clock-output-names = "mii_phy_tx";
-+ };
-+
-+ gmac_int_tx_clk: clk@3 {
-+ #clock-cells = <0>;
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ clock-output-names = "gmac_int_tx";
-+ };
-+
-+ gmac_tx_clk: clk@01c20164 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun7i-a20-gmac-clk";
-+ reg = <0x01c20164 0x4>;
-+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
-+ clock-output-names = "gmac_tx";
-+ };
-+
-+ /*
- * Dummy clock used by output clocks
- */
- osc24M_32k: clk@1 {
---
-1.8.5.5
-
+++ /dev/null
-From 7584e81f6d9fecf0ad6e2854654b183432adb918 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:49 +0800
-Subject: [PATCH] ARM: dts: sun7i: Add GMAC controller node to sun7i DTSI
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 7d98edc..87eab0d 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -645,6 +645,21 @@
- status = "disabled";
- };
-
-+ gmac: ethernet@01c50000 {
-+ compatible = "allwinner,sun7i-a20-gmac";
-+ reg = <0x01c50000 0x10000>;
-+ interrupts = <0 85 4>;
-+ interrupt-names = "macirq";
-+ clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
-+ clock-names = "stmmaceth", "allwinner_gmac_tx";
-+ snps,pbl = <2>;
-+ snps,fixed-burst;
-+ snps,force_sf_dma_mode;
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- hstimer@01c60000 {
- compatible = "allwinner,sun7i-a20-hstimer";
- reg = <0x01c60000 0x1000>;
---
-1.8.5.5
-
+++ /dev/null
-From 249ac8d24efdc07f521b796b96796ffa55abe0a5 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:50 +0800
-Subject: [PATCH] ARM: dts: sun7i: Add pin muxing options for the GMAC
-
-The A20 has EMAC and GMAC muxed on the same pins.
-Add pin sets with gmac function for MII and RGMII mode to the DTSI.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 87eab0d..9bb6fdf 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -484,6 +484,32 @@
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-+
-+ gmac_pins_mii_a: gmac_mii@0 {
-+ allwinner,pins = "PA0", "PA1", "PA2",
-+ "PA3", "PA4", "PA5", "PA6",
-+ "PA7", "PA8", "PA9", "PA10",
-+ "PA11", "PA12", "PA13", "PA14",
-+ "PA15", "PA16";
-+ allwinner,function = "gmac";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ gmac_pins_rgmii_a: gmac_rgmii@0 {
-+ allwinner,pins = "PA0", "PA1", "PA2",
-+ "PA3", "PA4", "PA5", "PA6",
-+ "PA7", "PA8", "PA10",
-+ "PA11", "PA12", "PA13",
-+ "PA15", "PA16";
-+ allwinner,function = "gmac";
-+ /*
-+ * data lines in RGMII mode use DDR mode
-+ * and need a higher signal drive strength
-+ */
-+ allwinner,drive = <3>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- timer@01c20c00 {
---
-1.8.5.5
-
+++ /dev/null
-From 33ba4079ea8c611c1aeca34f2d6d53a8214c14c5 Mon Sep 17 00:00:00 2001
-From: Rashika Kheria <rashika.kheria@gmail.com>
-Date: Thu, 19 Dec 2013 14:19:44 +0530
-Subject: [PATCH] drivers: net: Mark functions as static in stmmac_platform.c
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This patch marks the function stmmac_pltfr_freeze() and
-stmmac_pltfr_restore() in stmmac_platform.c as static because they are
-not used outside this file.
-
-Thus, it also removes the following warnings in
-ethernet/stmicro/stmmac/stmmac_platform.c:
-
-drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:222:5: warning: no previous prototype for ‘stmmac_pltfr_freeze’ [-Wmissing-prototypes]
-drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:236:5: warning: no previous prototype for ‘stmmac_pltfr_restore’ [-Wmissing-prototypes]
-
-Signed-off-by: Rashika Kheria <rashika.kheria@gmail.com>
-Reviewed-by: Josh Triplett <josh@joshtriplett.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 51c9069..38bd1f4 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -219,7 +219,7 @@ static int stmmac_pltfr_resume(struct device *dev)
- return stmmac_resume(ndev);
- }
-
--int stmmac_pltfr_freeze(struct device *dev)
-+static int stmmac_pltfr_freeze(struct device *dev)
- {
- int ret;
- struct plat_stmmacenet_data *plat_dat = dev_get_platdata(dev);
-@@ -233,7 +233,7 @@ int stmmac_pltfr_freeze(struct device *dev)
- return ret;
- }
-
--int stmmac_pltfr_restore(struct device *dev)
-+static int stmmac_pltfr_restore(struct device *dev)
- {
- struct plat_stmmacenet_data *plat_dat = dev_get_platdata(dev);
- struct net_device *ndev = dev_get_drvdata(dev);
---
-1.8.5.5
-
+++ /dev/null
-From 9cbadf094d9d479413dc8cfa77dff9e732184337 Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:51:43 +0000
-Subject: [PATCH] net: stmmac: support max-speed device tree property
-
-This patch adds support to "max-speed" property which is a standard
-Ethernet device tree property. max-speed specifies maximum speed
-(specified in megabits per second) supported the device.
-
-Depending on the clocking schemes some of the boards can only support
-few link speeds, so having a way to limit the link speed in the mac
-driver would allow such setups to work reliably.
-
-Without this patch there is no way to tell the driver to limit the
-link speed.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 +++-
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ++++
- include/linux/stmmac.h | 1 +
- 3 files changed, 8 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index ecdc8ab..15192c0 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -776,6 +776,7 @@ static int stmmac_init_phy(struct net_device *dev)
- char phy_id_fmt[MII_BUS_ID_SIZE + 3];
- char bus_id[MII_BUS_ID_SIZE];
- int interface = priv->plat->interface;
-+ int max_speed = priv->plat->max_speed;
- priv->oldlink = 0;
- priv->speed = 0;
- priv->oldduplex = -1;
-@@ -800,7 +801,8 @@ static int stmmac_init_phy(struct net_device *dev)
-
- /* Stop Advertising 1000BASE Capability if interface is not GMII */
- if ((interface == PHY_INTERFACE_MODE_MII) ||
-- (interface == PHY_INTERFACE_MODE_RMII))
-+ (interface == PHY_INTERFACE_MODE_RMII) ||
-+ (max_speed < 1000 && max_speed > 0))
- phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
- SUPPORTED_1000baseT_Full);
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 38bd1f4..9377ee6 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -42,6 +42,10 @@ static int stmmac_probe_config_dt(struct platform_device *pdev,
- *mac = of_get_mac_address(np);
- plat->interface = of_get_phy_mode(np);
-
-+ /* Get max speed of operation from device tree */
-+ if (of_property_read_u32(np, "max-speed", &plat->max_speed))
-+ plat->max_speed = -1;
-+
- plat->bus_id = of_alias_get_id(np, "ethernet");
- if (plat->bus_id < 0)
- plat->bus_id = 0;
-diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
-index bb5deb0..33ace71 100644
---- a/include/linux/stmmac.h
-+++ b/include/linux/stmmac.h
-@@ -110,6 +110,7 @@ struct plat_stmmacenet_data {
- int force_sf_dma_mode;
- int force_thresh_dma_mode;
- int riwt_off;
-+ int max_speed;
- void (*fix_mac_speed)(void *priv, unsigned int speed);
- void (*bus_setup)(void __iomem *ioaddr);
- int (*init)(struct platform_device *pdev);
---
-1.8.5.5
-
+++ /dev/null
-From 984203ceff27e9d6d94fbae4b043fc9afb658121 Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:51:58 +0000
-Subject: [PATCH] net: stmmac: mdio: remove reset gpio free
-
-This patch removes gpio_free for reset line of the phy, driver stores
-the gpio number in its private data-structure to use in future. As the
-driver uses this pin in future this pin should not be freed.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
-index fe7bc99..aab12d2 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
-@@ -166,7 +166,6 @@ static int stmmac_mdio_reset(struct mii_bus *bus)
- udelay(data->delays[1]);
- gpio_set_value(reset_gpio, active_low ? 1 : 0);
- udelay(data->delays[2]);
-- gpio_free(reset_gpio);
- }
- }
- #endif
---
-1.8.5.5
-
+++ /dev/null
-From 09f8d6960b69e474eef9d2aebdd0d536d00af0c8 Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:52:06 +0000
-Subject: [PATCH] net: stmmac: move dma allocation to new function
-
-This patch moves dma resource allocation to a new function
-alloc_dma_desc_resources, the reason for moving this to a new function
-is to keep the memory allocations in a separate function. One more reason
-it to get suspend and hibernation cases working without releasing and
-allocating these resources during suspend-resume and freeze-restore
-cases.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 169 +++++++++++-----------
- 1 file changed, 85 insertions(+), 84 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index 15192c0..532f2b4 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -996,66 +996,6 @@ static int init_dma_desc_rings(struct net_device *dev)
- pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
- txsize, rxsize, bfsize);
-
-- if (priv->extend_desc) {
-- priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
-- sizeof(struct
-- dma_extended_desc),
-- &priv->dma_rx_phy,
-- GFP_KERNEL);
-- if (!priv->dma_erx)
-- goto err_dma;
--
-- priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
-- sizeof(struct
-- dma_extended_desc),
-- &priv->dma_tx_phy,
-- GFP_KERNEL);
-- if (!priv->dma_etx) {
-- dma_free_coherent(priv->device, priv->dma_rx_size *
-- sizeof(struct dma_extended_desc),
-- priv->dma_erx, priv->dma_rx_phy);
-- goto err_dma;
-- }
-- } else {
-- priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
-- sizeof(struct dma_desc),
-- &priv->dma_rx_phy,
-- GFP_KERNEL);
-- if (!priv->dma_rx)
-- goto err_dma;
--
-- priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
-- sizeof(struct dma_desc),
-- &priv->dma_tx_phy,
-- GFP_KERNEL);
-- if (!priv->dma_tx) {
-- dma_free_coherent(priv->device, priv->dma_rx_size *
-- sizeof(struct dma_desc),
-- priv->dma_rx, priv->dma_rx_phy);
-- goto err_dma;
-- }
-- }
--
-- priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
-- GFP_KERNEL);
-- if (!priv->rx_skbuff_dma)
-- goto err_rx_skbuff_dma;
--
-- priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
-- GFP_KERNEL);
-- if (!priv->rx_skbuff)
-- goto err_rx_skbuff;
--
-- priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
-- GFP_KERNEL);
-- if (!priv->tx_skbuff_dma)
-- goto err_tx_skbuff_dma;
--
-- priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
-- GFP_KERNEL);
-- if (!priv->tx_skbuff)
-- goto err_tx_skbuff;
--
- if (netif_msg_probe(priv)) {
- pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
- (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
-@@ -1123,30 +1063,6 @@ static int init_dma_desc_rings(struct net_device *dev)
- err_init_rx_buffers:
- while (--i >= 0)
- stmmac_free_rx_buffers(priv, i);
-- kfree(priv->tx_skbuff);
--err_tx_skbuff:
-- kfree(priv->tx_skbuff_dma);
--err_tx_skbuff_dma:
-- kfree(priv->rx_skbuff);
--err_rx_skbuff:
-- kfree(priv->rx_skbuff_dma);
--err_rx_skbuff_dma:
-- if (priv->extend_desc) {
-- dma_free_coherent(priv->device, priv->dma_tx_size *
-- sizeof(struct dma_extended_desc),
-- priv->dma_etx, priv->dma_tx_phy);
-- dma_free_coherent(priv->device, priv->dma_rx_size *
-- sizeof(struct dma_extended_desc),
-- priv->dma_erx, priv->dma_rx_phy);
-- } else {
-- dma_free_coherent(priv->device,
-- priv->dma_tx_size * sizeof(struct dma_desc),
-- priv->dma_tx, priv->dma_tx_phy);
-- dma_free_coherent(priv->device,
-- priv->dma_rx_size * sizeof(struct dma_desc),
-- priv->dma_rx, priv->dma_rx_phy);
-- }
--err_dma:
- return ret;
- }
-
-@@ -1182,6 +1098,85 @@ static void dma_free_tx_skbufs(struct stmmac_priv *priv)
- }
- }
-
-+static int alloc_dma_desc_resources(struct stmmac_priv *priv)
-+{
-+ unsigned int txsize = priv->dma_tx_size;
-+ unsigned int rxsize = priv->dma_rx_size;
-+ int ret = -ENOMEM;
-+
-+ priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
-+ GFP_KERNEL);
-+ if (!priv->rx_skbuff_dma)
-+ return -ENOMEM;
-+
-+ priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
-+ GFP_KERNEL);
-+ if (!priv->rx_skbuff)
-+ goto err_rx_skbuff;
-+
-+ priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
-+ GFP_KERNEL);
-+ if (!priv->tx_skbuff_dma)
-+ goto err_tx_skbuff_dma;
-+
-+ priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
-+ GFP_KERNEL);
-+ if (!priv->tx_skbuff)
-+ goto err_tx_skbuff;
-+
-+ if (priv->extend_desc) {
-+ priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
-+ sizeof(struct
-+ dma_extended_desc),
-+ &priv->dma_rx_phy,
-+ GFP_KERNEL);
-+ if (!priv->dma_erx)
-+ goto err_dma;
-+
-+ priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
-+ sizeof(struct
-+ dma_extended_desc),
-+ &priv->dma_tx_phy,
-+ GFP_KERNEL);
-+ if (!priv->dma_etx) {
-+ dma_free_coherent(priv->device, priv->dma_rx_size *
-+ sizeof(struct dma_extended_desc),
-+ priv->dma_erx, priv->dma_rx_phy);
-+ goto err_dma;
-+ }
-+ } else {
-+ priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
-+ sizeof(struct dma_desc),
-+ &priv->dma_rx_phy,
-+ GFP_KERNEL);
-+ if (!priv->dma_rx)
-+ goto err_dma;
-+
-+ priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
-+ sizeof(struct dma_desc),
-+ &priv->dma_tx_phy,
-+ GFP_KERNEL);
-+ if (!priv->dma_tx) {
-+ dma_free_coherent(priv->device, priv->dma_rx_size *
-+ sizeof(struct dma_desc),
-+ priv->dma_rx, priv->dma_rx_phy);
-+ goto err_dma;
-+ }
-+ }
-+
-+ return 0;
-+
-+err_dma:
-+ kfree(priv->tx_skbuff);
-+err_tx_skbuff:
-+ kfree(priv->tx_skbuff_dma);
-+err_tx_skbuff_dma:
-+ kfree(priv->rx_skbuff);
-+err_rx_skbuff:
-+ kfree(priv->rx_skbuff_dma);
-+ return ret;
-+}
-+
- static void free_dma_desc_resources(struct stmmac_priv *priv)
- {
- /* Release the DMA TX/RX socket buffers */
-@@ -1623,6 +1618,12 @@ static int stmmac_open(struct net_device *dev)
- priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
- priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
-
-+ alloc_dma_desc_resources(priv);
-+ if (ret < 0) {
-+ pr_err("%s: DMA descriptors allocation failed\n", __func__);
-+ goto dma_desc_error;
-+ }
-+
- ret = init_dma_desc_rings(dev);
- if (ret < 0) {
- pr_err("%s: DMA descriptors initialization failed\n", __func__);
---
-1.8.5.5
-
+++ /dev/null
-From 523f11b5d4fd72efb72b04cd7006bfd1d1d4f341 Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:52:14 +0000
-Subject: [PATCH] net: stmmac: move hardware setup for stmmac_open to new
- function
-
-This patch moves hardware setup part of the code in stmmac_open to a new
-function stmmac_hw_setup, the reason for doing this is to make hw
-initialization independent function so that PM functions can re-use it to
-re-initialize the IP after returning from low power state.
-This will also avoid code duplication across stmmac_resume/restore and
-stmmac_open.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 155 ++++++++++++----------
- 1 file changed, 88 insertions(+), 67 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index 532f2b4..341c8dc3 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -1586,6 +1586,86 @@ static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
- }
-
- /**
-+ * stmmac_hw_setup: setup mac in a usable state.
-+ * @dev : pointer to the device structure.
-+ * Description:
-+ * This function sets up the ip in a usable state.
-+ * Return value:
-+ * 0 on success and an appropriate (-)ve integer as defined in errno.h
-+ * file on failure.
-+ */
-+static int stmmac_hw_setup(struct net_device *dev)
-+{
-+ struct stmmac_priv *priv = netdev_priv(dev);
-+ int ret;
-+
-+ ret = init_dma_desc_rings(dev);
-+ if (ret < 0) {
-+ pr_err("%s: DMA descriptors initialization failed\n", __func__);
-+ return ret;
-+ }
-+ /* DMA initialization and SW reset */
-+ ret = stmmac_init_dma_engine(priv);
-+ if (ret < 0) {
-+ pr_err("%s: DMA engine initialization failed\n", __func__);
-+ return ret;
-+ }
-+
-+ /* Copy the MAC addr into the HW */
-+ priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
-+
-+ /* If required, perform hw setup of the bus. */
-+ if (priv->plat->bus_setup)
-+ priv->plat->bus_setup(priv->ioaddr);
-+
-+ /* Initialize the MAC Core */
-+ priv->hw->mac->core_init(priv->ioaddr);
-+
-+ /* Enable the MAC Rx/Tx */
-+ stmmac_set_mac(priv->ioaddr, true);
-+
-+ /* Set the HW DMA mode and the COE */
-+ stmmac_dma_operation_mode(priv);
-+
-+ stmmac_mmc_setup(priv);
-+
-+ ret = stmmac_init_ptp(priv);
-+ if (ret)
-+ pr_warn("%s: failed PTP initialisation\n", __func__);
-+
-+#ifdef CONFIG_STMMAC_DEBUG_FS
-+ ret = stmmac_init_fs(dev);
-+ if (ret < 0)
-+ pr_warn("%s: failed debugFS registration\n", __func__);
-+#endif
-+ /* Start the ball rolling... */
-+ pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
-+ priv->hw->dma->start_tx(priv->ioaddr);
-+ priv->hw->dma->start_rx(priv->ioaddr);
-+
-+ /* Dump DMA/MAC registers */
-+ if (netif_msg_hw(priv)) {
-+ priv->hw->mac->dump_regs(priv->ioaddr);
-+ priv->hw->dma->dump_regs(priv->ioaddr);
-+ }
-+ priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
-+
-+ priv->eee_enabled = stmmac_eee_init(priv);
-+
-+ stmmac_init_tx_coalesce(priv);
-+
-+ if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
-+ priv->rx_riwt = MAX_DMA_RIWT;
-+ priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
-+ }
-+
-+ if (priv->pcs && priv->hw->mac->ctrl_ane)
-+ priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
-+
-+ return 0;
-+}
-+
-+/**
- * stmmac_open - open entry point of the driver
- * @dev : pointer to the device structure.
- * Description:
-@@ -1613,6 +1693,10 @@ static int stmmac_open(struct net_device *dev)
- }
- }
-
-+ /* Extra statistics */
-+ memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
-+ priv->xstats.threshold = tc;
-+
- /* Create and initialize the TX/RX descriptors chains. */
- priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
- priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
-@@ -1624,28 +1708,14 @@ static int stmmac_open(struct net_device *dev)
- goto dma_desc_error;
- }
-
-- ret = init_dma_desc_rings(dev);
-+ ret = stmmac_hw_setup(dev);
- if (ret < 0) {
-- pr_err("%s: DMA descriptors initialization failed\n", __func__);
-- goto dma_desc_error;
-- }
--
-- /* DMA initialization and SW reset */
-- ret = stmmac_init_dma_engine(priv);
-- if (ret < 0) {
-- pr_err("%s: DMA engine initialization failed\n", __func__);
-+ pr_err("%s: Hw setup failed\n", __func__);
- goto init_error;
- }
-
-- /* Copy the MAC addr into the HW */
-- priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
--
-- /* If required, perform hw setup of the bus. */
-- if (priv->plat->bus_setup)
-- priv->plat->bus_setup(priv->ioaddr);
--
-- /* Initialize the MAC Core */
-- priv->hw->mac->core_init(priv->ioaddr);
-+ if (priv->phydev)
-+ phy_start(priv->phydev);
-
- /* Request the IRQ lines */
- ret = request_irq(dev->irq, stmmac_interrupt,
-@@ -1678,55 +1748,6 @@ static int stmmac_open(struct net_device *dev)
- }
- }
-
-- /* Enable the MAC Rx/Tx */
-- stmmac_set_mac(priv->ioaddr, true);
--
-- /* Set the HW DMA mode and the COE */
-- stmmac_dma_operation_mode(priv);
--
-- /* Extra statistics */
-- memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
-- priv->xstats.threshold = tc;
--
-- stmmac_mmc_setup(priv);
--
-- ret = stmmac_init_ptp(priv);
-- if (ret)
-- pr_warn("%s: failed PTP initialisation\n", __func__);
--
--#ifdef CONFIG_STMMAC_DEBUG_FS
-- ret = stmmac_init_fs(dev);
-- if (ret < 0)
-- pr_warn("%s: failed debugFS registration\n", __func__);
--#endif
-- /* Start the ball rolling... */
-- pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
-- priv->hw->dma->start_tx(priv->ioaddr);
-- priv->hw->dma->start_rx(priv->ioaddr);
--
-- /* Dump DMA/MAC registers */
-- if (netif_msg_hw(priv)) {
-- priv->hw->mac->dump_regs(priv->ioaddr);
-- priv->hw->dma->dump_regs(priv->ioaddr);
-- }
--
-- if (priv->phydev)
-- phy_start(priv->phydev);
--
-- priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
--
-- priv->eee_enabled = stmmac_eee_init(priv);
--
-- stmmac_init_tx_coalesce(priv);
--
-- if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
-- priv->rx_riwt = MAX_DMA_RIWT;
-- priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
-- }
--
-- if (priv->pcs && priv->hw->mac->ctrl_ane)
-- priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
--
- napi_enable(&priv->napi);
- netif_start_queue(dev);
-
---
-1.8.5.5
-
+++ /dev/null
-From 073752aa59b3db120b2508d5bdd0598ada25fd25 Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:52:27 +0000
-Subject: [PATCH] net: stmmac: make stmmac_mdio_reset non-static
-
-This patch promotes stmmac_mdio_reset function from static to
-non-static, so that power management functions can decide to reset if
-the IP comes out from lowe power state specially hibernation cases.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
- drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 2 +-
- 2 files changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-index 92be6b3..5a568015 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-@@ -110,6 +110,7 @@ struct stmmac_priv {
-
- int stmmac_mdio_unregister(struct net_device *ndev);
- int stmmac_mdio_register(struct net_device *ndev);
-+int stmmac_mdio_reset(struct mii_bus *mii);
- void stmmac_set_ethtool_ops(struct net_device *netdev);
- extern const struct stmmac_desc_ops enh_desc_ops;
- extern const struct stmmac_desc_ops ndesc_ops;
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
-index aab12d2..a468eb1 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
-@@ -128,7 +128,7 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
- * @bus: points to the mii_bus structure
- * Description: reset the MII bus
- */
--static int stmmac_mdio_reset(struct mii_bus *bus)
-+int stmmac_mdio_reset(struct mii_bus *bus)
- {
- #if defined(CONFIG_STMMAC_PLATFORM)
- struct net_device *ndev = bus->priv;
---
-1.8.5.5
-
+++ /dev/null
-From 623997fb90eab7a135c2c68a332c8450a488baca Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:52:35 +0000
-Subject: [PATCH] net: stmmac: fix power management suspend-resume case
-
-The driver PM resume assumes that the IP is still powered up and the
-all the register contents are not disturbed when it comes out of low
-power suspend case. This assumption is wrong, basically the driver
-should not consider any state of registers after it comes out of low
-power. However driver can keep the part of the IP powered up if its a
-wake up source. But it can not assume the register state of the IP. Also
-its possible that SOC glue layer can take the power off the IP if its
-not wake-up source to reduce the power consumption.
-
-This patch re initializes hardware by calling stmmac_hw_setup function in
-resume case.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 13 +++++++------
- 1 file changed, 7 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index 341c8dc3..742a83f 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2887,18 +2887,19 @@ int stmmac_resume(struct net_device *ndev)
- * this bit because it can generate problems while resuming
- * from another devices (e.g. serial console).
- */
-- if (device_may_wakeup(priv->device))
-+ if (device_may_wakeup(priv->device)) {
- priv->hw->mac->pmt(priv->ioaddr, 0);
-- else
-+ } else {
- /* enable the clk prevously disabled */
- clk_prepare_enable(priv->stmmac_clk);
-+ /* reset the phy so that it's ready */
-+ if (priv->mii)
-+ stmmac_mdio_reset(priv->mii);
-+ }
-
- netif_device_attach(ndev);
-
-- /* Enable the MAC and DMA */
-- stmmac_set_mac(priv->ioaddr, true);
-- priv->hw->dma->start_tx(priv->ioaddr);
-- priv->hw->dma->start_rx(priv->ioaddr);
-+ stmmac_hw_setup(ndev);
-
- napi_enable(&priv->napi);
-
---
-1.8.5.5
-
+++ /dev/null
-From 33a23e223749c45ff8099ff9baa235301a3ad07f Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:52:44 +0000
-Subject: [PATCH] net: stmmac: use suspend functions for hibernation
-
-In hibernation freeze case the driver just releases the resources like
-dma buffers, irqs, unregisters the drivers and during restore it does
-register, request the resources. This is not really necessary, as part
-of power management all the data structures are intact, all the
-previously allocated resources can be used after coming out of low
-power.
-
-This patch uses the suspend and resume callbacks for freeze and
-restore which initializes the hardware correctly without unregistering
-or releasing the resources, this should also help in reducing the time
-to restore.
-
-Also this patch fixes a bug in stmmac_pltfr_restore and
-stmmac_pltfr_freeze where it tries to get hold of platform data via
-dev_get_platdata call, which would return NULL in device tree cases and
-the next if statement would crash as there is no NULL check.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 -
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 16 --------
- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 44 ++++++----------------
- 3 files changed, 12 insertions(+), 50 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-index 5a568015..027f1dd 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-@@ -117,8 +117,6 @@ struct stmmac_priv {
- extern const struct stmmac_hwtimestamp stmmac_ptp;
- int stmmac_ptp_register(struct stmmac_priv *priv);
- void stmmac_ptp_unregister(struct stmmac_priv *priv);
--int stmmac_freeze(struct net_device *ndev);
--int stmmac_restore(struct net_device *ndev);
- int stmmac_resume(struct net_device *ndev);
- int stmmac_suspend(struct net_device *ndev);
- int stmmac_dvr_remove(struct net_device *ndev);
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index 742a83f..c1298a0 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2912,22 +2912,6 @@ int stmmac_resume(struct net_device *ndev)
-
- return 0;
- }
--
--int stmmac_freeze(struct net_device *ndev)
--{
-- if (!ndev || !netif_running(ndev))
-- return 0;
--
-- return stmmac_release(ndev);
--}
--
--int stmmac_restore(struct net_device *ndev)
--{
-- if (!ndev || !netif_running(ndev))
-- return 0;
--
-- return stmmac_open(ndev);
--}
- #endif /* CONFIG_PM */
-
- /* Driver can be configured w/ and w/ both PCI and Platf drivers
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 9377ee6..6d0bf22 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -211,55 +211,35 @@ static int stmmac_pltfr_remove(struct platform_device *pdev)
- #ifdef CONFIG_PM
- static int stmmac_pltfr_suspend(struct device *dev)
- {
-- struct net_device *ndev = dev_get_drvdata(dev);
--
-- return stmmac_suspend(ndev);
--}
--
--static int stmmac_pltfr_resume(struct device *dev)
--{
-- struct net_device *ndev = dev_get_drvdata(dev);
--
-- return stmmac_resume(ndev);
--}
--
--static int stmmac_pltfr_freeze(struct device *dev)
--{
- int ret;
-- struct plat_stmmacenet_data *plat_dat = dev_get_platdata(dev);
- struct net_device *ndev = dev_get_drvdata(dev);
-+ struct stmmac_priv *priv = netdev_priv(ndev);
- struct platform_device *pdev = to_platform_device(dev);
-
-- ret = stmmac_freeze(ndev);
-- if (plat_dat->exit)
-- plat_dat->exit(pdev);
-+ ret = stmmac_suspend(ndev);
-+ if (priv->plat->exit)
-+ priv->plat->exit(pdev);
-
- return ret;
- }
-
--static int stmmac_pltfr_restore(struct device *dev)
-+static int stmmac_pltfr_resume(struct device *dev)
- {
-- struct plat_stmmacenet_data *plat_dat = dev_get_platdata(dev);
- struct net_device *ndev = dev_get_drvdata(dev);
-+ struct stmmac_priv *priv = netdev_priv(ndev);
- struct platform_device *pdev = to_platform_device(dev);
-
-- if (plat_dat->init)
-- plat_dat->init(pdev);
-+ if (priv->plat->init)
-+ priv->plat->init(pdev);
-
-- return stmmac_restore(ndev);
-+ return stmmac_resume(ndev);
- }
-
--static const struct dev_pm_ops stmmac_pltfr_pm_ops = {
-- .suspend = stmmac_pltfr_suspend,
-- .resume = stmmac_pltfr_resume,
-- .freeze = stmmac_pltfr_freeze,
-- .thaw = stmmac_pltfr_restore,
-- .restore = stmmac_pltfr_restore,
--};
--#else
--static const struct dev_pm_ops stmmac_pltfr_pm_ops;
- #endif /* CONFIG_PM */
-
-+static SIMPLE_DEV_PM_OPS(stmmac_pltfr_pm_ops,
-+ stmmac_pltfr_suspend, stmmac_pltfr_resume);
-+
- static const struct of_device_id stmmac_dt_ids[] = {
- { .compatible = "st,spear600-gmac"},
- { .compatible = "snps,dwmac-3.610"},
---
-1.8.5.5
-
+++ /dev/null
-From db88f10ad6a84c5bcb71bf51f0988a4bb1733bea Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:52:52 +0000
-Subject: [PATCH] net: stmmac: restore pinstate in pm resume.
-
-This patch adds code to restore default pinstate of the pins when it
-comes back from low power state. Without this patch the state of the
-pins would be unknown and the driver would not work.
-
-This patch also adds code to put the pins in to sleep state when the
-driver enters low power state.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index c1298a0..df7d8d6 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -43,6 +43,7 @@
- #include <linux/dma-mapping.h>
- #include <linux/slab.h>
- #include <linux/prefetch.h>
-+#include <linux/pinctrl/consumer.h>
- #ifdef CONFIG_STMMAC_DEBUG_FS
- #include <linux/debugfs.h>
- #include <linux/seq_file.h>
-@@ -2864,6 +2865,7 @@ int stmmac_suspend(struct net_device *ndev)
- priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
- else {
- stmmac_set_mac(priv->ioaddr, false);
-+ pinctrl_pm_select_sleep_state(priv->device);
- /* Disable clock in case of PWM is off */
- clk_disable_unprepare(priv->stmmac_clk);
- }
-@@ -2890,6 +2892,7 @@ int stmmac_resume(struct net_device *ndev)
- if (device_may_wakeup(priv->device)) {
- priv->hw->mac->pmt(priv->ioaddr, 0);
- } else {
-+ pinctrl_pm_select_default_state(priv->device);
- /* enable the clk prevously disabled */
- clk_prepare_enable(priv->stmmac_clk);
- /* reset the phy so that it's ready */
---
-1.8.5.5
-
+++ /dev/null
-From 89f7f2cfdd7ade55d5230501c21271690790ceda Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:53:00 +0000
-Subject: [PATCH] net: stmmac: notify the PM core of a wakeup event.
-
-In PM_SUSPEND_FREEZE and WOL(Wakeup On Lan) case, when the driver gets a
-wakeup event, either the driver or platform specific PM code should notify
-the pm core about it, so that the system can wakeup from low power.
-
-In cases where there is no involvement of platform specific PM, it
-becomes driver responsibility to notify the PM core to wakeup the
-system.
-
-Without this WOL with PM_SUSPEND_FREEZE does not work on STi based SOCs.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 9 +++++++--
- 2 files changed, 8 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-index 027f1dd..73709e9 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-@@ -105,6 +105,7 @@ struct stmmac_priv {
- unsigned int default_addend;
- u32 adv_ts;
- int use_riwt;
-+ int irq_wake;
- spinlock_t ptp_lock;
- };
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index df7d8d6..cddcf76 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2320,6 +2320,9 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
- struct net_device *dev = (struct net_device *)dev_id;
- struct stmmac_priv *priv = netdev_priv(dev);
-
-+ if (priv->irq_wake)
-+ pm_wakeup_event(priv->device, 0);
-+
- if (unlikely(!dev)) {
- pr_err("%s: invalid dev pointer\n", __func__);
- return IRQ_NONE;
-@@ -2861,9 +2864,10 @@ int stmmac_suspend(struct net_device *ndev)
- stmmac_clear_descriptors(priv);
-
- /* Enable Power down mode by programming the PMT regs */
-- if (device_may_wakeup(priv->device))
-+ if (device_may_wakeup(priv->device)) {
- priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
-- else {
-+ priv->irq_wake = 1;
-+ } else {
- stmmac_set_mac(priv->ioaddr, false);
- pinctrl_pm_select_sleep_state(priv->device);
- /* Disable clock in case of PWM is off */
-@@ -2891,6 +2895,7 @@ int stmmac_resume(struct net_device *ndev)
- */
- if (device_may_wakeup(priv->device)) {
- priv->hw->mac->pmt(priv->ioaddr, 0);
-+ priv->irq_wake = 0;
- } else {
- pinctrl_pm_select_default_state(priv->device);
- /* enable the clk prevously disabled */
---
-1.8.5.5
-
+++ /dev/null
-From 957f00fbab201f429ad81cc87ee3177e4289567d Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:51 +0800
-Subject: [PATCH] ARM: dts: sun7i: cubietruck: Enable the GMAC
-
-The CubieTruck uses the GMAC with an RGMII phy.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-index f9dcb61..025ce52 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-@@ -51,6 +51,18 @@
- pinctrl-0 = <&i2c2_pins_a>;
- status = "okay";
- };
-+
-+ gmac: ethernet@01c50000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac_pins_rgmii_a>;
-+ phy = <&phy1>;
-+ phy-mode = "rgmii";
-+ status = "okay";
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
- };
-
- leds {
---
-1.8.5.5
-
+++ /dev/null
-From 7405ae68d251191677e51aadb4308d6ce5212bbe Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:52 +0800
-Subject: [PATCH] ARM: dts: sun7i: cubieboard2: Enable GMAC instead of EMAC
-
-GMAC has better performance and fewer hardware issues.
-Use the GMAC in MII mode for ethernet instead of the EMAC.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 27 ++++++++++++---------------
- 1 file changed, 12 insertions(+), 15 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-index 5c51cb8..7bf4935 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-@@ -19,21 +19,6 @@
- compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-- emac: ethernet@01c0b000 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&emac_pins_a>;
-- phy = <&phy1>;
-- status = "okay";
-- };
--
-- mdio@01c0b080 {
-- status = "okay";
--
-- phy1: ethernet-phy@1 {
-- reg = <1>;
-- };
-- };
--
- pinctrl@01c20800 {
- led_pins_cubieboard2: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
-@@ -60,6 +45,18 @@
- pinctrl-0 = <&i2c1_pins_a>;
- status = "okay";
- };
-+
-+ gmac: ethernet@01c50000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac_pins_mii_a>;
-+ phy = <&phy1>;
-+ phy-mode = "mii";
-+ status = "okay";
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
- };
-
- leds {
---
-1.8.5.5
-
+++ /dev/null
-From e401b86036245d2d62d825f0e3e12286c111b281 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:53 +0800
-Subject: [PATCH] ARM: dts: sun7i: a20-olinuxino-micro: Enable GMAC instead of
- EMAC
-
-GMAC has better performance and fewer hardware issues.
-Use the GMAC in MII mode for ethernet instead of the EMAC.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 27 +++++++++++--------------
- 1 file changed, 12 insertions(+), 15 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-index ead3013..b02a796 100644
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -19,21 +19,6 @@
- compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-- emac: ethernet@01c0b000 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&emac_pins_a>;
-- phy = <&phy1>;
-- status = "okay";
-- };
--
-- mdio@01c0b080 {
-- status = "okay";
--
-- phy1: ethernet-phy@1 {
-- reg = <1>;
-- };
-- };
--
- pinctrl@01c20800 {
- led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PH2";
-@@ -78,6 +63,18 @@
- pinctrl-0 = <&i2c2_pins_a>;
- status = "okay";
- };
-+
-+ gmac: ethernet@01c50000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac_pins_mii_a>;
-+ phy = <&phy1>;
-+ phy-mode = "mii";
-+ status = "okay";
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
- };
-
- leds {
---
-1.8.5.5
-
+++ /dev/null
-From 62866e98737e77c87f9dec99edea76ab54360770 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:40 +0800
-Subject: [PATCH] net: stmmac: Enable stmmac main clock when probing hardware
-
-The stmmac driver does not enable the main clock during the probe phase.
-If the clock was not enabled by the boot loader or was disabled by the
-kernel, hardware features and the MDIO bus would not be probed properly.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 26 +++++++++++------------
- 1 file changed, 13 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index cddcf76..0d2c4cb 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -1680,8 +1680,6 @@ static int stmmac_open(struct net_device *dev)
- struct stmmac_priv *priv = netdev_priv(dev);
- int ret;
-
-- clk_prepare_enable(priv->stmmac_clk);
--
- stmmac_check_ether_addr(priv);
-
- if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
-@@ -1819,7 +1817,6 @@ static int stmmac_release(struct net_device *dev)
- #ifdef CONFIG_STMMAC_DEBUG_FS
- stmmac_exit_fs();
- #endif
-- clk_disable_unprepare(priv->stmmac_clk);
-
- stmmac_release_ptp(priv);
-
-@@ -2727,10 +2724,18 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device,
- if ((phyaddr >= 0) && (phyaddr <= 31))
- priv->plat->phy_addr = phyaddr;
-
-+ priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
-+ if (IS_ERR(priv->stmmac_clk)) {
-+ dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
-+ __func__);
-+ goto error_clk_get;
-+ }
-+ clk_prepare_enable(priv->stmmac_clk);
-+
- /* Init MAC and get the capabilities */
- ret = stmmac_hw_init(priv);
- if (ret)
-- goto error_free_netdev;
-+ goto error_hw_init;
-
- ndev->netdev_ops = &stmmac_netdev_ops;
-
-@@ -2768,12 +2773,6 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device,
- goto error_netdev_register;
- }
-
-- priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
-- if (IS_ERR(priv->stmmac_clk)) {
-- pr_warn("%s: warning: cannot get CSR clock\n", __func__);
-- goto error_clk_get;
-- }
--
- /* If a specific clk_csr value is passed from the platform
- * this means that the CSR Clock Range selection cannot be
- * changed at run-time and it is fixed. Viceversa the driver'll try to
-@@ -2801,12 +2800,12 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device,
- return priv;
-
- error_mdio_register:
-- clk_put(priv->stmmac_clk);
--error_clk_get:
- unregister_netdev(ndev);
- error_netdev_register:
- netif_napi_del(&priv->napi);
--error_free_netdev:
-+error_hw_init:
-+ clk_disable_unprepare(priv->stmmac_clk);
-+error_clk_get:
- free_netdev(ndev);
-
- return NULL;
-@@ -2833,6 +2832,7 @@ int stmmac_dvr_remove(struct net_device *ndev)
- stmmac_mdio_unregister(ndev);
- netif_carrier_off(ndev);
- unregister_netdev(ndev);
-+ clk_disable_unprepare(priv->stmmac_clk);
- free_netdev(ndev);
-
- return 0;
---
-1.8.5.5
-
+++ /dev/null
-From c5e4ddbdfa1134a36589c1466ed4abb85fe6f976 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:41 +0800
-Subject: [PATCH] net: stmmac: Add support for optional reset control
-
-The DWMAC has a reset assert line, which is used on some SoCs. Add an
-optional reset control to stmmac driver core.
-
-To support reset control deferred probing, this patch changes the driver
-probe function to return the actual error, instead of just -EINVAL.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- Documentation/devicetree/bindings/net/stmmac.txt | 3 +++
- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 19 ++++++++++++++++++-
- drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 4 ++--
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ++--
- 6 files changed, 28 insertions(+), 5 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
-index eba0e5e..d132513 100644
---- a/Documentation/devicetree/bindings/net/stmmac.txt
-+++ b/Documentation/devicetree/bindings/net/stmmac.txt
-@@ -30,6 +30,9 @@ Required properties:
-
- Optional properties:
- - mac-address: 6 bytes, mac address
-+- resets: Should contain a phandle to the STMMAC reset signal, if any
-+- reset-names: Should contain the reset signal name "stmmaceth", if a
-+ reset phandle is given
-
- Examples:
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
-index 6e52c0f..b59d1ef 100644
---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
-+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
-@@ -5,6 +5,7 @@ config STMMAC_ETH
- select PHYLIB
- select CRC32
- select PTP_1588_CLOCK
-+ select RESET_CONTROLLER
- ---help---
- This is the driver for the Ethernet IPs are built around a
- Synopsys IP Core and only tested on the STMicroelectronics
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-index 73709e9..c1c141f 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-@@ -32,6 +32,7 @@
- #include <linux/pci.h>
- #include "common.h"
- #include <linux/ptp_clock_kernel.h>
-+#include <linux/reset.h>
-
- struct stmmac_priv {
- /* Frequently used values are kept adjacent for cache effect */
-@@ -91,6 +92,7 @@ struct stmmac_priv {
- int wolopts;
- int wol_irq;
- struct clk *stmmac_clk;
-+ struct reset_control *stmmac_rst;
- int clk_csr;
- struct timer_list eee_ctrl_timer;
- int lpi_irq;
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index 0d2c4cb..0c5c120 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -51,6 +51,7 @@
- #include <linux/net_tstamp.h>
- #include "stmmac_ptp.h"
- #include "stmmac.h"
-+#include <linux/reset.h>
-
- #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
- #define JUMBO_LEN 9000
-@@ -2728,10 +2729,24 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device,
- if (IS_ERR(priv->stmmac_clk)) {
- dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
- __func__);
-+ ret = PTR_ERR(priv->stmmac_clk);
- goto error_clk_get;
- }
- clk_prepare_enable(priv->stmmac_clk);
-
-+ priv->stmmac_rst = devm_reset_control_get(priv->device,
-+ STMMAC_RESOURCE_NAME);
-+ if (IS_ERR(priv->stmmac_rst)) {
-+ if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
-+ ret = -EPROBE_DEFER;
-+ goto error_hw_init;
-+ }
-+ dev_info(priv->device, "no reset control found\n");
-+ priv->stmmac_rst = NULL;
-+ }
-+ if (priv->stmmac_rst)
-+ reset_control_deassert(priv->stmmac_rst);
-+
- /* Init MAC and get the capabilities */
- ret = stmmac_hw_init(priv);
- if (ret)
-@@ -2808,7 +2823,7 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device,
- error_clk_get:
- free_netdev(ndev);
-
-- return NULL;
-+ return ERR_PTR(ret);
- }
-
- /**
-@@ -2832,6 +2847,8 @@ int stmmac_dvr_remove(struct net_device *ndev)
- stmmac_mdio_unregister(ndev);
- netif_carrier_off(ndev);
- unregister_netdev(ndev);
-+ if (priv->stmmac_rst)
-+ reset_control_assert(priv->stmmac_rst);
- clk_disable_unprepare(priv->stmmac_clk);
- free_netdev(ndev);
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
-index 37ba2e0..2916089 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
-@@ -100,9 +100,9 @@ static int stmmac_pci_probe(struct pci_dev *pdev,
- stmmac_default_data();
-
- priv = stmmac_dvr_probe(&(pdev->dev), &plat_dat, addr);
-- if (!priv) {
-+ if (IS_ERR(priv)) {
- pr_err("%s: main driver probe failed", __func__);
-- ret = -ENODEV;
-+ ret = PTR_ERR(priv);
- goto err_out;
- }
- priv->dev->irq = pdev->irq;
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 6d0bf22..cc6b89a7 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -152,9 +152,9 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
- }
-
- priv = stmmac_dvr_probe(&(pdev->dev), plat_dat, addr);
-- if (!priv) {
-+ if (IS_ERR(priv)) {
- pr_err("%s: main driver probe failed", __func__);
-- return -ENODEV;
-+ return PTR_ERR(priv);
- }
-
- /* Get MAC address if available (DT) */
---
-1.8.5.5
-
+++ /dev/null
-From 938dfdaa3c0f92e9a490d324f3bce43bbaef7632 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:42 +0800
-Subject: [PATCH] net: stmmac: Allocate and pass soc/board specific data to
- callbacks
-
-The current .init and .exit callbacks requires access to driver
-private data structures. This is not a good seperation and abstraction.
-
-Instead, we add a new .setup callback for allocating private data, and
-pass the returned pointer to the other callbacks.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- Documentation/networking/stmmac.txt | 12 ++++++++----
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 18 ++++++++++++++----
- include/linux/stmmac.h | 6 ++++--
- 3 files changed, 26 insertions(+), 10 deletions(-)
-
-diff --git a/Documentation/networking/stmmac.txt b/Documentation/networking/stmmac.txt
-index cdd916d..2090895 100644
---- a/Documentation/networking/stmmac.txt
-+++ b/Documentation/networking/stmmac.txt
-@@ -127,8 +127,9 @@ struct plat_stmmacenet_data {
- int riwt_off;
- void (*fix_mac_speed)(void *priv, unsigned int speed);
- void (*bus_setup)(void __iomem *ioaddr);
-- int (*init)(struct platform_device *pdev);
-- void (*exit)(struct platform_device *pdev);
-+ void *(*setup)(struct platform_device *pdev);
-+ int (*init)(struct platform_device *pdev, void *priv);
-+ void (*exit)(struct platform_device *pdev, void *priv);
- void *custom_cfg;
- void *custom_data;
- void *bsp_priv;
-@@ -169,10 +170,13 @@ Where:
- o bus_setup: perform HW setup of the bus. For example, on some ST platforms
- this field is used to configure the AMBA bridge to generate more
- efficient STBus traffic.
-- o init/exit: callbacks used for calling a custom initialization;
-+ o setup/init/exit: callbacks used for calling a custom initialization;
- this is sometime necessary on some platforms (e.g. ST boxes)
- where the HW needs to have set some PIO lines or system cfg
-- registers.
-+ registers. setup should return a pointer to private data,
-+ which will be stored in bsp_priv, and then passed to init and
-+ exit callbacks. init/exit callbacks should not use or modify
-+ platform data.
- o custom_cfg/custom_data: this is a custom configuration that can be passed
- while initializing the resources.
- o bsp_priv: another private pointer.
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index cc6b89a7..704a5e0 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -144,9 +144,16 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
- }
- }
-
-+ /* Custom setup (if needed) */
-+ if (plat_dat->setup) {
-+ plat_dat->bsp_priv = plat_dat->setup(pdev);
-+ if (IS_ERR(plat_dat->bsp_priv))
-+ return PTR_ERR(plat_dat->bsp_priv);
-+ }
-+
- /* Custom initialisation (if needed)*/
- if (plat_dat->init) {
-- ret = plat_dat->init(pdev);
-+ ret = plat_dat->init(pdev, plat_dat->bsp_priv);
- if (unlikely(ret))
- return ret;
- }
-@@ -203,7 +210,10 @@ static int stmmac_pltfr_remove(struct platform_device *pdev)
- int ret = stmmac_dvr_remove(ndev);
-
- if (priv->plat->exit)
-- priv->plat->exit(pdev);
-+ priv->plat->exit(pdev, priv->plat->bsp_priv);
-+
-+ if (priv->plat->free)
-+ priv->plat->free(pdev, priv->plat->bsp_priv);
-
- return ret;
- }
-@@ -218,7 +228,7 @@ static int stmmac_pltfr_suspend(struct device *dev)
-
- ret = stmmac_suspend(ndev);
- if (priv->plat->exit)
-- priv->plat->exit(pdev);
-+ priv->plat->exit(pdev, priv->plat->bsp_priv);
-
- return ret;
- }
-@@ -230,7 +240,7 @@ static int stmmac_pltfr_resume(struct device *dev)
- struct platform_device *pdev = to_platform_device(dev);
-
- if (priv->plat->init)
-- priv->plat->init(pdev);
-+ priv->plat->init(pdev, priv->plat->bsp_priv);
-
- return stmmac_resume(ndev);
- }
-diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
-index 33ace71..0a5a7ac 100644
---- a/include/linux/stmmac.h
-+++ b/include/linux/stmmac.h
-@@ -113,8 +113,10 @@ struct plat_stmmacenet_data {
- int max_speed;
- void (*fix_mac_speed)(void *priv, unsigned int speed);
- void (*bus_setup)(void __iomem *ioaddr);
-- int (*init)(struct platform_device *pdev);
-- void (*exit)(struct platform_device *pdev);
-+ void *(*setup)(struct platform_device *pdev);
-+ void (*free)(struct platform_device *pdev, void *priv);
-+ int (*init)(struct platform_device *pdev, void *priv);
-+ void (*exit)(struct platform_device *pdev, void *priv);
- void *custom_cfg;
- void *custom_data;
- void *bsp_priv;
---
-1.8.5.5
-
+++ /dev/null
-From 6aedb8c06df732625cf998c1428396914f3139b4 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:44 +0800
-Subject: [PATCH] net: stmmac: Honor DT parameter to force DMA store and
- forward mode
-
-"snps,force_sf_dma_mode" is documented in stmmac device tree bindings,
-but is never handled by the driver.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 704a5e0..634260e 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -56,6 +56,8 @@ static int stmmac_probe_config_dt(struct platform_device *pdev,
- sizeof(struct stmmac_mdio_bus_data),
- GFP_KERNEL);
-
-+ plat->force_sf_dma_mode = of_property_read_bool(np, "snps,force_sf_dma_mode");
-+
- /*
- * Currently only the properties needed on SPEAr600
- * are provided. All other properties should be added
---
-1.8.5.5
-
+++ /dev/null
-From 436f7ecdcc08f71ddc106b7bbe3bcbf1785f3bff Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:45 +0800
-Subject: [PATCH] net: stmmac: Deprecate snps, phy-addr and auto-detect PHY
- address
-
-The snps,phy-addr device tree property is non-standard, and should be
-removed in favor of proper phy node support. Remove it from the binding
-documents and warn if the property is still used.
-
-Most PHYs respond to address 0, but a few don't, so auto-detect PHY
-address by default, to make up for the lack of explicit address selection.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- Documentation/devicetree/bindings/net/stmmac.txt | 1 -
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 9 ++++++++-
- 2 files changed, 8 insertions(+), 2 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
-index d132513..aefb639 100644
---- a/Documentation/devicetree/bindings/net/stmmac.txt
-+++ b/Documentation/devicetree/bindings/net/stmmac.txt
-@@ -12,7 +12,6 @@ Required properties:
- property
- - phy-mode: String, operation mode of the PHY interface.
- Supported values are: "mii", "rmii", "gmii", "rgmii".
--- snps,phy-addr phy address to connect to.
- - snps,reset-gpio gpio number for phy reset.
- - snps,reset-active-low boolean flag to indicate if phy reset is active low.
- - snps,reset-delays-us is triplet of delays
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 634260e..82110f1 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -50,7 +50,14 @@ static int stmmac_probe_config_dt(struct platform_device *pdev,
- if (plat->bus_id < 0)
- plat->bus_id = 0;
-
-- of_property_read_u32(np, "snps,phy-addr", &plat->phy_addr);
-+ /* Default to phy auto-detection */
-+ plat->phy_addr = -1;
-+
-+ /* "snps,phy-addr" is not a standard property. Mark it as deprecated
-+ * and warn of its use. Remove this when phy node support is added.
-+ */
-+ if (of_property_read_u32(np, "snps,phy-addr", &plat->phy_addr) == 0)
-+ dev_warn(&pdev->dev, "snps,phy-addr property is deprecated\n");
-
- plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
- sizeof(struct stmmac_mdio_bus_data),
---
-1.8.5.5
-
+++ /dev/null
-From 022066f50f53000679d31eb407693085f37b3f14 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:46 +0800
-Subject: [PATCH] net: stmmac: Use driver data and callbacks tied with
- compatible strings
-
-The stmmac driver core allows passing feature flags and callbacks via
-platform data. Add a similar stmmac_of_data to pass flags and callbacks
-tied to compatible strings. This allows us to extend stmmac with glue
-layers for different SoCs.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 44 +++++++++++++++++-----
- include/linux/stmmac.h | 18 +++++++++
- 2 files changed, 52 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 82110f1..bf119db 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -26,8 +26,20 @@
- #include <linux/io.h>
- #include <linux/of.h>
- #include <linux/of_net.h>
-+#include <linux/of_device.h>
- #include "stmmac.h"
-
-+static const struct of_device_id stmmac_dt_ids[] = {
-+ /* SoC specific glue layers should come before generic bindings */
-+ { .compatible = "st,spear600-gmac"},
-+ { .compatible = "snps,dwmac-3.610"},
-+ { .compatible = "snps,dwmac-3.70a"},
-+ { .compatible = "snps,dwmac-3.710"},
-+ { .compatible = "snps,dwmac"},
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, stmmac_dt_ids);
-+
- #ifdef CONFIG_OF
- static int stmmac_probe_config_dt(struct platform_device *pdev,
- struct plat_stmmacenet_data *plat,
-@@ -35,10 +47,32 @@ static int stmmac_probe_config_dt(struct platform_device *pdev,
- {
- struct device_node *np = pdev->dev.of_node;
- struct stmmac_dma_cfg *dma_cfg;
-+ const struct of_device_id *device;
-
- if (!np)
- return -ENODEV;
-
-+ device = of_match_device(stmmac_dt_ids, &pdev->dev);
-+ if (!device)
-+ return -ENODEV;
-+
-+ if (device->data) {
-+ const struct stmmac_of_data *data = device->data;
-+ plat->has_gmac = data->has_gmac;
-+ plat->enh_desc = data->enh_desc;
-+ plat->tx_coe = data->tx_coe;
-+ plat->rx_coe = data->rx_coe;
-+ plat->bugged_jumbo = data->bugged_jumbo;
-+ plat->pmt = data->pmt;
-+ plat->riwt_off = data->riwt_off;
-+ plat->fix_mac_speed = data->fix_mac_speed;
-+ plat->bus_setup = data->bus_setup;
-+ plat->setup = data->setup;
-+ plat->free = data->free;
-+ plat->init = data->init;
-+ plat->exit = data->exit;
-+ }
-+
- *mac = of_get_mac_address(np);
- plat->interface = of_get_phy_mode(np);
-
-@@ -259,16 +293,6 @@ static int stmmac_pltfr_resume(struct device *dev)
- static SIMPLE_DEV_PM_OPS(stmmac_pltfr_pm_ops,
- stmmac_pltfr_suspend, stmmac_pltfr_resume);
-
--static const struct of_device_id stmmac_dt_ids[] = {
-- { .compatible = "st,spear600-gmac"},
-- { .compatible = "snps,dwmac-3.610"},
-- { .compatible = "snps,dwmac-3.70a"},
-- { .compatible = "snps,dwmac-3.710"},
-- { .compatible = "snps,dwmac"},
-- { /* sentinel */ }
--};
--MODULE_DEVICE_TABLE(of, stmmac_dt_ids);
--
- struct platform_driver stmmac_pltfr_driver = {
- .probe = stmmac_pltfr_probe,
- .remove = stmmac_pltfr_remove,
-diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
-index 0a5a7ac..1367974 100644
---- a/include/linux/stmmac.h
-+++ b/include/linux/stmmac.h
-@@ -121,4 +121,22 @@ struct plat_stmmacenet_data {
- void *custom_data;
- void *bsp_priv;
- };
-+
-+/* of_data for SoC glue layer device tree bindings */
-+
-+struct stmmac_of_data {
-+ int has_gmac;
-+ int enh_desc;
-+ int tx_coe;
-+ int rx_coe;
-+ int bugged_jumbo;
-+ int pmt;
-+ int riwt_off;
-+ void (*fix_mac_speed)(void *priv, unsigned int speed);
-+ void (*bus_setup)(void __iomem *ioaddr);
-+ void *(*setup)(struct platform_device *pdev);
-+ void (*free)(struct platform_device *pdev, void *priv);
-+ int (*init)(struct platform_device *pdev, void *priv);
-+ void (*exit)(struct platform_device *pdev, void *priv);
-+};
- #endif
---
-1.8.5.5
-
+++ /dev/null
-From af0bd4e9ba809391f275d0c094ac0bfbfbb3f430 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:47 +0800
-Subject: [PATCH] net: stmmac: sunxi platform extensions for GMAC in Allwinner
- A20 SoC's
-
-The Allwinner A20 has an ethernet controller that seems to be
-an early version of Synopsys DesignWare MAC 10/100/1000 Universal,
-which is supported by the stmmac driver.
-
-Allwinner's GMAC requires setting additional registers in the SoC's
-clock control unit.
-
-The exact version of the DWMAC IP that Allwinner uses is unknown,
-thus the exact feature set is unknown.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- .../bindings/net/allwinner,sun7i-a20-gmac.txt | 27 ++++
- drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 ++
- drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
- drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c | 140 +++++++++++++++++++++
- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 3 +
- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +
- 6 files changed, 185 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt
- create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
-
-diff --git a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt
-new file mode 100644
-index 0000000..ea4d752
---- /dev/null
-+++ b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt
-@@ -0,0 +1,27 @@
-+* Allwinner GMAC ethernet controller
-+
-+This device is a platform glue layer for stmmac.
-+Please see stmmac.txt for the other unchanged properties.
-+
-+Required properties:
-+ - compatible: Should be "allwinner,sun7i-a20-gmac"
-+ - clocks: Should contain the GMAC main clock, and tx clock
-+ The tx clock type should be "allwinner,sun7i-a20-gmac-clk"
-+ - clock-names: Should contain the clock names "stmmaceth",
-+ and "allwinner_gmac_tx"
-+
-+Optional properties:
-+- phy-supply: phandle to a regulator if the PHY needs one
-+
-+Examples:
-+
-+ gmac: ethernet@01c50000 {
-+ compatible = "allwinner,sun7i-a20-gmac";
-+ reg = <0x01c50000 0x10000>,
-+ <0x01c20164 0x4>;
-+ interrupts = <0 85 1>;
-+ interrupt-names = "macirq";
-+ clocks = <&ahb_gates 49>, <&gmac_tx>;
-+ clock-names = "stmmaceth", "allwinner_gmac_tx";
-+ phy-mode = "mii";
-+ };
-diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
-index b59d1ef..e2f202e 100644
---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
-+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
-@@ -26,6 +26,17 @@ config STMMAC_PLATFORM
-
- If unsure, say N.
-
-+config DWMAC_SUNXI
-+ bool "Allwinner GMAC support"
-+ depends on STMMAC_PLATFORM && ARCH_SUNXI
-+ default y
-+ ---help---
-+ Support for Allwinner A20/A31 GMAC ethernet controllers.
-+
-+ This selects Allwinner SoC glue layer support for the
-+ stmmac device driver. This driver is used for A20/A31
-+ GMAC ethernet controller.
-+
- config STMMAC_PCI
- bool "STMMAC PCI bus support"
- depends on STMMAC_ETH && PCI
-diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
-index 356a9dd..ecadece 100644
---- a/drivers/net/ethernet/stmicro/stmmac/Makefile
-+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
-@@ -1,6 +1,7 @@
- obj-$(CONFIG_STMMAC_ETH) += stmmac.o
- stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o
- stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o
-+stmmac-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o
- stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
- chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
- dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
-diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
-new file mode 100644
-index 0000000..771cd15f
---- /dev/null
-+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
-@@ -0,0 +1,140 @@
-+/**
-+ * dwmac-sunxi.c - Allwinner sunxi DWMAC specific glue layer
-+ *
-+ * Copyright (C) 2013 Chen-Yu Tsai
-+ *
-+ * Chen-Yu Tsai <wens@csie.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/stmmac.h>
-+#include <linux/clk.h>
-+#include <linux/phy.h>
-+#include <linux/of_net.h>
-+#include <linux/regulator/consumer.h>
-+
-+struct sunxi_priv_data {
-+ int interface;
-+ int clk_enabled;
-+ struct clk *tx_clk;
-+ struct regulator *regulator;
-+};
-+
-+static void *sun7i_gmac_setup(struct platform_device *pdev)
-+{
-+ struct sunxi_priv_data *gmac;
-+ struct device *dev = &pdev->dev;
-+
-+ gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
-+ if (!gmac)
-+ return ERR_PTR(-ENOMEM);
-+
-+ gmac->interface = of_get_phy_mode(dev->of_node);
-+
-+ gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx");
-+ if (IS_ERR(gmac->tx_clk)) {
-+ dev_err(dev, "could not get tx clock\n");
-+ return gmac->tx_clk;
-+ }
-+
-+ /* Optional regulator for PHY */
-+ gmac->regulator = devm_regulator_get_optional(dev, "phy");
-+ if (IS_ERR(gmac->regulator)) {
-+ if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
-+ return ERR_PTR(-EPROBE_DEFER);
-+ dev_info(dev, "no regulator found\n");
-+ gmac->regulator = NULL;
-+ }
-+
-+ return gmac;
-+}
-+
-+#define SUN7I_GMAC_GMII_RGMII_RATE 125000000
-+#define SUN7I_GMAC_MII_RATE 25000000
-+
-+static int sun7i_gmac_init(struct platform_device *pdev, void *priv)
-+{
-+ struct sunxi_priv_data *gmac = priv;
-+ int ret;
-+
-+ if (gmac->regulator) {
-+ ret = regulator_enable(gmac->regulator);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ /* Set GMAC interface port mode
-+ *
-+ * The GMAC TX clock lines are configured by setting the clock
-+ * rate, which then uses the auto-reparenting feature of the
-+ * clock driver, and enabling/disabling the clock.
-+ */
-+ if (gmac->interface == PHY_INTERFACE_MODE_RGMII) {
-+ clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE);
-+ clk_prepare_enable(gmac->tx_clk);
-+ gmac->clk_enabled = 1;
-+ } else {
-+ clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE);
-+ clk_prepare(gmac->tx_clk);
-+ }
-+
-+ return 0;
-+}
-+
-+static void sun7i_gmac_exit(struct platform_device *pdev, void *priv)
-+{
-+ struct sunxi_priv_data *gmac = priv;
-+
-+ if (gmac->clk_enabled) {
-+ clk_disable(gmac->tx_clk);
-+ gmac->clk_enabled = 0;
-+ }
-+ clk_unprepare(gmac->tx_clk);
-+
-+ if (gmac->regulator)
-+ regulator_disable(gmac->regulator);
-+}
-+
-+static void sun7i_fix_speed(void *priv, unsigned int speed)
-+{
-+ struct sunxi_priv_data *gmac = priv;
-+
-+ /* only GMII mode requires us to reconfigure the clock lines */
-+ if (gmac->interface != PHY_INTERFACE_MODE_GMII)
-+ return;
-+
-+ if (gmac->clk_enabled) {
-+ clk_disable(gmac->tx_clk);
-+ gmac->clk_enabled = 0;
-+ }
-+ clk_unprepare(gmac->tx_clk);
-+
-+ if (speed == 1000) {
-+ clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE);
-+ clk_prepare_enable(gmac->tx_clk);
-+ gmac->clk_enabled = 1;
-+ } else {
-+ clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE);
-+ clk_prepare(gmac->tx_clk);
-+ }
-+}
-+
-+/* of_data specifying hardware features and callbacks.
-+ * hardware features were copied from Allwinner drivers. */
-+const struct stmmac_of_data sun7i_gmac_data = {
-+ .has_gmac = 1,
-+ .tx_coe = 1,
-+ .fix_mac_speed = sun7i_fix_speed,
-+ .setup = sun7i_gmac_setup,
-+ .init = sun7i_gmac_init,
-+ .exit = sun7i_gmac_exit,
-+};
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-index c1c141f..d9af26e 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-@@ -130,6 +130,9 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device,
- bool stmmac_eee_init(struct stmmac_priv *priv);
-
- #ifdef CONFIG_STMMAC_PLATFORM
-+#ifdef CONFIG_DWMAC_SUNXI
-+extern const struct stmmac_of_data sun7i_gmac_data;
-+#endif
- extern struct platform_driver stmmac_pltfr_driver;
- static inline int stmmac_register_platform(void)
- {
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index bf119db..9d4baa8 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -30,6 +30,9 @@
- #include "stmmac.h"
-
- static const struct of_device_id stmmac_dt_ids[] = {
-+#ifdef CONFIG_DWMAC_SUNXI
-+ { .compatible = "allwinner,sun7i-a20-gmac", .data = &sun7i_gmac_data},
-+#endif
- /* SoC specific glue layers should come before generic bindings */
- { .compatible = "st,spear600-gmac"},
- { .compatible = "snps,dwmac-3.610"},
---
-1.8.5.5
-
+++ /dev/null
-From cc8e5932c671ba2d3ce511a15c19c47b015bc4ab Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 5 Jan 2014 00:00:30 +0100
-Subject: [PATCH] phy-core: phy_get: Leave error logging to the caller
-
-In various cases errors may be expected, ie probe-deferral or a call to
-phy_get from a driver where the use of a phy is optional.
-
-Rather then adding all sort of complicated checks for this, and/or adding
-special functions like devm_phy_get_optional, simply don't log an error,
-and let deciding if get_phy returning an error really should result in a
-dev_err up to the caller.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/phy/phy-core.c | 10 ++--------
- 1 file changed, 2 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
-index 5f5b0f4..b355553 100644
---- a/drivers/phy/phy-core.c
-+++ b/drivers/phy/phy-core.c
-@@ -404,17 +404,11 @@ struct phy *phy_get(struct device *dev, const char *string)
- index = of_property_match_string(dev->of_node, "phy-names",
- string);
- phy = of_phy_get(dev, index);
-- if (IS_ERR(phy)) {
-- dev_err(dev, "unable to find phy\n");
-- return phy;
-- }
- } else {
- phy = phy_lookup(dev, string);
-- if (IS_ERR(phy)) {
-- dev_err(dev, "unable to find phy\n");
-- return phy;
-- }
- }
-+ if (IS_ERR(phy))
-+ return phy;
-
- if (!try_module_get(phy->ops->owner))
- return ERR_PTR(-EPROBE_DEFER);
---
-1.8.5.5
-
+++ /dev/null
-From 37e3cce7288f7d5c34ae630f16faf48bd3d01c18 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 5 Jan 2014 22:40:39 +0100
-Subject: [PATCH] phy-core: Don't propagate -ENOSUPP from
- phy_pm_runtime_get_sync to caller
-
-The phy-core allows phy_init and phy_power_on to be called multiple times,
-but before this patch -ENOSUPP from phy_pm_runtime_get_sync would be
-propagated to the caller for the 2nd and later calls.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/phy/phy-core.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
-index b355553..6c73837 100644
---- a/drivers/phy/phy-core.c
-+++ b/drivers/phy/phy-core.c
-@@ -176,6 +176,8 @@ int phy_init(struct phy *phy)
- dev_err(&phy->dev, "phy init failed --> %d\n", ret);
- goto out;
- }
-+ } else {
-+ ret = 0; /* Override possible ret == -ENOTSUPP */
- }
- ++phy->init_count;
-
-@@ -232,6 +234,8 @@ int phy_power_on(struct phy *phy)
- dev_err(&phy->dev, "phy poweron failed --> %d\n", ret);
- goto out;
- }
-+ } else {
-+ ret = 0; /* Override possible ret == -ENOTSUPP */
- }
- ++phy->power_count;
- mutex_unlock(&phy->mutex);
---
-1.8.5.5
-
+++ /dev/null
-From 87c01c9ef0602abaa909771c6c6eab1f4c2c384d Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 11 Feb 2014 16:55:57 +0100
-Subject: [PATCH] phy-core: Don't allow building phy-core as a module
-
-include/phy/phy.h has stub code in there for when building without the
-phy-core enabled. This is useful for generic drivers such as ahci-platform,
-ehci-platoform and ohci-platform which have support for driving an optional
-phy passed to them through the devicetree.
-
-Since on some boards this phy functionality is not needed, being able to
-disable the phy subsystem without needing a lot of #ifdef magic in the
-driver using it is quite useful.
-
-However this breaks when the module using the phy subsystem is build-in and
-the phy-core is not, which leads to the build failing with missing symbol
-errors in the linking stage of the zImage.
-
-Which leads to gems such as this being added to the Kconfig for achi_platform:
-
- depends on GENERIC_PHY || !GENERIC_PHY
-
-Rather then duplicating this code in a lot of places using the phy-core,
-I believe it is better to simply not allow the phy-core to be built as a
-module. The phy core is quite small and has no external dependencies, so
-always building it in when enabling it should not be an issue.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/phy/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
-index afa2354..4ef8755 100644
---- a/drivers/phy/Kconfig
-+++ b/drivers/phy/Kconfig
-@@ -5,7 +5,7 @@
- menu "PHY Subsystem"
-
- config GENERIC_PHY
-- tristate "PHY Core"
-+ bool "PHY Core"
- help
- Generic PHY support.
-
---
-1.8.5.5
-
+++ /dev/null
-From 9b10bc9f84fc221fcef9ddca92972af9b442f49d Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 2 Dec 2013 16:13:32 +0100
-Subject: [PATCH] libahci: Allow drivers to override start_engine
-
-Allwinner A10 and A20 ARM SoCs have an AHCI sata controller which needs a
-special register to be poked before starting the DMA engine.
-
-This register gets reset on an ahci_stop_engine call, so there is no other
-place then ahci_start_engine where this poking can be done.
-
-This commit allows drivers to override ahci_start_engine behavior for use by
-the Allwinner AHCI driver (and potentially other drivers in the future).
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci.c | 6 ++++--
- drivers/ata/ahci.h | 6 ++++++
- drivers/ata/libahci.c | 26 +++++++++++++++++++-------
- drivers/ata/sata_highbank.c | 3 ++-
- 4 files changed, 31 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
-index dc2756f..eda68b4 100644
---- a/drivers/ata/ahci.c
-+++ b/drivers/ata/ahci.c
-@@ -564,6 +564,7 @@ static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
- unsigned long deadline)
- {
- struct ata_port *ap = link->ap;
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- bool online;
- int rc;
-
-@@ -574,7 +575,7 @@ static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
- rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
- deadline, &online, NULL);
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
-
- DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
-
-@@ -589,6 +590,7 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
- {
- struct ata_port *ap = link->ap;
- struct ahci_port_priv *pp = ap->private_data;
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
- struct ata_taskfile tf;
- bool online;
-@@ -604,7 +606,7 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
- rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
- deadline, &online, NULL);
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
-
- /* The pseudo configuration device on SIMG4726 attached to
- * ASUS P5W-DH Deluxe doesn't send signature FIS after
-diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
-index 2289efd..64d1a99d 100644
---- a/drivers/ata/ahci.h
-+++ b/drivers/ata/ahci.h
-@@ -323,6 +323,12 @@ struct ahci_host_priv {
- u32 em_msg_type; /* EM message type */
- struct clk *clk; /* Only for platforms supporting clk */
- void *plat_data; /* Other platform data */
-+ /*
-+ * Optional ahci_start_engine override, if not set this gets set to the
-+ * default ahci_start_engine during ahci_save_initial_config, this can
-+ * be overridden anytime before the host is activated.
-+ */
-+ void (*start_engine)(struct ata_port *ap);
- };
-
- extern int ahci_ignore_sss;
-diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
-index 36605ab..f839bb3 100644
---- a/drivers/ata/libahci.c
-+++ b/drivers/ata/libahci.c
-@@ -394,6 +394,9 @@ static ssize_t ahci_show_em_supported(struct device *dev,
- *
- * If inconsistent, config values are fixed up by this function.
- *
-+ * If it is not set already this function sets hpriv->start_engine to
-+ * ahci_start_engine.
-+ *
- * LOCKING:
- * None.
- */
-@@ -500,6 +503,9 @@ void ahci_save_initial_config(struct device *dev,
- hpriv->cap = cap;
- hpriv->cap2 = cap2;
- hpriv->port_map = port_map;
-+
-+ if (!hpriv->start_engine)
-+ hpriv->start_engine = ahci_start_engine;
- }
- EXPORT_SYMBOL_GPL(ahci_save_initial_config);
-
-@@ -766,7 +772,7 @@ static void ahci_start_port(struct ata_port *ap)
-
- /* enable DMA */
- if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
-
- /* turn on LEDs */
- if (ap->flags & ATA_FLAG_EM) {
-@@ -1234,7 +1240,7 @@ int ahci_kick_engine(struct ata_port *ap)
-
- /* restart engine */
- out_restart:
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
- return rc;
- }
- EXPORT_SYMBOL_GPL(ahci_kick_engine);
-@@ -1426,6 +1432,7 @@ static int ahci_hardreset(struct ata_link *link, unsigned int *class,
- const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
- struct ata_port *ap = link->ap;
- struct ahci_port_priv *pp = ap->private_data;
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
- struct ata_taskfile tf;
- bool online;
-@@ -1443,7 +1450,7 @@ static int ahci_hardreset(struct ata_link *link, unsigned int *class,
- rc = sata_link_hardreset(link, timing, deadline, &online,
- ahci_check_ready);
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
-
- if (online)
- *class = ahci_dev_classify(ap);
-@@ -2007,10 +2014,12 @@ static void ahci_thaw(struct ata_port *ap)
-
- void ahci_error_handler(struct ata_port *ap)
- {
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
-+
- if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
- /* restart engine */
- ahci_stop_engine(ap);
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
- }
-
- sata_pmp_error_handler(ap);
-@@ -2031,6 +2040,7 @@ static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
-
- static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
- {
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- void __iomem *port_mmio = ahci_port_base(ap);
- struct ata_device *dev = ap->link.device;
- u32 devslp, dm, dito, mdat, deto;
-@@ -2094,7 +2104,7 @@ static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
- PORT_DEVSLP_ADSE);
- writel(devslp, port_mmio + PORT_DEVSLP);
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
-
- /* enable device sleep feature for the drive */
- err_mask = ata_dev_set_feature(dev,
-@@ -2106,6 +2116,7 @@ static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
-
- static void ahci_enable_fbs(struct ata_port *ap)
- {
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- struct ahci_port_priv *pp = ap->private_data;
- void __iomem *port_mmio = ahci_port_base(ap);
- u32 fbs;
-@@ -2134,11 +2145,12 @@ static void ahci_enable_fbs(struct ata_port *ap)
- } else
- dev_err(ap->host->dev, "Failed to enable FBS\n");
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
- }
-
- static void ahci_disable_fbs(struct ata_port *ap)
- {
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- struct ahci_port_priv *pp = ap->private_data;
- void __iomem *port_mmio = ahci_port_base(ap);
- u32 fbs;
-@@ -2166,7 +2178,7 @@ static void ahci_disable_fbs(struct ata_port *ap)
- pp->fbs_enabled = false;
- }
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
- }
-
- static void ahci_pmp_attach(struct ata_port *ap)
-diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
-index 870b11e..b3b18d1 100644
---- a/drivers/ata/sata_highbank.c
-+++ b/drivers/ata/sata_highbank.c
-@@ -403,6 +403,7 @@ static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
- static const unsigned long timing[] = { 5, 100, 500};
- struct ata_port *ap = link->ap;
- struct ahci_port_priv *pp = ap->private_data;
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
- struct ata_taskfile tf;
- bool online;
-@@ -431,7 +432,7 @@ static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
- break;
- } while (!online && retry--);
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
-
- if (online)
- *class = ahci_dev_classify(ap);
---
-1.8.5.5
-
+++ /dev/null
-From bdad8090b5efdb24fa9db00d8e2891927b68dcec Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Thu, 16 Jan 2014 14:32:35 +0100
-Subject: [PATCH] ahci-platform: Add support for devices with more then 1 clock
-
-The allwinner-sun4i AHCI controller needs 2 clocks to be enabled and the
-imx AHCI controller needs 3 clocks to be enabled.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../devicetree/bindings/ata/ahci-platform.txt | 1 +
- drivers/ata/ahci.h | 3 +-
- drivers/ata/ahci_platform.c | 119 ++++++++++++++++-----
- include/linux/ahci_platform.h | 4 +
- 4 files changed, 99 insertions(+), 28 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
-index 89de156..3ced07d 100644
---- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
-+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
-@@ -10,6 +10,7 @@ Required properties:
-
- Optional properties:
- - dma-coherent : Present if dma operations are coherent
-+- clocks : a list of phandle + clock specifier pairs
-
- Example:
- sata@ffe08000 {
-diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
-index 64d1a99d..c12862b 100644
---- a/drivers/ata/ahci.h
-+++ b/drivers/ata/ahci.h
-@@ -51,6 +51,7 @@
-
- enum {
- AHCI_MAX_PORTS = 32,
-+ AHCI_MAX_CLKS = 3,
- AHCI_MAX_SG = 168, /* hardware max is 64K */
- AHCI_DMA_BOUNDARY = 0xffffffff,
- AHCI_MAX_CMDS = 32,
-@@ -321,7 +322,7 @@ struct ahci_host_priv {
- u32 em_loc; /* enclosure management location */
- u32 em_buf_sz; /* EM buffer size in byte */
- u32 em_msg_type; /* EM message type */
-- struct clk *clk; /* Only for platforms supporting clk */
-+ struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
- void *plat_data; /* Other platform data */
- /*
- * Optional ahci_start_engine override, if not set this gets set to the
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 4b231ba..609975d 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -87,6 +87,66 @@ struct ata_port_operations ahci_platform_ops = {
- AHCI_SHT("ahci_platform"),
- };
-
-+/**
-+ * ahci_platform_enable_clks - Enable platform clocks
-+ * @hpriv: host private area to store config values
-+ *
-+ * This function enables all the clks found in hpriv->clks, starting
-+ * at index 0. If any clk fails to enable it disables all the clks
-+ * already enabled in reverse order, and then returns an error.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_enable_clks(struct ahci_host_priv *hpriv)
-+{
-+ int c, rc;
-+
-+ for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++) {
-+ rc = clk_prepare_enable(hpriv->clks[c]);
-+ if (rc)
-+ goto disable_unprepare_clk;
-+ }
-+ return 0;
-+
-+disable_unprepare_clk:
-+ while (--c >= 0)
-+ clk_disable_unprepare(hpriv->clks[c]);
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_enable_clks);
-+
-+/**
-+ * ahci_platform_disable_clks - Disable platform clocks
-+ * @hpriv: host private area to store config values
-+ *
-+ * This function disables all the clks found in hpriv->clks, in reverse
-+ * order of ahci_platform_enable_clks (starting at the end of the array).
-+ *
-+ * LOCKING:
-+ * None.
-+ */
-+void ahci_platform_disable_clks(struct ahci_host_priv *hpriv)
-+{
-+ int c;
-+
-+ for (c = AHCI_MAX_CLKS - 1; c >= 0; c--)
-+ if (hpriv->clks[c])
-+ clk_disable_unprepare(hpriv->clks[c]);
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_disable_clks);
-+
-+static void ahci_put_clks(struct ahci_host_priv *hpriv)
-+{
-+ int c;
-+
-+ for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++)
-+ clk_put(hpriv->clks[c]);
-+}
-+
- static int ahci_probe(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
-@@ -97,6 +157,7 @@ static int ahci_probe(struct platform_device *pdev)
- struct ahci_host_priv *hpriv;
- struct ata_host *host;
- struct resource *mem;
-+ struct clk *clk;
- int irq;
- int n_ports;
- int i;
-@@ -131,17 +192,31 @@ static int ahci_probe(struct platform_device *pdev)
- return -ENOMEM;
- }
-
-- hpriv->clk = clk_get(dev, NULL);
-- if (IS_ERR(hpriv->clk)) {
-- dev_err(dev, "can't get clock\n");
-- } else {
-- rc = clk_prepare_enable(hpriv->clk);
-- if (rc) {
-- dev_err(dev, "clock prepare enable failed");
-- goto free_clk;
-+ for (i = 0; i < AHCI_MAX_CLKS; i++) {
-+ /*
-+ * For now we must use clk_get(dev, NULL) for the first clock,
-+ * because some platforms (da850, spear13xx) are not yet
-+ * converted to use devicetree for clocks. For new platforms
-+ * this is equivalent to of_clk_get(dev->of_node, 0).
-+ */
-+ if (i == 0)
-+ clk = clk_get(dev, NULL);
-+ else
-+ clk = of_clk_get(dev->of_node, i);
-+
-+ if (IS_ERR(clk)) {
-+ rc = PTR_ERR(clk);
-+ if (rc == -EPROBE_DEFER)
-+ goto free_clk;
-+ break;
- }
-+ hpriv->clks[i] = clk;
- }
-
-+ rc = ahci_enable_clks(dev, hpriv);
-+ if (rc)
-+ goto free_clk;
-+
- /*
- * Some platforms might need to prepare for mmio region access,
- * which could be done in the following init call. So, the mmio
-@@ -222,11 +297,9 @@ static int ahci_probe(struct platform_device *pdev)
- if (pdata && pdata->exit)
- pdata->exit(dev);
- disable_unprepare_clk:
-- if (!IS_ERR(hpriv->clk))
-- clk_disable_unprepare(hpriv->clk);
-+ ahci_disable_clks(hpriv);
- free_clk:
-- if (!IS_ERR(hpriv->clk))
-- clk_put(hpriv->clk);
-+ ahci_put_clks(hpriv);
- return rc;
- }
-
-@@ -239,10 +312,8 @@ static void ahci_host_stop(struct ata_host *host)
- if (pdata && pdata->exit)
- pdata->exit(dev);
-
-- if (!IS_ERR(hpriv->clk)) {
-- clk_disable_unprepare(hpriv->clk);
-- clk_put(hpriv->clk);
-- }
-+ ahci_disable_clks(hpriv);
-+ ahci_put_clks(hpriv);
- }
-
- #ifdef CONFIG_PM_SLEEP
-@@ -277,8 +348,7 @@ static int ahci_suspend(struct device *dev)
- if (pdata && pdata->suspend)
- return pdata->suspend(dev);
-
-- if (!IS_ERR(hpriv->clk))
-- clk_disable_unprepare(hpriv->clk);
-+ ahci_disable_clks(hpriv);
-
- return 0;
- }
-@@ -290,13 +360,9 @@ static int ahci_resume(struct device *dev)
- struct ahci_host_priv *hpriv = host->private_data;
- int rc;
-
-- if (!IS_ERR(hpriv->clk)) {
-- rc = clk_prepare_enable(hpriv->clk);
-- if (rc) {
-- dev_err(dev, "clock prepare enable failed");
-- return rc;
-- }
-- }
-+ rc = ahci_enable_clks(dev, hpriv);
-+ if (rc)
-+ return rc;
-
- if (pdata && pdata->resume) {
- rc = pdata->resume(dev);
-@@ -317,8 +383,7 @@ static int ahci_resume(struct device *dev)
- return 0;
-
- disable_unprepare_clk:
-- if (!IS_ERR(hpriv->clk))
-- clk_disable_unprepare(hpriv->clk);
-+ ahci_disable_clks(hpriv);
-
- return rc;
- }
-diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h
-index 73a2500..769d065 100644
---- a/include/linux/ahci_platform.h
-+++ b/include/linux/ahci_platform.h
-@@ -19,6 +19,7 @@
-
- struct device;
- struct ata_port_info;
-+struct ahci_host_priv;
-
- struct ahci_platform_data {
- int (*init)(struct device *dev, void __iomem *addr);
-@@ -30,4 +31,7 @@ struct ahci_platform_data {
- unsigned int mask_port_map;
- };
-
-+int ahci_platform_enable_clks(struct ahci_host_priv *hpriv);
-+void ahci_platform_disable_clks(struct ahci_host_priv *hpriv);
-+
- #endif /* _AHCI_PLATFORM_H */
---
-1.8.5.5
-
+++ /dev/null
-From ba6850946d9e1959be1b00f6ae06454546350c75 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Fri, 17 Jan 2014 13:23:21 +0100
-Subject: [PATCH] ahci-platform: Add support for an optional regulator for
- sata-target power
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../devicetree/bindings/ata/ahci-platform.txt | 1 +
- drivers/ata/ahci.h | 2 ++
- drivers/ata/ahci_platform.c | 36 ++++++++++++++++++++--
- 3 files changed, 37 insertions(+), 2 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
-index 3ced07d..1ac807f 100644
---- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
-+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
-@@ -11,6 +11,7 @@ Required properties:
- Optional properties:
- - dma-coherent : Present if dma operations are coherent
- - clocks : a list of phandle + clock specifier pairs
-+- target-supply : regulator for SATA target power
-
- Example:
- sata@ffe08000 {
-diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
-index c12862b..bf8100c 100644
---- a/drivers/ata/ahci.h
-+++ b/drivers/ata/ahci.h
-@@ -37,6 +37,7 @@
-
- #include <linux/clk.h>
- #include <linux/libata.h>
-+#include <linux/regulator/consumer.h>
-
- /* Enclosure Management Control */
- #define EM_CTRL_MSG_TYPE 0x000f0000
-@@ -323,6 +324,7 @@ struct ahci_host_priv {
- u32 em_buf_sz; /* EM buffer size in byte */
- u32 em_msg_type; /* EM message type */
- struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
-+ struct regulator *target_pwr; /* Optional */
- void *plat_data; /* Other platform data */
- /*
- * Optional ahci_start_engine override, if not set this gets set to the
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 609975d..907c076 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -192,6 +192,14 @@ static int ahci_probe(struct platform_device *pdev)
- return -ENOMEM;
- }
-
-+ hpriv->target_pwr = devm_regulator_get_optional(dev, "target");
-+ if (IS_ERR(hpriv->target_pwr)) {
-+ rc = PTR_ERR(hpriv->target_pwr);
-+ if (rc == -EPROBE_DEFER)
-+ return -EPROBE_DEFER;
-+ hpriv->target_pwr = NULL;
-+ }
-+
- for (i = 0; i < AHCI_MAX_CLKS; i++) {
- /*
- * For now we must use clk_get(dev, NULL) for the first clock,
-@@ -213,9 +221,15 @@ static int ahci_probe(struct platform_device *pdev)
- hpriv->clks[i] = clk;
- }
-
-+ if (hpriv->target_pwr) {
-+ rc = regulator_enable(hpriv->target_pwr);
-+ if (rc)
-+ goto free_clk;
-+ }
-+
- rc = ahci_enable_clks(dev, hpriv);
- if (rc)
-- goto free_clk;
-+ goto disable_regulator;
-
- /*
- * Some platforms might need to prepare for mmio region access,
-@@ -298,6 +312,9 @@ static int ahci_probe(struct platform_device *pdev)
- pdata->exit(dev);
- disable_unprepare_clk:
- ahci_disable_clks(hpriv);
-+disable_regulator:
-+ if (hpriv->target_pwr)
-+ regulator_disable(hpriv->target_pwr);
- free_clk:
- ahci_put_clks(hpriv);
- return rc;
-@@ -314,6 +331,9 @@ static void ahci_host_stop(struct ata_host *host)
-
- ahci_disable_clks(hpriv);
- ahci_put_clks(hpriv);
-+
-+ if (hpriv->target_pwr)
-+ regulator_disable(hpriv->target_pwr);
- }
-
- #ifdef CONFIG_PM_SLEEP
-@@ -350,6 +370,9 @@ static int ahci_suspend(struct device *dev)
-
- ahci_disable_clks(hpriv);
-
-+ if (hpriv->target_pwr)
-+ regulator_disable(hpriv->target_pwr);
-+
- return 0;
- }
-
-@@ -360,9 +383,15 @@ static int ahci_resume(struct device *dev)
- struct ahci_host_priv *hpriv = host->private_data;
- int rc;
-
-+ if (hpriv->target_pwr) {
-+ rc = regulator_enable(hpriv->target_pwr);
-+ if (rc)
-+ return rc;
-+ }
-+
- rc = ahci_enable_clks(dev, hpriv);
- if (rc)
-- return rc;
-+ goto disable_regulator;
-
- if (pdata && pdata->resume) {
- rc = pdata->resume(dev);
-@@ -384,6 +413,9 @@ static int ahci_resume(struct device *dev)
-
- disable_unprepare_clk:
- ahci_disable_clks(hpriv);
-+disable_regulator:
-+ if (hpriv->target_pwr)
-+ regulator_disable(hpriv->target_pwr);
-
- return rc;
- }
---
-1.8.5.5
-
+++ /dev/null
-From 05d5a60ae336c122e478cc002afccc880d462b3b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 20 Jan 2014 14:54:40 +0100
-Subject: [PATCH] ahci-platform: Add enable_ / disable_resources helper
- functions
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci_platform.c | 112 ++++++++++++++++++++++++++++--------------
- include/linux/ahci_platform.h | 2 +
- 2 files changed, 77 insertions(+), 37 deletions(-)
-
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 907c076..6ebbc17 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -139,6 +139,68 @@ void ahci_platform_disable_clks(struct ahci_host_priv *hpriv)
- }
- EXPORT_SYMBOL_GPL(ahci_platform_disable_clks);
-
-+/**
-+ * ahci_platform_enable_resources - Enable platform resources
-+ * @hpriv: host private area to store config values
-+ *
-+ * This function enables all ahci_platform managed resources in
-+ * the following order:
-+ * 1) Regulator
-+ * 2) Clocks (through ahci_platform_enable_clks)
-+ *
-+ * If resource enabling fails at any point the previous enabled
-+ * resources are disabled in reverse order.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_enable_resources(struct ahci_host_priv *hpriv)
-+{
-+ int rc;
-+
-+ if (hpriv->target_pwr) {
-+ rc = regulator_enable(hpriv->target_pwr);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ rc = ahci_platform_enable_clks(hpriv);
-+ if (rc)
-+ goto disable_regulator;
-+
-+ return 0;
-+
-+disable_regulator:
-+ if (hpriv->target_pwr)
-+ regulator_disable(hpriv->target_pwr);
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_enable_resources);
-+
-+/**
-+ * ahci_platform_disable_resources - Disable platform resources
-+ * @hpriv: host private area to store config values
-+ *
-+ * This function disables all ahci_platform managed resources in
-+ * the following order:
-+ * 1) Clocks (through ahci_platform_disable_clks)
-+ * 2) Regulator
-+ *
-+ * LOCKING:
-+ * None.
-+ */
-+void ahci_platform_disable_resources(struct ahci_host_priv *hpriv)
-+{
-+ ahci_platform_disable_clks(hpriv);
-+
-+ if (hpriv->target_pwr)
-+ regulator_disable(hpriv->target_pwr);
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_disable_resources);
-+
- static void ahci_put_clks(struct ahci_host_priv *hpriv)
- {
- int c;
-@@ -221,15 +283,9 @@ static int ahci_probe(struct platform_device *pdev)
- hpriv->clks[i] = clk;
- }
-
-- if (hpriv->target_pwr) {
-- rc = regulator_enable(hpriv->target_pwr);
-- if (rc)
-- goto free_clk;
-- }
--
-- rc = ahci_enable_clks(dev, hpriv);
-+ rc = ahci_platform_enable_resources(hpriv);
- if (rc)
-- goto disable_regulator;
-+ goto free_clk;
-
- /*
- * Some platforms might need to prepare for mmio region access,
-@@ -240,7 +296,7 @@ static int ahci_probe(struct platform_device *pdev)
- if (pdata && pdata->init) {
- rc = pdata->init(dev, hpriv->mmio);
- if (rc)
-- goto disable_unprepare_clk;
-+ goto disable_resources;
- }
-
- ahci_save_initial_config(dev, hpriv,
-@@ -310,11 +366,8 @@ static int ahci_probe(struct platform_device *pdev)
- pdata_exit:
- if (pdata && pdata->exit)
- pdata->exit(dev);
--disable_unprepare_clk:
-- ahci_disable_clks(hpriv);
--disable_regulator:
-- if (hpriv->target_pwr)
-- regulator_disable(hpriv->target_pwr);
-+disable_resources:
-+ ahci_platform_disable_resources(hpriv);
- free_clk:
- ahci_put_clks(hpriv);
- return rc;
-@@ -329,11 +382,8 @@ static void ahci_host_stop(struct ata_host *host)
- if (pdata && pdata->exit)
- pdata->exit(dev);
-
-- ahci_disable_clks(hpriv);
-+ ahci_platform_disable_resources(hpriv);
- ahci_put_clks(hpriv);
--
-- if (hpriv->target_pwr)
-- regulator_disable(hpriv->target_pwr);
- }
-
- #ifdef CONFIG_PM_SLEEP
-@@ -368,10 +418,7 @@ static int ahci_suspend(struct device *dev)
- if (pdata && pdata->suspend)
- return pdata->suspend(dev);
-
-- ahci_disable_clks(hpriv);
--
-- if (hpriv->target_pwr)
-- regulator_disable(hpriv->target_pwr);
-+ ahci_platform_disable_resources(hpriv);
-
- return 0;
- }
-@@ -383,26 +430,20 @@ static int ahci_resume(struct device *dev)
- struct ahci_host_priv *hpriv = host->private_data;
- int rc;
-
-- if (hpriv->target_pwr) {
-- rc = regulator_enable(hpriv->target_pwr);
-- if (rc)
-- return rc;
-- }
--
-- rc = ahci_enable_clks(dev, hpriv);
-+ rc = ahci_platform_enable_resources(hpriv);
- if (rc)
-- goto disable_regulator;
-+ return rc;
-
- if (pdata && pdata->resume) {
- rc = pdata->resume(dev);
- if (rc)
-- goto disable_unprepare_clk;
-+ goto disable_resources;
- }
-
- if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
- rc = ahci_reset_controller(host);
- if (rc)
-- goto disable_unprepare_clk;
-+ goto disable_resources;
-
- ahci_init_controller(host);
- }
-@@ -411,11 +452,8 @@ static int ahci_resume(struct device *dev)
-
- return 0;
-
--disable_unprepare_clk:
-- ahci_disable_clks(hpriv);
--disable_regulator:
-- if (hpriv->target_pwr)
-- regulator_disable(hpriv->target_pwr);
-+disable_resources:
-+ ahci_platform_disable_resources(hpriv);
-
- return rc;
- }
-diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h
-index 769d065..b674b01 100644
---- a/include/linux/ahci_platform.h
-+++ b/include/linux/ahci_platform.h
-@@ -33,5 +33,7 @@ struct ahci_platform_data {
-
- int ahci_platform_enable_clks(struct ahci_host_priv *hpriv);
- void ahci_platform_disable_clks(struct ahci_host_priv *hpriv);
-+int ahci_platform_enable_resources(struct ahci_host_priv *hpriv);
-+void ahci_platform_disable_resources(struct ahci_host_priv *hpriv);
-
- #endif /* _AHCI_PLATFORM_H */
---
-1.8.5.5
-
+++ /dev/null
-From 98601575da5276173233dd575bdd61cccdeb861a Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 20 Jan 2014 14:58:04 +0100
-Subject: [PATCH] ahci-platform: "Library-ise" ahci_probe functionality
-
-ahci_probe consists of 3 steps:
-1) Get resources (get mmio, clks, regulator)
-2) Enable resources, handled by ahci_platform_enable_resouces
-3) The more or less standard ahci-host controller init sequence
-
-This commit refactors step 1 and 3 into separate functions, so the platform
-drivers for AHCI implementations which need a specific order in step 2,
-and / or need to do some custom register poking at some time, can re-use
-ahci-platform.c code without needing to copy and paste it.
-
-Note that ahci_platform_init_host's prototype takes the 3 non function
-members of ahci_platform_data as arguments, the idea is that drivers using
-the new exported utility functions will not use ahci_platform_data at all,
-and hopefully in the future ahci_platform_data can go away entirely.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci_platform.c | 195 ++++++++++++++++++++++++++++--------------
- include/linux/ahci_platform.h | 14 +++
- 2 files changed, 144 insertions(+), 65 deletions(-)
-
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 6ebbc17..7f3f2ac 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -201,64 +201,64 @@ void ahci_platform_disable_resources(struct ahci_host_priv *hpriv)
- }
- EXPORT_SYMBOL_GPL(ahci_platform_disable_resources);
-
--static void ahci_put_clks(struct ahci_host_priv *hpriv)
-+static void ahci_platform_put_resources(struct device *dev, void *res)
- {
-+ struct ahci_host_priv *hpriv = res;
- int c;
-
- for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++)
- clk_put(hpriv->clks[c]);
- }
-
--static int ahci_probe(struct platform_device *pdev)
-+/**
-+ * ahci_platform_get_resources - Get platform resources
-+ * @pdev: platform device to get resources for
-+ *
-+ * This function allocates an ahci_host_priv struct, and gets the
-+ * following resources, storing a reference to them inside the returned
-+ * struct:
-+ *
-+ * 1) mmio registers (IORESOURCE_MEM 0, mandatory)
-+ * 2) regulator for controlling the targets power (optional)
-+ * 3) 0 - AHCI_MAX_CLKS clocks, as specified in the devs devicetree node,
-+ * or for non devicetree enabled platforms a single clock
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * The allocated ahci_host_priv on success, otherwise an ERR_PTR value
-+ */
-+struct ahci_host_priv *ahci_platform_get_resources(
-+ struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
-- struct ahci_platform_data *pdata = dev_get_platdata(dev);
-- const struct platform_device_id *id = platform_get_device_id(pdev);
-- struct ata_port_info pi = ahci_port_info[id ? id->driver_data : 0];
-- const struct ata_port_info *ppi[] = { &pi, NULL };
- struct ahci_host_priv *hpriv;
-- struct ata_host *host;
-- struct resource *mem;
- struct clk *clk;
-- int irq;
-- int n_ports;
-- int i;
-- int rc;
-+ int i, rc = -ENOMEM;
-
-- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- if (!mem) {
-- dev_err(dev, "no mmio space\n");
-- return -EINVAL;
-- }
-+ if (!devres_open_group(dev, NULL, GFP_KERNEL))
-+ return ERR_PTR(-ENOMEM);
-
-- irq = platform_get_irq(pdev, 0);
-- if (irq <= 0) {
-- dev_err(dev, "no irq\n");
-- return -EINVAL;
-- }
-+ hpriv = devres_alloc(ahci_platform_put_resources, sizeof(*hpriv),
-+ GFP_KERNEL);
-+ if (!hpriv)
-+ goto err_out;
-
-- if (pdata && pdata->ata_port_info)
-- pi = *pdata->ata_port_info;
-+ devres_add(dev, hpriv);
-
-- hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
-- if (!hpriv) {
-- dev_err(dev, "can't alloc ahci_host_priv\n");
-- return -ENOMEM;
-- }
--
-- hpriv->flags |= (unsigned long)pi.private_data;
--
-- hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
-+ hpriv->mmio = devm_ioremap_resource(dev,
-+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
- if (!hpriv->mmio) {
-- dev_err(dev, "can't map %pR\n", mem);
-- return -ENOMEM;
-+ dev_err(dev, "no mmio space\n");
-+ goto err_out;
- }
-
- hpriv->target_pwr = devm_regulator_get_optional(dev, "target");
- if (IS_ERR(hpriv->target_pwr)) {
- rc = PTR_ERR(hpriv->target_pwr);
- if (rc == -EPROBE_DEFER)
-- return -EPROBE_DEFER;
-+ goto err_out;
- hpriv->target_pwr = NULL;
- }
-
-@@ -277,33 +277,62 @@ static int ahci_probe(struct platform_device *pdev)
- if (IS_ERR(clk)) {
- rc = PTR_ERR(clk);
- if (rc == -EPROBE_DEFER)
-- goto free_clk;
-+ goto err_out;
- break;
- }
- hpriv->clks[i] = clk;
- }
-
-- rc = ahci_platform_enable_resources(hpriv);
-- if (rc)
-- goto free_clk;
-+ devres_remove_group(dev, NULL);
-+ return hpriv;
-
-- /*
-- * Some platforms might need to prepare for mmio region access,
-- * which could be done in the following init call. So, the mmio
-- * region shouldn't be accessed before init (if provided) has
-- * returned successfully.
-- */
-- if (pdata && pdata->init) {
-- rc = pdata->init(dev, hpriv->mmio);
-- if (rc)
-- goto disable_resources;
-- }
-+err_out:
-+ devres_release_group(dev, NULL);
-+ return ERR_PTR(rc);
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_get_resources);
-+
-+/**
-+ * ahci_platform_init_host - Bring up an ahci-platform host
-+ * @pdev: platform device pointer for the host
-+ * @hpriv: ahci-host private data for the host
-+ * @pi_template: template for the ata_port_info to use
-+ * @force_port_map: param passed to ahci_save_initial_config
-+ * @mask_port_map: param passed to ahci_save_initial_config
-+ *
-+ * This function does all the usual steps needed to bring up an
-+ * ahci-platform host, note any necessary resources (ie clks, phy, etc.)
-+ * must be initialized / enabled before calling this.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_init_host(struct platform_device *pdev,
-+ struct ahci_host_priv *hpriv,
-+ const struct ata_port_info *pi_template,
-+ unsigned int force_port_map,
-+ unsigned int mask_port_map)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct ata_port_info pi = *pi_template;
-+ const struct ata_port_info *ppi[] = { &pi, NULL };
-+ struct ata_host *host;
-+ int i, irq, n_ports, rc;
-
-- ahci_save_initial_config(dev, hpriv,
-- pdata ? pdata->force_port_map : 0,
-- pdata ? pdata->mask_port_map : 0);
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq <= 0) {
-+ dev_err(dev, "no irq\n");
-+ return -EINVAL;
-+ }
-
- /* prepare host */
-+ hpriv->flags |= (unsigned long)pi.private_data;
-+
-+ ahci_save_initial_config(dev, hpriv, force_port_map, mask_port_map);
-+
- if (hpriv->cap & HOST_CAP_NCQ)
- pi.flags |= ATA_FLAG_NCQ;
-
-@@ -320,10 +349,8 @@ static int ahci_probe(struct platform_device *pdev)
- n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
-
- host = ata_host_alloc_pinfo(dev, ppi, n_ports);
-- if (!host) {
-- rc = -ENOMEM;
-- goto pdata_exit;
-- }
-+ if (!host)
-+ return -ENOMEM;
-
- host->private_data = hpriv;
-
-@@ -338,7 +365,8 @@ static int ahci_probe(struct platform_device *pdev)
- for (i = 0; i < host->n_ports; i++) {
- struct ata_port *ap = host->ports[i];
-
-- ata_port_desc(ap, "mmio %pR", mem);
-+ ata_port_desc(ap, "mmio %pR",
-+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
- ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
-
- /* set enclosure management message type */
-@@ -352,13 +380,53 @@ static int ahci_probe(struct platform_device *pdev)
-
- rc = ahci_reset_controller(host);
- if (rc)
-- goto pdata_exit;
-+ return rc;
-
- ahci_init_controller(host);
- ahci_print_info(host, "platform");
-
-- rc = ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED,
-- &ahci_platform_sht);
-+ return ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED,
-+ &ahci_platform_sht);
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_init_host);
-+
-+static int ahci_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct ahci_platform_data *pdata = dev_get_platdata(dev);
-+ const struct platform_device_id *id = platform_get_device_id(pdev);
-+ const struct ata_port_info *pi_template;
-+ struct ahci_host_priv *hpriv;
-+ int rc;
-+
-+ hpriv = ahci_platform_get_resources(pdev);
-+ if (IS_ERR(hpriv))
-+ return PTR_ERR(hpriv);
-+
-+ rc = ahci_platform_enable_resources(hpriv);
-+ if (rc)
-+ return rc;
-+
-+ /*
-+ * Some platforms might need to prepare for mmio region access,
-+ * which could be done in the following init call. So, the mmio
-+ * region shouldn't be accessed before init (if provided) has
-+ * returned successfully.
-+ */
-+ if (pdata && pdata->init) {
-+ rc = pdata->init(dev, hpriv->mmio);
-+ if (rc)
-+ goto disable_resources;
-+ }
-+
-+ if (pdata && pdata->ata_port_info)
-+ pi_template = pdata->ata_port_info;
-+ else
-+ pi_template = &ahci_port_info[id ? id->driver_data : 0];
-+
-+ rc = ahci_platform_init_host(pdev, hpriv, pi_template,
-+ pdata ? pdata->force_port_map : 0,
-+ pdata ? pdata->mask_port_map : 0);
- if (rc)
- goto pdata_exit;
-
-@@ -368,8 +436,6 @@ static int ahci_probe(struct platform_device *pdev)
- pdata->exit(dev);
- disable_resources:
- ahci_platform_disable_resources(hpriv);
--free_clk:
-- ahci_put_clks(hpriv);
- return rc;
- }
-
-@@ -383,7 +449,6 @@ static void ahci_host_stop(struct ata_host *host)
- pdata->exit(dev);
-
- ahci_platform_disable_resources(hpriv);
-- ahci_put_clks(hpriv);
- }
-
- #ifdef CONFIG_PM_SLEEP
-diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h
-index b674b01..b80c51c 100644
---- a/include/linux/ahci_platform.h
-+++ b/include/linux/ahci_platform.h
-@@ -20,7 +20,14 @@
- struct device;
- struct ata_port_info;
- struct ahci_host_priv;
-+struct platform_device;
-
-+/*
-+ * Note ahci_platform_data is deprecated, it is only kept around for use
-+ * by the old da850 and spear13xx ahci code.
-+ * New drivers should instead declare their own platform_driver struct, and
-+ * use ahci_platform* functions in their own probe, suspend and resume methods.
-+ */
- struct ahci_platform_data {
- int (*init)(struct device *dev, void __iomem *addr);
- void (*exit)(struct device *dev);
-@@ -35,5 +42,12 @@ struct ahci_platform_data {
- void ahci_platform_disable_clks(struct ahci_host_priv *hpriv);
- int ahci_platform_enable_resources(struct ahci_host_priv *hpriv);
- void ahci_platform_disable_resources(struct ahci_host_priv *hpriv);
-+struct ahci_host_priv *ahci_platform_get_resources(
-+ struct platform_device *pdev);
-+int ahci_platform_init_host(struct platform_device *pdev,
-+ struct ahci_host_priv *hpriv,
-+ const struct ata_port_info *pi_template,
-+ unsigned int force_port_map,
-+ unsigned int mask_port_map);
-
- #endif /* _AHCI_PLATFORM_H */
---
-1.8.5.5
-
+++ /dev/null
-From 041cf8356a4eb91ee8118004b2bc9c78cdd7866c Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 20 Jan 2014 15:52:07 +0100
-Subject: [PATCH] ahci-platform: "Library-ise" suspend / resume functionality
-
-Split suspend / resume code into host suspend / resume functionality and
-resource enable / disabling phases, and export the new suspend_ / resume_host
-functions.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci_platform.c | 109 ++++++++++++++++++++++++++++++++++++------
- include/linux/ahci_platform.h | 5 ++
- 2 files changed, 99 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 7f3f2ac..bdadec1 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -452,14 +452,26 @@ static void ahci_host_stop(struct ata_host *host)
- }
-
- #ifdef CONFIG_PM_SLEEP
--static int ahci_suspend(struct device *dev)
-+/**
-+ * ahci_platform_suspend_host - Suspend an ahci-platform host
-+ * @dev: device pointer for the host
-+ *
-+ * This function does all the usual steps needed to suspend an
-+ * ahci-platform host, note any necessary resources (ie clks, phy, etc.)
-+ * must be disabled after calling this.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_suspend_host(struct device *dev)
- {
-- struct ahci_platform_data *pdata = dev_get_platdata(dev);
- struct ata_host *host = dev_get_drvdata(dev);
- struct ahci_host_priv *hpriv = host->private_data;
- void __iomem *mmio = hpriv->mmio;
- u32 ctl;
-- int rc;
-
- if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
- dev_err(dev, "firmware update required for suspend/resume\n");
-@@ -476,7 +488,64 @@ static int ahci_suspend(struct device *dev)
- writel(ctl, mmio + HOST_CTL);
- readl(mmio + HOST_CTL); /* flush */
-
-- rc = ata_host_suspend(host, PMSG_SUSPEND);
-+ return ata_host_suspend(host, PMSG_SUSPEND);
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_suspend_host);
-+
-+/**
-+ * ahci_platform_resume_host - Resume an ahci-platform host
-+ * @dev: device pointer for the host
-+ *
-+ * This function does all the usual steps needed to resume an
-+ * ahci-platform host, note any necessary resources (ie clks, phy, etc.)
-+ * must be initialized / enabled before calling this.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_resume_host(struct device *dev)
-+{
-+ struct ata_host *host = dev_get_drvdata(dev);
-+ int rc;
-+
-+ if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
-+ rc = ahci_reset_controller(host);
-+ if (rc)
-+ return rc;
-+
-+ ahci_init_controller(host);
-+ }
-+
-+ ata_host_resume(host);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_resume_host);
-+
-+/**
-+ * ahci_platform_suspend - Suspend an ahci-platform device
-+ * @dev: the platform device to suspend
-+ *
-+ * This function suspends the host associated with the device, followed
-+ * by disabling all the resources of the device.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_suspend(struct device *dev)
-+{
-+ struct ahci_platform_data *pdata = dev_get_platdata(dev);
-+ struct ata_host *host = dev_get_drvdata(dev);
-+ struct ahci_host_priv *hpriv = host->private_data;
-+ int rc;
-+
-+ rc = ahci_platform_suspend_host(dev);
- if (rc)
- return rc;
-
-@@ -487,8 +556,22 @@ static int ahci_suspend(struct device *dev)
-
- return 0;
- }
-+EXPORT_SYMBOL_GPL(ahci_platform_suspend);
-
--static int ahci_resume(struct device *dev)
-+/**
-+ * ahci_platform_resume - Resume an ahci-platform device
-+ * @dev: the platform device to resume
-+ *
-+ * This function enables all the resources of the device followed by
-+ * resuming the host associated with the device.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_resume(struct device *dev)
- {
- struct ahci_platform_data *pdata = dev_get_platdata(dev);
- struct ata_host *host = dev_get_drvdata(dev);
-@@ -505,15 +588,9 @@ static int ahci_resume(struct device *dev)
- goto disable_resources;
- }
-
-- if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
-- rc = ahci_reset_controller(host);
-- if (rc)
-- goto disable_resources;
--
-- ahci_init_controller(host);
-- }
--
-- ata_host_resume(host);
-+ rc = ahci_platform_resume_host(dev);
-+ if (rc)
-+ goto disable_resources;
-
- return 0;
-
-@@ -522,9 +599,11 @@ static int ahci_resume(struct device *dev)
-
- return rc;
- }
-+EXPORT_SYMBOL_GPL(ahci_platform_resume);
- #endif
-
--static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_suspend, ahci_resume);
-+static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
-+ ahci_platform_resume);
-
- static const struct of_device_id ahci_of_match[] = {
- { .compatible = "snps,spear-ahci", },
-diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h
-index b80c51c..542f268 100644
---- a/include/linux/ahci_platform.h
-+++ b/include/linux/ahci_platform.h
-@@ -50,4 +50,9 @@ int ahci_platform_init_host(struct platform_device *pdev,
- unsigned int force_port_map,
- unsigned int mask_port_map);
-
-+int ahci_platform_suspend_host(struct device *dev);
-+int ahci_platform_resume_host(struct device *dev);
-+int ahci_platform_suspend(struct device *dev);
-+int ahci_platform_resume(struct device *dev);
-+
- #endif /* _AHCI_PLATFORM_H */
---
-1.8.5.5
-
+++ /dev/null
-From 93dd2c512a24c552f1146d746aac112da7677430 Mon Sep 17 00:00:00 2001
-From: Olliver Schinagl <oliver@schinagl.nl>
-Date: Sat, 18 Jan 2014 15:00:45 +0100
-Subject: [PATCH] ARM: sunxi: Add support for Allwinner SUNXi SoCs sata to
- ahci_platform
-
-This patch adds support for the ahci sata controler found on Allwinner A10
-and A20 SoCs to the ahci_platform driver.
-
-Orignally written by Olliver Schinagl using the approach of having a platform
-device which probe method creates a new child platform device which gets
-driven by ahci_platform.c, as done by ahci_imx.c .
-
-Refactored by Hans de Goede to add most of the non sunxi specific functionality
-to ahci_platform.c and use a platform_data pointer from of_device_id for the
-sunxi specific bits.
-
-Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../devicetree/bindings/ata/ahci-platform.txt | 15 +-
- drivers/ata/Kconfig | 9 +
- drivers/ata/Makefile | 1 +
- drivers/ata/ahci_sunxi.c | 249 +++++++++++++++++++++
- 4 files changed, 271 insertions(+), 3 deletions(-)
- create mode 100644 drivers/ata/ahci_sunxi.c
-
-diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
-index 1ac807f..499bfed 100644
---- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
-+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
-@@ -4,7 +4,9 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
- Each SATA controller should have its own node.
-
- Required properties:
--- compatible : compatible list, contains "snps,spear-ahci"
-+- compatible : compatible list, one of "snps,spear-ahci",
-+ "snps,exynos5440-ahci", "ibm,476gtr-ahci", or
-+ "allwinner,sun4i-a10-ahci"
- - interrupts : <interrupt mapping for SATA IRQ>
- - reg : <registers mapping>
-
-@@ -13,10 +15,17 @@ Optional properties:
- - clocks : a list of phandle + clock specifier pairs
- - target-supply : regulator for SATA target power
-
--Example:
-+Examples:
- sata@ffe08000 {
- compatible = "snps,spear-ahci";
- reg = <0xffe08000 0x1000>;
- interrupts = <115>;
--
- };
-+
-+ ahci: sata@01c18000 {
-+ compatible = "allwinner,sun4i-a10-ahci";
-+ reg = <0x01c18000 0x1000>;
-+ interrupts = <56>;
-+ clocks = <&pll6 0>, <&ahb_gates 25>;
-+ target-supply = <®_ahci_5v>;
-+ };
-diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
-index 4e73772..cc67cc0 100644
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -106,6 +106,15 @@ config AHCI_IMX
-
- If unsure, say N.
-
-+config AHCI_SUNXI
-+ tristate "Allwinner sunxi AHCI SATA support"
-+ depends on ARCH_SUNXI && SATA_AHCI_PLATFORM
-+ help
-+ This option enables support for the Allwinner sunxi SoC's
-+ onboard AHCI SATA.
-+
-+ If unsure, say N.
-+
- config SATA_FSL
- tristate "Freescale 3.0Gbps SATA support"
- depends on FSL_SOC
-diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
-index 46518c6..246050b 100644
---- a/drivers/ata/Makefile
-+++ b/drivers/ata/Makefile
-@@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
- obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
- obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
- obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
-+obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o
-
- # SFF w/ custom DMA
- obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
-diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
-new file mode 100644
-index 0000000..001f7dfc
---- /dev/null
-+++ b/drivers/ata/ahci_sunxi.c
-@@ -0,0 +1,249 @@
-+/*
-+ * Allwinner sunxi AHCI SATA platform driver
-+ * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
-+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
-+ * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
-+ * Daniel Wang <danielwang@allwinnertech.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ */
-+
-+#include <linux/ahci_platform.h>
-+#include <linux/clk.h>
-+#include <linux/errno.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include "ahci.h"
-+
-+#define AHCI_BISTAFR 0x00a0
-+#define AHCI_BISTCR 0x00a4
-+#define AHCI_BISTFCTR 0x00a8
-+#define AHCI_BISTSR 0x00ac
-+#define AHCI_BISTDECR 0x00b0
-+#define AHCI_DIAGNR0 0x00b4
-+#define AHCI_DIAGNR1 0x00b8
-+#define AHCI_OOBR 0x00bc
-+#define AHCI_PHYCS0R 0x00c0
-+#define AHCI_PHYCS1R 0x00c4
-+#define AHCI_PHYCS2R 0x00c8
-+#define AHCI_TIMER1MS 0x00e0
-+#define AHCI_GPARAM1R 0x00e8
-+#define AHCI_GPARAM2R 0x00ec
-+#define AHCI_PPARAMR 0x00f0
-+#define AHCI_TESTR 0x00f4
-+#define AHCI_VERSIONR 0x00f8
-+#define AHCI_IDR 0x00fc
-+#define AHCI_RWCR 0x00fc
-+#define AHCI_P0DMACR 0x0170
-+#define AHCI_P0PHYCR 0x0178
-+#define AHCI_P0PHYSR 0x017c
-+
-+static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
-+{
-+ u32 reg_val;
-+
-+ reg_val = readl(reg);
-+ reg_val &= ~(clr_val);
-+ writel(reg_val, reg);
-+}
-+
-+static void sunxi_setbits(void __iomem *reg, u32 set_val)
-+{
-+ u32 reg_val;
-+
-+ reg_val = readl(reg);
-+ reg_val |= set_val;
-+ writel(reg_val, reg);
-+}
-+
-+static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
-+{
-+ u32 reg_val;
-+
-+ reg_val = readl(reg);
-+ reg_val &= ~(clr_val);
-+ reg_val |= set_val;
-+ writel(reg_val, reg);
-+}
-+
-+static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
-+{
-+ return (readl(reg) >> shift) & mask;
-+}
-+
-+static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
-+{
-+ u32 reg_val;
-+ int timeout;
-+
-+ /* This magic is from the original code */
-+ writel(0, reg_base + AHCI_RWCR);
-+ mdelay(5);
-+
-+ sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
-+ sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
-+ (0x7 << 24),
-+ (0x5 << 24) | BIT(23) | BIT(18));
-+ sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
-+ (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
-+ (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
-+ sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
-+ sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
-+ sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
-+ (0x7 << 20), (0x3 << 20));
-+ sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
-+ (0x1f << 5), (0x19 << 5));
-+ mdelay(5);
-+
-+ sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
-+
-+ timeout = 250; /* Power up takes aprox 50 us */
-+ do {
-+ reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
-+ if (reg_val == 0x02)
-+ break;
-+
-+ if (--timeout == 0) {
-+ dev_err(dev, "PHY power up failed.\n");
-+ return -EIO;
-+ }
-+ udelay(1);
-+ } while (1);
-+
-+ sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
-+
-+ timeout = 100; /* Calibration takes aprox 10 us */
-+ do {
-+ reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
-+ if (reg_val == 0x00)
-+ break;
-+
-+ if (--timeout == 0) {
-+ dev_err(dev, "PHY calibration failed.\n");
-+ return -EIO;
-+ }
-+ udelay(1);
-+ } while (1);
-+
-+ mdelay(15);
-+
-+ writel(0x7, reg_base + AHCI_RWCR);
-+
-+ return 0;
-+}
-+
-+static void ahci_sunxi_start_engine(struct ata_port *ap)
-+{
-+ void __iomem *port_mmio = ahci_port_base(ap);
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
-+
-+ /* Setup DMA before DMA start */
-+ sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
-+
-+ /* Start DMA */
-+ sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
-+}
-+
-+static const struct ata_port_info ahci_sunxi_port_info = {
-+ AHCI_HFLAGS(AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
-+ AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ),
-+ .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
-+ .pio_mask = ATA_PIO4,
-+ .udma_mask = ATA_UDMA6,
-+ .port_ops = &ahci_platform_ops,
-+};
-+
-+static int ahci_sunxi_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct ahci_host_priv *hpriv;
-+ int rc;
-+
-+ hpriv = ahci_platform_get_resources(pdev);
-+ if (IS_ERR(hpriv))
-+ return PTR_ERR(hpriv);
-+
-+ hpriv->start_engine = ahci_sunxi_start_engine;
-+
-+ rc = ahci_platform_enable_resources(hpriv);
-+ if (rc)
-+ return rc;
-+
-+ rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
-+ if (rc)
-+ goto disable_resources;
-+
-+ rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info, 0, 0);
-+ if (rc)
-+ goto disable_resources;
-+
-+ return 0;
-+
-+disable_resources:
-+ ahci_platform_disable_resources(hpriv);
-+ return rc;
-+}
-+
-+#ifdef CONFIG_PM_SLEEP
-+int ahci_sunxi_resume(struct device *dev)
-+{
-+ struct ata_host *host = dev_get_drvdata(dev);
-+ struct ahci_host_priv *hpriv = host->private_data;
-+ int rc;
-+
-+ rc = ahci_platform_enable_resources(hpriv);
-+ if (rc)
-+ return rc;
-+
-+ rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
-+ if (rc)
-+ goto disable_resources;
-+
-+ rc = ahci_platform_resume_host(dev);
-+ if (rc)
-+ goto disable_resources;
-+
-+ return 0;
-+
-+disable_resources:
-+ ahci_platform_disable_resources(hpriv);
-+ return rc;
-+}
-+#endif
-+
-+static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
-+ ahci_sunxi_resume);
-+
-+static const struct of_device_id ahci_sunxi_of_match[] = {
-+ { .compatible = "allwinner,sun4i-a10-ahci", },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);
-+
-+static struct platform_driver ahci_sunxi_driver = {
-+ .probe = ahci_sunxi_probe,
-+ .remove = ata_platform_remove_one,
-+ .driver = {
-+ .name = "ahci-sunxi",
-+ .owner = THIS_MODULE,
-+ .of_match_table = ahci_sunxi_of_match,
-+ .pm = &ahci_sunxi_pm_ops,
-+ },
-+};
-+module_platform_driver(ahci_sunxi_driver);
-+
-+MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA driver");
-+MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
-+MODULE_LICENSE("GPL");
---
-1.8.5.5
-
+++ /dev/null
-From 90189e2c18e983da0ce22e44cd610f9ce2db69b1 Mon Sep 17 00:00:00 2001
-From: Roger Quadros <rogerq@ti.com>
-Date: Mon, 20 Jan 2014 16:32:33 +0200
-Subject: [PATCH] ata: ahci_platform: Add DT compatible for Synopsis DWC AHCI
- controller
-
-Add compatible string "snps,dwc-ahci", which should be used
-for Synopsis Designware SATA cores. e.g. on TI OMAP5 and DRA7 platforms.
-
-Signed-off-by: Roger Quadros <rogerq@ti.com>
-Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci_platform.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index bdadec1..d7e55ba 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -609,6 +609,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
- { .compatible = "snps,spear-ahci", },
- { .compatible = "snps,exynos5440-ahci", },
- { .compatible = "ibm,476gtr-ahci", },
-+ { .compatible = "snps,dwc-ahci", },
- {},
- };
- MODULE_DEVICE_TABLE(of, ahci_of_match);
---
-1.8.5.5
-
+++ /dev/null
-From 154a670a945c54300749d5ba008f30bbd6089017 Mon Sep 17 00:00:00 2001
-From: Roger Quadros <rogerq@ti.com>
-Date: Mon, 27 Jan 2014 16:41:18 +0200
-Subject: [PATCH] ata: ahci_platform: Manage SATA PHY
-
-Some platforms have a PHY hooked up to the
-SATA controller. The PHY needs to be initialized
-and powered up for SATA to work. We do that
-using the PHY framework.
-
-CC: Balaji T K <balajitk@ti.com>
-Signed-off-by: Roger Quadros <rogerq@ti.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci.h | 2 ++
- drivers/ata/ahci_platform.c | 47 +++++++++++++++++++++++++++++++++++++++++++--
- 2 files changed, 47 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
-index bf8100c..3ab7ac9 100644
---- a/drivers/ata/ahci.h
-+++ b/drivers/ata/ahci.h
-@@ -37,6 +37,7 @@
-
- #include <linux/clk.h>
- #include <linux/libata.h>
-+#include <linux/phy/phy.h>
- #include <linux/regulator/consumer.h>
-
- /* Enclosure Management Control */
-@@ -325,6 +326,7 @@ struct ahci_host_priv {
- u32 em_msg_type; /* EM message type */
- struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
- struct regulator *target_pwr; /* Optional */
-+ struct phy *phy; /* If platform uses phy */
- void *plat_data; /* Other platform data */
- /*
- * Optional ahci_start_engine override, if not set this gets set to the
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index d7e55ba..99d38c1 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -23,6 +23,7 @@
- #include <linux/platform_device.h>
- #include <linux/libata.h>
- #include <linux/ahci_platform.h>
-+#include <linux/phy/phy.h>
- #include "ahci.h"
-
- static void ahci_host_stop(struct ata_host *host);
-@@ -147,6 +148,7 @@ void ahci_platform_disable_clks(struct ahci_host_priv *hpriv)
- * the following order:
- * 1) Regulator
- * 2) Clocks (through ahci_platform_enable_clks)
-+ * 3) Phy
- *
- * If resource enabling fails at any point the previous enabled
- * resources are disabled in reverse order.
-@@ -171,8 +173,23 @@ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv)
- if (rc)
- goto disable_regulator;
-
-+ if (hpriv->phy) {
-+ rc = phy_init(hpriv->phy);
-+ if (rc)
-+ goto disable_clks;
-+
-+ rc = phy_power_on(hpriv->phy);
-+ if (rc) {
-+ phy_exit(hpriv->phy);
-+ goto disable_clks;
-+ }
-+ }
-+
- return 0;
-
-+disable_clks:
-+ ahci_platform_disable_clks(hpriv);
-+
- disable_regulator:
- if (hpriv->target_pwr)
- regulator_disable(hpriv->target_pwr);
-@@ -186,14 +203,20 @@ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv)
- *
- * This function disables all ahci_platform managed resources in
- * the following order:
-- * 1) Clocks (through ahci_platform_disable_clks)
-- * 2) Regulator
-+ * 1) Phy
-+ * 2) Clocks (through ahci_platform_disable_clks)
-+ * 3) Regulator
- *
- * LOCKING:
- * None.
- */
- void ahci_platform_disable_resources(struct ahci_host_priv *hpriv)
- {
-+ if (hpriv->phy) {
-+ phy_power_off(hpriv->phy);
-+ phy_exit(hpriv->phy);
-+ }
-+
- ahci_platform_disable_clks(hpriv);
-
- if (hpriv->target_pwr)
-@@ -222,6 +245,7 @@ static void ahci_platform_put_resources(struct device *dev, void *res)
- * 2) regulator for controlling the targets power (optional)
- * 3) 0 - AHCI_MAX_CLKS clocks, as specified in the devs devicetree node,
- * or for non devicetree enabled platforms a single clock
-+ * 4) phy (optional)
- *
- * LOCKING:
- * None.
-@@ -283,6 +307,25 @@ struct ahci_host_priv *ahci_platform_get_resources(
- hpriv->clks[i] = clk;
- }
-
-+ hpriv->phy = devm_phy_get(dev, "sata-phy");
-+ if (IS_ERR(hpriv->phy)) {
-+ rc = PTR_ERR(hpriv->phy);
-+ switch (rc) {
-+ case -ENODEV:
-+ case -ENOSYS:
-+ /* continue normally */
-+ hpriv->phy = NULL;
-+ break;
-+
-+ case -EPROBE_DEFER:
-+ goto err_out;
-+
-+ default:
-+ dev_err(dev, "couldn't get sata-phy\n");
-+ goto err_out;
-+ }
-+ }
-+
- devres_remove_group(dev, NULL);
- return hpriv;
-
---
-1.8.5.5
-
+++ /dev/null
-From 48379fed3987d587a25a48e155872e9d3125490d Mon Sep 17 00:00:00 2001
-From: Roger Quadros <rogerq@ti.com>
-Date: Wed, 9 Oct 2013 15:08:59 +0300
-Subject: [PATCH] ata: ahci_platform: runtime resume the device before use
-
-On OMAP platforms the device needs to be runtime resumed before
-it can be accessed. The OMAP HWMOD framework takes care of
-enabling the module and its resources based on the
-device's runtime PM state.
-
-In this patch we runtime resume during .probe() and runtime suspend
-after .remove().
-
-We also update the runtime PM state during .resume().
-
-CC: Balaji T K <balajitk@ti.com>
-Signed-off-by: Roger Quadros <rogerq@ti.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci.h | 1 +
- drivers/ata/ahci_platform.c | 15 +++++++++++++++
- 2 files changed, 16 insertions(+)
-
-diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
-index 3ab7ac9..51af275b 100644
---- a/drivers/ata/ahci.h
-+++ b/drivers/ata/ahci.h
-@@ -324,6 +324,7 @@ struct ahci_host_priv {
- u32 em_loc; /* enclosure management location */
- u32 em_buf_sz; /* EM buffer size in byte */
- u32 em_msg_type; /* EM message type */
-+ bool got_runtime_pm; /* Did we do pm_runtime_get? */
- struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
- struct regulator *target_pwr; /* Optional */
- struct phy *phy; /* If platform uses phy */
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 99d38c1..75698a4 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -24,6 +24,7 @@
- #include <linux/libata.h>
- #include <linux/ahci_platform.h>
- #include <linux/phy/phy.h>
-+#include <linux/pm_runtime.h>
- #include "ahci.h"
-
- static void ahci_host_stop(struct ata_host *host);
-@@ -229,6 +230,11 @@ static void ahci_platform_put_resources(struct device *dev, void *res)
- struct ahci_host_priv *hpriv = res;
- int c;
-
-+ if (hpriv->got_runtime_pm) {
-+ pm_runtime_put_sync(dev);
-+ pm_runtime_disable(dev);
-+ }
-+
- for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++)
- clk_put(hpriv->clks[c]);
- }
-@@ -326,6 +332,10 @@ struct ahci_host_priv *ahci_platform_get_resources(
- }
- }
-
-+ pm_runtime_enable(dev);
-+ pm_runtime_get_sync(dev);
-+ hpriv->got_runtime_pm = true;
-+
- devres_remove_group(dev, NULL);
- return hpriv;
-
-@@ -635,6 +645,11 @@ int ahci_platform_resume(struct device *dev)
- if (rc)
- goto disable_resources;
-
-+ /* We resumed so update PM runtime state */
-+ pm_runtime_disable(dev);
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+
- return 0;
-
- disable_resources:
---
-1.8.5.5
-
+++ /dev/null
-From 09de09bc2c236dccb0ed5ed38015e829550a5c28 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 23 Feb 2014 11:37:17 +0100
-Subject: [PATCH] ahci_sunxi: Use msleep instead of mdelay
-
-ahci_sunxi_phy_init is called from the probe and resume code paths, and
-sleeping is safe in both, so use msleep instead of mdelay.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci_sunxi.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
-index 001f7dfc..d1bf3f7 100644
---- a/drivers/ata/ahci_sunxi.c
-+++ b/drivers/ata/ahci_sunxi.c
-@@ -90,7 +90,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
-
- /* This magic is from the original code */
- writel(0, reg_base + AHCI_RWCR);
-- mdelay(5);
-+ msleep(5);
-
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
-@@ -105,7 +105,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
- (0x7 << 20), (0x3 << 20));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
- (0x1f << 5), (0x19 << 5));
-- mdelay(5);
-+ msleep(5);
-
- sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
-
-@@ -137,7 +137,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
- udelay(1);
- } while (1);
-
-- mdelay(15);
-+ msleep(15);
-
- writel(0x7, reg_base + AHCI_RWCR);
-
---
-1.8.5.5
-
+++ /dev/null
-From 3cae1df0e62432a80db86c80e261eb9bbed326ee Mon Sep 17 00:00:00 2001
-From: Oliver Schinagl <oliver@schinagl.nl>
-Date: Tue, 3 Dec 2013 12:10:11 +0100
-Subject: [PATCH] ARM: sun4i: dt: Add ahci / sata support
-
-This patch adds sunxi sata support to A10 boards that have such a connector.
-Some boards also feature a regulator via a GPIO and support for this is also
-added.
-
-Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-a1000.dts | 4 ++++
- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 6 +++++
- arch/arm/boot/dts/sun4i-a10.dtsi | 8 +++++++
- arch/arm/boot/dts/sunxi-ahci-reg.dtsi | 36 ++++++++++++++++++++++++++++++
- 4 files changed, 54 insertions(+)
- create mode 100644 arch/arm/boot/dts/sunxi-ahci-reg.dtsi
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-index cbd2e13..d6ec839 100644
---- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-@@ -35,6 +35,10 @@
- };
- };
-
-+ ahci: sata@01c18000 {
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- emac_power_pin_a1000: emac_power_pin@0 {
- allwinner,pins = "PH15";
-diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-index b139ee6..6df237d8 100644
---- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-@@ -12,6 +12,7 @@
-
- /dts-v1/;
- /include/ "sun4i-a10.dtsi"
-+/include/ "sunxi-ahci-reg.dtsi"
-
- / {
- model = "Cubietech Cubieboard";
-@@ -33,6 +34,11 @@
- };
- };
-
-+ ahci: sata@01c18000 {
-+ target-supply = <®_ahci_5v>;
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- led_pins_cubieboard: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 336dbec..454077a 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -338,6 +338,14 @@
- #size-cells = <0>;
- };
-
-+ ahci: sata@01c18000 {
-+ compatible = "allwinner,sun4i-a10-ahci";
-+ reg = <0x01c18000 0x1000>;
-+ interrupts = <56>;
-+ clocks = <&pll6 0>, <&ahb_gates 25>;
-+ status = "disabled";
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
-diff --git a/arch/arm/boot/dts/sunxi-ahci-reg.dtsi b/arch/arm/boot/dts/sunxi-ahci-reg.dtsi
-new file mode 100644
-index 0000000..7072af1
---- /dev/null
-+++ b/arch/arm/boot/dts/sunxi-ahci-reg.dtsi
-@@ -0,0 +1,36 @@
-+/*
-+ * sunxi boards sata target power supply common code
-+ *
-+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/ {
-+ soc@01c00000 {
-+ pio: pinctrl@01c20800 {
-+ ahci_pwr_pin_a: ahci_pwr_pin@0 {
-+ allwinner,pins = "PB8";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+ };
-+ };
-+
-+ reg_ahci_5v: ahci-5v {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&ahci_pwr_pin_a>;
-+ regulator-name = "ahci-5v";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ gpio = <&pio 1 8 0>;
-+ };
-+};
---
-1.8.5.5
-
+++ /dev/null
-From c7b99b7afc3882c1b38a15da8d1625dd448c6fee Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Fri, 3 Jan 2014 10:27:51 +0100
-Subject: [PATCH] ARM: sun7i: dt: Add ahci / sata support
-
-This patch adds sunxi sata support to A20 boards that have such a connector.
-Some boards also feature a regulator via a GPIO and support for this is also
-added.
-
-Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 6 ++++++
- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 18 ++++++++++++++++++
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 6 ++++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
- 4 files changed, 38 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-index 7bf4935..07823c2 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-@@ -13,12 +13,18 @@
-
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
-+/include/ "sunxi-ahci-reg.dtsi"
-
- / {
- model = "Cubietech Cubieboard2";
- compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ ahci: sata@01c18000 {
-+ target-supply = <®_ahci_5v>;
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- led_pins_cubieboard2: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-index 025ce52..403bd2e 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-@@ -13,13 +13,26 @@
-
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
-+/include/ "sunxi-ahci-reg.dtsi"
-
- / {
- model = "Cubietech Cubietruck";
- compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ ahci: sata@01c18000 {
-+ target-supply = <®_ahci_5v>;
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
-+ ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
-+ allwinner,pins = "PH12";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
- led_pins_cubietruck: led_pins@0 {
- allwinner,pins = "PH7", "PH11", "PH20", "PH21";
- allwinner,function = "gpio_out";
-@@ -90,4 +103,10 @@
- gpios = <&pio 7 7 0>;
- };
- };
-+
-+ reg_ahci_5v: ahci-5v {
-+ pinctrl-0 = <&ahci_pwr_pin_cubietruck>;
-+ gpio = <&pio 7 12 0>;
-+ status = "okay";
-+ };
- };
-diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-index b02a796..d5c6799 100644
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -13,12 +13,18 @@
-
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
-+/include/ "sunxi-ahci-reg.dtsi"
-
- / {
- model = "Olimex A20-Olinuxino Micro";
- compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ ahci: sata@01c18000 {
-+ target-supply = <®_ahci_5v>;
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PH2";
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index daaafd0..3385994 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -392,6 +392,14 @@
- #size-cells = <0>;
- };
-
-+ ahci: sata@01c18000 {
-+ compatible = "allwinner,sun4i-a10-ahci";
-+ reg = <0x01c18000 0x1000>;
-+ interrupts = <0 56 4>;
-+ clocks = <&pll6 0>, <&ahb_gates 25>;
-+ status = "disabled";
-+ };
-+
- pio: pinctrl@01c20800 {
- compatible = "allwinner,sun7i-a20-pinctrl";
- reg = <0x01c20800 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From 00f082cbfe43bd45ddcff3572875ee9fbeafdfdd Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <david.lanzendoerfer@o2s.ch>
-Date: Sat, 15 Feb 2014 16:37:33 +0100
-Subject: [PATCH] ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner
- sunxi SoCs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This is based on the driver Allwinner ships in their Android kernel sources.
-
-Initial porting to upstream kernels done by David Lanzendörfer, additional
-fixes and cleanups by Hans de Goede.
-
-It uses dma in bus-master mode using a built-in designware idmac controller,
-which is identical to the one found in the mmc-dw hosts.
-The rest of the host is not identical to mmc-dw.
-
-Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/Kconfig | 7 +
- drivers/mmc/host/Makefile | 2 +
- drivers/mmc/host/sunxi-mmc.c | 876 +++++++++++++++++++++++++++++++++++++++++++
- drivers/mmc/host/sunxi-mmc.h | 239 ++++++++++++
- 4 files changed, 1124 insertions(+)
- create mode 100644 drivers/mmc/host/sunxi-mmc.c
- create mode 100644 drivers/mmc/host/sunxi-mmc.h
-
-diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
-index 1384f67..7caf266 100644
---- a/drivers/mmc/host/Kconfig
-+++ b/drivers/mmc/host/Kconfig
-@@ -689,3 +689,10 @@ config MMC_REALTEK_PCI
- help
- Say Y here to include driver code to support SD/MMC card interface
- of Realtek PCI-E card reader
-+
-+config MMC_SUNXI
-+ tristate "Allwinner sunxi SD/MMC Host Controller support"
-+ depends on ARCH_SUNXI
-+ help
-+ This selects support for the SD/MMC Host Controller on
-+ Allwinner sunxi SoCs.
-diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
-index 3483b6b..f3c7c243 100644
---- a/drivers/mmc/host/Makefile
-+++ b/drivers/mmc/host/Makefile
-@@ -54,6 +54,8 @@ obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
-
- obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
-
-+obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o
-+
- obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
- obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o
- obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-new file mode 100644
-index 0000000..2dc446c
---- /dev/null
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -0,0 +1,876 @@
-+/*
-+ * Driver for sunxi SD/MMC host controllers
-+ * (C) Copyright 2014-2015 Reuuimlla Technology Co., Ltd.
-+ * (C) Copyright 2014-2015 Aaron Maoye <leafy.myeh@reuuimllatech.com>
-+ * (C) Copyright 2014-2015 O2S GmbH <www.o2s.ch>
-+ * (C) Copyright 2014-2015 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
-+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/device.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+
-+#include <linux/clk.h>
-+#include <linux/clk-private.h>
-+#include <linux/clk/sunxi.h>
-+
-+#include <linux/gpio.h>
-+#include <linux/platform_device.h>
-+#include <linux/spinlock.h>
-+#include <linux/scatterlist.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/slab.h>
-+#include <linux/regulator/consumer.h>
-+
-+#include <linux/of_address.h>
-+#include <linux/of_gpio.h>
-+#include <linux/of_platform.h>
-+
-+#include <linux/mmc/host.h>
-+#include <linux/mmc/sd.h>
-+#include <linux/mmc/sdio.h>
-+#include <linux/mmc/mmc.h>
-+#include <linux/mmc/core.h>
-+#include <linux/mmc/card.h>
-+#include <linux/mmc/slot-gpio.h>
-+
-+#include "sunxi-mmc.h"
-+
-+static int sunxi_mmc_init_host(struct mmc_host *mmc)
-+{
-+ u32 rval;
-+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
-+ int ret;
-+
-+ ret = clk_prepare_enable(smc_host->clk_ahb);
-+ if (ret) {
-+ dev_err(mmc_dev(smc_host->mmc), "AHB clk err %d\n", ret);
-+ return ret;
-+ }
-+ ret = clk_prepare_enable(smc_host->clk_mod);
-+ if (ret) {
-+ dev_err(mmc_dev(smc_host->mmc), "MOD clk err %d\n", ret);
-+ clk_disable_unprepare(smc_host->clk_ahb);
-+ return ret;
-+ }
-+
-+ /* reset controller */
-+ rval = mci_readl(smc_host, REG_GCTRL) | SDXC_HARDWARE_RESET;
-+ mci_writel(smc_host, REG_GCTRL, rval);
-+
-+ mci_writel(smc_host, REG_FTRGL, 0x20070008);
-+ mci_writel(smc_host, REG_TMOUT, 0xffffffff);
-+ mci_writel(smc_host, REG_IMASK, smc_host->sdio_imask);
-+ mci_writel(smc_host, REG_RINTR, 0xffffffff);
-+ mci_writel(smc_host, REG_DBGC, 0xdeb);
-+ mci_writel(smc_host, REG_FUNS, 0xceaa0000);
-+ mci_writel(smc_host, REG_DLBA, smc_host->sg_dma);
-+ rval = mci_readl(smc_host, REG_GCTRL)|SDXC_INTERRUPT_ENABLE_BIT;
-+ rval &= ~SDXC_ACCESS_DONE_DIRECT;
-+ mci_writel(smc_host, REG_GCTRL, rval);
-+
-+ return 0;
-+}
-+
-+static void sunxi_mmc_exit_host(struct sunxi_mmc_host *smc_host)
-+{
-+ mci_writel(smc_host, REG_GCTRL, SDXC_HARDWARE_RESET);
-+ clk_disable_unprepare(smc_host->clk_ahb);
-+ clk_disable_unprepare(smc_host->clk_mod);
-+}
-+
-+/* /\* UHS-I Operation Modes */
-+/* * DS 25MHz 12.5MB/s 3.3V */
-+/* * HS 50MHz 25MB/s 3.3V */
-+/* * SDR12 25MHz 12.5MB/s 1.8V */
-+/* * SDR25 50MHz 25MB/s 1.8V */
-+/* * SDR50 100MHz 50MB/s 1.8V */
-+/* * SDR104 208MHz 104MB/s 1.8V */
-+/* * DDR50 50MHz 50MB/s 1.8V */
-+/* * MMC Operation Modes */
-+/* * DS 26MHz 26MB/s 3/1.8/1.2V */
-+/* * HS 52MHz 52MB/s 3/1.8/1.2V */
-+/* * HSDDR 52MHz 104MB/s 3/1.8/1.2V */
-+/* * HS200 200MHz 200MB/s 1.8/1.2V */
-+/* * */
-+/* * Spec. Timing */
-+/* * SD3.0 */
-+/* * Fcclk Tcclk Fsclk Tsclk Tis Tih odly RTis RTih */
-+/* * 400K 2.5us 24M 41ns 5ns 5ns 1 2209ns 41ns */
-+/* * 25M 40ns 600M 1.67ns 5ns 5ns 3 14.99ns 5.01ns */
-+/* * 50M 20ns 600M 1.67ns 6ns 2ns 3 14.99ns 5.01ns */
-+/* * 50MDDR 20ns 600M 1.67ns 6ns 0.8ns 2 6.67ns 3.33ns */
-+/* * 104M 9.6ns 600M 1.67ns 3ns 0.8ns 1 7.93ns 1.67ns */
-+/* * 208M 4.8ns 600M 1.67ns 1.4ns 0.8ns 1 3.33ns 1.67ns */
-+
-+/* * 25M 40ns 300M 3.33ns 5ns 5ns 2 13.34ns 6.66ns */
-+/* * 50M 20ns 300M 3.33ns 6ns 2ns 2 13.34ns 6.66ns */
-+/* * 50MDDR 20ns 300M 3.33ns 6ns 0.8ns 1 6.67ns 3.33ns */
-+/* * 104M 9.6ns 300M 3.33ns 3ns 0.8ns 0 7.93ns 1.67ns */
-+/* * 208M 4.8ns 300M 3.33ns 1.4ns 0.8ns 0 3.13ns 1.67ns */
-+
-+/* * eMMC4.5 */
-+/* * 400K 2.5us 24M 41ns 3ns 3ns 1 2209ns 41ns */
-+/* * 25M 40ns 600M 1.67ns 3ns 3ns 3 14.99ns 5.01ns */
-+/* * 50M 20ns 600M 1.67ns 3ns 3ns 3 14.99ns 5.01ns */
-+/* * 50MDDR 20ns 600M 1.67ns 2.5ns 2.5ns 2 6.67ns 3.33ns */
-+/* * 200M 5ns 600M 1.67ns 1.4ns 0.8ns 1 3.33ns 1.67ns */
-+/* *\/ */
-+
-+static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
-+ struct mmc_data *data)
-+{
-+ struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
-+ struct sunxi_idma_des *pdes_pa = (struct sunxi_idma_des *)host->sg_dma;
-+ int i, max_len = (1 << host->idma_des_size_bits);
-+
-+ for (i = 0; i < data->sg_len; i++) {
-+ pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
-+ SDXC_IDMAC_DES0_DIC;
-+
-+ if (data->sg[i].length == max_len)
-+ pdes[i].buf_size = 0; /* 0 == max_len */
-+ else
-+ pdes[i].buf_size = data->sg[i].length;
-+
-+ pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
-+ pdes[i].buf_addr_ptr2 = (u32)&pdes_pa[i + 1];
-+ }
-+
-+ pdes[0].config |= SDXC_IDMAC_DES0_FD;
-+ pdes[i - 1].config = SDXC_IDMAC_DES0_OWN | SDXC_IDMAC_DES0_LD;
-+
-+ wmb(); /* Ensure idma_des hit main mem before we start the idmac */
-+}
-+
-+static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
-+{
-+ if (data->flags & MMC_DATA_WRITE)
-+ return DMA_TO_DEVICE;
-+ else
-+ return DMA_FROM_DEVICE;
-+}
-+
-+static int sunxi_mmc_prepare_dma(struct sunxi_mmc_host *smc_host,
-+ struct mmc_data *data)
-+{
-+ u32 dma_len;
-+ u32 i;
-+ u32 temp;
-+ struct scatterlist *sg;
-+
-+ dma_len = dma_map_sg(mmc_dev(smc_host->mmc), data->sg, data->sg_len,
-+ sunxi_mmc_get_dma_dir(data));
-+ if (dma_len == 0) {
-+ dev_err(mmc_dev(smc_host->mmc), "dma_map_sg failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ for_each_sg(data->sg, sg, data->sg_len, i) {
-+ if (sg->offset & 3 || sg->length & 3) {
-+ dev_err(mmc_dev(smc_host->mmc),
-+ "unaligned scatterlist: os %x length %d\n",
-+ sg->offset, sg->length);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ sunxi_mmc_init_idma_des(smc_host, data);
-+
-+ temp = mci_readl(smc_host, REG_GCTRL);
-+ temp |= SDXC_DMA_ENABLE_BIT;
-+ mci_writel(smc_host, REG_GCTRL, temp);
-+ temp |= SDXC_DMA_RESET;
-+ mci_writel(smc_host, REG_GCTRL, temp);
-+ mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
-+
-+ if (!(data->flags & MMC_DATA_WRITE))
-+ mci_writel(smc_host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
-+
-+ mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
-+
-+ return 0;
-+}
-+
-+static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
-+ struct mmc_request *req)
-+{
-+ u32 cmd_val = SDXC_START | SDXC_RESPONSE_EXPIRE | SDXC_STOP_ABORT_CMD
-+ | SDXC_CHECK_RESPONSE_CRC | MMC_STOP_TRANSMISSION;
-+ u32 ri = 0;
-+ unsigned long expire = jiffies + msecs_to_jiffies(1000);
-+
-+ mci_writel(host, REG_CARG, 0);
-+ mci_writel(host, REG_CMDR, cmd_val);
-+
-+ do {
-+ ri = mci_readl(host, REG_RINTR);
-+ } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
-+ time_before(jiffies, expire));
-+
-+ if (ri & SDXC_INTERRUPT_ERROR_BIT) {
-+ dev_err(mmc_dev(host->mmc), "send stop command failed\n");
-+ if (req->stop)
-+ req->stop->resp[0] = -ETIMEDOUT;
-+ } else {
-+ if (req->stop)
-+ req->stop->resp[0] = mci_readl(host, REG_RESP0);
-+ }
-+
-+ mci_writel(host, REG_RINTR, 0xffff);
-+}
-+
-+static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *smc_host)
-+{
-+ struct mmc_command *cmd = smc_host->mrq->cmd;
-+ struct mmc_data *data = smc_host->mrq->data;
-+
-+ /* For some cmds timeout is normal with sd/mmc cards */
-+ if ((smc_host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == SDXC_RESPONSE_TIMEOUT &&
-+ (cmd->opcode == SD_IO_SEND_OP_COND || cmd->opcode == SD_IO_RW_DIRECT))
-+ return;
-+
-+ dev_err(mmc_dev(smc_host->mmc),
-+ "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
-+ smc_host->mmc->index, cmd->opcode,
-+ data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
-+ smc_host->int_sum & SDXC_RESPONSE_ERROR ? " RE" : "",
-+ smc_host->int_sum & SDXC_RESPONSE_CRC_ERROR ? " RCE" : "",
-+ smc_host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
-+ smc_host->int_sum & SDXC_RESPONSE_TIMEOUT ? " RTO" : "",
-+ smc_host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
-+ smc_host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
-+ smc_host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
-+ smc_host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
-+ smc_host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
-+ );
-+}
-+
-+static void sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
-+{
-+ struct mmc_request *mrq;
-+ unsigned long iflags;
-+
-+ spin_lock_irqsave(&host->lock, iflags);
-+
-+ mrq = host->mrq;
-+ if (!mrq) {
-+ spin_unlock_irqrestore(&host->lock, iflags);
-+ dev_err(mmc_dev(host->mmc), "no request to finalize\n");
-+ return;
-+ }
-+
-+ if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
-+ sunxi_mmc_dump_errinfo(host);
-+ mrq->cmd->error = -ETIMEDOUT;
-+ if (mrq->data)
-+ mrq->data->error = -ETIMEDOUT;
-+ if (mrq->stop)
-+ mrq->stop->error = -ETIMEDOUT;
-+ } else {
-+ if (mrq->cmd->flags & MMC_RSP_136) {
-+ mrq->cmd->resp[0] = mci_readl(host, REG_RESP3);
-+ mrq->cmd->resp[1] = mci_readl(host, REG_RESP2);
-+ mrq->cmd->resp[2] = mci_readl(host, REG_RESP1);
-+ mrq->cmd->resp[3] = mci_readl(host, REG_RESP0);
-+ } else {
-+ mrq->cmd->resp[0] = mci_readl(host, REG_RESP0);
-+ }
-+ if (mrq->data)
-+ mrq->data->bytes_xfered =
-+ mrq->data->blocks * mrq->data->blksz;
-+ }
-+
-+ if (mrq->data) {
-+ struct mmc_data *data = mrq->data;
-+ u32 temp;
-+
-+ mci_writel(host, REG_IDST, 0x337);
-+ mci_writel(host, REG_DMAC, 0);
-+ temp = mci_readl(host, REG_GCTRL);
-+ mci_writel(host, REG_GCTRL, temp|SDXC_DMA_RESET);
-+ temp &= ~SDXC_DMA_ENABLE_BIT;
-+ mci_writel(host, REG_GCTRL, temp);
-+ temp |= SDXC_FIFO_RESET;
-+ mci_writel(host, REG_GCTRL, temp);
-+ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
-+ sunxi_mmc_get_dma_dir(data));
-+ }
-+
-+ mci_writel(host, REG_RINTR, 0xffff);
-+
-+ dev_dbg(mmc_dev(host->mmc), "req done, resp %08x %08x %08x %08x\n",
-+ mrq->cmd->resp[0], mrq->cmd->resp[1],
-+ mrq->cmd->resp[2], mrq->cmd->resp[3]);
-+
-+ host->mrq = NULL;
-+ host->int_sum = 0;
-+ host->wait_dma = 0;
-+
-+ spin_unlock_irqrestore(&host->lock, iflags);
-+
-+ if (mrq->data && mrq->data->error) {
-+ dev_err(mmc_dev(host->mmc),
-+ "data error, sending stop command\n");
-+ sunxi_mmc_send_manual_stop(host, mrq);
-+ }
-+
-+ mmc_request_done(host->mmc, mrq);
-+}
-+
-+static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
-+{
-+ struct sunxi_mmc_host *host = dev_id;
-+ u32 finalize = 0;
-+ u32 sdio_int = 0;
-+ u32 msk_int;
-+ u32 idma_int;
-+
-+ spin_lock(&host->lock);
-+
-+ idma_int = mci_readl(host, REG_IDST);
-+ msk_int = mci_readl(host, REG_MISTA);
-+
-+ dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
-+ host->mrq, msk_int, idma_int);
-+
-+ if (host->mrq) {
-+ if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
-+ host->wait_dma = 0;
-+
-+ host->int_sum |= msk_int;
-+
-+ /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finishing the req */
-+ if ((host->int_sum & SDXC_RESPONSE_TIMEOUT) &&
-+ !(host->int_sum & SDXC_COMMAND_DONE))
-+ mci_writel(host, REG_IMASK,
-+ host->sdio_imask | SDXC_COMMAND_DONE);
-+ else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
-+ finalize = 1; /* Don't wait for dma on error */
-+ else if (host->int_sum & SDXC_INTERRUPT_DONE_BIT && !host->wait_dma)
-+ finalize = 1; /* Done */
-+
-+ if (finalize) {
-+ mci_writel(host, REG_IMASK, host->sdio_imask);
-+ mci_writel(host, REG_IDIE, 0);
-+ }
-+ }
-+
-+ if (msk_int & SDXC_SDIO_INTERRUPT)
-+ sdio_int = 1;
-+
-+ mci_writel(host, REG_RINTR, msk_int);
-+ mci_writel(host, REG_IDST, idma_int);
-+
-+ spin_unlock(&host->lock);
-+
-+ if (finalize)
-+ tasklet_schedule(&host->tasklet);
-+
-+ if (sdio_int)
-+ mmc_signal_sdio_irq(host->mmc);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static void sunxi_mmc_tasklet(unsigned long data)
-+{
-+ struct sunxi_mmc_host *smc_host = (struct sunxi_mmc_host *) data;
-+ sunxi_mmc_finalize_request(smc_host);
-+}
-+
-+static void sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
-+{
-+ unsigned long expire = jiffies + msecs_to_jiffies(2000);
-+ u32 rval;
-+
-+ rval = mci_readl(host, REG_CLKCR);
-+ rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
-+
-+ if (oclk_en)
-+ rval |= SDXC_CARD_CLOCK_ON;
-+
-+ if (!host->io_flag)
-+ rval |= SDXC_LOW_POWER_ON;
-+
-+ mci_writel(host, REG_CLKCR, rval);
-+
-+ rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
-+ if (host->voltage_switching)
-+ rval |= SDXC_VOLTAGE_SWITCH;
-+ mci_writel(host, REG_CMDR, rval);
-+
-+ do {
-+ rval = mci_readl(host, REG_CMDR);
-+ } while (time_before(jiffies, expire) && (rval & SDXC_START));
-+
-+ if (rval & SDXC_START) {
-+ dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
-+ host->ferror = 1;
-+ }
-+}
-+
-+static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *smc_host,
-+ u32 oclk_dly, u32 sclk_dly)
-+{
-+ unsigned long iflags;
-+ struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
-+
-+ spin_lock_irqsave(&smc_host->lock, iflags);
-+ clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
-+ spin_unlock_irqrestore(&smc_host->lock, iflags);
-+}
-+
-+struct sunxi_mmc_clk_dly mmc_clk_dly[MMC_CLK_MOD_NUM] = {
-+ { MMC_CLK_400K, 0, 7 },
-+ { MMC_CLK_25M, 0, 5 },
-+ { MMC_CLK_50M, 3, 5 },
-+ { MMC_CLK_50MDDR, 2, 4 },
-+ { MMC_CLK_50MDDR_8BIT, 2, 4 },
-+ { MMC_CLK_100M, 1, 4 },
-+ { MMC_CLK_200M, 1, 4 },
-+};
-+
-+static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
-+ unsigned int rate)
-+{
-+ u32 newrate;
-+ u32 src_clk;
-+ u32 oclk_dly;
-+ u32 sclk_dly;
-+ u32 temp;
-+ struct sunxi_mmc_clk_dly *dly = NULL;
-+
-+ newrate = clk_round_rate(smc_host->clk_mod, rate);
-+ if (smc_host->clk_mod_rate == newrate) {
-+ dev_dbg(mmc_dev(smc_host->mmc), "clk already %d, rounded %d\n",
-+ rate, newrate);
-+ return;
-+ }
-+
-+ dev_dbg(mmc_dev(smc_host->mmc), "setting clk to %d, rounded %d\n",
-+ rate, newrate);
-+
-+ /* setting clock rate */
-+ clk_disable(smc_host->clk_mod);
-+ clk_set_rate(smc_host->clk_mod, newrate);
-+ clk_enable(smc_host->clk_mod);
-+ smc_host->clk_mod_rate = newrate = clk_get_rate(smc_host->clk_mod);
-+ dev_dbg(mmc_dev(smc_host->mmc), "clk is now %d\n", newrate);
-+
-+ sunxi_mmc_oclk_onoff(smc_host, 0);
-+ /* clear internal divider */
-+ temp = mci_readl(smc_host, REG_CLKCR);
-+ temp &= ~0xff;
-+ mci_writel(smc_host, REG_CLKCR, temp);
-+
-+ /* determine delays */
-+ if (rate <= 400000) {
-+ dly = &mmc_clk_dly[MMC_CLK_400K];
-+ } else if (rate <= 25000000) {
-+ dly = &mmc_clk_dly[MMC_CLK_25M];
-+ } else if (rate <= 50000000) {
-+ if (smc_host->ddr) {
-+ if (smc_host->bus_width == 8)
-+ dly = &mmc_clk_dly[MMC_CLK_50MDDR_8BIT];
-+ else
-+ dly = &mmc_clk_dly[MMC_CLK_50MDDR];
-+ } else {
-+ dly = &mmc_clk_dly[MMC_CLK_50M];
-+ }
-+ } else if (rate <= 104000000) {
-+ dly = &mmc_clk_dly[MMC_CLK_100M];
-+ } else if (rate <= 208000000) {
-+ dly = &mmc_clk_dly[MMC_CLK_200M];
-+ } else {
-+ dly = &mmc_clk_dly[MMC_CLK_50M];
-+ }
-+
-+ oclk_dly = dly->oclk_dly;
-+ sclk_dly = dly->sclk_dly;
-+
-+ src_clk = clk_get_rate(clk_get_parent(smc_host->clk_mod));
-+
-+ if (src_clk >= 300000000 && src_clk <= 400000000) {
-+ if (oclk_dly)
-+ oclk_dly--;
-+ if (sclk_dly)
-+ sclk_dly--;
-+ }
-+
-+ sunxi_mmc_set_clk_dly(smc_host, oclk_dly, sclk_dly);
-+ sunxi_mmc_oclk_onoff(smc_host, 1);
-+
-+ /* oclk_onoff sets various irq status bits, clear these */
-+ mci_writel(smc_host, REG_RINTR,
-+ mci_readl(smc_host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
-+}
-+
-+static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
-+{
-+ struct sunxi_mmc_host *host = mmc_priv(mmc);
-+ u32 temp;
-+ s32 err;
-+
-+ /* Set the power state */
-+ switch (ios->power_mode) {
-+ case MMC_POWER_ON:
-+ break;
-+
-+ case MMC_POWER_UP:
-+ if (!IS_ERR(host->vmmc)) {
-+ mmc_regulator_set_ocr(host->mmc, host->vmmc, ios->vdd);
-+ udelay(200);
-+ }
-+
-+ err = sunxi_mmc_init_host(mmc);
-+ if (err) {
-+ host->ferror = 1;
-+ return;
-+ }
-+ enable_irq(host->irq);
-+
-+ dev_dbg(mmc_dev(host->mmc), "power on!\n");
-+ host->ferror = 0;
-+ break;
-+
-+ case MMC_POWER_OFF:
-+ dev_dbg(mmc_dev(host->mmc), "power off!\n");
-+ disable_irq(host->irq);
-+ sunxi_mmc_exit_host(host);
-+ if (!IS_ERR(host->vmmc))
-+ mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
-+ host->ferror = 0;
-+ break;
-+ }
-+
-+ /* set bus width */
-+ switch (ios->bus_width) {
-+ case MMC_BUS_WIDTH_1:
-+ mci_writel(host, REG_WIDTH, SDXC_WIDTH1);
-+ host->bus_width = 1;
-+ break;
-+ case MMC_BUS_WIDTH_4:
-+ mci_writel(host, REG_WIDTH, SDXC_WIDTH4);
-+ host->bus_width = 4;
-+ break;
-+ case MMC_BUS_WIDTH_8:
-+ mci_writel(host, REG_WIDTH, SDXC_WIDTH8);
-+ host->bus_width = 8;
-+ break;
-+ }
-+
-+ /* set ddr mode */
-+ temp = mci_readl(host, REG_GCTRL);
-+ if (ios->timing == MMC_TIMING_UHS_DDR50) {
-+ temp |= SDXC_DDR_MODE;
-+ host->ddr = 1;
-+ } else {
-+ temp &= ~SDXC_DDR_MODE;
-+ host->ddr = 0;
-+ }
-+ mci_writel(host, REG_GCTRL, temp);
-+
-+ /* set up clock */
-+ if (ios->clock && ios->power_mode) {
-+ dev_dbg(mmc_dev(host->mmc), "ios->clock: %d\n", ios->clock);
-+ sunxi_mmc_clk_set_rate(host, ios->clock);
-+ usleep_range(50000, 55000);
-+ }
-+}
-+
-+static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
-+{
-+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
-+ unsigned long flags;
-+ int ret;
-+ u32 imask;
-+
-+ spin_lock_irqsave(&smc_host->lock, flags);
-+
-+ /* Make sure the controller is in a sane state before enabling irqs */
-+ ret = sunxi_mmc_init_host(host->mmc);
-+ if (ret) {
-+ spin_unlock_irqrestore(&smc_host->lock, flags);
-+ return ret;
-+ }
-+
-+ imask = mci_readl(smc_host, REG_IMASK);
-+ if (enable) {
-+ smc_host->sdio_imask = SDXC_SDIO_INTERRUPT;
-+ imask |= SDXC_SDIO_INTERRUPT;
-+ } else {
-+ smc_host->sdio_imask = 0;
-+ imask &= ~SDXC_SDIO_INTERRUPT;
-+ }
-+ mci_writel(smc_host, REG_IMASK, imask);
-+ spin_unlock_irqrestore(&smc_host->lock, flags);
-+}
-+
-+static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
-+{
-+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
-+ mci_writel(smc_host, REG_HWRST, 0);
-+ udelay(10);
-+ mci_writel(smc_host, REG_HWRST, 1);
-+ udelay(300);
-+}
-+
-+static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
-+{
-+ struct sunxi_mmc_host *host = mmc_priv(mmc);
-+ struct mmc_command *cmd = mrq->cmd;
-+ struct mmc_data *data = mrq->data;
-+ unsigned long iflags;
-+ u32 imask = SDXC_INTERRUPT_ERROR_BIT;
-+ u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
-+ u32 byte_cnt = 0;
-+ int ret;
-+
-+ if (!mmc_gpio_get_cd(mmc) || host->ferror) {
-+ dev_dbg(mmc_dev(host->mmc), "no medium present\n");
-+ mrq->cmd->error = -ENOMEDIUM;
-+ mmc_request_done(mmc, mrq);
-+ return;
-+ }
-+
-+ if (data) {
-+ byte_cnt = data->blksz * data->blocks;
-+ mci_writel(host, REG_BLKSZ, data->blksz);
-+ mci_writel(host, REG_BCNTR, byte_cnt);
-+ ret = sunxi_mmc_prepare_dma(host, data);
-+ if (ret < 0) {
-+ dev_err(mmc_dev(host->mmc), "prepare DMA failed\n");
-+ cmd->error = ret;
-+ cmd->data->error = ret;
-+ mmc_request_done(host->mmc, mrq);
-+ return;
-+ }
-+ }
-+
-+ if (cmd->opcode == MMC_GO_IDLE_STATE) {
-+ cmd_val |= SDXC_SEND_INIT_SEQUENCE;
-+ imask |= SDXC_COMMAND_DONE;
-+ }
-+
-+ if (cmd->opcode == SD_SWITCH_VOLTAGE) {
-+ cmd_val |= SDXC_VOLTAGE_SWITCH;
-+ imask |= SDXC_VOLTAGE_CHANGE_DONE;
-+ host->voltage_switching = 1;
-+ sunxi_mmc_oclk_onoff(host, 1);
-+ }
-+
-+ if (cmd->flags & MMC_RSP_PRESENT) {
-+ cmd_val |= SDXC_RESPONSE_EXPIRE;
-+ if (cmd->flags & MMC_RSP_136)
-+ cmd_val |= SDXC_LONG_RESPONSE;
-+ if (cmd->flags & MMC_RSP_CRC)
-+ cmd_val |= SDXC_CHECK_RESPONSE_CRC;
-+
-+ if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
-+ cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
-+ if (cmd->data->flags & MMC_DATA_STREAM) {
-+ imask |= SDXC_AUTO_COMMAND_DONE;
-+ cmd_val |= SDXC_SEQUENCE_MODE | SDXC_SEND_AUTO_STOP;
-+ }
-+ if (cmd->data->stop) {
-+ imask |= SDXC_AUTO_COMMAND_DONE;
-+ cmd_val |= SDXC_SEND_AUTO_STOP;
-+ } else
-+ imask |= SDXC_DATA_OVER;
-+
-+ if (cmd->data->flags & MMC_DATA_WRITE)
-+ cmd_val |= SDXC_WRITE;
-+ else
-+ host->wait_dma = 1;
-+ } else
-+ imask |= SDXC_COMMAND_DONE;
-+ } else
-+ imask |= SDXC_COMMAND_DONE;
-+
-+ dev_dbg(mmc_dev(host->mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
-+ cmd_val & 0x3f, cmd_val, cmd->arg, imask,
-+ mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
-+
-+ spin_lock_irqsave(&host->lock, iflags);
-+ host->mrq = mrq;
-+ mci_writel(host, REG_IMASK, host->sdio_imask | imask);
-+ spin_unlock_irqrestore(&host->lock, iflags);
-+
-+ mci_writel(host, REG_CARG, cmd->arg);
-+ mci_writel(host, REG_CMDR, cmd_val);
-+}
-+
-+static const struct of_device_id sunxi_mmc_of_match[] = {
-+ { .compatible = "allwinner,sun4i-a10-mmc", },
-+ { .compatible = "allwinner,sun5i-a13-mmc", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
-+
-+static struct mmc_host_ops sunxi_mmc_ops = {
-+ .request = sunxi_mmc_request,
-+ .set_ios = sunxi_mmc_set_ios,
-+ .get_ro = mmc_gpio_get_ro,
-+ .get_cd = mmc_gpio_get_cd,
-+ .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
-+ .hw_reset = sunxi_mmc_hw_reset,
-+};
-+
-+static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
-+ struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ int ret;
-+
-+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc"))
-+ host->idma_des_size_bits = 13;
-+ else
-+ host->idma_des_size_bits = 16;
-+
-+ host->vmmc = devm_regulator_get_optional(&pdev->dev, "vmmc");
-+ if (IS_ERR(host->vmmc) && PTR_ERR(host->vmmc) == -EPROBE_DEFER)
-+ return -EPROBE_DEFER;
-+
-+ host->reg_base = devm_ioremap_resource(&pdev->dev,
-+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
-+ if (IS_ERR(host->reg_base))
-+ return PTR_ERR(host->reg_base);
-+
-+ host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
-+ if (IS_ERR(host->clk_ahb)) {
-+ dev_err(&pdev->dev, "Could not get ahb clock\n");
-+ return PTR_ERR(host->clk_ahb);
-+ }
-+
-+ host->clk_mod = devm_clk_get(&pdev->dev, "mod");
-+ if (IS_ERR(host->clk_mod)) {
-+ dev_err(&pdev->dev, "Could not get mod clock\n");
-+ return PTR_ERR(host->clk_mod);
-+ }
-+
-+ /* Make sure the controller is in a sane state before enabling irqs */
-+ ret = sunxi_mmc_init_host(host->mmc);
-+ if (ret)
-+ return ret;
-+
-+ host->irq = platform_get_irq(pdev, 0);
-+ ret = devm_request_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 0,
-+ "sunxi-mmc", host);
-+ if (ret == 0)
-+ disable_irq(host->irq);
-+
-+ /* And put it back in reset */
-+ sunxi_mmc_exit_host(host);
-+
-+ return ret;
-+}
-+
-+static int sunxi_mmc_probe(struct platform_device *pdev)
-+{
-+ struct sunxi_mmc_host *host;
-+ struct mmc_host *mmc;
-+ int ret;
-+
-+ mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
-+ if (!mmc) {
-+ dev_err(&pdev->dev, "mmc alloc host failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ ret = mmc_of_parse(mmc);
-+ if (ret)
-+ goto error_free_host;
-+
-+ host = mmc_priv(mmc);
-+ host->mmc = mmc;
-+ spin_lock_init(&host->lock);
-+ tasklet_init(&host->tasklet, sunxi_mmc_tasklet, (unsigned long)host);
-+
-+ ret = sunxi_mmc_resource_request(host, pdev);
-+ if (ret)
-+ goto error_free_host;
-+
-+ host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
-+ &host->sg_dma, GFP_KERNEL);
-+ if (!host->sg_cpu) {
-+ dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
-+ ret = -ENOMEM;
-+ goto error_free_host;
-+ }
-+
-+ mmc->ops = &sunxi_mmc_ops;
-+ mmc->max_blk_count = 8192;
-+ mmc->max_blk_size = 4096;
-+ mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
-+ mmc->max_seg_size = (1 << host->idma_des_size_bits);
-+ mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
-+ /* 400kHz ~ 50MHz */
-+ mmc->f_min = 400000;
-+ mmc->f_max = 50000000;
-+ /* available voltages */
-+ if (!IS_ERR(host->vmmc))
-+ mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vmmc);
-+ else
-+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-+
-+ mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-+ MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 |
-+ MMC_CAP_UHS_DDR50 | MMC_CAP_SDIO_IRQ | MMC_CAP_DRIVER_TYPE_A;
-+ mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP;
-+
-+ ret = mmc_add_host(mmc);
-+
-+ if (ret)
-+ goto error_free_dma;
-+
-+ dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
-+ platform_set_drvdata(pdev, mmc);
-+ return 0;
-+
-+error_free_dma:
-+ dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
-+error_free_host:
-+ mmc_free_host(mmc);
-+ return ret;
-+}
-+
-+static int sunxi_mmc_remove(struct platform_device *pdev)
-+{
-+ struct mmc_host *mmc = platform_get_drvdata(pdev);
-+ struct sunxi_mmc_host *host = mmc_priv(mmc);
-+
-+ mmc_remove_host(mmc);
-+ sunxi_mmc_exit_host(host);
-+ tasklet_disable(&host->tasklet);
-+ dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
-+ mmc_free_host(mmc);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver sunxi_mmc_driver = {
-+ .driver = {
-+ .name = "sunxi-mmc",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(sunxi_mmc_of_match),
-+ },
-+ .probe = sunxi_mmc_probe,
-+ .remove = sunxi_mmc_remove,
-+};
-+module_platform_driver(sunxi_mmc_driver);
-+
-+MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>");
-+MODULE_ALIAS("platform:sunxi-mmc");
-diff --git a/drivers/mmc/host/sunxi-mmc.h b/drivers/mmc/host/sunxi-mmc.h
-new file mode 100644
-index 0000000..cbd6d49
---- /dev/null
-+++ b/drivers/mmc/host/sunxi-mmc.h
-@@ -0,0 +1,239 @@
-+/*
-+ * Driver for sunxi SD/MMC host controllers
-+ * (C) Copyright 2014-2015 Reuuimlla Technology Co., Ltd.
-+ * (C) Copyright 2014-2015 Aaron Maoye <leafy.myeh@reuuimllatech.com>
-+ * (C) Copyright 2014-2015 O2S GmbH <www.o2s.ch>
-+ * (C) Copyright 2014-2015 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
-+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ */
-+
-+#ifndef __SUNXI_MCI_H__
-+#define __SUNXI_MCI_H__
-+
-+/* register offset define */
-+#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
-+#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
-+#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
-+#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
-+#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
-+#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
-+#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
-+#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
-+#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
-+#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
-+#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
-+#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
-+#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
-+#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
-+#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
-+#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
-+#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
-+#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
-+#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
-+#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
-+#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
-+#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
-+#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
-+#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
-+#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
-+#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
-+#define SDXC_REG_CHDA (0x90)
-+#define SDXC_REG_CBDA (0x94)
-+
-+#define mci_readl(host, reg) \
-+ readl((host)->reg_base + SDXC_##reg)
-+#define mci_writel(host, reg, value) \
-+ writel((value), (host)->reg_base + SDXC_##reg)
-+
-+/* global control register bits */
-+#define SDXC_SOFT_RESET BIT(0)
-+#define SDXC_FIFO_RESET BIT(1)
-+#define SDXC_DMA_RESET BIT(2)
-+#define SDXC_HARDWARE_RESET (SDXC_SOFT_RESET|SDXC_FIFO_RESET|SDXC_DMA_RESET)
-+#define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
-+#define SDXC_DMA_ENABLE_BIT BIT(5)
-+#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
-+#define SDXC_POSEDGE_LATCH_DATA BIT(9)
-+#define SDXC_DDR_MODE BIT(10)
-+#define SDXC_MEMORY_ACCESS_DONE BIT(29)
-+#define SDXC_ACCESS_DONE_DIRECT BIT(30)
-+#define SDXC_ACCESS_BY_AHB BIT(31)
-+#define SDXC_ACCESS_BY_DMA (0U << 31)
-+/* clock control bits */
-+#define SDXC_CARD_CLOCK_ON BIT(16)
-+#define SDXC_LOW_POWER_ON BIT(17)
-+/* bus width */
-+#define SDXC_WIDTH1 (0)
-+#define SDXC_WIDTH4 (1)
-+#define SDXC_WIDTH8 (2)
-+/* smc command bits */
-+#define SDXC_RESPONSE_EXPIRE BIT(6)
-+#define SDXC_LONG_RESPONSE BIT(7)
-+#define SDXC_CHECK_RESPONSE_CRC BIT(8)
-+#define SDXC_DATA_EXPIRE BIT(9)
-+#define SDXC_WRITE BIT(10)
-+#define SDXC_SEQUENCE_MODE BIT(11)
-+#define SDXC_SEND_AUTO_STOP BIT(12)
-+#define SDXC_WAIT_PRE_OVER BIT(13)
-+#define SDXC_STOP_ABORT_CMD BIT(14)
-+#define SDXC_SEND_INIT_SEQUENCE BIT(15)
-+#define SDXC_UPCLK_ONLY BIT(21)
-+#define SDXC_READ_CEATA_DEV BIT(22)
-+#define SDXC_CCS_EXPIRE BIT(23)
-+#define SDXC_ENABLE_BIT_BOOT BIT(24)
-+#define SDXC_ALT_BOOT_OPTIONS BIT(25)
-+#define SDXC_BOOT_ACK_EXPIRE BIT(26)
-+#define SDXC_BOOT_ABORT BIT(27)
-+#define SDXC_VOLTAGE_SWITCH BIT(28)
-+#define SDXC_USE_HOLD_REGISTER BIT(29)
-+#define SDXC_START BIT(31)
-+/* interrupt bits */
-+#define SDXC_RESPONSE_ERROR BIT(1)
-+#define SDXC_COMMAND_DONE BIT(2)
-+#define SDXC_DATA_OVER BIT(3)
-+#define SDXC_TX_DATA_REQUEST BIT(4)
-+#define SDXC_RX_DATA_REQUEST BIT(5)
-+#define SDXC_RESPONSE_CRC_ERROR BIT(6)
-+#define SDXC_DATA_CRC_ERROR BIT(7)
-+#define SDXC_RESPONSE_TIMEOUT BIT(8)
-+#define SDXC_DATA_TIMEOUT BIT(9)
-+#define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
-+#define SDXC_FIFO_RUN_ERROR BIT(11)
-+#define SDXC_HARD_WARE_LOCKED BIT(12)
-+#define SDXC_START_BIT_ERROR BIT(13)
-+#define SDXC_AUTO_COMMAND_DONE BIT(14)
-+#define SDXC_END_BIT_ERROR BIT(15)
-+#define SDXC_SDIO_INTERRUPT BIT(16)
-+#define SDXC_CARD_INSERT BIT(30)
-+#define SDXC_CARD_REMOVE BIT(31)
-+#define SDXC_INTERRUPT_ERROR_BIT (SDXC_RESPONSE_ERROR | SDXC_RESPONSE_CRC_ERROR | \
-+ SDXC_DATA_CRC_ERROR | SDXC_RESPONSE_TIMEOUT | \
-+ SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
-+ SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | \
-+ SDXC_END_BIT_ERROR) /* 0xbbc2 */
-+#define SDXC_INTERRUPT_DONE_BIT (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
-+ SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
-+/* status */
-+#define SDXC_RXWL_FLAG BIT(0)
-+#define SDXC_TXWL_FLAG BIT(1)
-+#define SDXC_FIFO_EMPTY BIT(2)
-+#define SDXC_FIFO_FULL BIT(3)
-+#define SDXC_CARD_PRESENT BIT(8)
-+#define SDXC_CARD_DATA_BUSY BIT(9)
-+#define SDXC_DATA_FSM_BUSY BIT(10)
-+#define SDXC_DMA_REQUEST BIT(31)
-+#define SDXC_FIFO_SIZE (16)
-+/* Function select */
-+#define SDXC_CEATA_ON (0xceaaU << 16)
-+#define SDXC_SEND_IRQ_RESPONSE BIT(0)
-+#define SDXC_SDIO_READ_WAIT BIT(1)
-+#define SDXC_ABORT_READ_DATA BIT(2)
-+#define SDXC_SEND_CCSD BIT(8)
-+#define SDXC_SEND_AUTO_STOPCCSD BIT(9)
-+#define SDXC_CEATA_DEV_INTERRUPT_ENABLE_BIT BIT(10)
-+/* IDMA controller bus mod bit field */
-+#define SDXC_IDMAC_SOFT_RESET BIT(0)
-+#define SDXC_IDMAC_FIX_BURST BIT(1)
-+#define SDXC_IDMAC_IDMA_ON BIT(7)
-+#define SDXC_IDMAC_REFETCH_DES BIT(31)
-+/* IDMA status bit field */
-+#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
-+#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
-+#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
-+#define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
-+#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
-+#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
-+#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
-+#define SDXC_IDMAC_HOST_ABORT_INTERRUPT_TX BIT(10)
-+#define SDXC_IDMAC_HOST_ABORT_INTERRUPT_RX BIT(10)
-+#define SDXC_IDMAC_IDLE (0U << 13)
-+#define SDXC_IDMAC_SUSPEND (1U << 13)
-+#define SDXC_IDMAC_DESC_READ (2U << 13)
-+#define SDXC_IDMAC_DESC_CHECK (3U << 13)
-+#define SDXC_IDMAC_READ_REQUEST_WAIT (4U << 13)
-+#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5U << 13)
-+#define SDXC_IDMAC_READ (6U << 13)
-+#define SDXC_IDMAC_WRITE (7U << 13)
-+#define SDXC_IDMAC_DESC_CLOSE (8U << 13)
-+
-+/*
-+* If the idma-des-size-bits of property is ie 13, bufsize bits are:
-+* Bits 0-12: buf1 size
-+* Bits 13-25: buf2 size
-+* Bits 26-31: not used
-+* Since we only ever set buf1 size, we can simply store it directly.
-+*/
-+#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
-+#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
-+#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
-+#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
-+#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
-+#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
-+#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
-+
-+struct sunxi_idma_des {
-+ u32 config;
-+ u32 buf_size;
-+ u32 buf_addr_ptr1;
-+ u32 buf_addr_ptr2;
-+};
-+
-+struct sunxi_mmc_host {
-+ struct mmc_host *mmc;
-+ struct regulator *vmmc;
-+
-+ /* IO mapping base */
-+ void __iomem *reg_base;
-+
-+ spinlock_t lock;
-+ struct tasklet_struct tasklet;
-+
-+ /* clock management */
-+ struct clk *clk_ahb;
-+ struct clk *clk_mod;
-+
-+ /* ios information */
-+ u32 clk_mod_rate;
-+ u32 bus_width;
-+ u32 idma_des_size_bits;
-+ u32 ddr;
-+ u32 voltage_switching;
-+
-+ /* irq */
-+ int irq;
-+ u32 int_sum;
-+ u32 sdio_imask;
-+
-+ /* flags */
-+ u32 power_on:1;
-+ u32 io_flag:1;
-+ u32 wait_dma:1;
-+
-+ dma_addr_t sg_dma;
-+ void *sg_cpu;
-+
-+ struct mmc_request *mrq;
-+ u32 ferror;
-+};
-+
-+#define MMC_CLK_400K 0
-+#define MMC_CLK_25M 1
-+#define MMC_CLK_50M 2
-+#define MMC_CLK_50MDDR 3
-+#define MMC_CLK_50MDDR_8BIT 4
-+#define MMC_CLK_100M 5
-+#define MMC_CLK_200M 6
-+#define MMC_CLK_MOD_NUM 7
-+
-+struct sunxi_mmc_clk_dly {
-+ u32 mode;
-+ u32 oclk_dly;
-+ u32 sclk_dly;
-+};
-+
-+#endif
---
-1.8.5.5
-
+++ /dev/null
-From 40889884d53094fe9987a45f9df99fdf1f311910 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 16 Feb 2014 10:47:51 +0100
-Subject: [PATCH] sunxi-mmc: Simplify clk delay setting
-
-clk_sunxi_mmc_phase_control() does its own locking, so there is no need to
-lock at the host. Without the locking having a separate sunxi_mmc_set_clk_dly()
-makes no sense, so simply call clk_sunxi_mmc_phase_control() directly.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/sunxi-mmc.c | 14 ++------------
- 1 file changed, 2 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index f33bc30..f4bfaf0 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -420,17 +420,6 @@ static void sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
- }
- }
-
--static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *smc_host,
-- u32 oclk_dly, u32 sclk_dly)
--{
-- unsigned long iflags;
-- struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
--
-- spin_lock_irqsave(&smc_host->lock, iflags);
-- clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
-- spin_unlock_irqrestore(&smc_host->lock, iflags);
--}
--
- struct sunxi_mmc_clk_dly mmc_clk_dly[MMC_CLK_MOD_NUM] = {
- { MMC_CLK_400K, 0, 7 },
- { MMC_CLK_25M, 0, 5 },
-@@ -450,6 +439,7 @@ static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
- u32 sclk_dly;
- u32 temp;
- struct sunxi_mmc_clk_dly *dly = NULL;
-+ struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
-
- newrate = clk_round_rate(smc_host->clk_mod, rate);
- if (smc_host->clk_mod_rate == newrate) {
-@@ -508,7 +498,7 @@ static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
- sclk_dly--;
- }
-
-- sunxi_mmc_set_clk_dly(smc_host, oclk_dly, sclk_dly);
-+ clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
- sunxi_mmc_oclk_onoff(smc_host, 1);
-
- /* oclk_onoff sets various irq status bits, clear these */
---
-1.8.5.5
-
+++ /dev/null
-From 0a6ec6db90c73b037428bf3a94a6281754007c25 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 16:55:54 +0100
-Subject: [PATCH] sunxi-mmc: Don't set mmc clk in low power mode
-
-The android driver uses an io-flag to descern whether a controller is
-hooked up to a sdcard slot, or to an onboard sdio dev. And for sdcard slots
-it sets the clock in a low-power mode.
-
-This is causing transmission errors when talking to the sdio-wifi on the
-cubietruck, and this may be the cause of problems with some type sdcards
-too. This patch fixes things by simply never setting the clk in low power
-mode.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/sunxi-mmc.c | 3 ---
- drivers/mmc/host/sunxi-mmc.h | 1 -
- 2 files changed, 4 deletions(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index f4bfaf0..c1a9d8a 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -400,9 +400,6 @@ static void sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
- if (oclk_en)
- rval |= SDXC_CARD_CLOCK_ON;
-
-- if (!host->io_flag)
-- rval |= SDXC_LOW_POWER_ON;
--
- mci_writel(host, REG_CLKCR, rval);
-
- rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
-diff --git a/drivers/mmc/host/sunxi-mmc.h b/drivers/mmc/host/sunxi-mmc.h
-index cbd6d49..a738850 100644
---- a/drivers/mmc/host/sunxi-mmc.h
-+++ b/drivers/mmc/host/sunxi-mmc.h
-@@ -211,7 +211,6 @@ struct sunxi_mmc_host {
-
- /* flags */
- u32 power_on:1;
-- u32 io_flag:1;
- u32 wait_dma:1;
-
- dma_addr_t sg_dma;
---
-1.8.5.5
-
+++ /dev/null
-From 3ec947a9717509e204c7f09609717951beb7ef04 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 17:11:58 +0100
-Subject: [PATCH] sunxi-mmc: Stop claiming UHS modes
-
-UHS requires a regulator to set the signaling voltage, as well as special
-code to handle the signal voltage switching. We've never added the code
-for this from the android driver to the upstream driver, so stop claiming
-support for this.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/sunxi-mmc.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index c1a9d8a..2eaed10 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -803,8 +803,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
- mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-
- mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-- MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 |
-- MMC_CAP_UHS_DDR50 | MMC_CAP_SDIO_IRQ | MMC_CAP_DRIVER_TYPE_A;
-+ MMC_CAP_SDIO_IRQ;
- mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP;
-
- ret = mmc_add_host(mmc);
---
-1.8.5.5
-
+++ /dev/null
-From dffb4d4d1fe3a6ba93102756152ec4518dbeac00 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 17:13:19 +0100
-Subject: [PATCH] sunxi-mmc: Or in caps, rather then overriding them
-
-Now that we use mmc_of_parse() there are already some caps set by mmc_of_parse,
-so or in our driver caps, rather then using an assignment. This fixes the
-card running only in 1 bit mode instead of 4 bit mode problem we've had
-since we switched to using mmc_of_parse().
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/sunxi-mmc.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index 2eaed10..d5e8ff9 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -802,9 +802,9 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
- else
- mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-
-- mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-+ mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
- MMC_CAP_SDIO_IRQ;
-- mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP;
-+ mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
-
- ret = mmc_add_host(mmc);
-
---
-1.8.5.5
-
+++ /dev/null
-From 73797537f3904fec60a647b3b209bf7add092ad5 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 21:59:08 +0100
-Subject: [PATCH] sunxi-mmc: Don't call mmc_of_parse until we're ready to
-
-mmc_of_parse registers an irq handler for the gpio pins for cd, this irq
-handler will reference host->ops, so don't call mmc_of_parse until we're
-done setting everything up.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/sunxi-mmc.c | 9 ++++-----
- 1 file changed, 4 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index d5e8ff9..cceae68 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -766,10 +766,6 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
- return -ENOMEM;
- }
-
-- ret = mmc_of_parse(mmc);
-- if (ret)
-- goto error_free_host;
--
- host = mmc_priv(mmc);
- host->mmc = mmc;
- spin_lock_init(&host->lock);
-@@ -806,8 +802,11 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
- MMC_CAP_SDIO_IRQ;
- mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
-
-- ret = mmc_add_host(mmc);
-+ ret = mmc_of_parse(mmc);
-+ if (ret)
-+ goto error_free_dma;
-
-+ ret = mmc_add_host(mmc);
- if (ret)
- goto error_free_dma;
-
---
-1.8.5.5
-
+++ /dev/null
-From 7bd0d82ef525e8949425fe271fb86eacf3822821 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 15 Dec 2013 19:44:01 +0100
-Subject: [PATCH] ARM: sunxi: clk: export clk_sunxi_mmc_phase_control
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- include/linux/clk/sunxi.h | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
- create mode 100644 include/linux/clk/sunxi.h
-
-diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
-new file mode 100644
-index 0000000..1ef5c89
---- /dev/null
-+++ b/include/linux/clk/sunxi.h
-@@ -0,0 +1,22 @@
-+/*
-+ * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __LINUX_CLK_SUNXI_H_
-+#define __LINUX_CLK_SUNXI_H_
-+
-+#include <linux/clk.h>
-+
-+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output);
-+
-+#endif
---
-1.8.5.5
-
+++ /dev/null
-From fcba369ee1af8657353bb1e37807aa492c462263 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Fri, 20 Sep 2013 20:29:17 -0300
-Subject: [PATCH] clk: sunxi: Implement MMC phase control
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 3283179..46a38b4 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -500,6 +500,41 @@ static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
-
-
- /**
-+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
-+ */
-+
-+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
-+{
-+ #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
-+ #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
-+
-+ struct clk_composite *composite = to_clk_composite(hw);
-+ struct clk_hw *rate_hw = composite->rate_hw;
-+ struct clk_factors *factors = to_clk_factors(rate_hw);
-+ unsigned long flags = 0;
-+ u32 reg;
-+
-+ if (factors->lock)
-+ spin_lock_irqsave(factors->lock, flags);
-+
-+ reg = readl(factors->reg);
-+
-+ /* set sample clock phase control */
-+ reg &= ~(0x7 << 20);
-+ reg |= ((sample & 0x7) << 20);
-+
-+ /* set output clock phase control */
-+ reg &= ~(0x7 << 8);
-+ reg |= ((output & 0x7) << 8);
-+
-+ writel(reg, factors->reg);
-+
-+ if (factors->lock)
-+ spin_unlock_irqrestore(factors->lock, flags);
-+}
-+
-+
-+/**
- * sunxi_factors_clk_setup() - Setup function for factor clocks
- */
-
---
-1.8.5.5
-
+++ /dev/null
-From 0483aa124d32bdcafc84623a31141a49e71cc72d Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 16 Feb 2014 08:54:20 +0100
-Subject: [PATCH] sunxi-mmc: fixup: revert "add host initialization for when
- the sdio irq is enabled"
-
-This is not necessary since when the host is not initialized at this point
-yet the irq line from the mmc controller is not enabled, so writing the
-host controller interrupt mask cannot cause interrupts at this point.
-
-More over doing this is wrong, as it leads to unbalanced calling of
-clk_prepare_enable and regulator_power_on.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/sunxi-mmc.c | 9 ---------
- 1 file changed, 9 deletions(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index 2dc446c..f33bc30 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -593,18 +593,9 @@ static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
- {
- struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
- unsigned long flags;
-- int ret;
- u32 imask;
-
- spin_lock_irqsave(&smc_host->lock, flags);
--
-- /* Make sure the controller is in a sane state before enabling irqs */
-- ret = sunxi_mmc_init_host(host->mmc);
-- if (ret) {
-- spin_unlock_irqrestore(&smc_host->lock, flags);
-- return ret;
-- }
--
- imask = mci_readl(smc_host, REG_IMASK);
- if (enable) {
- smc_host->sdio_imask = SDXC_SDIO_INTERRUPT;
---
-1.8.5.5
-
+++ /dev/null
-From 85f17a0d652853455ac633fc965cea8431038518 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 14 Dec 2013 17:20:13 +0100
-Subject: [PATCH] pinctrl-sunxi: Fix sun5i-a13 port F multiplexing
-
-The correct value for selecting the mmc0 function on port F pins is 2 not 4,
-as per the data-sheet:
-http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/pinctrl/pinctrl-sunxi-pins.h | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
-index 6fd8d4d..3d60669 100644
---- a/drivers/pinctrl/pinctrl-sunxi-pins.h
-+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
-@@ -1932,27 +1932,27 @@
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-- SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */
-+ SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-- SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */
-+ SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-- SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */
-+ SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-- SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */
-+ SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-- SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */
-+ SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-- SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */
-+ SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
- /* Hole */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
- SUNXI_FUNCTION(0x0, "gpio_in"),
---
-1.8.5.5
-
+++ /dev/null
-From 9d506cbf0e7b0e017d78f244e2b4c0fc71206c6c Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 15 Feb 2014 12:56:42 +0100
-Subject: [PATCH] pinctrl-sunxi: Fix masking when setting irq type
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/pinctrl/pinctrl-sunxi.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
-index cc9bd1b..917af0a 100644
---- a/drivers/pinctrl/pinctrl-sunxi.c
-+++ b/drivers/pinctrl/pinctrl-sunxi.c
-@@ -583,7 +583,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
- spin_lock_irqsave(&pctl->lock, flags);
-
- regval = readl(pctl->membase + reg);
-- regval &= ~IRQ_CFG_IRQ_MASK;
-+ regval &= ~(IRQ_CFG_IRQ_MASK << index);
- writel(regval | (mode << index), pctl->membase + reg);
-
- spin_unlock_irqrestore(&pctl->lock, flags);
---
-1.8.5.5
-
+++ /dev/null
-From a5f3d2672d5b9efe93be0bf66d69156bf806220b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 22:04:20 +0100
-Subject: [PATCH] pinctrl-sunxi: Fix interrupt register offset calculation
-
-This fixing setting the interrupt type for eints >= 8.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/pinctrl/pinctrl-sunxi.h | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
-index 01c494f..552b0e9 100644
---- a/drivers/pinctrl/pinctrl-sunxi.h
-+++ b/drivers/pinctrl/pinctrl-sunxi.h
-@@ -511,7 +511,7 @@ static inline u32 sunxi_pull_offset(u16 pin)
-
- static inline u32 sunxi_irq_cfg_reg(u16 irq)
- {
-- u8 reg = irq / IRQ_CFG_IRQ_PER_REG;
-+ u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
- return reg + IRQ_CFG_REG;
- }
-
-@@ -523,7 +523,7 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq)
-
- static inline u32 sunxi_irq_ctrl_reg(u16 irq)
- {
-- u8 reg = irq / IRQ_CTRL_IRQ_PER_REG;
-+ u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
- return reg + IRQ_CTRL_REG;
- }
-
-@@ -535,7 +535,7 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq)
-
- static inline u32 sunxi_irq_status_reg(u16 irq)
- {
-- u8 reg = irq / IRQ_STATUS_IRQ_PER_REG;
-+ u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
- return reg + IRQ_STATUS_REG;
- }
-
---
-1.8.5.5
-
+++ /dev/null
-From 6c6bc98f6a2b1f91071564efdb77c90307610018 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <david.lanzendoerfer@o2s.ch>
-Date: Sat, 15 Feb 2014 14:02:51 +0100
-Subject: [PATCH] ARM: dts: sun4i: Add support for mmc
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-a1000.dts | 8 +++++
- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 8 +++++
- arch/arm/boot/dts/sun4i-a10.dtsi | 54 ++++++++++++++++++++++++++++++
- 3 files changed, 70 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-index d6ec839..4b2a694 100644
---- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-@@ -35,6 +35,14 @@
- };
- };
-
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- status = "okay";
- };
-diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-index 6df237d8..ef85b8e 100644
---- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-@@ -34,6 +34,14 @@
- };
- };
-
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 454077a..a8e0df3 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -338,6 +338,50 @@
- #size-cells = <0>;
- };
-
-+ mmc0: mmc@01c0f000 {
-+ compatible = "allwinner,sun4i-a10-mmc";
-+ reg = <0x01c0f000 0x1000>;
-+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <32>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ cd-inverted;
-+ };
-+
-+ mmc1: mmc@01c10000 {
-+ compatible = "allwinner,sun4i-a10-mmc";
-+ reg = <0x01c10000 0x1000>;
-+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <33>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ cd-inverted;
-+ };
-+
-+ mmc2: mmc@01c11000 {
-+ compatible = "allwinner,sun4i-a10-mmc";
-+ reg = <0x01c11000 0x1000>;
-+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <34>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ cd-inverted;
-+ };
-+
-+ mmc3: mmc@01c12000 {
-+ compatible = "allwinner,sun4i-a10-mmc";
-+ reg = <0x01c12000 0x1000>;
-+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <35>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ cd-inverted;
-+ };
-+
- ahci: sata@01c18000 {
- compatible = "allwinner,sun4i-a10-ahci";
- reg = <0x01c18000 0x1000>;
-@@ -416,6 +456,20 @@
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-+
-+ mmc0_pins_a: mmc0@0 {
-+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
-+ allwinner,function = "mmc0";
-+ allwinner,drive = <2>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
-+ allwinner,pins = "PH1";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
- };
-
- timer@01c20c00 {
---
-1.8.5.5
-
+++ /dev/null
-From 5bfbb46a8685de4c67f084aea983fc9a50c882ad Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <david.lanzendoerfer@o2s.ch>
-Date: Sat, 15 Feb 2014 14:02:29 +0100
-Subject: [PATCH] ARM: dts: sun5i: Add support for mmc
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 30 ++++++++++++++++
- arch/arm/boot/dts/sun5i-a10s.dtsi | 44 ++++++++++++++++++++++++
- arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 15 ++++++++
- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 15 ++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 37 ++++++++++++++++++++
- 5 files changed, 141 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-index 3c9f8b3..5c7b454 100644
---- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-@@ -34,7 +34,37 @@
- };
- };
-
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_olinuxino_micro>;
-+ cd-gpios = <&pio 6 1 0>; /* PG1 */
-+ status = "okay";
-+ };
-+
-+ mmc1: mmc@01c10000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc1_pins_a>;
-+ pinctrl-1 = <&mmc1_cd_pin_olinuxino_micro>;
-+ cd-gpios = <&pio 6 13 0>; /* PG13 */
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
-+ mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 {
-+ allwinner,pins = "PG1";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
-+
-+ mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 {
-+ allwinner,pins = "PG13";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
-+
- led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PE3";
- allwinner,function = "gpio_out";
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 3a9b33d..3a7039e 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -299,6 +299,36 @@
- #size-cells = <0>;
- };
-
-+ mmc0: mmc@01c0f000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c0f000 0x1000>;
-+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <32>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc1: mmc@01c10000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c10000 0x1000>;
-+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <33>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc2: mmc@01c11000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c11000 0x1000>;
-+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <34>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
-@@ -369,6 +399,20 @@
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-+
-+ mmc0_pins_a: mmc0@0 {
-+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
-+ allwinner,function = "mmc0";
-+ allwinner,drive = <3>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ mmc1_pins_a: mmc1@0 {
-+ allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
-+ allwinner,function = "mmc1";
-+ allwinner,drive = <3>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- timer@01c20c00 {
-diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
-index fe2ce0a..2f08bb2 100644
---- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
-@@ -20,7 +20,22 @@
- compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
-
- soc@01c00000 {
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_olinuxinom>;
-+ cd-gpios = <&pio 6 0 0>; /* PG0 */
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
-+ mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
-+ allwinner,pins = "PG0";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
-+
- led_pins_olinuxinom: led_pins@0 {
- allwinner,pins = "PG9";
- allwinner,function = "gpio_out";
-diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-index a4ba5ff..a7280f5 100644
---- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-@@ -19,7 +19,22 @@
- compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
-
- soc@01c00000 {
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_olinuxino>;
-+ cd-gpios = <&pio 6 0 0>; /* PG0 */
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
-+ mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
-+ allwinner,pins = "PG0";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
-+
- led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PG9";
- allwinner,function = "gpio_out";
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 9612c52..63a35b8 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -281,6 +281,36 @@
- #size-cells = <1>;
- ranges;
-
-+ mmc0: mmc@01c0f000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c0f000 0x1000>;
-+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <32>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc1: mmc@01c10000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c10000 0x1000>;
-+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <33>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc2: mmc@01c11000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c11000 0x1000>;
-+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <34>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
-@@ -333,6 +363,13 @@
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-+
-+ mmc0_pins_a: mmc0@0 {
-+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
-+ allwinner,function = "mmc0";
-+ allwinner,drive = <3>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- timer@01c20c00 {
---
-1.8.5.5
-
+++ /dev/null
-From a3bddfdd19c49f0bde7aa2ff496773c575763d07 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <david.lanzendoerfer@o2s.ch>
-Date: Sat, 15 Feb 2014 14:02:01 +0100
-Subject: [PATCH] ARM: dts: sun7i: Add support for mmc
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 8 ++++
- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 8 ++++
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 ++++++++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 61 +++++++++++++++++++++++++
- 4 files changed, 100 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-index 07823c2..a8186f5 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-@@ -20,6 +20,14 @@
- compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-index 403bd2e..6cd7cca 100644
-diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-index d5c6799..d4e2355 100644
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -20,12 +20,35 @@
- compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
-+ mmc3: mmc@01c12000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc3_pins_a>;
-+ pinctrl-1 = <&mmc3_cd_pin_olinuxinom>;
-+ cd-gpios = <&pio 7 11 0>; /* PH11 */
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
- };
-
- pinctrl@01c20800 {
-+ mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
-+ allwinner,pins = "PH11";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
-+
- led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PH2";
- allwinner,function = "gpio_out";
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-index cb25d3c..66bb3ef 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-@@ -20,6 +20,14 @@
- compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 3385994..3bc6ac5 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -392,6 +392,46 @@
- #size-cells = <0>;
- };
-
-+ mmc0: mmc@01c0f000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c0f000 0x1000>;
-+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <0 32 4>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc1: mmc@01c10000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c10000 0x1000>;
-+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <0 33 4>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc2: mmc@01c11000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c11000 0x1000>;
-+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <0 34 4>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc3: mmc@01c12000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c12000 0x1000>;
-+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <0 35 4>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
- ahci: sata@01c18000 {
- compatible = "allwinner,sun4i-a10-ahci";
- reg = <0x01c18000 0x1000>;
-@@ -510,6 +550,27 @@
- allwinner,drive = <3>;
- allwinner,pull = <0>;
- };
-+
-+ mmc0_pins_a: mmc0@0 {
-+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
-+ allwinner,function = "mmc0";
-+ allwinner,drive = <3>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
-+ allwinner,pins = "PH1";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
-+
-+ mmc3_pins_a: mmc3@0 {
-+ allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
-+ allwinner,function = "mmc3";
-+ allwinner,drive = <3>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- timer@01c20c00 {
---
-1.8.5.5
-
+++ /dev/null
-From 1fa41bc5a6659e453ca19086f195b02a23dc3bbe Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 17:25:54 +0100
-Subject: [PATCH] ARM: sun5i: dt: Fixup mmc bindings
-
-1) Now that we're no longer overriding the caps set by mmc_of_parse we need
-to set cd-inverted for our card detection to work.
-
-2) Now that we no longer claim UHS modes support we will never use any DDR
-modes, so drive-strength 2 is enough for the mmc data pins.
-
-3) mmc1 on the A13 is not routed to any pins, and thus unusable, remove it
-from the dtsi
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++--
- arch/arm/boot/dts/sun5i-a13.dtsi | 14 +++-----------
- 2 files changed, 8 insertions(+), 13 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 3a7039e..15dfa9a 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -306,6 +306,7 @@
- clock-names = "ahb", "mod";
- interrupts = <32>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -316,6 +317,7 @@
- clock-names = "ahb", "mod";
- interrupts = <33>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -326,6 +328,7 @@
- clock-names = "ahb", "mod";
- interrupts = <34>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -403,14 +406,14 @@
- mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
- allwinner,function = "mmc0";
-- allwinner,drive = <3>;
-+ allwinner,drive = <2>;
- allwinner,pull = <0>;
- };
-
- mmc1_pins_a: mmc1@0 {
- allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
- allwinner,function = "mmc1";
-- allwinner,drive = <3>;
-+ allwinner,drive = <2>;
- allwinner,pull = <0>;
- };
- };
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 63a35b8..14a99d0 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -288,16 +288,7 @@
- clock-names = "ahb", "mod";
- interrupts = <32>;
- bus-width = <4>;
-- status = "disabled";
-- };
--
-- mmc1: mmc@01c10000 {
-- compatible = "allwinner,sun5i-a13-mmc";
-- reg = <0x01c10000 0x1000>;
-- clocks = <&ahb_gates 9>, <&mmc1_clk>;
-- clock-names = "ahb", "mod";
-- interrupts = <33>;
-- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -308,6 +299,7 @@
- clock-names = "ahb", "mod";
- interrupts = <34>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -367,7 +359,7 @@
- mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
- allwinner,function = "mmc0";
-- allwinner,drive = <3>;
-+ allwinner,drive = <2>;
- allwinner,pull = <0>;
- };
- };
---
-1.8.5.5
-
+++ /dev/null
-From e48e7ba7f97e883a24036df04cb474cf7cd22574 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 17:16:08 +0100
-Subject: [PATCH] ARM: sun7i: dt: Fixup mmc bindings
-
-1) Now that we're no longer overriding the caps set by mmc_of_parse we need
-to set cd-inverted for our card detection to work.
-
-2) Now that we no longer claim UHS modes support we will never use any DDR
-modes, so drive-strength 2 is enough for the mmc data pins.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 3bc6ac5..f4ecd79 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -399,6 +399,7 @@
- clock-names = "ahb", "mod";
- interrupts = <0 32 4>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -409,6 +410,7 @@
- clock-names = "ahb", "mod";
- interrupts = <0 33 4>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -419,6 +421,7 @@
- clock-names = "ahb", "mod";
- interrupts = <0 34 4>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -429,6 +432,7 @@
- clock-names = "ahb", "mod";
- interrupts = <0 35 4>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -554,7 +558,7 @@
- mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
- allwinner,function = "mmc0";
-- allwinner,drive = <3>;
-+ allwinner,drive = <2>;
- allwinner,pull = <0>;
- };
-
-@@ -568,7 +572,7 @@
- mmc3_pins_a: mmc3@0 {
- allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
- allwinner,function = "mmc3";
-- allwinner,drive = <3>;
-+ allwinner,drive = <2>;
- allwinner,pull = <0>;
- };
- };
---
-1.8.5.5
-
+++ /dev/null
-From 14cf22b1db1b6e6b7333e8a7245055966f5497e3 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Jan 2014 19:44:49 +0100
-Subject: [PATCH] input: Add new sun4i-lradc-keys driver
-
-Allwinnner sunxi SoCs have a low resolution adc (called lradc) which is
-specifically designed to have various (tablet) keys (ie home, back, search,
-etc). attached to it using a resistor network. This adds a driver for this.
-
-There are 2 channels, currently this driver only supports chan0 since there
-are no boards known to use chan1. The devicetree properties are already
-prefixed with chan0 as preparation for chan1 support in the future.
-
-This has been tested on an olimex a10s-olinuxino-micro, a13-olinuxino, and
-a20-olinuxino-micro.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../devicetree/bindings/input/sun4i-lradc-keys.txt | 22 ++
- drivers/input/keyboard/Kconfig | 10 +
- drivers/input/keyboard/Makefile | 1 +
- drivers/input/keyboard/sun4i-lradc-keys.c | 243 +++++++++++++++++++++
- 4 files changed, 276 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
- create mode 100644 drivers/input/keyboard/sun4i-lradc-keys.c
-
-diff --git a/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt b/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
-new file mode 100644
-index 0000000..7801264
---- /dev/null
-+++ b/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
-@@ -0,0 +1,22 @@
-+Allwinner sun4i low res adc attached tablet keys
-+------------------------------------------------
-+
-+Required properties:
-+ - compatible: "allwinner,sun4i-lradc-keys"
-+ - reg: mmio address range of the chip
-+ - interrupts: interrupt to which the chip is connected
-+ - allwinner,chan0-step: step in mV between keys must be 150 or 200
-+ - linux,chan0-keycodes: array of dt-bindings/input/input.h KEY_ codes
-+
-+Example:
-+
-+#include <dt-bindings/input/input.h>
-+
-+ lradc: lradc@01c22800 {
-+ compatible = "allwinner,sun4i-lradc-keys";
-+ reg = <0x01c22800 0x100>;
-+ interrupts = <31>;
-+ allwinner,chan0-step = <200>;
-+ linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN
-+ KEY_MENU KEY_ENTER KEY_HOME>;
-+ };
-diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
-index a673c9f..d8a51cd 100644
---- a/drivers/input/keyboard/Kconfig
-+++ b/drivers/input/keyboard/Kconfig
-@@ -544,6 +544,16 @@ config KEYBOARD_STMPE
- To compile this driver as a module, choose M here: the module will be
- called stmpe-keypad.
-
-+config KEYBOARD_SUN4I_LRADC
-+ tristate "Allwinner sun4i low res adc attached tablet keys support"
-+ depends on ARCH_SUNXI
-+ help
-+ This selects support for the Allwinner low res adc attached tablet
-+ keys found on Allwinner sunxi SoCs.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called sun4i-lradc-keys.
-+
- config KEYBOARD_DAVINCI
- tristate "TI DaVinci Key Scan"
- depends on ARCH_DAVINCI_DM365
-diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
-index a699b61..f3265bd 100644
---- a/drivers/input/keyboard/Makefile
-+++ b/drivers/input/keyboard/Makefile
-@@ -50,6 +50,7 @@ obj-$(CONFIG_KEYBOARD_SH_KEYSC) += sh_keysc.o
- obj-$(CONFIG_KEYBOARD_SPEAR) += spear-keyboard.o
- obj-$(CONFIG_KEYBOARD_STMPE) += stmpe-keypad.o
- obj-$(CONFIG_KEYBOARD_STOWAWAY) += stowaway.o
-+obj-$(CONFIG_KEYBOARD_SUN4I_LRADC) += sun4i-lradc-keys.o
- obj-$(CONFIG_KEYBOARD_SUNKBD) += sunkbd.o
- obj-$(CONFIG_KEYBOARD_TC3589X) += tc3589x-keypad.o
- obj-$(CONFIG_KEYBOARD_TEGRA) += tegra-kbc.o
-diff --git a/drivers/input/keyboard/sun4i-lradc-keys.c b/drivers/input/keyboard/sun4i-lradc-keys.c
-new file mode 100644
-index 0000000..5c55e17
---- /dev/null
-+++ b/drivers/input/keyboard/sun4i-lradc-keys.c
-@@ -0,0 +1,243 @@
-+/*
-+ * Allwinner sun4i low res adc attached tablet keys driver
-+ *
-+ * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+/*
-+ * Allwinnner sunxi SoCs have a lradc which is specifically designed to have
-+ * various (tablet) keys (ie home, back, search, etc). attached to it using
-+ * a resistor network. This driver is for the keys on such boards.
-+ *
-+ * There are 2 channels, currently this driver only supports chan0 since there
-+ * are no boards known to use chan1. The devicetree properties are already
-+ * prefixed with chan0 as preparation for chan1 support in the future.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/input.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+
-+#define LRADC_CTRL 0x00
-+#define LRADC_INTC 0x04
-+#define LRADC_INTS 0x08
-+#define LRADC_DATA0 0x0c
-+#define LRADC_DATA1 0x10
-+
-+/* LRADC_CTRL bits */
-+#define FIRST_CONVERT_DLY(x) ((x) << 24) /* 8 bits */
-+#define CHAN_SELECT(x) ((x) << 22) /* 2 bits */
-+#define CONTINUE_TIME_SEL(x) ((x) << 16) /* 4 bits */
-+#define KEY_MODE_SEL(x) ((x) << 12) /* 2 bits */
-+#define LEVELA_B_CNT(x) ((x) << 8) /* 4 bits */
-+#define HOLD_EN(x) ((x) << 6)
-+#define LEVELB_VOL(x) ((x) << 4) /* 2 bits */
-+#define SAMPLE_RATE(x) ((x) << 2) /* 2 bits */
-+#define ENABLE(x) ((x) << 0)
-+
-+/* LRADC_INTC and LRADC_INTS bits */
-+#define CHAN1_KEYUP_IRQ BIT(12)
-+#define CHAN1_ALRDY_HOLD_IRQ BIT(11)
-+#define CHAN1_HOLD_IRQ BIT(10)
-+#define CHAN1_KEYDOWN_IRQ BIT(9)
-+#define CHAN1_DATA_IRQ BIT(8)
-+#define CHAN0_KEYUP_IRQ BIT(4)
-+#define CHAN0_ALRDY_HOLD_IRQ BIT(3)
-+#define CHAN0_HOLD_IRQ BIT(2)
-+#define CHAN0_KEYDOWN_IRQ BIT(1)
-+#define CHAN0_DATA_IRQ BIT(0)
-+
-+#define MAX_KEYS 13
-+
-+/* Lookup table to map the adc val to a keycode index for 150 mv step size */
-+static const u8 adc_val_to_key_index_step150[64] = {
-+ 0, 0, 0,
-+ 1, 1, 1, 1, 1,
-+ 2, 2, 2, 2, 2,
-+ 3, 3, 3, 3,
-+ 4, 4, 4, 4, 4,
-+ 5, 5, 5, 5, 5,
-+ 6, 6, 6, 6, 6,
-+ 7, 7, 7, 7,
-+ 8, 8, 8, 8, 8,
-+ 9, 9, 9, 9, 9,
-+ 10, 10, 10, 10,
-+ 11, 11, 11, 11,
-+ 12, 12, 12, 12, 12, 12, 12, 12, 12, 12
-+};
-+
-+/* Lookup table to map the adc val to a keycode index for 200 mv step size */
-+static const u8 adc_val_to_key_index_step200[64] = {
-+ 0, 0, 0, 0, 0, 0, 0, 0,
-+ 1, 1, 1, 1, 1, 1, 1,
-+ 2, 2, 2, 2, 2, 2, 2,
-+ 3, 3, 3, 3, 3, 3,
-+ 4, 4, 4, 4, 4, 4,
-+ 5, 5, 5, 5, 5, 5,
-+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
-+ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
-+};
-+
-+struct sun4i_lradc_data {
-+ struct device *dev;
-+ struct input_dev *input;
-+ void __iomem *base;
-+ u32 chan0_step;
-+ u32 chan0_keycode;
-+ u32 chan0_keycodes[MAX_KEYS];
-+};
-+
-+static irqreturn_t sun4i_lradc_irq(int irq, void *dev_id)
-+{
-+ struct sun4i_lradc_data *lradc = dev_id;
-+ u32 ints, val;
-+
-+ ints = readl(lradc->base + LRADC_INTS);
-+
-+ /*
-+ * lradc supports only one keypress at a time, release does not give
-+ * any info as to which key was released, so we cache the keycode.
-+ */
-+ if ((ints & CHAN0_KEYDOWN_IRQ) && lradc->chan0_keycode == 0) {
-+ val = readl(lradc->base + LRADC_DATA0);
-+ if (lradc->chan0_step == 150)
-+ val = adc_val_to_key_index_step150[val];
-+ else
-+ val = adc_val_to_key_index_step200[val];
-+
-+ lradc->chan0_keycode = lradc->chan0_keycodes[val];
-+ input_report_key(lradc->input, lradc->chan0_keycode, 1);
-+ }
-+
-+ if (ints & CHAN0_KEYUP_IRQ) {
-+ input_report_key(lradc->input, lradc->chan0_keycode, 0);
-+ lradc->chan0_keycode = 0;
-+ }
-+
-+ input_sync(lradc->input);
-+
-+ writel(ints, lradc->base + LRADC_INTS);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int sun4i_lradc_open(struct input_dev *dev)
-+{
-+ struct sun4i_lradc_data *lradc = input_get_drvdata(dev);
-+
-+ /*
-+ * Set sample time to 16 ms / 62.5 Hz. Wait 2 * 16 ms for key to
-+ * stabilize on press, wait (1 + 1) * 16 ms for key release
-+ */
-+ writel(FIRST_CONVERT_DLY(2) | LEVELA_B_CNT(1) | HOLD_EN(1) |
-+ SAMPLE_RATE(2) | ENABLE(1), lradc->base + LRADC_CTRL);
-+
-+ writel(CHAN0_KEYUP_IRQ | CHAN0_KEYDOWN_IRQ, lradc->base + LRADC_INTC);
-+
-+ return 0;
-+}
-+
-+static void sun4i_lradc_close(struct input_dev *dev)
-+{
-+ struct sun4i_lradc_data *lradc = input_get_drvdata(dev);
-+
-+ /* Disable lradc, leave other settings unchanged */
-+ writel(FIRST_CONVERT_DLY(2) | LEVELA_B_CNT(1) | HOLD_EN(1) |
-+ SAMPLE_RATE(2), lradc->base + LRADC_CTRL);
-+ writel(0, lradc->base + LRADC_INTC);
-+}
-+
-+static int sun4i_lradc_probe(struct platform_device *pdev)
-+{
-+ struct sun4i_lradc_data *lradc;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *np = dev->of_node;
-+ int i, ret;
-+
-+ lradc = devm_kzalloc(dev, sizeof(struct sun4i_lradc_data), GFP_KERNEL);
-+ if (!lradc)
-+ return -ENOMEM;
-+
-+ ret = of_property_read_u32(np, "allwinner,chan0-step",
-+ &lradc->chan0_step);
-+ if (ret || (lradc->chan0_step != 150 && lradc->chan0_step != 200)) {
-+ dev_err(dev, "Invalid allwinner,chan0-step dt-property\n");
-+ return -EINVAL;
-+ }
-+
-+ for (i = 0; i < MAX_KEYS; i++)
-+ of_property_read_u32_index(np, "linux,chan0-keycodes",
-+ i, &lradc->chan0_keycodes[i]);
-+
-+ lradc->dev = dev;
-+ lradc->input = devm_input_allocate_device(dev);
-+ if (!lradc->input)
-+ return -ENOMEM;
-+
-+ lradc->input->name = pdev->name;
-+ lradc->input->phys = "sun4i_lradc/input0";
-+ lradc->input->open = sun4i_lradc_open;
-+ lradc->input->close = sun4i_lradc_close;
-+ lradc->input->id.bustype = BUS_HOST;
-+ lradc->input->id.vendor = 0x0001;
-+ lradc->input->id.product = 0x0001;
-+ lradc->input->id.version = 0x0100;
-+ lradc->input->evbit[0] = BIT(EV_SYN) | BIT(EV_KEY);
-+ for (i = 0; i < MAX_KEYS; i++)
-+ set_bit(lradc->chan0_keycodes[i], lradc->input->keybit);
-+ input_set_drvdata(lradc->input, lradc);
-+
-+ lradc->base = devm_ioremap_resource(dev,
-+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
-+ if (IS_ERR(lradc->base))
-+ return PTR_ERR(lradc->base);
-+
-+ ret = devm_request_irq(dev, platform_get_irq(pdev, 0), sun4i_lradc_irq,
-+ 0, "sun4i-lradc-keys", lradc);
-+ if (ret)
-+ return ret;
-+
-+ ret = input_register_device(lradc->input);
-+ if (ret)
-+ return ret;
-+
-+ platform_set_drvdata(pdev, lradc);
-+ return 0;
-+}
-+
-+static const struct of_device_id sun4i_lradc_of_match[] = {
-+ { .compatible = "allwinner,sun4i-lradc-keys", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, sun4i_lradc_of_match);
-+
-+static struct platform_driver sun4i_lradc_driver = {
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = "sun4i-lradc-keys",
-+ .of_match_table = of_match_ptr(sun4i_lradc_of_match),
-+ },
-+ .probe = sun4i_lradc_probe,
-+};
-+
-+module_platform_driver(sun4i_lradc_driver);
-+
-+MODULE_DESCRIPTION("Allwinner sun4i low res adc attached tablet keys driver");
-+MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
-+MODULE_LICENSE("GPL");
---
-1.8.5.5
-
+++ /dev/null
-From 0b35a283be3dcd9495bb7c0e13ef2cd58a5d2afc Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Jan 2014 20:26:21 +0100
-Subject: [PATCH] ARM: dts: sun7i: Add lradc node
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 9 +++++++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++
- 2 files changed, 16 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-index d4e2355..aef289f 100644
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -14,6 +14,7 @@
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
- /include/ "sunxi-ahci-reg.dtsi"
-+#include <dt-bindings/input/input.h>
-
- / {
- model = "Olimex A20-Olinuxino Micro";
-@@ -57,6 +58,14 @@
- };
- };
-
-+ lradc: lradc@01c22800 {
-+ allwinner,chan0-step = <200>;
-+ linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN
-+ KEY_MENU KEY_SEARCH KEY_HOME
-+ KEY_ESC KEY_ENTER>;
-+ status = "okay";
-+ };
-+
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index fa2ef07..b58ce25 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -608,6 +608,13 @@
- interrupts = <0 24 1>;
- };
-
-+ lradc: lradc@01c22800 {
-+ compatible = "allwinner,sun4i-lradc-keys";
-+ reg = <0x01c22800 0x100>;
-+ interrupts = <0 31 4>;
-+ status = "disabled";
-+ };
-+
- sid: eeprom@01c23800 {
- compatible = "allwinner,sun7i-a20-sid";
- reg = <0x01c23800 0x200>;
---
-1.8.5.5
-
+++ /dev/null
-From 7d6d16c0c9b96695cd0f5e5845ac192209f0811d Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Jan 2014 19:51:36 +0100
-Subject: [PATCH] ARM: dts: sun4i: Add lradc node
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index ba05e6e..1a9ab7e 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -494,6 +494,13 @@
- interrupts = <24>;
- };
-
-+ lradc: lradc@01c22800 {
-+ compatible = "allwinner,sun4i-lradc-keys";
-+ reg = <0x01c22800 0x100>;
-+ interrupts = <31>;
-+ status = "disabled";
-+ };
-+
- sid: eeprom@01c23800 {
- compatible = "allwinner,sun4i-sid";
- reg = <0x01c23800 0x10>;
---
-1.8.5.5
-
+++ /dev/null
-From 23f834fe6efd9f97e9b336cc53d902e6a0158cc5 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Jan 2014 19:50:33 +0100
-Subject: [PATCH] ARM: dts: sun5i: Add lradc node
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 8 ++++++++
- arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++
- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 8 ++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++
- 4 files changed, 30 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-index 5c7b454..2cbca7b 100644
---- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-@@ -13,6 +13,7 @@
-
- /dts-v1/;
- /include/ "sun5i-a10s.dtsi"
-+#include <dt-bindings/input/input.h>
-
- / {
- model = "Olimex A10s-Olinuxino Micro";
-@@ -73,6 +74,13 @@
- };
- };
-
-+ lradc: lradc@01c22800 {
-+ allwinner,chan0-step = <200>;
-+ linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN
-+ KEY_MENU KEY_ENTER KEY_HOME>;
-+ status = "okay";
-+ };
-+
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 15dfa9a..95cb245 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -430,6 +430,13 @@
- reg = <0x01c20c90 0x10>;
- };
-
-+ lradc: lradc@01c22800 {
-+ compatible = "allwinner,sun4i-lradc-keys";
-+ reg = <0x01c22800 0x100>;
-+ interrupts = <31>;
-+ status = "disabled";
-+ };
-+
- sid: eeprom@01c23800 {
- compatible = "allwinner,sun4i-sid";
- reg = <0x01c23800 0x10>;
-diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-index a7280f5..ba32a41 100644
---- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-@@ -13,6 +13,7 @@
-
- /dts-v1/;
- /include/ "sun5i-a13.dtsi"
-+#include <dt-bindings/input/input.h>
-
- / {
- model = "Olimex A13-Olinuxino";
-@@ -43,6 +44,13 @@
- };
- };
-
-+ lradc: lradc@01c22800 {
-+ allwinner,chan0-step = <200>;
-+ linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN
-+ KEY_MENU KEY_ENTER KEY_HOME>;
-+ status = "okay";
-+ };
-+
- uart1: serial@01c28400 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>;
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 14a99d0..bae0f5f 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -376,6 +376,13 @@
- reg = <0x01c20c90 0x10>;
- };
-
-+ lradc: lradc@01c22800 {
-+ compatible = "allwinner,sun4i-lradc-keys";
-+ reg = <0x01c22800 0x100>;
-+ interrupts = <31>;
-+ status = "disabled";
-+ };
-+
- sid: eeprom@01c23800 {
- compatible = "allwinner,sun4i-sid";
- reg = <0x01c23800 0x10>;
---
-1.8.5.5
-
+++ /dev/null
-From 3c9740a117d40a74412775b5d3fe2b88a7635a0e Mon Sep 17 00:00:00 2001
-From: Peter Chen <peter.chen@freescale.com>
-Date: Tue, 5 Nov 2013 10:46:02 +0800
-Subject: [PATCH] usb: hcd: move controller wakeup setting initialization to
- individual driver
-
-Individual controller driver has different requirement for wakeup
-setting, so move it from core to itself. In order to align with
-current etting the default wakeup setting is enabled (except for
-chipidea host).
-
-Pass compile test with below commands:
- make O=outout/all allmodconfig
- make -j$CPU_NUM O=outout/all drivers/usb
-
-Signed-off-by: Peter Chen <peter.chen@freescale.com>
-Acked-by: Alan Stern <stern@rowland.harvard.edu>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/staging/dwc2/hcd.c | 2 ++
- drivers/staging/octeon-usb/octeon-hcd.c | 1 +
- drivers/staging/ozwpan/ozhcd.c | 2 ++
- drivers/usb/c67x00/c67x00-hcd.c | 2 ++
- drivers/usb/core/hcd-pci.c | 1 +
- drivers/usb/core/hcd.c | 6 ------
- drivers/usb/host/ehci-atmel.c | 1 +
- drivers/usb/host/ehci-exynos.c | 1 +
- drivers/usb/host/ehci-fsl.c | 1 +
- drivers/usb/host/ehci-grlib.c | 1 +
- drivers/usb/host/ehci-mv.c | 1 +
- drivers/usb/host/ehci-mxc.c | 1 +
- drivers/usb/host/ehci-octeon.c | 1 +
- drivers/usb/host/ehci-omap.c | 1 +
- drivers/usb/host/ehci-orion.c | 1 +
- drivers/usb/host/ehci-platform.c | 1 +
- drivers/usb/host/ehci-pmcmsp.c | 4 +++-
- drivers/usb/host/ehci-ppc-of.c | 1 +
- drivers/usb/host/ehci-ps3.c | 1 +
- drivers/usb/host/ehci-sead3.c | 1 +
- drivers/usb/host/ehci-sh.c | 1 +
- drivers/usb/host/ehci-spear.c | 1 +
- drivers/usb/host/ehci-tegra.c | 1 +
- drivers/usb/host/ehci-tilegx.c | 1 +
- drivers/usb/host/ehci-w90x900.c | 1 +
- drivers/usb/host/ehci-xilinx-of.c | 4 +++-
- drivers/usb/host/fhci-hcd.c | 2 ++
- drivers/usb/host/fotg210-hcd.c | 1 +
- drivers/usb/host/fusbh200-hcd.c | 1 +
- drivers/usb/host/hwa-hc.c | 1 +
- drivers/usb/host/imx21-hcd.c | 1 +
- drivers/usb/host/isp116x-hcd.c | 2 ++
- drivers/usb/host/isp1362-hcd.c | 2 ++
- drivers/usb/host/isp1760-hcd.c | 1 +
- drivers/usb/host/ohci-at91.c | 4 +++-
- drivers/usb/host/ohci-da8xx.c | 2 ++
- drivers/usb/host/ohci-exynos.c | 1 +
- drivers/usb/host/ohci-jz4740.c | 1 +
- drivers/usb/host/ohci-nxp.c | 4 +++-
- drivers/usb/host/ohci-octeon.c | 2 ++
- drivers/usb/host/ohci-omap.c | 1 +
- drivers/usb/host/ohci-omap3.c | 1 +
- drivers/usb/host/ohci-platform.c | 2 ++
- drivers/usb/host/ohci-ppc-of.c | 4 +++-
- drivers/usb/host/ohci-ps3.c | 1 +
- drivers/usb/host/ohci-pxa27x.c | 4 +++-
- drivers/usb/host/ohci-s3c2410.c | 1 +
- drivers/usb/host/ohci-sa1111.c | 4 +++-
- drivers/usb/host/ohci-sm501.c | 1 +
- drivers/usb/host/ohci-spear.c | 4 +++-
- drivers/usb/host/ohci-tilegx.c | 1 +
- drivers/usb/host/ohci-tmio.c | 1 +
- drivers/usb/host/oxu210hp-hcd.c | 1 +
- drivers/usb/host/r8a66597-hcd.c | 1 +
- drivers/usb/host/sl811-hcd.c | 2 ++
- drivers/usb/host/u132-hcd.c | 1 +
- drivers/usb/host/uhci-grlib.c | 1 +
- drivers/usb/host/uhci-platform.c | 1 +
- drivers/usb/host/whci/hcd.c | 1 +
- drivers/usb/host/xhci-plat.c | 1 +
- drivers/usb/musb/musb_host.c | 1 +
- drivers/usb/phy/phy-msm-usb.c | 1 +
- drivers/usb/phy/phy-mv-usb.c | 6 ++++--
- drivers/usb/renesas_usbhs/mod_host.c | 1 +
- 64 files changed, 92 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/staging/dwc2/hcd.c b/drivers/staging/dwc2/hcd.c
-index 3cfd2d5..078cd91 100644
---- a/drivers/staging/dwc2/hcd.c
-+++ b/drivers/staging/dwc2/hcd.c
-@@ -2921,6 +2921,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
- if (retval < 0)
- goto error3;
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- dwc2_hcd_dump_state(hsotg);
-
- dwc2_enable_global_interrupts(hsotg);
-diff --git a/drivers/staging/octeon-usb/octeon-hcd.c b/drivers/staging/octeon-usb/octeon-hcd.c
-index d118952..47e0a91 100644
---- a/drivers/staging/octeon-usb/octeon-hcd.c
-+++ b/drivers/staging/octeon-usb/octeon-hcd.c
-@@ -3498,6 +3498,7 @@ static int octeon_usb_driver_probe(struct device *dev)
- kfree(hcd);
- return -1;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- dev_dbg(dev, "Registered HCD for port %d on irq %d\n", usb_num, irq);
-
-diff --git a/drivers/staging/ozwpan/ozhcd.c b/drivers/staging/ozwpan/ozhcd.c
-index d9c43c3..efaf26f 100644
---- a/drivers/staging/ozwpan/ozhcd.c
-+++ b/drivers/staging/ozwpan/ozhcd.c
-@@ -2270,6 +2270,8 @@ static int oz_plat_probe(struct platform_device *dev)
- usb_put_hcd(hcd);
- return -1;
- }
-+ device_wakeup_enable(hcd->self.controller);
-+
- spin_lock_bh(&g_hcdlock);
- g_ozhcd = ozhcd;
- spin_unlock_bh(&g_hcdlock);
-diff --git a/drivers/usb/c67x00/c67x00-hcd.c b/drivers/usb/c67x00/c67x00-hcd.c
-index 75e47b8..20ec4ee 100644
---- a/drivers/usb/c67x00/c67x00-hcd.c
-+++ b/drivers/usb/c67x00/c67x00-hcd.c
-@@ -384,6 +384,8 @@ int c67x00_hcd_probe(struct c67x00_sie *sie)
- goto err2;
- }
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- spin_lock_irqsave(&sie->lock, flags);
- sie->private_data = c67x00;
- sie->irq = c67x00_hcd_irq;
-diff --git a/drivers/usb/core/hcd-pci.c b/drivers/usb/core/hcd-pci.c
-index dfe9d0f..d59d993 100644
---- a/drivers/usb/core/hcd-pci.c
-+++ b/drivers/usb/core/hcd-pci.c
-@@ -282,6 +282,7 @@ int usb_hcd_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
-
- if (retval != 0)
- goto unmap_registers;
-+ device_wakeup_enable(hcd->self.controller);
-
- if (pci_dev_run_wake(dev))
- pm_runtime_put_noidle(&dev->dev);
-diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
-index d3a9bcd..6297c9e 100644
---- a/drivers/usb/core/hcd.c
-+++ b/drivers/usb/core/hcd.c
-@@ -2712,12 +2712,6 @@ int usb_add_hcd(struct usb_hcd *hcd,
- if (hcd->uses_new_polling && HCD_POLL_RH(hcd))
- usb_hcd_poll_rh_status(hcd);
-
-- /*
-- * Host controllers don't generate their own wakeup requests;
-- * they only forward requests from the root hub. Therefore
-- * controllers should always be enabled for remote wakeup.
-- */
-- device_wakeup_enable(hcd->self.controller);
- return retval;
-
- error_create_attr_group:
-diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
-index 284f841..ec9f7b7 100644
---- a/drivers/usb/host/ehci-atmel.c
-+++ b/drivers/usb/host/ehci-atmel.c
-@@ -153,6 +153,7 @@ static int ehci_atmel_drv_probe(struct platform_device *pdev)
- retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (retval)
- goto fail_add_hcd;
-+ device_wakeup_enable(hcd->self.controller);
-
- return retval;
-
-diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
-index e97c198..d1d8c47 100644
---- a/drivers/usb/host/ehci-exynos.c
-+++ b/drivers/usb/host/ehci-exynos.c
-@@ -166,6 +166,7 @@ static int exynos_ehci_probe(struct platform_device *pdev)
- dev_err(&pdev->dev, "Failed to add USB HCD\n");
- goto fail_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- platform_set_drvdata(pdev, hcd);
-
-diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
-index 87a7426..854a68f 100644
---- a/drivers/usb/host/ehci-fsl.c
-+++ b/drivers/usb/host/ehci-fsl.c
-@@ -138,6 +138,7 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
- retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (retval != 0)
- goto err4;
-+ device_wakeup_enable(hcd->self.controller);
-
- #ifdef CONFIG_USB_OTG
- if (pdata->operating_mode == FSL_USB2_DR_OTG) {
-diff --git a/drivers/usb/host/ehci-grlib.c b/drivers/usb/host/ehci-grlib.c
-index b52a66c..054792c 100644
---- a/drivers/usb/host/ehci-grlib.c
-+++ b/drivers/usb/host/ehci-grlib.c
-@@ -140,6 +140,7 @@ static int ehci_hcd_grlib_probe(struct platform_device *op)
- if (rv)
- goto err_ioremap;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err_ioremap:
-diff --git a/drivers/usb/host/ehci-mv.c b/drivers/usb/host/ehci-mv.c
-index 6e8afca..bd61612 100644
---- a/drivers/usb/host/ehci-mv.c
-+++ b/drivers/usb/host/ehci-mv.c
-@@ -257,6 +257,7 @@ static int mv_ehci_probe(struct platform_device *pdev)
- "failed to add hcd with err %d\n", retval);
- goto err_set_vbus;
- }
-+ device_wakeup_enable(hcd->self.controller);
- }
-
- if (pdata->private_init)
-diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
-index 0528dc4..dbe5e4e 100644
---- a/drivers/usb/host/ehci-mxc.c
-+++ b/drivers/usb/host/ehci-mxc.c
-@@ -155,6 +155,7 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
- if (ret)
- goto err_add;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err_add:
-diff --git a/drivers/usb/host/ehci-octeon.c b/drivers/usb/host/ehci-octeon.c
-index 4c528b2..c4ad7ed 100644
---- a/drivers/usb/host/ehci-octeon.c
-+++ b/drivers/usb/host/ehci-octeon.c
-@@ -158,6 +158,7 @@ static int ehci_octeon_drv_probe(struct platform_device *pdev)
- dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
- goto err3;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- platform_set_drvdata(pdev, hcd);
-
-diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
-index 6fa82d6..a24720b 100644
---- a/drivers/usb/host/ehci-omap.c
-+++ b/drivers/usb/host/ehci-omap.c
-@@ -215,6 +215,7 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev)
- dev_err(dev, "failed to add hcd with err %d\n", ret);
- goto err_pm_runtime;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- /*
- * Bring PHYs out of reset for non PHY modes.
-diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
-index 2ba7673..aa8b92b 100644
---- a/drivers/usb/host/ehci-orion.c
-+++ b/drivers/usb/host/ehci-orion.c
-@@ -252,6 +252,7 @@ static int ehci_orion_drv_probe(struct platform_device *pdev)
- if (err)
- goto err4;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err4:
-diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
-index 7f30b71..01536cf 100644
---- a/drivers/usb/host/ehci-platform.c
-+++ b/drivers/usb/host/ehci-platform.c
-@@ -132,6 +132,7 @@ static int ehci_platform_probe(struct platform_device *dev)
- if (err)
- goto err_put_hcd;
-
-+ device_wakeup_enable(hcd->self.controller);
- platform_set_drvdata(dev, hcd);
-
- return err;
-diff --git a/drivers/usb/host/ehci-pmcmsp.c b/drivers/usb/host/ehci-pmcmsp.c
-index 893b707f..af3974a 100644
---- a/drivers/usb/host/ehci-pmcmsp.c
-+++ b/drivers/usb/host/ehci-pmcmsp.c
-@@ -210,8 +210,10 @@ int usb_hcd_msp_probe(const struct hc_driver *driver,
-
-
- retval = usb_add_hcd(hcd, res->start, IRQF_SHARED);
-- if (retval == 0)
-+ if (retval == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-+ }
-
- usb_remove_hcd(hcd);
- err3:
-diff --git a/drivers/usb/host/ehci-ppc-of.c b/drivers/usb/host/ehci-ppc-of.c
-index 875d2fc..b0965eb 100644
---- a/drivers/usb/host/ehci-ppc-of.c
-+++ b/drivers/usb/host/ehci-ppc-of.c
-@@ -169,6 +169,7 @@ static int ehci_hcd_ppc_of_probe(struct platform_device *op)
- if (rv)
- goto err_ioremap;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err_ioremap:
-diff --git a/drivers/usb/host/ehci-ps3.c b/drivers/usb/host/ehci-ps3.c
-index 8188542..7934ff9 100644
---- a/drivers/usb/host/ehci-ps3.c
-+++ b/drivers/usb/host/ehci-ps3.c
-@@ -189,6 +189,7 @@ static int ps3_ehci_probe(struct ps3_system_bus_device *dev)
- goto fail_add_hcd;
- }
-
-+ device_wakeup_enable(hcd->self.controller);
- return result;
-
- fail_add_hcd:
-diff --git a/drivers/usb/host/ehci-sead3.c b/drivers/usb/host/ehci-sead3.c
-index 8a73449..cf12676 100644
---- a/drivers/usb/host/ehci-sead3.c
-+++ b/drivers/usb/host/ehci-sead3.c
-@@ -126,6 +126,7 @@ static int ehci_hcd_sead3_drv_probe(struct platform_device *pdev)
- IRQF_SHARED);
- if (ret == 0) {
- platform_set_drvdata(pdev, hcd);
-+ device_wakeup_enable(hcd->self.controller);
- return ret;
- }
-
-diff --git a/drivers/usb/host/ehci-sh.c b/drivers/usb/host/ehci-sh.c
-index dc899eb..9b9b9f5 100644
---- a/drivers/usb/host/ehci-sh.c
-+++ b/drivers/usb/host/ehci-sh.c
-@@ -151,6 +151,7 @@ static int ehci_hcd_sh_probe(struct platform_device *pdev)
- dev_err(&pdev->dev, "Failed to add hcd");
- goto fail_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- priv->hcd = hcd;
- platform_set_drvdata(pdev, priv);
-diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
-index ee6f9ff..8bd915b 100644
---- a/drivers/usb/host/ehci-spear.c
-+++ b/drivers/usb/host/ehci-spear.c
-@@ -130,6 +130,7 @@ static int spear_ehci_hcd_drv_probe(struct platform_device *pdev)
- if (retval)
- goto err_stop_ehci;
-
-+ device_wakeup_enable(hcd->self.controller);
- return retval;
-
- err_stop_ehci:
-diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
-index b9fd039..a8f4471 100644
---- a/drivers/usb/host/ehci-tegra.c
-+++ b/drivers/usb/host/ehci-tegra.c
-@@ -455,6 +455,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
- dev_err(&pdev->dev, "Failed to add USB HCD\n");
- goto cleanup_otg_set_host;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return err;
-
-diff --git a/drivers/usb/host/ehci-tilegx.c b/drivers/usb/host/ehci-tilegx.c
-index 67026ff..f3713d3 100644
---- a/drivers/usb/host/ehci-tilegx.c
-+++ b/drivers/usb/host/ehci-tilegx.c
-@@ -170,6 +170,7 @@ static int ehci_hcd_tilegx_drv_probe(struct platform_device *pdev)
- ret = usb_add_hcd(hcd, pdata->irq, IRQF_SHARED);
- if (ret == 0) {
- platform_set_drvdata(pdev, hcd);
-+ device_wakeup_enable(hcd->self.controller);
- return ret;
- }
-
-diff --git a/drivers/usb/host/ehci-w90x900.c b/drivers/usb/host/ehci-w90x900.c
-index cdad843..12c1a56 100644
---- a/drivers/usb/host/ehci-w90x900.c
-+++ b/drivers/usb/host/ehci-w90x900.c
-@@ -94,6 +94,7 @@ static int usb_w90x900_probe(const struct hc_driver *driver,
- if (retval != 0)
- goto err4;
-
-+ device_wakeup_enable(hcd->self.controller);
- return retval;
- err4:
- iounmap(hcd->regs);
-diff --git a/drivers/usb/host/ehci-xilinx-of.c b/drivers/usb/host/ehci-xilinx-of.c
-index 95979f9..3cd2efa 100644
---- a/drivers/usb/host/ehci-xilinx-of.c
-+++ b/drivers/usb/host/ehci-xilinx-of.c
-@@ -191,8 +191,10 @@ static int ehci_hcd_xilinx_of_probe(struct platform_device *op)
- ehci->caps = hcd->regs + 0x100;
-
- rv = usb_add_hcd(hcd, irq, 0);
-- if (rv == 0)
-+ if (rv == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-+ }
-
- err_irq:
- usb_put_hcd(hcd);
-diff --git a/drivers/usb/host/fhci-hcd.c b/drivers/usb/host/fhci-hcd.c
-index 0551c0a..1cf68ea 100644
---- a/drivers/usb/host/fhci-hcd.c
-+++ b/drivers/usb/host/fhci-hcd.c
-@@ -754,6 +754,8 @@ static int of_fhci_probe(struct platform_device *ofdev)
- if (ret < 0)
- goto err_add_hcd;
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- fhci_dfs_create(fhci);
-
- return 0;
-diff --git a/drivers/usb/host/fotg210-hcd.c b/drivers/usb/host/fotg210-hcd.c
-index 97d6939..98a89d1 100644
---- a/drivers/usb/host/fotg210-hcd.c
-+++ b/drivers/usb/host/fotg210-hcd.c
-@@ -5889,6 +5889,7 @@ static int fotg210_hcd_probe(struct platform_device *pdev)
- dev_err(dev, "failed to add hcd with err %d\n", retval);
- goto fail_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return retval;
-
-diff --git a/drivers/usb/host/fusbh200-hcd.c b/drivers/usb/host/fusbh200-hcd.c
-index 9ea85b6..ba94990 100644
---- a/drivers/usb/host/fusbh200-hcd.c
-+++ b/drivers/usb/host/fusbh200-hcd.c
-@@ -5798,6 +5798,7 @@ static int fusbh200_hcd_probe(struct platform_device *pdev)
- dev_err(dev, "failed to add hcd with err %d\n", retval);
- goto fail_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return retval;
-
-diff --git a/drivers/usb/host/hwa-hc.c b/drivers/usb/host/hwa-hc.c
-index a4ec9e6..7fd3f9b 100644
---- a/drivers/usb/host/hwa-hc.c
-+++ b/drivers/usb/host/hwa-hc.c
-@@ -791,6 +791,7 @@ static int hwahc_probe(struct usb_interface *usb_iface,
- dev_err(dev, "Cannot add HCD: %d\n", result);
- goto error_add_hcd;
- }
-+ device_wakeup_enable(usb_hcd->self.controller);
- result = wusbhc_b_create(&hwahc->wusbhc);
- if (result < 0) {
- dev_err(dev, "Cannot setup phase B of WUSBHC: %d\n", result);
-diff --git a/drivers/usb/host/imx21-hcd.c b/drivers/usb/host/imx21-hcd.c
-index 0122624..207bad9 100644
---- a/drivers/usb/host/imx21-hcd.c
-+++ b/drivers/usb/host/imx21-hcd.c
-@@ -1910,6 +1910,7 @@ static int imx21_probe(struct platform_device *pdev)
- dev_err(imx21->dev, "usb_add_hcd() returned %d\n", ret);
- goto failed_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return 0;
-
-diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c
-index 7722ec6..2740f65 100644
---- a/drivers/usb/host/isp116x-hcd.c
-+++ b/drivers/usb/host/isp116x-hcd.c
-@@ -1645,6 +1645,8 @@ static int isp116x_probe(struct platform_device *pdev)
- if (ret)
- goto err6;
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- ret = create_debug_file(isp116x);
- if (ret) {
- ERR("Couldn't create debugfs entry\n");
-diff --git a/drivers/usb/host/isp1362-hcd.c b/drivers/usb/host/isp1362-hcd.c
-index cd94b10..34645ae 100644
---- a/drivers/usb/host/isp1362-hcd.c
-+++ b/drivers/usb/host/isp1362-hcd.c
-@@ -2746,6 +2746,8 @@ static int isp1362_probe(struct platform_device *pdev)
- retval = usb_add_hcd(hcd, irq, irq_flags | IRQF_SHARED);
- if (retval != 0)
- goto err6;
-+ device_wakeup_enable(hcd->self.controller);
-+
- pr_info("%s, irq %d\n", hcd->product_desc, irq);
-
- create_debug_file(isp1362_hcd);
-diff --git a/drivers/usb/host/isp1760-hcd.c b/drivers/usb/host/isp1760-hcd.c
-index 2facee5..51a0ae9 100644
---- a/drivers/usb/host/isp1760-hcd.c
-+++ b/drivers/usb/host/isp1760-hcd.c
-@@ -2250,6 +2250,7 @@ struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
- ret = usb_add_hcd(hcd, irq, irqflags);
- if (ret)
- goto err_unmap;
-+ device_wakeup_enable(hcd->self.controller);
-
- return hcd;
-
-diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
-index cc9462f..29d2093 100644
-diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c
-index 71dbd85..f0fe0d2 100644
---- a/drivers/usb/host/ohci-da8xx.c
-+++ b/drivers/usb/host/ohci-da8xx.c
-@@ -348,6 +348,8 @@ static int usb_hcd_da8xx_probe(const struct hc_driver *driver,
- if (error)
- goto err4;
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- if (hub->ocic_notify) {
- error = hub->ocic_notify(ohci_da8xx_ocic_handler);
- if (!error)
-diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
-index 9897d70..68588d8 100644
---- a/drivers/usb/host/ohci-exynos.c
-+++ b/drivers/usb/host/ohci-exynos.c
-@@ -146,6 +146,7 @@ static int exynos_ohci_probe(struct platform_device *pdev)
- dev_err(&pdev->dev, "Failed to add USB HCD\n");
- goto fail_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- fail_add_hcd:
-diff --git a/drivers/usb/host/ohci-jz4740.c b/drivers/usb/host/ohci-jz4740.c
-index d4ef539..efe31f3 100644
---- a/drivers/usb/host/ohci-jz4740.c
-+++ b/drivers/usb/host/ohci-jz4740.c
-@@ -217,6 +217,7 @@ static int jz4740_ohci_probe(struct platform_device *pdev)
- dev_err(&pdev->dev, "Failed to add hcd: %d\n", ret);
- goto err_disable;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return 0;
-
-diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c
-index e99db8a..719f28e 100644
---- a/drivers/usb/host/ohci-nxp.c
-+++ b/drivers/usb/host/ohci-nxp.c
-@@ -274,8 +274,10 @@ static int ohci_hcd_nxp_probe(struct platform_device *pdev)
-
- dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq);
- ret = usb_add_hcd(hcd, irq, 0);
-- if (ret == 0)
-+ if (ret == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return ret;
-+ }
-
- ohci_nxp_stop_hc();
- fail_resource:
-diff --git a/drivers/usb/host/ohci-octeon.c b/drivers/usb/host/ohci-octeon.c
-index 6c16dce..49b220d 100644
---- a/drivers/usb/host/ohci-octeon.c
-+++ b/drivers/usb/host/ohci-octeon.c
-@@ -171,6 +171,8 @@ static int ohci_octeon_drv_probe(struct platform_device *pdev)
- goto err3;
- }
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- platform_set_drvdata(pdev, hcd);
-
- return 0;
-diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
-index f253214..a44a4fe 100644
---- a/drivers/usb/host/ohci-omap.c
-+++ b/drivers/usb/host/ohci-omap.c
-@@ -367,6 +367,7 @@ static int usb_hcd_omap_probe (const struct hc_driver *driver,
- if (retval)
- goto err3;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
- err3:
- iounmap(hcd->regs);
-diff --git a/drivers/usb/host/ohci-omap3.c b/drivers/usb/host/ohci-omap3.c
-index 2145741..ec15aeb 100644
---- a/drivers/usb/host/ohci-omap3.c
-+++ b/drivers/usb/host/ohci-omap3.c
-@@ -130,6 +130,7 @@ static int ohci_hcd_omap3_probe(struct platform_device *pdev)
- dev_dbg(dev, "failed to add hcd with err %d\n", ret);
- goto err_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return 0;
-
-diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
-index f351ff5..68f674c 100644
---- a/drivers/usb/host/ohci-platform.c
-+++ b/drivers/usb/host/ohci-platform.c
-@@ -108,6 +108,8 @@ static int ohci_platform_probe(struct platform_device *dev)
- if (err)
- goto err_put_hcd;
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- platform_set_drvdata(dev, hcd);
-
- return err;
-diff --git a/drivers/usb/host/ohci-ppc-of.c b/drivers/usb/host/ohci-ppc-of.c
-index 81f3eba..83e33d4 100644
---- a/drivers/usb/host/ohci-ppc-of.c
-+++ b/drivers/usb/host/ohci-ppc-of.c
-@@ -147,8 +147,10 @@ static int ohci_hcd_ppc_of_probe(struct platform_device *op)
- ohci_hcd_init(ohci);
-
- rv = usb_add_hcd(hcd, irq, 0);
-- if (rv == 0)
-+ if (rv == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-+ }
-
- /* by now, 440epx is known to show usb_23 erratum */
- np = of_find_compatible_node(NULL, NULL, "ibm,usb-ehci-440epx");
-diff --git a/drivers/usb/host/ohci-ps3.c b/drivers/usb/host/ohci-ps3.c
-index 7d35cd9..71d8bc4 100644
---- a/drivers/usb/host/ohci-ps3.c
-+++ b/drivers/usb/host/ohci-ps3.c
-@@ -173,6 +173,7 @@ static int ps3_ohci_probe(struct ps3_system_bus_device *dev)
- goto fail_add_hcd;
- }
-
-+ device_wakeup_enable(hcd->self.controller);
- return result;
-
- fail_add_hcd:
-diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
-index e89ac4d..5343ecf 100644
---- a/drivers/usb/host/ohci-pxa27x.c
-+++ b/drivers/usb/host/ohci-pxa27x.c
-@@ -442,8 +442,10 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
- ohci->num_ports = 3;
-
- retval = usb_add_hcd(hcd, irq, 0);
-- if (retval == 0)
-+ if (retval == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return retval;
-+ }
-
- pxa27x_stop_hc(pxa_ohci, &pdev->dev);
- err3:
-diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c
-index 83cd1dc..ff7c8f1 100644
---- a/drivers/usb/host/ohci-s3c2410.c
-+++ b/drivers/usb/host/ohci-s3c2410.c
-@@ -395,6 +395,7 @@ static int usb_hcd_s3c2410_probe(const struct hc_driver *driver,
- if (retval != 0)
- goto err_ioremap;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err_ioremap:
-diff --git a/drivers/usb/host/ohci-sa1111.c b/drivers/usb/host/ohci-sa1111.c
-index aa9e127..2ac266d 100644
---- a/drivers/usb/host/ohci-sa1111.c
-+++ b/drivers/usb/host/ohci-sa1111.c
-@@ -211,8 +211,10 @@ static int ohci_hcd_sa1111_probe(struct sa1111_dev *dev)
- goto err2;
-
- ret = usb_add_hcd(hcd, dev->irq[1], 0);
-- if (ret == 0)
-+ if (ret == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return ret;
-+ }
-
- sa1111_stop_hc(dev);
- err2:
-diff --git a/drivers/usb/host/ohci-sm501.c b/drivers/usb/host/ohci-sm501.c
-index 2a5de5f..4e81c80 100644
---- a/drivers/usb/host/ohci-sm501.c
-+++ b/drivers/usb/host/ohci-sm501.c
-@@ -168,6 +168,7 @@ static int ohci_hcd_sm501_drv_probe(struct platform_device *pdev)
- retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (retval)
- goto err5;
-+ device_wakeup_enable(hcd->self.controller);
-
- /* enable power and unmask interrupts */
-
-diff --git a/drivers/usb/host/ohci-spear.c b/drivers/usb/host/ohci-spear.c
-index e418c19..4cb98ab 100644
---- a/drivers/usb/host/ohci-spear.c
-+++ b/drivers/usb/host/ohci-spear.c
-@@ -103,8 +103,10 @@ static int spear_ohci_hcd_drv_probe(struct platform_device *pdev)
- ohci = hcd_to_ohci(hcd);
-
- retval = usb_add_hcd(hcd, platform_get_irq(pdev, 0), 0);
-- if (retval == 0)
-+ if (retval == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return retval;
-+ }
-
- clk_disable_unprepare(sohci_p->clk);
- err_put_hcd:
-diff --git a/drivers/usb/host/ohci-tilegx.c b/drivers/usb/host/ohci-tilegx.c
-index 22540ab..0b183e0 100644
---- a/drivers/usb/host/ohci-tilegx.c
-+++ b/drivers/usb/host/ohci-tilegx.c
-@@ -159,6 +159,7 @@ static int ohci_hcd_tilegx_drv_probe(struct platform_device *pdev)
- ret = usb_add_hcd(hcd, pdata->irq, IRQF_SHARED);
- if (ret == 0) {
- platform_set_drvdata(pdev, hcd);
-+ device_wakeup_enable(hcd->self.controller);
- return ret;
- }
-
-diff --git a/drivers/usb/host/ohci-tmio.c b/drivers/usb/host/ohci-tmio.c
-index ecb09a5..9c44093 100644
---- a/drivers/usb/host/ohci-tmio.c
-+++ b/drivers/usb/host/ohci-tmio.c
-@@ -250,6 +250,7 @@ static int ohci_hcd_tmio_drv_probe(struct platform_device *dev)
- if (ret)
- goto err_add_hcd;
-
-+ device_wakeup_enable(hcd->self.controller);
- if (ret == 0)
- return ret;
-
-diff --git a/drivers/usb/host/oxu210hp-hcd.c b/drivers/usb/host/oxu210hp-hcd.c
-index 4a05148..778eeaf 100644
---- a/drivers/usb/host/oxu210hp-hcd.c
-+++ b/drivers/usb/host/oxu210hp-hcd.c
-@@ -3751,6 +3751,7 @@ static struct usb_hcd *oxu_create(struct platform_device *pdev,
- if (ret < 0)
- return ERR_PTR(ret);
-
-+ device_wakeup_enable(hcd->self.controller);
- return hcd;
- }
-
-diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
-index 3bddfcf..47b1322 100644
---- a/drivers/usb/host/r8a66597-hcd.c
-+++ b/drivers/usb/host/r8a66597-hcd.c
-@@ -2514,6 +2514,7 @@ static int r8a66597_probe(struct platform_device *pdev)
- dev_err(&pdev->dev, "Failed to add hcd\n");
- goto clean_up3;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return 0;
-
-diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c
-index 79620c3..0115e7f 100644
---- a/drivers/usb/host/sl811-hcd.c
-+++ b/drivers/usb/host/sl811-hcd.c
-@@ -1732,6 +1732,8 @@ static void remove_debug_file(struct sl811 *sl811)
- if (retval != 0)
- goto err6;
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- create_debug_file(sl811);
- return retval;
-
-diff --git a/drivers/usb/host/u132-hcd.c b/drivers/usb/host/u132-hcd.c
-index 46236e9..c067175 100644
---- a/drivers/usb/host/u132-hcd.c
-+++ b/drivers/usb/host/u132-hcd.c
-@@ -3133,6 +3133,7 @@ static int u132_probe(struct platform_device *pdev)
- u132_u132_put_kref(u132);
- return retval;
- } else {
-+ device_wakeup_enable(hcd->self.controller);
- u132_monitor_queue_work(u132, 100);
- return 0;
- }
-diff --git a/drivers/usb/host/uhci-grlib.c b/drivers/usb/host/uhci-grlib.c
-index 53c23ff..ab25dc3 100644
---- a/drivers/usb/host/uhci-grlib.c
-+++ b/drivers/usb/host/uhci-grlib.c
-@@ -141,6 +141,7 @@ static int uhci_hcd_grlib_probe(struct platform_device *op)
- if (rv)
- goto err_uhci;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err_uhci:
-diff --git a/drivers/usb/host/uhci-platform.c b/drivers/usb/host/uhci-platform.c
-index 3003fef..44e6c9d 100644
---- a/drivers/usb/host/uhci-platform.c
-+++ b/drivers/usb/host/uhci-platform.c
-@@ -108,6 +108,7 @@ static int uhci_hcd_platform_probe(struct platform_device *pdev)
- if (ret)
- goto err_uhci;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err_uhci:
-diff --git a/drivers/usb/host/whci/hcd.c b/drivers/usb/host/whci/hcd.c
-index 1b0888f..d7b363a 100644
---- a/drivers/usb/host/whci/hcd.c
-+++ b/drivers/usb/host/whci/hcd.c
-@@ -293,6 +293,7 @@ static int whc_probe(struct umc_dev *umc)
- dev_err(dev, "cannot add HCD: %d\n", ret);
- goto error_usb_add_hcd;
- }
-+ device_wakeup_enable(usb_hcd->self.controller);
-
- ret = wusbhc_b_create(wusbhc);
- if (ret) {
-diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
-index d9c169f..9d29aa1 100644
---- a/drivers/usb/host/xhci-plat.c
-+++ b/drivers/usb/host/xhci-plat.c
-@@ -139,6 +139,7 @@ static int xhci_plat_probe(struct platform_device *pdev)
- ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (ret)
- goto unmap_registers;
-+ device_wakeup_enable(hcd->self.controller);
-
- /* USB 2.0 roothub is stored in the platform_device now. */
- hcd = platform_get_drvdata(pdev);
-diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
-index 6582a20..e208375 100644
---- a/drivers/usb/musb/musb_host.c
-+++ b/drivers/usb/musb/musb_host.c
-@@ -2657,6 +2657,7 @@ int musb_host_setup(struct musb *musb, int power_budget)
- if (ret < 0)
- return ret;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
- }
-
-diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
-index e9d4cd9..3775283 100644
---- a/drivers/usb/phy/phy-msm-usb.c
-+++ b/drivers/usb/phy/phy-msm-usb.c
-@@ -669,6 +669,7 @@ static void msm_otg_start_host(struct usb_phy *phy, int on)
- pdata->setup_gpio(OTG_STATE_A_HOST);
- #ifdef CONFIG_USB
- usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
-+ device_wakeup_enable(hcd->self.controller);
- #endif
- } else {
- dev_dbg(phy->dev, "host off\n");
-diff --git a/drivers/usb/phy/phy-mv-usb.c b/drivers/usb/phy/phy-mv-usb.c
-index 98f6ac6..44f316e 100644
---- a/drivers/usb/phy/phy-mv-usb.c
-+++ b/drivers/usb/phy/phy-mv-usb.c
-@@ -213,10 +213,12 @@ static void mv_otg_start_host(struct mv_otg *mvotg, int on)
-
- hcd = bus_to_hcd(otg->host);
-
-- if (on)
-+ if (on) {
- usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
-- else
-+ device_wakeup_enable(hcd->self.controller);
-+ } else {
- usb_remove_hcd(hcd);
-+ }
- #endif /* CONFIG_USB */
- }
-
-diff --git a/drivers/usb/renesas_usbhs/mod_host.c b/drivers/usb/renesas_usbhs/mod_host.c
-index e40f565..10e1ded 100644
---- a/drivers/usb/renesas_usbhs/mod_host.c
-+++ b/drivers/usb/renesas_usbhs/mod_host.c
-@@ -1469,6 +1469,7 @@ static int usbhsh_start(struct usbhs_priv *priv)
- ret = usb_add_hcd(hcd, 0, 0);
- if (ret < 0)
- return 0;
-+ device_wakeup_enable(hcd->self.controller);
-
- /*
- * pipe initialize and enable DCP
---
-1.8.5.5
-
+++ /dev/null
-From 6b63b9b2093258541dd79a3ed311cd1d0412b846 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 5 Jan 2014 14:42:39 +0100
-Subject: [PATCH] ohci-platform: Add support for devicetree instantiation
-
-Add support for ohci-platform instantiation from devicetree, including
-optionally getting clks and a phy from devicetree, and enabling / disabling
-those on power_on / off.
-
-This should allow using ohci-platform from devicetree in various cases.
-Specifically after this commit it can be used for the ohci controller found
-on Allwinner sunxi SoCs.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
-Acked-by: Alan Stern <stern@rowland.harvard.edu>
----
- Documentation/devicetree/bindings/usb/usb-ohci.txt | 22 +++
- drivers/usb/host/ohci-platform.c | 162 ++++++++++++++++++---
- 2 files changed, 162 insertions(+), 22 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/usb/usb-ohci.txt
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt
-new file mode 100644
-index 0000000..6ba38d9
---- /dev/null
-+++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt
-@@ -0,0 +1,22 @@
-+USB OHCI controllers
-+
-+Required properties:
-+- compatible : "usb-ohci"
-+- reg : ohci controller register range (address and length)
-+- interrupts : ohci controller interrupt
-+
-+Optional properties:
-+- clocks : a list of phandle + clock specifier pairs
-+- phys : phandle + phy specifier pair
-+- phy-names : "usb"
-+
-+Example:
-+
-+ ohci0: usb@01c14400 {
-+ compatible = "allwinner,sun4i-a10-ohci", "usb-ohci";
-+ reg = <0x01c14400 0x100>;
-+ interrupts = <64>;
-+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ };
-diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
-index 68f674c..49304dd 100644
---- a/drivers/usb/host/ohci-platform.c
-+++ b/drivers/usb/host/ohci-platform.c
-@@ -3,6 +3,7 @@
- *
- * Copyright 2007 Michael Buesch <m@bues.ch>
- * Copyright 2011-2012 Hauke Mehrtens <hauke@hauke-m.de>
-+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
- *
- * Derived from the OCHI-SSB driver
- * Derived from the OHCI-PCI driver
-@@ -14,11 +15,14 @@
- * Licensed under the GNU/GPL. See COPYING for details.
- */
-
-+#include <linux/clk.h>
-+#include <linux/dma-mapping.h>
- #include <linux/hrtimer.h>
- #include <linux/io.h>
- #include <linux/kernel.h>
- #include <linux/module.h>
- #include <linux/err.h>
-+#include <linux/phy/phy.h>
- #include <linux/platform_device.h>
- #include <linux/usb/ohci_pdriver.h>
- #include <linux/usb.h>
-@@ -27,6 +31,13 @@
- #include "ohci.h"
-
- #define DRIVER_DESC "OHCI generic platform driver"
-+#define OHCI_MAX_CLKS 3
-+#define hcd_to_ohci_priv(h) ((struct ohci_platform_priv *)hcd_to_ohci(h)->priv)
-+
-+struct ohci_platform_priv {
-+ struct clk *clks[OHCI_MAX_CLKS];
-+ struct phy *phy;
-+};
-
- static const char hcd_name[] = "ohci-platform";
-
-@@ -48,11 +59,67 @@ static int ohci_platform_reset(struct usb_hcd *hcd)
- return ohci_setup(hcd);
- }
-
-+static int ohci_platform_power_on(struct platform_device *dev)
-+{
-+ struct usb_hcd *hcd = platform_get_drvdata(dev);
-+ struct ohci_platform_priv *priv = hcd_to_ohci_priv(hcd);
-+ int clk, ret;
-+
-+ for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++) {
-+ ret = clk_prepare_enable(priv->clks[clk]);
-+ if (ret)
-+ goto err_disable_clks;
-+ }
-+
-+ if (priv->phy) {
-+ ret = phy_init(priv->phy);
-+ if (ret)
-+ goto err_disable_clks;
-+
-+ ret = phy_power_on(priv->phy);
-+ if (ret)
-+ goto err_exit_phy;
-+ }
-+
-+ return 0;
-+
-+err_exit_phy:
-+ phy_exit(priv->phy);
-+err_disable_clks:
-+ while (--clk >= 0)
-+ clk_disable_unprepare(priv->clks[clk]);
-+
-+ return ret;
-+}
-+
-+static void ohci_platform_power_off(struct platform_device *dev)
-+{
-+ struct usb_hcd *hcd = platform_get_drvdata(dev);
-+ struct ohci_platform_priv *priv = hcd_to_ohci_priv(hcd);
-+ int clk;
-+
-+ if (priv->phy) {
-+ phy_power_off(priv->phy);
-+ phy_exit(priv->phy);
-+ }
-+
-+ for (clk = OHCI_MAX_CLKS - 1; clk >= 0; clk--)
-+ if (priv->clks[clk])
-+ clk_disable_unprepare(priv->clks[clk]);
-+}
-+
- static struct hc_driver __read_mostly ohci_platform_hc_driver;
-
- static const struct ohci_driver_overrides platform_overrides __initconst = {
-- .product_desc = "Generic Platform OHCI controller",
-- .reset = ohci_platform_reset,
-+ .product_desc = "Generic Platform OHCI controller",
-+ .reset = ohci_platform_reset,
-+ .extra_priv_size = sizeof(struct ohci_platform_priv),
-+};
-+
-+static struct usb_ohci_pdata ohci_platform_defaults = {
-+ .power_on = ohci_platform_power_on,
-+ .power_suspend = ohci_platform_power_off,
-+ .power_off = ohci_platform_power_off,
- };
-
- static int ohci_platform_probe(struct platform_device *dev)
-@@ -60,17 +127,23 @@ static int ohci_platform_probe(struct platform_device *dev)
- struct usb_hcd *hcd;
- struct resource *res_mem;
- struct usb_ohci_pdata *pdata = dev_get_platdata(&dev->dev);
-- int irq;
-- int err = -ENOMEM;
--
-- if (!pdata) {
-- WARN_ON(1);
-- return -ENODEV;
-- }
-+ struct ohci_platform_priv *priv;
-+ int err, irq, clk = 0;
-
- if (usb_disabled())
- return -ENODEV;
-
-+ /*
-+ * Use reasonable defaults so platforms don't have to provide these
-+ * with DT probing on ARM.
-+ */
-+ if (!pdata)
-+ pdata = &ohci_platform_defaults;
-+
-+ err = dma_coerce_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
-+ if (err)
-+ return err;
-+
- irq = platform_get_irq(dev, 0);
- if (irq < 0) {
- dev_err(&dev->dev, "no irq provided");
-@@ -83,17 +156,40 @@ static int ohci_platform_probe(struct platform_device *dev)
- return -ENXIO;
- }
-
-+ hcd = usb_create_hcd(&ohci_platform_hc_driver, &dev->dev,
-+ dev_name(&dev->dev));
-+ if (!hcd)
-+ return -ENOMEM;
-+
-+ platform_set_drvdata(dev, hcd);
-+ dev->dev.platform_data = pdata;
-+ priv = hcd_to_ohci_priv(hcd);
-+
-+ if (pdata == &ohci_platform_defaults && dev->dev.of_node) {
-+ priv->phy = devm_phy_get(&dev->dev, "usb");
-+ if (IS_ERR(priv->phy)) {
-+ err = PTR_ERR(priv->phy);
-+ if (err == -EPROBE_DEFER)
-+ goto err_put_hcd;
-+ priv->phy = NULL;
-+ }
-+
-+ for (clk = 0; clk < OHCI_MAX_CLKS; clk++) {
-+ priv->clks[clk] = of_clk_get(dev->dev.of_node, clk);
-+ if (IS_ERR(priv->clks[clk])) {
-+ err = PTR_ERR(priv->clks[clk]);
-+ if (err == -EPROBE_DEFER)
-+ goto err_put_clks;
-+ priv->clks[clk] = NULL;
-+ break;
-+ }
-+ }
-+ }
-+
- if (pdata->power_on) {
- err = pdata->power_on(dev);
- if (err < 0)
-- return err;
-- }
--
-- hcd = usb_create_hcd(&ohci_platform_hc_driver, &dev->dev,
-- dev_name(&dev->dev));
-- if (!hcd) {
-- err = -ENOMEM;
-- goto err_power;
-+ goto err_put_clks;
- }
-
- hcd->rsrc_start = res_mem->start;
-@@ -102,11 +198,11 @@ static int ohci_platform_probe(struct platform_device *dev)
- hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
- if (IS_ERR(hcd->regs)) {
- err = PTR_ERR(hcd->regs);
-- goto err_put_hcd;
-+ goto err_power;
- }
- err = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (err)
-- goto err_put_hcd;
-+ goto err_power;
-
- device_wakeup_enable(hcd->self.controller);
-
-@@ -114,11 +210,17 @@ static int ohci_platform_probe(struct platform_device *dev)
-
- return err;
-
--err_put_hcd:
-- usb_put_hcd(hcd);
- err_power:
- if (pdata->power_off)
- pdata->power_off(dev);
-+err_put_clks:
-+ while (--clk >= 0)
-+ clk_put(priv->clks[clk]);
-+err_put_hcd:
-+ if (pdata == &ohci_platform_defaults)
-+ dev->dev.platform_data = NULL;
-+
-+ usb_put_hcd(hcd);
-
- return err;
- }
-@@ -127,13 +229,22 @@ static int ohci_platform_remove(struct platform_device *dev)
- {
- struct usb_hcd *hcd = platform_get_drvdata(dev);
- struct usb_ohci_pdata *pdata = dev_get_platdata(&dev->dev);
-+ struct ohci_platform_priv *priv = hcd_to_ohci_priv(hcd);
-+ int clk;
-
- usb_remove_hcd(hcd);
-- usb_put_hcd(hcd);
-
- if (pdata->power_off)
- pdata->power_off(dev);
-
-+ for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++)
-+ clk_put(priv->clks[clk]);
-+
-+ usb_put_hcd(hcd);
-+
-+ if (pdata == &ohci_platform_defaults)
-+ dev->dev.platform_data = NULL;
-+
- return 0;
- }
-
-@@ -180,6 +291,12 @@ static int ohci_platform_resume(struct device *dev)
- #define ohci_platform_resume NULL
- #endif /* CONFIG_PM */
-
-+static const struct of_device_id ohci_platform_ids[] = {
-+ { .compatible = "usb-ohci", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, ohci_platform_ids);
-+
- static const struct platform_device_id ohci_platform_table[] = {
- { "ohci-platform", 0 },
- { }
-@@ -200,6 +317,7 @@ static int ohci_platform_resume(struct device *dev)
- .owner = THIS_MODULE,
- .name = "ohci-platform",
- .pm = &ohci_platform_pm_ops,
-+ .of_match_table = ohci_platform_ids,
- }
- };
-
---
-1.8.5.5
-
+++ /dev/null
-From 543824fa2a8a592a6eec0e0053063284980dc378 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 5 Jan 2014 00:04:02 +0100
-Subject: [PATCH] ehci-platform: Add support for clks and phy passed through
- devicetree
-
-Currently ehci-platform is only used in combination with devicetree when used
-with some Via socs. By extending it to (optionally) get clks and a phy from
-devicetree, and enabling / disabling those on power_on / off, it can be used
-more generically. Specifically after this commit it can be used for the
-ehci controller on Allwinner sunxi SoCs.
-
-Since ehci-platform is intended to handle any generic enough non pci ehci
-device, add a "usb-ehci" compatibility string.
-
-There already is a usb-ehci device-tree bindings document, update this
-with clks and phy bindings info.
-
-Although actually quite generic so far the via,vt8500 compatibilty string
-had its own bindings document. Somehow we even ended up with 2 of them. Since
-these provide no extra information over the generic usb-ehci documentation,
-this patch removes them.
-
-The ehci-ppc-of.c driver also claims the usb-ehci compatibility string,
-even though it mostly is ibm,usb-ehci-440epx specific. ehci-platform.c is
-not needed on ppc platforms, so add a !PPC_OF dependency to it to avoid
-2 drivers claiming the same compatibility string getting build on ppc.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
-Acked-by: Alan Stern <stern@rowland.harvard.edu>
----
- Documentation/devicetree/bindings/usb/usb-ehci.txt | 25 +++-
- .../devicetree/bindings/usb/via,vt8500-ehci.txt | 15 ---
- .../devicetree/bindings/usb/vt8500-ehci.txt | 12 --
- drivers/usb/host/Kconfig | 1 +
- drivers/usb/host/ehci-platform.c | 147 +++++++++++++++++----
- 5 files changed, 142 insertions(+), 58 deletions(-)
- delete mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
- delete mode 100644 Documentation/devicetree/bindings/usb/vt8500-ehci.txt
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt
-index fa18612..2c1aeeb 100644
---- a/Documentation/devicetree/bindings/usb/usb-ehci.txt
-+++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt
-@@ -7,13 +7,14 @@ Required properties:
- (debug-port or other) can be also specified here, but only after
- definition of standard EHCI registers.
- - interrupts : one EHCI interrupt should be described here.
--If device registers are implemented in big endian mode, the device
--node should have "big-endian-regs" property.
--If controller implementation operates with big endian descriptors,
--"big-endian-desc" property should be specified.
--If both big endian registers and descriptors are used by the controller
--implementation, "big-endian" property can be specified instead of having
--both "big-endian-regs" and "big-endian-desc".
-+
-+Optional properties:
-+ - big-endian-regs : boolean, set this for hcds with big-endian registers
-+ - big-endian-desc : boolean, set this for hcds with big-endian descriptors
-+ - big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
-+ - clocks : a list of phandle + clock specifier pairs
-+ - phys : phandle + phy specifier pair
-+ - phy-names : "usb"
-
- Example (Sequoia 440EPx):
- ehci@e0000300 {
-@@ -23,3 +24,13 @@ Example (Sequoia 440EPx):
- reg = <0 e0000300 90 0 e0000390 70>;
- big-endian;
- };
-+
-+Example (Allwinner sun4i A10 SoC):
-+ ehci0: usb@01c14000 {
-+ compatible = "allwinner,sun4i-a10-ehci", "usb-ehci";
-+ reg = <0x01c14000 0x100>;
-+ interrupts = <39>;
-+ clocks = <&ahb_gates 1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ };
-diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
-deleted file mode 100644
-index 17b3ad1..0000000
---- a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
-+++ /dev/null
-@@ -1,15 +0,0 @@
--VIA/Wondermedia VT8500 EHCI Controller
-------------------------------------------------------
--
--Required properties:
--- compatible : "via,vt8500-ehci"
--- reg : Should contain 1 register ranges(address and length)
--- interrupts : ehci controller interrupt
--
--Example:
--
-- ehci@d8007900 {
-- compatible = "via,vt8500-ehci";
-- reg = <0xd8007900 0x200>;
-- interrupts = <43>;
-- };
-diff --git a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
-deleted file mode 100644
-index 5fb8fd6..0000000
---- a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
-+++ /dev/null
-@@ -1,12 +0,0 @@
--VIA VT8500 and Wondermedia WM8xxx SoC USB controllers.
--
--Required properties:
-- - compatible: Should be "via,vt8500-ehci" or "wm,prizm-ehci".
-- - reg: Address range of the ehci registers. size should be 0x200
-- - interrupts: Should contain the ehci interrupt.
--
--usb: ehci@D8007100 {
-- compatible = "wm,prizm-ehci", "usb-ehci";
-- reg = <0xD8007100 0x200>;
-- interrupts = <1>;
--};
-diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
-index a9707da..e28cbe0 100644
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -255,6 +255,7 @@ config USB_EHCI_ATH79
-
- config USB_EHCI_HCD_PLATFORM
- tristate "Generic EHCI driver for a platform device"
-+ depends on !PPC_OF
- default n
- ---help---
- Adds an EHCI host driver for a generic platform device, which
-diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
-index 01536cf..5ebd0b7 100644
---- a/drivers/usb/host/ehci-platform.c
-+++ b/drivers/usb/host/ehci-platform.c
-@@ -3,6 +3,7 @@
- *
- * Copyright 2007 Steven Brown <sbrown@cortland.com>
- * Copyright 2010-2012 Hauke Mehrtens <hauke@hauke-m.de>
-+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
- *
- * Derived from the ohci-ssb driver
- * Copyright 2007 Michael Buesch <m@bues.ch>
-@@ -18,6 +19,7 @@
- *
- * Licensed under the GNU/GPL. See COPYING for details.
- */
-+#include <linux/clk.h>
- #include <linux/dma-mapping.h>
- #include <linux/err.h>
- #include <linux/kernel.h>
-@@ -25,6 +27,7 @@
- #include <linux/io.h>
- #include <linux/module.h>
- #include <linux/of.h>
-+#include <linux/phy/phy.h>
- #include <linux/platform_device.h>
- #include <linux/usb.h>
- #include <linux/usb/hcd.h>
-@@ -33,6 +36,13 @@
- #include "ehci.h"
-
- #define DRIVER_DESC "EHCI generic platform driver"
-+#define EHCI_MAX_CLKS 3
-+#define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv)
-+
-+struct ehci_platform_priv {
-+ struct clk *clks[EHCI_MAX_CLKS];
-+ struct phy *phy;
-+};
-
- static const char hcd_name[] = "ehci-platform";
-
-@@ -64,38 +74,90 @@ static int ehci_platform_reset(struct usb_hcd *hcd)
- return 0;
- }
-
-+static int ehci_platform_power_on(struct platform_device *dev)
-+{
-+ struct usb_hcd *hcd = platform_get_drvdata(dev);
-+ struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
-+ int clk, ret;
-+
-+ for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) {
-+ ret = clk_prepare_enable(priv->clks[clk]);
-+ if (ret)
-+ goto err_disable_clks;
-+ }
-+
-+ if (priv->phy) {
-+ ret = phy_init(priv->phy);
-+ if (ret)
-+ goto err_disable_clks;
-+
-+ ret = phy_power_on(priv->phy);
-+ if (ret)
-+ goto err_exit_phy;
-+ }
-+
-+ return 0;
-+
-+err_exit_phy:
-+ phy_exit(priv->phy);
-+err_disable_clks:
-+ while (--clk >= 0)
-+ clk_disable_unprepare(priv->clks[clk]);
-+
-+ return ret;
-+}
-+
-+static void ehci_platform_power_off(struct platform_device *dev)
-+{
-+ struct usb_hcd *hcd = platform_get_drvdata(dev);
-+ struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
-+ int clk;
-+
-+ if (priv->phy) {
-+ phy_power_off(priv->phy);
-+ phy_exit(priv->phy);
-+ }
-+
-+ for (clk = EHCI_MAX_CLKS - 1; clk >= 0; clk--)
-+ if (priv->clks[clk])
-+ clk_disable_unprepare(priv->clks[clk]);
-+}
-+
- static struct hc_driver __read_mostly ehci_platform_hc_driver;
-
- static const struct ehci_driver_overrides platform_overrides __initconst = {
-- .reset = ehci_platform_reset,
-+ .reset = ehci_platform_reset,
-+ .extra_priv_size = sizeof(struct ehci_platform_priv),
- };
-
--static struct usb_ehci_pdata ehci_platform_defaults;
-+static struct usb_ehci_pdata ehci_platform_defaults = {
-+ .power_on = ehci_platform_power_on,
-+ .power_suspend = ehci_platform_power_off,
-+ .power_off = ehci_platform_power_off,
-+};
-
- static int ehci_platform_probe(struct platform_device *dev)
- {
- struct usb_hcd *hcd;
- struct resource *res_mem;
-- struct usb_ehci_pdata *pdata;
-- int irq;
-- int err;
-+ struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
-+ struct ehci_platform_priv *priv;
-+ int err, irq, clk = 0;
-
- if (usb_disabled())
- return -ENODEV;
-
- /*
-- * use reasonable defaults so platforms don't have to provide these.
-- * with DT probing on ARM, none of these are set.
-+ * Use reasonable defaults so platforms don't have to provide these
-+ * with DT probing on ARM.
- */
-- if (!dev_get_platdata(&dev->dev))
-- dev->dev.platform_data = &ehci_platform_defaults;
-+ if (!pdata)
-+ pdata = &ehci_platform_defaults;
-
- err = dma_coerce_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
- if (err)
- return err;
-
-- pdata = dev_get_platdata(&dev->dev);
--
- irq = platform_get_irq(dev, 0);
- if (irq < 0) {
- dev_err(&dev->dev, "no irq provided");
-@@ -107,17 +169,40 @@ static int ehci_platform_probe(struct platform_device *dev)
- return -ENXIO;
- }
-
-+ hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
-+ dev_name(&dev->dev));
-+ if (!hcd)
-+ return -ENOMEM;
-+
-+ platform_set_drvdata(dev, hcd);
-+ dev->dev.platform_data = pdata;
-+ priv = hcd_to_ehci_priv(hcd);
-+
-+ if (pdata == &ehci_platform_defaults && dev->dev.of_node) {
-+ priv->phy = devm_phy_get(&dev->dev, "usb");
-+ if (IS_ERR(priv->phy)) {
-+ err = PTR_ERR(priv->phy);
-+ if (err == -EPROBE_DEFER)
-+ goto err_put_hcd;
-+ priv->phy = NULL;
-+ }
-+
-+ for (clk = 0; clk < EHCI_MAX_CLKS; clk++) {
-+ priv->clks[clk] = of_clk_get(dev->dev.of_node, clk);
-+ if (IS_ERR(priv->clks[clk])) {
-+ err = PTR_ERR(priv->clks[clk]);
-+ if (err == -EPROBE_DEFER)
-+ goto err_put_clks;
-+ priv->clks[clk] = NULL;
-+ break;
-+ }
-+ }
-+ }
-+
- if (pdata->power_on) {
- err = pdata->power_on(dev);
- if (err < 0)
-- return err;
-- }
--
-- hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
-- dev_name(&dev->dev));
-- if (!hcd) {
-- err = -ENOMEM;
-- goto err_power;
-+ goto err_put_clks;
- }
-
- hcd->rsrc_start = res_mem->start;
-@@ -126,22 +211,28 @@ static int ehci_platform_probe(struct platform_device *dev)
- hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
- if (IS_ERR(hcd->regs)) {
- err = PTR_ERR(hcd->regs);
-- goto err_put_hcd;
-+ goto err_power;
- }
- err = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (err)
-- goto err_put_hcd;
-+ goto err_power;
-
- device_wakeup_enable(hcd->self.controller);
- platform_set_drvdata(dev, hcd);
-
- return err;
-
--err_put_hcd:
-- usb_put_hcd(hcd);
- err_power:
- if (pdata->power_off)
- pdata->power_off(dev);
-+err_put_clks:
-+ while (--clk >= 0)
-+ clk_put(priv->clks[clk]);
-+err_put_hcd:
-+ if (pdata == &ehci_platform_defaults)
-+ dev->dev.platform_data = NULL;
-+
-+ usb_put_hcd(hcd);
-
- return err;
- }
-@@ -150,13 +241,19 @@ static int ehci_platform_remove(struct platform_device *dev)
- {
- struct usb_hcd *hcd = platform_get_drvdata(dev);
- struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
-+ struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
-+ int clk;
-
- usb_remove_hcd(hcd);
-- usb_put_hcd(hcd);
-
- if (pdata->power_off)
- pdata->power_off(dev);
-
-+ for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++)
-+ clk_put(priv->clks[clk]);
-+
-+ usb_put_hcd(hcd);
-+
- if (pdata == &ehci_platform_defaults)
- dev->dev.platform_data = NULL;
-
-@@ -207,8 +304,10 @@ static int ehci_platform_resume(struct device *dev)
- static const struct of_device_id vt8500_ehci_ids[] = {
- { .compatible = "via,vt8500-ehci", },
- { .compatible = "wm,prizm-ehci", },
-+ { .compatible = "usb-ehci", },
- {}
- };
-+MODULE_DEVICE_TABLE(of, vt8500_ehci_ids);
-
- static const struct platform_device_id ehci_platform_table[] = {
- { "ehci-platform", 0 },
---
-1.8.5.5
-
+++ /dev/null
-From 10d7c018269928db8487057c4c143dbd014d2262 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 21 Jan 2014 16:05:47 +0100
-Subject: [PATCH] ohci-platform: Add support for controllers with big-endian
- regs / descriptors
-
-Note this commit uses the same devicetree booleans for this as the ones
-already existing in the usb-ehci bindings, see:
-Documentation/devicetree/bindings/usb/usb-ehci.txt
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- Documentation/devicetree/bindings/usb/usb-ohci.txt | 3 +++
- drivers/usb/host/ohci-platform.c | 27 ++++++++++++++++++++++
- 2 files changed, 30 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt
-index 6ba38d9..6933b0c 100644
---- a/Documentation/devicetree/bindings/usb/usb-ohci.txt
-+++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt
-@@ -6,6 +6,9 @@ Required properties:
- - interrupts : ohci controller interrupt
-
- Optional properties:
-+- big-endian-regs : boolean, set this for hcds with big-endian registers
-+- big-endian-desc : boolean, set this for hcds with big-endian descriptors
-+- big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
- - clocks : a list of phandle + clock specifier pairs
- - phys : phandle + phy specifier pair
- - phy-names : "usb"
-diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
-index 49304dd..e2c28fd 100644
---- a/drivers/usb/host/ohci-platform.c
-+++ b/drivers/usb/host/ohci-platform.c
-@@ -128,6 +128,7 @@ static int ohci_platform_probe(struct platform_device *dev)
- struct resource *res_mem;
- struct usb_ohci_pdata *pdata = dev_get_platdata(&dev->dev);
- struct ohci_platform_priv *priv;
-+ struct ohci_hcd *ohci;
- int err, irq, clk = 0;
-
- if (usb_disabled())
-@@ -164,8 +165,34 @@ static int ohci_platform_probe(struct platform_device *dev)
- platform_set_drvdata(dev, hcd);
- dev->dev.platform_data = pdata;
- priv = hcd_to_ohci_priv(hcd);
-+ ohci = hcd_to_ohci(hcd);
-
- if (pdata == &ohci_platform_defaults && dev->dev.of_node) {
-+ if (of_property_read_bool(dev->dev.of_node, "big-endian-regs"))
-+ ohci->flags |= OHCI_QUIRK_BE_MMIO;
-+
-+ if (of_property_read_bool(dev->dev.of_node, "big-endian-desc"))
-+ ohci->flags |= OHCI_QUIRK_BE_DESC;
-+
-+ if (of_property_read_bool(dev->dev.of_node, "big-endian"))
-+ ohci->flags |= OHCI_QUIRK_BE_MMIO | OHCI_QUIRK_BE_DESC;
-+
-+#ifndef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
-+ if (ohci->flags & OHCI_QUIRK_BE_MMIO) {
-+ dev_err(&dev->dev,
-+ "Error big-endian-regs not compiled in\n");
-+ err = -EINVAL;
-+ goto err_put_hcd;
-+ }
-+#endif
-+#ifndef CONFIG_USB_OHCI_BIG_ENDIAN_DESC
-+ if (ohci->flags & OHCI_QUIRK_BE_DESC) {
-+ dev_err(&dev->dev,
-+ "Error big-endian-desc not compiled in\n");
-+ err = -EINVAL;
-+ goto err_put_hcd;
-+ }
-+#endif
- priv->phy = devm_phy_get(&dev->dev, "usb");
- if (IS_ERR(priv->phy)) {
- err = PTR_ERR(priv->phy);
---
-1.8.5.5
-
+++ /dev/null
-From 57b5e74a0d7ba5dbf77ee05a2693635faba5fe30 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 21 Jan 2014 16:20:53 +0100
-Subject: [PATCH] ehci-platform: Add support for controllers with big-endian
- regs / descriptors
-
-This uses the already documented devicetree booleans for this, see:
-Documentation/devicetree/bindings/usb/usb-ehci.txt
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/usb/host/ehci-platform.c | 33 +++++++++++++++++++++++++++++++--
- 1 file changed, 31 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
-index 5ebd0b7..8fde649 100644
---- a/drivers/usb/host/ehci-platform.c
-+++ b/drivers/usb/host/ehci-platform.c
-@@ -55,8 +55,10 @@ static int ehci_platform_reset(struct usb_hcd *hcd)
-
- hcd->has_tt = pdata->has_tt;
- ehci->has_synopsys_hc_bug = pdata->has_synopsys_hc_bug;
-- ehci->big_endian_desc = pdata->big_endian_desc;
-- ehci->big_endian_mmio = pdata->big_endian_mmio;
-+ if (pdata->big_endian_desc)
-+ ehci->big_endian_desc = 1;
-+ if (pdata->big_endian_mmio)
-+ ehci->big_endian_mmio = 1;
- ehci->ignore_oc = pdata->ignore_oc;
-
- if (pdata->pre_setup) {
-@@ -142,6 +144,7 @@ static int ehci_platform_probe(struct platform_device *dev)
- struct resource *res_mem;
- struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
- struct ehci_platform_priv *priv;
-+ struct ehci_hcd *ehci;
- int err, irq, clk = 0;
-
- if (usb_disabled())
-@@ -177,8 +180,34 @@ static int ehci_platform_probe(struct platform_device *dev)
- platform_set_drvdata(dev, hcd);
- dev->dev.platform_data = pdata;
- priv = hcd_to_ehci_priv(hcd);
-+ ehci = hcd_to_ehci(hcd);
-
- if (pdata == &ehci_platform_defaults && dev->dev.of_node) {
-+ if (of_property_read_bool(dev->dev.of_node, "big-endian-regs"))
-+ ehci->big_endian_mmio = 1;
-+
-+ if (of_property_read_bool(dev->dev.of_node, "big-endian-desc"))
-+ ehci->big_endian_desc = 1;
-+
-+ if (of_property_read_bool(dev->dev.of_node, "big-endian"))
-+ ehci->big_endian_mmio = ehci->big_endian_desc = 1;
-+
-+#ifndef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
-+ if (ehci->big_endian_mmio) {
-+ dev_err(&dev->dev,
-+ "Error big-endian-regs not compiled in\n");
-+ err = -EINVAL;
-+ goto err_put_hcd;
-+ }
-+#endif
-+#ifndef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
-+ if (ehci->big_endian_desc) {
-+ dev_err(&dev->dev,
-+ "Error big-endian-desc not compiled in\n");
-+ err = -EINVAL;
-+ goto err_put_hcd;
-+ }
-+#endif
- priv->phy = devm_phy_get(&dev->dev, "usb");
- if (IS_ERR(priv->phy)) {
- err = PTR_ERR(priv->phy);
---
-1.8.5.5
-
+++ /dev/null
-From abddd82743cc2c4acdfe66a6d5e63f2085d2269b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 11 Feb 2014 11:27:29 +0100
-Subject: [PATCH] ohci-platform: Change compatible string from usb-ohci to
- generic-ohci
-
-The initial versions of the devicetree enablement patches for ohci-platform
-used "ohci-platform" as compatible string. However this was disliked by various
-reviewers because the platform bus is a Linux invention and devicetree is
-supposed to be OS agnostic. After much discussion I gave up and went with
-the generic usb-ohci as requested.
-
-In retro-spect I should have chosen something different, the dts files for many
-existing boards already claim to be compatible with "usb-ohci", ie they have:
-
- compatible = "ti,ohci-omap3", "usb-ohci";
-
-In theory this should not be a problem since the "ti,ohci-omap3" entry takes
-presedence, but in practice using a conflicting compatible string is an issue,
-because it makes which driver gets used depend on driver registration order.
-
-This patch changes the compatible string claimed by ohci-platform to
-"generic-ohci", avoiding the driver registration / module loading ordering
-problems.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- Documentation/devicetree/bindings/usb/usb-ohci.txt | 4 ++--
- drivers/usb/host/ohci-platform.c | 2 +-
- 2 files changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt
-index 6933b0c..45f67d9 100644
---- a/Documentation/devicetree/bindings/usb/usb-ohci.txt
-+++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt
-@@ -1,7 +1,7 @@
- USB OHCI controllers
-
- Required properties:
--- compatible : "usb-ohci"
-+- compatible : "generic-ohci"
- - reg : ohci controller register range (address and length)
- - interrupts : ohci controller interrupt
-
-@@ -16,7 +16,7 @@ Optional properties:
- Example:
-
- ohci0: usb@01c14400 {
-- compatible = "allwinner,sun4i-a10-ohci", "usb-ohci";
-+ compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
- reg = <0x01c14400 0x100>;
- interrupts = <64>;
- clocks = <&usb_clk 6>, <&ahb_gates 2>;
-diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
-index e2c28fd..b6ca0b2 100644
---- a/drivers/usb/host/ohci-platform.c
-+++ b/drivers/usb/host/ohci-platform.c
-@@ -319,7 +319,7 @@ static int ohci_platform_resume(struct device *dev)
- #endif /* CONFIG_PM */
-
- static const struct of_device_id ohci_platform_ids[] = {
-- { .compatible = "usb-ohci", },
-+ { .compatible = "generic-ohci", },
- { }
- };
- MODULE_DEVICE_TABLE(of, ohci_platform_ids);
---
-1.8.5.5
-
+++ /dev/null
-From 80c544c77beeffee4e9484bf193ab391297688cd Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 11 Feb 2014 11:46:13 +0100
-Subject: [PATCH] ehci-platform: Change compatible string from usb-ehci to
- generic-ehci
-
-The initial versions of the devicetree enablement patches for ehci-platform
-used "ehci-platform" as compatible string. However this was disliked by various
-reviewers because the platform bus is a Linux invention and devicetree is
-supposed to be OS agnostic. After much discussion I gave up, added a:
-"depends on !PPC_OF" to Kconfig to avoid a known conflict with PPC-OF platforms
-and went with the generic usb-ehci as requested.
-
-In retro-spect I should have chosen something different, the dts files for many
-existing boards already claim to be compatible with "usb-ehci", ie they have:
-
- compatible = "ti,ehci-omap", "usb-ehci";
-
-In theory this should not be a problem since the "ti,ehci-omap" entry takes
-presedence, but in practice using a conflicting compatible string is an issue,
-because it makes which driver gets used depend on driver registration order.
-
-This patch changes the compatible string claimed by ehci-platform to
-"generic-ehci", avoiding the driver registration / module loading ordering
-problems, and removes the "depends on !PPC_OF" workaround.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- Documentation/devicetree/bindings/usb/usb-ehci.txt | 4 ++--
- drivers/usb/host/Kconfig | 1 -
- drivers/usb/host/ehci-platform.c | 2 +-
- 3 files changed, 3 insertions(+), 4 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt
-index 2c1aeeb..ff151ec 100644
---- a/Documentation/devicetree/bindings/usb/usb-ehci.txt
-+++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt
-@@ -1,7 +1,7 @@
- USB EHCI controllers
-
- Required properties:
-- - compatible : should be "usb-ehci".
-+ - compatible : should be "generic-ehci".
- - reg : should contain at least address and length of the standard EHCI
- register set for the device. Optional platform-dependent registers
- (debug-port or other) can be also specified here, but only after
-@@ -27,7 +27,7 @@ Example (Sequoia 440EPx):
-
- Example (Allwinner sun4i A10 SoC):
- ehci0: usb@01c14000 {
-- compatible = "allwinner,sun4i-a10-ehci", "usb-ehci";
-+ compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
- reg = <0x01c14000 0x100>;
- interrupts = <39>;
- clocks = <&ahb_gates 1>;
-diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
-index e28cbe0..a9707da 100644
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -255,7 +255,6 @@ config USB_EHCI_ATH79
-
- config USB_EHCI_HCD_PLATFORM
- tristate "Generic EHCI driver for a platform device"
-- depends on !PPC_OF
- default n
- ---help---
- Adds an EHCI host driver for a generic platform device, which
-diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
-index 8fde649..1178730 100644
---- a/drivers/usb/host/ehci-platform.c
-+++ b/drivers/usb/host/ehci-platform.c
-@@ -333,7 +333,7 @@ static int ehci_platform_resume(struct device *dev)
- static const struct of_device_id vt8500_ehci_ids[] = {
- { .compatible = "via,vt8500-ehci", },
- { .compatible = "wm,prizm-ehci", },
-- { .compatible = "usb-ehci", },
-+ { .compatible = "generic-ehci", },
- {}
- };
- MODULE_DEVICE_TABLE(of, vt8500_ehci_ids);
---
-1.8.5.5
-
+++ /dev/null
-From 3aa1e8b65b7db768fade643e26f8995860596795 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 11 Feb 2014 17:41:48 +0100
-Subject: [PATCH] uhci-platform: Change compatible string from platform-uhci to
- generic-uhci
-
-This brings the uhci-platform bindings in sync with what we've done for
-the ohci- and ehci-platform drivers. As discussed there using platform as a
-prefix is a bit weird as the platform bus is a Linux specific thing and
-the bindings are supposed to be OS agnostic.
-
-Note that the old platform-uhci compatible string is kept around for, well,
-compatibility reasons.
-
-While at it rename the bindings txt file to match the name of all the
-other ?hci-platform bindings docs.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- Documentation/devicetree/bindings/usb/platform-uhci.txt | 15 ---------------
- Documentation/devicetree/bindings/usb/usb-uhci.txt | 15 +++++++++++++++
- drivers/usb/host/uhci-platform.c | 1 +
- 3 files changed, 16 insertions(+), 15 deletions(-)
- delete mode 100644 Documentation/devicetree/bindings/usb/platform-uhci.txt
- create mode 100644 Documentation/devicetree/bindings/usb/usb-uhci.txt
-
-diff --git a/Documentation/devicetree/bindings/usb/platform-uhci.txt b/Documentation/devicetree/bindings/usb/platform-uhci.txt
-deleted file mode 100644
-index a4fb071..0000000
---- a/Documentation/devicetree/bindings/usb/platform-uhci.txt
-+++ /dev/null
-@@ -1,15 +0,0 @@
--Generic Platform UHCI Controller
-------------------------------------------------------
--
--Required properties:
--- compatible : "platform-uhci"
--- reg : Should contain 1 register ranges(address and length)
--- interrupts : UHCI controller interrupt
--
--Example:
--
-- uhci@d8007b00 {
-- compatible = "platform-uhci";
-- reg = <0xd8007b00 0x200>;
-- interrupts = <43>;
-- };
-diff --git a/Documentation/devicetree/bindings/usb/usb-uhci.txt b/Documentation/devicetree/bindings/usb/usb-uhci.txt
-new file mode 100644
-index 0000000..2981334
---- /dev/null
-+++ b/Documentation/devicetree/bindings/usb/usb-uhci.txt
-@@ -0,0 +1,15 @@
-+Generic Platform UHCI Controller
-+-----------------------------------------------------
-+
-+Required properties:
-+- compatible : "generic-uhci" (deprecated: "platform-uhci")
-+- reg : Should contain 1 register ranges(address and length)
-+- interrupts : UHCI controller interrupt
-+
-+Example:
-+
-+ uhci@d8007b00 {
-+ compatible = "generic-uhci";
-+ reg = <0xd8007b00 0x200>;
-+ interrupts = <43>;
-+ };
-diff --git a/drivers/usb/host/uhci-platform.c b/drivers/usb/host/uhci-platform.c
-index 44e6c9d..01833ab 100644
---- a/drivers/usb/host/uhci-platform.c
-+++ b/drivers/usb/host/uhci-platform.c
-@@ -148,6 +148,7 @@ static void uhci_hcd_platform_shutdown(struct platform_device *op)
- }
-
- static const struct of_device_id platform_uhci_ids[] = {
-+ { .compatible = "generic-uhci", },
- { .compatible = "platform-uhci", },
- {}
- };
---
-1.8.5.5
-
+++ /dev/null
-From 1f5109503787538c4a5deb3be7da8336951b105b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 11 Feb 2014 17:50:51 +0100
-Subject: [PATCH] xhci-platform: Change compatible string from xhci-platform to
- generic-xhci
-
-This brings the xhci-platform bindings in sync with what we've done for
-the ohci- and ehci-platform drivers. As discussed there using platform as a
-postfix is a bit weird as the platform bus is a Linux specific thing and
-the bindings are supposed to be OS agnostic.
-
-Note that the old xhci-platform compatible string is kept around for, well,
-compatibility reasons.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- Documentation/devicetree/bindings/usb/usb-xhci.txt | 4 ++--
- drivers/usb/host/xhci-plat.c | 1 +
- 2 files changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
-index 5752df0..90f8f60 100644
---- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
-+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
-@@ -1,14 +1,14 @@
- USB xHCI controllers
-
- Required properties:
-- - compatible: should be "xhci-platform".
-+ - compatible: should be "generic-xhci" (deprecated: "xhci-platform").
- - reg: should contain address and length of the standard XHCI
- register set for the device.
- - interrupts: one XHCI interrupt should be described here.
-
- Example:
- usb@f0931000 {
-- compatible = "xhci-platform";
-+ compatible = "generic-xhci";
- reg = <0xf0931000 0x8c8>;
- interrupts = <0x0 0x4e 0x0>;
- };
-diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
-index 8abda5c..8affef9 100644
---- a/drivers/usb/host/xhci-plat.c
-+++ b/drivers/usb/host/xhci-plat.c
-@@ -226,6 +226,7 @@ static int xhci_plat_resume(struct device *dev)
-
- #ifdef CONFIG_OF
- static const struct of_device_id usb_xhci_of_match[] = {
-+ { .compatible = "generic-xhci" },
- { .compatible = "xhci-platform" },
- { },
- };
---
-1.8.5.5
-
+++ /dev/null
-From edb7ebba49b6946e80dfac0d13ac15028952aa29 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Thu, 9 Jan 2014 19:33:04 +0100
-Subject: [PATCH] clk: sunxi: Add support for USB clock-register reset bits
-
-The usb-clk register is special in that it not only contains clk gate bits,
-but also has a few reset bits. This commit adds support for this by allowing
-gates type sunxi clks to also register a reset controller.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/clk/sunxi/clk-sunxi.c | 71 +++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 71 insertions(+)
-
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 46a38b4..2dbaee7 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -18,6 +18,7 @@
- #include <linux/clkdev.h>
- #include <linux/of.h>
- #include <linux/of_address.h>
-+#include <linux/reset-controller.h>
-
- #include "clk-factors.h"
-
-@@ -852,6 +853,59 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
-
-
- /**
-+ * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
-+ */
-+
-+struct gates_reset_data {
-+ void __iomem *reg;
-+ spinlock_t *lock;
-+ struct reset_controller_dev rcdev;
-+};
-+
-+static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ struct gates_reset_data *data = container_of(rcdev,
-+ struct gates_reset_data,
-+ rcdev);
-+ unsigned long flags;
-+ u32 reg;
-+
-+ spin_lock_irqsave(data->lock, flags);
-+
-+ reg = readl(data->reg);
-+ writel(reg & ~BIT(id), data->reg);
-+
-+ spin_unlock_irqrestore(data->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ struct gates_reset_data *data = container_of(rcdev,
-+ struct gates_reset_data,
-+ rcdev);
-+ unsigned long flags;
-+ u32 reg;
-+
-+ spin_lock_irqsave(data->lock, flags);
-+
-+ reg = readl(data->reg);
-+ writel(reg | BIT(id), data->reg);
-+
-+ spin_unlock_irqrestore(data->lock, flags);
-+
-+ return 0;
-+}
-+
-+static struct reset_control_ops sunxi_gates_reset_ops = {
-+ .assert = sunxi_gates_reset_assert,
-+ .deassert = sunxi_gates_reset_deassert,
-+};
-+
-+/**
- * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
- */
-
-@@ -859,6 +913,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
-
- struct gates_data {
- DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
-+ u32 reset_mask;
- };
-
- static const struct gates_data sun4i_axi_gates_data __initconst = {
-@@ -929,6 +984,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
- struct gates_data *data)
- {
- struct clk_onecell_data *clk_data;
-+ struct gates_reset_data *reset_data;
- const char *clk_parent;
- const char *clk_name;
- void *reg;
-@@ -972,6 +1028,21 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
- clk_data->clk_num = i;
-
- of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+ /* Register a reset controler for gates with reset bits */
-+ if (data->reset_mask == 0)
-+ return;
-+
-+ reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
-+ if (!reset_data)
-+ return;
-+
-+ reset_data->reg = reg;
-+ reset_data->lock = &clk_lock;
-+ reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
-+ reset_data->rcdev.ops = &sunxi_gates_reset_ops;
-+ reset_data->rcdev.of_node = node;
-+ reset_controller_register(&reset_data->rcdev);
- }
-
-
---
-1.8.5.5
-
+++ /dev/null
-From a6459be451bc7eb541aca2be3b36b06955d06622 Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Thu, 19 Sep 2013 21:59:32 +0200
-Subject: [PATCH] clk: sunxi: Add USB clock register defintions
-
-Add register definitions for the usb-clk register found on sun4i, sun5i and
-sun7i SoCs.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 5 +++++
- drivers/clk/sunxi/clk-sunxi.c | 12 ++++++++++++
- 2 files changed, 17 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
-index 0da774c..c77a5b8 100644
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 2dbaee7..9daa9b0 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -924,6 +924,16 @@ struct gates_data {
- .mask = {0x7F77FFF, 0x14FB3F},
- };
-
-+static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
-+ .mask = {0x1C0},
-+ .reset_mask = 0x07,
-+};
-+
-+static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
-+ .mask = {0x140},
-+ .reset_mask = 0x03,
-+};
-+
- static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
- .mask = {0x147667e7, 0x185915},
- };
-@@ -1271,6 +1281,8 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
- {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
- {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
- {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
-+ {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
-+ {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
- {}
- };
-
---
-1.8.5.5
-
+++ /dev/null
-From c3593cc95c240663bd9c191c1029237e467575af Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Fri, 7 Feb 2014 18:08:03 +0100
-Subject: [PATCH] ARM: sun4i: dt: Add sun4i-a10-usb-vbus-reg dts include file
-
-Almost all sun4i and sun7i boards have a gpio controlled vbus for usb1 and
-usb2, using gpio pin PH6 and PH3 as in the reference design. This commit adds
-an include file for this, avoiding the need to copy and paste the exact same
-dts code to almost all sun4i and sun7i dts files.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-usb-vbus-reg.dtsi | 54 +++++++++++++++++++++++++++
- 1 file changed, 54 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun4i-a10-usb-vbus-reg.dtsi
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-usb-vbus-reg.dtsi b/arch/arm/boot/dts/sun4i-a10-usb-vbus-reg.dtsi
-new file mode 100644
-index 0000000..803be0c
---- /dev/null
-+++ b/arch/arm/boot/dts/sun4i-a10-usb-vbus-reg.dtsi
-@@ -0,0 +1,54 @@
-+/*
-+ * sun4i boards usb vbus supply common code
-+ *
-+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/ {
-+ soc@01c00000 {
-+ pio: pinctrl@01c20800 {
-+ usb1_vbus_pin_a: usb1_vbus_pin@0 {
-+ allwinner,pins = "PH6";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ usb2_vbus_pin_a: usb2_vbus_pin@0 {
-+ allwinner,pins = "PH3";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+ };
-+ };
-+
-+ reg_usb1_vbus: usb1-vbus {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usb1_vbus_pin_a>;
-+ regulator-name = "usb1-vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ gpio = <&pio 7 6 0>;
-+ };
-+
-+ reg_usb2_vbus: usb2-vbus {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usb2_vbus_pin_a>;
-+ regulator-name = "usb2-vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ gpio = <&pio 7 3 0>;
-+ };
-+};
---
-1.8.5.5
-
+++ /dev/null
-From d11b47592e6af40fff595900c2af30774ee0b88e Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 9 Feb 2014 14:17:28 +0100
-Subject: [PATCH] ARM: sun5i: dt: Add sun5i-a1*-usb-vbus-reg dts include files
-
-Almost all sun5i-a10s boards have a gpio controlled vbus for usb1 using gpio
-pin PB10 as in the reference design. This commit adds an include file for this,
-avoiding the need to copy and paste the dts code.
-
-For sun5i-a13 based board the reference design uses a gpio on the pmic, which
-we don't support yet. Still for consistency with all the other dts files also
-add a sun5i-a13-usb-vbus-reg.dtsi files, without a gpio reference for now.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s-usb-vbus-reg.dtsi | 36 ++++++++++++++++++++++++++
- arch/arm/boot/dts/sun5i-a13-usb-vbus-reg.dtsi | 23 ++++++++++++++++
- 2 files changed, 59 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun5i-a10s-usb-vbus-reg.dtsi
- create mode 100644 arch/arm/boot/dts/sun5i-a13-usb-vbus-reg.dtsi
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s-usb-vbus-reg.dtsi b/arch/arm/boot/dts/sun5i-a10s-usb-vbus-reg.dtsi
-new file mode 100644
-index 0000000..bb1a693
---- /dev/null
-+++ b/arch/arm/boot/dts/sun5i-a10s-usb-vbus-reg.dtsi
-@@ -0,0 +1,36 @@
-+/*
-+ * sun5i a10s boards usb vbus supply common code
-+ *
-+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/ {
-+ soc@01c00000 {
-+ pio: pinctrl@01c20800 {
-+ usb1_vbus_pin_a: usb1_vbus_pin@0 {
-+ allwinner,pins = "PB10";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+ };
-+ };
-+
-+ reg_usb1_vbus: usb1-vbus {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usb1_vbus_pin_a>;
-+ regulator-name = "usb1-vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ gpio = <&pio 1 10 0>;
-+ };
-+};
-diff --git a/arch/arm/boot/dts/sun5i-a13-usb-vbus-reg.dtsi b/arch/arm/boot/dts/sun5i-a13-usb-vbus-reg.dtsi
-new file mode 100644
-index 0000000..4d70b9a
---- /dev/null
-+++ b/arch/arm/boot/dts/sun5i-a13-usb-vbus-reg.dtsi
-@@ -0,0 +1,23 @@
-+/*
-+ * sun5i a13 boards usb vbus supply common code
-+ *
-+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/ {
-+ reg_usb1_vbus: usb1-vbus {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ regulator-name = "usb1-vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ };
-+};
---
-1.8.5.5
-
+++ /dev/null
-From ac74dd1167924c412498a651edda63df49941f10 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 4 Jan 2014 23:56:17 +0100
-Subject: [PATCH] ARM: sunxi: Add driver for sunxi usb phy
-
-The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
-through a single set of registers. Besides this there are also some other
-phy related bits which need poking, which are per phy, but shared between the
-ohci and ehci controllers, so these are also controlled from this new phy
-driver.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../devicetree/bindings/phy/sun4i-usb-phy.txt | 26 ++
- drivers/phy/Kconfig | 11 +
- drivers/phy/Makefile | 1 +
- drivers/phy/phy-sun4i-usb.c | 329 +++++++++++++++++++++
- 4 files changed, 367 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
- create mode 100644 drivers/phy/phy-sun4i-usb.c
-
-diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
-new file mode 100644
-index 0000000..a82361b
---- /dev/null
-+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
-@@ -0,0 +1,26 @@
-+Allwinner sun4i USB PHY
-+-----------------------
-+
-+Required properties:
-+- compatible : should be one of "allwinner,sun4i-a10-usb-phy",
-+ "allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"
-+- reg : a list of offset + length pairs
-+- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"
-+- #phy-cells : from the generic phy bindings, must be 1
-+- clocks : phandle + clock specifier for the phy clock
-+- clock-names : "usb_phy"
-+- resets : a list of phandle + reset specifier pairs
-+- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset"
-+
-+Example:
-+ usbphy: phy@0x01c13400 {
-+ #phy-cells = <1>;
-+ compatible = "allwinner,sun4i-a10-usb-phy";
-+ /* phy base regs, phy1 pmu reg, phy2 pmu reg */
-+ reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
-+ reg-names = "phy_ctrl", "pmu1", "pmu2";
-+ clocks = <&usb_clk 8>;
-+ clock-names = "usb_phy";
-+ resets = <&usb_clk 1>, <&usb_clk 2>;
-+ reset-names = "usb1_reset", "usb2_reset";
-+ };
-diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
-index 4ef8755..6e336b4 100644
---- a/drivers/phy/Kconfig
-+++ b/drivers/phy/Kconfig
-@@ -64,4 +64,15 @@ config BCM_KONA_USB2_PHY
- help
- Enable this to support the Broadcom Kona USB 2.0 PHY.
-
-+config PHY_SUN4I_USB
-+ tristate "Allwinner sunxi SoC USB PHY driver"
-+ depends on ARCH_SUNXI
-+ select GENERIC_PHY
-+ help
-+ Enable this to support the transceiver that is part of Allwinner
-+ sunxi SoCs.
-+
-+ This driver controls the entire USB PHY block, both the USB OTG
-+ parts, as well as the 2 regular USB 2 host PHYs.
-+
- endmenu
-diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
-index b57c253..9d4f8bb 100644
---- a/drivers/phy/Makefile
-+++ b/drivers/phy/Makefile
-@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
- obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
- obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
- obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
-+obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o
-diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
-new file mode 100644
-index 0000000..31c4611
---- /dev/null
-+++ b/drivers/phy/phy-sun4i-usb.c
-@@ -0,0 +1,329 @@
-+/*
-+ * Allwinner sun4i USB phy driver
-+ *
-+ * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * Based on code from
-+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
-+ *
-+ * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
-+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
-+ * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+
-+#define REG_ISCR 0x00
-+#define REG_PHYCTL 0x04
-+#define REG_PHYBIST 0x08
-+#define REG_PHYTUNE 0x0c
-+
-+#define SUNXI_AHB_ICHR8_EN BIT(10)
-+#define SUNXI_AHB_INCR4_BURST_EN BIT(9)
-+#define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
-+#define SUNXI_ULPI_BYPASS_EN BIT(0)
-+
-+/* Common Control Bits for Both PHYs */
-+#define PHY_PLL_BW 0x03
-+#define PHY_RES45_CAL_EN 0x0c
-+
-+/* Private Control Bits for Each PHY */
-+#define PHY_TX_AMPLITUDE_TUNE 0x20
-+#define PHY_TX_SLEWRATE_TUNE 0x22
-+#define PHY_VBUSVALID_TH_SEL 0x25
-+#define PHY_PULLUP_RES_SEL 0x27
-+#define PHY_OTG_FUNC_EN 0x28
-+#define PHY_VBUS_DET_EN 0x29
-+#define PHY_DISCON_TH_SEL 0x2a
-+
-+#define MAX_PHYS 3
-+
-+struct sun4i_usb_phy_data {
-+ struct clk *clk;
-+ void __iomem *base;
-+ struct mutex mutex;
-+ int num_phys;
-+ u32 disc_thresh;
-+ struct sun4i_usb_phy {
-+ struct phy *phy;
-+ void __iomem *pmu;
-+ struct regulator *vbus;
-+ struct reset_control *reset;
-+ int index;
-+ } phys[MAX_PHYS];
-+};
-+
-+#define to_sun4i_usb_phy_data(phy) \
-+ container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
-+
-+static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
-+ int len)
-+{
-+ struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
-+ u32 temp, usbc_bit = BIT(phy->index * 2);
-+ int i;
-+
-+ mutex_lock(&phy_data->mutex);
-+
-+ for (i = 0; i < len; i++) {
-+ temp = readl(phy_data->base + REG_PHYCTL);
-+
-+ /* clear the address portion */
-+ temp &= ~(0xff << 8);
-+
-+ /* set the address */
-+ temp |= ((addr + i) << 8);
-+ writel(temp, phy_data->base + REG_PHYCTL);
-+
-+ /* set the data bit and clear usbc bit*/
-+ temp = readb(phy_data->base + REG_PHYCTL);
-+ if (data & 0x1)
-+ temp |= BIT(7);
-+ else
-+ temp &= ~BIT(7);
-+ temp &= ~usbc_bit;
-+ writeb(temp, phy_data->base + REG_PHYCTL);
-+
-+ /* pulse usbc_bit */
-+ temp = readb(phy_data->base + REG_PHYCTL);
-+ temp |= usbc_bit;
-+ writeb(temp, phy_data->base + REG_PHYCTL);
-+
-+ temp = readb(phy_data->base + REG_PHYCTL);
-+ temp &= ~usbc_bit;
-+ writeb(temp, phy_data->base + REG_PHYCTL);
-+
-+ data >>= 1;
-+ }
-+ mutex_unlock(&phy_data->mutex);
-+}
-+
-+static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
-+{
-+ u32 bits, reg_value;
-+
-+ if (!phy->pmu)
-+ return;
-+
-+ bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
-+ SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
-+
-+ reg_value = readl(phy->pmu);
-+
-+ if (enable)
-+ reg_value |= bits;
-+ else
-+ reg_value &= ~bits;
-+
-+ writel(reg_value, phy->pmu);
-+}
-+
-+static int sun4i_usb_phy_init(struct phy *_phy)
-+{
-+ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
-+ struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
-+ int ret;
-+
-+ ret = clk_prepare_enable(data->clk);
-+ if (ret)
-+ return ret;
-+
-+ ret = reset_control_deassert(phy->reset);
-+ if (ret) {
-+ clk_disable_unprepare(data->clk);
-+ return ret;
-+ }
-+
-+ /* Adjust PHY's magnitude and rate */
-+ sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
-+
-+ /* Disconnect threshold adjustment */
-+ sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
-+
-+ sun4i_usb_phy_passby(phy, 1);
-+
-+ return 0;
-+}
-+
-+static int sun4i_usb_phy_exit(struct phy *_phy)
-+{
-+ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
-+ struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
-+
-+ sun4i_usb_phy_passby(phy, 0);
-+ reset_control_assert(phy->reset);
-+ clk_disable_unprepare(data->clk);
-+
-+ return 0;
-+}
-+
-+static int sun4i_usb_phy_power_on(struct phy *_phy)
-+{
-+ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
-+ int ret = 0;
-+
-+ if (phy->vbus)
-+ ret = regulator_enable(phy->vbus);
-+
-+ return ret;
-+}
-+
-+static int sun4i_usb_phy_power_off(struct phy *_phy)
-+{
-+ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
-+
-+ if (phy->vbus)
-+ regulator_disable(phy->vbus);
-+
-+ return 0;
-+}
-+
-+static struct phy_ops sun4i_usb_phy_ops = {
-+ .init = sun4i_usb_phy_init,
-+ .exit = sun4i_usb_phy_exit,
-+ .power_on = sun4i_usb_phy_power_on,
-+ .power_off = sun4i_usb_phy_power_off,
-+ .owner = THIS_MODULE,
-+};
-+
-+static struct phy *sun4i_usb_phy_xlate(struct device *dev,
-+ struct of_phandle_args *args)
-+{
-+ struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
-+
-+ if (WARN_ON(args->args[0] == 0 || args->args[0] >= data->num_phys))
-+ return ERR_PTR(-ENODEV);
-+
-+ return data->phys[args->args[0]].phy;
-+}
-+
-+static int sun4i_usb_phy_probe(struct platform_device *pdev)
-+{
-+ struct sun4i_usb_phy_data *data;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *np = dev->of_node;
-+ void __iomem *pmu = NULL;
-+ struct phy_provider *phy_provider;
-+ struct reset_control *reset;
-+ struct regulator *vbus;
-+ struct resource *res;
-+ struct phy *phy;
-+ char name[16];
-+ int i;
-+
-+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-+ if (!data)
-+ return -ENOMEM;
-+
-+ mutex_init(&data->mutex);
-+
-+ if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy"))
-+ data->num_phys = 2;
-+ else
-+ data->num_phys = 3;
-+
-+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy"))
-+ data->disc_thresh = 3;
-+ else
-+ data->disc_thresh = 2;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
-+ data->base = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(data->base))
-+ return PTR_ERR(data->base);
-+
-+ data->clk = devm_clk_get(dev, "usb_phy");
-+ if (IS_ERR(data->clk)) {
-+ dev_err(dev, "could not get usb_phy clock\n");
-+ return PTR_ERR(data->clk);
-+ }
-+
-+ /* Skip 0, 0 is the phy for otg which is not yet supported. */
-+ for (i = 1; i < data->num_phys; i++) {
-+ snprintf(name, sizeof(name), "usb%d_vbus", i);
-+ vbus = devm_regulator_get_optional(dev, name);
-+ if (IS_ERR(vbus)) {
-+ if (PTR_ERR(vbus) == -EPROBE_DEFER)
-+ return -EPROBE_DEFER;
-+ vbus = NULL;
-+ }
-+
-+ snprintf(name, sizeof(name), "usb%d_reset", i);
-+ reset = devm_reset_control_get(dev, name);
-+ if (IS_ERR(reset)) {
-+ dev_err(dev, "failed to get reset %s\n", name);
-+ return PTR_ERR(phy);
-+ }
-+
-+ if (i) { /* No pmu for usbc0 */
-+ snprintf(name, sizeof(name), "pmu%d", i);
-+ res = platform_get_resource_byname(pdev,
-+ IORESOURCE_MEM, name);
-+ pmu = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(pmu))
-+ return PTR_ERR(pmu);
-+ }
-+
-+ phy = devm_phy_create(dev, &sun4i_usb_phy_ops, NULL);
-+ if (IS_ERR(phy)) {
-+ dev_err(dev, "failed to create PHY %d\n", i);
-+ return PTR_ERR(phy);
-+ }
-+
-+ data->phys[i].phy = phy;
-+ data->phys[i].pmu = pmu;
-+ data->phys[i].vbus = vbus;
-+ data->phys[i].reset = reset;
-+ data->phys[i].index = i;
-+ phy_set_drvdata(phy, &data->phys[i]);
-+ }
-+
-+ dev_set_drvdata(dev, data);
-+ phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
-+ if (IS_ERR(phy_provider))
-+ return PTR_ERR(phy_provider);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id sun4i_usb_phy_of_match[] = {
-+ { .compatible = "allwinner,sun4i-a10-usb-phy" },
-+ { .compatible = "allwinner,sun5i-a13-usb-phy" },
-+ { .compatible = "allwinner,sun7i-a20-usb-phy" },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
-+
-+static struct platform_driver sun4i_usb_phy_driver = {
-+ .probe = sun4i_usb_phy_probe,
-+ .driver = {
-+ .of_match_table = sun4i_usb_phy_of_match,
-+ .name = "sun4i-usb-phy",
-+ .owner = THIS_MODULE,
-+ }
-+};
-+module_platform_driver(sun4i_usb_phy_driver);
-+
-+MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
-+MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
-+MODULE_LICENSE("GPL v2");
---
-1.8.5.5
-
+++ /dev/null
-From a6ff9c88c09c81cb612f2588a5bfbde21bdcbf7b Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Thu, 19 Sep 2013 21:58:47 +0200
-Subject: [PATCH] ARM: sun4i: dt: Add bindings for USB clocks
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 1a9ab7e..7550c4e 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -307,6 +307,15 @@
- clock-output-names = "ir1";
- };
-
-+ usb_clk: clk@01c200cc {
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun4i-a10-usb-clk";
-+ reg = <0x01c200cc 0x4>;
-+ clocks = <&pll6 1>;
-+ clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
-+ };
-+
- spi3_clk: clk@01c200d4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-mod0-clk";
---
-1.8.5.5
-
+++ /dev/null
-From f1a981bd49f310775780c221fe92f6861c5e8f3f Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Wed, 18 Sep 2013 00:30:04 +0200
-Subject: [PATCH] ARM: sun4i: dt: Add USB host bindings
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 52 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 7550c4e..80bbdeb 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -391,6 +391,38 @@
- status = "disabled";
- };
-
-+ usbphy: phy@01c13400 {
-+ #phy-cells = <1>;
-+ compatible = "allwinner,sun4i-a10-usb-phy";
-+ reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
-+ reg-names = "phy_ctrl", "pmu1", "pmu2";
-+ clocks = <&usb_clk 8>;
-+ clock-names = "usb_phy";
-+ resets = <&usb_clk 1>, <&usb_clk 2>;
-+ reset-names = "usb1_reset", "usb2_reset";
-+ status = "disabled";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
-+ reg = <0x01c14000 0x100>;
-+ interrupts = <39>;
-+ clocks = <&ahb_gates 1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
-+ reg = <0x01c14400 0x100>;
-+ interrupts = <64>;
-+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- ahci: sata@01c18000 {
- compatible = "allwinner,sun4i-a10-ahci";
- reg = <0x01c18000 0x1000>;
-@@ -399,6 +431,26 @@
- status = "disabled";
- };
-
-+ ehci1: usb@01c1c000 {
-+ compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
-+ reg = <0x01c1c000 0x100>;
-+ interrupts = <40>;
-+ clocks = <&ahb_gates 3>;
-+ phys = <&usbphy 2>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
-+ reg = <0x01c1c400 0x100>;
-+ interrupts = <65>;
-+ clocks = <&usb_clk 7>, <&ahb_gates 4>;
-+ phys = <&usbphy 2>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From d2afb2629087ab17d87d605d4b7f49da3a85f1b1 Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Wed, 18 Sep 2013 22:45:06 +0200
-Subject: [PATCH] ARM: sun4i: dt: Add USB host nodes to cubieboard dts
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-index ef85b8e..57d2c9c 100644
---- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-@@ -13,6 +13,7 @@
- /dts-v1/;
- /include/ "sun4i-a10.dtsi"
- /include/ "sunxi-ahci-reg.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-
- / {
- model = "Cubietech Cubieboard";
-@@ -42,11 +43,33 @@
- status = "okay";
- };
-
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
- };
-
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- led_pins_cubieboard: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
---
-1.8.5.5
-
+++ /dev/null
-From dee94e49177c0bac675d543b16de0f354b0f476a Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Wed, 18 Sep 2013 00:30:40 +0200
-Subject: [PATCH] ARM: sun4i: dt: Add USB host nodes to Mele A1000 dts
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-a1000.dts | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-index 4b2a694..144b8e6 100644
---- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-@@ -13,6 +13,7 @@
-
- /dts-v1/;
- /include/ "sun4i-a10.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-
- / {
- model = "Mele A1000";
-@@ -43,10 +44,32 @@
- status = "okay";
- };
-
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- status = "okay";
- };
-
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- emac_power_pin_a1000: emac_power_pin@0 {
- allwinner,pins = "PH15";
---
-1.8.5.5
-
+++ /dev/null
-From ebac8eac9b49c914a975c04a62ea5cfc058d958d Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Thu, 19 Sep 2013 21:24:20 +0200
-Subject: [PATCH] ARM: sun7i: dt: Add bindings for USB clocks
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index b58ce25..ed9b8cc 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -297,6 +297,15 @@
- clock-output-names = "ir1";
- };
-
-+ usb_clk: clk@01c200cc {
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun4i-a10-usb-clk";
-+ reg = <0x01c200cc 0x4>;
-+ clocks = <&pll6 1>;
-+ clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
-+ };
-+
- spi3_clk: clk@01c200d4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-mod0-clk";
---
-1.8.5.5
-
+++ /dev/null
-From bc68c927139d1cac9647c8bcd3e8cea1cac9eaef Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Thu, 19 Sep 2013 21:36:10 +0200
-Subject: [PATCH] ARM: sun7i: dt: Add USB host bindings
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 52 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index ed9b8cc..bdfa594 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -453,6 +453,38 @@
- status = "disabled";
- };
-
-+ usbphy: phy@01c13400 {
-+ #phy-cells = <1>;
-+ compatible = "allwinner,sun7i-a20-usb-phy";
-+ reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
-+ reg-names = "phy_ctrl", "pmu1", "pmu2";
-+ clocks = <&usb_clk 8>;
-+ clock-names = "usb_phy";
-+ resets = <&usb_clk 1>, <&usb_clk 2>;
-+ reset-names = "usb1_reset", "usb2_reset";
-+ status = "disabled";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
-+ reg = <0x01c14000 0x100>;
-+ interrupts = <0 39 4>;
-+ clocks = <&ahb_gates 1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
-+ reg = <0x01c14400 0x100>;
-+ interrupts = <0 64 4>;
-+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- ahci: sata@01c18000 {
- compatible = "allwinner,sun4i-a10-ahci";
- reg = <0x01c18000 0x1000>;
-@@ -461,6 +493,26 @@
- status = "disabled";
- };
-
-+ ehci1: usb@01c1c000 {
-+ compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
-+ reg = <0x01c1c000 0x100>;
-+ interrupts = <0 40 4>;
-+ clocks = <&ahb_gates 3>;
-+ phys = <&usbphy 2>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
-+ reg = <0x01c1c400 0x100>;
-+ interrupts = <0 65 4>;
-+ clocks = <&usb_clk 7>, <&ahb_gates 4>;
-+ phys = <&usbphy 2>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- pio: pinctrl@01c20800 {
- compatible = "allwinner,sun7i-a20-pinctrl";
- reg = <0x01c20800 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From 5b820d3062a436cf36ddf2fecc88524b9adf7b6e Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Thu, 19 Sep 2013 21:29:45 +0200
-Subject: [PATCH] ARM: sun7i: dt: Add USB host nodes to cubieboard2 dts
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-index a8186f5..9fa1d85 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-@@ -14,6 +14,7 @@
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
- /include/ "sunxi-ahci-reg.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-
- / {
- model = "Cubietech Cubieboard2";
-@@ -28,11 +29,33 @@
- status = "okay";
- };
-
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
- };
-
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- led_pins_cubieboard2: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
---
-1.8.5.5
-
+++ /dev/null
-From 2f2ffd5ea0174434c8214722127e5e977dcecf32 Mon Sep 17 00:00:00 2001
-From: Zalan Blenessy <zalan.blenessy@gmail.com>
-Date: Sun, 22 Dec 2013 17:08:10 +0100
-Subject: [PATCH] ARM: sun7i: dt: Add USB host nodes to a20-olinuxino-micro dts
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-index aef289f..824ce0a 100644
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -14,6 +14,7 @@
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
- /include/ "sunxi-ahci-reg.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
- #include <dt-bindings/input/input.h>
-
- / {
-@@ -37,11 +38,33 @@
- status = "okay";
- };
-
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
- };
-
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
- allwinner,pins = "PH11";
---
-1.8.5.5
-
+++ /dev/null
-diff -ruN old/arch/arm/boot/dts/sun7i-a20-cubietruck.dts new/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
---- old/arch/arm/boot/dts/sun7i-a20-cubietruck.dts 2014-03-18 10:08:24.000000000 +0100
-+++ new/arch/arm/boot/dts/sun7i-a20-cubietruck.dts 2014-03-18 10:27:25.142067751 +0100
-@@ -14,12 +14,35 @@
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
- /include/ "sunxi-ahci-reg.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-
- / {
- model = "Cubietech Cubietruck";
- compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
- mmc0: mmc@01c0f000 {
- pinctrl-names = "default", "default";
- pinctrl-0 = <&mmc0_pins_a>;
+++ /dev/null
-From 84e5402d6755b0563cfbe1b6b930b13b1c10d56c Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Tue, 24 Sep 2013 20:02:39 +0200
-Subject: [PATCH] ARM: sun5i: dt: Add bindings for USB clocks
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 9 +++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 9 +++++++++
- 2 files changed, 18 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 95cb245..0565040 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -268,6 +268,15 @@
- clock-output-names = "ir0";
- };
-
-+ usb_clk: clk@01c200cc {
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun5i-a13-usb-clk";
-+ reg = <0x01c200cc 0x4>;
-+ clocks = <&pll6 1>;
-+ clock-output-names = "usb_ohci0", "usb_phy";
-+ };
-+
- mbus_clk: clk@01c2015c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-mod0-clk";
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index bae0f5f..785dea5 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -266,6 +266,15 @@
- clock-output-names = "ir0";
- };
-
-+ usb_clk: clk@01c200cc {
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun5i-a13-usb-clk";
-+ reg = <0x01c200cc 0x4>;
-+ clocks = <&pll6 1>;
-+ clock-output-names = "usb_ohci0", "usb_phy";
-+ };
-+
- mbus_clk: clk@01c2015c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-mod0-clk";
---
-1.8.5.5
-
+++ /dev/null
-From 22f661c548042565ffa32e468267f94cadafe144 Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Tue, 24 Sep 2013 20:03:40 +0200
-Subject: [PATCH] ARM: sun5i: dt: Add USB host bindings
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 32 ++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 32 ++++++++++++++++++++++++++++++++
- 2 files changed, 64 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 0565040..a5431ed 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -341,6 +341,38 @@
- status = "disabled";
- };
-
-+ usbphy: phy@01c13400 {
-+ #phy-cells = <1>;
-+ compatible = "allwinner,sun5i-a13-usb-phy";
-+ reg = <0x01c13400 0x10 0x01c14800 0x4>;
-+ reg-names = "phy_ctrl", "pmu1";
-+ clocks = <&usb_clk 8>;
-+ clock-names = "usb_phy";
-+ resets = <&usb_clk 1>;
-+ reset-names = "usb1_reset";
-+ status = "disabled";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
-+ reg = <0x01c14000 0x100>;
-+ interrupts = <39>;
-+ clocks = <&ahb_gates 1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
-+ reg = <0x01c14400 0x100>;
-+ interrupts = <40>;
-+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 785dea5..7fe9cdc 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -312,6 +312,38 @@
- status = "disabled";
- };
-
-+ usbphy: phy@01c13400 {
-+ #phy-cells = <1>;
-+ compatible = "allwinner,sun5i-a13-usb-phy";
-+ reg = <0x01c13400 0x10 0x01c14800 0x4>;
-+ reg-names = "phy_ctrl", "pmu1";
-+ clocks = <&usb_clk 8>;
-+ clock-names = "usb_phy";
-+ resets = <&usb_clk 1>;
-+ reset-names = "usb1_reset";
-+ status = "disabled";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
-+ reg = <0x01c14000 0x100>;
-+ interrupts = <39>;
-+ clocks = <&ahb_gates 1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
-+ reg = <0x01c14400 0x100>;
-+ interrupts = <40>;
-+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From 8bf60620f751f93157c81038527b03716c8aeede Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Tue, 24 Sep 2013 20:07:53 +0200
-Subject: [PATCH] ARM: sun5i: dt: Add USB host nodes to A13-Olinuxino
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-index ba32a41..39556d1 100644
---- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-@@ -13,6 +13,7 @@
-
- /dts-v1/;
- /include/ "sun5i-a13.dtsi"
-+/include/ "sun5i-a13-usb-vbus-reg.dtsi"
- #include <dt-bindings/input/input.h>
-
- / {
-@@ -28,6 +29,19 @@
- status = "okay";
- };
-
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
- allwinner,pins = "PG0";
-@@ -42,6 +56,13 @@
- allwinner,drive = <1>;
- allwinner,pull = <0>;
- };
-+
-+ usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 {
-+ allwinner,pins = "PG11";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- lradc: lradc@01c22800 {
-@@ -86,4 +107,9 @@
- default-state = "on";
- };
- };
-+
-+ reg_usb1_vbus: usb1-vbus {
-+ pinctrl-0 = <&usb1_vbus_pin_olinuxino>;
-+ gpio = <&pio 6 11 0>;
-+ };
- };
---
-1.8.5.5
-
+++ /dev/null
-From d46cebc1431948638fe4e6cfd27fb9da48e6c593 Mon Sep 17 00:00:00 2001
-From: Zalan Blenessy <zalan.blenessy@gmail.com>
-Date: Sun, 22 Dec 2013 17:10:06 +0100
-Subject: [PATCH] ARM: sunxi: select ARM_PSCI
-
-This is necessary for SMP on sun7i.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/mach-sunxi/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/mach-sunxi/Kconfig
-+++ b/arch/arm/mach-sunxi/Kconfig
-@@ -3,6 +3,7 @@ config ARCH_SUNXI
- select ARCH_HAS_RESET_CONTROLLER
- select ARCH_REQUIRE_GPIOLIB
- select ARM_GIC
-+ select ARM_PSCI
- select CLKSRC_MMIO
- select CLKSRC_OF
- select COMMON_CLK
+++ /dev/null
-From 99489f45debd07f6e1cfa36f5c9890409714518d Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Fri, 20 Dec 2013 22:41:08 +0100
-Subject: [PATCH] clocksource: sun5i: Add support for reset controller
-
-The Allwinner A31 that uses this timer has the timer IP asserted in reset.
-Add an optional reset property to the DT, and deassert the timer from reset if
-it's there.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- .../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt | 4 ++++
- drivers/clocksource/timer-sun5i.c | 6 ++++++
- 2 files changed, 10 insertions(+)
-
---- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
-+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
-@@ -9,6 +9,9 @@ Required properties:
- one)
- - clocks: phandle to the source clock (usually the AHB clock)
-
-+Optionnal properties:
-+- resets: phandle to a reset controller asserting the timer
-+
- Example:
-
- timer@01c60000 {
-@@ -19,4 +22,5 @@ timer@01c60000 {
- <0 53 1>,
- <0 54 1>;
- clocks = <&ahb1_gates 19>;
-+ resets = <&ahb1rst 19>;
- };
---- a/drivers/clocksource/timer-sun5i.c
-+++ b/drivers/clocksource/timer-sun5i.c
-@@ -16,6 +16,7 @@
- #include <linux/interrupt.h>
- #include <linux/irq.h>
- #include <linux/irqreturn.h>
-+#include <linux/reset.h>
- #include <linux/sched_clock.h>
- #include <linux/of.h>
- #include <linux/of_address.h>
-@@ -143,6 +144,7 @@ static u32 sun5i_timer_sched_read(void)
-
- static void __init sun5i_timer_init(struct device_node *node)
- {
-+ struct reset_control *rstc;
- unsigned long rate;
- struct clk *clk;
- int ret, irq;
-@@ -162,6 +164,10 @@ static void __init sun5i_timer_init(stru
- clk_prepare_enable(clk);
- rate = clk_get_rate(clk);
-
-+ rstc = of_reset_control_get(node, NULL);
-+ if (!IS_ERR(rstc))
-+ reset_control_deassert(rstc);
-+
- writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
- writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
- timer_base + TIMER_CTL_REG(1));
+++ /dev/null
-From 0325b48d6149e131c90ed6ec77458f4d2df73898 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Fri, 20 Dec 2013 22:41:07 +0100
-Subject: [PATCH] reset: Add of_reset_control_get
-
-In some cases, you might need to deassert from reset an hardware block that
-doesn't associated to a struct device (CPUs, timers, etc.).
-
-Add a small helper to retrieve the reset controller from the device tree
-without the need to pass a struct device.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/reset/core.c | 39 ++++++++++++++++++++++++++++++---------
- include/linux/reset.h | 4 ++++
- 2 files changed, 34 insertions(+), 9 deletions(-)
-
---- a/drivers/reset/core.c
-+++ b/drivers/reset/core.c
-@@ -127,15 +127,16 @@ int reset_control_deassert(struct reset_
- EXPORT_SYMBOL_GPL(reset_control_deassert);
-
- /**
-- * reset_control_get - Lookup and obtain a reference to a reset controller.
-- * @dev: device to be reset by the controller
-+ * of_reset_control_get - Lookup and obtain a reference to a reset controller.
-+ * @node: device to be reset by the controller
- * @id: reset line name
- *
- * Returns a struct reset_control or IS_ERR() condition containing errno.
- *
- * Use of id names is optional.
- */
--struct reset_control *reset_control_get(struct device *dev, const char *id)
-+struct reset_control *of_reset_control_get(struct device_node *node,
-+ const char *id)
- {
- struct reset_control *rstc = ERR_PTR(-EPROBE_DEFER);
- struct reset_controller_dev *r, *rcdev;
-@@ -144,13 +145,10 @@ struct reset_control *reset_control_get(
- int rstc_id;
- int ret;
-
-- if (!dev)
-- return ERR_PTR(-EINVAL);
--
- if (id)
-- index = of_property_match_string(dev->of_node,
-+ index = of_property_match_string(node,
- "reset-names", id);
-- ret = of_parse_phandle_with_args(dev->of_node, "resets", "#reset-cells",
-+ ret = of_parse_phandle_with_args(node, "resets", "#reset-cells",
- index, &args);
- if (ret)
- return ERR_PTR(ret);
-@@ -185,12 +183,35 @@ struct reset_control *reset_control_get(
- return ERR_PTR(-ENOMEM);
- }
-
-- rstc->dev = dev;
- rstc->rcdev = rcdev;
- rstc->id = rstc_id;
-
- return rstc;
- }
-+EXPORT_SYMBOL_GPL(of_reset_control_get);
-+
-+/**
-+ * reset_control_get - Lookup and obtain a reference to a reset controller.
-+ * @dev: device to be reset by the controller
-+ * @id: reset line name
-+ *
-+ * Returns a struct reset_control or IS_ERR() condition containing errno.
-+ *
-+ * Use of id names is optional.
-+ */
-+struct reset_control *reset_control_get(struct device *dev, const char *id)
-+{
-+ struct reset_control *rstc;
-+
-+ if (!dev)
-+ return ERR_PTR(-EINVAL);
-+
-+ rstc = of_reset_control_get(dev->of_node, id);
-+ if (!IS_ERR(rstc))
-+ rstc->dev = dev;
-+
-+ return rstc;
-+}
- EXPORT_SYMBOL_GPL(reset_control_get);
-
- /**
---- a/include/linux/reset.h
-+++ b/include/linux/reset.h
-@@ -1,6 +1,8 @@
- #ifndef _LINUX_RESET_H_
- #define _LINUX_RESET_H_
-
-+#include <linux/of.h>
-+
- struct device;
- struct reset_control;
-
-@@ -8,6 +10,8 @@ int reset_control_reset(struct reset_con
- int reset_control_assert(struct reset_control *rstc);
- int reset_control_deassert(struct reset_control *rstc);
-
-+struct reset_control *of_reset_control_get(struct device_node *node,
-+ const char *id);
- struct reset_control *reset_control_get(struct device *dev, const char *id);
- void reset_control_put(struct reset_control *rstc);
- struct reset_control *devm_reset_control_get(struct device *dev, const char *id);
+++ /dev/null
-From a1c859ab115c043662c2779d2e965bb09a90b8cb Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 17 Dec 2013 23:57:24 +0100
-Subject: [PATCH] ARM: sunxi-clock-reset: rename compat property
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 4 ++--
- drivers/reset/reset-sunxi.c | 2 +-
- 2 files changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -220,13 +220,13 @@
-
- apb1_rst: reset@01c202d0 {
- #reset-cells = <1>;
-- compatible = "allwinner,sun6i-a31-clock-reset";
-+ compatible = "allwinner,sun4i-clock-reset";
- reg = <0x01c202d0 0x4>;
- };
-
- apb2_rst: reset@01c202d8 {
- #reset-cells = <1>;
-- compatible = "allwinner,sun6i-a31-clock-reset";
-+ compatible = "allwinner,sun4i-clock-reset";
- reg = <0x01c202d8 0x4>;
- };
-
---- a/drivers/reset/reset-sunxi.c
-+++ b/drivers/reset/reset-sunxi.c
-@@ -138,7 +138,7 @@ void __init sun6i_reset_init(void)
- * device model.
- */
- static const struct of_device_id sunxi_reset_dt_ids[] = {
-- { .compatible = "allwinner,sun6i-a31-clock-reset", },
-+ { .compatible = "allwinner,sun4i-clock-reset", },
- { /* sentinel */ },
- };
- MODULE_DEVICE_TABLE(of, sunxi_reset_dt_ids);
+++ /dev/null
-From 5ca9eadcb5f5cd9af6f1650029ad64052a1a0b10 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Tue, 24 Dec 2013 21:26:17 +0800
-Subject: [PATCH] clk: sunxi: Allwinner A20 output clock support
-
-This patch adds support for the external clock outputs on the
-Allwinner A20 SoC. The clock outputs are similar to "module 0"
-type clocks, with different offsets and widths for clock factors.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
- drivers/clk/sunxi/clk-sunxi.c | 57 +++++++++++++++++++++++
- 2 files changed, 58 insertions(+)
-
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -37,6 +37,7 @@ Required properties:
- "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
- "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
- "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
-+ "allwinner,sun7i-a20-out-clk" - for the external output clocks
-
- Required properties for all clocks:
- - reg : shall be the control register address for the clock.
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -396,6 +396,47 @@ void clk_sunxi_mmc_phase_control(struct
-
-
- /**
-+ * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
-+ * CLK_OUT rate is calculated as follows
-+ * rate = (parent_rate >> p) / (m + 1);
-+ */
-+
-+static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
-+ u8 *n, u8 *k, u8 *m, u8 *p)
-+{
-+ u8 div, calcm, calcp;
-+
-+ /* These clocks can only divide, so we will never be able to achieve
-+ * frequencies higher than the parent frequency */
-+ if (*freq > parent_rate)
-+ *freq = parent_rate;
-+
-+ div = parent_rate / *freq;
-+
-+ if (div < 32)
-+ calcp = 0;
-+ else if (div / 2 < 32)
-+ calcp = 1;
-+ else if (div / 4 < 32)
-+ calcp = 2;
-+ else
-+ calcp = 3;
-+
-+ calcm = DIV_ROUND_UP(div, 1 << calcp);
-+
-+ *freq = (parent_rate >> calcp) / calcm;
-+
-+ /* we were called to round the frequency, we can now return */
-+ if (n == NULL)
-+ return;
-+
-+ *m = calcm - 1;
-+ *p = calcp;
-+}
-+
-+
-+
-+/**
- * sunxi_factors_clk_setup() - Setup function for factor clocks
- */
-
-@@ -455,6 +496,14 @@ static struct clk_factors_config sun4i_m
- .pwidth = 2,
- };
-
-+/* user manual says "n" but it's really "p" */
-+static struct clk_factors_config sun7i_a20_out_config = {
-+ .mshift = 8,
-+ .mwidth = 5,
-+ .pshift = 20,
-+ .pwidth = 2,
-+};
-+
- static const struct factors_data sun4i_pll1_data __initconst = {
- .enable = 31,
- .table = &sun4i_pll1_config,
-@@ -491,6 +540,13 @@ static const struct factors_data sun4i_m
- .getter = sun4i_get_mod0_factors,
- };
-
-+static const struct factors_data sun7i_a20_out_data __initconst = {
-+ .enable = 31,
-+ .mux = 24,
-+ .table = &sun7i_a20_out_config,
-+ .getter = sun7i_a20_get_out_factors,
-+};
-+
- static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
- const struct factors_data *data)
- {
-@@ -998,6 +1054,7 @@ static const struct of_device_id clk_fac
- {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
- {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
- {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
-+ {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
- {}
- };
-
+++ /dev/null
-From 271a35ef6237c3b775aad357969dc75ae5b56988 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Tue, 24 Dec 2013 21:26:19 +0800
-Subject: [PATCH] pinctrl: sunxi: Add Allwinner A20 clock output pin functions
-
-This patch adds the clock output pin functions on the A20.
-The 2 pins can output a configurable clock to be used by
-external modules. This is used on the CubieTruck, to supply
-a 32768 Hz low power clock to the onboard Wifi+BT module.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- drivers/pinctrl/pinctrl-sunxi-pins.h | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/pinctrl/pinctrl-sunxi-pins.h
-+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
-@@ -3774,12 +3774,14 @@ static const struct sunxi_desc_pin sun7i
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
- SUNXI_FUNCTION(0x3, "uart6"), /* TX */
-+ SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
- SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
- SUNXI_FUNCTION(0x3, "uart6"), /* RX */
-+ SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
- SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
- SUNXI_FUNCTION(0x0, "gpio_in"),
+++ /dev/null
-From f3a50c26f33a4627e5d3e35f80db3f22a5375237 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Tue, 24 Dec 2013 21:26:20 +0800
-Subject: [PATCH] ARM: dts: sun7i: Add pin muxing options for clock outputs
-
-This patch adds the clock output pin options on the A20.
-The 2 pins can output a configurable clock to be used by
-external modules. This is used on the CubieTruck, to supply
-a 32768 Hz low power clock to the onboard Wifi+BT module.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -490,6 +490,20 @@
- allwinner,drive = <3>;
- allwinner,pull = <0>;
- };
-+
-+ clk_out_a_pins: clk_out_a@0 {
-+ allwinner,pins = "PI12";
-+ allwinner,function = "clk_out_a";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ clk_out_b_pins: clk_out_b@0 {
-+ allwinner,pins = "PI13";
-+ allwinner,function = "clk_out_b";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- sata: ahci@01c18000 {
+++ /dev/null
-From 10b302a297aee952949423aaec0749b757f34950 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 17 Nov 2013 10:03:04 +0100
-Subject: [PATCH] ARM: sun4i: dt: Move the aliases to the DTSI
-
-The aliases are shared across boards are really belong to the DTSI.
-Move them there.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10-a1000.dts | 4 ----
- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 5 -----
- arch/arm/boot/dts/sun4i-a10.dtsi | 2 ++
- 3 files changed, 2 insertions(+), 9 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-index eb4d73b..d4b081d 100644
---- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-@@ -18,10 +18,6 @@
- model = "Mele A1000";
- compatible = "mele,a1000", "allwinner,sun4i-a10";
-
-- aliases {
-- serial0 = &uart0;
-- };
--
- soc@01c00000 {
- emac: ethernet@01c0b000 {
- pinctrl-names = "default";
-diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-index 425a7db..f1c77e0 100644
---- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-@@ -17,11 +17,6 @@
- model = "Cubietech Cubieboard";
- compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10";
-
-- aliases {
-- serial0 = &uart0;
-- serial1 = &uart1;
-- };
--
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- };
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 3ba2b46..0adbbe3 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -17,6 +17,8 @@
-
- aliases {
- ethernet0 = &emac;
-+ serial0 = &uart0;
-+ serial1 = &uart1;
- };
-
- cpus {
---
-1.8.5.5
-
+++ /dev/null
-From 4dae1686782d52084893421b89ff1aa61e223aaf Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 2 Feb 2014 14:49:11 +0100
-Subject: [PATCH] net: ethernet: sunxi: Add new compatibles
-
-The Allwinner A10 compatibles were following a slightly different compatible
-patterns than the rest of the SoCs for historical reasons. Add compatibles
-matching the other pattern to the ethernet driver for consistency, and keep the
-older one for backward compatibility.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt | 5 +++--
- drivers/net/ethernet/allwinner/sun4i-emac.c | 3 +++
- 2 files changed, 6 insertions(+), 2 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
-index b90bfcd..863d5b81 100644
---- a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
-+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
-@@ -1,7 +1,8 @@
- * Allwinner EMAC ethernet controller
-
- Required properties:
--- compatible: should be "allwinner,sun4i-emac".
-+- compatible: should be "allwinner,sun4i-a10-emac" (Deprecated:
-+ "allwinner,sun4i-emac")
- - reg: address and length of the register set for the device.
- - interrupts: interrupt for the device
- - phy: A phandle to a phy node defining the PHY address (as the reg
-@@ -14,7 +15,7 @@ Optional properties:
- Example:
-
- emac: ethernet@01c0b000 {
-- compatible = "allwinner,sun4i-emac";
-+ compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <55>;
- clocks = <&ahb_gates 17>;
-diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.c b/drivers/net/ethernet/allwinner/sun4i-emac.c
-index 0cc2143..511f6ee 100644
---- a/drivers/net/ethernet/allwinner/sun4i-emac.c
-+++ b/drivers/net/ethernet/allwinner/sun4i-emac.c
-@@ -929,6 +929,9 @@ static int emac_resume(struct platform_device *dev)
- }
-
- static const struct of_device_id emac_of_match[] = {
-+ {.compatible = "allwinner,sun4i-a10-emac",},
-+
-+ /* Deprecated */
- {.compatible = "allwinner,sun4i-emac",},
- {},
- };
---
-1.8.5.5
-
+++ /dev/null
-From efe205704fa8435b7bca495138dd2dbd973e0c28 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 2 Feb 2014 14:49:12 +0100
-Subject: [PATCH] net: phy: sunxi: Add new compatibles
-
-The Allwinner A10 compatibles were following a slightly different compatible
-patterns than the rest of the SoCs for historical reasons. Add compatibles
-matching the other pattern to the mdio driver for consistency, and keep the
-older one for backward compatibility.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt | 5 +++--
- drivers/net/phy/mdio-sun4i.c | 3 +++
- 2 files changed, 6 insertions(+), 2 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
-index 00b9f9a..4ec5641 100644
---- a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
-+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
-@@ -1,7 +1,8 @@
- * Allwinner A10 MDIO Ethernet Controller interface
-
- Required properties:
--- compatible: should be "allwinner,sun4i-mdio".
-+- compatible: should be "allwinner,sun4i-a10-mdio"
-+ (Deprecated: "allwinner,sun4i-mdio").
- - reg: address and length of the register set for the device.
-
- Optional properties:
-@@ -9,7 +10,7 @@ Optional properties:
-
- Example at the SoC level:
- mdio@01c0b080 {
-- compatible = "allwinner,sun4i-mdio";
-+ compatible = "allwinner,sun4i-a10-mdio";
- reg = <0x01c0b080 0x14>;
- #address-cells = <1>;
- #size-cells = <0>;
-diff --git a/drivers/net/phy/mdio-sun4i.c b/drivers/net/phy/mdio-sun4i.c
-index bb88bc7..9367acc 100644
---- a/drivers/net/phy/mdio-sun4i.c
-+++ b/drivers/net/phy/mdio-sun4i.c
-@@ -170,6 +170,9 @@ static int sun4i_mdio_remove(struct platform_device *pdev)
- }
-
- static const struct of_device_id sun4i_mdio_dt_ids[] = {
-+ { .compatible = "allwinner,sun4i-a10-mdio" },
-+
-+ /* Deprecated */
- { .compatible = "allwinner,sun4i-mdio" },
- { }
- };
---
-1.8.5.5
-
+++ /dev/null
-From 1c70e099ac80ee779ffac66a6169ad936425fe41 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 2 Feb 2014 14:49:13 +0100
-Subject: [PATCH] ARM: sunxi: dt: Convert to the new net compatibles
-
-Switch the device tree to the new compatibles introduced in the ethernet and
-mdio drivers to have a common pattern accross all Allwinner SoCs.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 4 ++--
- arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++--
- arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++--
- 3 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 040bb0e..10666ca 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -315,7 +315,7 @@
- ranges;
-
- emac: ethernet@01c0b000 {
-- compatible = "allwinner,sun4i-emac";
-+ compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <55>;
- clocks = <&ahb_gates 17>;
-@@ -323,7 +323,7 @@
- };
-
- mdio@01c0b080 {
-- compatible = "allwinner,sun4i-mdio";
-+ compatible = "allwinner,sun4i-a10-mdio";
- reg = <0x01c0b080 0x14>;
- status = "disabled";
- #address-cells = <1>;
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index ea16054..6496159 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -278,7 +278,7 @@
- ranges;
-
- emac: ethernet@01c0b000 {
-- compatible = "allwinner,sun4i-emac";
-+ compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <55>;
- clocks = <&ahb_gates 17>;
-@@ -286,7 +286,7 @@
- };
-
- mdio@01c0b080 {
-- compatible = "allwinner,sun4i-mdio";
-+ compatible = "allwinner,sun4i-a10-mdio";
- reg = <0x01c0b080 0x14>;
- status = "disabled";
- #address-cells = <1>;
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 119f066..9ff0948 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -340,7 +340,7 @@
- ranges;
-
- emac: ethernet@01c0b000 {
-- compatible = "allwinner,sun4i-emac";
-+ compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <0 55 4>;
- clocks = <&ahb_gates 17>;
-@@ -348,7 +348,7 @@
- };
-
- mdio@01c0b080 {
-- compatible = "allwinner,sun4i-mdio";
-+ compatible = "allwinner,sun4i-a10-mdio";
- reg = <0x01c0b080 0x14>;
- status = "disabled";
- #address-cells = <1>;
---
-1.8.5.5
-
+++ /dev/null
-From 791f631bb8f3feb10871b82015a25a7f40ce68e7 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 2 Jan 2014 22:05:04 +0100
-Subject: [PATCH] ARM: sun4i: a10: Add missing serial aliases
-
-Some UART aliases have been defined, but not all of them. Add the remaining
-ones to be consistent and to ease the parsing of the DT by the bootloaders.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 10666ca..d9c097c 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -19,6 +19,12 @@
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
-+ serial2 = &uart2;
-+ serial3 = &uart3;
-+ serial4 = &uart4;
-+ serial5 = &uart5;
-+ serial6 = &uart6;
-+ serial7 = &uart7;
- };
-
- cpus {
---
-1.8.5.5
-
+++ /dev/null
-From 64c3866d232e6b29862f4773ea97b16f4dad6950 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 2 Jan 2014 22:05:04 +0100
-Subject: [PATCH] ARM: sun5i: a10s: Add missing serial aliases
-
-Some UART aliases have been defined, but not all of them. Add the remaining
-ones to be consistent and to ease the parsing of the DT by the bootloaders.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 6496159..e00f292 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -18,6 +18,10 @@
-
- aliases {
- ethernet0 = &emac;
-+ serial0 = &uart0;
-+ serial1 = &uart1;
-+ serial2 = &uart2;
-+ serial3 = &uart3;
- };
-
- cpus {
---
-1.8.5.5
-
+++ /dev/null
-From 0cc774ef2524ec54e9d2db8771ba3739cb8ebc99 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Mon, 13 Jan 2014 11:08:47 +0100
-Subject: [PATCH] ARM: sun5i: a13: Add missing serial aliases
-
-Some UART aliases have been defined, but not all of them. Add the remaining
-ones to be consistent and to ease the parsing of the DT by the bootloaders.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a13.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 320335a..6de40b6 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -16,6 +16,11 @@
- / {
- interrupt-parent = <&intc>;
-
-+ aliases {
-+ serial0 = &uart1;
-+ serial1 = &uart3;
-+ };
-+
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
---
-1.8.5.5
-
+++ /dev/null
-From 27fb9d199aa3d2f89b4d0b1930062bb1a5a69a57 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 2 Jan 2014 22:05:04 +0100
-Subject: [PATCH] ARM: sun6i: Add missing serial aliases
-
-Some UART aliases have been defined, but not all of them. Add the remaining
-ones to be consistent and to ease the parsing of the DT by the bootloaders.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
-index 5256ad9..092bf97 100644
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -16,6 +16,16 @@
- / {
- interrupt-parent = <&gic>;
-
-+ aliases {
-+ serial0 = &uart0;
-+ serial1 = &uart1;
-+ serial2 = &uart2;
-+ serial3 = &uart3;
-+ serial4 = &uart4;
-+ serial5 = &uart5;
-+ };
-+
-+
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
---
-1.8.5.5
-
+++ /dev/null
-From 4261ec43b199a214f6b0ae5fefefff2e524f8977 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Tue, 14 Jan 2014 22:49:50 +0800
-Subject: [PATCH] ARM: dts: sun7i: add pin muxing options for UART2
-
-UART2 is used on CubieTruck to connect to the Bluetooth module.
-Add the pin set used in this case.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index b476855..bfb2cf2 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -381,6 +381,13 @@
- allwinner,pull = <0>;
- };
-
-+ uart2_pins_a: uart2@0 {
-+ allwinner,pins = "PI16", "PI17", "PI18", "PI19";
-+ allwinner,function = "uart2";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
- uart6_pins_a: uart6@0 {
- allwinner,pins = "PI12", "PI13";
- allwinner,function = "uart6";
---
-1.8.5.5
-
+++ /dev/null
-From 97e36b3ce3106988b82e1ca53b1d1c872bde855a Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:40 +0800
-Subject: [PATCH] clk: sunxi: get divs parent clock name from parent factor
- clock
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Divs clocks consist of a parent factor clock with multiple outputs,
-and seperate clocks for each output. Get the name of the parent
-clock from the parent factor clock, instead of the DT node name.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Mike Turquette <mturquette@linaro.org>
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 7a2ed98..736fb60 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -869,7 +869,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
- struct divs_data *data)
- {
- struct clk_onecell_data *clk_data;
-- const char *parent = node->name;
-+ const char *parent;
- const char *clk_name;
- struct clk **clks, *pclk;
- struct clk_hw *gate_hw, *rate_hw;
-@@ -883,6 +883,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
-
- /* Set up factor clock that we will be dividing */
- pclk = sunxi_factors_clk_setup(node, data->factors);
-+ parent = __clk_get_name(pclk);
-
- reg = of_iomap(node, 0);
-
---
-1.8.5.5
-
+++ /dev/null
-From f64111ebaf6776558f0e60d0ea8c7a9c579b9436 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:37 +0800
-Subject: [PATCH] clk: sunxi: add clock-output-names dt property support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-sunxi clock drivers use dt node name as clock name, but clock
-nodes should be named clk@X, so the names would be the same.
-Let the drivers read clock names from dt clock-output-names
-property.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Mike Turquette <mturquette@linaro.org>
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index abb6c5a..0ed9794 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -51,6 +51,8 @@ static void __init sun4i_osc_clk_setup(struct device_node *node)
- if (!gate)
- goto err_free_fixed;
-
-+ of_property_read_string(node, "clock-output-names", &clk_name);
-+
- /* set up gate and fixed rate properties */
- gate->reg = of_iomap(node, 0);
- gate->bit_idx = SUNXI_OSC24M_GATE;
-@@ -601,6 +603,8 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
- (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
- i++;
-
-+ of_property_read_string(node, "clock-output-names", &clk_name);
-+
- clk = clk_register_mux(NULL, clk_name, parents, i,
- CLK_SET_RATE_NO_REPARENT, reg,
- data->shift, SUNXI_MUX_GATE_WIDTH,
-@@ -660,6 +664,8 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
-
- clk_parent = of_clk_get_parent_name(node, 0);
-
-+ of_property_read_string(node, "clock-output-names", &clk_name);
-+
- clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
- reg, data->shift, data->width,
- data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
---
-1.8.5.5
-
+++ /dev/null
-From 667f542db542fddc62d1299b17451d7cae84f6e1 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:39 +0800
-Subject: [PATCH] clk: sunxi: add names for pll5, pll6 parent clocks to
- factors_data
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Some factor clocks, such as the parent clock of pll5 and pll6, have
-multiple output names. Add the corresponding names to factors_data
-tied to compatible string.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Mike Turquette <mturquette@linaro.org>
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 27 ++++++++++++++++++---------
- 1 file changed, 18 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 0ed9794..7a2ed98 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -389,6 +389,7 @@ struct factors_data {
- int mux;
- struct clk_factors_config *table;
- void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
-+ const char *name;
- };
-
- static struct clk_factors_config sun4i_pll1_config = {
-@@ -457,6 +458,14 @@ struct factors_data {
- .enable = 31,
- .table = &sun4i_pll5_config,
- .getter = sun4i_get_pll5_factors,
-+ .name = "pll5",
-+};
-+
-+static const struct factors_data sun4i_pll6_data __initconst = {
-+ .enable = 31,
-+ .table = &sun4i_pll5_config,
-+ .getter = sun4i_get_pll5_factors,
-+ .name = "pll6",
- };
-
- static const struct factors_data sun4i_apb1_data __initconst = {
-@@ -499,14 +508,14 @@ static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
- (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
- i++;
-
-- /* Nodes should be providing the name via clock-output-names
-- * but originally our dts didn't, and so we used node->name.
-- * The new, better nodes look like clk@deadbeef, so we pull the
-- * name just in this case */
-- if (!strcmp("clk", clk_name)) {
-- of_property_read_string_index(node, "clock-output-names",
-- 0, &clk_name);
-- }
-+ /*
-+ * some factor clocks, such as pll5 and pll6, may have multiple
-+ * outputs, and have their name designated in factors_data
-+ */
-+ if (data->name)
-+ clk_name = data->name;
-+ else
-+ of_property_read_string(node, "clock-output-names", &clk_name);
-
- factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
- if (!factors)
-@@ -838,7 +847,7 @@ struct divs_data {
- };
-
- static const struct divs_data pll6_divs_data __initconst = {
-- .factors = &sun4i_pll5_data,
-+ .factors = &sun4i_pll6_data,
- .div = {
- { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
- { .fixed = 2 }, /* P, other */
---
-1.8.5.5
-
+++ /dev/null
-From 967f938d4b16233fd7596e94803a36161847c6a8 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:47 +0800
-Subject: [PATCH] clk: sunxi: Add Allwinner A20/A31 GMAC clock unit
-
-The Allwinner A20/A31 clock module controls the transmit clock source
-and interface type of the GMAC ethernet controller. Model this as
-a single clock for GMAC drivers to use.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 30 +++++++
- drivers/clk/sunxi/clk-sunxi.c | 96 +++++++++++++++++++++++
- 2 files changed, 126 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
-index 93d003c..0da774c 100644
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -37,6 +37,7 @@ Required properties:
- "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
- "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
- "allwinner,sun7i-a20-out-clk" - for the external output clocks
-+ "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
-
- Required properties for all clocks:
- - reg : shall be the control register address for the clock.
-@@ -50,6 +51,9 @@ Required properties for all clocks:
- If the clock module only has one output, the name shall be the
- module name.
-
-+For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
-+dummy clocks at 25 MHz and 125 MHz, respectively. See example.
-+
- Clock consumers should specify the desired clocks they use with a
- "clocks" phandle cell. Consumers that are using a gated clock should
- provide an additional ID in their clock property. This ID is the
-@@ -96,3 +100,29 @@ mmc0_clk: clk@01c20088 {
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc0";
- };
-+
-+mii_phy_tx_clk: clk@2 {
-+ #clock-cells = <0>;
-+ compatible = "fixed-clock";
-+ clock-frequency = <25000000>;
-+ clock-output-names = "mii_phy_tx";
-+};
-+
-+gmac_int_tx_clk: clk@3 {
-+ #clock-cells = <0>;
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ clock-output-names = "gmac_int_tx";
-+};
-+
-+gmac_clk: clk@01c20164 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun7i-a20-gmac-clk";
-+ reg = <0x01c20164 0x4>;
-+ /*
-+ * The first clock must be fixed at 25MHz;
-+ * the second clock must be fixed at 125MHz
-+ */
-+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
-+ clock-output-names = "gmac";
-+};
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 0dce6fd..3283179 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -404,6 +404,102 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
-
-
- /**
-+ * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
-+ *
-+ * This clock looks something like this
-+ * ________________________
-+ * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
-+ * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
-+ * Ext. 125MHz RGMII TX clk >--|__divider__/ |
-+ * |________________________|
-+ *
-+ * The external 125 MHz reference is optional, i.e. GMAC can use its
-+ * internal TX clock just fine. The A31 GMAC clock module does not have
-+ * the divider controls for the external reference.
-+ *
-+ * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
-+ * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
-+ * select the appropriate source and gate/ungate the output to the PHY.
-+ *
-+ * Only the GMAC should use this clock. Altering the clock so that it doesn't
-+ * match the GMAC's operation parameters will result in the GMAC not being
-+ * able to send traffic out. The GMAC driver should set the clock rate and
-+ * enable/disable this clock to configure the required state. The clock
-+ * driver then responds by auto-reparenting the clock.
-+ */
-+
-+#define SUN7I_A20_GMAC_GPIT 2
-+#define SUN7I_A20_GMAC_MASK 0x3
-+#define SUN7I_A20_GMAC_PARENTS 2
-+
-+static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
-+{
-+ struct clk *clk;
-+ struct clk_mux *mux;
-+ struct clk_gate *gate;
-+ const char *clk_name = node->name;
-+ const char *parents[SUN7I_A20_GMAC_PARENTS];
-+ void *reg;
-+
-+ if (of_property_read_string(node, "clock-output-names", &clk_name))
-+ return;
-+
-+ /* allocate mux and gate clock structs */
-+ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
-+ if (!mux)
-+ return;
-+
-+ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
-+ if (!gate)
-+ goto free_mux;
-+
-+ /* gmac clock requires exactly 2 parents */
-+ parents[0] = of_clk_get_parent_name(node, 0);
-+ parents[1] = of_clk_get_parent_name(node, 1);
-+ if (!parents[0] || !parents[1])
-+ goto free_gate;
-+
-+ reg = of_iomap(node, 0);
-+ if (!reg)
-+ goto free_gate;
-+
-+ /* set up gate and fixed rate properties */
-+ gate->reg = reg;
-+ gate->bit_idx = SUN7I_A20_GMAC_GPIT;
-+ gate->lock = &clk_lock;
-+ mux->reg = reg;
-+ mux->mask = SUN7I_A20_GMAC_MASK;
-+ mux->flags = CLK_MUX_INDEX_BIT;
-+ mux->lock = &clk_lock;
-+
-+ clk = clk_register_composite(NULL, clk_name,
-+ parents, SUN7I_A20_GMAC_PARENTS,
-+ &mux->hw, &clk_mux_ops,
-+ NULL, NULL,
-+ &gate->hw, &clk_gate_ops,
-+ 0);
-+
-+ if (IS_ERR(clk))
-+ goto iounmap_reg;
-+
-+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
-+ clk_register_clkdev(clk, clk_name, NULL);
-+
-+ return;
-+
-+iounmap_reg:
-+ iounmap(reg);
-+free_gate:
-+ kfree(gate);
-+free_mux:
-+ kfree(mux);
-+}
-+CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
-+ sun7i_a20_gmac_clk_setup);
-+
-+
-+
-+/**
- * sunxi_factors_clk_setup() - Setup function for factor clocks
- */
-
---
-1.8.5.5
-
+++ /dev/null
-From 673fac742946bcb7cc43b9e67459862d6c4a8a6c Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Wed, 1 Jan 2014 10:30:47 +0800
-Subject: [PATCH] ARM: dts: sun7i: Change 32768 Hz oscillator node name to
- clk@N style
-
-Device tree naming conventions state that node names should match
-the nodes function. Change external low speed oscillator node name
-to match.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 898b021..edad6f1 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -53,10 +53,11 @@
- clock-frequency = <24000000>;
- };
-
-- osc32k: osc32k {
-+ osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
-+ clock-output-names = "osc32k";
- };
-
- pll1: pll1@01c20000 {
---
-1.8.5.5
-
+++ /dev/null
-From 92ef67c53ad92487c3c8de75e7940384c2edd793 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Wed, 5 Feb 2014 14:05:03 +0100
-Subject: [PATCH] clk: sunxi: Add support for PLL6 on the A31
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The A31 has a slightly different PLL6 clock. Add support for this new clock in
-our driver.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
- drivers/clk/sunxi/clk-sunxi.c | 45 +++++++++++++++++++++++
- 2 files changed, 46 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
-index ca2b692..c37c764 100644
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -11,6 +11,7 @@ Required properties:
- "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
- "allwinner,sun4i-pll5-clk" - for the PLL5 clock
- "allwinner,sun4i-pll6-clk" - for the PLL6 clock
-+ "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
- "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
- "allwinner,sun4i-axi-clk" - for the AXI clock
- "allwinner,sun4i-axi-gates-clk" - for the AXI gates
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index a779c31..d4cf297 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -252,7 +252,38 @@ static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
- *n = DIV_ROUND_UP(div, (*k+1));
- }
-
-+/**
-+ * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
-+ * PLL6 rate is calculated as follows
-+ * rate = parent_rate * n * (k + 1) / 2
-+ * parent_rate is always 24Mhz
-+ */
-+
-+static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
-+ u8 *n, u8 *k, u8 *m, u8 *p)
-+{
-+ u8 div;
-+
-+ /*
-+ * We always have 24MHz / 2, so we can just say that our
-+ * parent clock is 12MHz.
-+ */
-+ parent_rate = parent_rate / 2;
-+
-+ /* Normalize value to a parent_rate multiple (24M / 2) */
-+ div = *freq / parent_rate;
-+ *freq = parent_rate * div;
-+
-+ /* we were called to round the frequency, we can now return */
-+ if (n == NULL)
-+ return;
-+
-+ *k = div / 32;
-+ if (*k > 3)
-+ *k = 3;
-
-+ *n = DIV_ROUND_UP(div, (*k+1));
-+}
-
- /**
- * sun4i_get_apb1_factors() - calculates m, p factors for APB1
-@@ -420,6 +451,13 @@ struct factors_data {
- .kwidth = 2,
- };
-
-+static struct clk_factors_config sun6i_a31_pll6_config = {
-+ .nshift = 8,
-+ .nwidth = 5,
-+ .kshift = 4,
-+ .kwidth = 2,
-+};
-+
- static struct clk_factors_config sun4i_apb1_config = {
- .mshift = 0,
- .mwidth = 5,
-@@ -469,6 +507,12 @@ struct factors_data {
- .name = "pll6",
- };
-
-+static const struct factors_data sun6i_a31_pll6_data __initconst = {
-+ .enable = 31,
-+ .table = &sun6i_a31_pll6_config,
-+ .getter = sun6i_a31_get_pll6_factors,
-+};
-+
- static const struct factors_data sun4i_apb1_data __initconst = {
- .table = &sun4i_apb1_config,
- .getter = sun4i_get_apb1_factors,
-@@ -1069,6 +1113,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
- static const struct of_device_id clk_factors_match[] __initconst = {
- {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
- {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
-+ {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
- {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
- {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
- {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
---
-1.8.5.5
-
+++ /dev/null
-From 3558fe900e8af6c3bfadeff24a12ffb19ac9b108 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Wed, 5 Feb 2014 14:05:05 +0100
-Subject: [PATCH 1/2] spi: sunxi: Add Allwinner A31 SPI controller driver
-
-The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
-SoCs.
-
-It supports DMA, but the driver only does PIO for now, and DMA will be
-supported eventually.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- .../devicetree/bindings/spi/spi-sun6i.txt | 24 +
- drivers/spi/Kconfig | 6 +
- drivers/spi/Makefile | 1 +
- drivers/spi/spi-sun6i.c | 483 +++++++++++++++++++++
- 4 files changed, 514 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/spi/spi-sun6i.txt
- create mode 100644 drivers/spi/spi-sun6i.c
-
-diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
-new file mode 100644
-index 0000000..21de73d
---- /dev/null
-+++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
-@@ -0,0 +1,24 @@
-+Allwinner A31 SPI controller
-+
-+Required properties:
-+- compatible: Should be "allwinner,sun6i-a31-spi".
-+- reg: Should contain register location and length.
-+- interrupts: Should contain interrupt.
-+- clocks: phandle to the clocks feeding the SPI controller. Two are
-+ needed:
-+ - "ahb": the gated AHB parent clock
-+ - "mod": the parent module clock
-+- clock-names: Must contain the clock names described just above
-+- resets: phandle to the reset controller asserting this device in
-+ reset
-+
-+Example:
-+
-+spi1: spi@01c69000 {
-+ compatible = "allwinner,sun6i-a31-spi";
-+ reg = <0x01c69000 0x1000>;
-+ interrupts = <0 66 4>;
-+ clocks = <&ahb1_gates 21>, <&spi1_clk>;
-+ clock-names = "ahb", "mod";
-+ resets = <&ahb1_rst 21>;
-+};
-diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
-index ba9310b..7cfe0ee 100644
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -446,6 +446,12 @@ config SPI_SIRF
- help
- SPI driver for CSR SiRFprimaII SoCs
-
-+config SPI_SUN6I
-+ tristate "Allwinner A31 SPI controller"
-+ depends on ARCH_SUNXI || COMPILE_TEST
-+ help
-+ This enables using the SPI controller on the Allwinner A31 SoCs.
-+
- config SPI_MXS
- tristate "Freescale MXS SPI controller"
- depends on ARCH_MXS
-diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
-index 95af48d..13b6ccf 100644
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -70,6 +70,7 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
- obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
- obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
- obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
-+obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
- obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
- obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
- obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
-diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
-new file mode 100644
-index 0000000..94d38d0
---- /dev/null
-+++ b/drivers/spi/spi-sun6i.c
-@@ -0,0 +1,483 @@
-+/*
-+ * Copyright (C) 2012 - 2014 Allwinner Tech
-+ * Pan Nan <pannan@allwinnertech.com>
-+ *
-+ * Copyright (C) 2014 Maxime Ripard
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/reset.h>
-+#include <linux/workqueue.h>
-+
-+#include <linux/spi/spi.h>
-+
-+#define SUN6I_FIFO_DEPTH 128
-+
-+#define SUN6I_GBL_CTL_REG 0x04
-+#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
-+#define SUN6I_GBL_CTL_MASTER BIT(1)
-+#define SUN6I_GBL_CTL_TP BIT(7)
-+#define SUN6I_GBL_CTL_RST BIT(31)
-+
-+#define SUN6I_TFR_CTL_REG 0x08
-+#define SUN6I_TFR_CTL_CPHA BIT(0)
-+#define SUN6I_TFR_CTL_CPOL BIT(1)
-+#define SUN6I_TFR_CTL_SPOL BIT(2)
-+#define SUN6I_TFR_CTL_CS_MASK 0x3
-+#define SUN6I_TFR_CTL_CS(cs) (((cs) & SUN6I_TFR_CTL_CS_MASK) << 4)
-+#define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
-+#define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
-+#define SUN6I_TFR_CTL_DHB BIT(8)
-+#define SUN6I_TFR_CTL_FBS BIT(12)
-+#define SUN6I_TFR_CTL_XCH BIT(31)
-+
-+#define SUN6I_INT_CTL_REG 0x10
-+#define SUN6I_INT_CTL_RF_OVF BIT(8)
-+#define SUN6I_INT_CTL_TC BIT(12)
-+
-+#define SUN6I_INT_STA_REG 0x14
-+
-+#define SUN6I_FIFO_CTL_REG 0x18
-+#define SUN6I_FIFO_CTL_RF_RST BIT(15)
-+#define SUN6I_FIFO_CTL_TF_RST BIT(31)
-+
-+#define SUN6I_FIFO_STA_REG 0x1c
-+#define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
-+#define SUN6I_FIFO_STA_RF_CNT_BITS 0
-+#define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
-+#define SUN6I_FIFO_STA_TF_CNT_BITS 16
-+
-+#define SUN6I_CLK_CTL_REG 0x24
-+#define SUN6I_CLK_CTL_CDR2_MASK 0xff
-+#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
-+#define SUN6I_CLK_CTL_CDR1_MASK 0xf
-+#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
-+#define SUN6I_CLK_CTL_DRS BIT(12)
-+
-+#define SUN6I_BURST_CNT_REG 0x30
-+#define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff)
-+
-+#define SUN6I_XMIT_CNT_REG 0x34
-+#define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
-+
-+#define SUN6I_BURST_CTL_CNT_REG 0x38
-+#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff)
-+
-+#define SUN6I_TXDATA_REG 0x200
-+#define SUN6I_RXDATA_REG 0x300
-+
-+struct sun6i_spi {
-+ struct spi_master *master;
-+ void __iomem *base_addr;
-+ struct clk *hclk;
-+ struct clk *mclk;
-+ struct reset_control *rstc;
-+
-+ struct completion done;
-+
-+ const u8 *tx_buf;
-+ u8 *rx_buf;
-+ int len;
-+};
-+
-+static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
-+{
-+ return readl(sspi->base_addr + reg);
-+}
-+
-+static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
-+{
-+ writel(value, sspi->base_addr + reg);
-+}
-+
-+static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
-+{
-+ u32 reg, cnt;
-+ u8 byte;
-+
-+ /* See how much data is available */
-+ reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
-+ reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
-+ cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
-+
-+ if (len > cnt)
-+ len = cnt;
-+
-+ while (len--) {
-+ byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
-+ if (sspi->rx_buf)
-+ *sspi->rx_buf++ = byte;
-+ }
-+}
-+
-+static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
-+{
-+ u8 byte;
-+
-+ if (len > sspi->len)
-+ len = sspi->len;
-+
-+ while (len--) {
-+ byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
-+ writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
-+ sspi->len--;
-+ }
-+}
-+
-+static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
-+{
-+ struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
-+ u32 reg;
-+
-+ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
-+ reg &= ~SUN6I_TFR_CTL_CS_MASK;
-+ reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
-+
-+ if (enable)
-+ reg |= SUN6I_TFR_CTL_CS_LEVEL;
-+ else
-+ reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
-+
-+ sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
-+}
-+
-+
-+static int sun6i_spi_transfer_one(struct spi_master *master,
-+ struct spi_device *spi,
-+ struct spi_transfer *tfr)
-+{
-+ struct sun6i_spi *sspi = spi_master_get_devdata(master);
-+ unsigned int mclk_rate, div, timeout;
-+ unsigned int tx_len = 0;
-+ int ret = 0;
-+ u32 reg;
-+
-+ /* We don't support transfer larger than the FIFO */
-+ if (tfr->len > SUN6I_FIFO_DEPTH)
-+ return -EINVAL;
-+
-+ reinit_completion(&sspi->done);
-+ sspi->tx_buf = tfr->tx_buf;
-+ sspi->rx_buf = tfr->rx_buf;
-+ sspi->len = tfr->len;
-+
-+ /* Clear pending interrupts */
-+ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
-+
-+ /* Reset FIFO */
-+ sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
-+ SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
-+
-+ /*
-+ * Setup the transfer control register: Chip Select,
-+ * polarities, etc.
-+ */
-+ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
-+
-+ if (spi->mode & SPI_CPOL)
-+ reg |= SUN6I_TFR_CTL_CPOL;
-+ else
-+ reg &= ~SUN6I_TFR_CTL_CPOL;
-+
-+ if (spi->mode & SPI_CPHA)
-+ reg |= SUN6I_TFR_CTL_CPHA;
-+ else
-+ reg &= ~SUN6I_TFR_CTL_CPHA;
-+
-+ if (spi->mode & SPI_LSB_FIRST)
-+ reg |= SUN6I_TFR_CTL_FBS;
-+ else
-+ reg &= ~SUN6I_TFR_CTL_FBS;
-+
-+ /*
-+ * If it's a TX only transfer, we don't want to fill the RX
-+ * FIFO with bogus data
-+ */
-+ if (sspi->rx_buf)
-+ reg &= ~SUN6I_TFR_CTL_DHB;
-+ else
-+ reg |= SUN6I_TFR_CTL_DHB;
-+
-+ /* We want to control the chip select manually */
-+ reg |= SUN6I_TFR_CTL_CS_MANUAL;
-+
-+ sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
-+
-+ /* Ensure that we have a parent clock fast enough */
-+ mclk_rate = clk_get_rate(sspi->mclk);
-+ if (mclk_rate < (2 * spi->max_speed_hz)) {
-+ clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
-+ mclk_rate = clk_get_rate(sspi->mclk);
-+ }
-+
-+ /*
-+ * Setup clock divider.
-+ *
-+ * We have two choices there. Either we can use the clock
-+ * divide rate 1, which is calculated thanks to this formula:
-+ * SPI_CLK = MOD_CLK / (2 ^ cdr)
-+ * Or we can use CDR2, which is calculated with the formula:
-+ * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
-+ * Wether we use the former or the latter is set through the
-+ * DRS bit.
-+ *
-+ * First try CDR2, and if we can't reach the expected
-+ * frequency, fall back to CDR1.
-+ */
-+ div = mclk_rate / (2 * spi->max_speed_hz);
-+ if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
-+ if (div > 0)
-+ div--;
-+
-+ reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
-+ } else {
-+ div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
-+ reg = SUN6I_CLK_CTL_CDR1(div);
-+ }
-+
-+ sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
-+
-+ /* Setup the transfer now... */
-+ if (sspi->tx_buf)
-+ tx_len = tfr->len;
-+
-+ /* Setup the counters */
-+ sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
-+ sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
-+ sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
-+ SUN6I_BURST_CTL_CNT_STC(tx_len));
-+
-+ /* Fill the TX FIFO */
-+ sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
-+
-+ /* Enable the interrupts */
-+ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
-+
-+ /* Start the transfer */
-+ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
-+ sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
-+
-+ timeout = wait_for_completion_timeout(&sspi->done,
-+ msecs_to_jiffies(1000));
-+ if (!timeout) {
-+ ret = -ETIMEDOUT;
-+ goto out;
-+ }
-+
-+ sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
-+
-+out:
-+ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
-+
-+ return ret;
-+}
-+
-+static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
-+{
-+ struct sun6i_spi *sspi = dev_id;
-+ u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
-+
-+ /* Transfer complete */
-+ if (status & SUN6I_INT_CTL_TC) {
-+ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
-+ complete(&sspi->done);
-+ return IRQ_HANDLED;
-+ }
-+
-+ return IRQ_NONE;
-+}
-+
-+static int sun6i_spi_runtime_resume(struct device *dev)
-+{
-+ struct spi_master *master = dev_get_drvdata(dev);
-+ struct sun6i_spi *sspi = spi_master_get_devdata(master);
-+ int ret;
-+
-+ ret = clk_prepare_enable(sspi->hclk);
-+ if (ret) {
-+ dev_err(dev, "Couldn't enable AHB clock\n");
-+ goto out;
-+ }
-+
-+ ret = clk_prepare_enable(sspi->mclk);
-+ if (ret) {
-+ dev_err(dev, "Couldn't enable module clock\n");
-+ goto err;
-+ }
-+
-+ ret = reset_control_deassert(sspi->rstc);
-+ if (ret) {
-+ dev_err(dev, "Couldn't deassert the device from reset\n");
-+ goto err2;
-+ }
-+
-+ sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
-+ SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
-+
-+ return 0;
-+
-+err2:
-+ clk_disable_unprepare(sspi->mclk);
-+err:
-+ clk_disable_unprepare(sspi->hclk);
-+out:
-+ return ret;
-+}
-+
-+static int sun6i_spi_runtime_suspend(struct device *dev)
-+{
-+ struct spi_master *master = dev_get_drvdata(dev);
-+ struct sun6i_spi *sspi = spi_master_get_devdata(master);
-+
-+ reset_control_assert(sspi->rstc);
-+ clk_disable_unprepare(sspi->mclk);
-+ clk_disable_unprepare(sspi->hclk);
-+
-+ return 0;
-+}
-+
-+static int sun6i_spi_probe(struct platform_device *pdev)
-+{
-+ struct spi_master *master;
-+ struct sun6i_spi *sspi;
-+ struct resource *res;
-+ int ret = 0, irq;
-+
-+ master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
-+ if (!master) {
-+ dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
-+ return -ENOMEM;
-+ }
-+
-+ platform_set_drvdata(pdev, master);
-+ sspi = spi_master_get_devdata(master);
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(sspi->base_addr)) {
-+ ret = PTR_ERR(sspi->base_addr);
-+ goto err_free_master;
-+ }
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0) {
-+ dev_err(&pdev->dev, "No spi IRQ specified\n");
-+ ret = -ENXIO;
-+ goto err_free_master;
-+ }
-+
-+ ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
-+ 0, "sun6i-spi", sspi);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Cannot request IRQ\n");
-+ goto err_free_master;
-+ }
-+
-+ sspi->master = master;
-+ master->set_cs = sun6i_spi_set_cs;
-+ master->transfer_one = sun6i_spi_transfer_one;
-+ master->num_chipselect = 4;
-+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
-+ master->dev.of_node = pdev->dev.of_node;
-+ master->auto_runtime_pm = true;
-+
-+ sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
-+ if (IS_ERR(sspi->hclk)) {
-+ dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
-+ ret = PTR_ERR(sspi->hclk);
-+ goto err_free_master;
-+ }
-+
-+ sspi->mclk = devm_clk_get(&pdev->dev, "mod");
-+ if (IS_ERR(sspi->mclk)) {
-+ dev_err(&pdev->dev, "Unable to acquire module clock\n");
-+ ret = PTR_ERR(sspi->mclk);
-+ goto err_free_master;
-+ }
-+
-+ init_completion(&sspi->done);
-+
-+ sspi->rstc = devm_reset_control_get(&pdev->dev, NULL);
-+ if (IS_ERR(sspi->rstc)) {
-+ dev_err(&pdev->dev, "Couldn't get reset controller\n");
-+ ret = PTR_ERR(sspi->rstc);
-+ goto err_free_master;
-+ }
-+
-+ /*
-+ * This wake-up/shutdown pattern is to be able to have the
-+ * device woken up, even if runtime_pm is disabled
-+ */
-+ ret = sun6i_spi_runtime_resume(&pdev->dev);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Couldn't resume the device\n");
-+ goto err_free_master;
-+ }
-+
-+ pm_runtime_set_active(&pdev->dev);
-+ pm_runtime_enable(&pdev->dev);
-+ pm_runtime_idle(&pdev->dev);
-+
-+ ret = devm_spi_register_master(&pdev->dev, master);
-+ if (ret) {
-+ dev_err(&pdev->dev, "cannot register SPI master\n");
-+ goto err_pm_disable;
-+ }
-+
-+ return 0;
-+
-+err_pm_disable:
-+ pm_runtime_disable(&pdev->dev);
-+ sun6i_spi_runtime_suspend(&pdev->dev);
-+err_free_master:
-+ spi_master_put(master);
-+ return ret;
-+}
-+
-+static int sun6i_spi_remove(struct platform_device *pdev)
-+{
-+ pm_runtime_disable(&pdev->dev);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id sun6i_spi_match[] = {
-+ { .compatible = "allwinner,sun6i-a31-spi", },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, sun6i_spi_match);
-+
-+static const struct dev_pm_ops sun6i_spi_pm_ops = {
-+ .runtime_resume = sun6i_spi_runtime_resume,
-+ .runtime_suspend = sun6i_spi_runtime_suspend,
-+};
-+
-+static struct platform_driver sun6i_spi_driver = {
-+ .probe = sun6i_spi_probe,
-+ .remove = sun6i_spi_remove,
-+ .driver = {
-+ .name = "sun6i-spi",
-+ .owner = THIS_MODULE,
-+ .of_match_table = sun6i_spi_match,
-+ .pm = &sun6i_spi_pm_ops,
-+ },
-+};
-+module_platform_driver(sun6i_spi_driver);
-+
-+MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
-+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
-+MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
-+MODULE_LICENSE("GPL");
---
-1.8.5.5
-
-
-From 7961656a6f11b69966500d7bd25273203fd930da Mon Sep 17 00:00:00 2001
-From: Mark Brown <broonie@linaro.org>
-Date: Thu, 6 Feb 2014 10:53:51 +0000
-Subject: [PATCH 2/2] spi/sunxi: Add missing dependency on RESET_CONTROLLER
-
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- drivers/spi/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
-index 7cfe0ee..0ec4641 100644
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -449,6 +449,7 @@ config SPI_SIRF
- config SPI_SUN6I
- tristate "Allwinner A31 SPI controller"
- depends on ARCH_SUNXI || COMPILE_TEST
-+ depends on RESET_CONTROLLER
- help
- This enables using the SPI controller on the Allwinner A31 SoCs.
-
---
-1.8.5.5
-
+++ /dev/null
-From b0a09c756bf6e0b89d6b88a7620ba4cd86b1895b Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Wed, 5 Feb 2014 14:05:04 +0100
-Subject: [PATCH] ARM: sun6i: dt: Add PLL6 and SPI module clocks
-
-The module clocks in the A31 are still compatible with the A10 one. Add the SPI
-module clocks and the PLL6 in the device tree to allow their use by the SPI
-controllers.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 46 ++++++++++++++++++++++++++++++++--------
- 1 file changed, 37 insertions(+), 9 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
-index 092bf97..93d7bb6 100644
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -83,16 +83,12 @@
- clocks = <&osc24M>;
- };
-
-- /*
-- * This is a dummy clock, to be used as placeholder on
-- * other mux clocks when a specific parent clock is not
-- * yet implemented. It should be dropped when the driver
-- * is complete.
-- */
-- pll6: pll6 {
-+ pll6: clk@01c20028 {
- #clock-cells = <0>;
-- compatible = "fixed-clock";
-- clock-frequency = <0>;
-+ compatible = "allwinner,sun6i-a31-pll6-clk";
-+ reg = <0x01c20028 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll6";
- };
-
- cpu: cpu@01c20050 {
-@@ -192,6 +188,38 @@
- "apb2_uart1", "apb2_uart2", "apb2_uart3",
- "apb2_uart4", "apb2_uart5";
- };
-+
-+ spi0_clk: clk@01c200a0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a0 0x4>;
-+ clocks = <&osc24M>, <&pll6>;
-+ clock-output-names = "spi0";
-+ };
-+
-+ spi1_clk: clk@01c200a4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a4 0x4>;
-+ clocks = <&osc24M>, <&pll6>;
-+ clock-output-names = "spi1";
-+ };
-+
-+ spi2_clk: clk@01c200a8 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a8 0x4>;
-+ clocks = <&osc24M>, <&pll6>;
-+ clock-output-names = "spi2";
-+ };
-+
-+ spi3_clk: clk@01c200ac {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200ac 0x4>;
-+ clocks = <&osc24M>, <&pll6>;
-+ clock-output-names = "spi3";
-+ };
- };
-
- soc@01c00000 {
---
-1.8.5.5
-
+++ /dev/null
-From 67e7ba38902a28679bf6ee8fd82952ae6795f5f5 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:53 +0100
-Subject: [PATCH] spi: sunxi: Add Allwinner A10 SPI controller driver
-
-The older Allwinner SoCs (A10, A13, A10s and A20) all have the same SPI
-controller.
-
-Unfortunately, this SPI controller, even though quite similar, is significantly
-different from the recently supported A31 SPI controller (different registers
-offset, split/merged registers, etc.). Supporting both controllers in a single
-driver would be unreasonable, hence the addition of a new driver.
-
-Like its more recent counterpart, it supports DMA, but the driver only does PIO
-until we have a dmaengine driver for this platform.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- .../devicetree/bindings/spi/spi-sun4i.txt | 24 ++
- drivers/spi/Kconfig | 6 +
- drivers/spi/Makefile | 1 +
- drivers/spi/spi-sun4i.c | 477 +++++++++++++++++++++
- 4 files changed, 508 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/spi/spi-sun4i.txt
- create mode 100644 drivers/spi/spi-sun4i.c
-
-diff --git a/Documentation/devicetree/bindings/spi/spi-sun4i.txt b/Documentation/devicetree/bindings/spi/spi-sun4i.txt
-new file mode 100644
-index 0000000..de827f5
---- /dev/null
-+++ b/Documentation/devicetree/bindings/spi/spi-sun4i.txt
-@@ -0,0 +1,24 @@
-+Allwinner A10 SPI controller
-+
-+Required properties:
-+- compatible: Should be "allwinner,sun4-a10-spi".
-+- reg: Should contain register location and length.
-+- interrupts: Should contain interrupt.
-+- clocks: phandle to the clocks feeding the SPI controller. Two are
-+ needed:
-+ - "ahb": the gated AHB parent clock
-+ - "mod": the parent module clock
-+- clock-names: Must contain the clock names described just above
-+
-+Example:
-+
-+spi1: spi@01c06000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c06000 0x1000>;
-+ interrupts = <11>;
-+ clocks = <&ahb_gates 21>, <&spi1_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+};
-diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
-index 58530d3..78adfae 100644
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -446,6 +446,12 @@ config SPI_SIRF
- help
- SPI driver for CSR SiRFprimaII SoCs
-
-+config SPI_SUN4I
-+ tristate "Allwinner A10 SoCs SPI controller"
-+ depends on ARCH_SUNXI || COMPILE_TEST
-+ help
-+ SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
-+
- config SPI_SUN6I
- tristate "Allwinner A31 SPI controller"
- depends on ARCH_SUNXI || COMPILE_TEST
-diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
-index 13b6ccf..65f4993 100644
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -70,6 +70,7 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
- obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
- obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
- obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
-+obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
- obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
- obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
- obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
-diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
-new file mode 100644
-index 0000000..3f82705
---- /dev/null
-+++ b/drivers/spi/spi-sun4i.c
-@@ -0,0 +1,477 @@
-+/*
-+ * Copyright (C) 2012 - 2014 Allwinner Tech
-+ * Pan Nan <pannan@allwinnertech.com>
-+ *
-+ * Copyright (C) 2014 Maxime Ripard
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/workqueue.h>
-+
-+#include <linux/spi/spi.h>
-+
-+#define SUN4I_FIFO_DEPTH 64
-+
-+#define SUN4I_RXDATA_REG 0x00
-+
-+#define SUN4I_TXDATA_REG 0x04
-+
-+#define SUN4I_CTL_REG 0x08
-+#define SUN4I_CTL_ENABLE BIT(0)
-+#define SUN4I_CTL_MASTER BIT(1)
-+#define SUN4I_CTL_CPHA BIT(2)
-+#define SUN4I_CTL_CPOL BIT(3)
-+#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
-+#define SUN4I_CTL_LMTF BIT(6)
-+#define SUN4I_CTL_TF_RST BIT(8)
-+#define SUN4I_CTL_RF_RST BIT(9)
-+#define SUN4I_CTL_XCH BIT(10)
-+#define SUN4I_CTL_CS_MASK 0x3000
-+#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK)
-+#define SUN4I_CTL_DHB BIT(15)
-+#define SUN4I_CTL_CS_MANUAL BIT(16)
-+#define SUN4I_CTL_CS_LEVEL BIT(17)
-+#define SUN4I_CTL_TP BIT(18)
-+
-+#define SUN4I_INT_CTL_REG 0x0c
-+#define SUN4I_INT_CTL_TC BIT(16)
-+
-+#define SUN4I_INT_STA_REG 0x10
-+
-+#define SUN4I_DMA_CTL_REG 0x14
-+
-+#define SUN4I_WAIT_REG 0x18
-+
-+#define SUN4I_CLK_CTL_REG 0x1c
-+#define SUN4I_CLK_CTL_CDR2_MASK 0xff
-+#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
-+#define SUN4I_CLK_CTL_CDR1_MASK 0xf
-+#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
-+#define SUN4I_CLK_CTL_DRS BIT(12)
-+
-+#define SUN4I_BURST_CNT_REG 0x20
-+#define SUN4I_BURST_CNT(cnt) ((cnt) & 0xffffff)
-+
-+#define SUN4I_XMIT_CNT_REG 0x24
-+#define SUN4I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
-+
-+#define SUN4I_FIFO_STA_REG 0x28
-+#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
-+#define SUN4I_FIFO_STA_RF_CNT_BITS 0
-+#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
-+#define SUN4I_FIFO_STA_TF_CNT_BITS 16
-+
-+struct sun4i_spi {
-+ struct spi_master *master;
-+ void __iomem *base_addr;
-+ struct clk *hclk;
-+ struct clk *mclk;
-+
-+ struct completion done;
-+
-+ const u8 *tx_buf;
-+ u8 *rx_buf;
-+ int len;
-+};
-+
-+static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
-+{
-+ return readl(sspi->base_addr + reg);
-+}
-+
-+static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
-+{
-+ writel(value, sspi->base_addr + reg);
-+}
-+
-+static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
-+{
-+ u32 reg, cnt;
-+ u8 byte;
-+
-+ /* See how much data is available */
-+ reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
-+ reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
-+ cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
-+
-+ if (len > cnt)
-+ len = cnt;
-+
-+ while (len--) {
-+ byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
-+ if (sspi->rx_buf)
-+ *sspi->rx_buf++ = byte;
-+ }
-+}
-+
-+static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
-+{
-+ u8 byte;
-+
-+ if (len > sspi->len)
-+ len = sspi->len;
-+
-+ while (len--) {
-+ byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
-+ writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
-+ sspi->len--;
-+ }
-+}
-+
-+static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
-+{
-+ struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
-+ u32 reg;
-+
-+ reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
-+
-+ reg &= ~SUN4I_CTL_CS_MASK;
-+ reg |= SUN4I_CTL_CS(spi->chip_select);
-+
-+ if (enable)
-+ reg |= SUN4I_CTL_CS_LEVEL;
-+ else
-+ reg &= ~SUN4I_CTL_CS_LEVEL;
-+
-+ /*
-+ * Even though this looks irrelevant since we are supposed to
-+ * be controlling the chip select manually, this bit also
-+ * controls the levels of the chip select for inactive
-+ * devices.
-+ *
-+ * If we don't set it, the chip select level will go low by
-+ * default when the device is idle, which is not really
-+ * expected in the common case where the chip select is active
-+ * low.
-+ */
-+ if (spi->mode & SPI_CS_HIGH)
-+ reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
-+ else
-+ reg |= SUN4I_CTL_CS_ACTIVE_LOW;
-+
-+ sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
-+}
-+
-+static int sun4i_spi_transfer_one(struct spi_master *master,
-+ struct spi_device *spi,
-+ struct spi_transfer *tfr)
-+{
-+ struct sun4i_spi *sspi = spi_master_get_devdata(master);
-+ unsigned int mclk_rate, div, timeout;
-+ unsigned int tx_len = 0;
-+ int ret = 0;
-+ u32 reg;
-+
-+ /* We don't support transfer larger than the FIFO */
-+ if (tfr->len > SUN4I_FIFO_DEPTH)
-+ return -EINVAL;
-+
-+ reinit_completion(&sspi->done);
-+ sspi->tx_buf = tfr->tx_buf;
-+ sspi->rx_buf = tfr->rx_buf;
-+ sspi->len = tfr->len;
-+
-+ /* Clear pending interrupts */
-+ sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
-+
-+
-+ reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
-+
-+ /* Reset FIFOs */
-+ sun4i_spi_write(sspi, SUN4I_CTL_REG,
-+ reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
-+
-+ /*
-+ * Setup the transfer control register: Chip Select,
-+ * polarities, etc.
-+ */
-+ if (spi->mode & SPI_CPOL)
-+ reg |= SUN4I_CTL_CPOL;
-+ else
-+ reg &= ~SUN4I_CTL_CPOL;
-+
-+ if (spi->mode & SPI_CPHA)
-+ reg |= SUN4I_CTL_CPHA;
-+ else
-+ reg &= ~SUN4I_CTL_CPHA;
-+
-+ if (spi->mode & SPI_LSB_FIRST)
-+ reg |= SUN4I_CTL_LMTF;
-+ else
-+ reg &= ~SUN4I_CTL_LMTF;
-+
-+
-+ /*
-+ * If it's a TX only transfer, we don't want to fill the RX
-+ * FIFO with bogus data
-+ */
-+ if (sspi->rx_buf)
-+ reg &= ~SUN4I_CTL_DHB;
-+ else
-+ reg |= SUN4I_CTL_DHB;
-+
-+ /* We want to control the chip select manually */
-+ reg |= SUN4I_CTL_CS_MANUAL;
-+
-+ sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
-+
-+ /* Ensure that we have a parent clock fast enough */
-+ mclk_rate = clk_get_rate(sspi->mclk);
-+ if (mclk_rate < (2 * spi->max_speed_hz)) {
-+ clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
-+ mclk_rate = clk_get_rate(sspi->mclk);
-+ }
-+
-+ /*
-+ * Setup clock divider.
-+ *
-+ * We have two choices there. Either we can use the clock
-+ * divide rate 1, which is calculated thanks to this formula:
-+ * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
-+ * Or we can use CDR2, which is calculated with the formula:
-+ * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
-+ * Wether we use the former or the latter is set through the
-+ * DRS bit.
-+ *
-+ * First try CDR2, and if we can't reach the expected
-+ * frequency, fall back to CDR1.
-+ */
-+ div = mclk_rate / (2 * spi->max_speed_hz);
-+ if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
-+ if (div > 0)
-+ div--;
-+
-+ reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
-+ } else {
-+ div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
-+ reg = SUN4I_CLK_CTL_CDR1(div);
-+ }
-+
-+ sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
-+
-+ /* Setup the transfer now... */
-+ if (sspi->tx_buf)
-+ tx_len = tfr->len;
-+
-+ /* Setup the counters */
-+ sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
-+ sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
-+
-+ /* Fill the TX FIFO */
-+ sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
-+
-+ /* Enable the interrupts */
-+ sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
-+
-+ /* Start the transfer */
-+ reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
-+ sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
-+
-+ timeout = wait_for_completion_timeout(&sspi->done,
-+ msecs_to_jiffies(1000));
-+ if (!timeout) {
-+ ret = -ETIMEDOUT;
-+ goto out;
-+ }
-+
-+ sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
-+
-+out:
-+ sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
-+
-+ return ret;
-+}
-+
-+static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
-+{
-+ struct sun4i_spi *sspi = dev_id;
-+ u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
-+
-+ /* Transfer complete */
-+ if (status & SUN4I_INT_CTL_TC) {
-+ sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
-+ complete(&sspi->done);
-+ return IRQ_HANDLED;
-+ }
-+
-+ return IRQ_NONE;
-+}
-+
-+static int sun4i_spi_runtime_resume(struct device *dev)
-+{
-+ struct spi_master *master = dev_get_drvdata(dev);
-+ struct sun4i_spi *sspi = spi_master_get_devdata(master);
-+ int ret;
-+
-+ ret = clk_prepare_enable(sspi->hclk);
-+ if (ret) {
-+ dev_err(dev, "Couldn't enable AHB clock\n");
-+ goto out;
-+ }
-+
-+ ret = clk_prepare_enable(sspi->mclk);
-+ if (ret) {
-+ dev_err(dev, "Couldn't enable module clock\n");
-+ goto err;
-+ }
-+
-+ sun4i_spi_write(sspi, SUN4I_CTL_REG,
-+ SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
-+
-+ return 0;
-+
-+err:
-+ clk_disable_unprepare(sspi->hclk);
-+out:
-+ return ret;
-+}
-+
-+static int sun4i_spi_runtime_suspend(struct device *dev)
-+{
-+ struct spi_master *master = dev_get_drvdata(dev);
-+ struct sun4i_spi *sspi = spi_master_get_devdata(master);
-+
-+ clk_disable_unprepare(sspi->mclk);
-+ clk_disable_unprepare(sspi->hclk);
-+
-+ return 0;
-+}
-+
-+static int sun4i_spi_probe(struct platform_device *pdev)
-+{
-+ struct spi_master *master;
-+ struct sun4i_spi *sspi;
-+ struct resource *res;
-+ int ret = 0, irq;
-+
-+ master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi));
-+ if (!master) {
-+ dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
-+ return -ENOMEM;
-+ }
-+
-+ platform_set_drvdata(pdev, master);
-+ sspi = spi_master_get_devdata(master);
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(sspi->base_addr)) {
-+ ret = PTR_ERR(sspi->base_addr);
-+ goto err_free_master;
-+ }
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0) {
-+ dev_err(&pdev->dev, "No spi IRQ specified\n");
-+ ret = -ENXIO;
-+ goto err_free_master;
-+ }
-+
-+ ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler,
-+ 0, "sun4i-spi", sspi);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Cannot request IRQ\n");
-+ goto err_free_master;
-+ }
-+
-+ sspi->master = master;
-+ master->set_cs = sun4i_spi_set_cs;
-+ master->transfer_one = sun4i_spi_transfer_one;
-+ master->num_chipselect = 4;
-+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
-+ master->dev.of_node = pdev->dev.of_node;
-+ master->auto_runtime_pm = true;
-+
-+ sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
-+ if (IS_ERR(sspi->hclk)) {
-+ dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
-+ ret = PTR_ERR(sspi->hclk);
-+ goto err_free_master;
-+ }
-+
-+ sspi->mclk = devm_clk_get(&pdev->dev, "mod");
-+ if (IS_ERR(sspi->mclk)) {
-+ dev_err(&pdev->dev, "Unable to acquire module clock\n");
-+ ret = PTR_ERR(sspi->mclk);
-+ goto err_free_master;
-+ }
-+
-+ init_completion(&sspi->done);
-+
-+ /*
-+ * This wake-up/shutdown pattern is to be able to have the
-+ * device woken up, even if runtime_pm is disabled
-+ */
-+ ret = sun4i_spi_runtime_resume(&pdev->dev);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Couldn't resume the device\n");
-+ goto err_free_master;
-+ }
-+
-+ pm_runtime_set_active(&pdev->dev);
-+ pm_runtime_enable(&pdev->dev);
-+ pm_runtime_idle(&pdev->dev);
-+
-+ ret = devm_spi_register_master(&pdev->dev, master);
-+ if (ret) {
-+ dev_err(&pdev->dev, "cannot register SPI master\n");
-+ goto err_pm_disable;
-+ }
-+
-+ return 0;
-+
-+err_pm_disable:
-+ pm_runtime_disable(&pdev->dev);
-+ sun4i_spi_runtime_suspend(&pdev->dev);
-+err_free_master:
-+ spi_master_put(master);
-+ return ret;
-+}
-+
-+static int sun4i_spi_remove(struct platform_device *pdev)
-+{
-+ pm_runtime_disable(&pdev->dev);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id sun4i_spi_match[] = {
-+ { .compatible = "allwinner,sun4i-a10-spi", },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, sun4i_spi_match);
-+
-+static const struct dev_pm_ops sun4i_spi_pm_ops = {
-+ .runtime_resume = sun4i_spi_runtime_resume,
-+ .runtime_suspend = sun4i_spi_runtime_suspend,
-+};
-+
-+static struct platform_driver sun4i_spi_driver = {
-+ .probe = sun4i_spi_probe,
-+ .remove = sun4i_spi_remove,
-+ .driver = {
-+ .name = "sun4i-spi",
-+ .owner = THIS_MODULE,
-+ .of_match_table = sun4i_spi_match,
-+ .pm = &sun4i_spi_pm_ops,
-+ },
-+};
-+module_platform_driver(sun4i_spi_driver);
-+
-+MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
-+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
-+MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
-+MODULE_LICENSE("GPL");
---
-1.8.5.5
-
+++ /dev/null
-From 3fff6e0d2bdd3b3f999a9dfcc8432ecba56eaad8 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:54 +0100
-Subject: [PATCH] ARM: dt: sun7i: Add A20 SPI controller nodes
-
-The A20 has 4 SPI controllers compatible with the one found in the A10. Add
-them in the DT.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 44 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 1961751..bcea04a 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -393,6 +393,28 @@
- #size-cells = <1>;
- ranges;
-
-+ spi0: spi@01c05000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c05000 0x1000>;
-+ interrupts = <0 10 4>;
-+ clocks = <&ahb_gates 20>, <&spi0_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ spi1: spi@01c06000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c06000 0x1000>;
-+ interrupts = <0 11 4>;
-+ clocks = <&ahb_gates 21>, <&spi1_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- emac: ethernet@01c0b000 {
- compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
-@@ -485,6 +507,17 @@
- status = "disabled";
- };
-
-+ spi2: spi@01c17000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c17000 0x1000>;
-+ interrupts = <0 12 4>;
-+ clocks = <&ahb_gates 22>, <&spi2_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- ahci: sata@01c18000 {
- compatible = "allwinner,sun4i-a10-ahci";
- reg = <0x01c18000 0x1000>;
-@@ -513,6 +546,17 @@
- status = "disabled";
- };
-
-+ spi3: spi@01c1f000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c1f000 0x1000>;
-+ interrupts = <0 50 4>;
-+ clocks = <&ahb_gates 23>, <&spi3_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- pio: pinctrl@01c20800 {
- compatible = "allwinner,sun7i-a20-pinctrl";
- reg = <0x01c20800 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From f21f034bd5b288068e1fa35c28d5e48e9ae8cbf5 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:55 +0100
-Subject: [PATCH] ARM: dt: sun4i: Add A10 SPI controller nodes
-
-The A10 has 4 SPI controllers that are now supported. Add them in the DT.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 44 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 3a5775c..cdd5b72 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -331,6 +331,28 @@
- #size-cells = <1>;
- ranges;
-
-+ spi0: spi@01c05000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c05000 0x1000>;
-+ interrupts = <10>;
-+ clocks = <&ahb_gates 20>, <&spi0_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ spi1: spi@01c06000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c06000 0x1000>;
-+ interrupts = <11>;
-+ clocks = <&ahb_gates 21>, <&spi1_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- emac: ethernet@01c0b000 {
- compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
-@@ -423,6 +445,17 @@
- status = "disabled";
- };
-
-+ spi2: spi@01c17000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c17000 0x1000>;
-+ interrupts = <12>;
-+ clocks = <&ahb_gates 22>, <&spi2_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- ahci: sata@01c18000 {
- compatible = "allwinner,sun4i-a10-ahci";
- reg = <0x01c18000 0x1000>;
-@@ -451,6 +484,17 @@
- status = "disabled";
- };
-
-+ spi3: spi@01c1f000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c1f000 0x1000>;
-+ interrupts = <50>;
-+ clocks = <&ahb_gates 23>, <&spi3_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From f76e72a20510fa17934c82bed5e23f7c4a4f2931 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:56 +0100
-Subject: [PATCH] ARM: dt: sun5i: Add A10s SPI controller nodes
-
-The A10s has 3 SPI controllers compatible with the one found in the A10. Add
-them in the DT.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 33 +++++++++++++++++++++++++++++++++
- 1 file changed, 33 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index e5064dc..2dedb7c 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -292,6 +292,28 @@
- #size-cells = <1>;
- ranges;
-
-+ spi0: spi@01c05000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c05000 0x1000>;
-+ interrupts = <10>;
-+ clocks = <&ahb_gates 20>, <&spi0_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ spi1: spi@01c06000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c06000 0x1000>;
-+ interrupts = <11>;
-+ clocks = <&ahb_gates 21>, <&spi1_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- emac: ethernet@01c0b000 {
- compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
-@@ -373,6 +395,17 @@
- status = "disabled";
- };
-
-+ spi2: spi@01c17000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c17000 0x1000>;
-+ interrupts = <12>;
-+ clocks = <&ahb_gates 22>, <&spi2_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From a02b2ef06a3f11d2e6c20c2cdcdd6f0b4217d234 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:57 +0100
-Subject: [PATCH] ARM: dt: sun5i: Add A13 SPI controller nodes
-
-The A13 has 3 SPI controllers compatible with the one found in the A10. Add
-them in the DT.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a13.dtsi | 33 +++++++++++++++++++++++++++++++++
- 1 file changed, 33 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index b0cc56c..1ff406b 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -290,6 +290,28 @@
- #size-cells = <1>;
- ranges;
-
-+ spi0: spi@01c05000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c05000 0x1000>;
-+ interrupts = <10>;
-+ clocks = <&ahb_gates 20>, <&spi0_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ spi1: spi@01c06000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c06000 0x1000>;
-+ interrupts = <11>;
-+ clocks = <&ahb_gates 21>, <&spi1_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- mmc0: mmc@01c0f000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c0f000 0x1000>;
-@@ -344,6 +366,17 @@
- status = "disabled";
- };
-
-+ spi2: spi@01c17000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c17000 0x1000>;
-+ interrupts = <12>;
-+ clocks = <&ahb_gates 22>, <&spi2_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From eb9180f426a7da1da5ed0f3aa13b92609c869fc0 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:58 +0100
-Subject: [PATCH] ARM: dt: sun7i: Add SPI muxing options
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index bcea04a..9f57035 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -688,6 +688,20 @@
- allwinner,drive = <2>;
- allwinner,pull = <0>;
- };
-+
-+ spi1_pins_a: spi1@0 {
-+ allwinner,pins = "PI16", "PI17", "PI18", "PI19";
-+ allwinner,function = "spi1";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ spi2_pins_a: spi2@0 {
-+ allwinner,pins = "PC19", "PC20", "PC21", "PC22";
-+ allwinner,function = "spi2";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- timer@01c20c00 {
---
-1.8.5.5
-
+++ /dev/null
-From 5c5ac3fb749c64e7c1e6e3208fcabab065359f56 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:59 +0100
-Subject: [PATCH] ARM: dts: sun7i: Enable the SPI controllers of the
- A20-olinuxino-micro
-
-The A20-Olinuxino-micro has two SPI bus exposed on its UEXT connectors, enable
-them.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-index 824ce0a..68cedf3 100644
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -21,7 +21,24 @@
- model = "Olimex A20-Olinuxino Micro";
- compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
-
-+ aliases {
-+ spi0 = &spi1;
-+ spi1 = &spi2;
-+ };
-+
- soc@01c00000 {
-+ spi1: spi@01c06000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi1_pins_a>;
-+ status = "okay";
-+ };
-+
-+ spi2: spi@01c17000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi2_pins_a>;
-+ status = "okay";
-+ };
-+
- mmc0: mmc@01c0f000 {
- pinctrl-names = "default", "default";
- pinctrl-0 = <&mmc0_pins_a>;
---
-1.8.5.5
-
+++ /dev/null
-From 111579574584c73a91c2b1bf8657c3691cc22409 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 2 Feb 2014 14:55:23 +0100
-Subject: [PATCH] wdt: sunxi: Introduce a new compatible for the A10 and A31
-
-For historical reasons, the Allwinner A10 compatibles are not following the
-patterns used for this other Allwinner SoCs.
-
-Introduce a new compatible following the usual pattern, and deprecate the olders.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 7 ++++---
- drivers/watchdog/sunxi_wdt.c | 1 +
- 2 files changed, 5 insertions(+), 3 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
-index e39cb26..6e8c937 100644
---- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
-+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
-@@ -2,13 +2,14 @@ Allwinner SoCs Watchdog timer
-
- Required properties:
-
--- compatible : should be "allwinner,<soc-family>-wdt", the currently supported
-- SoC families being sun4i and sun6i
-+- compatible : should be either "allwinner,sun4i-a10-wdt" or
-+ "allwinner,sun6i-a31-wdt" (deprecated:
-+ "allwinner,sun4i-wdt", "allwinner,sun6i-wdt")
- - reg : Specifies base physical address and size of the registers.
-
- Example:
-
- wdt: watchdog@01c20c90 {
-- compatible = "allwinner,sun4i-wdt";
-+ compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
-index 76332d89..7c8923d 100644
---- a/drivers/watchdog/sunxi_wdt.c
-+++ b/drivers/watchdog/sunxi_wdt.c
-@@ -206,6 +206,7 @@ static void sunxi_wdt_shutdown(struct platform_device *pdev)
-
- static const struct of_device_id sunxi_wdt_dt_ids[] = {
- { .compatible = "allwinner,sun4i-wdt" },
-+ { .compatible = "allwinner,sun4i-a10-wdt" },
- { /* sentinel */ }
- };
- MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
---
-1.8.5.5
-
+++ /dev/null
-From b50ff681c8e3e9e408ee1fb6c6317bc8da653a01 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 2 Feb 2014 14:55:24 +0100
-Subject: [PATCH] ARM: sunxi: Add the new watchog compatibles to the reboot
- code
-
-Now that the watchdog driver has new compatibles, we need to support them in
-the machine reboot code too.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/mach-sunxi/sunxi.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
-index aeea6ce..c310df6 100644
---- a/arch/arm/mach-sunxi/sunxi.c
-+++ b/arch/arm/mach-sunxi/sunxi.c
-@@ -95,7 +95,9 @@ static void sun6i_restart(enum reboot_mode mode, const char *cmd)
-
- static struct of_device_id sunxi_restart_ids[] = {
- { .compatible = "allwinner,sun4i-wdt" },
-+ { .compatible = "allwinner,sun4i-a10-wdt" },
- { .compatible = "allwinner,sun6i-wdt" },
-+ { .compatible = "allwinner,sun6i-a31-wdt" },
- { /*sentinel*/ }
- };
-
---
-1.8.5.5
-
+++ /dev/null
-From 0dba36162dffdee935287645d515f53057de3537 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 2 Feb 2014 14:55:25 +0100
-Subject: [PATCH] ARM: sunxi: dt: Update the watchdog compatibles
-
-The watchdog compatibles were following a different pattern than the one found
-in the other devices. Now that the driver supports the right pattern, switch to
-it in the DT.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 2 +-
- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +-
- arch/arm/boot/dts/sun5i-a13.dtsi | 2 +-
- arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
- 5 files changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 80bbdeb..3a5775c 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -545,7 +545,7 @@
- };
-
- wdt: watchdog@01c20c90 {
-- compatible = "allwinner,sun4i-wdt";
-+ compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index a5431ed..e5064dc 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -467,7 +467,7 @@
- };
-
- wdt: watchdog@01c20c90 {
-- compatible = "allwinner,sun4i-wdt";
-+ compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 7fe9cdc..b0cc56c 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -413,7 +413,7 @@
- };
-
- wdt: watchdog@01c20c90 {
-- compatible = "allwinner,sun4i-wdt";
-+ compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-
-diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
-index b4407f17..c15f30e 100644
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -289,7 +289,7 @@
- };
-
- wdt1: watchdog@01c20ca0 {
-- compatible = "allwinner,sun6i-wdt";
-+ compatible = "allwinner,sun6i-a31-wdt";
- reg = <0x01c20ca0 0x20>;
- };
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index e67924a..1961751 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -659,7 +659,7 @@
- };
-
- wdt: watchdog@01c20c90 {
-- compatible = "allwinner,sun4i-wdt";
-+ compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-
---
-1.8.5.5
-
+++ /dev/null
-From 328d21d9c56ddca56ed80b1595066b1621f6926b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 23 Dec 2013 16:21:02 +0100
-Subject: [PATCH] input: Add new sun4i-ts driver for Allwinner sunxi SoC's rtp
- controller
-
-Note the sun4i-ts controller is capable of detecting a second touch, but when
-a second touch is present then the accuracy becomes so bad the reported touch
-location is not useable.
-
-The original android driver contains some complicated heuristics using the
-aprox. distance between the 2 touches to see if the user is making a pinch
-open / close movement, and then reports emulated multi-touch events around
-the last touch coordinate (as the dual-touch coordinates are worthless).
-
-These kinds of heuristics are just asking for trouble (and don't belong
-in the kernel). So this driver offers straight forward, reliable single
-touch functionality only.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../bindings/input/touchscreen/sun4i.txt | 15 ++
- drivers/input/touchscreen/Kconfig | 10 +
- drivers/input/touchscreen/Makefile | 1 +
- drivers/input/touchscreen/sun4i-ts.c | 262 +++++++++++++++++++++
- 4 files changed, 288 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/input/touchscreen/sun4i.txt
- create mode 100644 drivers/input/touchscreen/sun4i-ts.c
-
-diff --git a/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt b/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt
-new file mode 100644
-index 0000000..e45927e
---- /dev/null
-+++ b/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt
-@@ -0,0 +1,15 @@
-+sun4i resistive touchscreen controller
-+--------------------------------------
-+
-+Required properties:
-+ - compatible: "allwinner,sun4i-ts"
-+ - reg: mmio address range of the chip
-+ - interrupts: interrupt to which the chip is connected
-+
-+Example:
-+
-+ rtp: rtp@01c25000 {
-+ compatible = "allwinner,sun4i-ts";
-+ reg = <0x01c25000 0x100>;
-+ interrupts = <29>;
-+ };
-diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
-index 07e9e82..f4c5ca3 100644
---- a/drivers/input/touchscreen/Kconfig
-+++ b/drivers/input/touchscreen/Kconfig
-@@ -906,6 +906,16 @@ config TOUCHSCREEN_STMPE
- To compile this driver as a module, choose M here: the
- module will be called stmpe-ts.
-
-+config TOUCHSCREEN_SUN4I
-+ tristate "Allwinner sun4i resistive touchscreen controller support"
-+ depends on ARCH_SUNXI
-+ help
-+ This selects support for the resistive touchscreen controller
-+ found on Allwinner sunxi SoCs.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called sun4i-ts.
-+
- config TOUCHSCREEN_SUR40
- tristate "Samsung SUR40 (Surface 2.0/PixelSense) touchscreen"
- depends on USB
-diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
-index 62801f2..c8f7375 100644
---- a/drivers/input/touchscreen/Makefile
-+++ b/drivers/input/touchscreen/Makefile
-@@ -54,6 +54,7 @@ obj-$(CONFIG_TOUCHSCREEN_PIXCIR) += pixcir_i2c_ts.o
- obj-$(CONFIG_TOUCHSCREEN_S3C2410) += s3c2410_ts.o
- obj-$(CONFIG_TOUCHSCREEN_ST1232) += st1232.o
- obj-$(CONFIG_TOUCHSCREEN_STMPE) += stmpe-ts.o
-+obj-$(CONFIG_TOUCHSCREEN_SUN4I) += sun4i-ts.o
- obj-$(CONFIG_TOUCHSCREEN_SUR40) += sur40.o
- obj-$(CONFIG_TOUCHSCREEN_TI_AM335X_TSC) += ti_am335x_tsc.o
- obj-$(CONFIG_TOUCHSCREEN_TNETV107X) += tnetv107x-ts.o
-diff --git a/drivers/input/touchscreen/sun4i-ts.c b/drivers/input/touchscreen/sun4i-ts.c
-new file mode 100644
-index 0000000..5945219
---- /dev/null
-+++ b/drivers/input/touchscreen/sun4i-ts.c
-@@ -0,0 +1,262 @@
-+/*
-+ * Allwinner sunxi resistive touchscreen controller driver
-+ *
-+ * Copyright (C) 2013 - 2014 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+/*
-+ * The sun4i-ts controller is capable of detecting a second touch, but when a
-+ * second touch is present then the accuracy becomes so bad the reported touch
-+ * location is not useable.
-+ *
-+ * The original android driver contains some complicated heuristics using the
-+ * aprox. distance between the 2 touches to see if the user is making a pinch
-+ * open / close movement, and then reports emulated multi-touch events around
-+ * the last touch coordinate (as the dual-touch coordinates are worthless).
-+ *
-+ * These kinds of heuristics are just asking for trouble (and don't belong
-+ * in the kernel). So this driver offers straight forward, reliable single
-+ * touch functionality only.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/input.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+
-+#define TP_CTRL0 0x00
-+#define TP_CTRL1 0x04
-+#define TP_CTRL2 0x08
-+#define TP_CTRL3 0x0c
-+#define TP_INT_FIFOC 0x10
-+#define TP_INT_FIFOS 0x14
-+#define TP_TPR 0x18
-+#define TP_CDAT 0x1c
-+#define TEMP_DATA 0x20
-+#define TP_DATA 0x24
-+
-+/* TP_CTRL0 bits */
-+#define ADC_FIRST_DLY(x) ((x) << 24) /* 8 bits */
-+#define ADC_FIRST_DLY_MODE(x) ((x) << 23)
-+#define ADC_CLK_SEL(x) ((x) << 22)
-+#define ADC_CLK_DIV(x) ((x) << 20) /* 3 bits */
-+#define FS_DIV(x) ((x) << 16) /* 4 bits */
-+#define T_ACQ(x) ((x) << 0) /* 16 bits */
-+
-+/* TP_CTRL1 bits */
-+#define STYLUS_UP_DEBOUN(x) ((x) << 12) /* 8 bits */
-+#define STYLUS_UP_DEBOUN_EN(x) ((x) << 9)
-+#define TOUCH_PAN_CALI_EN(x) ((x) << 6)
-+#define TP_DUAL_EN(x) ((x) << 5)
-+#define TP_MODE_EN(x) ((x) << 4)
-+#define TP_ADC_SELECT(x) ((x) << 3)
-+#define ADC_CHAN_SELECT(x) ((x) << 0) /* 3 bits */
-+
-+/* TP_CTRL2 bits */
-+#define TP_SENSITIVE_ADJUST(x) ((x) << 28) /* 4 bits */
-+#define TP_MODE_SELECT(x) ((x) << 26) /* 2 bits */
-+#define PRE_MEA_EN(x) ((x) << 24)
-+#define PRE_MEA_THRE_CNT(x) ((x) << 0) /* 24 bits */
-+
-+/* TP_CTRL3 bits */
-+#define FILTER_EN(x) ((x) << 2)
-+#define FILTER_TYPE(x) ((x) << 0) /* 2 bits */
-+
-+/* TP_INT_FIFOC irq and fifo mask / control bits */
-+#define TEMP_IRQ_EN(x) ((x) << 18)
-+#define OVERRUN_IRQ_EN(x) ((x) << 17)
-+#define DATA_IRQ_EN(x) ((x) << 16)
-+#define TP_DATA_XY_CHANGE(x) ((x) << 13)
-+#define FIFO_TRIG(x) ((x) << 8) /* 5 bits */
-+#define DATA_DRQ_EN(x) ((x) << 7)
-+#define FIFO_FLUSH(x) ((x) << 4)
-+#define TP_UP_IRQ_EN(x) ((x) << 1)
-+#define TP_DOWN_IRQ_EN(x) ((x) << 0)
-+
-+/* TP_INT_FIFOS irq and fifo status bits */
-+#define TEMP_DATA_PENDING BIT(18)
-+#define FIFO_OVERRUN_PENDING BIT(17)
-+#define FIFO_DATA_PENDING BIT(16)
-+#define TP_IDLE_FLG BIT(2)
-+#define TP_UP_PENDING BIT(1)
-+#define TP_DOWN_PENDING BIT(0)
-+
-+/* TP_TPR bits */
-+#define TEMP_ENABLE(x) ((x) << 16)
-+#define TEMP_PERIOD(x) ((x) << 0) /* t = x * 256 * 16 / clkin */
-+
-+struct sun4i_ts_data {
-+ struct device *dev;
-+ struct input_dev *input;
-+ void __iomem *base;
-+ unsigned int irq;
-+ bool ignore_fifo_data;
-+};
-+
-+static irqreturn_t sun4i_ts_irq(int irq, void *dev_id)
-+{
-+ struct sun4i_ts_data *ts = dev_id;
-+ u32 reg_val, x, y;
-+
-+ reg_val = readl(ts->base + TP_INT_FIFOS);
-+
-+ if (reg_val & FIFO_DATA_PENDING) {
-+ x = readl(ts->base + TP_DATA);
-+ y = readl(ts->base + TP_DATA);
-+ /* The 1st location reported after an up event is unreliable */
-+ if (!ts->ignore_fifo_data) {
-+ input_report_abs(ts->input, ABS_X, x);
-+ input_report_abs(ts->input, ABS_Y, y);
-+ /*
-+ * The hardware has a separate down status bit, but
-+ * that gets set before we get the first location,
-+ * resulting in reporting a click on the old location.
-+ */
-+ input_report_key(ts->input, BTN_TOUCH, 1);
-+ input_sync(ts->input);
-+ } else {
-+ ts->ignore_fifo_data = false;
-+ }
-+ }
-+
-+ if (reg_val & TP_UP_PENDING) {
-+ ts->ignore_fifo_data = true;
-+ input_report_key(ts->input, BTN_TOUCH, 0);
-+ input_sync(ts->input);
-+ }
-+
-+ writel(reg_val, ts->base + TP_INT_FIFOS);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int sun4i_ts_open(struct input_dev *dev)
-+{
-+ struct sun4i_ts_data *ts = input_get_drvdata(dev);
-+
-+ /* Flush, set trig level to 1, enable data and up irqs */
-+ writel(DATA_IRQ_EN(1) | FIFO_TRIG(1) | FIFO_FLUSH(1) | TP_UP_IRQ_EN(1),
-+ ts->base + TP_INT_FIFOC);
-+
-+ return 0;
-+}
-+
-+static void sun4i_ts_close(struct input_dev *dev)
-+{
-+ struct sun4i_ts_data *ts = input_get_drvdata(dev);
-+
-+ /* Deactivate all IRQs */
-+ writel(0, ts->base + TP_INT_FIFOC);
-+}
-+
-+static int sun4i_ts_probe(struct platform_device *pdev)
-+{
-+ struct sun4i_ts_data *ts;
-+ struct device *dev = &pdev->dev;
-+ int ret;
-+
-+ ts = devm_kzalloc(dev, sizeof(struct sun4i_ts_data), GFP_KERNEL);
-+ if (!ts)
-+ return -ENOMEM;
-+
-+ ts->dev = dev;
-+ ts->ignore_fifo_data = true;
-+
-+ ts->input = devm_input_allocate_device(dev);
-+ if (!ts->input)
-+ return -ENOMEM;
-+
-+ ts->input->name = pdev->name;
-+ ts->input->phys = "sun4i_ts/input0";
-+ ts->input->open = sun4i_ts_open;
-+ ts->input->close = sun4i_ts_close;
-+ ts->input->id.bustype = BUS_HOST;
-+ ts->input->id.vendor = 0x0001;
-+ ts->input->id.product = 0x0001;
-+ ts->input->id.version = 0x0100;
-+ ts->input->evbit[0] = BIT(EV_SYN) | BIT(EV_KEY) | BIT(EV_ABS);
-+ set_bit(BTN_TOUCH, ts->input->keybit);
-+ input_set_abs_params(ts->input, ABS_X, 0, 4095, 0, 0);
-+ input_set_abs_params(ts->input, ABS_Y, 0, 4095, 0, 0);
-+ input_set_drvdata(ts->input, ts);
-+
-+ ts->base = devm_ioremap_resource(dev,
-+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
-+ if (IS_ERR(ts->base))
-+ return PTR_ERR(ts->base);
-+
-+ ts->irq = platform_get_irq(pdev, 0);
-+ ret = devm_request_irq(dev, ts->irq, sun4i_ts_irq, 0, "sun4i-ts", ts);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Select HOSC clk, clkin = clk / 6, adc samplefreq = clkin / 8192,
-+ * t_acq = clkin / (16 * 64)
-+ */
-+ writel(ADC_CLK_SEL(0) | ADC_CLK_DIV(2) | FS_DIV(7) | T_ACQ(63),
-+ ts->base + TP_CTRL0);
-+
-+ /*
-+ * sensitive_adjust = 15 : max, which is not all that sensitive,
-+ * tp_mode = 0 : only x and y coordinates, as we don't use dual touch
-+ */
-+ writel(TP_SENSITIVE_ADJUST(15) | TP_MODE_SELECT(0),
-+ ts->base + TP_CTRL2);
-+
-+ /* Enable median filter, type 1 : 5/3 */
-+ writel(FILTER_EN(1) | FILTER_TYPE(1), ts->base + TP_CTRL3);
-+
-+ /* Enable temperature measurement, period 1953 (2 seconds) */
-+ writel(TEMP_ENABLE(1) | TEMP_PERIOD(1953), ts->base + TP_TPR);
-+
-+ /*
-+ * Set stylus up debounce to aprox 10 ms, enable debounce, and
-+ * finally enable tp mode.
-+ */
-+ writel(STYLUS_UP_DEBOUN(5) | STYLUS_UP_DEBOUN_EN(1) | TP_MODE_EN(1),
-+ ts->base + TP_CTRL1);
-+
-+ ret = input_register_device(ts->input);
-+ if (ret)
-+ return ret;
-+
-+ platform_set_drvdata(pdev, ts);
-+ return 0;
-+}
-+
-+static const struct of_device_id sun4i_ts_of_match[] = {
-+ { .compatible = "allwinner,sun4i-ts", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, sun4i_ts_of_match);
-+
-+static struct platform_driver sun4i_ts_driver = {
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = "sun4i-ts",
-+ .of_match_table = of_match_ptr(sun4i_ts_of_match),
-+ },
-+ .probe = sun4i_ts_probe,
-+};
-+
-+module_platform_driver(sun4i_ts_driver);
-+
-+MODULE_DESCRIPTION("Allwinner sun4i resistive touchscreen controller driver");
-+MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
-+MODULE_LICENSE("GPL");
---
-1.8.5.5
-
+++ /dev/null
-From 248529e6c78ba746988f1313f7bfb7ae74eae785 Mon Sep 17 00:00:00 2001
-From: Zoltan HERPAI <wigyori@uid0.hu>
-Date: Mon, 13 Jan 2014 14:15:01 +0100
-Subject: [PATCH] ARM: sun4i: dt: Add basic board support for LinkSprite
- pcDuino
-
-This patch will add a basic board support DT for the
-LinkSprite pcDuino board.
-
-Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/sun4i-a10-pcduino.dts | 48 +++++++++++++++++++++++++++++++++
- 2 files changed, 49 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun4i-a10-pcduino.dts
-
-diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
-index 6d1e43d..0b127db 100644
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -283,6 +283,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
- sun4i-a10-cubieboard.dtb \
- sun4i-a10-mini-xplus.dtb \
- sun4i-a10-hackberry.dtb \
-+ sun4i-a10-pcduino.dtb \
- sun5i-a10s-olinuxino-micro.dtb \
- sun5i-a13-olinuxino.dtb \
- sun5i-a13-olinuxino-micro.dtb \
-diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-new file mode 100644
-index 0000000..f5692a3
---- /dev/null
-+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-@@ -0,0 +1,48 @@
-+/*
-+ * Copyright 2014 Zoltan HERPAI
-+ * Zoltan HERPAI <wigyori@uid0.hu>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/dts-v1/;
-+/include/ "sun4i-a10.dtsi"
-+
-+/ {
-+ model = "LinkSprite pcDuino";
-+ compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10";
-+
-+ soc@01c00000 {
-+ emac: ethernet@01c0b000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_pins_a>;
-+ phy = <&phy1>;
-+ status = "okay";
-+ };
-+
-+ mdio@01c0b080 {
-+ status = "okay";
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
-+
-+ uart0: serial@01c28000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart0_pins_a>;
-+ status = "okay";
-+ };
-+
-+ i2c0: i2c@01c2ac00 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c0_pins_a>;
-+ status = "okay";
-+ };
-+ };
-+};
---
-1.8.5.5
-
+++ /dev/null
-From 54b9b9ab635ed8e643784402096524768f490f5d Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 11 Jan 2014 04:33:23 +0100
-Subject: [PATCH] ARM: sun4i: dt: Add mmc node to a few more boards
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-hackberry.dts | 9 +++++++++
- arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 8 ++++++++
- arch/arm/boot/dts/sun4i-a10-pcduino.dts | 8 ++++++++
- 3 files changed, 25 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
-index 6692d336..2eb30d0 100644
---- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
-@@ -35,6 +35,15 @@
- };
- };
-
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ cd-mode = <1>;
-+ status = "okay";
-+ };
-+
- pio: pinctrl@01c20800 {
- pinctrl-names = "default";
- pinctrl-0 = <&hackberry_hogs>;
-diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
-index 70b3323..6dbe53c 100644
---- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
-@@ -19,6 +19,14 @@
- compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
-
- soc@01c00000 {
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
-diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-index f5692a3..87f7742 100644
---- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-@@ -33,6 +33,14 @@
- };
- };
-
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
---
-1.8.5.5
-
+++ /dev/null
-From 713c2957f8b9e49b2170c9e546d705c9c358faee Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 20:41:04 +0100
-Subject: [PATCH] ARM: sun4i: dt: Add USB host nodes to pcduino.dts
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-pcduino.dts | 27 +++++++++++++++++++++++++++
- 1 file changed, 27 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-index 87f7742..3ccd357 100644
---- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-@@ -12,6 +12,7 @@
-
- /dts-v1/;
- /include/ "sun4i-a10.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-
- / {
- model = "LinkSprite pcDuino";
-@@ -41,6 +42,32 @@
- status = "okay";
- };
-
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
-+ ahci: sata@01c18000 {
-+ status = "okay";
-+ };
-+
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
---
-1.8.5.5
-
+++ /dev/null
-From 75e7218e107016a4baae26c70a81b1111fc8c70b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Fri, 10 Jan 2014 23:23:06 +0100
-Subject: [PATCH] ARM: sun4i: dt: Add sun4i-a10-olinuxino-lime.dtb
-
-This add support for the A10-OLinuXino-LIME:
-https://www.olimex.com/Products/OLinuXino/A10/A10-OLinuXino-LIME
-
-A low cost Allwinner A10 based dev-board, with sata, ethernet, hdmi and 2x USB.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 112 +++++++++++++++++++++++++
- 2 files changed, 113 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
-
-diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
-index 0b127db..c576de8 100644
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -283,6 +283,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
- sun4i-a10-cubieboard.dtb \
- sun4i-a10-mini-xplus.dtb \
- sun4i-a10-hackberry.dtb \
-+ sun4i-a10-olinuxino-lime.dtb \
- sun4i-a10-pcduino.dtb \
- sun5i-a10s-olinuxino-micro.dtb \
- sun5i-a13-olinuxino.dtb \
-diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
-new file mode 100644
-index 0000000..3c076f2
---- /dev/null
-+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
-@@ -0,0 +1,112 @@
-+/*
-+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/dts-v1/;
-+/include/ "sun4i-a10.dtsi"
-+/include/ "sunxi-ahci-reg.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-+
-+/ {
-+ model = "Olimex A10-OLinuXino-LIME";
-+ compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10";
-+
-+ soc@01c00000 {
-+ emac: ethernet@01c0b000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_pins_a>;
-+ phy = <&phy1>;
-+ status = "okay";
-+ };
-+
-+ mdio@01c0b080 {
-+ status = "okay";
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
-+
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ cd-mode = <1>;
-+ status = "okay";
-+ };
-+
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
-+ ahci: sata@01c18000 {
-+ target-supply = <®_ahci_5v>;
-+ status = "okay";
-+ };
-+
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
-+ pinctrl@01c20800 {
-+ ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
-+ allwinner,pins = "PC3";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ led_pins_olinuxinolime: led_pins@0 {
-+ allwinner,pins = "PH2";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <1>;
-+ allwinner,pull = <0>;
-+ };
-+ };
-+
-+ uart0: serial@01c28000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart0_pins_a>;
-+ status = "okay";
-+ };
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&led_pins_olinuxinolime>;
-+
-+ green {
-+ label = "a10-olinuxino-lime:green:usr";
-+ gpios = <&pio 7 2 0>;
-+ default-state = "on";
-+ };
-+ };
-+
-+ reg_ahci_5v: ahci-5v {
-+ pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
-+ gpio = <&pio 2 3 0>;
-+ };
-+};
---
-1.8.5.5
-
+++ /dev/null
-diff -ruN old/arch/arm/boot/dts/Makefile new/arch/arm/boot/dts/Makefile
---- old/arch/arm/boot/dts/Makefile 2014-04-26 15:15:01.000000000 +0200
-+++ new/arch/arm/boot/dts/Makefile 2014-04-26 15:46:58.336223315 +0200
-@@ -292,7 +292,8 @@
- sun6i-a31-colombus.dtb \
- sun7i-a20-cubieboard2.dtb \
- sun7i-a20-cubietruck.dtb \
-- sun7i-a20-olinuxino-micro.dtb
-+ sun7i-a20-olinuxino-micro.dtb \
-+ sun7i-a20-pcduino3.dtb
- dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
- tegra20-iris-512.dtb \
- tegra20-medcom-wide.dtb \
+++ /dev/null
-diff -ruN old/arch/arm/boot/dts/Makefile new/arch/arm/boot/dts/Makefile
---- old/arch/arm/boot/dts/Makefile 2014-04-28 22:20:54.000000000 +0200
-+++ new/arch/arm/boot/dts/Makefile 2014-06-01 17:28:54.187703560 +0200
-@@ -259,6 +259,7 @@
- sun5i-a13-olinuxino.dtb \
- sun5i-a13-olinuxino-micro.dtb \
- sun6i-a31-colombus.dtb \
-+ sun7i-a20-bananapi.dtb \
- sun7i-a20-cubieboard2.dtb \
- sun7i-a20-cubietruck.dtb \
- sun7i-a20-olinuxino-micro.dtb \
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Default
- NAME:=Default package set
- PACKAGES += uboot-sunxi-A13-OLinuXino
-endef
-
-define Profile/Default/Description
- Default package set compatible with most boards.
-endef
-$(eval $(call Profile,Default))
-
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/A10-OLinuXino-Lime
- NAME:=A10 OLinuXino LIME
- PACKAGES:=\
- uboot-sunxi-A10-OLinuXino-Lime kmod-ata-sunxi kmod-sun4i-emac kmod-rtc-sunxi
-endef
-
-define Profile/A10-OLinuXino-Lime/Description
- Package set optimized for the Olimex A10 OLinuXino LIME
-endef
-
-$(eval $(call Profile,A10-OLinuXino-Lime))
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/A13_OLinuXino
- NAME:=A13 OLinuXino
- PACKAGES:=\
- uboot-sunxi-A13-OLinuXino kmod-rtl8192cu
-endef
-
-define Profile/A13_OLinuXino/Description
- Package set optimized for the Olimex A13 OLinuXino
-endef
-
-$(eval $(call Profile,A13_OLinuXino))
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/A20-OLinuXino_MICRO
- NAME:=A20 OLinuXino Micro
- PACKAGES:=\
- uboot-sunxi-A20-OLinuXino_MICRO kmod-ata-sunxi kmod-sun4i-emac kmod-rtc-sunxi
-endef
-
-define Profile/A20-OLinuXino_MICRO/Description
- Package set optimized for the Olimex A20 OLinuXino micro
-endef
-
-$(eval $(call Profile,A20-OLinuXino_MICRO))
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/bananaPi
- NAME:=bananaPi
- PACKAGES:=\
- uboot-sunxi-bananapi kmod-rtc-sunxi
-endef
-
-define Profile/bananaPi/Description
- Package set optimized for the bananaPi
-endef
-
-$(eval $(call Profile,bananaPi))
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Cubieboard
- NAME:=Cubieboard
- PACKAGES:=\
- uboot-sunxi-Cubieboard kmod-ata-sunxi kmod-sun4i-emac kmod-rtc-sunxi
-endef
-
-define Profile/Cubieboard/Description
- Package set optimized for the Cubieboard
-endef
-
-$(eval $(call Profile,Cubieboard))
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/Cubieboard2
- NAME:=Cubieboard2
- PACKAGES:=\
- uboot-sunxi-Cubieboard2 kmod-ata-sunxi kmod-sun4i-emac kmod-rtc-sunxi
-endef
-
-define Profile/Cubieboard2/Description
- Package set optimized for the Cubieboard2
-endef
-
-$(eval $(call Profile,Cubieboard2))
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/pcDuino
- NAME:=pcDuino
- PACKAGES:=\
- uboot-sunxi-pcDuino kmod-sun4i-emac kmod-rtc-sunxi kmod-rtl8192cu
-endef
-
-define Profile/pcDuino/Description
- Package set optimized for the pcDuino
-endef
-
-$(eval $(call Profile,pcDuino))
+++ /dev/null
-#
-# Copyright (C) 2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-define Profile/pcDuino3
- NAME:=pcDuino3
- PACKAGES:=\
- uboot-sunxi-pcDuino3 kmod-sun4i-emac kmod-rtc-sunxi kmod-net-rtl8188eu
-endef
-
-define Profile/pcDuino3/Description
- Package set optimized for the pcDuino3
-endef
-
-$(eval $(call Profile,pcDuino3))
BOARD:=x86
BOARDNAME:=x86
FEATURES:=squashfs ext4 vdi vmdk pcmcia targz
-SUBTARGETS=generic olpc xen_domu ep80579 net5501 kvm_guest geos alix2 thincan \
+SUBTARGETS=generic olpc xen_domu net5501 kvm_guest geos alix2 thincan \
rdc
LINUX_VERSION:=3.10.49
+++ /dev/null
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHMEM4G=y
-# CONFIG_HIGHPTE is not set
-# CONFIG_ITCO_VENDOR_SUPPORT is not set
-CONFIG_ITCO_WDT=y
-CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_MTD is not set
-# CONFIG_NOHIGHMEM is not set
-CONFIG_SATA_AHCI=y
-# CONFIG_SQUASHFS is not set
+++ /dev/null
-BOARDNAME:=Intel EP80579
-LINUX_VERSION:=3.3.8
-DEFAULT_PACKAGES += kmod-ep80579-can kmod-ep80579-eth kmod-ep80579-misc \
- kmod-usb-core kmod-usb2 kmod-usb-hid kmod-usb-uhci
-
-define Target/Description
- Build firmware images for Intel EP80579 based boards
- (e.g : ADI Engineering Ocracoke Island)
-endef
-
+++ /dev/null
-#
-# Copyright (C) 2013-2014 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=x86_64
-BOARD:=x86_64
-BOARDNAME:=x86_64
-FEATURES:=ext4 vdi vmdk targz
-MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
-
-LINUX_VERSION:=3.14.12
-
-KERNELNAME:=bzImage
-
-include $(INCLUDE_DIR)/target.mk
-
-DEFAULT_PACKAGES += kmod-e1000
-
-$(eval $(call BuildTarget))
+++ /dev/null
-::sysinit:/etc/init.d/rcS S boot
-::shutdown:/etc/init.d/rcS K shutdown
-ttyS0::askfirst:/bin/ash --login
-tty1::askfirst:/bin/ash --login
+++ /dev/null
-#!/bin/sh
-# Copyright (C) 2006-2010 OpenWrt.org
-# Copyright (C) 2010 Vertical Communications
-
-do_mount_procfs() {
- mount -o noatime -t proc none /proc
-}
-
+++ /dev/null
-#!/bin/sh
-# Copyright (C) 2012 OpenWrt.org
-
-move_config() {
- local rootfsdev
- local rootfstype
-
- rootfstype="$(awk 'BEGIN { RS=" "; FS="="; } ($1 == "rootfstype") { print $2 }' < /proc/cmdline)"
- case "$rootfstype" in
- squashfs|jffs2)
- rootfsdev="$(awk 'BEGIN { RS=" "; FS="="; } ($1 == "block2mtd.block2mtd") { print substr($2,1,index($2, ",")-1) }' < /proc/cmdline)";;
- ext4)
- rootfsdev="$(awk 'BEGIN { RS=" "; FS="="; } ($1 == "root") { print $2 }' < /proc/cmdline)";;
- esac
-
- mount -t ext4 -o rw,noatime "${rootfsdev%[0-9]}1" /mnt
- mv -f /mnt/sysupgrade.tgz /
- umount /mnt
-}
-
-boot_hook_add preinit_mount_root move_config
-
+++ /dev/null
-x86_get_rootfs() {
- local rootfsdev
- local rootfstype
-
- rootfstype="$(awk 'BEGIN { RS=" "; FS="="; } ($1 == "rootfstype") { print $2 }' < /proc/cmdline)"
- case "$rootfstype" in
- squashfs|jffs2)
- rootfsdev="$(awk 'BEGIN { RS=" "; FS="="; } ($1 == "block2mtd.block2mtd") { print substr($2,1,index($2, ",")-1) }' < /proc/cmdline)";;
- ext4)
- rootfsdev="$(awk 'BEGIN { RS=" "; FS="="; } ($1 == "root") { print $2 }' < /proc/cmdline)";;
- esac
-
- echo "$rootfstype:$rootfsdev"
-}
-
-platform_check_image() {
- [ "$#" -gt 1 ] && return 1
-
- case "$(get_magic_word "$1")" in
- eb48|eb63) return 0;;
- *)
- echo "Invalid image type"
- return 1
- ;;
- esac
-}
-
-platform_copy_config() {
- local rootfs="$(x86_get_rootfs)"
- local rootfsdev="${rootfs##*:}"
-
- mount -t ext4 -o rw,noatime "${rootfsdev%[0-9]}1" /mnt
- cp -af "$CONF_TAR" /mnt/
- umount /mnt
-}
-
-platform_do_upgrade() {
- local rootfs="$(x86_get_rootfs)"
- local rootfsdev="${rootfs##*:}"
-
- sync
- [ -b ${rootfsdev%[0-9]} ] && get_image "$@" | dd of=${rootfsdev%[0-9]} bs=4096 conv=fsync
- sleep 1
-}
+++ /dev/null
-# CONFIG_60XX_WDT is not set
-CONFIG_64BIT=y
-CONFIG_ACPI=y
-CONFIG_ACPI_AC=y
-CONFIG_ACPI_BATTERY=y
-CONFIG_ACPI_BUTTON=y
-# CONFIG_ACPI_CMPC is not set
-# CONFIG_ACPI_CONTAINER is not set
-# CONFIG_ACPI_CUSTOM_DSDT is not set
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_DOCK is not set
-# CONFIG_ACPI_EC_DEBUGFS is not set
-CONFIG_ACPI_FAN=y
-# CONFIG_ACPI_INITRD_TABLE_OVERRIDE is not set
-# CONFIG_ACPI_PCI_SLOT is not set
-CONFIG_ACPI_PROCESSOR=y
-# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
-# CONFIG_ACPI_PROCFS is not set
-# CONFIG_ACPI_PROCFS_POWER is not set
-# CONFIG_ACPI_SBS is not set
-CONFIG_ACPI_THERMAL=y
-# CONFIG_ACPI_WMI is not set
-# CONFIG_ACQUIRE_WDT is not set
-# CONFIG_ADVANTECH_WDT is not set
-# CONFIG_ALIM1535_WDT is not set
-CONFIG_AMD_NB=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig"
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
-CONFIG_ARCH_HAS_CPU_AUTOPROBE=y
-CONFIG_ARCH_HAS_CPU_RELAX=y
-CONFIG_ARCH_HAS_DEBUG_STRICT_USER_COPY_CHECKS=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_HWEIGHT_CFLAGS="-fcall-saved-rdi -fcall-saved-rsi -fcall-saved-rdx -fcall-saved-rcx -fcall-saved-r8 -fcall-saved-r9 -fcall-saved-r10 -fcall-saved-r11"
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
-# CONFIG_ARCH_RANDOM is not set
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_INT128=y
-CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
-CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USES_PG_UNCACHED=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANTS_PROT_NUMA_PROT_NONE=y
-CONFIG_ARCH_WANT_FRAME_POINTERS=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-# CONFIG_ASUS_LAPTOP is not set
-CONFIG_ATA=y
-# CONFIG_ATA_SFF is not set
-CONFIG_AUDIT_ARCH=y
-CONFIG_AVERAGE=y
-CONFIG_BINFMT_MISC=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BOUNCE=y
-CONFIG_CALGARY_IOMMU=y
-CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y
-CONFIG_CLKBLD_I8253=y
-CONFIG_CLKEVT_I8253=y
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-# CONFIG_CPU5_WDT is not set
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_SUP_AMD=y
-CONFIG_CPU_SUP_CENTAUR=y
-CONFIG_CPU_SUP_INTEL=y
-CONFIG_CRC16=y
-# CONFIG_CRYPTO_AES_X86_64 is not set
-# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set
-# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set
-# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set
-# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set
-# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set
-# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_CRC32_PCLMUL is not set
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-# CONFIG_CRYPTO_SALSA20_X86_64 is not set
-# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set
-# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set
-# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set
-# CONFIG_CRYPTO_SHA1_SSSE3 is not set
-# CONFIG_CRYPTO_SHA256_SSSE3 is not set
-# CONFIG_CRYPTO_SHA512_SSSE3 is not set
-# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set
-# CONFIG_CRYPTO_TWOFISH_X86_64 is not set
-# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set
-CONFIG_DCACHE_WORD_ACCESS=y
-# CONFIG_DCDBAS is not set
-# CONFIG_DEBUG_BOOT_PARAMS is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_NMI_SELFTEST is not set
-# CONFIG_DEBUG_TLBFLUSH is not set
-# CONFIG_DEBUG_VIRTUAL is not set
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DEFAULT_IO_DELAY_TYPE=0
-# CONFIG_DELL_RBU is not set
-CONFIG_DIRECT_GBPAGES=y
-# CONFIG_DMI is not set
-CONFIG_DNOTIFY=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EARLY_PRINTK_DBGP is not set
-# CONFIG_EDD is not set
-# CONFIG_EFI is not set
-# CONFIG_EUROTECH_WDT is not set
-CONFIG_EXT4_FS=y
-# CONFIG_F71808E_WDT is not set
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-# CONFIG_FB_VESA is not set
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_FIRMWARE_MEMMAP=y
-CONFIG_FIX_EARLYCON_MEM=y
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_GART_IOMMU=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-# CONFIG_GOOGLE_FIRMWARE is not set
-# CONFIG_HANGCHECK_TIMER is not set
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_KMEMCHECK=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_SOFT_DIRTY=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CMPXCHG_DOUBLE=y
-CONFIG_HAVE_CMPXCHG_LOCAL=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FENTRY=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_BZIP2=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_KPROBES_ON_FTRACE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MEMORY_PRESENT=y
-CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
-CONFIG_HAVE_MMIOTRACE_SUPPORT=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_PCSPKR_PLATFORM=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_EVENTS_NMI=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
-CONFIG_HAVE_USER_RETURN_NOTIFIER=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HID=y
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_HPET=y
-CONFIG_HPET_EMULATE_RTC=y
-CONFIG_HPET_MMAP=y
-CONFIG_HPET_TIMER=y
-# CONFIG_HP_ACCEL is not set
-# CONFIG_HP_WATCHDOG is not set
-CONFIG_HT_IRQ=y
-# CONFIG_HUGETLBFS is not set
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_INTEL=y
-# CONFIG_HW_RANDOM_VIRTIO is not set
-CONFIG_HYPERVISOR_GUEST=y
-CONFIG_HZ_PERIODIC=y
-# CONFIG_I7300_IDLE is not set
-CONFIG_I8253_LOCK=y
-# CONFIG_I8K is not set
-# CONFIG_IA32_EMULATION is not set
-# CONFIG_IB700_WDT is not set
-# CONFIG_IBMASR is not set
-# CONFIG_IBM_RTL is not set
-# CONFIG_IE6XX_WDT is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INSTRUCTION_DECODER=y
-# CONFIG_INTEL_IPS is not set
-# CONFIG_INTEL_MENLOW is not set
-# CONFIG_INTEL_POWERCLAMP is not set
-# CONFIG_IOMMU_DEBUG is not set
-CONFIG_IOMMU_HELPER=y
-# CONFIG_IOMMU_STRESS is not set
-CONFIG_IO_DELAY_0X80=y
-# CONFIG_IO_DELAY_0XED is not set
-# CONFIG_IO_DELAY_NONE is not set
-CONFIG_IO_DELAY_TYPE_0X80=0
-CONFIG_IO_DELAY_TYPE_0XED=1
-CONFIG_IO_DELAY_TYPE_NONE=3
-CONFIG_IO_DELAY_TYPE_UDELAY=2
-# CONFIG_IO_DELAY_UDELAY is not set
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_ISA_DMA_API=y
-# CONFIG_ISCSI_IBFT_FIND is not set
-# CONFIG_IT8712F_WDT is not set
-# CONFIG_IT87_WDT is not set
-# CONFIG_ITCO_VENDOR_SUPPORT is not set
-CONFIG_ITCO_WDT=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KEXEC=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KVM_DEBUG_FS is not set
-CONFIG_KVM_GUEST=y
-CONFIG_LPC_ICH=y
-# CONFIG_MACHZ_WDT is not set
-# CONFIG_MATOM is not set
-# CONFIG_MCORE2 is not set
-# CONFIG_MEMORY_HOTPLUG is not set
-# CONFIG_MEMTEST is not set
-CONFIG_MFD_CORE=y
-# CONFIG_MICROCODE is not set
-# CONFIG_MICROCODE_AMD_EARLY is not set
-# CONFIG_MICROCODE_INTEL_EARLY is not set
-# CONFIG_MK8 is not set
-# CONFIG_MLX5_CORE is not set
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MPSC is not set
-# CONFIG_MTD is not set
-CONFIG_MTRR=y
-# CONFIG_MTRR_SANITIZER is not set
-CONFIG_NAMESPACES=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-# CONFIG_NET_NS is not set
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_NLS=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NR_CPUS=1
-# CONFIG_NTB is not set
-CONFIG_NVRAM=y
-CONFIG_OPROFILE_NMI_TIMER=y
-# CONFIG_OPTIMIZE_INLINING is not set
-CONFIG_OUTPUT_FORMAT="elf64-x86-64"
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PARAVIRT=y
-CONFIG_PARAVIRT_CLOCK=y
-# CONFIG_PARAVIRT_DEBUG is not set
-# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
-# CONFIG_PC87413_WDT is not set
-CONFIG_PCI=y
-CONFIG_PCI_DIRECT=y
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PCI_IOAPIC is not set
-CONFIG_PCI_LABEL=y
-# CONFIG_PCI_MMCONFIG is not set
-CONFIG_PCI_MSI=y
-CONFIG_PCSPKR_PLATFORM=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PHYSICAL_ALIGN=0x1000000
-CONFIG_PHYSICAL_START=0x1000000
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PNP=y
-CONFIG_PNPACPI=y
-CONFIG_PNP_DEBUG_MESSAGES=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_PROCESSOR_SELECT is not set
-CONFIG_PROC_PAGE_MONITOR=y
-# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
-# CONFIG_PVPANIC is not set
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-# CONFIG_RELOCATABLE is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SAMSUNG_Q10 is not set
-CONFIG_SATA_AHCI=y
-# CONFIG_SBC8360_WDT is not set
-# CONFIG_SBC_EPX_C3_WATCHDOG is not set
-# CONFIG_SC1200_WDT is not set
-# CONFIG_SC520_WDT is not set
-# CONFIG_SCHED_HRTICK is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_VIRTIO=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIO=y
-# CONFIG_SERIO_CT82C710 is not set
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SMSC37B787_WDT is not set
-# CONFIG_SMSC_SCH311X_WDT is not set
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_MANUAL=y
-# CONFIG_SPARSEMEM_VMEMMAP is not set
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_SQUASHFS is not set
-CONFIG_STRICT_DEVMEM=y
-CONFIG_SWIOTLB=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-# CONFIG_TELCLOCK is not set
-CONFIG_THERMAL=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_EMULATION is not set
-# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
-CONFIG_THERMAL_GOV_STEP_WISE=y
-# CONFIG_THERMAL_GOV_USER_SPACE is not set
-# CONFIG_THINKPAD_ACPI is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_TOPSTAR_LAPTOP is not set
-# CONFIG_TOSHIBA_BT_RFKILL is not set
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PCI=y
-# CONFIG_USB_OHCI_HCD_PLATFORM is not set
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_UHCI_HCD=y
-CONFIG_USB_XHCI_HCD=y
-# CONFIG_USER_NS is not set
-CONFIG_USER_STACKTRACE_SUPPORT=y
-CONFIG_VGACON_SOFT_SCROLLBACK=y
-CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64
-CONFIG_VGA_CONSOLE=y
-# CONFIG_VIA_WDT is not set
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_BALLOON=y
-# CONFIG_VIRTIO_BLK is not set
-# CONFIG_VIRTIO_CONSOLE is not set
-CONFIG_VIRTIO_MMIO=y
-# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
-CONFIG_VIRTIO_NET=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VMWARE_BALLOON=y
-CONFIG_VMWARE_PVSCSI=y
-CONFIG_VMWARE_VMCI=y
-CONFIG_VMWARE_VMCI_VSOCKETS=y
-CONFIG_VMXNET3=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VSOCKETS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_W83697UG_WDT is not set
-# CONFIG_WAFER_WDT is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_X86=y
-CONFIG_X86_64=y
-# CONFIG_X86_ACPI_CPUFREQ is not set
-# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set
-CONFIG_X86_CMOV=y
-CONFIG_X86_CMPXCHG64=y
-# CONFIG_X86_CPUID is not set
-CONFIG_X86_DEBUGCTLMSR=y
-CONFIG_X86_DEV_DMA_OPS=y
-# CONFIG_X86_EXTENDED_PLATFORM is not set
-# CONFIG_X86_INTEL_LPSS is not set
-# CONFIG_X86_INTEL_PSTATE is not set
-CONFIG_X86_INTERNODE_CACHE_SHIFT=6
-CONFIG_X86_IO_APIC=y
-CONFIG_X86_L1_CACHE_SHIFT=6
-CONFIG_X86_LOCAL_APIC=y
-CONFIG_X86_MCE=y
-CONFIG_X86_MCE_AMD=y
-# CONFIG_X86_MCE_INJECT is not set
-CONFIG_X86_MCE_INTEL=y
-CONFIG_X86_MCE_THRESHOLD=y
-CONFIG_X86_MINIMUM_CPU_FAMILY=64
-CONFIG_X86_MPPARSE=y
-# CONFIG_X86_MSR is not set
-# CONFIG_X86_P4_CLOCKMOD is not set
-CONFIG_X86_PAT=y
-# CONFIG_X86_PCC_CPUFREQ is not set
-CONFIG_X86_PLATFORM_DEVICES=y
-CONFIG_X86_PM_TIMER=y
-# CONFIG_X86_PTDUMP is not set
-CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
-CONFIG_X86_RESERVE_LOW=64
-# CONFIG_X86_SMAP is not set
-# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
-# CONFIG_X86_SPEEDSTEP_LIB is not set
-CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_X86_THERMAL_VECTOR=y
-CONFIG_X86_TSC=y
-CONFIG_X86_VERBOSE_BOOTUP=y
-# CONFIG_XEN is not set
-# CONFIG_XEN_PRIVILEGED_GUEST is not set
-# CONFIG_XO15_EBOOK is not set
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_X86=y
-# CONFIG_ZBUD is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
+++ /dev/null
-#
-# Copyright (C) 2006-2013 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-export PATH=$(TARGET_PATH):/sbin
-
-GRUB2_MODULES = biosdisk boot chain configfile ext2 linux ls part_msdos reboot serial vga
-GRUB2_MODULES_ISO = biosdisk boot chain configfile iso9660 linux ls part_msdos reboot serial vga
-GRUB_TERMINALS =
-GRUB_SERIAL_CONFIG =
-GRUB_TERMINAL_CONFIG =
-GRUB_CONSOLE_CMDLINE =
-
-USE_ATKBD = generic kvm_guest
-
-ifneq ($(strip $(foreach subtarget,$(USE_ATKBD),$(CONFIG_TARGET_x86_64_$(subtarget)))),)
- GRUB2_MODULES += at_keyboard
- GRUB2_MODULES_ISO += at_keyboard
-endif
-
-ifneq ($(CONFIG_GRUB_CONSOLE),)
- GRUB_CONSOLE_CMDLINE += console=tty0
- GRUB_TERMINALS += console
-endif
-
-GRUB_SERIAL:=$(call qstrip,$(CONFIG_GRUB_SERIAL))
-
-ifneq ($(GRUB_SERIAL),)
- GRUB_CONSOLE_CMDLINE += console=$(GRUB_SERIAL),$(CONFIG_GRUB_BAUDRATE)n8
- GRUB_SERIAL_CONFIG := serial --unit=0 --speed=$(CONFIG_GRUB_BAUDRATE) --word=8 --parity=no --stop=1
- GRUB_TERMINALS += serial
-endif
-
-ifneq ($(GRUB_TERMINALS),)
- GRUB_TERMINAL_CONFIG := terminal_input $(GRUB_TERMINALS); terminal_output $(GRUB_TERMINALS)
-endif
-
-ROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME))
-
-GRUB_TIMEOUT:=$(call qstrip,$(CONFIG_GRUB_TIMEOUT))
-
-ifneq ($(CONFIG_GRUB_IMAGES),)
-
- BOOTOPTS:=$(call qstrip,$(CONFIG_GRUB_BOOTOPTS))
-
- define Image/cmdline/ext4
- root=$(ROOTPART) rootfstype=ext4 rootwait
- endef
-
- define Image/cmdline/jffs2-64k
- block2mtd.block2mtd=$(ROOTPART),65536,rootfs root=/dev/mtdblock0 rootfstype=jffs2 rootwait
- endef
-
- define Image/cmdline/jffs2-128k
- block2mtd.block2mtd=$(ROOTPART),131072,rootfs root=/dev/mtdblock0 rootfstype=jffs2 rootwait
- endef
-
- define Image/cmdline/squashfs
- block2mtd.block2mtd=$(ROOTPART),65536,rootfs root=/dev/mtdblock0 rootfstype=squashfs rootwait
- endef
-
- define Image/Build/grub2
- # left here because the image builder doesnt need these
- $(INSTALL_DIR) $(KDIR)/root.grub/boot/grub $(KDIR)/grub2
- $(CP) $(KDIR)/bzImage $(KDIR)/root.grub/boot/vmlinuz
- grub-mkimage \
- -d $(STAGING_DIR_HOST)/lib/grub/i386-pc \
- -o $(KDIR)/grub2/core.img \
- -O i386-pc \
- -c ./grub-early.cfg \
- $(GRUB2_MODULES)
- $(CP) $(STAGING_DIR_HOST)/lib/grub/i386-pc/*.img $(KDIR)/grub2/
- echo '(hd0) $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1).img' > $(KDIR)/grub2/device.map
- sed \
- -e 's#@SERIAL_CONFIG@#$(strip $(GRUB_SERIAL_CONFIG))#g' \
- -e 's#@TERMINAL_CONFIG@#$(strip $(GRUB_TERMINAL_CONFIG))#g' \
- -e 's#@CMDLINE@#$(strip $(call Image/cmdline/$(1)) $(BOOTOPTS) $(GRUB_CONSOLE_CMDLINE))#g' \
- -e 's#@TIMEOUT@#$(GRUB_TIMEOUT)#g' \
- ./grub.cfg > $(KDIR)/root.grub/boot/grub/grub.cfg
- PADDING="$(CONFIG_TARGET_IMAGES_PAD)" PATH="$(TARGET_PATH)" ./gen_image_generic.sh \
- $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1).img \
- $(CONFIG_TARGET_KERNEL_PARTSIZE) $(KDIR)/root.grub \
- $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(KDIR)/root.$(1) \
- 256
- grub-bios-setup \
- --device-map="$(KDIR)/grub2/device.map" \
- -d "$(KDIR)/grub2" \
- -r "hd0,msdos1" \
- "$(BIN_DIR)/$(IMG_PREFIX)-combined-$(1).img"
- $(call Image/Build/grub/$(1))
- endef
-endif
-
-ROOTDELAY=10
-
-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
-endef
-
-define Image/Build/iso
- $(INSTALL_DIR) $(KDIR)/root.grub/boot/grub $(KDIR)/grub2
- $(CP) $(KDIR)/bzImage $(KDIR)/root.grub/boot/vmlinuz
- grub-mkimage \
- -d $(STAGING_DIR_HOST)/lib/grub/i386-pc \
- -o $(KDIR)/grub2/eltorito.img \
- -O i386-pc \
- -c ./grub-early.cfg \
- $(GRUB2_MODULES_ISO)
- cat \
- $(STAGING_DIR_HOST)/lib/grub/i386-pc/cdboot.img \
- $(KDIR)/grub2/eltorito.img \
- > $(KDIR)/root.grub/boot/grub/eltorito.img
- sed \
- -e 's#@SERIAL_CONFIG@#$(strip $(GRUB_SERIAL_CONFIG))#g' \
- -e 's#@TERMINAL_CONFIG@#$(strip $(GRUB_TERMINAL_CONFIG))#g' \
- -e 's#@CMDLINE@#root=/dev/sr0 rootfstype=iso9660 rootwait $(strip $(call Image/cmdline/$(1)) $(BOOTOPTS) $(GRUB_CONSOLE_CMDLINE))#g' \
- -e 's#@TIMEOUT@#$(GRUB_TIMEOUT)#g' \
- ./grub-iso.cfg > $(KDIR)/root.grub/boot/grub/grub.cfg
- $(CP) $(KDIR)/bzImage $(KDIR)/root.grub/boot/vmlinuz
- mkisofs -R -b boot/grub/eltorito.img -no-emul-boot -boot-info-table \
- -o $(KDIR)/root.iso $(KDIR)/root.grub $(TARGET_DIR)
-endef
-
-ifneq ($(CONFIG_VDI_IMAGES),)
- define Image/Build/vdi
- # left here because the image builder doesnt need these
- ifeq ($(1),ext4)
- rm $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1).vdi || true
- qemu-img convert -f raw -O vdi \
- $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1).img \
- $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1).vdi
- # XXX: VBoxManage insists on setting perms to 0600
- chmod 0644 $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1).vdi
- endif
- endef
-endif
-
-ifneq ($(CONFIG_VMDK_IMAGES),)
- define Image/Build/vmdk
- # left here because the image builder doesnt need these
- ifeq ($(1),ext4)
- rm $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1).vmdk || true
- qemu-img convert -f raw -O vmdk -o adapter_type=lsilogic \
- $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1).img \
- $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1).vmdk
- rm $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1)-esxi.vmdk || true
- qemu-img convert -f raw -O vmdk -o adapter_type=lsilogic,subformat=monolithicFlat \
- $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1).img \
- $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1)-esxi.vmdk
- endif
- endef
-endif
-
-define Image/Build/gzip
- gzip -f9 $(BIN_DIR)/$(IMG_PREFIX)-combined-$(1).img
- gzip -f9 $(BIN_DIR)/$(IMG_PREFIX)-rootfs-$(1).img
-endef
-
-ifneq ($(CONFIG_TARGET_IMAGES_GZIP),)
- define Image/Build/gzip/ext4
- $(call Image/Build/gzip,ext4)
- endef
- ifneq ($(CONFIG_TARGET_IMAGES_PAD),)
- define Image/Build/gzip/squashfs
- $(call Image/Build/gzip,squashfs)
- endef
- define Image/Build/gzip/jffs2-64k
- $(call Image/Build/gzip,jffs2-64k)
- endef
- define Image/Build/gzip/jffs2-128k
- $(call Image/Build/gzip,jffs2-128k)
- endef
- endif
-endif
-
-define Image/BuildKernel
- $(CP) $(KDIR)/bzImage $(BIN_DIR)/$(IMG_PREFIX)-vmlinuz
-endef
-
-define Image/Prepare
- $(CP) $(LINUX_DIR)/arch/x86/boot/bzImage $(KDIR)/bzImage
- $(call Image/Prepare/bootscript)
- $(call Image/Prepare/grub2)
-endef
-
-define Image/Build/Initramfs
- $(CP) $(KDIR)/bzImage-initramfs $(BIN_DIR)/$(IMG_PREFIX)-ramfs.bzImage
-endef
-
-define Image/Build
- $(call Image/Build/$(1))
- $(call Image/Build/bootscript,$(1))
- ifneq ($(1),iso)
- $(call Image/Build/grub2,$(1))
- $(call Image/Build/vdi,$(1))
- $(call Image/Build/vmdk,$(1))
- $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-rootfs-$(1).img
- else
- $(CP) $(KDIR)/root.iso $(BIN_DIR)/$(IMG_PREFIX).iso
- endif
- $(CP) $(KDIR)/bzImage $(BIN_DIR)/$(IMG_PREFIX)-vmlinuz
- $(call Image/Build/gzip/$(1))
- $(call Image/Build/Profile/$(PROFILE),$(1))
-ifeq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),y)
- $(call Image/Build/Initramfs)
-endif
-endef
-
-$(eval $(call BuildImage))
-
-$(eval $(call RequireCommand,qemu-img, \
- Please install qemu-img (package qemu-utils in Ubuntu/Debian). \
-))
+++ /dev/null
-#!/usr/bin/env bash
-# Copyright (C) 2006-2012 OpenWrt.org
-set -x
-[ $# == 5 -o $# == 6 ] || {
- echo "SYNTAX: $0 <file> <kernel size> <kernel directory> <rootfs size> <rootfs image> [<align>]"
- exit 1
-}
-
-OUTPUT="$1"
-KERNELSIZE="$2"
-KERNELDIR="$3"
-ROOTFSSIZE="$4"
-ROOTFSIMAGE="$5"
-ALIGN="$6"
-
-rm -f "$OUTPUT"
-
-head=16
-sect=63
-cyl=$(( ($KERNELSIZE + $ROOTFSSIZE) * 1024 * 1024 / ($head * $sect * 512)))
-
-# create partition table
-set `ptgen -o "$OUTPUT" -h $head -s $sect -p ${KERNELSIZE}m -p ${ROOTFSSIZE}m ${ALIGN:+-l $ALIGN}`
-
-KERNELOFFSET="$(($1 / 512))"
-KERNELSIZE="$(($2 / 512))"
-ROOTFSOFFSET="$(($3 / 512))"
-ROOTFSSIZE="$(($4 / 512))"
-
-BLOCKS="$((($KERNELSIZE / 2) - 1))"
-
-[ -n "$PADDING" ] && dd if=/dev/zero of="$OUTPUT" bs=512 seek="$ROOTFSOFFSET" conv=notrunc count="$ROOTFSSIZE"
-dd if="$ROOTFSIMAGE" of="$OUTPUT" bs=512 seek="$ROOTFSOFFSET" conv=notrunc
-
-[ -n "$NOGRUB" ] && exit 0
-
-genext2fs -d "$KERNELDIR" -b "$BLOCKS" "$OUTPUT.kernel"
-dd if="$OUTPUT.kernel" of="$OUTPUT" bs=512 seek="$KERNELOFFSET" conv=notrunc
-rm -f "$OUTPUT.kernel"
+++ /dev/null
-configfile (hd0,msdos1)/boot/grub/grub.cfg
+++ /dev/null
-@SERIAL_CONFIG@
-@TERMINAL_CONFIG@
-
-set default="0"
-set timeout="@TIMEOUT@"
-set root='(cd)'
-
-menuentry "OpenWrt" {
- linux /boot/vmlinuz @CMDLINE@ noinitrd
-}
+++ /dev/null
-@SERIAL_CONFIG@
-@TERMINAL_CONFIG@
-
-set default="0"
-set timeout="@TIMEOUT@"
-set root='(hd0,msdos1)'
-
-menuentry "OpenWrt" {
- linux /boot/vmlinuz @CMDLINE@ noinitrd
-}
-menuentry "OpenWrt (failsafe)" {
- linux /boot/vmlinuz failsafe=true @CMDLINE@ noinitrd
-}
+++ /dev/null
---- a/scripts/Makefile.lib
-+++ b/scripts/Makefile.lib
-@@ -304,7 +304,7 @@ cmd_bzip2 = (cat $(filter-out FORCE,$^)
-
- quiet_cmd_lzma = LZMA $@
- cmd_lzma = (cat $(filter-out FORCE,$^) | \
-- lzma e -d20 -lc1 -lp2 -pb2 -eos -si -so && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
-+ lzma e -lc8 -eos -si -so && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
- (rm -f $@ ; false)
-
- quiet_cmd_lzo = LZO $@
---- a/arch/x86/include/asm/boot.h
-+++ b/arch/x86/include/asm/boot.h
-@@ -23,7 +23,7 @@
- #error "Invalid value for CONFIG_PHYSICAL_ALIGN"
- #endif
-
--#ifdef CONFIG_KERNEL_BZIP2
-+#if defined(CONFIG_KERNEL_BZIP2) || defined(CONFIG_KERNEL_LZMA)
- #define BOOT_HEAP_SIZE 0x400000
- #else /* !CONFIG_KERNEL_BZIP2 */
-
+++ /dev/null
---- a/drivers/mtd/mtdblock.c
-+++ b/drivers/mtd/mtdblock.c
-@@ -63,7 +63,7 @@ static void erase_callback(struct erase_
- wake_up(wait_q);
- }
-
--static int erase_write (struct mtd_info *mtd, unsigned long pos,
-+int erase_write (struct mtd_info *mtd, unsigned long pos,
- int len, const char *buf)
- {
- struct erase_info erase;
---- a/include/linux/mtd/mtd.h
-+++ b/include/linux/mtd/mtd.h
-@@ -414,6 +414,9 @@ extern void register_mtd_user (struct mt
- extern int unregister_mtd_user (struct mtd_notifier *old);
- void *mtd_kmalloc_up_to(const struct mtd_info *mtd, size_t *size);
-
-+int erase_write (struct mtd_info *mtd, unsigned long pos,
-+ int len, const char *buf);
-+
- void mtd_erase_callback(struct erase_info *instr);
-
- static inline int mtd_is_bitflip(int err) {
projects / 14.07 / openwrt.git / commitdiff