#include <linux/debugfs.h>
#endif
-#define RTL8366S_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
-#define RTL8366S_DRIVER_VER "0.2.2"
+#define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
+#define RTL8366RB_DRIVER_VER "0.2.2"
-#define RTL8366S_PHY_NO_MAX 4
-#define RTL8366S_PHY_PAGE_MAX 7
-#define RTL8366S_PHY_ADDR_MAX 31
+#define RTL8366RB_PHY_NO_MAX 4
+#define RTL8366RB_PHY_PAGE_MAX 7
+#define RTL8366RB_PHY_ADDR_MAX 31
-#define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
-#define RTL8366_CHIP_CTRL_VLAN (1 << 13)
-#define RTL8366_CHIP_CTRL_VLAN_4KTB (1 << 14)
+#define RTL8366RB_CHIP_GLOBAL_CTRL_REG 0x0000
+#define RTL8366RB_CHIP_CTRL_VLAN (1 << 13)
+#define RTL8366RB_CHIP_CTRL_VLAN_4KTB (1 << 14)
/* Switch Global Configuration register */
-#define RTL8366_SGCR 0x0000
-#define RTL8366_SGCR_EN_BC_STORM_CTRL BIT(0)
-#define RTL8366_SGCR_MAX_LENGTH(_x) (_x << 4)
-#define RTL8366_SGCR_MAX_LENGTH_MASK RTL8366_SGCR_MAX_LENGTH(0x3)
-#define RTL8366_SGCR_MAX_LENGTH_1522 RTL8366_SGCR_MAX_LENGTH(0x0)
-#define RTL8366_SGCR_MAX_LENGTH_1536 RTL8366_SGCR_MAX_LENGTH(0x1)
-#define RTL8366_SGCR_MAX_LENGTH_1552 RTL8366_SGCR_MAX_LENGTH(0x2)
-#define RTL8366_SGCR_MAX_LENGTH_9216 RTL8366_SGCR_MAX_LENGTH(0x3)
+#define RTL8366RB_SGCR 0x0000
+#define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
+#define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
+#define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
+#define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
+#define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
+#define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
+#define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
/* Port Enable Control register */
-#define RTL8366_PECR 0x0001
+#define RTL8366RB_PECR 0x0001
/* Switch Security Control registers */
-#define RTL8366_SSCR0 0x0002
-#define RTL8366_SSCR1 0x0003
-#define RTL8366_SSCR2 0x0004
-#define RTL8366_SSCR2_DROP_UNKNOWN_DA BIT(0)
+#define RTL8366RB_SSCR0 0x0002
+#define RTL8366RB_SSCR1 0x0003
+#define RTL8366RB_SSCR2 0x0004
+#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
-#define RTL8366_RESET_CTRL_REG 0x0100
-#define RTL8366_CHIP_CTRL_RESET_HW 1
-#define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
+#define RTL8366RB_RESET_CTRL_REG 0x0100
+#define RTL8366RB_CHIP_CTRL_RESET_HW 1
+#define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
-#define RTL8366S_CHIP_VERSION_CTRL_REG 0x050A
-#define RTL8366S_CHIP_VERSION_MASK 0xf
-#define RTL8366S_CHIP_ID_REG 0x0509
-#define RTL8366S_CHIP_ID_8366 0x5937
+#define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
+#define RTL8366RB_CHIP_VERSION_MASK 0xf
+#define RTL8366RB_CHIP_ID_REG 0x0509
+#define RTL8366RB_CHIP_ID_8366 0x5937
/* PHY registers control */
-#define RTL8366S_PHY_ACCESS_CTRL_REG 0x8000
-#define RTL8366S_PHY_ACCESS_DATA_REG 0x8002
+#define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
+#define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
-#define RTL8366S_PHY_CTRL_READ 1
-#define RTL8366S_PHY_CTRL_WRITE 0
+#define RTL8366RB_PHY_CTRL_READ 1
+#define RTL8366RB_PHY_CTRL_WRITE 0
-#define RTL8366S_PHY_REG_MASK 0x1f
-#define RTL8366S_PHY_PAGE_OFFSET 5
-#define RTL8366S_PHY_PAGE_MASK (0xf << 5)
-#define RTL8366S_PHY_NO_OFFSET 9
-#define RTL8366S_PHY_NO_MASK (0x1f << 9)
+#define RTL8366RB_PHY_REG_MASK 0x1f
+#define RTL8366RB_PHY_PAGE_OFFSET 5
+#define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
+#define RTL8366RB_PHY_NO_OFFSET 9
+#define RTL8366RB_PHY_NO_MASK (0x1f << 9)
/* LED control registers */
-#define RTL8366_LED_BLINKRATE_REG 0x0430
-#define RTL8366_LED_BLINKRATE_BIT 0
-#define RTL8366_LED_BLINKRATE_MASK 0x0007
+#define RTL8366RB_LED_BLINKRATE_REG 0x0430
+#define RTL8366RB_LED_BLINKRATE_BIT 0
+#define RTL8366RB_LED_BLINKRATE_MASK 0x0007
-#define RTL8366_LED_CTRL_REG 0x0431
-#define RTL8366_LED_0_1_CTRL_REG 0x0432
-#define RTL8366_LED_2_3_CTRL_REG 0x0433
+#define RTL8366RB_LED_CTRL_REG 0x0431
+#define RTL8366RB_LED_0_1_CTRL_REG 0x0432
+#define RTL8366RB_LED_2_3_CTRL_REG 0x0433
-#define RTL8366S_MIB_COUNT 33
-#define RTL8366S_GLOBAL_MIB_COUNT 1
-#define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0050
-#define RTL8366S_MIB_COUNTER_BASE 0x1000
-#define RTL8366S_MIB_CTRL_REG 0x13F0
-#define RTL8366S_MIB_CTRL_USER_MASK 0x0FFC
-#define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
-#define RTL8366S_MIB_CTRL_RESET_MASK 0x0001
+#define RTL8366RB_MIB_COUNT 33
+#define RTL8366RB_GLOBAL_MIB_COUNT 1
+#define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
+#define RTL8366RB_MIB_COUNTER_BASE 0x1000
+#define RTL8366RB_MIB_CTRL_REG 0x13F0
+#define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
+#define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
+#define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
+#define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
+#define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
-#define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
-#define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
-#define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
+#define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
+#define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
+ (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
+#define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
+#define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
-#define RTL8366S_PORT_VLAN_CTRL_BASE 0x0063
-#define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
- (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
-#define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
-#define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
+#define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
+#define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
-#define RTL8366S_VLAN_TABLE_READ_BASE 0x018C
-#define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
+#define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
+#define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
+#define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
+#define RTL8366RB_VLAN_MEMCONF_BASE 0x0020
-#define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
-#define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
-#define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
-#define RTL8366S_VLAN_MEMCONF_BASE 0x0020
+#define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
+#define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
+#define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
+#define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
+#define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
+#define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
+#define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
-#define RTL8366S_PORT_LINK_STATUS_BASE 0x0014
-#define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
-#define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
-#define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
-#define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
-#define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
-#define RTL8366S_PORT_STATUS_AN_MASK 0x0080
+#define RTL8366RB_PORT_NUM_CPU 5
+#define RTL8366RB_NUM_PORTS 6
+#define RTL8366RB_NUM_VLANS 16
+#define RTL8366RB_NUM_LEDGROUPS 4
+#define RTL8366RB_NUM_VIDS 4096
+#define RTL8366RB_PRIORITYMAX 7
+#define RTL8366RB_FIDMAX 7
-#define RTL8366_PORT_NUM_CPU 5
-#define RTL8366_NUM_PORTS 6
-#define RTL8366_NUM_VLANS 16
-#define RTL8366_NUM_LEDGROUPS 4
-#define RTL8366_NUM_VIDS 4096
-#define RTL8366S_PRIORITYMAX 7
-#define RTL8366S_FIDMAX 7
+#define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
+#define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
+#define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
+#define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
+#define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
+#define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
-#define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
-#define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
-#define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
-#define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
-#define RTL8366_PORT_5 (1 << 4) /* In userspace port 4 */
+#define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
+ RTL8366RB_PORT_2 | \
+ RTL8366RB_PORT_3 | \
+ RTL8366RB_PORT_4 | \
+ RTL8366RB_PORT_5 | \
+ RTL8366RB_PORT_CPU)
-#define RTL8366_PORT_CPU (1 << 5) /* CPU port */
+#define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
+ RTL8366RB_PORT_2 | \
+ RTL8366RB_PORT_3 | \
+ RTL8366RB_PORT_4 | \
+ RTL8366RB_PORT_5)
-#define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
- RTL8366_PORT_2 | \
- RTL8366_PORT_3 | \
- RTL8366_PORT_4 | \
- RTL8366_PORT_5 | \
- RTL8366_PORT_CPU)
+#define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
+ RTL8366RB_PORT_2 | \
+ RTL8366RB_PORT_3 | \
+ RTL8366RB_PORT_4)
-#define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
- RTL8366_PORT_2 | \
- RTL8366_PORT_3 | \
- RTL8366_PORT_4 | \
- RTL8366_PORT_5)
-
-#define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
- RTL8366_PORT_2 | \
- RTL8366_PORT_3 | \
- RTL8366_PORT_4)
-
-#define RTL8366_PORT_ALL_INTERNAL RTL8366_PORT_CPU
+#define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
struct rtl8366rb {
struct device *parent;
const char *name;
};
-static struct mib_counter rtl8366rb_mib_counters[RTL8366S_MIB_COUNT] = {
+static struct mib_counter rtl8366rb_mib_counters[RTL8366RB_MIB_COUNT] = {
{ 0, 4, "IfInOctets" },
{ 4, 4, "EtherStatsOctets" },
{ 8, 2, "EtherStatsUnderSizePkts" },
int timeout = 10;
u32 data;
- rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
- RTL8366_CHIP_CTRL_RESET_HW);
+ rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
+ RTL8366RB_CHIP_CTRL_RESET_HW);
do {
msleep(1);
- if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
+ if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
return -EIO;
- if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
+ if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
break;
} while (--timeout);
int err;
/* set maximum packet length to 1536 bytes */
- REG_RMW(smi, RTL8366_SGCR, RTL8366_SGCR_MAX_LENGTH_MASK,
- RTL8366_SGCR_MAX_LENGTH_1536);
+ REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
+ RTL8366RB_SGCR_MAX_LENGTH_1536);
/* enable all ports */
- REG_WR(smi, RTL8366_PECR, 0);
+ REG_WR(smi, RTL8366RB_PECR, 0);
/* disable learning for all ports */
- REG_WR(smi, RTL8366_SSCR0, RTL8366_PORT_ALL);
+ REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
/* disable auto ageing for all ports */
- REG_WR(smi, RTL8366_SSCR1, RTL8366_PORT_ALL);
+ REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
/* don't drop packets whose DA has not been learned */
- REG_RMW(smi, RTL8366_SSCR2, RTL8366_SSCR2_DROP_UNKNOWN_DA, 0);
+ REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
return 0;
}
u32 reg;
int ret;
- if (phy_no > RTL8366S_PHY_NO_MAX)
+ if (phy_no > RTL8366RB_PHY_NO_MAX)
return -EINVAL;
- if (page > RTL8366S_PHY_PAGE_MAX)
+ if (page > RTL8366RB_PHY_PAGE_MAX)
return -EINVAL;
- if (addr > RTL8366S_PHY_ADDR_MAX)
+ if (addr > RTL8366RB_PHY_ADDR_MAX)
return -EINVAL;
- ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
- RTL8366S_PHY_CTRL_READ);
+ ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
+ RTL8366RB_PHY_CTRL_READ);
if (ret)
return ret;
- reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
- ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
- (addr & RTL8366S_PHY_REG_MASK);
+ reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
+ ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
+ (addr & RTL8366RB_PHY_REG_MASK);
ret = rtl8366_smi_write_reg(smi, reg, 0);
if (ret)
return ret;
- ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
+ ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
if (ret)
return ret;
u32 reg;
int ret;
- if (phy_no > RTL8366S_PHY_NO_MAX)
+ if (phy_no > RTL8366RB_PHY_NO_MAX)
return -EINVAL;
- if (page > RTL8366S_PHY_PAGE_MAX)
+ if (page > RTL8366RB_PHY_PAGE_MAX)
return -EINVAL;
- if (addr > RTL8366S_PHY_ADDR_MAX)
+ if (addr > RTL8366RB_PHY_ADDR_MAX)
return -EINVAL;
- ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
- RTL8366S_PHY_CTRL_WRITE);
+ ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
+ RTL8366RB_PHY_CTRL_WRITE);
if (ret)
return ret;
- reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
- ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
- (addr & RTL8366S_PHY_REG_MASK);
+ reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
+ ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
+ (addr & RTL8366RB_PHY_REG_MASK);
ret = rtl8366_smi_write_reg(smi, reg, data);
if (ret)
u32 addr, data;
u64 mibvalue;
- if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
+ if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
return -EINVAL;
- addr = RTL8366S_MIB_COUNTER_BASE +
- RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
+ addr = RTL8366RB_MIB_COUNTER_BASE +
+ RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
rtl8366rb_mib_counters[counter].offset;
/*
return err;
/* read MIB control register */
- err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
+ err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
if (err)
return err;
- if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
+ if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
return -EBUSY;
- if (data & RTL8366S_MIB_CTRL_RESET_MASK)
+ if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
return -EIO;
mibvalue = 0;
memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
vlan4k_priv.vid = vid;
- if (vid >= RTL8366_NUM_VIDS)
+ if (vid >= RTL8366RB_NUM_VIDS)
return -EINVAL;
tableaddr = (u16 *)&vlan4k_priv;
/* write VID */
data = *tableaddr;
- err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
+ err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
if (err)
return err;
/* write table access control word */
- err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
- RTL8366S_TABLE_VLAN_READ_CTRL);
+ err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
+ RTL8366RB_TABLE_VLAN_READ_CTRL);
if (err)
return err;
- err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
+ err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data);
if (err)
return err;
*tableaddr = data;
tableaddr++;
- err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
+ err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1,
&data);
if (err)
return err;
*tableaddr = data;
tableaddr++;
- err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 2,
+ err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2,
&data);
if (err)
return err;
u32 data;
u16 *tableaddr;
- if (vlan4k->vid >= RTL8366_NUM_VIDS ||
- vlan4k->member > RTL8366_PORT_ALL ||
- vlan4k->untag > RTL8366_PORT_ALL ||
- vlan4k->fid > RTL8366S_FIDMAX)
+ if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
+ vlan4k->member > RTL8366RB_PORT_ALL ||
+ vlan4k->untag > RTL8366RB_PORT_ALL ||
+ vlan4k->fid > RTL8366RB_FIDMAX)
return -EINVAL;
vlan4k_priv.vid = vlan4k->vid;
data = *tableaddr;
- err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
+ err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
if (err)
return err;
data = *tableaddr;
- err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
+ err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1,
data);
if (err)
return err;
data = *tableaddr;
- err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 2,
+ err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2,
data);
if (err)
return err;
/* write table access control word */
- err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
- RTL8366S_TABLE_VLAN_WRITE_CTRL);
+ err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
+ RTL8366RB_TABLE_VLAN_WRITE_CTRL);
return err;
}
memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
- if (index >= RTL8366_NUM_VLANS)
+ if (index >= RTL8366RB_NUM_VLANS)
return -EINVAL;
tableaddr = (u16 *)&vlanmc_priv;
- addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
+ addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
err = rtl8366_smi_read_reg(smi, addr, &data);
if (err)
return err;
*tableaddr = data;
tableaddr++;
- addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
+ addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
err = rtl8366_smi_read_reg(smi, addr, &data);
if (err)
return err;
*tableaddr = data;
tableaddr++;
- addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
+ addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
err = rtl8366_smi_read_reg(smi, addr, &data);
if (err)
return err;
u32 data;
u16 *tableaddr;
- if (index >= RTL8366_NUM_VLANS ||
- vlanmc->vid >= RTL8366_NUM_VIDS ||
- vlanmc->priority > RTL8366S_PRIORITYMAX ||
- vlanmc->member > RTL8366_PORT_ALL ||
- vlanmc->untag > RTL8366_PORT_ALL ||
- vlanmc->fid > RTL8366S_FIDMAX)
+ if (index >= RTL8366RB_NUM_VLANS ||
+ vlanmc->vid >= RTL8366RB_NUM_VIDS ||
+ vlanmc->priority > RTL8366RB_PRIORITYMAX ||
+ vlanmc->member > RTL8366RB_PORT_ALL ||
+ vlanmc->untag > RTL8366RB_PORT_ALL ||
+ vlanmc->fid > RTL8366RB_FIDMAX)
return -EINVAL;
vlanmc_priv.vid = vlanmc->vid;
vlanmc_priv.stag_idx = 0;
vlanmc_priv.fid = vlanmc->fid;
- addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
+ addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
tableaddr = (u16 *)&vlanmc_priv;
data = *tableaddr;
if (err)
return err;
- addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
+ addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
tableaddr++;
data = *tableaddr;
if (err)
return err;
- addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
+ addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
tableaddr++;
data = *tableaddr;
return 0;
}
-static int rtl8366rb_get_port_vlan_index(struct rtl8366_smi *smi, int port,
- int *val)
+static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
{
u32 data;
int err;
- if (port >= RTL8366_NUM_PORTS)
+ if (port >= RTL8366RB_NUM_PORTS)
return -EINVAL;
- err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
+ err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
&data);
if (err)
return err;
- *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
- RTL8366S_PORT_VLAN_CTRL_MASK;
+ *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
+ RTL8366RB_PORT_VLAN_CTRL_MASK;
return 0;
}
-static int rtl8366rb_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
- int *val)
+static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
+{
+ if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
+ return -EINVAL;
+
+ return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
+ RTL8366RB_PORT_VLAN_CTRL_MASK <<
+ RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
+ (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
+ RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
+}
+
+static int rtl8366rb_set_vlan(struct rtl8366_smi *smi, int vid, u32 member,
+ u32 untag, u32 fid)
+{
+ struct rtl8366_vlan_4k vlan4k;
+ int err;
+ int i;
+
+ /* Update the 4K table */
+ err = smi->ops->get_vlan_4k(smi, vid, &vlan4k);
+ if (err)
+ return err;
+
+ vlan4k.member = member;
+ vlan4k.untag = untag;
+ vlan4k.fid = fid;
+ err = smi->ops->set_vlan_4k(smi, &vlan4k);
+ if (err)
+ return err;
+
+ /* Try to find an existing MC entry for this VID */
+ for (i = 0; i < smi->num_vlan_mc; i++) {
+ struct rtl8366_vlan_mc vlanmc;
+
+ err = smi->ops->get_vlan_mc(smi, i, &vlanmc);
+ if (err)
+ return err;
+
+ if (vid == vlanmc.vid) {
+ /* update the MC entry */
+ vlanmc.member = member;
+ vlanmc.untag = untag;
+ vlanmc.fid = fid;
+
+ err = smi->ops->set_vlan_mc(smi, i, &vlanmc);
+ break;
+ }
+ }
+
+ return err;
+}
+
+static int rtl8366rb_get_pvid(struct rtl8366_smi *smi, int port, int *val)
{
struct rtl8366_vlan_mc vlanmc;
int err;
int index;
- err = rtl8366rb_get_port_vlan_index(smi, port, &index);
+ err = smi->ops->get_mc_index(smi, port, &index);
if (err)
return err;
- err = rtl8366rb_get_vlan_mc(smi, index, &vlanmc);
+ err = smi->ops->get_vlan_mc(smi, index, &vlanmc);
if (err)
return err;
return 0;
}
-static int rtl8366rb_set_port_vlan_index(struct rtl8366_smi *smi, int port,
- int index)
+static int rtl8366rb_mc_is_used(struct rtl8366_smi *smi, int mc_index,
+ int *used)
{
- if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
- return -EINVAL;
+ int err;
+ int i;
- return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
- RTL8366S_PORT_VLAN_CTRL_MASK <<
- RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
- (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
- RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
+ *used = 0;
+ for (i = 0; i < smi->num_ports; i++) {
+ int index = 0;
+
+ err = smi->ops->get_mc_index(smi, i, &index);
+ if (err)
+ return err;
+
+ if (mc_index == index) {
+ *used = 1;
+ break;
+ }
+ }
+
+ return 0;
}
-static int rtl8366rb_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
- int val)
+static int rtl8366rb_set_pvid(struct rtl8366_smi *smi, unsigned port,
+ unsigned vid)
{
- int i;
struct rtl8366_vlan_mc vlanmc;
struct rtl8366_vlan_4k vlan4k;
+ int err;
+ int i;
- if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
- return -EINVAL;
-
- /* Updating the 4K entry; lookup it and change the port member set */
- rtl8366rb_get_vlan_4k(smi, val, &vlan4k);
- vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
- vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
- rtl8366rb_set_vlan_4k(smi, &vlan4k);
-
- /*
- * For the 16 entries more work needs to be done. First see if such
- * VID is already there and change it
- */
- for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
- rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
-
- /* Try to find an existing vid and update port member set */
- if (val == vlanmc.vid) {
- vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
- rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
+ /* Try to find an existing MC entry for this VID */
+ for (i = 0; i < smi->num_vlan_mc; i++) {
+ err = smi->ops->get_vlan_mc(smi, i, &vlanmc);
+ if (err)
+ return err;
- /* Now update PVID register settings */
- rtl8366rb_set_port_vlan_index(smi, port, i);
+ if (vid == vlanmc.vid) {
+ err = smi->ops->set_vlan_mc(smi, i, &vlanmc);
+ if (err)
+ return err;
- return 0;
+ err = smi->ops->set_mc_index(smi, port, i);
+ return err;
}
}
- /*
- * PVID could not be found from vlan table. Replace unused (one that
- * has no member ports) with new one
- */
- for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
- rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
+ /* We have no MC entry for this VID, try to find an empty one */
+ for (i = 0; i < smi->num_vlan_mc; i++) {
+ err = smi->ops->get_vlan_mc(smi, i, &vlanmc);
+ if (err)
+ return err;
- /*
- * See if this vlan member configuration is unused. It is
- * unused if member set contains no ports or CPU port only
- */
- if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
- vlanmc.vid = val;
- vlanmc.priority = 0;
- vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
- vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
- vlanmc.fid = 0;
+ if (vlanmc.vid == 0 && vlanmc.member == 0) {
+ /* Update the entry from the 4K table */
+ err = smi->ops->get_vlan_4k(smi, vid, &vlan4k);
+ if (err)
+ return err;
+
+ vlanmc.vid = vid;
+ vlanmc.member = vlan4k.member;
+ vlanmc.untag = vlan4k.untag;
+ vlanmc.fid = vlan4k.fid;
+ err = smi->ops->set_vlan_mc(smi, i, &vlanmc);
+ if (err)
+ return err;
+
+ err = smi->ops->set_mc_index(smi, port, i);
+ return err;
+ }
+ }
- rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
+ /* MC table is full, try to find an unused entry and replace it */
+ for (i = 0; i < smi->num_vlan_mc; i++) {
+ int used;
- /* Now update PVID register settings */
- rtl8366rb_set_port_vlan_index(smi, port, i);
+ err = rtl8366rb_mc_is_used(smi, i, &used);
+ if (err)
+ return err;
- return 0;
+ if (!used) {
+ /* Update the entry from the 4K table */
+ err = smi->ops->get_vlan_4k(smi, vid, &vlan4k);
+ if (err)
+ return err;
+
+ vlanmc.vid = vid;
+ vlanmc.member = vlan4k.member;
+ vlanmc.untag = vlan4k.untag;
+ vlanmc.fid = vlan4k.fid;
+ err = smi->ops->set_vlan_mc(smi, i, &vlanmc);
+ if (err)
+ return err;
+
+ err = smi->ops->set_mc_index(smi, port, i);
+ return err;
}
}
dev_err(smi->parent,
- "All 16 vlan member configurations are in use\n");
+ "all VLAN member configurations are in use\n");
- return -EINVAL;
+ return -ENOSPC;
}
-
static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
{
- return rtl8366_smi_rmwr(smi, RTL8366_CHIP_GLOBAL_CTRL_REG,
- RTL8366_CHIP_CTRL_VLAN,
- (enable) ? RTL8366_CHIP_CTRL_VLAN : 0);
+ return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
+ RTL8366RB_CHIP_CTRL_VLAN,
+ (enable) ? RTL8366RB_CHIP_CTRL_VLAN : 0);
}
static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
{
- return rtl8366_smi_rmwr(smi, RTL8366_CHIP_GLOBAL_CTRL_REG,
- RTL8366_CHIP_CTRL_VLAN_4KTB,
- (enable) ? RTL8366_CHIP_CTRL_VLAN_4KTB : 0);
+ return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
+ RTL8366RB_CHIP_CTRL_VLAN_4KTB,
+ (enable) ? RTL8366RB_CHIP_CTRL_VLAN_4KTB : 0);
}
static int rtl8366rb_reset_vlan(struct rtl8366_smi *smi)
{
- struct rtl8366_vlan_4k vlan4k;
struct rtl8366_vlan_mc vlanmc;
int err;
int i;
- /* clear 16 VLAN member configuration */
+ /* clear VLAN member configurations */
vlanmc.vid = 0;
vlanmc.priority = 0;
vlanmc.member = 0;
vlanmc.untag = 0;
vlanmc.fid = 0;
- for (i = 0; i < RTL8366_NUM_VLANS; i++) {
- err = rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
+ for (i = 0; i < smi->num_vlan_mc; i++) {
+ err = smi->ops->set_vlan_mc(smi, i, &vlanmc);
if (err)
return err;
}
- /* Set a default VLAN with vid 1 to 4K table for all ports */
- vlan4k.vid = 1;
- vlan4k.member = RTL8366_PORT_ALL;
- vlan4k.untag = RTL8366_PORT_ALL;
- vlan4k.fid = 0;
- err = rtl8366rb_set_vlan_4k(smi, &vlan4k);
- if (err)
- return err;
+ for (i = 0; i < smi->num_ports; i++) {
+ if (i == smi->cpu_port)
+ continue;
- /* Set all ports PVID to default VLAN */
- for (i = 0; i < RTL8366_NUM_PORTS; i++) {
- err = rtl8366rb_set_vlan_port_pvid(smi, i, 0);
+ err = rtl8366rb_set_vlan(smi, (i + 1),
+ (1 << i) | (1 << smi->cpu_port),
+ (1 << i) | (1 << smi->cpu_port),
+ 0);
+ if (err)
+ return err;
+
+ err = rtl8366rb_set_pvid(smi, i, (i + 1));
if (err)
return err;
}
for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ",
rtl8366rb_mib_counters[i].name);
- for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
+ for (j = 0; j < RTL8366RB_NUM_PORTS; ++j) {
unsigned long long counter = 0;
if (!rtl8366_get_mib_counter(smi, i, j, &counter))
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
}
-static ssize_t rtl8366rb_read_debugfs_vlan(struct file *file,
- char __user *user_buf,
- size_t count, loff_t *ppos)
+static ssize_t rtl8366rb_read_debugfs_vlan_mc(struct file *file,
+ char __user *user_buf,
+ size_t count, loff_t *ppos)
{
struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
struct rtl8366_smi *smi = &rtl->smi;
- int i, j, len = 0;
+ int i, len = 0;
char *buf = rtl->buf;
len += snprintf(buf + len, sizeof(rtl->buf) - len,
- "VLAN Member Config:\n");
- len += snprintf(buf + len, sizeof(rtl->buf) - len,
- "\t id \t vid \t prio \t member \t untag \t fid "
- "\tports\n");
+ "%2s %6s %4s %6s %6s %3s\n",
+ "id", "vid","prio", "member", "untag", "fid");
- for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
+ for (i = 0; i < RTL8366RB_NUM_VLANS; ++i) {
struct rtl8366_vlan_mc vlanmc;
rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
len += snprintf(buf + len, sizeof(rtl->buf) - len,
- "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
- "\t", i, vlanmc.vid, vlanmc.priority,
+ "%2d %6d %4d 0x%04x 0x%04x %3d\n",
+ i, vlanmc.vid, vlanmc.priority,
vlanmc.member, vlanmc.untag, vlanmc.fid);
-
- for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
- int index = 0;
- if (!rtl8366rb_get_port_vlan_index(smi, j, &index)) {
- if (index == i)
- len += snprintf(buf + len,
- sizeof(rtl->buf) - len,
- "%d", j);
- }
- }
- len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
}
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
.owner = THIS_MODULE
};
-static const struct file_operations fops_rtl8366rb_vlan = {
- .read = rtl8366rb_read_debugfs_vlan,
+static const struct file_operations fops_rtl8366rb_vlan_mc = {
+ .read = rtl8366rb_read_debugfs_vlan_mc,
.open = rtl8366rb_debugfs_open,
.owner = THIS_MODULE
};
return;
}
- node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
- &fops_rtl8366rb_vlan);
+ node = debugfs_create_file("vlan_mc", S_IRUSR, root, rtl,
+ &fops_rtl8366rb_vlan_mc);
if (!node) {
dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
- "vlan");
+ "vlan_mc");
return;
}
int err = 0;
if (val->value.i == 1)
- err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
+ err = rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
+ RTL8366RB_MIB_CTRL_GLOBAL_RESET);
return err;
}
u32 data;
if (attr->ofs == 1) {
- rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
+ rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
- if (data & RTL8366_CHIP_CTRL_VLAN)
+ if (data & RTL8366RB_CHIP_CTRL_VLAN)
val->value.i = 1;
else
val->value.i = 0;
} else if (attr->ofs == 2) {
- rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
+ rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
- if (data & RTL8366_CHIP_CTRL_VLAN_4KTB)
+ if (data & RTL8366RB_CHIP_CTRL_VLAN_4KTB)
val->value.i = 1;
else
val->value.i = 0;
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
u32 data;
- rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
+ rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
- val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
+ val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
return 0;
}
if (val->value.i >= 6)
return -EINVAL;
- return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG,
- RTL8366_LED_BLINKRATE_MASK,
+ return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
+ RTL8366RB_LED_BLINKRATE_MASK,
val->value.i);
}
struct rtl8366_smi *smi = &rtl->smi;
u32 len = 0, data = 0;
- if (val->port_vlan >= RTL8366_NUM_PORTS)
+ if (val->port_vlan >= RTL8366RB_NUM_PORTS)
return -EINVAL;
memset(rtl->buf, '\0', sizeof(rtl->buf));
- rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
+ rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
(val->port_vlan / 2), &data);
if (val->port_vlan % 2)
data = data >> 8;
- if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
+ if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
len = snprintf(rtl->buf, sizeof(rtl->buf),
"port:%d link:up speed:%s %s-duplex %s%s%s",
val->port_vlan,
rtl8366rb_speed_str(data &
- RTL8366S_PORT_STATUS_SPEED_MASK),
- (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
+ RTL8366RB_PORT_STATUS_SPEED_MASK),
+ (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
"full" : "half",
- (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
+ (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
"tx-pause ": "",
- (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
+ (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
"rx-pause " : "",
- (data & RTL8366S_PORT_STATUS_AN_MASK) ?
+ (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
"nway ": "");
} else {
len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
{
int i;
u32 len = 0;
- struct rtl8366_vlan_mc vlanmc;
struct rtl8366_vlan_4k vlan4k;
struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
struct rtl8366_smi *smi = &rtl->smi;
char *buf = rtl->buf;
+ int err;
- if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
+ if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
return -EINVAL;
memset(buf, '\0', sizeof(rtl->buf));
- rtl8366rb_get_vlan_mc(smi, val->port_vlan, &vlanmc);
- rtl8366rb_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
+ err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
+ if (err)
+ return err;
- len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
- val->port_vlan);
+ len += snprintf(buf + len, sizeof(rtl->buf) - len,
+ "VLAN %d: Ports: '", vlan4k.vid);
- for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
- int index = 0;
- if (!rtl8366rb_get_port_vlan_index(smi, i, &index) &&
- index == val->port_vlan)
- len += snprintf(buf + len, sizeof(rtl->buf) - len,
- "%d", i);
+ for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
+ if (!(vlan4k.member & (1 << i)))
+ continue;
+
+ len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d%s", i,
+ (vlan4k.untag & (1 << i)) ? "" : "t");
}
- len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
len += snprintf(buf + len, sizeof(rtl->buf) - len,
- "\t\t vid \t prio \t member \t untag \t fid\n");
- len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
- len += snprintf(buf + len, sizeof(rtl->buf) - len,
- "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
- vlanmc.vid, vlanmc.priority, vlanmc.member,
- vlanmc.untag, vlanmc.fid);
- len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
- len += snprintf(buf + len, sizeof(rtl->buf) - len,
- "%d \t \t 0x%04x \t 0x%04x \t %d",
- vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
+ "', members=%04x, untag=%04x, fid=%u",
+ vlan4k.member, vlan4k.untag, vlan4k.fid);
val->value.s = buf;
val->len = len;
u32 mask;
u32 reg;
- if (val->port_vlan >= RTL8366_NUM_PORTS)
+ if (val->port_vlan >= RTL8366RB_NUM_PORTS)
return -EINVAL;
- if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
- reg = RTL8366_LED_BLINKRATE_REG;
+ if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
+ reg = RTL8366RB_LED_BLINKRATE_REG;
mask = 0xF << 4;
data = val->value.i << 4;
} else {
- reg = RTL8366_LED_CTRL_REG;
+ reg = RTL8366RB_LED_CTRL_REG;
mask = 0xF << (val->port_vlan * 4),
data = val->value.i << (val->port_vlan * 4);
}
- return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG, mask, data);
+ return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
}
static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
u32 data = 0;
- if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
+ if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
return -EINVAL;
- rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
+ rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
return 0;
{
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
- if (val->port_vlan >= RTL8366_NUM_PORTS)
+ if (val->port_vlan >= RTL8366RB_NUM_PORTS)
return -EINVAL;
- return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
- 0, (1 << (val->port_vlan + 3)));
+ return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
+ RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
}
static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
unsigned long long counter = 0;
char *buf = rtl->buf;
- if (val->port_vlan >= RTL8366_NUM_PORTS)
+ if (val->port_vlan >= RTL8366RB_NUM_PORTS)
return -EINVAL;
len += snprintf(buf + len, sizeof(rtl->buf) - len,
static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
struct switch_val *val)
{
- struct rtl8366_vlan_mc vlanmc;
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
struct switch_port *port;
+ struct rtl8366_vlan_4k vlan4k;
int i;
- if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
+ if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
return -EINVAL;
- rtl8366rb_get_vlan_mc(smi, val->port_vlan, &vlanmc);
+ rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
port = &val->value.ports[0];
val->len = 0;
- for (i = 0; i < RTL8366_NUM_PORTS; i++) {
- if (!(vlanmc.member & BIT(i)))
+ for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
+ if (!(vlan4k.member & BIT(i)))
continue;
port->id = i;
- port->flags = (vlanmc.untag & BIT(i)) ?
+ port->flags = (vlan4k.untag & BIT(i)) ?
0 : BIT(SWITCH_PORT_FLAG_TAGGED);
val->len++;
port++;
static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
struct switch_val *val)
{
- struct rtl8366_vlan_mc vlanmc;
- struct rtl8366_vlan_4k vlan4k;
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
struct switch_port *port;
+ u32 member = 0;
+ u32 untag = 0;
int i;
- if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
+ if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
return -EINVAL;
- rtl8366rb_get_vlan_mc(smi, val->port_vlan, &vlanmc);
- rtl8366rb_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
-
- vlanmc.untag = 0;
- vlanmc.member = 0;
-
port = &val->value.ports[0];
for (i = 0; i < val->len; i++, port++) {
- vlanmc.member |= BIT(port->id);
+ member |= BIT(port->id);
if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
- vlanmc.untag |= BIT(port->id);
+ untag |= BIT(port->id);
}
- vlan4k.member = vlanmc.member;
- vlan4k.untag = vlanmc.untag;
-
- rtl8366rb_set_vlan_mc(smi, val->port_vlan, &vlanmc);
- rtl8366rb_set_vlan_4k(smi, &vlan4k);
- return 0;
+ return rtl8366rb_set_vlan(smi, val->port_vlan, member, untag, 0);
}
static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
{
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
- return rtl8366rb_get_vlan_port_pvid(smi, port, val);
+ return rtl8366rb_get_pvid(smi, port, val);
}
static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
{
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
- return rtl8366rb_set_vlan_port_pvid(smi, port, val);
+ return rtl8366rb_set_pvid(smi, port, val);
}
static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
/* template */
static struct switch_dev rtl8366_switch_dev = {
.name = "RTL8366S",
- .cpu_port = RTL8366_PORT_NUM_CPU,
- .ports = RTL8366_NUM_PORTS,
- .vlans = RTL8366_NUM_VLANS,
+ .cpu_port = RTL8366RB_PORT_NUM_CPU,
+ .ports = RTL8366RB_NUM_PORTS,
+ .vlans = RTL8366RB_NUM_VLANS,
.attr_global = {
.attr = rtl8366rb_globals,
.n_attr = ARRAY_SIZE(rtl8366rb_globals),
u32 chip_ver = 0;
int ret;
- ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
+ ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
if (ret) {
dev_err(smi->parent, "unable to read chip id\n");
return ret;
}
switch (chip_id) {
- case RTL8366S_CHIP_ID_8366:
+ case RTL8366RB_CHIP_ID_8366:
break;
default:
dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
return -ENODEV;
}
- ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
+ ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
&chip_ver);
if (ret) {
dev_err(smi->parent, "unable to read chip version\n");
}
dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
- chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
+ chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
return 0;
}
.detect = rtl8366rb_detect,
.mii_read = rtl8366rb_mii_read,
.mii_write = rtl8366rb_mii_write,
+
+ .get_vlan_mc = rtl8366rb_get_vlan_mc,
+ .set_vlan_mc = rtl8366rb_set_vlan_mc,
+ .get_vlan_4k = rtl8366rb_get_vlan_4k,
+ .set_vlan_4k = rtl8366rb_set_vlan_4k,
+ .get_mc_index = rtl8366rb_get_mc_index,
+ .set_mc_index = rtl8366rb_set_mc_index,
};
static int __init rtl8366rb_probe(struct platform_device *pdev)
int err;
if (!rtl8366_smi_version_printed++)
- printk(KERN_NOTICE RTL8366S_DRIVER_DESC
- " version " RTL8366S_DRIVER_VER"\n");
+ printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
+ " version " RTL8366RB_DRIVER_VER"\n");
pdata = pdev->dev.platform_data;
if (!pdata) {
smi->gpio_sda = pdata->gpio_sda;
smi->gpio_sck = pdata->gpio_sck;
smi->ops = &rtl8366rb_smi_ops;
+ smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
+ smi->num_ports = RTL8366RB_NUM_PORTS;
+ smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
err = rtl8366_smi_init(smi);
if (err)
}
module_exit(rtl8366rb_module_exit);
-MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
-MODULE_VERSION(RTL8366S_DRIVER_VER);
+MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
+MODULE_VERSION(RTL8366RB_DRIVER_VER);
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
MODULE_LICENSE("GPL v2");
projects / 10.03 / openwrt.git / blobdiff