target/linux/xburst/files-2.6.32/drivers/mmc/host/jz_mmc.c

   1 /*
   2  *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
   3  *      JZ7420/JZ4740 GPIO SD/MMC controller driver
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  You should have received a copy of the  GNU General Public License along
  11  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  12  *  675 Mass Ave, Cambridge, MA 02139, USA.
  13  *
  14  */
  15
  16 #include <linux/mmc/host.h>
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/delay.h>
  23 #include <linux/scatterlist.h>
  24 #include <linux/clk.h>
  25 #include <linux/mmc/jz4740_mmc.h>
  26
  27 #include <linux/gpio.h>
  28 #include <asm/mach-jz4740/gpio.h>
  29 #include <asm/cacheflush.h>
  30 #include <linux/dma-mapping.h>
  31
  32 #define JZ_REG_MMC_STRPCL       0x00
  33 #define JZ_REG_MMC_STATUS       0x04
  34 #define JZ_REG_MMC_CLKRT        0x08
  35 #define JZ_REG_MMC_CMDAT        0x0C
  36 #define JZ_REG_MMC_RESTO        0x10
  37 #define JZ_REG_MMC_RDTO         0x14
  38 #define JZ_REG_MMC_BLKLEN       0x18
  39 #define JZ_REG_MMC_NOB          0x1C
  40 #define JZ_REG_MMC_SNOB         0x20
  41 #define JZ_REG_MMC_IMASK        0x24
  42 #define JZ_REG_MMC_IREG         0x28
  43 #define JZ_REG_MMC_CMD          0x2C
  44 #define JZ_REG_MMC_ARG          0x30
  45 #define JZ_REG_MMC_RESP_FIFO    0x34
  46 #define JZ_REG_MMC_RXFIFO       0x38
  47 #define JZ_REG_MMC_TXFIFO       0x3C
  48
  49 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
  50 #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
  51 #define JZ_MMC_STRPCL_START_READWAIT BIT(5)
  52 #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
  53 #define JZ_MMC_STRPCL_RESET BIT(3)
  54 #define JZ_MMC_STRPCL_START_OP BIT(2)
  55 #define JZ_MMC_STRPCL_CLOCK_CONTROL BIT(1) | BIT(0)
  56 #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
  57 #define JZ_MMC_STRPCL_CLOCK_START BIT(1)
  58
  59
  60 #define JZ_MMC_STATUS_IS_RESETTING BIT(15)
  61 #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
  62 #define JZ_MMC_STATUS_PRG_DONE BIT(13)
  63 #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
  64 #define JZ_MMC_STATUS_END_CMD_RES BIT(11)
  65 #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
  66 #define JZ_MMC_STATUS_IS_READWAIT BIT(9)
  67 #define JZ_MMC_STATUS_CLK_EN BIT(8)
  68 #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
  69 #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
  70 #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
  71 #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
  72 #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
  73 #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
  74 #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
  75 #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
  76
  77 #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
  78 #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
  79
  80
  81 #define JZ_MMC_CMDAT_IO_ABORT BIT(11)
  82 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
  83 #define JZ_MMC_CMDAT_DMA_EN BIT(8)
  84 #define JZ_MMC_CMDAT_INIT BIT(7)
  85 #define JZ_MMC_CMDAT_BUSY BIT(6)
  86 #define JZ_MMC_CMDAT_STREAM BIT(5)
  87 #define JZ_MMC_CMDAT_WRITE BIT(4)
  88 #define JZ_MMC_CMDAT_DATA_EN BIT(3)
  89 #define JZ_MMC_CMDAT_RESPONSE_FORMAT BIT(2) | BIT(1) | BIT(0)
  90 #define JZ_MMC_CMDAT_RSP_R1 1
  91 #define JZ_MMC_CMDAT_RSP_R2 2
  92 #define JZ_MMC_CMDAT_RSP_R3 3
  93
  94 #define JZ_MMC_IRQ_SDIO BIT(7)
  95 #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
  96 #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
  97 #define JZ_MMC_IRQ_END_CMD_RES BIT(2)
  98 #define JZ_MMC_IRQ_PRG_DONE BIT(1)
  99 #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
 100
 101
 102 #define JZ_MMC_CLK_RATE 24000000
 103
 104 struct jz4740_mmc_host {
 105         struct mmc_host *mmc;
 106         struct platform_device *pdev;
 107         struct jz4740_mmc_platform_data *pdata;
 108         struct clk *clk;
 109
 110         int irq;
 111         int card_detect_irq;
 112
 113         struct resource *mem;
 114         void __iomem *base;
 115         struct mmc_request *req;
 116         struct mmc_command *cmd;
 117
 118         int max_clock;
 119         uint32_t cmdat;
 120
 121         uint16_t irq_mask;
 122
 123         spinlock_t lock;
 124         struct timer_list clock_timer;
 125         struct timer_list timeout_timer;
 126         unsigned waiting:1;
 127 };
 128
 129 static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host);
 130
 131 static void jz4740_mmc_enable_irq(struct jz4740_mmc_host *host, unsigned int irq)
 132 {
 133         unsigned long flags;
 134         spin_lock_irqsave(&host->lock, flags);
 135
 136         host->irq_mask &= ~irq;
 137         writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
 138
 139         spin_unlock_irqrestore(&host->lock, flags);
 140 }
 141
 142 static void jz4740_mmc_disable_irq(struct jz4740_mmc_host *host, unsigned int irq)
 143 {
 144         unsigned long flags;
 145         spin_lock_irqsave(&host->lock, flags);
 146
 147         host->irq_mask |= irq;
 148         writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
 149
 150         spin_unlock_irqrestore(&host->lock, flags);
 151 }
 152
 153 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, bool start_transfer)
 154 {
 155         uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
 156
 157         if (start_transfer)
 158                 val |= JZ_MMC_STRPCL_START_OP;
 159
 160         writew(val, host->base + JZ_REG_MMC_STRPCL);
 161 }
 162
 163 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
 164 {
 165         uint16_t status;
 166         writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
 167         do {
 168                 status = readl(host->base + JZ_REG_MMC_STATUS);
 169         } while (status & JZ_MMC_STATUS_CLK_EN);
 170
 171 }
 172
 173 static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
 174 {
 175         writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
 176         udelay(10);
 177         while(readw(host->base + JZ_REG_MMC_STATUS) & JZ_MMC_STATUS_IS_RESETTING);
 178 }
 179
 180 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
 181 {
 182         struct mmc_request *req;
 183         unsigned long flags;
 184
 185         spin_lock_irqsave(&host->lock, flags);
 186         req = host->req;
 187         host->req = NULL;
 188         host->waiting = 0;
 189         spin_unlock_irqrestore(&host->lock, flags);
 190
 191         if (!unlikely(req))
 192                 return;
 193
 194 /*      if (req->cmd->error != 0) {
 195                 printk("error\n");
 196                 jz4740_mmc_reset(host);
 197         }*/
 198
 199         mmc_request_done(host->mmc, req);
 200 }
 201
 202 static void jz4740_mmc_write_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
 203         struct scatterlist *sg;
 204         uint32_t *sg_pointer;
 205         int status;
 206         size_t i, j;
 207
 208         for (sg = data->sg; sg; sg = sg_next(sg)) {
 209                 sg_pointer = sg_virt(sg);
 210                 i = sg->length / 4;
 211                 j = i >> 3;
 212                 i = i & 0x7;
 213                 while (j) {
 214                         do {
 215                                 status = readw(host->base + JZ_REG_MMC_IREG);
 216                         } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ));
 217                         writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
 218
 219                         writel(sg_pointer[0], host->base + JZ_REG_MMC_TXFIFO);
 220                         writel(sg_pointer[1], host->base + JZ_REG_MMC_TXFIFO);
 221                         writel(sg_pointer[2], host->base + JZ_REG_MMC_TXFIFO);
 222                         writel(sg_pointer[3], host->base + JZ_REG_MMC_TXFIFO);
 223                         writel(sg_pointer[4], host->base + JZ_REG_MMC_TXFIFO);
 224                         writel(sg_pointer[5], host->base + JZ_REG_MMC_TXFIFO);
 225                         writel(sg_pointer[6], host->base + JZ_REG_MMC_TXFIFO);
 226                         writel(sg_pointer[7], host->base + JZ_REG_MMC_TXFIFO);
 227                         sg_pointer += 8;
 228                         --j;
 229                 }
 230                 if (i) {
 231                         do {
 232                                 status = readw(host->base + JZ_REG_MMC_IREG);
 233                         } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ));
 234                         writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
 235
 236                         while (i) {
 237                                 writel(*sg_pointer, host->base + JZ_REG_MMC_TXFIFO);
 238                                 ++sg_pointer;
 239                                 --i;
 240                         }
 241                 }
 242                 data->bytes_xfered += sg->length;
 243         }
 244
 245         status = readl(host->base + JZ_REG_MMC_STATUS);
 246         if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK)
 247                 goto err;
 248
 249         writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
 250         do {
 251                 status = readl(host->base + JZ_REG_MMC_STATUS);
 252         } while ((status & JZ_MMC_STATUS_DATA_TRAN_DONE) == 0);
 253         writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
 254
 255         return;
 256 err:
 257         if(status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
 258                 host->req->cmd->error = -ETIMEDOUT;
 259                 data->error = -ETIMEDOUT;
 260         } else {
 261                 host->req->cmd->error = -EILSEQ;
 262                 data->error = -EILSEQ;
 263         }
 264 }
 265
 266 static void jz4740_mmc_timeout(unsigned long data)
 267 {
 268         struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)data;
 269         unsigned long flags;
 270
 271         spin_lock_irqsave(&host->lock, flags);
 272         if (!host->waiting) {
 273                 spin_unlock_irqrestore(&host->lock, flags);
 274                 return;
 275         }
 276
 277         host->waiting = 0;
 278
 279         spin_unlock_irqrestore(&host->lock, flags);
 280
 281         host->req->cmd->error = -ETIMEDOUT;
 282         jz4740_mmc_request_done(host);
 283 }
 284
 285 static void jz4740_mmc_read_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
 286         struct scatterlist *sg;
 287         uint32_t *sg_pointer;
 288         uint32_t d;
 289         uint16_t status = 0;
 290         size_t i, j;
 291
 292         for (sg = data->sg; sg; sg = sg_next(sg)) {
 293                 sg_pointer = sg_virt(sg);
 294                 i = sg->length;
 295                 j = i >> 5;
 296                 i = i & 0x1f;
 297                 while (j) {
 298                         do {
 299                                 status = readw(host->base + JZ_REG_MMC_IREG);
 300                         } while (!(status & JZ_MMC_IRQ_RXFIFO_RD_REQ));
 301                         writew(JZ_MMC_IRQ_RXFIFO_RD_REQ, host->base + JZ_REG_MMC_IREG);
 302
 303                         sg_pointer[0] = readl(host->base + JZ_REG_MMC_RXFIFO);
 304                         sg_pointer[1] = readl(host->base + JZ_REG_MMC_RXFIFO);
 305                         sg_pointer[2] = readl(host->base + JZ_REG_MMC_RXFIFO);
 306                         sg_pointer[3] = readl(host->base + JZ_REG_MMC_RXFIFO);
 307                         sg_pointer[4] = readl(host->base + JZ_REG_MMC_RXFIFO);
 308                         sg_pointer[5] = readl(host->base + JZ_REG_MMC_RXFIFO);
 309                         sg_pointer[6] = readl(host->base + JZ_REG_MMC_RXFIFO);
 310                         sg_pointer[7] = readl(host->base + JZ_REG_MMC_RXFIFO);
 311
 312                         sg_pointer += 8;
 313                         --j;
 314                 }
 315
 316                 while (i >= 4) {
 317                         do {
 318                                 status = readl(host->base + JZ_REG_MMC_STATUS);
 319                         } while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY));
 320
 321                         *sg_pointer = readl(host->base + JZ_REG_MMC_RXFIFO);
 322                         ++sg_pointer;
 323                         i -= 4;
 324                 }
 325                 if (i > 0) {
 326                         d = readl(host->base + JZ_REG_MMC_RXFIFO);
 327                         memcpy(sg_pointer, &d, i);
 328                 }
 329                 data->bytes_xfered += sg->length;
 330
 331                 flush_dcache_page(sg_page(sg));
 332         }
 333
 334         status = readl(host->base + JZ_REG_MMC_STATUS);
 335         if (status & JZ_MMC_STATUS_READ_ERROR_MASK)
 336                 goto err;
 337
 338         /* For whatever reason there is sometime one word more in the fifo then
 339          * requested */
 340         while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) == 0) {
 341                 d = readl(host->base + JZ_REG_MMC_RXFIFO);
 342                 status = readl(host->base + JZ_REG_MMC_STATUS);
 343         }
 344         return;
 345
 346 err:
 347         if(status & JZ_MMC_STATUS_TIMEOUT_READ) {
 348                 host->req->cmd->error = -ETIMEDOUT;
 349                 data->error = -ETIMEDOUT;
 350         } else {
 351                 host->req->cmd->error = -EILSEQ;
 352                 data->error = -EILSEQ;
 353         }
 354 }
 355
 356 static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
 357 {
 358         struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)devid;
 359
 360         if (host->cmd->error)
 361                 jz4740_mmc_request_done(host);
 362         else
 363                 jz4740_mmc_cmd_done(host);
 364
 365         return IRQ_HANDLED;
 366 }
 367
 368 static irqreturn_t jz_mmc_irq(int irq, void *devid)
 369 {
 370         struct jz4740_mmc_host *host = devid;
 371         uint16_t irq_reg, status, tmp;
 372         unsigned long flags;
 373         irqreturn_t ret = IRQ_HANDLED;
 374
 375         irq_reg = readw(host->base + JZ_REG_MMC_IREG);
 376
 377         tmp = irq_reg;
 378         spin_lock(&host->lock);
 379         irq_reg &= ~host->irq_mask;
 380         spin_unlock(&host->lock);
 381
 382         if (irq_reg & JZ_MMC_IRQ_SDIO) {
 383                 writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
 384                 mmc_signal_sdio_irq(host->mmc);
 385         }
 386
 387         if (!host->req || !host->cmd) {
 388                 goto handled;
 389         }
 390
 391
 392         spin_lock_irqsave(&host->lock, flags);
 393         if (!host->waiting) {
 394                 spin_unlock_irqrestore(&host->lock, flags);
 395                 goto handled;
 396         }
 397         host->waiting = 0;
 398         spin_unlock_irqrestore(&host->lock, flags);
 399
 400         del_timer(&host->timeout_timer);
 401
 402         status = readl(host->base + JZ_REG_MMC_STATUS);
 403
 404         if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
 405                 host->cmd->error = -ETIMEDOUT;
 406         } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
 407                 host->cmd->error = -EIO;
 408         } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
 409                                                 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
 410                 host->cmd->data->error = -EIO;
 411         } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
 412                                                 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
 413                 host->cmd->data->error = -EIO;
 414         }
 415
 416         if (irq_reg & JZ_MMC_IRQ_END_CMD_RES) {
 417                 jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
 418                 writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
 419                 ret = IRQ_WAKE_THREAD;
 420         }
 421
 422         return ret;
 423 handled:
 424
 425         writew(0xff, host->base + JZ_REG_MMC_IREG);
 426         return IRQ_HANDLED;
 427 }
 428
 429 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) {
 430         int div = 0;
 431         int real_rate = host->max_clock;
 432         jz4740_mmc_clock_disable(host);
 433
 434         while ((real_rate >> 1) >= rate && div < 7) {
 435                 ++div;
 436                 real_rate >>= 1;
 437         }
 438         clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
 439
 440         writew(div, host->base + JZ_REG_MMC_CLKRT);
 441         return real_rate;
 442 }
 443
 444
 445 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, struct mmc_command *cmd)
 446 {
 447         int i;
 448         uint16_t tmp;
 449         if (cmd->flags & MMC_RSP_136) {
 450                 tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
 451                 for (i = 0; i < 4; ++i) {
 452                         cmd->resp[i] = tmp << 24;
 453                         cmd->resp[i] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
 454                         tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
 455                         cmd->resp[i] |= tmp >> 8;
 456                 }
 457         } else {
 458                 cmd->resp[0] = readw(host->base + JZ_REG_MMC_RESP_FIFO) << 24;
 459                 cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
 460                 cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) & 0xff;
 461         }
 462 }
 463
 464 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, struct mmc_command *cmd)
 465 {
 466         uint32_t cmdat = host->cmdat;
 467
 468         host->cmdat &= ~JZ_MMC_CMDAT_INIT;
 469         jz4740_mmc_clock_disable(host);
 470
 471         host->cmd = cmd;
 472
 473         if (cmd->flags & MMC_RSP_BUSY)
 474                 cmdat |= JZ_MMC_CMDAT_BUSY;
 475
 476         switch (mmc_resp_type(cmd)) {
 477         case MMC_RSP_R1B:
 478         case MMC_RSP_R1:
 479                 cmdat |= JZ_MMC_CMDAT_RSP_R1;
 480                 break;
 481         case MMC_RSP_R2:
 482                 cmdat |= JZ_MMC_CMDAT_RSP_R2;
 483                 break;
 484         case MMC_RSP_R3:
 485                 cmdat |= JZ_MMC_CMDAT_RSP_R3;
 486                 break;
 487         default:
 488                 break;
 489         }
 490
 491         if (cmd->data) {
 492                 cmdat |= JZ_MMC_CMDAT_DATA_EN;
 493                 if (cmd->data->flags & MMC_DATA_WRITE)
 494                         cmdat |= JZ_MMC_CMDAT_WRITE;
 495                 if (cmd->data->flags & MMC_DATA_STREAM)
 496                         cmdat |= JZ_MMC_CMDAT_STREAM;
 497
 498                 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
 499                 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
 500         }
 501
 502         writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
 503         writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
 504         writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
 505
 506         host->waiting = 1;
 507         jz4740_mmc_clock_enable(host, 1);
 508         mod_timer(&host->timeout_timer, 4*HZ);
 509 }
 510
 511 static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host)
 512 {
 513         uint32_t status;
 514         struct mmc_command *cmd = host->req->cmd;
 515         struct mmc_request *req = host->req;
 516         status = readl(host->base + JZ_REG_MMC_STATUS);
 517
 518         if (cmd->flags & MMC_RSP_PRESENT)
 519                 jz4740_mmc_read_response(host, cmd);
 520
 521         if (cmd->data) {
 522                 if (cmd->data->flags & MMC_DATA_READ)
 523                         jz4740_mmc_read_data(host, cmd->data);
 524                 else
 525                         jz4740_mmc_write_data(host, cmd->data);
 526         }
 527
 528         if (req->stop) {
 529                 jz4740_mmc_send_command(host, req->stop);
 530                 do {
 531                         status = readl(host->base + JZ_REG_MMC_STATUS);
 532                 } while ((status & JZ_MMC_STATUS_PRG_DONE) == 0);
 533                 writew(JZ_MMC_IRQ_PRG_DONE, host->base + JZ_REG_MMC_IREG);
 534         }
 535
 536         jz4740_mmc_request_done(host);
 537 }
 538
 539 static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 540 {
 541         struct jz4740_mmc_host *host = mmc_priv(mmc);
 542
 543         host->req = req;
 544
 545         writew(0xffff, host->base + JZ_REG_MMC_IREG);
 546
 547         writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
 548         jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
 549         jz4740_mmc_send_command(host, req->cmd);
 550 }
 551
 552
 553 static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 554 {
 555         struct jz4740_mmc_host *host = mmc_priv(mmc);
 556         if (ios->clock)
 557                 jz4740_mmc_set_clock_rate(host, ios->clock);
 558
 559         switch(ios->power_mode) {
 560         case MMC_POWER_UP:
 561                 if (gpio_is_valid(host->pdata->gpio_power))
 562                         gpio_set_value(host->pdata->gpio_power,
 563                                         !host->pdata->power_active_low);
 564                 host->cmdat |= JZ_MMC_CMDAT_INIT;
 565                 clk_enable(host->clk);
 566                 break;
 567         case MMC_POWER_ON:
 568                 break;
 569         default:
 570                 if (gpio_is_valid(host->pdata->gpio_power))
 571                         gpio_set_value(host->pdata->gpio_power,
 572                                         host->pdata->power_active_low);
 573                 clk_disable(host->clk);
 574                 break;
 575         }
 576
 577         switch(ios->bus_width) {
 578         case MMC_BUS_WIDTH_1:
 579                 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
 580                 break;
 581         case MMC_BUS_WIDTH_4:
 582                 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
 583                 break;
 584         default:
 585                 dev_err(&host->pdev->dev, "Invalid bus width: %d\n", ios->bus_width);
 586         }
 587 }
 588
 589 static int jz4740_mmc_get_ro(struct mmc_host *mmc)
 590 {
 591         struct jz4740_mmc_host *host = mmc_priv(mmc);
 592         if (!gpio_is_valid(host->pdata->gpio_read_only))
 593                 return -ENOSYS;
 594
 595         return gpio_get_value(host->pdata->gpio_read_only) ^
 596                 host->pdata->read_only_active_low;
 597 }
 598
 599 static int jz4740_mmc_get_cd(struct mmc_host *mmc)
 600 {
 601         struct jz4740_mmc_host *host = mmc_priv(mmc);
 602         if (!gpio_is_valid(host->pdata->gpio_card_detect))
 603                 return -ENOSYS;
 604
 605         return gpio_get_value(host->pdata->gpio_card_detect) ^
 606                         host->pdata->card_detect_active_low;
 607 }
 608
 609 static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
 610 {
 611         struct jz4740_mmc_host *host = devid;
 612
 613         mmc_detect_change(host->mmc, HZ / 3);
 614
 615         return IRQ_HANDLED;
 616 }
 617
 618 static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 619 {
 620         struct jz4740_mmc_host *host = mmc_priv(mmc);
 621         if (enable)
 622                 jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_SDIO);
 623         else
 624                 jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_SDIO);
 625 }
 626
 627 static const struct mmc_host_ops jz4740_mmc_ops = {
 628         .request        = jz4740_mmc_request,
 629         .set_ios        = jz4740_mmc_set_ios,
 630         .get_ro         = jz4740_mmc_get_ro,
 631         .get_cd         = jz4740_mmc_get_cd,
 632         .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
 633 };
 634
 635 static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
 636         JZ_GPIO_BULK_PIN(MSC_CMD),
 637         JZ_GPIO_BULK_PIN(MSC_CLK),
 638         JZ_GPIO_BULK_PIN(MSC_DATA0),
 639         JZ_GPIO_BULK_PIN(MSC_DATA1),
 640         JZ_GPIO_BULK_PIN(MSC_DATA2),
 641         JZ_GPIO_BULK_PIN(MSC_DATA3),
 642 };
 643
 644 static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev)
 645 {
 646         int ret;
 647         struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
 648
 649         if (!pdata)
 650                 return 0;
 651
 652         if (gpio_is_valid(pdata->gpio_card_detect)) {
 653                 ret = gpio_request(pdata->gpio_card_detect, "MMC detect change");
 654                 if (ret) {
 655                         dev_err(&pdev->dev, "Failed to request detect change gpio\n");
 656                         goto err;
 657                 }
 658                 gpio_direction_input(pdata->gpio_card_detect);
 659         }
 660
 661         if (gpio_is_valid(pdata->gpio_read_only)) {
 662                 ret = gpio_request(pdata->gpio_read_only, "MMC read only");
 663                 if (ret) {
 664                         dev_err(&pdev->dev, "Failed to request read only gpio: %d\n", ret);
 665                         goto err_free_gpio_card_detect;
 666                 }
 667                 gpio_direction_input(pdata->gpio_read_only);
 668         }
 669
 670         if (gpio_is_valid(pdata->gpio_power)) {
 671                 ret = gpio_request(pdata->gpio_power, "MMC power");
 672                 if (ret) {
 673                         dev_err(&pdev->dev, "Failed to request power gpio: %d\n", ret);
 674                         goto err_free_gpio_read_only;
 675                 }
 676                 gpio_direction_output(pdata->gpio_power, pdata->power_active_low);
 677         }
 678
 679         return 0;
 680
 681 err_free_gpio_read_only:
 682         if (gpio_is_valid(pdata->gpio_read_only))
 683                 gpio_free(pdata->gpio_read_only);
 684 err_free_gpio_card_detect:
 685         if (gpio_is_valid(pdata->gpio_card_detect))
 686                 gpio_free(pdata->gpio_card_detect);
 687 err:
 688         return ret;
 689 }
 690
 691 static void jz4740_mmc_free_gpios(struct platform_device *pdev)
 692 {
 693         struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
 694
 695         if (!pdata)
 696                 return;
 697
 698         if (gpio_is_valid(pdata->gpio_power))
 699                 gpio_free(pdata->gpio_power);
 700         if (gpio_is_valid(pdata->gpio_read_only))
 701                 gpio_free(pdata->gpio_read_only);
 702         if (gpio_is_valid(pdata->gpio_card_detect))
 703                 gpio_free(pdata->gpio_card_detect);
 704 }
 705
 706 static int __devinit jz4740_mmc_probe(struct platform_device* pdev)
 707 {
 708         int ret;
 709         struct mmc_host *mmc;
 710         struct jz4740_mmc_host *host;
 711         struct jz4740_mmc_platform_data *pdata;
 712
 713         pdata = pdev->dev.platform_data;
 714
 715         mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
 716
 717         if (!mmc) {
 718                 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
 719                 return -ENOMEM;
 720         }
 721
 722         host = mmc_priv(mmc);
 723
 724         host->irq = platform_get_irq(pdev, 0);
 725
 726         if (host->irq < 0) {
 727                 ret = host->irq;
 728                 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
 729                 goto err_free_host;
 730         }
 731
 732         host->clk = clk_get(&pdev->dev, "mmc");
 733         if (!host->clk) {
 734                 ret = -ENOENT;
 735                 dev_err(&pdev->dev, "Failed to get mmc clock\n");
 736                 goto err_free_host;
 737         }
 738
 739         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 740
 741         if (!host->mem) {
 742                 ret = -ENOENT;
 743                 dev_err(&pdev->dev, "Failed to get base platform memory\n");
 744                 goto err_clk_put;
 745         }
 746
 747         host->mem = request_mem_region(host->mem->start, resource_size(host->mem),
 748                                         pdev->name);
 749
 750         if (!host->mem) {
 751                 ret = -EBUSY;
 752                 dev_err(&pdev->dev, "Failed to request base memory region\n");
 753                 goto err_clk_put;
 754         }
 755
 756         host->base = ioremap_nocache(host->mem->start, resource_size(host->mem));
 757
 758         if (!host->base) {
 759                 ret = -EBUSY;
 760                 dev_err(&pdev->dev, "Failed to ioremap base memory\n");
 761                 goto err_release_mem_region;
 762         }
 763
 764         if (pdata && pdata->data_1bit)
 765                 ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 766         else
 767                 ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 768
 769         if (ret) {
 770                 dev_err(&pdev->dev, "Failed to request function pins: %d\n", ret);
 771                 goto err_iounmap;
 772         }
 773
 774         ret = jz4740_mmc_request_gpios(pdev);
 775         if (ret)
 776                 goto err_gpio_bulk_free;
 777
 778         mmc->ops = &jz4740_mmc_ops;
 779         mmc->f_min = JZ_MMC_CLK_RATE / 128;
 780         mmc->f_max = JZ_MMC_CLK_RATE;
 781         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 782         mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
 783         mmc->caps |= MMC_CAP_SDIO_IRQ;
 784         mmc->max_seg_size = 4096;
 785         mmc->max_phys_segs = 128;
 786
 787         mmc->max_blk_size = (1 << 10) - 1;
 788         mmc->max_blk_count = (1 << 15) - 1;
 789         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 790
 791         host->mmc = mmc;
 792         host->pdev = pdev;
 793         host->pdata = pdata;
 794         host->max_clock = JZ_MMC_CLK_RATE;
 795         spin_lock_init(&host->lock);
 796         host->irq_mask = 0xffff;
 797
 798         host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
 799
 800         if (host->card_detect_irq < 0) {
 801                 dev_warn(&pdev->dev, "Failed to get irq for card detect gpio\n");
 802         } else {
 803                 ret = request_irq(host->card_detect_irq,
 804                                 jz4740_mmc_card_detect_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "MMC/SD detect changed", host);
 805
 806                 if (ret) {
 807                         dev_err(&pdev->dev, "Failed to request card detect irq");
 808                         goto err_free_gpios;
 809                 }
 810         }
 811
 812         ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, IRQF_DISABLED, "MMC/SD", host);
 813         if (ret) {
 814                 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
 815                 goto err_free_card_detect_irq;
 816         }
 817
 818         jz4740_mmc_reset(host);
 819         jz4740_mmc_clock_disable(host);
 820         setup_timer(&host->timeout_timer, jz4740_mmc_timeout, (unsigned long)host);
 821
 822         platform_set_drvdata(pdev, host);
 823         ret = mmc_add_host(mmc);
 824
 825         if (ret) {
 826                 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
 827                 goto err_free_irq;
 828         }
 829         printk("JZ SD/MMC card driver registered\n");
 830
 831         return 0;
 832
 833 err_free_irq:
 834         free_irq(host->irq, host);
 835 err_free_card_detect_irq:
 836         if (host->card_detect_irq >= 0)
 837                 free_irq(host->card_detect_irq, host);
 838 err_free_gpios:
 839         jz4740_mmc_free_gpios(pdev);
 840 err_gpio_bulk_free:
 841         if (pdata && pdata->data_1bit)
 842                 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 843         else
 844                 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 845 err_iounmap:
 846         iounmap(host->base);
 847 err_release_mem_region:
 848         release_mem_region(host->mem->start, resource_size(host->mem));
 849 err_clk_put:
 850         clk_put(host->clk);
 851 err_free_host:
 852         platform_set_drvdata(pdev, NULL);
 853         mmc_free_host(mmc);
 854
 855         return ret;
 856 }
 857
 858 static int jz4740_mmc_remove(struct platform_device *pdev)
 859 {
 860         struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
 861         struct jz4740_mmc_platform_data *pdata = host->pdata;
 862
 863         del_timer_sync(&host->timeout_timer);
 864         jz4740_mmc_disable_irq(host, 0xff);
 865         jz4740_mmc_reset(host);
 866
 867         mmc_remove_host(host->mmc);
 868
 869         free_irq(host->irq, host);
 870         if (host->card_detect_irq >= 0)
 871                 free_irq(host->card_detect_irq, host);
 872
 873         jz4740_mmc_free_gpios(pdev);
 874         if (pdata && pdata->data_1bit)
 875                 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 876         else
 877                 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 878
 879         iounmap(host->base);
 880         release_mem_region(host->mem->start, resource_size(host->mem));
 881
 882         clk_put(host->clk);
 883
 884         platform_set_drvdata(pdev, NULL);
 885         mmc_free_host(host->mmc);
 886
 887         return 0;
 888 }
 889
 890 #ifdef CONFIG_PM
 891 static int jz4740_mmc_suspend(struct device *dev)
 892 {
 893         struct jz4740_mmc_host *host = dev_get_drvdata(dev);
 894         struct jz4740_mmc_platform_data *pdata = host->pdata;
 895
 896         mmc_suspend_host(host->mmc, PMSG_SUSPEND);
 897
 898         if (pdata && pdata->data_1bit)
 899                 jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 900         else
 901                 jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 902
 903         return 0;
 904 }
 905
 906 static int jz4740_mmc_resume(struct device *dev)
 907 {
 908         struct jz4740_mmc_host *host = dev_get_drvdata(dev);
 909         struct jz4740_mmc_platform_data *pdata = host->pdata;
 910
 911         if (pdata && pdata->data_1bit)
 912                 jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
 913         else
 914                 jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
 915
 916         mmc_resume_host(host->mmc);
 917
 918         return 0;
 919 }
 920
 921 struct dev_pm_ops jz4740_mmc_pm_ops = {
 922         .suspend        = jz4740_mmc_suspend,
 923         .resume         = jz4740_mmc_resume,
 924         .poweroff       = jz4740_mmc_suspend,
 925         .restore        = jz4740_mmc_resume,
 926 };
 927
 928 #define jz4740_mmc_PM_OPS (&jz4740_mmc_pm_ops)
 929 #else
 930 #define jz4740_mmc_PM_OPS NULL
 931 #endif
 932
 933 static struct platform_driver jz4740_mmc_driver = {
 934         .probe = jz4740_mmc_probe,
 935         .remove = jz4740_mmc_remove,
 936         .driver = {
 937                 .name = "jz4740-mmc",
 938                 .owner = THIS_MODULE,
 939                 .pm = jz4740_mmc_PM_OPS,
 940         },
 941 };
 942
 943 static int __init jz4740_mmc_init(void) {
 944         return platform_driver_register(&jz4740_mmc_driver);
 945 }
 946 module_init(jz4740_mmc_init);
 947
 948 static void __exit jz4740_mmc_exit(void) {
 949         platform_driver_unregister(&jz4740_mmc_driver);
 950 }
 951 module_exit(jz4740_mmc_exit);
 952
 953 MODULE_DESCRIPTION("JZ4720/JZ4740 SD/MMC controller driver");
 954 MODULE_LICENSE("GPL");
 955 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");