target/linux/xburst/files-2.6.32/drivers/misc/jz4740-adc.c

   1 /*
   2  * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
   3  *              JZ4720/JZ4740 SoC ADC driver
   4  *
   5  * This program is free software; you can redistribute   it and/or modify it
   6  * under  the terms of   the GNU General  Public License as published by the
   7  * Free Software Foundation;  either version 2 of the   License, or (at your
   8  * option) any later version.
   9  *
  10  * You should have received a copy of the  GNU General Public License along
  11  * with this program; if not, write  to the Free Software Foundation, Inc.,
  12  * 675 Mass Ave, Cambridge, MA 02139, USA.
  13  *
  14  * This driver is meant to synchronize access to the adc core for the battery
  15  * and touchscreen driver. Thus these drivers should use the adc driver as a
  16  * parent.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/jz4740-adc.h>
  27
  28 #define JZ_REG_ADC_ENABLE       0x00
  29 #define JZ_REG_ADC_CFG          0x04
  30 #define JZ_REG_ADC_CTRL         0x08
  31 #define JZ_REG_ADC_STATUS       0x0C
  32 #define JZ_REG_ADC_SAME         0x10
  33 #define JZ_REG_ADC_WAIT         0x14
  34 #define JZ_REG_ADC_TOUCH        0x18
  35 #define JZ_REG_ADC_BATTERY      0x1C
  36 #define JZ_REG_ADC_ADCIN        0x20
  37
  38 #define JZ_ADC_ENABLE_TOUCH             BIT(2)
  39 #define JZ_ADC_ENABLE_BATTERY           BIT(1)
  40 #define JZ_ADC_ENABLE_ADCIN             BIT(0)
  41
  42 #define JZ_ADC_CFG_SPZZ                 BIT(31)
  43 #define JZ_ADC_CFG_EX_IN                BIT(30)
  44 #define JZ_ADC_CFG_DNUM_MASK            (0x7 << 16)
  45 #define JZ_ADC_CFG_DMA_ENABLE           BIT(15)
  46 #define JZ_ADC_CFG_XYZ_MASK             (0x2 << 13)
  47 #define JZ_ADC_CFG_SAMPLE_NUM_MASK      (0x7 << 10)
  48 #define JZ_ADC_CFG_CLKDIV               (0xf << 5)
  49 #define JZ_ADC_CFG_BAT_MB               BIT(4)
  50
  51 #define JZ_ADC_CFG_DNUM_OFFSET          16
  52 #define JZ_ADC_CFG_XYZ_OFFSET           13
  53 #define JZ_ADC_CFG_SAMPLE_NUM_OFFSET    10
  54 #define JZ_ADC_CFG_CLKDIV_OFFSET        5
  55
  56 #define JZ_ADC_IRQ_PENDOWN              BIT(4)
  57 #define JZ_ADC_IRQ_PENUP                BIT(3)
  58 #define JZ_ADC_IRQ_TOUCH                BIT(2)
  59 #define JZ_ADC_IRQ_BATTERY              BIT(1)
  60 #define JZ_ADC_IRQ_ADCIN                BIT(0)
  61
  62 #define JZ_ADC_TOUCH_TYPE1              BIT(31)
  63 #define JZ_ADC_TOUCH_DATA1_MASK         0xfff
  64 #define JZ_ADC_TOUCH_TYPE0              BIT(15)
  65 #define JZ_ADC_TOUCH_DATA0_MASK         0xfff
  66
  67 #define JZ_ADC_BATTERY_MASK             0xfff
  68
  69 #define JZ_ADC_ADCIN_MASK               0xfff
  70
  71 struct jz4740_adc {
  72         struct resource *mem;
  73         void __iomem *base;
  74
  75         int irq;
  76
  77         struct clk *clk;
  78         unsigned int clk_ref;
  79
  80         struct completion bat_completion;
  81         struct completion adc_completion;
  82
  83         spinlock_t lock;
  84 };
  85
  86 static irqreturn_t jz4740_adc_irq(int irq, void *data)
  87 {
  88         struct jz4740_adc *adc = data;
  89         uint8_t status;
  90
  91         status = readb(adc->base + JZ_REG_ADC_STATUS);
  92
  93         if (status & JZ_ADC_IRQ_BATTERY)
  94                 complete(&adc->bat_completion);
  95         if (status & JZ_ADC_IRQ_ADCIN)
  96                 complete(&adc->adc_completion);
  97
  98         writeb(0xff, adc->base + JZ_REG_ADC_STATUS);
  99
 100         return IRQ_HANDLED;
 101 }
 102
 103 static void jz4740_adc_enable_irq(struct jz4740_adc *adc, int irq)
 104 {
 105         unsigned long flags;
 106         uint8_t val;
 107
 108         spin_lock_irqsave(&adc->lock, flags);
 109
 110         val = readb(adc->base + JZ_REG_ADC_CTRL);
 111         val &= ~irq;
 112         writeb(val, adc->base + JZ_REG_ADC_CTRL);
 113
 114         spin_unlock_irqrestore(&adc->lock, flags);
 115 }
 116
 117 static void jz4740_adc_disable_irq(struct jz4740_adc *adc, int irq)
 118 {
 119         unsigned long flags;
 120         uint8_t val;
 121
 122         spin_lock_irqsave(&adc->lock, flags);
 123
 124         val = readb(adc->base + JZ_REG_ADC_CTRL);
 125         val |= irq;
 126         writeb(val, adc->base + JZ_REG_ADC_CTRL);
 127
 128         spin_unlock_irqrestore(&adc->lock, flags);
 129 }
 130
 131 static void jz4740_adc_enable_adc(struct jz4740_adc *adc, int engine)
 132 {
 133         unsigned long flags;
 134         uint8_t val;
 135
 136         spin_lock_irqsave(&adc->lock, flags);
 137
 138         val = readb(adc->base + JZ_REG_ADC_ENABLE);
 139         val |= engine;
 140         writeb(val, adc->base + JZ_REG_ADC_ENABLE);
 141
 142         spin_unlock_irqrestore(&adc->lock, flags);
 143 }
 144
 145 static void jz4740_adc_disable_adc(struct jz4740_adc *adc, int engine)
 146 {
 147         unsigned long flags;
 148         uint8_t val;
 149
 150         spin_lock_irqsave(&adc->lock, flags);
 151
 152         val = readb(adc->base + JZ_REG_ADC_ENABLE);
 153         val &= ~engine;
 154         writeb(val, adc->base + JZ_REG_ADC_ENABLE);
 155
 156         spin_unlock_irqrestore(&adc->lock, flags);
 157 }
 158
 159 static inline void jz4740_adc_set_cfg(struct jz4740_adc *adc, uint32_t mask,
 160 uint32_t val)
 161 {
 162         unsigned long flags;
 163         uint32_t cfg;
 164
 165         spin_lock_irqsave(&adc->lock, flags);
 166
 167         cfg = readl(adc->base + JZ_REG_ADC_CFG);
 168
 169         cfg &= ~mask;
 170         cfg |= val;
 171
 172         writel(cfg, adc->base + JZ_REG_ADC_CFG);
 173
 174         spin_unlock_irqrestore(&adc->lock, flags);
 175 }
 176
 177 static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
 178 {
 179         unsigned long flags;
 180
 181         spin_lock_irqsave(&adc->lock, flags);
 182         if (adc->clk_ref++ == 0)
 183                 clk_enable(adc->clk);
 184         spin_unlock_irqrestore(&adc->lock, flags);
 185 }
 186
 187 static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
 188 {
 189         unsigned long flags;
 190
 191         spin_lock_irqsave(&adc->lock, flags);
 192         if (--adc->clk_ref == 0)
 193                 clk_disable(adc->clk);
 194         spin_unlock_irqrestore(&adc->lock, flags);
 195 }
 196
 197 long jz4740_adc_read_battery_voltage(struct device *dev,
 198                                                 enum jz_adc_battery_scale scale)
 199 {
 200         struct jz4740_adc *adc = dev_get_drvdata(dev);
 201         unsigned long t;
 202         long long voltage;
 203         uint16_t val;
 204
 205         if (!adc)
 206                 return -ENODEV;
 207
 208         jz4740_adc_clk_enable(adc);
 209
 210         if (scale == JZ_ADC_BATTERY_SCALE_2V5)
 211                 jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, JZ_ADC_CFG_BAT_MB);
 212         else
 213                 jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, 0);
 214
 215         jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_BATTERY);
 216         jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_BATTERY);
 217
 218         t = wait_for_completion_interruptible_timeout(&adc->bat_completion,
 219                                                         HZ);
 220
 221         jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_BATTERY);
 222
 223         if (t <= 0) {
 224                 jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_BATTERY);
 225                 return t ? t : -ETIMEDOUT;
 226         }
 227
 228         val = readw(adc->base + JZ_REG_ADC_BATTERY);
 229
 230         jz4740_adc_clk_disable(adc);
 231
 232         if (scale == JZ_ADC_BATTERY_SCALE_2V5)
 233                 voltage = (((long long)val) * 2500000LL) >> 12LL;
 234         else
 235                 voltage = ((((long long)val) * 7395000LL) >> 12LL) + 33000LL;
 236
 237         return voltage;
 238 }
 239 EXPORT_SYMBOL_GPL(jz4740_adc_read_battery_voltage);
 240
 241 static ssize_t jz4740_adc_read_adcin(struct device *dev,
 242                                         struct device_attribute *dev_attr,
 243                                         char *buf)
 244 {
 245         struct jz4740_adc *adc = dev_get_drvdata(dev);
 246         unsigned long t;
 247         uint16_t val;
 248
 249         jz4740_adc_clk_enable(adc);
 250
 251         jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_ADCIN);
 252         jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_ADCIN);
 253
 254         t = wait_for_completion_interruptible_timeout(&adc->adc_completion,
 255                                                         HZ);
 256
 257         jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_ADCIN);
 258
 259         if (t <= 0) {
 260                 jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_ADCIN);
 261                 return t ? t : -ETIMEDOUT;
 262         }
 263
 264         val = readw(adc->base + JZ_REG_ADC_ADCIN);
 265         jz4740_adc_clk_disable(adc);
 266
 267         return sprintf(buf, "%d\n", val);
 268 }
 269
 270 static DEVICE_ATTR(adcin, S_IRUGO, jz4740_adc_read_adcin, NULL);
 271
 272 static int __devinit jz4740_adc_probe(struct platform_device *pdev)
 273 {
 274         int ret;
 275         struct jz4740_adc *adc;
 276
 277         adc = kmalloc(sizeof(*adc), GFP_KERNEL);
 278
 279         adc->irq = platform_get_irq(pdev, 0);
 280
 281         if (adc->irq < 0) {
 282                 ret = adc->irq;
 283                 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
 284                 goto err_free;
 285         }
 286
 287         adc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 288
 289         if (!adc->mem) {
 290                 ret = -ENOENT;
 291                 dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
 292                 goto err_free;
 293         }
 294
 295         adc->mem = request_mem_region(adc->mem->start, resource_size(adc->mem),
 296                                         pdev->name);
 297
 298         if (!adc->mem) {
 299                 ret = -EBUSY;
 300                 dev_err(&pdev->dev, "Failed to request mmio memory region\n");
 301                 goto err_free;
 302         }
 303
 304         adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
 305
 306         if (!adc->base) {
 307                 ret = -EBUSY;
 308                 dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
 309                 goto err_release_mem_region;
 310         }
 311
 312         adc->clk = clk_get(&pdev->dev, "adc");
 313
 314         if (IS_ERR(adc->clk)) {
 315                 ret = PTR_ERR(adc->clk);
 316                 dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
 317                 goto err_iounmap;
 318         }
 319
 320         init_completion(&adc->bat_completion);
 321         init_completion(&adc->adc_completion);
 322
 323         spin_lock_init(&adc->lock);
 324
 325         adc->clk_ref = 0;
 326
 327         platform_set_drvdata(pdev, adc);
 328
 329         ret = request_irq(adc->irq, jz4740_adc_irq, 0, pdev->name, adc);
 330
 331         if (ret) {
 332                 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
 333                 goto err_clk_put;
 334         }
 335
 336         ret = device_create_file(&pdev->dev, &dev_attr_adcin);
 337         if (ret) {
 338                 dev_err(&pdev->dev, "Failed to create sysfs file: %d\n", ret);
 339                 goto err_free_irq;
 340         }
 341
 342         writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
 343         writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
 344
 345         return 0;
 346
 347 err_free_irq:
 348         free_irq(adc->irq, adc);
 349 err_clk_put:
 350         clk_put(adc->clk);
 351 err_iounmap:
 352         platform_set_drvdata(pdev, NULL);
 353         iounmap(adc->base);
 354 err_release_mem_region:
 355         release_mem_region(adc->mem->start, resource_size(adc->mem));
 356 err_free:
 357         kfree(adc);
 358
 359         return ret;
 360 }
 361
 362 static int __devexit jz4740_adc_remove(struct platform_device *pdev)
 363 {
 364         struct jz4740_adc *adc = platform_get_drvdata(pdev);
 365
 366         device_remove_file(&pdev->dev, &dev_attr_adcin);
 367
 368         free_irq(adc->irq, adc);
 369
 370         iounmap(adc->base);
 371         release_mem_region(adc->mem->start, resource_size(adc->mem));
 372
 373         clk_put(adc->clk);
 374
 375         platform_set_drvdata(pdev, NULL);
 376
 377         kfree(adc);
 378
 379         return 0;
 380 }
 381
 382 struct platform_driver jz4740_adc_driver = {
 383         .probe  = jz4740_adc_probe,
 384         .remove = jz4740_adc_remove,
 385         .driver = {
 386                 .name = "jz4740-adc",
 387                 .owner = THIS_MODULE,
 388         },
 389 };
 390
 391 static int __init jz4740_adc_init(void)
 392 {
 393         return platform_driver_register(&jz4740_adc_driver);
 394 }
 395 module_init(jz4740_adc_init);
 396
 397 static void __exit jz4740_adc_exit(void)
 398 {
 399         platform_driver_unregister(&jz4740_adc_driver);
 400 }
 401 module_exit(jz4740_adc_exit);
 402
 403 MODULE_DESCRIPTION("JZ4720/JZ4740 SoC ADC driver");
 404 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 405 MODULE_LICENSE("GPL");
 406 MODULE_ALIAS("platform:jz4740-adc");
 407 MODULE_ALIAS("platform:jz4720-adc");