2 * Micron SPI-ER NAND Flash Memory
4 * (C) Copyright 2009, Ubicom, Inc.
6 * This file is part of the Ubicom32 Linux Kernel Port.
8 * The Ubicom32 Linux Kernel Port is free software: you can redistribute
9 * it and/or modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation, either version 2 of the
11 * License, or (at your option) any later version.
13 * The Ubicom32 Linux Kernel Port is distributed in the hope that it
14 * will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 * the GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with the Ubicom32 Linux Kernel Port. If not,
20 * see <http://www.gnu.org/licenses/>.
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/device.h>
27 #include <linux/mutex.h>
28 #include <linux/err.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/flash.h>
33 #include <linux/mtd/mtd.h>
34 #include <linux/mtd/partitions.h>
36 #define NAND_SPI_ER_BLOCK_FROM_ROW(row) (row >> 6)
38 #define NAND_SPI_ER_STATUS_P_FAIL (1 << 3)
39 #define NAND_SPI_ER_STATUS_E_FAIL (1 << 2)
40 #define NAND_SPI_ER_STATUS_OIP (1 << 0)
42 #define NAND_SPI_ER_LAST_ROW_INVALID 0xFFFFFFFF
43 #define NAND_SPI_ER_BAD_BLOCK_MARK_OFFSET 0x08
45 struct nand_spi_er_device {
52 unsigned int pages_per_block;
53 unsigned int page_size;
54 unsigned int write_size;
55 unsigned int erase_size;
61 const struct nand_spi_er_device *device;
64 struct spi_device *spi;
68 unsigned int last_row; /* the last row we fetched */
71 * Bad block table (MUST be last in strcuture)
77 const struct nand_spi_er_device nand_spi_er_devices[] = {
86 erase_size: 64 * 2048,
96 erase_size: 64 * 2048,
100 static int read_only = 0;
101 module_param(read_only, int, 0);
102 MODULE_PARM_DESC(read_only, "Leave device locked");
105 * nand_spi_er_get_feature
106 * Get Feature register
108 static int nand_spi_er_get_feature(struct nand_spi_er *chip, int reg, uint8_t *data)
116 res = spi_write_then_read(chip->spi, txbuf, 2, rxbuf, 1);
118 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed get feature res=%d\n", chip->name, res);
126 * nand_spi_er_busywait
127 * Wait until the chip is not busy
129 static int nand_spi_er_busywait(struct nand_spi_er *chip, uint8_t *data)
133 for (i = 0; i < 100; i++) {
134 int res = nand_spi_er_get_feature(chip, 0xC0, data);
138 if (!(*data & NAND_SPI_ER_STATUS_OIP)) {
148 * Erase a block, parameters must be block aligned
150 static int nand_spi_er_erase(struct mtd_info *mtd, struct erase_info *instr)
152 struct nand_spi_er *chip = mtd->priv;
153 struct spi_device *spi = chip->spi;
157 DEBUG(MTD_DEBUG_LEVEL3, "%s: erase addr:%x len:%x\n", chip->name, instr->addr, instr->len);
159 if ((instr->addr + instr->len) > mtd->size) {
163 if (instr->addr & (chip->device->erase_size - 1)) {
164 DEBUG(MTD_DEBUG_LEVEL1, "%s: erase address is not aligned %x\n", chip->name, instr->addr);
168 if (instr->len & (chip->device->erase_size - 1)) {
169 DEBUG(MTD_DEBUG_LEVEL1, "%s: erase len is not aligned %x\n", chip->name, instr->len);
173 mutex_lock(&chip->lock);
174 chip->last_row = NAND_SPI_ER_LAST_ROW_INVALID;
177 uint32_t block = instr->addr >> 17;
178 uint32_t row = block << 6;
180 DEBUG(MTD_DEBUG_LEVEL3, "%s: block erase row:%x block:%x addr:%x rem:%x\n", chip->name, row, block, instr->addr, instr->len);
186 res = spi_write(spi, txbuf, 1);
188 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write enable res=%d\n", chip->name, res);
189 mutex_unlock(&chip->lock);
196 if (test_bit(block, chip->bbt)) {
197 instr->fail_addr = block << 17;
198 instr->state = MTD_ERASE_FAILED;
209 txbuf[3] = row & 0xFF;
210 res = spi_write(spi, txbuf, 4);
212 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed block erase res=%d\n", chip->name, res);
213 instr->fail_addr = block << 17;
214 instr->state = MTD_ERASE_FAILED;
221 res = nand_spi_er_busywait(chip, &stat);
222 if (res || (stat & NAND_SPI_ER_STATUS_OIP)) {
223 instr->fail_addr = block << 17;
224 instr->state = MTD_ERASE_FAILED;
225 DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive res=%d stat=%02x\n", chip->name, res, stat);
238 * Check the status register
240 if (stat & NAND_SPI_ER_STATUS_E_FAIL) {
241 DEBUG(MTD_DEBUG_LEVEL1, "%s: E_FAIL signalled (%02x)\n", chip->name, stat);
242 instr->fail_addr = block << 17;
243 instr->state = MTD_ERASE_FAILED;
251 instr->len -= chip->device->erase_size;
252 instr->addr += chip->device->erase_size;
255 instr->state = MTD_ERASE_DONE;
257 mutex_unlock(&chip->lock);
265 res = spi_write(spi, txbuf, 1);
267 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write disable res=%d\n", chip->name, res);
270 mutex_unlock(&chip->lock);
272 mtd_erase_callback(instr);
279 * return -EUCLEAN: ecc error recovered
280 * return -EBADMSG: ecc error not recovered
282 static int nand_spi_er_read(struct mtd_info *mtd, loff_t from, size_t len,
283 size_t *retlen, u_char *buf)
285 struct nand_spi_er *chip = mtd->priv;
286 struct spi_device *spi = chip->spi;
293 DEBUG(MTD_DEBUG_LEVEL2, "%s: read block from %llx len %d into %p\n", chip->name, from, len, buf);
296 * Zero length reads, nothing to do
303 * Reject reads which go over the end of the flash
305 if ((from + len) > mtd->size) {
310 * Get the row and column address to start at
313 column = from & 0x7FF;
314 DEBUG(MTD_DEBUG_LEVEL3, "%s: row=%x %d column=%x %d last_row=%x %d\n", chip->name, row, row, column, column, chip->last_row, chip->last_row);
317 * Read the data from the chip
319 mutex_lock(&chip->lock);
323 struct spi_message message;
324 struct spi_transfer x[2];
329 * Figure out how much to read
331 * If we are reading from the middle of a page then the most we
332 * can read is to the end of the page
335 if (toread > (chip->device->page_size - column)) {
336 toread = chip->device->page_size - column;
339 DEBUG(MTD_DEBUG_LEVEL3, "%s: buf=%p toread=%x row=%x column=%x last_row=%x\n", chip->name, buf, toread, row, column, chip->last_row);
341 if (chip->last_row != row) {
343 * Check if the block is bad
345 if (test_bit(NAND_SPI_ER_BLOCK_FROM_ROW(row), chip->bbt)) {
346 mutex_unlock(&chip->lock);
351 * Load the appropriate page
356 txbuf[3] = row & 0xFF;
357 res = spi_write(spi, txbuf, 4);
359 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed page load res=%d\n", chip->name, res);
360 mutex_unlock(&chip->lock);
367 res = nand_spi_er_busywait(chip, &stat);
368 if (res || (stat & NAND_SPI_ER_STATUS_OIP)) {
369 DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive res=%d stat=%02x\n", chip->name, res, stat);
371 mutex_unlock(&chip->lock);
378 mutex_unlock(&chip->lock);
387 DEBUG(MTD_DEBUG_LEVEL1, "%s: ECC recovered, row=%x\n", chip->name, row);
391 DEBUG(MTD_DEBUG_LEVEL0, "%s: failed ECC, row=%x\n", chip->name, row);
392 chip->last_row = NAND_SPI_ER_LAST_ROW_INVALID;
393 mutex_unlock(&chip->lock);
399 chip->last_row = row;
404 spi_message_init(&message);
405 memset(x, 0, sizeof(x));
408 txbuf[1] = column >> 8;
409 txbuf[2] = column & 0xFF;
413 spi_message_add_tail(&x[0], &message);
417 spi_message_add_tail(&x[1], &message);
419 res = spi_sync(spi, &message);
421 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed data read res=%d\n", chip->name, res);
422 mutex_unlock(&chip->lock);
430 * For the next page, increment the row and always start at column 0
436 mutex_unlock(&chip->lock);
443 #define NOT_ALIGNED(x) ((x & (device->write_size - 1)) != 0)
444 static int nand_spi_er_write(struct mtd_info *mtd, loff_t to, size_t len,
445 size_t *retlen, const u_char *buf)
447 struct nand_spi_er *chip = mtd->priv;
448 struct spi_device *spi = chip->spi;
449 const struct nand_spi_er_device *device = chip->device;
456 DEBUG(MTD_DEBUG_LEVEL2, "%s: write block to %llx len %d from %p\n", chip->name, to, len, buf);
468 * Reject writes which go over the end of the flash
470 if ((to + len) > mtd->size) {
475 * Check to see if everything is page aligned
477 if (NOT_ALIGNED(to) || NOT_ALIGNED(len)) {
478 printk(KERN_NOTICE "nand_spi_er_write: Attempt to write non page aligned data\n");
482 mutex_lock(&chip->lock);
483 chip->last_row = NAND_SPI_ER_LAST_ROW_INVALID;
486 * If the first write is a partial write then write at most the number of
487 * bytes to get us page aligned and then the remainder will be
488 * page aligned. The last bit may be a partial page as well.
490 col = to & (device->page_size - 1);
491 towrite = device->page_size - col;
501 struct spi_message message;
502 struct spi_transfer x[2];
505 DEBUG(MTD_DEBUG_LEVEL3, "%s: write %p to row:%x col:%x len:%x rem:%x\n", chip->name, buf, row, col, towrite, len);
511 res = spi_write(spi, txbuf, 1);
513 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write enable res=%d\n", chip->name, res);
514 mutex_unlock(&chip->lock);
519 * Write the data into the cache
521 spi_message_init(&message);
522 memset(x, 0, sizeof(x));
525 txbuf[2] = col & 0xFF;
528 spi_message_add_tail(&x[0], &message);
531 spi_message_add_tail(&x[1], &message);
532 res = spi_sync(spi, &message);
534 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed cache write res=%d\n", chip->name, res);
544 txbuf[3] = row & 0xFF;
545 res = spi_write(spi, txbuf, 4);
547 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed prog execute res=%d\n", chip->name, res);
554 res = nand_spi_er_busywait(chip, &stat);
555 if (res || (stat & NAND_SPI_ER_STATUS_OIP)) {
556 DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive res=%d stat=%02x\n", chip->name, res, stat);
568 if (stat & (1 << 3)) {
579 * At this point, we are always page aligned so start at column 0.
580 * Note we may not have a full page to write at the end, hence the
581 * check if towrite > len.
584 towrite = device->page_size;
590 mutex_unlock(&chip->lock);
598 res = spi_write(spi, txbuf, 1);
600 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write disable res=%d\n", chip->name, res);
603 mutex_unlock(&chip->lock);
611 static int nand_spi_er_isbad(struct mtd_info *mtd, loff_t ofs)
613 struct nand_spi_er *chip = mtd->priv;
616 if (ofs & (chip->device->erase_size - 1)) {
617 DEBUG(MTD_DEBUG_LEVEL1, "%s: address not aligned %llx\n", chip->name, ofs);
623 return test_bit(block, chip->bbt);
627 * nand_spi_er_markbad
629 static int nand_spi_er_markbad(struct mtd_info *mtd, loff_t ofs)
631 struct nand_spi_er *chip = mtd->priv;
632 struct spi_device *spi = chip->spi;
639 if (ofs & (chip->device->erase_size - 1)) {
640 DEBUG(MTD_DEBUG_LEVEL1, "%s: address not aligned %llx\n", chip->name, ofs);
647 * If it's already marked bad, no need to mark it
649 if (test_bit(block, chip->bbt)) {
654 * Mark it in our cache
656 __set_bit(block, chip->bbt);
659 * Write the user bad block mark. If it fails, then we really
660 * can't do anything about it.
662 mutex_lock(&chip->lock);
663 chip->last_row = NAND_SPI_ER_LAST_ROW_INVALID;
669 res = spi_write(spi, txbuf, 1);
671 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write enable res=%d\n", chip->name, res);
672 mutex_unlock(&chip->lock);
681 txbuf[2] = NAND_SPI_ER_BAD_BLOCK_MARK_OFFSET;
686 res = spi_write(spi, txbuf, 7);
688 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write mark res=%d\n", chip->name, res);
699 txbuf[3] = row & 0xFF;
700 res = spi_write(spi, txbuf, 4);
702 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed program execute res=%d\n", chip->name, res);
709 res = nand_spi_er_busywait(chip, &stat);
710 if (res || (stat & NAND_SPI_ER_STATUS_OIP)) {
711 DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive res=%d stat=%02x\n", chip->name, res, stat);
723 if (stat & (1 << 3)) {
732 res = spi_write(spi, txbuf, 1);
734 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write disable res=%d\n", chip->name, res);
737 mutex_unlock(&chip->lock);
743 * nand_spi_er_read_bbt
745 static int nand_spi_er_read_bbt(struct nand_spi_er *chip)
748 for (j = 0; j < chip->device->blocks; j++) {
753 unsigned short row = j << 6;
762 txbuf[3] = row & 0xFF;
763 res = spi_write(chip->spi, txbuf, 4);
771 res = nand_spi_er_busywait(chip, &stat);
772 if (res || (stat & NAND_SPI_ER_STATUS_OIP)) {
773 DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive res=%d stat=%02x\n", chip->name, res, stat);
785 * Check factory bad block mark
791 res = spi_write_then_read(chip->spi, txbuf, 4, rxbuf, 16);
795 if (rxbuf[0] != 0xFF) {
797 __set_bit(j, chip->bbt);
801 memcpy(&bbmark, &rxbuf[8], 4);
802 if (bbmark == 0xdeadbeef) {
804 __set_bit(j, chip->bbt);
808 #if defined(CONFIG_MTD_DEBUG) && (MTD_DEBUG_LEVEL3 <= CONFIG_MTD_DEBUG_VERBOSE)
809 printk("%s: Bad Block Table:", chip->name);
810 for (j = 0; j < chip->device->blocks; j++) {
812 printk("\n%s: block %03x: ", chip->name, j);
814 printk("%c", test_bit(j, chip->bbt) ? 'X' : '.');
816 printk("\n%s: Bad Block Numbers: ", chip->name);
817 for (j = 0; j < chip->device->blocks; j++) {
818 if (test_bit(j, chip->bbt)) {
830 * Called at boot time:
832 * nand_spi_er=read_only
833 * if read_only specified then do not unlock device
835 static int __init nand_spi_er_setup(char *str)
837 if (str && (strncasecmp(str, "read_only", 9) == 0)) {
843 __setup("nand_spi_er=", nand_spi_er_setup);
848 * Detect and initialize nand_spi_er device.
850 static int __devinit nand_spi_er_probe(struct spi_device *spi)
857 struct nand_spi_er *chip;
858 const struct nand_spi_er_device *device;
860 res = spi_setup(spi);
868 for (i = 0; i < 2; i++) {
870 res = spi_write(spi, txbuf, 1);
883 res = spi_write_then_read(spi, txbuf, 2, rxbuf, 2);
888 device = nand_spi_er_devices;
889 for (i = 0; i < ARRAY_SIZE(nand_spi_er_devices); i++) {
890 if ((device->id0 == rxbuf[0]) && (device->id1 == rxbuf[1])) {
895 if (i == ARRAY_SIZE(nand_spi_er_devices)) {
900 * Initialize our chip structure
902 bbt_bytes = DIV_ROUND_UP(device->blocks, BITS_PER_BYTE);
903 chip = kzalloc(sizeof(struct nand_spi_er) + bbt_bytes, GFP_KERNEL);
907 snprintf(chip->name, sizeof(chip->name), "%s.%d.%d", device->name, spi->master->bus_num, spi->chip_select);
910 chip->device = device;
911 chip->last_row = NAND_SPI_ER_LAST_ROW_INVALID;
913 mutex_init(&chip->lock);
915 chip->mtd.type = MTD_NANDFLASH;
916 chip->mtd.flags = MTD_WRITEABLE;
919 * #blocks * block size * n blocks
921 chip->mtd.size = device->blocks * device->pages_per_block * device->page_size;
922 chip->mtd.erasesize = device->erase_size;
925 * 1 page, optionally we can support partial write (512)
927 chip->mtd.writesize = device->write_size;
928 chip->mtd.name = device->name;
929 chip->mtd.erase = nand_spi_er_erase;
930 chip->mtd.read = nand_spi_er_read;
931 chip->mtd.write = nand_spi_er_write;
932 chip->mtd.block_isbad = nand_spi_er_isbad;
933 chip->mtd.block_markbad = nand_spi_er_markbad;
934 chip->mtd.priv = chip;
937 * Cache the bad block table
939 res = nand_spi_er_read_bbt(chip);
955 res = spi_write(spi, txbuf, 3);
957 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed lock operation res=%d\n", chip->name, res);
958 mutex_unlock(&chip->lock);
962 spi_set_drvdata(spi, chip);
964 printk(KERN_INFO "%s: added device %s size: %u KBytes %u bad blocks %s\n", spi->dev.bus_id, chip->mtd.name, DIV_ROUND_UP(chip->mtd.size, 1024), chip->nbb, read_only ? "[read only]" : "");
965 return add_mtd_device(&chip->mtd);
971 static int __devexit nand_spi_er_remove(struct spi_device *spi)
973 struct nand_spi_er *chip = spi_get_drvdata(spi);
976 DEBUG(MTD_DEBUG_LEVEL1, "%s: remove\n", spi->dev.bus_id);
977 status = del_mtd_device(&chip->mtd);
983 static struct spi_driver nand_spi_er_driver = {
985 .name = "nand-spi-er",
986 .bus = &spi_bus_type,
987 .owner = THIS_MODULE,
990 .probe = nand_spi_er_probe,
991 .remove = __devexit_p(nand_spi_er_remove),
993 /* FIXME: investigate suspend and resume... */
999 static int __init nand_spi_er_init(void)
1001 return spi_register_driver(&nand_spi_er_driver);
1003 module_init(nand_spi_er_init);
1008 static void __exit nand_spi_er_exit(void)
1010 spi_unregister_driver(&nand_spi_er_driver);
1012 module_exit(nand_spi_er_exit);
1015 MODULE_LICENSE("GPL");
1016 MODULE_AUTHOR("Patrick Tjin");
1017 MODULE_DESCRIPTION("MTD nand_spi_er driver");