1 --- a/drivers/spi/Kconfig
2 +++ b/drivers/spi/Kconfig
5 This selects a driver for the Ralink RT288x/RT305x SPI Controller.
8 + tristate "MediaTek MT7621 SPI Controller"
11 + This selects a driver for the MediaTek MT7621 SPI Controller.
14 tristate "Samsung S3C24XX series SPI"
15 depends on ARCH_S3C24XX
16 --- a/drivers/spi/Makefile
17 +++ b/drivers/spi/Makefile
19 obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
20 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
21 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
22 +obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
23 obj-$(CONFIG_SPI_MXS) += spi-mxs.o
24 obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
25 obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
27 +++ b/drivers/spi/spi-mt7621.c
30 + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
32 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
33 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
34 + * Copyright (C) 2014-2015 Felix Fietkau <nbd@openwrt.org>
36 + * Some parts are based on spi-orion.c:
37 + * Author: Shadi Ammouri <shadi@marvell.com>
38 + * Copyright (C) 2007-2008 Marvell Ltd.
40 + * This program is free software; you can redistribute it and/or modify
41 + * it under the terms of the GNU General Public License version 2 as
42 + * published by the Free Software Foundation.
45 +#include <linux/init.h>
46 +#include <linux/module.h>
47 +#include <linux/clk.h>
48 +#include <linux/err.h>
49 +#include <linux/delay.h>
50 +#include <linux/io.h>
51 +#include <linux/reset.h>
52 +#include <linux/spi/spi.h>
53 +#include <linux/of_device.h>
54 +#include <linux/platform_device.h>
55 +#include <linux/swab.h>
57 +#include <ralink_regs.h>
59 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
61 +#define DRIVER_NAME "spi-mt7621"
63 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
65 +/* SPISTAT register bit field */
66 +#define SPISTAT_BUSY BIT(0)
68 +#define MT7621_SPI_TRANS 0x00
69 +#define SPITRANS_BUSY BIT(16)
71 +#define MT7621_SPI_OPCODE 0x04
72 +#define MT7621_SPI_DATA0 0x08
73 +#define MT7621_SPI_DATA4 0x18
74 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
75 +#define SPI_CTL_START BIT(8)
77 +#define MT7621_SPI_POLAR 0x38
78 +#define MT7621_SPI_MASTER 0x28
79 +#define MT7621_SPI_MOREBUF 0x2c
80 +#define MT7621_SPI_SPACE 0x3c
82 +#define MT7621_CPHA BIT(5)
83 +#define MT7621_CPOL BIT(4)
84 +#define MT7621_LSB_FIRST BIT(3)
86 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
91 + struct spi_master *master;
93 + unsigned int sys_freq;
98 + struct mt7621_spi_ops *ops;
101 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
103 + return spi_master_get_devdata(spi->master);
106 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
108 + return ioread32(rs->base + reg);
111 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
113 + iowrite32(val, rs->base + reg);
116 +static void mt7621_spi_reset(struct mt7621_spi *rs)
118 + u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
122 + master &= ~(1 << 10);
124 + mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
127 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
129 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
130 + int cs = spi->chip_select;
133 + mt7621_spi_reset(rs);
136 + mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
139 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
141 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
145 + dev_dbg(&spi->dev, "speed:%u\n", speed);
147 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
148 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
156 + reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
157 + reg &= ~(0xfff << 16);
158 + reg |= (rate - 2) << 16;
161 + reg &= ~MT7621_LSB_FIRST;
162 + if (spi->mode & SPI_LSB_FIRST)
163 + reg |= MT7621_LSB_FIRST;
165 + reg &= ~(MT7621_CPHA | MT7621_CPOL);
166 + switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
170 + reg |= MT7621_CPHA;
173 + reg |= MT7621_CPOL;
176 + reg |= MT7621_CPOL | MT7621_CPHA;
179 + mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
184 +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
186 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
189 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
192 + status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
193 + if ((status & SPITRANS_BUSY) == 0) {
203 +static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
204 + struct spi_message *m)
206 + struct mt7621_spi *rs = spi_master_get_devdata(master);
207 + struct spi_device *spi = m->spi;
208 + unsigned int speed = spi->max_speed_hz;
209 + struct spi_transfer *t = NULL;
213 + u32 data[9] = { 0 };
216 + mt7621_spi_wait_till_ready(spi);
218 + list_for_each_entry(t, &m->transfers, transfer_list) {
219 + const u8 *buf = t->tx_buf;
227 + if (WARN_ON(len + t->len > 36)) {
232 + for (i = 0; i < t->len; i++, len++)
233 + data[len / 4] |= buf[i] << (8 * (len & 3));
236 + if (WARN_ON(rx_len > 32)) {
241 + if (mt7621_spi_prepare(spi, speed)) {
245 + data[0] = swab32(data[0]);
247 + data[0] >>= (4 - len) * 8;
249 + for (i = 0; i < len; i += 4)
250 + mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
252 + val = (min_t(int, len, 4) * 8) << 24;
254 + val |= (len - 4) * 8;
255 + val |= (rx_len * 8) << 12;
256 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
258 + mt7621_spi_set_cs(spi, 1);
260 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
261 + val |= SPI_CTL_START;
262 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
264 + mt7621_spi_wait_till_ready(spi);
266 + mt7621_spi_set_cs(spi, 0);
268 + for (i = 0; i < rx_len; i += 4)
269 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
271 + m->actual_length = len + rx_len;
274 + list_for_each_entry(t, &m->transfers, transfer_list) {
275 + u8 *buf = t->rx_buf;
280 + for (i = 0; i < t->len; i++, len++)
281 + buf[i] = data[len / 4] >> (8 * (len & 3));
285 + m->status = status;
286 + spi_finalize_current_message(master);
291 +static int mt7621_spi_transfer_one_message(struct spi_master *master,
292 + struct spi_message *m)
294 + struct spi_device *spi = m->spi;
295 + int cs = spi->chip_select;
297 + return mt7621_spi_transfer_half_duplex(master, m);
300 +static int mt7621_spi_setup(struct spi_device *spi)
302 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
304 + if ((spi->max_speed_hz == 0) ||
305 + (spi->max_speed_hz > (rs->sys_freq / 2)))
306 + spi->max_speed_hz = (rs->sys_freq / 2);
308 + if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
309 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
310 + spi->max_speed_hz);
317 +static const struct of_device_id mt7621_spi_match[] = {
318 + { .compatible = "ralink,mt7621-spi" },
321 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
323 +static int mt7621_spi_probe(struct platform_device *pdev)
325 + const struct of_device_id *match;
326 + struct spi_master *master;
327 + struct mt7621_spi *rs;
328 + unsigned long flags;
329 + void __iomem *base;
330 + struct resource *r;
333 + struct mt7621_spi_ops *ops;
335 + match = of_match_device(mt7621_spi_match, &pdev->dev);
338 + ops = (struct mt7621_spi_ops *)match->data;
340 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
341 + base = devm_ioremap_resource(&pdev->dev, r);
343 + return PTR_ERR(base);
345 + clk = devm_clk_get(&pdev->dev, NULL);
347 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
349 + return PTR_ERR(clk);
352 + status = clk_prepare_enable(clk);
356 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
357 + if (master == NULL) {
358 + dev_info(&pdev->dev, "master allocation failed\n");
362 + master->mode_bits = RT2880_SPI_MODE_BITS;
364 + master->setup = mt7621_spi_setup;
365 + master->transfer_one_message = mt7621_spi_transfer_one_message;
366 + master->bits_per_word_mask = SPI_BPW_MASK(8);
367 + master->dev.of_node = pdev->dev.of_node;
368 + master->num_chipselect = 2;
370 + dev_set_drvdata(&pdev->dev, master);
372 + rs = spi_master_get_devdata(master);
375 + rs->master = master;
376 + rs->sys_freq = clk_get_rate(rs->clk);
378 + dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
379 + spin_lock_irqsave(&rs->lock, flags);
381 + device_reset(&pdev->dev);
383 + mt7621_spi_reset(rs);
385 + return spi_register_master(master);
388 +static int mt7621_spi_remove(struct platform_device *pdev)
390 + struct spi_master *master;
391 + struct mt7621_spi *rs;
393 + master = dev_get_drvdata(&pdev->dev);
394 + rs = spi_master_get_devdata(master);
396 + clk_disable(rs->clk);
397 + spi_unregister_master(master);
402 +MODULE_ALIAS("platform:" DRIVER_NAME);
404 +static struct platform_driver mt7621_spi_driver = {
406 + .name = DRIVER_NAME,
407 + .owner = THIS_MODULE,
408 + .of_match_table = mt7621_spi_match,
410 + .probe = mt7621_spi_probe,
411 + .remove = mt7621_spi_remove,
414 +module_platform_driver(mt7621_spi_driver);
416 +MODULE_DESCRIPTION("MT7621 SPI driver");
417 +MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
418 +MODULE_LICENSE("GPL");