target/linux/lantiq/patches-3.3/0009-ethernet-support.patch

   1 From a19b113fc05b46605f9ff57c2d15b047d6c392aa Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 3 Aug 2012 09:54:02 +0200
   4 Subject: [PATCH 09/25] ethernet support
   5
   6 ---
   7  drivers/net/ethernet/Kconfig       |   18 ++
   8  drivers/net/ethernet/Makefile      |    3 +
   9  drivers/net/ethernet/lantiq_etop.c |  419 ++++++++++++++++++++++++++----------
  10  net/ipv4/Kconfig                   |    7 +
  11  net/ipv4/Makefile                  |    1 +
  12  5 files changed, 332 insertions(+), 116 deletions(-)
  13
  14 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
  15 index 3474a61..1d91eb6 100644
  16 --- a/drivers/net/ethernet/Kconfig
  17 +++ b/drivers/net/ethernet/Kconfig
  18 @@ -85,6 +85,24 @@ config LANTIQ_ETOP
  19         ---help---
  20           Support for the MII0 inside the Lantiq SoC
  21
  22 +config LANTIQ_VRX200
  23 +       tristate "Lantiq SoC vrx200 driver"
  24 +       depends on SOC_TYPE_XWAY
  25 +       ---help---
  26 +         Support for the MII0 inside the Lantiq SoC
  27 +
  28 +config LANTIQ_SVIP_ETH
  29 +       default y
  30 +       tristate "Lantiq SoC SVIP Ethernet driver"
  31 +       depends on SOC_SVIP
  32 +       help
  33 +         Support for the MII0 inside the Lantiq SVIP SoC
  34 +
  35 +config LANTIQ_SVIP_VIRTUAL_ETH
  36 +       default y
  37 +       tristate "Lantiq SoC SVIP Virtual Ethernet driver"
  38 +       depends on SOC_SVIP
  39 +
  40  source "drivers/net/ethernet/marvell/Kconfig"
  41  source "drivers/net/ethernet/mellanox/Kconfig"
  42  source "drivers/net/ethernet/micrel/Kconfig"
  43 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
  44 index 08d5f03..c8fb1b3 100644
  45 --- a/drivers/net/ethernet/Makefile
  46 +++ b/drivers/net/ethernet/Makefile
  47 @@ -36,6 +36,9 @@ obj-$(CONFIG_IP1000) += icplus/
  48  obj-$(CONFIG_JME) += jme.o
  49  obj-$(CONFIG_KORINA) += korina.o
  50  obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
  51 +obj-$(CONFIG_LANTIQ_VRX200) += lantiq_vrx200.o
  52 +obj-$(CONFIG_LANTIQ_SVIP_ETH) += svip_eth.o
  53 +obj-$(CONFIG_LANTIQ_SVIP_VIRTUAL_ETH) += svip_virtual_eth.o
  54  obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
  55  obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
  56  obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
  57 diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
  58 index 85e2c6c..97ddb09 100644
  59 --- a/drivers/net/ethernet/lantiq_etop.c
  60 +++ b/drivers/net/ethernet/lantiq_etop.c
  61 @@ -36,6 +36,7 @@
  62  #include <linux/io.h>
  63  #include <linux/dma-mapping.h>
  64  #include <linux/module.h>
  65 +#include <linux/clk.h>
  66
  67  #include <asm/checksum.h>
  68
  69 @@ -71,25 +72,55 @@
  70  #define ETOP_MII_REVERSE       0xe
  71  #define ETOP_PLEN_UNDER                0x40
  72  #define ETOP_CGEN              0x800
  73 -
  74 -/* use 2 static channels for TX/RX */
  75 -#define LTQ_ETOP_TX_CHANNEL    1
  76 -#define LTQ_ETOP_RX_CHANNEL    6
  77 -#define IS_TX(x)               (x == LTQ_ETOP_TX_CHANNEL)
  78 -#define IS_RX(x)               (x == LTQ_ETOP_RX_CHANNEL)
  79 +#define ETOP_CFG_MII0          0x01
  80 +
  81 +#define LTQ_GBIT_MDIO_CTL      0xCC
  82 +#define LTQ_GBIT_MDIO_DATA     0xd0
  83 +#define LTQ_GBIT_GCTL0         0x68
  84 +#define LTQ_GBIT_PMAC_HD_CTL   0x8c
  85 +#define LTQ_GBIT_P0_CTL                0x4
  86 +#define LTQ_GBIT_PMAC_RX_IPG   0xa8
  87 +
  88 +#define PMAC_HD_CTL_AS         (1 << 19)
  89 +#define PMAC_HD_CTL_RXSH       (1 << 22)
  90 +
  91 +/* Switch Enable (0=disable, 1=enable) */
  92 +#define GCTL0_SE               0x80000000
  93 +/* Disable MDIO auto polling (0=disable, 1=enable) */
  94 +#define PX_CTL_DMDIO           0x00400000
  95 +
  96 +/* register information for the gbit's MDIO bus */
  97 +#define MDIO_XR9_REQUEST       0x00008000
  98 +#define MDIO_XR9_READ          0x00000800
  99 +#define MDIO_XR9_WRITE         0x00000400
 100 +#define MDIO_XR9_REG_MASK      0x1f
 101 +#define MDIO_XR9_ADDR_MASK     0x1f
 102 +#define MDIO_XR9_RD_MASK       0xffff
 103 +#define MDIO_XR9_REG_OFFSET    0
 104 +#define MDIO_XR9_ADDR_OFFSET   5
 105 +#define MDIO_XR9_WR_OFFSET     16
 106 +
 107 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
 108 +#define ltq_has_gbit()         (ltq_is_ar9() || ltq_is_vr9())
 109
 110  #define ltq_etop_r32(x)                ltq_r32(ltq_etop_membase + (x))
 111  #define ltq_etop_w32(x, y)     ltq_w32(x, ltq_etop_membase + (y))
 112  #define ltq_etop_w32_mask(x, y, z)     \
 113                 ltq_w32_mask(x, y, ltq_etop_membase + (z))
 114
 115 +#define ltq_gbit_r32(x)                ltq_r32(ltq_gbit_membase + (x))
 116 +#define ltq_gbit_w32(x, y)     ltq_w32(x, ltq_gbit_membase + (y))
 117 +#define ltq_gbit_w32_mask(x, y, z)     \
 118 +               ltq_w32_mask(x, y, ltq_gbit_membase + (z))
 119 +
 120  #define DRV_VERSION    "1.0"
 121
 122  static void __iomem *ltq_etop_membase;
 123 +static void __iomem *ltq_gbit_membase;
 124
 125  struct ltq_etop_chan {
 126 -       int idx;
 127         int tx_free;
 128 +       int irq;
 129         struct net_device *netdev;
 130         struct napi_struct napi;
 131         struct ltq_dma_channel dma;
 132 @@ -105,12 +136,20 @@ struct ltq_etop_priv {
 133         struct mii_bus *mii_bus;
 134         struct phy_device *phydev;
 135
 136 -       struct ltq_etop_chan ch[MAX_DMA_CHAN];
 137 -       int tx_free[MAX_DMA_CHAN >> 1];
 138 +       struct ltq_etop_chan txch;
 139 +       struct ltq_etop_chan rxch;
 140
 141         spinlock_t lock;
 142 +
 143 +       struct clk *clk_ppe;
 144 +       struct clk *clk_switch;
 145 +       struct clk *clk_ephy;
 146 +       struct clk *clk_ephycgu;
 147  };
 148
 149 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
 150 +                               int phy_reg, u16 phy_data);
 151 +
 152  static int
 153  ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
 154  {
 155 @@ -159,8 +198,10 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
 156  {
 157         struct ltq_etop_chan *ch = container_of(napi,
 158                                 struct ltq_etop_chan, napi);
 159 +       struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 160         int rx = 0;
 161         int complete = 0;
 162 +       unsigned long flags;
 163
 164         while ((rx < budget) && !complete) {
 165                 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 166 @@ -174,7 +215,9 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
 167         }
 168         if (complete || !rx) {
 169                 napi_complete(&ch->napi);
 170 +               spin_lock_irqsave(&priv->lock, flags);
 171                 ltq_dma_ack_irq(&ch->dma);
 172 +               spin_unlock_irqrestore(&priv->lock, flags);
 173         }
 174         return rx;
 175  }
 176 @@ -186,7 +229,7 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
 177                 container_of(napi, struct ltq_etop_chan, napi);
 178         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 179         struct netdev_queue *txq =
 180 -               netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
 181 +               netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
 182         unsigned long flags;
 183
 184         spin_lock_irqsave(&priv->lock, flags);
 185 @@ -204,7 +247,9 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
 186         if (netif_tx_queue_stopped(txq))
 187                 netif_tx_start_queue(txq);
 188         napi_complete(&ch->napi);
 189 +       spin_lock_irqsave(&priv->lock, flags);
 190         ltq_dma_ack_irq(&ch->dma);
 191 +       spin_unlock_irqrestore(&priv->lock, flags);
 192         return 1;
 193  }
 194
 195 @@ -212,9 +257,10 @@ static irqreturn_t
 196  ltq_etop_dma_irq(int irq, void *_priv)
 197  {
 198         struct ltq_etop_priv *priv = _priv;
 199 -       int ch = irq - LTQ_DMA_CH0_INT;
 200 -
 201 -       napi_schedule(&priv->ch[ch].napi);
 202 +       if (irq == priv->txch.dma.irq)
 203 +               napi_schedule(&priv->txch.napi);
 204 +       else
 205 +               napi_schedule(&priv->rxch.napi);
 206         return IRQ_HANDLED;
 207  }
 208
 209 @@ -226,7 +272,7 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
 210         ltq_dma_free(&ch->dma);
 211         if (ch->dma.irq)
 212                 free_irq(ch->dma.irq, priv);
 213 -       if (IS_RX(ch->idx)) {
 214 +       if (ch == &priv->txch) {
 215                 int desc;
 216                 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
 217                         dev_kfree_skb_any(ch->skb[ch->dma.desc]);
 218 @@ -237,23 +283,56 @@ static void
 219  ltq_etop_hw_exit(struct net_device *dev)
 220  {
 221         struct ltq_etop_priv *priv = netdev_priv(dev);
 222 -       int i;
 223
 224 -       ltq_pmu_disable(PMU_PPE);
 225 -       for (i = 0; i < MAX_DMA_CHAN; i++)
 226 -               if (IS_TX(i) || IS_RX(i))
 227 -                       ltq_etop_free_channel(dev, &priv->ch[i]);
 228 +       clk_disable(priv->clk_ppe);
 229 +
 230 +       if (ltq_has_gbit())
 231 +               clk_disable(priv->clk_switch);
 232 +
 233 +       if (ltq_is_ase()) {
 234 +               clk_disable(priv->clk_ephy);
 235 +               clk_disable(priv->clk_ephycgu);
 236 +       }
 237 +
 238 +       ltq_etop_free_channel(dev, &priv->txch);
 239 +       ltq_etop_free_channel(dev, &priv->rxch);
 240 +}
 241 +
 242 +static void
 243 +ltq_etop_gbit_init(struct net_device *dev)
 244 +{
 245 +       struct ltq_etop_priv *priv = netdev_priv(dev);
 246 +
 247 +       clk_enable(priv->clk_switch);
 248 +
 249 +       ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
 250 +       /** Disable MDIO auto polling mode */
 251 +       ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
 252 +       /* set 1522 packet size */
 253 +       ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
 254 +       /* disable pmac & dmac headers */
 255 +       ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
 256 +               LTQ_GBIT_PMAC_HD_CTL);
 257 +       /* Due to traffic halt when burst length 8,
 258 +               replace default IPG value with 0x3B */
 259 +       ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
 260  }
 261
 262  static int
 263  ltq_etop_hw_init(struct net_device *dev)
 264  {
 265         struct ltq_etop_priv *priv = netdev_priv(dev);
 266 -       int i;
 267 +       unsigned int mii_mode = priv->pldata->mii_mode;
 268
 269 -       ltq_pmu_enable(PMU_PPE);
 270 +       clk_enable(priv->clk_ppe);
 271
 272 -       switch (priv->pldata->mii_mode) {
 273 +       if (ltq_has_gbit()) {
 274 +               ltq_etop_gbit_init(dev);
 275 +               /* force the etops link to the gbit to MII */
 276 +               mii_mode = PHY_INTERFACE_MODE_MII;
 277 +       }
 278 +
 279 +       switch (mii_mode) {
 280         case PHY_INTERFACE_MODE_RMII:
 281                 ltq_etop_w32_mask(ETOP_MII_MASK,
 282                         ETOP_MII_REVERSE, LTQ_ETOP_CFG);
 283 @@ -265,6 +344,18 @@ ltq_etop_hw_init(struct net_device *dev)
 284                 break;
 285
 286         default:
 287 +               if (ltq_is_ase()) {
 288 +                       clk_enable(priv->clk_ephy);
 289 +                       /* disable external MII */
 290 +                       ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
 291 +                       /* enable clock for internal PHY */
 292 +                       clk_enable(priv->clk_ephycgu);
 293 +                       /* we need to write this magic to the internal phy to
 294 +                          make it work */
 295 +                       ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
 296 +                       pr_info("Selected EPHY mode\n");
 297 +                       break;
 298 +               }
 299                 netdev_err(dev, "unknown mii mode %d\n",
 300                         priv->pldata->mii_mode);
 301                 return -ENOTSUPP;
 302 @@ -273,31 +364,51 @@ ltq_etop_hw_init(struct net_device *dev)
 303         /* enable crc generation */
 304         ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
 305
 306 +       return 0;
 307 +}
 308 +
 309 +static int
 310 +ltq_etop_dma_init(struct net_device *dev)
 311 +{
 312 +       struct ltq_etop_priv *priv = netdev_priv(dev);
 313 +       int tx = 1;
 314 +       int rx = ((ltq_is_ase()) ? (5) : \
 315 +               ((ltq_is_ar9()) ? (0) : (6)));
 316 +       int tx_irq = LTQ_DMA_ETOP + tx;
 317 +       int rx_irq = LTQ_DMA_ETOP + rx;
 318 +       int err;
 319 +
 320         ltq_dma_init_port(DMA_PORT_ETOP);
 321
 322 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 323 -               int irq = LTQ_DMA_CH0_INT + i;
 324 -               struct ltq_etop_chan *ch = &priv->ch[i];
 325 -
 326 -               ch->idx = ch->dma.nr = i;
 327 -
 328 -               if (IS_TX(i)) {
 329 -                       ltq_dma_alloc_tx(&ch->dma);
 330 -                       request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
 331 -                               "etop_tx", priv);
 332 -               } else if (IS_RX(i)) {
 333 -                       ltq_dma_alloc_rx(&ch->dma);
 334 -                       for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
 335 -                                       ch->dma.desc++)
 336 -                               if (ltq_etop_alloc_skb(ch))
 337 -                                       return -ENOMEM;
 338 -                       ch->dma.desc = 0;
 339 -                       request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
 340 -                               "etop_rx", priv);
 341 +       priv->txch.dma.nr = tx;
 342 +       ltq_dma_alloc_tx(&priv->txch.dma);
 343 +       err = request_irq(tx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
 344 +               "eth_tx", priv);
 345 +       if (err) {
 346 +               netdev_err(dev, "failed to allocate tx irq\n");
 347 +               goto err_out;
 348 +       }
 349 +       priv->txch.dma.irq = tx_irq;
 350 +
 351 +       priv->rxch.dma.nr = rx;
 352 +       ltq_dma_alloc_rx(&priv->rxch.dma);
 353 +       for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
 354 +                       priv->rxch.dma.desc++) {
 355 +               if (ltq_etop_alloc_skb(&priv->rxch)) {
 356 +                       netdev_err(dev, "failed to allocate skbs\n");
 357 +                       err = -ENOMEM;
 358 +                       goto err_out;
 359                 }
 360 -               ch->dma.irq = irq;
 361         }
 362 -       return 0;
 363 +       priv->rxch.dma.desc = 0;
 364 +       err = request_irq(rx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
 365 +               "eth_rx", priv);
 366 +       if (err)
 367 +               netdev_err(dev, "failed to allocate rx irq\n");
 368 +       else
 369 +               priv->rxch.dma.irq = rx_irq;
 370 +err_out:
 371 +       return err;
 372  }
 373
 374  static void
 375 @@ -313,7 +424,10 @@ ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 376  {
 377         struct ltq_etop_priv *priv = netdev_priv(dev);
 378
 379 -       return phy_ethtool_gset(priv->phydev, cmd);
 380 +       if (priv->phydev)
 381 +               return phy_ethtool_gset(priv->phydev, cmd);
 382 +       else
 383 +               return 0;
 384  }
 385
 386  static int
 387 @@ -321,7 +435,10 @@ ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 388  {
 389         struct ltq_etop_priv *priv = netdev_priv(dev);
 390
 391 -       return phy_ethtool_sset(priv->phydev, cmd);
 392 +       if (priv->phydev)
 393 +               return phy_ethtool_sset(priv->phydev, cmd);
 394 +       else
 395 +               return 0;
 396  }
 397
 398  static int
 399 @@ -329,7 +446,10 @@ ltq_etop_nway_reset(struct net_device *dev)
 400  {
 401         struct ltq_etop_priv *priv = netdev_priv(dev);
 402
 403 -       return phy_start_aneg(priv->phydev);
 404 +       if (priv->phydev)
 405 +               return phy_start_aneg(priv->phydev);
 406 +       else
 407 +               return 0;
 408  }
 409
 410  static const struct ethtool_ops ltq_etop_ethtool_ops = {
 411 @@ -340,6 +460,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = {
 412  };
 413
 414  static int
 415 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
 416 +               int phy_reg, u16 phy_data)
 417 +{
 418 +       u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
 419 +               (phy_data << MDIO_XR9_WR_OFFSET) |
 420 +               ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
 421 +               ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
 422 +
 423 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 424 +               ;
 425 +       ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
 426 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 427 +               ;
 428 +       return 0;
 429 +}
 430 +
 431 +static int
 432 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
 433 +{
 434 +       u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
 435 +               ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
 436 +               ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
 437 +
 438 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 439 +               ;
 440 +       ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
 441 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 442 +               ;
 443 +       val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
 444 +       return val;
 445 +}
 446 +
 447 +static int
 448  ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
 449  {
 450         u32 val = MDIO_REQUEST |
 451 @@ -380,14 +533,11 @@ ltq_etop_mdio_probe(struct net_device *dev)
 452  {
 453         struct ltq_etop_priv *priv = netdev_priv(dev);
 454         struct phy_device *phydev = NULL;
 455 -       int phy_addr;
 456
 457 -       for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
 458 -               if (priv->mii_bus->phy_map[phy_addr]) {
 459 -                       phydev = priv->mii_bus->phy_map[phy_addr];
 460 -                       break;
 461 -               }
 462 -       }
 463 +       if (ltq_is_ase())
 464 +               phydev = priv->mii_bus->phy_map[8];
 465 +       else
 466 +               phydev = priv->mii_bus->phy_map[0];
 467
 468         if (!phydev) {
 469                 netdev_err(dev, "no PHY found\n");
 470 @@ -409,6 +559,9 @@ ltq_etop_mdio_probe(struct net_device *dev)
 471                               | SUPPORTED_Autoneg
 472                               | SUPPORTED_MII
 473                               | SUPPORTED_TP);
 474 +       if (ltq_has_gbit())
 475 +               phydev->supported &= SUPPORTED_1000baseT_Half
 476 +                                       | SUPPORTED_1000baseT_Full;
 477
 478         phydev->advertising = phydev->supported;
 479         priv->phydev = phydev;
 480 @@ -434,8 +587,13 @@ ltq_etop_mdio_init(struct net_device *dev)
 481         }
 482
 483         priv->mii_bus->priv = dev;
 484 -       priv->mii_bus->read = ltq_etop_mdio_rd;
 485 -       priv->mii_bus->write = ltq_etop_mdio_wr;
 486 +       if (ltq_has_gbit()) {
 487 +               priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
 488 +               priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
 489 +       } else {
 490 +               priv->mii_bus->read = ltq_etop_mdio_rd;
 491 +               priv->mii_bus->write = ltq_etop_mdio_wr;
 492 +       }
 493         priv->mii_bus->name = "ltq_mii";
 494         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
 495                 priv->pdev->name, priv->pdev->id);
 496 @@ -484,17 +642,19 @@ static int
 497  ltq_etop_open(struct net_device *dev)
 498  {
 499         struct ltq_etop_priv *priv = netdev_priv(dev);
 500 -       int i;
 501 +       unsigned long flags;
 502
 503 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 504 -               struct ltq_etop_chan *ch = &priv->ch[i];
 505 +       napi_enable(&priv->txch.napi);
 506 +       napi_enable(&priv->rxch.napi);
 507 +
 508 +       spin_lock_irqsave(&priv->lock, flags);
 509 +       ltq_dma_open(&priv->txch.dma);
 510 +       ltq_dma_open(&priv->rxch.dma);
 511 +       spin_unlock_irqrestore(&priv->lock, flags);
 512 +
 513 +       if (priv->phydev)
 514 +               phy_start(priv->phydev);
 515
 516 -               if (!IS_TX(i) && (!IS_RX(i)))
 517 -                       continue;
 518 -               ltq_dma_open(&ch->dma);
 519 -               napi_enable(&ch->napi);
 520 -       }
 521 -       phy_start(priv->phydev);
 522         netif_tx_start_all_queues(dev);
 523         return 0;
 524  }
 525 @@ -503,18 +663,19 @@ static int
 526  ltq_etop_stop(struct net_device *dev)
 527  {
 528         struct ltq_etop_priv *priv = netdev_priv(dev);
 529 -       int i;
 530 +       unsigned long flags;
 531
 532         netif_tx_stop_all_queues(dev);
 533 -       phy_stop(priv->phydev);
 534 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 535 -               struct ltq_etop_chan *ch = &priv->ch[i];
 536 +       if (priv->phydev)
 537 +               phy_stop(priv->phydev);
 538 +       napi_disable(&priv->txch.napi);
 539 +       napi_disable(&priv->rxch.napi);
 540 +
 541 +       spin_lock_irqsave(&priv->lock, flags);
 542 +       ltq_dma_close(&priv->txch.dma);
 543 +       ltq_dma_close(&priv->rxch.dma);
 544 +       spin_unlock_irqrestore(&priv->lock, flags);
 545
 546 -               if (!IS_RX(i) && !IS_TX(i))
 547 -                       continue;
 548 -               napi_disable(&ch->napi);
 549 -               ltq_dma_close(&ch->dma);
 550 -       }
 551         return 0;
 552  }
 553
 554 @@ -524,16 +685,16 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
 555         int queue = skb_get_queue_mapping(skb);
 556         struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
 557         struct ltq_etop_priv *priv = netdev_priv(dev);
 558 -       struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
 559 -       struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 560 -       int len;
 561 +       struct ltq_dma_desc *desc =
 562 +               &priv->txch.dma.desc_base[priv->txch.dma.desc];
 563         unsigned long flags;
 564         u32 byte_offset;
 565 +       int len;
 566
 567         len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
 568
 569 -       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
 570 -               dev_kfree_skb_any(skb);
 571 +       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
 572 +                       priv->txch.skb[priv->txch.dma.desc]) {
 573                 netdev_err(dev, "tx ring full\n");
 574                 netif_tx_stop_queue(txq);
 575                 return NETDEV_TX_BUSY;
 576 @@ -541,7 +702,7 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
 577
 578         /* dma needs to start on a 16 byte aligned address */
 579         byte_offset = CPHYSADDR(skb->data) % 16;
 580 -       ch->skb[ch->dma.desc] = skb;
 581 +       priv->txch.skb[priv->txch.dma.desc] = skb;
 582
 583         dev->trans_start = jiffies;
 584
 585 @@ -551,11 +712,11 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
 586         wmb();
 587         desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
 588                 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
 589 -       ch->dma.desc++;
 590 -       ch->dma.desc %= LTQ_DESC_NUM;
 591 +       priv->txch.dma.desc++;
 592 +       priv->txch.dma.desc %= LTQ_DESC_NUM;
 593         spin_unlock_irqrestore(&priv->lock, flags);
 594
 595 -       if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
 596 +       if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
 597                 netif_tx_stop_queue(txq);
 598
 599         return NETDEV_TX_OK;
 600 @@ -640,6 +801,10 @@ ltq_etop_init(struct net_device *dev)
 601         err = ltq_etop_hw_init(dev);
 602         if (err)
 603                 goto err_hw;
 604 +       err = ltq_etop_dma_init(dev);
 605 +       if (err)
 606 +               goto err_hw;
 607 +
 608         ltq_etop_change_mtu(dev, 1500);
 609
 610         memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
 611 @@ -652,9 +817,10 @@ ltq_etop_init(struct net_device *dev)
 612         if (err)
 613                 goto err_netdev;
 614         ltq_etop_set_multicast_list(dev);
 615 -       err = ltq_etop_mdio_init(dev);
 616 -       if (err)
 617 -               goto err_netdev;
 618 +       if (!ltq_etop_mdio_init(dev))
 619 +               dev->ethtool_ops = &ltq_etop_ethtool_ops;
 620 +       else
 621 +               pr_warn("etop: mdio probe failed\n");;
 622         return 0;
 623
 624  err_netdev:
 625 @@ -674,6 +840,9 @@ ltq_etop_tx_timeout(struct net_device *dev)
 626         err = ltq_etop_hw_init(dev);
 627         if (err)
 628                 goto err_hw;
 629 +       err = ltq_etop_dma_init(dev);
 630 +       if (err)
 631 +               goto err_hw;
 632         dev->trans_start = jiffies;
 633         netif_wake_queue(dev);
 634         return;
 635 @@ -697,14 +866,13 @@ static const struct net_device_ops ltq_eth_netdev_ops = {
 636         .ndo_tx_timeout = ltq_etop_tx_timeout,
 637  };
 638
 639 -static int __init
 640 +static int __devinit
 641  ltq_etop_probe(struct platform_device *pdev)
 642  {
 643         struct net_device *dev;
 644         struct ltq_etop_priv *priv;
 645 -       struct resource *res;
 646 +       struct resource *res, *gbit_res;
 647         int err;
 648 -       int i;
 649
 650         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 651         if (!res) {
 652 @@ -730,27 +898,62 @@ ltq_etop_probe(struct platform_device *pdev)
 653                 goto err_out;
 654         }
 655
 656 +       if (ltq_has_gbit()) {
 657 +               gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 658 +               if (!gbit_res) {
 659 +                       dev_err(&pdev->dev, "failed to get gbit resource\n");
 660 +                       err = -ENOENT;
 661 +                       goto err_out;
 662 +               }
 663 +               ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
 664 +                       gbit_res->start, resource_size(gbit_res));
 665 +               if (!ltq_gbit_membase) {
 666 +                       dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
 667 +                               pdev->id);
 668 +                       err = -ENOMEM;
 669 +                       goto err_out;
 670 +               }
 671 +               if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") ||
 672 +                               ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) {
 673 +                       dev_err(&pdev->dev, "failed to request MDIO gpios\n");
 674 +                       err = -EBUSY;
 675 +                       goto err_out;
 676 +               }
 677 +       }
 678 +
 679         dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 680         strcpy(dev->name, "eth%d");
 681         dev->netdev_ops = &ltq_eth_netdev_ops;
 682 -       dev->ethtool_ops = &ltq_etop_ethtool_ops;
 683         priv = netdev_priv(dev);
 684         priv->res = res;
 685         priv->pdev = pdev;
 686         priv->pldata = dev_get_platdata(&pdev->dev);
 687         priv->netdev = dev;
 688 -       spin_lock_init(&priv->lock);
 689
 690 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 691 -               if (IS_TX(i))
 692 -                       netif_napi_add(dev, &priv->ch[i].napi,
 693 -                               ltq_etop_poll_tx, 8);
 694 -               else if (IS_RX(i))
 695 -                       netif_napi_add(dev, &priv->ch[i].napi,
 696 -                               ltq_etop_poll_rx, 32);
 697 -               priv->ch[i].netdev = dev;
 698 +       priv->clk_ppe = clk_get(&pdev->dev, NULL);
 699 +       if (IS_ERR(priv->clk_ppe))
 700 +               return PTR_ERR(priv->clk_ppe);
 701 +       if (ltq_has_gbit()) {
 702 +               priv->clk_switch = clk_get(&pdev->dev, "switch");
 703 +               if (IS_ERR(priv->clk_switch))
 704 +                       return PTR_ERR(priv->clk_switch);
 705 +       }
 706 +       if (ltq_is_ase()) {
 707 +               priv->clk_ephy = clk_get(&pdev->dev, "ephy");
 708 +               if (IS_ERR(priv->clk_ephy))
 709 +                       return PTR_ERR(priv->clk_ephy);
 710 +               priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
 711 +               if (IS_ERR(priv->clk_ephycgu))
 712 +                       return PTR_ERR(priv->clk_ephycgu);
 713         }
 714
 715 +       spin_lock_init(&priv->lock);
 716 +
 717 +       netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
 718 +       netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
 719 +       priv->txch.netdev = dev;
 720 +       priv->rxch.netdev = dev;
 721 +
 722         err = register_netdev(dev);
 723         if (err)
 724                 goto err_free;
 725 @@ -779,6 +982,7 @@ ltq_etop_remove(struct platform_device *pdev)
 726  }
 727
 728  static struct platform_driver ltq_mii_driver = {
 729 +       .probe = ltq_etop_probe,
 730         .remove = __devexit_p(ltq_etop_remove),
 731         .driver = {
 732                 .name = "ltq_etop",
 733 @@ -786,24 +990,7 @@ static struct platform_driver ltq_mii_driver = {
 734         },
 735  };
 736
 737 -int __init
 738 -init_ltq_etop(void)
 739 -{
 740 -       int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
 741 -
 742 -       if (ret)
 743 -               pr_err("ltq_etop: Error registering platfom driver!");
 744 -       return ret;
 745 -}
 746 -
 747 -static void __exit
 748 -exit_ltq_etop(void)
 749 -{
 750 -       platform_driver_unregister(&ltq_mii_driver);
 751 -}
 752 -
 753 -module_init(init_ltq_etop);
 754 -module_exit(exit_ltq_etop);
 755 +module_platform_driver(ltq_mii_driver);
 756
 757  MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 758  MODULE_DESCRIPTION("Lantiq SoC ETOP");
 759 diff --git a/net/ipv4/Kconfig b/net/ipv4/Kconfig
 760 index d183262..7d444e0 100644
 761 --- a/net/ipv4/Kconfig
 762 +++ b/net/ipv4/Kconfig
 763 @@ -630,3 +630,10 @@ config TCP_MD5SIG
 764           on the Internet.
 765
 766           If unsure, say N.
 767 +
 768 +config SVIP_NAT
 769 +       bool "Include SVIP NAT"
 770 +       depends on SOC_SVIP
 771 +       default y
 772 +       ---help---
 773 +         Include the SVIP NAT.
 774 diff --git a/net/ipv4/Makefile b/net/ipv4/Makefile
 775 index ff75d3b..1d57fe0 100644
 776 --- a/net/ipv4/Makefile
 777 +++ b/net/ipv4/Makefile
 778 @@ -53,3 +53,4 @@ obj-$(CONFIG_NETLABEL) += cipso_ipv4.o
 779
 780  obj-$(CONFIG_XFRM) += xfrm4_policy.o xfrm4_state.o xfrm4_input.o \
 781                       xfrm4_output.o
 782 +obj-$(CONFIG_SVIP_NAT) += svip_nat.o
 783 --
 784 1.7.9.1
 785