target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; either version 2 of the License, or
   5  *   (at your option) any later version.
   6  *
   7  *   This program is distributed in the hope that it will be useful,
   8  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *   GNU General Public License for more details.
  11  *
  12  *   You should have received a copy of the GNU General Public License
  13  *   along with this program; if not, write to the Free Software
  14  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  15  *
  16  *   Copyright (C) 2005 Wu Qi Ming infineon
  17  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/sched.h>
  22 #include <linux/slab.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/kernel_stat.h>
  25 #include <linux/module.h>
  26
  27 #include <asm/bootinfo.h>
  28 #include <asm/irq.h>
  29 #include <asm/ifxmips/ifxmips.h>
  30 #include <asm/ifxmips/ifxmips_irq.h>
  31 #include <asm/irq_cpu.h>
  32
  33 void
  34 ifxmips_disable_irq(unsigned int irq_nr)
  35 {
  36         int i;
  37         u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
  38
  39         irq_nr -= INT_NUM_IRQ0;
  40         for(i = 0; i <= 4; i++)
  41         {
  42                 if(irq_nr < INT_NUM_IM_OFFSET){
  43                         ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
  44                         return;
  45                 }
  46                 ifxmips_ier += IFXMIPS_ICU_OFFSET;
  47                 irq_nr -= INT_NUM_IM_OFFSET;
  48         }
  49 }
  50 EXPORT_SYMBOL(ifxmips_disable_irq);
  51
  52 void
  53 ifxmips_mask_and_ack_irq(unsigned int irq_nr)
  54 {
  55         int i;
  56         u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
  57         u32 *ifxmips_isr = IFXMIPS_ICU_IM0_ISR;
  58
  59         irq_nr -= INT_NUM_IRQ0;
  60         for(i = 0; i <= 4; i++)
  61         {
  62                 if(irq_nr < INT_NUM_IM_OFFSET)
  63                 {
  64                         ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
  65                         ifxmips_w32((1 << irq_nr ), ifxmips_isr);
  66                         return;
  67                 }
  68                 ifxmips_ier += IFXMIPS_ICU_OFFSET;
  69                 ifxmips_isr += IFXMIPS_ICU_OFFSET;
  70                 irq_nr -= INT_NUM_IM_OFFSET;
  71         }
  72 }
  73 EXPORT_SYMBOL(ifxmips_mask_and_ack_irq);
  74
  75 void
  76 ifxmips_enable_irq(unsigned int irq_nr)
  77 {
  78         int i;
  79         u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
  80
  81         irq_nr -= INT_NUM_IRQ0;
  82         for(i = 0; i <= 4; i++)
  83         {
  84                 if(irq_nr < INT_NUM_IM_OFFSET)
  85                 {
  86                         ifxmips_w32(ifxmips_r32(ifxmips_ier) | (1 << irq_nr ), ifxmips_ier);
  87                         return;
  88                 }
  89                 ifxmips_ier += IFXMIPS_ICU_OFFSET;
  90                 irq_nr -= INT_NUM_IM_OFFSET;
  91         }
  92 }
  93 EXPORT_SYMBOL(ifxmips_enable_irq);
  94
  95 static unsigned int
  96 ifxmips_startup_irq(unsigned int irq)
  97 {
  98         ifxmips_enable_irq(irq);
  99         return 0;
 100 }
 101
 102 static void
 103 ifxmips_end_irq(unsigned int irq)
 104 {
 105         if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 106                 ifxmips_enable_irq (irq);
 107 }
 108
 109 static struct hw_interrupt_type
 110 ifxmips_irq_type = {
 111         "IFXMIPS",
 112         .startup = ifxmips_startup_irq,
 113         .enable = ifxmips_enable_irq,
 114         .disable = ifxmips_disable_irq,
 115         .unmask = ifxmips_enable_irq,
 116         .ack = ifxmips_end_irq,
 117         .mask = ifxmips_disable_irq,
 118         .mask_ack = ifxmips_mask_and_ack_irq,
 119         .end = ifxmips_end_irq,
 120 };
 121
 122 static inline int
 123 ls1bit32(unsigned long x)
 124 {
 125         __asm__ (
 126                 ".set push \n"
 127                 ".set mips32 \n"
 128                 "clz %0, %1 \n"
 129                 ".set pop \n"
 130                 : "=r" (x)
 131                 : "r" (x));
 132         return 31 - x;
 133 }
 134
 135 void
 136 ifxmips_hw_irqdispatch(int module)
 137 {
 138         u32 irq;
 139
 140         irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
 141         if(irq == 0)
 142                 return;
 143
 144         irq = ls1bit32(irq);
 145         do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
 146
 147         if((irq == 22) && (module == 0)){
 148                 ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10, IFXMIPS_EBU_PCC_ISTAT);
 149         }
 150 }
 151
 152 asmlinkage void
 153 plat_irq_dispatch(void)
 154 {
 155         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 156         unsigned int i;
 157
 158         if(pending & CAUSEF_IP7)
 159         {
 160                 do_IRQ(MIPS_CPU_TIMER_IRQ);
 161                 goto out;
 162         } else {
 163                 for(i = 0; i < 5; i++)
 164                 {
 165                         if(pending & (CAUSEF_IP2 << i))
 166                         {
 167                                 ifxmips_hw_irqdispatch(i);
 168                                 goto out;
 169                         }
 170                 }
 171         }
 172         printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
 173
 174 out:
 175         return;
 176 }
 177
 178 static struct irqaction
 179 cascade = {
 180         .handler = no_action,
 181         .flags = IRQF_DISABLED,
 182         .name = "cascade",
 183 };
 184
 185 void __init
 186 arch_init_irq(void)
 187 {
 188         int i;
 189
 190         for(i = 0; i < 5; i++)
 191                 ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
 192
 193         mips_cpu_irq_init();
 194
 195         for(i = 2; i <= 6; i++)
 196                 setup_irq(i, &cascade);
 197
 198         for(i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
 199                 set_irq_chip_and_handler(i, &ifxmips_irq_type, handle_level_irq);
 200
 201         set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 202 }