target/linux/ifxmips/files/arch/mips/ifxmips/clock.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; either version 2 of the License, or
   5  *   (at your option) any later version.
   6  *
   7  *   This program is distributed in the hope that it will be useful,
   8  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *   GNU General Public License for more details.
  11  *
  12  *   You should have received a copy of the GNU General Public License
  13  *   along with this program; if not, write to the Free Software
  14  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  15  *
  16  *   Copyright (C) 2007 Xu Liang, infineon
  17  *   Copyright (C) 2008 John Crispin <blogic@openwrt.org>
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/version.h>
  23 #include <linux/types.h>
  24 #include <linux/fs.h>
  25 #include <linux/miscdevice.h>
  26 #include <linux/init.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/unistd.h>
  29 #include <asm/irq.h>
  30 #include <asm/div64.h>
  31 #include <linux/errno.h>
  32 #include <asm/ifxmips/ifxmips.h>
  33
  34 #define BASIC_INPUT_CLOCK_FREQUENCY_1   35328000
  35 #define BASIC_INPUT_CLOCK_FREQUENCY_2   36000000
  36
  37 #define BASIS_INPUT_CRYSTAL_USB         12000000
  38
  39 #define GET_BITS(x, msb, lsb)           (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
  40
  41
  42 #define CGU_PLL0_PHASE_DIVIDER_ENABLE   (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 31))
  43 #define CGU_PLL0_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 30))
  44 #define CGU_PLL0_CFG_DSMSEL             (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 28))
  45 #define CGU_PLL0_CFG_FRAC_EN            (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 27))
  46 #define CGU_PLL1_SRC                    (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 31))
  47 #define CGU_PLL1_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 30))
  48 #define CGU_PLL1_CFG_DSMSEL             (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 28))
  49 #define CGU_PLL1_CFG_FRAC_EN            (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 27))
  50 #define CGU_PLL2_PHASE_DIVIDER_ENABLE   (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 20))
  51 #define CGU_PLL2_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 19))
  52 #define CGU_SYS_FPI_SEL                 (1 << 6)
  53 #define CGU_SYS_DDR_SEL                 0x3
  54 #define CGU_PLL0_SRC                    (1 << 29)
  55
  56 #define CGU_PLL0_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
  57 #define CGU_PLL0_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
  58 #define CGU_PLL0_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
  59 #define CGU_PLL1_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
  60 #define CGU_PLL1_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
  61 #define CGU_PLL1_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
  62 #define CGU_PLL2_SRC                    GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
  63 #define CGU_PLL2_CFG_INPUT_DIV          GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
  64 #define CGU_PLL2_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
  65 #define CGU_PLL2_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
  66 #define CGU_IF_CLK_PCI_CLK              GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
  67
  68 static unsigned int cgu_get_pll0_fdiv(void);
  69 unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
  70
  71 #define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
  72
  73 static inline unsigned int get_input_clock(int pll)
  74 {
  75         switch (pll) {
  76         case 0:
  77                 if (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC)
  78                         return BASIS_INPUT_CRYSTAL_USB;
  79                 else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
  80                         return BASIC_INPUT_CLOCK_FREQUENCY_1;
  81                 else
  82                         return BASIC_INPUT_CLOCK_FREQUENCY_2;
  83         case 1:
  84                 if (CGU_PLL1_SRC)
  85                         return BASIS_INPUT_CRYSTAL_USB;
  86                 else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
  87                         return BASIC_INPUT_CLOCK_FREQUENCY_1;
  88                 else
  89                         return BASIC_INPUT_CLOCK_FREQUENCY_2;
  90         case 2:
  91                 switch (CGU_PLL2_SRC) {
  92                 case 0:
  93                         return cgu_get_pll0_fdiv();
  94                 case 1:
  95                         return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
  96                                 BASIC_INPUT_CLOCK_FREQUENCY_1 :
  97                                 BASIC_INPUT_CLOCK_FREQUENCY_2;
  98                 case 2:
  99                         return BASIS_INPUT_CRYSTAL_USB;
 100                 }
 101         default:
 102                 return 0;
 103         }
 104 }
 105
 106 static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
 107 {
 108         u64 res, clock = get_input_clock(pll);
 109
 110         res = num * clock;
 111         do_div(res, den);
 112         return res;
 113 }
 114
 115 static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
 116         unsigned int K)
 117 {
 118         unsigned int num = ((N + 1) << 10) + K;
 119         unsigned int den = (M + 1) << 10;
 120
 121         return cal_dsm(pll, num, den);
 122 }
 123
 124 static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
 125         unsigned int K)
 126 {
 127         unsigned int num = ((N + 1) << 11) + K + 512;
 128         unsigned int den = (M + 1) << 11;
 129
 130         return cal_dsm(pll, num, den);
 131 }
 132
 133 static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
 134         unsigned int K)
 135 {
 136         unsigned int num = K >= 512 ?
 137                 ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
 138         unsigned int den = (M + 1) << 12;
 139
 140         return cal_dsm(pll, num, den);
 141 }
 142
 143 static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
 144         unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
 145 {
 146         if (!dsmsel)
 147                 return mash_dsm(pll, M, N, K);
 148         else if (!phase_div_en)
 149                 return mash_dsm(pll, M, N, K);
 150         else
 151                 return ssff_dsm_2(pll, M, N, K);
 152 }
 153
 154 static inline unsigned int cgu_get_pll0_fosc(void)
 155 {
 156         if (CGU_PLL0_BYPASS)
 157                 return get_input_clock(0);
 158         else
 159                 return !CGU_PLL0_CFG_FRAC_EN
 160                         ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
 161                                 CGU_PLL0_PHASE_DIVIDER_ENABLE)
 162                         : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
 163                                 CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
 164 }
 165
 166 static unsigned int cgu_get_pll0_fdiv(void)
 167 {
 168         unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
 169         return (cgu_get_pll0_fosc() + (div >> 1)) / div;
 170 }
 171
 172 unsigned int cgu_get_io_region_clock(void)
 173 {
 174         unsigned int ret = cgu_get_pll0_fosc();
 175         switch (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
 176         default:
 177         case 0:
 178                 return (ret + 1) / 2;
 179         case 1:
 180                 return (ret * 2 + 2) / 5;
 181         case 2:
 182                 return (ret + 1) / 3;
 183         case 3:
 184                 return (ret + 2) / 4;
 185         }
 186 }
 187
 188 unsigned int cgu_get_fpi_bus_clock(int fpi)
 189 {
 190         unsigned int ret = cgu_get_io_region_clock();
 191         if ((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL))
 192                 ret >>= 1;
 193         return ret;
 194 }
 195
 196 void cgu_setup_pci_clk(int external_clock)
 197 {
 198         /* set clock to 33Mhz */
 199         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000,
 200                 IFXMIPS_CGU_IFCCR);
 201         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000,
 202                 IFXMIPS_CGU_IFCCR);
 203         if (external_clock)     {
 204                 ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~(1 << 16),
 205                         IFXMIPS_CGU_IFCCR);
 206                 ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR);
 207         } else {
 208                 ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16),
 209                         IFXMIPS_CGU_IFCCR);
 210                 ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
 211         }
 212 }
 213
 214 unsigned int ifxmips_get_cpu_hz(void)
 215 {
 216         unsigned int ddr_clock = DDR_HZ;
 217         switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc) {
 218         case 0:
 219                 return CLOCK_333M;
 220         case 4:
 221                 return ddr_clock;
 222         }
 223         return ddr_clock << 1;
 224 }
 225 EXPORT_SYMBOL(ifxmips_get_cpu_hz);
 226
 227 unsigned int ifxmips_get_fpi_hz(void)
 228 {
 229         unsigned int ddr_clock = DDR_HZ;
 230         if (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
 231                 return ddr_clock >> 1;
 232         return ddr_clock;
 233 }
 234 EXPORT_SYMBOL(ifxmips_get_fpi_hz);