2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
21 #include "rtl8366_smi.h"
23 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
24 #define RTL8366S_DRIVER_VER "0.2.2"
26 #define RTL8366S_PHY_NO_MAX 4
27 #define RTL8366S_PHY_PAGE_MAX 7
28 #define RTL8366S_PHY_ADDR_MAX 31
30 /* Switch Global Configuration register */
31 #define RTL8366S_SGCR 0x0000
32 #define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
33 #define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
34 #define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
35 #define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
36 #define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
37 #define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
38 #define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
39 #define RTL8366S_SGCR_EN_VLAN BIT(13)
41 /* Port Enable Control register */
42 #define RTL8366S_PECR 0x0001
44 /* Switch Security Control registers */
45 #define RTL8366S_SSCR0 0x0002
46 #define RTL8366S_SSCR1 0x0003
47 #define RTL8366S_SSCR2 0x0004
48 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
50 #define RTL8366S_RESET_CTRL_REG 0x0100
51 #define RTL8366S_CHIP_CTRL_RESET_HW 1
52 #define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
54 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
55 #define RTL8366S_CHIP_VERSION_MASK 0xf
56 #define RTL8366S_CHIP_ID_REG 0x0105
57 #define RTL8366S_CHIP_ID_8366 0x8366
59 /* PHY registers control */
60 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
61 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
63 #define RTL8366S_PHY_CTRL_READ 1
64 #define RTL8366S_PHY_CTRL_WRITE 0
66 #define RTL8366S_PHY_REG_MASK 0x1f
67 #define RTL8366S_PHY_PAGE_OFFSET 5
68 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
69 #define RTL8366S_PHY_NO_OFFSET 9
70 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
72 /* LED control registers */
73 #define RTL8366S_LED_BLINKRATE_REG 0x0420
74 #define RTL8366S_LED_BLINKRATE_BIT 0
75 #define RTL8366S_LED_BLINKRATE_MASK 0x0007
77 #define RTL8366S_LED_CTRL_REG 0x0421
78 #define RTL8366S_LED_0_1_CTRL_REG 0x0422
79 #define RTL8366S_LED_2_3_CTRL_REG 0x0423
81 #define RTL8366S_MIB_COUNT 33
82 #define RTL8366S_GLOBAL_MIB_COUNT 1
83 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
84 #define RTL8366S_MIB_COUNTER_BASE 0x1000
85 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
86 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
87 #define RTL8366S_MIB_CTRL_REG 0x11F0
88 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
89 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
90 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
92 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
93 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
94 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
97 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
98 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
99 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
100 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
101 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
104 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
105 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
107 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
109 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
110 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
111 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
113 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
115 #define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379
117 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
118 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
119 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
120 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
121 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
122 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
123 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
126 #define RTL8366S_PORT_NUM_CPU 5
127 #define RTL8366S_NUM_PORTS 6
128 #define RTL8366S_NUM_VLANS 16
129 #define RTL8366S_NUM_LEDGROUPS 4
130 #define RTL8366S_NUM_VIDS 4096
131 #define RTL8366S_PRIORITYMAX 7
132 #define RTL8366S_FIDMAX 7
135 #define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
136 #define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
137 #define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
138 #define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
140 #define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
141 #define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
143 #define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
147 RTL8366S_PORT_UNKNOWN | \
150 #define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
154 RTL8366S_PORT_UNKNOWN)
156 #define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
161 #define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
165 struct device *parent;
166 struct rtl8366_smi smi;
167 struct switch_dev dev;
170 struct rtl8366s_vlan_mc {
181 struct rtl8366s_vlan_4k {
191 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
192 { 0, 0, 4, "IfInOctets" },
193 { 0, 4, 4, "EtherStatsOctets" },
194 { 0, 8, 2, "EtherStatsUnderSizePkts" },
195 { 0, 10, 2, "EtherFragments" },
196 { 0, 12, 2, "EtherStatsPkts64Octets" },
197 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
198 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
199 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
200 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
201 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
202 { 0, 24, 2, "EtherOversizeStats" },
203 { 0, 26, 2, "EtherStatsJabbers" },
204 { 0, 28, 2, "IfInUcastPkts" },
205 { 0, 30, 2, "EtherStatsMulticastPkts" },
206 { 0, 32, 2, "EtherStatsBroadcastPkts" },
207 { 0, 34, 2, "EtherStatsDropEvents" },
208 { 0, 36, 2, "Dot3StatsFCSErrors" },
209 { 0, 38, 2, "Dot3StatsSymbolErrors" },
210 { 0, 40, 2, "Dot3InPauseFrames" },
211 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
212 { 0, 44, 4, "IfOutOctets" },
213 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
214 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
215 { 0, 52, 2, "Dot3sDeferredTransmissions" },
216 { 0, 54, 2, "Dot3StatsLateCollisions" },
217 { 0, 56, 2, "EtherStatsCollisions" },
218 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
219 { 0, 60, 2, "Dot3OutPauseFrames" },
220 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
223 * The following counters are accessible at a different
226 { 1, 0, 2, "Dot1dTpPortInDiscards" },
227 { 1, 2, 2, "IfOutUcastPkts" },
228 { 1, 4, 2, "IfOutMulticastPkts" },
229 { 1, 6, 2, "IfOutBroadcastPkts" },
232 #define REG_WR(_smi, _reg, _val) \
234 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
239 #define REG_RMW(_smi, _reg, _mask, _val) \
241 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
246 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
248 return container_of(smi, struct rtl8366s, smi);
251 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
253 return container_of(sw, struct rtl8366s, dev);
256 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
258 struct rtl8366s *rtl = sw_to_rtl8366s(sw);
262 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
267 rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
268 RTL8366S_CHIP_CTRL_RESET_HW);
271 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
274 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
279 printk("Timeout waiting for the switch to reset\n");
286 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
290 /* set maximum packet length to 1536 bytes */
291 REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
292 RTL8366S_SGCR_MAX_LENGTH_1536);
294 /* enable all ports */
295 REG_WR(smi, RTL8366S_PECR, 0);
297 /* enable learning for all ports */
298 REG_WR(smi, RTL8366S_SSCR0, 0);
300 /* enable auto ageing for all ports */
301 REG_WR(smi, RTL8366S_SSCR1, 0);
304 * discard VLAN tagged packets if the port is not a member of
305 * the VLAN with which the packets is associated.
307 REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
309 /* don't drop packets whose DA has not been learned */
310 REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
315 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
316 u32 phy_no, u32 page, u32 addr, u32 *data)
321 if (phy_no > RTL8366S_PHY_NO_MAX)
324 if (page > RTL8366S_PHY_PAGE_MAX)
327 if (addr > RTL8366S_PHY_ADDR_MAX)
330 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
331 RTL8366S_PHY_CTRL_READ);
335 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
336 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
337 (addr & RTL8366S_PHY_REG_MASK);
339 ret = rtl8366_smi_write_reg(smi, reg, 0);
343 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
350 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
351 u32 phy_no, u32 page, u32 addr, u32 data)
356 if (phy_no > RTL8366S_PHY_NO_MAX)
359 if (page > RTL8366S_PHY_PAGE_MAX)
362 if (addr > RTL8366S_PHY_ADDR_MAX)
365 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
366 RTL8366S_PHY_CTRL_WRITE);
370 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
371 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
372 (addr & RTL8366S_PHY_REG_MASK);
374 ret = rtl8366_smi_write_reg(smi, reg, data);
381 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
382 int port, unsigned long long *val)
389 if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
392 switch (rtl8366s_mib_counters[counter].base) {
394 addr = RTL8366S_MIB_COUNTER_BASE +
395 RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
399 addr = RTL8366S_MIB_COUNTER_BASE2 +
400 RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
407 addr += rtl8366s_mib_counters[counter].offset;
410 * Writing access counter address first
411 * then ASIC will prepare 64bits counter wait for being retrived
413 data = 0; /* writing data will be discard by ASIC */
414 err = rtl8366_smi_write_reg(smi, addr, data);
418 /* read MIB control register */
419 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
423 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
426 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
430 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
431 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
435 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
442 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
443 struct rtl8366_vlan_4k *vlan4k)
445 struct rtl8366s_vlan_4k vlan4k_priv;
450 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
451 vlan4k_priv.vid = vid;
453 if (vid >= RTL8366S_NUM_VIDS)
456 tableaddr = (u16 *)&vlan4k_priv;
460 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
464 /* write table access control word */
465 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
466 RTL8366S_TABLE_VLAN_READ_CTRL);
470 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
477 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
485 vlan4k->untag = vlan4k_priv.untag;
486 vlan4k->member = vlan4k_priv.member;
487 vlan4k->fid = vlan4k_priv.fid;
492 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
493 const struct rtl8366_vlan_4k *vlan4k)
495 struct rtl8366s_vlan_4k vlan4k_priv;
500 if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
501 vlan4k->member > RTL8366S_PORT_ALL ||
502 vlan4k->untag > RTL8366S_PORT_ALL ||
503 vlan4k->fid > RTL8366S_FIDMAX)
506 vlan4k_priv.vid = vlan4k->vid;
507 vlan4k_priv.untag = vlan4k->untag;
508 vlan4k_priv.member = vlan4k->member;
509 vlan4k_priv.fid = vlan4k->fid;
511 tableaddr = (u16 *)&vlan4k_priv;
515 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
523 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
528 /* write table access control word */
529 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
530 RTL8366S_TABLE_VLAN_WRITE_CTRL);
535 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
536 struct rtl8366_vlan_mc *vlanmc)
538 struct rtl8366s_vlan_mc vlanmc_priv;
544 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
546 if (index >= RTL8366S_NUM_VLANS)
549 tableaddr = (u16 *)&vlanmc_priv;
551 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
552 err = rtl8366_smi_read_reg(smi, addr, &data);
559 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
560 err = rtl8366_smi_read_reg(smi, addr, &data);
566 vlanmc->vid = vlanmc_priv.vid;
567 vlanmc->priority = vlanmc_priv.priority;
568 vlanmc->untag = vlanmc_priv.untag;
569 vlanmc->member = vlanmc_priv.member;
570 vlanmc->fid = vlanmc_priv.fid;
575 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
576 const struct rtl8366_vlan_mc *vlanmc)
578 struct rtl8366s_vlan_mc vlanmc_priv;
584 if (index >= RTL8366S_NUM_VLANS ||
585 vlanmc->vid >= RTL8366S_NUM_VIDS ||
586 vlanmc->priority > RTL8366S_PRIORITYMAX ||
587 vlanmc->member > RTL8366S_PORT_ALL ||
588 vlanmc->untag > RTL8366S_PORT_ALL ||
589 vlanmc->fid > RTL8366S_FIDMAX)
592 vlanmc_priv.vid = vlanmc->vid;
593 vlanmc_priv.priority = vlanmc->priority;
594 vlanmc_priv.untag = vlanmc->untag;
595 vlanmc_priv.member = vlanmc->member;
596 vlanmc_priv.fid = vlanmc->fid;
598 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
600 tableaddr = (u16 *)&vlanmc_priv;
603 err = rtl8366_smi_write_reg(smi, addr, data);
607 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
612 err = rtl8366_smi_write_reg(smi, addr, data);
619 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
624 if (port >= RTL8366S_NUM_PORTS)
627 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
632 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
633 RTL8366S_PORT_VLAN_CTRL_MASK;
638 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
640 if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
643 return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
644 RTL8366S_PORT_VLAN_CTRL_MASK <<
645 RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
646 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
647 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
650 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
652 return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
653 (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
656 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
658 return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
659 1, (enable) ? 1 : 0);
662 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
663 const struct switch_attr *attr,
664 struct switch_val *val)
666 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
669 if (val->value.i == 1)
670 err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
675 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
676 const struct switch_attr *attr,
677 struct switch_val *val)
679 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
682 if (attr->ofs == 1) {
683 rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);
685 if (data & RTL8366S_SGCR_EN_VLAN)
689 } else if (attr->ofs == 2) {
690 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
701 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
702 const struct switch_attr *attr,
703 struct switch_val *val)
705 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
708 rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
710 val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
715 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
716 const struct switch_attr *attr,
717 struct switch_val *val)
719 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
721 if (val->value.i >= 6)
724 return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
725 RTL8366S_LED_BLINKRATE_MASK,
729 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
730 const struct switch_attr *attr,
731 struct switch_val *val)
733 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
736 return rtl8366s_vlan_set_vlan(smi, val->value.i);
738 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
741 static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,
742 const struct switch_attr *attr,
743 struct switch_val *val)
745 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
748 rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);
749 val->value.i = !data;
755 static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
756 const struct switch_attr *attr,
757 struct switch_val *val)
759 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
764 portmask = RTL8366S_PORT_ALL;
766 /* set learning for all ports */
767 REG_WR(smi, RTL8366S_SSCR0, portmask);
769 /* set auto ageing for all ports */
770 REG_WR(smi, RTL8366S_SSCR1, portmask);
776 static const char *rtl8366s_speed_str(unsigned speed)
790 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
791 const struct switch_attr *attr,
792 struct switch_val *val)
794 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
795 u32 len = 0, data = 0;
797 if (val->port_vlan >= RTL8366S_NUM_PORTS)
800 memset(smi->buf, '\0', sizeof(smi->buf));
801 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
802 (val->port_vlan / 2), &data);
804 if (val->port_vlan % 2)
807 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
808 len = snprintf(smi->buf, sizeof(smi->buf),
809 "port:%d link:up speed:%s %s-duplex %s%s%s",
811 rtl8366s_speed_str(data &
812 RTL8366S_PORT_STATUS_SPEED_MASK),
813 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
815 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
817 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
819 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
822 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
826 val->value.s = smi->buf;
832 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
833 const struct switch_attr *attr,
834 struct switch_val *val)
838 struct rtl8366_vlan_4k vlan4k;
839 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
840 char *buf = smi->buf;
843 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
846 memset(buf, '\0', sizeof(smi->buf));
848 err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
852 len += snprintf(buf + len, sizeof(smi->buf) - len,
853 "VLAN %d: Ports: '", vlan4k.vid);
855 for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
856 if (!(vlan4k.member & (1 << i)))
859 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
860 (vlan4k.untag & (1 << i)) ? "" : "t");
863 len += snprintf(buf + len, sizeof(smi->buf) - len,
864 "', members=%04x, untag=%04x, fid=%u",
865 vlan4k.member, vlan4k.untag, vlan4k.fid);
873 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
874 const struct switch_attr *attr,
875 struct switch_val *val)
877 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
882 if (val->port_vlan >= RTL8366S_NUM_PORTS ||
883 (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
886 if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
887 reg = RTL8366S_LED_BLINKRATE_REG;
889 data = val->value.i << 4;
891 reg = RTL8366S_LED_CTRL_REG;
892 mask = 0xF << (val->port_vlan * 4),
893 data = val->value.i << (val->port_vlan * 4);
896 return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, mask, data);
899 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
900 const struct switch_attr *attr,
901 struct switch_val *val)
903 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
906 if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
909 rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
910 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
915 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
916 const struct switch_attr *attr,
917 struct switch_val *val)
919 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
921 if (val->port_vlan >= RTL8366S_NUM_PORTS)
925 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
926 0, (1 << (val->port_vlan + 3)));
929 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
930 const struct switch_attr *attr,
931 struct switch_val *val)
933 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
935 unsigned long long counter = 0;
936 char *buf = smi->buf;
938 if (val->port_vlan >= RTL8366S_NUM_PORTS)
941 len += snprintf(buf + len, sizeof(smi->buf) - len,
942 "Port %d MIB counters\n",
945 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
946 len += snprintf(buf + len, sizeof(smi->buf) - len,
947 "%-36s: ", rtl8366s_mib_counters[i].name);
948 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
949 len += snprintf(buf + len, sizeof(smi->buf) - len,
952 len += snprintf(buf + len, sizeof(smi->buf) - len,
961 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
962 struct switch_val *val)
964 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
965 struct switch_port *port;
966 struct rtl8366_vlan_4k vlan4k;
969 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
972 rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
974 port = &val->value.ports[0];
976 for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
977 if (!(vlan4k.member & BIT(i)))
981 port->flags = (vlan4k.untag & BIT(i)) ?
982 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
989 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
990 struct switch_val *val)
992 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
993 struct switch_port *port;
998 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
1001 port = &val->value.ports[0];
1002 for (i = 0; i < val->len; i++, port++) {
1003 member |= BIT(port->id);
1005 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1006 untag |= BIT(port->id);
1009 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
1012 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1014 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1015 return rtl8366_get_pvid(smi, port, val);
1018 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1020 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1021 return rtl8366_set_pvid(smi, port, val);
1024 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1026 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1029 err = rtl8366s_reset_chip(smi);
1033 err = rtl8366s_hw_init(smi);
1037 return rtl8366_reset_vlan(smi);
1040 static struct switch_attr rtl8366s_globals[] = {
1042 .type = SWITCH_TYPE_INT,
1043 .name = "enable_learning",
1044 .description = "Enable learning, enable aging",
1045 .set = rtl8366s_sw_set_learning_enable,
1046 .get = rtl8366s_sw_get_learning_enable,
1049 .type = SWITCH_TYPE_INT,
1050 .name = "enable_vlan",
1051 .description = "Enable VLAN mode",
1052 .set = rtl8366s_sw_set_vlan_enable,
1053 .get = rtl8366s_sw_get_vlan_enable,
1057 .type = SWITCH_TYPE_INT,
1058 .name = "enable_vlan4k",
1059 .description = "Enable VLAN 4K mode",
1060 .set = rtl8366s_sw_set_vlan_enable,
1061 .get = rtl8366s_sw_get_vlan_enable,
1065 .type = SWITCH_TYPE_INT,
1066 .name = "reset_mibs",
1067 .description = "Reset all MIB counters",
1068 .set = rtl8366s_sw_reset_mibs,
1072 .type = SWITCH_TYPE_INT,
1073 .name = "blinkrate",
1074 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1075 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1076 .set = rtl8366s_sw_set_blinkrate,
1077 .get = rtl8366s_sw_get_blinkrate,
1082 static struct switch_attr rtl8366s_port[] = {
1084 .type = SWITCH_TYPE_STRING,
1086 .description = "Get port link information",
1089 .get = rtl8366s_sw_get_port_link,
1091 .type = SWITCH_TYPE_INT,
1092 .name = "reset_mib",
1093 .description = "Reset single port MIB counters",
1095 .set = rtl8366s_sw_reset_port_mibs,
1098 .type = SWITCH_TYPE_STRING,
1100 .description = "Get MIB counters for port",
1103 .get = rtl8366s_sw_get_port_mib,
1105 .type = SWITCH_TYPE_INT,
1107 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1109 .set = rtl8366s_sw_set_port_led,
1110 .get = rtl8366s_sw_get_port_led,
1114 static struct switch_attr rtl8366s_vlan[] = {
1116 .type = SWITCH_TYPE_STRING,
1118 .description = "Get vlan information",
1121 .get = rtl8366s_sw_get_vlan_info,
1126 static struct switch_dev rtl8366_switch_dev = {
1128 .cpu_port = RTL8366S_PORT_NUM_CPU,
1129 .ports = RTL8366S_NUM_PORTS,
1130 .vlans = RTL8366S_NUM_VLANS,
1132 .attr = rtl8366s_globals,
1133 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1136 .attr = rtl8366s_port,
1137 .n_attr = ARRAY_SIZE(rtl8366s_port),
1140 .attr = rtl8366s_vlan,
1141 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1144 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1145 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1146 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1147 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1148 .reset_switch = rtl8366s_sw_reset_switch,
1151 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1153 struct switch_dev *dev = &rtl->dev;
1156 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1158 dev->devname = dev_name(rtl->parent);
1160 err = register_switch(dev, NULL);
1162 dev_err(rtl->parent, "switch registration failed\n");
1167 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1169 unregister_switch(&rtl->dev);
1172 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1174 struct rtl8366_smi *smi = bus->priv;
1178 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1185 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1187 struct rtl8366_smi *smi = bus->priv;
1191 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1193 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1198 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1200 return (bus->read == rtl8366s_mii_read &&
1201 bus->write == rtl8366s_mii_write);
1204 static int rtl8366s_setup(struct rtl8366s *rtl)
1206 struct rtl8366_smi *smi = &rtl->smi;
1209 ret = rtl8366s_reset_chip(smi);
1213 ret = rtl8366s_hw_init(smi);
1217 static int rtl8366s_detect(struct rtl8366_smi *smi)
1223 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1225 dev_err(smi->parent, "unable to read chip id\n");
1230 case RTL8366S_CHIP_ID_8366:
1233 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1237 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1240 dev_err(smi->parent, "unable to read chip version\n");
1244 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1245 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1250 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1251 .detect = rtl8366s_detect,
1252 .mii_read = rtl8366s_mii_read,
1253 .mii_write = rtl8366s_mii_write,
1255 .get_vlan_mc = rtl8366s_get_vlan_mc,
1256 .set_vlan_mc = rtl8366s_set_vlan_mc,
1257 .get_vlan_4k = rtl8366s_get_vlan_4k,
1258 .set_vlan_4k = rtl8366s_set_vlan_4k,
1259 .get_mc_index = rtl8366s_get_mc_index,
1260 .set_mc_index = rtl8366s_set_mc_index,
1261 .get_mib_counter = rtl8366_get_mib_counter,
1264 static int __init rtl8366s_probe(struct platform_device *pdev)
1266 static int rtl8366_smi_version_printed;
1267 struct rtl8366s_platform_data *pdata;
1268 struct rtl8366s *rtl;
1269 struct rtl8366_smi *smi;
1272 if (!rtl8366_smi_version_printed++)
1273 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1274 " version " RTL8366S_DRIVER_VER"\n");
1276 pdata = pdev->dev.platform_data;
1278 dev_err(&pdev->dev, "no platform data specified\n");
1283 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1285 dev_err(&pdev->dev, "no memory for private data\n");
1290 rtl->parent = &pdev->dev;
1293 smi->parent = &pdev->dev;
1294 smi->gpio_sda = pdata->gpio_sda;
1295 smi->gpio_sck = pdata->gpio_sck;
1296 smi->ops = &rtl8366s_smi_ops;
1297 smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1298 smi->num_ports = RTL8366S_NUM_PORTS;
1299 smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1300 smi->mib_counters = rtl8366s_mib_counters;
1301 smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1303 err = rtl8366_smi_init(smi);
1307 platform_set_drvdata(pdev, rtl);
1309 err = rtl8366s_setup(rtl);
1311 goto err_clear_drvdata;
1313 err = rtl8366s_switch_init(rtl);
1315 goto err_clear_drvdata;
1320 platform_set_drvdata(pdev, NULL);
1321 rtl8366_smi_cleanup(smi);
1328 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1330 if (!rtl8366s_mii_bus_match(phydev->bus))
1336 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1341 static struct phy_driver rtl8366s_phy_driver = {
1342 .phy_id = 0x001cc960,
1343 .name = "Realtek RTL8366S",
1344 .phy_id_mask = 0x1ffffff0,
1345 .features = PHY_GBIT_FEATURES,
1346 .config_aneg = rtl8366s_phy_config_aneg,
1347 .config_init = rtl8366s_phy_config_init,
1348 .read_status = genphy_read_status,
1350 .owner = THIS_MODULE,
1354 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1356 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1359 rtl8366s_switch_cleanup(rtl);
1360 platform_set_drvdata(pdev, NULL);
1361 rtl8366_smi_cleanup(&rtl->smi);
1368 static struct platform_driver rtl8366s_driver = {
1370 .name = RTL8366S_DRIVER_NAME,
1371 .owner = THIS_MODULE,
1373 .probe = rtl8366s_probe,
1374 .remove = __devexit_p(rtl8366s_remove),
1377 static int __init rtl8366s_module_init(void)
1380 ret = platform_driver_register(&rtl8366s_driver);
1384 ret = phy_driver_register(&rtl8366s_phy_driver);
1386 goto err_platform_unregister;
1390 err_platform_unregister:
1391 platform_driver_unregister(&rtl8366s_driver);
1394 module_init(rtl8366s_module_init);
1396 static void __exit rtl8366s_module_exit(void)
1398 phy_driver_unregister(&rtl8366s_phy_driver);
1399 platform_driver_unregister(&rtl8366s_driver);
1401 module_exit(rtl8366s_module_exit);
1403 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1404 MODULE_VERSION(RTL8366S_DRIVER_VER);
1405 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1406 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1407 MODULE_LICENSE("GPL v2");
1408 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);