target/linux/generic-2.6/files/drivers/net/phy/rtl8366s.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/switch.h>
  19 #include <linux/rtl8366s.h>
  20
  21 #include "rtl8366_smi.h"
  22
  23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
  24 #include <linux/debugfs.h>
  25 #endif
  26
  27 #define RTL8366S_DRIVER_DESC    "Realtek RTL8366S ethernet switch driver"
  28 #define RTL8366S_DRIVER_VER     "0.2.2"
  29
  30 #define RTL8366S_PHY_NO_MAX     4
  31 #define RTL8366S_PHY_PAGE_MAX   7
  32 #define RTL8366S_PHY_ADDR_MAX   31
  33
  34 #define RTL8366S_CHIP_GLOBAL_CTRL_REG           0x0000
  35 #define RTL8366S_CHIP_CTRL_VLAN                 (1 << 13)
  36
  37 /* Switch Global Configuration register */
  38 #define RTL8366S_SGCR                           0x0000
  39 #define RTL8366S_SGCR_EN_BC_STORM_CTRL          BIT(0)
  40 #define RTL8366S_SGCR_MAX_LENGTH(_x)            (_x << 4)
  41 #define RTL8366S_SGCR_MAX_LENGTH_MASK           RTL8366S_SGCR_MAX_LENGTH(0x3)
  42 #define RTL8366S_SGCR_MAX_LENGTH_1522           RTL8366S_SGCR_MAX_LENGTH(0x0)
  43 #define RTL8366S_SGCR_MAX_LENGTH_1536           RTL8366S_SGCR_MAX_LENGTH(0x1)
  44 #define RTL8366S_SGCR_MAX_LENGTH_1552           RTL8366S_SGCR_MAX_LENGTH(0x2)
  45 #define RTL8366S_SGCR_MAX_LENGTH_16000          RTL8366S_SGCR_MAX_LENGTH(0x3)
  46
  47 /* Port Enable Control register */
  48 #define RTL8366S_PECR                           0x0001
  49
  50 /* Switch Security Control registers */
  51 #define RTL8366S_SSCR0                          0x0002
  52 #define RTL8366S_SSCR1                          0x0003
  53 #define RTL8366S_SSCR2                          0x0004
  54 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA          BIT(0)
  55
  56 #define RTL8366S_RESET_CTRL_REG                 0x0100
  57 #define RTL8366S_CHIP_CTRL_RESET_HW             1
  58 #define RTL8366S_CHIP_CTRL_RESET_SW             (1 << 1)
  59
  60 #define RTL8366S_CHIP_VERSION_CTRL_REG          0x0104
  61 #define RTL8366S_CHIP_VERSION_MASK              0xf
  62 #define RTL8366S_CHIP_ID_REG                    0x0105
  63 #define RTL8366S_CHIP_ID_8366                   0x8366
  64
  65 /* PHY registers control */
  66 #define RTL8366S_PHY_ACCESS_CTRL_REG            0x8028
  67 #define RTL8366S_PHY_ACCESS_DATA_REG            0x8029
  68
  69 #define RTL8366S_PHY_CTRL_READ                  1
  70 #define RTL8366S_PHY_CTRL_WRITE                 0
  71
  72 #define RTL8366S_PHY_REG_MASK                   0x1f
  73 #define RTL8366S_PHY_PAGE_OFFSET                5
  74 #define RTL8366S_PHY_PAGE_MASK                  (0x7 << 5)
  75 #define RTL8366S_PHY_NO_OFFSET                  9
  76 #define RTL8366S_PHY_NO_MASK                    (0x1f << 9)
  77
  78 /* LED control registers */
  79 #define RTL8366S_LED_BLINKRATE_REG              0x0420
  80 #define RTL8366S_LED_BLINKRATE_BIT              0
  81 #define RTL8366S_LED_BLINKRATE_MASK             0x0007
  82
  83 #define RTL8366S_LED_CTRL_REG                   0x0421
  84 #define RTL8366S_LED_0_1_CTRL_REG               0x0422
  85 #define RTL8366S_LED_2_3_CTRL_REG               0x0423
  86
  87 #define RTL8366S_MIB_COUNT                      33
  88 #define RTL8366S_GLOBAL_MIB_COUNT               1
  89 #define RTL8366S_MIB_COUNTER_PORT_OFFSET        0x0040
  90 #define RTL8366S_MIB_COUNTER_BASE               0x1000
  91 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2       0x0008
  92 #define RTL8366S_MIB_COUNTER_BASE2              0x1180
  93 #define RTL8366S_MIB_CTRL_REG                   0x11F0
  94 #define RTL8366S_MIB_CTRL_USER_MASK             0x01FF
  95 #define RTL8366S_MIB_CTRL_BUSY_MASK             0x0001
  96 #define RTL8366S_MIB_CTRL_RESET_MASK            0x0002
  97
  98 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK     0x0004
  99 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT        0x0003
 100 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK       0x01FC
 101
 102
 103 #define RTL8366S_PORT_VLAN_CTRL_BASE            0x0058
 104 #define RTL8366S_PORT_VLAN_CTRL_REG(_p)  \
 105                 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
 106 #define RTL8366S_PORT_VLAN_CTRL_MASK            0xf
 107 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p)       (4 * ((_p) % 4))
 108
 109
 110 #define RTL8366S_VLAN_TABLE_READ_BASE           0x018B
 111 #define RTL8366S_VLAN_TABLE_WRITE_BASE          0x0185
 112
 113 #define RTL8366S_VLAN_TB_CTRL_REG               0x010F
 114
 115 #define RTL8366S_TABLE_ACCESS_CTRL_REG          0x0180
 116 #define RTL8366S_TABLE_VLAN_READ_CTRL           0x0E01
 117 #define RTL8366S_TABLE_VLAN_WRITE_CTRL          0x0F01
 118
 119 #define RTL8366S_VLAN_MEMCONF_BASE              0x0016
 120
 121
 122 #define RTL8366S_PORT_LINK_STATUS_BASE          0x0060
 123 #define RTL8366S_PORT_STATUS_SPEED_MASK         0x0003
 124 #define RTL8366S_PORT_STATUS_DUPLEX_MASK        0x0004
 125 #define RTL8366S_PORT_STATUS_LINK_MASK          0x0010
 126 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK       0x0020
 127 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK       0x0040
 128 #define RTL8366S_PORT_STATUS_AN_MASK            0x0080
 129
 130
 131 #define RTL8366S_PORT_NUM_CPU           5
 132 #define RTL8366S_NUM_PORTS              6
 133 #define RTL8366S_NUM_VLANS              16
 134 #define RTL8366S_NUM_LEDGROUPS          4
 135 #define RTL8366S_NUM_VIDS               4096
 136 #define RTL8366S_PRIORITYMAX            7
 137 #define RTL8366S_FIDMAX                 7
 138
 139
 140 #define RTL8366S_PORT_1                 (1 << 0) /* In userspace port 0 */
 141 #define RTL8366S_PORT_2                 (1 << 1) /* In userspace port 1 */
 142 #define RTL8366S_PORT_3                 (1 << 2) /* In userspace port 2 */
 143 #define RTL8366S_PORT_4                 (1 << 3) /* In userspace port 3 */
 144
 145 #define RTL8366S_PORT_UNKNOWN           (1 << 4) /* No known connection */
 146 #define RTL8366S_PORT_CPU               (1 << 5) /* CPU port */
 147
 148 #define RTL8366S_PORT_ALL               (RTL8366S_PORT_1 |      \
 149                                          RTL8366S_PORT_2 |      \
 150                                          RTL8366S_PORT_3 |      \
 151                                          RTL8366S_PORT_4 |      \
 152                                          RTL8366S_PORT_UNKNOWN | \
 153                                          RTL8366S_PORT_CPU)
 154
 155 #define RTL8366S_PORT_ALL_BUT_CPU       (RTL8366S_PORT_1 |      \
 156                                          RTL8366S_PORT_2 |      \
 157                                          RTL8366S_PORT_3 |      \
 158                                          RTL8366S_PORT_4 |      \
 159                                          RTL8366S_PORT_UNKNOWN)
 160
 161 #define RTL8366S_PORT_ALL_EXTERNAL      (RTL8366S_PORT_1 |      \
 162                                          RTL8366S_PORT_2 |      \
 163                                          RTL8366S_PORT_3 |      \
 164                                          RTL8366S_PORT_4)
 165
 166 #define RTL8366S_PORT_ALL_INTERNAL      (RTL8366S_PORT_UNKNOWN | \
 167                                          RTL8366S_PORT_CPU)
 168
 169 struct rtl8366s {
 170         struct device           *parent;
 171         struct rtl8366_smi      smi;
 172         struct switch_dev       dev;
 173 };
 174
 175 struct rtl8366s_vlan_mc {
 176         u16     reserved2:1;
 177         u16     priority:3;
 178         u16     vid:12;
 179
 180         u16     reserved1:1;
 181         u16     fid:3;
 182         u16     untag:6;
 183         u16     member:6;
 184 };
 185
 186 struct rtl8366s_vlan_4k {
 187         u16     reserved1:4;
 188         u16     vid:12;
 189
 190         u16     reserved2:1;
 191         u16     fid:3;
 192         u16     untag:6;
 193         u16     member:6;
 194 };
 195
 196 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
 197         { 0,  0, 4, "IfInOctets"                                },
 198         { 0,  4, 4, "EtherStatsOctets"                          },
 199         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 200         { 0, 10, 2, "EtherFragments"                            },
 201         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 202         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 203         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 204         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 205         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 206         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 207         { 0, 24, 2, "EtherOversizeStats"                        },
 208         { 0, 26, 2, "EtherStatsJabbers"                         },
 209         { 0, 28, 2, "IfInUcastPkts"                             },
 210         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 211         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 212         { 0, 34, 2, "EtherStatsDropEvents"                      },
 213         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 214         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 215         { 0, 40, 2, "Dot3InPauseFrames"                         },
 216         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 217         { 0, 44, 4, "IfOutOctets"                               },
 218         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 219         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 220         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 221         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 222         { 0, 56, 2, "EtherStatsCollisions"                      },
 223         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 224         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 225         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 226
 227         /*
 228          * The following counters are accessible at a different
 229          * base address.
 230          */
 231         { 1,  0, 2, "Dot1dTpPortInDiscards"                     },
 232         { 1,  2, 2, "IfOutUcastPkts"                            },
 233         { 1,  4, 2, "IfOutMulticastPkts"                        },
 234         { 1,  6, 2, "IfOutBroadcastPkts"                        },
 235 };
 236
 237 #define REG_WR(_smi, _reg, _val)                                        \
 238         do {                                                            \
 239                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 240                 if (err)                                                \
 241                         return err;                                     \
 242         } while (0)
 243
 244 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 245         do {                                                            \
 246                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 247                 if (err)                                                \
 248                         return err;                                     \
 249         } while (0)
 250
 251 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
 252 {
 253         return container_of(smi, struct rtl8366s, smi);
 254 }
 255
 256 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
 257 {
 258         return container_of(sw, struct rtl8366s, dev);
 259 }
 260
 261 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
 262 {
 263         struct rtl8366s *rtl = sw_to_rtl8366s(sw);
 264         return &rtl->smi;
 265 }
 266
 267 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
 268 {
 269         int timeout = 10;
 270         u32 data;
 271
 272         rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
 273                               RTL8366S_CHIP_CTRL_RESET_HW);
 274         do {
 275                 msleep(1);
 276                 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
 277                         return -EIO;
 278
 279                 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
 280                         break;
 281         } while (--timeout);
 282
 283         if (!timeout) {
 284                 printk("Timeout waiting for the switch to reset\n");
 285                 return -EIO;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
 292 {
 293         int err;
 294
 295         /* set maximum packet length to 1536 bytes */
 296         REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
 297                 RTL8366S_SGCR_MAX_LENGTH_1536);
 298
 299         /* enable all ports */
 300         REG_WR(smi, RTL8366S_PECR, 0);
 301
 302         /* disable learning for all ports */
 303         REG_WR(smi, RTL8366S_SSCR0, RTL8366S_PORT_ALL);
 304
 305         /* disable auto ageing for all ports */
 306         REG_WR(smi, RTL8366S_SSCR1, RTL8366S_PORT_ALL);
 307
 308         /* don't drop packets whose DA has not been learned */
 309         REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
 310
 311         return 0;
 312 }
 313
 314 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
 315                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 316 {
 317         u32 reg;
 318         int ret;
 319
 320         if (phy_no > RTL8366S_PHY_NO_MAX)
 321                 return -EINVAL;
 322
 323         if (page > RTL8366S_PHY_PAGE_MAX)
 324                 return -EINVAL;
 325
 326         if (addr > RTL8366S_PHY_ADDR_MAX)
 327                 return -EINVAL;
 328
 329         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 330                                     RTL8366S_PHY_CTRL_READ);
 331         if (ret)
 332                 return ret;
 333
 334         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 335               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 336               (addr & RTL8366S_PHY_REG_MASK);
 337
 338         ret = rtl8366_smi_write_reg(smi, reg, 0);
 339         if (ret)
 340                 return ret;
 341
 342         ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
 343         if (ret)
 344                 return ret;
 345
 346         return 0;
 347 }
 348
 349 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
 350                                   u32 phy_no, u32 page, u32 addr, u32 data)
 351 {
 352         u32 reg;
 353         int ret;
 354
 355         if (phy_no > RTL8366S_PHY_NO_MAX)
 356                 return -EINVAL;
 357
 358         if (page > RTL8366S_PHY_PAGE_MAX)
 359                 return -EINVAL;
 360
 361         if (addr > RTL8366S_PHY_ADDR_MAX)
 362                 return -EINVAL;
 363
 364         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 365                                     RTL8366S_PHY_CTRL_WRITE);
 366         if (ret)
 367                 return ret;
 368
 369         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 370               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 371               (addr & RTL8366S_PHY_REG_MASK);
 372
 373         ret = rtl8366_smi_write_reg(smi, reg, data);
 374         if (ret)
 375                 return ret;
 376
 377         return 0;
 378 }
 379
 380 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
 381                                    int port, unsigned long long *val)
 382 {
 383         int i;
 384         int err;
 385         u32 addr, data;
 386         u64 mibvalue;
 387
 388         if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
 389                 return -EINVAL;
 390
 391         switch (rtl8366s_mib_counters[counter].base) {
 392         case 0:
 393                 addr = RTL8366S_MIB_COUNTER_BASE +
 394                        RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
 395                 break;
 396
 397         case 1:
 398                 addr = RTL8366S_MIB_COUNTER_BASE2 +
 399                         RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
 400                 break;
 401
 402         default:
 403                 return -EINVAL;
 404         }
 405
 406         addr += rtl8366s_mib_counters[counter].offset;
 407
 408         /*
 409          * Writing access counter address first
 410          * then ASIC will prepare 64bits counter wait for being retrived
 411          */
 412         data = 0; /* writing data will be discard by ASIC */
 413         err = rtl8366_smi_write_reg(smi, addr, data);
 414         if (err)
 415                 return err;
 416
 417         /* read MIB control register */
 418         err =  rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
 419         if (err)
 420                 return err;
 421
 422         if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
 423                 return -EBUSY;
 424
 425         if (data & RTL8366S_MIB_CTRL_RESET_MASK)
 426                 return -EIO;
 427
 428         mibvalue = 0;
 429         for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
 430                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 431                 if (err)
 432                         return err;
 433
 434                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 435         }
 436
 437         *val = mibvalue;
 438         return 0;
 439 }
 440
 441 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 442                                 struct rtl8366_vlan_4k *vlan4k)
 443 {
 444         struct rtl8366s_vlan_4k vlan4k_priv;
 445         int err;
 446         u32 data;
 447         u16 *tableaddr;
 448
 449         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 450         vlan4k_priv.vid = vid;
 451
 452         if (vid >= RTL8366S_NUM_VIDS)
 453                 return -EINVAL;
 454
 455         tableaddr = (u16 *)&vlan4k_priv;
 456
 457         /* write VID */
 458         data = *tableaddr;
 459         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
 460         if (err)
 461                 return err;
 462
 463         /* write table access control word */
 464         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 465                                     RTL8366S_TABLE_VLAN_READ_CTRL);
 466         if (err)
 467                 return err;
 468
 469         err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
 470         if (err)
 471                 return err;
 472
 473         *tableaddr = data;
 474         tableaddr++;
 475
 476         err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
 477                                    &data);
 478         if (err)
 479                 return err;
 480
 481         *tableaddr = data;
 482
 483         vlan4k->vid = vid;
 484         vlan4k->untag = vlan4k_priv.untag;
 485         vlan4k->member = vlan4k_priv.member;
 486         vlan4k->fid = vlan4k_priv.fid;
 487
 488         return 0;
 489 }
 490
 491 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
 492                                 const struct rtl8366_vlan_4k *vlan4k)
 493 {
 494         struct rtl8366s_vlan_4k vlan4k_priv;
 495         int err;
 496         u32 data;
 497         u16 *tableaddr;
 498
 499         if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
 500             vlan4k->member > RTL8366S_PORT_ALL ||
 501             vlan4k->untag > RTL8366S_PORT_ALL ||
 502             vlan4k->fid > RTL8366S_FIDMAX)
 503                 return -EINVAL;
 504
 505         vlan4k_priv.vid = vlan4k->vid;
 506         vlan4k_priv.untag = vlan4k->untag;
 507         vlan4k_priv.member = vlan4k->member;
 508         vlan4k_priv.fid = vlan4k->fid;
 509
 510         tableaddr = (u16 *)&vlan4k_priv;
 511
 512         data = *tableaddr;
 513
 514         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
 515         if (err)
 516                 return err;
 517
 518         tableaddr++;
 519
 520         data = *tableaddr;
 521
 522         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
 523                                     data);
 524         if (err)
 525                 return err;
 526
 527         /* write table access control word */
 528         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 529                                     RTL8366S_TABLE_VLAN_WRITE_CTRL);
 530
 531         return err;
 532 }
 533
 534 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 535                                 struct rtl8366_vlan_mc *vlanmc)
 536 {
 537         struct rtl8366s_vlan_mc vlanmc_priv;
 538         int err;
 539         u32 addr;
 540         u32 data;
 541         u16 *tableaddr;
 542
 543         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 544
 545         if (index >= RTL8366S_NUM_VLANS)
 546                 return -EINVAL;
 547
 548         tableaddr = (u16 *)&vlanmc_priv;
 549
 550         addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
 551         err = rtl8366_smi_read_reg(smi, addr, &data);
 552         if (err)
 553                 return err;
 554
 555         *tableaddr = data;
 556         tableaddr++;
 557
 558         addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
 559         err = rtl8366_smi_read_reg(smi, addr, &data);
 560         if (err)
 561                 return err;
 562
 563         *tableaddr = data;
 564
 565         vlanmc->vid = vlanmc_priv.vid;
 566         vlanmc->priority = vlanmc_priv.priority;
 567         vlanmc->untag = vlanmc_priv.untag;
 568         vlanmc->member = vlanmc_priv.member;
 569         vlanmc->fid = vlanmc_priv.fid;
 570
 571         return 0;
 572 }
 573
 574 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 575                                 const struct rtl8366_vlan_mc *vlanmc)
 576 {
 577         struct rtl8366s_vlan_mc vlanmc_priv;
 578         int err;
 579         u32 addr;
 580         u32 data;
 581         u16 *tableaddr;
 582
 583         if (index >= RTL8366S_NUM_VLANS ||
 584             vlanmc->vid >= RTL8366S_NUM_VIDS ||
 585             vlanmc->priority > RTL8366S_PRIORITYMAX ||
 586             vlanmc->member > RTL8366S_PORT_ALL ||
 587             vlanmc->untag > RTL8366S_PORT_ALL ||
 588             vlanmc->fid > RTL8366S_FIDMAX)
 589                 return -EINVAL;
 590
 591         vlanmc_priv.vid = vlanmc->vid;
 592         vlanmc_priv.priority = vlanmc->priority;
 593         vlanmc_priv.untag = vlanmc->untag;
 594         vlanmc_priv.member = vlanmc->member;
 595         vlanmc_priv.fid = vlanmc->fid;
 596
 597         addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
 598
 599         tableaddr = (u16 *)&vlanmc_priv;
 600         data = *tableaddr;
 601
 602         err = rtl8366_smi_write_reg(smi, addr, data);
 603         if (err)
 604                 return err;
 605
 606         addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
 607
 608         tableaddr++;
 609         data = *tableaddr;
 610
 611         err = rtl8366_smi_write_reg(smi, addr, data);
 612         if (err)
 613                 return err;
 614
 615         return 0;
 616 }
 617
 618 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 619 {
 620         u32 data;
 621         int err;
 622
 623         if (port >= RTL8366S_NUM_PORTS)
 624                 return -EINVAL;
 625
 626         err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 627                                    &data);
 628         if (err)
 629                 return err;
 630
 631         *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
 632                RTL8366S_PORT_VLAN_CTRL_MASK;
 633
 634         return 0;
 635 }
 636
 637 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 638 {
 639         if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
 640                 return -EINVAL;
 641
 642         return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 643                                 RTL8366S_PORT_VLAN_CTRL_MASK <<
 644                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
 645                                 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
 646                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
 647 }
 648
 649 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
 650 {
 651         return rtl8366_smi_rmwr(smi, RTL8366S_CHIP_GLOBAL_CTRL_REG,
 652                                 RTL8366S_CHIP_CTRL_VLAN,
 653                                 (enable) ? RTL8366S_CHIP_CTRL_VLAN : 0);
 654 }
 655
 656 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
 657 {
 658         return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
 659                                 1, (enable) ? 1 : 0);
 660 }
 661
 662 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
 663 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
 664                                           char __user *user_buf,
 665                                           size_t count, loff_t *ppos)
 666 {
 667         struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
 668         int i, j, len = 0;
 669         char *buf = smi->buf;
 670
 671         len += snprintf(buf + len, sizeof(smi->buf) - len,
 672                         "%-36s %12s %12s %12s %12s %12s %12s\n",
 673                         "Counter",
 674                         "Port 0", "Port 1", "Port 2",
 675                         "Port 3", "Port 4", "Port 5");
 676
 677         for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
 678                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%-36s ",
 679                                 rtl8366s_mib_counters[i].name);
 680                 for (j = 0; j < RTL8366S_NUM_PORTS; ++j) {
 681                         unsigned long long counter = 0;
 682
 683                         if (!rtl8366_get_mib_counter(smi, i, j, &counter))
 684                                 len += snprintf(buf + len,
 685                                                 sizeof(smi->buf) - len,
 686                                                 "%12llu ", counter);
 687                         else
 688                                 len += snprintf(buf + len,
 689                                                 sizeof(smi->buf) - len,
 690                                                 "%12s ", "error");
 691                 }
 692                 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
 693         }
 694
 695         return simple_read_from_buffer(user_buf, count, ppos, buf, len);
 696 }
 697
 698 static const struct file_operations fops_rtl8366s_mibs = {
 699         .read = rtl8366s_read_debugfs_mibs,
 700         .open = rtl8366_debugfs_open,
 701         .owner = THIS_MODULE
 702 };
 703
 704 static void rtl8366s_debugfs_init(struct rtl8366_smi *smi)
 705 {
 706         struct dentry *node;
 707
 708         if (!smi->debugfs_root)
 709                 return;
 710
 711         node = debugfs_create_file("mibs", S_IRUSR, smi->debugfs_root, smi,
 712                                    &fops_rtl8366s_mibs);
 713         if (!node)
 714                 dev_err(smi->parent, "Creating debugfs file '%s' failed\n",
 715                         "mibs");
 716 }
 717 #else
 718 static inline void rtl8366s_debugfs_init(struct rtl8366_smi *smi) {}
 719 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
 720
 721 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
 722                                   const struct switch_attr *attr,
 723                                   struct switch_val *val)
 724 {
 725         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 726         int err = 0;
 727
 728         if (val->value.i == 1)
 729                 err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
 730
 731         return err;
 732 }
 733
 734 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
 735                                        const struct switch_attr *attr,
 736                                        struct switch_val *val)
 737 {
 738         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 739         u32 data;
 740
 741         if (attr->ofs == 1) {
 742                 rtl8366_smi_read_reg(smi, RTL8366S_CHIP_GLOBAL_CTRL_REG, &data);
 743
 744                 if (data & RTL8366S_CHIP_CTRL_VLAN)
 745                         val->value.i = 1;
 746                 else
 747                         val->value.i = 0;
 748         } else if (attr->ofs == 2) {
 749                 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
 750
 751                 if (data & 0x0001)
 752                         val->value.i = 1;
 753                 else
 754                         val->value.i = 0;
 755         }
 756
 757         return 0;
 758 }
 759
 760 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
 761                                      const struct switch_attr *attr,
 762                                      struct switch_val *val)
 763 {
 764         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 765         u32 data;
 766
 767         rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
 768
 769         val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
 770
 771         return 0;
 772 }
 773
 774 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
 775                                     const struct switch_attr *attr,
 776                                     struct switch_val *val)
 777 {
 778         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 779
 780         if (val->value.i >= 6)
 781                 return -EINVAL;
 782
 783         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
 784                                 RTL8366S_LED_BLINKRATE_MASK,
 785                                 val->value.i);
 786 }
 787
 788 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
 789                                        const struct switch_attr *attr,
 790                                        struct switch_val *val)
 791 {
 792         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 793
 794         if (attr->ofs == 1)
 795                 return rtl8366s_vlan_set_vlan(smi, val->value.i);
 796         else
 797                 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
 798 }
 799
 800 static const char *rtl8366s_speed_str(unsigned speed)
 801 {
 802         switch (speed) {
 803         case 0:
 804                 return "10baseT";
 805         case 1:
 806                 return "100baseT";
 807         case 2:
 808                 return "1000baseT";
 809         }
 810
 811         return "unknown";
 812 }
 813
 814 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
 815                                      const struct switch_attr *attr,
 816                                      struct switch_val *val)
 817 {
 818         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 819         u32 len = 0, data = 0;
 820
 821         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 822                 return -EINVAL;
 823
 824         memset(smi->buf, '\0', sizeof(smi->buf));
 825         rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
 826                              (val->port_vlan / 2), &data);
 827
 828         if (val->port_vlan % 2)
 829                 data = data >> 8;
 830
 831         if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
 832                 len = snprintf(smi->buf, sizeof(smi->buf),
 833                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 834                                 val->port_vlan,
 835                                 rtl8366s_speed_str(data &
 836                                           RTL8366S_PORT_STATUS_SPEED_MASK),
 837                                 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
 838                                         "full" : "half",
 839                                 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
 840                                         "tx-pause ": "",
 841                                 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
 842                                         "rx-pause " : "",
 843                                 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
 844                                         "nway ": "");
 845         } else {
 846                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 847                                 val->port_vlan);
 848         }
 849
 850         val->value.s = smi->buf;
 851         val->len = len;
 852
 853         return 0;
 854 }
 855
 856 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
 857                                      const struct switch_attr *attr,
 858                                      struct switch_val *val)
 859 {
 860         int i;
 861         u32 len = 0;
 862         struct rtl8366_vlan_4k vlan4k;
 863         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 864         char *buf = smi->buf;
 865         int err;
 866
 867         if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
 868                 return -EINVAL;
 869
 870         memset(buf, '\0', sizeof(smi->buf));
 871
 872         err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 873         if (err)
 874                 return err;
 875
 876         len += snprintf(buf + len, sizeof(smi->buf) - len,
 877                         "VLAN %d: Ports: '", vlan4k.vid);
 878
 879         for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
 880                 if (!(vlan4k.member & (1 << i)))
 881                         continue;
 882
 883                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
 884                                 (vlan4k.untag & (1 << i)) ? "" : "t");
 885         }
 886
 887         len += snprintf(buf + len, sizeof(smi->buf) - len,
 888                         "', members=%04x, untag=%04x, fid=%u",
 889                         vlan4k.member, vlan4k.untag, vlan4k.fid);
 890
 891         val->value.s = buf;
 892         val->len = len;
 893
 894         return 0;
 895 }
 896
 897 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
 898                                     const struct switch_attr *attr,
 899                                     struct switch_val *val)
 900 {
 901         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 902         u32 data;
 903         u32 mask;
 904         u32 reg;
 905
 906         if (val->port_vlan >= RTL8366S_NUM_PORTS ||
 907             (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
 908                 return -EINVAL;
 909
 910         if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
 911                 reg = RTL8366S_LED_BLINKRATE_REG;
 912                 mask = 0xF << 4;
 913                 data = val->value.i << 4;
 914         } else {
 915                 reg = RTL8366S_LED_CTRL_REG;
 916                 mask = 0xF << (val->port_vlan * 4),
 917                 data = val->value.i << (val->port_vlan * 4);
 918         }
 919
 920         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, mask, data);
 921 }
 922
 923 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
 924                                     const struct switch_attr *attr,
 925                                     struct switch_val *val)
 926 {
 927         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 928         u32 data = 0;
 929
 930         if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
 931                 return -EINVAL;
 932
 933         rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
 934         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 935
 936         return 0;
 937 }
 938
 939 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
 940                                        const struct switch_attr *attr,
 941                                        struct switch_val *val)
 942 {
 943         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 944
 945         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 946                 return -EINVAL;
 947
 948
 949         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
 950                                 0, (1 << (val->port_vlan + 3)));
 951 }
 952
 953 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
 954                                     const struct switch_attr *attr,
 955                                     struct switch_val *val)
 956 {
 957         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 958         int i, len = 0;
 959         unsigned long long counter = 0;
 960         char *buf = smi->buf;
 961
 962         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 963                 return -EINVAL;
 964
 965         len += snprintf(buf + len, sizeof(smi->buf) - len,
 966                         "Port %d MIB counters\n",
 967                         val->port_vlan);
 968
 969         for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
 970                 len += snprintf(buf + len, sizeof(smi->buf) - len,
 971                                 "%-36s: ", rtl8366s_mib_counters[i].name);
 972                 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
 973                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 974                                         "%llu\n", counter);
 975                 else
 976                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 977                                         "%s\n", "error");
 978         }
 979
 980         val->value.s = buf;
 981         val->len = len;
 982         return 0;
 983 }
 984
 985 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
 986                                       struct switch_val *val)
 987 {
 988         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 989         struct switch_port *port;
 990         struct rtl8366_vlan_4k vlan4k;
 991         int i;
 992
 993         if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
 994                 return -EINVAL;
 995
 996         rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 997
 998         port = &val->value.ports[0];
 999         val->len = 0;
1000         for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
1001                 if (!(vlan4k.member & BIT(i)))
1002                         continue;
1003
1004                 port->id = i;
1005                 port->flags = (vlan4k.untag & BIT(i)) ?
1006                                         0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1007                 val->len++;
1008                 port++;
1009         }
1010         return 0;
1011 }
1012
1013 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1014                                       struct switch_val *val)
1015 {
1016         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1017         struct switch_port *port;
1018         u32 member = 0;
1019         u32 untag = 0;
1020         int i;
1021
1022         if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
1023                 return -EINVAL;
1024
1025         port = &val->value.ports[0];
1026         for (i = 0; i < val->len; i++, port++) {
1027                 member |= BIT(port->id);
1028
1029                 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1030                         untag |= BIT(port->id);
1031         }
1032
1033         return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
1034 }
1035
1036 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1037 {
1038         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1039         return rtl8366_get_pvid(smi, port, val);
1040 }
1041
1042 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1043 {
1044         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1045         return rtl8366_set_pvid(smi, port, val);
1046 }
1047
1048 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1049 {
1050         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1051         int err;
1052
1053         err = rtl8366s_reset_chip(smi);
1054         if (err)
1055                 return err;
1056
1057         err = rtl8366s_hw_init(smi);
1058         if (err)
1059                 return err;
1060
1061         return rtl8366_reset_vlan(smi);
1062 }
1063
1064 static struct switch_attr rtl8366s_globals[] = {
1065         {
1066                 .type = SWITCH_TYPE_INT,
1067                 .name = "enable_vlan",
1068                 .description = "Enable VLAN mode",
1069                 .set = rtl8366s_sw_set_vlan_enable,
1070                 .get = rtl8366s_sw_get_vlan_enable,
1071                 .max = 1,
1072                 .ofs = 1
1073         }, {
1074                 .type = SWITCH_TYPE_INT,
1075                 .name = "enable_vlan4k",
1076                 .description = "Enable VLAN 4K mode",
1077                 .set = rtl8366s_sw_set_vlan_enable,
1078                 .get = rtl8366s_sw_get_vlan_enable,
1079                 .max = 1,
1080                 .ofs = 2
1081         }, {
1082                 .type = SWITCH_TYPE_INT,
1083                 .name = "reset_mibs",
1084                 .description = "Reset all MIB counters",
1085                 .set = rtl8366s_sw_reset_mibs,
1086                 .get = NULL,
1087                 .max = 1
1088         }, {
1089                 .type = SWITCH_TYPE_INT,
1090                 .name = "blinkrate",
1091                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1092                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1093                 .set = rtl8366s_sw_set_blinkrate,
1094                 .get = rtl8366s_sw_get_blinkrate,
1095                 .max = 5
1096         },
1097 };
1098
1099 static struct switch_attr rtl8366s_port[] = {
1100         {
1101                 .type = SWITCH_TYPE_STRING,
1102                 .name = "link",
1103                 .description = "Get port link information",
1104                 .max = 1,
1105                 .set = NULL,
1106                 .get = rtl8366s_sw_get_port_link,
1107         }, {
1108                 .type = SWITCH_TYPE_INT,
1109                 .name = "reset_mib",
1110                 .description = "Reset single port MIB counters",
1111                 .max = 1,
1112                 .set = rtl8366s_sw_reset_port_mibs,
1113                 .get = NULL,
1114         }, {
1115                 .type = SWITCH_TYPE_STRING,
1116                 .name = "mib",
1117                 .description = "Get MIB counters for port",
1118                 .max = 33,
1119                 .set = NULL,
1120                 .get = rtl8366s_sw_get_port_mib,
1121         }, {
1122                 .type = SWITCH_TYPE_INT,
1123                 .name = "led",
1124                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1125                 .max = 15,
1126                 .set = rtl8366s_sw_set_port_led,
1127                 .get = rtl8366s_sw_get_port_led,
1128         },
1129 };
1130
1131 static struct switch_attr rtl8366s_vlan[] = {
1132         {
1133                 .type = SWITCH_TYPE_STRING,
1134                 .name = "info",
1135                 .description = "Get vlan information",
1136                 .max = 1,
1137                 .set = NULL,
1138                 .get = rtl8366s_sw_get_vlan_info,
1139         },
1140 };
1141
1142 /* template */
1143 static struct switch_dev rtl8366_switch_dev = {
1144         .name = "RTL8366S",
1145         .cpu_port = RTL8366S_PORT_NUM_CPU,
1146         .ports = RTL8366S_NUM_PORTS,
1147         .vlans = RTL8366S_NUM_VLANS,
1148         .attr_global = {
1149                 .attr = rtl8366s_globals,
1150                 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1151         },
1152         .attr_port = {
1153                 .attr = rtl8366s_port,
1154                 .n_attr = ARRAY_SIZE(rtl8366s_port),
1155         },
1156         .attr_vlan = {
1157                 .attr = rtl8366s_vlan,
1158                 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1159         },
1160
1161         .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1162         .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1163         .get_port_pvid = rtl8366s_sw_get_port_pvid,
1164         .set_port_pvid = rtl8366s_sw_set_port_pvid,
1165         .reset_switch = rtl8366s_sw_reset_switch,
1166 };
1167
1168 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1169 {
1170         struct switch_dev *dev = &rtl->dev;
1171         int err;
1172
1173         memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1174         dev->priv = rtl;
1175         dev->devname = dev_name(rtl->parent);
1176
1177         err = register_switch(dev, NULL);
1178         if (err)
1179                 dev_err(rtl->parent, "switch registration failed\n");
1180
1181         return err;
1182 }
1183
1184 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1185 {
1186         unregister_switch(&rtl->dev);
1187 }
1188
1189 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1190 {
1191         struct rtl8366_smi *smi = bus->priv;
1192         u32 val = 0;
1193         int err;
1194
1195         err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1196         if (err)
1197                 return 0xffff;
1198
1199         return val;
1200 }
1201
1202 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1203 {
1204         struct rtl8366_smi *smi = bus->priv;
1205         u32 t;
1206         int err;
1207
1208         err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1209         /* flush write */
1210         (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1211
1212         return err;
1213 }
1214
1215 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1216 {
1217         return (bus->read == rtl8366s_mii_read &&
1218                 bus->write == rtl8366s_mii_write);
1219 }
1220
1221 static int rtl8366s_setup(struct rtl8366s *rtl)
1222 {
1223         struct rtl8366_smi *smi = &rtl->smi;
1224         int ret;
1225
1226         rtl8366s_debugfs_init(smi);
1227
1228         ret = rtl8366s_reset_chip(smi);
1229         if (ret)
1230                 return ret;
1231
1232         ret = rtl8366s_hw_init(smi);
1233         return ret;
1234 }
1235
1236 static int rtl8366s_detect(struct rtl8366_smi *smi)
1237 {
1238         u32 chip_id = 0;
1239         u32 chip_ver = 0;
1240         int ret;
1241
1242         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1243         if (ret) {
1244                 dev_err(smi->parent, "unable to read chip id\n");
1245                 return ret;
1246         }
1247
1248         switch (chip_id) {
1249         case RTL8366S_CHIP_ID_8366:
1250                 break;
1251         default:
1252                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1253                 return -ENODEV;
1254         }
1255
1256         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1257                                    &chip_ver);
1258         if (ret) {
1259                 dev_err(smi->parent, "unable to read chip version\n");
1260                 return ret;
1261         }
1262
1263         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1264                  chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1265
1266         return 0;
1267 }
1268
1269 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1270         .detect         = rtl8366s_detect,
1271         .mii_read       = rtl8366s_mii_read,
1272         .mii_write      = rtl8366s_mii_write,
1273
1274         .get_vlan_mc    = rtl8366s_get_vlan_mc,
1275         .set_vlan_mc    = rtl8366s_set_vlan_mc,
1276         .get_vlan_4k    = rtl8366s_get_vlan_4k,
1277         .set_vlan_4k    = rtl8366s_set_vlan_4k,
1278         .get_mc_index   = rtl8366s_get_mc_index,
1279         .set_mc_index   = rtl8366s_set_mc_index,
1280 };
1281
1282 static int __init rtl8366s_probe(struct platform_device *pdev)
1283 {
1284         static int rtl8366_smi_version_printed;
1285         struct rtl8366s_platform_data *pdata;
1286         struct rtl8366s *rtl;
1287         struct rtl8366_smi *smi;
1288         int err;
1289
1290         if (!rtl8366_smi_version_printed++)
1291                 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1292                        " version " RTL8366S_DRIVER_VER"\n");
1293
1294         pdata = pdev->dev.platform_data;
1295         if (!pdata) {
1296                 dev_err(&pdev->dev, "no platform data specified\n");
1297                 err = -EINVAL;
1298                 goto err_out;
1299         }
1300
1301         rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1302         if (!rtl) {
1303                 dev_err(&pdev->dev, "no memory for private data\n");
1304                 err = -ENOMEM;
1305                 goto err_out;
1306         }
1307
1308         rtl->parent = &pdev->dev;
1309
1310         smi = &rtl->smi;
1311         smi->parent = &pdev->dev;
1312         smi->gpio_sda = pdata->gpio_sda;
1313         smi->gpio_sck = pdata->gpio_sck;
1314         smi->ops = &rtl8366s_smi_ops;
1315         smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1316         smi->num_ports = RTL8366S_NUM_PORTS;
1317         smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1318
1319         err = rtl8366_smi_init(smi);
1320         if (err)
1321                 goto err_free_rtl;
1322
1323         platform_set_drvdata(pdev, rtl);
1324
1325         err = rtl8366s_setup(rtl);
1326         if (err)
1327                 goto err_clear_drvdata;
1328
1329         err = rtl8366s_switch_init(rtl);
1330         if (err)
1331                 goto err_clear_drvdata;
1332
1333         return 0;
1334
1335  err_clear_drvdata:
1336         platform_set_drvdata(pdev, NULL);
1337         rtl8366_smi_cleanup(smi);
1338  err_free_rtl:
1339         kfree(rtl);
1340  err_out:
1341         return err;
1342 }
1343
1344 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1345 {
1346         if (!rtl8366s_mii_bus_match(phydev->bus))
1347                 return -EINVAL;
1348
1349         return 0;
1350 }
1351
1352 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1353 {
1354         return 0;
1355 }
1356
1357 static struct phy_driver rtl8366s_phy_driver = {
1358         .phy_id         = 0x001cc960,
1359         .name           = "Realtek RTL8366S",
1360         .phy_id_mask    = 0x1ffffff0,
1361         .features       = PHY_GBIT_FEATURES,
1362         .config_aneg    = rtl8366s_phy_config_aneg,
1363         .config_init    = rtl8366s_phy_config_init,
1364         .read_status    = genphy_read_status,
1365         .driver         = {
1366                 .owner = THIS_MODULE,
1367         },
1368 };
1369
1370 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1371 {
1372         struct rtl8366s *rtl = platform_get_drvdata(pdev);
1373
1374         if (rtl) {
1375                 rtl8366s_switch_cleanup(rtl);
1376                 platform_set_drvdata(pdev, NULL);
1377                 rtl8366_smi_cleanup(&rtl->smi);
1378                 kfree(rtl);
1379         }
1380
1381         return 0;
1382 }
1383
1384 static struct platform_driver rtl8366s_driver = {
1385         .driver = {
1386                 .name           = RTL8366S_DRIVER_NAME,
1387                 .owner          = THIS_MODULE,
1388         },
1389         .probe          = rtl8366s_probe,
1390         .remove         = __devexit_p(rtl8366s_remove),
1391 };
1392
1393 static int __init rtl8366s_module_init(void)
1394 {
1395         int ret;
1396         ret = platform_driver_register(&rtl8366s_driver);
1397         if (ret)
1398                 return ret;
1399
1400         ret = phy_driver_register(&rtl8366s_phy_driver);
1401         if (ret)
1402                 goto err_platform_unregister;
1403
1404         return 0;
1405
1406  err_platform_unregister:
1407         platform_driver_unregister(&rtl8366s_driver);
1408         return ret;
1409 }
1410 module_init(rtl8366s_module_init);
1411
1412 static void __exit rtl8366s_module_exit(void)
1413 {
1414         phy_driver_unregister(&rtl8366s_phy_driver);
1415         platform_driver_unregister(&rtl8366s_driver);
1416 }
1417 module_exit(rtl8366s_module_exit);
1418
1419 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1420 MODULE_VERSION(RTL8366S_DRIVER_VER);
1421 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1422 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1423 MODULE_LICENSE("GPL v2");
1424 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);