target/linux/generic-2.6/files/drivers/net/phy/rtl8366s.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/switch.h>
  19 #include <linux/rtl8366s.h>
  20
  21 #include "rtl8366_smi.h"
  22
  23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
  24 #include <linux/debugfs.h>
  25 #endif
  26
  27 #define RTL8366S_DRIVER_DESC    "Realtek RTL8366S ethernet switch driver"
  28 #define RTL8366S_DRIVER_VER     "0.2.2"
  29
  30 #define RTL8366S_PHY_NO_MAX     4
  31 #define RTL8366S_PHY_PAGE_MAX   7
  32 #define RTL8366S_PHY_ADDR_MAX   31
  33
  34 #define RTL8366S_CHIP_GLOBAL_CTRL_REG           0x0000
  35 #define RTL8366S_CHIP_CTRL_VLAN                 (1 << 13)
  36
  37 /* Switch Global Configuration register */
  38 #define RTL8366S_SGCR                           0x0000
  39 #define RTL8366S_SGCR_EN_BC_STORM_CTRL          BIT(0)
  40 #define RTL8366S_SGCR_MAX_LENGTH(_x)            (_x << 4)
  41 #define RTL8366S_SGCR_MAX_LENGTH_MASK           RTL8366S_SGCR_MAX_LENGTH(0x3)
  42 #define RTL8366S_SGCR_MAX_LENGTH_1522           RTL8366S_SGCR_MAX_LENGTH(0x0)
  43 #define RTL8366S_SGCR_MAX_LENGTH_1536           RTL8366S_SGCR_MAX_LENGTH(0x1)
  44 #define RTL8366S_SGCR_MAX_LENGTH_1552           RTL8366S_SGCR_MAX_LENGTH(0x2)
  45 #define RTL8366S_SGCR_MAX_LENGTH_16000          RTL8366S_SGCR_MAX_LENGTH(0x3)
  46
  47 /* Port Enable Control register */
  48 #define RTL8366S_PECR                           0x0001
  49
  50 /* Switch Security Control registers */
  51 #define RTL8366S_SSCR0                          0x0002
  52 #define RTL8366S_SSCR1                          0x0003
  53 #define RTL8366S_SSCR2                          0x0004
  54 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA          BIT(0)
  55
  56 #define RTL8366S_RESET_CTRL_REG                 0x0100
  57 #define RTL8366S_CHIP_CTRL_RESET_HW             1
  58 #define RTL8366S_CHIP_CTRL_RESET_SW             (1 << 1)
  59
  60 #define RTL8366S_CHIP_VERSION_CTRL_REG          0x0104
  61 #define RTL8366S_CHIP_VERSION_MASK              0xf
  62 #define RTL8366S_CHIP_ID_REG                    0x0105
  63 #define RTL8366S_CHIP_ID_8366                   0x8366
  64
  65 /* PHY registers control */
  66 #define RTL8366S_PHY_ACCESS_CTRL_REG            0x8028
  67 #define RTL8366S_PHY_ACCESS_DATA_REG            0x8029
  68
  69 #define RTL8366S_PHY_CTRL_READ                  1
  70 #define RTL8366S_PHY_CTRL_WRITE                 0
  71
  72 #define RTL8366S_PHY_REG_MASK                   0x1f
  73 #define RTL8366S_PHY_PAGE_OFFSET                5
  74 #define RTL8366S_PHY_PAGE_MASK                  (0x7 << 5)
  75 #define RTL8366S_PHY_NO_OFFSET                  9
  76 #define RTL8366S_PHY_NO_MASK                    (0x1f << 9)
  77
  78 /* LED control registers */
  79 #define RTL8366S_LED_BLINKRATE_REG              0x0420
  80 #define RTL8366S_LED_BLINKRATE_BIT              0
  81 #define RTL8366S_LED_BLINKRATE_MASK             0x0007
  82
  83 #define RTL8366S_LED_CTRL_REG                   0x0421
  84 #define RTL8366S_LED_0_1_CTRL_REG               0x0422
  85 #define RTL8366S_LED_2_3_CTRL_REG               0x0423
  86
  87 #define RTL8366S_MIB_COUNT                      33
  88 #define RTL8366S_GLOBAL_MIB_COUNT               1
  89 #define RTL8366S_MIB_COUNTER_PORT_OFFSET        0x0040
  90 #define RTL8366S_MIB_COUNTER_BASE               0x1000
  91 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2       0x0008
  92 #define RTL8366S_MIB_COUNTER_BASE2              0x1180
  93 #define RTL8366S_MIB_CTRL_REG                   0x11F0
  94 #define RTL8366S_MIB_CTRL_USER_MASK             0x01FF
  95 #define RTL8366S_MIB_CTRL_BUSY_MASK             0x0001
  96 #define RTL8366S_MIB_CTRL_RESET_MASK            0x0002
  97
  98 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK     0x0004
  99 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT        0x0003
 100 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK       0x01FC
 101
 102
 103 #define RTL8366S_PORT_VLAN_CTRL_BASE            0x0058
 104 #define RTL8366S_PORT_VLAN_CTRL_REG(_p)  \
 105                 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
 106 #define RTL8366S_PORT_VLAN_CTRL_MASK            0xf
 107 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p)       (4 * ((_p) % 4))
 108
 109
 110 #define RTL8366S_VLAN_TABLE_READ_BASE           0x018B
 111 #define RTL8366S_VLAN_TABLE_WRITE_BASE          0x0185
 112
 113 #define RTL8366S_VLAN_TB_CTRL_REG               0x010F
 114
 115 #define RTL8366S_TABLE_ACCESS_CTRL_REG          0x0180
 116 #define RTL8366S_TABLE_VLAN_READ_CTRL           0x0E01
 117 #define RTL8366S_TABLE_VLAN_WRITE_CTRL          0x0F01
 118
 119 #define RTL8366S_VLAN_MEMCONF_BASE              0x0016
 120
 121
 122 #define RTL8366S_PORT_LINK_STATUS_BASE          0x0060
 123 #define RTL8366S_PORT_STATUS_SPEED_MASK         0x0003
 124 #define RTL8366S_PORT_STATUS_DUPLEX_MASK        0x0004
 125 #define RTL8366S_PORT_STATUS_LINK_MASK          0x0010
 126 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK       0x0020
 127 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK       0x0040
 128 #define RTL8366S_PORT_STATUS_AN_MASK            0x0080
 129
 130
 131 #define RTL8366S_PORT_NUM_CPU           5
 132 #define RTL8366S_NUM_PORTS              6
 133 #define RTL8366S_NUM_VLANS              16
 134 #define RTL8366S_NUM_LEDGROUPS          4
 135 #define RTL8366S_NUM_VIDS               4096
 136 #define RTL8366S_PRIORITYMAX            7
 137 #define RTL8366S_FIDMAX                 7
 138
 139
 140 #define RTL8366S_PORT_1                 (1 << 0) /* In userspace port 0 */
 141 #define RTL8366S_PORT_2                 (1 << 1) /* In userspace port 1 */
 142 #define RTL8366S_PORT_3                 (1 << 2) /* In userspace port 2 */
 143 #define RTL8366S_PORT_4                 (1 << 3) /* In userspace port 3 */
 144
 145 #define RTL8366S_PORT_UNKNOWN           (1 << 4) /* No known connection */
 146 #define RTL8366S_PORT_CPU               (1 << 5) /* CPU port */
 147
 148 #define RTL8366S_PORT_ALL               (RTL8366S_PORT_1 |      \
 149                                          RTL8366S_PORT_2 |      \
 150                                          RTL8366S_PORT_3 |      \
 151                                          RTL8366S_PORT_4 |      \
 152                                          RTL8366S_PORT_UNKNOWN | \
 153                                          RTL8366S_PORT_CPU)
 154
 155 #define RTL8366S_PORT_ALL_BUT_CPU       (RTL8366S_PORT_1 |      \
 156                                          RTL8366S_PORT_2 |      \
 157                                          RTL8366S_PORT_3 |      \
 158                                          RTL8366S_PORT_4 |      \
 159                                          RTL8366S_PORT_UNKNOWN)
 160
 161 #define RTL8366S_PORT_ALL_EXTERNAL      (RTL8366S_PORT_1 |      \
 162                                          RTL8366S_PORT_2 |      \
 163                                          RTL8366S_PORT_3 |      \
 164                                          RTL8366S_PORT_4)
 165
 166 #define RTL8366S_PORT_ALL_INTERNAL      (RTL8366S_PORT_UNKNOWN | \
 167                                          RTL8366S_PORT_CPU)
 168
 169 struct rtl8366s {
 170         struct device           *parent;
 171         struct rtl8366_smi      smi;
 172         struct switch_dev       dev;
 173 };
 174
 175 struct rtl8366s_vlan_mc {
 176         u16     reserved2:1;
 177         u16     priority:3;
 178         u16     vid:12;
 179
 180         u16     reserved1:1;
 181         u16     fid:3;
 182         u16     untag:6;
 183         u16     member:6;
 184 };
 185
 186 struct rtl8366s_vlan_4k {
 187         u16     reserved1:4;
 188         u16     vid:12;
 189
 190         u16     reserved2:1;
 191         u16     fid:3;
 192         u16     untag:6;
 193         u16     member:6;
 194 };
 195
 196 struct mib_counter {
 197         unsigned        base;
 198         unsigned        offset;
 199         unsigned        length;
 200         const char      *name;
 201 };
 202
 203 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
 204         { 0,  0, 4, "IfInOctets"                                },
 205         { 0,  4, 4, "EtherStatsOctets"                          },
 206         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 207         { 0, 10, 2, "EtherFragments"                            },
 208         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 209         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 210         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 211         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 212         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 213         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 214         { 0, 24, 2, "EtherOversizeStats"                        },
 215         { 0, 26, 2, "EtherStatsJabbers"                         },
 216         { 0, 28, 2, "IfInUcastPkts"                             },
 217         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 218         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 219         { 0, 34, 2, "EtherStatsDropEvents"                      },
 220         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 221         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 222         { 0, 40, 2, "Dot3InPauseFrames"                         },
 223         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 224         { 0, 44, 4, "IfOutOctets"                               },
 225         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 226         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 227         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 228         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 229         { 0, 56, 2, "EtherStatsCollisions"                      },
 230         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 231         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 232         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 233
 234         /*
 235          * The following counters are accessible at a different
 236          * base address.
 237          */
 238         { 1,  0, 2, "Dot1dTpPortInDiscards"                     },
 239         { 1,  2, 2, "IfOutUcastPkts"                            },
 240         { 1,  4, 2, "IfOutMulticastPkts"                        },
 241         { 1,  6, 2, "IfOutBroadcastPkts"                        },
 242 };
 243
 244 #define REG_WR(_smi, _reg, _val)                                        \
 245         do {                                                            \
 246                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 247                 if (err)                                                \
 248                         return err;                                     \
 249         } while (0)
 250
 251 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 252         do {                                                            \
 253                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 254                 if (err)                                                \
 255                         return err;                                     \
 256         } while (0)
 257
 258 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
 259 {
 260         return container_of(smi, struct rtl8366s, smi);
 261 }
 262
 263 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
 264 {
 265         return container_of(sw, struct rtl8366s, dev);
 266 }
 267
 268 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
 269 {
 270         struct rtl8366s *rtl = sw_to_rtl8366s(sw);
 271         return &rtl->smi;
 272 }
 273
 274 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
 275 {
 276         int timeout = 10;
 277         u32 data;
 278
 279         rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
 280                               RTL8366S_CHIP_CTRL_RESET_HW);
 281         do {
 282                 msleep(1);
 283                 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
 284                         return -EIO;
 285
 286                 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
 287                         break;
 288         } while (--timeout);
 289
 290         if (!timeout) {
 291                 printk("Timeout waiting for the switch to reset\n");
 292                 return -EIO;
 293         }
 294
 295         return 0;
 296 }
 297
 298 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
 299 {
 300         int err;
 301
 302         /* set maximum packet length to 1536 bytes */
 303         REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
 304                 RTL8366S_SGCR_MAX_LENGTH_1536);
 305
 306         /* enable all ports */
 307         REG_WR(smi, RTL8366S_PECR, 0);
 308
 309         /* disable learning for all ports */
 310         REG_WR(smi, RTL8366S_SSCR0, RTL8366S_PORT_ALL);
 311
 312         /* disable auto ageing for all ports */
 313         REG_WR(smi, RTL8366S_SSCR1, RTL8366S_PORT_ALL);
 314
 315         /* don't drop packets whose DA has not been learned */
 316         REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
 317
 318         return 0;
 319 }
 320
 321 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
 322                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 323 {
 324         u32 reg;
 325         int ret;
 326
 327         if (phy_no > RTL8366S_PHY_NO_MAX)
 328                 return -EINVAL;
 329
 330         if (page > RTL8366S_PHY_PAGE_MAX)
 331                 return -EINVAL;
 332
 333         if (addr > RTL8366S_PHY_ADDR_MAX)
 334                 return -EINVAL;
 335
 336         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 337                                     RTL8366S_PHY_CTRL_READ);
 338         if (ret)
 339                 return ret;
 340
 341         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 342               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 343               (addr & RTL8366S_PHY_REG_MASK);
 344
 345         ret = rtl8366_smi_write_reg(smi, reg, 0);
 346         if (ret)
 347                 return ret;
 348
 349         ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
 350         if (ret)
 351                 return ret;
 352
 353         return 0;
 354 }
 355
 356 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
 357                                   u32 phy_no, u32 page, u32 addr, u32 data)
 358 {
 359         u32 reg;
 360         int ret;
 361
 362         if (phy_no > RTL8366S_PHY_NO_MAX)
 363                 return -EINVAL;
 364
 365         if (page > RTL8366S_PHY_PAGE_MAX)
 366                 return -EINVAL;
 367
 368         if (addr > RTL8366S_PHY_ADDR_MAX)
 369                 return -EINVAL;
 370
 371         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 372                                     RTL8366S_PHY_CTRL_WRITE);
 373         if (ret)
 374                 return ret;
 375
 376         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 377               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 378               (addr & RTL8366S_PHY_REG_MASK);
 379
 380         ret = rtl8366_smi_write_reg(smi, reg, data);
 381         if (ret)
 382                 return ret;
 383
 384         return 0;
 385 }
 386
 387 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
 388                                    int port, unsigned long long *val)
 389 {
 390         int i;
 391         int err;
 392         u32 addr, data;
 393         u64 mibvalue;
 394
 395         if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
 396                 return -EINVAL;
 397
 398         switch (rtl8366s_mib_counters[counter].base) {
 399         case 0:
 400                 addr = RTL8366S_MIB_COUNTER_BASE +
 401                        RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
 402                 break;
 403
 404         case 1:
 405                 addr = RTL8366S_MIB_COUNTER_BASE2 +
 406                         RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
 407                 break;
 408
 409         default:
 410                 return -EINVAL;
 411         }
 412
 413         addr += rtl8366s_mib_counters[counter].offset;
 414
 415         /*
 416          * Writing access counter address first
 417          * then ASIC will prepare 64bits counter wait for being retrived
 418          */
 419         data = 0; /* writing data will be discard by ASIC */
 420         err = rtl8366_smi_write_reg(smi, addr, data);
 421         if (err)
 422                 return err;
 423
 424         /* read MIB control register */
 425         err =  rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
 426         if (err)
 427                 return err;
 428
 429         if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
 430                 return -EBUSY;
 431
 432         if (data & RTL8366S_MIB_CTRL_RESET_MASK)
 433                 return -EIO;
 434
 435         mibvalue = 0;
 436         for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
 437                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 438                 if (err)
 439                         return err;
 440
 441                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 442         }
 443
 444         *val = mibvalue;
 445         return 0;
 446 }
 447
 448 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 449                                 struct rtl8366_vlan_4k *vlan4k)
 450 {
 451         struct rtl8366s_vlan_4k vlan4k_priv;
 452         int err;
 453         u32 data;
 454         u16 *tableaddr;
 455
 456         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 457         vlan4k_priv.vid = vid;
 458
 459         if (vid >= RTL8366S_NUM_VIDS)
 460                 return -EINVAL;
 461
 462         tableaddr = (u16 *)&vlan4k_priv;
 463
 464         /* write VID */
 465         data = *tableaddr;
 466         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
 467         if (err)
 468                 return err;
 469
 470         /* write table access control word */
 471         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 472                                     RTL8366S_TABLE_VLAN_READ_CTRL);
 473         if (err)
 474                 return err;
 475
 476         err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
 477         if (err)
 478                 return err;
 479
 480         *tableaddr = data;
 481         tableaddr++;
 482
 483         err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
 484                                    &data);
 485         if (err)
 486                 return err;
 487
 488         *tableaddr = data;
 489
 490         vlan4k->vid = vid;
 491         vlan4k->untag = vlan4k_priv.untag;
 492         vlan4k->member = vlan4k_priv.member;
 493         vlan4k->fid = vlan4k_priv.fid;
 494
 495         return 0;
 496 }
 497
 498 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
 499                                 const struct rtl8366_vlan_4k *vlan4k)
 500 {
 501         struct rtl8366s_vlan_4k vlan4k_priv;
 502         int err;
 503         u32 data;
 504         u16 *tableaddr;
 505
 506         if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
 507             vlan4k->member > RTL8366S_PORT_ALL ||
 508             vlan4k->untag > RTL8366S_PORT_ALL ||
 509             vlan4k->fid > RTL8366S_FIDMAX)
 510                 return -EINVAL;
 511
 512         vlan4k_priv.vid = vlan4k->vid;
 513         vlan4k_priv.untag = vlan4k->untag;
 514         vlan4k_priv.member = vlan4k->member;
 515         vlan4k_priv.fid = vlan4k->fid;
 516
 517         tableaddr = (u16 *)&vlan4k_priv;
 518
 519         data = *tableaddr;
 520
 521         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
 522         if (err)
 523                 return err;
 524
 525         tableaddr++;
 526
 527         data = *tableaddr;
 528
 529         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
 530                                     data);
 531         if (err)
 532                 return err;
 533
 534         /* write table access control word */
 535         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 536                                     RTL8366S_TABLE_VLAN_WRITE_CTRL);
 537
 538         return err;
 539 }
 540
 541 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 542                                 struct rtl8366_vlan_mc *vlanmc)
 543 {
 544         struct rtl8366s_vlan_mc vlanmc_priv;
 545         int err;
 546         u32 addr;
 547         u32 data;
 548         u16 *tableaddr;
 549
 550         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 551
 552         if (index >= RTL8366S_NUM_VLANS)
 553                 return -EINVAL;
 554
 555         tableaddr = (u16 *)&vlanmc_priv;
 556
 557         addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
 558         err = rtl8366_smi_read_reg(smi, addr, &data);
 559         if (err)
 560                 return err;
 561
 562         *tableaddr = data;
 563         tableaddr++;
 564
 565         addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
 566         err = rtl8366_smi_read_reg(smi, addr, &data);
 567         if (err)
 568                 return err;
 569
 570         *tableaddr = data;
 571
 572         vlanmc->vid = vlanmc_priv.vid;
 573         vlanmc->priority = vlanmc_priv.priority;
 574         vlanmc->untag = vlanmc_priv.untag;
 575         vlanmc->member = vlanmc_priv.member;
 576         vlanmc->fid = vlanmc_priv.fid;
 577
 578         return 0;
 579 }
 580
 581 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 582                                 const struct rtl8366_vlan_mc *vlanmc)
 583 {
 584         struct rtl8366s_vlan_mc vlanmc_priv;
 585         int err;
 586         u32 addr;
 587         u32 data;
 588         u16 *tableaddr;
 589
 590         if (index >= RTL8366S_NUM_VLANS ||
 591             vlanmc->vid >= RTL8366S_NUM_VIDS ||
 592             vlanmc->priority > RTL8366S_PRIORITYMAX ||
 593             vlanmc->member > RTL8366S_PORT_ALL ||
 594             vlanmc->untag > RTL8366S_PORT_ALL ||
 595             vlanmc->fid > RTL8366S_FIDMAX)
 596                 return -EINVAL;
 597
 598         vlanmc_priv.vid = vlanmc->vid;
 599         vlanmc_priv.priority = vlanmc->priority;
 600         vlanmc_priv.untag = vlanmc->untag;
 601         vlanmc_priv.member = vlanmc->member;
 602         vlanmc_priv.fid = vlanmc->fid;
 603
 604         addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
 605
 606         tableaddr = (u16 *)&vlanmc_priv;
 607         data = *tableaddr;
 608
 609         err = rtl8366_smi_write_reg(smi, addr, data);
 610         if (err)
 611                 return err;
 612
 613         addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
 614
 615         tableaddr++;
 616         data = *tableaddr;
 617
 618         err = rtl8366_smi_write_reg(smi, addr, data);
 619         if (err)
 620                 return err;
 621
 622         return 0;
 623 }
 624
 625 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 626 {
 627         u32 data;
 628         int err;
 629
 630         if (port >= RTL8366S_NUM_PORTS)
 631                 return -EINVAL;
 632
 633         err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 634                                    &data);
 635         if (err)
 636                 return err;
 637
 638         *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
 639                RTL8366S_PORT_VLAN_CTRL_MASK;
 640
 641         return 0;
 642 }
 643
 644 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 645 {
 646         if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
 647                 return -EINVAL;
 648
 649         return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 650                                 RTL8366S_PORT_VLAN_CTRL_MASK <<
 651                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
 652                                 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
 653                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
 654 }
 655
 656 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
 657 {
 658         return rtl8366_smi_rmwr(smi, RTL8366S_CHIP_GLOBAL_CTRL_REG,
 659                                 RTL8366S_CHIP_CTRL_VLAN,
 660                                 (enable) ? RTL8366S_CHIP_CTRL_VLAN : 0);
 661 }
 662
 663 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
 664 {
 665         return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
 666                                 1, (enable) ? 1 : 0);
 667 }
 668
 669 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
 670 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
 671                                           char __user *user_buf,
 672                                           size_t count, loff_t *ppos)
 673 {
 674         struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
 675         int i, j, len = 0;
 676         char *buf = smi->buf;
 677
 678         len += snprintf(buf + len, sizeof(smi->buf) - len,
 679                         "%-36s %12s %12s %12s %12s %12s %12s\n",
 680                         "Counter",
 681                         "Port 0", "Port 1", "Port 2",
 682                         "Port 3", "Port 4", "Port 5");
 683
 684         for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
 685                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%-36s ",
 686                                 rtl8366s_mib_counters[i].name);
 687                 for (j = 0; j < RTL8366S_NUM_PORTS; ++j) {
 688                         unsigned long long counter = 0;
 689
 690                         if (!rtl8366_get_mib_counter(smi, i, j, &counter))
 691                                 len += snprintf(buf + len,
 692                                                 sizeof(smi->buf) - len,
 693                                                 "%12llu ", counter);
 694                         else
 695                                 len += snprintf(buf + len,
 696                                                 sizeof(smi->buf) - len,
 697                                                 "%12s ", "error");
 698                 }
 699                 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
 700         }
 701
 702         return simple_read_from_buffer(user_buf, count, ppos, buf, len);
 703 }
 704
 705 static const struct file_operations fops_rtl8366s_mibs = {
 706         .read = rtl8366s_read_debugfs_mibs,
 707         .open = rtl8366_debugfs_open,
 708         .owner = THIS_MODULE
 709 };
 710
 711 static void rtl8366s_debugfs_init(struct rtl8366_smi *smi)
 712 {
 713         struct dentry *node;
 714
 715         if (!smi->debugfs_root)
 716                 return;
 717
 718         node = debugfs_create_file("mibs", S_IRUSR, smi->debugfs_root, smi,
 719                                    &fops_rtl8366s_mibs);
 720         if (!node)
 721                 dev_err(smi->parent, "Creating debugfs file '%s' failed\n",
 722                         "mibs");
 723 }
 724 #else
 725 static inline void rtl8366s_debugfs_init(struct rtl8366_smi *smi) {}
 726 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
 727
 728 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
 729                                   const struct switch_attr *attr,
 730                                   struct switch_val *val)
 731 {
 732         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 733         int err = 0;
 734
 735         if (val->value.i == 1)
 736                 err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
 737
 738         return err;
 739 }
 740
 741 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
 742                                        const struct switch_attr *attr,
 743                                        struct switch_val *val)
 744 {
 745         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 746         u32 data;
 747
 748         if (attr->ofs == 1) {
 749                 rtl8366_smi_read_reg(smi, RTL8366S_CHIP_GLOBAL_CTRL_REG, &data);
 750
 751                 if (data & RTL8366S_CHIP_CTRL_VLAN)
 752                         val->value.i = 1;
 753                 else
 754                         val->value.i = 0;
 755         } else if (attr->ofs == 2) {
 756                 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
 757
 758                 if (data & 0x0001)
 759                         val->value.i = 1;
 760                 else
 761                         val->value.i = 0;
 762         }
 763
 764         return 0;
 765 }
 766
 767 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
 768                                      const struct switch_attr *attr,
 769                                      struct switch_val *val)
 770 {
 771         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 772         u32 data;
 773
 774         rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
 775
 776         val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
 777
 778         return 0;
 779 }
 780
 781 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
 782                                     const struct switch_attr *attr,
 783                                     struct switch_val *val)
 784 {
 785         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 786
 787         if (val->value.i >= 6)
 788                 return -EINVAL;
 789
 790         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
 791                                 RTL8366S_LED_BLINKRATE_MASK,
 792                                 val->value.i);
 793 }
 794
 795 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
 796                                        const struct switch_attr *attr,
 797                                        struct switch_val *val)
 798 {
 799         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 800
 801         if (attr->ofs == 1)
 802                 return rtl8366s_vlan_set_vlan(smi, val->value.i);
 803         else
 804                 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
 805 }
 806
 807 static const char *rtl8366s_speed_str(unsigned speed)
 808 {
 809         switch (speed) {
 810         case 0:
 811                 return "10baseT";
 812         case 1:
 813                 return "100baseT";
 814         case 2:
 815                 return "1000baseT";
 816         }
 817
 818         return "unknown";
 819 }
 820
 821 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
 822                                      const struct switch_attr *attr,
 823                                      struct switch_val *val)
 824 {
 825         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 826         u32 len = 0, data = 0;
 827
 828         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 829                 return -EINVAL;
 830
 831         memset(smi->buf, '\0', sizeof(smi->buf));
 832         rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
 833                              (val->port_vlan / 2), &data);
 834
 835         if (val->port_vlan % 2)
 836                 data = data >> 8;
 837
 838         if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
 839                 len = snprintf(smi->buf, sizeof(smi->buf),
 840                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 841                                 val->port_vlan,
 842                                 rtl8366s_speed_str(data &
 843                                           RTL8366S_PORT_STATUS_SPEED_MASK),
 844                                 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
 845                                         "full" : "half",
 846                                 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
 847                                         "tx-pause ": "",
 848                                 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
 849                                         "rx-pause " : "",
 850                                 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
 851                                         "nway ": "");
 852         } else {
 853                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 854                                 val->port_vlan);
 855         }
 856
 857         val->value.s = smi->buf;
 858         val->len = len;
 859
 860         return 0;
 861 }
 862
 863 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
 864                                      const struct switch_attr *attr,
 865                                      struct switch_val *val)
 866 {
 867         int i;
 868         u32 len = 0;
 869         struct rtl8366_vlan_4k vlan4k;
 870         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 871         char *buf = smi->buf;
 872         int err;
 873
 874         if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
 875                 return -EINVAL;
 876
 877         memset(buf, '\0', sizeof(smi->buf));
 878
 879         err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 880         if (err)
 881                 return err;
 882
 883         len += snprintf(buf + len, sizeof(smi->buf) - len,
 884                         "VLAN %d: Ports: '", vlan4k.vid);
 885
 886         for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
 887                 if (!(vlan4k.member & (1 << i)))
 888                         continue;
 889
 890                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
 891                                 (vlan4k.untag & (1 << i)) ? "" : "t");
 892         }
 893
 894         len += snprintf(buf + len, sizeof(smi->buf) - len,
 895                         "', members=%04x, untag=%04x, fid=%u",
 896                         vlan4k.member, vlan4k.untag, vlan4k.fid);
 897
 898         val->value.s = buf;
 899         val->len = len;
 900
 901         return 0;
 902 }
 903
 904 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
 905                                     const struct switch_attr *attr,
 906                                     struct switch_val *val)
 907 {
 908         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 909         u32 data;
 910         u32 mask;
 911         u32 reg;
 912
 913         if (val->port_vlan >= RTL8366S_NUM_PORTS ||
 914             (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
 915                 return -EINVAL;
 916
 917         if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
 918                 reg = RTL8366S_LED_BLINKRATE_REG;
 919                 mask = 0xF << 4;
 920                 data = val->value.i << 4;
 921         } else {
 922                 reg = RTL8366S_LED_CTRL_REG;
 923                 mask = 0xF << (val->port_vlan * 4),
 924                 data = val->value.i << (val->port_vlan * 4);
 925         }
 926
 927         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, mask, data);
 928 }
 929
 930 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
 931                                     const struct switch_attr *attr,
 932                                     struct switch_val *val)
 933 {
 934         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 935         u32 data = 0;
 936
 937         if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
 938                 return -EINVAL;
 939
 940         rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
 941         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 942
 943         return 0;
 944 }
 945
 946 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
 947                                        const struct switch_attr *attr,
 948                                        struct switch_val *val)
 949 {
 950         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 951
 952         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 953                 return -EINVAL;
 954
 955
 956         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
 957                                 0, (1 << (val->port_vlan + 3)));
 958 }
 959
 960 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
 961                                     const struct switch_attr *attr,
 962                                     struct switch_val *val)
 963 {
 964         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 965         int i, len = 0;
 966         unsigned long long counter = 0;
 967         char *buf = smi->buf;
 968
 969         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 970                 return -EINVAL;
 971
 972         len += snprintf(buf + len, sizeof(smi->buf) - len,
 973                         "Port %d MIB counters\n",
 974                         val->port_vlan);
 975
 976         for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
 977                 len += snprintf(buf + len, sizeof(smi->buf) - len,
 978                                 "%-36s: ", rtl8366s_mib_counters[i].name);
 979                 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
 980                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 981                                         "%llu\n", counter);
 982                 else
 983                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 984                                         "%s\n", "error");
 985         }
 986
 987         val->value.s = buf;
 988         val->len = len;
 989         return 0;
 990 }
 991
 992 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
 993                                       struct switch_val *val)
 994 {
 995         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 996         struct switch_port *port;
 997         struct rtl8366_vlan_4k vlan4k;
 998         int i;
 999
1000         if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
1001                 return -EINVAL;
1002
1003         rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1004
1005         port = &val->value.ports[0];
1006         val->len = 0;
1007         for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
1008                 if (!(vlan4k.member & BIT(i)))
1009                         continue;
1010
1011                 port->id = i;
1012                 port->flags = (vlan4k.untag & BIT(i)) ?
1013                                         0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1014                 val->len++;
1015                 port++;
1016         }
1017         return 0;
1018 }
1019
1020 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1021                                       struct switch_val *val)
1022 {
1023         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1024         struct switch_port *port;
1025         u32 member = 0;
1026         u32 untag = 0;
1027         int i;
1028
1029         if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
1030                 return -EINVAL;
1031
1032         port = &val->value.ports[0];
1033         for (i = 0; i < val->len; i++, port++) {
1034                 member |= BIT(port->id);
1035
1036                 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1037                         untag |= BIT(port->id);
1038         }
1039
1040         return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
1041 }
1042
1043 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1044 {
1045         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1046         return rtl8366_get_pvid(smi, port, val);
1047 }
1048
1049 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1050 {
1051         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1052         return rtl8366_set_pvid(smi, port, val);
1053 }
1054
1055 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1056 {
1057         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1058         int err;
1059
1060         err = rtl8366s_reset_chip(smi);
1061         if (err)
1062                 return err;
1063
1064         err = rtl8366s_hw_init(smi);
1065         if (err)
1066                 return err;
1067
1068         return rtl8366_reset_vlan(smi);
1069 }
1070
1071 static struct switch_attr rtl8366s_globals[] = {
1072         {
1073                 .type = SWITCH_TYPE_INT,
1074                 .name = "enable_vlan",
1075                 .description = "Enable VLAN mode",
1076                 .set = rtl8366s_sw_set_vlan_enable,
1077                 .get = rtl8366s_sw_get_vlan_enable,
1078                 .max = 1,
1079                 .ofs = 1
1080         }, {
1081                 .type = SWITCH_TYPE_INT,
1082                 .name = "enable_vlan4k",
1083                 .description = "Enable VLAN 4K mode",
1084                 .set = rtl8366s_sw_set_vlan_enable,
1085                 .get = rtl8366s_sw_get_vlan_enable,
1086                 .max = 1,
1087                 .ofs = 2
1088         }, {
1089                 .type = SWITCH_TYPE_INT,
1090                 .name = "reset_mibs",
1091                 .description = "Reset all MIB counters",
1092                 .set = rtl8366s_sw_reset_mibs,
1093                 .get = NULL,
1094                 .max = 1
1095         }, {
1096                 .type = SWITCH_TYPE_INT,
1097                 .name = "blinkrate",
1098                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1099                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1100                 .set = rtl8366s_sw_set_blinkrate,
1101                 .get = rtl8366s_sw_get_blinkrate,
1102                 .max = 5
1103         },
1104 };
1105
1106 static struct switch_attr rtl8366s_port[] = {
1107         {
1108                 .type = SWITCH_TYPE_STRING,
1109                 .name = "link",
1110                 .description = "Get port link information",
1111                 .max = 1,
1112                 .set = NULL,
1113                 .get = rtl8366s_sw_get_port_link,
1114         }, {
1115                 .type = SWITCH_TYPE_INT,
1116                 .name = "reset_mib",
1117                 .description = "Reset single port MIB counters",
1118                 .max = 1,
1119                 .set = rtl8366s_sw_reset_port_mibs,
1120                 .get = NULL,
1121         }, {
1122                 .type = SWITCH_TYPE_STRING,
1123                 .name = "mib",
1124                 .description = "Get MIB counters for port",
1125                 .max = 33,
1126                 .set = NULL,
1127                 .get = rtl8366s_sw_get_port_mib,
1128         }, {
1129                 .type = SWITCH_TYPE_INT,
1130                 .name = "led",
1131                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1132                 .max = 15,
1133                 .set = rtl8366s_sw_set_port_led,
1134                 .get = rtl8366s_sw_get_port_led,
1135         },
1136 };
1137
1138 static struct switch_attr rtl8366s_vlan[] = {
1139         {
1140                 .type = SWITCH_TYPE_STRING,
1141                 .name = "info",
1142                 .description = "Get vlan information",
1143                 .max = 1,
1144                 .set = NULL,
1145                 .get = rtl8366s_sw_get_vlan_info,
1146         },
1147 };
1148
1149 /* template */
1150 static struct switch_dev rtl8366_switch_dev = {
1151         .name = "RTL8366S",
1152         .cpu_port = RTL8366S_PORT_NUM_CPU,
1153         .ports = RTL8366S_NUM_PORTS,
1154         .vlans = RTL8366S_NUM_VLANS,
1155         .attr_global = {
1156                 .attr = rtl8366s_globals,
1157                 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1158         },
1159         .attr_port = {
1160                 .attr = rtl8366s_port,
1161                 .n_attr = ARRAY_SIZE(rtl8366s_port),
1162         },
1163         .attr_vlan = {
1164                 .attr = rtl8366s_vlan,
1165                 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1166         },
1167
1168         .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1169         .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1170         .get_port_pvid = rtl8366s_sw_get_port_pvid,
1171         .set_port_pvid = rtl8366s_sw_set_port_pvid,
1172         .reset_switch = rtl8366s_sw_reset_switch,
1173 };
1174
1175 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1176 {
1177         struct switch_dev *dev = &rtl->dev;
1178         int err;
1179
1180         memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1181         dev->priv = rtl;
1182         dev->devname = dev_name(rtl->parent);
1183
1184         err = register_switch(dev, NULL);
1185         if (err)
1186                 dev_err(rtl->parent, "switch registration failed\n");
1187
1188         return err;
1189 }
1190
1191 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1192 {
1193         unregister_switch(&rtl->dev);
1194 }
1195
1196 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1197 {
1198         struct rtl8366_smi *smi = bus->priv;
1199         u32 val = 0;
1200         int err;
1201
1202         err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1203         if (err)
1204                 return 0xffff;
1205
1206         return val;
1207 }
1208
1209 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1210 {
1211         struct rtl8366_smi *smi = bus->priv;
1212         u32 t;
1213         int err;
1214
1215         err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1216         /* flush write */
1217         (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1218
1219         return err;
1220 }
1221
1222 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1223 {
1224         return (bus->read == rtl8366s_mii_read &&
1225                 bus->write == rtl8366s_mii_write);
1226 }
1227
1228 static int rtl8366s_setup(struct rtl8366s *rtl)
1229 {
1230         struct rtl8366_smi *smi = &rtl->smi;
1231         int ret;
1232
1233         rtl8366s_debugfs_init(smi);
1234
1235         ret = rtl8366s_reset_chip(smi);
1236         if (ret)
1237                 return ret;
1238
1239         ret = rtl8366s_hw_init(smi);
1240         return ret;
1241 }
1242
1243 static int rtl8366s_detect(struct rtl8366_smi *smi)
1244 {
1245         u32 chip_id = 0;
1246         u32 chip_ver = 0;
1247         int ret;
1248
1249         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1250         if (ret) {
1251                 dev_err(smi->parent, "unable to read chip id\n");
1252                 return ret;
1253         }
1254
1255         switch (chip_id) {
1256         case RTL8366S_CHIP_ID_8366:
1257                 break;
1258         default:
1259                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1260                 return -ENODEV;
1261         }
1262
1263         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1264                                    &chip_ver);
1265         if (ret) {
1266                 dev_err(smi->parent, "unable to read chip version\n");
1267                 return ret;
1268         }
1269
1270         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1271                  chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1272
1273         return 0;
1274 }
1275
1276 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1277         .detect         = rtl8366s_detect,
1278         .mii_read       = rtl8366s_mii_read,
1279         .mii_write      = rtl8366s_mii_write,
1280
1281         .get_vlan_mc    = rtl8366s_get_vlan_mc,
1282         .set_vlan_mc    = rtl8366s_set_vlan_mc,
1283         .get_vlan_4k    = rtl8366s_get_vlan_4k,
1284         .set_vlan_4k    = rtl8366s_set_vlan_4k,
1285         .get_mc_index   = rtl8366s_get_mc_index,
1286         .set_mc_index   = rtl8366s_set_mc_index,
1287 };
1288
1289 static int __init rtl8366s_probe(struct platform_device *pdev)
1290 {
1291         static int rtl8366_smi_version_printed;
1292         struct rtl8366s_platform_data *pdata;
1293         struct rtl8366s *rtl;
1294         struct rtl8366_smi *smi;
1295         int err;
1296
1297         if (!rtl8366_smi_version_printed++)
1298                 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1299                        " version " RTL8366S_DRIVER_VER"\n");
1300
1301         pdata = pdev->dev.platform_data;
1302         if (!pdata) {
1303                 dev_err(&pdev->dev, "no platform data specified\n");
1304                 err = -EINVAL;
1305                 goto err_out;
1306         }
1307
1308         rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1309         if (!rtl) {
1310                 dev_err(&pdev->dev, "no memory for private data\n");
1311                 err = -ENOMEM;
1312                 goto err_out;
1313         }
1314
1315         rtl->parent = &pdev->dev;
1316
1317         smi = &rtl->smi;
1318         smi->parent = &pdev->dev;
1319         smi->gpio_sda = pdata->gpio_sda;
1320         smi->gpio_sck = pdata->gpio_sck;
1321         smi->ops = &rtl8366s_smi_ops;
1322         smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1323         smi->num_ports = RTL8366S_NUM_PORTS;
1324         smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1325
1326         err = rtl8366_smi_init(smi);
1327         if (err)
1328                 goto err_free_rtl;
1329
1330         platform_set_drvdata(pdev, rtl);
1331
1332         err = rtl8366s_setup(rtl);
1333         if (err)
1334                 goto err_clear_drvdata;
1335
1336         err = rtl8366s_switch_init(rtl);
1337         if (err)
1338                 goto err_clear_drvdata;
1339
1340         return 0;
1341
1342  err_clear_drvdata:
1343         platform_set_drvdata(pdev, NULL);
1344         rtl8366_smi_cleanup(smi);
1345  err_free_rtl:
1346         kfree(rtl);
1347  err_out:
1348         return err;
1349 }
1350
1351 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1352 {
1353         if (!rtl8366s_mii_bus_match(phydev->bus))
1354                 return -EINVAL;
1355
1356         return 0;
1357 }
1358
1359 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1360 {
1361         return 0;
1362 }
1363
1364 static struct phy_driver rtl8366s_phy_driver = {
1365         .phy_id         = 0x001cc960,
1366         .name           = "Realtek RTL8366S",
1367         .phy_id_mask    = 0x1ffffff0,
1368         .features       = PHY_GBIT_FEATURES,
1369         .config_aneg    = rtl8366s_phy_config_aneg,
1370         .config_init    = rtl8366s_phy_config_init,
1371         .read_status    = genphy_read_status,
1372         .driver         = {
1373                 .owner = THIS_MODULE,
1374         },
1375 };
1376
1377 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1378 {
1379         struct rtl8366s *rtl = platform_get_drvdata(pdev);
1380
1381         if (rtl) {
1382                 rtl8366s_switch_cleanup(rtl);
1383                 platform_set_drvdata(pdev, NULL);
1384                 rtl8366_smi_cleanup(&rtl->smi);
1385                 kfree(rtl);
1386         }
1387
1388         return 0;
1389 }
1390
1391 static struct platform_driver rtl8366s_driver = {
1392         .driver = {
1393                 .name           = RTL8366S_DRIVER_NAME,
1394                 .owner          = THIS_MODULE,
1395         },
1396         .probe          = rtl8366s_probe,
1397         .remove         = __devexit_p(rtl8366s_remove),
1398 };
1399
1400 static int __init rtl8366s_module_init(void)
1401 {
1402         int ret;
1403         ret = platform_driver_register(&rtl8366s_driver);
1404         if (ret)
1405                 return ret;
1406
1407         ret = phy_driver_register(&rtl8366s_phy_driver);
1408         if (ret)
1409                 goto err_platform_unregister;
1410
1411         return 0;
1412
1413  err_platform_unregister:
1414         platform_driver_unregister(&rtl8366s_driver);
1415         return ret;
1416 }
1417 module_init(rtl8366s_module_init);
1418
1419 static void __exit rtl8366s_module_exit(void)
1420 {
1421         phy_driver_unregister(&rtl8366s_phy_driver);
1422         platform_driver_unregister(&rtl8366s_driver);
1423 }
1424 module_exit(rtl8366s_module_exit);
1425
1426 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1427 MODULE_VERSION(RTL8366S_DRIVER_VER);
1428 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1429 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1430 MODULE_LICENSE("GPL v2");
1431 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);